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| author |   Arnd Bergmann <arnd@arndb.de> | 2021-08-12 22:35:50 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2021-08-12 22:35:50 +0200 |
| commit | a8c371f0cfe7224e4bc3f3f0495e54a035107653 (patch) | |
| tree | 997ecbc5df3bf7241df9a205aa4e020375d60388 /drivers/soc/mediatek/mt8183-mmsys.h | |
| parent | Merge tag 'imx-ecspi-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/drivers (diff) | |
| parent | soc: mediatek: mmsys: Fix missing UFOE component in mt8173 table routing (diff) | |
| download | linux-dev-a8c371f0cfe7224e4bc3f3f0495e54a035107653.tar.xz linux-dev-a8c371f0cfe7224e4bc3f3f0495e54a035107653.zip | |
Merge tag 'v5.14-next-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/drivers
pm-domains:
- correct mask define if used for update on TOPAXI bus
- mt8173: enable regulator befor turning on MFG_ASYNC
mmsys:
- add a mask property to the routing information
- add support for MT8365
- add UFOE routing for MT8173
* tag 'v5.14-next-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
soc: mediatek: mmsys: Fix missing UFOE component in mt8173 table routing
soc: mediatek: mmsys: add MT8365 support
soc: mmsys: mediatek: add mask to mmsys routes
soc: mediatek: pm-domains: Add domain_supply cap for mfg_async PD
soc: mediatek: pm-domains: Use correct mask for bus_prot_clr
Link: https://lore.kernel.org/r/49fc7bef-20db-b98c-9437-dd9e4d00e870@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'drivers/soc/mediatek/mt8183-mmsys.h')
| -rw-r--r-- | drivers/soc/mediatek/mt8183-mmsys.h | 21 |
1 files changed, 14 insertions, 7 deletions
diff --git a/drivers/soc/mediatek/mt8183-mmsys.h b/drivers/soc/mediatek/mt8183-mmsys.h index 579dfc8dc8fc..9dee485807c9 100644 --- a/drivers/soc/mediatek/mt8183-mmsys.h +++ b/drivers/soc/mediatek/mt8183-mmsys.h @@ -28,25 +28,32 @@ static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = { { DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0, - MT8183_DISP_OVL0_MOUT_EN, MT8183_OVL0_MOUT_EN_OVL0_2L + MT8183_DISP_OVL0_MOUT_EN, MT8183_OVL0_MOUT_EN_OVL0_2L, + MT8183_OVL0_MOUT_EN_OVL0_2L }, { DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, - MT8183_DISP_OVL0_2L_MOUT_EN, MT8183_OVL0_2L_MOUT_EN_DISP_PATH0 + MT8183_DISP_OVL0_2L_MOUT_EN, MT8183_OVL0_2L_MOUT_EN_DISP_PATH0, + MT8183_OVL0_2L_MOUT_EN_DISP_PATH0 }, { DDP_COMPONENT_OVL_2L1, DDP_COMPONENT_RDMA1, - MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1 + MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1, + MT8183_OVL1_2L_MOUT_EN_RDMA1 }, { DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, - MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0 + MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0, + MT8183_DITHER0_MOUT_IN_DSI0 }, { DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, - MT8183_DISP_PATH0_SEL_IN, MT8183_DISP_PATH0_SEL_IN_OVL0_2L + MT8183_DISP_PATH0_SEL_IN, MT8183_DISP_PATH0_SEL_IN_OVL0_2L, + MT8183_DISP_PATH0_SEL_IN_OVL0_2L }, { DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, - MT8183_DISP_DPI0_SEL_IN, MT8183_DPI0_SEL_IN_RDMA1 + MT8183_DISP_DPI0_SEL_IN, MT8183_DPI0_SEL_IN_RDMA1, + MT8183_DPI0_SEL_IN_RDMA1 }, { DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, - MT8183_DISP_RDMA0_SOUT_SEL_IN, MT8183_RDMA0_SOUT_COLOR0 + MT8183_DISP_RDMA0_SOUT_SEL_IN, MT8183_RDMA0_SOUT_COLOR0, + MT8183_RDMA0_SOUT_COLOR0 } }; |