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authorArnd Bergmann <arnd@arndb.de>2018-09-28 22:16:47 +0200
committerArnd Bergmann <arnd@arndb.de>2018-09-28 22:16:58 +0200
commit86e762d96713aeafac2dc582bbd38075d421c20a (patch)
treeea53fff11b286ed85afede77013d61e063670fa1 /drivers/soc/renesas/r8a774a1-sysc.c
parentMerge tag 'tegra-for-4.20-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers (diff)
parentdt-bindings: apmu: Document r8a7744 support (diff)
downloadlinux-dev-86e762d96713aeafac2dc582bbd38075d421c20a.tar.xz
linux-dev-86e762d96713aeafac2dc582bbd38075d421c20a.zip
Merge tag 'renesas-drivers-for-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/drivers
Renesas ARM Based SoC Drivers Updates for v4.20 * Convert to SPDX identifiers * R-Car V3M (r8a77970) and V3H (r8a77980): Document Timer Unit (TMU) bindings * RZ/G1N (r8a7744) and RZ/G1C (r8a77470) SoCs: - Document APMU and SMP enable method * RZ/G2M (r8a74a1), RZ/G1N (r8a7744) and RZ/G2E (r8a774c0) SoCs: - Add reset support - Add sysc support * RZ/G2M (r8a774a1), RZ/G2E (r8a774c0) and RZ/A2M (r7s9210) SoCs: - Add support for identifying SoC * RZ/A2M (r7s9210) SoC: - Add basic SoC setup support * tag 'renesas-drivers-for-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (21 commits) dt-bindings: apmu: Document r8a7744 support dt-bindings: timer: renesas: tmu: document R8A779{7|8}0 bindings dt-bindings: apmu: Document r8a77470 support soc: renesas: rcar-rst: Add support for RZ/G1N dt-bindings: reset: rcar-rst: Document r8a7744 reset module soc: renesas: rcar-sysc: Add r8a7744 support dt-bindings: power: rcar-sysc: Add r8a7744 power domain index macros dt-bindings: power: rcar-sysc: Document r8a7744 SYSC binding soc: renesas: rcar-rst: Add support for RZ/G2E dt-bindings: reset: rcar-rst: Document r8a774c0 rst soc: renesas: rcar-sysc: Add r8a774c0 support dt-bindings: power: rcar-sysc: Document r8a774c0 sysc dt-bindings: power: Add r8a774c0 SYSC power domain definitions soc: renesas: Identify RZ/G2E soc: renesas: convert to SPDX identifiers soc: renesas: rcar-rst: Add support for RZ/G2M soc: renesas: rcar-sysc: Add r8a774a1 support dt-bindings: power: Add r8a774a1 SYSC power domain definitions soc: renesas: identify RZ/A2 ARM: shmobile: Add basic RZ/A2 SoC support ... Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'drivers/soc/renesas/r8a774a1-sysc.c')
-rw-r--r--drivers/soc/renesas/r8a774a1-sysc.c45
1 files changed, 45 insertions, 0 deletions
diff --git a/drivers/soc/renesas/r8a774a1-sysc.c b/drivers/soc/renesas/r8a774a1-sysc.c
new file mode 100644
index 000000000000..9db51ff6f5ed
--- /dev/null
+++ b/drivers/soc/renesas/r8a774a1-sysc.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas RZ/G2M System Controller
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ *
+ * Based on Renesas R-Car M3-W System Controller
+ * Copyright (C) 2016 Glider bvba
+ */
+
+#include <linux/bug.h>
+#include <linux/kernel.h>
+
+#include <dt-bindings/power/r8a774a1-sysc.h>
+
+#include "rcar-sysc.h"
+
+static const struct rcar_sysc_area r8a774a1_areas[] __initconst = {
+ { "always-on", 0, 0, R8A774A1_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
+ { "ca57-scu", 0x1c0, 0, R8A774A1_PD_CA57_SCU, R8A774A1_PD_ALWAYS_ON,
+ PD_SCU },
+ { "ca57-cpu0", 0x80, 0, R8A774A1_PD_CA57_CPU0, R8A774A1_PD_CA57_SCU,
+ PD_CPU_NOCR },
+ { "ca57-cpu1", 0x80, 1, R8A774A1_PD_CA57_CPU1, R8A774A1_PD_CA57_SCU,
+ PD_CPU_NOCR },
+ { "ca53-scu", 0x140, 0, R8A774A1_PD_CA53_SCU, R8A774A1_PD_ALWAYS_ON,
+ PD_SCU },
+ { "ca53-cpu0", 0x200, 0, R8A774A1_PD_CA53_CPU0, R8A774A1_PD_CA53_SCU,
+ PD_CPU_NOCR },
+ { "ca53-cpu1", 0x200, 1, R8A774A1_PD_CA53_CPU1, R8A774A1_PD_CA53_SCU,
+ PD_CPU_NOCR },
+ { "ca53-cpu2", 0x200, 2, R8A774A1_PD_CA53_CPU2, R8A774A1_PD_CA53_SCU,
+ PD_CPU_NOCR },
+ { "ca53-cpu3", 0x200, 3, R8A774A1_PD_CA53_CPU3, R8A774A1_PD_CA53_SCU,
+ PD_CPU_NOCR },
+ { "a3vc", 0x380, 0, R8A774A1_PD_A3VC, R8A774A1_PD_ALWAYS_ON },
+ { "a2vc0", 0x3c0, 0, R8A774A1_PD_A2VC0, R8A774A1_PD_A3VC },
+ { "a2vc1", 0x3c0, 1, R8A774A1_PD_A2VC1, R8A774A1_PD_A3VC },
+ { "3dg-a", 0x100, 0, R8A774A1_PD_3DG_A, R8A774A1_PD_ALWAYS_ON },
+ { "3dg-b", 0x100, 1, R8A774A1_PD_3DG_B, R8A774A1_PD_3DG_A },
+};
+
+const struct rcar_sysc_info r8a774a1_sysc_info __initconst = {
+ .areas = r8a774a1_areas,
+ .num_areas = ARRAY_SIZE(r8a774a1_areas),
+};