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| author |   Esben Haabendal <eha@deif.com> | 2018-06-20 09:34:37 +0200 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2018-06-20 14:46:15 +0100 |
| commit | d87e08f1421373f010308b1d065a1f0c3b251a52 (patch) | |
| tree | efc054cfb659b883e07ebc4fb6a6b32ad0b87846 /drivers/spi/spi-fsl-dspi.c | |
| parent | spi: spi-fsl-dspi: Support 4 to 16 bits per word transfers (diff) | |
| download | linux-dev-d87e08f1421373f010308b1d065a1f0c3b251a52.tar.xz linux-dev-d87e08f1421373f010308b1d065a1f0c3b251a52.zip | |
spi: spi-fsl-dspi: Fix MCR register handling
The MCR register is not changed, so initialize it in dspi_init().
The exception is the CLR_TXF and CLR_RXF bits, which should be written to
before each transfer to make sure we start with empty FIFOs. With MCR
register now configured as volatile, the regmap_update_bits will do a real
read-modify-write cycle.
Signed-off-by: Esben Haabendal <eha@deif.com>
Acked-by: Martin Hundebøll <martin@geanix.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi/spi-fsl-dspi.c')
| -rw-r--r-- | drivers/spi/spi-fsl-dspi.c | 10 |
1 files changed, 3 insertions, 7 deletions
diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index df07dd4722fb..39b3c6f4f5c3 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -120,7 +120,6 @@ #define DMA_COMPLETION_TIMEOUT msecs_to_jiffies(3000) struct chip_data { - u32 mcr_val; u32 ctar_val; u16 void_write_data; }; @@ -644,10 +643,9 @@ static int dspi_transfer_one_message(struct spi_master *master, else dspi->bytes_per_word = 2; - regmap_write(dspi->regmap, SPI_MCR, dspi->cur_chip->mcr_val); regmap_update_bits(dspi->regmap, SPI_MCR, - SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF, - SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF); + SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF, + SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF); regmap_write(dspi->regmap, SPI_CTAR(0), dspi->cur_chip->ctar_val | SPI_FRAME_BITS(transfer->bits_per_word)); @@ -725,9 +723,6 @@ static int dspi_setup(struct spi_device *spi) sck_cs_delay = pdata->sck_cs_delay; } - chip->mcr_val = SPI_MCR_MASTER | SPI_MCR_PCSIS | - SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF; - chip->void_write_data = 0; clkrate = clk_get_rate(dspi->clk); @@ -871,6 +866,7 @@ static const struct regmap_config dspi_regmap_config = { static void dspi_init(struct fsl_dspi *dspi) { + regmap_write(dspi->regmap, SPI_MCR, SPI_MCR_MASTER | SPI_MCR_PCSIS); regmap_write(dspi->regmap, SPI_SR, SPI_SR_CLEAR); } |