diff options
| author |   Andrew Bresticker <abrestic@chromium.org> | 2015-04-06 14:29:03 -0700 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2015-04-07 12:19:10 +0100 |
| commit | 8543d0e72d4340001d756bd89bee70ce239e1ea5 (patch) | |
| tree | d1541d6533e9ad0dafedc68787d46c38e8681009 /drivers/spi | |
| parent | Linux 4.0-rc1 (diff) | |
| download | linux-dev-8543d0e72d4340001d756bd89bee70ce239e1ea5.tar.xz linux-dev-8543d0e72d4340001d756bd89bee70ce239e1ea5.zip | |
spi: img-spfi: Limit bit clock to 1/4th of input clock
Although the SPFI BITCLK divider supports a value of up to 255, only
values up to 128 are usable. This results in a maximum possible bit
clock rate of 1/4th the input clock rate.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi')
| -rw-r--r-- | drivers/spi/spi-img-spfi.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/spi/spi-img-spfi.c b/drivers/spi/spi-img-spfi.c index c01567d53581..99a3f7c0c7ff 100644 --- a/drivers/spi/spi-img-spfi.c +++ b/drivers/spi/spi-img-spfi.c @@ -405,10 +405,10 @@ static void img_spfi_config(struct spi_master *master, struct spi_device *spi, /* * output = spfi_clk * (BITCLK / 512), where BITCLK must be a - * power of 2 up to 256 (where 255 == 256 since BITCLK is 8 bits) + * power of 2 up to 128 */ - div = DIV_ROUND_UP(master->max_speed_hz, xfer->speed_hz); - div = clamp(512 / (1 << get_count_order(div)), 1, 255); + div = DIV_ROUND_UP(clk_get_rate(spfi->spfi_clk), xfer->speed_hz); + div = clamp(512 / (1 << get_count_order(div)), 1, 128); val = spfi_readl(spfi, SPFI_DEVICE_PARAMETER(spi->chip_select)); val &= ~(SPFI_DEVICE_PARAMETER_BITCLK_MASK << @@ -587,8 +587,8 @@ static int img_spfi_probe(struct platform_device *pdev) master->num_chipselect = 5; master->dev.of_node = pdev->dev.of_node; master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(8); - master->max_speed_hz = clk_get_rate(spfi->spfi_clk); - master->min_speed_hz = master->max_speed_hz / 512; + master->max_speed_hz = clk_get_rate(spfi->spfi_clk) / 4; + master->min_speed_hz = clk_get_rate(spfi->spfi_clk) / 512; master->set_cs = img_spfi_set_cs; master->transfer_one = img_spfi_transfer_one; |