diff options
| author |   Vasanthakumar Thiagarajan <vasanth@atheros.com> | 2011-05-02 11:22:46 +0530 |
|---|---|---|
| committer |   Greg Kroah-Hartman <gregkh@suse.de> | 2011-05-03 12:29:57 -0700 |
| commit | 30eb73696116341c133ab993e707fff73de395c5 (patch) | |
| tree | 74111deea79ed94f6e094629e0a01b9f72569349 /drivers/staging/ath6kl | |
| parent | ath6kl: Remove unused hw4.0/hw/vmc_reg.h (diff) | |
| download | linux-dev-30eb73696116341c133ab993e707fff73de395c5.tar.xz linux-dev-30eb73696116341c133ab993e707fff73de395c5.zip | |
ath6kl: Remove somemore unused header files from hw4.0/hw/
Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/staging/ath6kl')
6 files changed, 0 insertions, 4687 deletions
diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/efuse_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/efuse_reg.h deleted file mode 100644 index 12cadb337482..000000000000 --- a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/efuse_reg.h +++ /dev/null @@ -1,108 +0,0 @@ -// ------------------------------------------------------------------ -// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. -// -// -// Permission to use, copy, modify, and/or distribute this software for any -// purpose with or without fee is hereby granted, provided that the above -// copyright notice and this permission notice appear in all copies. -// -// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -// -// -// ------------------------------------------------------------------ -//=================================================================== -// Author(s): ="Atheros" -//=================================================================== - - -#ifndef _EFUSE_REG_REG_H_ -#define _EFUSE_REG_REG_H_ - -#define EFUSE_WR_ENABLE_REG_ADDRESS 0x00000000 -#define EFUSE_WR_ENABLE_REG_OFFSET 0x00000000 -#define EFUSE_WR_ENABLE_REG_V_MSB 0 -#define EFUSE_WR_ENABLE_REG_V_LSB 0 -#define EFUSE_WR_ENABLE_REG_V_MASK 0x00000001 -#define EFUSE_WR_ENABLE_REG_V_GET(x) (((x) & EFUSE_WR_ENABLE_REG_V_MASK) >> EFUSE_WR_ENABLE_REG_V_LSB) -#define EFUSE_WR_ENABLE_REG_V_SET(x) (((x) << EFUSE_WR_ENABLE_REG_V_LSB) & EFUSE_WR_ENABLE_REG_V_MASK) - -#define EFUSE_INT_ENABLE_REG_ADDRESS 0x00000004 -#define EFUSE_INT_ENABLE_REG_OFFSET 0x00000004 -#define EFUSE_INT_ENABLE_REG_V_MSB 0 -#define EFUSE_INT_ENABLE_REG_V_LSB 0 -#define EFUSE_INT_ENABLE_REG_V_MASK 0x00000001 -#define EFUSE_INT_ENABLE_REG_V_GET(x) (((x) & EFUSE_INT_ENABLE_REG_V_MASK) >> EFUSE_INT_ENABLE_REG_V_LSB) -#define EFUSE_INT_ENABLE_REG_V_SET(x) (((x) << EFUSE_INT_ENABLE_REG_V_LSB) & EFUSE_INT_ENABLE_REG_V_MASK) - -#define EFUSE_INT_STATUS_REG_ADDRESS 0x00000008 -#define EFUSE_INT_STATUS_REG_OFFSET 0x00000008 -#define EFUSE_INT_STATUS_REG_V_MSB 0 -#define EFUSE_INT_STATUS_REG_V_LSB 0 -#define EFUSE_INT_STATUS_REG_V_MASK 0x00000001 -#define EFUSE_INT_STATUS_REG_V_GET(x) (((x) & EFUSE_INT_STATUS_REG_V_MASK) >> EFUSE_INT_STATUS_REG_V_LSB) -#define EFUSE_INT_STATUS_REG_V_SET(x) (((x) << EFUSE_INT_STATUS_REG_V_LSB) & EFUSE_INT_STATUS_REG_V_MASK) - -#define BITMASK_WR_REG_ADDRESS 0x0000000c -#define BITMASK_WR_REG_OFFSET 0x0000000c -#define BITMASK_WR_REG_V_MSB 31 -#define BITMASK_WR_REG_V_LSB 0 -#define BITMASK_WR_REG_V_MASK 0xffffffff -#define BITMASK_WR_REG_V_GET(x) (((x) & BITMASK_WR_REG_V_MASK) >> BITMASK_WR_REG_V_LSB) -#define BITMASK_WR_REG_V_SET(x) (((x) << BITMASK_WR_REG_V_LSB) & BITMASK_WR_REG_V_MASK) - -#define VDDQ_SETTLE_TIME_REG_ADDRESS 0x00000010 -#define VDDQ_SETTLE_TIME_REG_OFFSET 0x00000010 -#define VDDQ_SETTLE_TIME_REG_V_MSB 31 -#define VDDQ_SETTLE_TIME_REG_V_LSB 0 -#define VDDQ_SETTLE_TIME_REG_V_MASK 0xffffffff -#define VDDQ_SETTLE_TIME_REG_V_GET(x) (((x) & VDDQ_SETTLE_TIME_REG_V_MASK) >> VDDQ_SETTLE_TIME_REG_V_LSB) -#define VDDQ_SETTLE_TIME_REG_V_SET(x) (((x) << VDDQ_SETTLE_TIME_REG_V_LSB) & VDDQ_SETTLE_TIME_REG_V_MASK) - -#define RD_STROBE_PW_REG_ADDRESS 0x00000014 -#define RD_STROBE_PW_REG_OFFSET 0x00000014 -#define RD_STROBE_PW_REG_V_MSB 31 -#define RD_STROBE_PW_REG_V_LSB 0 -#define RD_STROBE_PW_REG_V_MASK 0xffffffff -#define RD_STROBE_PW_REG_V_GET(x) (((x) & RD_STROBE_PW_REG_V_MASK) >> RD_STROBE_PW_REG_V_LSB) -#define RD_STROBE_PW_REG_V_SET(x) (((x) << RD_STROBE_PW_REG_V_LSB) & RD_STROBE_PW_REG_V_MASK) - -#define PG_STROBE_PW_REG_ADDRESS 0x00000018 -#define PG_STROBE_PW_REG_OFFSET 0x00000018 -#define PG_STROBE_PW_REG_V_MSB 31 -#define PG_STROBE_PW_REG_V_LSB 0 -#define PG_STROBE_PW_REG_V_MASK 0xffffffff -#define PG_STROBE_PW_REG_V_GET(x) (((x) & PG_STROBE_PW_REG_V_MASK) >> PG_STROBE_PW_REG_V_LSB) -#define PG_STROBE_PW_REG_V_SET(x) (((x) << PG_STROBE_PW_REG_V_LSB) & PG_STROBE_PW_REG_V_MASK) - -#define EFUSE_INTF_ADDRESS 0x00000800 -#define EFUSE_INTF_OFFSET 0x00000800 -#define EFUSE_INTF_R_MSB 31 -#define EFUSE_INTF_R_LSB 0 -#define EFUSE_INTF_R_MASK 0xffffffff -#define EFUSE_INTF_R_GET(x) (((x) & EFUSE_INTF_R_MASK) >> EFUSE_INTF_R_LSB) -#define EFUSE_INTF_R_SET(x) (((x) << EFUSE_INTF_R_LSB) & EFUSE_INTF_R_MASK) - - -#ifndef __ASSEMBLER__ - -typedef struct efuse_reg_reg_s { - volatile unsigned int efuse_wr_enable_reg; - volatile unsigned int efuse_int_enable_reg; - volatile unsigned int efuse_int_status_reg; - volatile unsigned int bitmask_wr_reg; - volatile unsigned int vddq_settle_time_reg; - volatile unsigned int rd_strobe_pw_reg; - volatile unsigned int pg_strobe_pw_reg; - unsigned char pad0[2020]; /* pad to 0x800 */ - volatile unsigned int efuse_intf[512]; -} efuse_reg_reg_t; - -#endif /* __ASSEMBLER__ */ - -#endif /* _EFUSE_REG_H_ */ diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mac_dma_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mac_dma_reg.h deleted file mode 100644 index f82f809171a0..000000000000 --- a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mac_dma_reg.h +++ /dev/null @@ -1,605 +0,0 @@ -// ------------------------------------------------------------------ -// Copyright (c) 2002-2010 Atheros Communications Inc. -// All rights reserved. -// -// -// Permission to use, copy, modify, and/or distribute this software for any -// purpose with or without fee is hereby granted, provided that the above -// copyright notice and this permission notice appear in all copies. -// -// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -// -// -// ------------------------------------------------------------------ -//=================================================================== -// Author(s): ="Atheros" -//=================================================================== - - -/*****************************************************************************/ -/* AR6003 WLAN MAC DMA register definitions */ -/*****************************************************************************/ - -#ifndef _AR6000_DMAREG_H_ -#define _AR6000_DMAREG_H_ - -/* - * Definitions for the Atheros AR6003 chipset. - */ - -/* DMA Control and Interrupt Registers */ -#define MAC_DMA_CR_ADDRESS 0x00000008 /* MAC control register */ -#define MAC_DMA_CR_RXE_MASK 0x00000004 /* Receive enable */ -#define MAC_DMA_CR_RXD_MASK 0x00000020 /* Receive disable */ -#define MAC_DMA_CR_SWI_MASK 0x00000040 /* One-shot software interrupt */ - -#define MAC_DMA_RXDP_ADDRESS 0x0000000C /* MAC receive queue descriptor pointer */ - -#define MAC_DMA_CFG_ADDRESS 0x00000014 /* MAC configuration and status register */ -#define MAC_DMA_CFG_SWTD_MASK 0x00000001 /* byteswap tx descriptor words */ -#define MAC_DMA_CFG_SWTB_MASK 0x00000002 /* byteswap tx data buffer words */ -#define MAC_DMA_CFG_SWRD_MASK 0x00000004 /* byteswap rx descriptor words */ -#define MAC_DMA_CFG_SWRB_MASK 0x00000008 /* byteswap rx data buffer words */ -#define MAC_DMA_CFG_SWRG_MASK 0x00000010 /* byteswap register access data words */ -#define MAC_DMA_CFG_AP_ADHOC_INDICATION_MASK 0x00000020 /* AP/adhoc indication (0-AP, 1-Adhoc) */ -#define MAC_DMA_CFG_PHOK_MASK 0x00000100 /* PHY OK status */ -#define MAC_DMA_CFG_CLK_GATE_DIS_MASK 0x00000400 /* Clock gating disable */ - -#define MAC_DMA_MIRT_ADDRESS 0x00000020 /* Maximum rate threshold register */ -#define MAC_DMA_MIRT_THRESH_MASK 0x0000FFFF - -#define MAC_DMA_IER_ADDRESS 0x00000024 /* MAC Interrupt enable register */ -#define MAC_DMA_IER_ENABLE_MASK 0x00000001 /* Global interrupt enable */ -#define MAC_DMA_IER_DISABLE_MASK 0x00000000 /* Global interrupt disable */ - -#define MAC_DMA_TIMT_ADDRESS 0x00000028 /* Transmit Interrupt Mitigation Threshold */ -#define MAC_DMA_TIMT_LAST_PACKER_THRESH_MASK 0x0000FFFF /* Last packet threshold mask */ -#define MAC_DMA_TIMT_FIRST_PACKER_THRESH_MASK 0xFFFF0000 /* First packet threshold mask */ - -#define MAC_DMA_RIMT_ADDRESS 0x0000002C /* Receive Interrupt Mitigation Threshold */ -#define MAC_DMA_RIMT_LAST_PACKER_THRESH_MASK 0x0000FFFF /* Last packet threshold mask */ -#define MAC_DMA_RIMT_FIRST_PACKER_THRESH_MASK 0xFFFF0000 /* First packet threshold mask */ - -#define MAC_DMA_TXCFG_ADDRESS 0x00000030 /* MAC tx DMA size config register */ -#define MAC_DMA_FTRIG_MASK 0x000003F0 /* Mask for Frame trigger level */ -#define MAC_DMA_FTRIG_LSB 4 /* Shift for Frame trigger level */ -#define MAC_DMA_FTRIG_IMMED 0x00000000 /* bytes in PCU TX FIFO before air */ -#define MAC_DMA_FTRIG_64B 0x00000010 /* default */ -#define MAC_DMA_FTRIG_128B 0x00000020 -#define MAC_DMA_FTRIG_192B 0x00000030 -#define MAC_DMA_FTRIG_256B 0x00000040 /* 5 bits total */ -#define MAC_DMA_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY_MASK 0x00000800 - -#define MAC_DMA_RXCFG_ADDRESS 0x00000034 /* MAC rx DMA size config register */ -#define MAC_DMA_RXCFG_ZLFDMA_MASK 0x00000010 /* Enable DMA of zero-length frame */ -#define MAC_DMA_RXCFG_DMASIZE_4B 0x00000000 /* DMA size 4 bytes (TXCFG + RXCFG) */ -#define MAC_DMA_RXCFG_DMASIZE_8B 0x00000001 /* DMA size 8 bytes */ -#define MAC_DMA_RXCFG_DMASIZE_16B 0x00000002 /* DMA size 16 bytes */ -#define MAC_DMA_RXCFG_DMASIZE_32B 0x00000003 /* DMA size 32 bytes */ -#define MAC_DMA_RXCFG_DMASIZE_64B 0x00000004 /* DMA size 64 bytes */ -#define MAC_DMA_RXCFG_DMASIZE_128B 0x00000005 /* DMA size 128 bytes */ -#define MAC_DMA_RXCFG_DMASIZE_256B 0x00000006 /* DMA size 256 bytes */ -#define MAC_DMA_RXCFG_DMASIZE_512B 0x00000007 /* DMA size 512 bytes */ - -#define MAC_DMA_MIBC_ADDRESS 0x00000040 /* MAC MIB control register */ -#define MAC_DMA_MIBC_COW_MASK 0x00000001 /* counter overflow warning */ -#define MAC_DMA_MIBC_FMC_MASK 0x00000002 /* freeze MIB counters */ -#define MAC_DMA_MIBC_CMC_MASK 0x00000004 /* clear MIB counters */ -#define MAC_DMA_MIBC_MCS_MASK 0x00000008 /* MIB counter strobe, increment all */ - -#define MAC_DMA_TOPS_ADDRESS 0x00000044 /* MAC timeout prescale count */ -#define MAC_DMA_TOPS_MASK 0x0000FFFF /* Mask for timeout prescale */ - -#define MAC_DMA_RXNPTO_ADDRESS 0x00000048 /* MAC no frame received timeout */ -#define MAC_DMA_RXNPTO_MASK 0x000003FF /* Mask for no frame received timeout */ - -#define MAC_DMA_TXNPTO_ADDRESS 0x0000004C /* MAC no frame trasmitted timeout */ -#define MAC_DMA_TXNPTO_MASK 0x000003FF /* Mask for no frame transmitted timeout */ -#define MAC_DMA_TXNPTO_QCU_MASK 0x000FFC00 /* Mask indicating the set of QCUs */ - /* for which frame completions will cause */ - /* a reset of the no frame xmit'd timeout */ - -#define MAC_DMA_RPGTO_ADDRESS 0x00000050 /* MAC receive frame gap timeout */ -#define MAC_DMA_RPGTO_MASK 0x000003FF /* Mask for receive frame gap timeout */ - -#define MAC_DMA_RPCNT_ADDRESS 0x00000054 /* MAC receive frame count limit */ -#define MAC_DMA_RPCNT_MASK 0x0000001F /* Mask for receive frame count limit */ - -#define MAC_DMA_MACMISC_ADDRESS 0x00000058 /* MAC miscellaneous control/status register */ -#define MAC_DMA_MACMISC_DMA_OBS_MASK 0x000001E0 /* Mask for DMA observation bus mux select */ -#define MAC_DMA_MACMISC_DMA_OBS_LSB 5 /* Shift for DMA observation bus mux select */ -#define MAC_DMA_MACMISC_MISC_OBS 0x00000E00 /* Mask for MISC observation bus mux select */ -#define MAC_DMA_MACMISC_MISC_OBS_LSB 9 /* Shift for MISC observation bus mux select */ -#define MAC_DMA_MACMISC_MAC_OBS_BUS_LSB 0x00007000 /* Mask for MAC observation bus mux select (lsb) */ -#define MAC_DMA_MACMISC_MAC_OBS_BUS_LSB_LSB 12 /* Shift for MAC observation bus mux select (lsb) */ -#define MAC_DMA_MACMISC_MAC_OBS_BUS_MSB 0x00038000 /* Mask for MAC observation bus mux select (msb) */ -#define MAC_DMA_MACMISC_MAC_OBS_BUS_MSB_LSB 15 /* Shift for MAC observation bus mux select (msb) */ - - -#define MAC_DMA_ISR_ADDRESS 0x00000080 /* MAC Primary interrupt status register */ -/* - * Interrupt Status Registers - * - * Only the bits in the ISR_P register and the IMR_P registers - * control whether the MAC's INTA# output is asserted. The bits in - * the secondary interrupt status/mask registers control what bits - * are set in the primary interrupt status register; however the - * IMR_S* registers DO NOT determine whether INTA# is asserted. - * That is INTA# is asserted only when the logical AND of ISR_P - * and IMR_P is non-zero. The secondary interrupt mask/status - * registers affect what bits are set in ISR_P but they do not - * directly affect whether INTA# is asserted. - */ -#define MAC_DMA_ISR_RXOK_MASK 0x00000001 /* At least one frame received sans errors */ -#define MAC_DMA_ISR_RXDESC_MASK 0x00000002 /* Receive interrupt request */ -#define MAC_DMA_ISR_RXERR_MASK 0x00000004 /* Receive error interrupt */ -#define MAC_DMA_ISR_RXNOPKT_MASK 0x00000008 /* No frame received within timeout clock */ -#define MAC_DMA_ISR_RXEOL_MASK 0x00000010 /* Received descriptor empty interrupt */ -#define MAC_DMA_ISR_RXORN_MASK 0x00000020 /* Receive FIFO overrun interrupt */ -#define MAC_DMA_ISR_TXOK_MASK 0x00000040 /* Transmit okay interrupt */ -#define MAC_DMA_ISR_TXDESC_MASK 0x00000080 /* Transmit interrupt request */ -#define MAC_DMA_ISR_TXERR_MASK 0x00000100 /* Transmit error interrupt */ -#define MAC_DMA_ISR_TXNOPKT_MASK 0x00000200 /* No frame transmitted interrupt */ -#define MAC_DMA_ISR_TXEOL_MASK 0x00000400 /* Transmit descriptor empty interrupt */ -#define MAC_DMA_ISR_TXURN_MASK 0x00000800 /* Transmit FIFO underrun interrupt */ -#define MAC_DMA_ISR_MIB_MASK 0x00001000 /* MIB interrupt - see MIBC */ -#define MAC_DMA_ISR_SWI_MASK 0x00002000 /* Software interrupt */ -#define MAC_DMA_ISR_RXPHY_MASK 0x00004000 /* PHY receive error interrupt */ -#define MAC_DMA_ISR_RXKCM_MASK 0x00008000 /* Key-cache miss interrupt */ -#define MAC_DMA_ISR_BRSSI_HI_MASK 0x00010000 /* Beacon rssi high threshold interrupt */ -#define MAC_DMA_ISR_BRSSI_LO_MASK 0x00020000 /* Beacon threshold interrupt */ -#define MAC_DMA_ISR_BMISS_MASK 0x00040000 /* Beacon missed interrupt */ -#define MAC_DMA_ISR_TXMINTR_MASK 0x00080000 /* Maximum transmit interrupt rate */ -#define MAC_DMA_ISR_BNR_MASK 0x00100000 /* Beacon not ready interrupt */ -#define MAC_DMA_ISR_HIUERR_MASK 0x00200000 /* An unexpected bus error has occurred */ -#define MAC_DMA_ISR_BCNMISC_MASK 0x00800000 /* 'or' of TIM, CABEND, DTIMSYNC, BCNTO */ -#define MAC_DMA_ISR_RXMINTR_MASK 0x01000000 /* Maximum receive interrupt rate */ -#define MAC_DMA_ISR_QCBROVF_MASK 0x02000000 /* QCU CBR overflow interrupt */ -#define MAC_DMA_ISR_QCBRURN_MASK 0x04000000 /* QCU CBR underrun interrupt */ -#define MAC_DMA_ISR_QTRIG_MASK 0x08000000 /* QCU scheduling trigger interrupt */ -#define MAC_DMA_ISR_TIMER_MASK 0x10000000 /* GENTMR interrupt */ -#define MAC_DMA_ISR_HCFTO_MASK 0x20000000 /* HCFTO interrupt */ -#define MAC_DMA_ISR_TXINTM_MASK 0x40000000 /* Transmit completion mitigation interrupt */ -#define MAC_DMA_ISR_RXINTM_MASK 0x80000000 /* Receive completion mitigation interrupt */ - -#define MAC_DMA_ISR_S0_ADDRESS 0x00000084 /* MAC Secondary interrupt status register 0 */ -#define MAC_DMA_ISR_S0_QCU_TXOK_MASK 0x000003FF /* Mask for TXOK (QCU 0-9) */ -#define MAC_DMA_ISR_S0_QCU_TXOK_LSB 0 -#define MAC_DMA_ISR_S0_QCU_TXDESC_MASK 0x03FF0000 /* Mask for TXDESC (QCU 0-9) */ -#define MAC_DMA_ISR_S0_QCU_TXDESC_LSB 16 - -#define MAC_DMA_ISR_S1_ADDRESS 0x00000088 /* MAC Secondary interrupt status register 1 */ -#define MAC_DMA_ISR_S1_QCU_TXERR_MASK 0x000003FF /* Mask for TXERR (QCU 0-9) */ -#define MAC_DMA_ISR_S1_QCU_TXERR_LSB 0 -#define MAC_DMA_ISR_S1_QCU_TXEOL_MASK 0x03FF0000 /* Mask for TXEOL (QCU 0-9) */ -#define MAC_DMA_ISR_S1_QCU_TXEOL_LSB 16 - -#define MAC_DMA_ISR_S2_ADDRESS 0x0000008c /* MAC Secondary interrupt status register 2 */ -#define MAC_DMA_ISR_S2_QCU_TXURN_MASK 0x000003FF /* Mask for TXURN (QCU 0-9) */ -#define MAC_DMA_ISR_S2_QCU_TXURN_LSB 0 /* Shift for TXURN (QCU 0-9) */ -#define MAC_DMA_ISR_S2_RX_INT_MASK 0x00000800 -#define MAC_DMA_ISR_S2_WL_STOMPED_MASK 0x00001000 -#define MAC_DMA_ISR_S2_RX_PTR_BAD_MASK 0x00002000 -#define MAC_DMA_ISR_S2_BT_LOW_PRIORITY_RISING_MASK 0x00004000 -#define MAC_DMA_ISR_S2_BT_LOW_PRIORITY_FALLING_MASK 0x00008000 -#define MAC_DMA_ISR_S2_BB_PANIC_IRQ_MASK 0x00010000 -#define MAC_DMA_ISR_S2_BT_STOMPED_MASK 0x00020000 -#define MAC_DMA_ISR_S2_BT_ACTIVE_RISING_MASK 0x00040000 -#define MAC_DMA_ISR_S2_BT_ACTIVE_FALLING_MASK 0x00080000 -#define MAC_DMA_ISR_S2_BT_PRIORITY_RISING_MASK 0x00100000 -#define MAC_DMA_ISR_S2_BT_PRIORITY_FALLING_MASK 0x00200000 -#define MAC_DMA_ISR_S2_CST_MASK 0x00400000 -#define MAC_DMA_ISR_S2_GTT_MASK 0x00800000 -#define MAC_DMA_ISR_S2_TIM_MASK 0x01000000 /* TIM */ -#define MAC_DMA_ISR_S2_CABEND_MASK 0x02000000 /* CABEND */ -#define MAC_DMA_ISR_S2_DTIMSYNC_MASK 0x04000000 /* DTIMSYNC */ -#define MAC_DMA_ISR_S2_BCNTO_MASK 0x08000000 /* BCNTO */ -#define MAC_DMA_ISR_S2_CABTO_MASK 0x10000000 /* CABTO */ -#define MAC_DMA_ISR_S2_DTIM_MASK 0x20000000 /* DTIM */ -#define MAC_DMA_ISR_S2_TSFOOR_MASK 0x40000000 /* TSFOOR */ - -#define MAC_DMA_ISR_S3_ADDRESS 0x00000090 /* MAC Secondary interrupt status register 3 */ -#define MAC_DMA_ISR_S3_QCU_QCBROVF_MASK 0x000003FF /* Mask for QCBROVF (QCU 0-9) */ -#define MAC_DMA_ISR_S3_QCU_QCBRURN_MASK 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */ - -#define MAC_DMA_ISR_S4_ADDRESS 0x00000094 /* MAC Secondary interrupt status register 4 */ -#define MAC_DMA_ISR_S4_QCU_QTRIG_MASK 0x000003FF /* Mask for QTRIG (QCU 0-9) */ - -#define MAC_DMA_ISR_S5_ADDRESS 0x00000098 /* MAC Secondary interrupt status register 5 */ -#define MAC_DMA_ISR_S5_TBTT_TIMER_TRIGGER_MASK 0x00000001 -#define MAC_DMA_ISR_S5_DBA_TIMER_TRIGGER_MASK 0x00000002 -#define MAC_DMA_ISR_S5_SBA_TIMER_TRIGGER_MASK 0x00000004 -#define MAC_DMA_ISR_S5_HCF_TIMER_TRIGGER_MASK 0x00000008 -#define MAC_DMA_ISR_S5_TIM_TIMER_TRIGGER_MASK 0x00000010 -#define MAC_DMA_ISR_S5_DTIM_TIMER_TRIGGER_MASK 0x00000020 -#define MAC_DMA_ISR_S5_QUIET_TIMER_TRIGGER_MASK 0x00000040 -#define MAC_DMA_ISR_S5_NDP_TIMER_TRIGGER_MASK 0x00000080 -#define MAC_DMA_ISR_S5_GENERIC_TIMER2_TRIGGER_MASK 0x0000FF00 -#define MAC_DMA_ISR_S5_GENERIC_TIMER2_TRIGGER_LSB 8 -#define MAC_DMA_ISR_S5_GENERIC_TIMER2_TRIGGER(_i) (0x00000100 << (_i)) -#define MAC_DMA_ISR_S5_TIMER_OVERFLOW_MASK 0x00010000 -#define MAC_DMA_ISR_S5_DBA_TIMER_THRESHOLD_MASK 0x00020000 -#define MAC_DMA_ISR_S5_SBA_TIMER_THRESHOLD_MASK 0x00040000 -#define MAC_DMA_ISR_S5_HCF_TIMER_THRESHOLD_MASK 0x00080000 -#define MAC_DMA_ISR_S5_TIM_TIMER_THRESHOLD_MASK 0x00100000 -#define MAC_DMA_ISR_S5_DTIM_TIMER_THRESHOLD_MASK 0x00200000 -#define MAC_DMA_ISR_S5_QUIET_TIMER_THRESHOLD_MASK 0x00400000 -#define MAC_DMA_ISR_S5_NDP_TIMER_THRESHOLD_MASK 0x00800000 -#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_MASK 0xFF000000 -#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_LSB 24 -#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD(_i) (0x01000000 << (_i)) - -#define MAC_DMA_IMR_ADDRESS 0x000000A0 /* MAC Primary interrupt mask register */ -/* - * Interrupt Mask Registers - * - * Only the bits in the IMR control whether the MAC's INTA# - * output will be asserted. The bits in the secondary interrupt - * mask registers control what bits get set in the primary - * interrupt status register; however the IMR_S* registers - * DO NOT determine whether INTA# is asserted. - */ -#define MAC_DMA_IMR_RXOK_MASK 0x00000001 /* At least one frame received sans errors */ -#define MAC_DMA_IMR_RXDESC_MASK 0x00000002 /* Receive interrupt request */ -#define MAC_DMA_IMR_RXERR_MASK 0x00000004 /* Receive error interrupt */ -#define MAC_DMA_IMR_RXNOPKT_MASK 0x00000008 /* No frame received within timeout clock */ -#define MAC_DMA_IMR_RXEOL_MASK 0x00000010 /* Received descriptor empty interrupt */ -#define MAC_DMA_IMR_RXORN_MASK 0x00000020 /* Receive FIFO overrun interrupt */ -#define MAC_DMA_IMR_TXOK_MASK 0x00000040 /* Transmit okay interrupt */ -#define MAC_DMA_IMR_TXDESC_MASK 0x00000080 /* Transmit interrupt request */ -#define MAC_DMA_IMR_TXERR_MASK 0x00000100 /* Transmit error interrupt */ -#define MAC_DMA_IMR_TXNOPKT_MASK 0x00000200 /* No frame transmitted interrupt */ -#define MAC_DMA_IMR_TXEOL_MASK 0x00000400 /* Transmit descriptor empty interrupt */ -#define MAC_DMA_IMR_TXURN_MASK 0x00000800 /* Transmit FIFO underrun interrupt */ -#define MAC_DMA_IMR_MIB_MASK 0x00001000 /* MIB interrupt - see MIBC */ -#define MAC_DMA_IMR_SWI_MASK 0x00002000 /* Software interrupt */ -#define MAC_DMA_IMR_RXPHY_MASK 0x00004000 /* PHY receive error interrupt */ -#define MAC_DMA_IMR_RXKCM_MASK 0x00008000 /* Key-cache miss interrupt */ -#define MAC_DMA_IMR_BRSSI_HI_MASK 0x00010000 /* Beacon rssi hi threshold interrupt */ -#define MAC_DMA_IMR_BRSSI_LO_MASK 0x00020000 /* Beacon rssi lo threshold interrupt */ -#define MAC_DMA_IMR_BMISS_MASK 0x00040000 /* Beacon missed interrupt */ -#define MAC_DMA_IMR_TXMINTR_MASK 0x00080000 /* Maximum transmit interrupt rate */ -#define MAC_DMA_IMR_BNR_MASK 0x00100000 /* BNR interrupt */ -#define MAC_DMA_IMR_HIUERR_MASK 0x00200000 /* An unexpected bus error has occurred */ -#define MAC_DMA_IMR_BCNMISC_MASK 0x00800000 /* Beacon Misc */ -#define MAC_DMA_IMR_RXMINTR_MASK 0x01000000 /* Maximum receive interrupt rate */ -#define MAC_DMA_IMR_QCBROVF_MASK 0x02000000 /* QCU CBR overflow interrupt */ -#define MAC_DMA_IMR_QCBRURN_MASK 0x04000000 /* QCU CBR underrun interrupt */ -#define MAC_DMA_IMR_QTRIG_MASK 0x08000000 /* QCU scheduling trigger interrupt */ -#define MAC_DMA_IMR_TIMER_MASK 0x10000000 /* GENTMR interrupt */ -#define MAC_DMA_IMR_HCFTO_MASK 0x20000000 /* HCFTO interrupt*/ -#define MAC_DMA_IMR_TXINTM_MASK 0x40000000 /* Transmit completion mitigation interrupt */ -#define MAC_DMA_IMR_RXINTM_MASK 0x80000000 /* Receive completion mitigation interrupt */ - -#define MAC_DMA_IMR_S0_ADDRESS 0x000000A4 /* MAC Secondary interrupt mask register 0 */ -#define MAC_DMA_IMR_S0_QCU_TXOK_MASK 0x000003FF /* TXOK (QCU 0-9) */ -#define MAC_DMA_IMR_S0_QCU_TXOK_LSB 0 -#define MAC_DMA_IMR_S0_QCU_TXDESC_MASK 0x03FF0000 /* TXDESC (QCU 0-9) */ -#define MAC_DMA_IMR_S0_QCU_TXDESC_LSB 16 - -#define MAC_DMA_IMR_S1_ADDRESS 0x000000A8 /* MAC Secondary interrupt mask register 1 */ -#define MAC_DMA_IMR_S1_QCU_TXERR_MASK 0x000003FF /* TXERR (QCU 0-9) */ -#define MAC_DMA_IMR_S1_QCU_TXERR_LSB 0 -#define MAC_DMA_IMR_S1_QCU_TXEOL_MASK 0x03FF0000 /* TXEOL (QCU 0-9) */ -#define MAC_DMA_IMR_S1_QCU_TXEOL_LSB 16 - -#define MAC_DMA_IMR_S2_ADDRESS 0x000000AC /* MAC Secondary interrupt mask register 2 */ -#define MAC_DMA_IMR_S2_QCU_TXURN_MASK 0x000003FF /* Mask for TXURN (QCU 0-9) */ -#define MAC_DMA_IMR_S2_QCU_TXURN_LSB 0 -#define MAC_DMA_IMR_S2_RX_INT_MASK 0x00000800 -#define MAC_DMA_IMR_S2_WL_STOMPED_MASK 0x00001000 -#define MAC_DMA_IMR_S2_RX_PTR_BAD_MASK 0x00002000 -#define MAC_DMA_IMR_S2_BT_LOW_PRIORITY_RISING_MASK 0x00004000 -#define MAC_DMA_IMR_S2_BT_LOW_PRIORITY_FALLING_MASK 0x00008000 -#define MAC_DMA_IMR_S2_BB_PANIC_IRQ_MASK 0x00010000 -#define MAC_DMA_IMR_S2_BT_STOMPED_MASK 0x00020000 -#define MAC_DMA_IMR_S2_BT_ACTIVE_RISING_MASK 0x00040000 -#define MAC_DMA_IMR_S2_BT_ACTIVE_FALLING_MASK 0x00080000 -#define MAC_DMA_IMR_S2_BT_PRIORITY_RISING_MASK 0x00100000 -#define MAC_DMA_IMR_S2_BT_PRIORITY_FALLING_MASK 0x00200000 -#define MAC_DMA_IMR_S2_CST_MASK 0x00400000 -#define MAC_DMA_IMR_S2_GTT_MASK 0x00800000 -#define MAC_DMA_IMR_S2_TIM_MASK 0x01000000 /* TIM */ -#define MAC_DMA_IMR_S2_CABEND_MASK 0x02000000 /* CABEND */ -#define MAC_DMA_IMR_S2_DTIMSYNC_MASK 0x04000000 /* DTIMSYNC */ -#define MAC_DMA_IMR_S2_BCNTO_MASK 0x08000000 /* BCNTO */ -#define MAC_DMA_IMR_S2_CABTO_MASK 0x10000000 /* CABTO */ -#define MAC_DMA_IMR_S2_DTIM_MASK 0x20000000 /* DTIM */ -#define MAC_DMA_IMR_S2_TSFOOR_MASK 0x40000000 /* TSFOOR */ - -#define MAC_DMA_IMR_S3_ADDRESS 0x000000B0 /* MAC Secondary interrupt mask register 3 */ -#define MAC_DMA_IMR_S3_QCU_QCBROVF_MASK 0x000003FF /* Mask for QCBROVF (QCU 0-9) */ -#define MAC_DMA_IMR_S3_QCU_QCBRURN_MASK 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */ -#define MAC_DMA_IMR_S3_QCU_QCBRURN_LSB 16 - -#define MAC_DMA_IMR_S4_ADDRESS 0x000000B4 /* MAC Secondary interrupt mask register 4 */ -#define MAC_DMA_IMR_S4_QCU_QTRIG_MASK 0x000003FF /* Mask for QTRIG (QCU 0-9) */ - -#define MAC_DMA_IMR_S5_ADDRESS 0x000000B8 /* MAC Secondary interrupt mask register 5 */ -#define MAC_DMA_IMR_S5_TBTT_TIMER_TRIGGER_MASK 0x00000001 -#define MAC_DMA_IMR_S5_DBA_TIMER_TRIGGER_MASK 0x00000002 -#define MAC_DMA_IMR_S5_SBA_TIMER_TRIGGER_MASK 0x00000004 -#define MAC_DMA_IMR_S5_HCF_TIMER_TRIGGER_MASK 0x00000008 -#define MAC_DMA_IMR_S5_TIM_TIMER_TRIGGER_MASK 0x00000010 -#define MAC_DMA_IMR_S5_DTIM_TIMER_TRIGGER_MASK 0x00000020 -#define MAC_DMA_IMR_S5_QUIET_TIMER_TRIGGER_MASK 0x00000040 -#define MAC_DMA_IMR_S5_NDP_TIMER_TRIGGER_MASK 0x00000080 -#define MAC_DMA_IMR_S5_GENERIC_TIMER2_TRIGGER_MASK 0x0000FF00 -#define MAC_DMA_IMR_S5_GENERIC_TIMER2_TRIGGER_LSB 8 -#define MAC_DMA_IMR_S5_GENERIC_TIMER2_TRIGGER(_i) (0x100 << (_i)) -#define MAC_DMA_IMR_S5_TIMER_OVERFLOW_MASK 0x00010000 -#define MAC_DMA_IMR_S5_DBA_TIMER_THRESHOLD_MASK 0x00020000 -#define MAC_DMA_IMR_S5_SBA_TIMER_THRESHOLD_MASK 0x00040000 -#define MAC_DMA_IMR_S5_HCF_TIMER_THRESHOLD_MASK 0x00080000 -#define MAC_DMA_IMR_S5_TIM_TIMER_THRESHOLD_MASK 0x00100000 -#define MAC_DMA_IMR_S5_DTIM_TIMER_THRESHOLD_MASK 0x00200000 -#define MAC_DMA_IMR_S5_QUIET_TIMER_THRESHOLD_MASK 0000400000 -#define MAC_DMA_IMR_S5_NDP_TIMER_THRESHOLD_MASK 0x00800000 -#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_MASK 0xFF000000 -#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_LSB 24 -#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD(_i) (0x01000000 << (_i)) - -#define MAC_DMA_ISR_RAC_ADDRESS 0x000000C0 /* ISR read-and-clear access */ - -/* Shadow copies with read-and-clear access */ -#define MAC_DMA_ISR_S0_S_ADDRESS 0x000000C4 /* ISR_S0 shadow copy */ -#define MAC_DMA_ISR_S1_S_ADDRESS 0x000000C8 /* ISR_S1 shadow copy */ -#define MAC_DMA_ISR_S2_S_ADDRESS 0x000000Cc /* ISR_S2 shadow copy */ -#define MAC_DMA_ISR_S3_S_ADDRESS 0x000000D0 /* ISR_S3 shadow copy */ -#define MAC_DMA_ISR_S4_S_ADDRESS 0x000000D4 /* ISR_S4 shadow copy */ -#define MAC_DMA_ISR_S5_S_ADDRESS 0x000000D8 /* ISR_S5 shadow copy */ - -#define MAC_DMA_Q0_TXDP_ADDRESS 0x00000800 /* MAC Transmit Queue descriptor pointer */ -#define MAC_DMA_Q1_TXDP_ADDRESS 0x00000804 /* MAC Transmit Queue descriptor pointer */ -#define MAC_DMA_Q2_TXDP_ADDRESS 0x00000808 /* MAC Transmit Queue descriptor pointer */ -#define MAC_DMA_Q3_TXDP_ADDRESS 0x0000080C /* MAC Transmit Queue descriptor pointer */ -#define MAC_DMA_Q4_TXDP_ADDRESS 0x00000810 /* MAC Transmit Queue descriptor pointer */ -#define MAC_DMA_Q5_TXDP_ADDRESS 0x00000814 /* MAC Transmit Queue descriptor pointer */ -#define MAC_DMA_Q6_TXDP_ADDRESS 0x00000818 /* MAC Transmit Queue descriptor pointer */ -#define MAC_DMA_Q7_TXDP_ADDRESS 0x0000081C /* MAC Transmit Queue descriptor pointer */ -#define MAC_DMA_Q8_TXDP_ADDRESS 0x00000820 /* MAC Transmit Queue descriptor pointer */ -#define MAC_DMA_Q9_TXDP_ADDRESS 0x00000824 /* MAC Transmit Queue descriptor pointer */ -#define MAC_DMA_QTXDP_ADDRESS(_i) (MAC_DMA_Q0_TXDP_ADDRESS + ((_i)<<2)) - -#define MAC_DMA_Q_TXE_ADDRESS 0x00000840 /* MAC Transmit Queue enable */ -#define MAC_DMA_Q_TXD_ADDRESS 0x00000880 /* MAC Transmit Queue disable */ -/* QCU registers */ - -#define MAC_DMA_Q0_CBRCFG_ADDRESS 0x000008C0 /* MAC CBR configuration */ -#define MAC_DMA_Q1_CBRCFG_ADDRESS 0x000008C4 /* MAC CBR configuration */ -#define MAC_DMA_Q2_CBRCFG_ADDRESS 0x000008C8 /* MAC CBR configuration */ -#define MAC_DMA_Q3_CBRCFG_ADDRESS 0x000008CC /* MAC CBR configuration */ -#define MAC_DMA_Q4_CBRCFG_ADDRESS 0x000008D0 /* MAC CBR configuration */ -#define MAC_DMA_Q5_CBRCFG_ADDRESS 0x000008D4 /* MAC CBR configuration */ -#define MAC_DMA_Q6_CBRCFG_ADDRESS 0x000008D8 /* MAC CBR configuration */ -#define MAC_DMA_Q7_CBRCFG_ADDRESS 0x000008DC /* MAC CBR configuration */ -#define MAC_DMA_Q8_CBRCFG_ADDRESS 0x000008E0 /* MAC CBR configuration */ -#define MAC_DMA_Q9_CBRCFG_ADDRESS 0x000008E4 /* MAC CBR configuration */ -#define MAC_DMA_QCBRCFG_ADDRESS(_i) (MAC_DMA_Q0_CBRCFG_ADDRESS + ((_i)<<2)) - -#define MAC_DMA_Q_CBRCFG_CBR_INTERVAL_MASK 0x00FFFFFF /* Mask for CBR interval (us) */ -#define MAC_DMA_Q_CBRCFG_CBR_INTERVAL_LSB 0 /* Shift for CBR interval */ -#define MAC_DMA_Q_CBRCFG_CBR_OVF_THRESH_MASK 0xFF000000 /* Mask for CBR overflow threshold */ -#define MAC_DMA_Q_CBRCFG_CBR_OVF_THRESH_LSB 24 /* Shift for CBR overflow thresh */ - - -#define MAC_DMA_Q0_RDYTIMECFG_ADDRESS 0x00000900 /* MAC ReadyTime configuration */ -#define MAC_DMA_Q1_RDYTIMECFG_ADDRESS 0x00000904 /* MAC ReadyTime configuration */ -#define MAC_DMA_Q2_RDYTIMECFG_ADDRESS 0x00000908 /* MAC ReadyTime configuration */ -#define MAC_DMA_Q3_RDYTIMECFG_ADDRESS 0x0000090C /* MAC ReadyTime configuration */ -#define MAC_DMA_Q4_RDYTIMECFG_ADDRESS 0x00000910 /* MAC ReadyTime configuration */ -#define MAC_DMA_Q5_RDYTIMECFG_ADDRESS 0x00000914 /* MAC ReadyTime configuration */ -#define MAC_DMA_Q6_RDYTIMECFG_ADDRESS 0x00000918 /* MAC ReadyTime configuration */ -#define MAC_DMA_Q7_RDYTIMECFG_ADDRESS 0x0000091C /* MAC ReadyTime configuration */ -#define MAC_DMA_Q8_RDYTIMECFG_ADDRESS 0x00000920 /* MAC ReadyTime configuration */ -#define MAC_DMA_Q9_RDYTIMECFG_ADDRESS 0x00000924 /* MAC ReadyTime configuration */ -#define MAC_DMA_QRDYTIMECFG_ADDRESS(_i) (MAC_DMA_Q0_RDYTIMECFG_ADDRESS + ((_i)<<2)) - -#define MAC_DMA_Q_RDYTIMECFG_INT_MASK 0x00FFFFFF /* CBR interval (us) */ -#define MAC_DMA_Q_RDYTIMECFG_INT_LSB 0 /* Shift for ReadyTime Interval (us) */ -#define MAC_DMA_Q_RDYTIMECFG_ENA_MASK 0x01000000 /* CBR enable */ - -#define MAC_DMA_Q_ONESHOTMAC_DMAM_SC_ADDRESS 0x00000940 /* MAC OneShotArm set control */ -#define MAC_DMA_Q_ONESHOTMAC_DMAM_CC_ADDRESS 0x00000980 /* MAC OneShotArm clear control */ - -#define MAC_DMA_Q0_MISC_ADDRESS 0x000009C0 /* MAC Miscellaneous QCU settings */ -#define MAC_DMA_Q1_MISC_ADDRESS 0x000009C4 /* MAC Miscellaneous QCU settings */ -#define MAC_DMA_Q2_MISC_ADDRESS 0x000009C8 /* MAC Miscellaneous QCU settings */ -#define MAC_DMA_Q3_MISC_ADDRESS 0x000009CC /* MAC Miscellaneous QCU settings */ -#define MAC_DMA_Q4_MISC_ADDRESS 0x000009D0 /* MAC Miscellaneous QCU settings */ -#define MAC_DMA_Q5_MISC_ADDRESS 0x000009D4 /* MAC Miscellaneous QCU settings */ -#define MAC_DMA_Q6_MISC_ADDRESS 0x000009D8 /* MAC Miscellaneous QCU settings */ -#define MAC_DMA_Q7_MISC_ADDRESS 0x000009DC /* MAC Miscellaneous QCU settings */ -#define MAC_DMA_Q8_MISC_ADDRESS 0x000009E0 /* MAC Miscellaneous QCU settings */ -#define MAC_DMA_Q9_MISC_ADDRESS 0x000009E4 /* MAC Miscellaneous QCU settings */ -#define MAC_DMA_QMISC_ADDRESS(_i) (MAC_DMA_Q0_MISC_ADDRESS + ((_i)<<2)) - -#define MAC_DMA_Q_MISC_FSP_MASK 0x0000000F /* Frame Scheduling Policy mask */ -#define MAC_DMA_Q_MISC_FSP_ASAP 0 /* ASAP */ -#define MAC_DMA_Q_MISC_FSP_CBR 1 /* CBR */ -#define MAC_DMA_Q_MISC_FSP_DBA_GATED 2 /* DMA Beacon Alert gated */ -#define MAC_DMA_Q_MISC_FSP_TIM_GATED 3 /* TIM gated */ -#define MAC_DMA_Q_MISC_FSP_BEACON_SENT_GATED 4 /* Beacon-sent-gated */ -#define MAC_DMA_Q_MISC_ONE_SHOT_EN_MASK 0x00000010 /* OneShot enable */ -#define MAC_DMA_Q_MISC_CBR_INCR_DIS1_MASK 0x00000020 /* Disable CBR expired counter incr - (empty q) */ -#define MAC_DMA_Q_MISC_CBR_INCR_DIS0_MASK 0x00000040 /* Disable CBR expired counter incr - (empty beacon q) */ -#define MAC_DMA_Q_MISC_BEACON_USE_MASK 0x00000080 /* Beacon use indication */ -#define MAC_DMA_Q_MISC_CBR_EXP_CNTR_LIMIT_MASK 0x00000100 /* CBR expired counter limit enable */ -#define MAC_DMA_Q_MISC_RDYTIME_EXP_POLICY_MASK 0x00000200 /* Enable TXE cleared on ReadyTime expired or VEOL */ -#define MAC_DMA_Q_MISC_RESET_CBR_EXP_CTR_MASK 0x00000400 /* Reset CBR expired counter */ -#define MAC_DMA_Q_MISC_DCU_EARLY_TERM_REQ_MASK 0x00000800 /* DCU frame early termination request control */ - -#define MAC_DMA_Q0_STS_ADDRESS 0x00000A00 /* MAC Miscellaneous QCU status */ -#define MAC_DMA_Q1_STS_ADDRESS 0x00000A04 /* MAC Miscellaneous QCU status */ -#define MAC_DMA_Q2_STS_ADDRESS 0x00000A08 /* MAC Miscellaneous QCU status */ -#define MAC_DMA_Q3_STS_ADDRESS 0x00000A0C /* MAC Miscellaneous QCU status */ -#define MAC_DMA_Q4_STS_ADDRESS 0x00000A10 /* MAC Miscellaneous QCU status */ -#define MAC_DMA_Q5_STS_ADDRESS 0x00000A14 /* MAC Miscellaneous QCU status */ -#define MAC_DMA_Q6_STS_ADDRESS 0x00000A18 /* MAC Miscellaneous QCU status */ -#define MAC_DMA_Q7_STS_ADDRESS 0x00000A1C /* MAC Miscellaneous QCU status */ -#define MAC_DMA_Q8_STS_ADDRESS 0x00000A20 /* MAC Miscellaneous QCU status */ -#define MAC_DMA_Q9_STS_ADDRESS 0x00000A24 /* MAC Miscellaneous QCU status */ -#define MAC_DMA_QSTS_ADDRESS(_i) (MAC_DMA_Q0_STS_ADDRESS + ((_i)<<2)) - -#define MAC_DMA_Q_STS_PEND_FR_CNT_MASK 0x00000003 /* Mask for Pending Frame Count */ -#define MAC_DMA_Q_STS_CBR_EXP_CNT_MASK 0x0000FF00 /* Mask for CBR expired counter */ - -#define MAC_DMA_Q_RDYTIMESHDN_ADDRESS 0x00000A40 /* MAC ReadyTimeShutdown status */ - -/* DCU registers */ - -#define MAC_DMA_D0_QCUMASK_ADDRESS 0x00001000 /* MAC QCU Mask */ -#define MAC_DMA_D1_QCUMASK_ADDRESS 0x00001004 /* MAC QCU Mask */ -#define MAC_DMA_D2_QCUMASK_ADDRESS 0x00001008 /* MAC QCU Mask */ -#define MAC_DMA_D3_QCUMASK_ADDRESS 0x0000100C /* MAC QCU Mask */ -#define MAC_DMA_D4_QCUMASK_ADDRESS 0x00001010 /* MAC QCU Mask */ -#define MAC_DMA_D5_QCUMASK_ADDRESS 0x00001014 /* MAC QCU Mask */ -#define MAC_DMA_D6_QCUMASK_ADDRESS 0x00001018 /* MAC QCU Mask */ -#define MAC_DMA_D7_QCUMASK_ADDRESS 0x0000101C /* MAC QCU Mask */ -#define MAC_DMA_D8_QCUMASK_ADDRESS 0x00001020 /* MAC QCU Mask */ -#define MAC_DMA_D9_QCUMASK_ADDRESS 0x00001024 /* MAC QCU Mask */ -#define MAC_DMA_DQCUMASK_ADDRESS(_i) (MAC_DMA_D0_QCUMASK_ADDRESS + ((_i)<<2)) - -#define MAC_DMA_D_QCUMASK_MASK 0x000003FF /* Mask for QCU Mask (QCU 0-9) */ - -#define MAC_DMA_D_GBL_IFS_SIFS_ADDRESS 0x00001030 /* DCU global SIFS settings */ - - -#define MAC_DMA_D0_LCL_IFS_ADDRESS 0x00001040 /* MAC DCU-specific IFS settings */ -#define MAC_DMA_D1_LCL_IFS_ADDRESS 0x00001044 /* MAC DCU-specific IFS settings */ -#define MAC_DMA_D2_LCL_IFS_ADDRESS 0x00001048 /* MAC DCU-specific IFS settings */ -#define MAC_DMA_D3_LCL_IFS_ADDRESS 0x0000104C /* MAC DCU-specific IFS settings */ -#define MAC_DMA_D4_LCL_IFS_ADDRESS 0x00001050 /* MAC DCU-specific IFS settings */ -#define MAC_DMA_D5_LCL_IFS_ADDRESS 0x00001054 /* MAC DCU-specific IFS settings */ -#define MAC_DMA_D6_LCL_IFS_ADDRESS 0x00001058 /* MAC DCU-specific IFS settings */ -#define MAC_DMA_D7_LCL_IFS_ADDRESS 0x0000105C /* MAC DCU-specific IFS settings */ -#define MAC_DMA_D8_LCL_IFS_ADDRESS 0x00001060 /* MAC DCU-specific IFS settings */ -#define MAC_DMA_D9_LCL_IFS_ADDRESS 0x00001064 /* MAC DCU-specific IFS settings */ -#define MAC_DMA_DLCL_IFS_ADDRESS(_i) (MAC_DMA_D0_LCL_IFS_ADDRESS + ((_i)<<2)) -#define MAC_DMA_D_LCL_IFS_CWMIN_MASK 0x000003FF /* Mask for CW_MIN */ -#define MAC_DMA_D_LCL_IFS_CWMIN_LSB 0 -#define MAC_DMA_D_LCL_IFS_CWMAX_MASK 0x000FFC00 /* Mask for CW_MAX */ -#define MAC_DMA_D_LCL_IFS_CWMAX_LSB 10 -#define MAC_DMA_D_LCL_IFS_AIFS_MASK 0x0FF00000 /* Mask for AIFS */ -#define MAC_DMA_D_LCL_IFS_AIFS_LSB 20 -/* - * Note: even though this field is 8 bits wide the - * maximum supported AIFS value is 0xFc. Setting the AIFS value - * to 0xFd 0xFe, or 0xFf will not work correctly and will cause - * the DCU to hang. - */ -#define MAC_DMA_D_GBL_IFS_SLOT_ADDRESS 0x00001070 /* DC global slot interval */ - -#define MAC_DMA_D0_RETRY_LIMIT_ADDRESS 0x00001080 /* MAC Retry limits */ -#define MAC_DMA_D1_RETRY_LIMIT_ADDRESS 0x00001084 /* MAC Retry limits */ -#define MAC_DMA_D2_RETRY_LIMIT_ADDRESS 0x00001088 /* MAC Retry limits */ -#define MAC_DMA_D3_RETRY_LIMIT_ADDRESS 0x0000108C /* MAC Retry limits */ -#define MAC_DMA_D4_RETRY_LIMIT_ADDRESS 0x00001090 /* MAC Retry limits */ -#define MAC_DMA_D5_RETRY_LIMIT_ADDRESS 0x00001094 /* MAC Retry limits */ -#define MAC_DMA_D6_RETRY_LIMIT_ADDRESS 0x00001098 /* MAC Retry limits */ -#define MAC_DMA_D7_RETRY_LIMIT_ADDRESS 0x0000109C /* MAC Retry limits */ -#define MAC_DMA_D8_RETRY_LIMIT_ADDRESS 0x000010A0 /* MAC Retry limits */ -#define MAC_DMA_D9_RETRY_LIMIT_ADDRESS 0x000010A4 /* MAC Retry limits */ -#define MAC_DMA_DRETRY_LIMIT_ADDRESS(_i) (MAC_DMA_D0_RETRY_LIMIT_ADDRESS + ((_i)<<2)) - -#define MAC_DMA_D_RETRY_LIMIT_FR_RTS_MASK 0x0000000F /* frame RTS failure limit */ -#define MAC_DMA_D_RETRY_LIMIT_FR_RTS_LSB 0 -#define MAC_DMA_D_RETRY_LIMIT_STA_RTS_MASK 0x00003F00 /* station RTS failure limit */ -#define MAC_DMA_D_RETRY_LIMIT_STA_RTS_LSB 8 -#define MAC_DMA_D_RETRY_LIMIT_STA_DATA_MASK 0x000FC000 /* station short retry limit */ -#define MAC_DMA_D_RETRY_LIMIT_STA_DATA_LSB 14 - -#define MAC_DMA_D_GBL_IFS_EIFS_ADDRESS 0x000010B0 /* DCU global EIFS setting */ - -#define MAC_DMA_D0_CHNTIME_ADDRESS 0x000010C0 /* MAC ChannelTime settings */ -#define MAC_DMA_D1_CHNTIME_ADDRESS 0x000010C4 /* MAC ChannelTime settings */ -#define MAC_DMA_D2_CHNTIME_ADDRESS 0x000010C8 /* MAC ChannelTime settings */ -#define MAC_DMA_D3_CHNTIME_ADDRESS 0x000010CC /* MAC ChannelTime settings */ -#define MAC_DMA_D4_CHNTIME_ADDRESS 0x000010D0 /* MAC ChannelTime settings */ -#define MAC_DMA_D5_CHNTIME_ADDRESS 0x000010D4 /* MAC ChannelTime settings */ -#define MAC_DMA_D6_CHNTIME_ADDRESS 0x000010D8 /* MAC ChannelTime settings */ -#define MAC_DMA_D7_CHNTIME_ADDRESS 0x000010DC /* MAC ChannelTime settings */ -#define MAC_DMA_D8_CHNTIME_ADDRESS 0x000010E0 /* MAC ChannelTime settings */ -#define MAC_DMA_D9_CHNTIME_ADDRESS 0x000010E4 /* MAC ChannelTime settings */ -#define MAC_DMA_DCHNTIME_ADDRESS(_i) (MAC_DMA_D0_CHNTIME_ADDRESS + ((_i)<<2)) - -#define MAC_DMA_D_CHNTIME_DUR_MASK 0x000FFFFF /* ChannelTime duration (us) */ -#define MAC_DMA_D_CHNTIME_DUR_LSB 0 /* Shift for ChannelTime duration */ -#define MAC_DMA_D_CHNTIME_EN_MASK 0x00100000 /* ChannelTime enable */ - -#define MAC_DMA_D_GBL_IFS_MISC_ADDRESS 0x000010f0 /* DCU global misc. IFS settings */ -#define MAC_DMA_D_GBL_IFS_MISC_LFSR_SLICE_SEL_MASK 0x00000007 /* LFSR slice select */ -#define MAC_DMA_D_GBL_IFS_MISC_TURBO_MODE_MASK 0x00000008 /* Turbo mode indication */ -#define MAC_DMA_D_GBL_IFS_MISC_DCU_ARBITER_DLY_MASK 0x00300000 /* DCU arbiter delay */ -#define MAC_DMA_D_GBL_IFS_IGNORE_BACKOFF_MASK 0x10000000 - -#define MAC_DMA_D0_MISC_ADDRESS 0x00001100 /* MAC Miscellaneous DCU-specific settings */ -#define MAC_DMA_D1_MISC_ADDRESS 0x00001104 /* MAC Miscellaneous DCU-specific settings */ -#define MAC_DMA_D2_MISC_ADDRESS 0x00001108 /* MAC Miscellaneous DCU-specific settings */ -#define MAC_DMA_D3_MISC_ADDRESS 0x0000110C /* MAC Miscellaneous DCU-specific settings */ -#define MAC_DMA_D4_MISC_ADDRESS 0x00001110 /* MAC Miscellaneous DCU-specific settings */ -#define MAC_DMA_D5_MISC_ADDRESS 0x00001114 /* MAC Miscellaneous DCU-specific settings */ -#define MAC_DMA_D6_MISC_ADDRESS 0x00001118 /* MAC Miscellaneous DCU-specific settings */ -#define MAC_DMA_D7_MISC_ADDRESS 0x0000111C /* MAC Miscellaneous DCU-specific settings */ -#define MAC_DMA_D8_MISC_ADDRESS 0x00001120 /* MAC Miscellaneous DCU-specific settings */ -#define MAC_DMA_D9_MISC_ADDRESS 0x00001124 /* MAC Miscellaneous DCU-specific settings */ -#define MAC_DMA_DMISC_ADDRESS(_i) (MAC_DMA_D0_MISC_ADDRESS + ((_i)<<2)) - -#define MAC_DMA_D0_EOL_ADDRESS 0x00001180 -#define MAC_DMA_D1_EOL_ADDRESS 0x00001184 -#define MAC_DMA_D2_EOL_ADDRESS 0x00001188 -#define MAC_DMA_D3_EOL_ADDRESS 0x0000118C -#define MAC_DMA_D4_EOL_ADDRESS 0x00001190 -#define MAC_DMA_D5_EOL_ADDRESS 0x00001194 -#define MAC_DMA_D6_EOL_ADDRESS 0x00001198 -#define MAC_DMA_D7_EOL_ADDRESS 0x0000119C -#define MAC_DMA_D8_EOL_ADDRESS 0x00001200 -#define MAC_DMA_D9_EOL_ADDRESS 0x00001204 -#define MAC_DMA_DEOL_ADDRESS(_i) (MAC_DMA_D0_EOL_ADDRESS + ((_i)<<2)) - -#define MAC_DMA_D_MISC_BKOFF_THRESH_MASK 0x0000003F /* Backoff threshold */ -#define MAC_DMA_D_MISC_BACK_OFF_THRESH_LSB 0 -#define MAC_DMA_D_MISC_ETS_RTS_MASK 0x00000040 /* End of transmission series - station RTS/data failure - count reset policy */ -#define MAC_DMA_D_MISC_ETS_CW_MASK 0x00000080 /* End of transmission series - CW reset policy */ -#define MAC_DMA_D_MISC_FRAG_WAIT_EN_MASK 0x00000100 /* Fragment Starvation Policy */ - -#define MAC_DMA_D_MISC_FRAG_BKOFF_EN_MASK 0x00000200 /* Backoff during a frag burst */ -#define MAC_DMA_D_MISC_HCF_POLL_EN_MASK 0x00000800 /* HFC poll enable */ -#define MAC_DMA_D_MISC_BKOFF_PERSISTENCE_MASK 0x00001000 /* Backoff persistence factor - setting */ -#define MAC_DMA_D_MISC_VIR_COL_HANDLING_MASK 0x0000C000 /* Mask for Virtual collision - handling policy */ -#define MAC_DMA_D_MISC_VIR_COL_HANDLING_LSB 14 -#define MAC_DMA_D_MISC_VIR_COL_HANDLING_DEFAULT 0 /* Normal */ -#define MAC_DMA_D_MISC_VIR_COL_HANDLING_IGNORE 1 /* Ignore */ -#define MAC_DMA_D_MISC_BEACON_USE_MASK 0x00010000 /* Beacon use indication */ -#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_MASK 0x00060000 /* Mask for DCU arbiter lockout control */ -#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_LSB 17 -#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_NONE 0 /* No lockout*/ -#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1 /* Intra-frame*/ -#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL 2 /* Global */ -#define MAC_DMA_D_MISC_ARB_LOCKOUT_IGNORE_MASK 0x00080000 /* DCU arbiter lockout ignore control */ -#define MAC_DMA_D_MISC_SEQ_NUM_INCR_DIS_MASK 0x00100000 /* Sequence number increment disable */ -#define MAC_DMA_D_MISC_POST_FR_BKOFF_DIS_MASK 0x00200000 /* Post-frame backoff disable */ -#define MAC_DMA_D_MISC_VIRT_COLL_POLICY_MASK 0x00400000 /* Virtual coll. handling policy */ -#define MAC_DMA_D_MISC_BLOWN_IFS_POLICY_MASK 0x00800000 /* Blown IFS handling policy */ - -#define MAC_DMA_D_SEQNUM_ADDRESS 0x00001140 /* MAC Frame sequence number */ - - - -#define MAC_DMA_D_FPCTL_ADDRESS 0x00001230 /* DCU frame prefetch settings */ -#define MAC_DMA_D_TXPSE_ADDRESS 0x00001270 /* DCU transmit pause control/status */ - -#endif /* _AR6000_DMMAEG_H_ */ diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mac_pcu_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mac_pcu_reg.h deleted file mode 100644 index 6ccb08c5dab2..000000000000 --- a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mac_pcu_reg.h +++ /dev/null @@ -1,3065 +0,0 @@ -// ------------------------------------------------------------------ -// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. -// -// -// Permission to use, copy, modify, and/or distribute this software for any -// purpose with or without fee is hereby granted, provided that the above -// copyright notice and this permission notice appear in all copies. -// -// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -// -// -// ------------------------------------------------------------------ -//=================================================================== -// Author(s): ="Atheros" -//=================================================================== - - -#ifndef _MAC_PCU_REG_H_ -#define _MAC_PCU_REG_H_ - -#define MAC_PCU_STA_ADDR_L32_ADDRESS 0x00008000 -#define MAC_PCU_STA_ADDR_L32_OFFSET 0x00000000 -#define MAC_PCU_STA_ADDR_L32_ADDR_31_0_MSB 31 -#define MAC_PCU_STA_ADDR_L32_ADDR_31_0_LSB 0 -#define MAC_PCU_STA_ADDR_L32_ADDR_31_0_MASK 0xffffffff -#define MAC_PCU_STA_ADDR_L32_ADDR_31_0_GET(x) (((x) & MAC_PCU_STA_ADDR_L32_ADDR_31_0_MASK) >> MAC_PCU_STA_ADDR_L32_ADDR_31_0_LSB) -#define MAC_PCU_STA_ADDR_L32_ADDR_31_0_SET(x) (((x) << MAC_PCU_STA_ADDR_L32_ADDR_31_0_LSB) & MAC_PCU_STA_ADDR_L32_ADDR_31_0_MASK) - -#define MAC_PCU_STA_ADDR_U16_ADDRESS 0x00008004 -#define MAC_PCU_STA_ADDR_U16_OFFSET 0x00000004 -#define MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_MSB 31 -#define MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_LSB 31 -#define MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_MASK 0x80000000 -#define MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_MASK) >> MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_LSB) -#define MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_LSB) & MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_MASK) -#define MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_MSB 30 -#define MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_LSB 30 -#define MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_MASK 0x40000000 -#define MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_MASK) >> MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_LSB) -#define MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_LSB) & MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_MASK) -#define MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_MSB 29 -#define MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_LSB 29 -#define MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_MASK 0x20000000 -#define MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_MASK) >> MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_LSB) -#define MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_LSB) & MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_MASK) -#define MAC_PCU_STA_ADDR_U16_KSRCH_MODE_MSB 28 -#define MAC_PCU_STA_ADDR_U16_KSRCH_MODE_LSB 28 -#define MAC_PCU_STA_ADDR_U16_KSRCH_MODE_MASK 0x10000000 -#define MAC_PCU_STA_ADDR_U16_KSRCH_MODE_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_KSRCH_MODE_MASK) >> MAC_PCU_STA_ADDR_U16_KSRCH_MODE_LSB) -#define MAC_PCU_STA_ADDR_U16_KSRCH_MODE_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_KSRCH_MODE_LSB) & MAC_PCU_STA_ADDR_U16_KSRCH_MODE_MASK) -#define MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_MSB 27 -#define MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_LSB 27 -#define MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_MASK 0x08000000 -#define MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_MASK) >> MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_LSB) -#define MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_LSB) & MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_MASK) -#define MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_MSB 26 -#define MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_LSB 26 -#define MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_MASK 0x04000000 -#define MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_MASK) >> MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_LSB) -#define MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_LSB) & MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_MASK) -#define MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_MSB 25 -#define MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_LSB 25 -#define MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_MASK 0x02000000 -#define MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_MASK) >> MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_LSB) -#define MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_LSB) & MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_MASK) -#define MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_MSB 24 -#define MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_LSB 24 -#define MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_MASK 0x01000000 -#define MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_MASK) >> MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_LSB) -#define MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_LSB) & MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_MASK) -#define MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_MSB 23 -#define MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_LSB 23 -#define MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_MASK 0x00800000 -#define MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_MASK) >> MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_LSB) -#define MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_LSB) & MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_MASK) -#define MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_MSB 22 -#define MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_LSB 22 -#define MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_MASK 0x00400000 -#define MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_MASK) >> MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_LSB) -#define MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_LSB) & MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_MASK) -#define MAC_PCU_STA_ADDR_U16_USE_DEFANT_MSB 21 -#define MAC_PCU_STA_ADDR_U16_USE_DEFANT_LSB 21 -#define MAC_PCU_STA_ADDR_U16_USE_DEFANT_MASK 0x00200000 -#define MAC_PCU_STA_ADDR_U16_USE_DEFANT_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_USE_DEFANT_MASK) >> MAC_PCU_STA_ADDR_U16_USE_DEFANT_LSB) -#define MAC_PCU_STA_ADDR_U16_USE_DEFANT_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_USE_DEFANT_LSB) & MAC_PCU_STA_ADDR_U16_USE_DEFANT_MASK) -#define MAC_PCU_STA_ADDR_U16_PCF_MSB 20 -#define MAC_PCU_STA_ADDR_U16_PCF_LSB 20 -#define MAC_PCU_STA_ADDR_U16_PCF_MASK 0x00100000 -#define MAC_PCU_STA_ADDR_U16_PCF_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_PCF_MASK) >> MAC_PCU_STA_ADDR_U16_PCF_LSB) -#define MAC_PCU_STA_ADDR_U16_PCF_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_PCF_LSB) & MAC_PCU_STA_ADDR_U16_PCF_MASK) -#define MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_MSB 19 -#define MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_LSB 19 -#define MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_MASK 0x00080000 -#define MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_MASK) >> MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_LSB) -#define MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_LSB) & MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_MASK) -#define MAC_PCU_STA_ADDR_U16_PW_SAVE_MSB 18 -#define MAC_PCU_STA_ADDR_U16_PW_SAVE_LSB 18 -#define MAC_PCU_STA_ADDR_U16_PW_SAVE_MASK 0x00040000 -#define MAC_PCU_STA_ADDR_U16_PW_SAVE_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_PW_SAVE_MASK) >> MAC_PCU_STA_ADDR_U16_PW_SAVE_LSB) -#define MAC_PCU_STA_ADDR_U16_PW_SAVE_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_PW_SAVE_LSB) & MAC_PCU_STA_ADDR_U16_PW_SAVE_MASK) -#define MAC_PCU_STA_ADDR_U16_ADHOC_MSB 17 -#define MAC_PCU_STA_ADDR_U16_ADHOC_LSB 17 -#define MAC_PCU_STA_ADDR_U16_ADHOC_MASK 0x00020000 -#define MAC_PCU_STA_ADDR_U16_ADHOC_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_ADHOC_MASK) >> MAC_PCU_STA_ADDR_U16_ADHOC_LSB) -#define MAC_PCU_STA_ADDR_U16_ADHOC_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_ADHOC_LSB) & MAC_PCU_STA_ADDR_U16_ADHOC_MASK) -#define MAC_PCU_STA_ADDR_U16_STA_AP_MSB 16 -#define MAC_PCU_STA_ADDR_U16_STA_AP_LSB 16 -#define MAC_PCU_STA_ADDR_U16_STA_AP_MASK 0x00010000 -#define MAC_PCU_STA_ADDR_U16_STA_AP_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_STA_AP_MASK) >> MAC_PCU_STA_ADDR_U16_STA_AP_LSB) -#define MAC_PCU_STA_ADDR_U16_STA_AP_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_STA_AP_LSB) & MAC_PCU_STA_ADDR_U16_STA_AP_MASK) -#define MAC_PCU_STA_ADDR_U16_ADDR_47_32_MSB 15 -#define MAC_PCU_STA_ADDR_U16_ADDR_47_32_LSB 0 -#define MAC_PCU_STA_ADDR_U16_ADDR_47_32_MASK 0x0000ffff -#define MAC_PCU_STA_ADDR_U16_ADDR_47_32_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_ADDR_47_32_MASK) >> MAC_PCU_STA_ADDR_U16_ADDR_47_32_LSB) -#define MAC_PCU_STA_ADDR_U16_ADDR_47_32_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_ADDR_47_32_LSB) & MAC_PCU_STA_ADDR_U16_ADDR_47_32_MASK) - -#define MAC_PCU_BSSID_L32_ADDRESS 0x00008008 -#define MAC_PCU_BSSID_L32_OFFSET 0x00000008 -#define MAC_PCU_BSSID_L32_ADDR_MSB 31 -#define MAC_PCU_BSSID_L32_ADDR_LSB 0 -#define MAC_PCU_BSSID_L32_ADDR_MASK 0xffffffff -#define MAC_PCU_BSSID_L32_ADDR_GET(x) (((x) & MAC_PCU_BSSID_L32_ADDR_MASK) >> MAC_PCU_BSSID_L32_ADDR_LSB) -#define MAC_PCU_BSSID_L32_ADDR_SET(x) (((x) << MAC_PCU_BSSID_L32_ADDR_LSB) & MAC_PCU_BSSID_L32_ADDR_MASK) - -#define MAC_PCU_BSSID_U16_ADDRESS 0x0000800c -#define MAC_PCU_BSSID_U16_OFFSET 0x0000000c -#define MAC_PCU_BSSID_U16_AID_MSB 26 -#define MAC_PCU_BSSID_U16_AID_LSB 16 -#define MAC_PCU_BSSID_U16_AID_MASK 0x07ff0000 -#define MAC_PCU_BSSID_U16_AID_GET(x) (((x) & MAC_PCU_BSSID_U16_AID_MASK) >> MAC_PCU_BSSID_U16_AID_LSB) -#define MAC_PCU_BSSID_U16_AID_SET(x) (((x) << MAC_PCU_BSSID_U16_AID_LSB) & MAC_PCU_BSSID_U16_AID_MASK) -#define MAC_PCU_BSSID_U16_ADDR_MSB 15 -#define MAC_PCU_BSSID_U16_ADDR_LSB 0 -#define MAC_PCU_BSSID_U16_ADDR_MASK 0x0000ffff -#define MAC_PCU_BSSID_U16_ADDR_GET(x) (((x) & MAC_PCU_BSSID_U16_ADDR_MASK) >> MAC_PCU_BSSID_U16_ADDR_LSB) -#define MAC_PCU_BSSID_U16_ADDR_SET(x) (((x) << MAC_PCU_BSSID_U16_ADDR_LSB) & MAC_PCU_BSSID_U16_ADDR_MASK) - -#define MAC_PCU_BCN_RSSI_AVE_ADDRESS 0x00008010 -#define MAC_PCU_BCN_RSSI_AVE_OFFSET 0x00000010 -#define MAC_PCU_BCN_RSSI_AVE_VALUE_MSB 11 -#define MAC_PCU_BCN_RSSI_AVE_VALUE_LSB 0 -#define MAC_PCU_BCN_RSSI_AVE_VALUE_MASK 0x00000fff -#define MAC_PCU_BCN_RSSI_AVE_VALUE_GET(x) (((x) & MAC_PCU_BCN_RSSI_AVE_VALUE_MASK) >> MAC_PCU_BCN_RSSI_AVE_VALUE_LSB) -#define MAC_PCU_BCN_RSSI_AVE_VALUE_SET(x) (((x) << MAC_PCU_BCN_RSSI_AVE_VALUE_LSB) & MAC_PCU_BCN_RSSI_AVE_VALUE_MASK) - -#define MAC_PCU_ACK_CTS_TIMEOUT_ADDRESS 0x00008014 -#define MAC_PCU_ACK_CTS_TIMEOUT_OFFSET 0x00000014 -#define MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_MSB 29 -#define MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_LSB 16 -#define MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_MASK 0x3fff0000 -#define MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_GET(x) (((x) & MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_MASK) >> MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_LSB) -#define MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_SET(x) (((x) << MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_LSB) & MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_MASK) -#define MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_MSB 13 -#define MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_LSB 0 -#define MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_MASK 0x00003fff -#define MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_GET(x) (((x) & MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_MASK) >> MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_LSB) -#define MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_SET(x) (((x) << MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_LSB) & MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_MASK) - -#define MAC_PCU_BCN_RSSI_CTL_ADDRESS 0x00008018 -#define MAC_PCU_BCN_RSSI_CTL_OFFSET 0x00000018 -#define MAC_PCU_BCN_RSSI_CTL_RESET_MSB 29 -#define MAC_PCU_BCN_RSSI_CTL_RESET_LSB 29 -#define MAC_PCU_BCN_RSSI_CTL_RESET_MASK 0x20000000 -#define MAC_PCU_BCN_RSSI_CTL_RESET_GET(x) (((x) & MAC_PCU_BCN_RSSI_CTL_RESET_MASK) >> MAC_PCU_BCN_RSSI_CTL_RESET_LSB) -#define MAC_PCU_BCN_RSSI_CTL_RESET_SET(x) (((x) << MAC_PCU_BCN_RSSI_CTL_RESET_LSB) & MAC_PCU_BCN_RSSI_CTL_RESET_MASK) -#define MAC_PCU_BCN_RSSI_CTL_WEIGHT_MSB 28 -#define MAC_PCU_BCN_RSSI_CTL_WEIGHT_LSB 24 -#define MAC_PCU_BCN_RSSI_CTL_WEIGHT_MASK 0x1f000000 -#define MAC_PCU_BCN_RSSI_CTL_WEIGHT_GET(x) (((x) & MAC_PCU_BCN_RSSI_CTL_WEIGHT_MASK) >> MAC_PCU_BCN_RSSI_CTL_WEIGHT_LSB) -#define MAC_PCU_BCN_RSSI_CTL_WEIGHT_SET(x) (((x) << MAC_PCU_BCN_RSSI_CTL_WEIGHT_LSB) & MAC_PCU_BCN_RSSI_CTL_WEIGHT_MASK) -#define MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_MSB 23 -#define MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_LSB 16 -#define MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_MASK 0x00ff0000 -#define MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_GET(x) (((x) & MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_MASK) >> MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_LSB) -#define MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_SET(x) (((x) << MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_LSB) & MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_MASK) -#define MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_MSB 15 -#define MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_LSB 8 -#define MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_MASK 0x0000ff00 -#define MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_GET(x) (((x) & MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_MASK) >> MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_LSB) -#define MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_SET(x) (((x) << MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_LSB) & MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_MASK) -#define MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_MSB 7 -#define MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_LSB 0 -#define MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_MASK 0x000000ff -#define MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_GET(x) (((x) & MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_MASK) >> MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_LSB) -#define MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_SET(x) (((x) << MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_LSB) & MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_MASK) - -#define MAC_PCU_USEC_LATENCY_ADDRESS 0x0000801c -#define MAC_PCU_USEC_LATENCY_OFFSET 0x0000001c -#define MAC_PCU_USEC_LATENCY_RX_LATENCY_MSB 28 -#define MAC_PCU_USEC_LATENCY_RX_LATENCY_LSB 23 -#define MAC_PCU_USEC_LATENCY_RX_LATENCY_MASK 0x1f800000 -#define MAC_PCU_USEC_LATENCY_RX_LATENCY_GET(x) (((x) & MAC_PCU_USEC_LATENCY_RX_LATENCY_MASK) >> MAC_PCU_USEC_LATENCY_RX_LATENCY_LSB) -#define MAC_PCU_USEC_LATENCY_RX_LATENCY_SET(x) (((x) << MAC_PCU_USEC_LATENCY_RX_LATENCY_LSB) & MAC_PCU_USEC_LATENCY_RX_LATENCY_MASK) -#define MAC_PCU_USEC_LATENCY_TX_LATENCY_MSB 22 -#define MAC_PCU_USEC_LATENCY_TX_LATENCY_LSB 14 -#define MAC_PCU_USEC_LATENCY_TX_LATENCY_MASK 0x007fc000 -#define MAC_PCU_USEC_LATENCY_TX_LATENCY_GET(x) (((x) & MAC_PCU_USEC_LATENCY_TX_LATENCY_MASK) >> MAC_PCU_USEC_LATENCY_TX_LATENCY_LSB) -#define MAC_PCU_USEC_LATENCY_TX_LATENCY_SET(x) (((x) << MAC_PCU_USEC_LATENCY_TX_LATENCY_LSB) & MAC_PCU_USEC_LATENCY_TX_LATENCY_MASK) -#define MAC_PCU_USEC_LATENCY_USEC_MSB 7 -#define MAC_PCU_USEC_LATENCY_USEC_LSB 0 -#define MAC_PCU_USEC_LATENCY_USEC_MASK 0x000000ff -#define MAC_PCU_USEC_LATENCY_USEC_GET(x) (((x) & MAC_PCU_USEC_LATENCY_USEC_MASK) >> MAC_PCU_USEC_LATENCY_USEC_LSB) -#define MAC_PCU_USEC_LATENCY_USEC_SET(x) (((x) << MAC_PCU_USEC_LATENCY_USEC_LSB) & MAC_PCU_USEC_LATENCY_USEC_MASK) - -#define PCU_MAX_CFP_DUR_ADDRESS 0x00008020 -#define PCU_MAX_CFP_DUR_OFFSET 0x00000020 -#define PCU_MAX_CFP_DUR_VALUE_MSB 15 -#define PCU_MAX_CFP_DUR_VALUE_LSB 0 -#define PCU_MAX_CFP_DUR_VALUE_MASK 0x0000ffff -#define PCU_MAX_CFP_DUR_VALUE_GET(x) (((x) & PCU_MAX_CFP_DUR_VALUE_MASK) >> PCU_MAX_CFP_DUR_VALUE_LSB) -#define PCU_MAX_CFP_DUR_VALUE_SET(x) (((x) << PCU_MAX_CFP_DUR_VALUE_LSB) & PCU_MAX_CFP_DUR_VALUE_MASK) - -#define MAC_PCU_RX_FILTER_ADDRESS 0x00008024 -#define MAC_PCU_RX_FILTER_OFFSET 0x00000024 -#define MAC_PCU_RX_FILTER_GENERIC_FILTER_MSB 25 -#define MAC_PCU_RX_FILTER_GENERIC_FILTER_LSB 24 -#define MAC_PCU_RX_FILTER_GENERIC_FILTER_MASK 0x03000000 -#define MAC_PCU_RX_FILTER_GENERIC_FILTER_GET(x) (((x) & MAC_PCU_RX_FILTER_GENERIC_FILTER_MASK) >> MAC_PCU_RX_FILTER_GENERIC_FILTER_LSB) -#define MAC_PCU_RX_FILTER_GENERIC_FILTER_SET(x) (((x) << MAC_PCU_RX_FILTER_GENERIC_FILTER_LSB) & MAC_PCU_RX_FILTER_GENERIC_FILTER_MASK) -#define MAC_PCU_RX_FILTER_GENERIC_FTYPE_MSB 23 -#define MAC_PCU_RX_FILTER_GENERIC_FTYPE_LSB 18 -#define MAC_PCU_RX_FILTER_GENERIC_FTYPE_MASK 0x00fc0000 -#define MAC_PCU_RX_FILTER_GENERIC_FTYPE_GET(x) (((x) & MAC_PCU_RX_FILTER_GENERIC_FTYPE_MASK) >> MAC_PCU_RX_FILTER_GENERIC_FTYPE_LSB) -#define MAC_PCU_RX_FILTER_GENERIC_FTYPE_SET(x) (((x) << MAC_PCU_RX_FILTER_GENERIC_FTYPE_LSB) & MAC_PCU_RX_FILTER_GENERIC_FTYPE_MASK) -#define MAC_PCU_RX_FILTER_FROM_TO_DS_MSB 17 -#define MAC_PCU_RX_FILTER_FROM_TO_DS_LSB 17 -#define MAC_PCU_RX_FILTER_FROM_TO_DS_MASK 0x00020000 -#define MAC_PCU_RX_FILTER_FROM_TO_DS_GET(x) (((x) & MAC_PCU_RX_FILTER_FROM_TO_DS_MASK) >> MAC_PCU_RX_FILTER_FROM_TO_DS_LSB) -#define MAC_PCU_RX_FILTER_FROM_TO_DS_SET(x) (((x) << MAC_PCU_RX_FILTER_FROM_TO_DS_LSB) & MAC_PCU_RX_FILTER_FROM_TO_DS_MASK) -#define MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_MSB 16 -#define MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_LSB 16 -#define MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_MASK 0x00010000 -#define MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_GET(x) (((x) & MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_MASK) >> MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_LSB) -#define MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_SET(x) (((x) << MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_LSB) & MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_MASK) -#define MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_MSB 15 -#define MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_LSB 15 -#define MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_MASK 0x00008000 -#define MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_GET(x) (((x) & MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_MASK) >> MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_LSB) -#define MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_SET(x) (((x) << MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_LSB) & MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_MASK) -#define MAC_PCU_RX_FILTER_PS_POLL_MSB 14 -#define MAC_PCU_RX_FILTER_PS_POLL_LSB 14 -#define MAC_PCU_RX_FILTER_PS_POLL_MASK 0x00004000 -#define MAC_PCU_RX_FILTER_PS_POLL_GET(x) (((x) & MAC_PCU_RX_FILTER_PS_POLL_MASK) >> MAC_PCU_RX_FILTER_PS_POLL_LSB) -#define MAC_PCU_RX_FILTER_PS_POLL_SET(x) (((x) << MAC_PCU_RX_FILTER_PS_POLL_LSB) & MAC_PCU_RX_FILTER_PS_POLL_MASK) -#define MAC_PCU_RX_FILTER_ASSUME_RADAR_MSB 13 -#define MAC_PCU_RX_FILTER_ASSUME_RADAR_LSB 13 -#define MAC_PCU_RX_FILTER_ASSUME_RADAR_MASK 0x00002000 -#define MAC_PCU_RX_FILTER_ASSUME_RADAR_GET(x) (((x) & MAC_PCU_RX_FILTER_ASSUME_RADAR_MASK) >> MAC_PCU_RX_FILTER_ASSUME_RADAR_LSB) -#define MAC_PCU_RX_FILTER_ASSUME_RADAR_SET(x) (((x) << MAC_PCU_RX_FILTER_ASSUME_RADAR_LSB) & MAC_PCU_RX_FILTER_ASSUME_RADAR_MASK) -#define MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_MSB 12 -#define MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_LSB 12 -#define MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_MASK 0x00001000 -#define MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_GET(x) (((x) & MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_MASK) >> MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_LSB) -#define MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_SET(x) (((x) << MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_LSB) & MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_MASK) -#define MAC_PCU_RX_FILTER_COMPRESSED_BA_MSB 11 -#define MAC_PCU_RX_FILTER_COMPRESSED_BA_LSB 11 -#define MAC_PCU_RX_FILTER_COMPRESSED_BA_MASK 0x00000800 -#define MAC_PCU_RX_FILTER_COMPRESSED_BA_GET(x) (((x) & MAC_PCU_RX_FILTER_COMPRESSED_BA_MASK) >> MAC_PCU_RX_FILTER_COMPRESSED_BA_LSB) -#define MAC_PCU_RX_FILTER_COMPRESSED_BA_SET(x) (((x) << MAC_PCU_RX_FILTER_COMPRESSED_BA_LSB) & MAC_PCU_RX_FILTER_COMPRESSED_BA_MASK) -#define MAC_PCU_RX_FILTER_COMPRESSED_BAR_MSB 10 -#define MAC_PCU_RX_FILTER_COMPRESSED_BAR_LSB 10 -#define MAC_PCU_RX_FILTER_COMPRESSED_BAR_MASK 0x00000400 -#define MAC_PCU_RX_FILTER_COMPRESSED_BAR_GET(x) (((x) & MAC_PCU_RX_FILTER_COMPRESSED_BAR_MASK) >> MAC_PCU_RX_FILTER_COMPRESSED_BAR_LSB) -#define MAC_PCU_RX_FILTER_COMPRESSED_BAR_SET(x) (((x) << MAC_PCU_RX_FILTER_COMPRESSED_BAR_LSB) & MAC_PCU_RX_FILTER_COMPRESSED_BAR_MASK) -#define MAC_PCU_RX_FILTER_MY_BEACON_MSB 9 -#define MAC_PCU_RX_FILTER_MY_BEACON_LSB 9 -#define MAC_PCU_RX_FILTER_MY_BEACON_MASK 0x00000200 -#define MAC_PCU_RX_FILTER_MY_BEACON_GET(x) (((x) & MAC_PCU_RX_FILTER_MY_BEACON_MASK) >> MAC_PCU_RX_FILTER_MY_BEACON_LSB) -#define MAC_PCU_RX_FILTER_MY_BEACON_SET(x) (((x) << MAC_PCU_RX_FILTER_MY_BEACON_LSB) & MAC_PCU_RX_FILTER_MY_BEACON_MASK) -#define MAC_PCU_RX_FILTER_SYNC_FRAME_MSB 8 -#define MAC_PCU_RX_FILTER_SYNC_FRAME_LSB 8 -#define MAC_PCU_RX_FILTER_SYNC_FRAME_MASK 0x00000100 -#define MAC_PCU_RX_FILTER_SYNC_FRAME_GET(x) (((x) & MAC_PCU_RX_FILTER_SYNC_FRAME_MASK) >> MAC_PCU_RX_FILTER_SYNC_FRAME_LSB) -#define MAC_PCU_RX_FILTER_SYNC_FRAME_SET(x) (((x) << MAC_PCU_RX_FILTER_SYNC_FRAME_LSB) & MAC_PCU_RX_FILTER_SYNC_FRAME_MASK) -#define MAC_PCU_RX_FILTER_PROBE_REQ_MSB 7 -#define MAC_PCU_RX_FILTER_PROBE_REQ_LSB 7 -#define MAC_PCU_RX_FILTER_PROBE_REQ_MASK 0x00000080 -#define MAC_PCU_RX_FILTER_PROBE_REQ_GET(x) (((x) & MAC_PCU_RX_FILTER_PROBE_REQ_MASK) >> MAC_PCU_RX_FILTER_PROBE_REQ_LSB) -#define MAC_PCU_RX_FILTER_PROBE_REQ_SET(x) (((x) << MAC_PCU_RX_FILTER_PROBE_REQ_LSB) & MAC_PCU_RX_FILTER_PROBE_REQ_MASK) -#define MAC_PCU_RX_FILTER_XR_POLL_MSB 6 -#define MAC_PCU_RX_FILTER_XR_POLL_LSB 6 -#define MAC_PCU_RX_FILTER_XR_POLL_MASK 0x00000040 -#define MAC_PCU_RX_FILTER_XR_POLL_GET(x) (((x) & MAC_PCU_RX_FILTER_XR_POLL_MASK) >> MAC_PCU_RX_FILTER_XR_POLL_LSB) -#define MAC_PCU_RX_FILTER_XR_POLL_SET(x) (((x) << MAC_PCU_RX_FILTER_XR_POLL_LSB) & MAC_PCU_RX_FILTER_XR_POLL_MASK) -#define MAC_PCU_RX_FILTER_PROMISCUOUS_MSB 5 -#define MAC_PCU_RX_FILTER_PROMISCUOUS_LSB 5 -#define MAC_PCU_RX_FILTER_PROMISCUOUS_MASK 0x00000020 -#define MAC_PCU_RX_FILTER_PROMISCUOUS_GET(x) (((x) & MAC_PCU_RX_FILTER_PROMISCUOUS_MASK) >> MAC_PCU_RX_FILTER_PROMISCUOUS_LSB) -#define MAC_PCU_RX_FILTER_PROMISCUOUS_SET(x) (((x) << MAC_PCU_RX_FILTER_PROMISCUOUS_LSB) & MAC_PCU_RX_FILTER_PROMISCUOUS_MASK) -#define MAC_PCU_RX_FILTER_BEACON_MSB 4 -#define MAC_PCU_RX_FILTER_BEACON_LSB 4 -#define MAC_PCU_RX_FILTER_BEACON_MASK 0x00000010 -#define MAC_PCU_RX_FILTER_BEACON_GET(x) (((x) & MAC_PCU_RX_FILTER_BEACON_MASK) >> MAC_PCU_RX_FILTER_BEACON_LSB) -#define MAC_PCU_RX_FILTER_BEACON_SET(x) (((x) << MAC_PCU_RX_FILTER_BEACON_LSB) & MAC_PCU_RX_FILTER_BEACON_MASK) -#define MAC_PCU_RX_FILTER_CONTROL_MSB 3 -#define MAC_PCU_RX_FILTER_CONTROL_LSB 3 -#define MAC_PCU_RX_FILTER_CONTROL_MASK 0x00000008 -#define MAC_PCU_RX_FILTER_CONTROL_GET(x) (((x) & MAC_PCU_RX_FILTER_CONTROL_MASK) >> MAC_PCU_RX_FILTER_CONTROL_LSB) -#define MAC_PCU_RX_FILTER_CONTROL_SET(x) (((x) << MAC_PCU_RX_FILTER_CONTROL_LSB) & MAC_PCU_RX_FILTER_CONTROL_MASK) -#define MAC_PCU_RX_FILTER_BROADCAST_MSB 2 -#define MAC_PCU_RX_FILTER_BROADCAST_LSB 2 -#define MAC_PCU_RX_FILTER_BROADCAST_MASK 0x00000004 -#define MAC_PCU_RX_FILTER_BROADCAST_GET(x) (((x) & MAC_PCU_RX_FILTER_BROADCAST_MASK) >> MAC_PCU_RX_FILTER_BROADCAST_LSB) -#define MAC_PCU_RX_FILTER_BROADCAST_SET(x) (((x) << MAC_PCU_RX_FILTER_BROADCAST_LSB) & MAC_PCU_RX_FILTER_BROADCAST_MASK) -#define MAC_PCU_RX_FILTER_MULTICAST_MSB 1 -#define MAC_PCU_RX_FILTER_MULTICAST_LSB 1 -#define MAC_PCU_RX_FILTER_MULTICAST_MASK 0x00000002 -#define MAC_PCU_RX_FILTER_MULTICAST_GET(x) (((x) & MAC_PCU_RX_FILTER_MULTICAST_MASK) >> MAC_PCU_RX_FILTER_MULTICAST_LSB) -#define MAC_PCU_RX_FILTER_MULTICAST_SET(x) (((x) << MAC_PCU_RX_FILTER_MULTICAST_LSB) & MAC_PCU_RX_FILTER_MULTICAST_MASK) -#define MAC_PCU_RX_FILTER_UNICAST_MSB 0 -#define MAC_PCU_RX_FILTER_UNICAST_LSB 0 -#define MAC_PCU_RX_FILTER_UNICAST_MASK 0x00000001 -#define MAC_PCU_RX_FILTER_UNICAST_GET(x) (((x) & MAC_PCU_RX_FILTER_UNICAST_MASK) >> MAC_PCU_RX_FILTER_UNICAST_LSB) -#define MAC_PCU_RX_FILTER_UNICAST_SET(x) (((x) << MAC_PCU_RX_FILTER_UNICAST_LSB) & MAC_PCU_RX_FILTER_UNICAST_MASK) - -#define MAC_PCU_MCAST_FILTER_L32_ADDRESS 0x00008028 -#define MAC_PCU_MCAST_FILTER_L32_OFFSET 0x00000028 -#define MAC_PCU_MCAST_FILTER_L32_VALUE_MSB 31 -#define MAC_PCU_MCAST_FILTER_L32_VALUE_LSB 0 -#define MAC_PCU_MCAST_FILTER_L32_VALUE_MASK 0xffffffff -#define MAC_PCU_MCAST_FILTER_L32_VALUE_GET(x) (((x) & MAC_PCU_MCAST_FILTER_L32_VALUE_MASK) >> MAC_PCU_MCAST_FILTER_L32_VALUE_LSB) -#define MAC_PCU_MCAST_FILTER_L32_VALUE_SET(x) (((x) << MAC_PCU_MCAST_FILTER_L32_VALUE_LSB) & MAC_PCU_MCAST_FILTER_L32_VALUE_MASK) - -#define MAC_PCU_MCAST_FILTER_U32_ADDRESS 0x0000802c -#define MAC_PCU_MCAST_FILTER_U32_OFFSET 0x0000002c -#define MAC_PCU_MCAST_FILTER_U32_VALUE_MSB 31 -#define MAC_PCU_MCAST_FILTER_U32_VALUE_LSB 0 -#define MAC_PCU_MCAST_FILTER_U32_VALUE_MASK 0xffffffff -#define MAC_PCU_MCAST_FILTER_U32_VALUE_GET(x) (((x) & MAC_PCU_MCAST_FILTER_U32_VALUE_MASK) >> MAC_PCU_MCAST_FILTER_U32_VALUE_LSB) -#define MAC_PCU_MCAST_FILTER_U32_VALUE_SET(x) (((x) << MAC_PCU_MCAST_FILTER_U32_VALUE_LSB) & MAC_PCU_MCAST_FILTER_U32_VALUE_MASK) - -#define MAC_PCU_DIAG_SW_ADDRESS 0x00008030 -#define MAC_PCU_DIAG_SW_OFFSET 0x00000030 -#define MAC_PCU_DIAG_SW_DEBUG_MODE_MSB 31 -#define MAC_PCU_DIAG_SW_DEBUG_MODE_LSB 30 -#define MAC_PCU_DIAG_SW_DEBUG_MODE_MASK 0xc0000000 -#define MAC_PCU_DIAG_SW_DEBUG_MODE_GET(x) (((x) & MAC_PCU_DIAG_SW_DEBUG_MODE_MASK) >> MAC_PCU_DIAG_SW_DEBUG_MODE_LSB) -#define MAC_PCU_DIAG_SW_DEBUG_MODE_SET(x) (((x) << MAC_PCU_DIAG_SW_DEBUG_MODE_LSB) & MAC_PCU_DIAG_SW_DEBUG_MODE_MASK) -#define MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_MSB 29 -#define MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_LSB 29 -#define MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_MASK 0x20000000 -#define MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_GET(x) (((x) & MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_MASK) >> MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_LSB) -#define MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_SET(x) (((x) << MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_LSB) & MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_MASK) -#define MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_MSB 28 -#define MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_LSB 28 -#define MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_MASK 0x10000000 -#define MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_GET(x) (((x) & MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_MASK) >> MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_LSB) -#define MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_SET(x) (((x) << MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_LSB) & MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_MASK) -#define MAC_PCU_DIAG_SW_OBS_SEL_2_MSB 27 -#define MAC_PCU_DIAG_SW_OBS_SEL_2_LSB 27 -#define MAC_PCU_DIAG_SW_OBS_SEL_2_MASK 0x08000000 -#define MAC_PCU_DIAG_SW_OBS_SEL_2_GET(x) (((x) & MAC_PCU_DIAG_SW_OBS_SEL_2_MASK) >> MAC_PCU_DIAG_SW_OBS_SEL_2_LSB) -#define MAC_PCU_DIAG_SW_OBS_SEL_2_SET(x) (((x) << MAC_PCU_DIAG_SW_OBS_SEL_2_LSB) & MAC_PCU_DIAG_SW_OBS_SEL_2_MASK) -#define MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_MSB 26 -#define MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_LSB 26 -#define MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_MASK 0x04000000 -#define MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_GET(x) (((x) & MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_MASK) >> MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_LSB) -#define MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_SET(x) (((x) << MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_LSB) & MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_MASK) -#define MAC_PCU_DIAG_SW_FORCE_RX_ABORT_MSB 25 -#define MAC_PCU_DIAG_SW_FORCE_RX_ABORT_LSB 25 -#define MAC_PCU_DIAG_SW_FORCE_RX_ABORT_MASK 0x02000000 -#define MAC_PCU_DIAG_SW_FORCE_RX_ABORT_GET(x) (((x) & MAC_PCU_DIAG_SW_FORCE_RX_ABORT_MASK) >> MAC_PCU_DIAG_SW_FORCE_RX_ABORT_LSB) -#define MAC_PCU_DIAG_SW_FORCE_RX_ABORT_SET(x) (((x) << MAC_PCU_DIAG_SW_FORCE_RX_ABORT_LSB) & MAC_PCU_DIAG_SW_FORCE_RX_ABORT_MASK) -#define MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_MSB 24 -#define MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_LSB 24 -#define MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_MASK 0x01000000 -#define MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_GET(x) (((x) & MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_MASK) >> MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_LSB) -#define MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_SET(x) (((x) << MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_LSB) & MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_MASK) -#define MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_MSB 23 -#define MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_LSB 23 -#define MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_MASK 0x00800000 -#define MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_GET(x) (((x) & MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_MASK) >> MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_LSB) -#define MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_SET(x) (((x) << MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_LSB) & MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_MASK) -#define MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_MSB 22 -#define MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_LSB 22 -#define MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_MASK 0x00400000 -#define MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_GET(x) (((x) & MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_MASK) >> MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_LSB) -#define MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_SET(x) (((x) << MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_LSB) & MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_MASK) -#define MAC_PCU_DIAG_SW_IGNORE_NAV_MSB 21 -#define MAC_PCU_DIAG_SW_IGNORE_NAV_LSB 21 -#define MAC_PCU_DIAG_SW_IGNORE_NAV_MASK 0x00200000 -#define MAC_PCU_DIAG_SW_IGNORE_NAV_GET(x) (((x) & MAC_PCU_DIAG_SW_IGNORE_NAV_MASK) >> MAC_PCU_DIAG_SW_IGNORE_NAV_LSB) -#define MAC_PCU_DIAG_SW_IGNORE_NAV_SET(x) (((x) << MAC_PCU_DIAG_SW_IGNORE_NAV_LSB) & MAC_PCU_DIAG_SW_IGNORE_NAV_MASK) -#define MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_MSB 20 -#define MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_LSB 20 -#define MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_MASK 0x00100000 -#define MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_GET(x) (((x) & MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_MASK) >> MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_LSB) -#define MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_SET(x) (((x) << MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_LSB) & MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_MASK) -#define MAC_PCU_DIAG_SW_OBS_SEL_1_0_MSB 19 -#define MAC_PCU_DIAG_SW_OBS_SEL_1_0_LSB 18 -#define MAC_PCU_DIAG_SW_OBS_SEL_1_0_MASK 0x000c0000 -#define MAC_PCU_DIAG_SW_OBS_SEL_1_0_GET(x) (((x) & MAC_PCU_DIAG_SW_OBS_SEL_1_0_MASK) >> MAC_PCU_DIAG_SW_OBS_SEL_1_0_LSB) -#define MAC_PCU_DIAG_SW_OBS_SEL_1_0_SET(x) (((x) << MAC_PCU_DIAG_SW_OBS_SEL_1_0_LSB) & MAC_PCU_DIAG_SW_OBS_SEL_1_0_MASK) -#define MAC_PCU_DIAG_SW_ACCEPT_NON_V0_MSB 17 -#define MAC_PCU_DIAG_SW_ACCEPT_NON_V0_LSB 17 -#define MAC_PCU_DIAG_SW_ACCEPT_NON_V0_MASK 0x00020000 -#define MAC_PCU_DIAG_SW_ACCEPT_NON_V0_GET(x) (((x) & MAC_PCU_DIAG_SW_ACCEPT_NON_V0_MASK) >> MAC_PCU_DIAG_SW_ACCEPT_NON_V0_LSB) -#define MAC_PCU_DIAG_SW_ACCEPT_NON_V0_SET(x) (((x) << MAC_PCU_DIAG_SW_ACCEPT_NON_V0_LSB) & MAC_PCU_DIAG_SW_ACCEPT_NON_V0_MASK) -#define MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_MSB 8 -#define MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_LSB 8 -#define MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_MASK 0x00000100 -#define MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_GET(x) (((x) & MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_MASK) >> MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_LSB) -#define MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_SET(x) (((x) << MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_LSB) & MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_MASK) -#define MAC_PCU_DIAG_SW_CORRUPT_FCS_MSB 7 -#define MAC_PCU_DIAG_SW_CORRUPT_FCS_LSB 7 -#define MAC_PCU_DIAG_SW_CORRUPT_FCS_MASK 0x00000080 -#define MAC_PCU_DIAG_SW_CORRUPT_FCS_GET(x) (((x) & MAC_PCU_DIAG_SW_CORRUPT_FCS_MASK) >> MAC_PCU_DIAG_SW_CORRUPT_FCS_LSB) -#define MAC_PCU_DIAG_SW_CORRUPT_FCS_SET(x) (((x) << MAC_PCU_DIAG_SW_CORRUPT_FCS_LSB) & MAC_PCU_DIAG_SW_CORRUPT_FCS_MASK) -#define MAC_PCU_DIAG_SW_LOOP_BACK_MSB 6 -#define MAC_PCU_DIAG_SW_LOOP_BACK_LSB 6 -#define MAC_PCU_DIAG_SW_LOOP_BACK_MASK 0x00000040 -#define MAC_PCU_DIAG_SW_LOOP_BACK_GET(x) (((x) & MAC_PCU_DIAG_SW_LOOP_BACK_MASK) >> MAC_PCU_DIAG_SW_LOOP_BACK_LSB) -#define MAC_PCU_DIAG_SW_LOOP_BACK_SET(x) (((x) << MAC_PCU_DIAG_SW_LOOP_BACK_LSB) & MAC_PCU_DIAG_SW_LOOP_BACK_MASK) -#define MAC_PCU_DIAG_SW_HALT_RX_MSB 5 -#define MAC_PCU_DIAG_SW_HALT_RX_LSB 5 -#define MAC_PCU_DIAG_SW_HALT_RX_MASK 0x00000020 -#define MAC_PCU_DIAG_SW_HALT_RX_GET(x) (((x) & MAC_PCU_DIAG_SW_HALT_RX_MASK) >> MAC_PCU_DIAG_SW_HALT_RX_LSB) -#define MAC_PCU_DIAG_SW_HALT_RX_SET(x) (((x) << MAC_PCU_DIAG_SW_HALT_RX_LSB) & MAC_PCU_DIAG_SW_HALT_RX_MASK) -#define MAC_PCU_DIAG_SW_NO_DECRYPT_MSB 4 -#define MAC_PCU_DIAG_SW_NO_DECRYPT_LSB 4 -#define MAC_PCU_DIAG_SW_NO_DECRYPT_MASK 0x00000010 -#define MAC_PCU_DIAG_SW_NO_DECRYPT_GET(x) (((x) & MAC_PCU_DIAG_SW_NO_DECRYPT_MASK) >> MAC_PCU_DIAG_SW_NO_DECRYPT_LSB) -#define MAC_PCU_DIAG_SW_NO_DECRYPT_SET(x) (((x) << MAC_PCU_DIAG_SW_NO_DECRYPT_LSB) & MAC_PCU_DIAG_SW_NO_DECRYPT_MASK) -#define MAC_PCU_DIAG_SW_NO_ENCRYPT_MSB 3 -#define MAC_PCU_DIAG_SW_NO_ENCRYPT_LSB 3 -#define MAC_PCU_DIAG_SW_NO_ENCRYPT_MASK 0x00000008 -#define MAC_PCU_DIAG_SW_NO_ENCRYPT_GET(x) (((x) & MAC_PCU_DIAG_SW_NO_ENCRYPT_MASK) >> MAC_PCU_DIAG_SW_NO_ENCRYPT_LSB) -#define MAC_PCU_DIAG_SW_NO_ENCRYPT_SET(x) (((x) << MAC_PCU_DIAG_SW_NO_ENCRYPT_LSB) & MAC_PCU_DIAG_SW_NO_ENCRYPT_MASK) -#define MAC_PCU_DIAG_SW_NO_CTS_MSB 2 -#define MAC_PCU_DIAG_SW_NO_CTS_LSB 2 -#define MAC_PCU_DIAG_SW_NO_CTS_MASK 0x00000004 -#define MAC_PCU_DIAG_SW_NO_CTS_GET(x) (((x) & MAC_PCU_DIAG_SW_NO_CTS_MASK) >> MAC_PCU_DIAG_SW_NO_CTS_LSB) -#define MAC_PCU_DIAG_SW_NO_CTS_SET(x) (((x) << MAC_PCU_DIAG_SW_NO_CTS_LSB) & MAC_PCU_DIAG_SW_NO_CTS_MASK) -#define MAC_PCU_DIAG_SW_NO_ACK_MSB 1 -#define MAC_PCU_DIAG_SW_NO_ACK_LSB 1 -#define MAC_PCU_DIAG_SW_NO_ACK_MASK 0x00000002 -#define MAC_PCU_DIAG_SW_NO_ACK_GET(x) (((x) & MAC_PCU_DIAG_SW_NO_ACK_MASK) >> MAC_PCU_DIAG_SW_NO_ACK_LSB) -#define MAC_PCU_DIAG_SW_NO_ACK_SET(x) (((x) << MAC_PCU_DIAG_SW_NO_ACK_LSB) & MAC_PCU_DIAG_SW_NO_ACK_MASK) -#define MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_MSB 0 -#define MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_LSB 0 -#define MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_MASK 0x00000001 -#define MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_GET(x) (((x) & MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_MASK) >> MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_LSB) -#define MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_SET(x) (((x) << MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_LSB) & MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_MASK) - -#define MAC_PCU_TST_ADDAC_ADDRESS 0x00008034 -#define MAC_PCU_TST_ADDAC_OFFSET 0x00000034 -#define MAC_PCU_TST_ADDAC_TEST_ARM_MSB 20 -#define MAC_PCU_TST_ADDAC_TEST_ARM_LSB 20 -#define MAC_PCU_TST_ADDAC_TEST_ARM_MASK 0x00100000 -#define MAC_PCU_TST_ADDAC_TEST_ARM_GET(x) (((x) & MAC_PCU_TST_ADDAC_TEST_ARM_MASK) >> MAC_PCU_TST_ADDAC_TEST_ARM_LSB) -#define MAC_PCU_TST_ADDAC_TEST_ARM_SET(x) (((x) << MAC_PCU_TST_ADDAC_TEST_ARM_LSB) & MAC_PCU_TST_ADDAC_TEST_ARM_MASK) -#define MAC_PCU_TST_ADDAC_TEST_CAPTURE_MSB 19 -#define MAC_PCU_TST_ADDAC_TEST_CAPTURE_LSB 19 -#define MAC_PCU_TST_ADDAC_TEST_CAPTURE_MASK 0x00080000 -#define MAC_PCU_TST_ADDAC_TEST_CAPTURE_GET(x) (((x) & MAC_PCU_TST_ADDAC_TEST_CAPTURE_MASK) >> MAC_PCU_TST_ADDAC_TEST_CAPTURE_LSB) -#define MAC_PCU_TST_ADDAC_TEST_CAPTURE_SET(x) (((x) << MAC_PCU_TST_ADDAC_TEST_CAPTURE_LSB) & MAC_PCU_TST_ADDAC_TEST_CAPTURE_MASK) -#define MAC_PCU_TST_ADDAC_CONT_TEST_MSB 18 -#define MAC_PCU_TST_ADDAC_CONT_TEST_LSB 18 -#define MAC_PCU_TST_ADDAC_CONT_TEST_MASK 0x00040000 -#define MAC_PCU_TST_ADDAC_CONT_TEST_GET(x) (((x) & MAC_PCU_TST_ADDAC_CONT_TEST_MASK) >> MAC_PCU_TST_ADDAC_CONT_TEST_LSB) -#define MAC_PCU_TST_ADDAC_CONT_TEST_SET(x) (((x) << MAC_PCU_TST_ADDAC_CONT_TEST_LSB) & MAC_PCU_TST_ADDAC_CONT_TEST_MASK) -#define MAC_PCU_TST_ADDAC_TRIG_POLARITY_MSB 17 -#define MAC_PCU_TST_ADDAC_TRIG_POLARITY_LSB 17 -#define MAC_PCU_TST_ADDAC_TRIG_POLARITY_MASK 0x00020000 -#define MAC_PCU_TST_ADDAC_TRIG_POLARITY_GET(x) (((x) & MAC_PCU_TST_ADDAC_TRIG_POLARITY_MASK) >> MAC_PCU_TST_ADDAC_TRIG_POLARITY_LSB) -#define MAC_PCU_TST_ADDAC_TRIG_POLARITY_SET(x) (((x) << MAC_PCU_TST_ADDAC_TRIG_POLARITY_LSB) & MAC_PCU_TST_ADDAC_TRIG_POLARITY_MASK) -#define MAC_PCU_TST_ADDAC_TRIG_SEL_MSB 16 -#define MAC_PCU_TST_ADDAC_TRIG_SEL_LSB 16 -#define MAC_PCU_TST_ADDAC_TRIG_SEL_MASK 0x00010000 -#define MAC_PCU_TST_ADDAC_TRIG_SEL_GET(x) (((x) & MAC_PCU_TST_ADDAC_TRIG_SEL_MASK) >> MAC_PCU_TST_ADDAC_TRIG_SEL_LSB) -#define MAC_PCU_TST_ADDAC_TRIG_SEL_SET(x) (((x) << MAC_PCU_TST_ADDAC_TRIG_SEL_LSB) & MAC_PCU_TST_ADDAC_TRIG_SEL_MASK) -#define MAC_PCU_TST_ADDAC_UPPER_8B_MSB 14 -#define MAC_PCU_TST_ADDAC_UPPER_8B_LSB 14 -#define MAC_PCU_TST_ADDAC_UPPER_8B_MASK 0x00004000 -#define MAC_PCU_TST_ADDAC_UPPER_8B_GET(x) (((x) & MAC_PCU_TST_ADDAC_UPPER_8B_MASK) >> MAC_PCU_TST_ADDAC_UPPER_8B_LSB) -#define MAC_PCU_TST_ADDAC_UPPER_8B_SET(x) (((x) << MAC_PCU_TST_ADDAC_UPPER_8B_LSB) & MAC_PCU_TST_ADDAC_UPPER_8B_MASK) -#define MAC_PCU_TST_ADDAC_LOOP_LEN_MSB 13 -#define MAC_PCU_TST_ADDAC_LOOP_LEN_LSB 3 -#define MAC_PCU_TST_ADDAC_LOOP_LEN_MASK 0x00003ff8 -#define MAC_PCU_TST_ADDAC_LOOP_LEN_GET(x) (((x) & MAC_PCU_TST_ADDAC_LOOP_LEN_MASK) >> MAC_PCU_TST_ADDAC_LOOP_LEN_LSB) -#define MAC_PCU_TST_ADDAC_LOOP_LEN_SET(x) (((x) << MAC_PCU_TST_ADDAC_LOOP_LEN_LSB) & MAC_PCU_TST_ADDAC_LOOP_LEN_MASK) -#define MAC_PCU_TST_ADDAC_LOOP_MSB 2 -#define MAC_PCU_TST_ADDAC_LOOP_LSB 2 -#define MAC_PCU_TST_ADDAC_LOOP_MASK 0x00000004 -#define MAC_PCU_TST_ADDAC_LOOP_GET(x) (((x) & MAC_PCU_TST_ADDAC_LOOP_MASK) >> MAC_PCU_TST_ADDAC_LOOP_LSB) -#define MAC_PCU_TST_ADDAC_LOOP_SET(x) (((x) << MAC_PCU_TST_ADDAC_LOOP_LSB) & MAC_PCU_TST_ADDAC_LOOP_MASK) -#define MAC_PCU_TST_ADDAC_TESTMODE_MSB 1 -#define MAC_PCU_TST_ADDAC_TESTMODE_LSB 1 -#define MAC_PCU_TST_ADDAC_TESTMODE_MASK 0x00000002 -#define MAC_PCU_TST_ADDAC_TESTMODE_GET(x) (((x) & MAC_PCU_TST_ADDAC_TESTMODE_MASK) >> MAC_PCU_TST_ADDAC_TESTMODE_LSB) -#define MAC_PCU_TST_ADDAC_TESTMODE_SET(x) (((x) << MAC_PCU_TST_ADDAC_TESTMODE_LSB) & MAC_PCU_TST_ADDAC_TESTMODE_MASK) -#define MAC_PCU_TST_ADDAC_CONT_TX_MSB 0 -#define MAC_PCU_TST_ADDAC_CONT_TX_LSB 0 -#define MAC_PCU_TST_ADDAC_CONT_TX_MASK 0x00000001 -#define MAC_PCU_TST_ADDAC_CONT_TX_GET(x) (((x) & MAC_PCU_TST_ADDAC_CONT_TX_MASK) >> MAC_PCU_TST_ADDAC_CONT_TX_LSB) -#define MAC_PCU_TST_ADDAC_CONT_TX_SET(x) (((x) << MAC_PCU_TST_ADDAC_CONT_TX_LSB) & MAC_PCU_TST_ADDAC_CONT_TX_MASK) - -#define MAC_PCU_DEF_ANTENNA_ADDRESS 0x00008038 -#define MAC_PCU_DEF_ANTENNA_OFFSET 0x00000038 -#define MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_MSB 28 -#define MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_LSB 28 -#define MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_MASK 0x10000000 -#define MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_GET(x) (((x) & MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_MASK) >> MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_LSB) -#define MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_SET(x) (((x) << MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_LSB) & MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_MASK) -#define MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_MSB 24 -#define MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_LSB 24 -#define MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_MASK 0x01000000 -#define MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_GET(x) (((x) & MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_MASK) >> MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_LSB) -#define MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_SET(x) (((x) << MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_LSB) & MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_MASK) -#define MAC_PCU_DEF_ANTENNA_VALUE_MSB 23 -#define MAC_PCU_DEF_ANTENNA_VALUE_LSB 0 -#define MAC_PCU_DEF_ANTENNA_VALUE_MASK 0x00ffffff -#define MAC_PCU_DEF_ANTENNA_VALUE_GET(x) (((x) & MAC_PCU_DEF_ANTENNA_VALUE_MASK) >> MAC_PCU_DEF_ANTENNA_VALUE_LSB) -#define MAC_PCU_DEF_ANTENNA_VALUE_SET(x) (((x) << MAC_PCU_DEF_ANTENNA_VALUE_LSB) & MAC_PCU_DEF_ANTENNA_VALUE_MASK) - -#define MAC_PCU_AES_MUTE_MASK_0_ADDRESS 0x0000803c -#define MAC_PCU_AES_MUTE_MASK_0_OFFSET 0x0000003c -#define MAC_PCU_AES_MUTE_MASK_0_QOS_MSB 31 -#define MAC_PCU_AES_MUTE_MASK_0_QOS_LSB 16 -#define MAC_PCU_AES_MUTE_MASK_0_QOS_MASK 0xffff0000 -#define MAC_PCU_AES_MUTE_MASK_0_QOS_GET(x) (((x) & MAC_PCU_AES_MUTE_MASK_0_QOS_MASK) >> MAC_PCU_AES_MUTE_MASK_0_QOS_LSB) -#define MAC_PCU_AES_MUTE_MASK_0_QOS_SET(x) (((x) << MAC_PCU_AES_MUTE_MASK_0_QOS_LSB) & MAC_PCU_AES_MUTE_MASK_0_QOS_MASK) -#define MAC_PCU_AES_MUTE_MASK_0_FC_MSB 15 -#define MAC_PCU_AES_MUTE_MASK_0_FC_LSB 0 -#define MAC_PCU_AES_MUTE_MASK_0_FC_MASK 0x0000ffff -#define MAC_PCU_AES_MUTE_MASK_0_FC_GET(x) (((x) & MAC_PCU_AES_MUTE_MASK_0_FC_MASK) >> MAC_PCU_AES_MUTE_MASK_0_FC_LSB) -#define MAC_PCU_AES_MUTE_MASK_0_FC_SET(x) (((x) << MAC_PCU_AES_MUTE_MASK_0_FC_LSB) & MAC_PCU_AES_MUTE_MASK_0_FC_MASK) - -#define MAC_PCU_AES_MUTE_MASK_1_ADDRESS 0x00008040 -#define MAC_PCU_AES_MUTE_MASK_1_OFFSET 0x00000040 -#define MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_MSB 31 -#define MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_LSB 16 -#define MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_MASK 0xffff0000 -#define MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_GET(x) (((x) & MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_MASK) >> MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_LSB) -#define MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_SET(x) (((x) << MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_LSB) & MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_MASK) -#define MAC_PCU_AES_MUTE_MASK_1_SEQ_MSB 15 -#define MAC_PCU_AES_MUTE_MASK_1_SEQ_LSB 0 -#define MAC_PCU_AES_MUTE_MASK_1_SEQ_MASK 0x0000ffff -#define MAC_PCU_AES_MUTE_MASK_1_SEQ_GET(x) (((x) & MAC_PCU_AES_MUTE_MASK_1_SEQ_MASK) >> MAC_PCU_AES_MUTE_MASK_1_SEQ_LSB) -#define MAC_PCU_AES_MUTE_MASK_1_SEQ_SET(x) (((x) << MAC_PCU_AES_MUTE_MASK_1_SEQ_LSB) & MAC_PCU_AES_MUTE_MASK_1_SEQ_MASK) - -#define MAC_PCU_GATED_CLKS_ADDRESS 0x00008044 -#define MAC_PCU_GATED_CLKS_OFFSET 0x00000044 -#define MAC_PCU_GATED_CLKS_GATED_REG_MSB 3 -#define MAC_PCU_GATED_CLKS_GATED_REG_LSB 3 -#define MAC_PCU_GATED_CLKS_GATED_REG_MASK 0x00000008 -#define MAC_PCU_GATED_CLKS_GATED_REG_GET(x) (((x) & MAC_PCU_GATED_CLKS_GATED_REG_MASK) >> MAC_PCU_GATED_CLKS_GATED_REG_LSB) -#define MAC_PCU_GATED_CLKS_GATED_REG_SET(x) (((x) << MAC_PCU_GATED_CLKS_GATED_REG_LSB) & MAC_PCU_GATED_CLKS_GATED_REG_MASK) -#define MAC_PCU_GATED_CLKS_GATED_RX_MSB 2 -#define MAC_PCU_GATED_CLKS_GATED_RX_LSB 2 -#define MAC_PCU_GATED_CLKS_GATED_RX_MASK 0x00000004 -#define MAC_PCU_GATED_CLKS_GATED_RX_GET(x) (((x) & MAC_PCU_GATED_CLKS_GATED_RX_MASK) >> MAC_PCU_GATED_CLKS_GATED_RX_LSB) -#define MAC_PCU_GATED_CLKS_GATED_RX_SET(x) (((x) << MAC_PCU_GATED_CLKS_GATED_RX_LSB) & MAC_PCU_GATED_CLKS_GATED_RX_MASK) -#define MAC_PCU_GATED_CLKS_GATED_TX_MSB 1 -#define MAC_PCU_GATED_CLKS_GATED_TX_LSB 1 -#define MAC_PCU_GATED_CLKS_GATED_TX_MASK 0x00000002 -#define MAC_PCU_GATED_CLKS_GATED_TX_GET(x) (((x) & MAC_PCU_GATED_CLKS_GATED_TX_MASK) >> MAC_PCU_GATED_CLKS_GATED_TX_LSB) -#define MAC_PCU_GATED_CLKS_GATED_TX_SET(x) (((x) << MAC_PCU_GATED_CLKS_GATED_TX_LSB) & MAC_PCU_GATED_CLKS_GATED_TX_MASK) - -#define MAC_PCU_OBS_BUS_2_ADDRESS 0x00008048 -#define MAC_PCU_OBS_BUS_2_OFFSET 0x00000048 -#define MAC_PCU_OBS_BUS_2_VALUE_MSB 17 -#define MAC_PCU_OBS_BUS_2_VALUE_LSB 0 -#define MAC_PCU_OBS_BUS_2_VALUE_MASK 0x0003ffff -#define MAC_PCU_OBS_BUS_2_VALUE_GET(x) (((x) & MAC_PCU_OBS_BUS_2_VALUE_MASK) >> MAC_PCU_OBS_BUS_2_VALUE_LSB) -#define MAC_PCU_OBS_BUS_2_VALUE_SET(x) (((x) << MAC_PCU_OBS_BUS_2_VALUE_LSB) & MAC_PCU_OBS_BUS_2_VALUE_MASK) - -#define MAC_PCU_OBS_BUS_1_ADDRESS 0x0000804c -#define MAC_PCU_OBS_BUS_1_OFFSET 0x0000004c -#define MAC_PCU_OBS_BUS_1_TX_STATE_MSB 30 -#define MAC_PCU_OBS_BUS_1_TX_STATE_LSB 25 -#define MAC_PCU_OBS_BUS_1_TX_STATE_MASK 0x7e000000 -#define MAC_PCU_OBS_BUS_1_TX_STATE_GET(x) (((x) & MAC_PCU_OBS_BUS_1_TX_STATE_MASK) >> MAC_PCU_OBS_BUS_1_TX_STATE_LSB) -#define MAC_PCU_OBS_BUS_1_TX_STATE_SET(x) (((x) << MAC_PCU_OBS_BUS_1_TX_STATE_LSB) & MAC_PCU_OBS_BUS_1_TX_STATE_MASK) -#define MAC_PCU_OBS_BUS_1_RX_STATE_MSB 24 -#define MAC_PCU_OBS_BUS_1_RX_STATE_LSB 20 -#define MAC_PCU_OBS_BUS_1_RX_STATE_MASK 0x01f00000 -#define MAC_PCU_OBS_BUS_1_RX_STATE_GET(x) (((x) & MAC_PCU_OBS_BUS_1_RX_STATE_MASK) >> MAC_PCU_OBS_BUS_1_RX_STATE_LSB) -#define MAC_PCU_OBS_BUS_1_RX_STATE_SET(x) (((x) << MAC_PCU_OBS_BUS_1_RX_STATE_LSB) & MAC_PCU_OBS_BUS_1_RX_STATE_MASK) -#define MAC_PCU_OBS_BUS_1_WEP_STATE_MSB 17 -#define MAC_PCU_OBS_BUS_1_WEP_STATE_LSB 12 -#define MAC_PCU_OBS_BUS_1_WEP_STATE_MASK 0x0003f000 -#define MAC_PCU_OBS_BUS_1_WEP_STATE_GET(x) (((x) & MAC_PCU_OBS_BUS_1_WEP_STATE_MASK) >> MAC_PCU_OBS_BUS_1_WEP_STATE_LSB) -#define MAC_PCU_OBS_BUS_1_WEP_STATE_SET(x) (((x) << MAC_PCU_OBS_BUS_1_WEP_STATE_LSB) & MAC_PCU_OBS_BUS_1_WEP_STATE_MASK) -#define MAC_PCU_OBS_BUS_1_RX_CLEAR_MSB 11 -#define MAC_PCU_OBS_BUS_1_RX_CLEAR_LSB 11 -#define MAC_PCU_OBS_BUS_1_RX_CLEAR_MASK 0x00000800 -#define MAC_PCU_OBS_BUS_1_RX_CLEAR_GET(x) (((x) & MAC_PCU_OBS_BUS_1_RX_CLEAR_MASK) >> MAC_PCU_OBS_BUS_1_RX_CLEAR_LSB) -#define MAC_PCU_OBS_BUS_1_RX_CLEAR_SET(x) (((x) << MAC_PCU_OBS_BUS_1_RX_CLEAR_LSB) & MAC_PCU_OBS_BUS_1_RX_CLEAR_MASK) -#define MAC_PCU_OBS_BUS_1_RX_FRAME_MSB 10 -#define MAC_PCU_OBS_BUS_1_RX_FRAME_LSB 10 -#define MAC_PCU_OBS_BUS_1_RX_FRAME_MASK 0x00000400 -#define MAC_PCU_OBS_BUS_1_RX_FRAME_GET(x) (((x) & MAC_PCU_OBS_BUS_1_RX_FRAME_MASK) >> MAC_PCU_OBS_BUS_1_RX_FRAME_LSB) -#define MAC_PCU_OBS_BUS_1_RX_FRAME_SET(x) (((x) << MAC_PCU_OBS_BUS_1_RX_FRAME_LSB) & MAC_PCU_OBS_BUS_1_RX_FRAME_MASK) -#define MAC_PCU_OBS_BUS_1_TX_FRAME_MSB 9 -#define MAC_PCU_OBS_BUS_1_TX_FRAME_LSB 9 -#define MAC_PCU_OBS_BUS_1_TX_FRAME_MASK 0x00000200 -#define MAC_PCU_OBS_BUS_1_TX_FRAME_GET(x) (((x) & MAC_PCU_OBS_BUS_1_TX_FRAME_MASK) >> MAC_PCU_OBS_BUS_1_TX_FRAME_LSB) -#define MAC_PCU_OBS_BUS_1_TX_FRAME_SET(x) (((x) << MAC_PCU_OBS_BUS_1_TX_FRAME_LSB) & MAC_PCU_OBS_BUS_1_TX_FRAME_MASK) -#define MAC_PCU_OBS_BUS_1_TX_HOLD_MSB 8 -#define MAC_PCU_OBS_BUS_1_TX_HOLD_LSB 8 -#define MAC_PCU_OBS_BUS_1_TX_HOLD_MASK 0x00000100 -#define MAC_PCU_OBS_BUS_1_TX_HOLD_GET(x) (((x) & MAC_PCU_OBS_BUS_1_TX_HOLD_MASK) >> MAC_PCU_OBS_BUS_1_TX_HOLD_LSB) -#define MAC_PCU_OBS_BUS_1_TX_HOLD_SET(x) (((x) << MAC_PCU_OBS_BUS_1_TX_HOLD_LSB) & MAC_PCU_OBS_BUS_1_TX_HOLD_MASK) -#define MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_MSB 7 -#define MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_LSB 7 -#define MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_MASK 0x00000080 -#define MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_GET(x) (((x) & MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_MASK) >> MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_LSB) -#define MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_SET(x) (((x) << MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_LSB) & MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_MASK) -#define MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_MSB 6 -#define MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_LSB 6 -#define MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_MASK 0x00000040 -#define MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_GET(x) (((x) & MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_MASK) >> MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_LSB) -#define MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_SET(x) (((x) << MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_LSB) & MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_MASK) -#define MAC_PCU_OBS_BUS_1_TX_HCF_MSB 5 -#define MAC_PCU_OBS_BUS_1_TX_HCF_LSB 5 -#define MAC_PCU_OBS_BUS_1_TX_HCF_MASK 0x00000020 -#define MAC_PCU_OBS_BUS_1_TX_HCF_GET(x) (((x) & MAC_PCU_OBS_BUS_1_TX_HCF_MASK) >> MAC_PCU_OBS_BUS_1_TX_HCF_LSB) -#define MAC_PCU_OBS_BUS_1_TX_HCF_SET(x) (((x) << MAC_PCU_OBS_BUS_1_TX_HCF_LSB) & MAC_PCU_OBS_BUS_1_TX_HCF_MASK) -#define MAC_PCU_OBS_BUS_1_FILTER_PASS_MSB 4 -#define MAC_PCU_OBS_BUS_1_FILTER_PASS_LSB 4 -#define MAC_PCU_OBS_BUS_1_FILTER_PASS_MASK 0x00000010 -#define MAC_PCU_OBS_BUS_1_FILTER_PASS_GET(x) (((x) & MAC_PCU_OBS_BUS_1_FILTER_PASS_MASK) >> MAC_PCU_OBS_BUS_1_FILTER_PASS_LSB) -#define MAC_PCU_OBS_BUS_1_FILTER_PASS_SET(x) (((x) << MAC_PCU_OBS_BUS_1_FILTER_PASS_LSB) & MAC_PCU_OBS_BUS_1_FILTER_PASS_MASK) -#define MAC_PCU_OBS_BUS_1_RX_MY_BEACON_MSB 3 -#define MAC_PCU_OBS_BUS_1_RX_MY_BEACON_LSB 3 -#define MAC_PCU_OBS_BUS_1_RX_MY_BEACON_MASK 0x00000008 -#define MAC_PCU_OBS_BUS_1_RX_MY_BEACON_GET(x) (((x) & MAC_PCU_OBS_BUS_1_RX_MY_BEACON_MASK) >> MAC_PCU_OBS_BUS_1_RX_MY_BEACON_LSB) -#define MAC_PCU_OBS_BUS_1_RX_MY_BEACON_SET(x) (((x) << MAC_PCU_OBS_BUS_1_RX_MY_BEACON_LSB) & MAC_PCU_OBS_BUS_1_RX_MY_BEACON_MASK) -#define MAC_PCU_OBS_BUS_1_RX_WEP_MSB 2 -#define MAC_PCU_OBS_BUS_1_RX_WEP_LSB 2 -#define MAC_PCU_OBS_BUS_1_RX_WEP_MASK 0x00000004 -#define MAC_PCU_OBS_BUS_1_RX_WEP_GET(x) (((x) & MAC_PCU_OBS_BUS_1_RX_WEP_MASK) >> MAC_PCU_OBS_BUS_1_RX_WEP_LSB) -#define MAC_PCU_OBS_BUS_1_RX_WEP_SET(x) (((x) << MAC_PCU_OBS_BUS_1_RX_WEP_LSB) & MAC_PCU_OBS_BUS_1_RX_WEP_MASK) -#define MAC_PCU_OBS_BUS_1_PCU_RX_END_MSB 1 -#define MAC_PCU_OBS_BUS_1_PCU_RX_END_LSB 1 -#define MAC_PCU_OBS_BUS_1_PCU_RX_END_MASK 0x00000002 -#define MAC_PCU_OBS_BUS_1_PCU_RX_END_GET(x) (((x) & MAC_PCU_OBS_BUS_1_PCU_RX_END_MASK) >> MAC_PCU_OBS_BUS_1_PCU_RX_END_LSB) -#define MAC_PCU_OBS_BUS_1_PCU_RX_END_SET(x) (((x) << MAC_PCU_OBS_BUS_1_PCU_RX_END_LSB) & MAC_PCU_OBS_BUS_1_PCU_RX_END_MASK) -#define MAC_PCU_OBS_BUS_1_PCU_DIRECTED_MSB 0 -#define MAC_PCU_OBS_BUS_1_PCU_DIRECTED_LSB 0 -#define MAC_PCU_OBS_BUS_1_PCU_DIRECTED_MASK 0x00000001 -#define MAC_PCU_OBS_BUS_1_PCU_DIRECTED_GET(x) (((x) & MAC_PCU_OBS_BUS_1_PCU_DIRECTED_MASK) >> MAC_PCU_OBS_BUS_1_PCU_DIRECTED_LSB) -#define MAC_PCU_OBS_BUS_1_PCU_DIRECTED_SET(x) (((x) << MAC_PCU_OBS_BUS_1_PCU_DIRECTED_LSB) & MAC_PCU_OBS_BUS_1_PCU_DIRECTED_MASK) - -#define MAC_PCU_DYM_MIMO_PWR_SAVE_ADDRESS 0x00008050 -#define MAC_PCU_DYM_MIMO_PWR_SAVE_OFFSET 0x00000050 -#define MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_MSB 10 -#define MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_LSB 8 -#define MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_MASK 0x00000700 -#define MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_GET(x) (((x) & MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_MASK) >> MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_LSB) -#define MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_SET(x) (((x) << MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_LSB) & MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_MASK) -#define MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_MSB 6 -#define MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_LSB 4 -#define MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_MASK 0x00000070 -#define MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_GET(x) (((x) & MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_MASK) >> MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_LSB) -#define MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_SET(x) (((x) << MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_LSB) & MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_MASK) -#define MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_MSB 2 -#define MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_LSB 2 -#define MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_MASK 0x00000004 -#define MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_GET(x) (((x) & MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_MASK) >> MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_LSB) -#define MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_SET(x) (((x) << MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_LSB) & MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_MASK) -#define MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_MSB 1 -#define MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_LSB 1 -#define MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_MASK 0x00000002 -#define MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_GET(x) (((x) & MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_MASK) >> MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_LSB) -#define MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_SET(x) (((x) << MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_LSB) & MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_MASK) -#define MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_MSB 0 -#define MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_LSB 0 -#define MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_MASK 0x00000001 -#define MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_GET(x) (((x) & MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_MASK) >> MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_LSB) -#define MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_SET(x) (((x) << MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_LSB) & MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_MASK) - -#define MAC_PCU_LAST_BEACON_TSF_ADDRESS 0x00008054 -#define MAC_PCU_LAST_BEACON_TSF_OFFSET 0x00000054 -#define MAC_PCU_LAST_BEACON_TSF_VALUE_MSB 31 -#define MAC_PCU_LAST_BEACON_TSF_VALUE_LSB 0 -#define MAC_PCU_LAST_BEACON_TSF_VALUE_MASK 0xffffffff -#define MAC_PCU_LAST_BEACON_TSF_VALUE_GET(x) (((x) & MAC_PCU_LAST_BEACON_TSF_VALUE_MASK) >> MAC_PCU_LAST_BEACON_TSF_VALUE_LSB) -#define MAC_PCU_LAST_BEACON_TSF_VALUE_SET(x) (((x) << MAC_PCU_LAST_BEACON_TSF_VALUE_LSB) & MAC_PCU_LAST_BEACON_TSF_VALUE_MASK) - -#define MAC_PCU_NAV_ADDRESS 0x00008058 -#define MAC_PCU_NAV_OFFSET 0x00000058 -#define MAC_PCU_NAV_VALUE_MSB 25 -#define MAC_PCU_NAV_VALUE_LSB 0 -#define MAC_PCU_NAV_VALUE_MASK 0x03ffffff -#define MAC_PCU_NAV_VALUE_GET(x) (((x) & MAC_PCU_NAV_VALUE_MASK) >> MAC_PCU_NAV_VALUE_LSB) -#define MAC_PCU_NAV_VALUE_SET(x) (((x) << MAC_PCU_NAV_VALUE_LSB) & MAC_PCU_NAV_VALUE_MASK) - -#define MAC_PCU_RTS_SUCCESS_CNT_ADDRESS 0x0000805c -#define MAC_PCU_RTS_SUCCESS_CNT_OFFSET 0x0000005c -#define MAC_PCU_RTS_SUCCESS_CNT_VALUE_MSB 15 -#define MAC_PCU_RTS_SUCCESS_CNT_VALUE_LSB 0 -#define MAC_PCU_RTS_SUCCESS_CNT_VALUE_MASK 0x0000ffff -#define MAC_PCU_RTS_SUCCESS_CNT_VALUE_GET(x) (((x) & MAC_PCU_RTS_SUCCESS_CNT_VALUE_MASK) >> MAC_PCU_RTS_SUCCESS_CNT_VALUE_LSB) -#define MAC_PCU_RTS_SUCCESS_CNT_VALUE_SET(x) (((x) << MAC_PCU_RTS_SUCCESS_CNT_VALUE_LSB) & MAC_PCU_RTS_SUCCESS_CNT_VALUE_MASK) - -#define MAC_PCU_RTS_FAIL_CNT_ADDRESS 0x00008060 -#define MAC_PCU_RTS_FAIL_CNT_OFFSET 0x00000060 -#define MAC_PCU_RTS_FAIL_CNT_VALUE_MSB 15 -#define MAC_PCU_RTS_FAIL_CNT_VALUE_LSB 0 -#define MAC_PCU_RTS_FAIL_CNT_VALUE_MASK 0x0000ffff -#define MAC_PCU_RTS_FAIL_CNT_VALUE_GET(x) (((x) & MAC_PCU_RTS_FAIL_CNT_VALUE_MASK) >> MAC_PCU_RTS_FAIL_CNT_VALUE_LSB) -#define MAC_PCU_RTS_FAIL_CNT_VALUE_SET(x) (((x) << MAC_PCU_RTS_FAIL_CNT_VALUE_LSB) & MAC_PCU_RTS_FAIL_CNT_VALUE_MASK) - -#define MAC_PCU_ACK_FAIL_CNT_ADDRESS 0x00008064 -#define MAC_PCU_ACK_FAIL_CNT_OFFSET 0x00000064 -#define MAC_PCU_ACK_FAIL_CNT_VALUE_MSB 15 -#define MAC_PCU_ACK_FAIL_CNT_VALUE_LSB 0 -#define MAC_PCU_ACK_FAIL_CNT_VALUE_MASK 0x0000ffff -#define MAC_PCU_ACK_FAIL_CNT_VALUE_GET(x) (((x) & MAC_PCU_ACK_FAIL_CNT_VALUE_MASK) >> MAC_PCU_ACK_FAIL_CNT_VALUE_LSB) -#define MAC_PCU_ACK_FAIL_CNT_VALUE_SET(x) (((x) << MAC_PCU_ACK_FAIL_CNT_VALUE_LSB) & MAC_PCU_ACK_FAIL_CNT_VALUE_MASK) - -#define MAC_PCU_FCS_FAIL_CNT_ADDRESS 0x00008068 -#define MAC_PCU_FCS_FAIL_CNT_OFFSET 0x00000068 -#define MAC_PCU_FCS_FAIL_CNT_VALUE_MSB 15 -#define MAC_PCU_FCS_FAIL_CNT_VALUE_LSB 0 -#define MAC_PCU_FCS_FAIL_CNT_VALUE_MASK 0x0000ffff -#define MAC_PCU_FCS_FAIL_CNT_VALUE_GET(x) (((x) & MAC_PCU_FCS_FAIL_CNT_VALUE_MASK) >> MAC_PCU_FCS_FAIL_CNT_VALUE_LSB) -#define MAC_PCU_FCS_FAIL_CNT_VALUE_SET(x) (((x) << MAC_PCU_FCS_FAIL_CNT_VALUE_LSB) & MAC_PCU_FCS_FAIL_CNT_VALUE_MASK) - -#define MAC_PCU_BEACON_CNT_ADDRESS 0x0000806c -#define MAC_PCU_BEACON_CNT_OFFSET 0x0000006c -#define MAC_PCU_BEACON_CNT_VALUE_MSB 15 -#define MAC_PCU_BEACON_CNT_VALUE_LSB 0 -#define MAC_PCU_BEACON_CNT_VALUE_MASK 0x0000ffff -#define MAC_PCU_BEACON_CNT_VALUE_GET(x) (((x) & MAC_PCU_BEACON_CNT_VALUE_MASK) >> MAC_PCU_BEACON_CNT_VALUE_LSB) -#define MAC_PCU_BEACON_CNT_VALUE_SET(x) (((x) << MAC_PCU_BEACON_CNT_VALUE_LSB) & MAC_PCU_BEACON_CNT_VALUE_MASK) - -#define MAC_PCU_XRMODE_ADDRESS 0x00008070 -#define MAC_PCU_XRMODE_OFFSET 0x00000070 -#define MAC_PCU_XRMODE_FRAME_HOLD_MSB 31 -#define MAC_PCU_XRMODE_FRAME_HOLD_LSB 20 -#define MAC_PCU_XRMODE_FRAME_HOLD_MASK 0xfff00000 -#define MAC_PCU_XRMODE_FRAME_HOLD_GET(x) (((x) & MAC_PCU_XRMODE_FRAME_HOLD_MASK) >> MAC_PCU_XRMODE_FRAME_HOLD_LSB) -#define MAC_PCU_XRMODE_FRAME_HOLD_SET(x) (((x) << MAC_PCU_XRMODE_FRAME_HOLD_LSB) & MAC_PCU_XRMODE_FRAME_HOLD_MASK) -#define MAC_PCU_XRMODE_WAIT_FOR_POLL_MSB 7 -#define MAC_PCU_XRMODE_WAIT_FOR_POLL_LSB 7 -#define MAC_PCU_XRMODE_WAIT_FOR_POLL_MASK 0x00000080 -#define MAC_PCU_XRMODE_WAIT_FOR_POLL_GET(x) (((x) & MAC_PCU_XRMODE_WAIT_FOR_POLL_MASK) >> MAC_PCU_XRMODE_WAIT_FOR_POLL_LSB) -#define MAC_PCU_XRMODE_WAIT_FOR_POLL_SET(x) (((x) << MAC_PCU_XRMODE_WAIT_FOR_POLL_LSB) & MAC_PCU_XRMODE_WAIT_FOR_POLL_MASK) -#define MAC_PCU_XRMODE_POLL_TYPE_MSB 5 -#define MAC_PCU_XRMODE_POLL_TYPE_LSB 0 -#define MAC_PCU_XRMODE_POLL_TYPE_MASK 0x0000003f -#define MAC_PCU_XRMODE_POLL_TYPE_GET(x) (((x) & MAC_PCU_XRMODE_POLL_TYPE_MASK) >> MAC_PCU_XRMODE_POLL_TYPE_LSB) -#define MAC_PCU_XRMODE_POLL_TYPE_SET(x) (((x) << MAC_PCU_XRMODE_POLL_TYPE_LSB) & MAC_PCU_XRMODE_POLL_TYPE_MASK) - -#define MAC_PCU_XRDEL_ADDRESS 0x00008074 -#define MAC_PCU_XRDEL_OFFSET 0x00000074 -#define MAC_PCU_XRDEL_CHIRP_DATA_DELAY_MSB 31 -#define MAC_PCU_XRDEL_CHIRP_DATA_DELAY_LSB 16 -#define MAC_PCU_XRDEL_CHIRP_DATA_DELAY_MASK 0xffff0000 -#define MAC_PCU_XRDEL_CHIRP_DATA_DELAY_GET(x) (((x) & MAC_PCU_XRDEL_CHIRP_DATA_DELAY_MASK) >> MAC_PCU_XRDEL_CHIRP_DATA_DELAY_LSB) -#define MAC_PCU_XRDEL_CHIRP_DATA_DELAY_SET(x) (((x) << MAC_PCU_XRDEL_CHIRP_DATA_DELAY_LSB) & MAC_PCU_XRDEL_CHIRP_DATA_DELAY_MASK) -#define MAC_PCU_XRDEL_SLOT_DELAY_MSB 15 -#define MAC_PCU_XRDEL_SLOT_DELAY_LSB 0 -#define MAC_PCU_XRDEL_SLOT_DELAY_MASK 0x0000ffff -#define MAC_PCU_XRDEL_SLOT_DELAY_GET(x) (((x) & MAC_PCU_XRDEL_SLOT_DELAY_MASK) >> MAC_PCU_XRDEL_SLOT_DELAY_LSB) -#define MAC_PCU_XRDEL_SLOT_DELAY_SET(x) (((x) << MAC_PCU_XRDEL_SLOT_DELAY_LSB) & MAC_PCU_XRDEL_SLOT_DELAY_MASK) - -#define MAC_PCU_XRTO_ADDRESS 0x00008078 -#define MAC_PCU_XRTO_OFFSET 0x00000078 -#define MAC_PCU_XRTO_POLL_TIMEOUT_MSB 31 -#define MAC_PCU_XRTO_POLL_TIMEOUT_LSB 16 -#define MAC_PCU_XRTO_POLL_TIMEOUT_MASK 0xffff0000 -#define MAC_PCU_XRTO_POLL_TIMEOUT_GET(x) (((x) & MAC_PCU_XRTO_POLL_TIMEOUT_MASK) >> MAC_PCU_XRTO_POLL_TIMEOUT_LSB) -#define MAC_PCU_XRTO_POLL_TIMEOUT_SET(x) (((x) << MAC_PCU_XRTO_POLL_TIMEOUT_LSB) & MAC_PCU_XRTO_POLL_TIMEOUT_MASK) -#define MAC_PCU_XRTO_CHIRP_TIMEOUT_MSB 15 -#define MAC_PCU_XRTO_CHIRP_TIMEOUT_LSB 0 -#define MAC_PCU_XRTO_CHIRP_TIMEOUT_MASK 0x0000ffff -#define MAC_PCU_XRTO_CHIRP_TIMEOUT_GET(x) (((x) & MAC_PCU_XRTO_CHIRP_TIMEOUT_MASK) >> MAC_PCU_XRTO_CHIRP_TIMEOUT_LSB) -#define MAC_PCU_XRTO_CHIRP_TIMEOUT_SET(x) (((x) << MAC_PCU_XRTO_CHIRP_TIMEOUT_LSB) & MAC_PCU_XRTO_CHIRP_TIMEOUT_MASK) - -#define MAC_PCU_XRCRP_ADDRESS 0x0000807c -#define MAC_PCU_XRCRP_OFFSET 0x0000007c -#define MAC_PCU_XRCRP_CHIRP_GAP_MSB 31 -#define MAC_PCU_XRCRP_CHIRP_GAP_LSB 16 -#define MAC_PCU_XRCRP_CHIRP_GAP_MASK 0xffff0000 -#define MAC_PCU_XRCRP_CHIRP_GAP_GET(x) (((x) & MAC_PCU_XRCRP_CHIRP_GAP_MASK) >> MAC_PCU_XRCRP_CHIRP_GAP_LSB) -#define MAC_PCU_XRCRP_CHIRP_GAP_SET(x) (((x) << MAC_PCU_XRCRP_CHIRP_GAP_LSB) & MAC_PCU_XRCRP_CHIRP_GAP_MASK) -#define MAC_PCU_XRCRP_SEND_CHIRP_MSB 0 -#define MAC_PCU_XRCRP_SEND_CHIRP_LSB 0 -#define MAC_PCU_XRCRP_SEND_CHIRP_MASK 0x00000001 -#define MAC_PCU_XRCRP_SEND_CHIRP_GET(x) (((x) & MAC_PCU_XRCRP_SEND_CHIRP_MASK) >> MAC_PCU_XRCRP_SEND_CHIRP_LSB) -#define MAC_PCU_XRCRP_SEND_CHIRP_SET(x) (((x) << MAC_PCU_XRCRP_SEND_CHIRP_LSB) & MAC_PCU_XRCRP_SEND_CHIRP_MASK) - -#define MAC_PCU_XRSTMP_ADDRESS 0x00008080 -#define MAC_PCU_XRSTMP_OFFSET 0x00000080 -#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_MSB 23 -#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_LSB 16 -#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_MASK 0x00ff0000 -#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_GET(x) (((x) & MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_MASK) >> MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_LSB) -#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_SET(x) (((x) << MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_LSB) & MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_MASK) -#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_MSB 15 -#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_LSB 8 -#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_MASK 0x0000ff00 -#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_GET(x) (((x) & MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_MASK) >> MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_LSB) -#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_SET(x) (((x) << MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_LSB) & MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_MASK) -#define MAC_PCU_XRSTMP_RX_ABORT_DATA_MSB 5 -#define MAC_PCU_XRSTMP_RX_ABORT_DATA_LSB 5 -#define MAC_PCU_XRSTMP_RX_ABORT_DATA_MASK 0x00000020 -#define MAC_PCU_XRSTMP_RX_ABORT_DATA_GET(x) (((x) & MAC_PCU_XRSTMP_RX_ABORT_DATA_MASK) >> MAC_PCU_XRSTMP_RX_ABORT_DATA_LSB) -#define MAC_PCU_XRSTMP_RX_ABORT_DATA_SET(x) (((x) << MAC_PCU_XRSTMP_RX_ABORT_DATA_LSB) & MAC_PCU_XRSTMP_RX_ABORT_DATA_MASK) -#define MAC_PCU_XRSTMP_TX_STOMP_DATA_MSB 4 -#define MAC_PCU_XRSTMP_TX_STOMP_DATA_LSB 4 -#define MAC_PCU_XRSTMP_TX_STOMP_DATA_MASK 0x00000010 -#define MAC_PCU_XRSTMP_TX_STOMP_DATA_GET(x) (((x) & MAC_PCU_XRSTMP_TX_STOMP_DATA_MASK) >> MAC_PCU_XRSTMP_TX_STOMP_DATA_LSB) -#define MAC_PCU_XRSTMP_TX_STOMP_DATA_SET(x) (((x) << MAC_PCU_XRSTMP_TX_STOMP_DATA_LSB) & MAC_PCU_XRSTMP_TX_STOMP_DATA_MASK) -#define MAC_PCU_XRSTMP_TX_STOMP_BSSID_MSB 3 -#define MAC_PCU_XRSTMP_TX_STOMP_BSSID_LSB 3 -#define MAC_PCU_XRSTMP_TX_STOMP_BSSID_MASK 0x00000008 -#define MAC_PCU_XRSTMP_TX_STOMP_BSSID_GET(x) (((x) & MAC_PCU_XRSTMP_TX_STOMP_BSSID_MASK) >> MAC_PCU_XRSTMP_TX_STOMP_BSSID_LSB) -#define MAC_PCU_XRSTMP_TX_STOMP_BSSID_SET(x) (((x) << MAC_PCU_XRSTMP_TX_STOMP_BSSID_LSB) & MAC_PCU_XRSTMP_TX_STOMP_BSSID_MASK) -#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_MSB 2 -#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_LSB 2 -#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_MASK 0x00000004 -#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_GET(x) (((x) & MAC_PCU_XRSTMP_TX_STOMP_RSSI_MASK) >> MAC_PCU_XRSTMP_TX_STOMP_RSSI_LSB) -#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_SET(x) (((x) << MAC_PCU_XRSTMP_TX_STOMP_RSSI_LSB) & MAC_PCU_XRSTMP_TX_STOMP_RSSI_MASK) -#define MAC_PCU_XRSTMP_RX_ABORT_BSSID_MSB 1 -#define MAC_PCU_XRSTMP_RX_ABORT_BSSID_LSB 1 -#define MAC_PCU_XRSTMP_RX_ABORT_BSSID_MASK 0x00000002 -#define MAC_PCU_XRSTMP_RX_ABORT_BSSID_GET(x) (((x) & MAC_PCU_XRSTMP_RX_ABORT_BSSID_MASK) >> MAC_PCU_XRSTMP_RX_ABORT_BSSID_LSB) -#define MAC_PCU_XRSTMP_RX_ABORT_BSSID_SET(x) (((x) << MAC_PCU_XRSTMP_RX_ABORT_BSSID_LSB) & MAC_PCU_XRSTMP_RX_ABORT_BSSID_MASK) -#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_MSB 0 -#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_LSB 0 -#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_MASK 0x00000001 -#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_GET(x) (((x) & MAC_PCU_XRSTMP_RX_ABORT_RSSI_MASK) >> MAC_PCU_XRSTMP_RX_ABORT_RSSI_LSB) -#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_SET(x) (((x) << MAC_PCU_XRSTMP_RX_ABORT_RSSI_LSB) & MAC_PCU_XRSTMP_RX_ABORT_RSSI_MASK) - -#define MAC_PCU_ADDR1_MASK_L32_ADDRESS 0x00008084 -#define MAC_PCU_ADDR1_MASK_L32_OFFSET 0x00000084 -#define MAC_PCU_ADDR1_MASK_L32_VALUE_MSB 31 -#define MAC_PCU_ADDR1_MASK_L32_VALUE_LSB 0 -#define MAC_PCU_ADDR1_MASK_L32_VALUE_MASK 0xffffffff -#define MAC_PCU_ADDR1_MASK_L32_VALUE_GET(x) (((x) & MAC_PCU_ADDR1_MASK_L32_VALUE_MASK) >> MAC_PCU_ADDR1_MASK_L32_VALUE_LSB) -#define MAC_PCU_ADDR1_MASK_L32_VALUE_SET(x) (((x) << MAC_PCU_ADDR1_MASK_L32_VALUE_LSB) & MAC_PCU_ADDR1_MASK_L32_VALUE_MASK) - -#define MAC_PCU_ADDR1_MASK_U16_ADDRESS 0x00008088 -#define MAC_PCU_ADDR1_MASK_U16_OFFSET 0x00000088 -#define MAC_PCU_ADDR1_MASK_U16_VALUE_MSB 15 -#define MAC_PCU_ADDR1_MASK_U16_VALUE_LSB 0 -#define MAC_PCU_ADDR1_MASK_U16_VALUE_MASK 0x0000ffff -#define MAC_PCU_ADDR1_MASK_U16_VALUE_GET(x) (((x) & MAC_PCU_ADDR1_MASK_U16_VALUE_MASK) >> MAC_PCU_ADDR1_MASK_U16_VALUE_LSB) -#define MAC_PCU_ADDR1_MASK_U16_VALUE_SET(x) (((x) << MAC_PCU_ADDR1_MASK_U16_VALUE_LSB) & MAC_PCU_ADDR1_MASK_U16_VALUE_MASK) - -#define MAC_PCU_TPC_ADDRESS 0x0000808c -#define MAC_PCU_TPC_OFFSET 0x0000008c -#define MAC_PCU_TPC_CHIRP_PWR_MSB 21 -#define MAC_PCU_TPC_CHIRP_PWR_LSB 16 -#define MAC_PCU_TPC_CHIRP_PWR_MASK 0x003f0000 -#define MAC_PCU_TPC_CHIRP_PWR_GET(x) (((x) & MAC_PCU_TPC_CHIRP_PWR_MASK) >> MAC_PCU_TPC_CHIRP_PWR_LSB) -#define MAC_PCU_TPC_CHIRP_PWR_SET(x) (((x) << MAC_PCU_TPC_CHIRP_PWR_LSB) & MAC_PCU_TPC_CHIRP_PWR_MASK) -#define MAC_PCU_TPC_CTS_PWR_MSB 13 -#define MAC_PCU_TPC_CTS_PWR_LSB 8 -#define MAC_PCU_TPC_CTS_PWR_MASK 0x00003f00 -#define MAC_PCU_TPC_CTS_PWR_GET(x) (((x) & MAC_PCU_TPC_CTS_PWR_MASK) >> MAC_PCU_TPC_CTS_PWR_LSB) -#define MAC_PCU_TPC_CTS_PWR_SET(x) (((x) << MAC_PCU_TPC_CTS_PWR_LSB) & MAC_PCU_TPC_CTS_PWR_MASK) -#define MAC_PCU_TPC_ACK_PWR_MSB 5 -#define MAC_PCU_TPC_ACK_PWR_LSB 0 -#define MAC_PCU_TPC_ACK_PWR_MASK 0x0000003f -#define MAC_PCU_TPC_ACK_PWR_GET(x) (((x) & MAC_PCU_TPC_ACK_PWR_MASK) >> MAC_PCU_TPC_ACK_PWR_LSB) -#define MAC_PCU_TPC_ACK_PWR_SET(x) (((x) << MAC_PCU_TPC_ACK_PWR_LSB) & MAC_PCU_TPC_ACK_PWR_MASK) - -#define MAC_PCU_TX_FRAME_CNT_ADDRESS 0x00008090 -#define MAC_PCU_TX_FRAME_CNT_OFFSET 0x00000090 -#define MAC_PCU_TX_FRAME_CNT_VALUE_MSB 31 -#define MAC_PCU_TX_FRAME_CNT_VALUE_LSB 0 -#define MAC_PCU_TX_FRAME_CNT_VALUE_MASK 0xffffffff -#define MAC_PCU_TX_FRAME_CNT_VALUE_GET(x) (((x) & MAC_PCU_TX_FRAME_CNT_VALUE_MASK) >> MAC_PCU_TX_FRAME_CNT_VALUE_LSB) -#define MAC_PCU_TX_FRAME_CNT_VALUE_SET(x) (((x) << MAC_PCU_TX_FRAME_CNT_VALUE_LSB) & MAC_PCU_TX_FRAME_CNT_VALUE_MASK) - -#define MAC_PCU_RX_FRAME_CNT_ADDRESS 0x00008094 -#define MAC_PCU_RX_FRAME_CNT_OFFSET 0x00000094 -#define MAC_PCU_RX_FRAME_CNT_VALUE_MSB 31 -#define MAC_PCU_RX_FRAME_CNT_VALUE_LSB 0 -#define MAC_PCU_RX_FRAME_CNT_VALUE_MASK 0xffffffff -#define MAC_PCU_RX_FRAME_CNT_VALUE_GET(x) (((x) & MAC_PCU_RX_FRAME_CNT_VALUE_MASK) >> MAC_PCU_RX_FRAME_CNT_VALUE_LSB) -#define MAC_PCU_RX_FRAME_CNT_VALUE_SET(x) (((x) << MAC_PCU_RX_FRAME_CNT_VALUE_LSB) & MAC_PCU_RX_FRAME_CNT_VALUE_MASK) - -#define MAC_PCU_RX_CLEAR_CNT_ADDRESS 0x00008098 -#define MAC_PCU_RX_CLEAR_CNT_OFFSET 0x00000098 -#define MAC_PCU_RX_CLEAR_CNT_VALUE_MSB 31 -#define MAC_PCU_RX_CLEAR_CNT_VALUE_LSB 0 -#define MAC_PCU_RX_CLEAR_CNT_VALUE_MASK 0xffffffff -#define MAC_PCU_RX_CLEAR_CNT_VALUE_GET(x) (((x) & MAC_PCU_RX_CLEAR_CNT_VALUE_MASK) >> MAC_PCU_RX_CLEAR_CNT_VALUE_LSB) -#define MAC_PCU_RX_CLEAR_CNT_VALUE_SET(x) (((x) << MAC_PCU_RX_CLEAR_CNT_VALUE_LSB) & MAC_PCU_RX_CLEAR_CNT_VALUE_MASK) - -#define MAC_PCU_CYCLE_CNT_ADDRESS 0x0000809c -#define MAC_PCU_CYCLE_CNT_OFFSET 0x0000009c -#define MAC_PCU_CYCLE_CNT_VALUE_MSB 31 -#define MAC_PCU_CYCLE_CNT_VALUE_LSB 0 -#define MAC_PCU_CYCLE_CNT_VALUE_MASK 0xffffffff -#define MAC_PCU_CYCLE_CNT_VALUE_GET(x) (((x) & MAC_PCU_CYCLE_CNT_VALUE_MASK) >> MAC_PCU_CYCLE_CNT_VALUE_LSB) -#define MAC_PCU_CYCLE_CNT_VALUE_SET(x) (((x) << MAC_PCU_CYCLE_CNT_VALUE_LSB) & MAC_PCU_CYCLE_CNT_VALUE_MASK) - -#define MAC_PCU_QUIET_TIME_1_ADDRESS 0x000080a0 -#define MAC_PCU_QUIET_TIME_1_OFFSET 0x000000a0 -#define MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_MSB 17 -#define MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_LSB 17 -#define MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_MASK 0x00020000 -#define MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_GET(x) (((x) & MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_MASK) >> MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_LSB) -#define MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_SET(x) (((x) << MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_LSB) & MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_MASK) - -#define MAC_PCU_QUIET_TIME_2_ADDRESS 0x000080a4 -#define MAC_PCU_QUIET_TIME_2_OFFSET 0x000000a4 -#define MAC_PCU_QUIET_TIME_2_DURATION_MSB 31 -#define MAC_PCU_QUIET_TIME_2_DURATION_LSB 16 -#define MAC_PCU_QUIET_TIME_2_DURATION_MASK 0xffff0000 -#define MAC_PCU_QUIET_TIME_2_DURATION_GET(x) (((x) & MAC_PCU_QUIET_TIME_2_DURATION_MASK) >> MAC_PCU_QUIET_TIME_2_DURATION_LSB) -#define MAC_PCU_QUIET_TIME_2_DURATION_SET(x) (((x) << MAC_PCU_QUIET_TIME_2_DURATION_LSB) & MAC_PCU_QUIET_TIME_2_DURATION_MASK) - -#define MAC_PCU_QOS_NO_ACK_ADDRESS 0x000080a8 -#define MAC_PCU_QOS_NO_ACK_OFFSET 0x000000a8 -#define MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_MSB 8 -#define MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_LSB 7 -#define MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_MASK 0x00000180 -#define MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_GET(x) (((x) & MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_MASK) >> MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_LSB) -#define MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_SET(x) (((x) << MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_LSB) & MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_MASK) -#define MAC_PCU_QOS_NO_ACK_BIT_OFFSET_MSB 6 -#define MAC_PCU_QOS_NO_ACK_BIT_OFFSET_LSB 4 -#define MAC_PCU_QOS_NO_ACK_BIT_OFFSET_MASK 0x00000070 -#define MAC_PCU_QOS_NO_ACK_BIT_OFFSET_GET(x) (((x) & MAC_PCU_QOS_NO_ACK_BIT_OFFSET_MASK) >> MAC_PCU_QOS_NO_ACK_BIT_OFFSET_LSB) -#define MAC_PCU_QOS_NO_ACK_BIT_OFFSET_SET(x) (((x) << MAC_PCU_QOS_NO_ACK_BIT_OFFSET_LSB) & MAC_PCU_QOS_NO_ACK_BIT_OFFSET_MASK) -#define MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_MSB 3 -#define MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_LSB 0 -#define MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_MASK 0x0000000f -#define MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_GET(x) (((x) & MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_MASK) >> MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_LSB) -#define MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_SET(x) (((x) << MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_LSB) & MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_MASK) - -#define MAC_PCU_PHY_ERROR_MASK_ADDRESS 0x000080ac -#define MAC_PCU_PHY_ERROR_MASK_OFFSET 0x000000ac -#define MAC_PCU_PHY_ERROR_MASK_VALUE_MSB 31 -#define MAC_PCU_PHY_ERROR_MASK_VALUE_LSB 0 -#define MAC_PCU_PHY_ERROR_MASK_VALUE_MASK 0xffffffff -#define MAC_PCU_PHY_ERROR_MASK_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERROR_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERROR_MASK_VALUE_LSB) -#define MAC_PCU_PHY_ERROR_MASK_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERROR_MASK_VALUE_LSB) & MAC_PCU_PHY_ERROR_MASK_VALUE_MASK) - -#define MAC_PCU_XRLAT_ADDRESS 0x000080b0 -#define MAC_PCU_XRLAT_OFFSET 0x000000b0 -#define MAC_PCU_XRLAT_VALUE_MSB 11 -#define MAC_PCU_XRLAT_VALUE_LSB 0 -#define MAC_PCU_XRLAT_VALUE_MASK 0x00000fff -#define MAC_PCU_XRLAT_VALUE_GET(x) (((x) & MAC_PCU_XRLAT_VALUE_MASK) >> MAC_PCU_XRLAT_VALUE_LSB) -#define MAC_PCU_XRLAT_VALUE_SET(x) (((x) << MAC_PCU_XRLAT_VALUE_LSB) & MAC_PCU_XRLAT_VALUE_MASK) - -#define MAC_PCU_RXBUF_ADDRESS 0x000080b4 -#define MAC_PCU_RXBUF_OFFSET 0x000000b4 -#define MAC_PCU_RXBUF_REG_RD_ENABLE_MSB 11 -#define MAC_PCU_RXBUF_REG_RD_ENABLE_LSB 11 -#define MAC_PCU_RXBUF_REG_RD_ENABLE_MASK 0x00000800 -#define MAC_PCU_RXBUF_REG_RD_ENABLE_GET(x) (((x) & MAC_PCU_RXBUF_REG_RD_ENABLE_MASK) >> MAC_PCU_RXBUF_REG_RD_ENABLE_LSB) -#define MAC_PCU_RXBUF_REG_RD_ENABLE_SET(x) (((x) << MAC_PCU_RXBUF_REG_RD_ENABLE_LSB) & MAC_PCU_RXBUF_REG_RD_ENABLE_MASK) -#define MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_MSB 10 -#define MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_LSB 0 -#define MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_MASK 0x000007ff -#define MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_GET(x) (((x) & MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_MASK) >> MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_LSB) -#define MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_SET(x) (((x) << MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_LSB) & MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_MASK) - -#define MAC_PCU_MIC_QOS_CONTROL_ADDRESS 0x000080b8 -#define MAC_PCU_MIC_QOS_CONTROL_OFFSET 0x000000b8 -#define MAC_PCU_MIC_QOS_CONTROL_ENABLE_MSB 16 -#define MAC_PCU_MIC_QOS_CONTROL_ENABLE_LSB 16 -#define MAC_PCU_MIC_QOS_CONTROL_ENABLE_MASK 0x00010000 -#define MAC_PCU_MIC_QOS_CONTROL_ENABLE_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_ENABLE_MASK) >> MAC_PCU_MIC_QOS_CONTROL_ENABLE_LSB) -#define MAC_PCU_MIC_QOS_CONTROL_ENABLE_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_ENABLE_LSB) & MAC_PCU_MIC_QOS_CONTROL_ENABLE_MASK) -#define MAC_PCU_MIC_QOS_CONTROL_VALUE_7_MSB 15 -#define MAC_PCU_MIC_QOS_CONTROL_VALUE_7_LSB 14 -#define MAC_PCU_MIC_QOS_CONTROL_VALUE_7_MASK 0x0000c000 -#define MAC_PCU_MIC_QOS_CONTROL_VALUE_7_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_7_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_7_LSB) -#define MAC_PCU_MIC_QOS_CONTROL_VALUE_7_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_7_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_7_MASK) -#define MAC_PCU_MIC_QOS_CONTROL_VALUE_6_MSB 13 -#define MAC_PCU_MIC_QOS_CONTROL_VALUE_6_LSB 12 -#define MAC_PCU_MIC_QOS_CONTROL_VALUE_6_MASK 0x00003000 -#define MAC_PCU_MIC_QOS_CONTROL_VALUE_6_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_6_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_6_LSB) -#define MAC_PCU_MIC_QOS_CONTROL_VALUE_6_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_6_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_6_MASK) -#define MAC_PCU_MIC_QOS_CONTROL_VALUE_5_MSB 11 -#define MAC_PCU_MIC_QOS_CONTROL_VALUE_5_LSB 10 -#define MAC_PCU_MIC_QOS_CONTROL_VALUE_5_MASK 0x00000c00 -#define MAC_PCU_MIC_QOS_CONTROL_VALUE_5_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_5_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_5_LSB) -#define MAC_PCU_MIC_QOS_CONTROL_VALUE_5_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_5_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_5_MASK) -#define MAC_PCU_MIC_QOS_CONTROL_VALUE_4_MSB 9 -#define MAC_PCU_MIC_QOS_CONTROL_VALUE_4_LSB 8 -#define MAC_PCU_MIC_QOS_CONTROL_VALUE_4_MASK 0x00000300 -#define MAC_PCU_MIC_QOS_CONTROL_VALUE_4_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_4_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_4_LSB) -#define MAC_PCU_MIC_QOS_CONTROL_VALUE_4_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_4_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_4_MASK) -#define MAC_PCU_MIC_QOS_CONTROL_VALUE_3_MSB 7 -#define MAC_PCU_MIC_QOS_CONTROL_VALUE_3_LSB 6 -#define MAC_PCU_MIC_QOS_CONTROL_VALUE_3_MASK 0x000000c0 -#define MAC_PCU_MIC_QOS_CONTROL_VALUE_3_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_3_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_3_LSB) -#define MAC_PCU_MIC_QOS_CONTROL_VALUE_3_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_3_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_3_MASK) -#define MAC_PCU_MIC_QOS_CONTROL_VALUE_2_MSB 5 -#define MAC_PCU_MIC_QOS_CONTROL_VALUE_2_LSB 4 -#define MAC_PCU_MIC_QOS_CONTROL_VALUE_2_MASK 0x00000030 -#define MAC_PCU_MIC_QOS_CONTROL_VALUE_2_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_2_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_2_LSB) -#define MAC_PCU_MIC_QOS_CONTROL_VALUE_2_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_2_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_2_MASK) -#define MAC_PCU_MIC_QOS_CONTROL_VALUE_1_MSB 3 -#define MAC_PCU_MIC_QOS_CONTROL_VALUE_1_LSB 2 -#define MAC_PCU_MIC_QOS_CONTROL_VALUE_1_MASK 0x0000000c -#define MAC_PCU_MIC_QOS_CONTROL_VALUE_1_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_1_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_1_LSB) -#define MAC_PCU_MIC_QOS_CONTROL_VALUE_1_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_1_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_1_MASK) -#define MAC_PCU_MIC_QOS_CONTROL_VALUE_0_MSB 1 -#define MAC_PCU_MIC_QOS_CONTROL_VALUE_0_LSB 0 -#define MAC_PCU_MIC_QOS_CONTROL_VALUE_0_MASK 0x00000003 -#define MAC_PCU_MIC_QOS_CONTROL_VALUE_0_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_0_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_0_LSB) -#define MAC_PCU_MIC_QOS_CONTROL_VALUE_0_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_0_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_0_MASK) - -#define MAC_PCU_MIC_QOS_SELECT_ADDRESS 0x000080bc -#define MAC_PCU_MIC_QOS_SELECT_OFFSET 0x000000bc -#define MAC_PCU_MIC_QOS_SELECT_VALUE_7_MSB 31 -#define MAC_PCU_MIC_QOS_SELECT_VALUE_7_LSB 28 -#define MAC_PCU_MIC_QOS_SELECT_VALUE_7_MASK 0xf0000000 -#define MAC_PCU_MIC_QOS_SELECT_VALUE_7_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_7_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_7_LSB) -#define MAC_PCU_MIC_QOS_SELECT_VALUE_7_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_7_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_7_MASK) -#define MAC_PCU_MIC_QOS_SELECT_VALUE_6_MSB 27 -#define MAC_PCU_MIC_QOS_SELECT_VALUE_6_LSB 24 -#define MAC_PCU_MIC_QOS_SELECT_VALUE_6_MASK 0x0f000000 -#define MAC_PCU_MIC_QOS_SELECT_VALUE_6_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_6_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_6_LSB) -#define MAC_PCU_MIC_QOS_SELECT_VALUE_6_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_6_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_6_MASK) -#define MAC_PCU_MIC_QOS_SELECT_VALUE_5_MSB 23 -#define MAC_PCU_MIC_QOS_SELECT_VALUE_5_LSB 20 -#define MAC_PCU_MIC_QOS_SELECT_VALUE_5_MASK 0x00f00000 -#define MAC_PCU_MIC_QOS_SELECT_VALUE_5_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_5_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_5_LSB) -#define MAC_PCU_MIC_QOS_SELECT_VALUE_5_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_5_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_5_MASK) -#define MAC_PCU_MIC_QOS_SELECT_VALUE_4_MSB 19 -#define MAC_PCU_MIC_QOS_SELECT_VALUE_4_LSB 16 -#define MAC_PCU_MIC_QOS_SELECT_VALUE_4_MASK 0x000f0000 -#define MAC_PCU_MIC_QOS_SELECT_VALUE_4_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_4_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_4_LSB) -#define MAC_PCU_MIC_QOS_SELECT_VALUE_4_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_4_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_4_MASK) -#define MAC_PCU_MIC_QOS_SELECT_VALUE_3_MSB 15 -#define MAC_PCU_MIC_QOS_SELECT_VALUE_3_LSB 12 -#define MAC_PCU_MIC_QOS_SELECT_VALUE_3_MASK 0x0000f000 -#define MAC_PCU_MIC_QOS_SELECT_VALUE_3_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_3_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_3_LSB) -#define MAC_PCU_MIC_QOS_SELECT_VALUE_3_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_3_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_3_MASK) -#define MAC_PCU_MIC_QOS_SELECT_VALUE_2_MSB 11 -#define MAC_PCU_MIC_QOS_SELECT_VALUE_2_LSB 8 -#define MAC_PCU_MIC_QOS_SELECT_VALUE_2_MASK 0x00000f00 -#define MAC_PCU_MIC_QOS_SELECT_VALUE_2_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_2_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_2_LSB) -#define MAC_PCU_MIC_QOS_SELECT_VALUE_2_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_2_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_2_MASK) -#define MAC_PCU_MIC_QOS_SELECT_VALUE_1_MSB 7 -#define MAC_PCU_MIC_QOS_SELECT_VALUE_1_LSB 4 -#define MAC_PCU_MIC_QOS_SELECT_VALUE_1_MASK 0x000000f0 -#define MAC_PCU_MIC_QOS_SELECT_VALUE_1_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_1_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_1_LSB) -#define MAC_PCU_MIC_QOS_SELECT_VALUE_1_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_1_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_1_MASK) -#define MAC_PCU_MIC_QOS_SELECT_VALUE_0_MSB 3 -#define MAC_PCU_MIC_QOS_SELECT_VALUE_0_LSB 0 -#define MAC_PCU_MIC_QOS_SELECT_VALUE_0_MASK 0x0000000f -#define MAC_PCU_MIC_QOS_SELECT_VALUE_0_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_0_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_0_LSB) -#define MAC_PCU_MIC_QOS_SELECT_VALUE_0_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_0_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_0_MASK) - -#define MAC_PCU_MISC_MODE_ADDRESS 0x000080c0 -#define MAC_PCU_MISC_MODE_OFFSET 0x000000c0 -#define MAC_PCU_MISC_MODE_DEBUG_MODE_MSB 31 -#define MAC_PCU_MISC_MODE_DEBUG_MODE_LSB 30 -#define MAC_PCU_MISC_MODE_DEBUG_MODE_MASK 0xc0000000 -#define MAC_PCU_MISC_MODE_DEBUG_MODE_GET(x) (((x) & MAC_PCU_MISC_MODE_DEBUG_MODE_MASK) >> MAC_PCU_MISC_MODE_DEBUG_MODE_LSB) -#define MAC_PCU_MISC_MODE_DEBUG_MODE_SET(x) (((x) << MAC_PCU_MISC_MODE_DEBUG_MODE_LSB) & MAC_PCU_MISC_MODE_DEBUG_MODE_MASK) -#define MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_MSB 29 -#define MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_LSB 29 -#define MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_MASK 0x20000000 -#define MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_GET(x) (((x) & MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_MASK) >> MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_LSB) -#define MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_SET(x) (((x) << MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_LSB) & MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_MASK) -#define MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_MSB 28 -#define MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_LSB 28 -#define MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_MASK 0x10000000 -#define MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_GET(x) (((x) & MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_MASK) >> MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_LSB) -#define MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_SET(x) (((x) << MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_LSB) & MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_MASK) -#define MAC_PCU_MISC_MODE_SEL_EVM_MSB 27 -#define MAC_PCU_MISC_MODE_SEL_EVM_LSB 27 -#define MAC_PCU_MISC_MODE_SEL_EVM_MASK 0x08000000 -#define MAC_PCU_MISC_MODE_SEL_EVM_GET(x) (((x) & MAC_PCU_MISC_MODE_SEL_EVM_MASK) >> MAC_PCU_MISC_MODE_SEL_EVM_LSB) -#define MAC_PCU_MISC_MODE_SEL_EVM_SET(x) (((x) << MAC_PCU_MISC_MODE_SEL_EVM_LSB) & MAC_PCU_MISC_MODE_SEL_EVM_MASK) -#define MAC_PCU_MISC_MODE_CLEAR_BA_VALID_MSB 26 -#define MAC_PCU_MISC_MODE_CLEAR_BA_VALID_LSB 26 -#define MAC_PCU_MISC_MODE_CLEAR_BA_VALID_MASK 0x04000000 -#define MAC_PCU_MISC_MODE_CLEAR_BA_VALID_GET(x) (((x) & MAC_PCU_MISC_MODE_CLEAR_BA_VALID_MASK) >> MAC_PCU_MISC_MODE_CLEAR_BA_VALID_LSB) -#define MAC_PCU_MISC_MODE_CLEAR_BA_VALID_SET(x) (((x) << MAC_PCU_MISC_MODE_CLEAR_BA_VALID_LSB) & MAC_PCU_MISC_MODE_CLEAR_BA_VALID_MASK) -#define MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_MSB 25 -#define MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_LSB 25 -#define MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_MASK 0x02000000 -#define MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_GET(x) (((x) & MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_MASK) >> MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_LSB) -#define MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_SET(x) (((x) << MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_LSB) & MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_MASK) -#define MAC_PCU_MISC_MODE_CLEAR_VMF_MSB 24 -#define MAC_PCU_MISC_MODE_CLEAR_VMF_LSB 24 -#define MAC_PCU_MISC_MODE_CLEAR_VMF_MASK 0x01000000 -#define MAC_PCU_MISC_MODE_CLEAR_VMF_GET(x) (((x) & MAC_PCU_MISC_MODE_CLEAR_VMF_MASK) >> MAC_PCU_MISC_MODE_CLEAR_VMF_LSB) -#define MAC_PCU_MISC_MODE_CLEAR_VMF_SET(x) (((x) << MAC_PCU_MISC_MODE_CLEAR_VMF_LSB) & MAC_PCU_MISC_MODE_CLEAR_VMF_MASK) -#define MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_MSB 23 -#define MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_LSB 23 -#define MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_MASK 0x00800000 -#define MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_MASK) >> MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_LSB) -#define MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_LSB) & MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_MASK) -#define MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_MSB 22 -#define MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_LSB 22 -#define MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_MASK 0x00400000 -#define MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_GET(x) (((x) & MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_MASK) >> MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_LSB) -#define MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_SET(x) (((x) << MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_LSB) & MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_MASK) -#define MAC_PCU_MISC_MODE_TBTT_PROTECT_MSB 21 -#define MAC_PCU_MISC_MODE_TBTT_PROTECT_LSB 21 -#define MAC_PCU_MISC_MODE_TBTT_PROTECT_MASK 0x00200000 -#define MAC_PCU_MISC_MODE_TBTT_PROTECT_GET(x) (((x) & MAC_PCU_MISC_MODE_TBTT_PROTECT_MASK) >> MAC_PCU_MISC_MODE_TBTT_PROTECT_LSB) -#define MAC_PCU_MISC_MODE_TBTT_PROTECT_SET(x) (((x) << MAC_PCU_MISC_MODE_TBTT_PROTECT_LSB) & MAC_PCU_MISC_MODE_TBTT_PROTECT_MASK) -#define MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_MSB 20 -#define MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_LSB 20 -#define MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_MASK 0x00100000 -#define MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_GET(x) (((x) & MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_MASK) >> MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_LSB) -#define MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_SET(x) (((x) << MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_LSB) & MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_MASK) -#define MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_MSB 18 -#define MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_LSB 18 -#define MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_MASK 0x00040000 -#define MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_GET(x) (((x) & MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_MASK) >> MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_LSB) -#define MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_SET(x) (((x) << MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_LSB) & MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_MASK) -#define MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_MSB 14 -#define MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_LSB 14 -#define MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_MASK 0x00004000 -#define MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_GET(x) (((x) & MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_MASK) >> MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_LSB) -#define MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_SET(x) (((x) << MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_LSB) & MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_MASK) -#define MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_MSB 12 -#define MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_LSB 12 -#define MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_MASK 0x00001000 -#define MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_MASK) >> MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_LSB) -#define MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_LSB) & MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_MASK) -#define MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_MSB 11 -#define MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_LSB 11 -#define MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_MASK 0x00000800 -#define MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_GET(x) (((x) & MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_MASK) >> MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_LSB) -#define MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_SET(x) (((x) << MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_LSB) & MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_MASK) -#define MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_MSB 10 -#define MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_LSB 10 -#define MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_MASK 0x00000400 -#define MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_GET(x) (((x) & MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_MASK) >> MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_LSB) -#define MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_SET(x) (((x) << MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_LSB) & MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_MASK) -#define MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_MSB 9 -#define MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_LSB 9 -#define MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_MASK 0x00000200 -#define MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_GET(x) (((x) & MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_MASK) >> MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_LSB) -#define MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_SET(x) (((x) << MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_LSB) & MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_MASK) -#define MAC_PCU_MISC_MODE_CCK_SIFS_MODE_MSB 4 -#define MAC_PCU_MISC_MODE_CCK_SIFS_MODE_LSB 4 -#define MAC_PCU_MISC_MODE_CCK_SIFS_MODE_MASK 0x00000010 -#define MAC_PCU_MISC_MODE_CCK_SIFS_MODE_GET(x) (((x) & MAC_PCU_MISC_MODE_CCK_SIFS_MODE_MASK) >> MAC_PCU_MISC_MODE_CCK_SIFS_MODE_LSB) -#define MAC_PCU_MISC_MODE_CCK_SIFS_MODE_SET(x) (((x) << MAC_PCU_MISC_MODE_CCK_SIFS_MODE_LSB) & MAC_PCU_MISC_MODE_CCK_SIFS_MODE_MASK) -#define MAC_PCU_MISC_MODE_TX_ADD_TSF_MSB 3 -#define MAC_PCU_MISC_MODE_TX_ADD_TSF_LSB 3 -#define MAC_PCU_MISC_MODE_TX_ADD_TSF_MASK 0x00000008 -#define MAC_PCU_MISC_MODE_TX_ADD_TSF_GET(x) (((x) & MAC_PCU_MISC_MODE_TX_ADD_TSF_MASK) >> MAC_PCU_MISC_MODE_TX_ADD_TSF_LSB) -#define MAC_PCU_MISC_MODE_TX_ADD_TSF_SET(x) (((x) << MAC_PCU_MISC_MODE_TX_ADD_TSF_LSB) & MAC_PCU_MISC_MODE_TX_ADD_TSF_MASK) -#define MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_MSB 2 -#define MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_LSB 2 -#define MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_MASK 0x00000004 -#define MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_MASK) >> MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_LSB) -#define MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_LSB) & MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_MASK) -#define MAC_PCU_MISC_MODE_DEBUG_MODE_AD_MSB 1 -#define MAC_PCU_MISC_MODE_DEBUG_MODE_AD_LSB 1 -#define MAC_PCU_MISC_MODE_DEBUG_MODE_AD_MASK 0x00000002 -#define MAC_PCU_MISC_MODE_DEBUG_MODE_AD_GET(x) (((x) & MAC_PCU_MISC_MODE_DEBUG_MODE_AD_MASK) >> MAC_PCU_MISC_MODE_DEBUG_MODE_AD_LSB) -#define MAC_PCU_MISC_MODE_DEBUG_MODE_AD_SET(x) (((x) << MAC_PCU_MISC_MODE_DEBUG_MODE_AD_LSB) & MAC_PCU_MISC_MODE_DEBUG_MODE_AD_MASK) -#define MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_MSB 0 -#define MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_LSB 0 -#define MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_MASK 0x00000001 -#define MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_GET(x) (((x) & MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_MASK) >> MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_LSB) -#define MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_SET(x) (((x) << MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_LSB) & MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_MASK) - -#define MAC_PCU_FILTER_OFDM_CNT_ADDRESS 0x000080c4 -#define MAC_PCU_FILTER_OFDM_CNT_OFFSET 0x000000c4 -#define MAC_PCU_FILTER_OFDM_CNT_VALUE_MSB 23 -#define MAC_PCU_FILTER_OFDM_CNT_VALUE_LSB 0 -#define MAC_PCU_FILTER_OFDM_CNT_VALUE_MASK 0x00ffffff -#define MAC_PCU_FILTER_OFDM_CNT_VALUE_GET(x) (((x) & MAC_PCU_FILTER_OFDM_CNT_VALUE_MASK) >> MAC_PCU_FILTER_OFDM_CNT_VALUE_LSB) -#define MAC_PCU_FILTER_OFDM_CNT_VALUE_SET(x) (((x) << MAC_PCU_FILTER_OFDM_CNT_VALUE_LSB) & MAC_PCU_FILTER_OFDM_CNT_VALUE_MASK) - -#define MAC_PCU_FILTER_CCK_CNT_ADDRESS 0x000080c8 -#define MAC_PCU_FILTER_CCK_CNT_OFFSET 0x000000c8 -#define MAC_PCU_FILTER_CCK_CNT_VALUE_MSB 23 -#define MAC_PCU_FILTER_CCK_CNT_VALUE_LSB 0 -#define MAC_PCU_FILTER_CCK_CNT_VALUE_MASK 0x00ffffff -#define MAC_PCU_FILTER_CCK_CNT_VALUE_GET(x) (((x) & MAC_PCU_FILTER_CCK_CNT_VALUE_MASK) >> MAC_PCU_FILTER_CCK_CNT_VALUE_LSB) -#define MAC_PCU_FILTER_CCK_CNT_VALUE_SET(x) (((x) << MAC_PCU_FILTER_CCK_CNT_VALUE_LSB) & MAC_PCU_FILTER_CCK_CNT_VALUE_MASK) - -#define MAC_PCU_PHY_ERR_CNT_1_ADDRESS 0x000080cc -#define MAC_PCU_PHY_ERR_CNT_1_OFFSET 0x000000cc -#define MAC_PCU_PHY_ERR_CNT_1_VALUE_MSB 23 -#define MAC_PCU_PHY_ERR_CNT_1_VALUE_LSB 0 -#define MAC_PCU_PHY_ERR_CNT_1_VALUE_MASK 0x00ffffff -#define MAC_PCU_PHY_ERR_CNT_1_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_1_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_1_VALUE_LSB) -#define MAC_PCU_PHY_ERR_CNT_1_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_1_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_1_VALUE_MASK) - -#define MAC_PCU_PHY_ERR_CNT_1_MASK_ADDRESS 0x000080d0 -#define MAC_PCU_PHY_ERR_CNT_1_MASK_OFFSET 0x000000d0 -#define MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_MSB 31 -#define MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_LSB 0 -#define MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_MASK 0xffffffff -#define MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_LSB) -#define MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_MASK) - -#define MAC_PCU_PHY_ERR_CNT_2_ADDRESS 0x000080d4 -#define MAC_PCU_PHY_ERR_CNT_2_OFFSET 0x000000d4 -#define MAC_PCU_PHY_ERR_CNT_2_VALUE_MSB 23 -#define MAC_PCU_PHY_ERR_CNT_2_VALUE_LSB 0 -#define MAC_PCU_PHY_ERR_CNT_2_VALUE_MASK 0x00ffffff -#define MAC_PCU_PHY_ERR_CNT_2_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_2_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_2_VALUE_LSB) -#define MAC_PCU_PHY_ERR_CNT_2_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_2_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_2_VALUE_MASK) - -#define MAC_PCU_PHY_ERR_CNT_2_MASK_ADDRESS 0x000080d8 -#define MAC_PCU_PHY_ERR_CNT_2_MASK_OFFSET 0x000000d8 -#define MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_MSB 31 -#define MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_LSB 0 -#define MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_MASK 0xffffffff -#define MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_LSB) -#define MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_MASK) - -#define MAC_PCU_TSF_THRESHOLD_ADDRESS 0x000080dc -#define MAC_PCU_TSF_THRESHOLD_OFFSET 0x000000dc -#define MAC_PCU_TSF_THRESHOLD_VALUE_MSB 15 -#define MAC_PCU_TSF_THRESHOLD_VALUE_LSB 0 -#define MAC_PCU_TSF_THRESHOLD_VALUE_MASK 0x0000ffff -#define MAC_PCU_TSF_THRESHOLD_VALUE_GET(x) (((x) & MAC_PCU_TSF_THRESHOLD_VALUE_MASK) >> MAC_PCU_TSF_THRESHOLD_VALUE_LSB) -#define MAC_PCU_TSF_THRESHOLD_VALUE_SET(x) (((x) << MAC_PCU_TSF_THRESHOLD_VALUE_LSB) & MAC_PCU_TSF_THRESHOLD_VALUE_MASK) - -#define MAC_PCU_PHY_ERROR_EIFS_MASK_ADDRESS 0x000080e0 -#define MAC_PCU_PHY_ERROR_EIFS_MASK_OFFSET 0x000000e0 -#define MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_MSB 31 -#define MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_LSB 0 -#define MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_MASK 0xffffffff -#define MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_LSB) -#define MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_LSB) & MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_MASK) - -#define MAC_PCU_PHY_ERR_CNT_3_ADDRESS 0x000080e4 -#define MAC_PCU_PHY_ERR_CNT_3_OFFSET 0x000000e4 -#define MAC_PCU_PHY_ERR_CNT_3_VALUE_MSB 23 -#define MAC_PCU_PHY_ERR_CNT_3_VALUE_LSB 0 -#define MAC_PCU_PHY_ERR_CNT_3_VALUE_MASK 0x00ffffff -#define MAC_PCU_PHY_ERR_CNT_3_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_3_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_3_VALUE_LSB) -#define MAC_PCU_PHY_ERR_CNT_3_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_3_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_3_VALUE_MASK) - -#define MAC_PCU_PHY_ERR_CNT_3_MASK_ADDRESS 0x000080e8 -#define MAC_PCU_PHY_ERR_CNT_3_MASK_OFFSET 0x000000e8 -#define MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_MSB 31 -#define MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_LSB 0 -#define MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_MASK 0xffffffff -#define MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_LSB) -#define MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_MASK) - -#define MAC_PCU_BLUETOOTH_MODE_ADDRESS 0x000080ec -#define MAC_PCU_BLUETOOTH_MODE_OFFSET 0x000000ec -#define MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_MSB 31 -#define MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_LSB 24 -#define MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_MASK 0xff000000 -#define MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_MASK) >> MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_LSB) -#define MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_LSB) & MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_MASK) -#define MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_MSB 23 -#define MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_LSB 18 -#define MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_MASK 0x00fc0000 -#define MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_MASK) >> MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_LSB) -#define MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_LSB) & MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_MASK) -#define MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_MSB 17 -#define MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_LSB 17 -#define MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_MASK 0x00020000 -#define MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_MASK) >> MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_LSB) -#define MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_LSB) & MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_MASK) -#define MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_MSB 16 -#define MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_LSB 13 -#define MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_MASK 0x0001e000 -#define MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_MASK) >> MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_LSB) -#define MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_LSB) & MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_MASK) -#define MAC_PCU_BLUETOOTH_MODE_QUIET_MSB 12 -#define MAC_PCU_BLUETOOTH_MODE_QUIET_LSB 12 -#define MAC_PCU_BLUETOOTH_MODE_QUIET_MASK 0x00001000 -#define MAC_PCU_BLUETOOTH_MODE_QUIET_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_QUIET_MASK) >> MAC_PCU_BLUETOOTH_MODE_QUIET_LSB) -#define MAC_PCU_BLUETOOTH_MODE_QUIET_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_QUIET_LSB) & MAC_PCU_BLUETOOTH_MODE_QUIET_MASK) -#define MAC_PCU_BLUETOOTH_MODE_MODE_MSB 11 -#define MAC_PCU_BLUETOOTH_MODE_MODE_LSB 10 -#define MAC_PCU_BLUETOOTH_MODE_MODE_MASK 0x00000c00 -#define MAC_PCU_BLUETOOTH_MODE_MODE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_MODE_MASK) >> MAC_PCU_BLUETOOTH_MODE_MODE_LSB) -#define MAC_PCU_BLUETOOTH_MODE_MODE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_MODE_LSB) & MAC_PCU_BLUETOOTH_MODE_MODE_MASK) -#define MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_MSB 9 -#define MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_LSB 9 -#define MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_MASK 0x00000200 -#define MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_LSB) -#define MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_MASK) -#define MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_MSB 8 -#define MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_LSB 8 -#define MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_MASK 0x00000100 -#define MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_LSB) -#define MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_MASK) -#define MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_MSB 7 -#define MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_LSB 0 -#define MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_MASK 0x000000ff -#define MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_LSB) -#define MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_MASK) - -#define MAC_PCU_BLUETOOTH_WEIGHTS_ADDRESS 0x000080f0 -#define MAC_PCU_BLUETOOTH_WEIGHTS_OFFSET 0x000000f0 -#define MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_MSB 31 -#define MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_LSB 16 -#define MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_MASK 0xffff0000 -#define MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_GET(x) (((x) & MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_MASK) >> MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_LSB) -#define MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_SET(x) (((x) << MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_LSB) & MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_MASK) -#define MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_MSB 15 -#define MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_LSB 0 -#define MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_MASK 0x0000ffff -#define MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_GET(x) (((x) & MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_MASK) >> MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_LSB) -#define MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_SET(x) (((x) << MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_LSB) & MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_MASK) - -#define MAC_PCU_BLUETOOTH_MODE2_ADDRESS 0x000080f4 -#define MAC_PCU_BLUETOOTH_MODE2_OFFSET 0x000000f4 -#define MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_MSB 31 -#define MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_LSB 31 -#define MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_MASK 0x80000000 -#define MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_MASK) >> MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_LSB) -#define MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_LSB) & MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_MASK) -#define MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_MSB 30 -#define MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_LSB 30 -#define MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_MASK 0x40000000 -#define MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_MASK) >> MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_LSB) -#define MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_LSB) & MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_MASK) -#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_MSB 29 -#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_LSB 28 -#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_MASK 0x30000000 -#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_MASK) >> MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_LSB) -#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_LSB) & MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_MASK) -#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_MSB 27 -#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_LSB 26 -#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_MASK 0x0c000000 -#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_MASK) >> MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_LSB) -#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_LSB) & MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_MASK) -#define MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_MSB 25 -#define MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_LSB 25 -#define MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_MASK 0x02000000 -#define MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_LSB) -#define MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_MASK) -#define MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_MSB 24 -#define MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_LSB 24 -#define MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_MASK 0x01000000 -#define MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_MASK) >> MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_LSB) -#define MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_LSB) & MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_MASK) -#define MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_MSB 23 -#define MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_LSB 22 -#define MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_MASK 0x00c00000 -#define MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_MASK) >> MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_LSB) -#define MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_LSB) & MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_MASK) -#define MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_MSB 21 -#define MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_LSB 21 -#define MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_MASK 0x00200000 -#define MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_MASK) >> MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_LSB) -#define MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_LSB) & MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_MASK) -#define MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_MSB 20 -#define MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_LSB 20 -#define MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_MASK 0x00100000 -#define MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_MASK) >> MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_LSB) -#define MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_LSB) & MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_MASK) -#define MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_MSB 19 -#define MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_LSB 19 -#define MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_MASK 0x00080000 -#define MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_MASK) >> MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_LSB) -#define MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_LSB) & MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_MASK) -#define MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_MSB 17 -#define MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_LSB 17 -#define MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_MASK 0x00020000 -#define MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_MASK) >> MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_LSB) -#define MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_LSB) & MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_MASK) -#define MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_MSB 16 -#define MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_LSB 16 -#define MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_MASK 0x00010000 -#define MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_MASK) >> MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_LSB) -#define MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_LSB) & MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_MASK) -#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_MSB 15 -#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_LSB 8 -#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_MASK 0x0000ff00 -#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_MASK) >> MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_LSB) -#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_LSB) & MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_MASK) -#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_MSB 7 -#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_LSB 0 -#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_MASK 0x000000ff -#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_MASK) >> MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_LSB) -#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_LSB) & MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_MASK) - -#define MAC_PCU_TXSIFS_ADDRESS 0x000080f8 -#define MAC_PCU_TXSIFS_OFFSET 0x000000f8 -#define MAC_PCU_TXSIFS_ACK_SHIFT_MSB 14 -#define MAC_PCU_TXSIFS_ACK_SHIFT_LSB 12 -#define MAC_PCU_TXSIFS_ACK_SHIFT_MASK 0x00007000 -#define MAC_PCU_TXSIFS_ACK_SHIFT_GET(x) (((x) & MAC_PCU_TXSIFS_ACK_SHIFT_MASK) >> MAC_PCU_TXSIFS_ACK_SHIFT_LSB) -#define MAC_PCU_TXSIFS_ACK_SHIFT_SET(x) (((x) << MAC_PCU_TXSIFS_ACK_SHIFT_LSB) & MAC_PCU_TXSIFS_ACK_SHIFT_MASK) -#define MAC_PCU_TXSIFS_TX_LATENCY_MSB 11 -#define MAC_PCU_TXSIFS_TX_LATENCY_LSB 8 -#define MAC_PCU_TXSIFS_TX_LATENCY_MASK 0x00000f00 -#define MAC_PCU_TXSIFS_TX_LATENCY_GET(x) (((x) & MAC_PCU_TXSIFS_TX_LATENCY_MASK) >> MAC_PCU_TXSIFS_TX_LATENCY_LSB) -#define MAC_PCU_TXSIFS_TX_LATENCY_SET(x) (((x) << MAC_PCU_TXSIFS_TX_LATENCY_LSB) & MAC_PCU_TXSIFS_TX_LATENCY_MASK) -#define MAC_PCU_TXSIFS_SIFS_TIME_MSB 7 -#define MAC_PCU_TXSIFS_SIFS_TIME_LSB 0 -#define MAC_PCU_TXSIFS_SIFS_TIME_MASK 0x000000ff -#define MAC_PCU_TXSIFS_SIFS_TIME_GET(x) (((x) & MAC_PCU_TXSIFS_SIFS_TIME_MASK) >> MAC_PCU_TXSIFS_SIFS_TIME_LSB) -#define MAC_PCU_TXSIFS_SIFS_TIME_SET(x) (((x) << MAC_PCU_TXSIFS_SIFS_TIME_LSB) & MAC_PCU_TXSIFS_SIFS_TIME_MASK) - -#define MAC_PCU_TXOP_X_ADDRESS 0x000080fc -#define MAC_PCU_TXOP_X_OFFSET 0x000000fc -#define MAC_PCU_TXOP_X_VALUE_MSB 7 -#define MAC_PCU_TXOP_X_VALUE_LSB 0 -#define MAC_PCU_TXOP_X_VALUE_MASK 0x000000ff -#define MAC_PCU_TXOP_X_VALUE_GET(x) (((x) & MAC_PCU_TXOP_X_VALUE_MASK) >> MAC_PCU_TXOP_X_VALUE_LSB) -#define MAC_PCU_TXOP_X_VALUE_SET(x) (((x) << MAC_PCU_TXOP_X_VALUE_LSB) & MAC_PCU_TXOP_X_VALUE_MASK) - -#define MAC_PCU_TXOP_0_3_ADDRESS 0x00008100 -#define MAC_PCU_TXOP_0_3_OFFSET 0x00000100 -#define MAC_PCU_TXOP_0_3_VALUE_3_MSB 31 -#define MAC_PCU_TXOP_0_3_VALUE_3_LSB 24 -#define MAC_PCU_TXOP_0_3_VALUE_3_MASK 0xff000000 -#define MAC_PCU_TXOP_0_3_VALUE_3_GET(x) (((x) & MAC_PCU_TXOP_0_3_VALUE_3_MASK) >> MAC_PCU_TXOP_0_3_VALUE_3_LSB) -#define MAC_PCU_TXOP_0_3_VALUE_3_SET(x) (((x) << MAC_PCU_TXOP_0_3_VALUE_3_LSB) & MAC_PCU_TXOP_0_3_VALUE_3_MASK) -#define MAC_PCU_TXOP_0_3_VALUE_2_MSB 23 -#define MAC_PCU_TXOP_0_3_VALUE_2_LSB 16 -#define MAC_PCU_TXOP_0_3_VALUE_2_MASK 0x00ff0000 -#define MAC_PCU_TXOP_0_3_VALUE_2_GET(x) (((x) & MAC_PCU_TXOP_0_3_VALUE_2_MASK) >> MAC_PCU_TXOP_0_3_VALUE_2_LSB) -#define MAC_PCU_TXOP_0_3_VALUE_2_SET(x) (((x) << MAC_PCU_TXOP_0_3_VALUE_2_LSB) & MAC_PCU_TXOP_0_3_VALUE_2_MASK) -#define MAC_PCU_TXOP_0_3_VALUE_1_MSB 15 -#define MAC_PCU_TXOP_0_3_VALUE_1_LSB 8 -#define MAC_PCU_TXOP_0_3_VALUE_1_MASK 0x0000ff00 -#define MAC_PCU_TXOP_0_3_VALUE_1_GET(x) (((x) & MAC_PCU_TXOP_0_3_VALUE_1_MASK) >> MAC_PCU_TXOP_0_3_VALUE_1_LSB) -#define MAC_PCU_TXOP_0_3_VALUE_1_SET(x) (((x) << MAC_PCU_TXOP_0_3_VALUE_1_LSB) & MAC_PCU_TXOP_0_3_VALUE_1_MASK) -#define MAC_PCU_TXOP_0_3_VALUE_0_MSB 7 -#define MAC_PCU_TXOP_0_3_VALUE_0_LSB 0 -#define MAC_PCU_TXOP_0_3_VALUE_0_MASK 0x000000ff -#define MAC_PCU_TXOP_0_3_VALUE_0_GET(x) (((x) & MAC_PCU_TXOP_0_3_VALUE_0_MASK) >> MAC_PCU_TXOP_0_3_VALUE_0_LSB) -#define MAC_PCU_TXOP_0_3_VALUE_0_SET(x) (((x) << MAC_PCU_TXOP_0_3_VALUE_0_LSB) & MAC_PCU_TXOP_0_3_VALUE_0_MASK) - -#define MAC_PCU_TXOP_4_7_ADDRESS 0x00008104 -#define MAC_PCU_TXOP_4_7_OFFSET 0x00000104 -#define MAC_PCU_TXOP_4_7_VALUE_7_MSB 31 -#define MAC_PCU_TXOP_4_7_VALUE_7_LSB 24 -#define MAC_PCU_TXOP_4_7_VALUE_7_MASK 0xff000000 -#define MAC_PCU_TXOP_4_7_VALUE_7_GET(x) (((x) & MAC_PCU_TXOP_4_7_VALUE_7_MASK) >> MAC_PCU_TXOP_4_7_VALUE_7_LSB) -#define MAC_PCU_TXOP_4_7_VALUE_7_SET(x) (((x) << MAC_PCU_TXOP_4_7_VALUE_7_LSB) & MAC_PCU_TXOP_4_7_VALUE_7_MASK) -#define MAC_PCU_TXOP_4_7_VALUE_6_MSB 23 -#define MAC_PCU_TXOP_4_7_VALUE_6_LSB 16 -#define MAC_PCU_TXOP_4_7_VALUE_6_MASK 0x00ff0000 -#define MAC_PCU_TXOP_4_7_VALUE_6_GET(x) (((x) & MAC_PCU_TXOP_4_7_VALUE_6_MASK) >> MAC_PCU_TXOP_4_7_VALUE_6_LSB) -#define MAC_PCU_TXOP_4_7_VALUE_6_SET(x) (((x) << MAC_PCU_TXOP_4_7_VALUE_6_LSB) & MAC_PCU_TXOP_4_7_VALUE_6_MASK) -#define MAC_PCU_TXOP_4_7_VALUE_5_MSB 15 -#define MAC_PCU_TXOP_4_7_VALUE_5_LSB 8 -#define MAC_PCU_TXOP_4_7_VALUE_5_MASK 0x0000ff00 -#define MAC_PCU_TXOP_4_7_VALUE_5_GET(x) (((x) & MAC_PCU_TXOP_4_7_VALUE_5_MASK) >> MAC_PCU_TXOP_4_7_VALUE_5_LSB) -#define MAC_PCU_TXOP_4_7_VALUE_5_SET(x) (((x) << MAC_PCU_TXOP_4_7_VALUE_5_LSB) & MAC_PCU_TXOP_4_7_VALUE_5_MASK) -#define MAC_PCU_TXOP_4_7_VALUE_4_MSB 7 -#define MAC_PCU_TXOP_4_7_VALUE_4_LSB 0 -#define MAC_PCU_TXOP_4_7_VALUE_4_MASK 0x000000ff -#define MAC_PCU_TXOP_4_7_VALUE_4_GET(x) (((x) & MAC_PCU_TXOP_4_7_VALUE_4_MASK) >> MAC_PCU_TXOP_4_7_VALUE_4_LSB) -#define MAC_PCU_TXOP_4_7_VALUE_4_SET(x) (((x) << MAC_PCU_TXOP_4_7_VALUE_4_LSB) & MAC_PCU_TXOP_4_7_VALUE_4_MASK) - -#define MAC_PCU_TXOP_8_11_ADDRESS 0x00008108 -#define MAC_PCU_TXOP_8_11_OFFSET 0x00000108 -#define MAC_PCU_TXOP_8_11_VALUE_11_MSB 31 -#define MAC_PCU_TXOP_8_11_VALUE_11_LSB 24 -#define MAC_PCU_TXOP_8_11_VALUE_11_MASK 0xff000000 -#define MAC_PCU_TXOP_8_11_VALUE_11_GET(x) (((x) & MAC_PCU_TXOP_8_11_VALUE_11_MASK) >> MAC_PCU_TXOP_8_11_VALUE_11_LSB) -#define MAC_PCU_TXOP_8_11_VALUE_11_SET(x) (((x) << MAC_PCU_TXOP_8_11_VALUE_11_LSB) & MAC_PCU_TXOP_8_11_VALUE_11_MASK) -#define MAC_PCU_TXOP_8_11_VALUE_10_MSB 23 -#define MAC_PCU_TXOP_8_11_VALUE_10_LSB 16 -#define MAC_PCU_TXOP_8_11_VALUE_10_MASK 0x00ff0000 -#define MAC_PCU_TXOP_8_11_VALUE_10_GET(x) (((x) & MAC_PCU_TXOP_8_11_VALUE_10_MASK) >> MAC_PCU_TXOP_8_11_VALUE_10_LSB) -#define MAC_PCU_TXOP_8_11_VALUE_10_SET(x) (((x) << MAC_PCU_TXOP_8_11_VALUE_10_LSB) & MAC_PCU_TXOP_8_11_VALUE_10_MASK) -#define MAC_PCU_TXOP_8_11_VALUE_9_MSB 15 -#define MAC_PCU_TXOP_8_11_VALUE_9_LSB 8 -#define MAC_PCU_TXOP_8_11_VALUE_9_MASK 0x0000ff00 -#define MAC_PCU_TXOP_8_11_VALUE_9_GET(x) (((x) & MAC_PCU_TXOP_8_11_VALUE_9_MASK) >> MAC_PCU_TXOP_8_11_VALUE_9_LSB) -#define MAC_PCU_TXOP_8_11_VALUE_9_SET(x) (((x) << MAC_PCU_TXOP_8_11_VALUE_9_LSB) & MAC_PCU_TXOP_8_11_VALUE_9_MASK) -#define MAC_PCU_TXOP_8_11_VALUE_8_MSB 7 -#define MAC_PCU_TXOP_8_11_VALUE_8_LSB 0 -#define MAC_PCU_TXOP_8_11_VALUE_8_MASK 0x000000ff -#define MAC_PCU_TXOP_8_11_VALUE_8_GET(x) (((x) & MAC_PCU_TXOP_8_11_VALUE_8_MASK) >> MAC_PCU_TXOP_8_11_VALUE_8_LSB) -#define MAC_PCU_TXOP_8_11_VALUE_8_SET(x) (((x) << MAC_PCU_TXOP_8_11_VALUE_8_LSB) & MAC_PCU_TXOP_8_11_VALUE_8_MASK) - -#define MAC_PCU_TXOP_12_15_ADDRESS 0x0000810c -#define MAC_PCU_TXOP_12_15_OFFSET 0x0000010c -#define MAC_PCU_TXOP_12_15_VALUE_15_MSB 31 -#define MAC_PCU_TXOP_12_15_VALUE_15_LSB 24 -#define MAC_PCU_TXOP_12_15_VALUE_15_MASK 0xff000000 -#define MAC_PCU_TXOP_12_15_VALUE_15_GET(x) (((x) & MAC_PCU_TXOP_12_15_VALUE_15_MASK) >> MAC_PCU_TXOP_12_15_VALUE_15_LSB) -#define MAC_PCU_TXOP_12_15_VALUE_15_SET(x) (((x) << MAC_PCU_TXOP_12_15_VALUE_15_LSB) & MAC_PCU_TXOP_12_15_VALUE_15_MASK) -#define MAC_PCU_TXOP_12_15_VALUE_14_MSB 23 -#define MAC_PCU_TXOP_12_15_VALUE_14_LSB 16 -#define MAC_PCU_TXOP_12_15_VALUE_14_MASK 0x00ff0000 -#define MAC_PCU_TXOP_12_15_VALUE_14_GET(x) (((x) & MAC_PCU_TXOP_12_15_VALUE_14_MASK) >> MAC_PCU_TXOP_12_15_VALUE_14_LSB) -#define MAC_PCU_TXOP_12_15_VALUE_14_SET(x) (((x) << MAC_PCU_TXOP_12_15_VALUE_14_LSB) & MAC_PCU_TXOP_12_15_VALUE_14_MASK) -#define MAC_PCU_TXOP_12_15_VALUE_13_MSB 15 -#define MAC_PCU_TXOP_12_15_VALUE_13_LSB 8 -#define MAC_PCU_TXOP_12_15_VALUE_13_MASK 0x0000ff00 -#define MAC_PCU_TXOP_12_15_VALUE_13_GET(x) (((x) & MAC_PCU_TXOP_12_15_VALUE_13_MASK) >> MAC_PCU_TXOP_12_15_VALUE_13_LSB) -#define MAC_PCU_TXOP_12_15_VALUE_13_SET(x) (((x) << MAC_PCU_TXOP_12_15_VALUE_13_LSB) & MAC_PCU_TXOP_12_15_VALUE_13_MASK) -#define MAC_PCU_TXOP_12_15_VALUE_12_MSB 7 -#define MAC_PCU_TXOP_12_15_VALUE_12_LSB 0 -#define MAC_PCU_TXOP_12_15_VALUE_12_MASK 0x000000ff -#define MAC_PCU_TXOP_12_15_VALUE_12_GET(x) (((x) & MAC_PCU_TXOP_12_15_VALUE_12_MASK) >> MAC_PCU_TXOP_12_15_VALUE_12_LSB) -#define MAC_PCU_TXOP_12_15_VALUE_12_SET(x) (((x) << MAC_PCU_TXOP_12_15_VALUE_12_LSB) & MAC_PCU_TXOP_12_15_VALUE_12_MASK) - -#define MAC_PCU_LOGIC_ANALYZER_ADDRESS 0x00008110 -#define MAC_PCU_LOGIC_ANALYZER_OFFSET 0x00000110 -#define MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_MSB 31 -#define MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_LSB 18 -#define MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_MASK 0xfffc0000 -#define MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_MASK) >> MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_LSB) -#define MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_LSB) & MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_MASK) -#define MAC_PCU_LOGIC_ANALYZER_INT_ADDR_MSB 17 -#define MAC_PCU_LOGIC_ANALYZER_INT_ADDR_LSB 8 -#define MAC_PCU_LOGIC_ANALYZER_INT_ADDR_MASK 0x0003ff00 -#define MAC_PCU_LOGIC_ANALYZER_INT_ADDR_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_INT_ADDR_MASK) >> MAC_PCU_LOGIC_ANALYZER_INT_ADDR_LSB) -#define MAC_PCU_LOGIC_ANALYZER_INT_ADDR_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_INT_ADDR_LSB) & MAC_PCU_LOGIC_ANALYZER_INT_ADDR_MASK) -#define MAC_PCU_LOGIC_ANALYZER_QCU_SEL_MSB 7 -#define MAC_PCU_LOGIC_ANALYZER_QCU_SEL_LSB 4 -#define MAC_PCU_LOGIC_ANALYZER_QCU_SEL_MASK 0x000000f0 -#define MAC_PCU_LOGIC_ANALYZER_QCU_SEL_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_QCU_SEL_MASK) >> MAC_PCU_LOGIC_ANALYZER_QCU_SEL_LSB) -#define MAC_PCU_LOGIC_ANALYZER_QCU_SEL_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_QCU_SEL_LSB) & MAC_PCU_LOGIC_ANALYZER_QCU_SEL_MASK) -#define MAC_PCU_LOGIC_ANALYZER_ENABLE_MSB 3 -#define MAC_PCU_LOGIC_ANALYZER_ENABLE_LSB 3 -#define MAC_PCU_LOGIC_ANALYZER_ENABLE_MASK 0x00000008 -#define MAC_PCU_LOGIC_ANALYZER_ENABLE_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_ENABLE_MASK) >> MAC_PCU_LOGIC_ANALYZER_ENABLE_LSB) -#define MAC_PCU_LOGIC_ANALYZER_ENABLE_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_ENABLE_LSB) & MAC_PCU_LOGIC_ANALYZER_ENABLE_MASK) -#define MAC_PCU_LOGIC_ANALYZER_STATE_MSB 2 -#define MAC_PCU_LOGIC_ANALYZER_STATE_LSB 2 -#define MAC_PCU_LOGIC_ANALYZER_STATE_MASK 0x00000004 -#define MAC_PCU_LOGIC_ANALYZER_STATE_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_STATE_MASK) >> MAC_PCU_LOGIC_ANALYZER_STATE_LSB) -#define MAC_PCU_LOGIC_ANALYZER_STATE_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_STATE_LSB) & MAC_PCU_LOGIC_ANALYZER_STATE_MASK) -#define MAC_PCU_LOGIC_ANALYZER_CLEAR_MSB 1 -#define MAC_PCU_LOGIC_ANALYZER_CLEAR_LSB 1 -#define MAC_PCU_LOGIC_ANALYZER_CLEAR_MASK 0x00000002 -#define MAC_PCU_LOGIC_ANALYZER_CLEAR_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_CLEAR_MASK) >> MAC_PCU_LOGIC_ANALYZER_CLEAR_LSB) -#define MAC_PCU_LOGIC_ANALYZER_CLEAR_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_CLEAR_LSB) & MAC_PCU_LOGIC_ANALYZER_CLEAR_MASK) -#define MAC_PCU_LOGIC_ANALYZER_HOLD_MSB 0 -#define MAC_PCU_LOGIC_ANALYZER_HOLD_LSB 0 -#define MAC_PCU_LOGIC_ANALYZER_HOLD_MASK 0x00000001 -#define MAC_PCU_LOGIC_ANALYZER_HOLD_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_HOLD_MASK) >> MAC_PCU_LOGIC_ANALYZER_HOLD_LSB) -#define MAC_PCU_LOGIC_ANALYZER_HOLD_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_HOLD_LSB) & MAC_PCU_LOGIC_ANALYZER_HOLD_MASK) - -#define MAC_PCU_LOGIC_ANALYZER_32L_ADDRESS 0x00008114 -#define MAC_PCU_LOGIC_ANALYZER_32L_OFFSET 0x00000114 -#define MAC_PCU_LOGIC_ANALYZER_32L_MASK_MSB 31 -#define MAC_PCU_LOGIC_ANALYZER_32L_MASK_LSB 0 -#define MAC_PCU_LOGIC_ANALYZER_32L_MASK_MASK 0xffffffff -#define MAC_PCU_LOGIC_ANALYZER_32L_MASK_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_32L_MASK_MASK) >> MAC_PCU_LOGIC_ANALYZER_32L_MASK_LSB) -#define MAC_PCU_LOGIC_ANALYZER_32L_MASK_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_32L_MASK_LSB) & MAC_PCU_LOGIC_ANALYZER_32L_MASK_MASK) - -#define MAC_PCU_LOGIC_ANALYZER_16U_ADDRESS 0x00008118 -#define MAC_PCU_LOGIC_ANALYZER_16U_OFFSET 0x00000118 -#define MAC_PCU_LOGIC_ANALYZER_16U_MASK_MSB 15 -#define MAC_PCU_LOGIC_ANALYZER_16U_MASK_LSB 0 -#define MAC_PCU_LOGIC_ANALYZER_16U_MASK_MASK 0x0000ffff -#define MAC_PCU_LOGIC_ANALYZER_16U_MASK_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_16U_MASK_MASK) >> MAC_PCU_LOGIC_ANALYZER_16U_MASK_LSB) -#define MAC_PCU_LOGIC_ANALYZER_16U_MASK_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_16U_MASK_LSB) & MAC_PCU_LOGIC_ANALYZER_16U_MASK_MASK) - -#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_ADDRESS 0x0000811c -#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_OFFSET 0x0000011c -#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_MSB 23 -#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_LSB 16 -#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_MASK 0x00ff0000 -#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_MASK) >> MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_LSB) -#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_LSB) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_MASK) -#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_MSB 15 -#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_LSB 8 -#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_MASK 0x0000ff00 -#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_MASK) >> MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_LSB) -#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_LSB) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_MASK) -#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_MSB 7 -#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_LSB 0 -#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_MASK 0x000000ff -#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_MASK) >> MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_LSB) -#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_LSB) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_MASK) - -#define MAC_PCU_AZIMUTH_MODE_ADDRESS 0x00008120 -#define MAC_PCU_AZIMUTH_MODE_OFFSET 0x00000120 -#define MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_MSB 7 -#define MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_LSB 7 -#define MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_MASK 0x00000080 -#define MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_MASK) >> MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_LSB) -#define MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_LSB) & MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_MASK) -#define MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_MSB 6 -#define MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_LSB 6 -#define MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_MASK 0x00000040 -#define MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_MASK) >> MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_LSB) -#define MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_LSB) & MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_MASK) -#define MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_MSB 5 -#define MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_LSB 5 -#define MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_MASK 0x00000020 -#define MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_MASK) >> MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_LSB) -#define MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_LSB) & MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_MASK) -#define MAC_PCU_AZIMUTH_MODE_CLK_EN_MSB 4 -#define MAC_PCU_AZIMUTH_MODE_CLK_EN_LSB 4 -#define MAC_PCU_AZIMUTH_MODE_CLK_EN_MASK 0x00000010 -#define MAC_PCU_AZIMUTH_MODE_CLK_EN_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_CLK_EN_MASK) >> MAC_PCU_AZIMUTH_MODE_CLK_EN_LSB) -#define MAC_PCU_AZIMUTH_MODE_CLK_EN_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_CLK_EN_LSB) & MAC_PCU_AZIMUTH_MODE_CLK_EN_MASK) -#define MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_MSB 3 -#define MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_LSB 3 -#define MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_MASK 0x00000008 -#define MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_MASK) >> MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_LSB) -#define MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_LSB) & MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_MASK) -#define MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_MSB 2 -#define MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_LSB 2 -#define MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_MASK 0x00000004 -#define MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_MASK) >> MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_LSB) -#define MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_LSB) & MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_MASK) -#define MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_MSB 1 -#define MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_LSB 1 -#define MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_MASK 0x00000002 -#define MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_MASK) >> MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_LSB) -#define MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_LSB) & MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_MASK) -#define MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_MSB 0 -#define MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_LSB 0 -#define MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_MASK 0x00000001 -#define MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_MASK) >> MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_LSB) -#define MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_LSB) & MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_MASK) - -#define MAC_PCU_20_40_MODE_ADDRESS 0x00008124 -#define MAC_PCU_20_40_MODE_OFFSET 0x00000124 -#define MAC_PCU_20_40_MODE_PIFS_CYCLES_MSB 15 -#define MAC_PCU_20_40_MODE_PIFS_CYCLES_LSB 4 -#define MAC_PCU_20_40_MODE_PIFS_CYCLES_MASK 0x0000fff0 -#define MAC_PCU_20_40_MODE_PIFS_CYCLES_GET(x) (((x) & MAC_PCU_20_40_MODE_PIFS_CYCLES_MASK) >> MAC_PCU_20_40_MODE_PIFS_CYCLES_LSB) -#define MAC_PCU_20_40_MODE_PIFS_CYCLES_SET(x) (((x) << MAC_PCU_20_40_MODE_PIFS_CYCLES_LSB) & MAC_PCU_20_40_MODE_PIFS_CYCLES_MASK) -#define MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_MSB 3 -#define MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_LSB 3 -#define MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_MASK 0x00000008 -#define MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_GET(x) (((x) & MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_MASK) >> MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_LSB) -#define MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_SET(x) (((x) << MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_LSB) & MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_MASK) -#define MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_MSB 2 -#define MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_LSB 2 -#define MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_MASK 0x00000004 -#define MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_GET(x) (((x) & MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_MASK) >> MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_LSB) -#define MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_SET(x) (((x) << MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_LSB) & MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_MASK) -#define MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_MSB 1 -#define MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_LSB 1 -#define MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_MASK 0x00000002 -#define MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_GET(x) (((x) & MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_MASK) >> MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_LSB) -#define MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_SET(x) (((x) << MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_LSB) & MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_MASK) -#define MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_MSB 0 -#define MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_LSB 0 -#define MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_MASK 0x00000001 -#define MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_GET(x) (((x) & MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_MASK) >> MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_LSB) -#define MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_SET(x) (((x) << MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_LSB) & MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_MASK) - -#define MAC_PCU_RX_CLEAR_DIFF_CNT_ADDRESS 0x00008128 -#define MAC_PCU_RX_CLEAR_DIFF_CNT_OFFSET 0x00000128 -#define MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_MSB 31 -#define MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_LSB 0 -#define MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_MASK 0xffffffff -#define MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_GET(x) (((x) & MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_MASK) >> MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_LSB) -#define MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_SET(x) (((x) << MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_LSB) & MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_MASK) - -#define MAC_PCU_SELF_GEN_ANTENNA_MASK_ADDRESS 0x0000812c -#define MAC_PCU_SELF_GEN_ANTENNA_MASK_OFFSET 0x0000012c -#define MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_MSB 2 -#define MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_LSB 0 -#define MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_MASK 0x00000007 -#define MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_GET(x) (((x) & MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_MASK) >> MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_LSB) -#define MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_SET(x) (((x) << MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_LSB) & MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_MASK) - -#define MAC_PCU_BA_BAR_CONTROL_ADDRESS 0x00008130 -#define MAC_PCU_BA_BAR_CONTROL_OFFSET 0x00000130 -#define MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_MSB 12 -#define MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_LSB 12 -#define MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_MASK 0x00001000 -#define MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_MASK) >> MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_LSB) -#define MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_LSB) & MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_MASK) -#define MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_MSB 11 -#define MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_LSB 11 -#define MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_MASK 0x00000800 -#define MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_MASK) >> MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_LSB) -#define MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_LSB) & MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_MASK) -#define MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_MSB 10 -#define MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_LSB 10 -#define MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_MASK 0x00000400 -#define MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_MASK) >> MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_LSB) -#define MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_LSB) & MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_MASK) -#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_MSB 9 -#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_LSB 9 -#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_MASK 0x00000200 -#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_MASK) >> MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_LSB) -#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_LSB) & MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_MASK) -#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_MSB 8 -#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_LSB 8 -#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_MASK 0x00000100 -#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_MASK) >> MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_LSB) -#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_LSB) & MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_MASK) -#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_MSB 7 -#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_LSB 4 -#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_MASK 0x000000f0 -#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_MASK) >> MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_LSB) -#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_LSB) & MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_MASK) -#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_MSB 3 -#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_LSB 0 -#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_MASK 0x0000000f -#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_MASK) >> MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_LSB) -#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_LSB) & MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_MASK) - -#define MAC_PCU_LEGACY_PLCP_SPOOF_ADDRESS 0x00008134 -#define MAC_PCU_LEGACY_PLCP_SPOOF_OFFSET 0x00000134 -#define MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_MSB 12 -#define MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_LSB 8 -#define MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_MASK 0x00001f00 -#define MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_GET(x) (((x) & MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_MASK) >> MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_LSB) -#define MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_SET(x) (((x) << MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_LSB) & MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_MASK) -#define MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_MSB 7 -#define MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_LSB 0 -#define MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_MASK 0x000000ff -#define MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_GET(x) (((x) & MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_MASK) >> MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_LSB) -#define MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_SET(x) (((x) << MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_LSB) & MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_MASK) - -#define MAC_PCU_PHY_ERROR_MASK_CONT_ADDRESS 0x00008138 -#define MAC_PCU_PHY_ERROR_MASK_CONT_OFFSET 0x00000138 -#define MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_MSB 23 -#define MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_LSB 16 -#define MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_MASK 0x00ff0000 -#define MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_MASK) >> MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_LSB) -#define MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_LSB) & MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_MASK) -#define MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_MSB 7 -#define MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_LSB 0 -#define MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_MASK 0x000000ff -#define MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_LSB) -#define MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_LSB) & MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_MASK) - -#define MAC_PCU_TX_TIMER_ADDRESS 0x0000813c -#define MAC_PCU_TX_TIMER_OFFSET 0x0000013c -#define MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_MSB 25 -#define MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_LSB 25 -#define MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_MASK 0x02000000 -#define MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_GET(x) (((x) & MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_MASK) >> MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_LSB) -#define MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_SET(x) (((x) << MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_LSB) & MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_MASK) -#define MAC_PCU_TX_TIMER_QUIET_TIMER_MSB 24 -#define MAC_PCU_TX_TIMER_QUIET_TIMER_LSB 20 -#define MAC_PCU_TX_TIMER_QUIET_TIMER_MASK 0x01f00000 -#define MAC_PCU_TX_TIMER_QUIET_TIMER_GET(x) (((x) & MAC_PCU_TX_TIMER_QUIET_TIMER_MASK) >> MAC_PCU_TX_TIMER_QUIET_TIMER_LSB) -#define MAC_PCU_TX_TIMER_QUIET_TIMER_SET(x) (((x) << MAC_PCU_TX_TIMER_QUIET_TIMER_LSB) & MAC_PCU_TX_TIMER_QUIET_TIMER_MASK) -#define MAC_PCU_TX_TIMER_RIFS_TIMER_MSB 19 -#define MAC_PCU_TX_TIMER_RIFS_TIMER_LSB 16 -#define MAC_PCU_TX_TIMER_RIFS_TIMER_MASK 0x000f0000 -#define MAC_PCU_TX_TIMER_RIFS_TIMER_GET(x) (((x) & MAC_PCU_TX_TIMER_RIFS_TIMER_MASK) >> MAC_PCU_TX_TIMER_RIFS_TIMER_LSB) -#define MAC_PCU_TX_TIMER_RIFS_TIMER_SET(x) (((x) << MAC_PCU_TX_TIMER_RIFS_TIMER_LSB) & MAC_PCU_TX_TIMER_RIFS_TIMER_MASK) -#define MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_MSB 15 -#define MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_LSB 15 -#define MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_MASK 0x00008000 -#define MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_GET(x) (((x) & MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_MASK) >> MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_LSB) -#define MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_SET(x) (((x) << MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_LSB) & MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_MASK) -#define MAC_PCU_TX_TIMER_TX_TIMER_MSB 14 -#define MAC_PCU_TX_TIMER_TX_TIMER_LSB 0 -#define MAC_PCU_TX_TIMER_TX_TIMER_MASK 0x00007fff -#define MAC_PCU_TX_TIMER_TX_TIMER_GET(x) (((x) & MAC_PCU_TX_TIMER_TX_TIMER_MASK) >> MAC_PCU_TX_TIMER_TX_TIMER_LSB) -#define MAC_PCU_TX_TIMER_TX_TIMER_SET(x) (((x) << MAC_PCU_TX_TIMER_TX_TIMER_LSB) & MAC_PCU_TX_TIMER_TX_TIMER_MASK) - -#define MAC_PCU_TXBUF_CTRL_ADDRESS 0x00008140 -#define MAC_PCU_TXBUF_CTRL_OFFSET 0x00000140 -#define MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_MSB 16 -#define MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_LSB 16 -#define MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_MASK 0x00010000 -#define MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_GET(x) (((x) & MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_MASK) >> MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_LSB) -#define MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_SET(x) (((x) << MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_LSB) & MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_MASK) -#define MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_MSB 11 -#define MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_LSB 0 -#define MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_MASK 0x00000fff -#define MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_GET(x) (((x) & MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_MASK) >> MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_LSB) -#define MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_SET(x) (((x) << MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_LSB) & MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_MASK) - -#define MAC_PCU_MISC_MODE2_ADDRESS 0x00008144 -#define MAC_PCU_MISC_MODE2_OFFSET 0x00000144 -#define MAC_PCU_MISC_MODE2_RESERVED_1_MSB 31 -#define MAC_PCU_MISC_MODE2_RESERVED_1_LSB 28 -#define MAC_PCU_MISC_MODE2_RESERVED_1_MASK 0xf0000000 -#define MAC_PCU_MISC_MODE2_RESERVED_1_GET(x) (((x) & MAC_PCU_MISC_MODE2_RESERVED_1_MASK) >> MAC_PCU_MISC_MODE2_RESERVED_1_LSB) -#define MAC_PCU_MISC_MODE2_RESERVED_1_SET(x) (((x) << MAC_PCU_MISC_MODE2_RESERVED_1_LSB) & MAC_PCU_MISC_MODE2_RESERVED_1_MASK) -#define MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_MSB 27 -#define MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_LSB 27 -#define MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_MASK 0x08000000 -#define MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_GET(x) (((x) & MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_MASK) >> MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_LSB) -#define MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_SET(x) (((x) << MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_LSB) & MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_MASK) -#define MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_MSB 26 -#define MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_LSB 26 -#define MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_MASK 0x04000000 -#define MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_GET(x) (((x) & MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_MASK) >> MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_LSB) -#define MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_SET(x) (((x) << MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_LSB) & MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_MASK) -#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_MSB 25 -#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_LSB 25 -#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_MASK 0x02000000 -#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_GET(x) (((x) & MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_MASK) >> MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_LSB) -#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_SET(x) (((x) << MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_LSB) & MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_MASK) -#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_MSB 24 -#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_LSB 24 -#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_MASK 0x01000000 -#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_GET(x) (((x) & MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_MASK) >> MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_LSB) -#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_SET(x) (((x) << MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_LSB) & MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_MASK) -#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_MSB 23 -#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_LSB 23 -#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_MASK 0x00800000 -#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_GET(x) (((x) & MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_MASK) >> MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_LSB) -#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_SET(x) (((x) << MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_LSB) & MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_MASK) -#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_MSB 22 -#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_LSB 22 -#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_MASK 0x00400000 -#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_GET(x) (((x) & MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_MASK) >> MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_LSB) -#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_SET(x) (((x) << MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_LSB) & MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_MASK) -#define MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_MSB 21 -#define MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_LSB 21 -#define MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_MASK 0x00200000 -#define MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_GET(x) (((x) & MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_MASK) >> MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_LSB) -#define MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_SET(x) (((x) << MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_LSB) & MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_MASK) -#define MAC_PCU_MISC_MODE2_BUG_28676_MSB 20 -#define MAC_PCU_MISC_MODE2_BUG_28676_LSB 20 -#define MAC_PCU_MISC_MODE2_BUG_28676_MASK 0x00100000 -#define MAC_PCU_MISC_MODE2_BUG_28676_GET(x) (((x) & MAC_PCU_MISC_MODE2_BUG_28676_MASK) >> MAC_PCU_MISC_MODE2_BUG_28676_LSB) -#define MAC_PCU_MISC_MODE2_BUG_28676_SET(x) (((x) << MAC_PCU_MISC_MODE2_BUG_28676_LSB) & MAC_PCU_MISC_MODE2_BUG_28676_MASK) -#define MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_MSB 19 -#define MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_LSB 19 -#define MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_MASK 0x00080000 -#define MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_GET(x) (((x) & MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_MASK) >> MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_LSB) -#define MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_SET(x) (((x) << MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_LSB) & MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_MASK) -#define MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_MSB 18 -#define MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_LSB 18 -#define MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_MASK 0x00040000 -#define MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_GET(x) (((x) & MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_MASK) >> MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_LSB) -#define MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_SET(x) (((x) << MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_LSB) & MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_MASK) -#define MAC_PCU_MISC_MODE2_AGG_WEP_MSB 17 -#define MAC_PCU_MISC_MODE2_AGG_WEP_LSB 17 -#define MAC_PCU_MISC_MODE2_AGG_WEP_MASK 0x00020000 -#define MAC_PCU_MISC_MODE2_AGG_WEP_GET(x) (((x) & MAC_PCU_MISC_MODE2_AGG_WEP_MASK) >> MAC_PCU_MISC_MODE2_AGG_WEP_LSB) -#define MAC_PCU_MISC_MODE2_AGG_WEP_SET(x) (((x) << MAC_PCU_MISC_MODE2_AGG_WEP_LSB) & MAC_PCU_MISC_MODE2_AGG_WEP_MASK) -#define MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_MSB 16 -#define MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_LSB 16 -#define MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_MASK 0x00010000 -#define MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_GET(x) (((x) & MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_MASK) >> MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_LSB) -#define MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_SET(x) (((x) << MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_LSB) & MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_MASK) -#define MAC_PCU_MISC_MODE2_MGMT_QOS_MSB 15 -#define MAC_PCU_MISC_MODE2_MGMT_QOS_LSB 8 -#define MAC_PCU_MISC_MODE2_MGMT_QOS_MASK 0x0000ff00 -#define MAC_PCU_MISC_MODE2_MGMT_QOS_GET(x) (((x) & MAC_PCU_MISC_MODE2_MGMT_QOS_MASK) >> MAC_PCU_MISC_MODE2_MGMT_QOS_LSB) -#define MAC_PCU_MISC_MODE2_MGMT_QOS_SET(x) (((x) << MAC_PCU_MISC_MODE2_MGMT_QOS_LSB) & MAC_PCU_MISC_MODE2_MGMT_QOS_MASK) -#define MAC_PCU_MISC_MODE2_CFP_IGNORE_MSB 7 -#define MAC_PCU_MISC_MODE2_CFP_IGNORE_LSB 7 -#define MAC_PCU_MISC_MODE2_CFP_IGNORE_MASK 0x00000080 -#define MAC_PCU_MISC_MODE2_CFP_IGNORE_GET(x) (((x) & MAC_PCU_MISC_MODE2_CFP_IGNORE_MASK) >> MAC_PCU_MISC_MODE2_CFP_IGNORE_LSB) -#define MAC_PCU_MISC_MODE2_CFP_IGNORE_SET(x) (((x) << MAC_PCU_MISC_MODE2_CFP_IGNORE_LSB) & MAC_PCU_MISC_MODE2_CFP_IGNORE_MASK) -#define MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_MSB 6 -#define MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_LSB 6 -#define MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_MASK 0x00000040 -#define MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_MASK) >> MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_LSB) -#define MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_LSB) & MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_MASK) -#define MAC_PCU_MISC_MODE2_RESERVED_2_MSB 5 -#define MAC_PCU_MISC_MODE2_RESERVED_2_LSB 5 -#define MAC_PCU_MISC_MODE2_RESERVED_2_MASK 0x00000020 -#define MAC_PCU_MISC_MODE2_RESERVED_2_GET(x) (((x) & MAC_PCU_MISC_MODE2_RESERVED_2_MASK) >> MAC_PCU_MISC_MODE2_RESERVED_2_LSB) -#define MAC_PCU_MISC_MODE2_RESERVED_2_SET(x) (((x) << MAC_PCU_MISC_MODE2_RESERVED_2_LSB) & MAC_PCU_MISC_MODE2_RESERVED_2_MASK) -#define MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_MSB 4 -#define MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_LSB 4 -#define MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_MASK 0x00000010 -#define MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_MASK) >> MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_LSB) -#define MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_LSB) & MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_MASK) -#define MAC_PCU_MISC_MODE2_RESERVED_0_MSB 3 -#define MAC_PCU_MISC_MODE2_RESERVED_0_LSB 3 -#define MAC_PCU_MISC_MODE2_RESERVED_0_MASK 0x00000008 -#define MAC_PCU_MISC_MODE2_RESERVED_0_GET(x) (((x) & MAC_PCU_MISC_MODE2_RESERVED_0_MASK) >> MAC_PCU_MISC_MODE2_RESERVED_0_LSB) -#define MAC_PCU_MISC_MODE2_RESERVED_0_SET(x) (((x) << MAC_PCU_MISC_MODE2_RESERVED_0_LSB) & MAC_PCU_MISC_MODE2_RESERVED_0_MASK) -#define MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_MSB 2 -#define MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_LSB 2 -#define MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_MASK 0x00000004 -#define MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_GET(x) (((x) & MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_MASK) >> MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_LSB) -#define MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_SET(x) (((x) << MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_LSB) & MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_MASK) -#define MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_MSB 1 -#define MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_LSB 1 -#define MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_MASK 0x00000002 -#define MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_MASK) >> MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_LSB) -#define MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_LSB) & MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_MASK) -#define MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_MSB 0 -#define MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_LSB 0 -#define MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_MASK 0x00000001 -#define MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_MASK) >> MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_LSB) -#define MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_LSB) & MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_MASK) - -#define MAC_PCU_ALT_AES_MUTE_MASK_ADDRESS 0x00008148 -#define MAC_PCU_ALT_AES_MUTE_MASK_OFFSET 0x00000148 -#define MAC_PCU_ALT_AES_MUTE_MASK_QOS_MSB 31 -#define MAC_PCU_ALT_AES_MUTE_MASK_QOS_LSB 16 -#define MAC_PCU_ALT_AES_MUTE_MASK_QOS_MASK 0xffff0000 -#define MAC_PCU_ALT_AES_MUTE_MASK_QOS_GET(x) (((x) & MAC_PCU_ALT_AES_MUTE_MASK_QOS_MASK) >> MAC_PCU_ALT_AES_MUTE_MASK_QOS_LSB) -#define MAC_PCU_ALT_AES_MUTE_MASK_QOS_SET(x) (((x) << MAC_PCU_ALT_AES_MUTE_MASK_QOS_LSB) & MAC_PCU_ALT_AES_MUTE_MASK_QOS_MASK) - -#define MAC_PCU_AZIMUTH_TIME_STAMP_ADDRESS 0x0000814c -#define MAC_PCU_AZIMUTH_TIME_STAMP_OFFSET 0x0000014c -#define MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_MSB 31 -#define MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_LSB 0 -#define MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_MASK 0xffffffff -#define MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_GET(x) (((x) & MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_MASK) >> MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_LSB) -#define MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_SET(x) (((x) << MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_LSB) & MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_MASK) - -#define MAC_PCU_MAX_CFP_DUR_ADDRESS 0x00008150 -#define MAC_PCU_MAX_CFP_DUR_OFFSET 0x00000150 -#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_MSB 7 -#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_LSB 4 -#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_MASK 0x000000f0 -#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_GET(x) (((x) & MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_MASK) >> MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_LSB) -#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_SET(x) (((x) << MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_LSB) & MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_MASK) -#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_MSB 3 -#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_LSB 0 -#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_MASK 0x0000000f -#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_GET(x) (((x) & MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_MASK) >> MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_LSB) -#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_SET(x) (((x) << MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_LSB) & MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_MASK) - -#define MAC_PCU_HCF_TIMEOUT_ADDRESS 0x00008154 -#define MAC_PCU_HCF_TIMEOUT_OFFSET 0x00000154 -#define MAC_PCU_HCF_TIMEOUT_VALUE_MSB 15 -#define MAC_PCU_HCF_TIMEOUT_VALUE_LSB 0 -#define MAC_PCU_HCF_TIMEOUT_VALUE_MASK 0x0000ffff -#define MAC_PCU_HCF_TIMEOUT_VALUE_GET(x) (((x) & MAC_PCU_HCF_TIMEOUT_VALUE_MASK) >> MAC_PCU_HCF_TIMEOUT_VALUE_LSB) -#define MAC_PCU_HCF_TIMEOUT_VALUE_SET(x) (((x) << MAC_PCU_HCF_TIMEOUT_VALUE_LSB) & MAC_PCU_HCF_TIMEOUT_VALUE_MASK) - -#define MAC_PCU_BLUETOOTH_WEIGHTS2_ADDRESS 0x00008158 -#define MAC_PCU_BLUETOOTH_WEIGHTS2_OFFSET 0x00000158 -#define MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_MSB 31 -#define MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_LSB 16 -#define MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_MASK 0xffff0000 -#define MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_GET(x) (((x) & MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_MASK) >> MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_LSB) -#define MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_SET(x) (((x) << MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_LSB) & MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_MASK) - -#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_ADDRESS 0x0000815c -#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_OFFSET 0x0000015c -#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_MSB 31 -#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_LSB 0 -#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_MASK 0xffffffff -#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_GET(x) (((x) & MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_MASK) >> MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_LSB) -#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_SET(x) (((x) << MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_LSB) & MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_MASK) - -#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_ADDRESS 0x00008160 -#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_OFFSET 0x00000160 -#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_MSB 31 -#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_LSB 0 -#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_MASK 0xffffffff -#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_GET(x) (((x) & MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_MASK) >> MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_LSB) -#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_SET(x) (((x) << MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_LSB) & MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_MASK) - -#define MAC_PCU_BLUETOOTH_MODE3_ADDRESS 0x00008164 -#define MAC_PCU_BLUETOOTH_MODE3_OFFSET 0x00000164 -#define MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_MSB 31 -#define MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_LSB 28 -#define MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_MASK 0xf0000000 -#define MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_MASK) >> MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_LSB) -#define MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_LSB) & MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_MASK) -#define MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_MSB 27 -#define MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_LSB 27 -#define MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_MASK 0x08000000 -#define MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_MASK) >> MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_LSB) -#define MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_LSB) & MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_MASK) -#define MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_MSB 26 -#define MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_LSB 25 -#define MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_MASK 0x06000000 -#define MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_MASK) >> MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_LSB) -#define MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_LSB) & MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_MASK) -#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_MSB 24 -#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_LSB 24 -#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_MASK 0x01000000 -#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_MASK) >> MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_LSB) -#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_LSB) & MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_MASK) -#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_MSB 23 -#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_LSB 23 -#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_MASK 0x00800000 -#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_MASK) >> MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_LSB) -#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_LSB) & MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_MASK) -#define MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_MSB 22 -#define MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_LSB 22 -#define MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_MASK 0x00400000 -#define MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_MASK) >> MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_LSB) -#define MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_LSB) & MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_MASK) -#define MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_MSB 21 -#define MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_LSB 21 -#define MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_MASK 0x00200000 -#define MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_MASK) >> MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_LSB) -#define MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_LSB) & MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_MASK) -#define MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_MSB 20 -#define MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_LSB 20 -#define MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_MASK 0x00100000 -#define MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_MASK) >> MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_LSB) -#define MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_LSB) & MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_MASK) -#define MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_MSB 19 -#define MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_LSB 16 -#define MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_MASK 0x000f0000 -#define MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_MASK) >> MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_LSB) -#define MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_LSB) & MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_MASK) -#define MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_MSB 15 -#define MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_LSB 8 -#define MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_MASK 0x0000ff00 -#define MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_MASK) >> MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_LSB) -#define MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_LSB) & MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_MASK) -#define MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_MSB 7 -#define MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_LSB 0 -#define MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_MASK 0x000000ff -#define MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_MASK) >> MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_LSB) -#define MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_LSB) & MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_MASK) - -#define MAC_PCU_BLUETOOTH_MODE4_ADDRESS 0x00008168 -#define MAC_PCU_BLUETOOTH_MODE4_OFFSET 0x00000168 -#define MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_MSB 31 -#define MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_LSB 16 -#define MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_MASK 0xffff0000 -#define MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_LSB) -#define MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_MASK) -#define MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_MSB 15 -#define MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_LSB 0 -#define MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_MASK 0x0000ffff -#define MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_LSB) -#define MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_MASK) - -#define MAC_PCU_BT_BT_ADDRESS 0x00008200 -#define MAC_PCU_BT_BT_OFFSET 0x00000200 -#define MAC_PCU_BT_BT_WEIGHT_MSB 31 -#define MAC_PCU_BT_BT_WEIGHT_LSB 0 -#define MAC_PCU_BT_BT_WEIGHT_MASK 0xffffffff -#define MAC_PCU_BT_BT_WEIGHT_GET(x) (((x) & MAC_PCU_BT_BT_WEIGHT_MASK) >> MAC_PCU_BT_BT_WEIGHT_LSB) -#define MAC_PCU_BT_BT_WEIGHT_SET(x) (((x) << MAC_PCU_BT_BT_WEIGHT_LSB) & MAC_PCU_BT_BT_WEIGHT_MASK) - -#define MAC_PCU_BT_BT_ASYNC_ADDRESS 0x00008300 -#define MAC_PCU_BT_BT_ASYNC_OFFSET 0x00000300 -#define MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_MSB 15 -#define MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_LSB 12 -#define MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_MASK 0x0000f000 -#define MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_GET(x) (((x) & MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_MASK) >> MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_LSB) -#define MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_SET(x) (((x) << MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_LSB) & MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_MASK) -#define MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_MSB 11 -#define MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_LSB 8 -#define MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_MASK 0x00000f00 -#define MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_GET(x) (((x) & MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_MASK) >> MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_LSB) -#define MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_SET(x) (((x) << MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_LSB) & MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_MASK) -#define MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_MSB 7 -#define MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_LSB 4 -#define MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_MASK 0x000000f0 -#define MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_GET(x) (((x) & MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_MASK) >> MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_LSB) -#define MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_SET(x) (((x) << MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_LSB) & MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_MASK) -#define MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_MSB 3 -#define MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_LSB 0 -#define MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_MASK 0x0000000f -#define MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_GET(x) (((x) & MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_MASK) >> MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_LSB) -#define MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_SET(x) (((x) << MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_LSB) & MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_MASK) - -#define MAC_PCU_BT_WL_1_ADDRESS 0x00008304 -#define MAC_PCU_BT_WL_1_OFFSET 0x00000304 -#define MAC_PCU_BT_WL_1_WEIGHT_MSB 31 -#define MAC_PCU_BT_WL_1_WEIGHT_LSB 0 -#define MAC_PCU_BT_WL_1_WEIGHT_MASK 0xffffffff -#define MAC_PCU_BT_WL_1_WEIGHT_GET(x) (((x) & MAC_PCU_BT_WL_1_WEIGHT_MASK) >> MAC_PCU_BT_WL_1_WEIGHT_LSB) -#define MAC_PCU_BT_WL_1_WEIGHT_SET(x) (((x) << MAC_PCU_BT_WL_1_WEIGHT_LSB) & MAC_PCU_BT_WL_1_WEIGHT_MASK) - -#define MAC_PCU_BT_WL_2_ADDRESS 0x00008308 -#define MAC_PCU_BT_WL_2_OFFSET 0x00000308 -#define MAC_PCU_BT_WL_2_WEIGHT_MSB 31 -#define MAC_PCU_BT_WL_2_WEIGHT_LSB 0 -#define MAC_PCU_BT_WL_2_WEIGHT_MASK 0xffffffff -#define MAC_PCU_BT_WL_2_WEIGHT_GET(x) (((x) & MAC_PCU_BT_WL_2_WEIGHT_MASK) >> MAC_PCU_BT_WL_2_WEIGHT_LSB) -#define MAC_PCU_BT_WL_2_WEIGHT_SET(x) (((x) << MAC_PCU_BT_WL_2_WEIGHT_LSB) & MAC_PCU_BT_WL_2_WEIGHT_MASK) - -#define MAC_PCU_BT_WL_3_ADDRESS 0x0000830c -#define MAC_PCU_BT_WL_3_OFFSET 0x0000030c -#define MAC_PCU_BT_WL_3_WEIGHT_MSB 31 -#define MAC_PCU_BT_WL_3_WEIGHT_LSB 0 -#define MAC_PCU_BT_WL_3_WEIGHT_MASK 0xffffffff -#define MAC_PCU_BT_WL_3_WEIGHT_GET(x) (((x) & MAC_PCU_BT_WL_3_WEIGHT_MASK) >> MAC_PCU_BT_WL_3_WEIGHT_LSB) -#define MAC_PCU_BT_WL_3_WEIGHT_SET(x) (((x) << MAC_PCU_BT_WL_3_WEIGHT_LSB) & MAC_PCU_BT_WL_3_WEIGHT_MASK) - -#define MAC_PCU_BT_WL_4_ADDRESS 0x00008310 -#define MAC_PCU_BT_WL_4_OFFSET 0x00000310 -#define MAC_PCU_BT_WL_4_WEIGHT_MSB 31 -#define MAC_PCU_BT_WL_4_WEIGHT_LSB 0 -#define MAC_PCU_BT_WL_4_WEIGHT_MASK 0xffffffff -#define MAC_PCU_BT_WL_4_WEIGHT_GET(x) (((x) & MAC_PCU_BT_WL_4_WEIGHT_MASK) >> MAC_PCU_BT_WL_4_WEIGHT_LSB) -#define MAC_PCU_BT_WL_4_WEIGHT_SET(x) (((x) << MAC_PCU_BT_WL_4_WEIGHT_LSB) & MAC_PCU_BT_WL_4_WEIGHT_MASK) - -#define MAC_PCU_COEX_EPTA_ADDRESS 0x00008314 -#define MAC_PCU_COEX_EPTA_OFFSET 0x00000314 -#define MAC_PCU_COEX_EPTA_WT_IDX_MSB 12 -#define MAC_PCU_COEX_EPTA_WT_IDX_LSB 6 -#define MAC_PCU_COEX_EPTA_WT_IDX_MASK 0x00001fc0 -#define MAC_PCU_COEX_EPTA_WT_IDX_GET(x) (((x) & MAC_PCU_COEX_EPTA_WT_IDX_MASK) >> MAC_PCU_COEX_EPTA_WT_IDX_LSB) -#define MAC_PCU_COEX_EPTA_WT_IDX_SET(x) (((x) << MAC_PCU_COEX_EPTA_WT_IDX_LSB) & MAC_PCU_COEX_EPTA_WT_IDX_MASK) -#define MAC_PCU_COEX_EPTA_LINKID_MSB 5 -#define MAC_PCU_COEX_EPTA_LINKID_LSB 0 -#define MAC_PCU_COEX_EPTA_LINKID_MASK 0x0000003f -#define MAC_PCU_COEX_EPTA_LINKID_GET(x) (((x) & MAC_PCU_COEX_EPTA_LINKID_MASK) >> MAC_PCU_COEX_EPTA_LINKID_LSB) -#define MAC_PCU_COEX_EPTA_LINKID_SET(x) (((x) << MAC_PCU_COEX_EPTA_LINKID_LSB) & MAC_PCU_COEX_EPTA_LINKID_MASK) - -#define MAC_PCU_COEX_LNAMAXGAIN1_ADDRESS 0x00008318 -#define MAC_PCU_COEX_LNAMAXGAIN1_OFFSET 0x00000318 -#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_MSB 31 -#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_LSB 24 -#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_MASK 0xff000000 -#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_MASK) >> MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_LSB) -#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_LSB) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_MASK) -#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_MSB 23 -#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_LSB 16 -#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_MASK 0x00ff0000 -#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_MASK) >> MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_LSB) -#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_LSB) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_MASK) -#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_MSB 15 -#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_LSB 8 -#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_MASK 0x0000ff00 -#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_MASK) >> MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_LSB) -#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_LSB) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_MASK) -#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_MSB 7 -#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_LSB 0 -#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_MASK 0x000000ff -#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_MASK) >> MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_LSB) -#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_LSB) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_MASK) - -#define MAC_PCU_COEX_LNAMAXGAIN2_ADDRESS 0x0000831c -#define MAC_PCU_COEX_LNAMAXGAIN2_OFFSET 0x0000031c -#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_MSB 31 -#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_LSB 24 -#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_MASK 0xff000000 -#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_MASK) >> MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_LSB) -#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_LSB) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_MASK) -#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_MSB 23 -#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_LSB 16 -#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_MASK 0x00ff0000 -#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_MASK) >> MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_LSB) -#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_LSB) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_MASK) -#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_MSB 15 -#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_LSB 8 -#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_MASK 0x0000ff00 -#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_MASK) >> MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_LSB) -#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_LSB) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_MASK) -#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_MSB 7 -#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_LSB 0 -#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_MASK 0x000000ff -#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_MASK) >> MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_LSB) -#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_LSB) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_MASK) - -#define MAC_PCU_COEX_LNAMAXGAIN3_ADDRESS 0x00008320 -#define MAC_PCU_COEX_LNAMAXGAIN3_OFFSET 0x00000320 -#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_MSB 31 -#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_LSB 24 -#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_MASK 0xff000000 -#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_MASK) >> MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_LSB) -#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_LSB) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_MASK) -#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_MSB 23 -#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_LSB 16 -#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_MASK 0x00ff0000 -#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_MASK) >> MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_LSB) -#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_LSB) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_MASK) -#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_MSB 15 -#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_LSB 8 -#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_MASK 0x0000ff00 -#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_MASK) >> MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_LSB) -#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_LSB) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_MASK) -#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_MSB 7 -#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_LSB 0 -#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_MASK 0x000000ff -#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_MASK) >> MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_LSB) -#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_LSB) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_MASK) - -#define MAC_PCU_COEX_LNAMAXGAIN4_ADDRESS 0x00008324 -#define MAC_PCU_COEX_LNAMAXGAIN4_OFFSET 0x00000324 -#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_MSB 31 -#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_LSB 24 -#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_MASK 0xff000000 -#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_MASK) >> MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_LSB) -#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_LSB) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_MASK) -#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_MSB 23 -#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_LSB 16 -#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_MASK 0x00ff0000 -#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_MASK) >> MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_LSB) -#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_LSB) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_MASK) -#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_MSB 15 -#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_LSB 8 -#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_MASK 0x0000ff00 -#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_MASK) >> MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_LSB) -#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_LSB) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_MASK) -#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_MSB 7 -#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_LSB 0 -#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_MASK 0x000000ff -#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_MASK) >> MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_LSB) -#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_LSB) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_MASK) - -#define MAC_PCU_BASIC_RATE_SET0_ADDRESS 0x00008328 -#define MAC_PCU_BASIC_RATE_SET0_OFFSET 0x00000328 -#define MAC_PCU_BASIC_RATE_SET0_VALUE_MSB 29 -#define MAC_PCU_BASIC_RATE_SET0_VALUE_LSB 0 -#define MAC_PCU_BASIC_RATE_SET0_VALUE_MASK 0x3fffffff -#define MAC_PCU_BASIC_RATE_SET0_VALUE_GET(x) (((x) & MAC_PCU_BASIC_RATE_SET0_VALUE_MASK) >> MAC_PCU_BASIC_RATE_SET0_VALUE_LSB) -#define MAC_PCU_BASIC_RATE_SET0_VALUE_SET(x) (((x) << MAC_PCU_BASIC_RATE_SET0_VALUE_LSB) & MAC_PCU_BASIC_RATE_SET0_VALUE_MASK) - -#define MAC_PCU_BASIC_RATE_SET1_ADDRESS 0x0000832c -#define MAC_PCU_BASIC_RATE_SET1_OFFSET 0x0000032c -#define MAC_PCU_BASIC_RATE_SET1_VALUE_MSB 29 -#define MAC_PCU_BASIC_RATE_SET1_VALUE_LSB 0 -#define MAC_PCU_BASIC_RATE_SET1_VALUE_MASK 0x3fffffff -#define MAC_PCU_BASIC_RATE_SET1_VALUE_GET(x) (((x) & MAC_PCU_BASIC_RATE_SET1_VALUE_MASK) >> MAC_PCU_BASIC_RATE_SET1_VALUE_LSB) -#define MAC_PCU_BASIC_RATE_SET1_VALUE_SET(x) (((x) << MAC_PCU_BASIC_RATE_SET1_VALUE_LSB) & MAC_PCU_BASIC_RATE_SET1_VALUE_MASK) - -#define MAC_PCU_BASIC_RATE_SET2_ADDRESS 0x00008330 -#define MAC_PCU_BASIC_RATE_SET2_OFFSET 0x00000330 -#define MAC_PCU_BASIC_RATE_SET2_VALUE_MSB 29 -#define MAC_PCU_BASIC_RATE_SET2_VALUE_LSB 0 -#define MAC_PCU_BASIC_RATE_SET2_VALUE_MASK 0x3fffffff -#define MAC_PCU_BASIC_RATE_SET2_VALUE_GET(x) (((x) & MAC_PCU_BASIC_RATE_SET2_VALUE_MASK) >> MAC_PCU_BASIC_RATE_SET2_VALUE_LSB) -#define MAC_PCU_BASIC_RATE_SET2_VALUE_SET(x) (((x) << MAC_PCU_BASIC_RATE_SET2_VALUE_LSB) & MAC_PCU_BASIC_RATE_SET2_VALUE_MASK) - -#define MAC_PCU_BASIC_RATE_SET3_ADDRESS 0x00008334 -#define MAC_PCU_BASIC_RATE_SET3_OFFSET 0x00000334 -#define MAC_PCU_BASIC_RATE_SET3_VALUE_MSB 24 -#define MAC_PCU_BASIC_RATE_SET3_VALUE_LSB 0 -#define MAC_PCU_BASIC_RATE_SET3_VALUE_MASK 0x01ffffff -#define MAC_PCU_BASIC_RATE_SET3_VALUE_GET(x) (((x) & MAC_PCU_BASIC_RATE_SET3_VALUE_MASK) >> MAC_PCU_BASIC_RATE_SET3_VALUE_LSB) -#define MAC_PCU_BASIC_RATE_SET3_VALUE_SET(x) (((x) << MAC_PCU_BASIC_RATE_SET3_VALUE_LSB) & MAC_PCU_BASIC_RATE_SET3_VALUE_MASK) - -#define MAC_PCU_RX_INT_STATUS0_ADDRESS 0x00008338 -#define MAC_PCU_RX_INT_STATUS0_OFFSET 0x00000338 -#define MAC_PCU_RX_INT_STATUS0_DURATION_H_MSB 31 -#define MAC_PCU_RX_INT_STATUS0_DURATION_H_LSB 24 -#define MAC_PCU_RX_INT_STATUS0_DURATION_H_MASK 0xff000000 -#define MAC_PCU_RX_INT_STATUS0_DURATION_H_GET(x) (((x) & MAC_PCU_RX_INT_STATUS0_DURATION_H_MASK) >> MAC_PCU_RX_INT_STATUS0_DURATION_H_LSB) -#define MAC_PCU_RX_INT_STATUS0_DURATION_H_SET(x) (((x) << MAC_PCU_RX_INT_STATUS0_DURATION_H_LSB) & MAC_PCU_RX_INT_STATUS0_DURATION_H_MASK) -#define MAC_PCU_RX_INT_STATUS0_DURATION_L_MSB 23 -#define MAC_PCU_RX_INT_STATUS0_DURATION_L_LSB 16 -#define MAC_PCU_RX_INT_STATUS0_DURATION_L_MASK 0x00ff0000 -#define MAC_PCU_RX_INT_STATUS0_DURATION_L_GET(x) (((x) & MAC_PCU_RX_INT_STATUS0_DURATION_L_MASK) >> MAC_PCU_RX_INT_STATUS0_DURATION_L_LSB) -#define MAC_PCU_RX_INT_STATUS0_DURATION_L_SET(x) (((x) << MAC_PCU_RX_INT_STATUS0_DURATION_L_LSB) & MAC_PCU_RX_INT_STATUS0_DURATION_L_MASK) -#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_MSB 15 -#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_LSB 8 -#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_MASK 0x0000ff00 -#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_GET(x) (((x) & MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_MASK) >> MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_LSB) -#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_SET(x) (((x) << MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_LSB) & MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_MASK) -#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_MSB 7 -#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_LSB 0 -#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_MASK 0x000000ff -#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_GET(x) (((x) & MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_MASK) >> MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_LSB) -#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_SET(x) (((x) << MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_LSB) & MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_MASK) - -#define MAC_PCU_RX_INT_STATUS1_ADDRESS 0x0000833c -#define MAC_PCU_RX_INT_STATUS1_OFFSET 0x0000033c -#define MAC_PCU_RX_INT_STATUS1_VALUE_MSB 17 -#define MAC_PCU_RX_INT_STATUS1_VALUE_LSB 0 -#define MAC_PCU_RX_INT_STATUS1_VALUE_MASK 0x0003ffff -#define MAC_PCU_RX_INT_STATUS1_VALUE_GET(x) (((x) & MAC_PCU_RX_INT_STATUS1_VALUE_MASK) >> MAC_PCU_RX_INT_STATUS1_VALUE_LSB) -#define MAC_PCU_RX_INT_STATUS1_VALUE_SET(x) (((x) << MAC_PCU_RX_INT_STATUS1_VALUE_LSB) & MAC_PCU_RX_INT_STATUS1_VALUE_MASK) - -#define MAC_PCU_RX_INT_STATUS2_ADDRESS 0x00008340 -#define MAC_PCU_RX_INT_STATUS2_OFFSET 0x00000340 -#define MAC_PCU_RX_INT_STATUS2_VALUE_MSB 26 -#define MAC_PCU_RX_INT_STATUS2_VALUE_LSB 0 -#define MAC_PCU_RX_INT_STATUS2_VALUE_MASK 0x07ffffff -#define MAC_PCU_RX_INT_STATUS2_VALUE_GET(x) (((x) & MAC_PCU_RX_INT_STATUS2_VALUE_MASK) >> MAC_PCU_RX_INT_STATUS2_VALUE_LSB) -#define MAC_PCU_RX_INT_STATUS2_VALUE_SET(x) (((x) << MAC_PCU_RX_INT_STATUS2_VALUE_LSB) & MAC_PCU_RX_INT_STATUS2_VALUE_MASK) - -#define MAC_PCU_RX_INT_STATUS3_ADDRESS 0x00008344 -#define MAC_PCU_RX_INT_STATUS3_OFFSET 0x00000344 -#define MAC_PCU_RX_INT_STATUS3_VALUE_MSB 23 -#define MAC_PCU_RX_INT_STATUS3_VALUE_LSB 0 -#define MAC_PCU_RX_INT_STATUS3_VALUE_MASK 0x00ffffff -#define MAC_PCU_RX_INT_STATUS3_VALUE_GET(x) (((x) & MAC_PCU_RX_INT_STATUS3_VALUE_MASK) >> MAC_PCU_RX_INT_STATUS3_VALUE_LSB) -#define MAC_PCU_RX_INT_STATUS3_VALUE_SET(x) (((x) << MAC_PCU_RX_INT_STATUS3_VALUE_LSB) & MAC_PCU_RX_INT_STATUS3_VALUE_MASK) - -#define HT_HALF_GI_RATE1_ADDRESS 0x00008348 -#define HT_HALF_GI_RATE1_OFFSET 0x00000348 -#define HT_HALF_GI_RATE1_MCS3_MSB 31 -#define HT_HALF_GI_RATE1_MCS3_LSB 24 -#define HT_HALF_GI_RATE1_MCS3_MASK 0xff000000 -#define HT_HALF_GI_RATE1_MCS3_GET(x) (((x) & HT_HALF_GI_RATE1_MCS3_MASK) >> HT_HALF_GI_RATE1_MCS3_LSB) -#define HT_HALF_GI_RATE1_MCS3_SET(x) (((x) << HT_HALF_GI_RATE1_MCS3_LSB) & HT_HALF_GI_RATE1_MCS3_MASK) -#define HT_HALF_GI_RATE1_MCS2_MSB 23 -#define HT_HALF_GI_RATE1_MCS2_LSB 16 -#define HT_HALF_GI_RATE1_MCS2_MASK 0x00ff0000 -#define HT_HALF_GI_RATE1_MCS2_GET(x) (((x) & HT_HALF_GI_RATE1_MCS2_MASK) >> HT_HALF_GI_RATE1_MCS2_LSB) -#define HT_HALF_GI_RATE1_MCS2_SET(x) (((x) << HT_HALF_GI_RATE1_MCS2_LSB) & HT_HALF_GI_RATE1_MCS2_MASK) -#define HT_HALF_GI_RATE1_MCS1_MSB 15 -#define HT_HALF_GI_RATE1_MCS1_LSB 8 -#define HT_HALF_GI_RATE1_MCS1_MASK 0x0000ff00 -#define HT_HALF_GI_RATE1_MCS1_GET(x) (((x) & HT_HALF_GI_RATE1_MCS1_MASK) >> HT_HALF_GI_RATE1_MCS1_LSB) -#define HT_HALF_GI_RATE1_MCS1_SET(x) (((x) << HT_HALF_GI_RATE1_MCS1_LSB) & HT_HALF_GI_RATE1_MCS1_MASK) -#define HT_HALF_GI_RATE1_MCS0_MSB 7 -#define HT_HALF_GI_RATE1_MCS0_LSB 0 -#define HT_HALF_GI_RATE1_MCS0_MASK 0x000000ff -#define HT_HALF_GI_RATE1_MCS0_GET(x) (((x) & HT_HALF_GI_RATE1_MCS0_MASK) >> HT_HALF_GI_RATE1_MCS0_LSB) -#define HT_HALF_GI_RATE1_MCS0_SET(x) (((x) << HT_HALF_GI_RATE1_MCS0_LSB) & HT_HALF_GI_RATE1_MCS0_MASK) - -#define HT_HALF_GI_RATE2_ADDRESS 0x0000834c -#define HT_HALF_GI_RATE2_OFFSET 0x0000034c -#define HT_HALF_GI_RATE2_MCS7_MSB 31 -#define HT_HALF_GI_RATE2_MCS7_LSB 24 -#define HT_HALF_GI_RATE2_MCS7_MASK 0xff000000 -#define HT_HALF_GI_RATE2_MCS7_GET(x) (((x) & HT_HALF_GI_RATE2_MCS7_MASK) >> HT_HALF_GI_RATE2_MCS7_LSB) -#define HT_HALF_GI_RATE2_MCS7_SET(x) (((x) << HT_HALF_GI_RATE2_MCS7_LSB) & HT_HALF_GI_RATE2_MCS7_MASK) -#define HT_HALF_GI_RATE2_MCS6_MSB 23 -#define HT_HALF_GI_RATE2_MCS6_LSB 16 -#define HT_HALF_GI_RATE2_MCS6_MASK 0x00ff0000 -#define HT_HALF_GI_RATE2_MCS6_GET(x) (((x) & HT_HALF_GI_RATE2_MCS6_MASK) >> HT_HALF_GI_RATE2_MCS6_LSB) -#define HT_HALF_GI_RATE2_MCS6_SET(x) (((x) << HT_HALF_GI_RATE2_MCS6_LSB) & HT_HALF_GI_RATE2_MCS6_MASK) -#define HT_HALF_GI_RATE2_MCS5_MSB 15 -#define HT_HALF_GI_RATE2_MCS5_LSB 8 -#define HT_HALF_GI_RATE2_MCS5_MASK 0x0000ff00 -#define HT_HALF_GI_RATE2_MCS5_GET(x) (((x) & HT_HALF_GI_RATE2_MCS5_MASK) >> HT_HALF_GI_RATE2_MCS5_LSB) -#define HT_HALF_GI_RATE2_MCS5_SET(x) (((x) << HT_HALF_GI_RATE2_MCS5_LSB) & HT_HALF_GI_RATE2_MCS5_MASK) -#define HT_HALF_GI_RATE2_MCS4_MSB 7 -#define HT_HALF_GI_RATE2_MCS4_LSB 0 -#define HT_HALF_GI_RATE2_MCS4_MASK 0x000000ff -#define HT_HALF_GI_RATE2_MCS4_GET(x) (((x) & HT_HALF_GI_RATE2_MCS4_MASK) >> HT_HALF_GI_RATE2_MCS4_LSB) -#define HT_HALF_GI_RATE2_MCS4_SET(x) (((x) << HT_HALF_GI_RATE2_MCS4_LSB) & HT_HALF_GI_RATE2_MCS4_MASK) - -#define HT_FULL_GI_RATE1_ADDRESS 0x00008350 -#define HT_FULL_GI_RATE1_OFFSET 0x00000350 -#define HT_FULL_GI_RATE1_MCS3_MSB 31 -#define HT_FULL_GI_RATE1_MCS3_LSB 24 -#define HT_FULL_GI_RATE1_MCS3_MASK 0xff000000 -#define HT_FULL_GI_RATE1_MCS3_GET(x) (((x) & HT_FULL_GI_RATE1_MCS3_MASK) >> HT_FULL_GI_RATE1_MCS3_LSB) -#define HT_FULL_GI_RATE1_MCS3_SET(x) (((x) << HT_FULL_GI_RATE1_MCS3_LSB) & HT_FULL_GI_RATE1_MCS3_MASK) -#define HT_FULL_GI_RATE1_MCS2_MSB 23 -#define HT_FULL_GI_RATE1_MCS2_LSB 16 -#define HT_FULL_GI_RATE1_MCS2_MASK 0x00ff0000 -#define HT_FULL_GI_RATE1_MCS2_GET(x) (((x) & HT_FULL_GI_RATE1_MCS2_MASK) >> HT_FULL_GI_RATE1_MCS2_LSB) -#define HT_FULL_GI_RATE1_MCS2_SET(x) (((x) << HT_FULL_GI_RATE1_MCS2_LSB) & HT_FULL_GI_RATE1_MCS2_MASK) -#define HT_FULL_GI_RATE1_MCS1_MSB 15 -#define HT_FULL_GI_RATE1_MCS1_LSB 8 -#define HT_FULL_GI_RATE1_MCS1_MASK 0x0000ff00 -#define HT_FULL_GI_RATE1_MCS1_GET(x) (((x) & HT_FULL_GI_RATE1_MCS1_MASK) >> HT_FULL_GI_RATE1_MCS1_LSB) -#define HT_FULL_GI_RATE1_MCS1_SET(x) (((x) << HT_FULL_GI_RATE1_MCS1_LSB) & HT_FULL_GI_RATE1_MCS1_MASK) -#define HT_FULL_GI_RATE1_MCS0_MSB 7 -#define HT_FULL_GI_RATE1_MCS0_LSB 0 -#define HT_FULL_GI_RATE1_MCS0_MASK 0x000000ff -#define HT_FULL_GI_RATE1_MCS0_GET(x) (((x) & HT_FULL_GI_RATE1_MCS0_MASK) >> HT_FULL_GI_RATE1_MCS0_LSB) -#define HT_FULL_GI_RATE1_MCS0_SET(x) (((x) << HT_FULL_GI_RATE1_MCS0_LSB) & HT_FULL_GI_RATE1_MCS0_MASK) - -#define HT_FULL_GI_RATE2_ADDRESS 0x00008354 -#define HT_FULL_GI_RATE2_OFFSET 0x00000354 -#define HT_FULL_GI_RATE2_MCS7_MSB 31 -#define HT_FULL_GI_RATE2_MCS7_LSB 24 -#define HT_FULL_GI_RATE2_MCS7_MASK 0xff000000 -#define HT_FULL_GI_RATE2_MCS7_GET(x) (((x) & HT_FULL_GI_RATE2_MCS7_MASK) >> HT_FULL_GI_RATE2_MCS7_LSB) -#define HT_FULL_GI_RATE2_MCS7_SET(x) (((x) << HT_FULL_GI_RATE2_MCS7_LSB) & HT_FULL_GI_RATE2_MCS7_MASK) -#define HT_FULL_GI_RATE2_MCS6_MSB 23 -#define HT_FULL_GI_RATE2_MCS6_LSB 16 -#define HT_FULL_GI_RATE2_MCS6_MASK 0x00ff0000 -#define HT_FULL_GI_RATE2_MCS6_GET(x) (((x) & HT_FULL_GI_RATE2_MCS6_MASK) >> HT_FULL_GI_RATE2_MCS6_LSB) -#define HT_FULL_GI_RATE2_MCS6_SET(x) (((x) << HT_FULL_GI_RATE2_MCS6_LSB) & HT_FULL_GI_RATE2_MCS6_MASK) -#define HT_FULL_GI_RATE2_MCS5_MSB 15 -#define HT_FULL_GI_RATE2_MCS5_LSB 8 -#define HT_FULL_GI_RATE2_MCS5_MASK 0x0000ff00 -#define HT_FULL_GI_RATE2_MCS5_GET(x) (((x) & HT_FULL_GI_RATE2_MCS5_MASK) >> HT_FULL_GI_RATE2_MCS5_LSB) -#define HT_FULL_GI_RATE2_MCS5_SET(x) (((x) << HT_FULL_GI_RATE2_MCS5_LSB) & HT_FULL_GI_RATE2_MCS5_MASK) -#define HT_FULL_GI_RATE2_MCS4_MSB 7 -#define HT_FULL_GI_RATE2_MCS4_LSB 0 -#define HT_FULL_GI_RATE2_MCS4_MASK 0x000000ff -#define HT_FULL_GI_RATE2_MCS4_GET(x) (((x) & HT_FULL_GI_RATE2_MCS4_MASK) >> HT_FULL_GI_RATE2_MCS4_LSB) -#define HT_FULL_GI_RATE2_MCS4_SET(x) (((x) << HT_FULL_GI_RATE2_MCS4_LSB) & HT_FULL_GI_RATE2_MCS4_MASK) - -#define LEGACY_RATE1_ADDRESS 0x00008358 -#define LEGACY_RATE1_OFFSET 0x00000358 -#define LEGACY_RATE1_RATE12_MSB 29 -#define LEGACY_RATE1_RATE12_LSB 24 -#define LEGACY_RATE1_RATE12_MASK 0x3f000000 -#define LEGACY_RATE1_RATE12_GET(x) (((x) & LEGACY_RATE1_RATE12_MASK) >> LEGACY_RATE1_RATE12_LSB) -#define LEGACY_RATE1_RATE12_SET(x) (((x) << LEGACY_RATE1_RATE12_LSB) & LEGACY_RATE1_RATE12_MASK) -#define LEGACY_RATE1_RATE11_MSB 23 -#define LEGACY_RATE1_RATE11_LSB 18 -#define LEGACY_RATE1_RATE11_MASK 0x00fc0000 -#define LEGACY_RATE1_RATE11_GET(x) (((x) & LEGACY_RATE1_RATE11_MASK) >> LEGACY_RATE1_RATE11_LSB) -#define LEGACY_RATE1_RATE11_SET(x) (((x) << LEGACY_RATE1_RATE11_LSB) & LEGACY_RATE1_RATE11_MASK) -#define LEGACY_RATE1_RATE10_MSB 17 -#define LEGACY_RATE1_RATE10_LSB 12 -#define LEGACY_RATE1_RATE10_MASK 0x0003f000 -#define LEGACY_RATE1_RATE10_GET(x) (((x) & LEGACY_RATE1_RATE10_MASK) >> LEGACY_RATE1_RATE10_LSB) -#define LEGACY_RATE1_RATE10_SET(x) (((x) << LEGACY_RATE1_RATE10_LSB) & LEGACY_RATE1_RATE10_MASK) -#define LEGACY_RATE1_RATE9_MSB 11 -#define LEGACY_RATE1_RATE9_LSB 6 -#define LEGACY_RATE1_RATE9_MASK 0x00000fc0 -#define LEGACY_RATE1_RATE9_GET(x) (((x) & LEGACY_RATE1_RATE9_MASK) >> LEGACY_RATE1_RATE9_LSB) -#define LEGACY_RATE1_RATE9_SET(x) (((x) << LEGACY_RATE1_RATE9_LSB) & LEGACY_RATE1_RATE9_MASK) -#define LEGACY_RATE1_RATE8_MSB 5 -#define LEGACY_RATE1_RATE8_LSB 0 -#define LEGACY_RATE1_RATE8_MASK 0x0000003f -#define LEGACY_RATE1_RATE8_GET(x) (((x) & LEGACY_RATE1_RATE8_MASK) >> LEGACY_RATE1_RATE8_LSB) -#define LEGACY_RATE1_RATE8_SET(x) (((x) << LEGACY_RATE1_RATE8_LSB) & LEGACY_RATE1_RATE8_MASK) - -#define LEGACY_RATE2_ADDRESS 0x0000835c -#define LEGACY_RATE2_OFFSET 0x0000035c -#define LEGACY_RATE2_RATE25_MSB 29 -#define LEGACY_RATE2_RATE25_LSB 24 -#define LEGACY_RATE2_RATE25_MASK 0x3f000000 -#define LEGACY_RATE2_RATE25_GET(x) (((x) & LEGACY_RATE2_RATE25_MASK) >> LEGACY_RATE2_RATE25_LSB) -#define LEGACY_RATE2_RATE25_SET(x) (((x) << LEGACY_RATE2_RATE25_LSB) & LEGACY_RATE2_RATE25_MASK) -#define LEGACY_RATE2_RATE24_MSB 23 -#define LEGACY_RATE2_RATE24_LSB 18 -#define LEGACY_RATE2_RATE24_MASK 0x00fc0000 -#define LEGACY_RATE2_RATE24_GET(x) (((x) & LEGACY_RATE2_RATE24_MASK) >> LEGACY_RATE2_RATE24_LSB) -#define LEGACY_RATE2_RATE24_SET(x) (((x) << LEGACY_RATE2_RATE24_LSB) & LEGACY_RATE2_RATE24_MASK) -#define LEGACY_RATE2_RATE15_MSB 17 -#define LEGACY_RATE2_RATE15_LSB 12 -#define LEGACY_RATE2_RATE15_MASK 0x0003f000 -#define LEGACY_RATE2_RATE15_GET(x) (((x) & LEGACY_RATE2_RATE15_MASK) >> LEGACY_RATE2_RATE15_LSB) -#define LEGACY_RATE2_RATE15_SET(x) (((x) << LEGACY_RATE2_RATE15_LSB) & LEGACY_RATE2_RATE15_MASK) -#define LEGACY_RATE2_RATE14_MSB 11 -#define LEGACY_RATE2_RATE14_LSB 6 -#define LEGACY_RATE2_RATE14_MASK 0x00000fc0 -#define LEGACY_RATE2_RATE14_GET(x) (((x) & LEGACY_RATE2_RATE14_MASK) >> LEGACY_RATE2_RATE14_LSB) -#define LEGACY_RATE2_RATE14_SET(x) (((x) << LEGACY_RATE2_RATE14_LSB) & LEGACY_RATE2_RATE14_MASK) -#define LEGACY_RATE2_RATE13_MSB 5 -#define LEGACY_RATE2_RATE13_LSB 0 -#define LEGACY_RATE2_RATE13_MASK 0x0000003f -#define LEGACY_RATE2_RATE13_GET(x) (((x) & LEGACY_RATE2_RATE13_MASK) >> LEGACY_RATE2_RATE13_LSB) -#define LEGACY_RATE2_RATE13_SET(x) (((x) << LEGACY_RATE2_RATE13_LSB) & LEGACY_RATE2_RATE13_MASK) - -#define LEGACY_RATE3_ADDRESS 0x00008360 -#define LEGACY_RATE3_OFFSET 0x00000360 -#define LEGACY_RATE3_RATE30_MSB 29 -#define LEGACY_RATE3_RATE30_LSB 24 -#define LEGACY_RATE3_RATE30_MASK 0x3f000000 -#define LEGACY_RATE3_RATE30_GET(x) (((x) & LEGACY_RATE3_RATE30_MASK) >> LEGACY_RATE3_RATE30_LSB) -#define LEGACY_RATE3_RATE30_SET(x) (((x) << LEGACY_RATE3_RATE30_LSB) & LEGACY_RATE3_RATE30_MASK) -#define LEGACY_RATE3_RATE29_MSB 23 -#define LEGACY_RATE3_RATE29_LSB 18 -#define LEGACY_RATE3_RATE29_MASK 0x00fc0000 -#define LEGACY_RATE3_RATE29_GET(x) (((x) & LEGACY_RATE3_RATE29_MASK) >> LEGACY_RATE3_RATE29_LSB) -#define LEGACY_RATE3_RATE29_SET(x) (((x) << LEGACY_RATE3_RATE29_LSB) & LEGACY_RATE3_RATE29_MASK) -#define LEGACY_RATE3_RATE28_MSB 17 -#define LEGACY_RATE3_RATE28_LSB 12 -#define LEGACY_RATE3_RATE28_MASK 0x0003f000 -#define LEGACY_RATE3_RATE28_GET(x) (((x) & LEGACY_RATE3_RATE28_MASK) >> LEGACY_RATE3_RATE28_LSB) -#define LEGACY_RATE3_RATE28_SET(x) (((x) << LEGACY_RATE3_RATE28_LSB) & LEGACY_RATE3_RATE28_MASK) -#define LEGACY_RATE3_RATE27_MSB 11 -#define LEGACY_RATE3_RATE27_LSB 6 -#define LEGACY_RATE3_RATE27_MASK 0x00000fc0 -#define LEGACY_RATE3_RATE27_GET(x) (((x) & LEGACY_RATE3_RATE27_MASK) >> LEGACY_RATE3_RATE27_LSB) -#define LEGACY_RATE3_RATE27_SET(x) (((x) << LEGACY_RATE3_RATE27_LSB) & LEGACY_RATE3_RATE27_MASK) -#define LEGACY_RATE3_RATE26_MSB 5 -#define LEGACY_RATE3_RATE26_LSB 0 -#define LEGACY_RATE3_RATE26_MASK 0x0000003f -#define LEGACY_RATE3_RATE26_GET(x) (((x) & LEGACY_RATE3_RATE26_MASK) >> LEGACY_RATE3_RATE26_LSB) -#define LEGACY_RATE3_RATE26_SET(x) (((x) << LEGACY_RATE3_RATE26_LSB) & LEGACY_RATE3_RATE26_MASK) - -#define RX_INT_FILTER_ADDRESS 0x00008364 -#define RX_INT_FILTER_OFFSET 0x00000364 -#define RX_INT_FILTER_BEACON_MSB 17 -#define RX_INT_FILTER_BEACON_LSB 17 -#define RX_INT_FILTER_BEACON_MASK 0x00020000 -#define RX_INT_FILTER_BEACON_GET(x) (((x) & RX_INT_FILTER_BEACON_MASK) >> RX_INT_FILTER_BEACON_LSB) -#define RX_INT_FILTER_BEACON_SET(x) (((x) << RX_INT_FILTER_BEACON_LSB) & RX_INT_FILTER_BEACON_MASK) -#define RX_INT_FILTER_AMPDU_MSB 16 -#define RX_INT_FILTER_AMPDU_LSB 16 -#define RX_INT_FILTER_AMPDU_MASK 0x00010000 -#define RX_INT_FILTER_AMPDU_GET(x) (((x) & RX_INT_FILTER_AMPDU_MASK) >> RX_INT_FILTER_AMPDU_LSB) -#define RX_INT_FILTER_AMPDU_SET(x) (((x) << RX_INT_FILTER_AMPDU_LSB) & RX_INT_FILTER_AMPDU_MASK) -#define RX_INT_FILTER_EOSP_MSB 15 -#define RX_INT_FILTER_EOSP_LSB 15 -#define RX_INT_FILTER_EOSP_MASK 0x00008000 -#define RX_INT_FILTER_EOSP_GET(x) (((x) & RX_INT_FILTER_EOSP_MASK) >> RX_INT_FILTER_EOSP_LSB) -#define RX_INT_FILTER_EOSP_SET(x) (((x) << RX_INT_FILTER_EOSP_LSB) & RX_INT_FILTER_EOSP_MASK) -#define RX_INT_FILTER_LENGTH_LOW_MSB 14 -#define RX_INT_FILTER_LENGTH_LOW_LSB 14 -#define RX_INT_FILTER_LENGTH_LOW_MASK 0x00004000 -#define RX_INT_FILTER_LENGTH_LOW_GET(x) (((x) & RX_INT_FILTER_LENGTH_LOW_MASK) >> RX_INT_FILTER_LENGTH_LOW_LSB) -#define RX_INT_FILTER_LENGTH_LOW_SET(x) (((x) << RX_INT_FILTER_LENGTH_LOW_LSB) & RX_INT_FILTER_LENGTH_LOW_MASK) -#define RX_INT_FILTER_LENGTH_HIGH_MSB 13 -#define RX_INT_FILTER_LENGTH_HIGH_LSB 13 -#define RX_INT_FILTER_LENGTH_HIGH_MASK 0x00002000 -#define RX_INT_FILTER_LENGTH_HIGH_GET(x) (((x) & RX_INT_FILTER_LENGTH_HIGH_MASK) >> RX_INT_FILTER_LENGTH_HIGH_LSB) -#define RX_INT_FILTER_LENGTH_HIGH_SET(x) (((x) << RX_INT_FILTER_LENGTH_HIGH_LSB) & RX_INT_FILTER_LENGTH_HIGH_MASK) -#define RX_INT_FILTER_RSSI_MSB 12 -#define RX_INT_FILTER_RSSI_LSB 12 -#define RX_INT_FILTER_RSSI_MASK 0x00001000 -#define RX_INT_FILTER_RSSI_GET(x) (((x) & RX_INT_FILTER_RSSI_MASK) >> RX_INT_FILTER_RSSI_LSB) -#define RX_INT_FILTER_RSSI_SET(x) (((x) << RX_INT_FILTER_RSSI_LSB) & RX_INT_FILTER_RSSI_MASK) -#define RX_INT_FILTER_RATE_LOW_MSB 11 -#define RX_INT_FILTER_RATE_LOW_LSB 11 -#define RX_INT_FILTER_RATE_LOW_MASK 0x00000800 -#define RX_INT_FILTER_RATE_LOW_GET(x) (((x) & RX_INT_FILTER_RATE_LOW_MASK) >> RX_INT_FILTER_RATE_LOW_LSB) -#define RX_INT_FILTER_RATE_LOW_SET(x) (((x) << RX_INT_FILTER_RATE_LOW_LSB) & RX_INT_FILTER_RATE_LOW_MASK) -#define RX_INT_FILTER_RATE_HIGH_MSB 10 -#define RX_INT_FILTER_RATE_HIGH_LSB 10 -#define RX_INT_FILTER_RATE_HIGH_MASK 0x00000400 -#define RX_INT_FILTER_RATE_HIGH_GET(x) (((x) & RX_INT_FILTER_RATE_HIGH_MASK) >> RX_INT_FILTER_RATE_HIGH_LSB) -#define RX_INT_FILTER_RATE_HIGH_SET(x) (((x) << RX_INT_FILTER_RATE_HIGH_LSB) & RX_INT_FILTER_RATE_HIGH_MASK) -#define RX_INT_FILTER_MORE_FRAG_MSB 9 -#define RX_INT_FILTER_MORE_FRAG_LSB 9 -#define RX_INT_FILTER_MORE_FRAG_MASK 0x00000200 -#define RX_INT_FILTER_MORE_FRAG_GET(x) (((x) & RX_INT_FILTER_MORE_FRAG_MASK) >> RX_INT_FILTER_MORE_FRAG_LSB) -#define RX_INT_FILTER_MORE_FRAG_SET(x) (((x) << RX_INT_FILTER_MORE_FRAG_LSB) & RX_INT_FILTER_MORE_FRAG_MASK) -#define RX_INT_FILTER_MORE_DATA_MSB 8 -#define RX_INT_FILTER_MORE_DATA_LSB 8 -#define RX_INT_FILTER_MORE_DATA_MASK 0x00000100 -#define RX_INT_FILTER_MORE_DATA_GET(x) (((x) & RX_INT_FILTER_MORE_DATA_MASK) >> RX_INT_FILTER_MORE_DATA_LSB) -#define RX_INT_FILTER_MORE_DATA_SET(x) (((x) << RX_INT_FILTER_MORE_DATA_LSB) & RX_INT_FILTER_MORE_DATA_MASK) -#define RX_INT_FILTER_RETRY_MSB 7 -#define RX_INT_FILTER_RETRY_LSB 7 -#define RX_INT_FILTER_RETRY_MASK 0x00000080 -#define RX_INT_FILTER_RETRY_GET(x) (((x) & RX_INT_FILTER_RETRY_MASK) >> RX_INT_FILTER_RETRY_LSB) -#define RX_INT_FILTER_RETRY_SET(x) (((x) << RX_INT_FILTER_RETRY_LSB) & RX_INT_FILTER_RETRY_MASK) -#define RX_INT_FILTER_CTS_MSB 6 -#define RX_INT_FILTER_CTS_LSB 6 -#define RX_INT_FILTER_CTS_MASK 0x00000040 -#define RX_INT_FILTER_CTS_GET(x) (((x) & RX_INT_FILTER_CTS_MASK) >> RX_INT_FILTER_CTS_LSB) -#define RX_INT_FILTER_CTS_SET(x) (((x) << RX_INT_FILTER_CTS_LSB) & RX_INT_FILTER_CTS_MASK) -#define RX_INT_FILTER_ACK_MSB 5 -#define RX_INT_FILTER_ACK_LSB 5 -#define RX_INT_FILTER_ACK_MASK 0x00000020 -#define RX_INT_FILTER_ACK_GET(x) (((x) & RX_INT_FILTER_ACK_MASK) >> RX_INT_FILTER_ACK_LSB) -#define RX_INT_FILTER_ACK_SET(x) (((x) << RX_INT_FILTER_ACK_LSB) & RX_INT_FILTER_ACK_MASK) -#define RX_INT_FILTER_RTS_MSB 4 -#define RX_INT_FILTER_RTS_LSB 4 -#define RX_INT_FILTER_RTS_MASK 0x00000010 -#define RX_INT_FILTER_RTS_GET(x) (((x) & RX_INT_FILTER_RTS_MASK) >> RX_INT_FILTER_RTS_LSB) -#define RX_INT_FILTER_RTS_SET(x) (((x) << RX_INT_FILTER_RTS_LSB) & RX_INT_FILTER_RTS_MASK) -#define RX_INT_FILTER_MCAST_MSB 3 -#define RX_INT_FILTER_MCAST_LSB 3 -#define RX_INT_FILTER_MCAST_MASK 0x00000008 -#define RX_INT_FILTER_MCAST_GET(x) (((x) & RX_INT_FILTER_MCAST_MASK) >> RX_INT_FILTER_MCAST_LSB) -#define RX_INT_FILTER_MCAST_SET(x) (((x) << RX_INT_FILTER_MCAST_LSB) & RX_INT_FILTER_MCAST_MASK) -#define RX_INT_FILTER_BCAST_MSB 2 -#define RX_INT_FILTER_BCAST_LSB 2 -#define RX_INT_FILTER_BCAST_MASK 0x00000004 -#define RX_INT_FILTER_BCAST_GET(x) (((x) & RX_INT_FILTER_BCAST_MASK) >> RX_INT_FILTER_BCAST_LSB) -#define RX_INT_FILTER_BCAST_SET(x) (((x) << RX_INT_FILTER_BCAST_LSB) & RX_INT_FILTER_BCAST_MASK) -#define RX_INT_FILTER_DIRECTED_MSB 1 -#define RX_INT_FILTER_DIRECTED_LSB 1 -#define RX_INT_FILTER_DIRECTED_MASK 0x00000002 -#define RX_INT_FILTER_DIRECTED_GET(x) (((x) & RX_INT_FILTER_DIRECTED_MASK) >> RX_INT_FILTER_DIRECTED_LSB) -#define RX_INT_FILTER_DIRECTED_SET(x) (((x) << RX_INT_FILTER_DIRECTED_LSB) & RX_INT_FILTER_DIRECTED_MASK) -#define RX_INT_FILTER_ENABLE_MSB 0 -#define RX_INT_FILTER_ENABLE_LSB 0 -#define RX_INT_FILTER_ENABLE_MASK 0x00000001 -#define RX_INT_FILTER_ENABLE_GET(x) (((x) & RX_INT_FILTER_ENABLE_MASK) >> RX_INT_FILTER_ENABLE_LSB) -#define RX_INT_FILTER_ENABLE_SET(x) (((x) << RX_INT_FILTER_ENABLE_LSB) & RX_INT_FILTER_ENABLE_MASK) - -#define RX_INT_OVERFLOW_ADDRESS 0x00008368 -#define RX_INT_OVERFLOW_OFFSET 0x00000368 -#define RX_INT_OVERFLOW_STATUS_MSB 0 -#define RX_INT_OVERFLOW_STATUS_LSB 0 -#define RX_INT_OVERFLOW_STATUS_MASK 0x00000001 -#define RX_INT_OVERFLOW_STATUS_GET(x) (((x) & RX_INT_OVERFLOW_STATUS_MASK) >> RX_INT_OVERFLOW_STATUS_LSB) -#define RX_INT_OVERFLOW_STATUS_SET(x) (((x) << RX_INT_OVERFLOW_STATUS_LSB) & RX_INT_OVERFLOW_STATUS_MASK) - -#define RX_FILTER_THRESH_ADDRESS 0x0000836c -#define RX_FILTER_THRESH_OFFSET 0x0000036c -#define RX_FILTER_THRESH_RSSI_LOW_MSB 23 -#define RX_FILTER_THRESH_RSSI_LOW_LSB 16 -#define RX_FILTER_THRESH_RSSI_LOW_MASK 0x00ff0000 -#define RX_FILTER_THRESH_RSSI_LOW_GET(x) (((x) & RX_FILTER_THRESH_RSSI_LOW_MASK) >> RX_FILTER_THRESH_RSSI_LOW_LSB) -#define RX_FILTER_THRESH_RSSI_LOW_SET(x) (((x) << RX_FILTER_THRESH_RSSI_LOW_LSB) & RX_FILTER_THRESH_RSSI_LOW_MASK) -#define RX_FILTER_THRESH_RATE_LOW_MSB 15 -#define RX_FILTER_THRESH_RATE_LOW_LSB 8 -#define RX_FILTER_THRESH_RATE_LOW_MASK 0x0000ff00 -#define RX_FILTER_THRESH_RATE_LOW_GET(x) (((x) & RX_FILTER_THRESH_RATE_LOW_MASK) >> RX_FILTER_THRESH_RATE_LOW_LSB) -#define RX_FILTER_THRESH_RATE_LOW_SET(x) (((x) << RX_FILTER_THRESH_RATE_LOW_LSB) & RX_FILTER_THRESH_RATE_LOW_MASK) -#define RX_FILTER_THRESH_RATE_HIGH_MSB 7 -#define RX_FILTER_THRESH_RATE_HIGH_LSB 0 -#define RX_FILTER_THRESH_RATE_HIGH_MASK 0x000000ff -#define RX_FILTER_THRESH_RATE_HIGH_GET(x) (((x) & RX_FILTER_THRESH_RATE_HIGH_MASK) >> RX_FILTER_THRESH_RATE_HIGH_LSB) -#define RX_FILTER_THRESH_RATE_HIGH_SET(x) (((x) << RX_FILTER_THRESH_RATE_HIGH_LSB) & RX_FILTER_THRESH_RATE_HIGH_MASK) - -#define RX_FILTER_THRESH1_ADDRESS 0x00008370 -#define RX_FILTER_THRESH1_OFFSET 0x00000370 -#define RX_FILTER_THRESH1_LENGTH_LOW_MSB 23 -#define RX_FILTER_THRESH1_LENGTH_LOW_LSB 12 -#define RX_FILTER_THRESH1_LENGTH_LOW_MASK 0x00fff000 -#define RX_FILTER_THRESH1_LENGTH_LOW_GET(x) (((x) & RX_FILTER_THRESH1_LENGTH_LOW_MASK) >> RX_FILTER_THRESH1_LENGTH_LOW_LSB) -#define RX_FILTER_THRESH1_LENGTH_LOW_SET(x) (((x) << RX_FILTER_THRESH1_LENGTH_LOW_LSB) & RX_FILTER_THRESH1_LENGTH_LOW_MASK) -#define RX_FILTER_THRESH1_LENGTH_HIGH_MSB 11 -#define RX_FILTER_THRESH1_LENGTH_HIGH_LSB 0 -#define RX_FILTER_THRESH1_LENGTH_HIGH_MASK 0x00000fff -#define RX_FILTER_THRESH1_LENGTH_HIGH_GET(x) (((x) & RX_FILTER_THRESH1_LENGTH_HIGH_MASK) >> RX_FILTER_THRESH1_LENGTH_HIGH_LSB) -#define RX_FILTER_THRESH1_LENGTH_HIGH_SET(x) (((x) << RX_FILTER_THRESH1_LENGTH_HIGH_LSB) & RX_FILTER_THRESH1_LENGTH_HIGH_MASK) - -#define RX_PRIORITY_THRESH0_ADDRESS 0x00008374 -#define RX_PRIORITY_THRESH0_OFFSET 0x00000374 -#define RX_PRIORITY_THRESH0_RSSI_LOW_MSB 31 -#define RX_PRIORITY_THRESH0_RSSI_LOW_LSB 24 -#define RX_PRIORITY_THRESH0_RSSI_LOW_MASK 0xff000000 -#define RX_PRIORITY_THRESH0_RSSI_LOW_GET(x) (((x) & RX_PRIORITY_THRESH0_RSSI_LOW_MASK) >> RX_PRIORITY_THRESH0_RSSI_LOW_LSB) -#define RX_PRIORITY_THRESH0_RSSI_LOW_SET(x) (((x) << RX_PRIORITY_THRESH0_RSSI_LOW_LSB) & RX_PRIORITY_THRESH0_RSSI_LOW_MASK) -#define RX_PRIORITY_THRESH0_RSSI_HIGH_MSB 23 -#define RX_PRIORITY_THRESH0_RSSI_HIGH_LSB 16 -#define RX_PRIORITY_THRESH0_RSSI_HIGH_MASK 0x00ff0000 -#define RX_PRIORITY_THRESH0_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH0_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH0_RSSI_HIGH_LSB) -#define RX_PRIORITY_THRESH0_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH0_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH0_RSSI_HIGH_MASK) -#define RX_PRIORITY_THRESH0_RATE_LOW_MSB 15 -#define RX_PRIORITY_THRESH0_RATE_LOW_LSB 8 -#define RX_PRIORITY_THRESH0_RATE_LOW_MASK 0x0000ff00 -#define RX_PRIORITY_THRESH0_RATE_LOW_GET(x) (((x) & RX_PRIORITY_THRESH0_RATE_LOW_MASK) >> RX_PRIORITY_THRESH0_RATE_LOW_LSB) -#define RX_PRIORITY_THRESH0_RATE_LOW_SET(x) (((x) << RX_PRIORITY_THRESH0_RATE_LOW_LSB) & RX_PRIORITY_THRESH0_RATE_LOW_MASK) -#define RX_PRIORITY_THRESH0_RATE_HIGH_MSB 7 -#define RX_PRIORITY_THRESH0_RATE_HIGH_LSB 0 -#define RX_PRIORITY_THRESH0_RATE_HIGH_MASK 0x000000ff -#define RX_PRIORITY_THRESH0_RATE_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH0_RATE_HIGH_MASK) >> RX_PRIORITY_THRESH0_RATE_HIGH_LSB) -#define RX_PRIORITY_THRESH0_RATE_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH0_RATE_HIGH_LSB) & RX_PRIORITY_THRESH0_RATE_HIGH_MASK) - -#define RX_PRIORITY_THRESH1_ADDRESS 0x00008378 -#define RX_PRIORITY_THRESH1_OFFSET 0x00000378 -#define RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_MSB 31 -#define RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_LSB 24 -#define RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_MASK 0xff000000 -#define RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_LSB) -#define RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_MASK) -#define RX_PRIORITY_THRESH1_LENGTH_LOW_MSB 23 -#define RX_PRIORITY_THRESH1_LENGTH_LOW_LSB 12 -#define RX_PRIORITY_THRESH1_LENGTH_LOW_MASK 0x00fff000 -#define RX_PRIORITY_THRESH1_LENGTH_LOW_GET(x) (((x) & RX_PRIORITY_THRESH1_LENGTH_LOW_MASK) >> RX_PRIORITY_THRESH1_LENGTH_LOW_LSB) -#define RX_PRIORITY_THRESH1_LENGTH_LOW_SET(x) (((x) << RX_PRIORITY_THRESH1_LENGTH_LOW_LSB) & RX_PRIORITY_THRESH1_LENGTH_LOW_MASK) -#define RX_PRIORITY_THRESH1_LENGTH_HIGH_MSB 11 -#define RX_PRIORITY_THRESH1_LENGTH_HIGH_LSB 0 -#define RX_PRIORITY_THRESH1_LENGTH_HIGH_MASK 0x00000fff -#define RX_PRIORITY_THRESH1_LENGTH_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH1_LENGTH_HIGH_MASK) >> RX_PRIORITY_THRESH1_LENGTH_HIGH_LSB) -#define RX_PRIORITY_THRESH1_LENGTH_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH1_LENGTH_HIGH_LSB) & RX_PRIORITY_THRESH1_LENGTH_HIGH_MASK) - -#define RX_PRIORITY_THRESH2_ADDRESS 0x0000837c -#define RX_PRIORITY_THRESH2_OFFSET 0x0000037c -#define RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_MSB 31 -#define RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_LSB 24 -#define RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_MASK 0xff000000 -#define RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_LSB) -#define RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_MASK) -#define RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_MSB 23 -#define RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_LSB 16 -#define RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_MASK 0x00ff0000 -#define RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_LSB) -#define RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_MASK) -#define RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_MSB 15 -#define RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_LSB 8 -#define RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_MASK 0x0000ff00 -#define RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_LSB) -#define RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_MASK) -#define RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_MSB 7 -#define RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_LSB 0 -#define RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_MASK 0x000000ff -#define RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_LSB) -#define RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_MASK) - -#define RX_PRIORITY_THRESH3_ADDRESS 0x00008380 -#define RX_PRIORITY_THRESH3_OFFSET 0x00000380 -#define RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_MSB 15 -#define RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_LSB 8 -#define RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_MASK 0x0000ff00 -#define RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_LSB) -#define RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_MASK) -#define RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_MSB 7 -#define RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_LSB 0 -#define RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_MASK 0x000000ff -#define RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_LSB) -#define RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_MASK) - -#define RX_PRIORITY_OFFSET0_ADDRESS 0x00008384 -#define RX_PRIORITY_OFFSET0_OFFSET 0x00000384 -#define RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_MSB 29 -#define RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_LSB 24 -#define RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_MASK 0x3f000000 -#define RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_LSB) -#define RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_MASK) -#define RX_PRIORITY_OFFSET0_RSSI_LOW_MSB 23 -#define RX_PRIORITY_OFFSET0_RSSI_LOW_LSB 18 -#define RX_PRIORITY_OFFSET0_RSSI_LOW_MASK 0x00fc0000 -#define RX_PRIORITY_OFFSET0_RSSI_LOW_GET(x) (((x) & RX_PRIORITY_OFFSET0_RSSI_LOW_MASK) >> RX_PRIORITY_OFFSET0_RSSI_LOW_LSB) -#define RX_PRIORITY_OFFSET0_RSSI_LOW_SET(x) (((x) << RX_PRIORITY_OFFSET0_RSSI_LOW_LSB) & RX_PRIORITY_OFFSET0_RSSI_LOW_MASK) -#define RX_PRIORITY_OFFSET0_RSSI_HIGH_MSB 17 -#define RX_PRIORITY_OFFSET0_RSSI_HIGH_LSB 12 -#define RX_PRIORITY_OFFSET0_RSSI_HIGH_MASK 0x0003f000 -#define RX_PRIORITY_OFFSET0_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET0_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET0_RSSI_HIGH_LSB) -#define RX_PRIORITY_OFFSET0_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET0_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET0_RSSI_HIGH_MASK) -#define RX_PRIORITY_OFFSET0_PHY_RATE_LOW_MSB 11 -#define RX_PRIORITY_OFFSET0_PHY_RATE_LOW_LSB 6 -#define RX_PRIORITY_OFFSET0_PHY_RATE_LOW_MASK 0x00000fc0 -#define RX_PRIORITY_OFFSET0_PHY_RATE_LOW_GET(x) (((x) & RX_PRIORITY_OFFSET0_PHY_RATE_LOW_MASK) >> RX_PRIORITY_OFFSET0_PHY_RATE_LOW_LSB) -#define RX_PRIORITY_OFFSET0_PHY_RATE_LOW_SET(x) (((x) << RX_PRIORITY_OFFSET0_PHY_RATE_LOW_LSB) & RX_PRIORITY_OFFSET0_PHY_RATE_LOW_MASK) -#define RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_MSB 5 -#define RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_LSB 0 -#define RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_MASK 0x0000003f -#define RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_MASK) >> RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_LSB) -#define RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_LSB) & RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_MASK) - -#define RX_PRIORITY_OFFSET1_ADDRESS 0x00008388 -#define RX_PRIORITY_OFFSET1_OFFSET 0x00000388 -#define RX_PRIORITY_OFFSET1_RTS_MSB 29 -#define RX_PRIORITY_OFFSET1_RTS_LSB 24 -#define RX_PRIORITY_OFFSET1_RTS_MASK 0x3f000000 -#define RX_PRIORITY_OFFSET1_RTS_GET(x) (((x) & RX_PRIORITY_OFFSET1_RTS_MASK) >> RX_PRIORITY_OFFSET1_RTS_LSB) -#define RX_PRIORITY_OFFSET1_RTS_SET(x) (((x) << RX_PRIORITY_OFFSET1_RTS_LSB) & RX_PRIORITY_OFFSET1_RTS_MASK) -#define RX_PRIORITY_OFFSET1_RETX_MSB 23 -#define RX_PRIORITY_OFFSET1_RETX_LSB 18 -#define RX_PRIORITY_OFFSET1_RETX_MASK 0x00fc0000 -#define RX_PRIORITY_OFFSET1_RETX_GET(x) (((x) & RX_PRIORITY_OFFSET1_RETX_MASK) >> RX_PRIORITY_OFFSET1_RETX_LSB) -#define RX_PRIORITY_OFFSET1_RETX_SET(x) (((x) << RX_PRIORITY_OFFSET1_RETX_LSB) & RX_PRIORITY_OFFSET1_RETX_MASK) -#define RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_MSB 17 -#define RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_LSB 12 -#define RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_MASK 0x0003f000 -#define RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_LSB) -#define RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_MASK) -#define RX_PRIORITY_OFFSET1_LENGTH_LOW_MSB 11 -#define RX_PRIORITY_OFFSET1_LENGTH_LOW_LSB 6 -#define RX_PRIORITY_OFFSET1_LENGTH_LOW_MASK 0x00000fc0 -#define RX_PRIORITY_OFFSET1_LENGTH_LOW_GET(x) (((x) & RX_PRIORITY_OFFSET1_LENGTH_LOW_MASK) >> RX_PRIORITY_OFFSET1_LENGTH_LOW_LSB) -#define RX_PRIORITY_OFFSET1_LENGTH_LOW_SET(x) (((x) << RX_PRIORITY_OFFSET1_LENGTH_LOW_LSB) & RX_PRIORITY_OFFSET1_LENGTH_LOW_MASK) -#define RX_PRIORITY_OFFSET1_LENGTH_HIGH_MSB 5 -#define RX_PRIORITY_OFFSET1_LENGTH_HIGH_LSB 0 -#define RX_PRIORITY_OFFSET1_LENGTH_HIGH_MASK 0x0000003f -#define RX_PRIORITY_OFFSET1_LENGTH_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET1_LENGTH_HIGH_MASK) >> RX_PRIORITY_OFFSET1_LENGTH_HIGH_LSB) -#define RX_PRIORITY_OFFSET1_LENGTH_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET1_LENGTH_HIGH_LSB) & RX_PRIORITY_OFFSET1_LENGTH_HIGH_MASK) - -#define RX_PRIORITY_OFFSET2_ADDRESS 0x0000838c -#define RX_PRIORITY_OFFSET2_OFFSET 0x0000038c -#define RX_PRIORITY_OFFSET2_BEACON_MSB 29 -#define RX_PRIORITY_OFFSET2_BEACON_LSB 24 -#define RX_PRIORITY_OFFSET2_BEACON_MASK 0x3f000000 -#define RX_PRIORITY_OFFSET2_BEACON_GET(x) (((x) & RX_PRIORITY_OFFSET2_BEACON_MASK) >> RX_PRIORITY_OFFSET2_BEACON_LSB) -#define RX_PRIORITY_OFFSET2_BEACON_SET(x) (((x) << RX_PRIORITY_OFFSET2_BEACON_LSB) & RX_PRIORITY_OFFSET2_BEACON_MASK) -#define RX_PRIORITY_OFFSET2_MGMT_MSB 23 -#define RX_PRIORITY_OFFSET2_MGMT_LSB 18 -#define RX_PRIORITY_OFFSET2_MGMT_MASK 0x00fc0000 -#define RX_PRIORITY_OFFSET2_MGMT_GET(x) (((x) & RX_PRIORITY_OFFSET2_MGMT_MASK) >> RX_PRIORITY_OFFSET2_MGMT_LSB) -#define RX_PRIORITY_OFFSET2_MGMT_SET(x) (((x) << RX_PRIORITY_OFFSET2_MGMT_LSB) & RX_PRIORITY_OFFSET2_MGMT_MASK) -#define RX_PRIORITY_OFFSET2_ATIM_MSB 17 -#define RX_PRIORITY_OFFSET2_ATIM_LSB 12 -#define RX_PRIORITY_OFFSET2_ATIM_MASK 0x0003f000 -#define RX_PRIORITY_OFFSET2_ATIM_GET(x) (((x) & RX_PRIORITY_OFFSET2_ATIM_MASK) >> RX_PRIORITY_OFFSET2_ATIM_LSB) -#define RX_PRIORITY_OFFSET2_ATIM_SET(x) (((x) << RX_PRIORITY_OFFSET2_ATIM_LSB) & RX_PRIORITY_OFFSET2_ATIM_MASK) -#define RX_PRIORITY_OFFSET2_PRESP_MSB 11 -#define RX_PRIORITY_OFFSET2_PRESP_LSB 6 -#define RX_PRIORITY_OFFSET2_PRESP_MASK 0x00000fc0 -#define RX_PRIORITY_OFFSET2_PRESP_GET(x) (((x) & RX_PRIORITY_OFFSET2_PRESP_MASK) >> RX_PRIORITY_OFFSET2_PRESP_LSB) -#define RX_PRIORITY_OFFSET2_PRESP_SET(x) (((x) << RX_PRIORITY_OFFSET2_PRESP_LSB) & RX_PRIORITY_OFFSET2_PRESP_MASK) -#define RX_PRIORITY_OFFSET2_XCAST_MSB 5 -#define RX_PRIORITY_OFFSET2_XCAST_LSB 0 -#define RX_PRIORITY_OFFSET2_XCAST_MASK 0x0000003f -#define RX_PRIORITY_OFFSET2_XCAST_GET(x) (((x) & RX_PRIORITY_OFFSET2_XCAST_MASK) >> RX_PRIORITY_OFFSET2_XCAST_LSB) -#define RX_PRIORITY_OFFSET2_XCAST_SET(x) (((x) << RX_PRIORITY_OFFSET2_XCAST_LSB) & RX_PRIORITY_OFFSET2_XCAST_MASK) - -#define RX_PRIORITY_OFFSET3_ADDRESS 0x00008390 -#define RX_PRIORITY_OFFSET3_OFFSET 0x00000390 -#define RX_PRIORITY_OFFSET3_PS_POLL_MSB 29 -#define RX_PRIORITY_OFFSET3_PS_POLL_LSB 24 -#define RX_PRIORITY_OFFSET3_PS_POLL_MASK 0x3f000000 -#define RX_PRIORITY_OFFSET3_PS_POLL_GET(x) (((x) & RX_PRIORITY_OFFSET3_PS_POLL_MASK) >> RX_PRIORITY_OFFSET3_PS_POLL_LSB) -#define RX_PRIORITY_OFFSET3_PS_POLL_SET(x) (((x) << RX_PRIORITY_OFFSET3_PS_POLL_LSB) & RX_PRIORITY_OFFSET3_PS_POLL_MASK) -#define RX_PRIORITY_OFFSET3_AMSDU_MSB 23 -#define RX_PRIORITY_OFFSET3_AMSDU_LSB 18 -#define RX_PRIORITY_OFFSET3_AMSDU_MASK 0x00fc0000 -#define RX_PRIORITY_OFFSET3_AMSDU_GET(x) (((x) & RX_PRIORITY_OFFSET3_AMSDU_MASK) >> RX_PRIORITY_OFFSET3_AMSDU_LSB) -#define RX_PRIORITY_OFFSET3_AMSDU_SET(x) (((x) << RX_PRIORITY_OFFSET3_AMSDU_LSB) & RX_PRIORITY_OFFSET3_AMSDU_MASK) -#define RX_PRIORITY_OFFSET3_AMPDU_MSB 17 -#define RX_PRIORITY_OFFSET3_AMPDU_LSB 12 -#define RX_PRIORITY_OFFSET3_AMPDU_MASK 0x0003f000 -#define RX_PRIORITY_OFFSET3_AMPDU_GET(x) (((x) & RX_PRIORITY_OFFSET3_AMPDU_MASK) >> RX_PRIORITY_OFFSET3_AMPDU_LSB) -#define RX_PRIORITY_OFFSET3_AMPDU_SET(x) (((x) << RX_PRIORITY_OFFSET3_AMPDU_LSB) & RX_PRIORITY_OFFSET3_AMPDU_MASK) -#define RX_PRIORITY_OFFSET3_EOSP_MSB 11 -#define RX_PRIORITY_OFFSET3_EOSP_LSB 6 -#define RX_PRIORITY_OFFSET3_EOSP_MASK 0x00000fc0 -#define RX_PRIORITY_OFFSET3_EOSP_GET(x) (((x) & RX_PRIORITY_OFFSET3_EOSP_MASK) >> RX_PRIORITY_OFFSET3_EOSP_LSB) -#define RX_PRIORITY_OFFSET3_EOSP_SET(x) (((x) << RX_PRIORITY_OFFSET3_EOSP_LSB) & RX_PRIORITY_OFFSET3_EOSP_MASK) -#define RX_PRIORITY_OFFSET3_MORE_MSB 5 -#define RX_PRIORITY_OFFSET3_MORE_LSB 0 -#define RX_PRIORITY_OFFSET3_MORE_MASK 0x0000003f -#define RX_PRIORITY_OFFSET3_MORE_GET(x) (((x) & RX_PRIORITY_OFFSET3_MORE_MASK) >> RX_PRIORITY_OFFSET3_MORE_LSB) -#define RX_PRIORITY_OFFSET3_MORE_SET(x) (((x) << RX_PRIORITY_OFFSET3_MORE_LSB) & RX_PRIORITY_OFFSET3_MORE_MASK) - -#define RX_PRIORITY_OFFSET4_ADDRESS 0x00008394 -#define RX_PRIORITY_OFFSET4_OFFSET 0x00000394 -#define RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_MSB 29 -#define RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_LSB 24 -#define RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_MASK 0x3f000000 -#define RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_LSB) -#define RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_MASK) -#define RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_MSB 23 -#define RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_LSB 18 -#define RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_MASK 0x00fc0000 -#define RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_LSB) -#define RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_MASK) -#define RX_PRIORITY_OFFSET4_BEACON_SSID_MSB 17 -#define RX_PRIORITY_OFFSET4_BEACON_SSID_LSB 12 -#define RX_PRIORITY_OFFSET4_BEACON_SSID_MASK 0x0003f000 -#define RX_PRIORITY_OFFSET4_BEACON_SSID_GET(x) (((x) & RX_PRIORITY_OFFSET4_BEACON_SSID_MASK) >> RX_PRIORITY_OFFSET4_BEACON_SSID_LSB) -#define RX_PRIORITY_OFFSET4_BEACON_SSID_SET(x) (((x) << RX_PRIORITY_OFFSET4_BEACON_SSID_LSB) & RX_PRIORITY_OFFSET4_BEACON_SSID_MASK) -#define RX_PRIORITY_OFFSET4_NULL_MSB 11 -#define RX_PRIORITY_OFFSET4_NULL_LSB 6 -#define RX_PRIORITY_OFFSET4_NULL_MASK 0x00000fc0 -#define RX_PRIORITY_OFFSET4_NULL_GET(x) (((x) & RX_PRIORITY_OFFSET4_NULL_MASK) >> RX_PRIORITY_OFFSET4_NULL_LSB) -#define RX_PRIORITY_OFFSET4_NULL_SET(x) (((x) << RX_PRIORITY_OFFSET4_NULL_LSB) & RX_PRIORITY_OFFSET4_NULL_MASK) -#define RX_PRIORITY_OFFSET4_PREQ_MSB 5 -#define RX_PRIORITY_OFFSET4_PREQ_LSB 0 -#define RX_PRIORITY_OFFSET4_PREQ_MASK 0x0000003f -#define RX_PRIORITY_OFFSET4_PREQ_GET(x) (((x) & RX_PRIORITY_OFFSET4_PREQ_MASK) >> RX_PRIORITY_OFFSET4_PREQ_LSB) -#define RX_PRIORITY_OFFSET4_PREQ_SET(x) (((x) << RX_PRIORITY_OFFSET4_PREQ_LSB) & RX_PRIORITY_OFFSET4_PREQ_MASK) - -#define RX_PRIORITY_OFFSET5_ADDRESS 0x00008398 -#define RX_PRIORITY_OFFSET5_OFFSET 0x00000398 -#define RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_MSB 17 -#define RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_LSB 12 -#define RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_MASK 0x0003f000 -#define RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_LSB) -#define RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_MASK) -#define RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_MSB 11 -#define RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_LSB 6 -#define RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_MASK 0x00000fc0 -#define RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_LSB) -#define RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_MASK) -#define RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_MSB 5 -#define RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_LSB 0 -#define RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_MASK 0x0000003f -#define RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_LSB) -#define RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_MASK) - -#define MAC_PCU_BSSID2_L32_ADDRESS 0x0000839c -#define MAC_PCU_BSSID2_L32_OFFSET 0x0000039c -#define MAC_PCU_BSSID2_L32_ADDR_MSB 31 -#define MAC_PCU_BSSID2_L32_ADDR_LSB 0 -#define MAC_PCU_BSSID2_L32_ADDR_MASK 0xffffffff -#define MAC_PCU_BSSID2_L32_ADDR_GET(x) (((x) & MAC_PCU_BSSID2_L32_ADDR_MASK) >> MAC_PCU_BSSID2_L32_ADDR_LSB) -#define MAC_PCU_BSSID2_L32_ADDR_SET(x) (((x) << MAC_PCU_BSSID2_L32_ADDR_LSB) & MAC_PCU_BSSID2_L32_ADDR_MASK) - -#define MAC_PCU_BSSID2_U16_ADDRESS 0x000083a0 -#define MAC_PCU_BSSID2_U16_OFFSET 0x000003a0 -#define MAC_PCU_BSSID2_U16_ENABLE_MSB 16 -#define MAC_PCU_BSSID2_U16_ENABLE_LSB 16 -#define MAC_PCU_BSSID2_U16_ENABLE_MASK 0x00010000 -#define MAC_PCU_BSSID2_U16_ENABLE_GET(x) (((x) & MAC_PCU_BSSID2_U16_ENABLE_MASK) >> MAC_PCU_BSSID2_U16_ENABLE_LSB) -#define MAC_PCU_BSSID2_U16_ENABLE_SET(x) (((x) << MAC_PCU_BSSID2_U16_ENABLE_LSB) & MAC_PCU_BSSID2_U16_ENABLE_MASK) -#define MAC_PCU_BSSID2_U16_ADDR_MSB 15 -#define MAC_PCU_BSSID2_U16_ADDR_LSB 0 -#define MAC_PCU_BSSID2_U16_ADDR_MASK 0x0000ffff -#define MAC_PCU_BSSID2_U16_ADDR_GET(x) (((x) & MAC_PCU_BSSID2_U16_ADDR_MASK) >> MAC_PCU_BSSID2_U16_ADDR_LSB) -#define MAC_PCU_BSSID2_U16_ADDR_SET(x) (((x) << MAC_PCU_BSSID2_U16_ADDR_LSB) & MAC_PCU_BSSID2_U16_ADDR_MASK) - -#define MAC_PCU_TSF1_STATUS_L32_ADDRESS 0x000083a4 -#define MAC_PCU_TSF1_STATUS_L32_OFFSET 0x000003a4 -#define MAC_PCU_TSF1_STATUS_L32_VALUE_MSB 31 -#define MAC_PCU_TSF1_STATUS_L32_VALUE_LSB 0 -#define MAC_PCU_TSF1_STATUS_L32_VALUE_MASK 0xffffffff -#define MAC_PCU_TSF1_STATUS_L32_VALUE_GET(x) (((x) & MAC_PCU_TSF1_STATUS_L32_VALUE_MASK) >> MAC_PCU_TSF1_STATUS_L32_VALUE_LSB) -#define MAC_PCU_TSF1_STATUS_L32_VALUE_SET(x) (((x) << MAC_PCU_TSF1_STATUS_L32_VALUE_LSB) & MAC_PCU_TSF1_STATUS_L32_VALUE_MASK) - -#define MAC_PCU_TSF1_STATUS_U32_ADDRESS 0x000083a8 -#define MAC_PCU_TSF1_STATUS_U32_OFFSET 0x000003a8 -#define MAC_PCU_TSF1_STATUS_U32_VALUE_MSB 31 -#define MAC_PCU_TSF1_STATUS_U32_VALUE_LSB 0 -#define MAC_PCU_TSF1_STATUS_U32_VALUE_MASK 0xffffffff -#define MAC_PCU_TSF1_STATUS_U32_VALUE_GET(x) (((x) & MAC_PCU_TSF1_STATUS_U32_VALUE_MASK) >> MAC_PCU_TSF1_STATUS_U32_VALUE_LSB) -#define MAC_PCU_TSF1_STATUS_U32_VALUE_SET(x) (((x) << MAC_PCU_TSF1_STATUS_U32_VALUE_LSB) & MAC_PCU_TSF1_STATUS_U32_VALUE_MASK) - -#define MAC_PCU_TSF2_STATUS_L32_ADDRESS 0x000083ac -#define MAC_PCU_TSF2_STATUS_L32_OFFSET 0x000003ac -#define MAC_PCU_TSF2_STATUS_L32_VALUE_MSB 31 -#define MAC_PCU_TSF2_STATUS_L32_VALUE_LSB 0 -#define MAC_PCU_TSF2_STATUS_L32_VALUE_MASK 0xffffffff -#define MAC_PCU_TSF2_STATUS_L32_VALUE_GET(x) (((x) & MAC_PCU_TSF2_STATUS_L32_VALUE_MASK) >> MAC_PCU_TSF2_STATUS_L32_VALUE_LSB) -#define MAC_PCU_TSF2_STATUS_L32_VALUE_SET(x) (((x) << MAC_PCU_TSF2_STATUS_L32_VALUE_LSB) & MAC_PCU_TSF2_STATUS_L32_VALUE_MASK) - -#define MAC_PCU_TSF2_STATUS_U32_ADDRESS 0x000083b0 -#define MAC_PCU_TSF2_STATUS_U32_OFFSET 0x000003b0 -#define MAC_PCU_TSF2_STATUS_U32_VALUE_MSB 31 -#define MAC_PCU_TSF2_STATUS_U32_VALUE_LSB 0 -#define MAC_PCU_TSF2_STATUS_U32_VALUE_MASK 0xffffffff -#define MAC_PCU_TSF2_STATUS_U32_VALUE_GET(x) (((x) & MAC_PCU_TSF2_STATUS_U32_VALUE_MASK) >> MAC_PCU_TSF2_STATUS_U32_VALUE_LSB) -#define MAC_PCU_TSF2_STATUS_U32_VALUE_SET(x) (((x) << MAC_PCU_TSF2_STATUS_U32_VALUE_LSB) & MAC_PCU_TSF2_STATUS_U32_VALUE_MASK) - -#define MAC_PCU_TXBUF_BA_ADDRESS 0x00008400 -#define MAC_PCU_TXBUF_BA_OFFSET 0x00000400 -#define MAC_PCU_TXBUF_BA_DATA_MSB 31 -#define MAC_PCU_TXBUF_BA_DATA_LSB 0 -#define MAC_PCU_TXBUF_BA_DATA_MASK 0xffffffff -#define MAC_PCU_TXBUF_BA_DATA_GET(x) (((x) & MAC_PCU_TXBUF_BA_DATA_MASK) >> MAC_PCU_TXBUF_BA_DATA_LSB) -#define MAC_PCU_TXBUF_BA_DATA_SET(x) (((x) << MAC_PCU_TXBUF_BA_DATA_LSB) & MAC_PCU_TXBUF_BA_DATA_MASK) - -#define MAC_PCU_KEY_CACHE_1_ADDRESS 0x00008800 -#define MAC_PCU_KEY_CACHE_1_OFFSET 0x00000800 -#define MAC_PCU_KEY_CACHE_1_DATA_MSB 31 -#define MAC_PCU_KEY_CACHE_1_DATA_LSB 0 -#define MAC_PCU_KEY_CACHE_1_DATA_MASK 0xffffffff -#define MAC_PCU_KEY_CACHE_1_DATA_GET(x) (((x) & MAC_PCU_KEY_CACHE_1_DATA_MASK) >> MAC_PCU_KEY_CACHE_1_DATA_LSB) -#define MAC_PCU_KEY_CACHE_1_DATA_SET(x) (((x) << MAC_PCU_KEY_CACHE_1_DATA_LSB) & MAC_PCU_KEY_CACHE_1_DATA_MASK) - -#define MAC_PCU_BASEBAND_0_ADDRESS 0x00009800 -#define MAC_PCU_BASEBAND_0_OFFSET 0x00001800 -#define MAC_PCU_BASEBAND_0_DATA_MSB 31 -#define MAC_PCU_BASEBAND_0_DATA_LSB 0 -#define MAC_PCU_BASEBAND_0_DATA_MASK 0xffffffff -#define MAC_PCU_BASEBAND_0_DATA_GET(x) (((x) & MAC_PCU_BASEBAND_0_DATA_MASK) >> MAC_PCU_BASEBAND_0_DATA_LSB) -#define MAC_PCU_BASEBAND_0_DATA_SET(x) (((x) << MAC_PCU_BASEBAND_0_DATA_LSB) & MAC_PCU_BASEBAND_0_DATA_MASK) - -#define MAC_PCU_BASEBAND_1_ADDRESS 0x0000a000 -#define MAC_PCU_BASEBAND_1_OFFSET 0x00002000 -#define MAC_PCU_BASEBAND_1_DATA_MSB 31 -#define MAC_PCU_BASEBAND_1_DATA_LSB 0 -#define MAC_PCU_BASEBAND_1_DATA_MASK 0xffffffff -#define MAC_PCU_BASEBAND_1_DATA_GET(x) (((x) & MAC_PCU_BASEBAND_1_DATA_MASK) >> MAC_PCU_BASEBAND_1_DATA_LSB) -#define MAC_PCU_BASEBAND_1_DATA_SET(x) (((x) << MAC_PCU_BASEBAND_1_DATA_LSB) & MAC_PCU_BASEBAND_1_DATA_MASK) - -#define MAC_PCU_BASEBAND_2_ADDRESS 0x0000c000 -#define MAC_PCU_BASEBAND_2_OFFSET 0x00004000 -#define MAC_PCU_BASEBAND_2_DATA_MSB 31 -#define MAC_PCU_BASEBAND_2_DATA_LSB 0 -#define MAC_PCU_BASEBAND_2_DATA_MASK 0xffffffff -#define MAC_PCU_BASEBAND_2_DATA_GET(x) (((x) & MAC_PCU_BASEBAND_2_DATA_MASK) >> MAC_PCU_BASEBAND_2_DATA_LSB) -#define MAC_PCU_BASEBAND_2_DATA_SET(x) (((x) << MAC_PCU_BASEBAND_2_DATA_LSB) & MAC_PCU_BASEBAND_2_DATA_MASK) - -#define MAC_PCU_BASEBAND_3_ADDRESS 0x0000d000 -#define MAC_PCU_BASEBAND_3_OFFSET 0x00005000 -#define MAC_PCU_BASEBAND_3_DATA_MSB 31 -#define MAC_PCU_BASEBAND_3_DATA_LSB 0 -#define MAC_PCU_BASEBAND_3_DATA_MASK 0xffffffff -#define MAC_PCU_BASEBAND_3_DATA_GET(x) (((x) & MAC_PCU_BASEBAND_3_DATA_MASK) >> MAC_PCU_BASEBAND_3_DATA_LSB) -#define MAC_PCU_BASEBAND_3_DATA_SET(x) (((x) << MAC_PCU_BASEBAND_3_DATA_LSB) & MAC_PCU_BASEBAND_3_DATA_MASK) - -#define MAC_PCU_BUF_ADDRESS 0x0000e000 -#define MAC_PCU_BUF_OFFSET 0x00006000 -#define MAC_PCU_BUF_DATA_MSB 31 -#define MAC_PCU_BUF_DATA_LSB 0 -#define MAC_PCU_BUF_DATA_MASK 0xffffffff -#define MAC_PCU_BUF_DATA_GET(x) (((x) & MAC_PCU_BUF_DATA_MASK) >> MAC_PCU_BUF_DATA_LSB) -#define MAC_PCU_BUF_DATA_SET(x) (((x) << MAC_PCU_BUF_DATA_LSB) & MAC_PCU_BUF_DATA_MASK) - - -#ifndef __ASSEMBLER__ - -typedef struct mac_pcu_reg_s { - volatile unsigned int mac_pcu_sta_addr_l32; - volatile unsigned int mac_pcu_sta_addr_u16; - volatile unsigned int mac_pcu_bssid_l32; - volatile unsigned int mac_pcu_bssid_u16; - volatile unsigned int mac_pcu_bcn_rssi_ave; - volatile unsigned int mac_pcu_ack_cts_timeout; - volatile unsigned int mac_pcu_bcn_rssi_ctl; - volatile unsigned int mac_pcu_usec_latency; - volatile unsigned int pcu_max_cfp_dur; - volatile unsigned int mac_pcu_rx_filter; - volatile unsigned int mac_pcu_mcast_filter_l32; - volatile unsigned int mac_pcu_mcast_filter_u32; - volatile unsigned int mac_pcu_diag_sw; - volatile unsigned int mac_pcu_tst_addac; - volatile unsigned int mac_pcu_def_antenna; - volatile unsigned int mac_pcu_aes_mute_mask_0; - volatile unsigned int mac_pcu_aes_mute_mask_1; - volatile unsigned int mac_pcu_gated_clks; - volatile unsigned int mac_pcu_obs_bus_2; - volatile unsigned int mac_pcu_obs_bus_1; - volatile unsigned int mac_pcu_dym_mimo_pwr_save; - volatile unsigned int mac_pcu_last_beacon_tsf; - volatile unsigned int mac_pcu_nav; - volatile unsigned int mac_pcu_rts_success_cnt; - volatile unsigned int mac_pcu_rts_fail_cnt; - volatile unsigned int mac_pcu_ack_fail_cnt; - volatile unsigned int mac_pcu_fcs_fail_cnt; - volatile unsigned int mac_pcu_beacon_cnt; - volatile unsigned int mac_pcu_xrmode; - volatile unsigned int mac_pcu_xrdel; - volatile unsigned int mac_pcu_xrto; - volatile unsigned int mac_pcu_xrcrp; - volatile unsigned int mac_pcu_xrstmp; - volatile unsigned int mac_pcu_addr1_mask_l32; - volatile unsigned int mac_pcu_addr1_mask_u16; - volatile unsigned int mac_pcu_tpc; - volatile unsigned int mac_pcu_tx_frame_cnt; - volatile unsigned int mac_pcu_rx_frame_cnt; - volatile unsigned int mac_pcu_rx_clear_cnt; - volatile unsigned int mac_pcu_cycle_cnt; - volatile unsigned int mac_pcu_quiet_time_1; - volatile unsigned int mac_pcu_quiet_time_2; - volatile unsigned int mac_pcu_qos_no_ack; - volatile unsigned int mac_pcu_phy_error_mask; - volatile unsigned int mac_pcu_xrlat; - volatile unsigned int mac_pcu_rxbuf; - volatile unsigned int mac_pcu_mic_qos_control; - volatile unsigned int mac_pcu_mic_qos_select; - volatile unsigned int mac_pcu_misc_mode; - volatile unsigned int mac_pcu_filter_ofdm_cnt; - volatile unsigned int mac_pcu_filter_cck_cnt; - volatile unsigned int mac_pcu_phy_err_cnt_1; - volatile unsigned int mac_pcu_phy_err_cnt_1_mask; - volatile unsigned int mac_pcu_phy_err_cnt_2; - volatile unsigned int mac_pcu_phy_err_cnt_2_mask; - volatile unsigned int mac_pcu_tsf_threshold; - volatile unsigned int mac_pcu_phy_error_eifs_mask; - volatile unsigned int mac_pcu_phy_err_cnt_3; - volatile unsigned int mac_pcu_phy_err_cnt_3_mask; - volatile unsigned int mac_pcu_bluetooth_mode; - volatile unsigned int mac_pcu_bluetooth_weights; - volatile unsigned int mac_pcu_bluetooth_mode2; - volatile unsigned int mac_pcu_txsifs; - volatile unsigned int mac_pcu_txop_x; - volatile unsigned int mac_pcu_txop_0_3; - volatile unsigned int mac_pcu_txop_4_7; - volatile unsigned int mac_pcu_txop_8_11; - volatile unsigned int mac_pcu_txop_12_15; - volatile unsigned int mac_pcu_logic_analyzer; - volatile unsigned int mac_pcu_logic_analyzer_32l; - volatile unsigned int mac_pcu_logic_analyzer_16u; - volatile unsigned int mac_pcu_phy_err_cnt_mask_cont; - volatile unsigned int mac_pcu_azimuth_mode; - volatile unsigned int mac_pcu_20_40_mode; - volatile unsigned int mac_pcu_rx_clear_diff_cnt; - volatile unsigned int mac_pcu_self_gen_antenna_mask; - volatile unsigned int mac_pcu_ba_bar_control; - volatile unsigned int mac_pcu_legacy_plcp_spoof; - volatile unsigned int mac_pcu_phy_error_mask_cont; - volatile unsigned int mac_pcu_tx_timer; - volatile unsigned int mac_pcu_txbuf_ctrl; - volatile unsigned int mac_pcu_misc_mode2; - volatile unsigned int mac_pcu_alt_aes_mute_mask; - volatile unsigned int mac_pcu_azimuth_time_stamp; - volatile unsigned int mac_pcu_max_cfp_dur; - volatile unsigned int mac_pcu_hcf_timeout; - volatile unsigned int mac_pcu_bluetooth_weights2; - volatile unsigned int mac_pcu_bluetooth_tsf_bt_active; - volatile unsigned int mac_pcu_bluetooth_tsf_bt_priority; - volatile unsigned int mac_pcu_bluetooth_mode3; - volatile unsigned int mac_pcu_bluetooth_mode4; - unsigned char pad0[148]; /* pad to 0x200 */ - volatile unsigned int mac_pcu_bt_bt[64]; - volatile unsigned int mac_pcu_bt_bt_async; - volatile unsigned int mac_pcu_bt_wl_1; - volatile unsigned int mac_pcu_bt_wl_2; - volatile unsigned int mac_pcu_bt_wl_3; - volatile unsigned int mac_pcu_bt_wl_4; - volatile unsigned int mac_pcu_coex_epta; - volatile unsigned int mac_pcu_coex_lnamaxgain1; - volatile unsigned int mac_pcu_coex_lnamaxgain2; - volatile unsigned int mac_pcu_coex_lnamaxgain3; - volatile unsigned int mac_pcu_coex_lnamaxgain4; - volatile unsigned int mac_pcu_basic_rate_set0; - volatile unsigned int mac_pcu_basic_rate_set1; - volatile unsigned int mac_pcu_basic_rate_set2; - volatile unsigned int mac_pcu_basic_rate_set3; - volatile unsigned int mac_pcu_rx_int_status0; - volatile unsigned int mac_pcu_rx_int_status1; - volatile unsigned int mac_pcu_rx_int_status2; - volatile unsigned int mac_pcu_rx_int_status3; - volatile unsigned int ht_half_gi_rate1; - volatile unsigned int ht_half_gi_rate2; - volatile unsigned int ht_full_gi_rate1; - volatile unsigned int ht_full_gi_rate2; - volatile unsigned int legacy_rate1; - volatile unsigned int legacy_rate2; - volatile unsigned int legacy_rate3; - volatile unsigned int rx_int_filter; - volatile unsigned int rx_int_overflow; - volatile unsigned int rx_filter_thresh; - volatile unsigned int rx_filter_thresh1; - volatile unsigned int rx_priority_thresh0; - volatile unsigned int rx_priority_thresh1; - volatile unsigned int rx_priority_thresh2; - volatile unsigned int rx_priority_thresh3; - volatile unsigned int rx_priority_offset0; - volatile unsigned int rx_priority_offset1; - volatile unsigned int rx_priority_offset2; - volatile unsigned int rx_priority_offset3; - volatile unsigned int rx_priority_offset4; - volatile unsigned int rx_priority_offset5; - volatile unsigned int mac_pcu_bssid2_l32; - volatile unsigned int mac_pcu_bssid2_u16; - volatile unsigned int mac_pcu_tsf1_status_l32; - volatile unsigned int mac_pcu_tsf1_status_u32; - volatile unsigned int mac_pcu_tsf2_status_l32; - volatile unsigned int mac_pcu_tsf2_status_u32; - unsigned char pad1[76]; /* pad to 0x400 */ - volatile unsigned int mac_pcu_txbuf_ba[64]; - unsigned char pad2[768]; /* pad to 0x800 */ - volatile unsigned int mac_pcu_key_cache_1[256]; - unsigned char pad3[3072]; /* pad to 0x1800 */ - volatile unsigned int mac_pcu_baseband_0[512]; - volatile unsigned int mac_pcu_baseband_1[2048]; - volatile unsigned int mac_pcu_baseband_2[1024]; - volatile unsigned int mac_pcu_baseband_3[1024]; - volatile unsigned int mac_pcu_buf[512]; -} mac_pcu_reg_t; - -#endif /* __ASSEMBLER__ */ - -#endif /* _MAC_PCU_H_ */ diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/rdma_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/rdma_reg.h deleted file mode 100644 index 56ffda5b1a30..000000000000 --- a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/rdma_reg.h +++ /dev/null @@ -1,564 +0,0 @@ -// ------------------------------------------------------------------ -// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. -// -// -// Permission to use, copy, modify, and/or distribute this software for any -// purpose with or without fee is hereby granted, provided that the above -// copyright notice and this permission notice appear in all copies. -// -// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -// -// -// ------------------------------------------------------------------ -//=================================================================== -// Author(s): ="Atheros" -//=================================================================== - - -#ifndef _RDMA_REG_REG_H_ -#define _RDMA_REG_REG_H_ - -#define DMA_CONFIG_ADDRESS 0x00000000 -#define DMA_CONFIG_OFFSET 0x00000000 -#define DMA_CONFIG_WLBB_PWD_EN_MSB 4 -#define DMA_CONFIG_WLBB_PWD_EN_LSB 4 -#define DMA_CONFIG_WLBB_PWD_EN_MASK 0x00000010 -#define DMA_CONFIG_WLBB_PWD_EN_GET(x) (((x) & DMA_CONFIG_WLBB_PWD_EN_MASK) >> DMA_CONFIG_WLBB_PWD_EN_LSB) -#define DMA_CONFIG_WLBB_PWD_EN_SET(x) (((x) << DMA_CONFIG_WLBB_PWD_EN_LSB) & DMA_CONFIG_WLBB_PWD_EN_MASK) -#define DMA_CONFIG_WLMAC_PWD_EN_MSB 3 -#define DMA_CONFIG_WLMAC_PWD_EN_LSB 3 -#define DMA_CONFIG_WLMAC_PWD_EN_MASK 0x00000008 -#define DMA_CONFIG_WLMAC_PWD_EN_GET(x) (((x) & DMA_CONFIG_WLMAC_PWD_EN_MASK) >> DMA_CONFIG_WLMAC_PWD_EN_LSB) -#define DMA_CONFIG_WLMAC_PWD_EN_SET(x) (((x) << DMA_CONFIG_WLMAC_PWD_EN_LSB) & DMA_CONFIG_WLMAC_PWD_EN_MASK) -#define DMA_CONFIG_ENABLE_RETENTION_MSB 2 -#define DMA_CONFIG_ENABLE_RETENTION_LSB 2 -#define DMA_CONFIG_ENABLE_RETENTION_MASK 0x00000004 -#define DMA_CONFIG_ENABLE_RETENTION_GET(x) (((x) & DMA_CONFIG_ENABLE_RETENTION_MASK) >> DMA_CONFIG_ENABLE_RETENTION_LSB) -#define DMA_CONFIG_ENABLE_RETENTION_SET(x) (((x) << DMA_CONFIG_ENABLE_RETENTION_LSB) & DMA_CONFIG_ENABLE_RETENTION_MASK) -#define DMA_CONFIG_RTC_PRIORITY_MSB 1 -#define DMA_CONFIG_RTC_PRIORITY_LSB 1 -#define DMA_CONFIG_RTC_PRIORITY_MASK 0x00000002 -#define DMA_CONFIG_RTC_PRIORITY_GET(x) (((x) & DMA_CONFIG_RTC_PRIORITY_MASK) >> DMA_CONFIG_RTC_PRIORITY_LSB) -#define DMA_CONFIG_RTC_PRIORITY_SET(x) (((x) << DMA_CONFIG_RTC_PRIORITY_LSB) & DMA_CONFIG_RTC_PRIORITY_MASK) -#define DMA_CONFIG_DMA_TYPE_MSB 0 -#define DMA_CONFIG_DMA_TYPE_LSB 0 -#define DMA_CONFIG_DMA_TYPE_MASK 0x00000001 -#define DMA_CONFIG_DMA_TYPE_GET(x) (((x) & DMA_CONFIG_DMA_TYPE_MASK) >> DMA_CONFIG_DMA_TYPE_LSB) -#define DMA_CONFIG_DMA_TYPE_SET(x) (((x) << DMA_CONFIG_DMA_TYPE_LSB) & DMA_CONFIG_DMA_TYPE_MASK) - -#define DMA_CONTROL_ADDRESS 0x00000004 -#define DMA_CONTROL_OFFSET 0x00000004 -#define DMA_CONTROL_START_MSB 1 -#define DMA_CONTROL_START_LSB 1 -#define DMA_CONTROL_START_MASK 0x00000002 -#define DMA_CONTROL_START_GET(x) (((x) & DMA_CONTROL_START_MASK) >> DMA_CONTROL_START_LSB) -#define DMA_CONTROL_START_SET(x) (((x) << DMA_CONTROL_START_LSB) & DMA_CONTROL_START_MASK) -#define DMA_CONTROL_STOP_MSB 0 -#define DMA_CONTROL_STOP_LSB 0 -#define DMA_CONTROL_STOP_MASK 0x00000001 -#define DMA_CONTROL_STOP_GET(x) (((x) & DMA_CONTROL_STOP_MASK) >> DMA_CONTROL_STOP_LSB) -#define DMA_CONTROL_STOP_SET(x) (((x) << DMA_CONTROL_STOP_LSB) & DMA_CONTROL_STOP_MASK) - -#define DMA_SRC_ADDRESS 0x00000008 -#define DMA_SRC_OFFSET 0x00000008 -#define DMA_SRC_ADDR_MSB 31 -#define DMA_SRC_ADDR_LSB 2 -#define DMA_SRC_ADDR_MASK 0xfffffffc -#define DMA_SRC_ADDR_GET(x) (((x) & DMA_SRC_ADDR_MASK) >> DMA_SRC_ADDR_LSB) -#define DMA_SRC_ADDR_SET(x) (((x) << DMA_SRC_ADDR_LSB) & DMA_SRC_ADDR_MASK) - -#define DMA_DEST_ADDRESS 0x0000000c -#define DMA_DEST_OFFSET 0x0000000c -#define DMA_DEST_ADDR_MSB 31 -#define DMA_DEST_ADDR_LSB 2 -#define DMA_DEST_ADDR_MASK 0xfffffffc -#define DMA_DEST_ADDR_GET(x) (((x) & DMA_DEST_ADDR_MASK) >> DMA_DEST_ADDR_LSB) -#define DMA_DEST_ADDR_SET(x) (((x) << DMA_DEST_ADDR_LSB) & DMA_DEST_ADDR_MASK) - -#define DMA_LENGTH_ADDRESS 0x00000010 -#define DMA_LENGTH_OFFSET 0x00000010 -#define DMA_LENGTH_WORDS_MSB 11 -#define DMA_LENGTH_WORDS_LSB 0 -#define DMA_LENGTH_WORDS_MASK 0x00000fff -#define DMA_LENGTH_WORDS_GET(x) (((x) & DMA_LENGTH_WORDS_MASK) >> DMA_LENGTH_WORDS_LSB) -#define DMA_LENGTH_WORDS_SET(x) (((x) << DMA_LENGTH_WORDS_LSB) & DMA_LENGTH_WORDS_MASK) - -#define VMC_BASE_ADDRESS 0x00000014 -#define VMC_BASE_OFFSET 0x00000014 -#define VMC_BASE_ADDR_MSB 31 -#define VMC_BASE_ADDR_LSB 2 -#define VMC_BASE_ADDR_MASK 0xfffffffc -#define VMC_BASE_ADDR_GET(x) (((x) & VMC_BASE_ADDR_MASK) >> VMC_BASE_ADDR_LSB) -#define VMC_BASE_ADDR_SET(x) (((x) << VMC_BASE_ADDR_LSB) & VMC_BASE_ADDR_MASK) - -#define INDIRECT_REG_ADDRESS 0x00000018 -#define INDIRECT_REG_OFFSET 0x00000018 -#define INDIRECT_REG_ID_MSB 31 -#define INDIRECT_REG_ID_LSB 2 -#define INDIRECT_REG_ID_MASK 0xfffffffc -#define INDIRECT_REG_ID_GET(x) (((x) & INDIRECT_REG_ID_MASK) >> INDIRECT_REG_ID_LSB) -#define INDIRECT_REG_ID_SET(x) (((x) << INDIRECT_REG_ID_LSB) & INDIRECT_REG_ID_MASK) - -#define INDIRECT_RETURN_ADDRESS 0x0000001c -#define INDIRECT_RETURN_OFFSET 0x0000001c -#define INDIRECT_RETURN_ADDR_MSB 31 -#define INDIRECT_RETURN_ADDR_LSB 2 -#define INDIRECT_RETURN_ADDR_MASK 0xfffffffc -#define INDIRECT_RETURN_ADDR_GET(x) (((x) & INDIRECT_RETURN_ADDR_MASK) >> INDIRECT_RETURN_ADDR_LSB) -#define INDIRECT_RETURN_ADDR_SET(x) (((x) << INDIRECT_RETURN_ADDR_LSB) & INDIRECT_RETURN_ADDR_MASK) - -#define RDMA_REGION_0__ADDRESS 0x00000020 -#define RDMA_REGION_0__OFFSET 0x00000020 -#define RDMA_REGION_0__ADDR_MSB 31 -#define RDMA_REGION_0__ADDR_LSB 13 -#define RDMA_REGION_0__ADDR_MASK 0xffffe000 -#define RDMA_REGION_0__ADDR_GET(x) (((x) & RDMA_REGION_0__ADDR_MASK) >> RDMA_REGION_0__ADDR_LSB) -#define RDMA_REGION_0__ADDR_SET(x) (((x) << RDMA_REGION_0__ADDR_LSB) & RDMA_REGION_0__ADDR_MASK) -#define RDMA_REGION_0__LENGTH_MSB 12 -#define RDMA_REGION_0__LENGTH_LSB 2 -#define RDMA_REGION_0__LENGTH_MASK 0x00001ffc -#define RDMA_REGION_0__LENGTH_GET(x) (((x) & RDMA_REGION_0__LENGTH_MASK) >> RDMA_REGION_0__LENGTH_LSB) -#define RDMA_REGION_0__LENGTH_SET(x) (((x) << RDMA_REGION_0__LENGTH_LSB) & RDMA_REGION_0__LENGTH_MASK) -#define RDMA_REGION_0__INDI_MSB 1 -#define RDMA_REGION_0__INDI_LSB 1 -#define RDMA_REGION_0__INDI_MASK 0x00000002 -#define RDMA_REGION_0__INDI_GET(x) (((x) & RDMA_REGION_0__INDI_MASK) >> RDMA_REGION_0__INDI_LSB) -#define RDMA_REGION_0__INDI_SET(x) (((x) << RDMA_REGION_0__INDI_LSB) & RDMA_REGION_0__INDI_MASK) -#define RDMA_REGION_0__NEXT_MSB 0 -#define RDMA_REGION_0__NEXT_LSB 0 -#define RDMA_REGION_0__NEXT_MASK 0x00000001 -#define RDMA_REGION_0__NEXT_GET(x) (((x) & RDMA_REGION_0__NEXT_MASK) >> RDMA_REGION_0__NEXT_LSB) -#define RDMA_REGION_0__NEXT_SET(x) (((x) << RDMA_REGION_0__NEXT_LSB) & RDMA_REGION_0__NEXT_MASK) - -#define RDMA_REGION_1__ADDRESS 0x00000024 -#define RDMA_REGION_1__OFFSET 0x00000024 -#define RDMA_REGION_1__ADDR_MSB 31 -#define RDMA_REGION_1__ADDR_LSB 13 -#define RDMA_REGION_1__ADDR_MASK 0xffffe000 -#define RDMA_REGION_1__ADDR_GET(x) (((x) & RDMA_REGION_1__ADDR_MASK) >> RDMA_REGION_1__ADDR_LSB) -#define RDMA_REGION_1__ADDR_SET(x) (((x) << RDMA_REGION_1__ADDR_LSB) & RDMA_REGION_1__ADDR_MASK) -#define RDMA_REGION_1__LENGTH_MSB 12 -#define RDMA_REGION_1__LENGTH_LSB 2 -#define RDMA_REGION_1__LENGTH_MASK 0x00001ffc -#define RDMA_REGION_1__LENGTH_GET(x) (((x) & RDMA_REGION_1__LENGTH_MASK) >> RDMA_REGION_1__LENGTH_LSB) -#define RDMA_REGION_1__LENGTH_SET(x) (((x) << RDMA_REGION_1__LENGTH_LSB) & RDMA_REGION_1__LENGTH_MASK) -#define RDMA_REGION_1__INDI_MSB 1 -#define RDMA_REGION_1__INDI_LSB 1 -#define RDMA_REGION_1__INDI_MASK 0x00000002 -#define RDMA_REGION_1__INDI_GET(x) (((x) & RDMA_REGION_1__INDI_MASK) >> RDMA_REGION_1__INDI_LSB) -#define RDMA_REGION_1__INDI_SET(x) (((x) << RDMA_REGION_1__INDI_LSB) & RDMA_REGION_1__INDI_MASK) -#define RDMA_REGION_1__NEXT_MSB 0 -#define RDMA_REGION_1__NEXT_LSB 0 -#define RDMA_REGION_1__NEXT_MASK 0x00000001 -#define RDMA_REGION_1__NEXT_GET(x) (((x) & RDMA_REGION_1__NEXT_MASK) >> RDMA_REGION_1__NEXT_LSB) -#define RDMA_REGION_1__NEXT_SET(x) (((x) << RDMA_REGION_1__NEXT_LSB) & RDMA_REGION_1__NEXT_MASK) - -#define RDMA_REGION_2__ADDRESS 0x00000028 -#define RDMA_REGION_2__OFFSET 0x00000028 -#define RDMA_REGION_2__ADDR_MSB 31 -#define RDMA_REGION_2__ADDR_LSB 13 -#define RDMA_REGION_2__ADDR_MASK 0xffffe000 -#define RDMA_REGION_2__ADDR_GET(x) (((x) & RDMA_REGION_2__ADDR_MASK) >> RDMA_REGION_2__ADDR_LSB) -#define RDMA_REGION_2__ADDR_SET(x) (((x) << RDMA_REGION_2__ADDR_LSB) & RDMA_REGION_2__ADDR_MASK) -#define RDMA_REGION_2__LENGTH_MSB 12 -#define RDMA_REGION_2__LENGTH_LSB 2 -#define RDMA_REGION_2__LENGTH_MASK 0x00001ffc -#define RDMA_REGION_2__LENGTH_GET(x) (((x) & RDMA_REGION_2__LENGTH_MASK) >> RDMA_REGION_2__LENGTH_LSB) -#define RDMA_REGION_2__LENGTH_SET(x) (((x) << RDMA_REGION_2__LENGTH_LSB) & RDMA_REGION_2__LENGTH_MASK) -#define RDMA_REGION_2__INDI_MSB 1 -#define RDMA_REGION_2__INDI_LSB 1 -#define RDMA_REGION_2__INDI_MASK 0x00000002 -#define RDMA_REGION_2__INDI_GET(x) (((x) & RDMA_REGION_2__INDI_MASK) >> RDMA_REGION_2__INDI_LSB) -#define RDMA_REGION_2__INDI_SET(x) (((x) << RDMA_REGION_2__INDI_LSB) & RDMA_REGION_2__INDI_MASK) -#define RDMA_REGION_2__NEXT_MSB 0 -#define RDMA_REGION_2__NEXT_LSB 0 -#define RDMA_REGION_2__NEXT_MASK 0x00000001 -#define RDMA_REGION_2__NEXT_GET(x) (((x) & RDMA_REGION_2__NEXT_MASK) >> RDMA_REGION_2__NEXT_LSB) -#define RDMA_REGION_2__NEXT_SET(x) (((x) << RDMA_REGION_2__NEXT_LSB) & RDMA_REGION_2__NEXT_MASK) - -#define RDMA_REGION_3__ADDRESS 0x0000002c -#define RDMA_REGION_3__OFFSET 0x0000002c -#define RDMA_REGION_3__ADDR_MSB 31 -#define RDMA_REGION_3__ADDR_LSB 13 -#define RDMA_REGION_3__ADDR_MASK 0xffffe000 -#define RDMA_REGION_3__ADDR_GET(x) (((x) & RDMA_REGION_3__ADDR_MASK) >> RDMA_REGION_3__ADDR_LSB) -#define RDMA_REGION_3__ADDR_SET(x) (((x) << RDMA_REGION_3__ADDR_LSB) & RDMA_REGION_3__ADDR_MASK) -#define RDMA_REGION_3__LENGTH_MSB 12 -#define RDMA_REGION_3__LENGTH_LSB 2 -#define RDMA_REGION_3__LENGTH_MASK 0x00001ffc -#define RDMA_REGION_3__LENGTH_GET(x) (((x) & RDMA_REGION_3__LENGTH_MASK) >> RDMA_REGION_3__LENGTH_LSB) -#define RDMA_REGION_3__LENGTH_SET(x) (((x) << RDMA_REGION_3__LENGTH_LSB) & RDMA_REGION_3__LENGTH_MASK) -#define RDMA_REGION_3__INDI_MSB 1 -#define RDMA_REGION_3__INDI_LSB 1 -#define RDMA_REGION_3__INDI_MASK 0x00000002 -#define RDMA_REGION_3__INDI_GET(x) (((x) & RDMA_REGION_3__INDI_MASK) >> RDMA_REGION_3__INDI_LSB) -#define RDMA_REGION_3__INDI_SET(x) (((x) << RDMA_REGION_3__INDI_LSB) & RDMA_REGION_3__INDI_MASK) -#define RDMA_REGION_3__NEXT_MSB 0 -#define RDMA_REGION_3__NEXT_LSB 0 -#define RDMA_REGION_3__NEXT_MASK 0x00000001 -#define RDMA_REGION_3__NEXT_GET(x) (((x) & RDMA_REGION_3__NEXT_MASK) >> RDMA_REGION_3__NEXT_LSB) -#define RDMA_REGION_3__NEXT_SET(x) (((x) << RDMA_REGION_3__NEXT_LSB) & RDMA_REGION_3__NEXT_MASK) - -#define RDMA_REGION_4__ADDRESS 0x00000030 -#define RDMA_REGION_4__OFFSET 0x00000030 -#define RDMA_REGION_4__ADDR_MSB 31 -#define RDMA_REGION_4__ADDR_LSB 13 -#define RDMA_REGION_4__ADDR_MASK 0xffffe000 -#define RDMA_REGION_4__ADDR_GET(x) (((x) & RDMA_REGION_4__ADDR_MASK) >> RDMA_REGION_4__ADDR_LSB) -#define RDMA_REGION_4__ADDR_SET(x) (((x) << RDMA_REGION_4__ADDR_LSB) & RDMA_REGION_4__ADDR_MASK) -#define RDMA_REGION_4__LENGTH_MSB 12 -#define RDMA_REGION_4__LENGTH_LSB 2 -#define RDMA_REGION_4__LENGTH_MASK 0x00001ffc -#define RDMA_REGION_4__LENGTH_GET(x) (((x) & RDMA_REGION_4__LENGTH_MASK) >> RDMA_REGION_4__LENGTH_LSB) -#define RDMA_REGION_4__LENGTH_SET(x) (((x) << RDMA_REGION_4__LENGTH_LSB) & RDMA_REGION_4__LENGTH_MASK) -#define RDMA_REGION_4__INDI_MSB 1 -#define RDMA_REGION_4__INDI_LSB 1 -#define RDMA_REGION_4__INDI_MASK 0x00000002 -#define RDMA_REGION_4__INDI_GET(x) (((x) & RDMA_REGION_4__INDI_MASK) >> RDMA_REGION_4__INDI_LSB) -#define RDMA_REGION_4__INDI_SET(x) (((x) << RDMA_REGION_4__INDI_LSB) & RDMA_REGION_4__INDI_MASK) -#define RDMA_REGION_4__NEXT_MSB 0 -#define RDMA_REGION_4__NEXT_LSB 0 -#define RDMA_REGION_4__NEXT_MASK 0x00000001 -#define RDMA_REGION_4__NEXT_GET(x) (((x) & RDMA_REGION_4__NEXT_MASK) >> RDMA_REGION_4__NEXT_LSB) -#define RDMA_REGION_4__NEXT_SET(x) (((x) << RDMA_REGION_4__NEXT_LSB) & RDMA_REGION_4__NEXT_MASK) - -#define RDMA_REGION_5__ADDRESS 0x00000034 -#define RDMA_REGION_5__OFFSET 0x00000034 -#define RDMA_REGION_5__ADDR_MSB 31 -#define RDMA_REGION_5__ADDR_LSB 13 -#define RDMA_REGION_5__ADDR_MASK 0xffffe000 -#define RDMA_REGION_5__ADDR_GET(x) (((x) & RDMA_REGION_5__ADDR_MASK) >> RDMA_REGION_5__ADDR_LSB) -#define RDMA_REGION_5__ADDR_SET(x) (((x) << RDMA_REGION_5__ADDR_LSB) & RDMA_REGION_5__ADDR_MASK) -#define RDMA_REGION_5__LENGTH_MSB 12 -#define RDMA_REGION_5__LENGTH_LSB 2 -#define RDMA_REGION_5__LENGTH_MASK 0x00001ffc -#define RDMA_REGION_5__LENGTH_GET(x) (((x) & RDMA_REGION_5__LENGTH_MASK) >> RDMA_REGION_5__LENGTH_LSB) -#define RDMA_REGION_5__LENGTH_SET(x) (((x) << RDMA_REGION_5__LENGTH_LSB) & RDMA_REGION_5__LENGTH_MASK) -#define RDMA_REGION_5__INDI_MSB 1 -#define RDMA_REGION_5__INDI_LSB 1 -#define RDMA_REGION_5__INDI_MASK 0x00000002 -#define RDMA_REGION_5__INDI_GET(x) (((x) & RDMA_REGION_5__INDI_MASK) >> RDMA_REGION_5__INDI_LSB) -#define RDMA_REGION_5__INDI_SET(x) (((x) << RDMA_REGION_5__INDI_LSB) & RDMA_REGION_5__INDI_MASK) -#define RDMA_REGION_5__NEXT_MSB 0 -#define RDMA_REGION_5__NEXT_LSB 0 -#define RDMA_REGION_5__NEXT_MASK 0x00000001 -#define RDMA_REGION_5__NEXT_GET(x) (((x) & RDMA_REGION_5__NEXT_MASK) >> RDMA_REGION_5__NEXT_LSB) -#define RDMA_REGION_5__NEXT_SET(x) (((x) << RDMA_REGION_5__NEXT_LSB) & RDMA_REGION_5__NEXT_MASK) - -#define RDMA_REGION_6__ADDRESS 0x00000038 -#define RDMA_REGION_6__OFFSET 0x00000038 -#define RDMA_REGION_6__ADDR_MSB 31 -#define RDMA_REGION_6__ADDR_LSB 13 -#define RDMA_REGION_6__ADDR_MASK 0xffffe000 -#define RDMA_REGION_6__ADDR_GET(x) (((x) & RDMA_REGION_6__ADDR_MASK) >> RDMA_REGION_6__ADDR_LSB) -#define RDMA_REGION_6__ADDR_SET(x) (((x) << RDMA_REGION_6__ADDR_LSB) & RDMA_REGION_6__ADDR_MASK) -#define RDMA_REGION_6__LENGTH_MSB 12 -#define RDMA_REGION_6__LENGTH_LSB 2 -#define RDMA_REGION_6__LENGTH_MASK 0x00001ffc -#define RDMA_REGION_6__LENGTH_GET(x) (((x) & RDMA_REGION_6__LENGTH_MASK) >> RDMA_REGION_6__LENGTH_LSB) -#define RDMA_REGION_6__LENGTH_SET(x) (((x) << RDMA_REGION_6__LENGTH_LSB) & RDMA_REGION_6__LENGTH_MASK) -#define RDMA_REGION_6__INDI_MSB 1 -#define RDMA_REGION_6__INDI_LSB 1 -#define RDMA_REGION_6__INDI_MASK 0x00000002 -#define RDMA_REGION_6__INDI_GET(x) (((x) & RDMA_REGION_6__INDI_MASK) >> RDMA_REGION_6__INDI_LSB) -#define RDMA_REGION_6__INDI_SET(x) (((x) << RDMA_REGION_6__INDI_LSB) & RDMA_REGION_6__INDI_MASK) -#define RDMA_REGION_6__NEXT_MSB 0 -#define RDMA_REGION_6__NEXT_LSB 0 -#define RDMA_REGION_6__NEXT_MASK 0x00000001 -#define RDMA_REGION_6__NEXT_GET(x) (((x) & RDMA_REGION_6__NEXT_MASK) >> RDMA_REGION_6__NEXT_LSB) -#define RDMA_REGION_6__NEXT_SET(x) (((x) << RDMA_REGION_6__NEXT_LSB) & RDMA_REGION_6__NEXT_MASK) - -#define RDMA_REGION_7__ADDRESS 0x0000003c -#define RDMA_REGION_7__OFFSET 0x0000003c -#define RDMA_REGION_7__ADDR_MSB 31 -#define RDMA_REGION_7__ADDR_LSB 13 -#define RDMA_REGION_7__ADDR_MASK 0xffffe000 -#define RDMA_REGION_7__ADDR_GET(x) (((x) & RDMA_REGION_7__ADDR_MASK) >> RDMA_REGION_7__ADDR_LSB) -#define RDMA_REGION_7__ADDR_SET(x) (((x) << RDMA_REGION_7__ADDR_LSB) & RDMA_REGION_7__ADDR_MASK) -#define RDMA_REGION_7__LENGTH_MSB 12 -#define RDMA_REGION_7__LENGTH_LSB 2 -#define RDMA_REGION_7__LENGTH_MASK 0x00001ffc -#define RDMA_REGION_7__LENGTH_GET(x) (((x) & RDMA_REGION_7__LENGTH_MASK) >> RDMA_REGION_7__LENGTH_LSB) -#define RDMA_REGION_7__LENGTH_SET(x) (((x) << RDMA_REGION_7__LENGTH_LSB) & RDMA_REGION_7__LENGTH_MASK) -#define RDMA_REGION_7__INDI_MSB 1 -#define RDMA_REGION_7__INDI_LSB 1 -#define RDMA_REGION_7__INDI_MASK 0x00000002 -#define RDMA_REGION_7__INDI_GET(x) (((x) & RDMA_REGION_7__INDI_MASK) >> RDMA_REGION_7__INDI_LSB) -#define RDMA_REGION_7__INDI_SET(x) (((x) << RDMA_REGION_7__INDI_LSB) & RDMA_REGION_7__INDI_MASK) -#define RDMA_REGION_7__NEXT_MSB 0 -#define RDMA_REGION_7__NEXT_LSB 0 -#define RDMA_REGION_7__NEXT_MASK 0x00000001 -#define RDMA_REGION_7__NEXT_GET(x) (((x) & RDMA_REGION_7__NEXT_MASK) >> RDMA_REGION_7__NEXT_LSB) -#define RDMA_REGION_7__NEXT_SET(x) (((x) << RDMA_REGION_7__NEXT_LSB) & RDMA_REGION_7__NEXT_MASK) - -#define RDMA_REGION_8__ADDRESS 0x00000040 -#define RDMA_REGION_8__OFFSET 0x00000040 -#define RDMA_REGION_8__ADDR_MSB 31 -#define RDMA_REGION_8__ADDR_LSB 13 -#define RDMA_REGION_8__ADDR_MASK 0xffffe000 -#define RDMA_REGION_8__ADDR_GET(x) (((x) & RDMA_REGION_8__ADDR_MASK) >> RDMA_REGION_8__ADDR_LSB) -#define RDMA_REGION_8__ADDR_SET(x) (((x) << RDMA_REGION_8__ADDR_LSB) & RDMA_REGION_8__ADDR_MASK) -#define RDMA_REGION_8__LENGTH_MSB 12 -#define RDMA_REGION_8__LENGTH_LSB 2 -#define RDMA_REGION_8__LENGTH_MASK 0x00001ffc -#define RDMA_REGION_8__LENGTH_GET(x) (((x) & RDMA_REGION_8__LENGTH_MASK) >> RDMA_REGION_8__LENGTH_LSB) -#define RDMA_REGION_8__LENGTH_SET(x) (((x) << RDMA_REGION_8__LENGTH_LSB) & RDMA_REGION_8__LENGTH_MASK) -#define RDMA_REGION_8__INDI_MSB 1 -#define RDMA_REGION_8__INDI_LSB 1 -#define RDMA_REGION_8__INDI_MASK 0x00000002 -#define RDMA_REGION_8__INDI_GET(x) (((x) & RDMA_REGION_8__INDI_MASK) >> RDMA_REGION_8__INDI_LSB) -#define RDMA_REGION_8__INDI_SET(x) (((x) << RDMA_REGION_8__INDI_LSB) & RDMA_REGION_8__INDI_MASK) -#define RDMA_REGION_8__NEXT_MSB 0 -#define RDMA_REGION_8__NEXT_LSB 0 -#define RDMA_REGION_8__NEXT_MASK 0x00000001 -#define RDMA_REGION_8__NEXT_GET(x) (((x) & RDMA_REGION_8__NEXT_MASK) >> RDMA_REGION_8__NEXT_LSB) -#define RDMA_REGION_8__NEXT_SET(x) (((x) << RDMA_REGION_8__NEXT_LSB) & RDMA_REGION_8__NEXT_MASK) - -#define RDMA_REGION_9__ADDRESS 0x00000044 -#define RDMA_REGION_9__OFFSET 0x00000044 -#define RDMA_REGION_9__ADDR_MSB 31 -#define RDMA_REGION_9__ADDR_LSB 13 -#define RDMA_REGION_9__ADDR_MASK 0xffffe000 -#define RDMA_REGION_9__ADDR_GET(x) (((x) & RDMA_REGION_9__ADDR_MASK) >> RDMA_REGION_9__ADDR_LSB) -#define RDMA_REGION_9__ADDR_SET(x) (((x) << RDMA_REGION_9__ADDR_LSB) & RDMA_REGION_9__ADDR_MASK) -#define RDMA_REGION_9__LENGTH_MSB 12 -#define RDMA_REGION_9__LENGTH_LSB 2 -#define RDMA_REGION_9__LENGTH_MASK 0x00001ffc -#define RDMA_REGION_9__LENGTH_GET(x) (((x) & RDMA_REGION_9__LENGTH_MASK) >> RDMA_REGION_9__LENGTH_LSB) -#define RDMA_REGION_9__LENGTH_SET(x) (((x) << RDMA_REGION_9__LENGTH_LSB) & RDMA_REGION_9__LENGTH_MASK) -#define RDMA_REGION_9__INDI_MSB 1 -#define RDMA_REGION_9__INDI_LSB 1 -#define RDMA_REGION_9__INDI_MASK 0x00000002 -#define RDMA_REGION_9__INDI_GET(x) (((x) & RDMA_REGION_9__INDI_MASK) >> RDMA_REGION_9__INDI_LSB) -#define RDMA_REGION_9__INDI_SET(x) (((x) << RDMA_REGION_9__INDI_LSB) & RDMA_REGION_9__INDI_MASK) -#define RDMA_REGION_9__NEXT_MSB 0 -#define RDMA_REGION_9__NEXT_LSB 0 -#define RDMA_REGION_9__NEXT_MASK 0x00000001 -#define RDMA_REGION_9__NEXT_GET(x) (((x) & RDMA_REGION_9__NEXT_MASK) >> RDMA_REGION_9__NEXT_LSB) -#define RDMA_REGION_9__NEXT_SET(x) (((x) << RDMA_REGION_9__NEXT_LSB) & RDMA_REGION_9__NEXT_MASK) - -#define RDMA_REGION_10__ADDRESS 0x00000048 -#define RDMA_REGION_10__OFFSET 0x00000048 -#define RDMA_REGION_10__ADDR_MSB 31 -#define RDMA_REGION_10__ADDR_LSB 13 -#define RDMA_REGION_10__ADDR_MASK 0xffffe000 -#define RDMA_REGION_10__ADDR_GET(x) (((x) & RDMA_REGION_10__ADDR_MASK) >> RDMA_REGION_10__ADDR_LSB) -#define RDMA_REGION_10__ADDR_SET(x) (((x) << RDMA_REGION_10__ADDR_LSB) & RDMA_REGION_10__ADDR_MASK) -#define RDMA_REGION_10__LENGTH_MSB 12 -#define RDMA_REGION_10__LENGTH_LSB 2 -#define RDMA_REGION_10__LENGTH_MASK 0x00001ffc -#define RDMA_REGION_10__LENGTH_GET(x) (((x) & RDMA_REGION_10__LENGTH_MASK) >> RDMA_REGION_10__LENGTH_LSB) -#define RDMA_REGION_10__LENGTH_SET(x) (((x) << RDMA_REGION_10__LENGTH_LSB) & RDMA_REGION_10__LENGTH_MASK) -#define RDMA_REGION_10__INDI_MSB 1 -#define RDMA_REGION_10__INDI_LSB 1 -#define RDMA_REGION_10__INDI_MASK 0x00000002 -#define RDMA_REGION_10__INDI_GET(x) (((x) & RDMA_REGION_10__INDI_MASK) >> RDMA_REGION_10__INDI_LSB) -#define RDMA_REGION_10__INDI_SET(x) (((x) << RDMA_REGION_10__INDI_LSB) & RDMA_REGION_10__INDI_MASK) -#define RDMA_REGION_10__NEXT_MSB 0 -#define RDMA_REGION_10__NEXT_LSB 0 -#define RDMA_REGION_10__NEXT_MASK 0x00000001 -#define RDMA_REGION_10__NEXT_GET(x) (((x) & RDMA_REGION_10__NEXT_MASK) >> RDMA_REGION_10__NEXT_LSB) -#define RDMA_REGION_10__NEXT_SET(x) (((x) << RDMA_REGION_10__NEXT_LSB) & RDMA_REGION_10__NEXT_MASK) - -#define RDMA_REGION_11__ADDRESS 0x0000004c -#define RDMA_REGION_11__OFFSET 0x0000004c -#define RDMA_REGION_11__ADDR_MSB 31 -#define RDMA_REGION_11__ADDR_LSB 13 -#define RDMA_REGION_11__ADDR_MASK 0xffffe000 -#define RDMA_REGION_11__ADDR_GET(x) (((x) & RDMA_REGION_11__ADDR_MASK) >> RDMA_REGION_11__ADDR_LSB) -#define RDMA_REGION_11__ADDR_SET(x) (((x) << RDMA_REGION_11__ADDR_LSB) & RDMA_REGION_11__ADDR_MASK) -#define RDMA_REGION_11__LENGTH_MSB 12 -#define RDMA_REGION_11__LENGTH_LSB 2 -#define RDMA_REGION_11__LENGTH_MASK 0x00001ffc -#define RDMA_REGION_11__LENGTH_GET(x) (((x) & RDMA_REGION_11__LENGTH_MASK) >> RDMA_REGION_11__LENGTH_LSB) -#define RDMA_REGION_11__LENGTH_SET(x) (((x) << RDMA_REGION_11__LENGTH_LSB) & RDMA_REGION_11__LENGTH_MASK) -#define RDMA_REGION_11__INDI_MSB 1 -#define RDMA_REGION_11__INDI_LSB 1 -#define RDMA_REGION_11__INDI_MASK 0x00000002 -#define RDMA_REGION_11__INDI_GET(x) (((x) & RDMA_REGION_11__INDI_MASK) >> RDMA_REGION_11__INDI_LSB) -#define RDMA_REGION_11__INDI_SET(x) (((x) << RDMA_REGION_11__INDI_LSB) & RDMA_REGION_11__INDI_MASK) -#define RDMA_REGION_11__NEXT_MSB 0 -#define RDMA_REGION_11__NEXT_LSB 0 -#define RDMA_REGION_11__NEXT_MASK 0x00000001 -#define RDMA_REGION_11__NEXT_GET(x) (((x) & RDMA_REGION_11__NEXT_MASK) >> RDMA_REGION_11__NEXT_LSB) -#define RDMA_REGION_11__NEXT_SET(x) (((x) << RDMA_REGION_11__NEXT_LSB) & RDMA_REGION_11__NEXT_MASK) - -#define RDMA_REGION_12__ADDRESS 0x00000050 -#define RDMA_REGION_12__OFFSET 0x00000050 -#define RDMA_REGION_12__ADDR_MSB 31 -#define RDMA_REGION_12__ADDR_LSB 13 -#define RDMA_REGION_12__ADDR_MASK 0xffffe000 -#define RDMA_REGION_12__ADDR_GET(x) (((x) & RDMA_REGION_12__ADDR_MASK) >> RDMA_REGION_12__ADDR_LSB) -#define RDMA_REGION_12__ADDR_SET(x) (((x) << RDMA_REGION_12__ADDR_LSB) & RDMA_REGION_12__ADDR_MASK) -#define RDMA_REGION_12__LENGTH_MSB 12 -#define RDMA_REGION_12__LENGTH_LSB 2 -#define RDMA_REGION_12__LENGTH_MASK 0x00001ffc -#define RDMA_REGION_12__LENGTH_GET(x) (((x) & RDMA_REGION_12__LENGTH_MASK) >> RDMA_REGION_12__LENGTH_LSB) -#define RDMA_REGION_12__LENGTH_SET(x) (((x) << RDMA_REGION_12__LENGTH_LSB) & RDMA_REGION_12__LENGTH_MASK) -#define RDMA_REGION_12__INDI_MSB 1 -#define RDMA_REGION_12__INDI_LSB 1 -#define RDMA_REGION_12__INDI_MASK 0x00000002 -#define RDMA_REGION_12__INDI_GET(x) (((x) & RDMA_REGION_12__INDI_MASK) >> RDMA_REGION_12__INDI_LSB) -#define RDMA_REGION_12__INDI_SET(x) (((x) << RDMA_REGION_12__INDI_LSB) & RDMA_REGION_12__INDI_MASK) -#define RDMA_REGION_12__NEXT_MSB 0 -#define RDMA_REGION_12__NEXT_LSB 0 -#define RDMA_REGION_12__NEXT_MASK 0x00000001 -#define RDMA_REGION_12__NEXT_GET(x) (((x) & RDMA_REGION_12__NEXT_MASK) >> RDMA_REGION_12__NEXT_LSB) -#define RDMA_REGION_12__NEXT_SET(x) (((x) << RDMA_REGION_12__NEXT_LSB) & RDMA_REGION_12__NEXT_MASK) - -#define RDMA_REGION_13__ADDRESS 0x00000054 -#define RDMA_REGION_13__OFFSET 0x00000054 -#define RDMA_REGION_13__ADDR_MSB 31 -#define RDMA_REGION_13__ADDR_LSB 13 -#define RDMA_REGION_13__ADDR_MASK 0xffffe000 -#define RDMA_REGION_13__ADDR_GET(x) (((x) & RDMA_REGION_13__ADDR_MASK) >> RDMA_REGION_13__ADDR_LSB) -#define RDMA_REGION_13__ADDR_SET(x) (((x) << RDMA_REGION_13__ADDR_LSB) & RDMA_REGION_13__ADDR_MASK) -#define RDMA_REGION_13__LENGTH_MSB 12 -#define RDMA_REGION_13__LENGTH_LSB 2 -#define RDMA_REGION_13__LENGTH_MASK 0x00001ffc -#define RDMA_REGION_13__LENGTH_GET(x) (((x) & RDMA_REGION_13__LENGTH_MASK) >> RDMA_REGION_13__LENGTH_LSB) -#define RDMA_REGION_13__LENGTH_SET(x) (((x) << RDMA_REGION_13__LENGTH_LSB) & RDMA_REGION_13__LENGTH_MASK) -#define RDMA_REGION_13__INDI_MSB 1 -#define RDMA_REGION_13__INDI_LSB 1 -#define RDMA_REGION_13__INDI_MASK 0x00000002 -#define RDMA_REGION_13__INDI_GET(x) (((x) & RDMA_REGION_13__INDI_MASK) >> RDMA_REGION_13__INDI_LSB) -#define RDMA_REGION_13__INDI_SET(x) (((x) << RDMA_REGION_13__INDI_LSB) & RDMA_REGION_13__INDI_MASK) -#define RDMA_REGION_13__NEXT_MSB 0 -#define RDMA_REGION_13__NEXT_LSB 0 -#define RDMA_REGION_13__NEXT_MASK 0x00000001 -#define RDMA_REGION_13__NEXT_GET(x) (((x) & RDMA_REGION_13__NEXT_MASK) >> RDMA_REGION_13__NEXT_LSB) -#define RDMA_REGION_13__NEXT_SET(x) (((x) << RDMA_REGION_13__NEXT_LSB) & RDMA_REGION_13__NEXT_MASK) - -#define RDMA_REGION_14__ADDRESS 0x00000058 -#define RDMA_REGION_14__OFFSET 0x00000058 -#define RDMA_REGION_14__ADDR_MSB 31 -#define RDMA_REGION_14__ADDR_LSB 13 -#define RDMA_REGION_14__ADDR_MASK 0xffffe000 -#define RDMA_REGION_14__ADDR_GET(x) (((x) & RDMA_REGION_14__ADDR_MASK) >> RDMA_REGION_14__ADDR_LSB) -#define RDMA_REGION_14__ADDR_SET(x) (((x) << RDMA_REGION_14__ADDR_LSB) & RDMA_REGION_14__ADDR_MASK) -#define RDMA_REGION_14__LENGTH_MSB 12 -#define RDMA_REGION_14__LENGTH_LSB 2 -#define RDMA_REGION_14__LENGTH_MASK 0x00001ffc -#define RDMA_REGION_14__LENGTH_GET(x) (((x) & RDMA_REGION_14__LENGTH_MASK) >> RDMA_REGION_14__LENGTH_LSB) -#define RDMA_REGION_14__LENGTH_SET(x) (((x) << RDMA_REGION_14__LENGTH_LSB) & RDMA_REGION_14__LENGTH_MASK) -#define RDMA_REGION_14__INDI_MSB 1 -#define RDMA_REGION_14__INDI_LSB 1 -#define RDMA_REGION_14__INDI_MASK 0x00000002 -#define RDMA_REGION_14__INDI_GET(x) (((x) & RDMA_REGION_14__INDI_MASK) >> RDMA_REGION_14__INDI_LSB) -#define RDMA_REGION_14__INDI_SET(x) (((x) << RDMA_REGION_14__INDI_LSB) & RDMA_REGION_14__INDI_MASK) -#define RDMA_REGION_14__NEXT_MSB 0 -#define RDMA_REGION_14__NEXT_LSB 0 -#define RDMA_REGION_14__NEXT_MASK 0x00000001 -#define RDMA_REGION_14__NEXT_GET(x) (((x) & RDMA_REGION_14__NEXT_MASK) >> RDMA_REGION_14__NEXT_LSB) -#define RDMA_REGION_14__NEXT_SET(x) (((x) << RDMA_REGION_14__NEXT_LSB) & RDMA_REGION_14__NEXT_MASK) - -#define RDMA_REGION_15__ADDRESS 0x0000005c -#define RDMA_REGION_15__OFFSET 0x0000005c -#define RDMA_REGION_15__ADDR_MSB 31 -#define RDMA_REGION_15__ADDR_LSB 13 -#define RDMA_REGION_15__ADDR_MASK 0xffffe000 -#define RDMA_REGION_15__ADDR_GET(x) (((x) & RDMA_REGION_15__ADDR_MASK) >> RDMA_REGION_15__ADDR_LSB) -#define RDMA_REGION_15__ADDR_SET(x) (((x) << RDMA_REGION_15__ADDR_LSB) & RDMA_REGION_15__ADDR_MASK) -#define RDMA_REGION_15__LENGTH_MSB 12 -#define RDMA_REGION_15__LENGTH_LSB 2 -#define RDMA_REGION_15__LENGTH_MASK 0x00001ffc -#define RDMA_REGION_15__LENGTH_GET(x) (((x) & RDMA_REGION_15__LENGTH_MASK) >> RDMA_REGION_15__LENGTH_LSB) -#define RDMA_REGION_15__LENGTH_SET(x) (((x) << RDMA_REGION_15__LENGTH_LSB) & RDMA_REGION_15__LENGTH_MASK) -#define RDMA_REGION_15__INDI_MSB 1 -#define RDMA_REGION_15__INDI_LSB 1 -#define RDMA_REGION_15__INDI_MASK 0x00000002 -#define RDMA_REGION_15__INDI_GET(x) (((x) & RDMA_REGION_15__INDI_MASK) >> RDMA_REGION_15__INDI_LSB) -#define RDMA_REGION_15__INDI_SET(x) (((x) << RDMA_REGION_15__INDI_LSB) & RDMA_REGION_15__INDI_MASK) -#define RDMA_REGION_15__NEXT_MSB 0 -#define RDMA_REGION_15__NEXT_LSB 0 -#define RDMA_REGION_15__NEXT_MASK 0x00000001 -#define RDMA_REGION_15__NEXT_GET(x) (((x) & RDMA_REGION_15__NEXT_MASK) >> RDMA_REGION_15__NEXT_LSB) -#define RDMA_REGION_15__NEXT_SET(x) (((x) << RDMA_REGION_15__NEXT_LSB) & RDMA_REGION_15__NEXT_MASK) - -#define DMA_STATUS_ADDRESS 0x00000060 -#define DMA_STATUS_OFFSET 0x00000060 -#define DMA_STATUS_ERROR_CODE_MSB 14 -#define DMA_STATUS_ERROR_CODE_LSB 4 -#define DMA_STATUS_ERROR_CODE_MASK 0x00007ff0 -#define DMA_STATUS_ERROR_CODE_GET(x) (((x) & DMA_STATUS_ERROR_CODE_MASK) >> DMA_STATUS_ERROR_CODE_LSB) -#define DMA_STATUS_ERROR_CODE_SET(x) (((x) << DMA_STATUS_ERROR_CODE_LSB) & DMA_STATUS_ERROR_CODE_MASK) -#define DMA_STATUS_ERROR_MSB 3 -#define DMA_STATUS_ERROR_LSB 3 -#define DMA_STATUS_ERROR_MASK 0x00000008 -#define DMA_STATUS_ERROR_GET(x) (((x) & DMA_STATUS_ERROR_MASK) >> DMA_STATUS_ERROR_LSB) -#define DMA_STATUS_ERROR_SET(x) (((x) << DMA_STATUS_ERROR_LSB) & DMA_STATUS_ERROR_MASK) -#define DMA_STATUS_DONE_MSB 2 -#define DMA_STATUS_DONE_LSB 2 -#define DMA_STATUS_DONE_MASK 0x00000004 -#define DMA_STATUS_DONE_GET(x) (((x) & DMA_STATUS_DONE_MASK) >> DMA_STATUS_DONE_LSB) -#define DMA_STATUS_DONE_SET(x) (((x) << DMA_STATUS_DONE_LSB) & DMA_STATUS_DONE_MASK) -#define DMA_STATUS_STOPPED_MSB 1 -#define DMA_STATUS_STOPPED_LSB 1 -#define DMA_STATUS_STOPPED_MASK 0x00000002 -#define DMA_STATUS_STOPPED_GET(x) (((x) & DMA_STATUS_STOPPED_MASK) >> DMA_STATUS_STOPPED_LSB) -#define DMA_STATUS_STOPPED_SET(x) (((x) << DMA_STATUS_STOPPED_LSB) & DMA_STATUS_STOPPED_MASK) -#define DMA_STATUS_RUNNING_MSB 0 -#define DMA_STATUS_RUNNING_LSB 0 -#define DMA_STATUS_RUNNING_MASK 0x00000001 -#define DMA_STATUS_RUNNING_GET(x) (((x) & DMA_STATUS_RUNNING_MASK) >> DMA_STATUS_RUNNING_LSB) -#define DMA_STATUS_RUNNING_SET(x) (((x) << DMA_STATUS_RUNNING_LSB) & DMA_STATUS_RUNNING_MASK) - -#define DMA_INT_EN_ADDRESS 0x00000064 -#define DMA_INT_EN_OFFSET 0x00000064 -#define DMA_INT_EN_ERROR_ENA_MSB 3 -#define DMA_INT_EN_ERROR_ENA_LSB 3 -#define DMA_INT_EN_ERROR_ENA_MASK 0x00000008 -#define DMA_INT_EN_ERROR_ENA_GET(x) (((x) & DMA_INT_EN_ERROR_ENA_MASK) >> DMA_INT_EN_ERROR_ENA_LSB) -#define DMA_INT_EN_ERROR_ENA_SET(x) (((x) << DMA_INT_EN_ERROR_ENA_LSB) & DMA_INT_EN_ERROR_ENA_MASK) -#define DMA_INT_EN_DONE_ENA_MSB 2 -#define DMA_INT_EN_DONE_ENA_LSB 2 -#define DMA_INT_EN_DONE_ENA_MASK 0x00000004 -#define DMA_INT_EN_DONE_ENA_GET(x) (((x) & DMA_INT_EN_DONE_ENA_MASK) >> DMA_INT_EN_DONE_ENA_LSB) -#define DMA_INT_EN_DONE_ENA_SET(x) (((x) << DMA_INT_EN_DONE_ENA_LSB) & DMA_INT_EN_DONE_ENA_MASK) -#define DMA_INT_EN_STOPPED_ENA_MSB 1 -#define DMA_INT_EN_STOPPED_ENA_LSB 1 -#define DMA_INT_EN_STOPPED_ENA_MASK 0x00000002 -#define DMA_INT_EN_STOPPED_ENA_GET(x) (((x) & DMA_INT_EN_STOPPED_ENA_MASK) >> DMA_INT_EN_STOPPED_ENA_LSB) -#define DMA_INT_EN_STOPPED_ENA_SET(x) (((x) << DMA_INT_EN_STOPPED_ENA_LSB) & DMA_INT_EN_STOPPED_ENA_MASK) - - -#ifndef __ASSEMBLER__ - -typedef struct rdma_reg_reg_s { - volatile unsigned int dma_config; - volatile unsigned int dma_control; - volatile unsigned int dma_src; - volatile unsigned int dma_dest; - volatile unsigned int dma_length; - volatile unsigned int vmc_base; - volatile unsigned int indirect_reg; - volatile unsigned int indirect_return; - volatile unsigned int rdma_region_0_; - volatile unsigned int rdma_region_1_; - volatile unsigned int rdma_region_2_; - volatile unsigned int rdma_region_3_; - volatile unsigned int rdma_region_4_; - volatile unsigned int rdma_region_5_; - volatile unsigned int rdma_region_6_; - volatile unsigned int rdma_region_7_; - volatile unsigned int rdma_region_8_; - volatile unsigned int rdma_region_9_; - volatile unsigned int rdma_region_10_; - volatile unsigned int rdma_region_11_; - volatile unsigned int rdma_region_12_; - volatile unsigned int rdma_region_13_; - volatile unsigned int rdma_region_14_; - volatile unsigned int rdma_region_15_; - volatile unsigned int dma_status; - volatile unsigned int dma_int_en; -} rdma_reg_reg_t; - -#endif /* __ASSEMBLER__ */ - -#endif /* _RDMA_REG_H_ */ diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/umbox_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/umbox_reg.h deleted file mode 100644 index b18ff48171a8..000000000000 --- a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/umbox_reg.h +++ /dev/null @@ -1,23 +0,0 @@ -// ------------------------------------------------------------------ -// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. -// -// -// Permission to use, copy, modify, and/or distribute this software for any -// purpose with or without fee is hereby granted, provided that the above -// copyright notice and this permission notice appear in all copies. -// -// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -// -// -// ------------------------------------------------------------------ -//=================================================================== -// Author(s): ="Atheros" -//=================================================================== - -#include "umbox_wlan_reg.h" diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/umbox_wlan_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/umbox_wlan_reg.h deleted file mode 100644 index 4737a2805b2f..000000000000 --- a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/umbox_wlan_reg.h +++ /dev/null @@ -1,322 +0,0 @@ -// ------------------------------------------------------------------ -// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. -// -// -// Permission to use, copy, modify, and/or distribute this software for any -// purpose with or without fee is hereby granted, provided that the above -// copyright notice and this permission notice appear in all copies. -// -// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -// -// -// ------------------------------------------------------------------ -//=================================================================== -// Author(s): ="Atheros" -//=================================================================== - - -#ifndef _UMBOX_WLAN_REG_REG_H_ -#define _UMBOX_WLAN_REG_REG_H_ - -#define UMBOX_FIFO_ADDRESS 0x00000000 -#define UMBOX_FIFO_OFFSET 0x00000000 -#define UMBOX_FIFO_DATA_MSB 8 -#define UMBOX_FIFO_DATA_LSB 0 -#define UMBOX_FIFO_DATA_MASK 0x000001ff -#define UMBOX_FIFO_DATA_GET(x) (((x) & UMBOX_FIFO_DATA_MASK) >> UMBOX_FIFO_DATA_LSB) -#define UMBOX_FIFO_DATA_SET(x) (((x) << UMBOX_FIFO_DATA_LSB) & UMBOX_FIFO_DATA_MASK) - -#define UMBOX_FIFO_STATUS_ADDRESS 0x00000008 -#define UMBOX_FIFO_STATUS_OFFSET 0x00000008 -#define UMBOX_FIFO_STATUS_TX_EMPTY_MSB 3 -#define UMBOX_FIFO_STATUS_TX_EMPTY_LSB 3 -#define UMBOX_FIFO_STATUS_TX_EMPTY_MASK 0x00000008 -#define UMBOX_FIFO_STATUS_TX_EMPTY_GET(x) (((x) & UMBOX_FIFO_STATUS_TX_EMPTY_MASK) >> UMBOX_FIFO_STATUS_TX_EMPTY_LSB) -#define UMBOX_FIFO_STATUS_TX_EMPTY_SET(x) (((x) << UMBOX_FIFO_STATUS_TX_EMPTY_LSB) & UMBOX_FIFO_STATUS_TX_EMPTY_MASK) -#define UMBOX_FIFO_STATUS_TX_FULL_MSB 2 -#define UMBOX_FIFO_STATUS_TX_FULL_LSB 2 -#define UMBOX_FIFO_STATUS_TX_FULL_MASK 0x00000004 -#define UMBOX_FIFO_STATUS_TX_FULL_GET(x) (((x) & UMBOX_FIFO_STATUS_TX_FULL_MASK) >> UMBOX_FIFO_STATUS_TX_FULL_LSB) -#define UMBOX_FIFO_STATUS_TX_FULL_SET(x) (((x) << UMBOX_FIFO_STATUS_TX_FULL_LSB) & UMBOX_FIFO_STATUS_TX_FULL_MASK) -#define UMBOX_FIFO_STATUS_RX_EMPTY_MSB 1 -#define UMBOX_FIFO_STATUS_RX_EMPTY_LSB 1 -#define UMBOX_FIFO_STATUS_RX_EMPTY_MASK 0x00000002 -#define UMBOX_FIFO_STATUS_RX_EMPTY_GET(x) (((x) & UMBOX_FIFO_STATUS_RX_EMPTY_MASK) >> UMBOX_FIFO_STATUS_RX_EMPTY_LSB) -#define UMBOX_FIFO_STATUS_RX_EMPTY_SET(x) (((x) << UMBOX_FIFO_STATUS_RX_EMPTY_LSB) & UMBOX_FIFO_STATUS_RX_EMPTY_MASK) -#define UMBOX_FIFO_STATUS_RX_FULL_MSB 0 -#define UMBOX_FIFO_STATUS_RX_FULL_LSB 0 -#define UMBOX_FIFO_STATUS_RX_FULL_MASK 0x00000001 -#define UMBOX_FIFO_STATUS_RX_FULL_GET(x) (((x) & UMBOX_FIFO_STATUS_RX_FULL_MASK) >> UMBOX_FIFO_STATUS_RX_FULL_LSB) -#define UMBOX_FIFO_STATUS_RX_FULL_SET(x) (((x) << UMBOX_FIFO_STATUS_RX_FULL_LSB) & UMBOX_FIFO_STATUS_RX_FULL_MASK) - -#define UMBOX_DMA_POLICY_ADDRESS 0x0000000c -#define UMBOX_DMA_POLICY_OFFSET 0x0000000c -#define UMBOX_DMA_POLICY_TX_QUANTUM_MSB 3 -#define UMBOX_DMA_POLICY_TX_QUANTUM_LSB 3 -#define UMBOX_DMA_POLICY_TX_QUANTUM_MASK 0x00000008 -#define UMBOX_DMA_POLICY_TX_QUANTUM_GET(x) (((x) & UMBOX_DMA_POLICY_TX_QUANTUM_MASK) >> UMBOX_DMA_POLICY_TX_QUANTUM_LSB) -#define UMBOX_DMA_POLICY_TX_QUANTUM_SET(x) (((x) << UMBOX_DMA_POLICY_TX_QUANTUM_LSB) & UMBOX_DMA_POLICY_TX_QUANTUM_MASK) -#define UMBOX_DMA_POLICY_TX_ORDER_MSB 2 -#define UMBOX_DMA_POLICY_TX_ORDER_LSB 2 -#define UMBOX_DMA_POLICY_TX_ORDER_MASK 0x00000004 -#define UMBOX_DMA_POLICY_TX_ORDER_GET(x) (((x) & UMBOX_DMA_POLICY_TX_ORDER_MASK) >> UMBOX_DMA_POLICY_TX_ORDER_LSB) -#define UMBOX_DMA_POLICY_TX_ORDER_SET(x) (((x) << UMBOX_DMA_POLICY_TX_ORDER_LSB) & UMBOX_DMA_POLICY_TX_ORDER_MASK) -#define UMBOX_DMA_POLICY_RX_QUANTUM_MSB 1 -#define UMBOX_DMA_POLICY_RX_QUANTUM_LSB 1 -#define UMBOX_DMA_POLICY_RX_QUANTUM_MASK 0x00000002 -#define UMBOX_DMA_POLICY_RX_QUANTUM_GET(x) (((x) & UMBOX_DMA_POLICY_RX_QUANTUM_MASK) >> UMBOX_DMA_POLICY_RX_QUANTUM_LSB) -#define UMBOX_DMA_POLICY_RX_QUANTUM_SET(x) (((x) << UMBOX_DMA_POLICY_RX_QUANTUM_LSB) & UMBOX_DMA_POLICY_RX_QUANTUM_MASK) -#define UMBOX_DMA_POLICY_RX_ORDER_MSB 0 -#define UMBOX_DMA_POLICY_RX_ORDER_LSB 0 -#define UMBOX_DMA_POLICY_RX_ORDER_MASK 0x00000001 -#define UMBOX_DMA_POLICY_RX_ORDER_GET(x) (((x) & UMBOX_DMA_POLICY_RX_ORDER_MASK) >> UMBOX_DMA_POLICY_RX_ORDER_LSB) -#define UMBOX_DMA_POLICY_RX_ORDER_SET(x) (((x) << UMBOX_DMA_POLICY_RX_ORDER_LSB) & UMBOX_DMA_POLICY_RX_ORDER_MASK) - -#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000010 -#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000010 -#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 -#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 -#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc -#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) -#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) - -#define UMBOX0_DMA_RX_CONTROL_ADDRESS 0x00000014 -#define UMBOX0_DMA_RX_CONTROL_OFFSET 0x00000014 -#define UMBOX0_DMA_RX_CONTROL_RESUME_MSB 2 -#define UMBOX0_DMA_RX_CONTROL_RESUME_LSB 2 -#define UMBOX0_DMA_RX_CONTROL_RESUME_MASK 0x00000004 -#define UMBOX0_DMA_RX_CONTROL_RESUME_GET(x) (((x) & UMBOX0_DMA_RX_CONTROL_RESUME_MASK) >> UMBOX0_DMA_RX_CONTROL_RESUME_LSB) -#define UMBOX0_DMA_RX_CONTROL_RESUME_SET(x) (((x) << UMBOX0_DMA_RX_CONTROL_RESUME_LSB) & UMBOX0_DMA_RX_CONTROL_RESUME_MASK) -#define UMBOX0_DMA_RX_CONTROL_START_MSB 1 -#define UMBOX0_DMA_RX_CONTROL_START_LSB 1 -#define UMBOX0_DMA_RX_CONTROL_START_MASK 0x00000002 -#define UMBOX0_DMA_RX_CONTROL_START_GET(x) (((x) & UMBOX0_DMA_RX_CONTROL_START_MASK) >> UMBOX0_DMA_RX_CONTROL_START_LSB) -#define UMBOX0_DMA_RX_CONTROL_START_SET(x) (((x) << UMBOX0_DMA_RX_CONTROL_START_LSB) & UMBOX0_DMA_RX_CONTROL_START_MASK) -#define UMBOX0_DMA_RX_CONTROL_STOP_MSB 0 -#define UMBOX0_DMA_RX_CONTROL_STOP_LSB 0 -#define UMBOX0_DMA_RX_CONTROL_STOP_MASK 0x00000001 -#define UMBOX0_DMA_RX_CONTROL_STOP_GET(x) (((x) & UMBOX0_DMA_RX_CONTROL_STOP_MASK) >> UMBOX0_DMA_RX_CONTROL_STOP_LSB) -#define UMBOX0_DMA_RX_CONTROL_STOP_SET(x) (((x) << UMBOX0_DMA_RX_CONTROL_STOP_LSB) & UMBOX0_DMA_RX_CONTROL_STOP_MASK) - -#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000018 -#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000018 -#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 -#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 -#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc -#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) -#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) - -#define UMBOX0_DMA_TX_CONTROL_ADDRESS 0x0000001c -#define UMBOX0_DMA_TX_CONTROL_OFFSET 0x0000001c -#define UMBOX0_DMA_TX_CONTROL_RESUME_MSB 2 -#define UMBOX0_DMA_TX_CONTROL_RESUME_LSB 2 -#define UMBOX0_DMA_TX_CONTROL_RESUME_MASK 0x00000004 -#define UMBOX0_DMA_TX_CONTROL_RESUME_GET(x) (((x) & UMBOX0_DMA_TX_CONTROL_RESUME_MASK) >> UMBOX0_DMA_TX_CONTROL_RESUME_LSB) -#define UMBOX0_DMA_TX_CONTROL_RESUME_SET(x) (((x) << UMBOX0_DMA_TX_CONTROL_RESUME_LSB) & UMBOX0_DMA_TX_CONTROL_RESUME_MASK) -#define UMBOX0_DMA_TX_CONTROL_START_MSB 1 -#define UMBOX0_DMA_TX_CONTROL_START_LSB 1 -#define UMBOX0_DMA_TX_CONTROL_START_MASK 0x00000002 -#define UMBOX0_DMA_TX_CONTROL_START_GET(x) (((x) & UMBOX0_DMA_TX_CONTROL_START_MASK) >> UMBOX0_DMA_TX_CONTROL_START_LSB) -#define UMBOX0_DMA_TX_CONTROL_START_SET(x) (((x) << UMBOX0_DMA_TX_CONTROL_START_LSB) & UMBOX0_DMA_TX_CONTROL_START_MASK) -#define UMBOX0_DMA_TX_CONTROL_STOP_MSB 0 -#define UMBOX0_DMA_TX_CONTROL_STOP_LSB 0 -#define UMBOX0_DMA_TX_CONTROL_STOP_MASK 0x00000001 -#define UMBOX0_DMA_TX_CONTROL_STOP_GET(x) (((x) & UMBOX0_DMA_TX_CONTROL_STOP_MASK) >> UMBOX0_DMA_TX_CONTROL_STOP_LSB) -#define UMBOX0_DMA_TX_CONTROL_STOP_SET(x) (((x) << UMBOX0_DMA_TX_CONTROL_STOP_LSB) & UMBOX0_DMA_TX_CONTROL_STOP_MASK) - -#define UMBOX_FIFO_TIMEOUT_ADDRESS 0x00000020 -#define UMBOX_FIFO_TIMEOUT_OFFSET 0x00000020 -#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_MSB 8 -#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_LSB 8 -#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_MASK 0x00000100 -#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_GET(x) (((x) & UMBOX_FIFO_TIMEOUT_ENABLE_SET_MASK) >> UMBOX_FIFO_TIMEOUT_ENABLE_SET_LSB) -#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_SET(x) (((x) << UMBOX_FIFO_TIMEOUT_ENABLE_SET_LSB) & UMBOX_FIFO_TIMEOUT_ENABLE_SET_MASK) -#define UMBOX_FIFO_TIMEOUT_VALUE_MSB 7 -#define UMBOX_FIFO_TIMEOUT_VALUE_LSB 0 -#define UMBOX_FIFO_TIMEOUT_VALUE_MASK 0x000000ff -#define UMBOX_FIFO_TIMEOUT_VALUE_GET(x) (((x) & UMBOX_FIFO_TIMEOUT_VALUE_MASK) >> UMBOX_FIFO_TIMEOUT_VALUE_LSB) -#define UMBOX_FIFO_TIMEOUT_VALUE_SET(x) (((x) << UMBOX_FIFO_TIMEOUT_VALUE_LSB) & UMBOX_FIFO_TIMEOUT_VALUE_MASK) - -#define UMBOX_INT_STATUS_ADDRESS 0x00000024 -#define UMBOX_INT_STATUS_OFFSET 0x00000024 -#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MSB 9 -#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_LSB 9 -#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MASK 0x00000200 -#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MASK) >> UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_LSB) -#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_LSB) & UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MASK) -#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MSB 8 -#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_LSB 8 -#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MASK 0x00000100 -#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_GET(x) (((x) & UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MASK) >> UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_LSB) -#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_SET(x) (((x) << UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_LSB) & UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MASK) -#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_MSB 7 -#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB 7 -#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK 0x00000080 -#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) (((x) & UMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> UMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) -#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) (((x) << UMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & UMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) -#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB 6 -#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB 6 -#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x00000040 -#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) -#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) -#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_MSB 5 -#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB 5 -#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK 0x00000020 -#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) (((x) & UMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> UMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) -#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) (((x) << UMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & UMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) -#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_MSB 4 -#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_LSB 4 -#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_MASK 0x00000010 -#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_GET(x) (((x) & UMBOX_INT_STATUS_HCI_SYNC_ERROR_MASK) >> UMBOX_INT_STATUS_HCI_SYNC_ERROR_LSB) -#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_SET(x) (((x) << UMBOX_INT_STATUS_HCI_SYNC_ERROR_LSB) & UMBOX_INT_STATUS_HCI_SYNC_ERROR_MASK) -#define UMBOX_INT_STATUS_TX_OVERFLOW_MSB 3 -#define UMBOX_INT_STATUS_TX_OVERFLOW_LSB 3 -#define UMBOX_INT_STATUS_TX_OVERFLOW_MASK 0x00000008 -#define UMBOX_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & UMBOX_INT_STATUS_TX_OVERFLOW_MASK) >> UMBOX_INT_STATUS_TX_OVERFLOW_LSB) -#define UMBOX_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << UMBOX_INT_STATUS_TX_OVERFLOW_LSB) & UMBOX_INT_STATUS_TX_OVERFLOW_MASK) -#define UMBOX_INT_STATUS_RX_UNDERFLOW_MSB 2 -#define UMBOX_INT_STATUS_RX_UNDERFLOW_LSB 2 -#define UMBOX_INT_STATUS_RX_UNDERFLOW_MASK 0x00000004 -#define UMBOX_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & UMBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> UMBOX_INT_STATUS_RX_UNDERFLOW_LSB) -#define UMBOX_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << UMBOX_INT_STATUS_RX_UNDERFLOW_LSB) & UMBOX_INT_STATUS_RX_UNDERFLOW_MASK) -#define UMBOX_INT_STATUS_TX_NOT_EMPTY_MSB 1 -#define UMBOX_INT_STATUS_TX_NOT_EMPTY_LSB 1 -#define UMBOX_INT_STATUS_TX_NOT_EMPTY_MASK 0x00000002 -#define UMBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) (((x) & UMBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> UMBOX_INT_STATUS_TX_NOT_EMPTY_LSB) -#define UMBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) (((x) << UMBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & UMBOX_INT_STATUS_TX_NOT_EMPTY_MASK) -#define UMBOX_INT_STATUS_RX_NOT_FULL_MSB 0 -#define UMBOX_INT_STATUS_RX_NOT_FULL_LSB 0 -#define UMBOX_INT_STATUS_RX_NOT_FULL_MASK 0x00000001 -#define UMBOX_INT_STATUS_RX_NOT_FULL_GET(x) (((x) & UMBOX_INT_STATUS_RX_NOT_FULL_MASK) >> UMBOX_INT_STATUS_RX_NOT_FULL_LSB) -#define UMBOX_INT_STATUS_RX_NOT_FULL_SET(x) (((x) << UMBOX_INT_STATUS_RX_NOT_FULL_LSB) & UMBOX_INT_STATUS_RX_NOT_FULL_MASK) - -#define UMBOX_INT_ENABLE_ADDRESS 0x00000028 -#define UMBOX_INT_ENABLE_OFFSET 0x00000028 -#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MSB 9 -#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_LSB 9 -#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MASK 0x00000200 -#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MASK) >> UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_LSB) -#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_LSB) & UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MASK) -#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MSB 8 -#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_LSB 8 -#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MASK 0x00000100 -#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_GET(x) (((x) & UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MASK) >> UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_LSB) -#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_SET(x) (((x) << UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_LSB) & UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MASK) -#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB 7 -#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB 7 -#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK 0x00000080 -#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) (((x) & UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> UMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) -#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) (((x) << UMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) -#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB 6 -#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB 6 -#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x00000040 -#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) -#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) -#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB 5 -#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB 5 -#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK 0x00000020 -#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) (((x) & UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> UMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) -#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) (((x) << UMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) -#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MSB 4 -#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_LSB 4 -#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MASK 0x00000010 -#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_GET(x) (((x) & UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MASK) >> UMBOX_INT_ENABLE_HCI_SYNC_ERROR_LSB) -#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_SET(x) (((x) << UMBOX_INT_ENABLE_HCI_SYNC_ERROR_LSB) & UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MASK) -#define UMBOX_INT_ENABLE_TX_OVERFLOW_MSB 3 -#define UMBOX_INT_ENABLE_TX_OVERFLOW_LSB 3 -#define UMBOX_INT_ENABLE_TX_OVERFLOW_MASK 0x00000008 -#define UMBOX_INT_ENABLE_TX_OVERFLOW_GET(x) (((x) & UMBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> UMBOX_INT_ENABLE_TX_OVERFLOW_LSB) -#define UMBOX_INT_ENABLE_TX_OVERFLOW_SET(x) (((x) << UMBOX_INT_ENABLE_TX_OVERFLOW_LSB) & UMBOX_INT_ENABLE_TX_OVERFLOW_MASK) -#define UMBOX_INT_ENABLE_RX_UNDERFLOW_MSB 2 -#define UMBOX_INT_ENABLE_RX_UNDERFLOW_LSB 2 -#define UMBOX_INT_ENABLE_RX_UNDERFLOW_MASK 0x00000004 -#define UMBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) (((x) & UMBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> UMBOX_INT_ENABLE_RX_UNDERFLOW_LSB) -#define UMBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) (((x) << UMBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & UMBOX_INT_ENABLE_RX_UNDERFLOW_MASK) -#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_MSB 1 -#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB 1 -#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK 0x00000002 -#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) (((x) & UMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> UMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) -#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) (((x) << UMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & UMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) -#define UMBOX_INT_ENABLE_RX_NOT_FULL_MSB 0 -#define UMBOX_INT_ENABLE_RX_NOT_FULL_LSB 0 -#define UMBOX_INT_ENABLE_RX_NOT_FULL_MASK 0x00000001 -#define UMBOX_INT_ENABLE_RX_NOT_FULL_GET(x) (((x) & UMBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> UMBOX_INT_ENABLE_RX_NOT_FULL_LSB) -#define UMBOX_INT_ENABLE_RX_NOT_FULL_SET(x) (((x) << UMBOX_INT_ENABLE_RX_NOT_FULL_LSB) & UMBOX_INT_ENABLE_RX_NOT_FULL_MASK) - -#define UMBOX_DEBUG_ADDRESS 0x0000002c -#define UMBOX_DEBUG_OFFSET 0x0000002c -#define UMBOX_DEBUG_SEL_MSB 2 -#define UMBOX_DEBUG_SEL_LSB 0 -#define UMBOX_DEBUG_SEL_MASK 0x00000007 -#define UMBOX_DEBUG_SEL_GET(x) (((x) & UMBOX_DEBUG_SEL_MASK) >> UMBOX_DEBUG_SEL_LSB) -#define UMBOX_DEBUG_SEL_SET(x) (((x) << UMBOX_DEBUG_SEL_LSB) & UMBOX_DEBUG_SEL_MASK) - -#define UMBOX_FIFO_RESET_ADDRESS 0x00000030 -#define UMBOX_FIFO_RESET_OFFSET 0x00000030 -#define UMBOX_FIFO_RESET_INIT_MSB 0 -#define UMBOX_FIFO_RESET_INIT_LSB 0 -#define UMBOX_FIFO_RESET_INIT_MASK 0x00000001 -#define UMBOX_FIFO_RESET_INIT_GET(x) (((x) & UMBOX_FIFO_RESET_INIT_MASK) >> UMBOX_FIFO_RESET_INIT_LSB) -#define UMBOX_FIFO_RESET_INIT_SET(x) (((x) << UMBOX_FIFO_RESET_INIT_LSB) & UMBOX_FIFO_RESET_INIT_MASK) - -#define UMBOX_HCI_FRAMER_ADDRESS 0x00000034 -#define UMBOX_HCI_FRAMER_OFFSET 0x00000034 -#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_MSB 6 -#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_LSB 6 -#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_MASK 0x00000040 -#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_GET(x) (((x) & UMBOX_HCI_FRAMER_CRC_OVERRIDE_MASK) >> UMBOX_HCI_FRAMER_CRC_OVERRIDE_LSB) -#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_SET(x) (((x) << UMBOX_HCI_FRAMER_CRC_OVERRIDE_LSB) & UMBOX_HCI_FRAMER_CRC_OVERRIDE_MASK) -#define UMBOX_HCI_FRAMER_ENABLE_MSB 5 -#define UMBOX_HCI_FRAMER_ENABLE_LSB 5 -#define UMBOX_HCI_FRAMER_ENABLE_MASK 0x00000020 -#define UMBOX_HCI_FRAMER_ENABLE_GET(x) (((x) & UMBOX_HCI_FRAMER_ENABLE_MASK) >> UMBOX_HCI_FRAMER_ENABLE_LSB) -#define UMBOX_HCI_FRAMER_ENABLE_SET(x) (((x) << UMBOX_HCI_FRAMER_ENABLE_LSB) & UMBOX_HCI_FRAMER_ENABLE_MASK) -#define UMBOX_HCI_FRAMER_SYNC_ERROR_MSB 4 -#define UMBOX_HCI_FRAMER_SYNC_ERROR_LSB 4 -#define UMBOX_HCI_FRAMER_SYNC_ERROR_MASK 0x00000010 -#define UMBOX_HCI_FRAMER_SYNC_ERROR_GET(x) (((x) & UMBOX_HCI_FRAMER_SYNC_ERROR_MASK) >> UMBOX_HCI_FRAMER_SYNC_ERROR_LSB) -#define UMBOX_HCI_FRAMER_SYNC_ERROR_SET(x) (((x) << UMBOX_HCI_FRAMER_SYNC_ERROR_LSB) & UMBOX_HCI_FRAMER_SYNC_ERROR_MASK) -#define UMBOX_HCI_FRAMER_UNDERFLOW_MSB 3 -#define UMBOX_HCI_FRAMER_UNDERFLOW_LSB 3 -#define UMBOX_HCI_FRAMER_UNDERFLOW_MASK 0x00000008 -#define UMBOX_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & UMBOX_HCI_FRAMER_UNDERFLOW_MASK) >> UMBOX_HCI_FRAMER_UNDERFLOW_LSB) -#define UMBOX_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << UMBOX_HCI_FRAMER_UNDERFLOW_LSB) & UMBOX_HCI_FRAMER_UNDERFLOW_MASK) -#define UMBOX_HCI_FRAMER_OVERFLOW_MSB 2 -#define UMBOX_HCI_FRAMER_OVERFLOW_LSB 2 -#define UMBOX_HCI_FRAMER_OVERFLOW_MASK 0x00000004 -#define UMBOX_HCI_FRAMER_OVERFLOW_GET(x) (((x) & UMBOX_HCI_FRAMER_OVERFLOW_MASK) >> UMBOX_HCI_FRAMER_OVERFLOW_LSB) -#define UMBOX_HCI_FRAMER_OVERFLOW_SET(x) (((x) << UMBOX_HCI_FRAMER_OVERFLOW_LSB) & UMBOX_HCI_FRAMER_OVERFLOW_MASK) -#define UMBOX_HCI_FRAMER_CONFIG_MODE_MSB 1 -#define UMBOX_HCI_FRAMER_CONFIG_MODE_LSB 0 -#define UMBOX_HCI_FRAMER_CONFIG_MODE_MASK 0x00000003 -#define UMBOX_HCI_FRAMER_CONFIG_MODE_GET(x) (((x) & UMBOX_HCI_FRAMER_CONFIG_MODE_MASK) >> UMBOX_HCI_FRAMER_CONFIG_MODE_LSB) -#define UMBOX_HCI_FRAMER_CONFIG_MODE_SET(x) (((x) << UMBOX_HCI_FRAMER_CONFIG_MODE_LSB) & UMBOX_HCI_FRAMER_CONFIG_MODE_MASK) - - -#ifndef __ASSEMBLER__ - -typedef struct umbox_wlan_reg_reg_s { - volatile unsigned int umbox_fifo[2]; - volatile unsigned int umbox_fifo_status; - volatile unsigned int umbox_dma_policy; - volatile unsigned int umbox0_dma_rx_descriptor_base; - volatile unsigned int umbox0_dma_rx_control; - volatile unsigned int umbox0_dma_tx_descriptor_base; - volatile unsigned int umbox0_dma_tx_control; - volatile unsigned int umbox_fifo_timeout; - volatile unsigned int umbox_int_status; - volatile unsigned int umbox_int_enable; - volatile unsigned int umbox_debug; - volatile unsigned int umbox_fifo_reset; - volatile unsigned int umbox_hci_framer; -} umbox_wlan_reg_reg_t; - -#endif /* __ASSEMBLER__ */ - -#endif /* _UMBOX_WLAN_REG_H_ */ |