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| author |   H Hartley Sweeten <hsweeten@visionengravers.com> | 2013-04-12 13:41:17 -0700 |
|---|---|---|
| committer |   Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2013-04-15 10:55:58 -0700 |
| commit | 4564cfd05236da2391753d13e03b8e49da5e2953 (patch) | |
| tree | 043156bf49aeb9c1dc44e2a679884e74d7eb55ab /drivers/staging/comedi/drivers/plx9052.h | |
| parent | staging: comedi: me4000: use plx9052.h defines (diff) | |
| download | linux-dev-4564cfd05236da2391753d13e03b8e49da5e2953.tar.xz linux-dev-4564cfd05236da2391753d13e03b8e49da5e2953.zip | |
staging: comedi: plx9052.h: document the CNTRL register
Add defines for the PLX 9052 CNTRL register defines and use them
instead of the magic numbers in the me4000 driver
Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Reviewed-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/staging/comedi/drivers/plx9052.h')
| -rw-r--r-- | drivers/staging/comedi/drivers/plx9052.h | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/drivers/staging/comedi/drivers/plx9052.h b/drivers/staging/comedi/drivers/plx9052.h index ab93b0b95fb7..ff76fbb4b3ef 100644 --- a/drivers/staging/comedi/drivers/plx9052.h +++ b/drivers/staging/comedi/drivers/plx9052.h @@ -44,4 +44,41 @@ #define PLX9052_INTCSR_LI2CLRINT (1 << 11) /* LI2 clear int */ #define PLX9052_INTCSR_ISAMODE (1 << 12) /* ISA interface mode */ +/* + * CNTRL - User I/O, Direct Slave Response, Serial EEPROM, and + * Initialization Control register + */ +#define PLX9052_CNTRL 0x50 +#define PLX9052_CNTRL_WAITO (1 << 0) /* UIO0 or WAITO# select */ +#define PLX9052_CNTRL_UIO0_DIR (1 << 1) /* UIO0 direction */ +#define PLX9052_CNTRL_UIO0_DATA (1 << 2) /* UIO0 data */ +#define PLX9052_CNTRL_LLOCKO (1 << 3) /* UIO1 or LLOCKo# select */ +#define PLX9052_CNTRL_UIO1_DIR (1 << 4) /* UIO1 direction */ +#define PLX9052_CNTRL_UIO1_DATA (1 << 5) /* UIO1 data */ +#define PLX9052_CNTRL_CS2 (1 << 6) /* UIO2 or CS2# select */ +#define PLX9052_CNTRL_UIO2_DIR (1 << 7) /* UIO2 direction */ +#define PLX9052_CNTRL_UIO2_DATA (1 << 8) /* UIO2 data */ +#define PLX9052_CNTRL_CS3 (1 << 9) /* UIO3 or CS3# select */ +#define PLX9052_CNTRL_UIO3_DIR (1 << 10) /* UIO3 direction */ +#define PLX9052_CNTRL_UIO3_DATA (1 << 11) /* UIO3 data */ +#define PLX9052_CNTRL_PCIBAR01 (0 << 12) /* bar 0 (mem) and 1 (I/O) */ +#define PLX9052_CNTRL_PCIBAR0 (1 << 12) /* bar 0 (mem) only */ +#define PLX9052_CNTRL_PCIBAR1 (2 << 12) /* bar 1 (I/O) only */ +#define PLX9052_CNTRL_PCI2_1_FEATURES (1 << 14) /* PCI r2.1 features enabled */ +#define PLX9052_CNTRL_PCI_R_W_FLUSH (1 << 15) /* read w/write flush mode */ +#define PLX9052_CNTRL_PCI_R_NO_FLUSH (1 << 16) /* read no flush mode */ +#define PLX9052_CNTRL_PCI_R_NO_WRITE (1 << 17) /* read no write mode */ +#define PLX9052_CNTRL_PCI_W_RELEASE (1 << 18) /* write release bus mode */ +#define PLX9052_CNTRL_RETRY_CLKS(x) (((x) & 0xf) << 19) /* slave retry clks */ +#define PLX9052_CNTRL_LOCK_ENAB (1 << 23) /* slave LOCK# enable */ +#define PLX9052_CNTRL_EEPROM_MASK (0x1f << 24) /* EEPROM bits */ +#define PLX9052_CNTRL_EEPROM_CLK (1 << 24) /* EEPROM clock */ +#define PLX9052_CNTRL_EEPROM_CS (1 << 25) /* EEPROM chip select */ +#define PLX9052_CNTRL_EEPROM_DOUT (1 << 26) /* EEPROM write bit */ +#define PLX9052_CNTRL_EEPROM_DIN (1 << 27) /* EEPROM read bit */ +#define PLX9052_CNTRL_EEPROM_PRESENT (1 << 28) /* EEPROM present */ +#define PLX9052_CNTRL_RELOAD_CFG (1 << 29) /* reload configuration */ +#define PLX9052_CNTRL_PCI_RESET (1 << 30) /* PCI adapter reset */ +#define PLX9052_CNTRL_MASK_REV (1 << 31) /* mask revision */ + #endif /* _PLX9052_H_ */ |