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| author |   Lidza Louina <lidza.louina@gmail.com> | 2013-08-26 10:53:09 -0400 |
|---|---|---|
| committer |   Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2013-08-26 16:26:55 -0700 |
| commit | 2ea550bdfad1442749e6a1353afda93c8bb7a9ac (patch) | |
| tree | 17fe575c9e859658a76d054c2ce9c4fe6429218e /drivers/staging/dgnc/dgnc_cls.h | |
| parent | staging: usbip: use DEVICE_ATTR_RO/RW for sysfs attributes (diff) | |
| download | linux-dev-2ea550bdfad1442749e6a1353afda93c8bb7a9ac.tar.xz linux-dev-2ea550bdfad1442749e6a1353afda93c8bb7a9ac.zip | |
staging: dgnc: cls_uart_struct: adds marker and changes vars' types for sparse
This patch removes these sparse warnings found in the cls.c file:
warning: incorrect type in argument 1 (different address spaces)
expected void const volatile [noderef] <asn:2>*addr
got unsigned char volatile *<noident>
warning: incorrect type in argument 2 (different address spaces)
expected void volatile [noderef] <asn:2>*addr
got unsigned char volatile *<noident>
The variables passed to readb and writeb need to
be of type u8 with a __iomem marker. These warnings
were popping up everytime the readb and writeb
functions were called with a cls_uart_struct variable.
The change made to the driver.h file adds the marker
to the cls_uart_struct and the changes in cls.h
changes its variables' types.
Signed-off-by: Lidza Louina <lidza.louina@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/staging/dgnc/dgnc_cls.h')
| -rw-r--r-- | drivers/staging/dgnc/dgnc_cls.h | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/staging/dgnc/dgnc_cls.h b/drivers/staging/dgnc/dgnc_cls.h index a27338573f75..ffe8535a84a9 100644 --- a/drivers/staging/dgnc/dgnc_cls.h +++ b/drivers/staging/dgnc/dgnc_cls.h @@ -36,14 +36,14 @@ ************************************************************************/ struct cls_uart_struct { - volatile uchar txrx; /* WR RHR/THR - Holding Reg */ - volatile uchar ier; /* WR IER - Interrupt Enable Reg */ - volatile uchar isr_fcr; /* WR ISR/FCR - Interrupt Status Reg/Fifo Control Reg */ - volatile uchar lcr; /* WR LCR - Line Control Reg */ - volatile uchar mcr; /* WR MCR - Modem Control Reg */ - volatile uchar lsr; /* WR LSR - Line Status Reg */ - volatile uchar msr; /* WR MSR - Modem Status Reg */ - volatile uchar spr; /* WR SPR - Scratch Pad Reg */ + u8 txrx; /* WR RHR/THR - Holding Reg */ + u8 ier; /* WR IER - Interrupt Enable Reg */ + u8 isr_fcr; /* WR ISR/FCR - Interrupt Status Reg/Fifo Control Reg */ + u8 lcr; /* WR LCR - Line Control Reg */ + u8 mcr; /* WR MCR - Modem Control Reg */ + u8 lsr; /* WR LSR - Line Status Reg */ + u8 msr; /* WR MSR - Modem Status Reg */ + u8 spr; /* WR SPR - Scratch Pad Reg */ }; /* Where to read the interrupt register (8bits) */ |