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| author |   Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2022-08-07 16:12:16 +0100 |
|---|---|---|
| committer | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2022-08-15 22:30:01 +0100 |
| commit | e48668a38bf420c660b07851985e6922fcf4b194 (patch) | |
| tree | 2a55cb847ed801b21bdd4b248e85f06058727b15 /drivers/staging/iio | |
| parent | iio: light: cm32181: Mark the dev_pm_ops static. (diff) | |
| download | linux-dev-e48668a38bf420c660b07851985e6922fcf4b194.tar.xz linux-dev-e48668a38bf420c660b07851985e6922fcf4b194.zip | |
staging: iio: frequency: ad9834: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20220807151218.656881-3-jic23@kernel.org
Diffstat (limited to 'drivers/staging/iio')
| -rw-r--r-- | drivers/staging/iio/frequency/ad9834.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/staging/iio/frequency/ad9834.c b/drivers/staging/iio/frequency/ad9834.c index 94b131ef8a22..2b4267a87e65 100644 --- a/drivers/staging/iio/frequency/ad9834.c +++ b/drivers/staging/iio/frequency/ad9834.c @@ -83,7 +83,7 @@ struct ad9834_state { * DMA (thus cache coherency maintenance) requires the * transfer buffers to live in their own cache lines. */ - __be16 data ____cacheline_aligned; + __be16 data __aligned(IIO_DMA_MINALIGN); __be16 freq_data[2]; }; |