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author | 2017-02-17 16:55:17 +0000 | |
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committer | 2017-03-06 09:39:54 +0100 | |
commit | a49d25364dfb9f8a64037488a39ab1f56c5fa419 (patch) | |
tree | bd97382cf06a958cef045e75334fc622500ba209 /drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/mmu_public.h | |
parent | staging: vc04_services: Removed unnecessary variable (diff) | |
download | linux-dev-a49d25364dfb9f8a64037488a39ab1f56c5fa419.tar.xz linux-dev-a49d25364dfb9f8a64037488a39ab1f56c5fa419.zip |
staging/atomisp: Add support for the Intel IPU v2
This patch adds support for the Intel IPU v2 as found on Android and IoT
Baytrail-T and Baytrail-CR platforms (those with the IPU PCI mapped). You
will also need the firmware files from your device (Android usually puts
them into /etc) - or you can find them in the downloadable restore/upgrade
kits if you blew them away for some reason.
It may be possible to extend the driver to handle the BYT/T windows
platforms such as the ASUS T100TA. These platforms don't expose the IPU via
the PCI interface but via ACPI buried in the GPU description and with the
camera information somewhere unknown so would need a platform driver
interface adding to the codebase *IFF* the firmware works on such devices.
To get good results you also need a suitable support library such as
libxcam. The camera is intended to be driven from Android so it has a lot of
features that many desktop apps don't fully spport.
In theory all the pieces are there to build it with -DISP2401 and some
differing files to get CherryTrail/T support, but unifying the drivers
properlly is a work in progress.
The IPU driver represents the work of a lot of people within Intel over many
years. It's historical goal was portability rather than Linux upstream. Any
queries about the upstream aimed driver should be sent to me not to the
original authors.
Signed-off-by: Alan Cox <alan@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/mmu_public.h')
-rw-r--r-- | drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/mmu_public.h | 82 |
1 files changed, 82 insertions, 0 deletions
diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/mmu_public.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/mmu_public.h new file mode 100644 index 000000000000..4258fa872087 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/mmu_public.h @@ -0,0 +1,82 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __MMU_PUBLIC_H_INCLUDED__ +#define __MMU_PUBLIC_H_INCLUDED__ + +#include "system_types.h" + +/*! Set the page table base index of MMU[ID] + + \param ID[in] MMU identifier + \param base_index[in] page table base index + + \return none, MMU[ID].page_table_base_index = base_index + */ +STORAGE_CLASS_EXTERN void mmu_set_page_table_base_index( + const mmu_ID_t ID, + const hrt_data base_index); + +/*! Get the page table base index of MMU[ID] + + \param ID[in] MMU identifier + \param base_index[in] page table base index + + \return MMU[ID].page_table_base_index + */ +STORAGE_CLASS_EXTERN hrt_data mmu_get_page_table_base_index( + const mmu_ID_t ID); + +/*! Invalidate the page table cache of MMU[ID] + + \param ID[in] MMU identifier + + \return none + */ +STORAGE_CLASS_EXTERN void mmu_invalidate_cache( + const mmu_ID_t ID); + + +/*! Invalidate the page table cache of all MMUs + + \return none + */ +STORAGE_CLASS_EXTERN void mmu_invalidate_cache_all(void); + +/*! Write to a control register of MMU[ID] + + \param ID[in] MMU identifier + \param reg[in] register index + \param value[in] The data to be written + + \return none, MMU[ID].ctrl[reg] = value + */ +STORAGE_CLASS_MMU_H void mmu_reg_store( + const mmu_ID_t ID, + const unsigned int reg, + const hrt_data value); + +/*! Read from a control register of MMU[ID] + + \param ID[in] MMU identifier + \param reg[in] register index + \param value[in] The data to be written + + \return MMU[ID].ctrl[reg] + */ +STORAGE_CLASS_MMU_H hrt_data mmu_reg_load( + const mmu_ID_t ID, + const unsigned int reg); + +#endif /* __MMU_PUBLIC_H_INCLUDED__ */ |