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| author |   Sergio Paracuellos <sergio.paracuellos@gmail.com> | 2020-03-21 14:36:24 +0100 |
|---|---|---|
| committer |   Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2020-03-23 11:32:43 +0100 |
| commit | 9791ca0dcb46dcedc5fb93fb4e8791cedc91babd (patch) | |
| tree | 0610fe3a58e13d2ea6bd41b4c6b0bd971fb4dd01 /drivers/staging/mt7621-pci-phy | |
| parent | staging: mt7621-pci-phy: use builtin_platform_driver() (diff) | |
| download | linux-dev-9791ca0dcb46dcedc5fb93fb4e8791cedc91babd.tar.xz linux-dev-9791ca0dcb46dcedc5fb93fb4e8791cedc91babd.zip | |
staging: mt7621-pci-phy: re-do 'xtal_mode' detection
Detection of the Xtal mode is using magic numbers that
can be avoided using properly some definitions and a more
accurate variable name from 'reg' into 'xtal_mode'. This
increase readability.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20200321133624.31388-4-sergio.paracuellos@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/staging/mt7621-pci-phy')
| -rw-r--r-- | drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c b/drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c index 8100d8286365..57743fd22be4 100644 --- a/drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c +++ b/drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c @@ -75,6 +75,9 @@ #define RG_PE1_FRC_MSTCKDIV BIT(5) +#define XTAL_MODE_SEL_SHIFT 6 +#define XTAL_MODE_SEL_MASK 0x7 + #define MAX_PHYS 2 /** @@ -136,9 +139,11 @@ static void mt7621_bypass_pipe_rst(struct mt7621_pci_phy *phy) static void mt7621_set_phy_for_ssc(struct mt7621_pci_phy *phy) { struct device *dev = phy->dev; - u32 reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0); + u32 xtal_mode; + + xtal_mode = (rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0) + >> XTAL_MODE_SEL_SHIFT) & XTAL_MODE_SEL_MASK; - reg = (reg >> 6) & 0x7; /* Set PCIe Port PHY to disable SSC */ /* Debug Xtal Type */ mt7621_phy_rmw(phy, RG_PE1_FRC_H_XTAL_REG, @@ -154,13 +159,13 @@ static void mt7621_set_phy_for_ssc(struct mt7621_pci_phy *phy) RG_PE1_PHY_EN, RG_PE1_FRC_PHY_EN); } - if (reg <= 5 && reg >= 3) { /* 40MHz Xtal */ + if (xtal_mode <= 5 && xtal_mode >= 3) { /* 40MHz Xtal */ /* Set Pre-divider ratio (for host mode) */ mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG, RG_PE1_H_PLL_PREDIV, RG_PE1_H_PLL_PREDIV_VAL(0x01)); dev_info(dev, "Xtal is 40MHz\n"); - } else if (reg >= 6) { /* 25MHz Xal */ + } else if (xtal_mode >= 6) { /* 25MHz Xal */ mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG, RG_PE1_H_PLL_PREDIV, RG_PE1_H_PLL_PREDIV_VAL(0x00)); @@ -206,7 +211,7 @@ static void mt7621_set_phy_for_ssc(struct mt7621_pci_phy *phy) mt7621_phy_rmw(phy, RG_PE1_H_PLL_BR_REG, RG_PE1_H_PLL_BR, RG_PE1_H_PLL_BR_VAL(0x00)); - if (reg <= 5 && reg >= 3) { /* 40MHz Xtal */ + if (xtal_mode <= 5 && xtal_mode >= 3) { /* 40MHz Xtal */ /* set force mode enable of da_pe1_mstckdiv */ mt7621_phy_rmw(phy, RG_PE1_MSTCKDIV_REG, RG_PE1_MSTCKDIV | RG_PE1_FRC_MSTCKDIV, |