diff options
| author |   Sergio Paracuellos <sergio.paracuellos@gmail.com> | 2018-11-04 11:49:47 +0100 |
|---|---|---|
| committer |   Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2018-11-11 11:36:15 -0800 |
| commit | 58180d33ee08b3b25255fed48cfc961ef9638bbb (patch) | |
| tree | e5b665f715e70887b097828e46153e90d3376fe1 /drivers/staging/mt7621-pci/pci-mt7621.c | |
| parent | staging: mt7621-pci: factor out 'mt7621_pcie_init_ports' function (diff) | |
| download | linux-dev-58180d33ee08b3b25255fed48cfc961ef9638bbb.tar.xz linux-dev-58180d33ee08b3b25255fed48cfc961ef9638bbb.zip | |
staging: mt7621-pci: remove unused preprocessor definitions
There are some preprocessor definition which are not being used at
all. Remove them cleaning the code a bit.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/staging/mt7621-pci/pci-mt7621.c')
| -rw-r--r-- | drivers/staging/mt7621-pci/pci-mt7621.c | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index cb677cd21792..36436b1f5272 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -43,10 +43,6 @@ #define CHIP_REV_MT7621_E2 0x0101 /* pcie */ -#define RALINK_PCIE0_CLK_EN BIT(24) -#define RALINK_PCIE1_CLK_EN BIT(25) -#define RALINK_PCIE2_CLK_EN BIT(26) - #define RALINK_PCI_CONFIG_ADDR 0x20 #define RALINK_PCI_CONFIG_DATA 0x24 #define RALINK_PCI_MEMBASE 0x28 @@ -54,9 +50,6 @@ /* RALINK_RSTCTRL bits */ #define RALINK_PCIE_RST BIT(23) -#define RALINK_PCIE0_RST BIT(24) -#define RALINK_PCIE1_RST BIT(25) -#define RALINK_PCIE2_RST BIT(26) #define RALINK_PCI_PCICFG_ADDR 0x0000 #define RALINK_PCI_PCIMSK_ADDR 0x000C @@ -79,12 +72,10 @@ #define RALINK_PCI_SUBID 0x0038 #define RALINK_PCI_STATUS 0x0050 -#define RALINK_PCI_MM_MAP_BASE 0x60000000 #define RALINK_PCI_IO_MAP_BASE 0x1e160000 #define RALINK_CLKCFG1 0x30 #define RALINK_RSTCTRL 0x34 -#define RALINK_GPIOMODE 0x60 #define RALINK_PCIE_CLK_GEN 0x7c #define RALINK_PCIE_CLK_GEN1 0x80 |