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| author |   Sergio Paracuellos <sergio.paracuellos@gmail.com> | 2018-11-04 11:49:50 +0100 |
|---|---|---|
| committer |   Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2018-11-11 11:36:16 -0800 |
| commit | ce3368dc942bdd518d599f1a452e03f81d3e9b30 (patch) | |
| tree | 2d9b4a7f8ccdb27ce8b08aaaecbc80fdb10c1d81 /drivers/staging/mt7621-pci/pci-mt7621.c | |
| parent | staging: mt7621-pci: remove non sense comment (diff) | |
| download | linux-dev-ce3368dc942bdd518d599f1a452e03f81d3e9b30.tar.xz linux-dev-ce3368dc942bdd518d599f1a452e03f81d3e9b30.zip | |
staging: mt7621-pci: align function definition style along the code
Make some function definition changes in order to get all the
functions in the code with the same style.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/staging/mt7621-pci/pci-mt7621.c')
| -rw-r--r-- | drivers/staging/mt7621-pci/pci-mt7621.c | 13 |
1 files changed, 5 insertions, 8 deletions
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index 5d151298e631..cca9a8245a30 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -235,8 +235,7 @@ struct pci_ops mt7621_pci_ops = { .write = pci_generic_config_write, }; -static u32 -read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg) +static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg) { u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg); @@ -244,8 +243,8 @@ read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg) return pcie_read(pcie, RALINK_PCI_CONFIG_DATA); } -static void -write_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg, u32 val) +static void write_config(struct mt7621_pcie *pcie, unsigned int dev, + u32 reg, u32 val) { u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg); @@ -253,8 +252,7 @@ write_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg, u32 val) pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA); } -static void -bypass_pipe_rst(struct mt7621_pcie_port *port) +static void bypass_pipe_rst(struct mt7621_pcie_port *port) { struct mt7621_pcie *pcie = port->pcie; u32 phy_offset = port->phy_reg_offset; @@ -268,8 +266,7 @@ bypass_pipe_rst(struct mt7621_pcie_port *port) pcie_write(pcie, reg, offset); } -static void -set_phy_for_ssc(struct mt7621_pcie_port *port) +static void set_phy_for_ssc(struct mt7621_pcie_port *port) { struct mt7621_pcie *pcie = port->pcie; struct device *dev = pcie->dev; |