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| author |   Sergio Paracuellos <sergio.paracuellos@gmail.com> | 2018-11-04 11:49:51 +0100 |
|---|---|---|
| committer |   Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2018-11-11 11:36:16 -0800 |
| commit | a4b2eb912bb13c3c55d2389ee7e954468d0df052 (patch) | |
| tree | 3f9c873c4b5fb018319aabd9fc5c81e4b1f9ebfc /drivers/staging/mt7621-pci | |
| parent | staging: mt7621-pci: align function definition style along the code (diff) | |
| download | linux-dev-a4b2eb912bb13c3c55d2389ee7e954468d0df052.tar.xz linux-dev-a4b2eb912bb13c3c55d2389ee7e954468d0df052.zip | |
staging: mt7621-pci: rewrite RC FTS configuration
The RC FTS configuration is done using hardcoded registers
and bitshift operations. Make it a bit clean defining some
prepocessor definitions and simple macros.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/staging/mt7621-pci')
| -rw-r--r-- | drivers/staging/mt7621-pci/pci-mt7621.c | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index cca9a8245a30..604b2871a336 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -42,6 +42,11 @@ /* RALINK_RSTCTRL bits */ #define RALINK_PCIE_RST BIT(23) +/* MediaTek specific configuration registers */ +#define PCIE_FTS_NUM 0x70c +#define PCIE_FTS_NUM_MASK GENMASK(15, 8) +#define PCIE_FTS_NUM_L0(x) ((x) & 0xff << 8) + /* rt_sysc_membase relative registers */ #define RALINK_PCIE_CLK_GEN 0x7c #define RALINK_PCIE_CLK_GEN1 0x80 @@ -591,7 +596,7 @@ static int mt7621_pcie_init_port(struct mt7621_pcie_port *port) mt7621_enable_phy(port); - val = read_config(pcie, slot, 0x70c); + val = read_config(pcie, slot, PCIE_FTS_NUM); dev_info(dev, "Port %d N_FTS = %x\n", (unsigned int)val, slot); return 0; @@ -642,10 +647,11 @@ static void mt7621_pcie_enable_ports(struct mt7621_pcie *pcie) for (slot = 0; slot < num_slots_enabled; slot++) { val = read_config(pcie, slot, 0x4); write_config(pcie, slot, 0x4, val | 0x4); - val = read_config(pcie, slot, 0x70c); - val &= ~(0xff) << 8; - val |= 0x50 << 8; - write_config(pcie, slot, 0x70c, val); + /* configure RC FTS number to 250 when it leaves L0s */ + val = read_config(pcie, slot, PCIE_FTS_NUM); + val &= ~PCIE_FTS_NUM_MASK; + val |= PCIE_FTS_NUM_L0(0x50); + write_config(pcie, slot, PCIE_FTS_NUM, val); } } |