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| author |   Sergio Paracuellos <sergio.paracuellos@gmail.com> | 2018-11-04 11:49:53 +0100 |
|---|---|---|
| committer |   Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2018-11-11 11:36:16 -0800 |
| commit | fb672b450ccced9032c58c111c6aaf6aa39ab544 (patch) | |
| tree | a217f94b7724b5bd56102892ba49addc94ce6a37 /drivers/staging/mt7621-pci | |
| parent | staging: mt7621-pci: rewrite hardcoded code for enabling ports (diff) | |
| download | linux-dev-fb672b450ccced9032c58c111c6aaf6aa39ab544.tar.xz linux-dev-fb672b450ccced9032c58c111c6aaf6aa39ab544.zip | |
staging: mt7621-pci: add some definitions for enabling and disabling GEN and GEN1 clocks
Instead of use hardcoded values when calling 'rt_sysc_m32' for enabling
and disabling RALINK_PCIE_CLK_GEN and RALINK_PCIE_CLK_GEN1 create
some preprocessor definitions.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/staging/mt7621-pci')
| -rw-r--r-- | drivers/staging/mt7621-pci/pci-mt7621.c | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index 0e898a4b7b63..0c78cc2c0440 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -87,6 +87,10 @@ #define PCIE_PORT_INT_EN(x) BIT(20 + (x)) #define PCIE_PORT_CLK_EN(x) BIT(24 + (x)) +#define PCIE_CLK_GEN_EN BIT(31) +#define PCIE_CLK_GEN_DIS 0 +#define PCIE_CLK_GEN1_DIS GENMASK(30,24) +#define PCIE_CLK_GEN1_EN (BIT(27) | BIT(25)) #define RALINK_PCI_IO_MAP_BASE 0x1e160000 #define MEMORY_BASE 0x0 @@ -815,9 +819,9 @@ static int mt7621_pci_probe(struct platform_device *pdev) rt_sysc_m32(0, RALINK_PCIE_RST, RALINK_RSTCTRL); rt_sysc_m32(0x30, 2 << 4, SYSC_REG_SYSTEM_CONFIG1); - rt_sysc_m32(0x80000000, 0, RALINK_PCIE_CLK_GEN); - rt_sysc_m32(0x7f000000, 0xa << 24, RALINK_PCIE_CLK_GEN1); - rt_sysc_m32(0, 0x80000000, RALINK_PCIE_CLK_GEN); + rt_sysc_m32(PCIE_CLK_GEN_EN, PCIE_CLK_GEN_DIS, RALINK_PCIE_CLK_GEN); + rt_sysc_m32(PCIE_CLK_GEN1_DIS, PCIE_CLK_GEN1_EN, RALINK_PCIE_CLK_GEN1); + rt_sysc_m32(PCIE_CLK_GEN_DIS, PCIE_CLK_GEN_EN, RALINK_PCIE_CLK_GEN); mdelay(50); rt_sysc_m32(RALINK_PCIE_RST, 0, RALINK_RSTCTRL); |