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authorBartlomiej Zolnierkiewicz <bzolnier@gmail.com>2009-12-11 12:23:15 -0800
committerGreg Kroah-Hartman <gregkh@suse.de>2009-12-11 12:23:15 -0800
commitcc27706961cbe2de1b2b1d1b498efa7b6f04a822 (patch)
tree3f8ff4864f56d13c3ad5a29eac81475d64620891 /drivers/staging/rt2860/chip
parentStaging: rt28x0: fix comments in sta/*.c files (diff)
downloadlinux-dev-cc27706961cbe2de1b2b1d1b498efa7b6f04a822.tar.xz
linux-dev-cc27706961cbe2de1b2b1d1b498efa7b6f04a822.zip
Staging: rt28x0: fix comments in *.h files
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/staging/rt2860/chip')
-rw-r--r--drivers/staging/rt2860/chip/mac_pci.h1
-rw-r--r--drivers/staging/rt2860/chip/mac_usb.h140
-rw-r--r--drivers/staging/rt2860/chip/rt2860.h12
-rw-r--r--drivers/staging/rt2860/chip/rt2870.h6
-rw-r--r--drivers/staging/rt2860/chip/rt3070.h10
-rw-r--r--drivers/staging/rt2860/chip/rt3090.h16
-rw-r--r--drivers/staging/rt2860/chip/rt30xx.h4
-rw-r--r--drivers/staging/rt2860/chip/rtmp_mac.h996
-rw-r--r--drivers/staging/rt2860/chip/rtmp_phy.h80
9 files changed, 632 insertions, 633 deletions
diff --git a/drivers/staging/rt2860/chip/mac_pci.h b/drivers/staging/rt2860/chip/mac_pci.h
index b0aa0d37a61e..34f7b9a302df 100644
--- a/drivers/staging/rt2860/chip/mac_pci.h
+++ b/drivers/staging/rt2860/chip/mac_pci.h
@@ -178,7 +178,6 @@ typedef union _TX_ATTENUATION_CTRL_STRUC {
#define NEED_QUEUE_BACK_FOR_AGG(pAd, QueIdx, freeNum, _TxFrameType) \
(((freeNum != (TX_RING_SIZE-1)) && (pAd->TxSwQueue[QueIdx].Number == 0)) || (freeNum<3))
- //(((freeNum) != (TX_RING_SIZE-1)) && (pAd->TxSwQueue[QueIdx].Number == 1 /*0*/))
#define HAL_KickOutMgmtTx(_pAd, _QueIdx, _pPacket, _pSrcBufVA, _SrcBufLen) \
RtmpPCIMgmtKickOut(_pAd, _QueIdx, _pPacket, _pSrcBufVA, _SrcBufLen)
diff --git a/drivers/staging/rt2860/chip/mac_usb.h b/drivers/staging/rt2860/chip/mac_usb.h
index 8ce696974921..fe7ba28b9fc6 100644
--- a/drivers/staging/rt2860/chip/mac_usb.h
+++ b/drivers/staging/rt2860/chip/mac_usb.h
@@ -46,18 +46,18 @@
#define USB_CYC_CFG 0x02a4
#define BEACON_RING_SIZE 2
-#define MGMTPIPEIDX 0 // EP6 is highest priority
+#define MGMTPIPEIDX 0 /* EP6 is highest priority */
-#define RTMP_PKT_TAIL_PADDING 11 // 3(max 4 byte padding) + 4 (last packet padding) + 4 (MaxBulkOutsize align padding)
+#define RTMP_PKT_TAIL_PADDING 11 /* 3(max 4 byte padding) + 4 (last packet padding) + 4 (MaxBulkOutsize align padding) */
#define fRTMP_ADAPTER_NEED_STOP_TX \
(fRTMP_ADAPTER_NIC_NOT_EXIST | fRTMP_ADAPTER_HALT_IN_PROGRESS | \
fRTMP_ADAPTER_RESET_IN_PROGRESS | fRTMP_ADAPTER_BULKOUT_RESET | \
fRTMP_ADAPTER_RADIO_OFF | fRTMP_ADAPTER_REMOVE_IN_PROGRESS)
-//
-// RXINFO appends at the end of each rx packet.
-//
+/* */
+/* RXINFO appends at the end of each rx packet. */
+/* */
#define RXINFO_SIZE 4
#define RT2870_RXDMALEN_FIELD_SIZE 4
@@ -66,17 +66,17 @@ typedef struct PACKED _RXINFO_STRUC {
UINT32 DATA:1;
UINT32 NULLDATA:1;
UINT32 FRAG:1;
- UINT32 U2M:1; // 1: this RX frame is unicast to me
- UINT32 Mcast:1; // 1: this is a multicast frame
- UINT32 Bcast:1; // 1: this is a broadcast frame
- UINT32 MyBss:1; // 1: this frame belongs to the same BSSID
- UINT32 Crc:1; // 1: CRC error
- UINT32 CipherErr:2; // 0: decryption okay, 1:ICV error, 2:MIC error, 3:KEY not valid
- UINT32 AMSDU:1; // rx with 802.3 header, not 802.11 header.
+ UINT32 U2M:1; /* 1: this RX frame is unicast to me */
+ UINT32 Mcast:1; /* 1: this is a multicast frame */
+ UINT32 Bcast:1; /* 1: this is a broadcast frame */
+ UINT32 MyBss:1; /* 1: this frame belongs to the same BSSID */
+ UINT32 Crc:1; /* 1: CRC error */
+ UINT32 CipherErr:2; /* 0: decryption okay, 1:ICV error, 2:MIC error, 3:KEY not valid */
+ UINT32 AMSDU:1; /* rx with 802.3 header, not 802.11 header. */
UINT32 HTC:1;
UINT32 RSSI:1;
UINT32 L2PAD:1;
- UINT32 AMPDU:1; // To be moved
+ UINT32 AMPDU:1; /* To be moved */
UINT32 Decrypted:1;
UINT32 PlcpRssil:1;
UINT32 CipherAlg:1;
@@ -84,35 +84,35 @@ typedef struct PACKED _RXINFO_STRUC {
UINT32 PlcpSignal:12;
} RXINFO_STRUC, *PRXINFO_STRUC, RT28XX_RXD_STRUC, *PRT28XX_RXD_STRUC;
-//
-// TXINFO
-//
+/* */
+/* TXINFO */
+/* */
#define TXINFO_SIZE 4
typedef struct _TXINFO_STRUC {
- // Word 0
- UINT32 USBDMATxPktLen:16; //used ONLY in USB bulk Aggregation, Total byte counts of all sub-frame.
+ /* Word 0 */
+ UINT32 USBDMATxPktLen:16; /*used ONLY in USB bulk Aggregation, Total byte counts of all sub-frame. */
UINT32 rsv:8;
- UINT32 WIV:1; // Wireless Info Valid. 1 if Driver already fill WI, o if DMA needs to copy WI to correctposition
- UINT32 QSEL:2; // select on-chip FIFO ID for 2nd-stage output scheduler.0:MGMT, 1:HCCA 2:EDCA
- UINT32 SwUseLastRound:1; // Software use.
- UINT32 rsv2:2; // Software use.
- UINT32 USBDMANextVLD:1; //used ONLY in USB bulk Aggregation, NextValid
- UINT32 USBDMATxburst:1; //used ONLY in USB bulk Aggre. Force USB DMA transmit frame from current selected endpoint
+ UINT32 WIV:1; /* Wireless Info Valid. 1 if Driver already fill WI, o if DMA needs to copy WI to correctposition */
+ UINT32 QSEL:2; /* select on-chip FIFO ID for 2nd-stage output scheduler.0:MGMT, 1:HCCA 2:EDCA */
+ UINT32 SwUseLastRound:1; /* Software use. */
+ UINT32 rsv2:2; /* Software use. */
+ UINT32 USBDMANextVLD:1; /*used ONLY in USB bulk Aggregation, NextValid */
+ UINT32 USBDMATxburst:1; /*used ONLY in USB bulk Aggre. Force USB DMA transmit frame from current selected endpoint */
} TXINFO_STRUC, *PTXINFO_STRUC;
-//
-// Management ring buffer format
-//
+/* */
+/* Management ring buffer format */
+/* */
typedef struct _MGMT_STRUC {
BOOLEAN Valid;
PUCHAR pBuffer;
ULONG Length;
} MGMT_STRUC, *PMGMT_STRUC;
-////////////////////////////////////////////////////////////////////////////
-// The TX_BUFFER structure forms the transmitted USB packet to the device
-////////////////////////////////////////////////////////////////////////////
+/*////////////////////////////////////////////////////////////////////////// */
+/* The TX_BUFFER structure forms the transmitted USB packet to the device */
+/*////////////////////////////////////////////////////////////////////////// */
typedef struct __TX_BUFFER {
union {
UCHAR WirelessPacket[TX_BUFFER_NORMSIZE];
@@ -120,7 +120,7 @@ typedef struct __TX_BUFFER {
PSPOLL_FRAME PsPollPacket;
RTS_FRAME RTSFrame;
} field;
- UCHAR Aggregation[4]; //Buffer for save Aggregation size.
+ UCHAR Aggregation[4]; /*Buffer for save Aggregation size. */
} TX_BUFFER, *PTX_BUFFER;
typedef struct __HTTX_BUFFER {
@@ -130,22 +130,22 @@ typedef struct __HTTX_BUFFER {
PSPOLL_FRAME PsPollPacket;
RTS_FRAME RTSFrame;
} field;
- UCHAR Aggregation[4]; //Buffer for save Aggregation size.
+ UCHAR Aggregation[4]; /*Buffer for save Aggregation size. */
} HTTX_BUFFER, *PHTTX_BUFFER;
-// used to track driver-generated write irps
+/* used to track driver-generated write irps */
typedef struct _TX_CONTEXT {
- PVOID pAd; //Initialized in MiniportInitialize
- PURB pUrb; //Initialized in MiniportInitialize
- PIRP pIrp; //used to cancel pending bulk out.
- //Initialized in MiniportInitialize
- PTX_BUFFER TransferBuffer; //Initialized in MiniportInitialize
+ PVOID pAd; /*Initialized in MiniportInitialize */
+ PURB pUrb; /*Initialized in MiniportInitialize */
+ PIRP pIrp; /*used to cancel pending bulk out. */
+ /*Initialized in MiniportInitialize */
+ PTX_BUFFER TransferBuffer; /*Initialized in MiniportInitialize */
ULONG BulkOutSize;
UCHAR BulkOutPipeId;
UCHAR SelfIdx;
BOOLEAN InUse;
- BOOLEAN bWaitingBulkOut; // at least one packet is in this TxContext, ready for making IRP anytime.
- BOOLEAN bFullForBulkOut; // all tx buffer are full , so waiting for tx bulkout.
+ BOOLEAN bWaitingBulkOut; /* at least one packet is in this TxContext, ready for making IRP anytime. */
+ BOOLEAN bFullForBulkOut; /* all tx buffer are full , so waiting for tx bulkout. */
BOOLEAN IRPPending;
BOOLEAN LastOne;
BOOLEAN bAggregatible;
@@ -153,18 +153,18 @@ typedef struct _TX_CONTEXT {
UCHAR Rsv[2];
ULONG DataOffset;
UINT TxRate;
- dma_addr_t data_dma; // urb dma on linux
+ dma_addr_t data_dma; /* urb dma on linux */
} TX_CONTEXT, *PTX_CONTEXT, **PPTX_CONTEXT;
-// used to track driver-generated write irps
+/* used to track driver-generated write irps */
typedef struct _HT_TX_CONTEXT {
- PVOID pAd; //Initialized in MiniportInitialize
- PURB pUrb; //Initialized in MiniportInitialize
- PIRP pIrp; //used to cancel pending bulk out.
- //Initialized in MiniportInitialize
- PHTTX_BUFFER TransferBuffer; //Initialized in MiniportInitialize
- ULONG BulkOutSize; // Indicate the total bulk-out size in bytes in one bulk-transmission
+ PVOID pAd; /*Initialized in MiniportInitialize */
+ PURB pUrb; /*Initialized in MiniportInitialize */
+ PIRP pIrp; /*used to cancel pending bulk out. */
+ /*Initialized in MiniportInitialize */
+ PHTTX_BUFFER TransferBuffer; /*Initialized in MiniportInitialize */
+ ULONG BulkOutSize; /* Indicate the total bulk-out size in bytes in one bulk-transmission */
UCHAR BulkOutPipeId;
BOOLEAN IRPPending;
BOOLEAN LastOne;
@@ -173,33 +173,33 @@ typedef struct _HT_TX_CONTEXT {
BOOLEAN bCopySavePad;
UCHAR SavedPad[8];
UCHAR Header_802_3[LENGTH_802_3];
- ULONG CurWritePosition; // Indicate the buffer offset which packet will be inserted start from.
- ULONG CurWriteRealPos; // Indicate the buffer offset which packet now are writing to.
- ULONG NextBulkOutPosition; // Indicate the buffer start offset of a bulk-transmission
- ULONG ENextBulkOutPosition; // Indicate the buffer end offset of a bulk-transmission
+ ULONG CurWritePosition; /* Indicate the buffer offset which packet will be inserted start from. */
+ ULONG CurWriteRealPos; /* Indicate the buffer offset which packet now are writing to. */
+ ULONG NextBulkOutPosition; /* Indicate the buffer start offset of a bulk-transmission */
+ ULONG ENextBulkOutPosition; /* Indicate the buffer end offset of a bulk-transmission */
UINT TxRate;
- dma_addr_t data_dma; // urb dma on linux
+ dma_addr_t data_dma; /* urb dma on linux */
} HT_TX_CONTEXT, *PHT_TX_CONTEXT, **PPHT_TX_CONTEXT;
-//
-// Structure to keep track of receive packets and buffers to indicate
-// receive data to the protocol.
-//
+/* */
+/* Structure to keep track of receive packets and buffers to indicate */
+/* receive data to the protocol. */
+/* */
typedef struct _RX_CONTEXT {
PUCHAR TransferBuffer;
PVOID pAd;
- PIRP pIrp; //used to cancel pending bulk in.
+ PIRP pIrp; /*used to cancel pending bulk in. */
PURB pUrb;
- //These 2 Boolean shouldn't both be 1 at the same time.
- ULONG BulkInOffset; // number of packets waiting for reordering .
-// BOOLEAN ReorderInUse; // At least one packet in this buffer are in reordering buffer and wait for receive indication
- BOOLEAN bRxHandling; // Notify this packet is being process now.
- BOOLEAN InUse; // USB Hardware Occupied. Wait for USB HW to put packet.
- BOOLEAN Readable; // Receive Complete back. OK for driver to indicate receiving packet.
- BOOLEAN IRPPending; // TODO: To be removed
+ /*These 2 Boolean shouldn't both be 1 at the same time. */
+ ULONG BulkInOffset; /* number of packets waiting for reordering . */
+/* BOOLEAN ReorderInUse; // At least one packet in this buffer are in reordering buffer and wait for receive indication */
+ BOOLEAN bRxHandling; /* Notify this packet is being process now. */
+ BOOLEAN InUse; /* USB Hardware Occupied. Wait for USB HW to put packet. */
+ BOOLEAN Readable; /* Receive Complete back. OK for driver to indicate receiving packet. */
+ BOOLEAN IRPPending; /* TODO: To be removed */
atomic_t IrpLock;
NDIS_SPIN_LOCK RxContextLock;
- dma_addr_t data_dma; // urb dma on linux
+ dma_addr_t data_dma; /* urb dma on linux */
} RX_CONTEXT, *PRX_CONTEXT;
/******************************************************************************
@@ -207,9 +207,9 @@ typedef struct _RX_CONTEXT {
USB Frimware Related MACRO
******************************************************************************/
-// 8051 firmware image for usb - use last-half base address = 0x3000
+/* 8051 firmware image for usb - use last-half base address = 0x3000 */
#define FIRMWARE_IMAGE_BASE 0x3000
-#define MAX_FIRMWARE_IMAGE_SIZE 0x1000 // 4kbyte
+#define MAX_FIRMWARE_IMAGE_SIZE 0x1000 /* 4kbyte */
#define RTMP_WRITE_FIRMWARE(_pAd, _pFwImage, _FwLen) \
RTUSBFirmwareWrite(_pAd, _pFwImage, _FwLen)
@@ -278,7 +278,7 @@ typedef struct _RX_CONTEXT {
#define HAL_KickOutNullFrameTx(_pAd, _QueIdx, _pNullFrame, _frameLen) \
RtmpUSBNullFrameKickOut(_pAd, _QueIdx, _pNullFrame, _frameLen)
-#define GET_TXRING_FREENO(_pAd, _QueIdx) (_QueIdx) //(_pAd->TxRing[_QueIdx].TxSwFreeIdx)
+#define GET_TXRING_FREENO(_pAd, _QueIdx) (_QueIdx) /*(_pAd->TxRing[_QueIdx].TxSwFreeIdx) */
#define GET_MGMTRING_FREENO(_pAd) (_pAd->MgmtRing.TxSwFreeIdx)
/* ----------------- RX Related MACRO ----------------- */
@@ -344,4 +344,4 @@ typedef struct _RX_CONTEXT {
#define RTMP_MLME_RADIO_OFF(pAd) \
RT28xxUsbMlmeRadioOFF(pAd);
-#endif //__MAC_USB_H__ //
+#endif /*__MAC_USB_H__ // */
diff --git a/drivers/staging/rt2860/chip/rt2860.h b/drivers/staging/rt2860/chip/rt2860.h
index 6b976b47ad8e..f30b80820b92 100644
--- a/drivers/staging/rt2860/chip/rt2860.h
+++ b/drivers/staging/rt2860/chip/rt2860.h
@@ -38,17 +38,17 @@
#error "For RT2880, you should define the compile flag -DRTMP_MAC_PCI"
#endif
-//
-// Device ID & Vendor ID, these values should match EEPROM value
-//
+/* */
+/* Device ID & Vendor ID, these values should match EEPROM value */
+/* */
#define NIC2860_PCI_DEVICE_ID 0x0601
#define NIC2860_PCIe_DEVICE_ID 0x0681
-#define NIC2760_PCI_DEVICE_ID 0x0701 // 1T/2R Cardbus ???
-#define NIC2790_PCIe_DEVICE_ID 0x0781 // 1T/2R miniCard
+#define NIC2760_PCI_DEVICE_ID 0x0701 /* 1T/2R Cardbus ??? */
+#define NIC2790_PCIe_DEVICE_ID 0x0781 /* 1T/2R miniCard */
#define VEN_AWT_PCIe_DEVICE_ID 0x1059
#define VEN_AWT_PCI_VENDOR_ID 0x1A3B
#define EDIMAX_PCI_VENDOR_ID 0x1432
-#endif //__RT2860_H__ //
+#endif /*__RT2860_H__ // */
diff --git a/drivers/staging/rt2860/chip/rt2870.h b/drivers/staging/rt2860/chip/rt2870.h
index 5115a3797e2c..8263f1baefae 100644
--- a/drivers/staging/rt2860/chip/rt2870.h
+++ b/drivers/staging/rt2860/chip/rt2870.h
@@ -40,7 +40,7 @@
#include "../rtmp_type.h"
#include "mac_usb.h"
-//#define RTMP_CHIP_NAME "RT2870"
+/*#define RTMP_CHIP_NAME "RT2870" */
-#endif // RT2870 //
-#endif //__RT2870_H__ //
+#endif /* RT2870 // */
+#endif /*__RT2870_H__ // */
diff --git a/drivers/staging/rt2860/chip/rt3070.h b/drivers/staging/rt2860/chip/rt3070.h
index 3781d9d9a927..172ce7054233 100644
--- a/drivers/staging/rt2860/chip/rt3070.h
+++ b/drivers/staging/rt2860/chip/rt3070.h
@@ -58,10 +58,10 @@
#include "mac_usb.h"
#include "rt30xx.h"
-//
-// Device ID & Vendor ID, these values should match EEPROM value
-//
+/* */
+/* Device ID & Vendor ID, these values should match EEPROM value */
+/* */
-#endif // RT3070 //
+#endif /* RT3070 // */
-#endif //__RT3070_H__ //
+#endif /*__RT3070_H__ // */
diff --git a/drivers/staging/rt2860/chip/rt3090.h b/drivers/staging/rt2860/chip/rt3090.h
index 92481ccabf38..102b938e74bd 100644
--- a/drivers/staging/rt2860/chip/rt3090.h
+++ b/drivers/staging/rt2860/chip/rt3090.h
@@ -60,13 +60,13 @@
#include "mac_pci.h"
#include "rt30xx.h"
-//
-// Device ID & Vendor ID, these values should match EEPROM value
-//
-#define NIC3090_PCIe_DEVICE_ID 0x3090 // 1T/1R miniCard
-#define NIC3091_PCIe_DEVICE_ID 0x3091 // 1T/2R miniCard
-#define NIC3092_PCIe_DEVICE_ID 0x3092 // 2T/2R miniCard
+/* */
+/* Device ID & Vendor ID, these values should match EEPROM value */
+/* */
+#define NIC3090_PCIe_DEVICE_ID 0x3090 /* 1T/1R miniCard */
+#define NIC3091_PCIe_DEVICE_ID 0x3091 /* 1T/2R miniCard */
+#define NIC3092_PCIe_DEVICE_ID 0x3092 /* 2T/2R miniCard */
-#endif // RT3090 //
+#endif /* RT3090 // */
-#endif //__RT3090_H__ //
+#endif /*__RT3090_H__ // */
diff --git a/drivers/staging/rt2860/chip/rt30xx.h b/drivers/staging/rt2860/chip/rt30xx.h
index e6aa1756b4f3..477a20509a57 100644
--- a/drivers/staging/rt2860/chip/rt30xx.h
+++ b/drivers/staging/rt2860/chip/rt30xx.h
@@ -42,6 +42,6 @@
extern REG_PAIR RT30xx_RFRegTable[];
extern UCHAR NUM_RF_REG_PARMS;
-#endif // RT30xx //
+#endif /* RT30xx // */
-#endif //__RT30XX_H__ //
+#endif /*__RT30XX_H__ // */
diff --git a/drivers/staging/rt2860/chip/rtmp_mac.h b/drivers/staging/rt2860/chip/rtmp_mac.h
index 06321c0deaf8..dac15776ae72 100644
--- a/drivers/staging/rt2860/chip/rtmp_mac.h
+++ b/drivers/staging/rt2860/chip/rtmp_mac.h
@@ -38,70 +38,70 @@
#ifndef __RTMP_MAC_H__
#define __RTMP_MAC_H__
-// =================================================================================
-// TX / RX ring descriptor format
-// =================================================================================
+/* ================================================================================= */
+/* TX / RX ring descriptor format */
+/* ================================================================================= */
-// the first 24-byte in TXD is called TXINFO and will be DMAed to MAC block through TXFIFO.
-// MAC block use this TXINFO to control the transmission behavior of this frame.
+/* the first 24-byte in TXD is called TXINFO and will be DMAed to MAC block through TXFIFO. */
+/* MAC block use this TXINFO to control the transmission behavior of this frame. */
#define FIFO_MGMT 0
#define FIFO_HCCA 1
#define FIFO_EDCA 2
-//
-// TXD Wireless Information format for Tx ring and Mgmt Ring
-//
-//txop : for txop mode
-// 0:txop for the MPDU frame will be handles by ASIC by register
-// 1/2/3:the MPDU frame is send after PIFS/backoff/SIFS
+/* */
+/* TXD Wireless Information format for Tx ring and Mgmt Ring */
+/* */
+/*txop : for txop mode */
+/* 0:txop for the MPDU frame will be handles by ASIC by register */
+/* 1/2/3:the MPDU frame is send after PIFS/backoff/SIFS */
typedef struct PACKED _TXWI_STRUC {
- // Word 0
- // ex: 00 03 00 40 means txop = 3, PHYMODE = 1
- UINT32 FRAG:1; // 1 to inform TKIP engine this is a fragment.
- UINT32 MIMOps:1; // the remote peer is in dynamic MIMO-PS mode
+ /* Word 0 */
+ /* ex: 00 03 00 40 means txop = 3, PHYMODE = 1 */
+ UINT32 FRAG:1; /* 1 to inform TKIP engine this is a fragment. */
+ UINT32 MIMOps:1; /* the remote peer is in dynamic MIMO-PS mode */
UINT32 CFACK:1;
UINT32 TS:1;
UINT32 AMPDU:1;
UINT32 MpduDensity:3;
- UINT32 txop:2; //FOR "THIS" frame. 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs only when previous frame exchange is successful.
+ UINT32 txop:2; /*FOR "THIS" frame. 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs only when previous frame exchange is successful. */
UINT32 rsv:6;
UINT32 MCS:7;
- UINT32 BW:1; //channel bandwidth 20MHz or 40 MHz
+ UINT32 BW:1; /*channel bandwidth 20MHz or 40 MHz */
UINT32 ShortGI:1;
- UINT32 STBC:2; // 1: STBC support MCS =0-7, 2,3 : RESERVE
- UINT32 Ifs:1; //
-// UINT32 rsv2:2; //channel bandwidth 20MHz or 40 MHz
+ UINT32 STBC:2; /* 1: STBC support MCS =0-7, 2,3 : RESERVE */
+ UINT32 Ifs:1; /* */
+/* UINT32 rsv2:2; //channel bandwidth 20MHz or 40 MHz */
UINT32 rsv2:1;
- UINT32 TxBF:1; // 3*3
+ UINT32 TxBF:1; /* 3*3 */
UINT32 PHYMODE:2;
- // Word1
- // ex: 1c ff 38 00 means ACK=0, BAWinSize=7, MPDUtotalByteCount = 0x38
+ /* Word1 */
+ /* ex: 1c ff 38 00 means ACK=0, BAWinSize=7, MPDUtotalByteCount = 0x38 */
UINT32 ACK:1;
UINT32 NSEQ:1;
UINT32 BAWinSize:6;
UINT32 WirelessCliID:8;
UINT32 MPDUtotalByteCount:12;
UINT32 PacketId:4;
- //Word2
+ /*Word2 */
UINT32 IV;
- //Word3
+ /*Word3 */
UINT32 EIV;
} TXWI_STRUC, *PTXWI_STRUC;
-//
-// RXWI wireless information format, in PBF. invisible in driver.
-//
+/* */
+/* RXWI wireless information format, in PBF. invisible in driver. */
+/* */
typedef struct PACKED _RXWI_STRUC {
- // Word 0
+ /* Word 0 */
UINT32 WirelessCliID:8;
UINT32 KeyIndex:2;
UINT32 BSSID:3;
UINT32 UDF:3;
UINT32 MPDUtotalByteCount:12;
UINT32 TID:4;
- // Word 1
+ /* Word 1 */
UINT32 FRAG:4;
UINT32 SEQUENCE:12;
UINT32 MCS:7;
@@ -109,29 +109,29 @@ typedef struct PACKED _RXWI_STRUC {
UINT32 ShortGI:1;
UINT32 STBC:2;
UINT32 rsv:3;
- UINT32 PHYMODE:2; // 1: this RX frame is unicast to me
- //Word2
+ UINT32 PHYMODE:2; /* 1: this RX frame is unicast to me */
+ /*Word2 */
UINT32 RSSI0:8;
UINT32 RSSI1:8;
UINT32 RSSI2:8;
UINT32 rsv1:8;
- //Word3
+ /*Word3 */
UINT32 SNR0:8;
UINT32 SNR1:8;
- UINT32 FOFFSET:8; // RT35xx
+ UINT32 FOFFSET:8; /* RT35xx */
UINT32 rsv2:8;
/*UINT32 rsv2:16; */
} RXWI_STRUC, *PRXWI_STRUC;
-// =================================================================================
-// Register format
-// =================================================================================
+/* ================================================================================= */
+/* Register format */
+/* ================================================================================= */
-//
-// SCH/DMA registers - base address 0x0200
-//
-// INT_SOURCE_CSR: Interrupt source register. Write one to clear corresponding bit
-//
+/* */
+/* SCH/DMA registers - base address 0x0200 */
+/* */
+/* INT_SOURCE_CSR: Interrupt source register. Write one to clear corresponding bit */
+/* */
#define DMA_CSR0 0x200
#define INT_SOURCE_CSR 0x200
typedef union _INT_SOURCE_CSR_STRUC {
@@ -139,29 +139,29 @@ typedef union _INT_SOURCE_CSR_STRUC {
UINT32 RxDelayINT:1;
UINT32 TxDelayINT:1;
UINT32 RxDone:1;
- UINT32 Ac0DmaDone:1; //4
+ UINT32 Ac0DmaDone:1; /*4 */
UINT32 Ac1DmaDone:1;
UINT32 Ac2DmaDone:1;
UINT32 Ac3DmaDone:1;
- UINT32 HccaDmaDone:1; // bit7
+ UINT32 HccaDmaDone:1; /* bit7 */
UINT32 MgmtDmaDone:1;
- UINT32 MCUCommandINT:1; //bit 9
+ UINT32 MCUCommandINT:1; /*bit 9 */
UINT32 RxTxCoherent:1;
UINT32 TBTTInt:1;
UINT32 PreTBTT:1;
- UINT32 TXFifoStatusInt:1; //FIFO Statistics is full, sw should read 0x171c
- UINT32 AutoWakeup:1; //bit14
+ UINT32 TXFifoStatusInt:1; /*FIFO Statistics is full, sw should read 0x171c */
+ UINT32 AutoWakeup:1; /*bit14 */
UINT32 GPTimer:1;
- UINT32 RxCoherent:1; //bit16
+ UINT32 RxCoherent:1; /*bit16 */
UINT32 TxCoherent:1;
UINT32:14;
} field;
UINT32 word;
} INT_SOURCE_CSR_STRUC, *PINT_SOURCE_CSR_STRUC;
-//
-// INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF
-//
+/* */
+/* INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF */
+/* */
#define INT_MASK_CSR 0x204
typedef union _INT_MASK_CSR_STRUC {
struct {
@@ -228,99 +228,99 @@ typedef union _DELAY_INT_CFG_STRUC {
#define WMM_AIFSN_CFG 0x0214
typedef union _AIFSN_CSR_STRUC {
struct {
- UINT32 Aifsn0:4; // for AC_BE
- UINT32 Aifsn1:4; // for AC_BK
- UINT32 Aifsn2:4; // for AC_VI
- UINT32 Aifsn3:4; // for AC_VO
+ UINT32 Aifsn0:4; /* for AC_BE */
+ UINT32 Aifsn1:4; /* for AC_BK */
+ UINT32 Aifsn2:4; /* for AC_VI */
+ UINT32 Aifsn3:4; /* for AC_VO */
UINT32 Rsv:16;
} field;
UINT32 word;
} AIFSN_CSR_STRUC, *PAIFSN_CSR_STRUC;
-//
-// CWMIN_CSR: CWmin for each EDCA AC
-//
+/* */
+/* CWMIN_CSR: CWmin for each EDCA AC */
+/* */
#define WMM_CWMIN_CFG 0x0218
typedef union _CWMIN_CSR_STRUC {
struct {
- UINT32 Cwmin0:4; // for AC_BE
- UINT32 Cwmin1:4; // for AC_BK
- UINT32 Cwmin2:4; // for AC_VI
- UINT32 Cwmin3:4; // for AC_VO
+ UINT32 Cwmin0:4; /* for AC_BE */
+ UINT32 Cwmin1:4; /* for AC_BK */
+ UINT32 Cwmin2:4; /* for AC_VI */
+ UINT32 Cwmin3:4; /* for AC_VO */
UINT32 Rsv:16;
} field;
UINT32 word;
} CWMIN_CSR_STRUC, *PCWMIN_CSR_STRUC;
-//
-// CWMAX_CSR: CWmin for each EDCA AC
-//
+/* */
+/* CWMAX_CSR: CWmin for each EDCA AC */
+/* */
#define WMM_CWMAX_CFG 0x021c
typedef union _CWMAX_CSR_STRUC {
struct {
- UINT32 Cwmax0:4; // for AC_BE
- UINT32 Cwmax1:4; // for AC_BK
- UINT32 Cwmax2:4; // for AC_VI
- UINT32 Cwmax3:4; // for AC_VO
+ UINT32 Cwmax0:4; /* for AC_BE */
+ UINT32 Cwmax1:4; /* for AC_BK */
+ UINT32 Cwmax2:4; /* for AC_VI */
+ UINT32 Cwmax3:4; /* for AC_VO */
UINT32 Rsv:16;
} field;
UINT32 word;
} CWMAX_CSR_STRUC, *PCWMAX_CSR_STRUC;
-//
-// AC_TXOP_CSR0: AC_BK/AC_BE TXOP register
-//
+/* */
+/* AC_TXOP_CSR0: AC_BK/AC_BE TXOP register */
+/* */
#define WMM_TXOP0_CFG 0x0220
typedef union _AC_TXOP_CSR0_STRUC {
struct {
- USHORT Ac0Txop; // for AC_BK, in unit of 32us
- USHORT Ac1Txop; // for AC_BE, in unit of 32us
+ USHORT Ac0Txop; /* for AC_BK, in unit of 32us */
+ USHORT Ac1Txop; /* for AC_BE, in unit of 32us */
} field;
UINT32 word;
} AC_TXOP_CSR0_STRUC, *PAC_TXOP_CSR0_STRUC;
-//
-// AC_TXOP_CSR1: AC_VO/AC_VI TXOP register
-//
+/* */
+/* AC_TXOP_CSR1: AC_VO/AC_VI TXOP register */
+/* */
#define WMM_TXOP1_CFG 0x0224
typedef union _AC_TXOP_CSR1_STRUC {
struct {
- USHORT Ac2Txop; // for AC_VI, in unit of 32us
- USHORT Ac3Txop; // for AC_VO, in unit of 32us
+ USHORT Ac2Txop; /* for AC_VI, in unit of 32us */
+ USHORT Ac3Txop; /* for AC_VO, in unit of 32us */
} field;
UINT32 word;
} AC_TXOP_CSR1_STRUC, *PAC_TXOP_CSR1_STRUC;
#define RINGREG_DIFF 0x10
-#define GPIO_CTRL_CFG 0x0228 //MAC_CSR13
+#define GPIO_CTRL_CFG 0x0228 /*MAC_CSR13 */
#define MCU_CMD_CFG 0x022c
-#define TX_BASE_PTR0 0x0230 //AC_BK base address
+#define TX_BASE_PTR0 0x0230 /*AC_BK base address */
#define TX_MAX_CNT0 0x0234
#define TX_CTX_IDX0 0x0238
#define TX_DTX_IDX0 0x023c
-#define TX_BASE_PTR1 0x0240 //AC_BE base address
+#define TX_BASE_PTR1 0x0240 /*AC_BE base address */
#define TX_MAX_CNT1 0x0244
#define TX_CTX_IDX1 0x0248
#define TX_DTX_IDX1 0x024c
-#define TX_BASE_PTR2 0x0250 //AC_VI base address
+#define TX_BASE_PTR2 0x0250 /*AC_VI base address */
#define TX_MAX_CNT2 0x0254
#define TX_CTX_IDX2 0x0258
#define TX_DTX_IDX2 0x025c
-#define TX_BASE_PTR3 0x0260 //AC_VO base address
+#define TX_BASE_PTR3 0x0260 /*AC_VO base address */
#define TX_MAX_CNT3 0x0264
#define TX_CTX_IDX3 0x0268
#define TX_DTX_IDX3 0x026c
-#define TX_BASE_PTR4 0x0270 //HCCA base address
+#define TX_BASE_PTR4 0x0270 /*HCCA base address */
#define TX_MAX_CNT4 0x0274
#define TX_CTX_IDX4 0x0278
#define TX_DTX_IDX4 0x027c
-#define TX_BASE_PTR5 0x0280 //MGMT base address
+#define TX_BASE_PTR5 0x0280 /*MGMT base address */
#define TX_MAX_CNT5 0x0284
#define TX_CTX_IDX5 0x0288
#define TX_DTX_IDX5 0x028c
#define TX_MGMTMAX_CNT TX_MAX_CNT5
#define TX_MGMTCTX_IDX TX_CTX_IDX5
#define TX_MGMTDTX_IDX TX_DTX_IDX5
-#define RX_BASE_PTR 0x0290 //RX base address
+#define RX_BASE_PTR 0x0290 /*RX base address */
#define RX_MAX_CNT 0x0294
#define RX_CRX_IDX 0x0298
#define RX_DRX_IDX 0x029c
@@ -328,27 +328,27 @@ typedef union _AC_TXOP_CSR1_STRUC {
#define USB_DMA_CFG 0x02a0
typedef union _USB_DMA_CFG_STRUC {
struct {
- UINT32 RxBulkAggTOut:8; //Rx Bulk Aggregation TimeOut in unit of 33ns
- UINT32 RxBulkAggLmt:8; //Rx Bulk Aggregation Limit in unit of 256 bytes
- UINT32 phyclear:1; //phy watch dog enable. write 1
+ UINT32 RxBulkAggTOut:8; /*Rx Bulk Aggregation TimeOut in unit of 33ns */
+ UINT32 RxBulkAggLmt:8; /*Rx Bulk Aggregation Limit in unit of 256 bytes */
+ UINT32 phyclear:1; /*phy watch dog enable. write 1 */
UINT32 rsv:2;
- UINT32 TxClear:1; //Clear USB DMA TX path
- UINT32 TxopHalt:1; //Halt TXOP count down when TX buffer is full.
- UINT32 RxBulkAggEn:1; //Enable Rx Bulk Aggregation
- UINT32 RxBulkEn:1; //Enable USB DMA Rx
- UINT32 TxBulkEn:1; //Enable USB DMA Tx
- UINT32 EpoutValid:6; //OUT endpoint data valid
- UINT32 RxBusy:1; //USB DMA RX FSM busy
- UINT32 TxBusy:1; //USB DMA TX FSM busy
+ UINT32 TxClear:1; /*Clear USB DMA TX path */
+ UINT32 TxopHalt:1; /*Halt TXOP count down when TX buffer is full. */
+ UINT32 RxBulkAggEn:1; /*Enable Rx Bulk Aggregation */
+ UINT32 RxBulkEn:1; /*Enable USB DMA Rx */
+ UINT32 TxBulkEn:1; /*Enable USB DMA Tx */
+ UINT32 EpoutValid:6; /*OUT endpoint data valid */
+ UINT32 RxBusy:1; /*USB DMA RX FSM busy */
+ UINT32 TxBusy:1; /*USB DMA TX FSM busy */
} field;
UINT32 word;
} USB_DMA_CFG_STRUC, *PUSB_DMA_CFG_STRUC;
-//
-// 3 PBF registers
-//
-//
-// Most are for debug. Driver doesn't touch PBF register.
+/* */
+/* 3 PBF registers */
+/* */
+/* */
+/* Most are for debug. Driver doesn't touch PBF register. */
#define PBF_SYS_CTRL 0x0400
#define PBF_CFG 0x0408
#define PBF_MAX_PCNT 0x040C
@@ -361,224 +361,224 @@ typedef union _USB_DMA_CFG_STRUC {
#ifdef RT30xx
#ifdef RTMP_EFUSE_SUPPORT
-// eFuse registers
+/* eFuse registers */
#define EFUSE_CTRL 0x0580
#define EFUSE_DATA0 0x0590
#define EFUSE_DATA1 0x0594
#define EFUSE_DATA2 0x0598
#define EFUSE_DATA3 0x059c
-#endif // RTMP_EFUSE_SUPPORT //
-#endif // RT30xx //
+#endif /* RTMP_EFUSE_SUPPORT // */
+#endif /* RT30xx // */
#define OSC_CTRL 0x5a4
#define PCIE_PHY_TX_ATTENUATION_CTRL 0x05C8
#define LDO_CFG0 0x05d4
#define GPIO_SWITCH 0x05dc
-//
-// 4 MAC registers
-//
-//
-// 4.1 MAC SYSTEM configuration registers (offset:0x1000)
-//
+/* */
+/* 4 MAC registers */
+/* */
+/* */
+/* 4.1 MAC SYSTEM configuration registers (offset:0x1000) */
+/* */
#define MAC_CSR0 0x1000
typedef union _ASIC_VER_ID_STRUC {
struct {
- USHORT ASICRev; // reversion : 0
- USHORT ASICVer; // version : 2860
+ USHORT ASICRev; /* reversion : 0 */
+ USHORT ASICVer; /* version : 2860 */
} field;
UINT32 word;
} ASIC_VER_ID_STRUC, *PASIC_VER_ID_STRUC;
-#define MAC_SYS_CTRL 0x1004 //MAC_CSR1
-#define MAC_ADDR_DW0 0x1008 // MAC ADDR DW0
-#define MAC_ADDR_DW1 0x100c // MAC ADDR DW1
-//
-// MAC_CSR2: STA MAC register 0
-//
+#define MAC_SYS_CTRL 0x1004 /*MAC_CSR1 */
+#define MAC_ADDR_DW0 0x1008 /* MAC ADDR DW0 */
+#define MAC_ADDR_DW1 0x100c /* MAC ADDR DW1 */
+/* */
+/* MAC_CSR2: STA MAC register 0 */
+/* */
typedef union _MAC_DW0_STRUC {
struct {
- UCHAR Byte0; // MAC address byte 0
- UCHAR Byte1; // MAC address byte 1
- UCHAR Byte2; // MAC address byte 2
- UCHAR Byte3; // MAC address byte 3
+ UCHAR Byte0; /* MAC address byte 0 */
+ UCHAR Byte1; /* MAC address byte 1 */
+ UCHAR Byte2; /* MAC address byte 2 */
+ UCHAR Byte3; /* MAC address byte 3 */
} field;
UINT32 word;
} MAC_DW0_STRUC, *PMAC_DW0_STRUC;
-//
-// MAC_CSR3: STA MAC register 1
-//
+/* */
+/* MAC_CSR3: STA MAC register 1 */
+/* */
typedef union _MAC_DW1_STRUC {
struct {
- UCHAR Byte4; // MAC address byte 4
- UCHAR Byte5; // MAC address byte 5
+ UCHAR Byte4; /* MAC address byte 4 */
+ UCHAR Byte5; /* MAC address byte 5 */
UCHAR U2MeMask;
UCHAR Rsvd1;
} field;
UINT32 word;
} MAC_DW1_STRUC, *PMAC_DW1_STRUC;
-#define MAC_BSSID_DW0 0x1010 // MAC BSSID DW0
-#define MAC_BSSID_DW1 0x1014 // MAC BSSID DW1
+#define MAC_BSSID_DW0 0x1010 /* MAC BSSID DW0 */
+#define MAC_BSSID_DW1 0x1014 /* MAC BSSID DW1 */
-//
-// MAC_CSR5: BSSID register 1
-//
+/* */
+/* MAC_CSR5: BSSID register 1 */
+/* */
typedef union _MAC_CSR5_STRUC {
struct {
- UCHAR Byte4; // BSSID byte 4
- UCHAR Byte5; // BSSID byte 5
- USHORT BssIdMask:2; // 0: one BSSID, 10: 4 BSSID, 01: 2 BSSID , 11: 8BSSID
+ UCHAR Byte4; /* BSSID byte 4 */
+ UCHAR Byte5; /* BSSID byte 5 */
+ USHORT BssIdMask:2; /* 0: one BSSID, 10: 4 BSSID, 01: 2 BSSID , 11: 8BSSID */
USHORT MBssBcnNum:3;
USHORT Rsvd:11;
} field;
UINT32 word;
} MAC_CSR5_STRUC, *PMAC_CSR5_STRUC;
-#define MAX_LEN_CFG 0x1018 // rt2860b max 16k bytes. bit12:13 Maximum PSDU length (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
-#define BBP_CSR_CFG 0x101c //
-//
-// BBP_CSR_CFG: BBP serial control register
-//
+#define MAX_LEN_CFG 0x1018 /* rt2860b max 16k bytes. bit12:13 Maximum PSDU length (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16 */
+#define BBP_CSR_CFG 0x101c /* */
+/* */
+/* BBP_CSR_CFG: BBP serial control register */
+/* */
typedef union _BBP_CSR_CFG_STRUC {
struct {
- UINT32 Value:8; // Register value to program into BBP
- UINT32 RegNum:8; // Selected BBP register
- UINT32 fRead:1; // 0: Write BBP, 1: Read BBP
- UINT32 Busy:1; // 1: ASIC is busy execute BBP programming.
- UINT32 BBP_PAR_DUR:1; // 0: 4 MAC clock cycles 1: 8 MAC clock cycles
- UINT32 BBP_RW_MODE:1; // 0: use serial mode 1:parallel
+ UINT32 Value:8; /* Register value to program into BBP */
+ UINT32 RegNum:8; /* Selected BBP register */
+ UINT32 fRead:1; /* 0: Write BBP, 1: Read BBP */
+ UINT32 Busy:1; /* 1: ASIC is busy execute BBP programming. */
+ UINT32 BBP_PAR_DUR:1; /* 0: 4 MAC clock cycles 1: 8 MAC clock cycles */
+ UINT32 BBP_RW_MODE:1; /* 0: use serial mode 1:parallel */
UINT32:12;
} field;
UINT32 word;
} BBP_CSR_CFG_STRUC, *PBBP_CSR_CFG_STRUC;
#define RF_CSR_CFG0 0x1020
-//
-// RF_CSR_CFG: RF control register
-//
+/* */
+/* RF_CSR_CFG: RF control register */
+/* */
typedef union _RF_CSR_CFG0_STRUC {
struct {
- UINT32 RegIdAndContent:24; // Register value to program into BBP
- UINT32 bitwidth:5; // Selected BBP register
- UINT32 StandbyMode:1; // 0: high when stand by 1: low when standby
- UINT32 Sel:1; // 0:RF_LE0 activate 1:RF_LE1 activate
- UINT32 Busy:1; // 0: idle 1: 8busy
+ UINT32 RegIdAndContent:24; /* Register value to program into BBP */
+ UINT32 bitwidth:5; /* Selected BBP register */
+ UINT32 StandbyMode:1; /* 0: high when stand by 1: low when standby */
+ UINT32 Sel:1; /* 0:RF_LE0 activate 1:RF_LE1 activate */
+ UINT32 Busy:1; /* 0: idle 1: 8busy */
} field;
UINT32 word;
} RF_CSR_CFG0_STRUC, *PRF_CSR_CFG0_STRUC;
#define RF_CSR_CFG1 0x1024
typedef union _RF_CSR_CFG1_STRUC {
struct {
- UINT32 RegIdAndContent:24; // Register value to program into BBP
- UINT32 RFGap:5; // Gap between BB_CONTROL_RF and RF_LE. 0: 3 system clock cycle (37.5usec) 1: 5 system clock cycle (62.5usec)
- UINT32 rsv:7; // 0: idle 1: 8busy
+ UINT32 RegIdAndContent:24; /* Register value to program into BBP */
+ UINT32 RFGap:5; /* Gap between BB_CONTROL_RF and RF_LE. 0: 3 system clock cycle (37.5usec) 1: 5 system clock cycle (62.5usec) */
+ UINT32 rsv:7; /* 0: idle 1: 8busy */
} field;
UINT32 word;
} RF_CSR_CFG1_STRUC, *PRF_CSR_CFG1_STRUC;
-#define RF_CSR_CFG2 0x1028 //
+#define RF_CSR_CFG2 0x1028 /* */
typedef union _RF_CSR_CFG2_STRUC {
struct {
- UINT32 RegIdAndContent:24; // Register value to program into BBP
- UINT32 rsv:8; // 0: idle 1: 8busy
+ UINT32 RegIdAndContent:24; /* Register value to program into BBP */
+ UINT32 rsv:8; /* 0: idle 1: 8busy */
} field;
UINT32 word;
} RF_CSR_CFG2_STRUC, *PRF_CSR_CFG2_STRUC;
-#define LED_CFG 0x102c // MAC_CSR14
+#define LED_CFG 0x102c /* MAC_CSR14 */
typedef union _LED_CFG_STRUC {
struct {
- UINT32 OnPeriod:8; // blinking on period unit 1ms
- UINT32 OffPeriod:8; // blinking off period unit 1ms
- UINT32 SlowBlinkPeriod:6; // slow blinking period. unit:1ms
+ UINT32 OnPeriod:8; /* blinking on period unit 1ms */
+ UINT32 OffPeriod:8; /* blinking off period unit 1ms */
+ UINT32 SlowBlinkPeriod:6; /* slow blinking period. unit:1ms */
UINT32 rsv:2;
- UINT32 RLedMode:2; // red Led Mode 0: off1: blinking upon TX2: periodic slow blinking3: always on
- UINT32 GLedMode:2; // green Led Mode
- UINT32 YLedMode:2; // yellow Led Mode
- UINT32 LedPolar:1; // Led Polarity. 0: active low1: active high
+ UINT32 RLedMode:2; /* red Led Mode 0: off1: blinking upon TX2: periodic slow blinking3: always on */
+ UINT32 GLedMode:2; /* green Led Mode */
+ UINT32 YLedMode:2; /* yellow Led Mode */
+ UINT32 LedPolar:1; /* Led Polarity. 0: active low1: active high */
UINT32:1;
} field;
UINT32 word;
} LED_CFG_STRUC, *PLED_CFG_STRUC;
-//
-// 4.2 MAC TIMING configuration registers (offset:0x1100)
-//
-#define XIFS_TIME_CFG 0x1100 // MAC_CSR8 MAC_CSR9
+/* */
+/* 4.2 MAC TIMING configuration registers (offset:0x1100) */
+/* */
+#define XIFS_TIME_CFG 0x1100 /* MAC_CSR8 MAC_CSR9 */
typedef union _IFS_SLOT_CFG_STRUC {
struct {
- UINT32 CckmSifsTime:8; // unit 1us. Applied after CCK RX/TX
- UINT32 OfdmSifsTime:8; // unit 1us. Applied after OFDM RX/TX
- UINT32 OfdmXifsTime:4; //OFDM SIFS. unit 1us. Applied after OFDM RX when MAC doesn't reference BBP signal BBRXEND
- UINT32 EIFS:9; // unit 1us
- UINT32 BBRxendEnable:1; // reference RXEND signal to begin XIFS defer
+ UINT32 CckmSifsTime:8; /* unit 1us. Applied after CCK RX/TX */
+ UINT32 OfdmSifsTime:8; /* unit 1us. Applied after OFDM RX/TX */
+ UINT32 OfdmXifsTime:4; /*OFDM SIFS. unit 1us. Applied after OFDM RX when MAC doesn't reference BBP signal BBRXEND */
+ UINT32 EIFS:9; /* unit 1us */
+ UINT32 BBRxendEnable:1; /* reference RXEND signal to begin XIFS defer */
UINT32 rsv:2;
} field;
UINT32 word;
} IFS_SLOT_CFG_STRUC, *PIFS_SLOT_CFG_STRUC;
-#define BKOFF_SLOT_CFG 0x1104 // mac_csr9 last 8 bits
-#define NAV_TIME_CFG 0x1108 // NAV (MAC_CSR15)
-#define CH_TIME_CFG 0x110C // Count as channel busy
-#define PBF_LIFE_TIMER 0x1110 //TX/RX MPDU timestamp timer (free run)Unit: 1us
-#define BCN_TIME_CFG 0x1114 // TXRX_CSR9
+#define BKOFF_SLOT_CFG 0x1104 /* mac_csr9 last 8 bits */
+#define NAV_TIME_CFG 0x1108 /* NAV (MAC_CSR15) */
+#define CH_TIME_CFG 0x110C /* Count as channel busy */
+#define PBF_LIFE_TIMER 0x1110 /*TX/RX MPDU timestamp timer (free run)Unit: 1us */
+#define BCN_TIME_CFG 0x1114 /* TXRX_CSR9 */
#define BCN_OFFSET0 0x042C
#define BCN_OFFSET1 0x0430
-//
-// BCN_TIME_CFG : Synchronization control register
-//
+/* */
+/* BCN_TIME_CFG : Synchronization control register */
+/* */
typedef union _BCN_TIME_CFG_STRUC {
struct {
- UINT32 BeaconInterval:16; // in unit of 1/16 TU
- UINT32 bTsfTicking:1; // Enable TSF auto counting
- UINT32 TsfSyncMode:2; // Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
+ UINT32 BeaconInterval:16; /* in unit of 1/16 TU */
+ UINT32 bTsfTicking:1; /* Enable TSF auto counting */
+ UINT32 TsfSyncMode:2; /* Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode */
UINT32 bTBTTEnable:1;
- UINT32 bBeaconGen:1; // Enable beacon generator
+ UINT32 bBeaconGen:1; /* Enable beacon generator */
UINT32:3;
UINT32 TxTimestampCompensate:8;
} field;
UINT32 word;
} BCN_TIME_CFG_STRUC, *PBCN_TIME_CFG_STRUC;
-#define TBTT_SYNC_CFG 0x1118 // txrx_csr10
-#define TSF_TIMER_DW0 0x111C // Local TSF timer lsb 32 bits. Read-only
-#define TSF_TIMER_DW1 0x1120 // msb 32 bits. Read-only.
-#define TBTT_TIMER 0x1124 // TImer remains till next TBTT. Read-only. TXRX_CSR14
-#define INT_TIMER_CFG 0x1128 //
-#define INT_TIMER_EN 0x112c // GP-timer and pre-tbtt Int enable
-#define CH_IDLE_STA 0x1130 // channel idle time
-#define CH_BUSY_STA 0x1134 // channle busy time
-//
-// 4.2 MAC POWER configuration registers (offset:0x1200)
-//
-#define MAC_STATUS_CFG 0x1200 // old MAC_CSR12
-#define PWR_PIN_CFG 0x1204 // old MAC_CSR12
-#define AUTO_WAKEUP_CFG 0x1208 // old MAC_CSR10
-//
-// AUTO_WAKEUP_CFG: Manual power control / status register
-//
+#define TBTT_SYNC_CFG 0x1118 /* txrx_csr10 */
+#define TSF_TIMER_DW0 0x111C /* Local TSF timer lsb 32 bits. Read-only */
+#define TSF_TIMER_DW1 0x1120 /* msb 32 bits. Read-only. */
+#define TBTT_TIMER 0x1124 /* TImer remains till next TBTT. Read-only. TXRX_CSR14 */
+#define INT_TIMER_CFG 0x1128 /* */
+#define INT_TIMER_EN 0x112c /* GP-timer and pre-tbtt Int enable */
+#define CH_IDLE_STA 0x1130 /* channel idle time */
+#define CH_BUSY_STA 0x1134 /* channle busy time */
+/* */
+/* 4.2 MAC POWER configuration registers (offset:0x1200) */
+/* */
+#define MAC_STATUS_CFG 0x1200 /* old MAC_CSR12 */
+#define PWR_PIN_CFG 0x1204 /* old MAC_CSR12 */
+#define AUTO_WAKEUP_CFG 0x1208 /* old MAC_CSR10 */
+/* */
+/* AUTO_WAKEUP_CFG: Manual power control / status register */
+/* */
typedef union _AUTO_WAKEUP_STRUC {
struct {
UINT32 AutoLeadTime:8;
- UINT32 NumofSleepingTbtt:7; // ForceWake has high privilege than PutToSleep when both set
- UINT32 EnableAutoWakeup:1; // 0:sleep, 1:awake
+ UINT32 NumofSleepingTbtt:7; /* ForceWake has high privilege than PutToSleep when both set */
+ UINT32 EnableAutoWakeup:1; /* 0:sleep, 1:awake */
UINT32:16;
} field;
UINT32 word;
} AUTO_WAKEUP_STRUC, *PAUTO_WAKEUP_STRUC;
-//
-// 4.3 MAC TX configuration registers (offset:0x1300)
-//
+/* */
+/* 4.3 MAC TX configuration registers (offset:0x1300) */
+/* */
-#define EDCA_AC0_CFG 0x1300 //AC_TXOP_CSR0 0x3474
+#define EDCA_AC0_CFG 0x1300 /*AC_TXOP_CSR0 0x3474 */
#define EDCA_AC1_CFG 0x1304
#define EDCA_AC2_CFG 0x1308
#define EDCA_AC3_CFG 0x130c
typedef union _EDCA_AC_CFG_STRUC {
struct {
- UINT32 AcTxop:8; // in unit of 32us
- UINT32 Aifsn:4; // # of slot time
- UINT32 Cwmin:4; //
- UINT32 Cwmax:4; //unit power of 2
- UINT32:12; //
+ UINT32 AcTxop:8; /* in unit of 32us */
+ UINT32 Aifsn:4; /* # of slot time */
+ UINT32 Cwmin:4; /* */
+ UINT32 Cwmax:4; /*unit power of 2 */
+ UINT32:12; /* */
} field;
UINT32 word;
} EDCA_AC_CFG_STRUC, *PEDCA_AC_CFG_STRUC;
@@ -590,7 +590,7 @@ typedef union _EDCA_AC_CFG_STRUC {
#define TX_PWR_CFG_3 0x1320
#define TX_PWR_CFG_4 0x1324
#define TX_PIN_CFG 0x1328
-#define TX_BAND_CFG 0x132c // 0x1 use upper 20MHz. 0 juse lower 20MHz
+#define TX_BAND_CFG 0x132c /* 0x1 use upper 20MHz. 0 juse lower 20MHz */
#define TX_SW_CFG0 0x1330
#define TX_SW_CFG1 0x1334
#define TX_SW_CFG2 0x1338
@@ -601,9 +601,9 @@ typedef union _EDCA_AC_CFG_STRUC {
typedef union _TX_RTS_CFG_STRUC {
struct {
UINT32 AutoRtsRetryLimit:8;
- UINT32 RtsThres:16; // unit:byte
- UINT32 RtsFbkEn:1; // enable rts rate fallback
- UINT32 rsv:7; // 1: HT non-STBC control frame enable
+ UINT32 RtsThres:16; /* unit:byte */
+ UINT32 RtsFbkEn:1; /* enable rts rate fallback */
+ UINT32 rsv:7; /* 1: HT non-STBC control frame enable */
} field;
UINT32 word;
} TX_RTS_CFG_STRUC, *PTX_RTS_CFG_STRUC;
@@ -611,38 +611,38 @@ typedef union _TX_RTS_CFG_STRUC {
typedef union _TX_TIMEOUT_CFG_STRUC {
struct {
UINT32 rsv:4;
- UINT32 MpduLifeTime:4; // expiration time = 2^(9+MPDU LIFE TIME) us
- UINT32 RxAckTimeout:8; // unit:slot. Used for TX precedure
- UINT32 TxopTimeout:8; //TXOP timeout value for TXOP truncation. It is recommended that (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
- UINT32 rsv2:8; // 1: HT non-STBC control frame enable
+ UINT32 MpduLifeTime:4; /* expiration time = 2^(9+MPDU LIFE TIME) us */
+ UINT32 RxAckTimeout:8; /* unit:slot. Used for TX precedure */
+ UINT32 TxopTimeout:8; /*TXOP timeout value for TXOP truncation. It is recommended that (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT) */
+ UINT32 rsv2:8; /* 1: HT non-STBC control frame enable */
} field;
UINT32 word;
} TX_TIMEOUT_CFG_STRUC, *PTX_TIMEOUT_CFG_STRUC;
#define TX_RTY_CFG 0x134c
typedef union PACKED _TX_RTY_CFG_STRUC {
struct {
- UINT32 ShortRtyLimit:8; // short retry limit
- UINT32 LongRtyLimit:8; //long retry limit
- UINT32 LongRtyThre:12; // Long retry threshoold
- UINT32 NonAggRtyMode:1; // Non-Aggregate MPDU retry mode. 0:expired by retry limit, 1: expired by mpdu life timer
- UINT32 AggRtyMode:1; // Aggregate MPDU retry mode. 0:expired by retry limit, 1: expired by mpdu life timer
- UINT32 TxautoFBEnable:1; // Tx retry PHY rate auto fallback enable
- UINT32 rsv:1; // 1: HT non-STBC control frame enable
+ UINT32 ShortRtyLimit:8; /* short retry limit */
+ UINT32 LongRtyLimit:8; /*long retry limit */
+ UINT32 LongRtyThre:12; /* Long retry threshoold */
+ UINT32 NonAggRtyMode:1; /* Non-Aggregate MPDU retry mode. 0:expired by retry limit, 1: expired by mpdu life timer */
+ UINT32 AggRtyMode:1; /* Aggregate MPDU retry mode. 0:expired by retry limit, 1: expired by mpdu life timer */
+ UINT32 TxautoFBEnable:1; /* Tx retry PHY rate auto fallback enable */
+ UINT32 rsv:1; /* 1: HT non-STBC control frame enable */
} field;
UINT32 word;
} TX_RTY_CFG_STRUC, *PTX_RTY_CFG_STRUC;
#define TX_LINK_CFG 0x1350
typedef union PACKED _TX_LINK_CFG_STRUC {
struct PACKED {
- UINT32 RemoteMFBLifeTime:8; //remote MFB life time. unit : 32us
- UINT32 MFBEnable:1; // TX apply remote MFB 1:enable
- UINT32 RemoteUMFSEnable:1; // remote unsolicit MFB enable. 0: not apply remote remote unsolicit (MFS=7)
- UINT32 TxMRQEn:1; // MCS request TX enable
- UINT32 TxRDGEn:1; // RDG TX enable
- UINT32 TxCFAckEn:1; // Piggyback CF-ACK enable
- UINT32 rsv:3; //
- UINT32 RemotMFB:8; // remote MCS feedback
- UINT32 RemotMFS:8; //remote MCS feedback sequence number
+ UINT32 RemoteMFBLifeTime:8; /*remote MFB life time. unit : 32us */
+ UINT32 MFBEnable:1; /* TX apply remote MFB 1:enable */
+ UINT32 RemoteUMFSEnable:1; /* remote unsolicit MFB enable. 0: not apply remote remote unsolicit (MFS=7) */
+ UINT32 TxMRQEn:1; /* MCS request TX enable */
+ UINT32 TxRDGEn:1; /* RDG TX enable */
+ UINT32 TxCFAckEn:1; /* Piggyback CF-ACK enable */
+ UINT32 rsv:3; /* */
+ UINT32 RemotMFB:8; /* remote MCS feedback */
+ UINT32 RemotMFS:8; /*remote MCS feedback sequence number */
} field;
UINT32 word;
} TX_LINK_CFG_STRUC, *PTX_LINK_CFG_STRUC;
@@ -677,116 +677,116 @@ typedef union _HT_FBK_CFG1_STRUC {
#define LG_FBK_CFG0 0x135c
typedef union _LG_FBK_CFG0_STRUC {
struct {
- UINT32 OFDMMCS0FBK:4; //initial value is 0
- UINT32 OFDMMCS1FBK:4; //initial value is 0
- UINT32 OFDMMCS2FBK:4; //initial value is 1
- UINT32 OFDMMCS3FBK:4; //initial value is 2
- UINT32 OFDMMCS4FBK:4; //initial value is 3
- UINT32 OFDMMCS5FBK:4; //initial value is 4
- UINT32 OFDMMCS6FBK:4; //initial value is 5
- UINT32 OFDMMCS7FBK:4; //initial value is 6
+ UINT32 OFDMMCS0FBK:4; /*initial value is 0 */
+ UINT32 OFDMMCS1FBK:4; /*initial value is 0 */
+ UINT32 OFDMMCS2FBK:4; /*initial value is 1 */
+ UINT32 OFDMMCS3FBK:4; /*initial value is 2 */
+ UINT32 OFDMMCS4FBK:4; /*initial value is 3 */
+ UINT32 OFDMMCS5FBK:4; /*initial value is 4 */
+ UINT32 OFDMMCS6FBK:4; /*initial value is 5 */
+ UINT32 OFDMMCS7FBK:4; /*initial value is 6 */
} field;
UINT32 word;
} LG_FBK_CFG0_STRUC, *PLG_FBK_CFG0_STRUC;
#define LG_FBK_CFG1 0x1360
typedef union _LG_FBK_CFG1_STRUC {
struct {
- UINT32 CCKMCS0FBK:4; //initial value is 0
- UINT32 CCKMCS1FBK:4; //initial value is 0
- UINT32 CCKMCS2FBK:4; //initial value is 1
- UINT32 CCKMCS3FBK:4; //initial value is 2
+ UINT32 CCKMCS0FBK:4; /*initial value is 0 */
+ UINT32 CCKMCS1FBK:4; /*initial value is 0 */
+ UINT32 CCKMCS2FBK:4; /*initial value is 1 */
+ UINT32 CCKMCS3FBK:4; /*initial value is 2 */
UINT32 rsv:16;
} field;
UINT32 word;
} LG_FBK_CFG1_STRUC, *PLG_FBK_CFG1_STRUC;
-//=======================================================
-//================ Protection Paramater================================
-//=======================================================
-#define CCK_PROT_CFG 0x1364 //CCK Protection
+/*======================================================= */
+/*================ Protection Paramater================================ */
+/*======================================================= */
+#define CCK_PROT_CFG 0x1364 /*CCK Protection */
#define ASIC_SHORTNAV 1
#define ASIC_LONGNAV 2
#define ASIC_RTS 1
#define ASIC_CTS 2
typedef union _PROT_CFG_STRUC {
struct {
- UINT32 ProtectRate:16; //Protection control frame rate for CCK TX(RTS/CTS/CFEnd).
- UINT32 ProtectCtrl:2; //Protection control frame type for CCK TX. 1:RTS/CTS, 2:CTS-to-self, 0:None, 3:rsv
- UINT32 ProtectNav:2; //TXOP protection type for CCK TX. 0:None, 1:ShortNAVprotect, 2:LongNAVProtect, 3:rsv
- UINT32 TxopAllowCck:1; //CCK TXOP allowance.0:disallow.
- UINT32 TxopAllowOfdm:1; //CCK TXOP allowance.0:disallow.
- UINT32 TxopAllowMM20:1; //CCK TXOP allowance. 0:disallow.
- UINT32 TxopAllowMM40:1; //CCK TXOP allowance.0:disallow.
- UINT32 TxopAllowGF20:1; //CCK TXOP allowance.0:disallow.
- UINT32 TxopAllowGF40:1; //CCK TXOP allowance.0:disallow.
- UINT32 RTSThEn:1; //RTS threshold enable on CCK TX
+ UINT32 ProtectRate:16; /*Protection control frame rate for CCK TX(RTS/CTS/CFEnd). */
+ UINT32 ProtectCtrl:2; /*Protection control frame type for CCK TX. 1:RTS/CTS, 2:CTS-to-self, 0:None, 3:rsv */
+ UINT32 ProtectNav:2; /*TXOP protection type for CCK TX. 0:None, 1:ShortNAVprotect, 2:LongNAVProtect, 3:rsv */
+ UINT32 TxopAllowCck:1; /*CCK TXOP allowance.0:disallow. */
+ UINT32 TxopAllowOfdm:1; /*CCK TXOP allowance.0:disallow. */
+ UINT32 TxopAllowMM20:1; /*CCK TXOP allowance. 0:disallow. */
+ UINT32 TxopAllowMM40:1; /*CCK TXOP allowance.0:disallow. */
+ UINT32 TxopAllowGF20:1; /*CCK TXOP allowance.0:disallow. */
+ UINT32 TxopAllowGF40:1; /*CCK TXOP allowance.0:disallow. */
+ UINT32 RTSThEn:1; /*RTS threshold enable on CCK TX */
UINT32 rsv:5;
} field;
UINT32 word;
} PROT_CFG_STRUC, *PPROT_CFG_STRUC;
-#define OFDM_PROT_CFG 0x1368 //OFDM Protection
-#define MM20_PROT_CFG 0x136C //MM20 Protection
-#define MM40_PROT_CFG 0x1370 //MM40 Protection
-#define GF20_PROT_CFG 0x1374 //GF20 Protection
-#define GF40_PROT_CFG 0x1378 //GR40 Protection
-#define EXP_CTS_TIME 0x137C //
-#define EXP_ACK_TIME 0x1380 //
-
-//
-// 4.4 MAC RX configuration registers (offset:0x1400)
-//
-#define RX_FILTR_CFG 0x1400 //TXRX_CSR0
-#define AUTO_RSP_CFG 0x1404 //TXRX_CSR4
-//
-// TXRX_CSR4: Auto-Responder/
-//
+#define OFDM_PROT_CFG 0x1368 /*OFDM Protection */
+#define MM20_PROT_CFG 0x136C /*MM20 Protection */
+#define MM40_PROT_CFG 0x1370 /*MM40 Protection */
+#define GF20_PROT_CFG 0x1374 /*GF20 Protection */
+#define GF40_PROT_CFG 0x1378 /*GR40 Protection */
+#define EXP_CTS_TIME 0x137C /* */
+#define EXP_ACK_TIME 0x1380 /* */
+
+/* */
+/* 4.4 MAC RX configuration registers (offset:0x1400) */
+/* */
+#define RX_FILTR_CFG 0x1400 /*TXRX_CSR0 */
+#define AUTO_RSP_CFG 0x1404 /*TXRX_CSR4 */
+/* */
+/* TXRX_CSR4: Auto-Responder/ */
+/* */
typedef union _AUTO_RSP_CFG_STRUC {
struct {
UINT32 AutoResponderEnable:1;
- UINT32 BACAckPolicyEnable:1; // 0:long, 1:short preamble
- UINT32 CTS40MMode:1; // Response CTS 40MHz duplicate mode
- UINT32 CTS40MRef:1; // Response CTS 40MHz duplicate mode
- UINT32 AutoResponderPreamble:1; // 0:long, 1:short preamble
- UINT32 rsv:1; // Power bit value in conrtrol frame
- UINT32 DualCTSEn:1; // Power bit value in conrtrol frame
- UINT32 AckCtsPsmBit:1; // Power bit value in conrtrol frame
+ UINT32 BACAckPolicyEnable:1; /* 0:long, 1:short preamble */
+ UINT32 CTS40MMode:1; /* Response CTS 40MHz duplicate mode */
+ UINT32 CTS40MRef:1; /* Response CTS 40MHz duplicate mode */
+ UINT32 AutoResponderPreamble:1; /* 0:long, 1:short preamble */
+ UINT32 rsv:1; /* Power bit value in conrtrol frame */
+ UINT32 DualCTSEn:1; /* Power bit value in conrtrol frame */
+ UINT32 AckCtsPsmBit:1; /* Power bit value in conrtrol frame */
UINT32:24;
} field;
UINT32 word;
} AUTO_RSP_CFG_STRUC, *PAUTO_RSP_CFG_STRUC;
-#define LEGACY_BASIC_RATE 0x1408 // TXRX_CSR5 0x3054
+#define LEGACY_BASIC_RATE 0x1408 /* TXRX_CSR5 0x3054 */
#define HT_BASIC_RATE 0x140c
#define HT_CTRL_CFG 0x1410
#define SIFS_COST_CFG 0x1414
-#define RX_PARSER_CFG 0x1418 //Set NAV for all received frames
-
-//
-// 4.5 MAC Security configuration (offset:0x1500)
-//
-#define TX_SEC_CNT0 0x1500 //
-#define RX_SEC_CNT0 0x1504 //
-#define CCMP_FC_MUTE 0x1508 //
-//
-// 4.6 HCCA/PSMP (offset:0x1600)
-//
+#define RX_PARSER_CFG 0x1418 /*Set NAV for all received frames */
+
+/* */
+/* 4.5 MAC Security configuration (offset:0x1500) */
+/* */
+#define TX_SEC_CNT0 0x1500 /* */
+#define RX_SEC_CNT0 0x1504 /* */
+#define CCMP_FC_MUTE 0x1508 /* */
+/* */
+/* 4.6 HCCA/PSMP (offset:0x1600) */
+/* */
#define TXOP_HLDR_ADDR0 0x1600
#define TXOP_HLDR_ADDR1 0x1604
#define TXOP_HLDR_ET 0x1608
#define QOS_CFPOLL_RA_DW0 0x160c
#define QOS_CFPOLL_A1_DW1 0x1610
#define QOS_CFPOLL_QC 0x1614
-//
-// 4.7 MAC Statistis registers (offset:0x1700)
-//
-#define RX_STA_CNT0 0x1700 //
-#define RX_STA_CNT1 0x1704 //
-#define RX_STA_CNT2 0x1708 //
-
-//
-// RX_STA_CNT0_STRUC: RX PLCP error count & RX CRC error count
-//
+/* */
+/* 4.7 MAC Statistis registers (offset:0x1700) */
+/* */
+#define RX_STA_CNT0 0x1700 /* */
+#define RX_STA_CNT1 0x1704 /* */
+#define RX_STA_CNT2 0x1708 /* */
+
+/* */
+/* RX_STA_CNT0_STRUC: RX PLCP error count & RX CRC error count */
+/* */
typedef union _RX_STA_CNT0_STRUC {
struct {
USHORT CrcErr;
@@ -795,9 +795,9 @@ typedef union _RX_STA_CNT0_STRUC {
UINT32 word;
} RX_STA_CNT0_STRUC, *PRX_STA_CNT0_STRUC;
-//
-// RX_STA_CNT1_STRUC: RX False CCA count & RX LONG frame count
-//
+/* */
+/* RX_STA_CNT1_STRUC: RX False CCA count & RX LONG frame count */
+/* */
typedef union _RX_STA_CNT1_STRUC {
struct {
USHORT FalseCca;
@@ -806,9 +806,9 @@ typedef union _RX_STA_CNT1_STRUC {
UINT32 word;
} RX_STA_CNT1_STRUC, *PRX_STA_CNT1_STRUC;
-//
-// RX_STA_CNT2_STRUC:
-//
+/* */
+/* RX_STA_CNT2_STRUC: */
+/* */
typedef union _RX_STA_CNT2_STRUC {
struct {
USHORT RxDupliCount;
@@ -816,10 +816,10 @@ typedef union _RX_STA_CNT2_STRUC {
} field;
UINT32 word;
} RX_STA_CNT2_STRUC, *PRX_STA_CNT2_STRUC;
-#define TX_STA_CNT0 0x170C //
-//
-// STA_CSR3: TX Beacon count
-//
+#define TX_STA_CNT0 0x170C /* */
+/* */
+/* STA_CSR3: TX Beacon count */
+/* */
typedef union _TX_STA_CNT0_STRUC {
struct {
USHORT TxFailCount;
@@ -827,10 +827,10 @@ typedef union _TX_STA_CNT0_STRUC {
} field;
UINT32 word;
} TX_STA_CNT0_STRUC, *PTX_STA_CNT0_STRUC;
-#define TX_STA_CNT1 0x1710 //
-//
-// TX_STA_CNT1: TX tx count
-//
+#define TX_STA_CNT1 0x1710 /* */
+/* */
+/* TX_STA_CNT1: TX tx count */
+/* */
typedef union _TX_STA_CNT1_STRUC {
struct {
USHORT TxSuccess;
@@ -838,10 +838,10 @@ typedef union _TX_STA_CNT1_STRUC {
} field;
UINT32 word;
} TX_STA_CNT1_STRUC, *PTX_STA_CNT1_STRUC;
-#define TX_STA_CNT2 0x1714 //
-//
-// TX_STA_CNT2: TX tx count
-//
+#define TX_STA_CNT2 0x1714 /* */
+/* */
+/* TX_STA_CNT2: TX tx count */
+/* */
typedef union _TX_STA_CNT2_STRUC {
struct {
USHORT TxZeroLenCount;
@@ -849,26 +849,26 @@ typedef union _TX_STA_CNT2_STRUC {
} field;
UINT32 word;
} TX_STA_CNT2_STRUC, *PTX_STA_CNT2_STRUC;
-#define TX_STA_FIFO 0x1718 //
-//
-// TX_STA_FIFO_STRUC: TX Result for specific PID status fifo register
-//
+#define TX_STA_FIFO 0x1718 /* */
+/* */
+/* TX_STA_FIFO_STRUC: TX Result for specific PID status fifo register */
+/* */
typedef union PACKED _TX_STA_FIFO_STRUC {
struct {
- UINT32 bValid:1; // 1:This register contains a valid TX result
+ UINT32 bValid:1; /* 1:This register contains a valid TX result */
UINT32 PidType:4;
- UINT32 TxSuccess:1; // Tx No retry success
- UINT32 TxAggre:1; // Tx Retry Success
- UINT32 TxAckRequired:1; // Tx fail
- UINT32 wcid:8; //wireless client index
-// UINT32 SuccessRate:16; //include MCS, mode ,shortGI, BW settingSame format as TXWI Word 0 Bit 31-16.
- UINT32 SuccessRate:13; //include MCS, mode ,shortGI, BW settingSame format as TXWI Word 0 Bit 31-16.
+ UINT32 TxSuccess:1; /* Tx No retry success */
+ UINT32 TxAggre:1; /* Tx Retry Success */
+ UINT32 TxAckRequired:1; /* Tx fail */
+ UINT32 wcid:8; /*wireless client index */
+/* UINT32 SuccessRate:16; //include MCS, mode ,shortGI, BW settingSame format as TXWI Word 0 Bit 31-16. */
+ UINT32 SuccessRate:13; /*include MCS, mode ,shortGI, BW settingSame format as TXWI Word 0 Bit 31-16. */
UINT32 TxBF:1;
UINT32 Reserve:2;
} field;
UINT32 word;
} TX_STA_FIFO_STRUC, *PTX_STA_FIFO_STRUC;
-// Debug counter
+/* Debug counter */
#define TX_AGG_CNT 0x171c
typedef union _TX_AGG_CNT_STRUC {
struct {
@@ -877,7 +877,7 @@ typedef union _TX_AGG_CNT_STRUC {
} field;
UINT32 word;
} TX_AGG_CNT_STRUC, *PTX_AGG_CNT_STRUC;
-// Debug counter
+/* Debug counter */
#define TX_AGG_CNT0 0x1720
typedef union _TX_AGG_CNT0_STRUC {
struct {
@@ -886,7 +886,7 @@ typedef union _TX_AGG_CNT0_STRUC {
} field;
UINT32 word;
} TX_AGG_CNT0_STRUC, *PTX_AGG_CNT0_STRUC;
-// Debug counter
+/* Debug counter */
#define TX_AGG_CNT1 0x1724
typedef union _TX_AGG_CNT1_STRUC {
struct {
@@ -903,7 +903,7 @@ typedef union _TX_AGG_CNT2_STRUC {
} field;
UINT32 word;
} TX_AGG_CNT2_STRUC, *PTX_AGG_CNT2_STRUC;
-// Debug counter
+/* Debug counter */
#define TX_AGG_CNT3 0x172c
typedef union _TX_AGG_CNT3_STRUC {
struct {
@@ -912,7 +912,7 @@ typedef union _TX_AGG_CNT3_STRUC {
} field;
UINT32 word;
} TX_AGG_CNT3_STRUC, *PTX_AGG_CNT3_STRUC;
-// Debug counter
+/* Debug counter */
#define TX_AGG_CNT4 0x1730
typedef union _TX_AGG_CNT4_STRUC {
struct {
@@ -948,32 +948,32 @@ typedef union _TX_AGG_CNT7_STRUC {
#define MPDU_DENSITY_CNT 0x1740
typedef union _MPDU_DEN_CNT_STRUC {
struct {
- USHORT TXZeroDelCount; //TX zero length delimiter count
- USHORT RXZeroDelCount; //RX zero length delimiter count
+ USHORT TXZeroDelCount; /*TX zero length delimiter count */
+ USHORT RXZeroDelCount; /*RX zero length delimiter count */
} field;
UINT32 word;
} MPDU_DEN_CNT_STRUC, *PMPDU_DEN_CNT_STRUC;
-//
-// TXRX control registers - base address 0x3000
-//
-// rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first..
+/* */
+/* TXRX control registers - base address 0x3000 */
+/* */
+/* rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first.. */
#define TXRX_CSR1 0x77d0
-//
-// Security key table memory, base address = 0x1000
-//
-#define MAC_WCID_BASE 0x1800 //8-bytes(use only 6-bytes) * 256 entry =
+/* */
+/* Security key table memory, base address = 0x1000 */
+/* */
+#define MAC_WCID_BASE 0x1800 /*8-bytes(use only 6-bytes) * 256 entry = */
#define HW_WCID_ENTRY_SIZE 8
-#define PAIRWISE_KEY_TABLE_BASE 0x4000 // 32-byte * 256-entry = -byte
+#define PAIRWISE_KEY_TABLE_BASE 0x4000 /* 32-byte * 256-entry = -byte */
#define HW_KEY_ENTRY_SIZE 0x20
-#define PAIRWISE_IVEIV_TABLE_BASE 0x6000 // 8-byte * 256-entry = -byte
-#define MAC_IVEIV_TABLE_BASE 0x6000 // 8-byte * 256-entry = -byte
+#define PAIRWISE_IVEIV_TABLE_BASE 0x6000 /* 8-byte * 256-entry = -byte */
+#define MAC_IVEIV_TABLE_BASE 0x6000 /* 8-byte * 256-entry = -byte */
#define HW_IVEIV_ENTRY_SIZE 8
-#define MAC_WCID_ATTRIBUTE_BASE 0x6800 // 4-byte * 256-entry = -byte
+#define MAC_WCID_ATTRIBUTE_BASE 0x6800 /* 4-byte * 256-entry = -byte */
#define HW_WCID_ATTRI_SIZE 4
#define WCID_RESERVED 0x6bfc
-#define SHARED_KEY_TABLE_BASE 0x6c00 // 32-byte * 16-entry = 512-byte
-#define SHARED_KEY_MODE_BASE 0x7000 // 32-byte * 16-entry = 512-byte
+#define SHARED_KEY_TABLE_BASE 0x6c00 /* 32-byte * 16-entry = 512-byte */
+#define SHARED_KEY_MODE_BASE 0x7000 /* 32-byte * 16-entry = 512-byte */
#define HW_SHARED_KEY_MODE_SIZE 4
#define SHAREDKEYTABLE 0
#define PAIRWISEKEYTABLE 1
@@ -999,48 +999,48 @@ typedef union _SHAREDKEY_MODE_STRUC {
} field;
UINT32 word;
} SHAREDKEY_MODE_STRUC, *PSHAREDKEY_MODE_STRUC;
-// 64-entry for pairwise key table
-typedef struct _HW_WCID_ENTRY { // 8-byte per entry
+/* 64-entry for pairwise key table */
+typedef struct _HW_WCID_ENTRY { /* 8-byte per entry */
UCHAR Address[6];
UCHAR Rsv[2];
} HW_WCID_ENTRY, PHW_WCID_ENTRY;
-// =================================================================================
-// WCID format
-// =================================================================================
-//7.1 WCID ENTRY format : 8bytes
+/* ================================================================================= */
+/* WCID format */
+/* ================================================================================= */
+/*7.1 WCID ENTRY format : 8bytes */
typedef struct _WCID_ENTRY_STRUC {
- UCHAR RXBABitmap7; // bit0 for TID8, bit7 for TID 15
- UCHAR RXBABitmap0; // bit0 for TID0, bit7 for TID 7
- UCHAR MAC[6]; // 0 for shared key table. 1 for pairwise key table
+ UCHAR RXBABitmap7; /* bit0 for TID8, bit7 for TID 15 */
+ UCHAR RXBABitmap0; /* bit0 for TID0, bit7 for TID 7 */
+ UCHAR MAC[6]; /* 0 for shared key table. 1 for pairwise key table */
} WCID_ENTRY_STRUC, *PWCID_ENTRY_STRUC;
-//8.1.1 SECURITY KEY format : 8DW
-// 32-byte per entry, total 16-entry for shared key table, 64-entry for pairwise key table
-typedef struct _HW_KEY_ENTRY { // 32-byte per entry
+/*8.1.1 SECURITY KEY format : 8DW */
+/* 32-byte per entry, total 16-entry for shared key table, 64-entry for pairwise key table */
+typedef struct _HW_KEY_ENTRY { /* 32-byte per entry */
UCHAR Key[16];
UCHAR TxMic[8];
UCHAR RxMic[8];
} HW_KEY_ENTRY, *PHW_KEY_ENTRY;
-//8.1.2 IV/EIV format : 2DW
+/*8.1.2 IV/EIV format : 2DW */
-//8.1.3 RX attribute entry format : 1DW
+/*8.1.3 RX attribute entry format : 1DW */
typedef struct _MAC_ATTRIBUTE_STRUC {
- UINT32 KeyTab:1; // 0 for shared key table. 1 for pairwise key table
+ UINT32 KeyTab:1; /* 0 for shared key table. 1 for pairwise key table */
UINT32 PairKeyMode:3;
- UINT32 BSSIDIdx:3; //multipleBSS index for the WCID
+ UINT32 BSSIDIdx:3; /*multipleBSS index for the WCID */
UINT32 RXWIUDF:3;
UINT32 rsv:22;
} MAC_ATTRIBUTE_STRUC, *PMAC_ATTRIBUTE_STRUC;
-// =================================================================================
-// HOST-MCU communication data structure
-// =================================================================================
+/* ================================================================================= */
+/* HOST-MCU communication data structure */
+/* ================================================================================= */
-//
-// H2M_MAILBOX_CSR: Host-to-MCU Mailbox
-//
+/* */
+/* H2M_MAILBOX_CSR: Host-to-MCU Mailbox */
+/* */
typedef union _H2M_MAILBOX_STRUC {
struct {
UINT32 LowByte:8;
@@ -1051,9 +1051,9 @@ typedef union _H2M_MAILBOX_STRUC {
UINT32 word;
} H2M_MAILBOX_STRUC, *PH2M_MAILBOX_STRUC;
-//
-// M2H_CMD_DONE_CSR: MCU-to-Host command complete indication
-//
+/* */
+/* M2H_CMD_DONE_CSR: MCU-to-Host command complete indication */
+/* */
typedef union _M2H_CMD_DONE_STRUC {
struct {
UINT32 CmdToken0;
@@ -1064,42 +1064,42 @@ typedef union _M2H_CMD_DONE_STRUC {
UINT32 word;
} M2H_CMD_DONE_STRUC, *PM2H_CMD_DONE_STRUC;
-//NAV_TIME_CFG :NAV
+/*NAV_TIME_CFG :NAV */
typedef union _NAV_TIME_CFG_STRUC {
struct {
- UCHAR Sifs; // in unit of 1-us
- UCHAR SlotTime; // in unit of 1-us
- USHORT Eifs:9; // in unit of 1-us
- USHORT ZeroSifs:1; // Applied zero SIFS timer after OFDM RX 0: disable
+ UCHAR Sifs; /* in unit of 1-us */
+ UCHAR SlotTime; /* in unit of 1-us */
+ USHORT Eifs:9; /* in unit of 1-us */
+ USHORT ZeroSifs:1; /* Applied zero SIFS timer after OFDM RX 0: disable */
USHORT rsv:6;
} field;
UINT32 word;
} NAV_TIME_CFG_STRUC, *PNAV_TIME_CFG_STRUC;
-//
-// RX_FILTR_CFG: /RX configuration register
-//
+/* */
+/* RX_FILTR_CFG: /RX configuration register */
+/* */
typedef union _RX_FILTR_CFG_STRUC {
struct {
- UINT32 DropCRCErr:1; // Drop CRC error
- UINT32 DropPhyErr:1; // Drop physical error
- UINT32 DropNotToMe:1; // Drop not to me unicast frame
- UINT32 DropNotMyBSSID:1; // Drop fram ToDs bit is true
-
- UINT32 DropVerErr:1; // Drop version error frame
- UINT32 DropMcast:1; // Drop multicast frames
- UINT32 DropBcast:1; // Drop broadcast frames
- UINT32 DropDuplicate:1; // Drop duplicate frame
-
- UINT32 DropCFEndAck:1; // Drop Ps-Poll
- UINT32 DropCFEnd:1; // Drop Ps-Poll
- UINT32 DropAck:1; // Drop Ps-Poll
- UINT32 DropCts:1; // Drop Ps-Poll
-
- UINT32 DropRts:1; // Drop Ps-Poll
- UINT32 DropPsPoll:1; // Drop Ps-Poll
- UINT32 DropBA:1; //
- UINT32 DropBAR:1; //
+ UINT32 DropCRCErr:1; /* Drop CRC error */
+ UINT32 DropPhyErr:1; /* Drop physical error */
+ UINT32 DropNotToMe:1; /* Drop not to me unicast frame */
+ UINT32 DropNotMyBSSID:1; /* Drop fram ToDs bit is true */
+
+ UINT32 DropVerErr:1; /* Drop version error frame */
+ UINT32 DropMcast:1; /* Drop multicast frames */
+ UINT32 DropBcast:1; /* Drop broadcast frames */
+ UINT32 DropDuplicate:1; /* Drop duplicate frame */
+
+ UINT32 DropCFEndAck:1; /* Drop Ps-Poll */
+ UINT32 DropCFEnd:1; /* Drop Ps-Poll */
+ UINT32 DropAck:1; /* Drop Ps-Poll */
+ UINT32 DropCts:1; /* Drop Ps-Poll */
+
+ UINT32 DropRts:1; /* Drop Ps-Poll */
+ UINT32 DropPsPoll:1; /* Drop Ps-Poll */
+ UINT32 DropBA:1; /* */
+ UINT32 DropBAR:1; /* */
UINT32 DropRsvCntlType:1;
UINT32:15;
@@ -1107,23 +1107,23 @@ typedef union _RX_FILTR_CFG_STRUC {
UINT32 word;
} RX_FILTR_CFG_STRUC, *PRX_FILTR_CFG_STRUC;
-//
-// PHY_CSR4: RF serial control register
-//
+/* */
+/* PHY_CSR4: RF serial control register */
+/* */
typedef union _PHY_CSR4_STRUC {
struct {
- UINT32 RFRegValue:24; // Register value (include register id) serial out to RF/IF chip.
- UINT32 NumberOfBits:5; // Number of bits used in RFRegValue (I:20, RFMD:22)
- UINT32 IFSelect:1; // 1: select IF to program, 0: select RF to program
- UINT32 PLL_LD:1; // RF PLL_LD status
- UINT32 Busy:1; // 1: ASIC is busy execute RF programming.
+ UINT32 RFRegValue:24; /* Register value (include register id) serial out to RF/IF chip. */
+ UINT32 NumberOfBits:5; /* Number of bits used in RFRegValue (I:20, RFMD:22) */
+ UINT32 IFSelect:1; /* 1: select IF to program, 0: select RF to program */
+ UINT32 PLL_LD:1; /* RF PLL_LD status */
+ UINT32 Busy:1; /* 1: ASIC is busy execute RF programming. */
} field;
UINT32 word;
} PHY_CSR4_STRUC, *PPHY_CSR4_STRUC;
-//
-// SEC_CSR5: shared key table security mode register
-//
+/* */
+/* SEC_CSR5: shared key table security mode register */
+/* */
typedef union _SEC_CSR5_STRUC {
struct {
UINT32 Bss2Key0CipherAlg:3;
@@ -1146,9 +1146,9 @@ typedef union _SEC_CSR5_STRUC {
UINT32 word;
} SEC_CSR5_STRUC, *PSEC_CSR5_STRUC;
-//
-// HOST_CMD_CSR: For HOST to interrupt embedded processor
-//
+/* */
+/* HOST_CMD_CSR: For HOST to interrupt embedded processor */
+/* */
typedef union _HOST_CMD_CSR_STRUC {
struct {
UINT32 HostCommand:8;
@@ -1157,47 +1157,47 @@ typedef union _HOST_CMD_CSR_STRUC {
UINT32 word;
} HOST_CMD_CSR_STRUC, *PHOST_CMD_CSR_STRUC;
-//
-// AIFSN_CSR: AIFSN for each EDCA AC
-//
+/* */
+/* AIFSN_CSR: AIFSN for each EDCA AC */
+/* */
-//
-// E2PROM_CSR: EEPROM control register
-//
+/* */
+/* E2PROM_CSR: EEPROM control register */
+/* */
typedef union _E2PROM_CSR_STRUC {
struct {
- UINT32 Reload:1; // Reload EEPROM content, write one to reload, self-cleared.
+ UINT32 Reload:1; /* Reload EEPROM content, write one to reload, self-cleared. */
UINT32 EepromSK:1;
UINT32 EepromCS:1;
UINT32 EepromDI:1;
UINT32 EepromDO:1;
- UINT32 Type:1; // 1: 93C46, 0:93C66
- UINT32 LoadStatus:1; // 1:loading, 0:done
+ UINT32 Type:1; /* 1: 93C46, 0:93C66 */
+ UINT32 LoadStatus:1; /* 1:loading, 0:done */
UINT32 Rsvd:25;
} field;
UINT32 word;
} E2PROM_CSR_STRUC, *PE2PROM_CSR_STRUC;
-//
-// QOS_CSR0: TXOP holder address0 register
-//
+/* */
+/* QOS_CSR0: TXOP holder address0 register */
+/* */
typedef union _QOS_CSR0_STRUC {
struct {
- UCHAR Byte0; // MAC address byte 0
- UCHAR Byte1; // MAC address byte 1
- UCHAR Byte2; // MAC address byte 2
- UCHAR Byte3; // MAC address byte 3
+ UCHAR Byte0; /* MAC address byte 0 */
+ UCHAR Byte1; /* MAC address byte 1 */
+ UCHAR Byte2; /* MAC address byte 2 */
+ UCHAR Byte3; /* MAC address byte 3 */
} field;
UINT32 word;
} QOS_CSR0_STRUC, *PQOS_CSR0_STRUC;
-//
-// QOS_CSR1: TXOP holder address1 register
-//
+/* */
+/* QOS_CSR1: TXOP holder address1 register */
+/* */
typedef union _QOS_CSR1_STRUC {
struct {
- UCHAR Byte4; // MAC address byte 4
- UCHAR Byte5; // MAC address byte 5
+ UCHAR Byte4; /* MAC address byte 4 */
+ UCHAR Byte5; /* MAC address byte 5 */
UCHAR Rsvd0;
UCHAR Rsvd1;
} field;
@@ -1207,41 +1207,41 @@ typedef union _QOS_CSR1_STRUC {
#define RF_CSR_CFG 0x500
typedef union _RF_CSR_CFG_STRUC {
struct {
- UINT RF_CSR_DATA:8; // DATA
- UINT TESTCSR_RFACC_REGNUM:5; // RF register ID
- UINT Rsvd2:3; // Reserved
- UINT RF_CSR_WR:1; // 0: read 1: write
- UINT RF_CSR_KICK:1; // kick RF register read/write
- UINT Rsvd1:14; // Reserved
+ UINT RF_CSR_DATA:8; /* DATA */
+ UINT TESTCSR_RFACC_REGNUM:5; /* RF register ID */
+ UINT Rsvd2:3; /* Reserved */
+ UINT RF_CSR_WR:1; /* 0: read 1: write */
+ UINT RF_CSR_KICK:1; /* kick RF register read/write */
+ UINT Rsvd1:14; /* Reserved */
} field;
UINT word;
} RF_CSR_CFG_STRUC, *PRF_CSR_CFG_STRUC;
-//
-// Other on-chip shared memory space, base = 0x2000
-//
+/* */
+/* Other on-chip shared memory space, base = 0x2000 */
+/* */
-// CIS space - base address = 0x2000
+/* CIS space - base address = 0x2000 */
#define HW_CIS_BASE 0x2000
-// Carrier-sense CTS frame base address. It's where mac stores carrier-sense frame for carrier-sense function.
+/* Carrier-sense CTS frame base address. It's where mac stores carrier-sense frame for carrier-sense function. */
#define HW_CS_CTS_BASE 0x7700
-// DFS CTS frame base address. It's where mac stores CTS frame for DFS.
+/* DFS CTS frame base address. It's where mac stores CTS frame for DFS. */
#define HW_DFS_CTS_BASE 0x7780
#define HW_CTS_FRAME_SIZE 0x80
-// 2004-11-08 john - since NULL frame won't be that long (256 byte). We steal 16 tail bytes
-// to save debugging settings
-#define HW_DEBUG_SETTING_BASE 0x77f0 // 0x77f0~0x77ff total 16 bytes
-#define HW_DEBUG_SETTING_BASE2 0x7770 // 0x77f0~0x77ff total 16 bytes
-
-// In order to support maximum 8 MBSS and its maximum length is 512 for each beacon
-// Three section discontinue memory segments will be used.
-// 1. The original region for BCN 0~3
-// 2. Extract memory from FCE table for BCN 4~5
-// 3. Extract memory from Pair-wise key table for BCN 6~7
-// It occupied those memory of wcid 238~253 for BCN 6
-// and wcid 222~237 for BCN 7
+/* 2004-11-08 john - since NULL frame won't be that long (256 byte). We steal 16 tail bytes */
+/* to save debugging settings */
+#define HW_DEBUG_SETTING_BASE 0x77f0 /* 0x77f0~0x77ff total 16 bytes */
+#define HW_DEBUG_SETTING_BASE2 0x7770 /* 0x77f0~0x77ff total 16 bytes */
+
+/* In order to support maximum 8 MBSS and its maximum length is 512 for each beacon */
+/* Three section discontinue memory segments will be used. */
+/* 1. The original region for BCN 0~3 */
+/* 2. Extract memory from FCE table for BCN 4~5 */
+/* 3. Extract memory from Pair-wise key table for BCN 6~7 */
+/* It occupied those memory of wcid 238~253 for BCN 6 */
+/* and wcid 222~237 for BCN 7 */
#define HW_BEACON_MAX_SIZE 0x1000 /* unit: byte */
#define HW_BEACON_BASE0 0x7800
#define HW_BEACON_BASE1 0x7A00
@@ -1256,7 +1256,7 @@ typedef union _RF_CSR_CFG_STRUC {
#define HW_BEACON_OFFSET 0x0200
#define HW_BEACON_CONTENT_LEN (HW_BEACON_OFFSET - TXWI_SIZE)
-// HOST-MCU shared memory - base address = 0x2100
+/* HOST-MCU shared memory - base address = 0x2100 */
#define HOST_CMD_CSR 0x404
#define H2M_MAILBOX_CSR 0x7010
#define H2M_MAILBOX_CID 0x7014
@@ -1264,37 +1264,37 @@ typedef union _RF_CSR_CFG_STRUC {
#define H2M_INT_SRC 0x7024
#define H2M_BBP_AGENT 0x7028
#define M2H_CMD_DONE_CSR 0x000c
-#define MCU_TXOP_ARRAY_BASE 0x000c // TODO: to be provided by Albert
-#define MCU_TXOP_ENTRY_SIZE 32 // TODO: to be provided by Albert
-#define MAX_NUM_OF_TXOP_ENTRY 16 // TODO: must be same with 8051 firmware
-#define MCU_MBOX_VERSION 0x01 // TODO: to be confirmed by Albert
-#define MCU_MBOX_VERSION_OFFSET 5 // TODO: to be provided by Albert
-
-//
-// Host DMA registers - base address 0x200 . TX0-3=EDCAQid0-3, TX4=HCCA, TX5=MGMT,
-//
-//
-// DMA RING DESCRIPTOR
-//
+#define MCU_TXOP_ARRAY_BASE 0x000c /* TODO: to be provided by Albert */
+#define MCU_TXOP_ENTRY_SIZE 32 /* TODO: to be provided by Albert */
+#define MAX_NUM_OF_TXOP_ENTRY 16 /* TODO: must be same with 8051 firmware */
+#define MCU_MBOX_VERSION 0x01 /* TODO: to be confirmed by Albert */
+#define MCU_MBOX_VERSION_OFFSET 5 /* TODO: to be provided by Albert */
+
+/* */
+/* Host DMA registers - base address 0x200 . TX0-3=EDCAQid0-3, TX4=HCCA, TX5=MGMT, */
+/* */
+/* */
+/* DMA RING DESCRIPTOR */
+/* */
#define E2PROM_CSR 0x0004
#define IO_CNTL_CSR 0x77d0
-// ================================================================
-// Tx / Rx / Mgmt ring descriptor definition
-// ================================================================
+/* ================================================================ */
+/* Tx / Rx / Mgmt ring descriptor definition */
+/* ================================================================ */
-// the following PID values are used to mark outgoing frame type in TXD->PID so that
-// proper TX statistics can be collected based on these categories
-// b3-2 of PID field -
+/* the following PID values are used to mark outgoing frame type in TXD->PID so that */
+/* proper TX statistics can be collected based on these categories */
+/* b3-2 of PID field - */
#define PID_MGMT 0x05
#define PID_BEACON 0x0c
#define PID_DATA_NORMALUCAST 0x02
#define PID_DATA_AMPDU 0x04
#define PID_DATA_NO_ACK 0x08
#define PID_DATA_NOT_NORM_ACK 0x03
-// value domain of pTxD->HostQId (4-bit: 0~15)
-#define QID_AC_BK 1 // meet ACI definition in 802.11e
-#define QID_AC_BE 0 // meet ACI definition in 802.11e
+/* value domain of pTxD->HostQId (4-bit: 0~15) */
+#define QID_AC_BK 1 /* meet ACI definition in 802.11e */
+#define QID_AC_BE 0 /* meet ACI definition in 802.11e */
#define QID_AC_VI 2
#define QID_AC_VO 3
#define QID_HCCA 4
@@ -1303,4 +1303,4 @@ typedef union _RF_CSR_CFG_STRUC {
#define QID_RX 14
#define QID_OTHER 15
-#endif // __RTMP_MAC_H__ //
+#endif /* __RTMP_MAC_H__ // */
diff --git a/drivers/staging/rt2860/chip/rtmp_phy.h b/drivers/staging/rt2860/chip/rtmp_phy.h
index bbf920d818d8..fd1a989c1110 100644
--- a/drivers/staging/rt2860/chip/rtmp_phy.h
+++ b/drivers/staging/rt2860/chip/rtmp_phy.h
@@ -74,30 +74,30 @@
#define RF_R30 30
#define RF_R31 31
-// value domain of pAd->RfIcType
-#define RFIC_2820 1 // 2.4G 2T3R
-#define RFIC_2850 2 // 2.4G/5G 2T3R
-#define RFIC_2720 3 // 2.4G 1T2R
-#define RFIC_2750 4 // 2.4G/5G 1T2R
-#define RFIC_3020 5 // 2.4G 1T1R
-#define RFIC_2020 6 // 2.4G B/G
-#define RFIC_3021 7 // 2.4G 1T2R
-#define RFIC_3022 8 // 2.4G 2T2R
-#define RFIC_3052 9 // 2.4G/5G 2T2R
+/* value domain of pAd->RfIcType */
+#define RFIC_2820 1 /* 2.4G 2T3R */
+#define RFIC_2850 2 /* 2.4G/5G 2T3R */
+#define RFIC_2720 3 /* 2.4G 1T2R */
+#define RFIC_2750 4 /* 2.4G/5G 1T2R */
+#define RFIC_3020 5 /* 2.4G 1T1R */
+#define RFIC_2020 6 /* 2.4G B/G */
+#define RFIC_3021 7 /* 2.4G 1T2R */
+#define RFIC_3022 8 /* 2.4G 2T2R */
+#define RFIC_3052 9 /* 2.4G/5G 2T2R */
/*
BBP sections
*/
-#define BBP_R0 0 // version
-#define BBP_R1 1 // TSSI
-#define BBP_R2 2 // TX configure
+#define BBP_R0 0 /* version */
+#define BBP_R1 1 /* TSSI */
+#define BBP_R2 2 /* TX configure */
#define BBP_R3 3
#define BBP_R4 4
#define BBP_R5 5
#define BBP_R6 6
-#define BBP_R14 14 // RX configure
+#define BBP_R14 14 /* RX configure */
#define BBP_R16 16
-#define BBP_R17 17 // RX sensibility
+#define BBP_R17 17 /* RX sensibility */
#define BBP_R18 18
#define BBP_R21 21
#define BBP_R22 22
@@ -106,12 +106,12 @@
#define BBP_R26 26
#define BBP_R27 27
#define BBP_R31 31
-#define BBP_R49 49 //TSSI
+#define BBP_R49 49 /*TSSI */
#define BBP_R50 50
#define BBP_R51 51
#define BBP_R52 52
#define BBP_R55 55
-#define BBP_R62 62 // Rx SQ0 Threshold HIGH
+#define BBP_R62 62 /* Rx SQ0 Threshold HIGH */
#define BBP_R63 63
#define BBP_R64 64
#define BBP_R65 65
@@ -119,7 +119,7 @@
#define BBP_R67 67
#define BBP_R68 68
#define BBP_R69 69
-#define BBP_R70 70 // Rx AGC SQ CCK Xcorr threshold
+#define BBP_R70 70 /* Rx AGC SQ CCK Xcorr threshold */
#define BBP_R73 73
#define BBP_R75 75
#define BBP_R77 77
@@ -133,7 +133,7 @@
#define BBP_R86 86
#define BBP_R91 91
#define BBP_R92 92
-#define BBP_R94 94 // Tx Gain Control
+#define BBP_R94 94 /* Tx Gain Control */
#define BBP_R103 103
#define BBP_R105 105
#define BBP_R106 106
@@ -149,22 +149,22 @@
#define BBP_R122 122
#define BBP_R123 123
#ifdef RT30xx
-#define BBP_R138 138 // add by johnli, RF power sequence setup, ADC dynamic on/off control
-#endif // RT30xx //
+#define BBP_R138 138 /* add by johnli, RF power sequence setup, ADC dynamic on/off control */
+#endif /* RT30xx // */
-#define BBPR94_DEFAULT 0x06 // Add 1 value will gain 1db
+#define BBPR94_DEFAULT 0x06 /* Add 1 value will gain 1db */
-//
-// BBP & RF are using indirect access. Before write any value into it.
-// We have to make sure there is no outstanding command pending via checking busy bit.
-//
-#define MAX_BUSY_COUNT 100 // Number of retry before failing access BBP & RF indirect register
+/* */
+/* BBP & RF are using indirect access. Before write any value into it. */
+/* We have to make sure there is no outstanding command pending via checking busy bit. */
+/* */
+#define MAX_BUSY_COUNT 100 /* Number of retry before failing access BBP & RF indirect register */
-//#define PHY_TR_SWITCH_TIME 5 // usec
+/*#define PHY_TR_SWITCH_TIME 5 // usec */
-//#define BBP_R17_LOW_SENSIBILITY 0x50
-//#define BBP_R17_MID_SENSIBILITY 0x41
-//#define BBP_R17_DYNAMIC_UP_BOUND 0x40
+/*#define BBP_R17_LOW_SENSIBILITY 0x50 */
+/*#define BBP_R17_MID_SENSIBILITY 0x41 */
+/*#define BBP_R17_DYNAMIC_UP_BOUND 0x40 */
#define RSSI_FOR_VERY_LOW_SENSIBILITY -35
#define RSSI_FOR_LOW_SENSIBILITY -58
@@ -194,15 +194,15 @@
} \
} \
}
-#endif // RTMP_MAC_PCI //
+#endif /* RTMP_MAC_PCI // */
#ifdef RTMP_MAC_USB
#define RTMP_RF_IO_WRITE32(_A, _V) RTUSBWriteRFRegister(_A, _V)
-#endif // RTMP_MAC_USB //
+#endif /* RTMP_MAC_USB // */
#ifdef RT30xx
#define RTMP_RF_IO_READ8_BY_REG_ID(_A, _I, _pV) RT30xxReadRFRegister(_A, _I, _pV)
#define RTMP_RF_IO_WRITE8_BY_REG_ID(_A, _I, _V) RT30xxWriteRFRegister(_A, _I, _V)
-#endif // RT30xx //
+#endif /* RT30xx // */
/*****************************************************************************
BBP register Read/Write marco definitions.
@@ -276,7 +276,7 @@
But for some chipset which didn't have mcu (e.g., RBUS based chipset), we
will use this function too and didn't access the bbp register via the MCU.
*/
-// Read BBP register by register's ID. Generate PER to test BA
+/* Read BBP register by register's ID. Generate PER to test BA */
#define RTMP_BBP_IO_READ8_BY_REG_ID(_A, _I, _pV) \
{ \
BBP_CSR_CFG_STRUC BbpCsr; \
@@ -425,7 +425,7 @@
But for some chipset which didn't have mcu (e.g., RBUS based chipset), we
will use this function too and didn't access the bbp register via the MCU.
*/
-// Write BBP register by register's ID & value
+/* Write BBP register by register's ID & value */
#define RTMP_BBP_IO_WRITE8_BY_REG_ID(_A, _I, _V) \
{ \
BBP_CSR_CFG_STRUC BbpCsr; \
@@ -510,7 +510,7 @@
DBGPRINT_ERR(("****** BBP_Write_Latch Buffer exceeds max boundry ****** \n")); \
} \
}
-#endif // RTMP_MAC_PCI //
+#endif /* RTMP_MAC_PCI // */
#ifdef RTMP_MAC_USB
#define RTMP_BBP_IO_READ8_BY_REG_ID(_A, _I, _pV) RTUSBReadBBPRegister(_A, _I, _pV)
@@ -518,7 +518,7 @@
#define BBP_IO_WRITE8_BY_REG_ID(_A, _I, _V) RTUSBWriteBBPRegister(_A, _I, _V)
#define BBP_IO_READ8_BY_REG_ID(_A, _I, _pV) RTUSBReadBBPRegister(_A, _I, _pV)
-#endif // RTMP_MAC_USB //
+#endif /* RTMP_MAC_USB // */
#ifdef RT30xx
#define RTMP_ASIC_MMPS_DISABLE(_pAd) \
@@ -551,6 +551,6 @@
RTMP_IO_WRITE32(_pAd, 0x1210, _macData); \
}while(0)
-#endif // RT30xx //
+#endif /* RT30xx // */
-#endif // __RTMP_PHY_H__ //
+#endif /* __RTMP_PHY_H__ // */
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.