Staging: rt2860: remove dead RT_BIG_ENDIAN code

Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

1 files changed, 41 insertions, 1110 deletions

diff --git a/drivers/staging/rt2860/rt28xx.h b/drivers/staging/rt2860/rt28xx.h
index e5e6f0a8de63..565358bb0b84 100644
--- a/drivers/staging/rt2860/rt28xx.h
+++ b/drivers/staging/rt2860/rt28xx.h
@@ -54,32 +54,6 @@
 //
 #define DMA_CSR0      0x200
 #define INT_SOURCE_CSR      0x200
-#ifdef RT_BIG_ENDIAN
-typedef	union	_INT_SOURCE_CSR_STRUC	{
-	struct	{
-		UINT32       	:14;
-		UINT32       	TxCoherent:1;
-		UINT32       	RxCoherent:1;
-		UINT32       	GPTimer:1;
-		UINT32       	AutoWakeup:1;//bit14
-		UINT32       	TXFifoStatusInt:1;//FIFO Statistics is full, sw should read 0x171c
-		UINT32       	PreTBTT:1;
-		UINT32       	TBTTInt:1;
-		UINT32       	RxTxCoherent:1;
-		UINT32       	MCUCommandINT:1;
-		UINT32       	MgmtDmaDone:1;
-		UINT32       	HccaDmaDone:1;
-		UINT32       	Ac3DmaDone:1;
-		UINT32       	Ac2DmaDone:1;
-		UINT32       	Ac1DmaDone:1;
-		UINT32		Ac0DmaDone:1;
-		UINT32		RxDone:1;
-		UINT32		TxDelayINT:1;	//delayed interrupt, not interrupt until several int or time limit hit
-		UINT32		RxDelayINT:1; //dealyed interrupt
-	}	field;
-	UINT32			word;
-}	INT_SOURCE_CSR_STRUC, *PINT_SOURCE_CSR_STRUC;
-#else
 typedef	union	_INT_SOURCE_CSR_STRUC	{
 	struct	{
 		UINT32		RxDelayINT:1;
@@ -104,32 +78,11 @@ typedef	union	_INT_SOURCE_CSR_STRUC	{
 	}	field;
 	UINT32			word;
 } INT_SOURCE_CSR_STRUC, *PINT_SOURCE_CSR_STRUC;
-#endif
 
 //
 // INT_MASK_CSR:   Interrupt MASK register.   1: the interrupt is mask OFF
 //
 #define INT_MASK_CSR        0x204
-#ifdef RT_BIG_ENDIAN
-typedef	union	_INT_MASK_CSR_STRUC	{
-	struct	{
-		UINT32       	TxCoherent:1;
-		UINT32       	RxCoherent:1;
-		UINT32       	:20;
-		UINT32       	MCUCommandINT:1;
-		UINT32       	MgmtDmaDone:1;
-		UINT32       	HccaDmaDone:1;
-		UINT32       	Ac3DmaDone:1;
-		UINT32       	Ac2DmaDone:1;
-		UINT32       	Ac1DmaDone:1;
-		UINT32		Ac0DmaDone:1;
-		UINT32		RxDone:1;
-		UINT32		TxDelay:1;
-		UINT32		RXDelay_INT_MSK:1;
-	}	field;
-	UINT32			word;
-}INT_MASK_CSR_STRUC, *PINT_MASK_CSR_STRUC;
-#else
 typedef	union	_INT_MASK_CSR_STRUC	{
 	struct	{
 		UINT32		RXDelay_INT_MSK:1;
@@ -148,24 +101,8 @@ typedef	union	_INT_MASK_CSR_STRUC	{
 	}	field;
 	UINT32			word;
 } INT_MASK_CSR_STRUC, *PINT_MASK_CSR_STRUC;
-#endif
+
 #define WPDMA_GLO_CFG 	0x208
-#ifdef RT_BIG_ENDIAN
-typedef	union	_WPDMA_GLO_CFG_STRUC	{
-	struct	{
-		UINT32       	HDR_SEG_LEN:16;
-		UINT32       	RXHdrScater:8;
-		UINT32       	BigEndian:1;
-		UINT32       	EnTXWriteBackDDONE:1;
-		UINT32       	WPDMABurstSIZE:2;
-		UINT32		RxDMABusy:1;
-		UINT32		EnableRxDMA:1;
-		UINT32		TxDMABusy:1;
-		UINT32		EnableTxDMA:1;
-	}	field;
-	UINT32			word;
-}WPDMA_GLO_CFG_STRUC, *PWPDMA_GLO_CFG_STRUC;
-#else
 typedef	union	_WPDMA_GLO_CFG_STRUC	{
 	struct	{
 		UINT32		EnableTxDMA:1;
@@ -180,24 +117,8 @@ typedef	union	_WPDMA_GLO_CFG_STRUC	{
 	}	field;
 	UINT32			word;
 } WPDMA_GLO_CFG_STRUC, *PWPDMA_GLO_CFG_STRUC;
-#endif
+
 #define WPDMA_RST_IDX 	0x20c
-#ifdef RT_BIG_ENDIAN
-typedef	union	_WPDMA_RST_IDX_STRUC	{
-	struct	{
-		UINT32       	:15;
-		UINT32       	RST_DRX_IDX0:1;
-		UINT32       	rsv:10;
-		UINT32       	RST_DTX_IDX5:1;
-		UINT32       	RST_DTX_IDX4:1;
-		UINT32		RST_DTX_IDX3:1;
-		UINT32		RST_DTX_IDX2:1;
-		UINT32		RST_DTX_IDX1:1;
-		UINT32		RST_DTX_IDX0:1;
-	}	field;
-	UINT32			word;
-}WPDMA_RST_IDX_STRUC, *PWPDMA_RST_IDX_STRUC;
-#else
 typedef	union	_WPDMA_RST_IDX_STRUC	{
 	struct	{
 		UINT32		RST_DTX_IDX0:1;
@@ -212,21 +133,8 @@ typedef	union	_WPDMA_RST_IDX_STRUC	{
 	}	field;
 	UINT32			word;
 } WPDMA_RST_IDX_STRUC, *PWPDMA_RST_IDX_STRUC;
-#endif
+
 #define DELAY_INT_CFG  0x0210
-#ifdef RT_BIG_ENDIAN
-typedef	union	_DELAY_INT_CFG_STRUC	{
-	struct	{
-		UINT32       	TXDLY_INT_EN:1;
-		UINT32       	TXMAX_PINT:7;
-		UINT32       	TXMAX_PTIME:8;
-		UINT32       	RXDLY_INT_EN:1;
-		UINT32       	RXMAX_PINT:7;
-		UINT32		RXMAX_PTIME:8;
-	}	field;
-	UINT32			word;
-}DELAY_INT_CFG_STRUC, *PDELAY_INT_CFG_STRUC;
-#else
 typedef	union	_DELAY_INT_CFG_STRUC	{
 	struct	{
 		UINT32		RXMAX_PTIME:8;
@@ -238,20 +146,8 @@ typedef	union	_DELAY_INT_CFG_STRUC	{
 	}	field;
 	UINT32			word;
 } DELAY_INT_CFG_STRUC, *PDELAY_INT_CFG_STRUC;
-#endif
+
 #define WMM_AIFSN_CFG   0x0214
-#ifdef RT_BIG_ENDIAN
-typedef	union	_AIFSN_CSR_STRUC	{
-	struct	{
-	    UINT32   Rsv:16;
-	    UINT32   Aifsn3:4;       // for AC_VO
-	    UINT32   Aifsn2:4;       // for AC_VI
-	    UINT32   Aifsn1:4;       // for AC_BK
-	    UINT32   Aifsn0:4;       // for AC_BE
-	}	field;
-	UINT32			word;
-}	AIFSN_CSR_STRUC, *PAIFSN_CSR_STRUC;
-#else
 typedef	union	_AIFSN_CSR_STRUC	{
 	struct	{
 	    UINT32   Aifsn0:4;       // for AC_BE
@@ -262,23 +158,11 @@ typedef	union	_AIFSN_CSR_STRUC	{
 	}	field;
 	UINT32			word;
 }	AIFSN_CSR_STRUC, *PAIFSN_CSR_STRUC;
-#endif
+
 //
 // CWMIN_CSR: CWmin for each EDCA AC
 //
 #define WMM_CWMIN_CFG   0x0218
-#ifdef RT_BIG_ENDIAN
-typedef	union	_CWMIN_CSR_STRUC	{
-	struct	{
-	    UINT32   Rsv:16;
-	    UINT32   Cwmin3:4;       // for AC_VO
-	    UINT32   Cwmin2:4;       // for AC_VI
-	    UINT32   Cwmin1:4;       // for AC_BK
-	    UINT32   Cwmin0:4;       // for AC_BE
-	}	field;
-	UINT32			word;
-}	CWMIN_CSR_STRUC, *PCWMIN_CSR_STRUC;
-#else
 typedef	union	_CWMIN_CSR_STRUC	{
 	struct	{
 	    UINT32   Cwmin0:4;       // for AC_BE
@@ -289,24 +173,11 @@ typedef	union	_CWMIN_CSR_STRUC	{
 	}	field;
 	UINT32			word;
 }	CWMIN_CSR_STRUC, *PCWMIN_CSR_STRUC;
-#endif
 
 //
 // CWMAX_CSR: CWmin for each EDCA AC
 //
 #define WMM_CWMAX_CFG   0x021c
-#ifdef RT_BIG_ENDIAN
-typedef	union	_CWMAX_CSR_STRUC	{
-	struct	{
-	    UINT32   Rsv:16;
-	    UINT32   Cwmax3:4;       // for AC_VO
-	    UINT32   Cwmax2:4;       // for AC_VI
-	    UINT32   Cwmax1:4;       // for AC_BK
-	    UINT32   Cwmax0:4;       // for AC_BE
-	}	field;
-	UINT32			word;
-}	CWMAX_CSR_STRUC, *PCWMAX_CSR_STRUC;
-#else
 typedef	union	_CWMAX_CSR_STRUC	{
 	struct	{
 	    UINT32   Cwmax0:4;       // for AC_BE
@@ -317,22 +188,11 @@ typedef	union	_CWMAX_CSR_STRUC	{
 	}	field;
 	UINT32			word;
 }	CWMAX_CSR_STRUC, *PCWMAX_CSR_STRUC;
-#endif
-
 
 //
 // AC_TXOP_CSR0: AC_BK/AC_BE TXOP register
 //
 #define WMM_TXOP0_CFG    0x0220
-#ifdef RT_BIG_ENDIAN
-typedef	union	_AC_TXOP_CSR0_STRUC	{
-	struct	{
-	    USHORT  Ac1Txop;        // for AC_BE, in unit of 32us
-	    USHORT  Ac0Txop;        // for AC_BK, in unit of 32us
-	}	field;
-	UINT32			word;
-}	AC_TXOP_CSR0_STRUC, *PAC_TXOP_CSR0_STRUC;
-#else
 typedef	union	_AC_TXOP_CSR0_STRUC	{
 	struct	{
 	    USHORT  Ac0Txop;        // for AC_BK, in unit of 32us
@@ -340,21 +200,11 @@ typedef	union	_AC_TXOP_CSR0_STRUC	{
 	}	field;
 	UINT32			word;
 }	AC_TXOP_CSR0_STRUC, *PAC_TXOP_CSR0_STRUC;
-#endif
 
 //
 // AC_TXOP_CSR1: AC_VO/AC_VI TXOP register
 //
 #define WMM_TXOP1_CFG    0x0224
-#ifdef RT_BIG_ENDIAN
-typedef	union	_AC_TXOP_CSR1_STRUC	{
-	struct	{
-	    USHORT  Ac3Txop;        // for AC_VO, in unit of 32us
-	    USHORT  Ac2Txop;        // for AC_VI, in unit of 32us
-	}	field;
-	UINT32			word;
-}	AC_TXOP_CSR1_STRUC, *PAC_TXOP_CSR1_STRUC;
-#else
 typedef	union	_AC_TXOP_CSR1_STRUC	{
 	struct	{
 	    USHORT  Ac2Txop;        // for AC_VI, in unit of 32us
@@ -362,7 +212,7 @@ typedef	union	_AC_TXOP_CSR1_STRUC	{
 	}	field;
 	UINT32			word;
 }	AC_TXOP_CSR1_STRUC, *PAC_TXOP_CSR1_STRUC;
-#endif
+
 #define RINGREG_DIFF			0x10
 #define GPIO_CTRL_CFG    0x0228	//MAC_CSR13
 #define MCU_CMD_CFG    0x022c
@@ -398,25 +248,7 @@ typedef	union	_AC_TXOP_CSR1_STRUC	{
 #define RX_CRX_IDX       0x0298
 #define RX_DRX_IDX      0x029c
 #define USB_DMA_CFG      0x02a0
-#ifdef RT_BIG_ENDIAN
-typedef	union	_USB_DMA_CFG_STRUC	{
-	struct	{
-	    UINT32  TxBusy:1;   	//USB DMA TX FSM busy . debug only
-	    UINT32  RxBusy:1;        //USB DMA RX FSM busy . debug only
-	    UINT32  EpoutValid:6;        //OUT endpoint data valid. debug only
-	    UINT32  TxBulkEn:1;        //Enable USB DMA Tx
-	    UINT32  RxBulkEn:1;        //Enable USB DMA Rx
-	    UINT32  RxBulkAggEn:1;        //Enable Rx Bulk Aggregation
-	    UINT32  TxopHalt:1;        //Halt TXOP count down when TX buffer is full.
-	    UINT32  TxClear:1;        //Clear USB DMA TX path
-	    UINT32  rsv:2;
-	    UINT32  phyclear:1;        		//phy watch dog enable. write 1
-	    UINT32  RxBulkAggLmt:8;        //Rx Bulk Aggregation Limit  in unit of 1024 bytes
-	    UINT32  RxBulkAggTOut:8;        //Rx Bulk Aggregation TimeOut  in unit of 33ns
-	}	field;
-	UINT32			word;
-}	USB_DMA_CFG_STRUC, *PUSB_DMA_CFG_STRUC;
-#else
+
 typedef	union	_USB_DMA_CFG_STRUC	{
 	struct	{
 	    UINT32  RxBulkAggTOut:8;        //Rx Bulk Aggregation TimeOut  in unit of 33ns
@@ -434,7 +266,6 @@ typedef	union	_USB_DMA_CFG_STRUC	{
 	}	field;
 	UINT32			word;
 }	USB_DMA_CFG_STRUC, *PUSB_DMA_CFG_STRUC;
-#endif
 
 //
 //  3  PBF  registers
@@ -458,15 +289,6 @@ typedef	union	_USB_DMA_CFG_STRUC	{
 //  4.1 MAC SYSTEM  configuration registers (offset:0x1000)
 //
 #define MAC_CSR0            0x1000
-#ifdef RT_BIG_ENDIAN
-typedef	union	_ASIC_VER_ID_STRUC	{
-	struct	{
-	    USHORT  ASICVer;        // version : 2860
-	    USHORT  ASICRev;        // reversion  : 0
-	}	field;
-	UINT32			word;
-}	ASIC_VER_ID_STRUC, *PASIC_VER_ID_STRUC;
-#else
 typedef	union	_ASIC_VER_ID_STRUC	{
 	struct	{
 	    USHORT  ASICRev;        // reversion  : 0
@@ -474,24 +296,13 @@ typedef	union	_ASIC_VER_ID_STRUC	{
 	}	field;
 	UINT32			word;
 }	ASIC_VER_ID_STRUC, *PASIC_VER_ID_STRUC;
-#endif
+
 #define MAC_SYS_CTRL            0x1004		//MAC_CSR1
 #define MAC_ADDR_DW0            		0x1008		// MAC ADDR DW0
 #define MAC_ADDR_DW1           		 0x100c		// MAC ADDR DW1
 //
 // MAC_CSR2: STA MAC register 0
 //
-#ifdef RT_BIG_ENDIAN
-typedef	union	_MAC_DW0_STRUC	{
-	struct	{
-		UCHAR		Byte3;		// MAC address byte 3
-		UCHAR		Byte2;		// MAC address byte 2
-		UCHAR		Byte1;		// MAC address byte 1
-		UCHAR		Byte0;		// MAC address byte 0
-	}	field;
-	UINT32			word;
-}	MAC_DW0_STRUC, *PMAC_DW0_STRUC;
-#else
 typedef	union	_MAC_DW0_STRUC	{
 	struct	{
 		UCHAR		Byte0;		// MAC address byte 0
@@ -501,22 +312,10 @@ typedef	union	_MAC_DW0_STRUC	{
 	}	field;
 	UINT32			word;
 }	MAC_DW0_STRUC, *PMAC_DW0_STRUC;
-#endif
 
 //
 // MAC_CSR3: STA MAC register 1
 //
-#ifdef RT_BIG_ENDIAN
-typedef	union	_MAC_DW1_STRUC	{
-	struct	{
-		UCHAR		Rsvd1;
-		UCHAR		U2MeMask;
-		UCHAR		Byte5;		// MAC address byte 5
-		UCHAR		Byte4;		// MAC address byte 4
-	}	field;
-	UINT32			word;
-}	MAC_DW1_STRUC, *PMAC_DW1_STRUC;
-#else
 typedef	union	_MAC_DW1_STRUC	{
 	struct	{
 		UCHAR		Byte4;		// MAC address byte 4
@@ -526,7 +325,6 @@ typedef	union	_MAC_DW1_STRUC	{
 	}	field;
 	UINT32			word;
 }	MAC_DW1_STRUC, *PMAC_DW1_STRUC;
-#endif
 
 #define MAC_BSSID_DW0            		0x1010		// MAC BSSID DW0
 #define MAC_BSSID_DW1            		0x1014		// MAC BSSID DW1
@@ -534,18 +332,6 @@ typedef	union	_MAC_DW1_STRUC	{
 //
 // MAC_CSR5: BSSID register 1
 //
-#ifdef RT_BIG_ENDIAN
-typedef	union	_MAC_CSR5_STRUC	{
-	struct	{
-		USHORT		Rsvd:11;
-		USHORT		MBssBcnNum:3;
-		USHORT		BssIdMode:2; // 0: one BSSID, 10: 4 BSSID,  01: 2 BSSID , 11: 8BSSID
-		UCHAR		Byte5;		 // BSSID byte 5
-		UCHAR		Byte4;		 // BSSID byte 4
-	}	field;
-	UINT32			word;
-}	MAC_CSR5_STRUC, *PMAC_CSR5_STRUC;
-#else
 typedef	union	_MAC_CSR5_STRUC	{
 	struct	{
 		UCHAR		Byte4;		 // BSSID byte 4
@@ -556,27 +342,12 @@ typedef	union	_MAC_CSR5_STRUC	{
 	}	field;
 	UINT32			word;
 }	MAC_CSR5_STRUC, *PMAC_CSR5_STRUC;
-#endif
 
 #define MAX_LEN_CFG              0x1018		// rt2860b max 16k bytes. bit12:13 Maximum PSDU length (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
 #define BBP_CSR_CFG            		0x101c		//
 //
 // BBP_CSR_CFG: BBP serial control register
 //
-#ifdef RT_BIG_ENDIAN
-typedef	union	_BBP_CSR_CFG_STRUC	{
-	struct	{
-		UINT32		:12;
-		UINT32		BBP_RW_MODE:1;		// 0: use serial mode  1:parallel
-		UINT32		BBP_PAR_DUR:1;		    // 0: 4 MAC clock cycles  1: 8 MAC clock cycles
-		UINT32		Busy:1;				// 1: ASIC is busy execute BBP programming.
-		UINT32		fRead:1;		    // 0: Write	BBP, 1:	Read BBP
-		UINT32		RegNum:8;			// Selected	BBP	register
-		UINT32		Value:8;			// Register	value to program into BBP
-	}	field;
-	UINT32			word;
-}	BBP_CSR_CFG_STRUC, *PBBP_CSR_CFG_STRUC;
-#else
 typedef	union	_BBP_CSR_CFG_STRUC	{
 	struct	{
 		UINT32		Value:8;			// Register	value to program into BBP
@@ -589,23 +360,11 @@ typedef	union	_BBP_CSR_CFG_STRUC	{
 	}	field;
 	UINT32			word;
 }	BBP_CSR_CFG_STRUC, *PBBP_CSR_CFG_STRUC;
-#endif
+
 #define RF_CSR_CFG0            		0x1020
 //
 // RF_CSR_CFG: RF control register
 //
-#ifdef RT_BIG_ENDIAN
-typedef	union	_RF_CSR_CFG0_STRUC	{
-	struct	{
-		UINT32		Busy:1;		    // 0: idle 1: 8busy
-		UINT32		Sel:1;				// 0:RF_LE0 activate  1:RF_LE1 activate
-		UINT32		StandbyMode:1;		    // 0: high when stand by 1:	low when standby
-		UINT32		bitwidth:5;			// Selected	BBP	register
-		UINT32		RegIdAndContent:24;			// Register	value to program into BBP
-	}	field;
-	UINT32			word;
-}	RF_CSR_CFG0_STRUC, *PRF_CSR_CFG0_STRUC;
-#else
 typedef	union	_RF_CSR_CFG0_STRUC	{
 	struct	{
 		UINT32		RegIdAndContent:24;			// Register	value to program into BBP
@@ -616,18 +375,8 @@ typedef	union	_RF_CSR_CFG0_STRUC	{
 	}	field;
 	UINT32			word;
 }	RF_CSR_CFG0_STRUC, *PRF_CSR_CFG0_STRUC;
-#endif
+
 #define RF_CSR_CFG1           		0x1024
-#ifdef RT_BIG_ENDIAN
-typedef	union	_RF_CSR_CFG1_STRUC	{
-	struct	{
-		UINT32		rsv:7;		    // 0: idle 1: 8busy
-		UINT32		RFGap:5;			// Gap between BB_CONTROL_RF and RF_LE. 0: 3 system clock cycle (37.5usec) 1: 5 system clock cycle (62.5usec)
-		UINT32		RegIdAndContent:24;			// Register	value to program into BBP
-	}	field;
-	UINT32			word;
-}	RF_CSR_CFG1_STRUC, *PRF_CSR_CFG1_STRUC;
-#else
 typedef	union	_RF_CSR_CFG1_STRUC	{
 	struct	{
 		UINT32		RegIdAndContent:24;			// Register	value to program into BBP
@@ -636,17 +385,8 @@ typedef	union	_RF_CSR_CFG1_STRUC	{
 	}	field;
 	UINT32			word;
 }	RF_CSR_CFG1_STRUC, *PRF_CSR_CFG1_STRUC;
-#endif
+
 #define RF_CSR_CFG2           		0x1028		//
-#ifdef RT_BIG_ENDIAN
-typedef	union	_RF_CSR_CFG2_STRUC	{
-	struct	{
-		UINT32		rsv:8;		    // 0: idle 1: 8busy
-		UINT32		RegIdAndContent:24;			// Register	value to program into BBP
-	}	field;
-	UINT32			word;
-}	RF_CSR_CFG2_STRUC, *PRF_CSR_CFG2_STRUC;
-#else
 typedef	union	_RF_CSR_CFG2_STRUC	{
 	struct	{
 		UINT32		RegIdAndContent:24;			// Register	value to program into BBP
@@ -654,24 +394,8 @@ typedef	union	_RF_CSR_CFG2_STRUC	{
 	}	field;
 	UINT32			word;
 }	RF_CSR_CFG2_STRUC, *PRF_CSR_CFG2_STRUC;
-#endif
+
 #define LED_CFG           		0x102c		//  MAC_CSR14
-#ifdef RT_BIG_ENDIAN
-typedef	union	_LED_CFG_STRUC	{
-	struct	{
-		UINT32		:1;
-		UINT32		LedPolar:1;			// Led Polarity.  0: active low1: active high
-		UINT32		YLedMode:2;			// yellow Led Mode
-		UINT32		GLedMode:2;			// green Led Mode
-		UINT32		RLedMode:2;			// red Led Mode    0: off1: blinking upon TX2: periodic slow blinking3: always on
-		UINT32		rsv:2;
-		UINT32		SlowBlinkPeriod:6;			// slow blinking period. unit:1ms
-		UINT32		OffPeriod:8;			// blinking off period unit 1ms
-		UINT32		OnPeriod:8;			// blinking on period unit 1ms
-	}	field;
-	UINT32			word;
-}	LED_CFG_STRUC, *PLED_CFG_STRUC;
-#else
 typedef	union	_LED_CFG_STRUC	{
 	struct	{
 		UINT32		OnPeriod:8;			// blinking on period unit 1ms
@@ -686,24 +410,11 @@ typedef	union	_LED_CFG_STRUC	{
 	}	field;
 	UINT32			word;
 }	LED_CFG_STRUC, *PLED_CFG_STRUC;
-#endif
+
 //
 //  4.2 MAC TIMING  configuration registers (offset:0x1100)
 //
 #define XIFS_TIME_CFG             0x1100		 // MAC_CSR8  MAC_CSR9
-#ifdef RT_BIG_ENDIAN
-typedef	union	_IFS_SLOT_CFG_STRUC	{
-	struct	{
-	    UINT32  rsv:2;
-	    UINT32  BBRxendEnable:1;        //  reference RXEND signal to begin XIFS defer
-	    UINT32  EIFS:9;        //  unit 1us
-	    UINT32  OfdmXifsTime:4;        //OFDM SIFS. unit 1us. Applied after OFDM RX when MAC doesn't reference BBP signal BBRXEND
-	    UINT32  OfdmSifsTime:8;        //  unit 1us. Applied after OFDM RX/TX
-	    UINT32  CckmSifsTime:8;        //  unit 1us. Applied after CCK RX/TX
-	}	field;
-	UINT32			word;
-}	IFS_SLOT_CFG_STRUC, *PIFS_SLOT_CFG_STRUC;
-#else
 typedef	union	_IFS_SLOT_CFG_STRUC	{
 	struct	{
 	    UINT32  CckmSifsTime:8;        //  unit 1us. Applied after CCK RX/TX
@@ -715,7 +426,6 @@ typedef	union	_IFS_SLOT_CFG_STRUC	{
 	}	field;
 	UINT32			word;
 }	IFS_SLOT_CFG_STRUC, *PIFS_SLOT_CFG_STRUC;
-#endif
 
 #define BKOFF_SLOT_CFG             0x1104		 //  mac_csr9 last 8 bits
 #define NAV_TIME_CFG             0x1108		 // NAV  (MAC_CSR15)
@@ -729,20 +439,6 @@ typedef	union	_IFS_SLOT_CFG_STRUC	{
 //
 // BCN_TIME_CFG : Synchronization control register
 //
-#ifdef RT_BIG_ENDIAN
-typedef	union	_BCN_TIME_CFG_STRUC	{
-	struct	{
-		UINT32		TxTimestampCompensate:8;
-        UINT32       :3;
-		UINT32		bBeaconGen:1;		// Enable beacon generator
-        UINT32       bTBTTEnable:1;
-		UINT32		TsfSyncMode:2;		// Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
-		UINT32		bTsfTicking:1;		// Enable TSF auto counting
-		UINT32       BeaconInterval:16;  // in unit of 1/16 TU
-	}	field;
-	UINT32			word;
-}	BCN_TIME_CFG_STRUC, *PBCN_TIME_CFG_STRUC;
-#else
 typedef	union	_BCN_TIME_CFG_STRUC	{
 	struct	{
 		UINT32       BeaconInterval:16;  // in unit of 1/16 TU
@@ -755,7 +451,7 @@ typedef	union	_BCN_TIME_CFG_STRUC	{
 	}	field;
 	UINT32			word;
 }	BCN_TIME_CFG_STRUC, *PBCN_TIME_CFG_STRUC;
-#endif
+
 #define TBTT_SYNC_CFG            0x1118  		// txrx_csr10
 #define TSF_TIMER_DW0             0x111C  		// Local TSF timer lsb 32 bits. Read-only
 #define TSF_TIMER_DW1             0x1120  		// msb 32 bits. Read-only.
@@ -773,17 +469,6 @@ typedef	union	_BCN_TIME_CFG_STRUC	{
 //
 // AUTO_WAKEUP_CFG: Manual power control / status register
 //
-#ifdef RT_BIG_ENDIAN
-typedef	union	_AUTO_WAKEUP_STRUC	{
-	struct	{
-		UINT32		:16;
-		UINT32		EnableAutoWakeup:1;	// 0:sleep, 1:awake
-		UINT32       NumofSleepingTbtt:7;          // ForceWake has high privilege than PutToSleep when both set
-		UINT32       AutoLeadTime:8;
-	}	field;
-	UINT32			word;
-}	AUTO_WAKEUP_STRUC, *PAUTO_WAKEUP_STRUC;
-#else
 typedef	union	_AUTO_WAKEUP_STRUC	{
 	struct	{
 		UINT32       AutoLeadTime:8;
@@ -793,7 +478,7 @@ typedef	union	_AUTO_WAKEUP_STRUC	{
 	}	field;
 	UINT32			word;
 }	AUTO_WAKEUP_STRUC, *PAUTO_WAKEUP_STRUC;
-#endif
+
 //
 //  4.3 MAC TX  configuration registers (offset:0x1300)
 //
@@ -802,18 +487,6 @@ typedef	union	_AUTO_WAKEUP_STRUC	{
 #define EDCA_AC1_CFG	0x1304
 #define EDCA_AC2_CFG	0x1308
 #define EDCA_AC3_CFG	0x130c
-#ifdef RT_BIG_ENDIAN
-typedef	union	_EDCA_AC_CFG_STRUC	{
-	struct	{
-	    UINT32  :12;        //
-	    UINT32  Cwmax:4;        //unit power of 2
-	    UINT32  Cwmin:4;        //
-	    UINT32  Aifsn:4;        // # of slot time
-	    UINT32  AcTxop:8;        //  in unit of 32us
-	}	field;
-	UINT32			word;
-}	EDCA_AC_CFG_STRUC, *PEDCA_AC_CFG_STRUC;
-#else
 typedef	union	_EDCA_AC_CFG_STRUC	{
 	struct	{
 	    UINT32  AcTxop:8;        //  in unit of 32us
@@ -824,7 +497,6 @@ typedef	union	_EDCA_AC_CFG_STRUC	{
 	}	field;
 	UINT32			word;
 }	EDCA_AC_CFG_STRUC, *PEDCA_AC_CFG_STRUC;
-#endif
 
 #define EDCA_TID_AC_MAP	0x1310
 #define TX_PWR_CFG_0	0x1314
@@ -841,17 +513,6 @@ typedef	union	_EDCA_AC_CFG_STRUC	{
 #define TXOP_CTRL_CFG		0x1340
 #define TX_RTS_CFG		0x1344
 
-#ifdef RT_BIG_ENDIAN
-typedef	union	_TX_RTS_CFG_STRUC	{
-	struct	{
-	    UINT32       rsv:7;
-	    UINT32       RtsFbkEn:1;    // enable rts rate fallback
-	    UINT32       RtsThres:16;    // unit:byte
-	    UINT32       AutoRtsRetryLimit:8;
-	}	field;
-	UINT32			word;
-}	TX_RTS_CFG_STRUC, *PTX_RTS_CFG_STRUC;
-#else
 typedef	union	_TX_RTS_CFG_STRUC	{
 	struct	{
 	    UINT32       AutoRtsRetryLimit:8;
@@ -861,20 +522,8 @@ typedef	union	_TX_RTS_CFG_STRUC	{
 	}	field;
 	UINT32			word;
 }	TX_RTS_CFG_STRUC, *PTX_RTS_CFG_STRUC;
-#endif
+
 #define TX_TIMEOUT_CFG	0x1348
-#ifdef RT_BIG_ENDIAN
-typedef	union	_TX_TIMEOUT_CFG_STRUC	{
-	struct	{
-	    UINT32       rsv2:8;
-	    UINT32       TxopTimeout:8;	//TXOP timeout value for TXOP truncation.  It is recommended that (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
-	    UINT32       RxAckTimeout:8;	// unit:slot. Used for TX precedure
-	    UINT32       MpduLifeTime:4;    //  expiration time = 2^(9+MPDU LIFE TIME)  us
-	    UINT32       rsv:4;
-	}	field;
-	UINT32			word;
-}	TX_TIMEOUT_CFG_STRUC, *PTX_TIMEOUT_CFG_STRUC;
-#else
 typedef	union	_TX_TIMEOUT_CFG_STRUC	{
 	struct	{
 	    UINT32       rsv:4;
@@ -885,23 +534,8 @@ typedef	union	_TX_TIMEOUT_CFG_STRUC	{
 	}	field;
 	UINT32			word;
 }	TX_TIMEOUT_CFG_STRUC, *PTX_TIMEOUT_CFG_STRUC;
-#endif
-#define TX_RTY_CFG	0x134c
-#ifdef RT_BIG_ENDIAN
-typedef	union PACKED _TX_RTY_CFG_STRUC	{
-	struct	{
-	    UINT32       rsv:1;
-	    UINT32       TxautoFBEnable:1;    // Tx retry PHY rate auto fallback enable
-	    UINT32       AggRtyMode:1;	// Aggregate MPDU retry mode.  0:expired by retry limit, 1: expired by mpdu life timer
-	    UINT32       NonAggRtyMode:1;	// Non-Aggregate MPDU retry mode.  0:expired by retry limit, 1: expired by mpdu life timer
-	    UINT32       LongRtyThre:12;	// Long retry threshoold
-	    UINT32       LongRtyLimit:8;	//long retry limit
-	    UINT32       ShortRtyLimit:8;	//  short retry limit
 
-	}	field;
-	UINT32			word;
-}	TX_RTY_CFG_STRUC, *PTX_RTY_CFG_STRUC;
-#else
+#define TX_RTY_CFG	0x134c
 typedef	union PACKED _TX_RTY_CFG_STRUC	{
 	struct	{
 	    UINT32       ShortRtyLimit:8;	//  short retry limit
@@ -914,24 +548,8 @@ typedef	union PACKED _TX_RTY_CFG_STRUC	{
 	}	field;
 	UINT32			word;
 }	TX_RTY_CFG_STRUC, *PTX_RTY_CFG_STRUC;
-#endif
+
 #define TX_LINK_CFG	0x1350
-#ifdef RT_BIG_ENDIAN
-typedef	union	PACKED _TX_LINK_CFG_STRUC	{
-	struct PACKED {
-	    UINT32       RemotMFS:8;	//remote MCS feedback sequence number
-	    UINT32       RemotMFB:8;    //  remote MCS feedback
-	    UINT32       rsv:3;	//
-	    UINT32       TxCFAckEn:1;	//   Piggyback CF-ACK enable
-	    UINT32       TxRDGEn:1;	// RDG TX enable
-	    UINT32       TxMRQEn:1;	//  MCS request TX enable
-	    UINT32       RemoteUMFSEnable:1;	//  remote unsolicit  MFB enable.  0: not apply remote remote unsolicit (MFS=7)
-	    UINT32       MFBEnable:1;	//  TX apply remote MFB 1:enable
-	    UINT32       RemoteMFBLifeTime:8;	//remote MFB life time. unit : 32us
-	}	field;
-	UINT32			word;
-}	TX_LINK_CFG_STRUC, *PTX_LINK_CFG_STRUC;
-#else
 typedef	union	PACKED _TX_LINK_CFG_STRUC	{
 	struct PACKED {
 	    UINT32       RemoteMFBLifeTime:8;	//remote MFB life time. unit : 32us
@@ -946,23 +564,8 @@ typedef	union	PACKED _TX_LINK_CFG_STRUC	{
 	}	field;
 	UINT32			word;
 }	TX_LINK_CFG_STRUC, *PTX_LINK_CFG_STRUC;
-#endif
+
 #define HT_FBK_CFG0	0x1354
-#ifdef RT_BIG_ENDIAN
-typedef	union PACKED _HT_FBK_CFG0_STRUC	{
-	struct	{
-	    UINT32       HTMCS7FBK:4;
-	    UINT32       HTMCS6FBK:4;
-	    UINT32       HTMCS5FBK:4;
-	    UINT32       HTMCS4FBK:4;
-	    UINT32       HTMCS3FBK:4;
-	    UINT32       HTMCS2FBK:4;
-	    UINT32       HTMCS1FBK:4;
-	    UINT32       HTMCS0FBK:4;
-	}	field;
-	UINT32			word;
-}	HT_FBK_CFG0_STRUC, *PHT_FBK_CFG0_STRUC;
-#else
 typedef	union PACKED _HT_FBK_CFG0_STRUC	{
 	struct	{
 	    UINT32       HTMCS0FBK:4;
@@ -976,23 +579,8 @@ typedef	union PACKED _HT_FBK_CFG0_STRUC	{
 	}	field;
 	UINT32			word;
 }	HT_FBK_CFG0_STRUC, *PHT_FBK_CFG0_STRUC;
-#endif
+
 #define HT_FBK_CFG1	0x1358
-#ifdef RT_BIG_ENDIAN
-typedef	union	_HT_FBK_CFG1_STRUC	{
-	struct	{
-	    UINT32       HTMCS15FBK:4;
-	    UINT32       HTMCS14FBK:4;
-	    UINT32       HTMCS13FBK:4;
-	    UINT32       HTMCS12FBK:4;
-	    UINT32       HTMCS11FBK:4;
-	    UINT32       HTMCS10FBK:4;
-	    UINT32       HTMCS9FBK:4;
-	    UINT32       HTMCS8FBK:4;
-	}	field;
-	UINT32			word;
-}	HT_FBK_CFG1_STRUC, *PHT_FBK_CFG1_STRUC;
-#else
 typedef	union	_HT_FBK_CFG1_STRUC	{
 	struct	{
 	    UINT32       HTMCS8FBK:4;
@@ -1006,23 +594,8 @@ typedef	union	_HT_FBK_CFG1_STRUC	{
 	}	field;
 	UINT32			word;
 }	HT_FBK_CFG1_STRUC, *PHT_FBK_CFG1_STRUC;
-#endif
+
 #define LG_FBK_CFG0	0x135c
-#ifdef RT_BIG_ENDIAN
-typedef	union	_LG_FBK_CFG0_STRUC	{
-	struct	{
-	    UINT32       OFDMMCS7FBK:4;	//initial value is 6
-	    UINT32       OFDMMCS6FBK:4;	//initial value is 5
-	    UINT32       OFDMMCS5FBK:4;	//initial value is 4
-	    UINT32       OFDMMCS4FBK:4;	//initial value is 3
-	    UINT32       OFDMMCS3FBK:4;	//initial value is 2
-	    UINT32       OFDMMCS2FBK:4;	//initial value is 1
-	    UINT32       OFDMMCS1FBK:4;	//initial value is 0
-	    UINT32       OFDMMCS0FBK:4;	//initial value is 0
-	}	field;
-	UINT32			word;
-}	LG_FBK_CFG0_STRUC, *PLG_FBK_CFG0_STRUC;
-#else
 typedef	union	_LG_FBK_CFG0_STRUC	{
 	struct	{
 	    UINT32       OFDMMCS0FBK:4;	//initial value is 0
@@ -1036,20 +609,8 @@ typedef	union	_LG_FBK_CFG0_STRUC	{
 	}	field;
 	UINT32			word;
 }	LG_FBK_CFG0_STRUC, *PLG_FBK_CFG0_STRUC;
-#endif
+
 #define LG_FBK_CFG1		0x1360
-#ifdef RT_BIG_ENDIAN
-typedef	union	_LG_FBK_CFG1_STRUC	{
-	struct	{
-	    UINT32       rsv:16;
-	    UINT32       CCKMCS3FBK:4;	//initial value is 2
-	    UINT32       CCKMCS2FBK:4;	//initial value is 1
-	    UINT32       CCKMCS1FBK:4;	//initial value is 0
-	    UINT32       CCKMCS0FBK:4;	//initial value is 0
-	}	field;
-	UINT32			word;
-}	LG_FBK_CFG1_STRUC, *PLG_FBK_CFG1_STRUC;
-#else
 typedef	union	_LG_FBK_CFG1_STRUC	{
 	struct	{
 	    UINT32       CCKMCS0FBK:4;	//initial value is 0
@@ -1060,7 +621,6 @@ typedef	union	_LG_FBK_CFG1_STRUC	{
 	}	field;
 	UINT32			word;
 }	LG_FBK_CFG1_STRUC, *PLG_FBK_CFG1_STRUC;
-#endif
 
 //=======================================================
 //================ Protection Paramater================================
@@ -1070,24 +630,6 @@ typedef	union	_LG_FBK_CFG1_STRUC	{
 #define ASIC_LONGNAV		2
 #define ASIC_RTS		1
 #define ASIC_CTS		2
-#ifdef RT_BIG_ENDIAN
-typedef	union	_PROT_CFG_STRUC	{
-	struct	{
-	    UINT32       rsv:5;
-	    UINT32       RTSThEn:1;	//RTS threshold enable on CCK TX
-	    UINT32       TxopAllowGF40:1;	//CCK TXOP allowance.0:disallow.
-	    UINT32       TxopAllowGF20:1;	//CCK TXOP allowance.0:disallow.
-	    UINT32       TxopAllowMM40:1;	//CCK TXOP allowance.0:disallow.
-	    UINT32       TxopAllowMM20:1;	//CCK TXOP allowance. 0:disallow.
-	    UINT32       TxopAllowOfdm:1;	//CCK TXOP allowance.0:disallow.
-	    UINT32       TxopAllowCck:1;	//CCK TXOP allowance.0:disallow.
-	    UINT32       ProtectNav:2;	//TXOP protection type for CCK TX. 0:None, 1:ShortNAVprotect,  2:LongNAVProtect, 3:rsv
-	    UINT32       ProtectCtrl:2;	//Protection control frame type for CCK TX. 1:RTS/CTS, 2:CTS-to-self, 0:None, 3:rsv
-	    UINT32       ProtectRate:16;	//Protection control frame rate for CCK TX(RTS/CTS/CFEnd).
-	}	field;
-	UINT32			word;
-}	PROT_CFG_STRUC, *PPROT_CFG_STRUC;
-#else
 typedef	union	_PROT_CFG_STRUC	{
 	struct	{
 	    UINT32       ProtectRate:16;	//Protection control frame rate for CCK TX(RTS/CTS/CFEnd).
@@ -1104,7 +646,6 @@ typedef	union	_PROT_CFG_STRUC	{
 	}	field;
 	UINT32			word;
 }	PROT_CFG_STRUC, *PPROT_CFG_STRUC;
-#endif
 
 #define OFDM_PROT_CFG	0x1368		//OFDM Protection
 #define MM20_PROT_CFG	0x136C		//MM20 Protection
@@ -1122,22 +663,6 @@ typedef	union	_PROT_CFG_STRUC	{
 //
 // TXRX_CSR4: Auto-Responder/
 //
-#ifdef RT_BIG_ENDIAN
-typedef union _AUTO_RSP_CFG_STRUC {
- struct {
-     UINT32        :24;
-     UINT32       AckCtsPsmBit:1;   // Power bit value in conrtrol frame
-     UINT32       DualCTSEn:1;   // Power bit value in conrtrol frame
-     UINT32       rsv:1;   // Power bit value in conrtrol frame
-     UINT32       AutoResponderPreamble:1;    // 0:long, 1:short preamble
-     UINT32       CTS40MRef:1;  // Response CTS 40MHz duplicate mode
-     UINT32       CTS40MMode:1;  // Response CTS 40MHz duplicate mode
-     UINT32       BACAckPolicyEnable:1;    // 0:long, 1:short preamble
-     UINT32       AutoResponderEnable:1;
- } field;
- UINT32   word;
-} AUTO_RSP_CFG_STRUC, *PAUTO_RSP_CFG_STRUC;
-#else
 typedef union _AUTO_RSP_CFG_STRUC {
  struct {
      UINT32       AutoResponderEnable:1;
@@ -1152,7 +677,6 @@ typedef union _AUTO_RSP_CFG_STRUC {
  } field;
  UINT32   word;
 } AUTO_RSP_CFG_STRUC, *PAUTO_RSP_CFG_STRUC;
-#endif
 
 #define LEGACY_BASIC_RATE	0x1408	//  TXRX_CSR5           0x3054
 #define HT_BASIC_RATE		0x140c
@@ -1185,15 +709,6 @@ typedef union _AUTO_RSP_CFG_STRUC {
 //
 // RX_STA_CNT0_STRUC: RX PLCP error count & RX CRC error count
 //
-#ifdef RT_BIG_ENDIAN
-typedef	union	_RX_STA_CNT0_STRUC	{
-	struct	{
-	    USHORT  PhyErr;
-	    USHORT  CrcErr;
-	}	field;
-	UINT32			word;
-}	RX_STA_CNT0_STRUC, *PRX_STA_CNT0_STRUC;
-#else
 typedef	union	_RX_STA_CNT0_STRUC	{
 	struct	{
 	    USHORT  CrcErr;
@@ -1201,20 +716,10 @@ typedef	union	_RX_STA_CNT0_STRUC	{
 	}	field;
 	UINT32			word;
 }	RX_STA_CNT0_STRUC, *PRX_STA_CNT0_STRUC;
-#endif
 
 //
 // RX_STA_CNT1_STRUC: RX False CCA count & RX LONG frame count
 //
-#ifdef RT_BIG_ENDIAN
-typedef	union	_RX_STA_CNT1_STRUC	{
-	struct	{
-	    USHORT  PlcpErr;
-	    USHORT  FalseCca;
-	}	field;
-	UINT32			word;
-}	RX_STA_CNT1_STRUC, *PRX_STA_CNT1_STRUC;
-#else
 typedef	union	_RX_STA_CNT1_STRUC	{
 	struct	{
 	    USHORT  FalseCca;
@@ -1222,20 +727,10 @@ typedef	union	_RX_STA_CNT1_STRUC	{
 	}	field;
 	UINT32			word;
 }	RX_STA_CNT1_STRUC, *PRX_STA_CNT1_STRUC;
-#endif
 
 //
 // RX_STA_CNT2_STRUC:
 //
-#ifdef RT_BIG_ENDIAN
-typedef	union	_RX_STA_CNT2_STRUC	{
-	struct	{
-	    USHORT  RxFifoOverflowCount;
-	    USHORT  RxDupliCount;
-	}	field;
-	UINT32			word;
-}	RX_STA_CNT2_STRUC, *PRX_STA_CNT2_STRUC;
-#else
 typedef	union	_RX_STA_CNT2_STRUC	{
 	struct	{
 	    USHORT  RxDupliCount;
@@ -1243,20 +738,11 @@ typedef	union	_RX_STA_CNT2_STRUC	{
 	}	field;
 	UINT32			word;
 }	RX_STA_CNT2_STRUC, *PRX_STA_CNT2_STRUC;
-#endif
+
 #define TX_STA_CNT0		0x170C		//
 //
 // STA_CSR3: TX Beacon count
 //
-#ifdef RT_BIG_ENDIAN
-typedef	union	_TX_STA_CNT0_STRUC	{
-	struct	{
-	    USHORT  TxBeaconCount;
-	    USHORT  TxFailCount;
-	}	field;
-	UINT32			word;
-}	TX_STA_CNT0_STRUC, *PTX_STA_CNT0_STRUC;
-#else
 typedef	union	_TX_STA_CNT0_STRUC	{
 	struct	{
 	    USHORT  TxFailCount;
@@ -1264,20 +750,11 @@ typedef	union	_TX_STA_CNT0_STRUC	{
 	}	field;
 	UINT32			word;
 }	TX_STA_CNT0_STRUC, *PTX_STA_CNT0_STRUC;
-#endif
+
 #define TX_STA_CNT1		0x1710		//
 //
 // TX_STA_CNT1: TX tx count
 //
-#ifdef RT_BIG_ENDIAN
-typedef	union	_TX_STA_CNT1_STRUC	{
-	struct	{
-	    USHORT  TxRetransmit;
-	    USHORT  TxSuccess;
-	}	field;
-	UINT32			word;
-}	TX_STA_CNT1_STRUC, *PTX_STA_CNT1_STRUC;
-#else
 typedef	union	_TX_STA_CNT1_STRUC	{
 	struct	{
 	    USHORT  TxSuccess;
@@ -1285,20 +762,11 @@ typedef	union	_TX_STA_CNT1_STRUC	{
 	}	field;
 	UINT32			word;
 }	TX_STA_CNT1_STRUC, *PTX_STA_CNT1_STRUC;
-#endif
+
 #define TX_STA_CNT2		0x1714		//
 //
 // TX_STA_CNT2: TX tx count
 //
-#ifdef RT_BIG_ENDIAN
-typedef	union	_TX_STA_CNT2_STRUC	{
-	struct	{
-	    USHORT  TxUnderFlowCount;
-	    USHORT  TxZeroLenCount;
-	}	field;
-	UINT32			word;
-}	TX_STA_CNT2_STRUC, *PTX_STA_CNT2_STRUC;
-#else
 typedef	union	_TX_STA_CNT2_STRUC	{
 	struct	{
 	    USHORT  TxZeroLenCount;
@@ -1306,28 +774,11 @@ typedef	union	_TX_STA_CNT2_STRUC	{
 	}	field;
 	UINT32			word;
 }	TX_STA_CNT2_STRUC, *PTX_STA_CNT2_STRUC;
-#endif
+
 #define TX_STA_FIFO		0x1718		//
 //
 // TX_STA_FIFO_STRUC: TX Result for specific PID status fifo register
 //
-#ifdef RT_BIG_ENDIAN
-typedef	union PACKED _TX_STA_FIFO_STRUC	{
-	struct	{
-		UINT32		Reserve:2;
-		UINT32		TxBF:1; // 3*3
-		UINT32		SuccessRate:13;	//include MCS, mode ,shortGI, BW settingSame format as TXWI Word 0 Bit 31-16.
-//		UINT32		SuccessRate:16;	//include MCS, mode ,shortGI, BW settingSame format as TXWI Word 0 Bit 31-16.
-		UINT32		wcid:8;		//wireless client index
-		UINT32       	TxAckRequired:1;    // ack required
-		UINT32       	TxAggre:1;    // Tx is aggregated
-		UINT32       	TxSuccess:1;   // Tx success. whether success or not
-		UINT32       	PidType:4;
-		UINT32       	bValid:1;   // 1:This register contains a valid TX result
-	}	field;
-	UINT32			word;
-}	TX_STA_FIFO_STRUC, *PTX_STA_FIFO_STRUC;
-#else
 typedef	union PACKED _TX_STA_FIFO_STRUC	{
 	struct	{
 		UINT32       	bValid:1;   // 1:This register contains a valid TX result
@@ -1343,18 +794,9 @@ typedef	union PACKED _TX_STA_FIFO_STRUC	{
 	}	field;
 	UINT32			word;
 }	TX_STA_FIFO_STRUC, *PTX_STA_FIFO_STRUC;
-#endif
+
 // Debug counter
 #define TX_AGG_CNT	0x171c
-#ifdef RT_BIG_ENDIAN
-typedef	union	_TX_AGG_CNT_STRUC	{
-	struct	{
-	    USHORT  AggTxCount;
-	    USHORT  NonAggTxCount;
-	}	field;
-	UINT32			word;
-}	TX_AGG_CNT_STRUC, *PTX_AGG_CNT_STRUC;
-#else
 typedef	union	_TX_AGG_CNT_STRUC	{
 	struct	{
 	    USHORT  NonAggTxCount;
@@ -1362,18 +804,9 @@ typedef	union	_TX_AGG_CNT_STRUC	{
 	}	field;
 	UINT32			word;
 }	TX_AGG_CNT_STRUC, *PTX_AGG_CNT_STRUC;
-#endif
+
 // Debug counter
 #define TX_AGG_CNT0	0x1720
-#ifdef RT_BIG_ENDIAN
-typedef	union	_TX_AGG_CNT0_STRUC	{
-	struct	{
-	    USHORT  AggSize2Count;
-	    USHORT  AggSize1Count;
-	}	field;
-	UINT32			word;
-}	TX_AGG_CNT0_STRUC, *PTX_AGG_CNT0_STRUC;
-#else
 typedef	union	_TX_AGG_CNT0_STRUC	{
 	struct	{
 	    USHORT  AggSize1Count;
@@ -1381,18 +814,9 @@ typedef	union	_TX_AGG_CNT0_STRUC	{
 	}	field;
 	UINT32			word;
 }	TX_AGG_CNT0_STRUC, *PTX_AGG_CNT0_STRUC;
-#endif
+
 // Debug counter
 #define TX_AGG_CNT1	0x1724
-#ifdef RT_BIG_ENDIAN
-typedef	union	_TX_AGG_CNT1_STRUC	{
-	struct	{
-	    USHORT  AggSize4Count;
-	    USHORT  AggSize3Count;
-	}	field;
-	UINT32			word;
-}	TX_AGG_CNT1_STRUC, *PTX_AGG_CNT1_STRUC;
-#else
 typedef	union	_TX_AGG_CNT1_STRUC	{
 	struct	{
 	    USHORT  AggSize3Count;
@@ -1400,17 +824,8 @@ typedef	union	_TX_AGG_CNT1_STRUC	{
 	}	field;
 	UINT32			word;
 }	TX_AGG_CNT1_STRUC, *PTX_AGG_CNT1_STRUC;
-#endif
+
 #define TX_AGG_CNT2	0x1728
-#ifdef RT_BIG_ENDIAN
-typedef	union	_TX_AGG_CNT2_STRUC	{
-	struct	{
-	    USHORT  AggSize6Count;
-	    USHORT  AggSize5Count;
-	}	field;
-	UINT32			word;
-}	TX_AGG_CNT2_STRUC, *PTX_AGG_CNT2_STRUC;
-#else
 typedef	union	_TX_AGG_CNT2_STRUC	{
 	struct	{
 	    USHORT  AggSize5Count;
@@ -1418,18 +833,9 @@ typedef	union	_TX_AGG_CNT2_STRUC	{
 	}	field;
 	UINT32			word;
 }	TX_AGG_CNT2_STRUC, *PTX_AGG_CNT2_STRUC;
-#endif
+
 // Debug counter
 #define TX_AGG_CNT3	0x172c
-#ifdef RT_BIG_ENDIAN
-typedef	union	_TX_AGG_CNT3_STRUC	{
-	struct	{
-	    USHORT  AggSize8Count;
-	    USHORT  AggSize7Count;
-	}	field;
-	UINT32			word;
-}	TX_AGG_CNT3_STRUC, *PTX_AGG_CNT3_STRUC;
-#else
 typedef	union	_TX_AGG_CNT3_STRUC	{
 	struct	{
 	    USHORT  AggSize7Count;
@@ -1437,18 +843,9 @@ typedef	union	_TX_AGG_CNT3_STRUC	{
 	}	field;
 	UINT32			word;
 }	TX_AGG_CNT3_STRUC, *PTX_AGG_CNT3_STRUC;
-#endif
+
 // Debug counter
 #define TX_AGG_CNT4	0x1730
-#ifdef RT_BIG_ENDIAN
-typedef	union	_TX_AGG_CNT4_STRUC	{
-	struct	{
-	    USHORT  AggSize10Count;
-	    USHORT  AggSize9Count;
-	}	field;
-	UINT32			word;
-}	TX_AGG_CNT4_STRUC, *PTX_AGG_CNT4_STRUC;
-#else
 typedef	union	_TX_AGG_CNT4_STRUC	{
 	struct	{
 	    USHORT  AggSize9Count;
@@ -1456,17 +853,8 @@ typedef	union	_TX_AGG_CNT4_STRUC	{
 	}	field;
 	UINT32			word;
 }	TX_AGG_CNT4_STRUC, *PTX_AGG_CNT4_STRUC;
-#endif
+
 #define TX_AGG_CNT5	0x1734
-#ifdef RT_BIG_ENDIAN
-typedef	union	_TX_AGG_CNT5_STRUC	{
-	struct	{
-	    USHORT  AggSize12Count;
-	    USHORT  AggSize11Count;
-	}	field;
-	UINT32			word;
-}	TX_AGG_CNT5_STRUC, *PTX_AGG_CNT5_STRUC;
-#else
 typedef	union	_TX_AGG_CNT5_STRUC	{
 	struct	{
 	    USHORT  AggSize11Count;
@@ -1474,17 +862,8 @@ typedef	union	_TX_AGG_CNT5_STRUC	{
 	}	field;
 	UINT32			word;
 }	TX_AGG_CNT5_STRUC, *PTX_AGG_CNT5_STRUC;
-#endif
+
 #define TX_AGG_CNT6		0x1738
-#ifdef RT_BIG_ENDIAN
-typedef	union	_TX_AGG_CNT6_STRUC	{
-	struct	{
-	    USHORT  AggSize14Count;
-	    USHORT  AggSize13Count;
-	}	field;
-	UINT32			word;
-}	TX_AGG_CNT6_STRUC, *PTX_AGG_CNT6_STRUC;
-#else
 typedef	union	_TX_AGG_CNT6_STRUC	{
 	struct	{
 	    USHORT  AggSize13Count;
@@ -1492,17 +871,8 @@ typedef	union	_TX_AGG_CNT6_STRUC	{
 	}	field;
 	UINT32			word;
 }	TX_AGG_CNT6_STRUC, *PTX_AGG_CNT6_STRUC;
-#endif
+
 #define TX_AGG_CNT7		0x173c
-#ifdef RT_BIG_ENDIAN
-typedef	union	_TX_AGG_CNT7_STRUC	{
-	struct	{
-	    USHORT  AggSize16Count;
-	    USHORT  AggSize15Count;
-	}	field;
-	UINT32			word;
-}	TX_AGG_CNT7_STRUC, *PTX_AGG_CNT7_STRUC;
-#else
 typedef	union	_TX_AGG_CNT7_STRUC	{
 	struct	{
 	    USHORT  AggSize15Count;
@@ -1510,17 +880,8 @@ typedef	union	_TX_AGG_CNT7_STRUC	{
 	}	field;
 	UINT32			word;
 }	TX_AGG_CNT7_STRUC, *PTX_AGG_CNT7_STRUC;
-#endif
+
 #define MPDU_DENSITY_CNT		0x1740
-#ifdef RT_BIG_ENDIAN
-typedef	union	_MPDU_DEN_CNT_STRUC	{
-	struct	{
-	    USHORT  RXZeroDelCount;	//RX zero length delimiter count
-	    USHORT  TXZeroDelCount;	//TX zero length delimiter count
-	}	field;
-	UINT32			word;
-}	MPDU_DEN_CNT_STRUC, *PMPDU_DEN_CNT_STRUC;
-#else
 typedef	union	_MPDU_DEN_CNT_STRUC	{
 	struct	{
 	    USHORT  TXZeroDelCount;	//TX zero length delimiter count
@@ -1528,7 +889,7 @@ typedef	union	_MPDU_DEN_CNT_STRUC	{
 	}	field;
 	UINT32			word;
 }	MPDU_DEN_CNT_STRUC, *PMPDU_DEN_CNT_STRUC;
-#endif
+
 //
 // TXRX control registers - base address 0x3000
 //
@@ -1554,30 +915,6 @@ typedef	union	_MPDU_DEN_CNT_STRUC	{
 #define SHAREDKEYTABLE			0
 #define PAIRWISEKEYTABLE			1
 
-
-#ifdef RT_BIG_ENDIAN
-typedef	union	_SHAREDKEY_MODE_STRUC	{
-	struct	{
-		UINT32       :1;
-		UINT32       Bss1Key3CipherAlg:3;
-		UINT32       :1;
-		UINT32       Bss1Key2CipherAlg:3;
-		UINT32       :1;
-		UINT32       Bss1Key1CipherAlg:3;
-		UINT32       :1;
-		UINT32       Bss1Key0CipherAlg:3;
-		UINT32       :1;
-		UINT32       Bss0Key3CipherAlg:3;
-		UINT32       :1;
-		UINT32       Bss0Key2CipherAlg:3;
-		UINT32       :1;
-		UINT32       Bss0Key1CipherAlg:3;
-		UINT32       :1;
-		UINT32       Bss0Key0CipherAlg:3;
-	}	field;
-	UINT32			word;
-}	SHAREDKEY_MODE_STRUC, *PSHAREDKEY_MODE_STRUC;
-#else
 typedef	union	_SHAREDKEY_MODE_STRUC	{
 	struct	{
 		UINT32       Bss0Key0CipherAlg:3;
@@ -1599,7 +936,7 @@ typedef	union	_SHAREDKEY_MODE_STRUC	{
 	}	field;
 	UINT32			word;
 }	SHAREDKEY_MODE_STRUC, *PSHAREDKEY_MODE_STRUC;
-#endif
+
 // 64-entry for pairwise key table
 typedef struct _HW_WCID_ENTRY {  // 8-byte per entry
     UCHAR   Address[6];
@@ -1872,15 +1209,6 @@ typedef struct _HW_KEY_ENTRY {          // 32-byte per entry
 //8.1.2	IV/EIV  format  : 2DW
 
 //8.1.3	RX attribute entry format  : 1DW
-#ifdef RT_BIG_ENDIAN
-typedef	struct	_MAC_ATTRIBUTE_STRUC {
-	UINT32		rsv:22;
-	UINT32		RXWIUDF:3;
-	UINT32		BSSIDIdx:3; //multipleBSS index for the WCID
-	UINT32		PairKeyMode:3;
-	UINT32		KeyTab:1;	// 0 for shared key table.  1 for pairwise key table
-}	MAC_ATTRIBUTE_STRUC, *PMAC_ATTRIBUTE_STRUC;
-#else
 typedef	struct	_MAC_ATTRIBUTE_STRUC {
 	UINT32		KeyTab:1;	// 0 for shared key table.  1 for pairwise key table
 	UINT32		PairKeyMode:3;
@@ -1888,8 +1216,6 @@ typedef	struct	_MAC_ATTRIBUTE_STRUC {
 	UINT32		RXWIUDF:3;
 	UINT32		rsv:22;
 }	MAC_ATTRIBUTE_STRUC, *PMAC_ATTRIBUTE_STRUC;
-#endif
-
 
 // =================================================================================
 // TX / RX ring descriptor format
@@ -1904,29 +1230,6 @@ typedef	struct	_MAC_ATTRIBUTE_STRUC {
 //
 // TX descriptor format, Tx	ring, Mgmt Ring
 //
-#ifdef RT_BIG_ENDIAN
-typedef	struct	PACKED _TXD_STRUC {
-	// Word 0
-	UINT32		SDPtr0;
-	// Word 1
-	UINT32		DMADONE:1;
-	UINT32		LastSec0:1;
-	UINT32		SDLen0:14;
-	UINT32		Burst:1;
-	UINT32		LastSec1:1;
-	UINT32		SDLen1:14;
-	// Word 2
-	UINT32		SDPtr1;
-	// Word 3
-	UINT32		ICO:1;
-	UINT32		UCO:1;
-	UINT32		TCO:1;
-	UINT32		rsv:2;
-	UINT32		QSEL:2;	// select on-chip FIFO ID for 2nd-stage output scheduler.0:MGMT, 1:HCCA 2:EDCA
-	UINT32		WIV:1;	// Wireless Info Valid. 1 if Driver already fill WI,  o if DMA needs to copy WI to correctposition
-	UINT32		rsv2:24;
-}	TXD_STRUC, *PTXD_STRUC;
-#else
 typedef	struct	PACKED _TXD_STRUC {
 	// Word	0
 	UINT32		SDPtr0;
@@ -1948,8 +1251,6 @@ typedef	struct	PACKED _TXD_STRUC {
 	UINT32		UCO:1;	//
 	UINT32		ICO:1;	//
 }	TXD_STRUC, *PTXD_STRUC;
-#endif
-
 
 //
 // TXD Wireless Information format for Tx ring and Mgmt Ring
@@ -1957,40 +1258,6 @@ typedef	struct	PACKED _TXD_STRUC {
 //txop : for txop mode
 // 0:txop for the MPDU frame will be handles by ASIC by register
 // 1/2/3:the MPDU frame is send after PIFS/backoff/SIFS
-#ifdef RT_BIG_ENDIAN
-typedef	struct	PACKED _TXWI_STRUC {
-	// Word 0
-	UINT32		PHYMODE:2;
-	UINT32		TxBF:1;	// 3*3
-	UINT32		rsv2:1;
-	UINT32		Ifs:1;	//
-	UINT32		STBC:2;	//channel bandwidth 20MHz or 40 MHz
-	UINT32		ShortGI:1;
-	UINT32		BW:1;	//channel bandwidth 20MHz or 40 MHz
-	UINT32		MCS:7;
-
-	UINT32		rsv:6;
-	UINT32		txop:2;	//tx back off mode 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs only when previous frame exchange is successful.
-	UINT32		MpduDensity:3;
-	UINT32		AMPDU:1;
-
-	UINT32		TS:1;
-	UINT32		CFACK:1;
-	UINT32		MIMOps:1;	// the remote peer is in dynamic MIMO-PS mode
-	UINT32		FRAG:1;		// 1 to inform TKIP engine this is a fragment.
-	// Word 1
-	UINT32		PacketId:4;
-	UINT32		MPDUtotalByteCount:12;
-	UINT32		WirelessCliID:8;
-	UINT32		BAWinSize:6;
-	UINT32		NSEQ:1;
-	UINT32		ACK:1;
-	// Word 2
-	UINT32		IV;
-	// Word 3
-	UINT32		EIV;
-}	TXWI_STRUC, *PTXWI_STRUC;
-#else
 typedef	struct	PACKED _TXWI_STRUC {
 	// Word	0
 	UINT32		FRAG:1;		// 1 to inform TKIP engine this is a fragment.
@@ -2023,45 +1290,10 @@ typedef	struct	PACKED _TXWI_STRUC {
 	//Word3
 	UINT32		EIV;
 }	TXWI_STRUC, *PTXWI_STRUC;
-#endif
+
 //
 // Rx descriptor format, Rx	Ring
 //
-#ifdef RT_BIG_ENDIAN
-typedef	struct	PACKED _RXD_STRUC	{
-	// Word 0
-	UINT32		SDP0;
-	// Word 1
-	UINT32		DDONE:1;
-	UINT32		LS0:1;
-	UINT32		SDL0:14;
-	UINT32		Rsv:2;
-	UINT32		SDL1:14;
-	// Word 2
-	UINT32		SDP1;
-	// Word 3
-	UINT32		Rsv1:13;
-	UINT32		PlcpRssil:1;// To be moved
-	UINT32		PlcpSignal:1;		// To be moved
-	UINT32		Decrypted:1;	// this frame is being decrypted.
-	UINT32		AMPDU:1;
-	UINT32		L2PAD:1;
-	UINT32		RSSI:1;
-	UINT32		HTC:1;
-	UINT32		AMSDU:1;		// rx with 802.3 header, not 802.11 header. obsolete.
-	UINT32		CipherErr:2;        // 0: decryption okay, 1:ICV error, 2:MIC error, 3:KEY not valid
-	UINT32		Crc:1;              // 1: CRC error
-	UINT32		MyBss:1;  	// 1: this frame belongs to the same BSSID
-	UINT32		Bcast:1;            // 1: this is a broadcast frame
-	UINT32		Mcast:1;            // 1: this is a multicast frame
-	UINT32		U2M:1;              // 1: this RX frame is unicast to me
-	UINT32		FRAG:1;
-	UINT32		NULLDATA:1;
-	UINT32		DATA:1;
-	UINT32		BA:1;
-
-}	RXD_STRUC, *PRXD_STRUC, RT28XX_RXD_STRUC, *PRT28XX_RXD_STRUC;
-#else
 typedef	struct	PACKED _RXD_STRUC	{
 	// Word	0
 	UINT32		SDP0;
@@ -2094,39 +1326,10 @@ typedef	struct	PACKED _RXD_STRUC	{
 	UINT32		PlcpRssil:1;// To be moved
 	UINT32		Rsv1:13;
 }	RXD_STRUC, *PRXD_STRUC, RT28XX_RXD_STRUC, *PRT28XX_RXD_STRUC;
-#endif
+
 //
 // RXWI wireless information format, in PBF. invisible in driver.
 //
-#ifdef RT_BIG_ENDIAN
-typedef	struct	PACKED _RXWI_STRUC {
-	// Word 0
-	UINT32		TID:4;
-	UINT32		MPDUtotalByteCount:12;
-	UINT32		UDF:3;
-	UINT32		BSSID:3;
-	UINT32		KeyIndex:2;
-	UINT32		WirelessCliID:8;
-	// Word 1
-	UINT32		PHYMODE:2;              // 1: this RX frame is unicast to me
-	UINT32		rsv:3;
-	UINT32		STBC:2;
-	UINT32		ShortGI:1;
-	UINT32		BW:1;
-	UINT32		MCS:7;
-	UINT32		SEQUENCE:12;
-	UINT32		FRAG:4;
-	// Word 2
-	UINT32		rsv1:8;
-	UINT32		RSSI2:8;
-	UINT32		RSSI1:8;
-	UINT32		RSSI0:8;
-	// Word 3
-	UINT32		rsv2:16;
-	UINT32		SNR1:8;
-	UINT32		SNR0:8;
-}	RXWI_STRUC, *PRXWI_STRUC;
-#else
 typedef	struct	PACKED _RXWI_STRUC {
 	// Word	0
 	UINT32		WirelessCliID:8;
@@ -2154,8 +1357,6 @@ typedef	struct	PACKED _RXWI_STRUC {
 	UINT32		SNR1:8;
 	UINT32		rsv2:16;
 }	RXWI_STRUC, *PRXWI_STRUC;
-#endif
-
 
 // =================================================================================
 // HOST-MCU communication data structure
@@ -2164,17 +1365,6 @@ typedef	struct	PACKED _RXWI_STRUC {
 //
 // H2M_MAILBOX_CSR: Host-to-MCU Mailbox
 //
-#ifdef RT_BIG_ENDIAN
-typedef union  _H2M_MAILBOX_STRUC {
-    struct {
-        UINT32       Owner:8;
-        UINT32       CmdToken:8;    // 0xff tells MCU not to report CmdDoneInt after excuting the command
-        UINT32       HighByte:8;
-        UINT32       LowByte:8;
-    }   field;
-    UINT32           word;
-} H2M_MAILBOX_STRUC, *PH2M_MAILBOX_STRUC;
-#else
 typedef union  _H2M_MAILBOX_STRUC {
     struct {
         UINT32       LowByte:8;
@@ -2184,22 +1374,10 @@ typedef union  _H2M_MAILBOX_STRUC {
     }   field;
     UINT32           word;
 } H2M_MAILBOX_STRUC, *PH2M_MAILBOX_STRUC;
-#endif
 
 //
 // M2H_CMD_DONE_CSR: MCU-to-Host command complete indication
 //
-#ifdef RT_BIG_ENDIAN
-typedef union _M2H_CMD_DONE_STRUC {
-    struct  {
-        UINT32       CmdToken3;
-        UINT32       CmdToken2;
-        UINT32       CmdToken1;
-        UINT32       CmdToken0;
-    } field;
-    UINT32           word;
-} M2H_CMD_DONE_STRUC, *PM2H_CMD_DONE_STRUC;
-#else
 typedef union _M2H_CMD_DONE_STRUC {
     struct  {
         UINT32       CmdToken0;
@@ -2209,22 +1387,10 @@ typedef union _M2H_CMD_DONE_STRUC {
     } field;
     UINT32           word;
 } M2H_CMD_DONE_STRUC, *PM2H_CMD_DONE_STRUC;
-#endif
-
-
 
 //
 // MCU_LEDCS: MCU LED Control Setting.
 //
-#ifdef RT_BIG_ENDIAN
-typedef union  _MCU_LEDCS_STRUC {
-	struct	{
-		UCHAR		Polarity:1;
-		UCHAR		LedMode:7;
-	} field;
-	UCHAR				word;
-} MCU_LEDCS_STRUC, *PMCU_LEDCS_STRUC;
-#else
 typedef union  _MCU_LEDCS_STRUC {
 	struct	{
 		UCHAR		LedMode:7;
@@ -2232,7 +1398,7 @@ typedef union  _MCU_LEDCS_STRUC {
 	} field;
 	UCHAR			word;
 } MCU_LEDCS_STRUC, *PMCU_LEDCS_STRUC;
-#endif
+
 // =================================================================================
 // Register format
 // =================================================================================
@@ -2240,18 +1406,6 @@ typedef union  _MCU_LEDCS_STRUC {
 
 
 //NAV_TIME_CFG :NAV
-#ifdef RT_BIG_ENDIAN
-typedef	union	_NAV_TIME_CFG_STRUC	{
-	struct	{
-		USHORT		rsv:6;
-		USHORT		ZeroSifs:1;               // Applied zero SIFS timer after OFDM RX 0: disable
-		USHORT		Eifs:9;               // in unit of 1-us
-		UCHAR       SlotTime;    // in unit of 1-us
-		UCHAR		Sifs;               // in unit of 1-us
-	}	field;
-	UINT32			word;
-}	NAV_TIME_CFG_STRUC, *PNAV_TIME_CFG_STRUC;
-#else
 typedef	union	_NAV_TIME_CFG_STRUC	{
 	struct	{
 		UCHAR		Sifs;               // in unit of 1-us
@@ -2262,44 +1416,10 @@ typedef	union	_NAV_TIME_CFG_STRUC	{
 	}	field;
 	UINT32			word;
 }	NAV_TIME_CFG_STRUC, *PNAV_TIME_CFG_STRUC;
-#endif
-
-
-
-
 
 //
 // RX_FILTR_CFG:  /RX configuration register
 //
-#ifdef RT_BIG_ENDIAN
-typedef	union	RX_FILTR_CFG_STRUC	{
-	struct	{
-		UINT32		:15;
-		UINT32       DropRsvCntlType:1;
-
-        	UINT32       	DropBAR:1;       //
-		UINT32		DropBA:1;		//
-		UINT32		DropPsPoll:1;		// Drop Ps-Poll
-		UINT32		DropRts:1;		// Drop Ps-Poll
-
-		UINT32		DropCts:1;		// Drop Ps-Poll
-		UINT32		DropAck:1;		// Drop Ps-Poll
-		UINT32		DropCFEnd:1;		// Drop Ps-Poll
-		UINT32		DropCFEndAck:1;		// Drop Ps-Poll
-
-		UINT32		DropDuplicate:1;		// Drop duplicate frame
-		UINT32		DropBcast:1;		// Drop broadcast frames
-		UINT32		DropMcast:1;		// Drop multicast frames
-		UINT32		DropVerErr:1;	    // Drop version error frame
-
-		UINT32		DropNotMyBSSID:1;			// Drop fram ToDs bit is true
-		UINT32		DropNotToMe:1;		// Drop not to me unicast frame
-		UINT32		DropPhyErr:1;		// Drop physical error
-		UINT32		DropCRCErr:1;		// Drop CRC error
-	}	field;
-	UINT32			word;
-}	RX_FILTR_CFG_STRUC, *PRX_FILTR_CFG_STRUC;
-#else
 typedef	union	_RX_FILTR_CFG_STRUC	{
 	struct	{
 		UINT32		DropCRCErr:1;		// Drop CRC error
@@ -2327,26 +1447,10 @@ typedef	union	_RX_FILTR_CFG_STRUC	{
 	}	field;
 	UINT32			word;
 }	RX_FILTR_CFG_STRUC, *PRX_FILTR_CFG_STRUC;
-#endif
-
-
-
 
 //
 // PHY_CSR4: RF serial control register
 //
-#ifdef RT_BIG_ENDIAN
-typedef	union	_PHY_CSR4_STRUC	{
-	struct	{
-		UINT32		Busy:1;				// 1: ASIC is busy execute RF programming.
-		UINT32		PLL_LD:1;			// RF PLL_LD status
-		UINT32		IFSelect:1;			// 1: select IF	to program,	0: select RF to	program
-		UINT32		NumberOfBits:5;		// Number of bits used in RFRegValue (I:20,	RFMD:22)
-		UINT32		RFRegValue:24;		// Register	value (include register	id)	serial out to RF/IF	chip.
-	}	field;
-	UINT32			word;
-}	PHY_CSR4_STRUC, *PPHY_CSR4_STRUC;
-#else
 typedef	union	_PHY_CSR4_STRUC	{
 	struct	{
 		UINT32		RFRegValue:24;		// Register	value (include register	id)	serial out to RF/IF	chip.
@@ -2357,35 +1461,10 @@ typedef	union	_PHY_CSR4_STRUC	{
 	}	field;
 	UINT32			word;
 }	PHY_CSR4_STRUC, *PPHY_CSR4_STRUC;
-#endif
-
 
 //
 // SEC_CSR5: shared key table security mode register
 //
-#ifdef RT_BIG_ENDIAN
-typedef	union	_SEC_CSR5_STRUC	{
-	struct	{
-        UINT32       :1;
-        UINT32       Bss3Key3CipherAlg:3;
-        UINT32       :1;
-        UINT32       Bss3Key2CipherAlg:3;
-        UINT32       :1;
-        UINT32       Bss3Key1CipherAlg:3;
-        UINT32       :1;
-        UINT32       Bss3Key0CipherAlg:3;
-        UINT32       :1;
-        UINT32       Bss2Key3CipherAlg:3;
-        UINT32       :1;
-        UINT32       Bss2Key2CipherAlg:3;
-        UINT32       :1;
-        UINT32       Bss2Key1CipherAlg:3;
-        UINT32       :1;
-        UINT32       Bss2Key0CipherAlg:3;
-	}	field;
-	UINT32			word;
-}	SEC_CSR5_STRUC, *PSEC_CSR5_STRUC;
-#else
 typedef	union	_SEC_CSR5_STRUC	{
 	struct	{
         UINT32       Bss2Key0CipherAlg:3;
@@ -2407,21 +1486,10 @@ typedef	union	_SEC_CSR5_STRUC	{
 	}	field;
 	UINT32			word;
 }	SEC_CSR5_STRUC, *PSEC_CSR5_STRUC;
-#endif
-
 
 //
 // HOST_CMD_CSR: For HOST to interrupt embedded processor
 //
-#ifdef RT_BIG_ENDIAN
-typedef	union	_HOST_CMD_CSR_STRUC	{
-	struct	{
-	    UINT32   Rsv:24;
-	    UINT32   HostCommand:8;
-	}	field;
-	UINT32			word;
-}	HOST_CMD_CSR_STRUC, *PHOST_CMD_CSR_STRUC;
-#else
 typedef	union	_HOST_CMD_CSR_STRUC	{
 	struct	{
 	    UINT32   HostCommand:8;
@@ -2429,8 +1497,6 @@ typedef	union	_HOST_CMD_CSR_STRUC	{
 	}	field;
 	UINT32			word;
 }	HOST_CMD_CSR_STRUC, *PHOST_CMD_CSR_STRUC;
-#endif
-
 
 //
 // AIFSN_CSR: AIFSN for each EDCA AC
@@ -2441,21 +1507,6 @@ typedef	union	_HOST_CMD_CSR_STRUC	{
 //
 // E2PROM_CSR: EEPROM control register
 //
-#ifdef RT_BIG_ENDIAN
-typedef	union	_E2PROM_CSR_STRUC	{
-	struct	{
-		UINT32		Rsvd:25;
-		UINT32       LoadStatus:1;   // 1:loading, 0:done
-		UINT32		Type:1;			// 1: 93C46, 0:93C66
-		UINT32		EepromDO:1;
-		UINT32		EepromDI:1;
-		UINT32		EepromCS:1;
-		UINT32		EepromSK:1;
-		UINT32		Reload:1;		// Reload EEPROM content, write one to reload, self-cleared.
-	}	field;
-	UINT32			word;
-}	E2PROM_CSR_STRUC, *PE2PROM_CSR_STRUC;
-#else
 typedef	union	_E2PROM_CSR_STRUC	{
 	struct	{
 		UINT32		Reload:1;		// Reload EEPROM content, write one to reload, self-cleared.
@@ -2469,8 +1520,6 @@ typedef	union	_E2PROM_CSR_STRUC	{
 	}	field;
 	UINT32			word;
 }	E2PROM_CSR_STRUC, *PE2PROM_CSR_STRUC;
-#endif
-
 
 // -------------------------------------------------------------------
 //  E2PROM data layout
@@ -2479,17 +1528,6 @@ typedef	union	_E2PROM_CSR_STRUC	{
 //
 // EEPROM antenna select format
 //
-#ifdef RT_BIG_ENDIAN
-typedef	union	_EEPROM_ANTENNA_STRUC	{
-	struct	{
-		USHORT      Rsv:4;
-		USHORT      RfIcType:4;             // see E2PROM document
-		USHORT		TxPath:4;	// 1: 1T, 2: 2T
-		USHORT		RxPath:4;	// 1: 1R, 2: 2R, 3: 3R
-	}	field;
-	USHORT			word;
-}	EEPROM_ANTENNA_STRUC, *PEEPROM_ANTENNA_STRUC;
-#else
 typedef	union	_EEPROM_ANTENNA_STRUC	{
 	struct	{
 		USHORT		RxPath:4;	// 1: 1R, 2: 2R, 3: 3R
@@ -2499,26 +1537,7 @@ typedef	union	_EEPROM_ANTENNA_STRUC	{
 	}	field;
 	USHORT			word;
 }	EEPROM_ANTENNA_STRUC, *PEEPROM_ANTENNA_STRUC;
-#endif
 
-#ifdef RT_BIG_ENDIAN
-typedef	union _EEPROM_NIC_CINFIG2_STRUC	{
-	struct	{
-        USHORT		Rsv2:6;					// must be 0
-		USHORT		BW40MAvailForA:1;			// 0:enable, 1:disable
-		USHORT		BW40MAvailForG:1;			// 0:enable, 1:disable
-		USHORT		EnableWPSPBC:1;                 // WPS PBC Control bit
-		USHORT		BW40MSidebandForA:1;
-		USHORT		BW40MSidebandForG:1;
-		USHORT		CardbusAcceleration:1;	// !!! NOTE: 0 - enable, 1 - disable
-		USHORT		ExternalLNAForA:1;			// external LNA enable for 5G
-		USHORT		ExternalLNAForG:1;			// external LNA enable for 2.4G
-		USHORT		DynamicTxAgcControl:1;			//
-		USHORT		HardwareRadioControl:1;	// Whether RF is controlled by driver or HW. 1:enable hw control, 0:disable
-	}	field;
-	USHORT			word;
-}	EEPROM_NIC_CONFIG2_STRUC, *PEEPROM_NIC_CONFIG2_STRUC;
-#else
 typedef	union _EEPROM_NIC_CINFIG2_STRUC	{
 	struct {
 		USHORT		HardwareRadioControl:1;	// 1:enable, 0:disable
@@ -2535,20 +1554,10 @@ typedef	union _EEPROM_NIC_CINFIG2_STRUC	{
 	}	field;
 	USHORT			word;
 }	EEPROM_NIC_CONFIG2_STRUC, *PEEPROM_NIC_CONFIG2_STRUC;
-#endif
 
 //
 // TX_PWR Value valid range 0xFA(-6) ~ 0x24(36)
 //
-#ifdef RT_BIG_ENDIAN
-typedef	union	_EEPROM_TX_PWR_STRUC	{
-	struct	{
-		CHAR	Byte1;				// High Byte
-		CHAR	Byte0;				// Low Byte
-	}	field;
-	USHORT	word;
-}	EEPROM_TX_PWR_STRUC, *PEEPROM_TX_PWR_STRUC;
-#else
 typedef	union	_EEPROM_TX_PWR_STRUC	{
 	struct	{
 		CHAR	Byte0;				// Low Byte
@@ -2556,17 +1565,7 @@ typedef	union	_EEPROM_TX_PWR_STRUC	{
 	}	field;
 	USHORT	word;
 }	EEPROM_TX_PWR_STRUC, *PEEPROM_TX_PWR_STRUC;
-#endif
 
-#ifdef RT_BIG_ENDIAN
-typedef	union	_EEPROM_VERSION_STRUC	{
-	struct	{
-		UCHAR	Version;			// High Byte
-		UCHAR	FaeReleaseNumber;	// Low Byte
-	}	field;
-	USHORT	word;
-}	EEPROM_VERSION_STRUC, *PEEPROM_VERSION_STRUC;
-#else
 typedef	union	_EEPROM_VERSION_STRUC	{
 	struct	{
 		UCHAR	FaeReleaseNumber;	// Low Byte
@@ -2574,25 +1573,7 @@ typedef	union	_EEPROM_VERSION_STRUC	{
 	}	field;
 	USHORT	word;
 }	EEPROM_VERSION_STRUC, *PEEPROM_VERSION_STRUC;
-#endif
 
-#ifdef RT_BIG_ENDIAN
-typedef	union	_EEPROM_LED_STRUC	{
-	struct	{
-		USHORT	Rsvd:3;				// Reserved
-		USHORT	LedMode:5;			// Led mode.
-		USHORT	PolarityGPIO_4:1;	// Polarity GPIO#4 setting.
-		USHORT	PolarityGPIO_3:1;	// Polarity GPIO#3 setting.
-		USHORT	PolarityGPIO_2:1;	// Polarity GPIO#2 setting.
-		USHORT	PolarityGPIO_1:1;	// Polarity GPIO#1 setting.
-		USHORT	PolarityGPIO_0:1;	// Polarity GPIO#0 setting.
-		USHORT	PolarityACT:1;		// Polarity ACT setting.
-		USHORT	PolarityRDY_A:1;		// Polarity RDY_A setting.
-		USHORT	PolarityRDY_G:1;		// Polarity RDY_G setting.
-	}	field;
-	USHORT	word;
-}	EEPROM_LED_STRUC, *PEEPROM_LED_STRUC;
-#else
 typedef	union	_EEPROM_LED_STRUC	{
 	struct	{
 		USHORT	PolarityRDY_G:1;		// Polarity RDY_G setting.
@@ -2608,18 +1589,7 @@ typedef	union	_EEPROM_LED_STRUC	{
 	}	field;
 	USHORT	word;
 }	EEPROM_LED_STRUC, *PEEPROM_LED_STRUC;
-#endif
 
-#ifdef RT_BIG_ENDIAN
-typedef	union	_EEPROM_TXPOWER_DELTA_STRUC	{
-	struct	{
-		UCHAR	TxPowerEnable:1;// Enable
-		UCHAR	Type:1;			// 1: plus the delta value, 0: minus the delta value
-		UCHAR	DeltaValue:6;	// Tx Power dalta value (MAX=4)
-	}	field;
-	UCHAR	value;
-}	EEPROM_TXPOWER_DELTA_STRUC, *PEEPROM_TXPOWER_DELTA_STRUC;
-#else
 typedef	union	_EEPROM_TXPOWER_DELTA_STRUC	{
 	struct	{
 		UCHAR	DeltaValue:6;	// Tx Power dalta value (MAX=4)
@@ -2628,22 +1598,10 @@ typedef	union	_EEPROM_TXPOWER_DELTA_STRUC	{
 	}	field;
 	UCHAR	value;
 }	EEPROM_TXPOWER_DELTA_STRUC, *PEEPROM_TXPOWER_DELTA_STRUC;
-#endif
 
 //
 // QOS_CSR0: TXOP holder address0 register
 //
-#ifdef RT_BIG_ENDIAN
-typedef	union	_QOS_CSR0_STRUC	{
-	struct	{
-		UCHAR		Byte3;		// MAC address byte 3
-		UCHAR		Byte2;		// MAC address byte 2
-		UCHAR		Byte1;		// MAC address byte 1
-		UCHAR		Byte0;		// MAC address byte 0
-	}	field;
-	UINT32			word;
-}	QOS_CSR0_STRUC, *PQOS_CSR0_STRUC;
-#else
 typedef	union	_QOS_CSR0_STRUC	{
 	struct	{
 		UCHAR		Byte0;		// MAC address byte 0
@@ -2653,22 +1611,10 @@ typedef	union	_QOS_CSR0_STRUC	{
 	}	field;
 	UINT32			word;
 }	QOS_CSR0_STRUC, *PQOS_CSR0_STRUC;
-#endif
 
 //
 // QOS_CSR1: TXOP holder address1 register
 //
-#ifdef RT_BIG_ENDIAN
-typedef	union	_QOS_CSR1_STRUC	{
-	struct	{
-		UCHAR		Rsvd1;
-		UCHAR		Rsvd0;
-		UCHAR		Byte5;		// MAC address byte 5
-		UCHAR		Byte4;		// MAC address byte 4
-	}	field;
-	UINT32			word;
-}	QOS_CSR1_STRUC, *PQOS_CSR1_STRUC;
-#else
 typedef	union	_QOS_CSR1_STRUC	{
 	struct	{
 		UCHAR		Byte4;		// MAC address byte 4
@@ -2678,22 +1624,8 @@ typedef	union	_QOS_CSR1_STRUC	{
 	}	field;
 	UINT32			word;
 }	QOS_CSR1_STRUC, *PQOS_CSR1_STRUC;
-#endif
 
 #define	RF_CSR_CFG	0x500
-#ifdef RT_BIG_ENDIAN
-typedef	union	_RF_CSR_CFG_STRUC	{
-	struct	{
-		UINT	Rsvd1:14;				// Reserved
-		UINT	RF_CSR_KICK:1;			// kick RF register read/write
-		UINT	RF_CSR_WR:1;			// 0: read  1: write
-		UINT	Rsvd2:3;				// Reserved
-		UINT	TESTCSR_RFACC_REGNUM:5;	// RF register ID
-		UINT	RF_CSR_DATA:8;			// DATA
-	}	field;
-	UINT	word;
-}	RF_CSR_CFG_STRUC, *PRF_CSR_CFG_STRUC;
-#else
 typedef	union	_RF_CSR_CFG_STRUC	{
 	struct	{
 		UINT	RF_CSR_DATA:8;			// DATA
@@ -2705,6 +1637,5 @@ typedef	union	_RF_CSR_CFG_STRUC	{
 	}	field;
 	UINT	word;
 }	RF_CSR_CFG_STRUC, *PRF_CSR_CFG_STRUC;
-#endif
 
 #endif	// __RT28XX_H__