diff options
| author |   Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> | 2009-04-26 16:05:44 +0200 |
|---|---|---|
| committer |   Greg Kroah-Hartman <gregkh@suse.de> | 2009-06-19 11:00:46 -0700 |
| commit | 2bc1c810c3dd295d8f1f65b4d68077b58f435c4b (patch) | |
| tree | f4dee1001aa788d1c3c46f7c926b919584ca1652 /drivers/staging/rt3070 | |
| parent | Staging: rt2870: remove dead RT_BIG_ENDIAN code (diff) | |
| download | linux-dev-2bc1c810c3dd295d8f1f65b4d68077b58f435c4b.tar.xz linux-dev-2bc1c810c3dd295d8f1f65b4d68077b58f435c4b.zip | |
Staging: rt3070: remove dead RT_BIG_ENDIAN code
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/staging/rt3070')
21 files changed, 44 insertions, 1982 deletions
diff --git a/drivers/staging/rt3070/2870_main_dev.c b/drivers/staging/rt3070/2870_main_dev.c index 7150373ff521..1783811b92c0 100644 --- a/drivers/staging/rt3070/2870_main_dev.c +++ b/drivers/staging/rt3070/2870_main_dev.c @@ -1264,9 +1264,7 @@ VOID RT28xx_UpdateBeaconToAsic( else { ptr = (PUCHAR)&pAd->BeaconTxWI; -#ifdef RT_BIG_ENDIAN - RTMPWIEndianChange(ptr, TYPE_TXWI); -#endif + if (NdisEqualMemory(pBeaconSync->BeaconTxWI[bcn_idx], &pAd->BeaconTxWI, TXWI_SIZE) == FALSE) { // If BeaconTxWI changed, we need to rewrite the TxWI for the Beacon frames. pBeaconSync->BeaconBitMap &= (~(BEACON_BITMAP_MASK & (1 << bcn_idx))); diff --git a/drivers/staging/rt3070/action.h b/drivers/staging/rt3070/action.h index ce3877dce81b..cfc2a5f8d1aa 100644 --- a/drivers/staging/rt3070/action.h +++ b/drivers/staging/rt3070/action.h @@ -41,17 +41,10 @@ typedef struct PACKED __HT_INFO_OCTET { -#ifdef RT_BIG_ENDIAN - UCHAR Reserved:5; - UCHAR STA_Channel_Width:1; - UCHAR Forty_MHz_Intolerant:1; - UCHAR Request:1; -#else UCHAR Request:1; UCHAR Forty_MHz_Intolerant:1; UCHAR STA_Channel_Width:1; UCHAR Reserved:5; -#endif } HT_INFORMATION_OCTET; diff --git a/drivers/staging/rt3070/common/2870_rtmp_init.c b/drivers/staging/rt3070/common/2870_rtmp_init.c index 9795638f33cf..5433fcc45371 100644 --- a/drivers/staging/rt3070/common/2870_rtmp_init.c +++ b/drivers/staging/rt3070/common/2870_rtmp_init.c @@ -1063,18 +1063,13 @@ PNDIS_PACKET GetPacketFromRxRing( // skip USB frame length field pData += RT2870_RXDMALEN_FIELD_SIZE; pRxWI = (PRXWI_STRUC)pData; -#ifdef RT_BIG_ENDIAN - RTMPWIEndianChange(pData, TYPE_RXWI); -#endif // RT_BIG_ENDIAN // + if (pRxWI->MPDUtotalByteCount > ThisFrameLen) { DBGPRINT(RT_DEBUG_ERROR, ("%s():pRxWIMPDUtotalByteCount(%d) large than RxDMALen(%ld)\n", __func__, pRxWI->MPDUtotalByteCount, ThisFrameLen)); goto label_null; } -#ifdef RT_BIG_ENDIAN - RTMPWIEndianChange(pData, TYPE_RXWI); -#endif // RT_BIG_ENDIAN // // allocate a rx packet pSkb = dev_alloc_skb(ThisFrameLen); @@ -1091,9 +1086,6 @@ PNDIS_PACKET GetPacketFromRxRing( // copy RxD *pSaveRxD = *(PRXINFO_STRUC)(pData + ThisFrameLen); -#ifdef RT_BIG_ENDIAN - RTMPDescriptorEndianChange((PUCHAR)pSaveRxD, TYPE_RXINFO); -#endif // RT_BIG_ENDIAN // // update next packet read position. pAd->ReadPosition += (ThisFrameLen + RT2870_RXDMALEN_FIELD_SIZE + RXINFO_SIZE); // 8 for (RT2870_RXDMALEN_FIELD_SIZE + sizeof(RXINFO_STRUC)) diff --git a/drivers/staging/rt3070/common/cmm_data.c b/drivers/staging/rt3070/common/cmm_data.c index 67d945bdde61..79828ec2fa02 100644 --- a/drivers/staging/rt3070/common/cmm_data.c +++ b/drivers/staging/rt3070/common/cmm_data.c @@ -495,10 +495,6 @@ NDIS_STATUS MlmeHardTransmitMgmtRing( return (NDIS_STATUS_FAILURE); } -#ifdef RT_BIG_ENDIAN - RTMPFrameEndianChange(pAd, (PUCHAR)pHeader_802_11, DIR_WRITE, FALSE); -#endif - // // fill scatter-and-gather buffer list into TXD. Internally created NDIS PACKET // should always has only one ohysical buffer, and the whole frame size equals @@ -526,10 +522,6 @@ NDIS_STATUS MlmeHardTransmitMgmtRing( IFS_BACKOFF, FALSE, &pMacEntry->MaxHTPhyMode); } -#ifdef RT_BIG_ENDIAN - RTMPWIEndianChange((PUCHAR)pFirstTxWI, TYPE_TXWI); -#endif - // Now do hardware-depened kick out. HAL_KickOutMgmtTx(pAd, QueIdx, pPacket, pSrcBufVA, SrcBufLen); diff --git a/drivers/staging/rt3070/common/cmm_data_2870.c b/drivers/staging/rt3070/common/cmm_data_2870.c index b1066aa2bb23..6866caa37ac7 100644 --- a/drivers/staging/rt3070/common/cmm_data_2870.c +++ b/drivers/staging/rt3070/common/cmm_data_2870.c @@ -189,9 +189,6 @@ USHORT RtmpUSB_WriteFragTxResource( } NdisMoveMemory(pWirelessPacket, pTxBlk->HeaderBuf, TXINFO_SIZE + TXWI_SIZE + hwHdrLen); -#ifdef RT_BIG_ENDIAN - RTMPFrameEndianChange(pAd, (PUCHAR)(pWirelessPacket + TXINFO_SIZE + TXWI_SIZE), DIR_WRITE, FALSE); -#endif // RT_BIG_ENDIAN // pWirelessPacket += (TXINFO_SIZE + TXWI_SIZE + hwHdrLen); pHTTXContext->CurWriteRealPos += (TXINFO_SIZE + TXWI_SIZE + hwHdrLen); @@ -307,9 +304,6 @@ USHORT RtmpUSB_WriteSingleTxResource( bTxQLastRound = TRUE; } NdisMoveMemory(pWirelessPacket, pTxBlk->HeaderBuf, TXINFO_SIZE + TXWI_SIZE + hwHdrLen); -#ifdef RT_BIG_ENDIAN - RTMPFrameEndianChange(pAd, (PUCHAR)(pWirelessPacket + TXINFO_SIZE + TXWI_SIZE), DIR_WRITE, FALSE); -#endif // RT_BIG_ENDIAN // pWirelessPacket += (TXINFO_SIZE + TXWI_SIZE + hwHdrLen); // We unlock it here to prevent the first 8 bytes maybe over-writed issue. @@ -421,9 +415,6 @@ USHORT RtmpUSB_WriteMultiTxResource( // Copy it. NdisMoveMemory(pWirelessPacket, pTxBlk->HeaderBuf, pTxBlk->Priv); -#ifdef RT_BIG_ENDIAN - RTMPFrameEndianChange(pAd, (PUCHAR)(pWirelessPacket+ TXINFO_SIZE + TXWI_SIZE), DIR_WRITE, FALSE); -#endif // RT_BIG_ENDIAN // pHTTXContext->CurWriteRealPos += pTxBlk->Priv; pWirelessPacket += pTxBlk->Priv; } @@ -691,14 +682,7 @@ VOID RtmpUSBNullFrameKickOut( pTxWI = (PTXWI_STRUC)&pWirelessPkt[TXINFO_SIZE]; RTMPWriteTxWI(pAd, pTxWI, FALSE, FALSE, FALSE, FALSE, TRUE, FALSE, 0, BSSID_WCID, (sizeof(HEADER_802_11)), 0, 0, (UCHAR)pAd->CommonCfg.MlmeTransmit.field.MCS, IFS_HTTXOP, FALSE, &pAd->CommonCfg.MlmeTransmit); -#ifdef RT_BIG_ENDIAN - RTMPWIEndianChange((PUCHAR)pTxWI, TYPE_TXWI); -#endif // RT_BIG_ENDIAN // - RTMPMoveMemory(&pWirelessPkt[TXWI_SIZE+TXINFO_SIZE], &pAd->NullFrame, sizeof(HEADER_802_11)); -#ifdef RT_BIG_ENDIAN - RTMPFrameEndianChange(pAd, (PUCHAR)&pWirelessPkt[TXINFO_SIZE + TXWI_SIZE], DIR_WRITE, FALSE); -#endif // RT_BIG_ENDIAN // pAd->NullContext.BulkOutSize = TXINFO_SIZE + TXWI_SIZE + sizeof(pAd->NullFrame) + 4; // Fill out frame length information for global Bulk out arbitor diff --git a/drivers/staging/rt3070/common/cmm_sync.c b/drivers/staging/rt3070/common/cmm_sync.c index 5dfbb7fc502d..93e03291cbad 100644 --- a/drivers/staging/rt3070/common/cmm_sync.c +++ b/drivers/staging/rt3070/common/cmm_sync.c @@ -591,52 +591,27 @@ VOID ScanNextChannel( ULONG Tmp; UCHAR HtLen; UCHAR BROADCOM[4] = {0x0, 0x90, 0x4c, 0x33}; -#ifdef RT_BIG_ENDIAN - HT_CAPABILITY_IE HtCapabilityTmp; -#endif + if (pAd->bBroadComHT == TRUE) { HtLen = pAd->MlmeAux.HtCapabilityLen + 4; -#ifdef RT_BIG_ENDIAN - NdisMoveMemory(&HtCapabilityTmp, &pAd->MlmeAux.HtCapability, SIZE_HT_CAP_IE); - *(USHORT *)(&HtCapabilityTmp.HtCapInfo) = SWAP16(*(USHORT *)(&HtCapabilityTmp.HtCapInfo)); - *(USHORT *)(&HtCapabilityTmp.ExtHtCapInfo) = SWAP16(*(USHORT *)(&HtCapabilityTmp.ExtHtCapInfo)); MakeOutgoingFrame(pOutBuffer + FrameLen, &Tmp, 1, &WpaIe, 1, &HtLen, 4, &BROADCOM[0], - pAd->MlmeAux.HtCapabilityLen, &HtCapabilityTmp, - END_OF_ARGS); -#else - MakeOutgoingFrame(pOutBuffer + FrameLen, &Tmp, - 1, &WpaIe, - 1, &HtLen, - 4, &BROADCOM[0], pAd->MlmeAux.HtCapabilityLen, &pAd->MlmeAux.HtCapability, END_OF_ARGS); -#endif // RT_BIG_ENDIAN // } else { HtLen = pAd->MlmeAux.HtCapabilityLen; -#ifdef RT_BIG_ENDIAN - NdisMoveMemory(&HtCapabilityTmp, &pAd->CommonCfg.HtCapability, SIZE_HT_CAP_IE); - *(USHORT *)(&HtCapabilityTmp.HtCapInfo) = SWAP16(*(USHORT *)(&HtCapabilityTmp.HtCapInfo)); - *(USHORT *)(&HtCapabilityTmp.ExtHtCapInfo) = SWAP16(*(USHORT *)(&HtCapabilityTmp.ExtHtCapInfo)); MakeOutgoingFrame(pOutBuffer + FrameLen, &Tmp, 1, &HtCapIe, 1, &HtLen, - HtLen, &HtCapabilityTmp, - END_OF_ARGS); -#else - MakeOutgoingFrame(pOutBuffer + FrameLen, &Tmp, - 1, &HtCapIe, - 1, &HtLen, HtLen, &pAd->CommonCfg.HtCapability, END_OF_ARGS); -#endif // RT_BIG_ENDIAN // } FrameLen += Tmp; } diff --git a/drivers/staging/rt3070/common/eeprom.c b/drivers/staging/rt3070/common/eeprom.c index 63e1dc14d151..ebd52f50a07b 100644 --- a/drivers/staging/rt3070/common/eeprom.c +++ b/drivers/staging/rt3070/common/eeprom.c @@ -361,11 +361,7 @@ UCHAR eFuseReadRegisters( //Return 2-bytes //The return byte statrs from S. Therefore, the little-endian will return BA, the Big-endian will return DC. //For returning the bottom 2 bytes, the Big-endian should shift right 2-bytes. -#ifdef RT_BIG_ENDIAN - data = data << (8*((Offset & 0x3)^0x2)); -#else data = data >> (8*(Offset & 0x3)); -#endif NdisMoveMemory(pData, &data, Length); } @@ -438,11 +434,7 @@ VOID eFusePhysicalReadRegisters( RTMP_IO_READ32(pAd, efuseDataOffset, &data); -#ifdef RT_BIG_ENDIAN - data = data << (8*((Offset & 0x3)^0x2)); -#else data = data >> (8*(Offset & 0x3)); -#endif NdisMoveMemory(pData, &data, Length); diff --git a/drivers/staging/rt3070/common/md5.c b/drivers/staging/rt3070/common/md5.c index 774776b4b8c3..ad883ca2ffc8 100644 --- a/drivers/staging/rt3070/common/md5.c +++ b/drivers/staging/rt3070/common/md5.c @@ -131,19 +131,7 @@ void hmac_md5(u8 *key, size_t key_len, u8 *data, size_t data_len, u8 *mac) MD5Final(mac, &context); /* finish up 2nd pass */ } -#ifndef RT_BIG_ENDIAN #define byteReverse(buf, len) /* Nothing */ -#else -void byteReverse(unsigned char *buf, unsigned longs); -void byteReverse(unsigned char *buf, unsigned longs) -{ - do { - *(UINT32 *)buf = SWAP32(*(UINT32 *)buf); - buf += 4; - } while (--longs); -} -#endif - /* ========================== MD5 implementation =========================== */ // four base functions for MD5 diff --git a/drivers/staging/rt3070/common/rtmp_tkip.c b/drivers/staging/rt3070/common/rtmp_tkip.c index bf8986e83679..27e4277152d8 100644 --- a/drivers/staging/rt3070/common/rtmp_tkip.c +++ b/drivers/staging/rt3070/common/rtmp_tkip.c @@ -199,15 +199,9 @@ typedef struct PACKED _IV_CONTROL_ { struct PACKED { -#ifdef RT_BIG_ENDIAN - UCHAR KeyID:2; - UCHAR ExtIV:1; - UCHAR Rsvd:5; -#else UCHAR Rsvd:5; UCHAR ExtIV:1; UCHAR KeyID:2; -#endif } field; UCHAR Byte; } CONTROL; @@ -1117,10 +1111,6 @@ BOOLEAN RTMPSoftDecryptTKIP( UCHAR MIC[8]; UCHAR TrailMIC[8]; -#ifdef RT_BIG_ENDIAN - RTMPFrameEndianChange(pAd, (PUCHAR)pData, DIR_READ, FALSE); -#endif - fc0 = *pData; fc1 = *(pData + 1); @@ -1228,9 +1218,6 @@ BOOLEAN RTMPSoftDecryptTKIP( return (FALSE); } -#ifdef RT_BIG_ENDIAN - RTMPFrameEndianChange(pAd, (PUCHAR)pData, DIR_READ, FALSE); -#endif //DBGPRINT(RT_DEBUG_TRACE, "RTMPSoftDecryptTKIP Decript done!!\n"); return TRUE; } @@ -1271,10 +1258,6 @@ BOOLEAN RTMPSoftDecryptAES( UCHAR MIC[8]; UCHAR TrailMIC[8]; -#ifdef RT_BIG_ENDIAN - RTMPFrameEndianChange(pAd, (PUCHAR)pData, DIR_READ, FALSE); -#endif - fc0 = *pData; fc1 = *(pData + 1); @@ -1443,10 +1426,6 @@ BOOLEAN RTMPSoftDecryptAES( return FALSE; } -#ifdef RT_BIG_ENDIAN - RTMPFrameEndianChange(pAd, (PUCHAR)pData, DIR_READ, FALSE); -#endif - return TRUE; } diff --git a/drivers/staging/rt3070/common/rtusb_bulk.c b/drivers/staging/rt3070/common/rtusb_bulk.c index e9b06e0a8f6a..912b50e99038 100644 --- a/drivers/staging/rt3070/common/rtusb_bulk.c +++ b/drivers/staging/rt3070/common/rtusb_bulk.c @@ -375,31 +375,14 @@ VOID RTUSBBulkOutDataPacket( bTxQLastRound = TRUE; pHTTXContext->ENextBulkOutPosition = 8; - #ifdef RT_BIG_ENDIAN - RTMPDescriptorEndianChange((PUCHAR)pTxInfo, TYPE_TXINFO); - RTMPWIEndianChange((PUCHAR)pTxWI, TYPE_TXWI); - #endif // RT_BIG_ENDIAN // - break; } - -#ifdef RT_BIG_ENDIAN - RTMPDescriptorEndianChange((PUCHAR)pTxInfo, TYPE_TXINFO); - RTMPWIEndianChange((PUCHAR)pTxWI, TYPE_TXWI); -#endif // RT_BIG_ENDIAN // - }while (TRUE); // adjust the pTxInfo->USBDMANextVLD value of last pTxInfo. if (pLastTxInfo) { -#ifdef RT_BIG_ENDIAN - RTMPDescriptorEndianChange((PUCHAR)pLastTxInfo, TYPE_TXINFO); -#endif // RT_BIG_ENDIAN // pLastTxInfo->USBDMANextVLD = 0; -#ifdef RT_BIG_ENDIAN - RTMPDescriptorEndianChange((PUCHAR)pLastTxInfo, TYPE_TXINFO); -#endif // RT_BIG_ENDIAN // } /* @@ -554,10 +537,6 @@ VOID RTUSBBulkOutNullFrame( // Clear Null frame bulk flag RTUSB_CLEAR_BULK_FLAG(pAd, fRTUSB_BULK_OUT_DATA_NULL); -#ifdef RT_BIG_ENDIAN - RTMPDescriptorEndianChange((PUCHAR)pNullContext->TransferBuffer, TYPE_TXINFO); -#endif // RT_BIG_ENDIAN // - // Init Tx context descriptor RTUSBInitTxDesc(pAd, pNullContext, 0, (usb_complete_t)RTUSBBulkOutNullFrameComplete); @@ -652,10 +631,6 @@ VOID RTUSBBulkOutMLMEPacket( // Clear MLME bulk flag RTUSB_CLEAR_BULK_FLAG(pAd, fRTUSB_BULK_OUT_MLME); -#ifdef RT_BIG_ENDIAN - RTMPDescriptorEndianChange((PUCHAR)pMLMEContext->TransferBuffer, TYPE_TXINFO); -#endif // RT_BIG_ENDIAN // - // Init Tx context descriptor RTUSBInitTxDesc(pAd, pMLMEContext, MGMTPIPEIDX, (usb_complete_t)RTUSBBulkOutMLMEPacketComplete); @@ -738,10 +713,6 @@ VOID RTUSBBulkOutPsPoll( // Clear PS-Poll bulk flag RTUSB_CLEAR_BULK_FLAG(pAd, fRTUSB_BULK_OUT_PSPOLL); -#ifdef RT_BIG_ENDIAN - RTMPDescriptorEndianChange((PUCHAR)pPsPollContext->TransferBuffer, TYPE_TXINFO); -#endif // RT_BIG_ENDIAN // - // Init Tx context descriptor RTUSBInitTxDesc(pAd, pPsPollContext, MGMTPIPEIDX, (usb_complete_t)RTUSBBulkOutPsPollComplete); diff --git a/drivers/staging/rt3070/mlme.h b/drivers/staging/rt3070/mlme.h index c530282ad8f0..56c0d41826c3 100644 --- a/drivers/staging/rt3070/mlme.h +++ b/drivers/staging/rt3070/mlme.h @@ -209,22 +209,6 @@ if (((__pEntry)) != NULL) \ // // HT Capability INFO field in HT Cap IE . typedef struct PACKED { -#ifdef RT_BIG_ENDIAN - USHORT LSIGTxopProSup:1; - USHORT Forty_Mhz_Intolerant:1; - USHORT PSMP:1; - USHORT CCKmodein40:1; - USHORT AMsduSize:1; - USHORT DelayedBA:1; //rt2860c not support - USHORT RxSTBC:2; - USHORT TxSTBC:1; - USHORT ShortGIfor40:1; //for40MHz - USHORT ShortGIfor20:1; - USHORT GF:1; //green field - USHORT MimoPs:2;//momi power safe - USHORT ChannelWidth:1; - USHORT AdvCoding:1; -#else USHORT AdvCoding:1; USHORT ChannelWidth:1; USHORT MimoPs:2;//momi power safe @@ -239,53 +223,29 @@ typedef struct PACKED { USHORT PSMP:1; USHORT Forty_Mhz_Intolerant:1; USHORT LSIGTxopProSup:1; -#endif /* !RT_BIG_ENDIAN */ } HT_CAP_INFO, *PHT_CAP_INFO; // HT Capability INFO field in HT Cap IE . typedef struct PACKED { -#ifdef RT_BIG_ENDIAN - UCHAR rsv:3;//momi power safe - UCHAR MpduDensity:3; - UCHAR MaxRAmpduFactor:2; -#else UCHAR MaxRAmpduFactor:2; UCHAR MpduDensity:3; UCHAR rsv:3;//momi power safe -#endif /* !RT_BIG_ENDIAN */ } HT_CAP_PARM, *PHT_CAP_PARM; // HT Capability INFO field in HT Cap IE . typedef struct PACKED { UCHAR MCSSet[10]; UCHAR SupRate[2]; // unit : 1Mbps -#ifdef RT_BIG_ENDIAN - UCHAR rsv:3; - UCHAR MpduDensity:1; - UCHAR TxStream:2; - UCHAR TxRxNotEqual:1; - UCHAR TxMCSSetDefined:1; -#else UCHAR TxMCSSetDefined:1; UCHAR TxRxNotEqual:1; UCHAR TxStream:2; UCHAR MpduDensity:1; UCHAR rsv:3; -#endif // RT_BIG_ENDIAN // UCHAR rsv3[3]; } HT_MCS_SET, *PHT_MCS_SET; // HT Capability INFO field in HT Cap IE . typedef struct PACKED { -#ifdef RT_BIG_ENDIAN - USHORT rsv2:4; - USHORT RDGSupport:1; //reverse Direction Grant support - USHORT PlusHTC:1; //+HTC control field support - USHORT MCSFeedback:2; //0:no MCS feedback, 2:unsolicited MCS feedback, 3:Full MCS feedback, 1:rsv. - USHORT rsv:5;//momi power safe - USHORT TranTime:2; - USHORT Pco:1; -#else USHORT Pco:1; USHORT TranTime:2; USHORT rsv:5;//momi power safe @@ -293,33 +253,10 @@ typedef struct PACKED { USHORT PlusHTC:1; //+HTC control field support USHORT RDGSupport:1; //reverse Direction Grant support USHORT rsv2:4; -#endif /* RT_BIG_ENDIAN */ } EXT_HT_CAP_INFO, *PEXT_HT_CAP_INFO; // HT Beamforming field in HT Cap IE . typedef struct PACKED _HT_BF_CAP{ -#ifdef RT_BIG_ENDIAN - ULONG rsv:3; - ULONG ChanEstimation:2; - ULONG CSIRowBFSup:2; - ULONG ComSteerBFAntSup:2; - ULONG NoComSteerBFAntSup:2; - ULONG CSIBFAntSup:2; - ULONG MinGrouping:2; - ULONG ExpComBF:2; - ULONG ExpNoComBF:2; - ULONG ExpCSIFbk:2; - ULONG ExpComSteerCapable:1; - ULONG ExpNoComSteerCapable:1; - ULONG ExpCSICapable:1; - ULONG Calibration:2; - ULONG ImpTxBFCapable:1; - ULONG TxNDPCapable:1; - ULONG RxNDPCapable:1; - ULONG TxSoundCapable:1; - ULONG RxSoundCapable:1; - ULONG TxBFRecCapable:1; -#else ULONG TxBFRecCapable:1; ULONG RxSoundCapable:1; ULONG TxSoundCapable:1; @@ -340,21 +277,10 @@ typedef struct PACKED _HT_BF_CAP{ ULONG CSIRowBFSup:2; ULONG ChanEstimation:2; ULONG rsv:3; -#endif // RT_BIG_ENDIAN // } HT_BF_CAP, *PHT_BF_CAP; // HT antenna selection field in HT Cap IE . typedef struct PACKED _HT_AS_CAP{ -#ifdef RT_BIG_ENDIAN - UCHAR rsv:1; - UCHAR TxSoundPPDU:1; - UCHAR RxASel:1; - UCHAR AntIndFbk:1; - UCHAR ExpCSIFbk:1; - UCHAR AntIndFbkTxASEL:1; - UCHAR ExpCSIFbkTxASEL:1; - UCHAR AntSelect:1; -#else UCHAR AntSelect:1; UCHAR ExpCSIFbkTxASEL:1; UCHAR AntIndFbkTxASEL:1; @@ -363,7 +289,6 @@ typedef struct PACKED _HT_AS_CAP{ UCHAR RxASel:1; UCHAR TxSoundPPDU:1; UCHAR rsv:1; -#endif // RT_BIG_ENDIAN // } HT_AS_CAP, *PHT_AS_CAP; // Draft 1.0 set IE length 26, but is extensible.. @@ -407,17 +332,10 @@ typedef struct PACKED _OVERLAP_BSS_SCAN_IE{ // 7.3.2.56. 20/40 Coexistence element used in Element ID = 72 = IE_2040_BSS_COEXIST typedef union PACKED _BSS_2040_COEXIST_IE{ struct PACKED { - #ifdef RT_BIG_ENDIAN - UCHAR rsv:5; - UCHAR BSS20WidthReq:1; - UCHAR Intolerant40:1; - UCHAR InfoReq:1; - #else UCHAR InfoReq:1; UCHAR Intolerant40:1; // Inter-BSS. set 1 when prohibits a receiving BSS from operating as a 20/40 Mhz BSS. UCHAR BSS20WidthReq:1; // Intra-BSS set 1 when prohibits a receiving AP from operating its BSS as a 20/40MHz BSS. UCHAR rsv:5; -#endif // RT_BIG_ENDIAN // } field; UCHAR word; } BSS_2040_COEXIST_IE, *PBSS_2040_COEXIST_IE; @@ -443,17 +361,10 @@ typedef struct _TRIGGER_EVENT_TAB{ // 7.3.27 20/40 Bss Coexistence Mgmt capability used in extended capabilities information IE( ID = 127 = IE_EXT_CAPABILITY). // This is the first octet and was defined in 802.11n D3.03 and 802.11yD9.0 typedef struct PACKED _EXT_CAP_INFO_ELEMENT{ -#ifdef RT_BIG_ENDIAN - UCHAR rsv2:5; - UCHAR ExtendChannelSwitch:1; - UCHAR rsv:1; - UCHAR BssCoexistMgmtSupport:1; -#else UCHAR BssCoexistMgmtSupport:1; UCHAR rsv:1; UCHAR ExtendChannelSwitch:1; UCHAR rsv2:5; -#endif // RT_BIG_ENDIAN // }EXT_CAP_INFO_ELEMENT, *PEXT_CAP_INFO_ELEMENT; @@ -499,18 +410,6 @@ typedef struct { //This structure substracts ralink supports from all 802.11n-related features. //Features not listed here but contained in 802.11n spec are not supported in rt2860. typedef struct { -#ifdef RT_BIG_ENDIAN - USHORT rsv:5; - USHORT AmsduSize:1; // Max receiving A-MSDU size - USHORT AmsduEnable:1; // Enable to transmit A-MSDU. Suggest disable. We should use A-MPDU to gain best benifit of 802.11n - USHORT RxSTBC:2; // 2 bits - USHORT TxSTBC:1; - USHORT ShortGIfor40:1; //for40MHz - USHORT ShortGIfor20:1; - USHORT GF:1; //green field - USHORT MimoPs:2;//mimo power safe MMPS_ - USHORT ChannelWidth:1; -#else USHORT ChannelWidth:1; USHORT MimoPs:2;//mimo power safe MMPS_ USHORT GF:1; //green field @@ -521,34 +420,18 @@ typedef struct { USHORT AmsduEnable:1; // Enable to transmit A-MSDU. Suggest disable. We should use A-MPDU to gain best benifit of 802.11n USHORT AmsduSize:1; // Max receiving A-MSDU size USHORT rsv:5; -#endif //Substract from Addiont HT INFO IE -#ifdef RT_BIG_ENDIAN - UCHAR RecomWidth:1; - UCHAR ExtChanOffset:2; // Please not the difference with following UCHAR NewExtChannelOffset; from 802.11n - UCHAR MpduDensity:3; - UCHAR MaxRAmpduFactor:2; -#else UCHAR MaxRAmpduFactor:2; UCHAR MpduDensity:3; UCHAR ExtChanOffset:2; // Please not the difference with following UCHAR NewExtChannelOffset; from 802.11n UCHAR RecomWidth:1; -#endif -#ifdef RT_BIG_ENDIAN - USHORT rsv2:11; - USHORT OBSS_NonHTExist:1; - USHORT rsv3:1; - USHORT NonGfPresent:1; - USHORT OperaionMode:2; -#else USHORT OperaionMode:2; USHORT NonGfPresent:1; USHORT rsv3:1; USHORT OBSS_NonHTExist:1; USHORT rsv2:11; -#endif // New Extension Channel Offset IE UCHAR NewExtChannelOffset; @@ -558,50 +441,24 @@ typedef struct { // field in Addtional HT Information IE . typedef struct PACKED { -#ifdef RT_BIG_ENDIAN - UCHAR SerInterGranu:3; - UCHAR S_PSMPSup:1; - UCHAR RifsMode:1; - UCHAR RecomWidth:1; - UCHAR ExtChanOffset:2; -#else UCHAR ExtChanOffset:2; UCHAR RecomWidth:1; UCHAR RifsMode:1; UCHAR S_PSMPSup:1; //Indicate support for scheduled PSMP UCHAR SerInterGranu:3; //service interval granularity -#endif } ADD_HTINFO, *PADD_HTINFO; typedef struct PACKED{ -#ifdef RT_BIG_ENDIAN - USHORT rsv2:11; - USHORT OBSS_NonHTExist:1; - USHORT rsv:1; - USHORT NonGfPresent:1; - USHORT OperaionMode:2; -#else USHORT OperaionMode:2; USHORT NonGfPresent:1; USHORT rsv:1; USHORT OBSS_NonHTExist:1; USHORT rsv2:11; -#endif } ADD_HTINFO2, *PADD_HTINFO2; // TODO: Need sync with spec about the definition of StbcMcs. In Draft 3.03, it's reserved. typedef struct PACKED{ -#ifdef RT_BIG_ENDIAN - USHORT rsv:4; - USHORT PcoPhase:1; - USHORT PcoActive:1; - USHORT LsigTxopProt:1; - USHORT STBCBeacon:1; - USHORT DualCTSProtect:1; - USHORT DualBeacon:1; - USHORT StbcMcs:6; -#else USHORT StbcMcs:6; USHORT DualBeacon:1; USHORT DualCTSProtect:1; @@ -610,7 +467,6 @@ typedef struct PACKED{ USHORT PcoActive:1; USHORT PcoPhase:1; USHORT rsv:4; -#endif // RT_BIG_ENDIAN // } ADD_HTINFO3, *PADD_HTINFO3; #define SIZE_ADD_HT_INFO_IE 22 @@ -629,22 +485,6 @@ typedef struct PACKED{ // 4-byte HTC field. maybe included in any frame except non-QOS data frame. The Order bit must set 1. typedef struct PACKED { -#ifdef RT_BIG_ENDIAN - UINT32 RDG:1; //RDG / More PPDU - UINT32 ACConstraint:1; //feedback request - UINT32 rsv:5; //calibration sequence - UINT32 ZLFAnnouce:1; // ZLF announcement - UINT32 CSISTEERING:2; //CSI/ STEERING - UINT32 FBKReq:2; //feedback request - UINT32 CalSeq:2; //calibration sequence - UINT32 CalPos:2; // calibration position - UINT32 MFBorASC:7; //Link adaptation feedback containing recommended MCS. 0x7f for no feedback or not available - UINT32 MFS:3; //SET to the received value of MRS. 0x111 for unsolicited MFB. - UINT32 MRSorASI:3; // MRQ Sequence identifier. unchanged during entire procedure. 0x000-0x110. - UINT32 MRQ:1; //MCS feedback. Request for a MCS feedback - UINT32 TRQ:1; //sounding request - UINT32 MA:1; //management action payload exist in (QoS Null+HTC) -#else UINT32 MA:1; //management action payload exist in (QoS Null+HTC) UINT32 TRQ:1; //sounding request UINT32 MRQ:1; //MCS feedback. Request for a MCS feedback @@ -659,41 +499,19 @@ typedef struct PACKED { UINT32 rsv:5; //calibration sequence UINT32 ACConstraint:1; //feedback request UINT32 RDG:1; //RDG / More PPDU -#endif /* !RT_BIG_ENDIAN */ } HT_CONTROL, *PHT_CONTROL; // 2-byte QOS CONTROL field typedef struct PACKED { -#ifdef RT_BIG_ENDIAN - USHORT Txop_QueueSize:8; - USHORT AMsduPresent:1; - USHORT AckPolicy:2; //0: normal ACK 1:No ACK 2:scheduled under MTBA/PSMP 3: BA - USHORT EOSP:1; - USHORT TID:4; -#else USHORT TID:4; USHORT EOSP:1; USHORT AckPolicy:2; //0: normal ACK 1:No ACK 2:scheduled under MTBA/PSMP 3: BA USHORT AMsduPresent:1; USHORT Txop_QueueSize:8; -#endif /* !RT_BIG_ENDIAN */ } QOS_CONTROL, *PQOS_CONTROL; // 2-byte Frame control field typedef struct PACKED { -#ifdef RT_BIG_ENDIAN - USHORT Order:1; // Strict order expected - USHORT Wep:1; // Wep data - USHORT MoreData:1; // More data bit - USHORT PwrMgmt:1; // Power management bit - USHORT Retry:1; // Retry status bit - USHORT MoreFrag:1; // More fragment bit - USHORT FrDs:1; // From DS indication - USHORT ToDs:1; // To DS indication - USHORT SubType:4; // MSDU subtype - USHORT Type:2; // MSDU type - USHORT Ver:2; // Protocol version -#else USHORT Ver:2; // Protocol version USHORT Type:2; // MSDU type USHORT SubType:4; // MSDU subtype @@ -705,7 +523,6 @@ typedef struct PACKED { USHORT MoreData:1; // More data bit USHORT Wep:1; // Wep data USHORT Order:1; // Strict order expected -#endif /* !RT_BIG_ENDIAN */ } FRAME_CONTROL, *PFRAME_CONTROL; typedef struct PACKED _HEADER_802_11 { @@ -714,13 +531,8 @@ typedef struct PACKED _HEADER_802_11 { UCHAR Addr1[MAC_ADDR_LEN]; UCHAR Addr2[MAC_ADDR_LEN]; UCHAR Addr3[MAC_ADDR_LEN]; -#ifdef RT_BIG_ENDIAN - USHORT Sequence:12; - USHORT Frag:4; -#else USHORT Frag:4; USHORT Sequence:12; -#endif /* !RT_BIG_ENDIAN */ UCHAR Octet[0]; } HEADER_802_11, *PHEADER_802_11; @@ -744,42 +556,24 @@ typedef struct PACKED _HEADER_802_3 { ////Block ACK related format // 2-byte BA Parameter field in DELBA frames to terminate an already set up bA typedef struct PACKED{ -#ifdef RT_BIG_ENDIAN - USHORT TID:4; // value of TC os TS - USHORT Initiator:1; // 1: originator 0:recipient - USHORT Rsv:11; // always set to 0 -#else USHORT Rsv:11; // always set to 0 USHORT Initiator:1; // 1: originator 0:recipient USHORT TID:4; // value of TC os TS -#endif /* !RT_BIG_ENDIAN */ } DELBA_PARM, *PDELBA_PARM; // 2-byte BA Parameter Set field in ADDBA frames to signal parm for setting up a BA typedef struct PACKED { -#ifdef RT_BIG_ENDIAN - USHORT BufSize:10; // number of buffe of size 2304 octetsr - USHORT TID:4; // value of TC os TS - USHORT BAPolicy:1; // 1: immediately BA 0:delayed BA - USHORT AMSDUSupported:1; // 0: not permitted 1: permitted -#else USHORT AMSDUSupported:1; // 0: not permitted 1: permitted USHORT BAPolicy:1; // 1: immediately BA 0:delayed BA USHORT TID:4; // value of TC os TS USHORT BufSize:10; // number of buffe of size 2304 octetsr -#endif /* !RT_BIG_ENDIAN */ } BA_PARM, *PBA_PARM; // 2-byte BA Starting Seq CONTROL field typedef union PACKED { struct PACKED { -#ifdef RT_BIG_ENDIAN - USHORT StartSeq:12; // sequence number of the 1st MSDU for which this BAR is sent - USHORT FragNum:4; // always set to 0 -#else USHORT FragNum:4; // always set to 0 USHORT StartSeq:12; // sequence number of the 1st MSDU for which this BAR is sent -#endif /* RT_BIG_ENDIAN */ } field; USHORT word; } BASEQ_CONTROL, *PBASEQ_CONTROL; @@ -787,63 +581,34 @@ typedef union PACKED { //BAControl and BARControl are the same // 2-byte BA CONTROL field in BA frame typedef struct PACKED { -#ifdef RT_BIG_ENDIAN - USHORT TID:4; - USHORT Rsv:9; - USHORT Compressed:1; - USHORT MTID:1; //EWC V1.24 - USHORT ACKPolicy:1; // only related to N-Delayed BA. But not support in RT2860b. 0:NormalACK 1:No ACK -#else USHORT ACKPolicy:1; // only related to N-Delayed BA. But not support in RT2860b. 0:NormalACK 1:No ACK USHORT MTID:1; //EWC V1.24 USHORT Compressed:1; USHORT Rsv:9; USHORT TID:4; -#endif /* !RT_BIG_ENDIAN */ } BA_CONTROL, *PBA_CONTROL; // 2-byte BAR CONTROL field in BAR frame typedef struct PACKED { -#ifdef RT_BIG_ENDIAN - USHORT TID:4; - USHORT Rsv1:9; - USHORT Compressed:1; - USHORT MTID:1; //if this bit1, use FRAME_MTBA_REQ, if 0, use FRAME_BA_REQ - USHORT ACKPolicy:1; -#else USHORT ACKPolicy:1; // 0:normal ack, 1:no ack. USHORT MTID:1; //if this bit1, use FRAME_MTBA_REQ, if 0, use FRAME_BA_REQ USHORT Compressed:1; USHORT Rsv1:9; USHORT TID:4; -#endif /* !RT_BIG_ENDIAN */ } BAR_CONTROL, *PBAR_CONTROL; // BARControl in MTBAR frame typedef struct PACKED { -#ifdef RT_BIG_ENDIAN - USHORT NumTID:4; - USHORT Rsv1:9; - USHORT Compressed:1; - USHORT MTID:1; - USHORT ACKPolicy:1; -#else USHORT ACKPolicy:1; USHORT MTID:1; USHORT Compressed:1; USHORT Rsv1:9; USHORT NumTID:4; -#endif /* !RT_BIG_ENDIAN */ } MTBAR_CONTROL, *PMTBAR_CONTROL; typedef struct PACKED { -#ifdef RT_BIG_ENDIAN - USHORT TID:4; - USHORT Rsv1:12; -#else USHORT Rsv1:12; USHORT TID:4; -#endif /* !RT_BIG_ENDIAN */ } PER_TID_INFO, *PPER_TID_INFO; typedef struct { @@ -1063,15 +828,6 @@ typedef struct { // QBSS Info field in QSTA's assoc req typedef struct PACKED { -#ifdef RT_BIG_ENDIAN - UCHAR Rsv2:1; - UCHAR MaxSPLength:2; - UCHAR Rsv1:1; - UCHAR UAPSD_AC_BE:1; - UCHAR UAPSD_AC_BK:1; - UCHAR UAPSD_AC_VI:1; - UCHAR UAPSD_AC_VO:1; -#else UCHAR UAPSD_AC_VO:1; UCHAR UAPSD_AC_VI:1; UCHAR UAPSD_AC_BK:1; @@ -1079,20 +835,13 @@ typedef struct PACKED { UCHAR Rsv1:1; UCHAR MaxSPLength:2; UCHAR Rsv2:1; -#endif /* !RT_BIG_ENDIAN */ } QBSS_STA_INFO_PARM, *PQBSS_STA_INFO_PARM; // QBSS Info field in QAP's Beacon/ProbeRsp typedef struct PACKED { -#ifdef RT_BIG_ENDIAN - UCHAR UAPSD:1; - UCHAR Rsv:3; - UCHAR ParamSetCount:4; -#else UCHAR ParamSetCount:4; UCHAR Rsv:3; UCHAR UAPSD:1; -#endif /* !RT_BIG_ENDIAN */ } QBSS_AP_INFO_PARM, *PQBSS_AP_INFO_PARM; // QOS Capability reported in QAP's BEACON/ProbeRsp @@ -1343,21 +1092,12 @@ typedef struct PACKED { typedef struct PACKED _RTMP_TX_RATE_SWITCH { UCHAR ItemNo; -#ifdef RT_BIG_ENDIAN - UCHAR Rsv2:2; - UCHAR Mode:2; - UCHAR Rsv1:1; - UCHAR BW:1; - UCHAR ShortGI:1; - UCHAR STBC:1; -#else UCHAR STBC:1; UCHAR ShortGI:1; UCHAR BW:1; UCHAR Rsv1:1; UCHAR Mode:2; UCHAR Rsv2:2; -#endif UCHAR CurrMCS; UCHAR TrainUp; UCHAR TrainDown; diff --git a/drivers/staging/rt3070/oid.h b/drivers/staging/rt3070/oid.h index a59855181ef7..a7fc23809f50 100644 --- a/drivers/staging/rt3070/oid.h +++ b/drivers/staging/rt3070/oid.h @@ -737,18 +737,6 @@ enum { // MIMO Tx parameter, ShortGI, MCS, STBC, etc. these are fields in TXWI. Don't change this definition!!! typedef union _HTTRANSMIT_SETTING { -#ifdef RT_BIG_ENDIAN - struct { - USHORT MODE:2; // Use definition MODE_xxx. -// USHORT rsv:3; - USHORT TxBF:1; - USHORT rsv:2; - USHORT STBC:2; //SPACE - USHORT ShortGI:1; - USHORT BW:1; //channel bandwidth 20MHz or 40 MHz - USHORT MCS:7; // MCS - } field; -#else struct { USHORT MCS:7; // MCS USHORT BW:1; //channel bandwidth 20MHz or 40 MHz @@ -759,7 +747,6 @@ typedef union _HTTRANSMIT_SETTING { USHORT TxBF:1; USHORT MODE:2; // Use definition MODE_xxx. } field; -#endif USHORT word; } HTTRANSMIT_SETTING, *PHTTRANSMIT_SETTING; diff --git a/drivers/staging/rt3070/rt2870.h b/drivers/staging/rt3070/rt2870.h index 79030c6066b5..3cfbe02ef4ba 100644 --- a/drivers/staging/rt3070/rt2870.h +++ b/drivers/staging/rt3070/rt2870.h @@ -157,30 +157,6 @@ // // RXINFO appends at the end of each rx packet. // -#ifdef RT_BIG_ENDIAN -typedef struct PACKED _RXINFO_STRUC { - UINT32 PlcpSignal:12; - UINT32 LastAMSDU:1; - UINT32 CipherAlg:1; - UINT32 PlcpRssil:1; - UINT32 Decrypted:1; - UINT32 AMPDU:1; // To be moved - UINT32 L2PAD:1; - UINT32 RSSI:1; - UINT32 HTC:1; - UINT32 AMSDU:1; // rx with 802.3 header, not 802.11 header. - UINT32 CipherErr:2; // 0: decryption okay, 1:ICV error, 2:MIC error, 3:KEY not valid - UINT32 Crc:1; // 1: CRC error - UINT32 MyBss:1; // 1: this frame belongs to the same BSSID - UINT32 Bcast:1; // 1: this is a broadcast frame - UINT32 Mcast:1; // 1: this is a multicast frame - UINT32 U2M:1; // 1: this RX frame is unicast to me - UINT32 FRAG:1; - UINT32 NULLDATA:1; - UINT32 DATA:1; - UINT32 BA:1; -} RXINFO_STRUC, *PRXINFO_STRUC, RT28XX_RXD_STRUC, *PRT28XX_RXD_STRUC; -#else typedef struct PACKED _RXINFO_STRUC { UINT32 BA:1; UINT32 DATA:1; @@ -203,25 +179,10 @@ typedef struct PACKED _RXINFO_STRUC { UINT32 LastAMSDU:1; UINT32 PlcpSignal:12; } RXINFO_STRUC, *PRXINFO_STRUC, RT28XX_RXD_STRUC, *PRT28XX_RXD_STRUC; -#endif - // // TXINFO // -#ifdef RT_BIG_ENDIAN -typedef struct _TXINFO_STRUC { - // Word 0 - UINT32 USBDMATxburst:1;//used ONLY in USB bulk Aggre. Force USB DMA transmit frame from current selected endpoint - UINT32 USBDMANextVLD:1; //used ONLY in USB bulk Aggregation, NextValid - UINT32 rsv2:2; // Software use. - UINT32 SwUseLastRound:1; // Software use. - UINT32 QSEL:2; // select on-chip FIFO ID for 2nd-stage output scheduler.0:MGMT, 1:HCCA 2:EDCA - UINT32 WIV:1; // Wireless Info Valid. 1 if Driver already fill WI, o if DMA needs to copy WI to correctposition - UINT32 rsv:8; - UINT32 USBDMATxPktLen:16; //used ONLY in USB bulk Aggregation, Total byte counts of all sub-frame. -} TXINFO_STRUC, *PTXINFO_STRUC; -#else typedef struct _TXINFO_STRUC { // Word 0 UINT32 USBDMATxPktLen:16; //used ONLY in USB bulk Aggregation, Total byte counts of all sub-frame. @@ -233,7 +194,6 @@ typedef struct _TXINFO_STRUC { UINT32 USBDMANextVLD:1; //used ONLY in USB bulk Aggregation, NextValid UINT32 USBDMATxburst:1;//used ONLY in USB bulk Aggre. Force USB DMA transmit frame from current selected endpoint } TXINFO_STRUC, *PTXINFO_STRUC; -#endif #define TXINFO_SIZE 4 #define RXINFO_SIZE 4 diff --git a/drivers/staging/rt3070/rt28xx.h b/drivers/staging/rt3070/rt28xx.h index b637c4ee6096..d150ab56e448 100644 --- a/drivers/staging/rt3070/rt28xx.h +++ b/drivers/staging/rt3070/rt28xx.h @@ -61,32 +61,6 @@ typedef int NTSTATUS; // #define DMA_CSR0 0x200 #define INT_SOURCE_CSR 0x200 -#ifdef RT_BIG_ENDIAN -typedef union _INT_SOURCE_CSR_STRUC { - struct { - UINT32 :14; - UINT32 TxCoherent:1; - UINT32 RxCoherent:1; - UINT32 GPTimer:1; - UINT32 AutoWakeup:1;//bit14 - UINT32 TXFifoStatusInt:1;//FIFO Statistics is full, sw should read 0x171c - UINT32 PreTBTT:1; - UINT32 TBTTInt:1; - UINT32 RxTxCoherent:1; - UINT32 MCUCommandINT:1; - UINT32 MgmtDmaDone:1; - UINT32 HccaDmaDone:1; - UINT32 Ac3DmaDone:1; - UINT32 Ac2DmaDone:1; - UINT32 Ac1DmaDone:1; - UINT32 Ac0DmaDone:1; - UINT32 RxDone:1; - UINT32 TxDelayINT:1; //delayed interrupt, not interrupt until several int or time limit hit - UINT32 RxDelayINT:1; //dealyed interrupt - } field; - UINT32 word; -} INT_SOURCE_CSR_STRUC, *PINT_SOURCE_CSR_STRUC; -#else typedef union _INT_SOURCE_CSR_STRUC { struct { UINT32 RxDelayINT:1; @@ -111,32 +85,11 @@ typedef union _INT_SOURCE_CSR_STRUC { } field; UINT32 word; } INT_SOURCE_CSR_STRUC, *PINT_SOURCE_CSR_STRUC; -#endif // // INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF // #define INT_MASK_CSR 0x204 -#ifdef RT_BIG_ENDIAN -typedef union _INT_MASK_CSR_STRUC { - struct { - UINT32 TxCoherent:1; - UINT32 RxCoherent:1; - UINT32 :20; - UINT32 MCUCommandINT:1; - UINT32 MgmtDmaDone:1; - UINT32 HccaDmaDone:1; - UINT32 Ac3DmaDone:1; - UINT32 Ac2DmaDone:1; - UINT32 Ac1DmaDone:1; - UINT32 Ac0DmaDone:1; - UINT32 RxDone:1; - UINT32 TxDelay:1; - UINT32 RXDelay_INT_MSK:1; - } field; - UINT32 word; -}INT_MASK_CSR_STRUC, *PINT_MASK_CSR_STRUC; -#else typedef union _INT_MASK_CSR_STRUC { struct { UINT32 RXDelay_INT_MSK:1; @@ -155,24 +108,8 @@ typedef union _INT_MASK_CSR_STRUC { } field; UINT32 word; } INT_MASK_CSR_STRUC, *PINT_MASK_CSR_STRUC; -#endif + #define WPDMA_GLO_CFG 0x208 -#ifdef RT_BIG_ENDIAN -typedef union _WPDMA_GLO_CFG_STRUC { - struct { - UINT32 HDR_SEG_LEN:16; - UINT32 RXHdrScater:8; - UINT32 BigEndian:1; - UINT32 EnTXWriteBackDDONE:1; - UINT32 WPDMABurstSIZE:2; - UINT32 RxDMABusy:1; - UINT32 EnableRxDMA:1; - UINT32 TxDMABusy:1; - UINT32 EnableTxDMA:1; - } field; - UINT32 word; -}WPDMA_GLO_CFG_STRUC, *PWPDMA_GLO_CFG_STRUC; -#else typedef union _WPDMA_GLO_CFG_STRUC { struct { UINT32 EnableTxDMA:1; @@ -187,24 +124,8 @@ typedef union _WPDMA_GLO_CFG_STRUC { } field; UINT32 word; } WPDMA_GLO_CFG_STRUC, *PWPDMA_GLO_CFG_STRUC; -#endif + #define WPDMA_RST_IDX 0x20c -#ifdef RT_BIG_ENDIAN -typedef union _WPDMA_RST_IDX_STRUC { - struct { - UINT32 :15; - UINT32 RST_DRX_IDX0:1; - UINT32 rsv:10; - UINT32 RST_DTX_IDX5:1; - UINT32 RST_DTX_IDX4:1; - UINT32 RST_DTX_IDX3:1; - UINT32 RST_DTX_IDX2:1; - UINT32 RST_DTX_IDX1:1; - UINT32 RST_DTX_IDX0:1; - } field; - UINT32 word; -}WPDMA_RST_IDX_STRUC, *PWPDMA_RST_IDX_STRUC; -#else typedef union _WPDMA_RST_IDX_STRUC { struct { UINT32 RST_DTX_IDX0:1; @@ -219,21 +140,8 @@ typedef union _WPDMA_RST_IDX_STRUC { } field; UINT32 word; } WPDMA_RST_IDX_STRUC, *PWPDMA_RST_IDX_STRUC; -#endif + #define DELAY_INT_CFG 0x0210 -#ifdef RT_BIG_ENDIAN -typedef union _DELAY_INT_CFG_STRUC { - struct { - UINT32 TXDLY_INT_EN:1; - UINT32 TXMAX_PINT:7; - UINT32 TXMAX_PTIME:8; - UINT32 RXDLY_INT_EN:1; - UINT32 RXMAX_PINT:7; - UINT32 RXMAX_PTIME:8; - } field; - UINT32 word; -}DELAY_INT_CFG_STRUC, *PDELAY_INT_CFG_STRUC; -#else typedef union _DELAY_INT_CFG_STRUC { struct { UINT32 RXMAX_PTIME:8; @@ -245,20 +153,8 @@ typedef union _DELAY_INT_CFG_STRUC { } field; UINT32 word; } DELAY_INT_CFG_STRUC, *PDELAY_INT_CFG_STRUC; -#endif + #define WMM_AIFSN_CFG 0x0214 -#ifdef RT_BIG_ENDIAN -typedef union _AIFSN_CSR_STRUC { - struct { - UINT32 Rsv:16; - UINT32 Aifsn3:4; // for AC_VO - UINT32 Aifsn2:4; // for AC_VI - UINT32 Aifsn1:4; // for AC_BK - UINT32 Aifsn0:4; // for AC_BE - } field; - UINT32 word; -} AIFSN_CSR_STRUC, *PAIFSN_CSR_STRUC; -#else typedef union _AIFSN_CSR_STRUC { struct { UINT32 Aifsn0:4; // for AC_BE @@ -269,23 +165,11 @@ typedef union _AIFSN_CSR_STRUC { } field; UINT32 word; } AIFSN_CSR_STRUC, *PAIFSN_CSR_STRUC; -#endif + // // CWMIN_CSR: CWmin for each EDCA AC // #define WMM_CWMIN_CFG 0x0218 -#ifdef RT_BIG_ENDIAN -typedef union _CWMIN_CSR_STRUC { - struct { - UINT32 Rsv:16; - UINT32 Cwmin3:4; // for AC_VO - UINT32 Cwmin2:4; // for AC_VI - UINT32 Cwmin1:4; // for AC_BK - UINT32 Cwmin0:4; // for AC_BE - } field; - UINT32 word; -} CWMIN_CSR_STRUC, *PCWMIN_CSR_STRUC; -#else typedef union _CWMIN_CSR_STRUC { struct { UINT32 Cwmin0:4; // for AC_BE @@ -296,24 +180,11 @@ typedef union _CWMIN_CSR_STRUC { } field; UINT32 word; } CWMIN_CSR_STRUC, *PCWMIN_CSR_STRUC; -#endif // // CWMAX_CSR: CWmin for each EDCA AC // #define WMM_CWMAX_CFG 0x021c -#ifdef RT_BIG_ENDIAN -typedef union _CWMAX_CSR_STRUC { - struct { - UINT32 Rsv:16; - UINT32 Cwmax3:4; // for AC_VO - UINT32 Cwmax2:4; // for AC_VI - UINT32 Cwmax1:4; // for AC_BK - UINT32 Cwmax0:4; // for AC_BE - } field; - UINT32 word; -} CWMAX_CSR_STRUC, *PCWMAX_CSR_STRUC; -#else typedef union _CWMAX_CSR_STRUC { struct { UINT32 Cwmax0:4; // for AC_BE @@ -324,22 +195,11 @@ typedef union _CWMAX_CSR_STRUC { } field; UINT32 word; } CWMAX_CSR_STRUC, *PCWMAX_CSR_STRUC; -#endif - // // AC_TXOP_CSR0: AC_BK/AC_BE TXOP register // #define WMM_TXOP0_CFG 0x0220 -#ifdef RT_BIG_ENDIAN -typedef union _AC_TXOP_CSR0_STRUC { - struct { - USHORT Ac1Txop; // for AC_BE, in unit of 32us - USHORT Ac0Txop; // for AC_BK, in unit of 32us - } field; - UINT32 word; -} AC_TXOP_CSR0_STRUC, *PAC_TXOP_CSR0_STRUC; -#else typedef union _AC_TXOP_CSR0_STRUC { struct { USHORT Ac0Txop; // for AC_BK, in unit of 32us @@ -347,21 +207,11 @@ typedef union _AC_TXOP_CSR0_STRUC { } field; UINT32 word; } AC_TXOP_CSR0_STRUC, *PAC_TXOP_CSR0_STRUC; -#endif // // AC_TXOP_CSR1: AC_VO/AC_VI TXOP register // #define WMM_TXOP1_CFG 0x0224 -#ifdef RT_BIG_ENDIAN -typedef union _AC_TXOP_CSR1_STRUC { - struct { - USHORT Ac3Txop; // for AC_VO, in unit of 32us - USHORT Ac2Txop; // for AC_VI, in unit of 32us - } field; - UINT32 word; -} AC_TXOP_CSR1_STRUC, *PAC_TXOP_CSR1_STRUC; -#else typedef union _AC_TXOP_CSR1_STRUC { struct { USHORT Ac2Txop; // for AC_VI, in unit of 32us @@ -369,7 +219,7 @@ typedef union _AC_TXOP_CSR1_STRUC { } field; UINT32 word; } AC_TXOP_CSR1_STRUC, *PAC_TXOP_CSR1_STRUC; -#endif + #define RINGREG_DIFF 0x10 #define GPIO_CTRL_CFG 0x0228 //MAC_CSR13 #define MCU_CMD_CFG 0x022c @@ -405,25 +255,7 @@ typedef union _AC_TXOP_CSR1_STRUC { #define RX_CRX_IDX 0x0298 #define RX_DRX_IDX 0x029c #define USB_DMA_CFG 0x02a0 -#ifdef RT_BIG_ENDIAN -typedef union _USB_DMA_CFG_STRUC { - struct { - UINT32 TxBusy:1; //USB DMA TX FSM busy . debug only - UINT32 RxBusy:1; //USB DMA RX FSM busy . debug only - UINT32 EpoutValid:6; //OUT endpoint data valid. debug only - UINT32 TxBulkEn:1; //Enable USB DMA Tx - UINT32 RxBulkEn:1; //Enable USB DMA Rx - UINT32 RxBulkAggEn:1; //Enable Rx Bulk Aggregation - UINT32 TxopHalt:1; //Halt TXOP count down when TX buffer is full. - UINT32 TxClear:1; //Clear USB DMA TX path - UINT32 rsv:2; - UINT32 phyclear:1; //phy watch dog enable. write 1 - UINT32 RxBulkAggLmt:8; //Rx Bulk Aggregation Limit in unit of 1024 bytes - UINT32 RxBulkAggTOut:8; //Rx Bulk Aggregation TimeOut in unit of 33ns - } field; - UINT32 word; -} USB_DMA_CFG_STRUC, *PUSB_DMA_CFG_STRUC; -#else + typedef union _USB_DMA_CFG_STRUC { struct { UINT32 RxBulkAggTOut:8; //Rx Bulk Aggregation TimeOut in unit of 33ns @@ -441,7 +273,6 @@ typedef union _USB_DMA_CFG_STRUC { } field; UINT32 word; } USB_DMA_CFG_STRUC, *PUSB_DMA_CFG_STRUC; -#endif // // 3 PBF registers @@ -470,21 +301,6 @@ typedef union _USB_DMA_CFG_STRUC { #define EFUSE_TAG 0x2fe #define EFUSE_USAGE_MAP_SIZE 45 -#ifdef RT_BIG_ENDIAN -typedef union _EFUSE_CTRL_STRUC { - struct { - UINT32 SEL_EFUSE:1; - UINT32 EFSROM_KICK:1; - UINT32 RESERVED:4; - UINT32 EFSROM_AIN:10; - UINT32 EFSROM_LDO_ON_TIME:2; - UINT32 EFSROM_LDO_OFF_TIME:6; - UINT32 EFSROM_MODE:2; - UINT32 EFSROM_AOUT:6; - } field; - UINT32 word; -} EFUSE_CTRL_STRUC, *PEFUSE_CTRL_STRUC; -#else typedef union _EFUSE_CTRL_STRUC { struct { UINT32 EFSROM_AOUT:6; @@ -498,7 +314,6 @@ typedef union _EFUSE_CTRL_STRUC { } field; UINT32 word; } EFUSE_CTRL_STRUC, *PEFUSE_CTRL_STRUC; -#endif // RT_BIG_ENDIAN // #define LDO_CFG0 0x05d4 #define GPIO_SWITCH 0x05dc @@ -510,15 +325,6 @@ typedef union _EFUSE_CTRL_STRUC { // 4.1 MAC SYSTEM configuration registers (offset:0x1000) // #define MAC_CSR0 0x1000 -#ifdef RT_BIG_ENDIAN -typedef union _ASIC_VER_ID_STRUC { - struct { - USHORT ASICVer; // version : 2860 - USHORT ASICRev; // reversion : 0 - } field; - UINT32 word; -} ASIC_VER_ID_STRUC, *PASIC_VER_ID_STRUC; -#else typedef union _ASIC_VER_ID_STRUC { struct { USHORT ASICRev; // reversion : 0 @@ -526,24 +332,13 @@ typedef union _ASIC_VER_ID_STRUC { } field; UINT32 word; } ASIC_VER_ID_STRUC, *PASIC_VER_ID_STRUC; -#endif + #define MAC_SYS_CTRL 0x1004 //MAC_CSR1 #define MAC_ADDR_DW0 0x1008 // MAC ADDR DW0 #define MAC_ADDR_DW1 0x100c // MAC ADDR DW1 // // MAC_CSR2: STA MAC register 0 // -#ifdef RT_BIG_ENDIAN -typedef union _MAC_DW0_STRUC { - struct { - UCHAR Byte3; // MAC address byte 3 - UCHAR Byte2; // MAC address byte 2 - UCHAR Byte1; // MAC address byte 1 - UCHAR Byte0; // MAC address byte 0 - } field; - UINT32 word; -} MAC_DW0_STRUC, *PMAC_DW0_STRUC; -#else typedef union _MAC_DW0_STRUC { struct { UCHAR Byte0; // MAC address byte 0 @@ -553,22 +348,10 @@ typedef union _MAC_DW0_STRUC { } field; UINT32 word; } MAC_DW0_STRUC, *PMAC_DW0_STRUC; -#endif // // MAC_CSR3: STA MAC register 1 // -#ifdef RT_BIG_ENDIAN -typedef union _MAC_DW1_STRUC { - struct { - UCHAR Rsvd1; - UCHAR U2MeMask; - UCHAR Byte5; // MAC address byte 5 - UCHAR Byte4; // MAC address byte 4 - } field; - UINT32 word; -} MAC_DW1_STRUC, *PMAC_DW1_STRUC; -#else typedef union _MAC_DW1_STRUC { struct { UCHAR Byte4; // MAC address byte 4 @@ -578,7 +361,6 @@ typedef union _MAC_DW1_STRUC { } field; UINT32 word; } MAC_DW1_STRUC, *PMAC_DW1_STRUC; -#endif #define MAC_BSSID_DW0 0x1010 // MAC BSSID DW0 #define MAC_BSSID_DW1 0x1014 // MAC BSSID DW1 @@ -586,18 +368,6 @@ typedef union _MAC_DW1_STRUC { // // MAC_CSR5: BSSID register 1 // -#ifdef RT_BIG_ENDIAN -typedef union _MAC_CSR5_STRUC { - struct { - USHORT Rsvd:11; - USHORT MBssBcnNum:3; - USHORT BssIdMode:2; // 0: one BSSID, 10: 4 BSSID, 01: 2 BSSID , 11: 8BSSID - UCHAR Byte5; // BSSID byte 5 - UCHAR Byte4; // BSSID byte 4 - } field; - UINT32 word; -} MAC_CSR5_STRUC, *PMAC_CSR5_STRUC; -#else typedef union _MAC_CSR5_STRUC { struct { UCHAR Byte4; // BSSID byte 4 @@ -608,27 +378,12 @@ typedef union _MAC_CSR5_STRUC { } field; UINT32 word; } MAC_CSR5_STRUC, *PMAC_CSR5_STRUC; -#endif #define MAX_LEN_CFG 0x1018 // rt2860b max 16k bytes. bit12:13 Maximum PSDU length (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16 #define BBP_CSR_CFG 0x101c // // // BBP_CSR_CFG: BBP serial control register // -#ifdef RT_BIG_ENDIAN -typedef union _BBP_CSR_CFG_STRUC { - struct { - UINT32 :12; - UINT32 BBP_RW_MODE:1; // 0: use serial mode 1:parallel - UINT32 BBP_PAR_DUR:1; // 0: 4 MAC clock cycles 1: 8 MAC clock cycles - UINT32 Busy:1; // 1: ASIC is busy execute BBP programming. - UINT32 fRead:1; // 0: Write BBP, 1: Read BBP - UINT32 RegNum:8; // Selected BBP register - UINT32 Value:8; // Register value to program into BBP - } field; - UINT32 word; -} BBP_CSR_CFG_STRUC, *PBBP_CSR_CFG_STRUC; -#else typedef union _BBP_CSR_CFG_STRUC { struct { UINT32 Value:8; // Register value to program into BBP @@ -641,23 +396,11 @@ typedef union _BBP_CSR_CFG_STRUC { } field; UINT32 word; } BBP_CSR_CFG_STRUC, *PBBP_CSR_CFG_STRUC; -#endif + #define RF_CSR_CFG0 0x1020 // // RF_CSR_CFG: RF control register // -#ifdef RT_BIG_ENDIAN -typedef union _RF_CSR_CFG0_STRUC { - struct { - UINT32 Busy:1; // 0: idle 1: 8busy - UINT32 Sel:1; // 0:RF_LE0 activate 1:RF_LE1 activate - UINT32 StandbyMode:1; // 0: high when stand by 1: low when standby - UINT32 bitwidth:5; // Selected BBP register - UINT32 RegIdAndContent:24; // Register value to program into BBP - } field; - UINT32 word; -} RF_CSR_CFG0_STRUC, *PRF_CSR_CFG0_STRUC; -#else typedef union _RF_CSR_CFG0_STRUC { struct { UINT32 RegIdAndContent:24; // Register value to program into BBP @@ -668,18 +411,8 @@ typedef union _RF_CSR_CFG0_STRUC { } field; UINT32 word; } RF_CSR_CFG0_STRUC, *PRF_CSR_CFG0_STRUC; -#endif + #define RF_CSR_CFG1 0x1024 -#ifdef RT_BIG_ENDIAN -typedef union _RF_CSR_CFG1_STRUC { - struct { - UINT32 rsv:7; // 0: idle 1: 8busy - UINT32 RFGap:5; // Gap between BB_CONTROL_RF and RF_LE. 0: 3 system clock cycle (37.5usec) 1: 5 system clock cycle (62.5usec) - UINT32 RegIdAndContent:24; // Register value to program into BBP - } field; - UINT32 word; -} RF_CSR_CFG1_STRUC, *PRF_CSR_CFG1_STRUC; -#else typedef union _RF_CSR_CFG1_STRUC { struct { UINT32 RegIdAndContent:24; // Register value to program into BBP @@ -688,17 +421,8 @@ typedef union _RF_CSR_CFG1_STRUC { } field; UINT32 word; } RF_CSR_CFG1_STRUC, *PRF_CSR_CFG1_STRUC; -#endif + #define RF_CSR_CFG2 0x1028 // -#ifdef RT_BIG_ENDIAN -typedef union _RF_CSR_CFG2_STRUC { - struct { - UINT32 rsv:8; // 0: idle 1: 8busy - UINT32 RegIdAndContent:24; // Register value to program into BBP - } field; - UINT32 word; -} RF_CSR_CFG2_STRUC, *PRF_CSR_CFG2_STRUC; -#else typedef union _RF_CSR_CFG2_STRUC { struct { UINT32 RegIdAndContent:24; // Register value to program into BBP @@ -706,24 +430,8 @@ typedef union _RF_CSR_CFG2_STRUC { } field; UINT32 word; } RF_CSR_CFG2_STRUC, *PRF_CSR_CFG2_STRUC; -#endif + #define LED_CFG 0x102c // MAC_CSR14 -#ifdef RT_BIG_ENDIAN -typedef union _LED_CFG_STRUC { - struct { - UINT32 :1; - UINT32 LedPolar:1; // Led Polarity. 0: active low1: active high - UINT32 YLedMode:2; // yellow Led Mode - UINT32 GLedMode:2; // green Led Mode - UINT32 RLedMode:2; // red Led Mode 0: off1: blinking upon TX2: periodic slow blinking3: always on - UINT32 rsv:2; - UINT32 SlowBlinkPeriod:6; // slow blinking period. unit:1ms - UINT32 OffPeriod:8; // blinking off period unit 1ms - UINT32 OnPeriod:8; // blinking on period unit 1ms - } field; - UINT32 word; -} LED_CFG_STRUC, *PLED_CFG_STRUC; -#else typedef union _LED_CFG_STRUC { struct { UINT32 OnPeriod:8; // blinking on period unit 1ms @@ -738,24 +446,11 @@ typedef union _LED_CFG_STRUC { } field; UINT32 word; } LED_CFG_STRUC, *PLED_CFG_STRUC; -#endif + // // 4.2 MAC TIMING configuration registers (offset:0x1100) // #define XIFS_TIME_CFG 0x1100 // MAC_CSR8 MAC_CSR9 -#ifdef RT_BIG_ENDIAN -typedef union _IFS_SLOT_CFG_STRUC { - struct { - UINT32 rsv:2; - UINT32 BBRxendEnable:1; // reference RXEND signal to begin XIFS defer - UINT32 EIFS:9; // unit 1us - UINT32 OfdmXifsTime:4; //OFDM SIFS. unit 1us. Applied after OFDM RX when MAC doesn't reference BBP signal BBRXEND - UINT32 OfdmSifsTime:8; // unit 1us. Applied after OFDM RX/TX - UINT32 CckmSifsTime:8; // unit 1us. Applied after CCK RX/TX - } field; - UINT32 word; -} IFS_SLOT_CFG_STRUC, *PIFS_SLOT_CFG_STRUC; -#else typedef union _IFS_SLOT_CFG_STRUC { struct { UINT32 CckmSifsTime:8; // unit 1us. Applied after CCK RX/TX @@ -767,7 +462,6 @@ typedef union _IFS_SLOT_CFG_STRUC { } field; UINT32 word; } IFS_SLOT_CFG_STRUC, *PIFS_SLOT_CFG_STRUC; -#endif #define BKOFF_SLOT_CFG 0x1104 // mac_csr9 last 8 bits #define NAV_TIME_CFG 0x1108 // NAV (MAC_CSR15) @@ -781,20 +475,6 @@ typedef union _IFS_SLOT_CFG_STRUC { // // BCN_TIME_CFG : Synchronization control register // -#ifdef RT_BIG_ENDIAN -typedef union _BCN_TIME_CFG_STRUC { - struct { - UINT32 TxTimestampCompensate:8; - UINT32 :3; - UINT32 bBeaconGen:1; // Enable beacon generator - UINT32 bTBTTEnable:1; - UINT32 TsfSyncMode:2; // Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode - UINT32 bTsfTicking:1; // Enable TSF auto counting - UINT32 BeaconInterval:16; // in unit of 1/16 TU - } field; - UINT32 word; -} BCN_TIME_CFG_STRUC, *PBCN_TIME_CFG_STRUC; -#else typedef union _BCN_TIME_CFG_STRUC { struct { UINT32 BeaconInterval:16; // in unit of 1/16 TU @@ -807,7 +487,7 @@ typedef union _BCN_TIME_CFG_STRUC { } field; UINT32 word; } BCN_TIME_CFG_STRUC, *PBCN_TIME_CFG_STRUC; -#endif + #define TBTT_SYNC_CFG 0x1118 // txrx_csr10 #define TSF_TIMER_DW0 0x111C // Local TSF timer lsb 32 bits. Read-only #define TSF_TIMER_DW1 0x1120 // msb 32 bits. Read-only. @@ -825,17 +505,6 @@ typedef union _BCN_TIME_CFG_STRUC { // // AUTO_WAKEUP_CFG: Manual power control / status register // -#ifdef RT_BIG_ENDIAN -typedef union _AUTO_WAKEUP_STRUC { - struct { - UINT32 :16; - UINT32 EnableAutoWakeup:1; // 0:sleep, 1:awake - UINT32 NumofSleepingTbtt:7; // ForceWake has high privilege than PutToSleep when both set - UINT32 AutoLeadTime:8; - } field; - UINT32 word; -} AUTO_WAKEUP_STRUC, *PAUTO_WAKEUP_STRUC; -#else typedef union _AUTO_WAKEUP_STRUC { struct { UINT32 AutoLeadTime:8; @@ -845,7 +514,7 @@ typedef union _AUTO_WAKEUP_STRUC { } field; UINT32 word; } AUTO_WAKEUP_STRUC, *PAUTO_WAKEUP_STRUC; -#endif + // // 4.3 MAC TX configuration registers (offset:0x1300) // @@ -854,18 +523,6 @@ typedef union _AUTO_WAKEUP_STRUC { #define EDCA_AC1_CFG 0x1304 #define EDCA_AC2_CFG 0x1308 #define EDCA_AC3_CFG 0x130c -#ifdef RT_BIG_ENDIAN -typedef union _EDCA_AC_CFG_STRUC { - struct { - UINT32 :12; // - UINT32 Cwmax:4; //unit power of 2 - UINT32 Cwmin:4; // - UINT32 Aifsn:4; // # of slot time - UINT32 AcTxop:8; // in unit of 32us - } field; - UINT32 word; -} EDCA_AC_CFG_STRUC, *PEDCA_AC_CFG_STRUC; -#else typedef union _EDCA_AC_CFG_STRUC { struct { UINT32 AcTxop:8; // in unit of 32us @@ -876,7 +533,6 @@ typedef union _EDCA_AC_CFG_STRUC { } field; UINT32 word; } EDCA_AC_CFG_STRUC, *PEDCA_AC_CFG_STRUC; -#endif #define EDCA_TID_AC_MAP 0x1310 #define TX_PWR_CFG_0 0x1314 @@ -893,17 +549,6 @@ typedef union _EDCA_AC_CFG_STRUC { #define TXOP_CTRL_CFG 0x1340 #define TX_RTS_CFG 0x1344 -#ifdef RT_BIG_ENDIAN -typedef union _TX_RTS_CFG_STRUC { - struct { - UINT32 rsv:7; - UINT32 RtsFbkEn:1; // enable rts rate fallback - UINT32 RtsThres:16; // unit:byte - UINT32 AutoRtsRetryLimit:8; - } field; - UINT32 word; -} TX_RTS_CFG_STRUC, *PTX_RTS_CFG_STRUC; -#else typedef union _TX_RTS_CFG_STRUC { struct { UINT32 AutoRtsRetryLimit:8; @@ -913,20 +558,8 @@ typedef union _TX_RTS_CFG_STRUC { } field; UINT32 word; } TX_RTS_CFG_STRUC, *PTX_RTS_CFG_STRUC; -#endif + #define TX_TIMEOUT_CFG 0x1348 -#ifdef RT_BIG_ENDIAN -typedef union _TX_TIMEOUT_CFG_STRUC { - struct { - UINT32 rsv2:8; - UINT32 TxopTimeout:8; //TXOP timeout value for TXOP truncation. It is recommended that (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT) - UINT32 RxAckTimeout:8; // unit:slot. Used for TX precedure - UINT32 MpduLifeTime:4; // expiration time = 2^(9+MPDU LIFE TIME) us - UINT32 rsv:4; - } field; - UINT32 word; -} TX_TIMEOUT_CFG_STRUC, *PTX_TIMEOUT_CFG_STRUC; -#else typedef union _TX_TIMEOUT_CFG_STRUC { struct { UINT32 rsv:4; @@ -937,23 +570,8 @@ typedef union _TX_TIMEOUT_CFG_STRUC { } field; UINT32 word; } TX_TIMEOUT_CFG_STRUC, *PTX_TIMEOUT_CFG_STRUC; -#endif -#define TX_RTY_CFG 0x134c -#ifdef RT_BIG_ENDIAN -typedef union PACKED _TX_RTY_CFG_STRUC { - struct { - UINT32 rsv:1; - UINT32 TxautoFBEnable:1; // Tx retry PHY rate auto fallback enable - UINT32 AggRtyMode:1; // Aggregate MPDU retry mode. 0:expired by retry limit, 1: expired by mpdu life timer - UINT32 NonAggRtyMode:1; // Non-Aggregate MPDU retry mode. 0:expired by retry limit, 1: expired by mpdu life timer - UINT32 LongRtyThre:12; // Long retry threshoold - UINT32 LongRtyLimit:8; //long retry limit - UINT32 ShortRtyLimit:8; // short retry limit - } field; - UINT32 word; -} TX_RTY_CFG_STRUC, *PTX_RTY_CFG_STRUC; -#else +#define TX_RTY_CFG 0x134c typedef union PACKED _TX_RTY_CFG_STRUC { struct { UINT32 ShortRtyLimit:8; // short retry limit @@ -966,24 +584,8 @@ typedef union PACKED _TX_RTY_CFG_STRUC { } field; UINT32 word; } TX_RTY_CFG_STRUC, *PTX_RTY_CFG_STRUC; -#endif + #define TX_LINK_CFG 0x1350 -#ifdef RT_BIG_ENDIAN -typedef union PACKED _TX_LINK_CFG_STRUC { - struct PACKED { - UINT32 RemotMFS:8; //remote MCS feedback sequence number - UINT32 RemotMFB:8; // remote MCS feedback - UINT32 rsv:3; // - UINT32 TxCFAckEn:1; // Piggyback CF-ACK enable - UINT32 TxRDGEn:1; // RDG TX enable - UINT32 TxMRQEn:1; // MCS request TX enable - UINT32 RemoteUMFSEnable:1; // remote unsolicit MFB enable. 0: not apply remote remote unsolicit (MFS=7) - UINT32 MFBEnable:1; // TX apply remote MFB 1:enable - UINT32 RemoteMFBLifeTime:8; //remote MFB life time. unit : 32us - } field; - UINT32 word; -} TX_LINK_CFG_STRUC, *PTX_LINK_CFG_STRUC; -#else typedef union PACKED _TX_LINK_CFG_STRUC { struct PACKED { UINT32 RemoteMFBLifeTime:8; //remote MFB life time. unit : 32us @@ -998,23 +600,8 @@ typedef union PACKED _TX_LINK_CFG_STRUC { } field; UINT32 word; } TX_LINK_CFG_STRUC, *PTX_LINK_CFG_STRUC; -#endif + #define HT_FBK_CFG0 0x1354 -#ifdef RT_BIG_ENDIAN -typedef union PACKED _HT_FBK_CFG0_STRUC { - struct { - UINT32 HTMCS7FBK:4; - UINT32 HTMCS6FBK:4; - UINT32 HTMCS5FBK:4; - UINT32 HTMCS4FBK:4; - UINT32 HTMCS3FBK:4; - UINT32 HTMCS2FBK:4; - UINT32 HTMCS1FBK:4; - UINT32 HTMCS0FBK:4; - } field; - UINT32 word; -} HT_FBK_CFG0_STRUC, *PHT_FBK_CFG0_STRUC; -#else typedef union PACKED _HT_FBK_CFG0_STRUC { struct { UINT32 HTMCS0FBK:4; @@ -1028,23 +615,8 @@ typedef union PACKED _HT_FBK_CFG0_STRUC { } field; UINT32 word; } HT_FBK_CFG0_STRUC, *PHT_FBK_CFG0_STRUC; -#endif + #define HT_FBK_CFG1 0x1358 -#ifdef RT_BIG_ENDIAN -typedef union _HT_FBK_CFG1_STRUC { - struct { - UINT32 HTMCS15FBK:4; - UINT32 HTMCS14FBK:4; - UINT32 HTMCS13FBK:4; - UINT32 HTMCS12FBK:4; - UINT32 HTMCS11FBK:4; - UINT32 HTMCS10FBK:4; - UINT32 HTMCS9FBK:4; - UINT32 HTMCS8FBK:4; - } field; - UINT32 word; -} HT_FBK_CFG1_STRUC, *PHT_FBK_CFG1_STRUC; -#else typedef union _HT_FBK_CFG1_STRUC { struct { UINT32 HTMCS8FBK:4; @@ -1058,23 +630,8 @@ typedef union _HT_FBK_CFG1_STRUC { } field; UINT32 word; } HT_FBK_CFG1_STRUC, *PHT_FBK_CFG1_STRUC; -#endif + #define LG_FBK_CFG0 0x135c -#ifdef RT_BIG_ENDIAN -typedef union _LG_FBK_CFG0_STRUC { - struct { - UINT32 OFDMMCS7FBK:4; //initial value is 6 - UINT32 OFDMMCS6FBK:4; //initial value is 5 - UINT32 OFDMMCS5FBK:4; //initial value is 4 - UINT32 OFDMMCS4FBK:4; //initial value is 3 - UINT32 OFDMMCS3FBK:4; //initial value is 2 - UINT32 OFDMMCS2FBK:4; //initial value is 1 - UINT32 OFDMMCS1FBK:4; //initial value is 0 - UINT32 OFDMMCS0FBK:4; //initial value is 0 - } field; - UINT32 word; -} LG_FBK_CFG0_STRUC, *PLG_FBK_CFG0_STRUC; -#else typedef union _LG_FBK_CFG0_STRUC { struct { UINT32 OFDMMCS0FBK:4; //initial value is 0 @@ -1088,20 +645,8 @@ typedef union _LG_FBK_CFG0_STRUC { } field; UINT32 word; } LG_FBK_CFG0_STRUC, *PLG_FBK_CFG0_STRUC; -#endif + #define LG_FBK_CFG1 0x1360 -#ifdef RT_BIG_ENDIAN -typedef union _LG_FBK_CFG1_STRUC { - struct { - UINT32 rsv:16; - UINT32 CCKMCS3FBK:4; //initial value is 2 - UINT32 CCKMCS2FBK:4; //initial value is 1 - UINT32 CCKMCS1FBK:4; //initial value is 0 - UINT32 CCKMCS0FBK:4; //initial value is 0 - } field; - UINT32 word; -} LG_FBK_CFG1_STRUC, *PLG_FBK_CFG1_STRUC; -#else typedef union _LG_FBK_CFG1_STRUC { struct { UINT32 CCKMCS0FBK:4; //initial value is 0 @@ -1112,7 +657,6 @@ typedef union _LG_FBK_CFG1_STRUC { } field; UINT32 word; } LG_FBK_CFG1_STRUC, *PLG_FBK_CFG1_STRUC; -#endif //======================================================= //================ Protection Paramater================================ @@ -1122,24 +666,6 @@ typedef union _LG_FBK_CFG1_STRUC { #define ASIC_LONGNAV 2 #define ASIC_RTS 1 #define ASIC_CTS 2 -#ifdef RT_BIG_ENDIAN -typedef union _PROT_CFG_STRUC { - struct { - UINT32 rsv:5; - UINT32 RTSThEn:1; //RTS threshold enable on CCK TX - UINT32 TxopAllowGF40:1; //CCK TXOP allowance.0:disallow. - UINT32 TxopAllowGF20:1; //CCK TXOP allowance.0:disallow. - UINT32 TxopAllowMM40:1; //CCK TXOP allowance.0:disallow. - UINT32 TxopAllowMM20:1; //CCK TXOP allowance. 0:disallow. - UINT32 TxopAllowOfdm:1; //CCK TXOP allowance.0:disallow. - UINT32 TxopAllowCck:1; //CCK TXOP allowance.0:disallow. - UINT32 ProtectNav:2; //TXOP protection type for CCK TX. 0:None, 1:ShortNAVprotect, 2:LongNAVProtect, 3:rsv - UINT32 ProtectCtrl:2; //Protection control frame type for CCK TX. 1:RTS/CTS, 2:CTS-to-self, 0:None, 3:rsv - UINT32 ProtectRate:16; //Protection control frame rate for CCK TX(RTS/CTS/CFEnd). - } field; - UINT32 word; -} PROT_CFG_STRUC, *PPROT_CFG_STRUC; -#else typedef union _PROT_CFG_STRUC { struct { UINT32 ProtectRate:16; //Protection control frame rate for CCK TX(RTS/CTS/CFEnd). @@ -1156,7 +682,6 @@ typedef union _PROT_CFG_STRUC { } field; UINT32 word; } PROT_CFG_STRUC, *PPROT_CFG_STRUC; -#endif #define OFDM_PROT_CFG 0x1368 //OFDM Protection #define MM20_PROT_CFG 0x136C //MM20 Protection @@ -1174,22 +699,6 @@ typedef union _PROT_CFG_STRUC { // // TXRX_CSR4: Auto-Responder/ // -#ifdef RT_BIG_ENDIAN -typedef union _AUTO_RSP_CFG_STRUC { - struct { - UINT32 :24; - UINT32 AckCtsPsmBit:1; // Power bit value in conrtrol frame - UINT32 DualCTSEn:1; // Power bit value in conrtrol frame - UINT32 rsv:1; // Power bit value in conrtrol frame - UINT32 AutoResponderPreamble:1; // 0:long, 1:short preamble - UINT32 CTS40MRef:1; // Response CTS 40MHz duplicate mode - UINT32 CTS40MMode:1; // Response CTS 40MHz duplicate mode - UINT32 BACAckPolicyEnable:1; // 0:long, 1:short preamble - UINT32 AutoResponderEnable:1; - } field; - UINT32 word; -} AUTO_RSP_CFG_STRUC, *PAUTO_RSP_CFG_STRUC; -#else typedef union _AUTO_RSP_CFG_STRUC { struct { UINT32 AutoResponderEnable:1; @@ -1204,7 +713,6 @@ typedef union _AUTO_RSP_CFG_STRUC { } field; UINT32 word; } AUTO_RSP_CFG_STRUC, *PAUTO_RSP_CFG_STRUC; -#endif #define LEGACY_BASIC_RATE 0x1408 // TXRX_CSR5 0x3054 #define HT_BASIC_RATE 0x140c @@ -1237,15 +745,6 @@ typedef union _AUTO_RSP_CFG_STRUC { // // RX_STA_CNT0_STRUC: RX PLCP error count & RX CRC error count // -#ifdef RT_BIG_ENDIAN -typedef union _RX_STA_CNT0_STRUC { - struct { - USHORT PhyErr; - USHORT CrcErr; - } field; - UINT32 word; -} RX_STA_CNT0_STRUC, *PRX_STA_CNT0_STRUC; -#else typedef union _RX_STA_CNT0_STRUC { struct { USHORT CrcErr; @@ -1253,20 +752,10 @@ typedef union _RX_STA_CNT0_STRUC { } field; UINT32 word; } RX_STA_CNT0_STRUC, *PRX_STA_CNT0_STRUC; -#endif // // RX_STA_CNT1_STRUC: RX False CCA count & RX LONG frame count // -#ifdef RT_BIG_ENDIAN -typedef union _RX_STA_CNT1_STRUC { - struct { - USHORT PlcpErr; - USHORT FalseCca; - } field; - UINT32 word; -} RX_STA_CNT1_STRUC, *PRX_STA_CNT1_STRUC; -#else typedef union _RX_STA_CNT1_STRUC { struct { USHORT FalseCca; @@ -1274,20 +763,10 @@ typedef union _RX_STA_CNT1_STRUC { } field; UINT32 word; } RX_STA_CNT1_STRUC, *PRX_STA_CNT1_STRUC; -#endif // // RX_STA_CNT2_STRUC: // -#ifdef RT_BIG_ENDIAN -typedef union _RX_STA_CNT2_STRUC { - struct { - USHORT RxFifoOverflowCount; - USHORT RxDupliCount; - } field; - UINT32 word; -} RX_STA_CNT2_STRUC, *PRX_STA_CNT2_STRUC; -#else typedef union _RX_STA_CNT2_STRUC { struct { USHORT RxDupliCount; @@ -1295,20 +774,11 @@ typedef union _RX_STA_CNT2_STRUC { } field; UINT32 word; } RX_STA_CNT2_STRUC, *PRX_STA_CNT2_STRUC; -#endif + #define TX_STA_CNT0 0x170C // // // STA_CSR3: TX Beacon count // -#ifdef RT_BIG_ENDIAN -typedef union _TX_STA_CNT0_STRUC { - struct { - USHORT TxBeaconCount; - USHORT TxFailCount; - } field; - UINT32 word; -} TX_STA_CNT0_STRUC, *PTX_STA_CNT0_STRUC; -#else typedef union _TX_STA_CNT0_STRUC { struct { USHORT TxFailCount; @@ -1316,20 +786,11 @@ typedef union _TX_STA_CNT0_STRUC { } field; UINT32 word; } TX_STA_CNT0_STRUC, *PTX_STA_CNT0_STRUC; -#endif + #define TX_STA_CNT1 0x1710 // // // TX_STA_CNT1: TX tx count // -#ifdef RT_BIG_ENDIAN -typedef union _TX_STA_CNT1_STRUC { - struct { - USHORT TxRetransmit; - USHORT TxSuccess; - } field; - UINT32 word; -} TX_STA_CNT1_STRUC, *PTX_STA_CNT1_STRUC; -#else typedef union _TX_STA_CNT1_STRUC { struct { USHORT TxSuccess; @@ -1337,20 +798,11 @@ typedef union _TX_STA_CNT1_STRUC { } field; UINT32 word; } TX_STA_CNT1_STRUC, *PTX_STA_CNT1_STRUC; -#endif + #define TX_STA_CNT2 0x1714 // // // TX_STA_CNT2: TX tx count // -#ifdef RT_BIG_ENDIAN -typedef union _TX_STA_CNT2_STRUC { - struct { - USHORT TxUnderFlowCount; - USHORT TxZeroLenCount; - } field; - UINT32 word; -} TX_STA_CNT2_STRUC, *PTX_STA_CNT2_STRUC; -#else typedef union _TX_STA_CNT2_STRUC { struct { USHORT TxZeroLenCount; @@ -1358,28 +810,11 @@ typedef union _TX_STA_CNT2_STRUC { } field; UINT32 word; } TX_STA_CNT2_STRUC, *PTX_STA_CNT2_STRUC; -#endif + #define TX_STA_FIFO 0x1718 // // // TX_STA_FIFO_STRUC: TX Result for specific PID status fifo register // -#ifdef RT_BIG_ENDIAN -typedef union PACKED _TX_STA_FIFO_STRUC { - struct { - UINT32 Reserve:2; - UINT32 TxBF:1; // 3*3 - UINT32 SuccessRate:13; //include MCS, mode ,shortGI, BW settingSame format as TXWI Word 0 Bit 31-16. -// UINT32 SuccessRate:16; //include MCS, mode ,shortGI, BW settingSame format as TXWI Word 0 Bit 31-16. - UINT32 wcid:8; //wireless client index - UINT32 TxAckRequired:1; // ack required - UINT32 TxAggre:1; // Tx is aggregated - UINT32 TxSuccess:1; // Tx success. whether success or not - UINT32 PidType:4; - UINT32 bValid:1; // 1:This register contains a valid TX result - } field; - UINT32 word; -} TX_STA_FIFO_STRUC, *PTX_STA_FIFO_STRUC; -#else typedef union PACKED _TX_STA_FIFO_STRUC { struct { UINT32 bValid:1; // 1:This register contains a valid TX result @@ -1395,18 +830,9 @@ typedef union PACKED _TX_STA_FIFO_STRUC { } field; UINT32 word; } TX_STA_FIFO_STRUC, *PTX_STA_FIFO_STRUC; -#endif + // Debug counter #define TX_AGG_CNT 0x171c -#ifdef RT_BIG_ENDIAN -typedef union _TX_AGG_CNT_STRUC { - struct { - USHORT AggTxCount; - USHORT NonAggTxCount; - } field; - UINT32 word; -} TX_AGG_CNT_STRUC, *PTX_AGG_CNT_STRUC; -#else typedef union _TX_AGG_CNT_STRUC { struct { USHORT NonAggTxCount; @@ -1414,18 +840,9 @@ typedef union _TX_AGG_CNT_STRUC { } field; UINT32 word; } TX_AGG_CNT_STRUC, *PTX_AGG_CNT_STRUC; -#endif + // Debug counter #define TX_AGG_CNT0 0x1720 -#ifdef RT_BIG_ENDIAN -typedef union _TX_AGG_CNT0_STRUC { - struct { - USHORT AggSize2Count; - USHORT AggSize1Count; - } field; - UINT32 word; -} TX_AGG_CNT0_STRUC, *PTX_AGG_CNT0_STRUC; -#else typedef union _TX_AGG_CNT0_STRUC { struct { USHORT AggSize1Count; @@ -1433,18 +850,9 @@ typedef union _TX_AGG_CNT0_STRUC { } field; UINT32 word; } TX_AGG_CNT0_STRUC, *PTX_AGG_CNT0_STRUC; -#endif + // Debug counter #define TX_AGG_CNT1 0x1724 -#ifdef RT_BIG_ENDIAN -typedef union _TX_AGG_CNT1_STRUC { - struct { - USHORT AggSize4Count; - USHORT AggSize3Count; - } field; - UINT32 word; -} TX_AGG_CNT1_STRUC, *PTX_AGG_CNT1_STRUC; -#else typedef union _TX_AGG_CNT1_STRUC { struct { USHORT AggSize3Count; @@ -1452,17 +860,8 @@ typedef union _TX_AGG_CNT1_STRUC { } field; UINT32 word; } TX_AGG_CNT1_STRUC, *PTX_AGG_CNT1_STRUC; -#endif + #define TX_AGG_CNT2 0x1728 -#ifdef RT_BIG_ENDIAN -typedef union _TX_AGG_CNT2_STRUC { - struct { - USHORT AggSize6Count; - USHORT AggSize5Count; - } field; - UINT32 word; -} TX_AGG_CNT2_STRUC, *PTX_AGG_CNT2_STRUC; -#else typedef union _TX_AGG_CNT2_STRUC { struct { USHORT AggSize5Count; @@ -1470,18 +869,9 @@ typedef union _TX_AGG_CNT2_STRUC { } field; UINT32 word; } TX_AGG_CNT2_STRUC, *PTX_AGG_CNT2_STRUC; -#endif + // Debug counter #define TX_AGG_CNT3 0x172c -#ifdef RT_BIG_ENDIAN -typedef union _TX_AGG_CNT3_STRUC { - struct { - USHORT AggSize8Count; - USHORT AggSize7Count; - } field; - UINT32 word; -} TX_AGG_CNT3_STRUC, *PTX_AGG_CNT3_STRUC; -#else typedef union _TX_AGG_CNT3_STRUC { struct { USHORT AggSize7Count; @@ -1489,18 +879,9 @@ typedef union _TX_AGG_CNT3_STRUC { } field; UINT32 word; } TX_AGG_CNT3_STRUC, *PTX_AGG_CNT3_STRUC; -#endif + // Debug counter #define TX_AGG_CNT4 0x1730 -#ifdef RT_BIG_ENDIAN -typedef union _TX_AGG_CNT4_STRUC { - struct { - USHORT AggSize10Count; - USHORT AggSize9Count; - } field; - UINT32 word; -} TX_AGG_CNT4_STRUC, *PTX_AGG_CNT4_STRUC; -#else typedef union _TX_AGG_CNT4_STRUC { struct { USHORT AggSize9Count; @@ -1508,17 +889,8 @@ typedef union _TX_AGG_CNT4_STRUC { } field; UINT32 word; } TX_AGG_CNT4_STRUC, *PTX_AGG_CNT4_STRUC; -#endif + #define TX_AGG_CNT5 0x1734 -#ifdef RT_BIG_ENDIAN -typedef union _TX_AGG_CNT5_STRUC { - struct { - USHORT AggSize12Count; - USHORT AggSize11Count; - } field; - UINT32 word; -} TX_AGG_CNT5_STRUC, *PTX_AGG_CNT5_STRUC; -#else typedef union _TX_AGG_CNT5_STRUC { struct { USHORT AggSize11Count; @@ -1526,17 +898,8 @@ typedef union _TX_AGG_CNT5_STRUC { } field; UINT32 word; } TX_AGG_CNT5_STRUC, *PTX_AGG_CNT5_STRUC; -#endif + #define TX_AGG_CNT6 0x1738 -#ifdef RT_BIG_ENDIAN -typedef union _TX_AGG_CNT6_STRUC { - struct { - USHORT AggSize14Count; - USHORT AggSize13Count; - } field; - UINT32 word; -} TX_AGG_CNT6_STRUC, *PTX_AGG_CNT6_STRUC; -#else typedef union _TX_AGG_CNT6_STRUC { struct { USHORT AggSize13Count; @@ -1544,17 +907,8 @@ typedef union _TX_AGG_CNT6_STRUC { } field; UINT32 word; } TX_AGG_CNT6_STRUC, *PTX_AGG_CNT6_STRUC; -#endif + #define TX_AGG_CNT7 0x173c -#ifdef RT_BIG_ENDIAN -typedef union _TX_AGG_CNT7_STRUC { - struct { - USHORT AggSize16Count; - USHORT AggSize15Count; - } field; - UINT32 word; -} TX_AGG_CNT7_STRUC, *PTX_AGG_CNT7_STRUC; -#else typedef union _TX_AGG_CNT7_STRUC { struct { USHORT AggSize15Count; @@ -1562,17 +916,8 @@ typedef union _TX_AGG_CNT7_STRUC { } field; UINT32 word; } TX_AGG_CNT7_STRUC, *PTX_AGG_CNT7_STRUC; -#endif + #define MPDU_DENSITY_CNT 0x1740 -#ifdef RT_BIG_ENDIAN -typedef union _MPDU_DEN_CNT_STRUC { - struct { - USHORT RXZeroDelCount; //RX zero length delimiter count - USHORT TXZeroDelCount; //TX zero length delimiter count - } field; - UINT32 word; -} MPDU_DEN_CNT_STRUC, *PMPDU_DEN_CNT_STRUC; -#else typedef union _MPDU_DEN_CNT_STRUC { struct { USHORT TXZeroDelCount; //TX zero length delimiter count @@ -1580,7 +925,7 @@ typedef union _MPDU_DEN_CNT_STRUC { } field; UINT32 word; } MPDU_DEN_CNT_STRUC, *PMPDU_DEN_CNT_STRUC; -#endif + // // TXRX control registers - base address 0x3000 // @@ -1606,30 +951,6 @@ typedef union _MPDU_DEN_CNT_STRUC { #define SHAREDKEYTABLE 0 #define PAIRWISEKEYTABLE 1 - -#ifdef RT_BIG_ENDIAN -typedef union _SHAREDKEY_MODE_STRUC { - struct { - UINT32 :1; - UINT32 Bss1Key3CipherAlg:3; - UINT32 :1; - UINT32 Bss1Key2CipherAlg:3; - UINT32 :1; - UINT32 Bss1Key1CipherAlg:3; - UINT32 :1; - UINT32 Bss1Key0CipherAlg:3; - UINT32 :1; - UINT32 Bss0Key3CipherAlg:3; - UINT32 :1; - UINT32 Bss0Key2CipherAlg:3; - UINT32 :1; - UINT32 Bss0Key1CipherAlg:3; - UINT32 :1; - UINT32 Bss0Key0CipherAlg:3; - } field; - UINT32 word; -} SHAREDKEY_MODE_STRUC, *PSHAREDKEY_MODE_STRUC; -#else typedef union _SHAREDKEY_MODE_STRUC { struct { UINT32 Bss0Key0CipherAlg:3; @@ -1651,7 +972,7 @@ typedef union _SHAREDKEY_MODE_STRUC { } field; UINT32 word; } SHAREDKEY_MODE_STRUC, *PSHAREDKEY_MODE_STRUC; -#endif + // 64-entry for pairwise key table typedef struct _HW_WCID_ENTRY { // 8-byte per entry UCHAR Address[6]; @@ -1947,15 +1268,6 @@ typedef struct _HW_KEY_ENTRY { // 32-byte per entry //8.1.2 IV/EIV format : 2DW //8.1.3 RX attribute entry format : 1DW -#ifdef RT_BIG_ENDIAN -typedef struct _MAC_ATTRIBUTE_STRUC { - UINT32 rsv:22; - UINT32 RXWIUDF:3; - UINT32 BSSIDIdx:3; //multipleBSS index for the WCID - UINT32 PairKeyMode:3; - UINT32 KeyTab:1; // 0 for shared key table. 1 for pairwise key table -} MAC_ATTRIBUTE_STRUC, *PMAC_ATTRIBUTE_STRUC; -#else typedef struct _MAC_ATTRIBUTE_STRUC { UINT32 KeyTab:1; // 0 for shared key table. 1 for pairwise key table UINT32 PairKeyMode:3; @@ -1963,8 +1275,6 @@ typedef struct _MAC_ATTRIBUTE_STRUC { UINT32 RXWIUDF:3; UINT32 rsv:22; } MAC_ATTRIBUTE_STRUC, *PMAC_ATTRIBUTE_STRUC; -#endif - // ================================================================================= // TX / RX ring descriptor format @@ -1979,29 +1289,6 @@ typedef struct _MAC_ATTRIBUTE_STRUC { // // TX descriptor format, Tx ring, Mgmt Ring // -#ifdef RT_BIG_ENDIAN -typedef struct PACKED _TXD_STRUC { - // Word 0 - UINT32 SDPtr0; - // Word 1 - UINT32 DMADONE:1; - UINT32 LastSec0:1; - UINT32 SDLen0:14; - UINT32 Burst:1; - UINT32 LastSec1:1; - UINT32 SDLen1:14; - // Word 2 - UINT32 SDPtr1; - // Word 3 - UINT32 ICO:1; - UINT32 UCO:1; - UINT32 TCO:1; - UINT32 rsv:2; - UINT32 QSEL:2; // select on-chip FIFO ID for 2nd-stage output scheduler.0:MGMT, 1:HCCA 2:EDCA - UINT32 WIV:1; // Wireless Info Valid. 1 if Driver already fill WI, o if DMA needs to copy WI to correctposition - UINT32 rsv2:24; -} TXD_STRUC, *PTXD_STRUC; -#else typedef struct PACKED _TXD_STRUC { // Word 0 UINT32 SDPtr0; @@ -2023,8 +1310,6 @@ typedef struct PACKED _TXD_STRUC { UINT32 UCO:1; // UINT32 ICO:1; // } TXD_STRUC, *PTXD_STRUC; -#endif - // // TXD Wireless Information format for Tx ring and Mgmt Ring @@ -2032,41 +1317,6 @@ typedef struct PACKED _TXD_STRUC { //txop : for txop mode // 0:txop for the MPDU frame will be handles by ASIC by register // 1/2/3:the MPDU frame is send after PIFS/backoff/SIFS -#ifdef RT_BIG_ENDIAN -typedef struct PACKED _TXWI_STRUC { - // Word 0 - UINT32 PHYMODE:2; - UINT32 TxBF:1; // 3*3 - UINT32 rsv2:1; -// UINT32 rsv2:2; - UINT32 Ifs:1; // - UINT32 STBC:2; //channel bandwidth 20MHz or 40 MHz - UINT32 ShortGI:1; - UINT32 BW:1; //channel bandwidth 20MHz or 40 MHz - UINT32 MCS:7; - - UINT32 rsv:6; - UINT32 txop:2; //tx back off mode 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs only when previous frame exchange is successful. - UINT32 MpduDensity:3; - UINT32 AMPDU:1; - - UINT32 TS:1; - UINT32 CFACK:1; - UINT32 MIMOps:1; // the remote peer is in dynamic MIMO-PS mode - UINT32 FRAG:1; // 1 to inform TKIP engine this is a fragment. - // Word 1 - UINT32 PacketId:4; - UINT32 MPDUtotalByteCount:12; - UINT32 WirelessCliID:8; - UINT32 BAWinSize:6; - UINT32 NSEQ:1; - UINT32 ACK:1; - // Word 2 - UINT32 IV; - // Word 3 - UINT32 EIV; -} TXWI_STRUC, *PTXWI_STRUC; -#else typedef struct PACKED _TXWI_STRUC { // Word 0 UINT32 FRAG:1; // 1 to inform TKIP engine this is a fragment. @@ -2100,42 +1350,13 @@ typedef struct PACKED _TXWI_STRUC { //Word3 UINT32 EIV; } TXWI_STRUC, *PTXWI_STRUC; -#endif + // // Rx descriptor format, Rx Ring // // // RXWI wireless information format, in PBF. invisible in driver. // -#ifdef RT_BIG_ENDIAN -typedef struct PACKED _RXWI_STRUC { - // Word 0 - UINT32 TID:4; - UINT32 MPDUtotalByteCount:12; - UINT32 UDF:3; - UINT32 BSSID:3; - UINT32 KeyIndex:2; - UINT32 WirelessCliID:8; - // Word 1 - UINT32 PHYMODE:2; // 1: this RX frame is unicast to me - UINT32 rsv:3; - UINT32 STBC:2; - UINT32 ShortGI:1; - UINT32 BW:1; - UINT32 MCS:7; - UINT32 SEQUENCE:12; - UINT32 FRAG:4; - // Word 2 - UINT32 rsv1:8; - UINT32 RSSI2:8; - UINT32 RSSI1:8; - UINT32 RSSI0:8; - // Word 3 - UINT32 rsv2:16; - UINT32 SNR1:8; - UINT32 SNR0:8; -} RXWI_STRUC, *PRXWI_STRUC; -#else typedef struct PACKED _RXWI_STRUC { // Word 0 UINT32 WirelessCliID:8; @@ -2163,8 +1384,6 @@ typedef struct PACKED _RXWI_STRUC { UINT32 SNR1:8; UINT32 rsv2:16; } RXWI_STRUC, *PRXWI_STRUC; -#endif - // ================================================================================= // HOST-MCU communication data structure @@ -2173,17 +1392,6 @@ typedef struct PACKED _RXWI_STRUC { // // H2M_MAILBOX_CSR: Host-to-MCU Mailbox // -#ifdef RT_BIG_ENDIAN -typedef union _H2M_MAILBOX_STRUC { - struct { - UINT32 Owner:8; - UINT32 CmdToken:8; // 0xff tells MCU not to report CmdDoneInt after excuting the command - UINT32 HighByte:8; - UINT32 LowByte:8; - } field; - UINT32 word; -} H2M_MAILBOX_STRUC, *PH2M_MAILBOX_STRUC; -#else typedef union _H2M_MAILBOX_STRUC { struct { UINT32 LowByte:8; @@ -2193,22 +1401,10 @@ typedef union _H2M_MAILBOX_STRUC { } field; UINT32 word; } H2M_MAILBOX_STRUC, *PH2M_MAILBOX_STRUC; -#endif // // M2H_CMD_DONE_CSR: MCU-to-Host command complete indication // -#ifdef RT_BIG_ENDIAN -typedef union _M2H_CMD_DONE_STRUC { - struct { - UINT32 CmdToken3; - UINT32 CmdToken2; - UINT32 CmdToken1; - UINT32 CmdToken0; - } field; - UINT32 word; -} M2H_CMD_DONE_STRUC, *PM2H_CMD_DONE_STRUC; -#else typedef union _M2H_CMD_DONE_STRUC { struct { UINT32 CmdToken0; @@ -2218,22 +1414,10 @@ typedef union _M2H_CMD_DONE_STRUC { } field; UINT32 word; } M2H_CMD_DONE_STRUC, *PM2H_CMD_DONE_STRUC; -#endif - - // // MCU_LEDCS: MCU LED Control Setting. // -#ifdef RT_BIG_ENDIAN -typedef union _MCU_LEDCS_STRUC { - struct { - UCHAR Polarity:1; - UCHAR LedMode:7; - } field; - UCHAR word; -} MCU_LEDCS_STRUC, *PMCU_LEDCS_STRUC; -#else typedef union _MCU_LEDCS_STRUC { struct { UCHAR LedMode:7; @@ -2241,7 +1425,7 @@ typedef union _MCU_LEDCS_STRUC { } field; UCHAR word; } MCU_LEDCS_STRUC, *PMCU_LEDCS_STRUC; -#endif + // ================================================================================= // Register format // ================================================================================= @@ -2249,18 +1433,6 @@ typedef union _MCU_LEDCS_STRUC { //NAV_TIME_CFG :NAV -#ifdef RT_BIG_ENDIAN -typedef union _NAV_TIME_CFG_STRUC { - struct { - USHORT rsv:6; - USHORT ZeroSifs:1; // Applied zero SIFS timer after OFDM RX 0: disable - USHORT Eifs:9; // in unit of 1-us - UCHAR SlotTime; // in unit of 1-us - UCHAR Sifs; // in unit of 1-us - } field; - UINT32 word; -} NAV_TIME_CFG_STRUC, *PNAV_TIME_CFG_STRUC; -#else typedef union _NAV_TIME_CFG_STRUC { struct { UCHAR Sifs; // in unit of 1-us @@ -2271,44 +1443,10 @@ typedef union _NAV_TIME_CFG_STRUC { } field; UINT32 word; } NAV_TIME_CFG_STRUC, *PNAV_TIME_CFG_STRUC; -#endif - - - - // // RX_FILTR_CFG: /RX configuration register // -#ifdef RT_BIG_ENDIAN -typedef union RX_FILTR_CFG_STRUC { - struct { - UINT32 :15; - UINT32 DropRsvCntlType:1; - - UINT32 DropBAR:1; // - UINT32 DropBA:1; // - UINT32 DropPsPoll:1; // Drop Ps-Poll - UINT32 DropRts:1; // Drop Ps-Poll - - UINT32 DropCts:1; // Drop Ps-Poll - UINT32 DropAck:1; // Drop Ps-Poll - UINT32 DropCFEnd:1; // Drop Ps-Poll - UINT32 DropCFEndAck:1; // Drop Ps-Poll - - UINT32 DropDuplicate:1; // Drop duplicate frame - UINT32 DropBcast:1; // Drop broadcast frames - UINT32 DropMcast:1; // Drop multicast frames - UINT32 DropVerErr:1; // Drop version error frame - - UINT32 DropNotMyBSSID:1; // Drop fram ToDs bit is true - UINT32 DropNotToMe:1; // Drop not to me unicast frame - UINT32 DropPhyErr:1; // Drop physical error - UINT32 DropCRCErr:1; // Drop CRC error - } field; - UINT32 word; -} RX_FILTR_CFG_STRUC, *PRX_FILTR_CFG_STRUC; -#else typedef union _RX_FILTR_CFG_STRUC { struct { UINT32 DropCRCErr:1; // Drop CRC error @@ -2336,26 +1474,10 @@ typedef union _RX_FILTR_CFG_STRUC { } field; UINT32 word; } RX_FILTR_CFG_STRUC, *PRX_FILTR_CFG_STRUC; -#endif - - - // // PHY_CSR4: RF serial control register // -#ifdef RT_BIG_ENDIAN -typedef union _PHY_CSR4_STRUC { - struct { - UINT32 Busy:1; // 1: ASIC is busy execute RF programming. - UINT32 PLL_LD:1; // RF PLL_LD status - UINT32 IFSelect:1; // 1: select IF to program, 0: select RF to program - UINT32 NumberOfBits:5; // Number of bits used in RFRegValue (I:20, RFMD:22) - UINT32 RFRegValue:24; // Register value (include register id) serial out to RF/IF chip. - } field; - UINT32 word; -} PHY_CSR4_STRUC, *PPHY_CSR4_STRUC; -#else typedef union _PHY_CSR4_STRUC { struct { UINT32 RFRegValue:24; // Register value (include register id) serial out to RF/IF chip. @@ -2366,35 +1488,10 @@ typedef union _PHY_CSR4_STRUC { } field; UINT32 word; } PHY_CSR4_STRUC, *PPHY_CSR4_STRUC; -#endif - // // SEC_CSR5: shared key table security mode register // -#ifdef RT_BIG_ENDIAN -typedef union _SEC_CSR5_STRUC { - struct { - UINT32 :1; - UINT32 Bss3Key3CipherAlg:3; - UINT32 :1; - UINT32 Bss3Key2CipherAlg:3; - UINT32 :1; - UINT32 Bss3Key1CipherAlg:3; - UINT32 :1; - UINT32 Bss3Key0CipherAlg:3; - UINT32 :1; - UINT32 Bss2Key3CipherAlg:3; - UINT32 :1; - UINT32 Bss2Key2CipherAlg:3; - UINT32 :1; - UINT32 Bss2Key1CipherAlg:3; - UINT32 :1; - UINT32 Bss2Key0CipherAlg:3; - } field; - UINT32 word; -} SEC_CSR5_STRUC, *PSEC_CSR5_STRUC; -#else typedef union _SEC_CSR5_STRUC { struct { UINT32 Bss2Key0CipherAlg:3; @@ -2416,21 +1513,10 @@ typedef union _SEC_CSR5_STRUC { } field; UINT32 word; } SEC_CSR5_STRUC, *PSEC_CSR5_STRUC; -#endif - // // HOST_CMD_CSR: For HOST to interrupt embedded processor // -#ifdef RT_BIG_ENDIAN -typedef union _HOST_CMD_CSR_STRUC { - struct { - UINT32 Rsv:24; - UINT32 HostCommand:8; - } field; - UINT32 word; -} HOST_CMD_CSR_STRUC, *PHOST_CMD_CSR_STRUC; -#else typedef union _HOST_CMD_CSR_STRUC { struct { UINT32 HostCommand:8; @@ -2438,8 +1524,6 @@ typedef union _HOST_CMD_CSR_STRUC { } field; UINT32 word; } HOST_CMD_CSR_STRUC, *PHOST_CMD_CSR_STRUC; -#endif - // // AIFSN_CSR: AIFSN for each EDCA AC @@ -2450,21 +1534,6 @@ typedef union _HOST_CMD_CSR_STRUC { // // E2PROM_CSR: EEPROM control register // -#ifdef RT_BIG_ENDIAN -typedef union _E2PROM_CSR_STRUC { - struct { - UINT32 Rsvd:25; - UINT32 LoadStatus:1; // 1:loading, 0:done - UINT32 Type:1; // 1: 93C46, 0:93C66 - UINT32 EepromDO:1; - UINT32 EepromDI:1; - UINT32 EepromCS:1; - UINT32 EepromSK:1; - UINT32 Reload:1; // Reload EEPROM content, write one to reload, self-cleared. - } field; - UINT32 word; -} E2PROM_CSR_STRUC, *PE2PROM_CSR_STRUC; -#else typedef union _E2PROM_CSR_STRUC { struct { UINT32 Reload:1; // Reload EEPROM content, write one to reload, self-cleared. @@ -2478,8 +1547,6 @@ typedef union _E2PROM_CSR_STRUC { } field; UINT32 word; } E2PROM_CSR_STRUC, *PE2PROM_CSR_STRUC; -#endif - // ------------------------------------------------------------------- // E2PROM data layout @@ -2488,17 +1555,6 @@ typedef union _E2PROM_CSR_STRUC { // // EEPROM antenna select format // -#ifdef RT_BIG_ENDIAN -typedef union _EEPROM_ANTENNA_STRUC { - struct { - USHORT Rsv:4; - USHORT RfIcType:4; // see E2PROM document - USHORT TxPath:4; // 1: 1T, 2: 2T - USHORT RxPath:4; // 1: 1R, 2: 2R, 3: 3R - } field; - USHORT word; -} EEPROM_ANTENNA_STRUC, *PEEPROM_ANTENNA_STRUC; -#else typedef union _EEPROM_ANTENNA_STRUC { struct { USHORT RxPath:4; // 1: 1R, 2: 2R, 3: 3R @@ -2508,29 +1564,7 @@ typedef union _EEPROM_ANTENNA_STRUC { } field; USHORT word; } EEPROM_ANTENNA_STRUC, *PEEPROM_ANTENNA_STRUC; -#endif -#ifdef RT_BIG_ENDIAN -typedef union _EEPROM_NIC_CINFIG2_STRUC { - struct { - USHORT DACTestBit:1; // control if driver should patch the DAC issue - USHORT Rsv2:3; // must be 0 - USHORT AntDiversity:1; // Antenna diversity - USHORT Rsv1:1; // must be 0 - USHORT BW40MAvailForA:1; // 0:enable, 1:disable - USHORT BW40MAvailForG:1; // 0:enable, 1:disable - USHORT EnableWPSPBC:1; // WPS PBC Control bit - USHORT BW40MSidebandForA:1; - USHORT BW40MSidebandForG:1; - USHORT CardbusAcceleration:1; // !!! NOTE: 0 - enable, 1 - disable - USHORT ExternalLNAForA:1; // external LNA enable for 5G - USHORT ExternalLNAForG:1; // external LNA enable for 2.4G - USHORT DynamicTxAgcControl:1; // - USHORT HardwareRadioControl:1; // Whether RF is controlled by driver or HW. 1:enable hw control, 0:disable - } field; - USHORT word; -} EEPROM_NIC_CONFIG2_STRUC, *PEEPROM_NIC_CONFIG2_STRUC; -#else typedef union _EEPROM_NIC_CINFIG2_STRUC { struct { USHORT HardwareRadioControl:1; // 1:enable, 0:disable @@ -2550,20 +1584,10 @@ typedef union _EEPROM_NIC_CINFIG2_STRUC { } field; USHORT word; } EEPROM_NIC_CONFIG2_STRUC, *PEEPROM_NIC_CONFIG2_STRUC; -#endif // // TX_PWR Value valid range 0xFA(-6) ~ 0x24(36) // -#ifdef RT_BIG_ENDIAN -typedef union _EEPROM_TX_PWR_STRUC { - struct { - CHAR Byte1; // High Byte - CHAR Byte0; // Low Byte - } field; - USHORT word; -} EEPROM_TX_PWR_STRUC, *PEEPROM_TX_PWR_STRUC; -#else typedef union _EEPROM_TX_PWR_STRUC { struct { CHAR Byte0; // Low Byte @@ -2571,17 +1595,7 @@ typedef union _EEPROM_TX_PWR_STRUC { } field; USHORT word; } EEPROM_TX_PWR_STRUC, *PEEPROM_TX_PWR_STRUC; -#endif -#ifdef RT_BIG_ENDIAN -typedef union _EEPROM_VERSION_STRUC { - struct { - UCHAR Version; // High Byte - UCHAR FaeReleaseNumber; // Low Byte - } field; - USHORT word; -} EEPROM_VERSION_STRUC, *PEEPROM_VERSION_STRUC; -#else typedef union _EEPROM_VERSION_STRUC { struct { UCHAR FaeReleaseNumber; // Low Byte @@ -2589,25 +1603,7 @@ typedef union _EEPROM_VERSION_STRUC { } field; USHORT word; } EEPROM_VERSION_STRUC, *PEEPROM_VERSION_STRUC; -#endif -#ifdef RT_BIG_ENDIAN -typedef union _EEPROM_LED_STRUC { - struct { - USHORT Rsvd:3; // Reserved - USHORT LedMode:5; // Led mode. - USHORT PolarityGPIO_4:1; // Polarity GPIO#4 setting. - USHORT PolarityGPIO_3:1; // Polarity GPIO#3 setting. - USHORT PolarityGPIO_2:1; // Polarity GPIO#2 setting. - USHORT PolarityGPIO_1:1; // Polarity GPIO#1 setting. - USHORT PolarityGPIO_0:1; // Polarity GPIO#0 setting. - USHORT PolarityACT:1; // Polarity ACT setting. - USHORT PolarityRDY_A:1; // Polarity RDY_A setting. - USHORT PolarityRDY_G:1; // Polarity RDY_G setting. - } field; - USHORT word; -} EEPROM_LED_STRUC, *PEEPROM_LED_STRUC; -#else typedef union _EEPROM_LED_STRUC { struct { USHORT PolarityRDY_G:1; // Polarity RDY_G setting. @@ -2623,18 +1619,7 @@ typedef union _EEPROM_LED_STRUC { } field; USHORT word; } EEPROM_LED_STRUC, *PEEPROM_LED_STRUC; -#endif -#ifdef RT_BIG_ENDIAN -typedef union _EEPROM_TXPOWER_DELTA_STRUC { - struct { - UCHAR TxPowerEnable:1;// Enable - UCHAR Type:1; // 1: plus the delta value, 0: minus the delta value - UCHAR DeltaValue:6; // Tx Power dalta value (MAX=4) - } field; - UCHAR value; -} EEPROM_TXPOWER_DELTA_STRUC, *PEEPROM_TXPOWER_DELTA_STRUC; -#else typedef union _EEPROM_TXPOWER_DELTA_STRUC { struct { UCHAR DeltaValue:6; // Tx Power dalta value (MAX=4) @@ -2643,22 +1628,10 @@ typedef union _EEPROM_TXPOWER_DELTA_STRUC { } field; UCHAR value; } EEPROM_TXPOWER_DELTA_STRUC, *PEEPROM_TXPOWER_DELTA_STRUC; -#endif // // QOS_CSR0: TXOP holder address0 register // -#ifdef RT_BIG_ENDIAN -typedef union _QOS_CSR0_STRUC { - struct { - UCHAR Byte3; // MAC address byte 3 - UCHAR Byte2; // MAC address byte 2 - UCHAR Byte1; // MAC address byte 1 - UCHAR Byte0; // MAC address byte 0 - } field; - UINT32 word; -} QOS_CSR0_STRUC, *PQOS_CSR0_STRUC; -#else typedef union _QOS_CSR0_STRUC { struct { UCHAR Byte0; // MAC address byte 0 @@ -2668,22 +1641,10 @@ typedef union _QOS_CSR0_STRUC { } field; UINT32 word; } QOS_CSR0_STRUC, *PQOS_CSR0_STRUC; -#endif // // QOS_CSR1: TXOP holder address1 register // -#ifdef RT_BIG_ENDIAN -typedef union _QOS_CSR1_STRUC { - struct { - UCHAR Rsvd1; - UCHAR Rsvd0; - UCHAR Byte5; // MAC address byte 5 - UCHAR Byte4; // MAC address byte 4 - } field; - UINT32 word; -} QOS_CSR1_STRUC, *PQOS_CSR1_STRUC; -#else typedef union _QOS_CSR1_STRUC { struct { UCHAR Byte4; // MAC address byte 4 @@ -2693,22 +1654,8 @@ typedef union _QOS_CSR1_STRUC { } field; UINT32 word; } QOS_CSR1_STRUC, *PQOS_CSR1_STRUC; -#endif #define RF_CSR_CFG 0x500 -#ifdef RT_BIG_ENDIAN -typedef union _RF_CSR_CFG_STRUC { - struct { - UINT Rsvd1:14; // Reserved - UINT RF_CSR_KICK:1; // kick RF register read/write - UINT RF_CSR_WR:1; // 0: read 1: write - UINT Rsvd2:3; // Reserved - UINT TESTCSR_RFACC_REGNUM:5; // RF register ID - UINT RF_CSR_DATA:8; // DATA - } field; - UINT word; -} RF_CSR_CFG_STRUC, *PRF_CSR_CFG_STRUC; -#else typedef union _RF_CSR_CFG_STRUC { struct { UINT RF_CSR_DATA:8; // DATA @@ -2720,6 +1667,5 @@ typedef union _RF_CSR_CFG_STRUC { } field; UINT word; } RF_CSR_CFG_STRUC, *PRF_CSR_CFG_STRUC; -#endif #endif // __RT28XX_H__ diff --git a/drivers/staging/rt3070/rtmp.h b/drivers/staging/rt3070/rtmp.h index faaf29c1e1f9..598f49f72717 100644 --- a/drivers/staging/rt3070/rtmp.h +++ b/drivers/staging/rt3070/rtmp.h @@ -877,17 +877,10 @@ typedef struct _RTMP_DMABUF typedef union _HEADER_802_11_SEQ{ -#ifdef RT_BIG_ENDIAN - struct { - USHORT Sequence:12; - USHORT Frag:4; - } field; -#else struct { USHORT Frag:4; USHORT Sequence:12; } field; -#endif USHORT value; } HEADER_802_11_SEQ, *PHEADER_802_11_SEQ; @@ -1103,15 +1096,6 @@ typedef struct _ARCFOUR // MIMO Tx parameter, ShortGI, MCS, STBC, etc. these are fields in TXWI too. just copy to TXWI. typedef struct _RECEIVE_SETTING { -#ifdef RT_BIG_ENDIAN - USHORT MIMO:1; - USHORT OFDM:1; - USHORT rsv:3; - USHORT STBC:2; //SPACE - USHORT ShortGI:1; - USHORT Mode:2; //channel bandwidth 20MHz or 40 MHz - USHORT NumOfRX:2; // MIMO. WE HAVE 3R -#else USHORT NumOfRX:2; // MIMO. WE HAVE 3R USHORT Mode:2; //channel bandwidth 20MHz or 40 MHz USHORT ShortGI:1; @@ -1119,7 +1103,6 @@ typedef struct _RECEIVE_SETTING { USHORT rsv:3; USHORT OFDM:1; USHORT MIMO:1; -#endif } RECEIVE_SETTING, *PRECEIVE_SETTING; // Shared key data structure @@ -1455,21 +1438,6 @@ typedef struct _QUERYBA_TABLE{ } QUERYBA_TABLE, *PQUERYBA_TABLE; typedef union _BACAP_STRUC { -#ifdef RT_BIG_ENDIAN - struct { - UINT32 :4; - UINT32 b2040CoexistScanSup:1; //As Sta, support do 2040 coexistence scan for AP. As Ap, support monitor trigger event to check if can use BW 40MHz. - UINT32 bHtAdhoc:1; // adhoc can use ht rate. - UINT32 MMPSmode:2; // MIMO power save more, 0:static, 1:dynamic, 2:rsv, 3:mimo enable - UINT32 AmsduSize:1; // 0:3839, 1:7935 bytes. UINT MSDUSizeToBytes[] = { 3839, 7935}; - UINT32 AmsduEnable:1; //Enable AMSDU transmisstion - UINT32 MpduDensity:3; - UINT32 Policy:2; // 0: DELAY_BA 1:IMMED_BA (//BA Policy subfiled value in ADDBA frame) 2:BA-not use - UINT32 AutoBA:1; // automatically BA - UINT32 TxBAWinLimit:8; - UINT32 RxBAWinLimit:8; - } field; -#else struct { UINT32 RxBAWinLimit:8; UINT32 TxBAWinLimit:8; @@ -1483,7 +1451,6 @@ typedef union _BACAP_STRUC { UINT32 b2040CoexistScanSup:1; //As Sta, support do 2040 coexistence scan for AP. As Ap, support monitor trigger event to check if can use BW 40MHz. UINT32 :4; } field; -#endif UINT32 word; } BACAP_STRUC, *PBACAP_STRUC; #endif // DOT11_N_SUPPORT // @@ -1512,21 +1479,6 @@ typedef struct _IOT_STRUC { // This is the registry setting for 802.11n transmit setting. Used in advanced page. typedef union _REG_TRANSMIT_SETTING { -#ifdef RT_BIG_ENDIAN - struct { - UINT32 rsv:13; - UINT32 EXTCHA:2; - UINT32 HTMODE:1; - UINT32 TRANSNO:2; - UINT32 STBC:1; //SPACE - UINT32 ShortGI:1; - UINT32 BW:1; //channel bandwidth 20MHz or 40 MHz - UINT32 TxBF:1; // 3*3 - UINT32 rsv0:10; - //UINT32 MCS:7; // MCS - //UINT32 PhyMode:4; - } field; -#else struct { //UINT32 PhyMode:4; //UINT32 MCS:7; // MCS @@ -1540,26 +1492,16 @@ typedef union _REG_TRANSMIT_SETTING { UINT32 EXTCHA:2; UINT32 rsv:13; } field; -#endif UINT32 word; } REG_TRANSMIT_SETTING, *PREG_TRANSMIT_SETTING; typedef union _DESIRED_TRANSMIT_SETTING { -#ifdef RT_BIG_ENDIAN - struct { - USHORT rsv:3; - USHORT FixedTxMode:2; // If MCS isn't AUTO, fix rate in CCK, OFDM or HT mode. - USHORT PhyMode:4; - USHORT MCS:7; // MCS - } field; -#else struct { USHORT MCS:7; // MCS USHORT PhyMode:4; USHORT FixedTxMode:2; // If MCS isn't AUTO, fix rate in CCK, OFDM or HT mode. USHORT rsv:3; } field; -#endif USHORT word; } DESIRED_TRANSMIT_SETTING, *PDESIRED_TRANSMIT_SETTING; @@ -3072,244 +3014,6 @@ typedef struct _TX_BLK_ //------------------------------------------------------------------------------------------ - - -#ifdef RT_BIG_ENDIAN -static inline VOID WriteBackToDescriptor( - IN PUCHAR Dest, - IN PUCHAR Src, - IN BOOLEAN DoEncrypt, - IN ULONG DescriptorType) -{ - UINT32 *p1, *p2; - - p1 = ((UINT32 *)Dest); - p2 = ((UINT32 *)Src); - - *p1 = *p2; - *(p1+2) = *(p2+2); - *(p1+3) = *(p2+3); - *(p1+1) = *(p2+1); // Word 1; this must be written back last -} - -/* - ======================================================================== - - Routine Description: - Endian conversion of Tx/Rx descriptor . - - Arguments: - pAd Pointer to our adapter - pData Pointer to Tx/Rx descriptor - DescriptorType Direction of the frame - - Return Value: - None - - Note: - Call this function when read or update descriptor - ======================================================================== -*/ -static inline VOID RTMPWIEndianChange( - IN PUCHAR pData, - IN ULONG DescriptorType) -{ - int size; - int i; - - size = ((DescriptorType == TYPE_TXWI) ? TXWI_SIZE : RXWI_SIZE); - - if(DescriptorType == TYPE_TXWI) - { - *((UINT32 *)(pData)) = SWAP32(*((UINT32 *)(pData))); // Byte 0~3 - *((UINT32 *)(pData + 4)) = SWAP32(*((UINT32 *)(pData+4))); // Byte 4~7 - } - else - { - for(i=0; i < size/4 ; i++) - *(((UINT32 *)pData) +i) = SWAP32(*(((UINT32 *)pData)+i)); - } -} - -/* - ======================================================================== - - Routine Description: - Endian conversion of Tx/Rx descriptor . - - Arguments: - pAd Pointer to our adapter - pData Pointer to Tx/Rx descriptor - DescriptorType Direction of the frame - - Return Value: - None - - Note: - Call this function when read or update descriptor - ======================================================================== -*/ - -#ifdef RT2870 -static inline VOID RTMPDescriptorEndianChange( - IN PUCHAR pData, - IN ULONG DescriptorType) -{ - *((UINT32 *)(pData)) = SWAP32(*((UINT32 *)(pData))); -} -#endif // RT2870 // -/* - ======================================================================== - - Routine Description: - Endian conversion of all kinds of 802.11 frames . - - Arguments: - pAd Pointer to our adapter - pData Pointer to the 802.11 frame structure - Dir Direction of the frame - FromRxDoneInt Caller is from RxDone interrupt - - Return Value: - None - - Note: - Call this function when read or update buffer data - ======================================================================== -*/ -static inline VOID RTMPFrameEndianChange( - IN PRTMP_ADAPTER pAd, - IN PUCHAR pData, - IN ULONG Dir, - IN BOOLEAN FromRxDoneInt) -{ - PHEADER_802_11 pFrame; - PUCHAR pMacHdr; - - // swab 16 bit fields - Frame Control field - if(Dir == DIR_READ) - { - *(USHORT *)pData = SWAP16(*(USHORT *)pData); - } - - pFrame = (PHEADER_802_11) pData; - pMacHdr = (PUCHAR) pFrame; - - // swab 16 bit fields - Duration/ID field - *(USHORT *)(pMacHdr + 2) = SWAP16(*(USHORT *)(pMacHdr + 2)); - - // swab 16 bit fields - Sequence Control field - *(USHORT *)(pMacHdr + 22) = SWAP16(*(USHORT *)(pMacHdr + 22)); - - if(pFrame->FC.Type == BTYPE_MGMT) - { - switch(pFrame->FC.SubType) - { - case SUBTYPE_ASSOC_REQ: - case SUBTYPE_REASSOC_REQ: - // swab 16 bit fields - CapabilityInfo field - pMacHdr += sizeof(HEADER_802_11); - *(USHORT *)pMacHdr = SWAP16(*(USHORT *)pMacHdr); - - // swab 16 bit fields - Listen Interval field - pMacHdr += 2; - *(USHORT *)pMacHdr = SWAP16(*(USHORT *)pMacHdr); - break; - - case SUBTYPE_ASSOC_RSP: - case SUBTYPE_REASSOC_RSP: - // swab 16 bit fields - CapabilityInfo field - pMacHdr += sizeof(HEADER_802_11); - *(USHORT *)pMacHdr = SWAP16(*(USHORT *)pMacHdr); - - // swab 16 bit fields - Status Code field - pMacHdr += 2; - *(USHORT *)pMacHdr = SWAP16(*(USHORT *)pMacHdr); - - // swab 16 bit fields - AID field - pMacHdr += 2; - *(USHORT *)pMacHdr = SWAP16(*(USHORT *)pMacHdr); - break; - - case SUBTYPE_AUTH: - // If from APHandleRxDoneInterrupt routine, it is still a encrypt format. - // The convertion is delayed to RTMPHandleDecryptionDoneInterrupt. - if(!FromRxDoneInt && pFrame->FC.Wep == 1) - break; - else - { - // swab 16 bit fields - Auth Alg No. field - pMacHdr += sizeof(HEADER_802_11); - *(USHORT *)pMacHdr = SWAP16(*(USHORT *)pMacHdr); - - // swab 16 bit fields - Auth Seq No. field - pMacHdr += 2; - *(USHORT *)pMacHdr = SWAP16(*(USHORT *)pMacHdr); - - // swab 16 bit fields - Status Code field - pMacHdr += 2; - *(USHORT *)pMacHdr = SWAP16(*(USHORT *)pMacHdr); - } - break; - - case SUBTYPE_BEACON: - case SUBTYPE_PROBE_RSP: - // swab 16 bit fields - BeaconInterval field - pMacHdr += (sizeof(HEADER_802_11) + TIMESTAMP_LEN); - *(USHORT *)pMacHdr = SWAP16(*(USHORT *)pMacHdr); - - // swab 16 bit fields - CapabilityInfo field - pMacHdr += sizeof(USHORT); - *(USHORT *)pMacHdr = SWAP16(*(USHORT *)pMacHdr); - break; - - case SUBTYPE_DEAUTH: - case SUBTYPE_DISASSOC: - // swab 16 bit fields - Reason code field - pMacHdr += sizeof(HEADER_802_11); - *(USHORT *)pMacHdr = SWAP16(*(USHORT *)pMacHdr); - break; - } - } - else if( pFrame->FC.Type == BTYPE_DATA ) - { - } - else if(pFrame->FC.Type == BTYPE_CNTL) - { - switch(pFrame->FC.SubType) - { - case SUBTYPE_BLOCK_ACK_REQ: - { - PFRAME_BA_REQ pBAReq = (PFRAME_BA_REQ)pFrame; - *(USHORT *)(&pBAReq->BARControl) = SWAP16(*(USHORT *)(&pBAReq->BARControl)); - pBAReq->BAStartingSeq.word = SWAP16(pBAReq->BAStartingSeq.word); - } - break; - case SUBTYPE_BLOCK_ACK: - // For Block Ack packet, the HT_CONTROL field is in the same offset with Addr3 - *(UINT32 *)(&pFrame->Addr3[0]) = SWAP32(*(UINT32 *)(&pFrame->Addr3[0])); - break; - - case SUBTYPE_ACK: - //For ACK packet, the HT_CONTROL field is in the same offset with Addr2 - *(UINT32 *)(&pFrame->Addr2[0])= SWAP32(*(UINT32 *)(&pFrame->Addr2[0])); - break; - } - } - else - { - DBGPRINT(RT_DEBUG_ERROR,("Invalid Frame Type!!!\n")); - } - - // swab 16 bit fields - Frame Control - if(Dir == DIR_WRITE) - { - *(USHORT *)pData = SWAP16(*(USHORT *)pData); - } -} -#endif // RT_BIG_ENDIAN // - - static inline VOID ConvertMulticastIP2MAC( IN PUCHAR pIpAddr, IN PUCHAR *ppMacAddr, diff --git a/drivers/staging/rt3070/rtmp_def.h b/drivers/staging/rt3070/rtmp_def.h index 8e01b6e37f9f..60827c9fbab8 100644 --- a/drivers/staging/rt3070/rtmp_def.h +++ b/drivers/staging/rt3070/rtmp_def.h @@ -1276,17 +1276,6 @@ #define OPMODE_AP 1 //#define OPMODE_L3_BRG 2 // as AP and STA at the same time -#ifdef RT_BIG_ENDIAN -#define DIR_READ 0 -#define DIR_WRITE 1 -#define TYPE_TXD 0 -#define TYPE_RXD 1 -#define TYPE_TXINFO 0 -#define TYPE_RXINFO 1 -#define TYPE_TXWI 0 -#define TYPE_RXWI 1 -#endif - // ========================= AP rtmp_def.h =========================== // value domain for pAd->EventTab.Log[].Event #define EVENT_RESET_ACCESS_POINT 0 // Log = "hh:mm:ss Restart Access Point" @@ -1467,23 +1456,6 @@ (UINT64)(((UINT64)(x) & (UINT64) 0x00ff000000000000ULL) >> 40) | \ (UINT64)(((UINT64)(x) & (UINT64) 0xff00000000000000ULL) >> 56) )) -#ifdef RT_BIG_ENDIAN - -#define cpu2le64(x) SWAP64((x)) -#define le2cpu64(x) SWAP64((x)) -#define cpu2le32(x) SWAP32((x)) -#define le2cpu32(x) SWAP32((x)) -#define cpu2le16(x) SWAP16((x)) -#define le2cpu16(x) SWAP16((x)) -#define cpu2be64(x) ((UINT64)(x)) -#define be2cpu64(x) ((UINT64)(x)) -#define cpu2be32(x) ((UINT32)(x)) -#define be2cpu32(x) ((UINT32)(x)) -#define cpu2be16(x) ((UINT16)(x)) -#define be2cpu16(x) ((UINT16)(x)) - -#else // Little_Endian - #define cpu2le64(x) ((UINT64)(x)) #define le2cpu64(x) ((UINT64)(x)) #define cpu2le32(x) ((UINT32)(x)) @@ -1497,8 +1469,6 @@ #define cpu2be16(x) SWAP16((x)) #define be2cpu16(x) SWAP16((x)) -#endif // RT_BIG_ENDIAN - #endif // __RTMP_DEF_H__ diff --git a/drivers/staging/rt3070/spectrum.h b/drivers/staging/rt3070/spectrum.h index 94cfa5b174fc..95e0b0ebfe9b 100644 --- a/drivers/staging/rt3070/spectrum.h +++ b/drivers/staging/rt3070/spectrum.h @@ -46,16 +46,6 @@ typedef struct PACKED _CH_SW_ANN_INFO typedef union PACKED _MEASURE_REQ_MODE { -#ifdef RT_BIG_ENDIAN - struct PACKED - { - UINT8 Rev1:4; - UINT8 Report:1; - UINT8 Request:1; - UINT8 Enable:1; - UINT8 Rev0:1; - } field; -#else struct PACKED { UINT8 Rev0:1; @@ -64,7 +54,6 @@ typedef union PACKED _MEASURE_REQ_MODE UINT8 Report:1; UINT8 Rev1:4; } field; -#endif // RT_BIG_ENDIAN // UINT8 word; } MEASURE_REQ_MODE, *PMEASURE_REQ_MODE; @@ -85,17 +74,6 @@ typedef struct PACKED _MEASURE_REQ_INFO typedef union PACKED _MEASURE_BASIC_REPORT_MAP { -#ifdef RT_BIG_ENDIAN - struct PACKED - { - UINT8 Rev:3; - UINT8 Unmeasure:1; - UINT8 Radar:1; - UINT8 UnidentifiedSignal:1; - UINT8 OfdmPreamble:1; - UINT8 BSS:1; - } field; -#else struct PACKED { UINT8 BSS:1; @@ -105,7 +83,6 @@ typedef union PACKED _MEASURE_BASIC_REPORT_MAP UINT8 Unmeasure:1; UINT8 Rev:3; } field; -#endif // RT_BIG_ENDIAN // UINT8 word; } MEASURE_BASIC_REPORT_MAP, *PMEASURE_BASIC_REPORT_MAP; @@ -137,17 +114,10 @@ typedef union PACKED _MEASURE_REPORT_MODE { struct PACKED { -#ifdef RT_BIG_ENDIAN - UINT8 Rev:5; - UINT8 Refused:1; - UINT8 Incapable:1; - UINT8 Late:1; -#else UINT8 Late:1; UINT8 Incapable:1; UINT8 Refused:1; UINT8 Rev:5; -#endif // RT_BIG_ENDIAN // } field; UINT8 word; } MEASURE_REPORT_MODE, *PMEASURE_REPORT_MODE; diff --git a/drivers/staging/rt3070/sta/assoc.c b/drivers/staging/rt3070/sta/assoc.c index f041d7edeb61..1891a7a50e04 100644 --- a/drivers/staging/rt3070/sta/assoc.c +++ b/drivers/staging/rt3070/sta/assoc.c @@ -360,28 +360,11 @@ VOID MlmeAssocReqAction( } else { -#ifdef RT_BIG_ENDIAN - HT_CAPABILITY_IE HtCapabilityTmp; -#endif - -#ifndef RT_BIG_ENDIAN MakeOutgoingFrame(pOutBuffer + FrameLen, &TmpLen, 1, &HtCapIe, 1, &pAd->MlmeAux.HtCapabilityLen, pAd->MlmeAux.HtCapabilityLen, &pAd->MlmeAux.HtCapability, END_OF_ARGS); -#else - NdisZeroMemory(&HtCapabilityTmp, sizeof(HT_CAPABILITY_IE)); - NdisMoveMemory(&HtCapabilityTmp, &pAd->MlmeAux.HtCapability, pAd->MlmeAux.HtCapabilityLen); - *(USHORT *)(&HtCapabilityTmp.HtCapInfo) = SWAP16(*(USHORT *)(&HtCapabilityTmp.HtCapInfo)); - *(USHORT *)(&HtCapabilityTmp.ExtHtCapInfo) = SWAP16(*(USHORT *)(&HtCapabilityTmp.ExtHtCapInfo)); - - MakeOutgoingFrame(pOutBuffer + FrameLen, &TmpLen, - 1, &HtCapIe, - 1, &pAd->MlmeAux.HtCapabilityLen, - pAd->MlmeAux.HtCapabilityLen,&HtCapabilityTmp, - END_OF_ARGS); -#endif } FrameLen += TmpLen; } diff --git a/drivers/staging/rt3070/sta/connect.c b/drivers/staging/rt3070/sta/connect.c index 66f28dec6dd3..c1224e49ad79 100644 --- a/drivers/staging/rt3070/sta/connect.c +++ b/drivers/staging/rt3070/sta/connect.c @@ -2484,16 +2484,10 @@ ULONG MakeIbssBeacon( ULONG TmpLen; UCHAR HtLen, HtLen1; -#ifdef RT_BIG_ENDIAN - HT_CAPABILITY_IE HtCapabilityTmp; - ADD_HT_INFO_IE addHTInfoTmp; - USHORT b2lTmp, b2lTmp2; -#endif - // add HT Capability IE HtLen = sizeof(pAd->CommonCfg.HtCapability); HtLen1 = sizeof(pAd->CommonCfg.AddHTInfo); -#ifndef RT_BIG_ENDIAN + MakeOutgoingFrame(pBeaconFrame+FrameLen, &TmpLen, 1, &HtCapIe, 1, &HtLen, @@ -2502,24 +2496,7 @@ ULONG MakeIbssBeacon( 1, &HtLen1, HtLen1, &pAd->CommonCfg.AddHTInfo, END_OF_ARGS); -#else - NdisMoveMemory(&HtCapabilityTmp, &pAd->CommonCfg.HtCapability, HtLen); - *(USHORT *)(&HtCapabilityTmp.HtCapInfo) = SWAP16(*(USHORT *)(&HtCapabilityTmp.HtCapInfo)); - *(USHORT *)(&HtCapabilityTmp.ExtHtCapInfo) = SWAP16(*(USHORT *)(&HtCapabilityTmp.ExtHtCapInfo)); - NdisMoveMemory(&addHTInfoTmp, &pAd->CommonCfg.AddHTInfo, HtLen1); - *(USHORT *)(&addHTInfoTmp.AddHtInfo2) = SWAP16(*(USHORT *)(&addHTInfoTmp.AddHtInfo2)); - *(USHORT *)(&addHTInfoTmp.AddHtInfo3) = SWAP16(*(USHORT *)(&addHTInfoTmp.AddHtInfo3)); - - MakeOutgoingFrame(pBeaconFrame+FrameLen, &TmpLen, - 1, &HtCapIe, - 1, &HtLen, - HtLen, &HtCapabilityTmp, - 1, &AddHtInfoIe, - 1, &HtLen1, - HtLen1, &addHTInfoTmp, - END_OF_ARGS); -#endif FrameLen += TmpLen; } #endif // DOT11_N_SUPPORT // @@ -2539,11 +2516,6 @@ ULONG MakeIbssBeacon( PID_MGMT, PID_BEACON, RATE_1, IFS_HTTXOP, FALSE, &Transmit); } -#ifdef RT_BIG_ENDIAN - RTMPFrameEndianChange(pAd, pBeaconFrame, DIR_WRITE, FALSE); - RTMPWIEndianChange((PUCHAR)pTxWI, TYPE_TXWI); -#endif - DBGPRINT(RT_DEBUG_TRACE, ("MakeIbssBeacon (len=%ld), SupRateLen=%d, ExtRateLen=%d, Channel=%d, PhyMode=%d\n", FrameLen, SupRateLen, ExtRateLen, pAd->CommonCfg.Channel, pAd->CommonCfg.PhyMode)); return FrameLen; diff --git a/drivers/staging/rt3070/sta/rtmp_data.c b/drivers/staging/rt3070/sta/rtmp_data.c index 175be8144c3a..15d7084190e3 100644 --- a/drivers/staging/rt3070/sta/rtmp_data.c +++ b/drivers/staging/rt3070/sta/rtmp_data.c @@ -709,11 +709,6 @@ BOOLEAN STARxDoneInterruptHandle( pRxWI = (PRXWI_STRUC) pData; pHeader = (PHEADER_802_11) (pData+RXWI_SIZE) ; -#ifdef RT_BIG_ENDIAN - RTMPFrameEndianChange(pAd, (PUCHAR)pHeader, DIR_READ, TRUE); - RTMPWIEndianChange((PUCHAR)pRxWI, TYPE_RXWI); -#endif - // build RxCell RxCell.pRxWI = pRxWI; RxCell.pHeader = pHeader; diff --git a/drivers/staging/rt3070/wpa.h b/drivers/staging/rt3070/wpa.h index 88c7c8bf3fcd..7006e389e323 100644 --- a/drivers/staging/rt3070/wpa.h +++ b/drivers/staging/rt3070/wpa.h @@ -149,19 +149,6 @@ // EAPOL Key Information definition within Key descriptor format typedef struct PACKED _KEY_INFO { -#ifdef RT_BIG_ENDIAN - UCHAR KeyAck:1; - UCHAR Install:1; - UCHAR KeyIndex:2; - UCHAR KeyType:1; - UCHAR KeyDescVer:3; - UCHAR Rsvd:3; - UCHAR EKD_DL:1; // EKD for AP; DL for STA - UCHAR Request:1; - UCHAR Error:1; - UCHAR Secure:1; - UCHAR KeyMic:1; -#else UCHAR KeyMic:1; UCHAR Secure:1; UCHAR Error:1; @@ -173,7 +160,6 @@ typedef struct PACKED _KEY_INFO UCHAR KeyIndex:2; UCHAR Install:1; UCHAR KeyAck:1; -#endif } KEY_INFO, *PKEY_INFO; // EAPOL Key descriptor format @@ -203,17 +189,10 @@ typedef struct PACKED _EAPOL_PACKET //802.11i D10 page 83 typedef struct PACKED _GTK_ENCAP { -#ifndef RT_BIG_ENDIAN UCHAR Kid:2; UCHAR tx:1; UCHAR rsv:5; UCHAR rsv1; -#else - UCHAR rsv:5; - UCHAR tx:1; - UCHAR Kid:2; - UCHAR rsv1; -#endif UCHAR GTK[TKIP_GTK_LENGTH]; } GTK_ENCAP, *PGTK_ENCAP; @@ -257,19 +236,11 @@ typedef struct PACKED _RSNIE_AUTH { typedef union PACKED _RSN_CAPABILITIES { struct PACKED { -#ifdef RT_BIG_ENDIAN - USHORT Rsvd:10; - USHORT GTKSA_R_Counter:2; - USHORT PTKSA_R_Counter:2; - USHORT No_Pairwise:1; - USHORT PreAuth:1; -#else USHORT PreAuth:1; USHORT No_Pairwise:1; USHORT PTKSA_R_Counter:2; USHORT GTKSA_R_Counter:2; USHORT Rsvd:10; -#endif } field; USHORT word; } RSN_CAPABILITIES, *PRSN_CAPABILITIES; |