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authorStephen Boyd <sboyd@codeaurora.org>2013-07-24 11:37:28 -0700
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2013-07-26 16:13:29 -0700
commit4a5662d6a6412dabe0b5518bec111e17babbba05 (patch)
treebd8c8bb7a169052f3fed6af81790e8efedd48c19 /drivers/tty/serial/msm_serial.h
parentpci_ids.h: remove PCI_VENDOR_ID_ADDIDATA_OLD and PCI_DEVICE_ID_ADDIDATA_APCI7800 (diff)
downloadlinux-dev-4a5662d6a6412dabe0b5518bec111e17babbba05.tar.xz
linux-dev-4a5662d6a6412dabe0b5518bec111e17babbba05.zip
msm_serial: Fix NUL byte output on UARTDM
UARTDM serial devices require us to wait for the entire TX fifo to drain before we can change the contents of the NCF_TX register. Furthermore, if we write any characters to the TX fifo within the same clock cycle of changing the NCF_TX register the NCF_TX register won't latch properly. To fix these issues we should read back the NCF_TX register to delay any TX fifo accesses by a clock cycle and we should wait for the TX fifo to drain (instead of just waiting for the fifo to be ready to receive more characters). Failure to do so leads to random NUL bytes interspersed in the output. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: David Brown <davidb@codeaurora.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/tty/serial/msm_serial.h')
-rw-r--r--drivers/tty/serial/msm_serial.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/tty/serial/msm_serial.h b/drivers/tty/serial/msm_serial.h
index e4acef5de77e..15c186ecbd9e 100644
--- a/drivers/tty/serial/msm_serial.h
+++ b/drivers/tty/serial/msm_serial.h
@@ -71,6 +71,7 @@
#define UART_CR_CMD_RESET_RFR (14 << 4)
#define UART_CR_CMD_PROTECTION_EN (16 << 4)
#define UART_CR_CMD_STALE_EVENT_ENABLE (80 << 4)
+#define UART_CR_CMD_RESET_TX_READY (3 << 8)
#define UART_CR_TX_DISABLE (1 << 3)
#define UART_CR_TX_ENABLE (1 << 2)
#define UART_CR_RX_DISABLE (1 << 1)