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| author |   Pavel Machek <pavel@ucw.cz> | 2014-12-11 22:44:26 +0100 |
|---|---|---|
| committer |   Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2015-01-09 14:10:46 -0800 |
| commit | fbf7ebe4d9faf2225d15edb9ebc66bf99800776a (patch) | |
| tree | 05a1609e472b6c0c99bbcff4720f0a5c892d5c83 /drivers/tty/serial/omap-serial.c | |
| parent | tty: serial: 8250: omap: add ttySx console if the user didn't (diff) | |
| download | linux-dev-fbf7ebe4d9faf2225d15edb9ebc66bf99800776a.tar.xz linux-dev-fbf7ebe4d9faf2225d15edb9ebc66bf99800776a.zip | |
trivial fixes for omap-serial
Trivial fixes for omap-serial.
Signed-off-by: Pavel Machek <pavel@ucw.cz>
index 18c30ca..f43ed2c 100644
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/tty/serial/omap-serial.c')
| -rw-r--r-- | drivers/tty/serial/omap-serial.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c index 2e1073da6719..b1cf9a3b673a 100644 --- a/drivers/tty/serial/omap-serial.c +++ b/drivers/tty/serial/omap-serial.c @@ -63,7 +63,7 @@ #define UART_ERRATA_i202_MDR1_ACCESS BIT(0) #define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1) -#define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/ +#define DEFAULT_CLK_SPEED 48000000 /* 48Mhz */ /* SCR register bitmasks */ #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) @@ -93,7 +93,7 @@ /* WER = 0x7F * Enable module level wakeup in WER reg */ -#define OMAP_UART_WER_MOD_WKUP 0X7F +#define OMAP_UART_WER_MOD_WKUP 0x7F /* Enable XON/XOFF flow control on output */ #define OMAP_UART_SW_TX 0x08 @@ -114,7 +114,7 @@ struct uart_omap_dma { dma_addr_t tx_buf_dma_phys; unsigned int uart_base; /* - * Buffer for rx dma.It is not required for tx because the buffer + * Buffer for rx dma. It is not required for tx because the buffer * comes from port structure. */ unsigned char *rx_buf; @@ -151,7 +151,7 @@ struct uart_omap_port { int use_dma; /* * Some bits in registers are cleared on a read, so they must - * be saved whenever the register is read but the bits will not + * be saved whenever the register is read, but the bits will not * be immediately processed. */ unsigned int lsr_break_flag; |