diff options
| author |   Douglas Anderson <dianders@chromium.org> | 2022-08-02 13:23:09 -0700 |
|---|---|---|
| committer |   Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2022-08-03 08:23:35 +0200 |
| commit | 0fec518018cc5ceffa706370b6e3acbbb1e3c798 (patch) | |
| tree | 5309aaf2dc23a1d35fc884723cc8824974ed5fc2 /drivers/tty | |
| parent | tty: amiserial: Fix comment typo (diff) | |
| download | linux-dev-0fec518018cc5ceffa706370b6e3acbbb1e3c798.tar.xz linux-dev-0fec518018cc5ceffa706370b6e3acbbb1e3c798.zip | |
tty: serial: qcom-geni-serial: Fix %lu -> %u in print statements
When we multiply an unsigned int by a u32 we still end up with an
unsigned int. That means we should specify "%u" not "%lu" in the
format code.
NOTE: this fix was chosen instead of somehow promoting the value to
"unsigned long" since the max baud rate from the earlier call to
uart_get_baud_rate() is 4000000 and the max sampling rate is 32.
4000000 * 32 = 0x07a12000, not even close to overflowing 32-bits.
Fixes: c474c775716e ("tty: serial: qcom-geni-serial: Fix get_clk_div_rate() which otherwise could return a sub-optimal clock rate.")
Reported-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20220802132250.1.Iea061e14157a17e114dbe2eca764568a02d6b889@changeid
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/tty')
| -rw-r--r-- | drivers/tty/serial/qcom_geni_serial.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c index f754619451dc..f7c1f1807040 100644 --- a/drivers/tty/serial/qcom_geni_serial.c +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -1033,12 +1033,12 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport, sampling_rate, &clk_div); if (!clk_rate) { dev_err(port->se.dev, - "Couldn't find suitable clock rate for %lu\n", + "Couldn't find suitable clock rate for %u\n", baud * sampling_rate); goto out_restart_rx; } - dev_dbg(port->se.dev, "desired_rate-%lu, clk_rate-%lu, clk_div-%u\n", + dev_dbg(port->se.dev, "desired_rate-%u, clk_rate-%lu, clk_div-%u\n", baud * sampling_rate, clk_rate, clk_div); uport->uartclk = clk_rate; |