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authorGreg Kroah-Hartman <gregkh@linuxfoundation.org>2020-05-15 16:09:24 +0200
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2020-05-15 16:09:24 +0200
commitf877a18c08fa6674364e469f318a3069c68204d2 (patch)
tree0e0dbf76b05d4c9119f18fca1d7563ce4ac4bbbb /drivers/uio/uio_hv_generic.c
parentgreybus: Replace zero-length array with flexible-array (diff)
parentfpga: dfl: afu: support debug access to memory-mapped afu regions (diff)
downloadlinux-dev-f877a18c08fa6674364e469f318a3069c68204d2.tar.xz
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Merge tag 'fpga-for-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/mdf/linux-fpga into char-misc-next
Moritz writes: FPGA Manager changes for 5.8 Here's the first set of changes for the 5.8-rc1 merge window. Dominic's change adds support for accessing AFU regions with gdb. Gustavo's change is a cleanup patch regarding variable lenght arrays. Richard's changes update dt-bindings and add support for stratix and agilex. Sergiu's changes update spi transfers with the new delay field. Xu's change addresses an issue with a wrong return value. Shubhrajyoti's change makes the Zynq FPGA driver return -EPROBE_DEFER on check of devm_clk_get failure. Xu's change for DFL enables multiple opens. All of these patches have been reviewed, have appropriate Acked-by's and have been in the last few linux-next releases without issues. Signed-off-by: Moritz Fischer <mdf@kernel.org> * tag 'fpga-for-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/mdf/linux-fpga: fpga: dfl: afu: support debug access to memory-mapped afu regions fpga: dfl.h: Replace zero-length array with flexible-array member arm64: dts: agilex: correct service layer driver's compatible value dt-bindings, firmware: add compatible value Intel Stratix10 service layer binding fpga: stratix10-soc: add compatible property value for intel agilex arm64: dts: agilex: correct FPGA manager driver's compatible value dt-bindings: fpga: add compatible value to Stratix10 SoC FPGA manager binding fpga: machxo2-spi: Use new structure for SPI transfer delays fpga: ice40-spi: Use new structure for SPI transfer delays fpga: dfl: support multiple opens on feature device node.
Diffstat (limited to 'drivers/uio/uio_hv_generic.c')
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