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| author |   Shruthi Sanil <shruthi.sanil@intel.com> | 2022-09-13 11:23:15 +0530 |
|---|---|---|
| committer |   Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2022-09-22 15:52:30 +0200 |
| commit | ff2d2bee475077cb5d023e65fcc0b4f01a3ecdaf (patch) | |
| tree | 51d96222816929d3b2fcfdeda4e20067c4c42b7a /drivers/usb/dwc3/dwc3-pci.c | |
| parent | usb: dwc3: xilinx: fix usb3 non-wakeup source resume failure (diff) | |
| download | linux-dev-ff2d2bee475077cb5d023e65fcc0b4f01a3ecdaf.tar.xz linux-dev-ff2d2bee475077cb5d023e65fcc0b4f01a3ecdaf.zip | |
usb: dwc3: pci: Update the macro names for USB PCIe device ID's for Alder Lake platforms
The device ID 0x465e is defined for the USB3 device controller in the CPU
sub-system of Alder Lake N platform. Hence updating the macro name
accordingly.
The device ID 0x54ee is defined for the USB2 controller on the PCH
sub-system for Alder Lake N platform. Hence updating the macro name
accordingly.
The device ID's defined for Alder Lake P is shared between
Alder Lake P, Alder Lake PS and Alder Lake M.
Hence updating the macro name to ADL from ADLP to make it common
and keeping it aligned with the xHCI ID's naming convention.
As we have two device controllers on Alder Lake platforms
i.e. one on PCH sub-system and another on CPU sub-system(USB3),
appending _PCH for the USB2 device ID macro to differentiate
between the 2 ID's.
Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Shruthi Sanil <shruthi.sanil@intel.com>
Link: https://lore.kernel.org/r/20220913055316.23050-2-shruthi.sanil@intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/usb/dwc3/dwc3-pci.c')
| -rw-r--r-- | drivers/usb/dwc3/dwc3-pci.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c index 4ee4ca09873a..7169d8865e17 100644 --- a/drivers/usb/dwc3/dwc3-pci.c +++ b/drivers/usb/dwc3/dwc3-pci.c @@ -40,9 +40,9 @@ #define PCI_DEVICE_ID_INTEL_TGPLP 0xa0ee #define PCI_DEVICE_ID_INTEL_TGPH 0x43ee #define PCI_DEVICE_ID_INTEL_JSP 0x4dee -#define PCI_DEVICE_ID_INTEL_ADL 0x465e -#define PCI_DEVICE_ID_INTEL_ADLP 0x51ee -#define PCI_DEVICE_ID_INTEL_ADLM 0x54ee +#define PCI_DEVICE_ID_INTEL_ADL_PCH 0x51ee +#define PCI_DEVICE_ID_INTEL_ADLN 0x465e +#define PCI_DEVICE_ID_INTEL_ADLN_PCH 0x54ee #define PCI_DEVICE_ID_INTEL_ADLS 0x7ae1 #define PCI_DEVICE_ID_INTEL_RPL 0x460e #define PCI_DEVICE_ID_INTEL_RPLS 0x7a61 @@ -445,13 +445,13 @@ static const struct pci_device_id dwc3_pci_id_table[] = { { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_JSP), (kernel_ulong_t) &dwc3_pci_intel_swnode, }, - { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADL), + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADL_PCH), (kernel_ulong_t) &dwc3_pci_intel_swnode, }, - { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLP), + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLN), (kernel_ulong_t) &dwc3_pci_intel_swnode, }, - { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLM), + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLN_PCH), (kernel_ulong_t) &dwc3_pci_intel_swnode, }, { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLS), |