diff options
| author |   Ville Syrjälä <syrjala@sci.fi> | 2006-01-09 20:53:27 -0800 |
|---|---|---|
| committer |   Linus Torvalds <torvalds@g5.osdl.org> | 2006-01-10 08:01:48 -0800 |
| commit | 25163c56ed88a3009e7c1d808d3a052357301d63 (patch) | |
| tree | 8b70b0c0e0cb1d84b1e9b75ebe57088a52c510ac /drivers/video/aty/mach64_ct.c | |
| parent | [PATCH] atyfb: Don't stretch with CRT (diff) | |
| download | linux-dev-25163c56ed88a3009e7c1d808d3a052357301d63.tar.xz linux-dev-25163c56ed88a3009e7c1d808d3a052357301d63.zip | |
[PATCH] atyfb: Set ECP divider
Set ECP (scaler/overlay clock) divider. The limits were taken from the
XFree86 ati driver.
Signed-off-by: Ville Syrjälä <syrjala@sci.fi>
Signed-off-by: Antonino Daplas <adaplas@pol.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'drivers/video/aty/mach64_ct.c')
| -rw-r--r-- | drivers/video/aty/mach64_ct.c | 17 |
1 files changed, 14 insertions, 3 deletions
diff --git a/drivers/video/aty/mach64_ct.c b/drivers/video/aty/mach64_ct.c index 9bdb2aab01aa..e7056934c6a8 100644 --- a/drivers/video/aty/mach64_ct.c +++ b/drivers/video/aty/mach64_ct.c @@ -206,9 +206,7 @@ static int aty_valid_pll_ct(const struct fb_info *info, u32 vclk_per, struct pll { u32 q; struct atyfb_par *par = (struct atyfb_par *) info->par; -#ifdef DEBUG int pllvclk; -#endif /* FIXME: use the VTB/GTB /{3,6,12} post dividers if they're better suited */ q = par->ref_clk_per * pll->pll_ref_div * 4 / vclk_per; @@ -223,13 +221,26 @@ static int aty_valid_pll_ct(const struct fb_info *info, u32 vclk_per, struct pll pll->vclk_post_div_real = postdividers[pll->vclk_post_div]; // pll->vclk_post_div <<= 6; pll->vclk_fb_div = q * pll->vclk_post_div_real / 8; -#ifdef DEBUG pllvclk = (1000000 * 2 * pll->vclk_fb_div) / (par->ref_clk_per * pll->pll_ref_div); +#ifdef DEBUG printk("atyfb(%s): pllvclk=%d MHz, vclk=%d MHz\n", __FUNCTION__, pllvclk, pllvclk / pll->vclk_post_div_real); #endif pll->pll_vclk_cntl = 0x03; /* VCLK = PLL_VCLK/VCLKx_POST */ + + /* Set ECP (scaler/overlay clock) divider */ + if (par->pll_limits.ecp_max) { + int ecp = pllvclk / pll->vclk_post_div_real; + int ecp_div = 0; + + while (ecp > par->pll_limits.ecp_max && ecp_div < 2) { + ecp >>= 1; + ecp_div++; + } + pll->pll_vclk_cntl |= ecp_div << 4; + } + return 0; } |