diff options
| author |   Archit Taneja <archit@ti.com> | 2011-02-24 14:17:30 +0530 |
|---|---|---|
| committer |   Tomi Valkeinen <tomi.valkeinen@ti.com> | 2011-03-11 15:46:27 +0200 |
| commit | 1bb478350670fadf708d3cbd6137c32dfbe3fd5f (patch) | |
| tree | 387ed4990280ad1bbfd17f763d9249c66a2d750c /drivers/video/omap2/dss/dss.c | |
| parent | OMAP2PLUS: DSS2: Use dss features to get clock source names of current OMAP (diff) | |
| download | linux-dev-1bb478350670fadf708d3cbd6137c32dfbe3fd5f.tar.xz linux-dev-1bb478350670fadf708d3cbd6137c32dfbe3fd5f.zip | |
OMAP2PLUS: DSS2: DSI: Generalize DSI PLL Clock Naming
DSI PLL output clock names have been made more generic. The clock name
describes what the source of the clock and what clock is used for. Some of
DSI PLL parameters like dividers and DSI PLL source have also been made more
generic.
dsi1_pll_fclk and dsi2_pll_fclk have been changed as dsi_pll_hsdiv_dispc_clk
and dsi_pll_hsdiv_dsi_clk respectively. Also, the hsdividers are now named
regm_dispc and regm_dsi instead of regm3 and regm4.
Functions and macros named on the basis of these clock names have also been
made generic.
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/video/omap2/dss/dss.c')
| -rw-r--r-- | drivers/video/omap2/dss/dss.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c index d049598bb412..5c6805b3362d 100644 --- a/drivers/video/omap2/dss/dss.c +++ b/drivers/video/omap2/dss/dss.c @@ -299,7 +299,7 @@ void dss_select_dispc_clk_source(enum dss_clk_source clk_src) b = clk_src == DSS_CLK_SRC_FCK ? 0 : 1; if (clk_src == DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC) - dsi_wait_dsi1_pll_active(); + dsi_wait_pll_hsdiv_dispc_active(); REG_FLD_MOD(DSS_CONTROL, b, 0, 0); /* DISPC_CLK_SWITCH */ @@ -316,7 +316,7 @@ void dss_select_dsi_clk_source(enum dss_clk_source clk_src) b = clk_src == DSS_CLK_SRC_FCK ? 0 : 1; if (clk_src == DSS_CLK_SRC_DSI_PLL_HSDIV_DSI) - dsi_wait_dsi2_pll_active(); + dsi_wait_pll_hsdiv_dsi_active(); REG_FLD_MOD(DSS_CONTROL, b, 1, 1); /* DSI_CLK_SWITCH */ |