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authorStephan Gatzka <stephan.gatzka@gmail.com>2017-08-22 14:25:07 +0200
committerDavid S. Miller <davem@davemloft.net>2017-08-23 20:26:58 -0700
commit013dae5dbc07aa521a38f1ca2d32123ec674bd5d (patch)
tree72be30944ded6c80347ac4421b7faf870814bdbd /drivers
parentfsl/man: Inherit parent device and of_node (diff)
downloadlinux-dev-013dae5dbc07aa521a38f1ca2d32123ec674bd5d.tar.xz
linux-dev-013dae5dbc07aa521a38f1ca2d32123ec674bd5d.zip
net: stmmac: socfgpa: Ensure emac bit set in sys manager for MII/GMII/SGMII.
When using MII/GMII/SGMII in the Altera SoC, the phy needs to be wired through the FPGA. To ensure correct behavior, the appropriate bit in the System Manager FPGA Interface Group register needs to be set. Signed-off-by: Stephan Gatzka <stephan.gatzka@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
index 17d4bbaeb65c..6e359572b9f0 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
@@ -269,7 +269,10 @@ static int socfpga_dwmac_set_phy_mode(struct socfpga_dwmac *dwmac)
ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift);
ctrl |= val << reg_shift;
- if (dwmac->f2h_ptp_ref_clk) {
+ if (dwmac->f2h_ptp_ref_clk ||
+ phymode == PHY_INTERFACE_MODE_MII ||
+ phymode == PHY_INTERFACE_MODE_GMII ||
+ phymode == PHY_INTERFACE_MODE_SGMII) {
ctrl |= SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2);
regmap_read(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG,
&module);