diff options
| author |   Ben Dooks <ben.dooks@sifive.com> | 2022-09-13 06:18:14 +0000 |
|---|---|---|
| committer |   Palmer Dabbelt <palmer@rivosinc.com> | 2022-10-13 11:06:53 -0700 |
| commit | 3fb787e5bad50687a65ded7f3bb805cab70dff59 (patch) | |
| tree | 784aeb6bb8e127cdf42b7c8d0839257a5ae74ec0 /drivers | |
| parent | soc: sifive: ccache: determine the cache level from dts (diff) | |
| download | linux-dev-3fb787e5bad50687a65ded7f3bb805cab70dff59.tar.xz linux-dev-3fb787e5bad50687a65ded7f3bb805cab70dff59.zip | |
soc: sifive: ccache: reduce printing on init
The driver prints out 6 lines on startup, which can easily be redcued
to two lines without losing any information.
Note, to make the types work better, uint64_t has been replaced with
ULL to make the unsigned long long match the format in the print
statement.
Signed-off-by: Ben Dooks <ben.dooks@sifive.com>
Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20220913061817.22564-5-zong.li@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/soc/sifive/sifive_ccache.c | 25 |
1 files changed, 11 insertions, 14 deletions
diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c index b361b661ea09..17080af7dfa0 100644 --- a/drivers/soc/sifive/sifive_ccache.c +++ b/drivers/soc/sifive/sifive_ccache.c @@ -81,20 +81,17 @@ static void setup_sifive_debug(void) static void ccache_config_read(void) { - u32 regval, val; - - regval = readl(ccache_base + SIFIVE_CCACHE_CONFIG); - val = regval & 0xFF; - pr_info("CCACHE: No. of Banks in the cache: %d\n", val); - val = (regval & 0xFF00) >> 8; - pr_info("CCACHE: No. of ways per bank: %d\n", val); - val = (regval & 0xFF0000) >> 16; - pr_info("CCACHE: Sets per bank: %llu\n", (uint64_t)1 << val); - val = (regval & 0xFF000000) >> 24; - pr_info("CCACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val); - - regval = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); - pr_info("CCACHE: Index of the largest way enabled: %d\n", regval); + u32 cfg; + + cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG); + + pr_info("CCACHE: %u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n", + (cfg & 0xff), (cfg >> 8) & 0xff, + BIT_ULL((cfg >> 16) & 0xff), + BIT_ULL((cfg >> 24) & 0xff)); + + cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); + pr_info("CCACHE: Index of the largest way enabled: %u\n", cfg); } static const struct of_device_id sifive_ccache_ids[] = { |