diff options
| author |   Michal Wajdeczko <michal.wajdeczko@intel.com> | 2019-10-29 09:58:54 +0000 |
|---|---|---|
| committer |   Chris Wilson <chris@chris-wilson.co.uk> | 2019-10-29 10:35:47 +0000 |
| commit | 4dc0a7cae212a3a9fb292e19b91f06012fc70d65 (patch) | |
| tree | 818fb07304e99dcddc5eba0558e8553e91fdda3f /drivers | |
| parent | drm/i915: error capture with no ggtt slot (diff) | |
| download | linux-dev-4dc0a7cae212a3a9fb292e19b91f06012fc70d65.tar.xz linux-dev-4dc0a7cae212a3a9fb292e19b91f06012fc70d65.zip | |
drm/i915: Don't try to place HWS in non-existing mappable region
HWS placement restrictions can't just rely on HAS_LLC flag.
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20191029095856.25431-5-matthew.auld@intel.com
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 9cc1ea6519ec..355523114c71 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -528,7 +528,7 @@ static int pin_ggtt_status_page(struct intel_engine_cs *engine, unsigned int flags; flags = PIN_GLOBAL; - if (!HAS_LLC(engine->i915)) + if (!HAS_LLC(engine->i915) && i915_ggtt_has_aperture(engine->gt->ggtt)) /* * On g33, we cannot place HWS above 256MiB, so * restrict its pinning to the low mappable arena. |