diff options
| author |   Linus Torvalds <torvalds@linux-foundation.org> | 2018-12-25 13:00:14 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2018-12-25 13:00:14 -0800 |
| commit | 5813540b584c3b1a507d1c61896bec164cad0905 (patch) | |
| tree | 439207beec829d15176aee7c0fd3838b024f1c94 /drivers | |
| parent | Merge tag 'mtd/for-4.21' of git://git.infradead.org/linux-mtd (diff) | |
| parent | media: cx23885: only reset DMA on problematic CPUs (diff) | |
| download | linux-dev-5813540b584c3b1a507d1c61896bec164cad0905.tar.xz linux-dev-5813540b584c3b1a507d1c61896bec164cad0905.zip | |
Merge tag 'media/v4.20-6' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media
Pull media updates from Mauro Carvalho Chehab:
"First set of media patches contains:
- Three new platform drivers: aspeed-video seco-sed and sun5i-csi;
- One new sensor driver: imx214;
- Support for Xbox DVD Movie Playback kit remote controller;
- Removal of the legacy friio driver. The functionalities were ported
to another driver, already merged;
- New staging driver: Rockchip VPU;
- Added license text or SPDX tags to all media documentation files;
- Usual set of cleanup, fixes and enhancements"
* tag 'media/v4.20-6' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media: (263 commits)
media: cx23885: only reset DMA on problematic CPUs
media: ddbridge: Move asm includes after linux ones
media: drxk_hard: check if parameter is not NULL
media: docs: fix some GPL licensing ambiguity at the text
media: platform: Add Aspeed Video Engine driver
media: dt-bindings: media: Add Aspeed Video Engine binding documentation
media: vimc: fix start stream when link is disabled
media: v4l2-device: Link subdevices to their parent devices if available
media: siano: Use kmemdup instead of duplicating its function
media: rockchip vpu: remove some unused vars
media: cedrus: don't initialize pointers with zero
media: cetrus: return an error if alloc fails
media: cedrus: Add device-tree compatible and variant for A64 support
media: cedrus: Add device-tree compatible and variant for H5 support
media: dt-bindings: media: cedrus: Add compatibles for the A64 and H5
media: video-i2c: check if chip struct has set_power function
media: video-i2c: support runtime PM
media: staging: media: imx: Use of_node_name_eq for node name comparisons
media: v4l2-subdev: document controls need _FL_HAS_DEVNODE
media: vivid: Improve timestamping
...
Diffstat (limited to 'drivers')
219 files changed, 13455 insertions, 3125 deletions
diff --git a/drivers/media/cec/cec-adap.c b/drivers/media/cec/cec-adap.c index 65a933a21e68..f1261cc2b6fa 100644 --- a/drivers/media/cec/cec-adap.c +++ b/drivers/media/cec/cec-adap.c @@ -455,7 +455,7 @@ int cec_thread_func(void *_adap) (adap->needs_hpd && (!adap->is_configured && !adap->is_configuring)) || kthread_should_stop() || - (!adap->transmitting && + (!adap->transmit_in_progress && !list_empty(&adap->transmit_queue)), msecs_to_jiffies(CEC_XFER_TIMEOUT_MS)); timeout = err == 0; @@ -463,7 +463,7 @@ int cec_thread_func(void *_adap) /* Otherwise we just wait for something to happen. */ wait_event_interruptible(adap->kthread_waitq, kthread_should_stop() || - (!adap->transmitting && + (!adap->transmit_in_progress && !list_empty(&adap->transmit_queue))); } @@ -488,6 +488,7 @@ int cec_thread_func(void *_adap) pr_warn("cec-%s: message %*ph timed out\n", adap->name, adap->transmitting->msg.len, adap->transmitting->msg.msg); + adap->transmit_in_progress = false; adap->tx_timeouts++; /* Just give up on this. */ cec_data_cancel(adap->transmitting, @@ -499,7 +500,7 @@ int cec_thread_func(void *_adap) * If we are still transmitting, or there is nothing new to * transmit, then just continue waiting. */ - if (adap->transmitting || list_empty(&adap->transmit_queue)) + if (adap->transmit_in_progress || list_empty(&adap->transmit_queue)) goto unlock; /* Get a new message to transmit */ @@ -545,6 +546,8 @@ int cec_thread_func(void *_adap) if (adap->ops->adap_transmit(adap, data->attempts, signal_free_time, &data->msg)) cec_data_cancel(data, CEC_TX_STATUS_ABORTED); + else + adap->transmit_in_progress = true; unlock: mutex_unlock(&adap->lock); @@ -575,14 +578,17 @@ void cec_transmit_done_ts(struct cec_adapter *adap, u8 status, data = adap->transmitting; if (!data) { /* - * This can happen if a transmit was issued and the cable is + * This might happen if a transmit was issued and the cable is * unplugged while the transmit is ongoing. Ignore this * transmit in that case. */ - dprintk(1, "%s was called without an ongoing transmit!\n", - __func__); - goto unlock; + if (!adap->transmit_in_progress) + dprintk(1, "%s was called without an ongoing transmit!\n", + __func__); + adap->transmit_in_progress = false; + goto wake_thread; } + adap->transmit_in_progress = false; msg = &data->msg; @@ -648,7 +654,6 @@ wake_thread: * for transmitting or to retry the current message. */ wake_up_interruptible(&adap->kthread_waitq); -unlock: mutex_unlock(&adap->lock); } EXPORT_SYMBOL_GPL(cec_transmit_done_ts); @@ -1432,6 +1437,13 @@ configured: las->log_addr[i], cec_phys_addr_exp(adap->phys_addr)); cec_transmit_msg_fh(adap, &msg, NULL, false); + + /* Report Vendor ID */ + if (adap->log_addrs.vendor_id != CEC_VENDOR_ID_NONE) { + cec_msg_device_vendor_id(&msg, + adap->log_addrs.vendor_id); + cec_transmit_msg_fh(adap, &msg, NULL, false); + } } adap->kthread_config = NULL; complete(&adap->config_completion); @@ -1496,8 +1508,11 @@ void __cec_s_phys_addr(struct cec_adapter *adap, u16 phys_addr, bool block) if (adap->monitor_all_cnt) WARN_ON(call_op(adap, adap_monitor_all_enable, false)); mutex_lock(&adap->devnode.lock); - if (adap->needs_hpd || list_empty(&adap->devnode.fhs)) + if (adap->needs_hpd || list_empty(&adap->devnode.fhs)) { WARN_ON(adap->ops->adap_enable(adap, false)); + adap->transmit_in_progress = false; + wake_up_interruptible(&adap->kthread_waitq); + } mutex_unlock(&adap->devnode.lock); if (phys_addr == CEC_PHYS_ADDR_INVALID) return; @@ -1505,6 +1520,7 @@ void __cec_s_phys_addr(struct cec_adapter *adap, u16 phys_addr, bool block) mutex_lock(&adap->devnode.lock); adap->last_initiator = 0xff; + adap->transmit_in_progress = false; if ((adap->needs_hpd || list_empty(&adap->devnode.fhs)) && adap->ops->adap_enable(adap, true)) { diff --git a/drivers/media/cec/cec-core.c b/drivers/media/cec/cec-core.c index e4edc930d4ed..cc875dabd765 100644 --- a/drivers/media/cec/cec-core.c +++ b/drivers/media/cec/cec-core.c @@ -24,6 +24,10 @@ int cec_debug; module_param_named(debug, cec_debug, int, 0644); MODULE_PARM_DESC(debug, "debug level (0-2)"); +static bool debug_phys_addr; +module_param(debug_phys_addr, bool, 0644); +MODULE_PARM_DESC(debug_phys_addr, "add CEC_CAP_PHYS_ADDR if set"); + static dev_t cec_dev_t; /* Active devices */ @@ -270,6 +274,8 @@ struct cec_adapter *cec_allocate_adapter(const struct cec_adap_ops *ops, adap->log_addrs.cec_version = CEC_OP_CEC_VERSION_2_0; adap->log_addrs.vendor_id = CEC_VENDOR_ID_NONE; adap->capabilities = caps; + if (debug_phys_addr) + adap->capabilities |= CEC_CAP_PHYS_ADDR; adap->needs_hpd = caps & CEC_CAP_NEEDS_HPD; adap->available_log_addrs = available_las; adap->sequence = 0; diff --git a/drivers/media/cec/cec-pin.c b/drivers/media/cec/cec-pin.c index 635db8e70ead..8f987bc0dd88 100644 --- a/drivers/media/cec/cec-pin.c +++ b/drivers/media/cec/cec-pin.c @@ -601,8 +601,9 @@ static void cec_pin_tx_states(struct cec_pin *pin, ktime_t ts) break; /* Was the message ACKed? */ ack = cec_msg_is_broadcast(&pin->tx_msg) ? v : !v; - if (!ack && !pin->tx_ignore_nack_until_eom && - pin->tx_bit / 10 < pin->tx_msg.len && !pin->tx_post_eom) { + if (!ack && (!pin->tx_ignore_nack_until_eom || + pin->tx_bit / 10 == pin->tx_msg.len - 1) && + !pin->tx_post_eom) { /* * Note: the CEC spec is ambiguous regarding * what action to take when a NACK appears diff --git a/drivers/media/common/v4l2-tpg/v4l2-tpg-core.c b/drivers/media/common/v4l2-tpg/v4l2-tpg-core.c index fa483b95bc5a..d9a590ae7545 100644 --- a/drivers/media/common/v4l2-tpg/v4l2-tpg-core.c +++ b/drivers/media/common/v4l2-tpg/v4l2-tpg-core.c @@ -1769,7 +1769,7 @@ typedef struct { u16 __; u8 _; } __packed x24; unsigned s; \ \ for (s = 0; s < len; s++) { \ - u8 chr = font8x16[text[s] * 16 + line]; \ + u8 chr = font8x16[(u8)text[s] * 16 + line]; \ \ if (hdiv == 2 && tpg->hflip) { \ pos[3] = (chr & (0x01 << 6) ? fg : bg); \ diff --git a/drivers/media/common/videobuf2/videobuf2-core.c b/drivers/media/common/videobuf2/videobuf2-core.c index 8ff8722cb6b1..70e8c3366f9c 100644 --- a/drivers/media/common/videobuf2/videobuf2-core.c +++ b/drivers/media/common/videobuf2/videobuf2-core.c @@ -679,11 +679,9 @@ int vb2_core_reqbufs(struct vb2_queue *q, enum vb2_memory memory, * are not in use and can be freed. */ mutex_lock(&q->mmap_lock); - if (q->memory == VB2_MEMORY_MMAP && __buffers_in_use(q)) { - mutex_unlock(&q->mmap_lock); - dprintk(1, "memory in use, cannot free\n"); - return -EBUSY; - } + if (debug && q->memory == VB2_MEMORY_MMAP && + __buffers_in_use(q)) + dprintk(1, "memory in use, orphaning buffers\n"); /* * Call queue_cancel to clean up any buffers in the @@ -812,6 +810,9 @@ int vb2_core_create_bufs(struct vb2_queue *q, enum vb2_memory memory, memset(q->alloc_devs, 0, sizeof(q->alloc_devs)); q->memory = memory; q->waiting_for_buffers = !q->is_output; + } else if (q->memory != memory) { + dprintk(1, "memory model mismatch\n"); + return -EINVAL; } num_buffers = min(*count, VB2_MAX_FRAME - q->num_buffers); @@ -2143,9 +2144,13 @@ int vb2_mmap(struct vb2_queue *q, struct vm_area_struct *vma) return -EINVAL; } } + + mutex_lock(&q->mmap_lock); + if (vb2_fileio_is_active(q)) { dprintk(1, "mmap: file io in progress\n"); - return -EBUSY; + ret = -EBUSY; + goto unlock; } /* @@ -2153,7 +2158,7 @@ int vb2_mmap(struct vb2_queue *q, struct vm_area_struct *vma) */ ret = __find_plane_by_offset(q, off, &buffer, &plane); if (ret) - return ret; + goto unlock; vb = q->bufs[buffer]; @@ -2166,11 +2171,13 @@ int vb2_mmap(struct vb2_queue *q, struct vm_area_struct *vma) if (length < (vma->vm_end - vma->vm_start)) { dprintk(1, "MMAP invalid, as it would overflow buffer length\n"); - return -EINVAL; + ret = -EINVAL; + goto unlock; } - mutex_lock(&q->mmap_lock); ret = call_memop(vb, mmap, vb->planes[plane].mem_priv, vma); + +unlock: mutex_unlock(&q->mmap_lock); if (ret) return ret; diff --git a/drivers/media/common/videobuf2/videobuf2-v4l2.c b/drivers/media/common/videobuf2/videobuf2-v4l2.c index 1d35aeabfd85..78a841b83d41 100644 --- a/drivers/media/common/videobuf2/videobuf2-v4l2.c +++ b/drivers/media/common/videobuf2/videobuf2-v4l2.c @@ -158,7 +158,6 @@ static void vb2_warn_zero_bytesused(struct vb2_buffer *vb) return; check_once = true; - WARN_ON(1); pr_warn("use of bytesused == 0 is deprecated and will be removed in the future,\n"); if (vb->vb2_queue->allow_zero_bytesused) @@ -627,7 +626,7 @@ EXPORT_SYMBOL(vb2_querybuf); static void fill_buf_caps(struct vb2_queue *q, u32 *caps) { - *caps = 0; + *caps = V4L2_BUF_CAP_SUPPORTS_ORPHANED_BUFS; if (q->io_modes & VB2_MMAP) *caps |= V4L2_BUF_CAP_SUPPORTS_MMAP; if (q->io_modes & VB2_USERPTR) diff --git a/drivers/media/dvb-core/dvb_frontend.c b/drivers/media/dvb-core/dvb_frontend.c index 961207cf09eb..27a1d4a98d73 100644 --- a/drivers/media/dvb-core/dvb_frontend.c +++ b/drivers/media/dvb-core/dvb_frontend.c @@ -917,6 +917,9 @@ static void dvb_frontend_get_frequency_limits(struct dvb_frontend *fe, "DVB: adapter %i frontend %u frequency limits undefined - fix the driver\n", fe->dvb->num, fe->id); + dprintk("frequency interval: tuner: %u...%u, frontend: %u...%u", + tuner_min, tuner_max, frontend_min, frontend_max); + /* If the standard is for satellite, convert frequencies to kHz */ switch (c->delivery_system) { case SYS_DVBS: @@ -2587,8 +2590,8 @@ static int dvb_frontend_handle_ioctl(struct file *file, u8 last = 1; if (dvb_frontend_debug) - dprintk("%s switch command: 0x%04lx\n", - __func__, swcmd); + dprintk("switch command: 0x%04lx\n", + swcmd); nexttime = ktime_get_boottime(); if (dvb_frontend_debug) tv[0] = nexttime; @@ -2611,8 +2614,8 @@ static int dvb_frontend_handle_ioctl(struct file *file, dvb_frontend_sleep_until(&nexttime, 8000); } if (dvb_frontend_debug) { - dprintk("%s(%d): switch delay (should be 32k followed by all 8k)\n", - __func__, fe->dvb->num); + dprintk("(adapter %d): switch delay (should be 32k followed by all 8k)\n", + fe->dvb->num); for (i = 1; i < 10; i++) pr_info("%d: %d\n", i, (int)ktime_us_delta(tv[i], tv[i - 1])); diff --git a/drivers/media/dvb-frontends/af9033.c b/drivers/media/dvb-frontends/af9033.c index 0cd57013ea25..23b831ce3439 100644 --- a/drivers/media/dvb-frontends/af9033.c +++ b/drivers/media/dvb-frontends/af9033.c @@ -1137,16 +1137,8 @@ static int af9033_probe(struct i2c_client *client, buf[4], buf[5], buf[6], buf[7]); /* Sleep as chip seems to be partly active by default */ - switch (dev->cfg.tuner) { - case AF9033_TUNER_IT9135_38: - case AF9033_TUNER_IT9135_51: - case AF9033_TUNER_IT9135_52: - case AF9033_TUNER_IT9135_60: - case AF9033_TUNER_IT9135_61: - case AF9033_TUNER_IT9135_62: - /* IT9135 did not like to sleep at that early */ - break; - default: + /* IT9135 did not like to sleep at that early */ + if (dev->is_af9035) { ret = regmap_write(dev->regmap, 0x80004c, 0x01); if (ret) goto err_regmap_exit; diff --git a/drivers/media/dvb-frontends/dib0090.c b/drivers/media/dvb-frontends/dib0090.c index 44a074261e69..4813a88eb9f7 100644 --- a/drivers/media/dvb-frontends/dib0090.c +++ b/drivers/media/dvb-frontends/dib0090.c @@ -1072,45 +1072,45 @@ static void dib0090_set_bbramp_pwm(struct dib0090_state *state, const u16 * cfg) void dib0090_pwm_gain_reset(struct dvb_frontend *fe) { struct dib0090_state *state = fe->tuner_priv; - u16 *bb_ramp = (u16 *)&bb_ramp_pwm_normal; /* default baseband config */ - u16 *rf_ramp = NULL; + const u16 *bb_ramp = bb_ramp_pwm_normal; /* default baseband config */ + const u16 *rf_ramp = NULL; u8 en_pwm_rf_mux = 1; /* reset the AGC */ if (state->config->use_pwm_agc) { if (state->current_band == BAND_CBAND) { if (state->identity.in_soc) { - bb_ramp = (u16 *)&bb_ramp_pwm_normal_socs; + bb_ramp = bb_ramp_pwm_normal_socs; if (state->identity.version == SOC_8090_P1G_11R1 || state->identity.version == SOC_8090_P1G_21R1) - rf_ramp = (u16 *)&rf_ramp_pwm_cband_8090; + rf_ramp = rf_ramp_pwm_cband_8090; else if (state->identity.version == SOC_7090_P1G_11R1 || state->identity.version == SOC_7090_P1G_21R1) { if (state->config->is_dib7090e) { if (state->rf_ramp == NULL) - rf_ramp = (u16 *)&rf_ramp_pwm_cband_7090e_sensitivity; + rf_ramp = rf_ramp_pwm_cband_7090e_sensitivity; else - rf_ramp = (u16 *)state->rf_ramp; + rf_ramp = state->rf_ramp; } else - rf_ramp = (u16 *)&rf_ramp_pwm_cband_7090p; + rf_ramp = rf_ramp_pwm_cband_7090p; } } else - rf_ramp = (u16 *)&rf_ramp_pwm_cband; + rf_ramp = rf_ramp_pwm_cband; } else if (state->current_band == BAND_VHF) { if (state->identity.in_soc) { - bb_ramp = (u16 *)&bb_ramp_pwm_normal_socs; + bb_ramp = bb_ramp_pwm_normal_socs; /* rf_ramp = &rf_ramp_pwm_vhf_socs; */ /* TODO */ } else - rf_ramp = (u16 *)&rf_ramp_pwm_vhf; + rf_ramp = rf_ramp_pwm_vhf; } else if (state->current_band == BAND_UHF) { if (state->identity.in_soc) { - bb_ramp = (u16 *)&bb_ramp_pwm_normal_socs; + bb_ramp = bb_ramp_pwm_normal_socs; if (state->identity.version == SOC_8090_P1G_11R1 || state->identity.version == SOC_8090_P1G_21R1) - rf_ramp = (u16 *)&rf_ramp_pwm_uhf_8090; + rf_ramp = rf_ramp_pwm_uhf_8090; else if (state->identity.version == SOC_7090_P1G_11R1 || state->identity.version == SOC_7090_P1G_21R1) - rf_ramp = (u16 *)&rf_ramp_pwm_uhf_7090; + rf_ramp = rf_ramp_pwm_uhf_7090; } else - rf_ramp = (u16 *)&rf_ramp_pwm_uhf; + rf_ramp = rf_ramp_pwm_uhf; } if (rf_ramp) dib0090_set_rframp_pwm(state, rf_ramp); @@ -1416,9 +1416,9 @@ int dib0090_update_rframp_7090(struct dvb_frontend *fe, u8 cfg_sensitivity) } if (cfg_sensitivity) - state->rf_ramp = (const u16 *)&rf_ramp_pwm_cband_7090e_sensitivity; + state->rf_ramp = rf_ramp_pwm_cband_7090e_sensitivity; else - state->rf_ramp = (const u16 *)&rf_ramp_pwm_cband_7090e_aci; + state->rf_ramp = rf_ramp_pwm_cband_7090e_aci; dib0090_pwm_gain_reset(fe); return 0; diff --git a/drivers/media/dvb-frontends/dib7000p.c b/drivers/media/dvb-frontends/dib7000p.c index 58387860b62d..2818e8def1b3 100644 --- a/drivers/media/dvb-frontends/dib7000p.c +++ b/drivers/media/dvb-frontends/dib7000p.c @@ -1871,10 +1871,13 @@ static u32 dib7000p_get_time_us(struct dvb_frontend *demod) break; } - interleaving = interleaving; - denom = bits_per_symbol * rate_num * fft_div * 384; + /* + * FIXME: check if the math makes sense. If so, fill the + * interleaving var. + */ + /* If calculus gets wrong, wait for 1s for the next stats */ if (!denom) return 0; diff --git a/drivers/media/dvb-frontends/drxk_hard.c b/drivers/media/dvb-frontends/drxk_hard.c index 84ac3f73f8fe..8ea1e45be710 100644 --- a/drivers/media/dvb-frontends/drxk_hard.c +++ b/drivers/media/dvb-frontends/drxk_hard.c @@ -1474,9 +1474,11 @@ static int scu_command(struct drxk_state *state, /* assume that the command register is ready since it is checked afterwards */ - for (ii = parameter_len - 1; ii >= 0; ii -= 1) { - buffer[cnt++] = (parameter[ii] & 0xFF); - buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF); + if (parameter) { + for (ii = parameter_len - 1; ii >= 0; ii -= 1) { + buffer[cnt++] = (parameter[ii] & 0xFF); + buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF); + } } buffer[cnt++] = (cmd & 0xFF); buffer[cnt++] = ((cmd >> 8) & 0xFF); diff --git a/drivers/media/dvb-frontends/lgdt3306a.c b/drivers/media/dvb-frontends/lgdt3306a.c index 0e1f5daaf20c..cee9c83e48de 100644 --- a/drivers/media/dvb-frontends/lgdt3306a.c +++ b/drivers/media/dvb-frontends/lgdt3306a.c @@ -2205,15 +2205,13 @@ static int lgdt3306a_probe(struct i2c_client *client, struct dvb_frontend *fe; int ret; - config = kzalloc(sizeof(struct lgdt3306a_config), GFP_KERNEL); + config = kmemdup(client->dev.platform_data, + sizeof(struct lgdt3306a_config), GFP_KERNEL); if (config == NULL) { ret = -ENOMEM; goto fail; } - memcpy(config, client->dev.platform_data, - sizeof(struct lgdt3306a_config)); - config->i2c_addr = client->addr; fe = lgdt3306a_attach(config, client->adapter); if (fe == NULL) { diff --git a/drivers/media/dvb-frontends/mxl5xx.c b/drivers/media/dvb-frontends/mxl5xx.c index 6191315f5970..290b9eab099f 100644 --- a/drivers/media/dvb-frontends/mxl5xx.c +++ b/drivers/media/dvb-frontends/mxl5xx.c @@ -781,7 +781,7 @@ static int set_input(struct dvb_frontend *fe, int input) return 0; } -static struct dvb_frontend_ops mxl_ops = { +static const struct dvb_frontend_ops mxl_ops = { .delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS }, .info = { .name = "MaxLinear MxL5xx DVB-S/S2 tuner-demodulator", diff --git a/drivers/media/dvb-frontends/tda18271c2dd.c b/drivers/media/dvb-frontends/tda18271c2dd.c index 5ce58612315d..eeb2318c102f 100644 --- a/drivers/media/dvb-frontends/tda18271c2dd.c +++ b/drivers/media/dvb-frontends/tda18271c2dd.c @@ -20,7 +20,6 @@ #include <linux/kernel.h> #include <linux/module.h> -#include <linux/moduleparam.h> #include <linux/init.h> #include <linux/delay.h> #include <linux/firmware.h> diff --git a/drivers/media/firewire/firedtv-avc.c b/drivers/media/firewire/firedtv-avc.c index 1c933b2cf760..3ef5df1648d7 100644 --- a/drivers/media/firewire/firedtv-avc.c +++ b/drivers/media/firewire/firedtv-avc.c @@ -968,7 +968,8 @@ static int get_ca_object_length(struct avc_response_frame *r) return r->operand[7]; } -int avc_ca_app_info(struct firedtv *fdtv, char *app_info, unsigned int *len) +int avc_ca_app_info(struct firedtv *fdtv, unsigned char *app_info, + unsigned int *len) { struct avc_command_frame *c = (void *)fdtv->avc_data; struct avc_response_frame *r = (void *)fdtv->avc_data; @@ -1009,7 +1010,8 @@ out: return ret; } -int avc_ca_info(struct firedtv *fdtv, char *app_info, unsigned int *len) +int avc_ca_info(struct firedtv *fdtv, unsigned char *app_info, + unsigned int *len) { struct avc_command_frame *c = (void *)fdtv->avc_data; struct avc_response_frame *r = (void *)fdtv->avc_data; diff --git a/drivers/media/firewire/firedtv.h b/drivers/media/firewire/firedtv.h index 876cdec8329b..009905a19947 100644 --- a/drivers/media/firewire/firedtv.h +++ b/drivers/media/firewire/firedtv.h @@ -124,8 +124,10 @@ int avc_lnb_control(struct firedtv *fdtv, char voltage, char burst, struct dvb_diseqc_master_cmd *diseqcmd); void avc_remote_ctrl_work(struct work_struct *work); int avc_register_remote_control(struct firedtv *fdtv); -int avc_ca_app_info(struct firedtv *fdtv, char *app_info, unsigned int *len); -int avc_ca_info(struct firedtv *fdtv, char *app_info, unsigned int *len); +int avc_ca_app_info(struct firedtv *fdtv, unsigned char *app_info, + unsigned int *len); +int avc_ca_info(struct firedtv *fdtv, unsigned char *app_info, + unsigned int *len); int avc_ca_reset(struct firedtv *fdtv); int avc_ca_pmt(struct firedtv *fdtv, char *app_info, int length); int avc_ca_get_time_date(struct firedtv *fdtv, int *interval); diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig index 704af210e270..4c936e129500 100644 --- a/drivers/media/i2c/Kconfig +++ b/drivers/media/i2c/Kconfig @@ -61,6 +61,7 @@ config VIDEO_TDA1997X depends on VIDEO_V4L2 && I2C && VIDEO_V4L2_SUBDEV_API depends on SND_SOC select SND_PCM + select HDMI ---help--- V4L2 subdevice driver for the NXP TDA1997x HDMI receivers. @@ -595,6 +596,18 @@ config VIDEO_APTINA_PLL config VIDEO_SMIAPP_PLL tristate +config VIDEO_IMX214 + tristate "Sony IMX214 sensor support" + depends on GPIOLIB && I2C && VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API + depends on MEDIA_CAMERA_SUPPORT + depends on V4L2_FWNODE + help + This is a Video4Linux2 sensor driver for the Sony + IMX214 camera. + + To compile this driver as a module, choose M here: the + module will be called imx214. + config VIDEO_IMX258 tristate "Sony IMX258 sensor support" depends on I2C && VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API @@ -610,6 +623,7 @@ config VIDEO_IMX274 tristate "Sony IMX274 sensor support" depends on I2C && VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API depends on MEDIA_CAMERA_SUPPORT + select REGMAP_I2C ---help--- This is a V4L2 sensor driver for the Sony IMX274 CMOS image sensor. @@ -846,6 +860,7 @@ config VIDEO_MT9M032 config VIDEO_MT9M111 tristate "mt9m111, mt9m112 and mt9m131 support" depends on I2C && VIDEO_V4L2 + select V4L2_FWNODE help This driver supports MT9M111, MT9M112 and MT9M131 cameras from Micron/Aptina diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile index 260d4d9ec2a1..65fae7732de0 100644 --- a/drivers/media/i2c/Makefile +++ b/drivers/media/i2c/Makefile @@ -106,6 +106,7 @@ obj-$(CONFIG_VIDEO_I2C) += video-i2c.o obj-$(CONFIG_VIDEO_ML86V7667) += ml86v7667.o obj-$(CONFIG_VIDEO_OV2659) += ov2659.o obj-$(CONFIG_VIDEO_TC358743) += tc358743.o +obj-$(CONFIG_VIDEO_IMX214) += imx214.o obj-$(CONFIG_VIDEO_IMX258) += imx258.o obj-$(CONFIG_VIDEO_IMX274) += imx274.o obj-$(CONFIG_VIDEO_IMX319) += imx319.o diff --git a/drivers/media/i2c/ad9389b.c b/drivers/media/i2c/ad9389b.c index 5b008b0002c0..aa8b04cfed0f 100644 --- a/drivers/media/i2c/ad9389b.c +++ b/drivers/media/i2c/ad9389b.c @@ -578,7 +578,7 @@ static const struct v4l2_dv_timings_cap ad9389b_timings_cap = { .type = V4L2_DV_BT_656_1120, /* keep this initialization for compatibility with GCC < 4.4.6 */ .reserved = { 0 }, - V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 170000000, + V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 170000000, V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING | diff --git a/drivers/media/i2c/adv7180.c b/drivers/media/i2c/adv7180.c index 99697baad2ea..6f3dc8862622 100644 --- a/drivers/media/i2c/adv7180.c +++ b/drivers/media/i2c/adv7180.c @@ -180,6 +180,9 @@ #define V4L2_CID_ADV_FAST_SWITCH (V4L2_CID_USER_ADV7180_BASE + 0x00) +/* Initial number of frames to skip to avoid possible garbage */ +#define ADV7180_NUM_OF_SKIP_FRAMES 2 + struct adv7180_state; #define ADV7180_FLAG_RESET_POWERED BIT(0) @@ -769,6 +772,13 @@ static int adv7180_g_mbus_config(struct v4l2_subdev *sd, return 0; } +static int adv7180_get_skip_frames(struct v4l2_subdev *sd, u32 *frames) +{ + *frames = ADV7180_NUM_OF_SKIP_FRAMES; + + return 0; +} + static int adv7180_g_pixelaspect(struct v4l2_subdev *sd, struct v4l2_fract *aspect) { struct adv7180_state *state = to_state(sd); @@ -849,10 +859,15 @@ static const struct v4l2_subdev_pad_ops adv7180_pad_ops = { .get_fmt = adv7180_get_pad_format, }; +static const struct v4l2_subdev_sensor_ops adv7180_sensor_ops = { + .g_skip_frames = adv7180_get_skip_frames, +}; + static const struct v4l2_subdev_ops adv7180_ops = { .core = &adv7180_core_ops, .video = &adv7180_video_ops, .pad = &adv7180_pad_ops, + .sensor = &adv7180_sensor_ops, }; static irqreturn_t adv7180_irq(int irq, void *devid) diff --git a/drivers/media/i2c/adv7511.c b/drivers/media/i2c/adv7511.c index 4551bca3c127..cec5ebb1c9e6 100644 --- a/drivers/media/i2c/adv7511.c +++ b/drivers/media/i2c/adv7511.c @@ -130,7 +130,7 @@ static const struct v4l2_dv_timings_cap adv7511_timings_cap = { .type = V4L2_DV_BT_656_1120, /* keep this initialization for compatibility with GCC < 4.4.6 */ .reserved = { 0 }, - V4L2_INIT_BT_TIMINGS(0, ADV7511_MAX_WIDTH, 0, ADV7511_MAX_HEIGHT, + V4L2_INIT_BT_TIMINGS(640, ADV7511_MAX_WIDTH, 350, ADV7511_MAX_HEIGHT, ADV7511_MIN_PIXELCLOCK, ADV7511_MAX_PIXELCLOCK, V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, diff --git a/drivers/media/i2c/adv7604.c b/drivers/media/i2c/adv7604.c index 9f99ef38bcca..28a84bf9f8a9 100644 --- a/drivers/media/i2c/adv7604.c +++ b/drivers/media/i2c/adv7604.c @@ -27,6 +27,7 @@ #include <linux/videodev2.h> #include <linux/workqueue.h> #include <linux/regmap.h> +#include <linux/interrupt.h> #include <media/i2c/adv7604.h> #include <media/cec.h> @@ -114,6 +115,11 @@ struct adv76xx_chip_info { unsigned int fmt_change_digital_mask; unsigned int cp_csc; + unsigned int cec_irq_status; + unsigned int cec_rx_enable; + unsigned int cec_rx_enable_mask; + bool cec_irq_swap; + const struct adv76xx_format_info *formats; unsigned int nformats; @@ -766,7 +772,7 @@ static const struct v4l2_dv_timings_cap adv7604_timings_cap_analog = { .type = V4L2_DV_BT_656_1120, /* keep this initialization for compatibility with GCC < 4.4.6 */ .reserved = { 0 }, - V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 170000000, + V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 170000000, V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING | @@ -777,7 +783,7 @@ static const struct v4l2_dv_timings_cap adv76xx_timings_cap_digital = { .type = V4L2_DV_BT_656_1120, /* keep this initialization for compatibility with GCC < 4.4.6 */ .reserved = { 0 }, - V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 225000000, + V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 225000000, V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING | @@ -2003,10 +2009,11 @@ static void adv76xx_cec_tx_raw_status(struct v4l2_subdev *sd, u8 tx_raw_status) static void adv76xx_cec_isr(struct v4l2_subdev *sd, bool *handled) { struct adv76xx_state *state = to_state(sd); + const struct adv76xx_chip_info *info = state->info; u8 cec_irq; /* cec controller */ - cec_irq = io_read(sd, 0x4d) & 0x0f; + cec_irq = io_read(sd, info->cec_irq_status) & 0x0f; if (!cec_irq) return; @@ -2024,15 +2031,21 @@ static void adv76xx_cec_isr(struct v4l2_subdev *sd, bool *handled) for (i = 0; i < msg.len; i++) msg.msg[i] = cec_read(sd, i + 0x15); - cec_write(sd, 0x26, 0x01); /* re-enable rx */ + cec_write(sd, info->cec_rx_enable, + info->cec_rx_enable_mask); /* re-enable rx */ cec_received_msg(state->cec_adap, &msg); } } - /* note: the bit order is swapped between 0x4d and 0x4e */ - cec_irq = ((cec_irq & 0x08) >> 3) | ((cec_irq & 0x04) >> 1) | - ((cec_irq & 0x02) << 1) | ((cec_irq & 0x01) << 3); - io_write(sd, 0x4e, cec_irq); + if (info->cec_irq_swap) { + /* + * Note: the bit order is swapped between 0x4d and 0x4e + * on adv7604 + */ + cec_irq = ((cec_irq & 0x08) >> 3) | ((cec_irq & 0x04) >> 1) | + ((cec_irq & 0x02) << 1) | ((cec_irq & 0x01) << 3); + } + io_write(sd, info->cec_irq_status + 1, cec_irq); if (handled) *handled = true; @@ -2041,6 +2054,7 @@ static void adv76xx_cec_isr(struct v4l2_subdev *sd, bool *handled) static int adv76xx_cec_adap_enable(struct cec_adapter *adap, bool enable) { struct adv76xx_state *state = cec_get_drvdata(adap); + const struct adv76xx_chip_info *info = state->info; struct v4l2_subdev *sd = &state->sd; if (!state->cec_enabled_adap && enable) { @@ -2052,11 +2066,11 @@ static int adv76xx_cec_adap_enable(struct cec_adapter *adap, bool enable) /* tx: arbitration lost */ /* tx: retry timeout */ /* rx: ready */ - io_write_clr_set(sd, 0x50, 0x0f, 0x0f); - cec_write(sd, 0x26, 0x01); /* enable rx */ + io_write_clr_set(sd, info->cec_irq_status + 3, 0x0f, 0x0f); + cec_write(sd, info->cec_rx_enable, info->cec_rx_enable_mask); } else if (state->cec_enabled_adap && !enable) { /* disable cec interrupts */ - io_write_clr_set(sd, 0x50, 0x0f, 0x00); + io_write_clr_set(sd, info->cec_irq_status + 3, 0x0f, 0x00); /* disable address mask 1-3 */ cec_write_clr_set(sd, 0x27, 0x70, 0x00); /* power down cec section */ @@ -2221,6 +2235,16 @@ static int adv76xx_isr(struct v4l2_subdev *sd, u32 status, bool *handled) return 0; } +static irqreturn_t adv76xx_irq_handler(int irq, void *dev_id) +{ + struct adv76xx_state *state = dev_id; + bool handled = false; + + adv76xx_isr(&state->sd, 0, &handled); + + return handled ? IRQ_HANDLED : IRQ_NONE; +} + static int adv76xx_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) { struct adv76xx_state *state = to_state(sd); @@ -2960,6 +2984,10 @@ static const struct adv76xx_chip_info adv76xx_chip_info[] = { .cable_det_mask = 0x1e, .fmt_change_digital_mask = 0xc1, .cp_csc = 0xfc, + .cec_irq_status = 0x4d, + .cec_rx_enable = 0x26, + .cec_rx_enable_mask = 0x01, + .cec_irq_swap = true, .formats = adv7604_formats, .nformats = ARRAY_SIZE(adv7604_formats), .set_termination = adv7604_set_termination, @@ -3006,6 +3034,9 @@ static const struct adv76xx_chip_info adv76xx_chip_info[] = { .cable_det_mask = 0x01, .fmt_change_digital_mask = 0x03, .cp_csc = 0xf4, + .cec_irq_status = 0x93, + .cec_rx_enable = 0x2c, + .cec_rx_enable_mask = 0x02, .formats = adv7611_formats, .nformats = ARRAY_SIZE(adv7611_formats), .set_termination = adv7611_set_termination, @@ -3047,6 +3078,9 @@ static const struct adv76xx_chip_info adv76xx_chip_info[] = { .cable_det_mask = 0x01, .fmt_change_digital_mask = 0x03, .cp_csc = 0xf4, + .cec_irq_status = 0x93, + .cec_rx_enable = 0x2c, + .cec_rx_enable_mask = 0x02, .formats = adv7612_formats, .nformats = ARRAY_SIZE(adv7612_formats), .set_termination = adv7611_set_termination, @@ -3134,7 +3168,7 @@ static int adv76xx_parse_dt(struct adv76xx_state *state) state->pdata.insert_av_codes = 1; /* Disable the interrupt for now as no DT-based board uses it. */ - state->pdata.int1_config = ADV76XX_INT1_CONFIG_DISABLED; + state->pdata.int1_config = ADV76XX_INT1_CONFIG_ACTIVE_HIGH; /* Hardcode the remaining platform data fields. */ state->pdata.disable_pwrdnb = 0; @@ -3517,6 +3551,16 @@ static int adv76xx_probe(struct i2c_client *client, if (err) goto err_entity; + if (client->irq) { + err = devm_request_threaded_irq(&client->dev, + client->irq, + NULL, adv76xx_irq_handler, + IRQF_TRIGGER_HIGH | IRQF_ONESHOT, + client->name, state); + if (err) + goto err_entity; + } + #if IS_ENABLED(CONFIG_VIDEO_ADV7604_CEC) state->cec_adap = cec_allocate_adapter(&adv76xx_cec_adap_ops, state, dev_name(&client->dev), diff --git a/drivers/media/i2c/adv7842.c b/drivers/media/i2c/adv7842.c index 0e6384f2016a..989259488e3d 100644 --- a/drivers/media/i2c/adv7842.c +++ b/drivers/media/i2c/adv7842.c @@ -663,7 +663,7 @@ static const struct v4l2_dv_timings_cap adv7842_timings_cap_analog = { .type = V4L2_DV_BT_656_1120, /* keep this initialization for compatibility with GCC < 4.4.6 */ .reserved = { 0 }, - V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 170000000, + V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 170000000, V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING | @@ -674,7 +674,7 @@ static const struct v4l2_dv_timings_cap adv7842_timings_cap_digital = { .type = V4L2_DV_BT_656_1120, /* keep this initialization for compatibility with GCC < 4.4.6 */ .reserved = { 0 }, - V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 225000000, + V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 225000000, V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING | diff --git a/drivers/media/i2c/imx214.c b/drivers/media/i2c/imx214.c new file mode 100644 index 000000000000..ec3d1b855f62 --- /dev/null +++ b/drivers/media/i2c/imx214.c @@ -0,0 +1,1118 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * imx214.c - imx214 sensor driver + * + * Copyright 2018 Qtechnology A/S + * + * Ricardo Ribalda <ricardo.ribalda@gmail.com> + */ +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/gpio/consumer.h> +#include <linux/i2c.h> +#include <linux/module.h> +#include <linux/pm_runtime.h> +#include <linux/regmap.h> +#include <linux/regulator/consumer.h> +#include <media/media-entity.h> +#include <media/v4l2-ctrls.h> +#include <media/v4l2-fwnode.h> +#include <media/v4l2-subdev.h> + +#define IMX214_DEFAULT_CLK_FREQ 24000000 +#define IMX214_DEFAULT_LINK_FREQ 480000000 +#define IMX214_DEFAULT_PIXEL_RATE ((IMX214_DEFAULT_LINK_FREQ * 8LL) / 10) +#define IMX214_FPS 30 +#define IMX214_MBUS_CODE MEDIA_BUS_FMT_SRGGB10_1X10 + +static const char * const imx214_supply_name[] = { + "vdda", + "vddd", + "vdddo", +}; + +#define IMX214_NUM_SUPPLIES ARRAY_SIZE(imx214_supply_name) + +struct imx214 { + struct device *dev; + struct clk *xclk; + struct regmap *regmap; + + struct v4l2_subdev sd; + struct media_pad pad; + struct v4l2_mbus_framefmt fmt; + struct v4l2_rect crop; + + struct v4l2_ctrl_handler ctrls; + struct v4l2_ctrl *pixel_rate; + struct v4l2_ctrl *link_freq; + struct v4l2_ctrl *exposure; + + struct regulator_bulk_data supplies[IMX214_NUM_SUPPLIES]; + + struct gpio_desc *enable_gpio; + + /* + * Serialize control access, get/set format, get selection + * and start streaming. + */ + struct mutex mutex; + + bool streaming; +}; + +struct reg_8 { + u16 addr; + u8 val; +}; + +enum { + IMX214_TABLE_WAIT_MS = 0, + IMX214_TABLE_END, + IMX214_MAX_RETRIES, + IMX214_WAIT_MS +}; + +/*From imx214_mode_tbls.h*/ +static const struct reg_8 mode_4096x2304[] = { + {0x0114, 0x03}, + {0x0220, 0x00}, + {0x0221, 0x11}, + {0x0222, 0x01}, + {0x0340, 0x0C}, + {0x0341, 0x7A}, + {0x0342, 0x13}, + {0x0343, 0x90}, + {0x0344, 0x00}, + {0x0345, 0x38}, + {0x0346, 0x01}, + {0x0347, 0x98}, + {0x0348, 0x10}, + {0x0349, 0x37}, + {0x034A, 0x0A}, + {0x034B, 0x97}, + {0x0381, 0x01}, + {0x0383, 0x01}, + {0x0385, 0x01}, + {0x0387, 0x01}, + {0x0900, 0x00}, + {0x0901, 0x00}, + {0x0902, 0x00}, + {0x3000, 0x35}, + {0x3054, 0x01}, + {0x305C, 0x11}, + + {0x0112, 0x0A}, + {0x0113, 0x0A}, + {0x034C, 0x10}, + {0x034D, 0x00}, + {0x034E, 0x09}, + {0x034F, 0x00}, + {0x0401, 0x00}, + {0x0404, 0x00}, + {0x0405, 0x10}, + {0x0408, 0x00}, + {0x0409, 0x00}, + {0x040A, 0x00}, + {0x040B, 0x00}, + {0x040C, 0x10}, + {0x040D, 0x00}, + {0x040E, 0x09}, + {0x040F, 0x00}, + + {0x0301, 0x05}, + {0x0303, 0x02}, + {0x0305, 0x03}, + {0x0306, 0x00}, + {0x0307, 0x96}, + {0x0309, 0x0A}, + {0x030B, 0x01}, + {0x0310, 0x00}, + + {0x0820, 0x12}, + {0x0821, 0xC0}, + {0x0822, 0x00}, + {0x0823, 0x00}, + + {0x3A03, 0x09}, + {0x3A04, 0x50}, + {0x3A05, 0x01}, + + {0x0B06, 0x01}, + {0x30A2, 0x00}, + + {0x30B4, 0x00}, + + {0x3A02, 0xFF}, + + {0x3011, 0x00}, + {0x3013, 0x01}, + + {0x0202, 0x0C}, + {0x0203, 0x70}, + {0x0224, 0x01}, + {0x0225, 0xF4}, + + {0x0204, 0x00}, + {0x0205, 0x00}, + {0x020E, 0x01}, + {0x020F, 0x00}, + {0x0210, 0x01}, + {0x0211, 0x00}, + {0x0212, 0x01}, + {0x0213, 0x00}, + {0x0214, 0x01}, + {0x0215, 0x00}, + {0x0216, 0x00}, + {0x0217, 0x00}, + + {0x4170, 0x00}, + {0x4171, 0x10}, + {0x4176, 0x00}, + {0x4177, 0x3C}, + {0xAE20, 0x04}, + {0xAE21, 0x5C}, + + {IMX214_TABLE_WAIT_MS, 10}, + {0x0138, 0x01}, + {IMX214_TABLE_END, 0x00} +}; + +static const struct reg_8 mode_1920x1080[] = { + {0x0114, 0x03}, + {0x0220, 0x00}, + {0x0221, 0x11}, + {0x0222, 0x01}, + {0x0340, 0x0C}, + {0x0341, 0x7A}, + {0x0342, 0x13}, + {0x0343, 0x90}, + {0x0344, 0x04}, + {0x0345, 0x78}, + {0x0346, 0x03}, + {0x0347, 0xFC}, + {0x0348, 0x0B}, + {0x0349, 0xF7}, + {0x034A, 0x08}, + {0x034B, 0x33}, + {0x0381, 0x01}, + {0x0383, 0x01}, + {0x0385, 0x01}, + {0x0387, 0x01}, + {0x0900, 0x00}, + {0x0901, 0x00}, + {0x0902, 0x00}, + {0x3000, 0x35}, + {0x3054, 0x01}, + {0x305C, 0x11}, + + {0x0112, 0x0A}, + {0x0113, 0x0A}, + {0x034C, 0x07}, + {0x034D, 0x80}, + {0x034E, 0x04}, + {0x034F, 0x38}, + {0x0401, 0x00}, + {0x0404, 0x00}, + {0x0405, 0x10}, + {0x0408, 0x00}, + {0x0409, 0x00}, + {0x040A, 0x00}, + {0x040B, 0x00}, + {0x040C, 0x07}, + {0x040D, 0x80}, + {0x040E, 0x04}, + {0x040F, 0x38}, + + {0x0301, 0x05}, + {0x0303, 0x02}, + {0x0305, 0x03}, + {0x0306, 0x00}, + {0x0307, 0x96}, + {0x0309, 0x0A}, + {0x030B, 0x01}, + {0x0310, 0x00}, + + {0x0820, 0x12}, + {0x0821, 0xC0}, + {0x0822, 0x00}, + {0x0823, 0x00}, + + {0x3A03, 0x04}, + {0x3A04, 0xF8}, + {0x3A05, 0x02}, + + {0x0B06, 0x01}, + {0x30A2, 0x00}, + + {0x30B4, 0x00}, + + {0x3A02, 0xFF}, + + {0x3011, 0x00}, + {0x3013, 0x01}, + + {0x0202, 0x0C}, + {0x0203, 0x70}, + {0x0224, 0x01}, + {0x0225, 0xF4}, + + {0x0204, 0x00}, + {0x0205, 0x00}, + {0x020E, 0x01}, + {0x020F, 0x00}, + {0x0210, 0x01}, + {0x0211, 0x00}, + {0x0212, 0x01}, + {0x0213, 0x00}, + {0x0214, 0x01}, + {0x0215, 0x00}, + {0x0216, 0x00}, + {0x0217, 0x00}, + + {0x4170, 0x00}, + {0x4171, 0x10}, + {0x4176, 0x00}, + {0x4177, 0x3C}, + {0xAE20, 0x04}, + {0xAE21, 0x5C}, + + {IMX214_TABLE_WAIT_MS, 10}, + {0x0138, 0x01}, + {IMX214_TABLE_END, 0x00} +}; + +static const struct reg_8 mode_table_common[] = { + /* software reset */ + + /* software standby settings */ + {0x0100, 0x00}, + + /* ATR setting */ + {0x9300, 0x02}, + + /* external clock setting */ + {0x0136, 0x18}, + {0x0137, 0x00}, + + /* global setting */ + /* basic config */ + {0x0101, 0x00}, + {0x0105, 0x01}, + {0x0106, 0x01}, + {0x4550, 0x02}, + {0x4601, 0x00}, + {0x4642, 0x05}, + {0x6227, 0x11}, + {0x6276, 0x00}, + {0x900E, 0x06}, + {0xA802, 0x90}, + {0xA803, 0x11}, + {0xA804, 0x62}, + {0xA805, 0x77}, + {0xA806, 0xAE}, + {0xA807, 0x34}, + {0xA808, 0xAE}, + {0xA809, 0x35}, + {0xA80A, 0x62}, + {0xA80B, 0x83}, + {0xAE33, 0x00}, + + /* analog setting */ + {0x4174, 0x00}, + {0x4175, 0x11}, + {0x4612, 0x29}, + {0x461B, 0x12}, + {0x461F, 0x06}, + {0x4635, 0x07}, + {0x4637, 0x30}, + {0x463F, 0x18}, + {0x4641, 0x0D}, + {0x465B, 0x12}, + {0x465F, 0x11}, + {0x4663, 0x11}, + {0x4667, 0x0F}, + {0x466F, 0x0F}, + {0x470E, 0x09}, + {0x4909, 0xAB}, + {0x490B, 0x95}, + {0x4915, 0x5D}, + {0x4A5F, 0xFF}, + {0x4A61, 0xFF}, + {0x4A73, 0x62}, + {0x4A85, 0x00}, + {0x4A87, 0xFF}, + + /* embedded data */ + {0x5041, 0x04}, + {0x583C, 0x04}, + {0x620E, 0x04}, + {0x6EB2, 0x01}, + {0x6EB3, 0x00}, + {0x9300, 0x02}, + + /* imagequality */ + /* HDR setting */ + {0x3001, 0x07}, + {0x6D12, 0x3F}, + {0x6D13, 0xFF}, + {0x9344, 0x03}, + {0x9706, 0x10}, + {0x9707, 0x03}, + {0x9708, 0x03}, + {0x9E04, 0x01}, + {0x9E05, 0x00}, + {0x9E0C, 0x01}, + {0x9E0D, 0x02}, + {0x9E24, 0x00}, + {0x9E25, 0x8C}, + {0x9E26, 0x00}, + {0x9E27, 0x94}, + {0x9E28, 0x00}, + {0x9E29, 0x96}, + + /* CNR parameter setting */ + {0x69DB, 0x01}, + + /* Moire reduction */ + {0x6957, 0x01}, + + /* image enhancment */ + {0x6987, 0x17}, + {0x698A, 0x03}, + {0x698B, 0x03}, + + /* white balanace */ + {0x0B8E, 0x01}, + {0x0B8F, 0x00}, + {0x0B90, 0x01}, + {0x0B91, 0x00}, + {0x0B92, 0x01}, + {0x0B93, 0x00}, + {0x0B94, 0x01}, + {0x0B95, 0x00}, + + /* ATR setting */ + {0x6E50, 0x00}, + {0x6E51, 0x32}, + {0x9340, 0x00}, + {0x9341, 0x3C}, + {0x9342, 0x03}, + {0x9343, 0xFF}, + {IMX214_TABLE_END, 0x00} +}; + +/* + * Declare modes in order, from biggest + * to smallest height. + */ +static const struct imx214_mode { + u32 width; + u32 height; + const struct reg_8 *reg_table; +} imx214_modes[] = { + { + .width = 4096, + .height = 2304, + .reg_table = mode_4096x2304, + }, + { + .width = 1920, + .height = 1080, + .reg_table = mode_1920x1080, + }, +}; + +static inline struct imx214 *to_imx214(struct v4l2_subdev *sd) +{ + return container_of(sd, struct imx214, sd); +} + +static int __maybe_unused imx214_power_on(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct imx214 *imx214 = to_imx214(sd); + int ret; + + ret = regulator_bulk_enable(IMX214_NUM_SUPPLIES, imx214->supplies); + if (ret < 0) { + dev_err(imx214->dev, "failed to enable regulators: %d\n", ret); + return ret; + } + + usleep_range(2000, 3000); + + ret = clk_prepare_enable(imx214->xclk); + if (ret < 0) { + regulator_bulk_disable(IMX214_NUM_SUPPLIES, imx214->supplies); + dev_err(imx214->dev, "clk prepare enable failed\n"); + return ret; + } + + gpiod_set_value_cansleep(imx214->enable_gpio, 1); + usleep_range(12000, 15000); + + return 0; +} + +static int __maybe_unused imx214_power_off(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct imx214 *imx214 = to_imx214(sd); + + gpiod_set_value_cansleep(imx214->enable_gpio, 0); + + clk_disable_unprepare(imx214->xclk); + + regulator_bulk_disable(IMX214_NUM_SUPPLIES, imx214->supplies); + usleep_range(10, 20); + + return 0; +} + +static int imx214_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +{ + if (code->index > 0) + return -EINVAL; + + code->code = IMX214_MBUS_CODE; + + return 0; +} + +static int imx214_enum_frame_size(struct v4l2_subdev *subdev, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) +{ + if (fse->code != IMX214_MBUS_CODE) + return -EINVAL; + + if (fse->index >= ARRAY_SIZE(imx214_modes)) + return -EINVAL; + + fse->min_width = fse->max_width = imx214_modes[fse->index].width; + fse->min_height = fse->max_height = imx214_modes[fse->index].height; + + return 0; +} + +#ifdef CONFIG_VIDEO_ADV_DEBUG +static int imx214_s_register(struct v4l2_subdev *subdev, + const struct v4l2_dbg_register *reg) +{ + struct imx214 *imx214 = container_of(subdev, struct imx214, sd); + + return regmap_write(imx214->regmap, reg->reg, reg->val); +} + +static int imx214_g_register(struct v4l2_subdev *subdev, + struct v4l2_dbg_register *reg) +{ + struct imx214 *imx214 = container_of(subdev, struct imx214, sd); + unsigned int aux; + int ret; + + reg->size = 1; + ret = regmap_read(imx214->regmap, reg->reg, &aux); + reg->val = aux; + + return ret; +} +#endif + +static const struct v4l2_subdev_core_ops imx214_core_ops = { +#ifdef CONFIG_VIDEO_ADV_DEBUG + .g_register = imx214_g_register, + .s_register = imx214_s_register, +#endif +}; + +static struct v4l2_mbus_framefmt * +__imx214_get_pad_format(struct imx214 *imx214, + struct v4l2_subdev_pad_config *cfg, + unsigned int pad, + enum v4l2_subdev_format_whence which) +{ + switch (which) { + case V4L2_SUBDEV_FORMAT_TRY: + return v4l2_subdev_get_try_format(&imx214->sd, cfg, pad); + case V4L2_SUBDEV_FORMAT_ACTIVE: + return &imx214->fmt; + default: + return NULL; + } +} + +static int imx214_get_format(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct imx214 *imx214 = to_imx214(sd); + + mutex_lock(&imx214->mutex); + format->format = *__imx214_get_pad_format(imx214, cfg, format->pad, + format->which); + mutex_unlock(&imx214->mutex); + + return 0; +} + +static struct v4l2_rect * +__imx214_get_pad_crop(struct imx214 *imx214, struct v4l2_subdev_pad_config *cfg, + unsigned int pad, enum v4l2_subdev_format_whence which) +{ + switch (which) { + case V4L2_SUBDEV_FORMAT_TRY: + return v4l2_subdev_get_try_crop(&imx214->sd, cfg, pad); + case V4L2_SUBDEV_FORMAT_ACTIVE: + return &imx214->crop; + default: + return NULL; + } +} + +static int imx214_set_format(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct imx214 *imx214 = to_imx214(sd); + struct v4l2_mbus_framefmt *__format; + struct v4l2_rect *__crop; + const struct imx214_mode *mode; + + mutex_lock(&imx214->mutex); + + __crop = __imx214_get_pad_crop(imx214, cfg, format->pad, format->which); + + if (format) + mode = v4l2_find_nearest_size(imx214_modes, + ARRAY_SIZE(imx214_modes), width, height, + format->format.width, format->format.height); + else + mode = &imx214_modes[0]; + + __crop->width = mode->width; + __crop->height = mode->height; + + __format = __imx214_get_pad_format(imx214, cfg, format->pad, + format->which); + __format->width = __crop->width; + __format->height = __crop->height; + __format->code = IMX214_MBUS_CODE; + __format->field = V4L2_FIELD_NONE; + __format->colorspace = V4L2_COLORSPACE_SRGB; + __format->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(__format->colorspace); + __format->quantization = V4L2_MAP_QUANTIZATION_DEFAULT(true, + __format->colorspace, __format->ycbcr_enc); + __format->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(__format->colorspace); + + format->format = *__format; + + mutex_unlock(&imx214->mutex); + + return 0; +} + +static int imx214_get_selection(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_selection *sel) +{ + struct imx214 *imx214 = to_imx214(sd); + + if (sel->target != V4L2_SEL_TGT_CROP) + return -EINVAL; + + mutex_lock(&imx214->mutex); + sel->r = *__imx214_get_pad_crop(imx214, cfg, sel->pad, + sel->which); + mutex_unlock(&imx214->mutex); + return 0; +} + +static int imx214_entity_init_cfg(struct v4l2_subdev *subdev, + struct v4l2_subdev_pad_config *cfg) +{ + struct v4l2_subdev_format fmt = { }; + + fmt.which = cfg ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE; + fmt.format.width = imx214_modes[0].width; + fmt.format.height = imx214_modes[0].height; + + imx214_set_format(subdev, cfg, &fmt); + + return 0; +} + +static int imx214_set_ctrl(struct v4l2_ctrl *ctrl) +{ + struct imx214 *imx214 = container_of(ctrl->handler, + struct imx214, ctrls); + u8 vals[2]; + int ret; + + /* + * Applying V4L2 control value only happens + * when power is up for streaming + */ + if (!pm_runtime_get_if_in_use(imx214->dev)) + return 0; + + switch (ctrl->id) { + case V4L2_CID_EXPOSURE: + vals[1] = ctrl->val; + vals[0] = ctrl->val >> 8; + ret = regmap_bulk_write(imx214->regmap, 0x202, vals, 2); + if (ret < 0) + dev_err(imx214->dev, "Error %d\n", ret); + ret = 0; + break; + + default: + ret = -EINVAL; + } + + pm_runtime_put(imx214->dev); + + return ret; +} + +static const struct v4l2_ctrl_ops imx214_ctrl_ops = { + .s_ctrl = imx214_set_ctrl, +}; + +#define MAX_CMD 4 +static int imx214_write_table(struct imx214 *imx214, + const struct reg_8 table[]) +{ + u8 vals[MAX_CMD]; + int i; + int ret; + + for (; table->addr != IMX214_TABLE_END ; table++) { + if (table->addr == IMX214_TABLE_WAIT_MS) { + usleep_range(table->val * 1000, + table->val * 1000 + 500); + continue; + } + + for (i = 0; i < MAX_CMD; i++) { + if (table[i].addr != (table[0].addr + i)) + break; + vals[i] = table[i].val; + } + + ret = regmap_bulk_write(imx214->regmap, table->addr, vals, i); + + if (ret) { + dev_err(imx214->dev, "write_table error: %d\n", ret); + return ret; + } + + table += i - 1; + } + + return 0; +} + +static int imx214_start_streaming(struct imx214 *imx214) +{ + const struct imx214_mode *mode; + int ret; + + mutex_lock(&imx214->mutex); + ret = imx214_write_table(imx214, mode_table_common); + if (ret < 0) { + dev_err(imx214->dev, "could not sent common table %d\n", ret); + goto error; + } + + mode = v4l2_find_nearest_size(imx214_modes, + ARRAY_SIZE(imx214_modes), width, height, + imx214->fmt.width, imx214->fmt.height); + ret = imx214_write_table(imx214, mode->reg_table); + if (ret < 0) { + dev_err(imx214->dev, "could not sent mode table %d\n", ret); + goto error; + } + ret = __v4l2_ctrl_handler_setup(&imx214->ctrls); + if (ret < 0) { + dev_err(imx214->dev, "could not sync v4l2 controls\n"); + goto error; + } + ret = regmap_write(imx214->regmap, 0x100, 1); + if (ret < 0) { + dev_err(imx214->dev, "could not sent start table %d\n", ret); + goto error; + } + + mutex_unlock(&imx214->mutex); + return 0; + +error: + mutex_unlock(&imx214->mutex); + return ret; +} + +static int imx214_stop_streaming(struct imx214 *imx214) +{ + int ret; + + ret = regmap_write(imx214->regmap, 0x100, 0); + if (ret < 0) + dev_err(imx214->dev, "could not sent stop table %d\n", ret); + + return ret; +} + +static int imx214_s_stream(struct v4l2_subdev *subdev, int enable) +{ + struct imx214 *imx214 = to_imx214(subdev); + int ret; + + if (imx214->streaming == enable) + return 0; + + if (enable) { + ret = pm_runtime_get_sync(imx214->dev); + if (ret < 0) { + pm_runtime_put_noidle(imx214->dev); + return ret; + } + + ret = imx214_start_streaming(imx214); + if (ret < 0) + goto err_rpm_put; + } else { + ret = imx214_start_streaming(imx214); + if (ret < 0) + goto err_rpm_put; + pm_runtime_put(imx214->dev); + } + + imx214->streaming = enable; + return 0; + +err_rpm_put: + pm_runtime_put(imx214->dev); + return ret; +} + +static int imx214_g_frame_interval(struct v4l2_subdev *subdev, + struct v4l2_subdev_frame_interval *fival) +{ + fival->pad = 0; + fival->interval.numerator = 1; + fival->interval.denominator = IMX214_FPS; + + return 0; +} + +static int imx214_enum_frame_interval(struct v4l2_subdev *subdev, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_interval_enum *fie) +{ + const struct imx214_mode *mode; + + if (fie->index != 0) + return -EINVAL; + + mode = v4l2_find_nearest_size(imx214_modes, + ARRAY_SIZE(imx214_modes), width, height, + fie->width, fie->height); + + fie->code = IMX214_MBUS_CODE; + fie->width = mode->width; + fie->height = mode->height; + fie->interval.numerator = 1; + fie->interval.denominator = IMX214_FPS; + + return 0; +} + +static const struct v4l2_subdev_video_ops imx214_video_ops = { + .s_stream = imx214_s_stream, + .g_frame_interval = imx214_g_frame_interval, + .s_frame_interval = imx214_g_frame_interval, +}; + +static const struct v4l2_subdev_pad_ops imx214_subdev_pad_ops = { + .enum_mbus_code = imx214_enum_mbus_code, + .enum_frame_size = imx214_enum_frame_size, + .enum_frame_interval = imx214_enum_frame_interval, + .get_fmt = imx214_get_format, + .set_fmt = imx214_set_format, + .get_selection = imx214_get_selection, + .init_cfg = imx214_entity_init_cfg, +}; + +static const struct v4l2_subdev_ops imx214_subdev_ops = { + .core = &imx214_core_ops, + .video = &imx214_video_ops, + .pad = &imx214_subdev_pad_ops, +}; + +static const struct regmap_config sensor_regmap_config = { + .reg_bits = 16, + .val_bits = 8, + .cache_type = REGCACHE_RBTREE, +}; + +static int imx214_get_regulators(struct device *dev, struct imx214 *imx214) +{ + unsigned int i; + + for (i = 0; i < IMX214_NUM_SUPPLIES; i++) + imx214->supplies[i].supply = imx214_supply_name[i]; + + return devm_regulator_bulk_get(dev, IMX214_NUM_SUPPLIES, + imx214->supplies); +} + +static int imx214_parse_fwnode(struct device *dev) +{ + struct fwnode_handle *endpoint; + struct v4l2_fwnode_endpoint bus_cfg = { + .bus_type = V4L2_MBUS_CSI2_DPHY, + }; + unsigned int i; + int ret; + + endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(dev), NULL); + if (!endpoint) { + dev_err(dev, "endpoint node not found\n"); + return -EINVAL; + } + + ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, &bus_cfg); + if (ret) { + dev_err(dev, "parsing endpoint node failed\n"); + goto done; + } + + for (i = 0; i < bus_cfg.nr_of_link_frequencies; i++) + if (bus_cfg.link_frequencies[i] == IMX214_DEFAULT_LINK_FREQ) + break; + + if (i == bus_cfg.nr_of_link_frequencies) { + dev_err(dev, "link-frequencies %d not supported, Please review your DT\n", + IMX214_DEFAULT_LINK_FREQ); + ret = -EINVAL; + goto done; + } + +done: + v4l2_fwnode_endpoint_free(&bus_cfg); + fwnode_handle_put(endpoint); + return ret; +} + +static int __maybe_unused imx214_suspend(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct imx214 *imx214 = to_imx214(sd); + + if (imx214->streaming) + imx214_stop_streaming(imx214); + + return 0; +} + +static int __maybe_unused imx214_resume(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct imx214 *imx214 = to_imx214(sd); + int ret; + + if (imx214->streaming) { + ret = imx214_start_streaming(imx214); + if (ret) + goto error; + } + + return 0; + +error: + imx214_stop_streaming(imx214); + imx214->streaming = 0; + return ret; +} + +static int imx214_probe(struct i2c_client *client) +{ + struct device *dev = &client->dev; + struct imx214 *imx214; + static const s64 link_freq[] = { + IMX214_DEFAULT_LINK_FREQ, + }; + int ret; + + ret = imx214_parse_fwnode(dev); + if (ret) + return ret; + + imx214 = devm_kzalloc(dev, sizeof(*imx214), GFP_KERNEL); + if (!imx214) + return -ENOMEM; + + imx214->dev = dev; + + imx214->xclk = devm_clk_get(dev, NULL); + if (IS_ERR(imx214->xclk)) { + dev_err(dev, "could not get xclk"); + return PTR_ERR(imx214->xclk); + } + + ret = clk_set_rate(imx214->xclk, IMX214_DEFAULT_CLK_FREQ); + if (ret) { + dev_err(dev, "could not set xclk frequency\n"); + return ret; + } + + ret = imx214_get_regulators(dev, imx214); + if (ret < 0) { + dev_err(dev, "cannot get regulators\n"); + return ret; + } + + imx214->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW); + if (IS_ERR(imx214->enable_gpio)) { + dev_err(dev, "cannot get enable gpio\n"); + return PTR_ERR(imx214->enable_gpio); + } + + imx214->regmap = devm_regmap_init_i2c(client, &sensor_regmap_config); + if (IS_ERR(imx214->regmap)) { + dev_err(dev, "regmap init failed\n"); + return PTR_ERR(imx214->regmap); + } + + v4l2_i2c_subdev_init(&imx214->sd, client, &imx214_subdev_ops); + + /* + * Enable power initially, to avoid warnings + * from clk_disable on power_off + */ + imx214_power_on(imx214->dev); + + pm_runtime_set_active(imx214->dev); + pm_runtime_enable(imx214->dev); + pm_runtime_idle(imx214->dev); + + v4l2_ctrl_handler_init(&imx214->ctrls, 3); + + imx214->pixel_rate = v4l2_ctrl_new_std(&imx214->ctrls, NULL, + V4L2_CID_PIXEL_RATE, 0, + IMX214_DEFAULT_PIXEL_RATE, 1, + IMX214_DEFAULT_PIXEL_RATE); + imx214->link_freq = v4l2_ctrl_new_int_menu(&imx214->ctrls, NULL, + V4L2_CID_LINK_FREQ, + ARRAY_SIZE(link_freq) - 1, + 0, link_freq); + if (imx214->link_freq) + imx214->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; + + /* + * WARNING! + * Values obtained reverse engineering blobs and/or devices. + * Ranges and functionality might be wrong. + * + * Sony, please release some register set documentation for the + * device. + * + * Yours sincerely, Ricardo. + */ + imx214->exposure = v4l2_ctrl_new_std(&imx214->ctrls, &imx214_ctrl_ops, + V4L2_CID_EXPOSURE, + 0, 3184, 1, 0x0c70); + + ret = imx214->ctrls.error; + if (ret) { + dev_err(&client->dev, "%s control init failed (%d)\n", + __func__, ret); + goto free_ctrl; + } + + imx214->sd.ctrl_handler = &imx214->ctrls; + mutex_init(&imx214->mutex); + imx214->ctrls.lock = &imx214->mutex; + + imx214->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + imx214->pad.flags = MEDIA_PAD_FL_SOURCE; + imx214->sd.dev = &client->dev; + imx214->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; + + ret = media_entity_pads_init(&imx214->sd.entity, 1, &imx214->pad); + if (ret < 0) { + dev_err(dev, "could not register media entity\n"); + goto free_ctrl; + } + + imx214_entity_init_cfg(&imx214->sd, NULL); + + ret = v4l2_async_register_subdev_sensor_common(&imx214->sd); + if (ret < 0) { + dev_err(dev, "could not register v4l2 device\n"); + goto free_entity; + } + + return 0; + +free_entity: + media_entity_cleanup(&imx214->sd.entity); +free_ctrl: + mutex_destroy(&imx214->mutex); + v4l2_ctrl_handler_free(&imx214->ctrls); + pm_runtime_disable(imx214->dev); + + return ret; +} + +static int imx214_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct imx214 *imx214 = to_imx214(sd); + + v4l2_async_unregister_subdev(&imx214->sd); + media_entity_cleanup(&imx214->sd.entity); + v4l2_ctrl_handler_free(&imx214->ctrls); + + pm_runtime_disable(&client->dev); + pm_runtime_set_suspended(&client->dev); + + mutex_destroy(&imx214->mutex); + + return 0; +} + +static const struct of_device_id imx214_of_match[] = { + { .compatible = "sony,imx214" }, + { } +}; +MODULE_DEVICE_TABLE(of, imx214_of_match); + +static const struct dev_pm_ops imx214_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(imx214_suspend, imx214_resume) + SET_RUNTIME_PM_OPS(imx214_power_off, imx214_power_on, NULL) +}; + +static struct i2c_driver imx214_i2c_driver = { + .driver = { + .of_match_table = imx214_of_match, + .pm = &imx214_pm_ops, + .name = "imx214", + }, + .probe_new = imx214_probe, + .remove = imx214_remove, +}; + +module_i2c_driver(imx214_i2c_driver); + +MODULE_DESCRIPTION("Sony IMX214 Camera drier"); +MODULE_AUTHOR("Ricardo Ribalda <ricardo.ribalda@gmail.com>"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/media/i2c/imx258.c b/drivers/media/i2c/imx258.c index 31a1e2294843..f86ae18bc104 100644 --- a/drivers/media/i2c/imx258.c +++ b/drivers/media/i2c/imx258.c @@ -62,11 +62,6 @@ /* Test Pattern Control */ #define IMX258_REG_TEST_PATTERN 0x0600 -#define IMX258_TEST_PATTERN_DISABLE 0 -#define IMX258_TEST_PATTERN_SOLID_COLOR 1 -#define IMX258_TEST_PATTERN_COLOR_BARS 2 -#define IMX258_TEST_PATTERN_GREY_COLOR 3 -#define IMX258_TEST_PATTERN_PN9 4 /* Orientation */ #define REG_MIRROR_FLIP_CONTROL 0x0101 @@ -504,18 +499,10 @@ static const struct imx258_reg mode_1048_780_regs[] = { static const char * const imx258_test_pattern_menu[] = { "Disabled", - "Color Bars", - "Solid Color", - "Grey Color Bars", - "PN9" -}; - -static const int imx258_test_pattern_val[] = { - IMX258_TEST_PATTERN_DISABLE, - IMX258_TEST_PATTERN_COLOR_BARS, - IMX258_TEST_PATTERN_SOLID_COLOR, - IMX258_TEST_PATTERN_GREY_COLOR, - IMX258_TEST_PATTERN_PN9, + "Solid Colour", + "Eight Vertical Colour Bars", + "Colour Bars With Fade to Grey", + "Pseudorandom Sequence (PN9)", }; /* Configurations for supported link frequencies */ @@ -778,13 +765,10 @@ static int imx258_set_ctrl(struct v4l2_ctrl *ctrl) case V4L2_CID_TEST_PATTERN: ret = imx258_write_reg(imx258, IMX258_REG_TEST_PATTERN, IMX258_REG_VALUE_16BIT, - imx258_test_pattern_val[ctrl->val]); - + ctrl->val); ret = imx258_write_reg(imx258, REG_MIRROR_FLIP_CONTROL, IMX258_REG_VALUE_08BIT, - ctrl->val == imx258_test_pattern_val - [IMX258_TEST_PATTERN_DISABLE] ? - REG_CONFIG_MIRROR_FLIP : + !ctrl->val ? REG_CONFIG_MIRROR_FLIP : REG_CONFIG_FLIP_TEST_PATTERN); break; default: diff --git a/drivers/media/i2c/imx274.c b/drivers/media/i2c/imx274.c index 11c69281692e..5fac7fd32634 100644 --- a/drivers/media/i2c/imx274.c +++ b/drivers/media/i2c/imx274.c @@ -619,16 +619,19 @@ static int imx274_write_table(struct stimx274 *priv, const struct reg_8 table[]) static inline int imx274_read_reg(struct stimx274 *priv, u16 addr, u8 *val) { + unsigned int uint_val; int err; - err = regmap_read(priv->regmap, addr, (unsigned int *)val); + err = regmap_read(priv->regmap, addr, &uint_val); if (err) dev_err(&priv->client->dev, "%s : i2c read failed, addr = %x\n", __func__, addr); else dev_dbg(&priv->client->dev, "%s : addr 0x%x, val=0x%x\n", __func__, - addr, *val); + addr, uint_val); + + *val = uint_val; return err; } @@ -1901,7 +1904,7 @@ static int imx274_probe(struct i2c_client *client, imx274_reset(imx274, 1); /* initialize controls */ - ret = v4l2_ctrl_handler_init(&imx274->ctrls.handler, 2); + ret = v4l2_ctrl_handler_init(&imx274->ctrls.handler, 4); if (ret < 0) { dev_err(&client->dev, "%s : ctrl handler init Failed\n", __func__); diff --git a/drivers/media/i2c/imx319.c b/drivers/media/i2c/imx319.c index 0d3e27812b93..17c2e4b41221 100644 --- a/drivers/media/i2c/imx319.c +++ b/drivers/media/i2c/imx319.c @@ -1648,10 +1648,10 @@ static const struct imx319_reg mode_1280x720_regs[] = { static const char * const imx319_test_pattern_menu[] = { "Disabled", - "100% color bars", - "Solid color", - "Fade to gray color bars", - "PN9" + "Solid Colour", + "Eight Vertical Colour Bars", + "Colour Bars With Fade to Grey", + "Pseudorandom Sequence (PN9)", }; /* supported link frequencies */ diff --git a/drivers/media/i2c/imx355.c b/drivers/media/i2c/imx355.c index 20c8eea5db4b..bed293b60e50 100644 --- a/drivers/media/i2c/imx355.c +++ b/drivers/media/i2c/imx355.c @@ -876,10 +876,10 @@ static const struct imx355_reg mode_820x616_regs[] = { static const char * const imx355_test_pattern_menu[] = { "Disabled", - "100% color bars", - "Solid color", - "Fade to gray color bars", - "PN9" + "Solid Colour", + "Eight Vertical Colour Bars", + "Colour Bars With Fade to Grey", + "Pseudorandom Sequence (PN9)", }; /* supported link frequencies */ diff --git a/drivers/media/i2c/mt9m111.c b/drivers/media/i2c/mt9m111.c index 1395986a07bb..d639b9bcf64a 100644 --- a/drivers/media/i2c/mt9m111.c +++ b/drivers/media/i2c/mt9m111.c @@ -15,12 +15,15 @@ #include <linux/delay.h> #include <linux/v4l2-mediabus.h> #include <linux/module.h> +#include <linux/property.h> #include <media/v4l2-async.h> #include <media/v4l2-clk.h> #include <media/v4l2-common.h> #include <media/v4l2-ctrls.h> #include <media/v4l2-device.h> +#include <media/v4l2-event.h> +#include <media/v4l2-fwnode.h> /* * MT9M111, MT9M112 and MT9M131: @@ -101,6 +104,7 @@ #define MT9M111_REDUCER_XSIZE_A 0x1a7 #define MT9M111_REDUCER_YZOOM_A 0x1a9 #define MT9M111_REDUCER_YSIZE_A 0x1aa +#define MT9M111_EFFECTS_MODE 0x1e2 #define MT9M111_OUTPUT_FORMAT_CTRL2_A 0x13a #define MT9M111_OUTPUT_FORMAT_CTRL2_B 0x19b @@ -126,6 +130,9 @@ #define MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN (1 << 1) #define MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B (1 << 0) #define MT9M111_TPG_SEL_MASK GENMASK(2, 0) +#define MT9M111_EFFECTS_MODE_MASK GENMASK(2, 0) +#define MT9M111_RM_PWR_MASK BIT(10) +#define MT9M111_RM_SKIP2_MASK GENMASK(3, 2) /* * Camera control register addresses (0x200..0x2ff not implemented) @@ -204,6 +211,23 @@ static const struct mt9m111_datafmt mt9m111_colour_fmts[] = { {MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE, V4L2_COLORSPACE_SRGB}, }; +enum mt9m111_mode_id { + MT9M111_MODE_SXGA_8FPS, + MT9M111_MODE_SXGA_15FPS, + MT9M111_MODE_QSXGA_30FPS, + MT9M111_NUM_MODES, +}; + +struct mt9m111_mode_info { + unsigned int sensor_w; + unsigned int sensor_h; + unsigned int max_image_w; + unsigned int max_image_h; + unsigned int max_fps; + unsigned int reg_val; + unsigned int reg_mask; +}; + struct mt9m111 { struct v4l2_subdev subdev; struct v4l2_ctrl_handler hdl; @@ -213,15 +237,51 @@ struct mt9m111 { struct v4l2_clk *clk; unsigned int width; /* output */ unsigned int height; /* sizes */ + struct v4l2_fract frame_interval; + const struct mt9m111_mode_info *current_mode; struct mutex power_lock; /* lock to protect power_count */ int power_count; const struct mt9m111_datafmt *fmt; int lastpage; /* PageMap cache value */ + bool is_streaming; + /* user point of view - 0: falling 1: rising edge */ + unsigned int pclk_sample:1; #ifdef CONFIG_MEDIA_CONTROLLER struct media_pad pad; #endif }; +static const struct mt9m111_mode_info mt9m111_mode_data[MT9M111_NUM_MODES] = { + [MT9M111_MODE_SXGA_8FPS] = { + .sensor_w = 1280, + .sensor_h = 1024, + .max_image_w = 1280, + .max_image_h = 1024, + .max_fps = 8, + .reg_val = MT9M111_RM_LOW_POWER_RD, + .reg_mask = MT9M111_RM_PWR_MASK | MT9M111_RM_SKIP2_MASK, + }, + [MT9M111_MODE_SXGA_15FPS] = { + .sensor_w = 1280, + .sensor_h = 1024, + .max_image_w = 1280, + .max_image_h = 1024, + .max_fps = 15, + .reg_val = MT9M111_RM_FULL_POWER_RD, + .reg_mask = MT9M111_RM_PWR_MASK | MT9M111_RM_SKIP2_MASK, + }, + [MT9M111_MODE_QSXGA_30FPS] = { + .sensor_w = 1280, + .sensor_h = 1024, + .max_image_w = 640, + .max_image_h = 512, + .max_fps = 30, + .reg_val = MT9M111_RM_LOW_POWER_RD | MT9M111_RM_COL_SKIP_2X | + MT9M111_RM_ROW_SKIP_2X, + .reg_mask = MT9M111_RM_PWR_MASK | MT9M111_RM_SKIP2_MASK, + }, +}; + /* Find a data format by a pixel code */ static const struct mt9m111_datafmt *mt9m111_find_datafmt(struct mt9m111 *mt9m111, u32 code) @@ -538,6 +598,10 @@ static int mt9m111_set_pixfmt(struct mt9m111 *mt9m111, return -EINVAL; } + /* receiver samples on falling edge, chip-hw default is rising */ + if (mt9m111->pclk_sample == 0) + mask_outfmt2 |= MT9M111_OUTFMT_INV_PIX_CLOCK; + ret = mt9m111_reg_mask(client, context_a.output_fmt_ctrl2, data_outfmt2, mask_outfmt2); if (!ret) @@ -559,6 +623,9 @@ static int mt9m111_set_fmt(struct v4l2_subdev *sd, bool bayer; int ret; + if (mt9m111->is_streaming) + return -EBUSY; + if (format->pad) return -EINVAL; @@ -611,6 +678,61 @@ static int mt9m111_set_fmt(struct v4l2_subdev *sd, return ret; } +static const struct mt9m111_mode_info * +mt9m111_find_mode(struct mt9m111 *mt9m111, unsigned int req_fps, + unsigned int width, unsigned int height) +{ + const struct mt9m111_mode_info *mode; + struct v4l2_rect *sensor_rect = &mt9m111->rect; + unsigned int gap, gap_best = (unsigned int) -1; + int i, best_gap_idx = MT9M111_MODE_SXGA_15FPS; + bool skip_30fps = false; + + /* + * The fps selection is based on the row, column skipping mechanism. + * So ensure that the sensor window is set to default else the fps + * aren't calculated correctly within the sensor hw. + */ + if (sensor_rect->width != MT9M111_MAX_WIDTH || + sensor_rect->height != MT9M111_MAX_HEIGHT) { + dev_info(mt9m111->subdev.dev, + "Framerate selection is not supported for cropped " + "images\n"); + return NULL; + } + + /* 30fps only supported for images not exceeding 640x512 */ + if (width > MT9M111_MAX_WIDTH / 2 || height > MT9M111_MAX_HEIGHT / 2) { + dev_dbg(mt9m111->subdev.dev, + "Framerates > 15fps are supported only for images " + "not exceeding 640x512\n"); + skip_30fps = true; + } + + /* find best matched fps */ + for (i = 0; i < MT9M111_NUM_MODES; i++) { + unsigned int fps = mt9m111_mode_data[i].max_fps; + + if (fps == 30 && skip_30fps) + continue; + + gap = abs(fps - req_fps); + if (gap < gap_best) { + best_gap_idx = i; + gap_best = gap; + } + } + + /* + * Use context a/b default timing values instead of calculate blanking + * timing values. + */ + mode = &mt9m111_mode_data[best_gap_idx]; + mt9m111->ctx = (best_gap_idx == MT9M111_MODE_QSXGA_30FPS) ? &context_a : + &context_b; + return mode; +} + #ifdef CONFIG_VIDEO_ADV_DEBUG static int mt9m111_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg) @@ -726,6 +848,29 @@ static int mt9m111_set_test_pattern(struct mt9m111 *mt9m111, int val) MT9M111_TPG_SEL_MASK); } +static int mt9m111_set_colorfx(struct mt9m111 *mt9m111, int val) +{ + struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); + static const struct v4l2_control colorfx[] = { + { V4L2_COLORFX_NONE, 0 }, + { V4L2_COLORFX_BW, 1 }, + { V4L2_COLORFX_SEPIA, 2 }, + { V4L2_COLORFX_NEGATIVE, 3 }, + { V4L2_COLORFX_SOLARIZATION, 4 }, + }; + int i; + + for (i = 0; i < ARRAY_SIZE(colorfx); i++) { + if (colorfx[i].id == val) { + return mt9m111_reg_mask(client, MT9M111_EFFECTS_MODE, + colorfx[i].value, + MT9M111_EFFECTS_MODE_MASK); + } + } + + return -EINVAL; +} + static int mt9m111_s_ctrl(struct v4l2_ctrl *ctrl) { struct mt9m111 *mt9m111 = container_of(ctrl->handler, @@ -746,6 +891,8 @@ static int mt9m111_s_ctrl(struct v4l2_ctrl *ctrl) return mt9m111_set_autowhitebalance(mt9m111, ctrl->val); case V4L2_CID_TEST_PATTERN: return mt9m111_set_test_pattern(mt9m111, ctrl->val); + case V4L2_CID_COLORFX: + return mt9m111_set_colorfx(mt9m111, ctrl->val); } return -EINVAL; @@ -771,11 +918,16 @@ static int mt9m111_suspend(struct mt9m111 *mt9m111) static void mt9m111_restore_state(struct mt9m111 *mt9m111) { + struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); + mt9m111_set_context(mt9m111, mt9m111->ctx); mt9m111_set_pixfmt(mt9m111, mt9m111->fmt->code); mt9m111_setup_geometry(mt9m111, &mt9m111->rect, mt9m111->width, mt9m111->height, mt9m111->fmt->code); v4l2_ctrl_handler_setup(&mt9m111->hdl); + mt9m111_reg_mask(client, mt9m111->ctx->read_mode, + mt9m111->current_mode->reg_val, + mt9m111->current_mode->reg_mask); } static int mt9m111_resume(struct mt9m111 *mt9m111) @@ -862,12 +1014,62 @@ static const struct v4l2_ctrl_ops mt9m111_ctrl_ops = { static const struct v4l2_subdev_core_ops mt9m111_subdev_core_ops = { .s_power = mt9m111_s_power, + .log_status = v4l2_ctrl_subdev_log_status, + .subscribe_event = v4l2_ctrl_subdev_subscribe_event, + .unsubscribe_event = v4l2_event_subdev_unsubscribe, #ifdef CONFIG_VIDEO_ADV_DEBUG .g_register = mt9m111_g_register, .s_register = mt9m111_s_register, #endif }; +static int mt9m111_g_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *fi) +{ + struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev); + + fi->interval = mt9m111->frame_interval; + + return 0; +} + +static int mt9m111_s_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *fi) +{ + struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev); + const struct mt9m111_mode_info *mode; + struct v4l2_fract *fract = &fi->interval; + int fps; + + if (mt9m111->is_streaming) + return -EBUSY; + + if (fi->pad != 0) + return -EINVAL; + + if (fract->numerator == 0) { + fract->denominator = 30; + fract->numerator = 1; + } + + fps = DIV_ROUND_CLOSEST(fract->denominator, fract->numerator); + + /* Find best fitting mode. Do not update the mode if no one was found. */ + mode = mt9m111_find_mode(mt9m111, fps, mt9m111->width, mt9m111->height); + if (!mode) + return 0; + + if (mode->max_fps != fps) { + fract->denominator = mode->max_fps; + fract->numerator = 1; + } + + mt9m111->current_mode = mode; + mt9m111->frame_interval = fi->interval; + + return 0; +} + static int mt9m111_enum_mbus_code(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg, struct v4l2_subdev_mbus_code_enum *code) @@ -879,12 +1081,26 @@ static int mt9m111_enum_mbus_code(struct v4l2_subdev *sd, return 0; } +static int mt9m111_s_stream(struct v4l2_subdev *sd, int enable) +{ + struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev); + + mt9m111->is_streaming = !!enable; + return 0; +} + static int mt9m111_g_mbus_config(struct v4l2_subdev *sd, struct v4l2_mbus_config *cfg) { - cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_PCLK_SAMPLE_RISING | + struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev); + + cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_DATA_ACTIVE_HIGH; + + cfg->flags |= mt9m111->pclk_sample ? V4L2_MBUS_PCLK_SAMPLE_RISING : + V4L2_MBUS_PCLK_SAMPLE_FALLING; + cfg->type = V4L2_MBUS_PARALLEL; return 0; @@ -892,6 +1108,9 @@ static int mt9m111_g_mbus_config(struct v4l2_subdev *sd, static const struct v4l2_subdev_video_ops mt9m111_subdev_video_ops = { .g_mbus_config = mt9m111_g_mbus_config, + .s_stream = mt9m111_s_stream, + .g_frame_interval = mt9m111_g_frame_interval, + .s_frame_interval = mt9m111_s_frame_interval, }; static const struct v4l2_subdev_pad_ops mt9m111_subdev_pad_ops = { @@ -951,6 +1170,30 @@ done: return ret; } +static int mt9m111_probe_fw(struct i2c_client *client, struct mt9m111 *mt9m111) +{ + struct v4l2_fwnode_endpoint bus_cfg = { + .bus_type = V4L2_MBUS_PARALLEL + }; + struct fwnode_handle *np; + int ret; + + np = fwnode_graph_get_next_endpoint(dev_fwnode(&client->dev), NULL); + if (!np) + return -EINVAL; + + ret = v4l2_fwnode_endpoint_parse(np, &bus_cfg); + if (ret) + goto out_put_fw; + + mt9m111->pclk_sample = !!(bus_cfg.bus.parallel.flags & + V4L2_MBUS_PCLK_SAMPLE_RISING); + +out_put_fw: + fwnode_handle_put(np); + return ret; +} + static int mt9m111_probe(struct i2c_client *client, const struct i2c_device_id *did) { @@ -968,6 +1211,10 @@ static int mt9m111_probe(struct i2c_client *client, if (!mt9m111) return -ENOMEM; + ret = mt9m111_probe_fw(client, mt9m111); + if (ret) + return ret; + mt9m111->clk = v4l2_clk_get(&client->dev, "mclk"); if (IS_ERR(mt9m111->clk)) return PTR_ERR(mt9m111->clk); @@ -976,9 +1223,10 @@ static int mt9m111_probe(struct i2c_client *client, mt9m111->ctx = &context_b; v4l2_i2c_subdev_init(&mt9m111->subdev, client, &mt9m111_subdev_ops); - mt9m111->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + mt9m111->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | + V4L2_SUBDEV_FL_HAS_EVENTS; - v4l2_ctrl_handler_init(&mt9m111->hdl, 5); + v4l2_ctrl_handler_init(&mt9m111->hdl, 7); v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops, V4L2_CID_VFLIP, 0, 1, 1, 0); v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops, @@ -994,6 +1242,14 @@ static int mt9m111_probe(struct i2c_client *client, &mt9m111_ctrl_ops, V4L2_CID_TEST_PATTERN, ARRAY_SIZE(mt9m111_test_pattern_menu) - 1, 0, 0, mt9m111_test_pattern_menu); + v4l2_ctrl_new_std_menu(&mt9m111->hdl, &mt9m111_ctrl_ops, + V4L2_CID_COLORFX, V4L2_COLORFX_SOLARIZATION, + ~(BIT(V4L2_COLORFX_NONE) | + BIT(V4L2_COLORFX_BW) | + BIT(V4L2_COLORFX_SEPIA) | + BIT(V4L2_COLORFX_NEGATIVE) | + BIT(V4L2_COLORFX_SOLARIZATION)), + V4L2_COLORFX_NONE); mt9m111->subdev.ctrl_handler = &mt9m111->hdl; if (mt9m111->hdl.error) { ret = mt9m111->hdl.error; @@ -1008,6 +1264,10 @@ static int mt9m111_probe(struct i2c_client *client, goto out_hdlfree; #endif + mt9m111->current_mode = &mt9m111_mode_data[MT9M111_MODE_SXGA_15FPS]; + mt9m111->frame_interval.numerator = 1; + mt9m111->frame_interval.denominator = mt9m111->current_mode->max_fps; + /* Second stage probe - when a capture adapter is there */ mt9m111->rect.left = MT9M111_MIN_DARK_COLS; mt9m111->rect.top = MT9M111_MIN_DARK_ROWS; diff --git a/drivers/media/i2c/ov13858.c b/drivers/media/i2c/ov13858.c index c8bbc1f52261..45bb872db3c5 100644 --- a/drivers/media/i2c/ov13858.c +++ b/drivers/media/i2c/ov13858.c @@ -1612,7 +1612,8 @@ static int ov13858_init_controls(struct ov13858 *ov13858) OV13858_NUM_OF_LINK_FREQS - 1, 0, link_freq_menu_items); - ov13858->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; + if (ov13858->link_freq) + ov13858->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; pixel_rate_max = link_freq_to_pixel_rate(link_freq_menu_items[0]); pixel_rate_min = link_freq_to_pixel_rate(link_freq_menu_items[1]); @@ -1635,7 +1636,8 @@ static int ov13858_init_controls(struct ov13858 *ov13858) ov13858->hblank = v4l2_ctrl_new_std( ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_HBLANK, hblank, hblank, 1, hblank); - ov13858->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; + if (ov13858->hblank) + ov13858->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; exposure_max = mode->vts_def - 8; ov13858->exposure = v4l2_ctrl_new_std( diff --git a/drivers/media/i2c/ov2640.c b/drivers/media/i2c/ov2640.c index 20a8853ba1e2..5d2d6735cc78 100644 --- a/drivers/media/i2c/ov2640.c +++ b/drivers/media/i2c/ov2640.c @@ -26,6 +26,7 @@ #include <linux/videodev2.h> #include <media/v4l2-device.h> +#include <media/v4l2-event.h> #include <media/v4l2-subdev.h> #include <media/v4l2-ctrls.h> #include <media/v4l2-image-sizes.h> @@ -705,6 +706,11 @@ err: return ret; } +static const char * const ov2640_test_pattern_menu[] = { + "Disabled", + "Eight Vertical Colour Bars", +}; + /* * functions */ @@ -740,6 +746,9 @@ static int ov2640_s_ctrl(struct v4l2_ctrl *ctrl) case V4L2_CID_HFLIP: val = ctrl->val ? REG04_HFLIP_IMG : 0x00; return ov2640_mask_set(client, REG04, REG04_HFLIP_IMG, val); + case V4L2_CID_TEST_PATTERN: + val = ctrl->val ? COM7_COLOR_BAR_TEST : 0x00; + return ov2640_mask_set(client, COM7, COM7_COLOR_BAR_TEST, val); } return -EINVAL; @@ -1088,6 +1097,9 @@ static const struct v4l2_ctrl_ops ov2640_ctrl_ops = { }; static const struct v4l2_subdev_core_ops ov2640_subdev_core_ops = { + .log_status = v4l2_ctrl_subdev_log_status, + .subscribe_event = v4l2_ctrl_subdev_subscribe_event, + .unsubscribe_event = v4l2_event_subdev_unsubscribe, #ifdef CONFIG_VIDEO_ADV_DEBUG .g_register = ov2640_g_register, .s_register = ov2640_s_register, @@ -1182,14 +1194,19 @@ static int ov2640_probe(struct i2c_client *client, goto err_clk; v4l2_i2c_subdev_init(&priv->subdev, client, &ov2640_subdev_ops); - priv->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + priv->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | + V4L2_SUBDEV_FL_HAS_EVENTS; mutex_init(&priv->lock); - v4l2_ctrl_handler_init(&priv->hdl, 2); + v4l2_ctrl_handler_init(&priv->hdl, 3); priv->hdl.lock = &priv->lock; v4l2_ctrl_new_std(&priv->hdl, &ov2640_ctrl_ops, V4L2_CID_VFLIP, 0, 1, 1, 0); v4l2_ctrl_new_std(&priv->hdl, &ov2640_ctrl_ops, V4L2_CID_HFLIP, 0, 1, 1, 0); + v4l2_ctrl_new_std_menu_items(&priv->hdl, &ov2640_ctrl_ops, + V4L2_CID_TEST_PATTERN, + ARRAY_SIZE(ov2640_test_pattern_menu) - 1, 0, 0, + ov2640_test_pattern_menu); priv->subdev.ctrl_handler = &priv->hdl; if (priv->hdl.error) { ret = priv->hdl.error; diff --git a/drivers/media/i2c/ov2680.c b/drivers/media/i2c/ov2680.c index 0e34e15b67b3..b10bcfabaeeb 100644 --- a/drivers/media/i2c/ov2680.c +++ b/drivers/media/i2c/ov2680.c @@ -568,10 +568,6 @@ static int ov2680_power_on(struct ov2680_dev *sensor) if (ret < 0) return ret; - ret = ov2680_mode_restore(sensor); - if (ret < 0) - goto disable; - sensor->is_enabled = true; /* Set clock lane into LP-11 state */ @@ -580,12 +576,6 @@ static int ov2680_power_on(struct ov2680_dev *sensor) ov2680_stream_disable(sensor); return 0; - -disable: - dev_err(dev, "failed to enable sensor: %d\n", ret); - ov2680_power_off(sensor); - - return ret; } static int ov2680_s_power(struct v4l2_subdev *sd, int on) @@ -606,6 +596,8 @@ static int ov2680_s_power(struct v4l2_subdev *sd, int on) ret = v4l2_ctrl_handler_setup(&sensor->ctrls.handler); if (ret < 0) return ret; + + ret = ov2680_mode_restore(sensor); } return ret; diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c index eaefdb58653b..bef3f3aae0ed 100644 --- a/drivers/media/i2c/ov5640.c +++ b/drivers/media/i2c/ov5640.c @@ -25,6 +25,7 @@ #include <media/v4l2-async.h> #include <media/v4l2-ctrls.h> #include <media/v4l2-device.h> +#include <media/v4l2-event.h> #include <media/v4l2-fwnode.h> #include <media/v4l2-subdev.h> @@ -94,9 +95,6 @@ #define OV5640_REG_SDE_CTRL5 0x5585 #define OV5640_REG_AVG_READOUT 0x56a1 -#define OV5640_SCLK2X_ROOT_DIVIDER_DEFAULT 1 -#define OV5640_SCLK_ROOT_DIVIDER_DEFAULT 2 - enum ov5640_mode_id { OV5640_MODE_QCIF_176_144 = 0, OV5640_MODE_QVGA_320_240, @@ -113,6 +111,7 @@ enum ov5640_mode_id { enum ov5640_frame_rate { OV5640_15_FPS = 0, OV5640_30_FPS, + OV5640_60_FPS, OV5640_NUM_FRAMERATES, }; @@ -141,6 +140,7 @@ MODULE_PARM_DESC(virtual_channel, static const int ov5640_framerates[] = { [OV5640_15_FPS] = 15, [OV5640_30_FPS] = 30, + [OV5640_60_FPS] = 60, }; /* regulator supplies */ @@ -261,8 +261,7 @@ static inline struct v4l2_subdev *ctrl_to_sd(struct v4l2_ctrl *ctrl) static const struct reg_value ov5640_init_setting_30fps_VGA[] = { {0x3103, 0x11, 0, 0}, {0x3008, 0x82, 0, 5}, {0x3008, 0x42, 0, 0}, {0x3103, 0x03, 0, 0}, {0x3017, 0x00, 0, 0}, {0x3018, 0x00, 0, 0}, - {0x3034, 0x18, 0, 0}, {0x3035, 0x14, 0, 0}, {0x3036, 0x38, 0, 0}, - {0x3037, 0x13, 0, 0}, {0x3630, 0x36, 0, 0}, + {0x3630, 0x36, 0, 0}, {0x3631, 0x0e, 0, 0}, {0x3632, 0xe2, 0, 0}, {0x3633, 0x12, 0, 0}, {0x3621, 0xe0, 0, 0}, {0x3704, 0xa0, 0, 0}, {0x3703, 0x5a, 0, 0}, {0x3715, 0x78, 0, 0}, {0x3717, 0x01, 0, 0}, {0x370b, 0x60, 0, 0}, @@ -344,27 +343,8 @@ static const struct reg_value ov5640_init_setting_30fps_VGA[] = { {0x3a1f, 0x14, 0, 0}, {0x3008, 0x02, 0, 0}, {0x3c00, 0x04, 0, 300}, }; -static const struct reg_value ov5640_setting_30fps_VGA_640_480[] = { - {0x3035, 0x14, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, - {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, - {0x3814, 0x31, 0, 0}, - {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, - {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0}, - {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0}, - {0x3810, 0x00, 0, 0}, - {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0}, - {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0}, - {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0}, - {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x0e, 0, 0}, - {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, - {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, - {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0}, - {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, - {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, {0x3503, 0x00, 0, 0}, -}; - -static const struct reg_value ov5640_setting_15fps_VGA_640_480[] = { - {0x3035, 0x22, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, +static const struct reg_value ov5640_setting_VGA_640_480[] = { + {0x3c07, 0x08, 0, 0}, {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, @@ -382,28 +362,8 @@ static const struct reg_value ov5640_setting_15fps_VGA_640_480[] = { {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, }; -static const struct reg_value ov5640_setting_30fps_XGA_1024_768[] = { - {0x3035, 0x14, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, - {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, - {0x3814, 0x31, 0, 0}, - {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, - {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0}, - {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0}, - {0x3810, 0x00, 0, 0}, - {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0}, - {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0}, - {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0}, - {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x0e, 0, 0}, - {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, - {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, - {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0}, - {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, - {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, {0x3503, 0x00, 0, 0}, - {0x3035, 0x12, 0, 0}, -}; - -static const struct reg_value ov5640_setting_15fps_XGA_1024_768[] = { - {0x3035, 0x22, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, +static const struct reg_value ov5640_setting_XGA_1024_768[] = { + {0x3c07, 0x08, 0, 0}, {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, @@ -421,8 +381,8 @@ static const struct reg_value ov5640_setting_15fps_XGA_1024_768[] = { {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, }; -static const struct reg_value ov5640_setting_30fps_QVGA_320_240[] = { - {0x3035, 0x14, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, +static const struct reg_value ov5640_setting_QVGA_320_240[] = { + {0x3c07, 0x08, 0, 0}, {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, @@ -440,8 +400,8 @@ static const struct reg_value ov5640_setting_30fps_QVGA_320_240[] = { {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, }; -static const struct reg_value ov5640_setting_15fps_QVGA_320_240[] = { - {0x3035, 0x22, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, +static const struct reg_value ov5640_setting_QCIF_176_144[] = { + {0x3c07, 0x08, 0, 0}, {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, @@ -459,46 +419,8 @@ static const struct reg_value ov5640_setting_15fps_QVGA_320_240[] = { {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, }; -static const struct reg_value ov5640_setting_30fps_QCIF_176_144[] = { - {0x3035, 0x14, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, - {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, - {0x3814, 0x31, 0, 0}, - {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, - {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0}, - {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0}, - {0x3810, 0x00, 0, 0}, - {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0}, - {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0}, - {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0}, - {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0}, - {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, - {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, - {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0}, - {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, - {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, -}; - -static const struct reg_value ov5640_setting_15fps_QCIF_176_144[] = { - {0x3035, 0x22, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, - {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, - {0x3814, 0x31, 0, 0}, - {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, - {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0}, - {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0}, - {0x3810, 0x00, 0, 0}, - {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0}, - {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0}, - {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0}, - {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0}, - {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, - {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, - {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0}, - {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, - {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, -}; - -static const struct reg_value ov5640_setting_30fps_NTSC_720_480[] = { - {0x3035, 0x12, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, +static const struct reg_value ov5640_setting_NTSC_720_480[] = { + {0x3c07, 0x08, 0, 0}, {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, @@ -516,27 +438,8 @@ static const struct reg_value ov5640_setting_30fps_NTSC_720_480[] = { {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, }; -static const struct reg_value ov5640_setting_15fps_NTSC_720_480[] = { - {0x3035, 0x22, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, - {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, - {0x3814, 0x31, 0, 0}, - {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, - {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0}, - {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0}, - {0x3810, 0x00, 0, 0}, - {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x3c, 0, 0}, - {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0}, - {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0}, - {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0}, - {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, - {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, - {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0}, - {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, - {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, -}; - -static const struct reg_value ov5640_setting_30fps_PAL_720_576[] = { - {0x3035, 0x12, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, +static const struct reg_value ov5640_setting_PAL_720_576[] = { + {0x3c07, 0x08, 0, 0}, {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, @@ -554,48 +457,8 @@ static const struct reg_value ov5640_setting_30fps_PAL_720_576[] = { {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, }; -static const struct reg_value ov5640_setting_15fps_PAL_720_576[] = { - {0x3035, 0x22, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, - {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, - {0x3814, 0x31, 0, 0}, - {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, - {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0}, - {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0}, - {0x3810, 0x00, 0, 0}, - {0x3811, 0x38, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0}, - {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0}, - {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0}, - {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0}, - {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, - {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, - {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0}, - {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, - {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, -}; - -static const struct reg_value ov5640_setting_30fps_720P_1280_720[] = { - {0x3008, 0x42, 0, 0}, - {0x3035, 0x21, 0, 0}, {0x3036, 0x54, 0, 0}, {0x3c07, 0x07, 0, 0}, - {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, - {0x3814, 0x31, 0, 0}, - {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, - {0x3802, 0x00, 0, 0}, {0x3803, 0xfa, 0, 0}, {0x3804, 0x0a, 0, 0}, - {0x3805, 0x3f, 0, 0}, {0x3806, 0x06, 0, 0}, {0x3807, 0xa9, 0, 0}, - {0x3810, 0x00, 0, 0}, - {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x04, 0, 0}, - {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0}, - {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x02, 0, 0}, - {0x3a03, 0xe4, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0xbc, 0, 0}, - {0x3a0a, 0x01, 0, 0}, {0x3a0b, 0x72, 0, 0}, {0x3a0e, 0x01, 0, 0}, - {0x3a0d, 0x02, 0, 0}, {0x3a14, 0x02, 0, 0}, {0x3a15, 0xe4, 0, 0}, - {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x02, 0, 0}, - {0x4407, 0x04, 0, 0}, {0x460b, 0x37, 0, 0}, {0x460c, 0x20, 0, 0}, - {0x3824, 0x04, 0, 0}, {0x5001, 0x83, 0, 0}, {0x4005, 0x1a, 0, 0}, - {0x3008, 0x02, 0, 0}, {0x3503, 0, 0, 0}, -}; - -static const struct reg_value ov5640_setting_15fps_720P_1280_720[] = { - {0x3035, 0x41, 0, 0}, {0x3036, 0x54, 0, 0}, {0x3c07, 0x07, 0, 0}, +static const struct reg_value ov5640_setting_720P_1280_720[] = { + {0x3c07, 0x07, 0, 0}, {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, @@ -613,9 +476,9 @@ static const struct reg_value ov5640_setting_15fps_720P_1280_720[] = { {0x3824, 0x04, 0, 0}, {0x5001, 0x83, 0, 0}, }; -static const struct reg_value ov5640_setting_30fps_1080P_1920_1080[] = { +static const struct reg_value ov5640_setting_1080P_1920_1080[] = { {0x3008, 0x42, 0, 0}, - {0x3035, 0x21, 0, 0}, {0x3036, 0x54, 0, 0}, {0x3c07, 0x08, 0, 0}, + {0x3c07, 0x08, 0, 0}, {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, {0x3814, 0x11, 0, 0}, {0x3815, 0x11, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, @@ -630,8 +493,8 @@ static const struct reg_value ov5640_setting_30fps_1080P_1920_1080[] = { {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, {0x4001, 0x02, 0, 0}, {0x4004, 0x06, 0, 0}, {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, - {0x3824, 0x02, 0, 0}, {0x5001, 0x83, 0, 0}, {0x3035, 0x11, 0, 0}, - {0x3036, 0x54, 0, 0}, {0x3c07, 0x07, 0, 0}, {0x3c08, 0x00, 0, 0}, + {0x3824, 0x02, 0, 0}, {0x5001, 0x83, 0, 0}, + {0x3c07, 0x07, 0, 0}, {0x3c08, 0x00, 0, 0}, {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, {0x3800, 0x01, 0, 0}, {0x3801, 0x50, 0, 0}, {0x3802, 0x01, 0, 0}, {0x3803, 0xb2, 0, 0}, {0x3804, 0x08, 0, 0}, {0x3805, 0xef, 0, 0}, @@ -643,43 +506,10 @@ static const struct reg_value ov5640_setting_30fps_1080P_1920_1080[] = { {0x3a15, 0x60, 0, 0}, {0x4713, 0x02, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x37, 0, 0}, {0x460c, 0x20, 0, 0}, {0x3824, 0x04, 0, 0}, {0x4005, 0x1a, 0, 0}, {0x3008, 0x02, 0, 0}, - {0x3503, 0, 0, 0}, -}; - -static const struct reg_value ov5640_setting_15fps_1080P_1920_1080[] = { - {0x3008, 0x42, 0, 0}, - {0x3035, 0x21, 0, 0}, {0x3036, 0x54, 0, 0}, {0x3c07, 0x08, 0, 0}, - {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, - {0x3814, 0x11, 0, 0}, - {0x3815, 0x11, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, - {0x3802, 0x00, 0, 0}, {0x3803, 0x00, 0, 0}, {0x3804, 0x0a, 0, 0}, - {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9f, 0, 0}, - {0x3810, 0x00, 0, 0}, - {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x04, 0, 0}, - {0x3618, 0x04, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x21, 0, 0}, - {0x3709, 0x12, 0, 0}, {0x370c, 0x00, 0, 0}, {0x3a02, 0x03, 0, 0}, - {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0}, - {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, - {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, - {0x4001, 0x02, 0, 0}, {0x4004, 0x06, 0, 0}, {0x4713, 0x03, 0, 0}, - {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, - {0x3824, 0x02, 0, 0}, {0x5001, 0x83, 0, 0}, {0x3035, 0x21, 0, 0}, - {0x3036, 0x54, 0, 1}, {0x3c07, 0x07, 0, 0}, {0x3c08, 0x00, 0, 0}, - {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, - {0x3800, 0x01, 0, 0}, {0x3801, 0x50, 0, 0}, {0x3802, 0x01, 0, 0}, - {0x3803, 0xb2, 0, 0}, {0x3804, 0x08, 0, 0}, {0x3805, 0xef, 0, 0}, - {0x3806, 0x05, 0, 0}, {0x3807, 0xf1, 0, 0}, - {0x3612, 0x2b, 0, 0}, {0x3708, 0x64, 0, 0}, - {0x3a02, 0x04, 0, 0}, {0x3a03, 0x60, 0, 0}, {0x3a08, 0x01, 0, 0}, - {0x3a09, 0x50, 0, 0}, {0x3a0a, 0x01, 0, 0}, {0x3a0b, 0x18, 0, 0}, - {0x3a0e, 0x03, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x04, 0, 0}, - {0x3a15, 0x60, 0, 0}, {0x4713, 0x02, 0, 0}, {0x4407, 0x04, 0, 0}, - {0x460b, 0x37, 0, 0}, {0x460c, 0x20, 0, 0}, {0x3824, 0x04, 0, 0}, - {0x4005, 0x1a, 0, 0}, {0x3008, 0x02, 0, 0}, {0x3503, 0, 0, 0}, }; -static const struct reg_value ov5640_setting_15fps_QSXGA_2592_1944[] = { - {0x3035, 0x21, 0, 0}, {0x3036, 0x54, 0, 0}, {0x3c07, 0x08, 0, 0}, +static const struct reg_value ov5640_setting_QSXGA_2592_1944[] = { + {0x3c07, 0x08, 0, 0}, {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, {0x3814, 0x11, 0, 0}, {0x3815, 0x11, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, @@ -705,79 +535,43 @@ static const struct ov5640_mode_info ov5640_mode_init_data = { }; static const struct ov5640_mode_info -ov5640_mode_data[OV5640_NUM_FRAMERATES][OV5640_NUM_MODES] = { - { - {OV5640_MODE_QCIF_176_144, SUBSAMPLING, - 176, 1896, 144, 984, - ov5640_setting_15fps_QCIF_176_144, - ARRAY_SIZE(ov5640_setting_15fps_QCIF_176_144)}, - {OV5640_MODE_QVGA_320_240, SUBSAMPLING, - 320, 1896, 240, 984, - ov5640_setting_15fps_QVGA_320_240, - ARRAY_SIZE(ov5640_setting_15fps_QVGA_320_240)}, - {OV5640_MODE_VGA_640_480, SUBSAMPLING, - 640, 1896, 480, 1080, - ov5640_setting_15fps_VGA_640_480, - ARRAY_SIZE(ov5640_setting_15fps_VGA_640_480)}, - {OV5640_MODE_NTSC_720_480, SUBSAMPLING, - 720, 1896, 480, 984, - ov5640_setting_15fps_NTSC_720_480, - ARRAY_SIZE(ov5640_setting_15fps_NTSC_720_480)}, - {OV5640_MODE_PAL_720_576, SUBSAMPLING, - 720, 1896, 576, 984, - ov5640_setting_15fps_PAL_720_576, - ARRAY_SIZE(ov5640_setting_15fps_PAL_720_576)}, - {OV5640_MODE_XGA_1024_768, SUBSAMPLING, - 1024, 1896, 768, 1080, - ov5640_setting_15fps_XGA_1024_768, - ARRAY_SIZE(ov5640_setting_15fps_XGA_1024_768)}, - {OV5640_MODE_720P_1280_720, SUBSAMPLING, - 1280, 1892, 720, 740, - ov5640_setting_15fps_720P_1280_720, - ARRAY_SIZE(ov5640_setting_15fps_720P_1280_720)}, - {OV5640_MODE_1080P_1920_1080, SCALING, - 1920, 2500, 1080, 1120, - ov5640_setting_15fps_1080P_1920_1080, - ARRAY_SIZE(ov5640_setting_15fps_1080P_1920_1080)}, - {OV5640_MODE_QSXGA_2592_1944, SCALING, - 2592, 2844, 1944, 1968, - ov5640_setting_15fps_QSXGA_2592_1944, - ARRAY_SIZE(ov5640_setting_15fps_QSXGA_2592_1944)}, - }, { - {OV5640_MODE_QCIF_176_144, SUBSAMPLING, - 176, 1896, 144, 984, - ov5640_setting_30fps_QCIF_176_144, - ARRAY_SIZE(ov5640_setting_30fps_QCIF_176_144)}, - {OV5640_MODE_QVGA_320_240, SUBSAMPLING, - 320, 1896, 240, 984, - ov5640_setting_30fps_QVGA_320_240, - ARRAY_SIZE(ov5640_setting_30fps_QVGA_320_240)}, - {OV5640_MODE_VGA_640_480, SUBSAMPLING, - 640, 1896, 480, 1080, - ov5640_setting_30fps_VGA_640_480, - ARRAY_SIZE(ov5640_setting_30fps_VGA_640_480)}, - {OV5640_MODE_NTSC_720_480, SUBSAMPLING, - 720, 1896, 480, 984, - ov5640_setting_30fps_NTSC_720_480, - ARRAY_SIZE(ov5640_setting_30fps_NTSC_720_480)}, - {OV5640_MODE_PAL_720_576, SUBSAMPLING, - 720, 1896, 576, 984, - ov5640_setting_30fps_PAL_720_576, - ARRAY_SIZE(ov5640_setting_30fps_PAL_720_576)}, - {OV5640_MODE_XGA_1024_768, SUBSAMPLING, - 1024, 1896, 768, 1080, - ov5640_setting_30fps_XGA_1024_768, - ARRAY_SIZE(ov5640_setting_30fps_XGA_1024_768)}, - {OV5640_MODE_720P_1280_720, SUBSAMPLING, - 1280, 1892, 720, 740, - ov5640_setting_30fps_720P_1280_720, - ARRAY_SIZE(ov5640_setting_30fps_720P_1280_720)}, - {OV5640_MODE_1080P_1920_1080, SCALING, - 1920, 2500, 1080, 1120, - ov5640_setting_30fps_1080P_1920_1080, - ARRAY_SIZE(ov5640_setting_30fps_1080P_1920_1080)}, - {OV5640_MODE_QSXGA_2592_1944, -1, 0, 0, 0, 0, NULL, 0}, - }, +ov5640_mode_data[OV5640_NUM_MODES] = { + {OV5640_MODE_QCIF_176_144, SUBSAMPLING, + 176, 1896, 144, 984, + ov5640_setting_QCIF_176_144, + ARRAY_SIZE(ov5640_setting_QCIF_176_144)}, + {OV5640_MODE_QVGA_320_240, SUBSAMPLING, + 320, 1896, 240, 984, + ov5640_setting_QVGA_320_240, + ARRAY_SIZE(ov5640_setting_QVGA_320_240)}, + {OV5640_MODE_VGA_640_480, SUBSAMPLING, + 640, 1896, 480, 1080, + ov5640_setting_VGA_640_480, + ARRAY_SIZE(ov5640_setting_VGA_640_480)}, + {OV5640_MODE_NTSC_720_480, SUBSAMPLING, + 720, 1896, 480, 984, + ov5640_setting_NTSC_720_480, + ARRAY_SIZE(ov5640_setting_NTSC_720_480)}, + {OV5640_MODE_PAL_720_576, SUBSAMPLING, + 720, 1896, 576, 984, + ov5640_setting_PAL_720_576, + ARRAY_SIZE(ov5640_setting_PAL_720_576)}, + {OV5640_MODE_XGA_1024_768, SUBSAMPLING, + 1024, 1896, 768, 1080, + ov5640_setting_XGA_1024_768, + ARRAY_SIZE(ov5640_setting_XGA_1024_768)}, + {OV5640_MODE_720P_1280_720, SUBSAMPLING, + 1280, 1892, 720, 740, + ov5640_setting_720P_1280_720, + ARRAY_SIZE(ov5640_setting_720P_1280_720)}, + {OV5640_MODE_1080P_1920_1080, SCALING, + 1920, 2500, 1080, 1120, + ov5640_setting_1080P_1920_1080, + ARRAY_SIZE(ov5640_setting_1080P_1920_1080)}, + {OV5640_MODE_QSXGA_2592_1944, SCALING, + 2592, 2844, 1944, 1968, + ov5640_setting_QSXGA_2592_1944, + ARRAY_SIZE(ov5640_setting_QSXGA_2592_1944)}, }; static int ov5640_init_slave_id(struct ov5640_dev *sensor) @@ -909,6 +703,333 @@ static int ov5640_mod_reg(struct ov5640_dev *sensor, u16 reg, return ov5640_write_reg(sensor, reg, val); } +/* + * After trying the various combinations, reading various + * documentations spreaded around the net, and from the various + * feedback, the clock tree is probably as follows: + * + * +--------------+ + * | Ext. Clock | + * +-+------------+ + * | +----------+ + * +->| PLL1 | - reg 0x3036, for the multiplier + * +-+--------+ - reg 0x3037, bits 0-3 for the pre-divider + * | +--------------+ + * +->| System Clock | - reg 0x3035, bits 4-7 + * +-+------------+ + * | +--------------+ + * +->| MIPI Divider | - reg 0x3035, bits 0-3 + * | +-+------------+ + * | +----------------> MIPI SCLK + * | + +-----+ + * | +->| / 2 |-------> MIPI BIT CLK + * | +-----+ + * | +--------------+ + * +->| PLL Root Div | - reg 0x3037, bit 4 + * +-+------------+ + * | +---------+ + * +->| Bit Div | - reg 0x3035, bits 0-3 + * +-+-------+ + * | +-------------+ + * +->| SCLK Div | - reg 0x3108, bits 0-1 + * | +-+-----------+ + * | +---------------> SCLK + * | +-------------+ + * +->| SCLK 2X Div | - reg 0x3108, bits 2-3 + * | +-+-----------+ + * | +---------------> SCLK 2X + * | +-------------+ + * +->| PCLK Div | - reg 0x3108, bits 4-5 + * ++------------+ + * + +-----------+ + * +->| P_DIV | - reg 0x3035, bits 0-3 + * +-----+-----+ + * +------------> PCLK + * + * This is deviating from the datasheet at least for the register + * 0x3108, since it's said here that the PCLK would be clocked from + * the PLL. + * + * There seems to be also (unverified) constraints: + * - the PLL pre-divider output rate should be in the 4-27MHz range + * - the PLL multiplier output rate should be in the 500-1000MHz range + * - PCLK >= SCLK * 2 in YUV, >= SCLK in Raw or JPEG + * + * In the two latter cases, these constraints are met since our + * factors are hardcoded. If we were to change that, we would need to + * take this into account. The only varying parts are the PLL + * multiplier and the system clock divider, which are shared between + * all these clocks so won't cause any issue. + */ + +/* + * This is supposed to be ranging from 1 to 8, but the value is always + * set to 3 in the vendor kernels. + */ +#define OV5640_PLL_PREDIV 3 + +#define OV5640_PLL_MULT_MIN 4 +#define OV5640_PLL_MULT_MAX 252 + +/* + * This is supposed to be ranging from 1 to 16, but the value is + * always set to either 1 or 2 in the vendor kernels. + */ +#define OV5640_SYSDIV_MIN 1 +#define OV5640_SYSDIV_MAX 16 + +/* + * Hardcode these values for scaler and non-scaler modes. + * FIXME: to be re-calcualted for 1 data lanes setups + */ +#define OV5640_MIPI_DIV_PCLK 2 +#define OV5640_MIPI_DIV_SCLK 1 + +/* + * This is supposed to be ranging from 1 to 2, but the value is always + * set to 2 in the vendor kernels. + */ +#define OV5640_PLL_ROOT_DIV 2 +#define OV5640_PLL_CTRL3_PLL_ROOT_DIV_2 BIT(4) + +/* + * We only supports 8-bit formats at the moment + */ +#define OV5640_BIT_DIV 2 +#define OV5640_PLL_CTRL0_MIPI_MODE_8BIT 0x08 + +/* + * This is supposed to be ranging from 1 to 8, but the value is always + * set to 2 in the vendor kernels. + */ +#define OV5640_SCLK_ROOT_DIV 2 + +/* + * This is hardcoded so that the consistency is maintained between SCLK and + * SCLK 2x. + */ +#define OV5640_SCLK2X_ROOT_DIV (OV5640_SCLK_ROOT_DIV / 2) + +/* + * This is supposed to be ranging from 1 to 8, but the value is always + * set to 1 in the vendor kernels. + */ +#define OV5640_PCLK_ROOT_DIV 1 +#define OV5640_PLL_SYS_ROOT_DIVIDER_BYPASS 0x00 + +static unsigned long ov5640_compute_sys_clk(struct ov5640_dev *sensor, + u8 pll_prediv, u8 pll_mult, + u8 sysdiv) +{ + unsigned long sysclk = sensor->xclk_freq / pll_prediv * pll_mult; + + /* PLL1 output cannot exceed 1GHz. */ + if (sysclk / 1000000 > 1000) + return 0; + + return sysclk / sysdiv; +} + +static unsigned long ov5640_calc_sys_clk(struct ov5640_dev *sensor, + unsigned long rate, + u8 *pll_prediv, u8 *pll_mult, + u8 *sysdiv) +{ + unsigned long best = ~0; + u8 best_sysdiv = 1, best_mult = 1; + u8 _sysdiv, _pll_mult; + + for (_sysdiv = OV5640_SYSDIV_MIN; + _sysdiv <= OV5640_SYSDIV_MAX; + _sysdiv++) { + for (_pll_mult = OV5640_PLL_MULT_MIN; + _pll_mult <= OV5640_PLL_MULT_MAX; + _pll_mult++) { + unsigned long _rate; + + /* + * The PLL multiplier cannot be odd if above + * 127. + */ + if (_pll_mult > 127 && (_pll_mult % 2)) + continue; + + _rate = ov5640_compute_sys_clk(sensor, + OV5640_PLL_PREDIV, + _pll_mult, _sysdiv); + + /* + * We have reached the maximum allowed PLL1 output, + * increase sysdiv. + */ + if (!rate) + break; + + /* + * Prefer rates above the expected clock rate than + * below, even if that means being less precise. + */ + if (_rate < rate) + continue; + + if (abs(rate - _rate) < abs(rate - best)) { + best = _rate; + best_sysdiv = _sysdiv; + best_mult = _pll_mult; + } + + if (_rate == rate) + goto out; + } + } + +out: + *sysdiv = best_sysdiv; + *pll_prediv = OV5640_PLL_PREDIV; + *pll_mult = best_mult; + + return best; +} + +/* + * ov5640_set_mipi_pclk() - Calculate the clock tree configuration values + * for the MIPI CSI-2 output. + * + * @rate: The requested bandwidth per lane in bytes per second. + * 'Bandwidth Per Lane' is calculated as: + * bpl = HTOT * VTOT * FPS * bpp / num_lanes; + * + * This function use the requested bandwidth to calculate: + * - sample_rate = bpl / (bpp / num_lanes); + * = bpl / (PLL_RDIV * BIT_DIV * PCLK_DIV * MIPI_DIV / num_lanes); + * + * - mipi_sclk = bpl / MIPI_DIV / 2; ( / 2 is for CSI-2 DDR) + * + * with these fixed parameters: + * PLL_RDIV = 2; + * BIT_DIVIDER = 2; (MIPI_BIT_MODE == 8 ? 2 : 2,5); + * PCLK_DIV = 1; + * + * The MIPI clock generation differs for modes that use the scaler and modes + * that do not. In case the scaler is in use, the MIPI_SCLK generates the MIPI + * BIT CLk, and thus: + * + * - mipi_sclk = bpl / MIPI_DIV / 2; + * MIPI_DIV = 1; + * + * For modes that do not go through the scaler, the MIPI BIT CLOCK is generated + * from the pixel clock, and thus: + * + * - sample_rate = bpl / (bpp / num_lanes); + * = bpl / (2 * 2 * 1 * MIPI_DIV / num_lanes); + * = bpl / (4 * MIPI_DIV / num_lanes); + * - MIPI_DIV = bpp / (4 * num_lanes); + * + * FIXME: this have been tested with 16bpp and 2 lanes setup only. + * MIPI_DIV is fixed to value 2, but it -might- be changed according to the + * above formula for setups with 1 lane or image formats with different bpp. + * + * FIXME: this deviates from the sensor manual documentation which is quite + * thin on the MIPI clock tree generation part. + */ +static int ov5640_set_mipi_pclk(struct ov5640_dev *sensor, + unsigned long rate) +{ + const struct ov5640_mode_info *mode = sensor->current_mode; + u8 prediv, mult, sysdiv; + u8 mipi_div; + int ret; + + /* + * 1280x720 is reported to use 'SUBSAMPLING' only, + * but according to the sensor manual it goes through the + * scaler before subsampling. + */ + if (mode->dn_mode == SCALING || + (mode->id == OV5640_MODE_720P_1280_720)) + mipi_div = OV5640_MIPI_DIV_SCLK; + else + mipi_div = OV5640_MIPI_DIV_PCLK; + + ov5640_calc_sys_clk(sensor, rate, &prediv, &mult, &sysdiv); + + ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL0, + 0x0f, OV5640_PLL_CTRL0_MIPI_MODE_8BIT); + + ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL1, + 0xff, sysdiv << 4 | mipi_div); + if (ret) + return ret; + + ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL2, 0xff, mult); + if (ret) + return ret; + + ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL3, + 0x1f, OV5640_PLL_CTRL3_PLL_ROOT_DIV_2 | prediv); + if (ret) + return ret; + + return ov5640_mod_reg(sensor, OV5640_REG_SYS_ROOT_DIVIDER, + 0x30, OV5640_PLL_SYS_ROOT_DIVIDER_BYPASS); +} + +static unsigned long ov5640_calc_pclk(struct ov5640_dev *sensor, + unsigned long rate, + u8 *pll_prediv, u8 *pll_mult, u8 *sysdiv, + u8 *pll_rdiv, u8 *bit_div, u8 *pclk_div) +{ + unsigned long _rate = rate * OV5640_PLL_ROOT_DIV * OV5640_BIT_DIV * + OV5640_PCLK_ROOT_DIV; + + _rate = ov5640_calc_sys_clk(sensor, _rate, pll_prediv, pll_mult, + sysdiv); + *pll_rdiv = OV5640_PLL_ROOT_DIV; + *bit_div = OV5640_BIT_DIV; + *pclk_div = OV5640_PCLK_ROOT_DIV; + + return _rate / *pll_rdiv / *bit_div / *pclk_div; +} + +static int ov5640_set_dvp_pclk(struct ov5640_dev *sensor, unsigned long rate) +{ + u8 prediv, mult, sysdiv, pll_rdiv, bit_div, pclk_div; + int ret; + + ov5640_calc_pclk(sensor, rate, &prediv, &mult, &sysdiv, &pll_rdiv, + &bit_div, &pclk_div); + + if (bit_div == 2) + bit_div = 8; + + ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL0, + 0x0f, bit_div); + if (ret) + return ret; + + /* + * We need to set sysdiv according to the clock, and to clear + * the MIPI divider. + */ + ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL1, + 0xff, sysdiv << 4); + if (ret) + return ret; + + ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL2, + 0xff, mult); + if (ret) + return ret; + + ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL3, + 0x1f, prediv | ((pll_rdiv - 1) << 4)); + if (ret) + return ret; + + return ov5640_mod_reg(sensor, OV5640_REG_SYS_ROOT_DIVIDER, 0x30, + (ilog2(pclk_div) << 4)); +} + /* download ov5640 settings to sensor through i2c */ static int ov5640_set_timings(struct ov5640_dev *sensor, const struct ov5640_mode_info *mode) @@ -1062,16 +1183,6 @@ static int ov5640_set_stream_dvp(struct ov5640_dev *sensor, bool on) if (on) { /* - * reset MIPI PCLK/SERCLK divider - * - * SC PLL CONTRL1 0 - * - [3..0]: MIPI PCLK/SERCLK divider - */ - ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL1, 0x0f, 0); - if (ret) - return ret; - - /* * configure parallel port control lines polarity * * POLARITY CTRL0 @@ -1444,8 +1555,8 @@ ov5640_find_mode(struct ov5640_dev *sensor, enum ov5640_frame_rate fr, { const struct ov5640_mode_info *mode; - mode = v4l2_find_nearest_size(ov5640_mode_data[fr], - ARRAY_SIZE(ov5640_mode_data[fr]), + mode = v4l2_find_nearest_size(ov5640_mode_data, + ARRAY_SIZE(ov5640_mode_data), hact, vact, width, height); @@ -1453,6 +1564,11 @@ ov5640_find_mode(struct ov5640_dev *sensor, enum ov5640_frame_rate fr, (!nearest && (mode->hact != width || mode->vact != height))) return NULL; + /* Only 640x480 can operate at 60fps (for now) */ + if (fr == OV5640_60_FPS && + !(mode->hact == 640 && mode->vact == 480)) + return NULL; + return mode; } @@ -1637,6 +1753,7 @@ static int ov5640_set_mode(struct ov5640_dev *sensor) enum ov5640_downsize_mode dn_mode, orig_dn_mode; bool auto_gain = sensor->ctrls.auto_gain->val == 1; bool auto_exp = sensor->ctrls.auto_exp->val == V4L2_EXPOSURE_AUTO; + unsigned long rate; int ret; dn_mode = mode->dn_mode; @@ -1655,6 +1772,23 @@ static int ov5640_set_mode(struct ov5640_dev *sensor) goto restore_auto_gain; } + /* + * All the formats we support have 16 bits per pixel, seems to require + * the same rate than YUV, so we can just use 16 bpp all the time. + */ + rate = mode->vtot * mode->htot * 16; + rate *= ov5640_framerates[sensor->current_fr]; + if (sensor->ep.bus_type == V4L2_MBUS_CSI2_DPHY) { + rate = rate / sensor->ep.bus.mipi_csi2.num_data_lanes; + ret = ov5640_set_mipi_pclk(sensor, rate); + } else { + rate = rate / sensor->ep.bus.parallel.bus_width; + ret = ov5640_set_dvp_pclk(sensor, rate); + } + + if (ret < 0) + return 0; + if ((dn_mode == SUBSAMPLING && orig_dn_mode == SCALING) || (dn_mode == SCALING && orig_dn_mode == SUBSAMPLING)) { /* @@ -1724,8 +1858,8 @@ static int ov5640_restore_mode(struct ov5640_dev *sensor) sensor->last_mode = &ov5640_mode_init_data; ret = ov5640_mod_reg(sensor, OV5640_REG_SYS_ROOT_DIVIDER, 0x3f, - (ilog2(OV5640_SCLK2X_ROOT_DIVIDER_DEFAULT) << 2) | - ilog2(OV5640_SCLK_ROOT_DIVIDER_DEFAULT)); + (ilog2(OV5640_SCLK2X_ROOT_DIV) << 2) | + ilog2(OV5640_SCLK_ROOT_DIV)); if (ret) return ret; @@ -1925,34 +2059,39 @@ static int ov5640_try_frame_interval(struct ov5640_dev *sensor, u32 width, u32 height) { const struct ov5640_mode_info *mode; - u32 minfps, maxfps, fps; - int ret; + enum ov5640_frame_rate rate = OV5640_30_FPS; + int minfps, maxfps, best_fps, fps; + int i; minfps = ov5640_framerates[OV5640_15_FPS]; - maxfps = ov5640_framerates[OV5640_30_FPS]; + maxfps = ov5640_framerates[OV5640_60_FPS]; if (fi->numerator == 0) { fi->denominator = maxfps; fi->numerator = 1; - return OV5640_30_FPS; + rate = OV5640_60_FPS; + goto find_mode; } - fps = DIV_ROUND_CLOSEST(fi->denominator, fi->numerator); + fps = clamp_val(DIV_ROUND_CLOSEST(fi->denominator, fi->numerator), + minfps, maxfps); - fi->numerator = 1; - if (fps > maxfps) - fi->denominator = maxfps; - else if (fps < minfps) - fi->denominator = minfps; - else if (2 * fps >= 2 * minfps + (maxfps - minfps)) - fi->denominator = maxfps; - else - fi->denominator = minfps; + best_fps = minfps; + for (i = 0; i < ARRAY_SIZE(ov5640_framerates); i++) { + int curr_fps = ov5640_framerates[i]; - ret = (fi->denominator == minfps) ? OV5640_15_FPS : OV5640_30_FPS; + if (abs(curr_fps - fps) < abs(best_fps - fps)) { + best_fps = curr_fps; + rate = i; + } + } - mode = ov5640_find_mode(sensor, ret, width, height, false); - return mode ? ret : -EINVAL; + fi->numerator = 1; + fi->denominator = best_fps; + +find_mode: + mode = ov5640_find_mode(sensor, rate, width, height, false); + return mode ? rate : -EINVAL; } static int ov5640_get_fmt(struct v4l2_subdev *sd, @@ -2020,6 +2159,7 @@ static int ov5640_set_fmt(struct v4l2_subdev *sd, struct ov5640_dev *sensor = to_ov5640_dev(sd); const struct ov5640_mode_info *new_mode; struct v4l2_mbus_framefmt *mbus_fmt = &format->format; + struct v4l2_mbus_framefmt *fmt; int ret; if (format->pad != 0) @@ -2037,22 +2177,20 @@ static int ov5640_set_fmt(struct v4l2_subdev *sd, if (ret) goto out; - if (format->which == V4L2_SUBDEV_FORMAT_TRY) { - struct v4l2_mbus_framefmt *fmt = - v4l2_subdev_get_try_format(sd, cfg, 0); + if (format->which == V4L2_SUBDEV_FORMAT_TRY) + fmt = v4l2_subdev_get_try_format(sd, cfg, 0); + else + fmt = &sensor->fmt; - *fmt = *mbus_fmt; - goto out; - } + *fmt = *mbus_fmt; if (new_mode != sensor->current_mode) { sensor->current_mode = new_mode; sensor->pending_mode_change = true; } - if (mbus_fmt->code != sensor->fmt.code) { - sensor->fmt = *mbus_fmt; + if (mbus_fmt->code != sensor->fmt.code) sensor->pending_fmt_change = true; - } + out: mutex_unlock(&sensor->lock); return ret; @@ -2502,10 +2640,10 @@ static int ov5640_enum_frame_size(struct v4l2_subdev *sd, return -EINVAL; fse->min_width = - ov5640_mode_data[0][fse->index].hact; + ov5640_mode_data[fse->index].hact; fse->max_width = fse->min_width; fse->min_height = - ov5640_mode_data[0][fse->index].vact; + ov5640_mode_data[fse->index].vact; fse->max_height = fse->min_height; return 0; @@ -2570,8 +2708,11 @@ static int ov5640_s_frame_interval(struct v4l2_subdev *sd, frame_rate = ov5640_try_frame_interval(sensor, &fi->interval, mode->hact, mode->vact); - if (frame_rate < 0) - frame_rate = OV5640_15_FPS; + if (frame_rate < 0) { + /* Always return a valid frame interval value */ + fi->interval = sensor->frame_interval; + goto out; + } mode = ov5640_find_mode(sensor, frame_rate, mode->hact, mode->vact, true); @@ -2641,6 +2782,9 @@ out: static const struct v4l2_subdev_core_ops ov5640_core_ops = { .s_power = ov5640_s_power, + .log_status = v4l2_ctrl_subdev_log_status, + .subscribe_event = v4l2_ctrl_subdev_subscribe_event, + .unsubscribe_event = v4l2_event_subdev_unsubscribe, }; static const struct v4l2_subdev_video_ops ov5640_video_ops = { @@ -2736,7 +2880,7 @@ static int ov5640_probe(struct i2c_client *client, sensor->frame_interval.denominator = ov5640_framerates[OV5640_30_FPS]; sensor->current_fr = OV5640_30_FPS; sensor->current_mode = - &ov5640_mode_data[OV5640_30_FPS][OV5640_MODE_VGA_640_480]; + &ov5640_mode_data[OV5640_MODE_VGA_640_480]; sensor->last_mode = sensor->current_mode; sensor->ae_target = 52; @@ -2795,7 +2939,8 @@ static int ov5640_probe(struct i2c_client *client, v4l2_i2c_subdev_init(&sensor->sd, client, &ov5640_subdev_ops); - sensor->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + sensor->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | + V4L2_SUBDEV_FL_HAS_EVENTS; sensor->pad.flags = MEDIA_PAD_FL_SOURCE; sensor->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; ret = media_entity_pads_init(&sensor->sd.entity, 1, &sensor->pad); diff --git a/drivers/media/i2c/ov5645.c b/drivers/media/i2c/ov5645.c index 5eba8dd7222b..785f326ac519 100644 --- a/drivers/media/i2c/ov5645.c +++ b/drivers/media/i2c/ov5645.c @@ -886,7 +886,7 @@ static int ov5645_s_ctrl(struct v4l2_ctrl *ctrl) return ret; } -static struct v4l2_ctrl_ops ov5645_ctrl_ops = { +static const struct v4l2_ctrl_ops ov5645_ctrl_ops = { .s_ctrl = ov5645_s_ctrl, }; diff --git a/drivers/media/i2c/ov7670.c b/drivers/media/i2c/ov7670.c index bc68a3a5b4ec..a70a6ff7b36e 100644 --- a/drivers/media/i2c/ov7670.c +++ b/drivers/media/i2c/ov7670.c @@ -20,6 +20,7 @@ #include <linux/gpio.h> #include <linux/gpio/consumer.h> #include <media/v4l2-device.h> +#include <media/v4l2-event.h> #include <media/v4l2-ctrls.h> #include <media/v4l2-fwnode.h> #include <media/v4l2-mediabus.h> @@ -1651,6 +1652,9 @@ static int ov7670_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) static const struct v4l2_subdev_core_ops ov7670_core_ops = { .reset = ov7670_reset, .init = ov7670_init, + .log_status = v4l2_ctrl_subdev_log_status, + .subscribe_event = v4l2_ctrl_subdev_subscribe_event, + .unsubscribe_event = v4l2_event_subdev_unsubscribe, #ifdef CONFIG_VIDEO_ADV_DEBUG .g_register = ov7670_g_register, .s_register = ov7670_s_register, @@ -1773,7 +1777,7 @@ static int ov7670_probe(struct i2c_client *client, #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API sd->internal_ops = &ov7670_subdev_internal_ops; - sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; #endif info->clock_speed = 30; /* default: a guess */ diff --git a/drivers/media/i2c/ov772x.c b/drivers/media/i2c/ov772x.c index fefff7fd7d68..2e9a758736a1 100644 --- a/drivers/media/i2c/ov772x.c +++ b/drivers/media/i2c/ov772x.c @@ -30,6 +30,7 @@ #include <media/v4l2-ctrls.h> #include <media/v4l2-device.h> +#include <media/v4l2-event.h> #include <media/v4l2-image-sizes.h> #include <media/v4l2-subdev.h> @@ -1287,6 +1288,9 @@ static const struct v4l2_ctrl_ops ov772x_ctrl_ops = { }; static const struct v4l2_subdev_core_ops ov772x_subdev_core_ops = { + .log_status = v4l2_ctrl_subdev_log_status, + .subscribe_event = v4l2_ctrl_subdev_subscribe_event, + .unsubscribe_event = v4l2_event_subdev_unsubscribe, #ifdef CONFIG_VIDEO_ADV_DEBUG .g_register = ov772x_g_register, .s_register = ov772x_s_register, @@ -1379,7 +1383,8 @@ static int ov772x_probe(struct i2c_client *client, mutex_init(&priv->lock); v4l2_i2c_subdev_init(&priv->subdev, client, &ov772x_subdev_ops); - priv->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + priv->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | + V4L2_SUBDEV_FL_HAS_EVENTS; v4l2_ctrl_handler_init(&priv->hdl, 3); /* Use our mutex for the controls */ priv->hdl.lock = &priv->lock; diff --git a/drivers/media/i2c/ov7740.c b/drivers/media/i2c/ov7740.c index 6e9c233cfbe3..177688afd9a6 100644 --- a/drivers/media/i2c/ov7740.c +++ b/drivers/media/i2c/ov7740.c @@ -322,7 +322,7 @@ static int ov7740_set_power(struct ov7740 *ov7740, int on) return 0; } -static struct v4l2_subdev_core_ops ov7740_subdev_core_ops = { +static const struct v4l2_subdev_core_ops ov7740_subdev_core_ops = { .log_status = v4l2_ctrl_subdev_log_status, #ifdef CONFIG_VIDEO_ADV_DEBUG .g_register = ov7740_get_register, @@ -648,7 +648,7 @@ static int ov7740_s_frame_interval(struct v4l2_subdev *sd, return 0; } -static struct v4l2_subdev_video_ops ov7740_subdev_video_ops = { +static const struct v4l2_subdev_video_ops ov7740_subdev_video_ops = { .s_stream = ov7740_set_stream, .s_frame_interval = ov7740_s_frame_interval, .g_frame_interval = ov7740_g_frame_interval, diff --git a/drivers/media/i2c/tc358743.c b/drivers/media/i2c/tc358743.c index 22cafc07de25..bc2e35e5ce61 100644 --- a/drivers/media/i2c/tc358743.c +++ b/drivers/media/i2c/tc358743.c @@ -59,7 +59,7 @@ static const struct v4l2_dv_timings_cap tc358743_timings_cap = { /* keep this initialization for compatibility with GCC < 4.4.6 */ .reserved = { 0 }, /* Pixel clock from REF_01 p. 20. Min/max height/width are unknown */ - V4L2_INIT_BT_TIMINGS(1, 10000, 1, 10000, 0, 165000000, + V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 13000000, 165000000, V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, V4L2_DV_BT_CAP_PROGRESSIVE | diff --git a/drivers/media/i2c/tda7432.c b/drivers/media/i2c/tda7432.c index 9b4f21237810..06a78c2cdaab 100644 --- a/drivers/media/i2c/tda7432.c +++ b/drivers/media/i2c/tda7432.c @@ -19,7 +19,7 @@ * * loudness - set between 0 and 15 for varying degrees of loudness effect * - * maxvol - set maximium volume to +20db (1), default is 0db(0) + * maxvol - set maximum volume to +20db (1), default is 0db(0) */ #include <linux/module.h> @@ -53,7 +53,7 @@ MODULE_PARM_DESC(debug, "Set debugging level from 0 to 3. Default is off(0)."); module_param(loudness, int, S_IRUGO); MODULE_PARM_DESC(loudness, "Turn loudness on(1) else off(0). Default is off(0)."); module_param(maxvol, int, S_IRUGO | S_IWUSR); -MODULE_PARM_DESC(maxvol, "Set maximium volume to +20dB(0) else +0dB(1). Default is +20dB(0)."); +MODULE_PARM_DESC(maxvol, "Set maximum volume to +20dB(0) else +0dB(1). Default is +20dB(0)."); /* Structure of address and subaddresses for the tda7432 */ diff --git a/drivers/media/i2c/ths8200.c b/drivers/media/i2c/ths8200.c index 498ad2368cbc..f5ee28058ea2 100644 --- a/drivers/media/i2c/ths8200.c +++ b/drivers/media/i2c/ths8200.c @@ -49,7 +49,7 @@ static const struct v4l2_dv_timings_cap ths8200_timings_cap = { .type = V4L2_DV_BT_656_1120, /* keep this initialization for compatibility with GCC < 4.4.6 */ .reserved = { 0 }, - V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1080, 25000000, 148500000, + V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1080, 25000000, 148500000, V4L2_DV_BT_STD_CEA861, V4L2_DV_BT_CAP_PROGRESSIVE) }; diff --git a/drivers/media/i2c/tvp5150.c b/drivers/media/i2c/tvp5150.c index 0e91b9949c3a..eaddd977ba40 100644 --- a/drivers/media/i2c/tvp5150.c +++ b/drivers/media/i2c/tvp5150.c @@ -1790,7 +1790,7 @@ static int tvp5150_probe(struct i2c_client *c, tvp5150_isr, IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "tvp5150", core); if (res) - return res; + goto err; } res = v4l2_async_register_subdev(sd); diff --git a/drivers/media/i2c/video-i2c.c b/drivers/media/i2c/video-i2c.c index 4d49af86c15e..01dcf179f203 100644 --- a/drivers/media/i2c/video-i2c.c +++ b/drivers/media/i2c/video-i2c.c @@ -17,6 +17,8 @@ #include <linux/module.h> #include <linux/mutex.h> #include <linux/of_device.h> +#include <linux/pm_runtime.h> +#include <linux/regmap.h> #include <linux/sched.h> #include <linux/slab.h> #include <linux/videodev2.h> @@ -38,7 +40,7 @@ struct video_i2c_buffer { }; struct video_i2c_data { - struct i2c_client *client; + struct regmap *regmap; const struct video_i2c_chip *chip; struct mutex lock; spinlock_t slock; @@ -51,6 +53,8 @@ struct video_i2c_data { struct task_struct *kthread_vid_cap; struct list_head vid_cap_active; + + struct v4l2_fract frame_interval; }; static const struct v4l2_fmtdesc amg88xx_format = { @@ -62,13 +66,20 @@ static const struct v4l2_frmsize_discrete amg88xx_size = { .height = 8, }; +static const struct regmap_config amg88xx_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .max_register = 0xff +}; + struct video_i2c_chip { /* video dimensions */ const struct v4l2_fmtdesc *format; const struct v4l2_frmsize_discrete *size; - /* max frames per second */ - unsigned int max_fps; + /* available frame intervals */ + const struct v4l2_fract *frame_intervals; + unsigned int num_frame_intervals; /* pixel buffer size */ unsigned int buffer_size; @@ -76,33 +87,111 @@ struct video_i2c_chip { /* pixel size in bits */ unsigned int bpp; + const struct regmap_config *regmap_config; + + /* setup function */ + int (*setup)(struct video_i2c_data *data); + /* xfer function */ int (*xfer)(struct video_i2c_data *data, char *buf); + /* power control function */ + int (*set_power)(struct video_i2c_data *data, bool on); + /* hwmon init function */ int (*hwmon_init)(struct video_i2c_data *data); }; +/* Power control register */ +#define AMG88XX_REG_PCTL 0x00 +#define AMG88XX_PCTL_NORMAL 0x00 +#define AMG88XX_PCTL_SLEEP 0x10 + +/* Reset register */ +#define AMG88XX_REG_RST 0x01 +#define AMG88XX_RST_FLAG 0x30 +#define AMG88XX_RST_INIT 0x3f + +/* Frame rate register */ +#define AMG88XX_REG_FPSC 0x02 +#define AMG88XX_FPSC_1FPS BIT(0) + +/* Thermistor register */ +#define AMG88XX_REG_TTHL 0x0e + +/* Temperature register */ +#define AMG88XX_REG_T01L 0x80 + static int amg88xx_xfer(struct video_i2c_data *data, char *buf) { - struct i2c_client *client = data->client; - struct i2c_msg msg[2]; - u8 reg = 0x80; + return regmap_bulk_read(data->regmap, AMG88XX_REG_T01L, buf, + data->chip->buffer_size); +} + +static int amg88xx_setup(struct video_i2c_data *data) +{ + unsigned int mask = AMG88XX_FPSC_1FPS; + unsigned int val; + + if (data->frame_interval.numerator == data->frame_interval.denominator) + val = mask; + else + val = 0; + + return regmap_update_bits(data->regmap, AMG88XX_REG_FPSC, mask, val); +} + +static int amg88xx_set_power_on(struct video_i2c_data *data) +{ + int ret; + + ret = regmap_write(data->regmap, AMG88XX_REG_PCTL, AMG88XX_PCTL_NORMAL); + if (ret) + return ret; + + msleep(50); + + ret = regmap_write(data->regmap, AMG88XX_REG_RST, AMG88XX_RST_INIT); + if (ret) + return ret; + + usleep_range(2000, 3000); + + ret = regmap_write(data->regmap, AMG88XX_REG_RST, AMG88XX_RST_FLAG); + if (ret) + return ret; + + /* + * Wait two frames before reading thermistor and temperature registers + */ + msleep(200); + + return 0; +} + +static int amg88xx_set_power_off(struct video_i2c_data *data) +{ int ret; - msg[0].addr = client->addr; - msg[0].flags = 0; - msg[0].len = 1; - msg[0].buf = (char *)® + ret = regmap_write(data->regmap, AMG88XX_REG_PCTL, AMG88XX_PCTL_SLEEP); + if (ret) + return ret; + /* + * Wait for a while to avoid resuming normal mode immediately after + * entering sleep mode, otherwise the device occasionally goes wrong + * (thermistor and temperature registers are not updated at all) + */ + msleep(100); - msg[1].addr = client->addr; - msg[1].flags = I2C_M_RD; - msg[1].len = data->chip->buffer_size; - msg[1].buf = (char *)buf; + return 0; +} - ret = i2c_transfer(client->adapter, msg, 2); +static int amg88xx_set_power(struct video_i2c_data *data, bool on) +{ + if (on) + return amg88xx_set_power_on(data); - return (ret == 2) ? 0 : -EIO; + return amg88xx_set_power_off(data); } #if IS_ENABLED(CONFIG_HWMON) @@ -133,12 +222,23 @@ static int amg88xx_read(struct device *dev, enum hwmon_sensor_types type, u32 attr, int channel, long *val) { struct video_i2c_data *data = dev_get_drvdata(dev); - struct i2c_client *client = data->client; - int tmp = i2c_smbus_read_word_data(client, 0x0e); + __le16 buf; + int tmp; + + tmp = pm_runtime_get_sync(regmap_get_device(data->regmap)); + if (tmp < 0) { + pm_runtime_put_noidle(regmap_get_device(data->regmap)); + return tmp; + } - if (tmp < 0) + tmp = regmap_bulk_read(data->regmap, AMG88XX_REG_TTHL, &buf, 2); + pm_runtime_mark_last_busy(regmap_get_device(data->regmap)); + pm_runtime_put_autosuspend(regmap_get_device(data->regmap)); + if (tmp) return tmp; + tmp = le16_to_cpu(buf); + /* * Check for sign bit, this isn't a two's complement value but an * absolute temperature that needs to be inverted in the case of being @@ -164,8 +264,9 @@ static const struct hwmon_chip_info amg88xx_chip_info = { static int amg88xx_hwmon_init(struct video_i2c_data *data) { - void *hwmon = devm_hwmon_device_register_with_info(&data->client->dev, - "amg88xx", data, &amg88xx_chip_info, NULL); + struct device *dev = regmap_get_device(data->regmap); + void *hwmon = devm_hwmon_device_register_with_info(dev, "amg88xx", data, + &amg88xx_chip_info, NULL); return PTR_ERR_OR_ZERO(hwmon); } @@ -175,14 +276,23 @@ static int amg88xx_hwmon_init(struct video_i2c_data *data) #define AMG88XX 0 +static const struct v4l2_fract amg88xx_frame_intervals[] = { + { 1, 10 }, + { 1, 1 }, +}; + static const struct video_i2c_chip video_i2c_chip[] = { [AMG88XX] = { .size = &amg88xx_size, .format = &amg88xx_format, - .max_fps = 10, + .frame_intervals = amg88xx_frame_intervals, + .num_frame_intervals = ARRAY_SIZE(amg88xx_frame_intervals), .buffer_size = 128, .bpp = 16, + .regmap_config = &amg88xx_regmap_config, + .setup = &amg88xx_setup, .xfer = &amg88xx_xfer, + .set_power = amg88xx_set_power, .hwmon_init = amg88xx_hwmon_init, }, }; @@ -246,7 +356,8 @@ static void buffer_queue(struct vb2_buffer *vb) static int video_i2c_thread_vid_cap(void *priv) { struct video_i2c_data *data = priv; - unsigned int delay = msecs_to_jiffies(1000 / data->chip->max_fps); + unsigned int delay = mult_frac(HZ, data->frame_interval.numerator, + data->frame_interval.denominator); set_freezable(); @@ -308,19 +419,36 @@ static void video_i2c_del_list(struct vb2_queue *vq, enum vb2_buffer_state state static int start_streaming(struct vb2_queue *vq, unsigned int count) { struct video_i2c_data *data = vb2_get_drv_priv(vq); + struct device *dev = regmap_get_device(data->regmap); + int ret; if (data->kthread_vid_cap) return 0; + ret = pm_runtime_get_sync(dev); + if (ret < 0) { + pm_runtime_put_noidle(dev); + goto error_del_list; + } + + ret = data->chip->setup(data); + if (ret) + goto error_rpm_put; + data->sequence = 0; data->kthread_vid_cap = kthread_run(video_i2c_thread_vid_cap, data, "%s-vid-cap", data->v4l2_dev.name); - if (!IS_ERR(data->kthread_vid_cap)) + ret = PTR_ERR_OR_ZERO(data->kthread_vid_cap); + if (!ret) return 0; +error_rpm_put: + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); +error_del_list: video_i2c_del_list(vq, VB2_BUF_STATE_QUEUED); - return PTR_ERR(data->kthread_vid_cap); + return ret; } static void stop_streaming(struct vb2_queue *vq) @@ -332,11 +460,13 @@ static void stop_streaming(struct vb2_queue *vq) kthread_stop(data->kthread_vid_cap); data->kthread_vid_cap = NULL; + pm_runtime_mark_last_busy(regmap_get_device(data->regmap)); + pm_runtime_put_autosuspend(regmap_get_device(data->regmap)); video_i2c_del_list(vq, VB2_BUF_STATE_ERROR); } -static struct vb2_ops video_i2c_video_qops = { +static const struct vb2_ops video_i2c_video_qops = { .queue_setup = queue_setup, .buf_prepare = buffer_prepare, .buf_queue = buffer_queue, @@ -350,7 +480,8 @@ static int video_i2c_querycap(struct file *file, void *priv, struct v4l2_capability *vcap) { struct video_i2c_data *data = video_drvdata(file); - struct i2c_client *client = data->client; + struct device *dev = regmap_get_device(data->regmap); + struct i2c_client *client = to_i2c_client(dev); strscpy(vcap->driver, data->v4l2_dev.name, sizeof(vcap->driver)); strscpy(vcap->card, data->vdev.name, sizeof(vcap->card)); @@ -426,15 +557,14 @@ static int video_i2c_enum_frameintervals(struct file *file, void *priv, const struct video_i2c_data *data = video_drvdata(file); const struct v4l2_frmsize_discrete *size = data->chip->size; - if (fe->index > 0) + if (fe->index >= data->chip->num_frame_intervals) return -EINVAL; if (fe->width != size->width || fe->height != size->height) return -EINVAL; fe->type = V4L2_FRMIVAL_TYPE_DISCRETE; - fe->discrete.numerator = 1; - fe->discrete.denominator = data->chip->max_fps; + fe->discrete = data->chip->frame_intervals[fe->index]; return 0; } @@ -479,12 +609,27 @@ static int video_i2c_g_parm(struct file *filp, void *priv, parm->parm.capture.readbuffers = 1; parm->parm.capture.capability = V4L2_CAP_TIMEPERFRAME; - parm->parm.capture.timeperframe.numerator = 1; - parm->parm.capture.timeperframe.denominator = data->chip->max_fps; + parm->parm.capture.timeperframe = data->frame_interval; return 0; } +static int video_i2c_s_parm(struct file *filp, void *priv, + struct v4l2_streamparm *parm) +{ + struct video_i2c_data *data = video_drvdata(filp); + int i; + + for (i = 0; i < data->chip->num_frame_intervals - 1; i++) { + if (V4L2_FRACT_COMPARE(parm->parm.capture.timeperframe, <=, + data->chip->frame_intervals[i])) + break; + } + data->frame_interval = data->chip->frame_intervals[i]; + + return video_i2c_g_parm(filp, priv, parm); +} + static const struct v4l2_ioctl_ops video_i2c_ioctl_ops = { .vidioc_querycap = video_i2c_querycap, .vidioc_g_input = video_i2c_g_input, @@ -496,7 +641,7 @@ static const struct v4l2_ioctl_ops video_i2c_ioctl_ops = { .vidioc_g_fmt_vid_cap = video_i2c_try_fmt_vid_cap, .vidioc_s_fmt_vid_cap = video_i2c_s_fmt_vid_cap, .vidioc_g_parm = video_i2c_g_parm, - .vidioc_s_parm = video_i2c_g_parm, + .vidioc_s_parm = video_i2c_s_parm, .vidioc_try_fmt_vid_cap = video_i2c_try_fmt_vid_cap, .vidioc_reqbufs = vb2_ioctl_reqbufs, .vidioc_create_bufs = vb2_ioctl_create_bufs, @@ -510,7 +655,13 @@ static const struct v4l2_ioctl_ops video_i2c_ioctl_ops = { static void video_i2c_release(struct video_device *vdev) { - kfree(video_get_drvdata(vdev)); + struct video_i2c_data *data = video_get_drvdata(vdev); + + v4l2_device_unregister(&data->v4l2_dev); + mutex_destroy(&data->lock); + mutex_destroy(&data->queue_lock); + regmap_exit(data->regmap); + kfree(data); } static int video_i2c_probe(struct i2c_client *client, @@ -532,13 +683,18 @@ static int video_i2c_probe(struct i2c_client *client, else goto error_free_device; - data->client = client; + data->regmap = regmap_init_i2c(client, data->chip->regmap_config); + if (IS_ERR(data->regmap)) { + ret = PTR_ERR(data->regmap); + goto error_free_device; + } + v4l2_dev = &data->v4l2_dev; strscpy(v4l2_dev->name, VIDEO_I2C_DRIVER, sizeof(v4l2_dev->name)); ret = v4l2_device_register(&client->dev, v4l2_dev); if (ret < 0) - goto error_free_device; + goto error_regmap_exit; mutex_init(&data->lock); mutex_init(&data->queue_lock); @@ -575,9 +731,23 @@ static int video_i2c_probe(struct i2c_client *client, spin_lock_init(&data->slock); INIT_LIST_HEAD(&data->vid_cap_active); + data->frame_interval = data->chip->frame_intervals[0]; + video_set_drvdata(&data->vdev, data); i2c_set_clientdata(client, data); + if (data->chip->set_power) { + ret = data->chip->set_power(data, true); + if (ret) + goto error_unregister_device; + } + + pm_runtime_get_noresume(&client->dev); + pm_runtime_set_active(&client->dev); + pm_runtime_enable(&client->dev); + pm_runtime_set_autosuspend_delay(&client->dev, 2000); + pm_runtime_use_autosuspend(&client->dev); + if (data->chip->hwmon_init) { ret = data->chip->hwmon_init(data); if (ret < 0) { @@ -588,15 +758,29 @@ static int video_i2c_probe(struct i2c_client *client, ret = video_register_device(&data->vdev, VFL_TYPE_GRABBER, -1); if (ret < 0) - goto error_unregister_device; + goto error_pm_disable; + + pm_runtime_mark_last_busy(&client->dev); + pm_runtime_put_autosuspend(&client->dev); return 0; +error_pm_disable: + pm_runtime_disable(&client->dev); + pm_runtime_set_suspended(&client->dev); + pm_runtime_put_noidle(&client->dev); + + if (data->chip->set_power) + data->chip->set_power(data, false); + error_unregister_device: v4l2_device_unregister(v4l2_dev); mutex_destroy(&data->lock); mutex_destroy(&data->queue_lock); +error_regmap_exit: + regmap_exit(data->regmap); + error_free_device: kfree(data); @@ -607,15 +791,48 @@ static int video_i2c_remove(struct i2c_client *client) { struct video_i2c_data *data = i2c_get_clientdata(client); - video_unregister_device(&data->vdev); - v4l2_device_unregister(&data->v4l2_dev); + pm_runtime_get_sync(&client->dev); + pm_runtime_disable(&client->dev); + pm_runtime_set_suspended(&client->dev); + pm_runtime_put_noidle(&client->dev); - mutex_destroy(&data->lock); - mutex_destroy(&data->queue_lock); + if (data->chip->set_power) + data->chip->set_power(data, false); + + video_unregister_device(&data->vdev); return 0; } +#ifdef CONFIG_PM + +static int video_i2c_pm_runtime_suspend(struct device *dev) +{ + struct video_i2c_data *data = i2c_get_clientdata(to_i2c_client(dev)); + + if (!data->chip->set_power) + return 0; + + return data->chip->set_power(data, false); +} + +static int video_i2c_pm_runtime_resume(struct device *dev) +{ + struct video_i2c_data *data = i2c_get_clientdata(to_i2c_client(dev)); + + if (!data->chip->set_power) + return 0; + + return data->chip->set_power(data, true); +} + +#endif + +static const struct dev_pm_ops video_i2c_pm_ops = { + SET_RUNTIME_PM_OPS(video_i2c_pm_runtime_suspend, + video_i2c_pm_runtime_resume, NULL) +}; + static const struct i2c_device_id video_i2c_id_table[] = { { "amg88xx", AMG88XX }, {} @@ -632,6 +849,7 @@ static struct i2c_driver video_i2c_driver = { .driver = { .name = VIDEO_I2C_DRIVER, .of_match_table = video_i2c_of_match, + .pm = &video_i2c_pm_ops, }, .probe = video_i2c_probe, .remove = video_i2c_remove, diff --git a/drivers/media/pci/b2c2/flexcop-dma.c b/drivers/media/pci/b2c2/flexcop-dma.c index f07610a1646d..ba45b378d739 100644 --- a/drivers/media/pci/b2c2/flexcop-dma.c +++ b/drivers/media/pci/b2c2/flexcop-dma.c @@ -17,7 +17,8 @@ int flexcop_dma_allocate(struct pci_dev *pdev, return -EINVAL; } - if ((tcpu = pci_alloc_consistent(pdev, size, &tdma)) != NULL) { + tcpu = pci_alloc_consistent(pdev, size, &tdma); + if (tcpu != NULL) { dma->pdev = pdev; dma->cpu_addr0 = tcpu; dma->dma_addr0 = tdma; @@ -34,7 +35,7 @@ void flexcop_dma_free(struct flexcop_dma *dma) { pci_free_consistent(dma->pdev, dma->size*2, dma->cpu_addr0, dma->dma_addr0); - memset(dma,0,sizeof(struct flexcop_dma)); + memset(dma, 0, sizeof(struct flexcop_dma)); } EXPORT_SYMBOL(flexcop_dma_free); @@ -42,23 +43,24 @@ int flexcop_dma_config(struct flexcop_device *fc, struct flexcop_dma *dma, flexcop_dma_index_t dma_idx) { - flexcop_ibi_value v0x0,v0x4,v0xc; - v0x0.raw = v0x4.raw = v0xc.raw = 0; + flexcop_ibi_value v0x0, v0x4, v0xc; + v0x0.raw = v0x4.raw = v0xc.raw = 0; v0x0.dma_0x0.dma_address0 = dma->dma_addr0 >> 2; v0xc.dma_0xc.dma_address1 = dma->dma_addr1 >> 2; v0x4.dma_0x4_write.dma_addr_size = dma->size / 4; if ((dma_idx & FC_DMA_1) == dma_idx) { - fc->write_ibi_reg(fc,dma1_000,v0x0); - fc->write_ibi_reg(fc,dma1_004,v0x4); - fc->write_ibi_reg(fc,dma1_00c,v0xc); + fc->write_ibi_reg(fc, dma1_000, v0x0); + fc->write_ibi_reg(fc, dma1_004, v0x4); + fc->write_ibi_reg(fc, dma1_00c, v0xc); } else if ((dma_idx & FC_DMA_2) == dma_idx) { - fc->write_ibi_reg(fc,dma2_010,v0x0); - fc->write_ibi_reg(fc,dma2_014,v0x4); - fc->write_ibi_reg(fc,dma2_01c,v0xc); + fc->write_ibi_reg(fc, dma2_010, v0x0); + fc->write_ibi_reg(fc, dma2_014, v0x4); + fc->write_ibi_reg(fc, dma2_01c, v0xc); } else { - err("either DMA1 or DMA2 can be configured within one flexcop_dma_config call."); + err("either DMA1 or DMA2 can be configured within one %s call.", + __func__); return -EINVAL; } @@ -72,8 +74,8 @@ int flexcop_dma_xfer_control(struct flexcop_device *fc, flexcop_dma_addr_index_t index, int onoff) { - flexcop_ibi_value v0x0,v0xc; - flexcop_ibi_register r0x0,r0xc; + flexcop_ibi_value v0x0, v0xc; + flexcop_ibi_register r0x0, r0xc; if ((dma_idx & FC_DMA_1) == dma_idx) { r0x0 = dma1_000; @@ -82,15 +84,16 @@ int flexcop_dma_xfer_control(struct flexcop_device *fc, r0x0 = dma2_010; r0xc = dma2_01c; } else { - err("either transfer DMA1 or DMA2 can be started within one flexcop_dma_xfer_control call."); + err("transfer DMA1 or DMA2 can be started within one %s call.", + __func__); return -EINVAL; } - v0x0 = fc->read_ibi_reg(fc,r0x0); - v0xc = fc->read_ibi_reg(fc,r0xc); + v0x0 = fc->read_ibi_reg(fc, r0x0); + v0xc = fc->read_ibi_reg(fc, r0xc); - deb_rdump("reg: %03x: %x\n",r0x0,v0x0.raw); - deb_rdump("reg: %03x: %x\n",r0xc,v0xc.raw); + deb_rdump("reg: %03x: %x\n", r0x0, v0x0.raw); + deb_rdump("reg: %03x: %x\n", r0xc, v0xc.raw); if (index & FC_DMA_SUBADDR_0) v0x0.dma_0x0.dma_0start = onoff; @@ -98,11 +101,11 @@ int flexcop_dma_xfer_control(struct flexcop_device *fc, if (index & FC_DMA_SUBADDR_1) v0xc.dma_0xc.dma_1start = onoff; - fc->write_ibi_reg(fc,r0x0,v0x0); - fc->write_ibi_reg(fc,r0xc,v0xc); + fc->write_ibi_reg(fc, r0x0, v0x0); + fc->write_ibi_reg(fc, r0xc, v0xc); - deb_rdump("reg: %03x: %x\n",r0x0,v0x0.raw); - deb_rdump("reg: %03x: %x\n",r0xc,v0xc.raw); + deb_rdump("reg: %03x: %x\n", r0x0, v0x0.raw); + deb_rdump("reg: %03x: %x\n", r0xc, v0xc.raw); return 0; } EXPORT_SYMBOL(flexcop_dma_xfer_control); @@ -112,10 +115,11 @@ static int flexcop_dma_remap(struct flexcop_device *fc, int onoff) { flexcop_ibi_register r = (dma_idx & FC_DMA_1) ? dma1_00c : dma2_01c; - flexcop_ibi_value v = fc->read_ibi_reg(fc,r); - deb_info("%s\n",__func__); + flexcop_ibi_value v = fc->read_ibi_reg(fc, r); + + deb_info("%s\n", __func__); v.dma_0xc.remap_enable = onoff; - fc->write_ibi_reg(fc,r,v); + fc->write_ibi_reg(fc, r, v); return 0; } @@ -123,7 +127,7 @@ int flexcop_dma_control_size_irq(struct flexcop_device *fc, flexcop_dma_index_t no, int onoff) { - flexcop_ibi_value v = fc->read_ibi_reg(fc,ctrl_208); + flexcop_ibi_value v = fc->read_ibi_reg(fc, ctrl_208); if (no & FC_DMA_1) v.ctrl_208.DMA1_IRQ_Enable_sig = onoff; @@ -131,7 +135,7 @@ int flexcop_dma_control_size_irq(struct flexcop_device *fc, if (no & FC_DMA_2) v.ctrl_208.DMA2_IRQ_Enable_sig = onoff; - fc->write_ibi_reg(fc,ctrl_208,v); + fc->write_ibi_reg(fc, ctrl_208, v); return 0; } EXPORT_SYMBOL(flexcop_dma_control_size_irq); @@ -140,7 +144,7 @@ int flexcop_dma_control_timer_irq(struct flexcop_device *fc, flexcop_dma_index_t no, int onoff) { - flexcop_ibi_value v = fc->read_ibi_reg(fc,ctrl_208); + flexcop_ibi_value v = fc->read_ibi_reg(fc, ctrl_208); if (no & FC_DMA_1) v.ctrl_208.DMA1_Timer_Enable_sig = onoff; @@ -148,7 +152,7 @@ int flexcop_dma_control_timer_irq(struct flexcop_device *fc, if (no & FC_DMA_2) v.ctrl_208.DMA2_Timer_Enable_sig = onoff; - fc->write_ibi_reg(fc,ctrl_208,v); + fc->write_ibi_reg(fc, ctrl_208, v); return 0; } EXPORT_SYMBOL(flexcop_dma_control_timer_irq); @@ -158,13 +162,13 @@ int flexcop_dma_config_timer(struct flexcop_device *fc, flexcop_dma_index_t dma_idx, u8 cycles) { flexcop_ibi_register r = (dma_idx & FC_DMA_1) ? dma1_004 : dma2_014; - flexcop_ibi_value v = fc->read_ibi_reg(fc,r); + flexcop_ibi_value v = fc->read_ibi_reg(fc, r); - flexcop_dma_remap(fc,dma_idx,0); + flexcop_dma_remap(fc, dma_idx, 0); - deb_info("%s\n",__func__); + deb_info("%s\n", __func__); v.dma_0x4_write.dmatimer = cycles; - fc->write_ibi_reg(fc,r,v); + fc->write_ibi_reg(fc, r, v); return 0; } EXPORT_SYMBOL(flexcop_dma_config_timer); diff --git a/drivers/media/pci/bt8xx/bttv-driver.c b/drivers/media/pci/bt8xx/bttv-driver.c index d4906c04dc6e..d09785fd37a8 100644 --- a/drivers/media/pci/bt8xx/bttv-driver.c +++ b/drivers/media/pci/bt8xx/bttv-driver.c @@ -2792,19 +2792,17 @@ static int bttv_g_tuner(struct file *file, void *priv, return 0; } -static int bttv_cropcap(struct file *file, void *priv, - struct v4l2_cropcap *cap) +static int bttv_g_pixelaspect(struct file *file, void *priv, + int type, struct v4l2_fract *f) { struct bttv_fh *fh = priv; struct bttv *btv = fh->btv; - if (cap->type != V4L2_BUF_TYPE_VIDEO_CAPTURE && - cap->type != V4L2_BUF_TYPE_VIDEO_OVERLAY) + if (type != V4L2_BUF_TYPE_VIDEO_CAPTURE) return -EINVAL; /* defrect and bounds are set via g_selection */ - cap->pixelaspect = bttv_tvnorms[btv->tvnorm].cropcap.pixelaspect; - + *f = bttv_tvnorms[btv->tvnorm].cropcap.pixelaspect; return 0; } @@ -3162,7 +3160,7 @@ static const struct v4l2_ioctl_ops bttv_ioctl_ops = { .vidioc_g_fmt_vbi_cap = bttv_g_fmt_vbi_cap, .vidioc_try_fmt_vbi_cap = bttv_try_fmt_vbi_cap, .vidioc_s_fmt_vbi_cap = bttv_s_fmt_vbi_cap, - .vidioc_cropcap = bttv_cropcap, + .vidioc_g_pixelaspect = bttv_g_pixelaspect, .vidioc_reqbufs = bttv_reqbufs, .vidioc_querybuf = bttv_querybuf, .vidioc_qbuf = bttv_qbuf, diff --git a/drivers/media/pci/cobalt/cobalt-v4l2.c b/drivers/media/pci/cobalt/cobalt-v4l2.c index 0525f5e1565b..c088de551081 100644 --- a/drivers/media/pci/cobalt/cobalt-v4l2.c +++ b/drivers/media/pci/cobalt/cobalt-v4l2.c @@ -1077,33 +1077,65 @@ static int cobalt_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a) return 0; } -static int cobalt_cropcap(struct file *file, void *fh, struct v4l2_cropcap *cc) +static int cobalt_g_pixelaspect(struct file *file, void *fh, + int type, struct v4l2_fract *f) { struct cobalt_stream *s = video_drvdata(file); struct v4l2_dv_timings timings; int err = 0; - if (cc->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + if (type != V4L2_BUF_TYPE_VIDEO_CAPTURE) return -EINVAL; + if (s->input == 1) timings = cea1080p60; else err = v4l2_subdev_call(s->sd, video, g_dv_timings, &timings); - if (!err) { - cc->bounds.width = cc->defrect.width = timings.bt.width; - cc->bounds.height = cc->defrect.height = timings.bt.height; - cc->pixelaspect = v4l2_dv_timings_aspect_ratio(&timings); - } + if (!err) + *f = v4l2_dv_timings_aspect_ratio(&timings); return err; } +static int cobalt_g_selection(struct file *file, void *fh, + struct v4l2_selection *sel) +{ + struct cobalt_stream *s = video_drvdata(file); + struct v4l2_dv_timings timings; + int err = 0; + + if (sel->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + + if (s->input == 1) + timings = cea1080p60; + else + err = v4l2_subdev_call(s->sd, video, g_dv_timings, &timings); + + if (err) + return err; + + switch (sel->target) { + case V4L2_SEL_TGT_CROP_BOUNDS: + case V4L2_SEL_TGT_CROP_DEFAULT: + sel->r.top = 0; + sel->r.left = 0; + sel->r.width = timings.bt.width; + sel->r.height = timings.bt.height; + break; + default: + return -EINVAL; + } + return 0; +} + static const struct v4l2_ioctl_ops cobalt_ioctl_ops = { .vidioc_querycap = cobalt_querycap, .vidioc_g_parm = cobalt_g_parm, .vidioc_log_status = cobalt_log_status, .vidioc_streamon = vb2_ioctl_streamon, .vidioc_streamoff = vb2_ioctl_streamoff, - .vidioc_cropcap = cobalt_cropcap, + .vidioc_g_pixelaspect = cobalt_g_pixelaspect, + .vidioc_g_selection = cobalt_g_selection, .vidioc_enum_input = cobalt_enum_input, .vidioc_g_input = cobalt_g_input, .vidioc_s_input = cobalt_s_input, diff --git a/drivers/media/pci/cx18/cx18-ioctl.c b/drivers/media/pci/cx18/cx18-ioctl.c index 854116375a7c..8c54b17f382a 100644 --- a/drivers/media/pci/cx18/cx18-ioctl.c +++ b/drivers/media/pci/cx18/cx18-ioctl.c @@ -441,15 +441,16 @@ static int cx18_enum_input(struct file *file, void *fh, struct v4l2_input *vin) return cx18_get_input(cx, vin->index, vin); } -static int cx18_cropcap(struct file *file, void *fh, - struct v4l2_cropcap *cropcap) +static int cx18_g_pixelaspect(struct file *file, void *fh, + int type, struct v4l2_fract *f) { struct cx18 *cx = fh2id(fh)->cx; - if (cropcap->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + if (type != V4L2_BUF_TYPE_VIDEO_CAPTURE) return -EINVAL; - cropcap->pixelaspect.numerator = cx->is_50hz ? 54 : 11; - cropcap->pixelaspect.denominator = cx->is_50hz ? 59 : 10; + + f->numerator = cx->is_50hz ? 54 : 11; + f->denominator = cx->is_50hz ? 59 : 10; return 0; } @@ -1079,7 +1080,7 @@ static const struct v4l2_ioctl_ops cx18_ioctl_ops = { .vidioc_g_audio = cx18_g_audio, .vidioc_enumaudio = cx18_enumaudio, .vidioc_enum_input = cx18_enum_input, - .vidioc_cropcap = cx18_cropcap, + .vidioc_g_pixelaspect = cx18_g_pixelaspect, .vidioc_g_selection = cx18_g_selection, .vidioc_g_input = cx18_g_input, .vidioc_s_input = cx18_s_input, diff --git a/drivers/media/pci/cx23885/cx23885-core.c b/drivers/media/pci/cx23885/cx23885-core.c index 39804d830305..fd5c52b21436 100644 --- a/drivers/media/pci/cx23885/cx23885-core.c +++ b/drivers/media/pci/cx23885/cx23885-core.c @@ -23,6 +23,7 @@ #include <linux/moduleparam.h> #include <linux/kmod.h> #include <linux/kernel.h> +#include <linux/pci.h> #include <linux/slab.h> #include <linux/interrupt.h> #include <linux/delay.h> @@ -41,6 +42,18 @@ MODULE_AUTHOR("Steven Toth <stoth@linuxtv.org>"); MODULE_LICENSE("GPL"); MODULE_VERSION(CX23885_VERSION); +/* + * Some platforms have been found to require periodic resetting of the DMA + * engine. Ryzen and XEON platforms are known to be affected. The symptom + * encountered is "mpeg risc op code error". Only Ryzen platforms employ + * this workaround if the option equals 1. The workaround can be explicitly + * disabled for all platforms by setting to 0, the workaround can be forced + * on for any platform by setting to 2. + */ +static unsigned int dma_reset_workaround = 1; +module_param(dma_reset_workaround, int, 0644); +MODULE_PARM_DESC(dma_reset_workaround, "periodic RiSC dma engine reset; 0-force disable, 1-driver detect (default), 2-force enable"); + static unsigned int debug; module_param(debug, int, 0644); MODULE_PARM_DESC(debug, "enable debug messages"); @@ -603,8 +616,13 @@ static void cx23885_risc_disasm(struct cx23885_tsport *port, static void cx23885_clear_bridge_error(struct cx23885_dev *dev) { - uint32_t reg1_val = cx_read(TC_REQ); /* read-only */ - uint32_t reg2_val = cx_read(TC_REQ_SET); + uint32_t reg1_val, reg2_val; + + if (!dev->need_dma_reset) + return; + + reg1_val = cx_read(TC_REQ); /* read-only */ + reg2_val = cx_read(TC_REQ_SET); if (reg1_val && reg2_val) { cx_write(TC_REQ, reg1_val); @@ -2058,6 +2076,37 @@ void cx23885_gpio_enable(struct cx23885_dev *dev, u32 mask, int asoutput) /* TODO: 23-19 */ } +static struct { + int vendor, dev; +} const broken_dev_id[] = { + /* According with + * https://openbenchmarking.org/system/1703021-RI-AMDZEN08075/Ryzen%207%201800X/lspci, + * 0x1451 is PCI ID for the IOMMU found on Ryzen + */ + { PCI_VENDOR_ID_AMD, 0x1451 }, +}; + +static bool cx23885_does_need_dma_reset(void) +{ + int i; + struct pci_dev *pdev = NULL; + + if (dma_reset_workaround == 0) + return false; + else if (dma_reset_workaround == 2) + return true; + + for (i = 0; i < ARRAY_SIZE(broken_dev_id); i++) { + pdev = pci_get_device(broken_dev_id[i].vendor, + broken_dev_id[i].dev, NULL); + if (pdev) { + pci_dev_put(pdev); + return true; + } + } + return false; +} + static int cx23885_initdev(struct pci_dev *pci_dev, const struct pci_device_id *pci_id) { @@ -2069,6 +2118,8 @@ static int cx23885_initdev(struct pci_dev *pci_dev, if (NULL == dev) return -ENOMEM; + dev->need_dma_reset = cx23885_does_need_dma_reset(); + err = v4l2_device_register(&pci_dev->dev, &dev->v4l2_dev); if (err < 0) goto fail_free; diff --git a/drivers/media/pci/cx23885/cx23885-i2c.c b/drivers/media/pci/cx23885/cx23885-i2c.c index d0df3dfff694..de6809b950ce 100644 --- a/drivers/media/pci/cx23885/cx23885-i2c.c +++ b/drivers/media/pci/cx23885/cx23885-i2c.c @@ -18,7 +18,6 @@ #include "cx23885.h" #include <linux/module.h> -#include <linux/moduleparam.h> #include <linux/init.h> #include <linux/delay.h> #include <asm/io.h> diff --git a/drivers/media/pci/cx23885/cx23885-video.c b/drivers/media/pci/cx23885/cx23885-video.c index 92d32a733f1b..168178c1e574 100644 --- a/drivers/media/pci/cx23885/cx23885-video.c +++ b/drivers/media/pci/cx23885/cx23885-video.c @@ -668,26 +668,43 @@ static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv, return 0; } -static int vidioc_cropcap(struct file *file, void *priv, - struct v4l2_cropcap *cc) +static int vidioc_g_pixelaspect(struct file *file, void *priv, + int type, struct v4l2_fract *f) { struct cx23885_dev *dev = video_drvdata(file); bool is_50hz = dev->tvnorm & V4L2_STD_625_50; - if (cc->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + if (type != V4L2_BUF_TYPE_VIDEO_CAPTURE) return -EINVAL; - cc->bounds.left = 0; - cc->bounds.top = 0; - cc->bounds.width = 720; - cc->bounds.height = norm_maxh(dev->tvnorm); - cc->defrect = cc->bounds; - cc->pixelaspect.numerator = is_50hz ? 54 : 11; - cc->pixelaspect.denominator = is_50hz ? 59 : 10; + f->numerator = is_50hz ? 54 : 11; + f->denominator = is_50hz ? 59 : 10; return 0; } +static int vidioc_g_selection(struct file *file, void *fh, + struct v4l2_selection *sel) +{ + struct cx23885_dev *dev = video_drvdata(file); + + if (sel->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + + switch (sel->target) { + case V4L2_SEL_TGT_CROP_BOUNDS: + case V4L2_SEL_TGT_CROP_DEFAULT: + sel->r.top = 0; + sel->r.left = 0; + sel->r.width = 720; + sel->r.height = norm_maxh(dev->tvnorm); + break; + default: + return -EINVAL; + } + return 0; +} + static int vidioc_g_std(struct file *file, void *priv, v4l2_std_id *id) { struct cx23885_dev *dev = video_drvdata(file); @@ -1122,7 +1139,8 @@ static const struct v4l2_ioctl_ops video_ioctl_ops = { .vidioc_dqbuf = vb2_ioctl_dqbuf, .vidioc_streamon = vb2_ioctl_streamon, .vidioc_streamoff = vb2_ioctl_streamoff, - .vidioc_cropcap = vidioc_cropcap, + .vidioc_g_pixelaspect = vidioc_g_pixelaspect, + .vidioc_g_selection = vidioc_g_selection, .vidioc_s_std = vidioc_s_std, .vidioc_g_std = vidioc_g_std, .vidioc_enum_input = vidioc_enum_input, diff --git a/drivers/media/pci/cx23885/cx23885.h b/drivers/media/pci/cx23885/cx23885.h index d54c7ee1ab21..cf965efabe66 100644 --- a/drivers/media/pci/cx23885/cx23885.h +++ b/drivers/media/pci/cx23885/cx23885.h @@ -451,6 +451,8 @@ struct cx23885_dev { /* Analog raw audio */ struct cx23885_audio_dev *audio_dev; + /* Does the system require periodic DMA resets? */ + unsigned int need_dma_reset:1; }; static inline struct cx23885_dev *to_cx23885(struct v4l2_device *v4l2_dev) diff --git a/drivers/media/pci/ddbridge/ddbridge.h b/drivers/media/pci/ddbridge/ddbridge.h index f137155bf79e..b834449e78f8 100644 --- a/drivers/media/pci/ddbridge/ddbridge.h +++ b/drivers/media/pci/ddbridge/ddbridge.h @@ -18,47 +18,43 @@ #ifndef _DDBRIDGE_H_ #define _DDBRIDGE_H_ -#include <linux/module.h> +#include <linux/clk.h> +#include <linux/completion.h> +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/dvb/ca.h> +#include <linux/gpio.h> +#include <linux/i2c.h> #include <linux/init.h> #include <linux/interrupt.h> -#include <linux/delay.h> -#include <linux/slab.h> -#include <linux/poll.h> #include <linux/io.h> +#include <linux/kthread.h> +#include <linux/module.h> +#include <linux/mutex.h> #include <linux/pci.h> -#include <linux/timer.h> -#include <linux/i2c.h> +#include <linux/platform_device.h> +#include <linux/poll.h> +#include <linux/sched.h> +#include <linux/slab.h> +#include <linux/socket.h> +#include <linux/spi/spi.h> #include <linux/swab.h> +#include <linux/timer.h> +#include <linux/types.h> +#include <linux/uaccess.h> #include <linux/vmalloc.h> #include <linux/workqueue.h> -#include <linux/kthread.h> -#include <linux/platform_device.h> -#include <linux/clk.h> -#include <linux/spi/spi.h> -#include <linux/gpio.h> -#include <linux/completion.h> -#include <linux/types.h> -#include <linux/sched.h> -#include <linux/interrupt.h> -#include <linux/mutex.h> #include <asm/dma.h> #include <asm/irq.h> -#include <linux/io.h> -#include <linux/uaccess.h> - -#include <linux/dvb/ca.h> -#include <linux/socket.h> -#include <linux/device.h> -#include <linux/io.h> #include <media/dmxdev.h> -#include <media/dvbdev.h> +#include <media/dvb_ca_en50221.h> #include <media/dvb_demux.h> +#include <media/dvbdev.h> #include <media/dvb_frontend.h> -#include <media/dvb_ringbuffer.h> -#include <media/dvb_ca_en50221.h> #include <media/dvb_net.h> +#include <media/dvb_ringbuffer.h> #define DDBRIDGE_VERSION "0.9.33-integrated" diff --git a/drivers/media/pci/intel/ipu3/ipu3-cio2.h b/drivers/media/pci/intel/ipu3/ipu3-cio2.h index 240635be7a31..7caab9b8c2b9 100644 --- a/drivers/media/pci/intel/ipu3/ipu3-cio2.h +++ b/drivers/media/pci/intel/ipu3/ipu3-cio2.h @@ -10,8 +10,6 @@ #define CIO2_PCI_ID 0x9d32 #define CIO2_PCI_BAR 0 #define CIO2_DMA_MASK DMA_BIT_MASK(39) -#define CIO2_IMAGE_MAX_WIDTH 4224 -#define CIO2_IMAGE_MAX_LENGTH 3136 #define CIO2_IMAGE_MAX_WIDTH 4224 #define CIO2_IMAGE_MAX_LENGTH 3136 diff --git a/drivers/media/pci/ivtv/ivtv-ioctl.c b/drivers/media/pci/ivtv/ivtv-ioctl.c index a66f8b872520..6c269ecd8d05 100644 --- a/drivers/media/pci/ivtv/ivtv-ioctl.c +++ b/drivers/media/pci/ivtv/ivtv-ioctl.c @@ -829,17 +829,18 @@ static int ivtv_enum_output(struct file *file, void *fh, struct v4l2_output *vou return ivtv_get_output(itv, vout->index, vout); } -static int ivtv_cropcap(struct file *file, void *fh, struct v4l2_cropcap *cropcap) +static int ivtv_g_pixelaspect(struct file *file, void *fh, + int type, struct v4l2_fract *f) { struct ivtv_open_id *id = fh2id(fh); struct ivtv *itv = id->itv; - if (cropcap->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) { - cropcap->pixelaspect.numerator = itv->is_50hz ? 54 : 11; - cropcap->pixelaspect.denominator = itv->is_50hz ? 59 : 10; - } else if (cropcap->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) { - cropcap->pixelaspect.numerator = itv->is_out_50hz ? 54 : 11; - cropcap->pixelaspect.denominator = itv->is_out_50hz ? 59 : 10; + if (type == V4L2_BUF_TYPE_VIDEO_CAPTURE) { + f->numerator = itv->is_50hz ? 54 : 11; + f->denominator = itv->is_50hz ? 59 : 10; + } else if (type == V4L2_BUF_TYPE_VIDEO_OUTPUT) { + f->numerator = itv->is_out_50hz ? 54 : 11; + f->denominator = itv->is_out_50hz ? 59 : 10; } else { return -EINVAL; } @@ -1923,7 +1924,7 @@ static const struct v4l2_ioctl_ops ivtv_ioctl_ops = { .vidioc_enum_input = ivtv_enum_input, .vidioc_enum_output = ivtv_enum_output, .vidioc_enumaudout = ivtv_enumaudout, - .vidioc_cropcap = ivtv_cropcap, + .vidioc_g_pixelaspect = ivtv_g_pixelaspect, .vidioc_s_selection = ivtv_s_selection, .vidioc_g_selection = ivtv_g_selection, .vidioc_g_input = ivtv_g_input, diff --git a/drivers/media/pci/mantis/mantis_cards.c b/drivers/media/pci/mantis/mantis_cards.c index 7eb75cb7d75a..e544bb9bab90 100644 --- a/drivers/media/pci/mantis/mantis_cards.c +++ b/drivers/media/pci/mantis/mantis_cards.c @@ -19,7 +19,6 @@ */ #include <linux/module.h> -#include <linux/moduleparam.h> #include <linux/kernel.h> #include <linux/pci.h> #include <linux/slab.h> diff --git a/drivers/media/pci/saa7134/saa7134-core.c b/drivers/media/pci/saa7134/saa7134-core.c index 8984b1bf57a5..aa98ea49558c 100644 --- a/drivers/media/pci/saa7134/saa7134-core.c +++ b/drivers/media/pci/saa7134/saa7134-core.c @@ -1419,8 +1419,8 @@ static int saa7134_suspend(struct pci_dev *pci_dev , pm_message_t state) del_timer(&dev->vbi_q.timeout); del_timer(&dev->ts_q.timeout); - if (dev->remote) - saa7134_ir_stop(dev); + if (dev->remote && dev->remote->dev->users) + saa7134_ir_close(dev->remote->dev); pci_save_state(pci_dev); pci_set_power_state(pci_dev, pci_choose_state(pci_dev, state)); @@ -1447,8 +1447,8 @@ static int saa7134_resume(struct pci_dev *pci_dev) saa7134_videoport_init(dev); if (card_has_mpeg(dev)) saa7134_ts_init_hw(dev); - if (dev->remote) - saa7134_ir_start(dev); + if (dev->remote && dev->remote->dev->users) + saa7134_ir_open(dev->remote->dev); saa7134_hw_enable1(dev); msleep(100); diff --git a/drivers/media/pci/saa7134/saa7134-input.c b/drivers/media/pci/saa7134/saa7134-input.c index 999b2774b220..35884d5b8337 100644 --- a/drivers/media/pci/saa7134/saa7134-input.c +++ b/drivers/media/pci/saa7134/saa7134-input.c @@ -299,43 +299,6 @@ static int get_key_purpletv(struct IR_i2c *ir, enum rc_proto *protocol, return 1; } -static int get_key_hvr1110(struct IR_i2c *ir, enum rc_proto *protocol, - u32 *scancode, u8 *toggle) -{ - int rc; - unsigned char buf[5]; - - /* poll IR chip */ - rc = i2c_master_recv(ir->c, buf, 5); - if (rc != 5) { - ir_dbg(ir, "read error\n"); - if (rc < 0) - return rc; - return -EIO; - } - - /* Check if some key were pressed */ - if (!(buf[0] & 0x80)) - return 0; - - /* - * buf[3] & 0x80 is always high. - * buf[3] & 0x40 is a parity bit. A repeat event is marked - * by preserving it into two separate readings - * buf[4] bits 0 and 1, and buf[1] and buf[2] are always - * zero. - * - * Note that the keymap which the hvr1110 uses is RC5. - * - * FIXME: start bits could maybe be used...? - */ - *protocol = RC_PROTO_RC5; - *scancode = RC_SCANCODE_RC5(buf[3] & 0x1f, buf[4] >> 2); - *toggle = !!(buf[3] & 0x40); - return 1; -} - - static int get_key_beholdm6xx(struct IR_i2c *ir, enum rc_proto *protocol, u32 *scancode, u8 *toggle) { @@ -485,17 +448,10 @@ static void saa7134_input_timer(struct timer_list *t) mod_timer(&ir->timer, jiffies + msecs_to_jiffies(ir->polling)); } -static int __saa7134_ir_start(void *priv) +int saa7134_ir_open(struct rc_dev *rc) { - struct saa7134_dev *dev = priv; - struct saa7134_card_ir *ir; - - if (!dev || !dev->remote) - return -EINVAL; - - ir = dev->remote; - if (ir->running) - return 0; + struct saa7134_dev *dev = rc->priv; + struct saa7134_card_ir *ir = dev->remote; /* Moved here from saa7134_input_init1() because the latter * is not called on device resume */ @@ -544,55 +500,15 @@ static int __saa7134_ir_start(void *priv) return 0; } -static void __saa7134_ir_stop(void *priv) +void saa7134_ir_close(struct rc_dev *rc) { - struct saa7134_dev *dev = priv; - struct saa7134_card_ir *ir; - - if (!dev || !dev->remote) - return; - - ir = dev->remote; - if (!ir->running) - return; + struct saa7134_dev *dev = rc->priv; + struct saa7134_card_ir *ir = dev->remote; if (ir->polling) del_timer_sync(&ir->timer); ir->running = false; - - return; -} - -int saa7134_ir_start(struct saa7134_dev *dev) -{ - if (dev->remote->users) - return __saa7134_ir_start(dev); - - return 0; -} - -void saa7134_ir_stop(struct saa7134_dev *dev) -{ - if (dev->remote->users) - __saa7134_ir_stop(dev); -} - -static int saa7134_ir_open(struct rc_dev *rc) -{ - struct saa7134_dev *dev = rc->priv; - - dev->remote->users++; - return __saa7134_ir_start(dev); -} - -static void saa7134_ir_close(struct rc_dev *rc) -{ - struct saa7134_dev *dev = rc->priv; - - dev->remote->users--; - if (!dev->remote->users) - __saa7134_ir_stop(dev); } int saa7134_input_init1(struct saa7134_dev *dev) @@ -661,7 +577,7 @@ int saa7134_input_init1(struct saa7134_dev *dev) mask_keycode = 0x0007C8; mask_keydown = 0x000010; polling = 50; // ms - /* GPIO stuff moved to __saa7134_ir_start() */ + /* GPIO stuff moved to saa7134_ir_open() */ break; case SAA7134_BOARD_AVERMEDIA_M135A: ir_codes = RC_MAP_AVERMEDIA_M135A; @@ -683,14 +599,14 @@ int saa7134_input_init1(struct saa7134_dev *dev) mask_keycode = 0x02F200; mask_keydown = 0x000400; polling = 50; // ms - /* GPIO stuff moved to __saa7134_ir_start() */ + /* GPIO stuff moved to saa7134_ir_open() */ break; case SAA7134_BOARD_AVERMEDIA_A16D: ir_codes = RC_MAP_AVERMEDIA_A16D; mask_keycode = 0x02F200; mask_keydown = 0x000400; polling = 50; /* ms */ - /* GPIO stuff moved to __saa7134_ir_start() */ + /* GPIO stuff moved to saa7134_ir_open() */ break; case SAA7134_BOARD_KWORLD_TERMINATOR: ir_codes = RC_MAP_PIXELVIEW; @@ -742,7 +658,7 @@ int saa7134_input_init1(struct saa7134_dev *dev) mask_keycode = 0x0003CC; mask_keydown = 0x000010; polling = 5; /* ms */ - /* GPIO stuff moved to __saa7134_ir_start() */ + /* GPIO stuff moved to saa7134_ir_open() */ break; case SAA7134_BOARD_VIDEOMATE_TV_PVR: case SAA7134_BOARD_VIDEOMATE_GOLD_PLUS: @@ -880,8 +796,6 @@ int saa7134_input_init1(struct saa7134_dev *dev) ir->raw_decode = raw_decode; /* init input device */ - snprintf(ir->name, sizeof(ir->name), "saa7134 IR (%s)", - saa7134_boards[dev->board].name); snprintf(ir->phys, sizeof(ir->phys), "pci-%s/ir0", pci_name(dev->pci)); @@ -893,7 +807,7 @@ int saa7134_input_init1(struct saa7134_dev *dev) rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER; } - rc->device_name = ir->name; + rc->device_name = saa7134_boards[dev->board].name; rc->input_phys = ir->phys; rc->input_id.bustype = BUS_PCI; rc->input_id.version = 1; @@ -929,7 +843,6 @@ void saa7134_input_fini(struct saa7134_dev *dev) if (NULL == dev->remote) return; - saa7134_ir_stop(dev); rc_unregister_device(dev->remote->dev); kfree(dev->remote); dev->remote = NULL; @@ -1031,9 +944,11 @@ void saa7134_probe_i2c_ir(struct saa7134_dev *dev) (1 == rc) ? "yes" : "no"); break; case SAA7134_BOARD_HAUPPAUGE_HVR1110: - dev->init_data.name = "HVR 1110"; - dev->init_data.get_key = get_key_hvr1110; + dev->init_data.name = saa7134_boards[dev->board].name; dev->init_data.ir_codes = RC_MAP_HAUPPAUGE; + dev->init_data.type = RC_PROTO_BIT_RC5 | + RC_PROTO_BIT_RC6_MCE | RC_PROTO_BIT_RC6_6A_32; + dev->init_data.internal_get_key_func = IR_KBD_GET_KEY_HAUP_XVR; info.addr = 0x71; break; case SAA7134_BOARD_BEHOLD_607FM_MK3: diff --git a/drivers/media/pci/saa7134/saa7134-video.c b/drivers/media/pci/saa7134/saa7134-video.c index 8f28741ebb35..5bc4b8fc8ebf 100644 --- a/drivers/media/pci/saa7134/saa7134-video.c +++ b/drivers/media/pci/saa7134/saa7134-video.c @@ -1650,23 +1650,22 @@ int saa7134_querystd(struct file *file, void *priv, v4l2_std_id *std) } EXPORT_SYMBOL_GPL(saa7134_querystd); -static int saa7134_cropcap(struct file *file, void *priv, - struct v4l2_cropcap *cap) +static int saa7134_g_pixelaspect(struct file *file, void *priv, + int type, struct v4l2_fract *f) { struct saa7134_dev *dev = video_drvdata(file); - if (cap->type != V4L2_BUF_TYPE_VIDEO_CAPTURE && - cap->type != V4L2_BUF_TYPE_VIDEO_OVERLAY) + if (type != V4L2_BUF_TYPE_VIDEO_CAPTURE && + type != V4L2_BUF_TYPE_VIDEO_OVERLAY) return -EINVAL; - cap->pixelaspect.numerator = 1; - cap->pixelaspect.denominator = 1; + if (dev->tvnorm->id & V4L2_STD_525_60) { - cap->pixelaspect.numerator = 11; - cap->pixelaspect.denominator = 10; + f->numerator = 11; + f->denominator = 10; } if (dev->tvnorm->id & V4L2_STD_625_50) { - cap->pixelaspect.numerator = 54; - cap->pixelaspect.denominator = 59; + f->numerator = 54; + f->denominator = 59; } return 0; } @@ -1987,7 +1986,7 @@ static const struct v4l2_ioctl_ops video_ioctl_ops = { .vidioc_g_fmt_vbi_cap = saa7134_try_get_set_fmt_vbi_cap, .vidioc_try_fmt_vbi_cap = saa7134_try_get_set_fmt_vbi_cap, .vidioc_s_fmt_vbi_cap = saa7134_try_get_set_fmt_vbi_cap, - .vidioc_cropcap = saa7134_cropcap, + .vidioc_g_pixelaspect = saa7134_g_pixelaspect, .vidioc_reqbufs = vb2_ioctl_reqbufs, .vidioc_querybuf = vb2_ioctl_querybuf, .vidioc_qbuf = vb2_ioctl_qbuf, diff --git a/drivers/media/pci/saa7134/saa7134.h b/drivers/media/pci/saa7134/saa7134.h index 480228456014..50b1d07d2ac1 100644 --- a/drivers/media/pci/saa7134/saa7134.h +++ b/drivers/media/pci/saa7134/saa7134.h @@ -123,9 +123,7 @@ struct saa7134_format { struct saa7134_card_ir { struct rc_dev *dev; - char name[32]; char phys[32]; - unsigned users; u32 polling; u32 last_gpio; @@ -923,13 +921,13 @@ int saa7134_input_init1(struct saa7134_dev *dev); void saa7134_input_fini(struct saa7134_dev *dev); void saa7134_input_irq(struct saa7134_dev *dev); void saa7134_probe_i2c_ir(struct saa7134_dev *dev); -int saa7134_ir_start(struct saa7134_dev *dev); -void saa7134_ir_stop(struct saa7134_dev *dev); +int saa7134_ir_open(struct rc_dev *dev); +void saa7134_ir_close(struct rc_dev *dev); #else #define saa7134_input_init1(dev) ((void)0) #define saa7134_input_fini(dev) ((void)0) #define saa7134_input_irq(dev) ((void)0) #define saa7134_probe_i2c_ir(dev) ((void)0) -#define saa7134_ir_start(dev) ((void)0) -#define saa7134_ir_stop(dev) ((void)0) +#define saa7134_ir_open(dev) ((void)0) +#define saa7134_ir_close(dev) ((void)0) #endif diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig index 70c4f6c54881..a505e9f5a1e2 100644 --- a/drivers/media/platform/Kconfig +++ b/drivers/media/platform/Kconfig @@ -32,6 +32,15 @@ source "drivers/media/platform/davinci/Kconfig" source "drivers/media/platform/omap/Kconfig" +config VIDEO_ASPEED + tristate "Aspeed AST2400 and AST2500 Video Engine driver" + depends on VIDEO_V4L2 + select VIDEOBUF2_DMA_CONTIG + help + Support for the Aspeed Video Engine (VE) embedded in the Aspeed + AST2400 and AST2500 SOCs. The VE can capture and compress video data + from digital or analog sources. + config VIDEO_SH_VOU tristate "SuperH VOU video output driver" depends on MEDIA_CAMERA_SUPPORT @@ -138,6 +147,7 @@ source "drivers/media/platform/am437x/Kconfig" source "drivers/media/platform/xilinx/Kconfig" source "drivers/media/platform/rcar-vin/Kconfig" source "drivers/media/platform/atmel/Kconfig" +source "drivers/media/platform/sunxi/sun6i-csi/Kconfig" config VIDEO_TI_CAL tristate "TI CAL (Camera Adaptation Layer) driver" @@ -625,6 +635,28 @@ config VIDEO_TEGRA_HDMI_CEC The CEC bus is present in the HDMI connector and enables communication between compatible devices. +config VIDEO_SECO_CEC + tristate "SECO Boards HDMI CEC driver" + depends on (X86 || IA64) || COMPILE_TEST + depends on PCI && DMI + select CEC_CORE + select CEC_NOTIFIER + help + This is a driver for SECO Boards integrated CEC interface. + Selecting it will enable support for this device. + CEC bus is present in the HDMI connector and enables communication + between compatible devices. + +config VIDEO_SECO_RC + bool "SECO Boards IR RC5 support" + depends on VIDEO_SECO_CEC + select RC_CORE + help + If you say yes here you will get support for the + SECO Boards Consumer-IR in seco-cec driver. + The embedded controller supports RC5 protocol only, default mapping + is set to rc-hauppauge. + endif #CEC_PLATFORM_DRIVERS menuconfig SDR_PLATFORM_DRIVERS diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile index 6ab6200dd9c9..e6deb2597738 100644 --- a/drivers/media/platform/Makefile +++ b/drivers/media/platform/Makefile @@ -3,6 +3,7 @@ # Makefile for the video capture/playback device drivers. # +obj-$(CONFIG_VIDEO_ASPEED) += aspeed-video.o obj-$(CONFIG_VIDEO_CADENCE) += cadence/ obj-$(CONFIG_VIDEO_VIA_CAMERA) += via-camera.o obj-$(CONFIG_VIDEO_CAFE_CCIC) += marvell-ccic/ @@ -55,6 +56,8 @@ obj-$(CONFIG_VIDEO_TEGRA_HDMI_CEC) += tegra-cec/ obj-y += stm32/ +obj-$(CONFIG_VIDEO_SECO_CEC) += seco-cec/ + obj-y += davinci/ obj-$(CONFIG_VIDEO_SH_VOU) += sh_vou.o @@ -98,3 +101,5 @@ obj-$(CONFIG_VIDEO_QCOM_VENUS) += qcom/venus/ obj-y += meson/ obj-y += cros-ec-cec/ + +obj-$(CONFIG_VIDEO_SUN6I_CSI) += sunxi/sun6i-csi/ diff --git a/drivers/media/platform/am437x/am437x-vpfe.c b/drivers/media/platform/am437x/am437x-vpfe.c index e13d2b3a7168..5c17624aaade 100644 --- a/drivers/media/platform/am437x/am437x-vpfe.c +++ b/drivers/media/platform/am437x/am437x-vpfe.c @@ -2081,24 +2081,18 @@ static void vpfe_stop_streaming(struct vb2_queue *vq) spin_unlock_irqrestore(&vpfe->dma_queue_lock, flags); } -static int vpfe_cropcap(struct file *file, void *priv, - struct v4l2_cropcap *crop) +static int vpfe_g_pixelaspect(struct file *file, void *priv, + int type, struct v4l2_fract *f) { struct vpfe_device *vpfe = video_drvdata(file); - vpfe_dbg(2, vpfe, "vpfe_cropcap\n"); + vpfe_dbg(2, vpfe, "vpfe_g_pixelaspect\n"); - if (vpfe->std_index >= ARRAY_SIZE(vpfe_standards)) + if (type != V4L2_BUF_TYPE_VIDEO_CAPTURE || + vpfe->std_index >= ARRAY_SIZE(vpfe_standards)) return -EINVAL; - memset(crop, 0, sizeof(struct v4l2_cropcap)); - - crop->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; - crop->defrect.width = vpfe_standards[vpfe->std_index].width; - crop->bounds.width = crop->defrect.width; - crop->defrect.height = vpfe_standards[vpfe->std_index].height; - crop->bounds.height = crop->defrect.height; - crop->pixelaspect = vpfe_standards[vpfe->std_index].pixelaspect; + *f = vpfe_standards[vpfe->std_index].pixelaspect; return 0; } @@ -2108,12 +2102,17 @@ vpfe_g_selection(struct file *file, void *fh, struct v4l2_selection *s) { struct vpfe_device *vpfe = video_drvdata(file); + if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE || + vpfe->std_index >= ARRAY_SIZE(vpfe_standards)) + return -EINVAL; + switch (s->target) { case V4L2_SEL_TGT_CROP_BOUNDS: case V4L2_SEL_TGT_CROP_DEFAULT: - s->r.left = s->r.top = 0; - s->r.width = vpfe->crop.width; - s->r.height = vpfe->crop.height; + s->r.left = 0; + s->r.top = 0; + s->r.width = vpfe_standards[vpfe->std_index].width; + s->r.height = vpfe_standards[vpfe->std_index].height; break; case V4L2_SEL_TGT_CROP: @@ -2282,7 +2281,7 @@ static const struct v4l2_ioctl_ops vpfe_ioctl_ops = { .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, .vidioc_unsubscribe_event = v4l2_event_unsubscribe, - .vidioc_cropcap = vpfe_cropcap, + .vidioc_g_pixelaspect = vpfe_g_pixelaspect, .vidioc_g_selection = vpfe_g_selection, .vidioc_s_selection = vpfe_s_selection, diff --git a/drivers/media/platform/aspeed-video.c b/drivers/media/platform/aspeed-video.c new file mode 100644 index 000000000000..dfec813f50a9 --- /dev/null +++ b/drivers/media/platform/aspeed-video.c @@ -0,0 +1,1729 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <linux/atomic.h> +#include <linux/bitfield.h> +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/dma-mapping.h> +#include <linux/interrupt.h> +#include <linux/jiffies.h> +#include <linux/module.h> +#include <linux/mutex.h> +#include <linux/of.h> +#include <linux/of_irq.h> +#include <linux/of_reserved_mem.h> +#include <linux/platform_device.h> +#include <linux/reset.h> +#include <linux/sched.h> +#include <linux/spinlock.h> +#include <linux/string.h> +#include <linux/v4l2-controls.h> +#include <linux/videodev2.h> +#include <linux/wait.h> +#include <linux/workqueue.h> +#include <media/v4l2-ctrls.h> +#include <media/v4l2-dev.h> +#include <media/v4l2-device.h> +#include <media/v4l2-dv-timings.h> +#include <media/v4l2-event.h> +#include <media/v4l2-ioctl.h> +#include <media/videobuf2-dma-contig.h> + +#define DEVICE_NAME "aspeed-video" + +#define ASPEED_VIDEO_JPEG_NUM_QUALITIES 12 +#define ASPEED_VIDEO_JPEG_HEADER_SIZE 10 +#define ASPEED_VIDEO_JPEG_QUANT_SIZE 116 +#define ASPEED_VIDEO_JPEG_DCT_SIZE 34 + +#define MAX_FRAME_RATE 60 +#define MAX_HEIGHT 1200 +#define MAX_WIDTH 1920 +#define MIN_HEIGHT 480 +#define MIN_WIDTH 640 + +#define NUM_POLARITY_CHECKS 10 +#define INVALID_RESOLUTION_RETRIES 2 +#define INVALID_RESOLUTION_DELAY msecs_to_jiffies(250) +#define RESOLUTION_CHANGE_DELAY msecs_to_jiffies(500) +#define MODE_DETECT_TIMEOUT msecs_to_jiffies(500) +#define STOP_TIMEOUT msecs_to_jiffies(1000) +#define DIRECT_FETCH_THRESHOLD 0x0c0000 /* 1024 * 768 */ + +#define VE_MAX_SRC_BUFFER_SIZE 0x8ca000 /* 1920 * 1200, 32bpp */ +#define VE_JPEG_HEADER_SIZE 0x006000 /* 512 * 12 * 4 */ + +#define VE_PROTECTION_KEY 0x000 +#define VE_PROTECTION_KEY_UNLOCK 0x1a038aa8 + +#define VE_SEQ_CTRL 0x004 +#define VE_SEQ_CTRL_TRIG_MODE_DET BIT(0) +#define VE_SEQ_CTRL_TRIG_CAPTURE BIT(1) +#define VE_SEQ_CTRL_FORCE_IDLE BIT(2) +#define VE_SEQ_CTRL_MULT_FRAME BIT(3) +#define VE_SEQ_CTRL_TRIG_COMP BIT(4) +#define VE_SEQ_CTRL_AUTO_COMP BIT(5) +#define VE_SEQ_CTRL_EN_WATCHDOG BIT(7) +#define VE_SEQ_CTRL_YUV420 BIT(10) +#define VE_SEQ_CTRL_COMP_FMT GENMASK(11, 10) +#define VE_SEQ_CTRL_HALT BIT(12) +#define VE_SEQ_CTRL_EN_WATCHDOG_COMP BIT(14) +#define VE_SEQ_CTRL_TRIG_JPG BIT(15) +#define VE_SEQ_CTRL_CAP_BUSY BIT(16) +#define VE_SEQ_CTRL_COMP_BUSY BIT(18) + +#ifdef CONFIG_MACH_ASPEED_G5 +#define VE_SEQ_CTRL_JPEG_MODE BIT(13) /* AST2500 */ +#else +#define VE_SEQ_CTRL_JPEG_MODE BIT(8) /* AST2400 */ +#endif /* CONFIG_MACH_ASPEED_G5 */ + +#define VE_CTRL 0x008 +#define VE_CTRL_HSYNC_POL BIT(0) +#define VE_CTRL_VSYNC_POL BIT(1) +#define VE_CTRL_SOURCE BIT(2) +#define VE_CTRL_INT_DE BIT(4) +#define VE_CTRL_DIRECT_FETCH BIT(5) +#define VE_CTRL_YUV BIT(6) +#define VE_CTRL_RGB BIT(7) +#define VE_CTRL_CAPTURE_FMT GENMASK(7, 6) +#define VE_CTRL_AUTO_OR_CURSOR BIT(8) +#define VE_CTRL_CLK_INVERSE BIT(11) +#define VE_CTRL_CLK_DELAY GENMASK(11, 9) +#define VE_CTRL_INTERLACE BIT(14) +#define VE_CTRL_HSYNC_POL_CTRL BIT(15) +#define VE_CTRL_FRC GENMASK(23, 16) + +#define VE_TGS_0 0x00c +#define VE_TGS_1 0x010 +#define VE_TGS_FIRST GENMASK(28, 16) +#define VE_TGS_LAST GENMASK(12, 0) + +#define VE_SCALING_FACTOR 0x014 +#define VE_SCALING_FILTER0 0x018 +#define VE_SCALING_FILTER1 0x01c +#define VE_SCALING_FILTER2 0x020 +#define VE_SCALING_FILTER3 0x024 + +#define VE_CAP_WINDOW 0x030 +#define VE_COMP_WINDOW 0x034 +#define VE_COMP_PROC_OFFSET 0x038 +#define VE_COMP_OFFSET 0x03c +#define VE_JPEG_ADDR 0x040 +#define VE_SRC0_ADDR 0x044 +#define VE_SRC_SCANLINE_OFFSET 0x048 +#define VE_SRC1_ADDR 0x04c +#define VE_COMP_ADDR 0x054 + +#define VE_STREAM_BUF_SIZE 0x058 +#define VE_STREAM_BUF_SIZE_N_PACKETS GENMASK(5, 3) +#define VE_STREAM_BUF_SIZE_P_SIZE GENMASK(2, 0) + +#define VE_COMP_CTRL 0x060 +#define VE_COMP_CTRL_VQ_DCT_ONLY BIT(0) +#define VE_COMP_CTRL_VQ_4COLOR BIT(1) +#define VE_COMP_CTRL_QUANTIZE BIT(2) +#define VE_COMP_CTRL_EN_BQ BIT(4) +#define VE_COMP_CTRL_EN_CRYPTO BIT(5) +#define VE_COMP_CTRL_DCT_CHR GENMASK(10, 6) +#define VE_COMP_CTRL_DCT_LUM GENMASK(15, 11) +#define VE_COMP_CTRL_EN_HQ BIT(16) +#define VE_COMP_CTRL_RSVD BIT(19) +#define VE_COMP_CTRL_ENCODE GENMASK(21, 20) +#define VE_COMP_CTRL_HQ_DCT_CHR GENMASK(26, 22) +#define VE_COMP_CTRL_HQ_DCT_LUM GENMASK(31, 27) + +#define VE_OFFSET_COMP_STREAM 0x078 + +#define VE_SRC_LR_EDGE_DET 0x090 +#define VE_SRC_LR_EDGE_DET_LEFT GENMASK(11, 0) +#define VE_SRC_LR_EDGE_DET_NO_V BIT(12) +#define VE_SRC_LR_EDGE_DET_NO_H BIT(13) +#define VE_SRC_LR_EDGE_DET_NO_DISP BIT(14) +#define VE_SRC_LR_EDGE_DET_NO_CLK BIT(15) +#define VE_SRC_LR_EDGE_DET_RT_SHF 16 +#define VE_SRC_LR_EDGE_DET_RT GENMASK(27, VE_SRC_LR_EDGE_DET_RT_SHF) +#define VE_SRC_LR_EDGE_DET_INTERLACE BIT(31) + +#define VE_SRC_TB_EDGE_DET 0x094 +#define VE_SRC_TB_EDGE_DET_TOP GENMASK(12, 0) +#define VE_SRC_TB_EDGE_DET_BOT_SHF 16 +#define VE_SRC_TB_EDGE_DET_BOT GENMASK(28, VE_SRC_TB_EDGE_DET_BOT_SHF) + +#define VE_MODE_DETECT_STATUS 0x098 +#define VE_MODE_DETECT_H_PIXELS GENMASK(11, 0) +#define VE_MODE_DETECT_V_LINES_SHF 16 +#define VE_MODE_DETECT_V_LINES GENMASK(27, VE_MODE_DETECT_V_LINES_SHF) +#define VE_MODE_DETECT_STATUS_VSYNC BIT(28) +#define VE_MODE_DETECT_STATUS_HSYNC BIT(29) + +#define VE_SYNC_STATUS 0x09c +#define VE_SYNC_STATUS_HSYNC GENMASK(11, 0) +#define VE_SYNC_STATUS_VSYNC_SHF 16 +#define VE_SYNC_STATUS_VSYNC GENMASK(27, VE_SYNC_STATUS_VSYNC_SHF) + +#define VE_INTERRUPT_CTRL 0x304 +#define VE_INTERRUPT_STATUS 0x308 +#define VE_INTERRUPT_MODE_DETECT_WD BIT(0) +#define VE_INTERRUPT_CAPTURE_COMPLETE BIT(1) +#define VE_INTERRUPT_COMP_READY BIT(2) +#define VE_INTERRUPT_COMP_COMPLETE BIT(3) +#define VE_INTERRUPT_MODE_DETECT BIT(4) +#define VE_INTERRUPT_FRAME_COMPLETE BIT(5) +#define VE_INTERRUPT_DECODE_ERR BIT(6) +#define VE_INTERRUPT_HALT_READY BIT(8) +#define VE_INTERRUPT_HANG_WD BIT(9) +#define VE_INTERRUPT_STREAM_DESC BIT(10) +#define VE_INTERRUPT_VSYNC_DESC BIT(11) + +#define VE_MODE_DETECT 0x30c +#define VE_MEM_RESTRICT_START 0x310 +#define VE_MEM_RESTRICT_END 0x314 + +enum { + VIDEO_MODE_DETECT_DONE, + VIDEO_RES_CHANGE, + VIDEO_RES_DETECT, + VIDEO_STREAMING, + VIDEO_FRAME_INPRG, + VIDEO_STOPPED, +}; + +struct aspeed_video_addr { + unsigned int size; + dma_addr_t dma; + void *virt; +}; + +struct aspeed_video_buffer { + struct vb2_v4l2_buffer vb; + struct list_head link; +}; + +#define to_aspeed_video_buffer(x) \ + container_of((x), struct aspeed_video_buffer, vb) + +struct aspeed_video { + void __iomem *base; + struct clk *eclk; + struct clk *vclk; + struct reset_control *rst; + + struct device *dev; + struct v4l2_ctrl_handler ctrl_handler; + struct v4l2_device v4l2_dev; + struct v4l2_pix_format pix_fmt; + struct v4l2_bt_timings active_timings; + struct v4l2_bt_timings detected_timings; + u32 v4l2_input_status; + struct vb2_queue queue; + struct video_device vdev; + struct mutex video_lock; /* v4l2 and videobuf2 lock */ + + wait_queue_head_t wait; + spinlock_t lock; /* buffer list lock */ + struct delayed_work res_work; + struct list_head buffers; + unsigned long flags; + unsigned int sequence; + + unsigned int max_compressed_size; + struct aspeed_video_addr srcs[2]; + struct aspeed_video_addr jpeg; + + bool yuv420; + unsigned int frame_rate; + unsigned int jpeg_quality; + + unsigned int frame_bottom; + unsigned int frame_left; + unsigned int frame_right; + unsigned int frame_top; +}; + +#define to_aspeed_video(x) container_of((x), struct aspeed_video, v4l2_dev) + +static const u32 aspeed_video_jpeg_header[ASPEED_VIDEO_JPEG_HEADER_SIZE] = { + 0xe0ffd8ff, 0x464a1000, 0x01004649, 0x60000101, 0x00006000, 0x0f00feff, + 0x00002d05, 0x00000000, 0x00000000, 0x00dbff00 +}; + +static const u32 aspeed_video_jpeg_quant[ASPEED_VIDEO_JPEG_QUANT_SIZE] = { + 0x081100c0, 0x00000000, 0x00110103, 0x03011102, 0xc4ff0111, 0x00001f00, + 0x01010501, 0x01010101, 0x00000000, 0x00000000, 0x04030201, 0x08070605, + 0xff0b0a09, 0x10b500c4, 0x03010200, 0x03040203, 0x04040505, 0x7d010000, + 0x00030201, 0x12051104, 0x06413121, 0x07615113, 0x32147122, 0x08a19181, + 0xc1b14223, 0xf0d15215, 0x72623324, 0x160a0982, 0x1a191817, 0x28272625, + 0x35342a29, 0x39383736, 0x4544433a, 0x49484746, 0x5554534a, 0x59585756, + 0x6564635a, 0x69686766, 0x7574736a, 0x79787776, 0x8584837a, 0x89888786, + 0x9493928a, 0x98979695, 0xa3a29a99, 0xa7a6a5a4, 0xb2aaa9a8, 0xb6b5b4b3, + 0xbab9b8b7, 0xc5c4c3c2, 0xc9c8c7c6, 0xd4d3d2ca, 0xd8d7d6d5, 0xe2e1dad9, + 0xe6e5e4e3, 0xeae9e8e7, 0xf4f3f2f1, 0xf8f7f6f5, 0xc4fffaf9, 0x00011f00, + 0x01010103, 0x01010101, 0x00000101, 0x00000000, 0x04030201, 0x08070605, + 0xff0b0a09, 0x11b500c4, 0x02010200, 0x04030404, 0x04040507, 0x77020100, + 0x03020100, 0x21050411, 0x41120631, 0x71610751, 0x81322213, 0x91421408, + 0x09c1b1a1, 0xf0523323, 0xd1726215, 0x3424160a, 0x17f125e1, 0x261a1918, + 0x2a292827, 0x38373635, 0x44433a39, 0x48474645, 0x54534a49, 0x58575655, + 0x64635a59, 0x68676665, 0x74736a69, 0x78777675, 0x83827a79, 0x87868584, + 0x928a8988, 0x96959493, 0x9a999897, 0xa5a4a3a2, 0xa9a8a7a6, 0xb4b3b2aa, + 0xb8b7b6b5, 0xc3c2bab9, 0xc7c6c5c4, 0xd2cac9c8, 0xd6d5d4d3, 0xdad9d8d7, + 0xe5e4e3e2, 0xe9e8e7e6, 0xf4f3f2ea, 0xf8f7f6f5, 0xdafffaf9, 0x01030c00, + 0x03110200, 0x003f0011 +}; + +static const u32 aspeed_video_jpeg_dct[ASPEED_VIDEO_JPEG_NUM_QUALITIES] + [ASPEED_VIDEO_JPEG_DCT_SIZE] = { + { 0x0d140043, 0x0c0f110f, 0x11101114, 0x17141516, 0x1e20321e, + 0x3d1e1b1b, 0x32242e2b, 0x4b4c3f48, 0x44463f47, 0x61735a50, + 0x566c5550, 0x88644644, 0x7a766c65, 0x4d808280, 0x8c978d60, + 0x7e73967d, 0xdbff7b80, 0x1f014300, 0x272d2121, 0x3030582d, + 0x697bb958, 0xb8b9b97b, 0xb9b8a6a6, 0xb9b9b9b9, 0xb9b9b9b9, + 0xb9b9b9b9, 0xb9b9b9b9, 0xb9b9b9b9, 0xb9b9b9b9, 0xb9b9b9b9, + 0xb9b9b9b9, 0xb9b9b9b9, 0xb9b9b9b9, 0xffb9b9b9 }, + { 0x0c110043, 0x0a0d0f0d, 0x0f0e0f11, 0x14111213, 0x1a1c2b1a, + 0x351a1818, 0x2b1f2826, 0x4142373f, 0x3c3d373e, 0x55644e46, + 0x4b5f4a46, 0x77573d3c, 0x6b675f58, 0x43707170, 0x7a847b54, + 0x6e64836d, 0xdbff6c70, 0x1b014300, 0x22271d1d, 0x2a2a4c27, + 0x5b6ba04c, 0xa0a0a06b, 0xa0a0a0a0, 0xa0a0a0a0, 0xa0a0a0a0, + 0xa0a0a0a0, 0xa0a0a0a0, 0xa0a0a0a0, 0xa0a0a0a0, 0xa0a0a0a0, + 0xa0a0a0a0, 0xa0a0a0a0, 0xa0a0a0a0, 0xffa0a0a0 }, + { 0x090e0043, 0x090a0c0a, 0x0c0b0c0e, 0x110e0f10, 0x15172415, + 0x2c151313, 0x241a211f, 0x36372e34, 0x31322e33, 0x4653413a, + 0x3e4e3d3a, 0x62483231, 0x58564e49, 0x385d5e5d, 0x656d6645, + 0x5b536c5a, 0xdbff595d, 0x16014300, 0x1c201818, 0x22223f20, + 0x4b58853f, 0x85858558, 0x85858585, 0x85858585, 0x85858585, + 0x85858585, 0x85858585, 0x85858585, 0x85858585, 0x85858585, + 0x85858585, 0x85858585, 0x85858585, 0xff858585 }, + { 0x070b0043, 0x07080a08, 0x0a090a0b, 0x0d0b0c0c, 0x11121c11, + 0x23110f0f, 0x1c141a19, 0x2b2b2429, 0x27282428, 0x3842332e, + 0x313e302e, 0x4e392827, 0x46443e3a, 0x2c4a4a4a, 0x50565137, + 0x48425647, 0xdbff474a, 0x12014300, 0x161a1313, 0x1c1c331a, + 0x3d486c33, 0x6c6c6c48, 0x6c6c6c6c, 0x6c6c6c6c, 0x6c6c6c6c, + 0x6c6c6c6c, 0x6c6c6c6c, 0x6c6c6c6c, 0x6c6c6c6c, 0x6c6c6c6c, + 0x6c6c6c6c, 0x6c6c6c6c, 0x6c6c6c6c, 0xff6c6c6c }, + { 0x06090043, 0x05060706, 0x07070709, 0x0a09090a, 0x0d0e160d, + 0x1b0d0c0c, 0x16101413, 0x21221c20, 0x1e1f1c20, 0x2b332824, + 0x26302624, 0x3d2d1f1e, 0x3735302d, 0x22393a39, 0x3f443f2b, + 0x38334338, 0xdbff3739, 0x0d014300, 0x11130e0e, 0x15152613, + 0x2d355026, 0x50505035, 0x50505050, 0x50505050, 0x50505050, + 0x50505050, 0x50505050, 0x50505050, 0x50505050, 0x50505050, + 0x50505050, 0x50505050, 0x50505050, 0xff505050 }, + { 0x04060043, 0x03040504, 0x05040506, 0x07060606, 0x09090f09, + 0x12090808, 0x0f0a0d0d, 0x16161315, 0x14151315, 0x1d221b18, + 0x19201918, 0x281e1514, 0x2423201e, 0x17262726, 0x2a2d2a1c, + 0x25222d25, 0xdbff2526, 0x09014300, 0x0b0d0a0a, 0x0e0e1a0d, + 0x1f25371a, 0x37373725, 0x37373737, 0x37373737, 0x37373737, + 0x37373737, 0x37373737, 0x37373737, 0x37373737, 0x37373737, + 0x37373737, 0x37373737, 0x37373737, 0xff373737 }, + { 0x02030043, 0x01020202, 0x02020203, 0x03030303, 0x04040704, + 0x09040404, 0x07050606, 0x0b0b090a, 0x0a0a090a, 0x0e110d0c, + 0x0c100c0c, 0x140f0a0a, 0x1211100f, 0x0b131313, 0x1516150e, + 0x12111612, 0xdbff1213, 0x04014300, 0x05060505, 0x07070d06, + 0x0f121b0d, 0x1b1b1b12, 0x1b1b1b1b, 0x1b1b1b1b, 0x1b1b1b1b, + 0x1b1b1b1b, 0x1b1b1b1b, 0x1b1b1b1b, 0x1b1b1b1b, 0x1b1b1b1b, + 0x1b1b1b1b, 0x1b1b1b1b, 0x1b1b1b1b, 0xff1b1b1b }, + { 0x01020043, 0x01010101, 0x01010102, 0x02020202, 0x03030503, + 0x06030202, 0x05030404, 0x07070607, 0x06070607, 0x090b0908, + 0x080a0808, 0x0d0a0706, 0x0c0b0a0a, 0x070c0d0c, 0x0e0f0e09, + 0x0c0b0f0c, 0xdbff0c0c, 0x03014300, 0x03040303, 0x04040804, + 0x0a0c1208, 0x1212120c, 0x12121212, 0x12121212, 0x12121212, + 0x12121212, 0x12121212, 0x12121212, 0x12121212, 0x12121212, + 0x12121212, 0x12121212, 0x12121212, 0xff121212 }, + { 0x01020043, 0x01010101, 0x01010102, 0x02020202, 0x03030503, + 0x06030202, 0x05030404, 0x07070607, 0x06070607, 0x090b0908, + 0x080a0808, 0x0d0a0706, 0x0c0b0a0a, 0x070c0d0c, 0x0e0f0e09, + 0x0c0b0f0c, 0xdbff0c0c, 0x02014300, 0x03030202, 0x04040703, + 0x080a0f07, 0x0f0f0f0a, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, + 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, + 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0xff0f0f0f }, + { 0x01010043, 0x01010101, 0x01010101, 0x01010101, 0x02020302, + 0x04020202, 0x03020303, 0x05050405, 0x05050405, 0x07080606, + 0x06080606, 0x0a070505, 0x09080807, 0x05090909, 0x0a0b0a07, + 0x09080b09, 0xdbff0909, 0x02014300, 0x02030202, 0x03030503, + 0x07080c05, 0x0c0c0c08, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, + 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, + 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0xff0c0c0c }, + { 0x01010043, 0x01010101, 0x01010101, 0x01010101, 0x01010201, + 0x03010101, 0x02010202, 0x03030303, 0x03030303, 0x04050404, + 0x04050404, 0x06050303, 0x06050505, 0x03060606, 0x07070704, + 0x06050706, 0xdbff0606, 0x01014300, 0x01020101, 0x02020402, + 0x05060904, 0x09090906, 0x09090909, 0x09090909, 0x09090909, + 0x09090909, 0x09090909, 0x09090909, 0x09090909, 0x09090909, + 0x09090909, 0x09090909, 0x09090909, 0xff090909 }, + { 0x01010043, 0x01010101, 0x01010101, 0x01010101, 0x01010101, + 0x01010101, 0x01010101, 0x01010101, 0x01010101, 0x02020202, + 0x02020202, 0x03020101, 0x03020202, 0x01030303, 0x03030302, + 0x03020303, 0xdbff0403, 0x01014300, 0x01010101, 0x01010201, + 0x03040602, 0x06060604, 0x06060606, 0x06060606, 0x06060606, + 0x06060606, 0x06060606, 0x06060606, 0x06060606, 0x06060606, + 0x06060606, 0x06060606, 0x06060606, 0xff060606 } +}; + +static const struct v4l2_dv_timings_cap aspeed_video_timings_cap = { + .type = V4L2_DV_BT_656_1120, + .bt = { + .min_width = MIN_WIDTH, + .max_width = MAX_WIDTH, + .min_height = MIN_HEIGHT, + .max_height = MAX_HEIGHT, + .min_pixelclock = 6574080, /* 640 x 480 x 24Hz */ + .max_pixelclock = 138240000, /* 1920 x 1200 x 60Hz */ + .standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | + V4L2_DV_BT_STD_CVT | V4L2_DV_BT_STD_GTF, + .capabilities = V4L2_DV_BT_CAP_PROGRESSIVE | + V4L2_DV_BT_CAP_REDUCED_BLANKING | + V4L2_DV_BT_CAP_CUSTOM, + }, +}; + +static void aspeed_video_init_jpeg_table(u32 *table, bool yuv420) +{ + int i; + unsigned int base; + + for (i = 0; i < ASPEED_VIDEO_JPEG_NUM_QUALITIES; i++) { + base = 256 * i; /* AST HW requires this header spacing */ + memcpy(&table[base], aspeed_video_jpeg_header, + sizeof(aspeed_video_jpeg_header)); + + base += ASPEED_VIDEO_JPEG_HEADER_SIZE; + memcpy(&table[base], aspeed_video_jpeg_dct[i], + sizeof(aspeed_video_jpeg_dct[i])); + + base += ASPEED_VIDEO_JPEG_DCT_SIZE; + memcpy(&table[base], aspeed_video_jpeg_quant, + sizeof(aspeed_video_jpeg_quant)); + + if (yuv420) + table[base + 2] = 0x00220103; + } +} + +static void aspeed_video_update(struct aspeed_video *video, u32 reg, u32 clear, + u32 bits) +{ + u32 t = readl(video->base + reg); + u32 before = t; + + t &= ~clear; + t |= bits; + writel(t, video->base + reg); + dev_dbg(video->dev, "update %03x[%08x -> %08x]\n", reg, before, + readl(video->base + reg)); +} + +static u32 aspeed_video_read(struct aspeed_video *video, u32 reg) +{ + u32 t = readl(video->base + reg); + + dev_dbg(video->dev, "read %03x[%08x]\n", reg, t); + return t; +} + +static void aspeed_video_write(struct aspeed_video *video, u32 reg, u32 val) +{ + writel(val, video->base + reg); + dev_dbg(video->dev, "write %03x[%08x]\n", reg, + readl(video->base + reg)); +} + +static int aspeed_video_start_frame(struct aspeed_video *video) +{ + dma_addr_t addr; + unsigned long flags; + struct aspeed_video_buffer *buf; + u32 seq_ctrl = aspeed_video_read(video, VE_SEQ_CTRL); + + if (video->v4l2_input_status) { + dev_dbg(video->dev, "No signal; don't start frame\n"); + return 0; + } + + if (!(seq_ctrl & VE_SEQ_CTRL_COMP_BUSY) || + !(seq_ctrl & VE_SEQ_CTRL_CAP_BUSY)) { + dev_err(video->dev, "Engine busy; don't start frame\n"); + return -EBUSY; + } + + spin_lock_irqsave(&video->lock, flags); + buf = list_first_entry_or_null(&video->buffers, + struct aspeed_video_buffer, link); + if (!buf) { + spin_unlock_irqrestore(&video->lock, flags); + dev_dbg(video->dev, "No buffers; don't start frame\n"); + return -EPROTO; + } + + set_bit(VIDEO_FRAME_INPRG, &video->flags); + addr = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0); + spin_unlock_irqrestore(&video->lock, flags); + + aspeed_video_write(video, VE_COMP_PROC_OFFSET, 0); + aspeed_video_write(video, VE_COMP_OFFSET, 0); + aspeed_video_write(video, VE_COMP_ADDR, addr); + + aspeed_video_update(video, VE_INTERRUPT_CTRL, 0, + VE_INTERRUPT_COMP_COMPLETE | + VE_INTERRUPT_CAPTURE_COMPLETE); + + aspeed_video_update(video, VE_SEQ_CTRL, 0, + VE_SEQ_CTRL_TRIG_CAPTURE | VE_SEQ_CTRL_TRIG_COMP); + + return 0; +} + +static void aspeed_video_enable_mode_detect(struct aspeed_video *video) +{ + /* Enable mode detect interrupts */ + aspeed_video_update(video, VE_INTERRUPT_CTRL, 0, + VE_INTERRUPT_MODE_DETECT); + + /* Trigger mode detect */ + aspeed_video_update(video, VE_SEQ_CTRL, 0, VE_SEQ_CTRL_TRIG_MODE_DET); +} + +static void aspeed_video_reset(struct aspeed_video *video) +{ + /* Reset the engine */ + reset_control_assert(video->rst); + + /* Don't usleep here; function may be called in interrupt context */ + udelay(100); + reset_control_deassert(video->rst); +} + +static void aspeed_video_off(struct aspeed_video *video) +{ + aspeed_video_reset(video); + + /* Turn off the relevant clocks */ + clk_disable_unprepare(video->vclk); + clk_disable_unprepare(video->eclk); +} + +static void aspeed_video_on(struct aspeed_video *video) +{ + /* Turn on the relevant clocks */ + clk_prepare_enable(video->eclk); + clk_prepare_enable(video->vclk); + + aspeed_video_reset(video); +} + +static void aspeed_video_bufs_done(struct aspeed_video *video, + enum vb2_buffer_state state) +{ + unsigned long flags; + struct aspeed_video_buffer *buf; + + spin_lock_irqsave(&video->lock, flags); + list_for_each_entry(buf, &video->buffers, link) + vb2_buffer_done(&buf->vb.vb2_buf, state); + INIT_LIST_HEAD(&video->buffers); + spin_unlock_irqrestore(&video->lock, flags); +} + +static void aspeed_video_irq_res_change(struct aspeed_video *video) +{ + dev_dbg(video->dev, "Resolution changed; resetting\n"); + + set_bit(VIDEO_RES_CHANGE, &video->flags); + clear_bit(VIDEO_FRAME_INPRG, &video->flags); + + aspeed_video_off(video); + aspeed_video_bufs_done(video, VB2_BUF_STATE_ERROR); + + schedule_delayed_work(&video->res_work, RESOLUTION_CHANGE_DELAY); +} + +static irqreturn_t aspeed_video_irq(int irq, void *arg) +{ + struct aspeed_video *video = arg; + u32 sts = aspeed_video_read(video, VE_INTERRUPT_STATUS); + + /* + * Resolution changed or signal was lost; reset the engine and + * re-initialize + */ + if (sts & VE_INTERRUPT_MODE_DETECT_WD) { + aspeed_video_irq_res_change(video); + return IRQ_HANDLED; + } + + if (sts & VE_INTERRUPT_MODE_DETECT) { + if (test_bit(VIDEO_RES_DETECT, &video->flags)) { + aspeed_video_update(video, VE_INTERRUPT_CTRL, + VE_INTERRUPT_MODE_DETECT, 0); + aspeed_video_write(video, VE_INTERRUPT_STATUS, + VE_INTERRUPT_MODE_DETECT); + + set_bit(VIDEO_MODE_DETECT_DONE, &video->flags); + wake_up_interruptible_all(&video->wait); + } else { + /* + * Signal acquired while NOT doing resolution + * detection; reset the engine and re-initialize + */ + aspeed_video_irq_res_change(video); + return IRQ_HANDLED; + } + } + + if ((sts & VE_INTERRUPT_COMP_COMPLETE) && + (sts & VE_INTERRUPT_CAPTURE_COMPLETE)) { + struct aspeed_video_buffer *buf; + u32 frame_size = aspeed_video_read(video, + VE_OFFSET_COMP_STREAM); + + spin_lock(&video->lock); + clear_bit(VIDEO_FRAME_INPRG, &video->flags); + buf = list_first_entry_or_null(&video->buffers, + struct aspeed_video_buffer, + link); + if (buf) { + vb2_set_plane_payload(&buf->vb.vb2_buf, 0, frame_size); + + if (!list_is_last(&buf->link, &video->buffers)) { + buf->vb.vb2_buf.timestamp = ktime_get_ns(); + buf->vb.sequence = video->sequence++; + buf->vb.field = V4L2_FIELD_NONE; + vb2_buffer_done(&buf->vb.vb2_buf, + VB2_BUF_STATE_DONE); + list_del(&buf->link); + } + } + spin_unlock(&video->lock); + + aspeed_video_update(video, VE_SEQ_CTRL, + VE_SEQ_CTRL_TRIG_CAPTURE | + VE_SEQ_CTRL_FORCE_IDLE | + VE_SEQ_CTRL_TRIG_COMP, 0); + aspeed_video_update(video, VE_INTERRUPT_CTRL, + VE_INTERRUPT_COMP_COMPLETE | + VE_INTERRUPT_CAPTURE_COMPLETE, 0); + aspeed_video_write(video, VE_INTERRUPT_STATUS, + VE_INTERRUPT_COMP_COMPLETE | + VE_INTERRUPT_CAPTURE_COMPLETE); + + if (test_bit(VIDEO_STREAMING, &video->flags) && buf) + aspeed_video_start_frame(video); + } + + return IRQ_HANDLED; +} + +static void aspeed_video_check_and_set_polarity(struct aspeed_video *video) +{ + int i; + int hsync_counter = 0; + int vsync_counter = 0; + u32 sts; + + for (i = 0; i < NUM_POLARITY_CHECKS; ++i) { + sts = aspeed_video_read(video, VE_MODE_DETECT_STATUS); + if (sts & VE_MODE_DETECT_STATUS_VSYNC) + vsync_counter--; + else + vsync_counter++; + + if (sts & VE_MODE_DETECT_STATUS_HSYNC) + hsync_counter--; + else + hsync_counter++; + } + + if (hsync_counter < 0 || vsync_counter < 0) { + u32 ctrl; + + if (hsync_counter < 0) { + ctrl = VE_CTRL_HSYNC_POL; + video->detected_timings.polarities &= + ~V4L2_DV_HSYNC_POS_POL; + } else { + video->detected_timings.polarities |= + V4L2_DV_HSYNC_POS_POL; + } + + if (vsync_counter < 0) { + ctrl = VE_CTRL_VSYNC_POL; + video->detected_timings.polarities &= + ~V4L2_DV_VSYNC_POS_POL; + } else { + video->detected_timings.polarities |= + V4L2_DV_VSYNC_POS_POL; + } + + aspeed_video_update(video, VE_CTRL, 0, ctrl); + } +} + +static bool aspeed_video_alloc_buf(struct aspeed_video *video, + struct aspeed_video_addr *addr, + unsigned int size) +{ + addr->virt = dma_alloc_coherent(video->dev, size, &addr->dma, + GFP_KERNEL); + if (!addr->virt) + return false; + + addr->size = size; + return true; +} + +static void aspeed_video_free_buf(struct aspeed_video *video, + struct aspeed_video_addr *addr) +{ + dma_free_coherent(video->dev, addr->size, addr->virt, addr->dma); + addr->size = 0; + addr->dma = 0ULL; + addr->virt = NULL; +} + +/* + * Get the minimum HW-supported compression buffer size for the frame size. + * Assume worst-case JPEG compression size is 1/8 raw size. This should be + * plenty even for maximum quality; any worse and the engine will simply return + * incomplete JPEGs. + */ +static void aspeed_video_calc_compressed_size(struct aspeed_video *video, + unsigned int frame_size) +{ + int i, j; + u32 compression_buffer_size_reg = 0; + unsigned int size; + const unsigned int num_compression_packets = 4; + const unsigned int compression_packet_size = 1024; + const unsigned int max_compressed_size = frame_size / 2; /* 4bpp / 8 */ + + video->max_compressed_size = UINT_MAX; + + for (i = 0; i < 6; ++i) { + for (j = 0; j < 8; ++j) { + size = (num_compression_packets << i) * + (compression_packet_size << j); + if (size < max_compressed_size) + continue; + + if (size < video->max_compressed_size) { + compression_buffer_size_reg = (i << 3) | j; + video->max_compressed_size = size; + } + } + } + + aspeed_video_write(video, VE_STREAM_BUF_SIZE, + compression_buffer_size_reg); + + dev_dbg(video->dev, "Max compressed size: %x\n", + video->max_compressed_size); +} + +#define res_check(v) test_and_clear_bit(VIDEO_MODE_DETECT_DONE, &(v)->flags) + +static void aspeed_video_get_resolution(struct aspeed_video *video) +{ + bool invalid_resolution = true; + int rc; + int tries = 0; + u32 mds; + u32 src_lr_edge; + u32 src_tb_edge; + u32 sync; + struct v4l2_bt_timings *det = &video->detected_timings; + + det->width = MIN_WIDTH; + det->height = MIN_HEIGHT; + video->v4l2_input_status = V4L2_IN_ST_NO_SIGNAL; + + /* + * Since we need max buffer size for detection, free the second source + * buffer first. + */ + if (video->srcs[1].size) + aspeed_video_free_buf(video, &video->srcs[1]); + + if (video->srcs[0].size < VE_MAX_SRC_BUFFER_SIZE) { + if (video->srcs[0].size) + aspeed_video_free_buf(video, &video->srcs[0]); + + if (!aspeed_video_alloc_buf(video, &video->srcs[0], + VE_MAX_SRC_BUFFER_SIZE)) { + dev_err(video->dev, + "Failed to allocate source buffers\n"); + return; + } + } + + aspeed_video_write(video, VE_SRC0_ADDR, video->srcs[0].dma); + + do { + if (tries) { + set_current_state(TASK_INTERRUPTIBLE); + if (schedule_timeout(INVALID_RESOLUTION_DELAY)) + return; + } + + set_bit(VIDEO_RES_DETECT, &video->flags); + aspeed_video_enable_mode_detect(video); + + rc = wait_event_interruptible_timeout(video->wait, + res_check(video), + MODE_DETECT_TIMEOUT); + if (!rc) { + dev_err(video->dev, "Timed out; first mode detect\n"); + clear_bit(VIDEO_RES_DETECT, &video->flags); + return; + } + + /* Disable mode detect in order to re-trigger */ + aspeed_video_update(video, VE_SEQ_CTRL, + VE_SEQ_CTRL_TRIG_MODE_DET, 0); + + aspeed_video_check_and_set_polarity(video); + + aspeed_video_enable_mode_detect(video); + + rc = wait_event_interruptible_timeout(video->wait, + res_check(video), + MODE_DETECT_TIMEOUT); + clear_bit(VIDEO_RES_DETECT, &video->flags); + if (!rc) { + dev_err(video->dev, "Timed out; second mode detect\n"); + return; + } + + src_lr_edge = aspeed_video_read(video, VE_SRC_LR_EDGE_DET); + src_tb_edge = aspeed_video_read(video, VE_SRC_TB_EDGE_DET); + mds = aspeed_video_read(video, VE_MODE_DETECT_STATUS); + sync = aspeed_video_read(video, VE_SYNC_STATUS); + + video->frame_bottom = (src_tb_edge & VE_SRC_TB_EDGE_DET_BOT) >> + VE_SRC_TB_EDGE_DET_BOT_SHF; + video->frame_top = src_tb_edge & VE_SRC_TB_EDGE_DET_TOP; + det->vfrontporch = video->frame_top; + det->vbackporch = ((mds & VE_MODE_DETECT_V_LINES) >> + VE_MODE_DETECT_V_LINES_SHF) - video->frame_bottom; + det->vsync = (sync & VE_SYNC_STATUS_VSYNC) >> + VE_SYNC_STATUS_VSYNC_SHF; + if (video->frame_top > video->frame_bottom) + continue; + + video->frame_right = (src_lr_edge & VE_SRC_LR_EDGE_DET_RT) >> + VE_SRC_LR_EDGE_DET_RT_SHF; + video->frame_left = src_lr_edge & VE_SRC_LR_EDGE_DET_LEFT; + det->hfrontporch = video->frame_left; + det->hbackporch = (mds & VE_MODE_DETECT_H_PIXELS) - + video->frame_right; + det->hsync = sync & VE_SYNC_STATUS_HSYNC; + if (video->frame_left > video->frame_right) + continue; + + invalid_resolution = false; + } while (invalid_resolution && (tries++ < INVALID_RESOLUTION_RETRIES)); + + if (invalid_resolution) { + dev_err(video->dev, "Invalid resolution detected\n"); + return; + } + + det->height = (video->frame_bottom - video->frame_top) + 1; + det->width = (video->frame_right - video->frame_left) + 1; + video->v4l2_input_status = 0; + + /* + * Enable mode-detect watchdog, resolution-change watchdog and + * automatic compression after frame capture. + */ + aspeed_video_update(video, VE_INTERRUPT_CTRL, 0, + VE_INTERRUPT_MODE_DETECT_WD); + aspeed_video_update(video, VE_SEQ_CTRL, 0, + VE_SEQ_CTRL_AUTO_COMP | VE_SEQ_CTRL_EN_WATCHDOG); + + dev_dbg(video->dev, "Got resolution: %dx%d\n", det->width, + det->height); +} + +static void aspeed_video_set_resolution(struct aspeed_video *video) +{ + struct v4l2_bt_timings *act = &video->active_timings; + unsigned int size = act->width * act->height; + + aspeed_video_calc_compressed_size(video, size); + + /* Don't use direct mode below 1024 x 768 (irqs don't fire) */ + if (size < DIRECT_FETCH_THRESHOLD) { + aspeed_video_write(video, VE_TGS_0, + FIELD_PREP(VE_TGS_FIRST, + video->frame_left - 1) | + FIELD_PREP(VE_TGS_LAST, + video->frame_right)); + aspeed_video_write(video, VE_TGS_1, + FIELD_PREP(VE_TGS_FIRST, video->frame_top) | + FIELD_PREP(VE_TGS_LAST, + video->frame_bottom + 1)); + aspeed_video_update(video, VE_CTRL, 0, VE_CTRL_INT_DE); + } else { + aspeed_video_update(video, VE_CTRL, 0, VE_CTRL_DIRECT_FETCH); + } + + /* Set capture/compression frame sizes */ + aspeed_video_write(video, VE_CAP_WINDOW, + act->width << 16 | act->height); + aspeed_video_write(video, VE_COMP_WINDOW, + act->width << 16 | act->height); + aspeed_video_write(video, VE_SRC_SCANLINE_OFFSET, act->width * 4); + + size *= 4; + + if (size == video->srcs[0].size / 2) { + aspeed_video_write(video, VE_SRC1_ADDR, + video->srcs[0].dma + size); + } else if (size == video->srcs[0].size) { + if (!aspeed_video_alloc_buf(video, &video->srcs[1], size)) + goto err_mem; + + aspeed_video_write(video, VE_SRC1_ADDR, video->srcs[1].dma); + } else { + aspeed_video_free_buf(video, &video->srcs[0]); + + if (!aspeed_video_alloc_buf(video, &video->srcs[0], size)) + goto err_mem; + + if (!aspeed_video_alloc_buf(video, &video->srcs[1], size)) + goto err_mem; + + aspeed_video_write(video, VE_SRC0_ADDR, video->srcs[0].dma); + aspeed_video_write(video, VE_SRC1_ADDR, video->srcs[1].dma); + } + + return; + +err_mem: + dev_err(video->dev, "Failed to allocate source buffers\n"); + + if (video->srcs[0].size) + aspeed_video_free_buf(video, &video->srcs[0]); +} + +static void aspeed_video_init_regs(struct aspeed_video *video) +{ + u32 comp_ctrl = VE_COMP_CTRL_RSVD | + FIELD_PREP(VE_COMP_CTRL_DCT_LUM, video->jpeg_quality) | + FIELD_PREP(VE_COMP_CTRL_DCT_CHR, video->jpeg_quality | 0x10); + u32 ctrl = VE_CTRL_AUTO_OR_CURSOR; + u32 seq_ctrl = VE_SEQ_CTRL_JPEG_MODE; + + if (video->frame_rate) + ctrl |= FIELD_PREP(VE_CTRL_FRC, video->frame_rate); + + if (video->yuv420) + seq_ctrl |= VE_SEQ_CTRL_YUV420; + + /* Unlock VE registers */ + aspeed_video_write(video, VE_PROTECTION_KEY, VE_PROTECTION_KEY_UNLOCK); + + /* Disable interrupts */ + aspeed_video_write(video, VE_INTERRUPT_CTRL, 0); + aspeed_video_write(video, VE_INTERRUPT_STATUS, 0xffffffff); + + /* Clear the offset */ + aspeed_video_write(video, VE_COMP_PROC_OFFSET, 0); + aspeed_video_write(video, VE_COMP_OFFSET, 0); + + aspeed_video_write(video, VE_JPEG_ADDR, video->jpeg.dma); + + /* Set control registers */ + aspeed_video_write(video, VE_SEQ_CTRL, seq_ctrl); + aspeed_video_write(video, VE_CTRL, ctrl); + aspeed_video_write(video, VE_COMP_CTRL, comp_ctrl); + + /* Don't downscale */ + aspeed_video_write(video, VE_SCALING_FACTOR, 0x10001000); + aspeed_video_write(video, VE_SCALING_FILTER0, 0x00200000); + aspeed_video_write(video, VE_SCALING_FILTER1, 0x00200000); + aspeed_video_write(video, VE_SCALING_FILTER2, 0x00200000); + aspeed_video_write(video, VE_SCALING_FILTER3, 0x00200000); + + /* Set mode detection defaults */ + aspeed_video_write(video, VE_MODE_DETECT, 0x22666500); +} + +static void aspeed_video_start(struct aspeed_video *video) +{ + aspeed_video_on(video); + + aspeed_video_init_regs(video); + + /* Resolution set to 640x480 if no signal found */ + aspeed_video_get_resolution(video); + + /* Set timings since the device is being opened for the first time */ + video->active_timings = video->detected_timings; + aspeed_video_set_resolution(video); + + video->pix_fmt.width = video->active_timings.width; + video->pix_fmt.height = video->active_timings.height; + video->pix_fmt.sizeimage = video->max_compressed_size; +} + +static void aspeed_video_stop(struct aspeed_video *video) +{ + set_bit(VIDEO_STOPPED, &video->flags); + cancel_delayed_work_sync(&video->res_work); + + aspeed_video_off(video); + + if (video->srcs[0].size) + aspeed_video_free_buf(video, &video->srcs[0]); + + if (video->srcs[1].size) + aspeed_video_free_buf(video, &video->srcs[1]); + + video->v4l2_input_status = V4L2_IN_ST_NO_SIGNAL; + video->flags = 0; +} + +static int aspeed_video_querycap(struct file *file, void *fh, + struct v4l2_capability *cap) +{ + strscpy(cap->driver, DEVICE_NAME, sizeof(cap->driver)); + strscpy(cap->card, "Aspeed Video Engine", sizeof(cap->card)); + snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s", + DEVICE_NAME); + + return 0; +} + +static int aspeed_video_enum_format(struct file *file, void *fh, + struct v4l2_fmtdesc *f) +{ + if (f->index) + return -EINVAL; + + f->pixelformat = V4L2_PIX_FMT_JPEG; + + return 0; +} + +static int aspeed_video_get_format(struct file *file, void *fh, + struct v4l2_format *f) +{ + struct aspeed_video *video = video_drvdata(file); + + f->fmt.pix = video->pix_fmt; + + return 0; +} + +static int aspeed_video_enum_input(struct file *file, void *fh, + struct v4l2_input *inp) +{ + struct aspeed_video *video = video_drvdata(file); + + if (inp->index) + return -EINVAL; + + strscpy(inp->name, "Host VGA capture", sizeof(inp->name)); + inp->type = V4L2_INPUT_TYPE_CAMERA; + inp->capabilities = V4L2_IN_CAP_DV_TIMINGS; + inp->status = video->v4l2_input_status; + + return 0; +} + +static int aspeed_video_get_input(struct file *file, void *fh, unsigned int *i) +{ + *i = 0; + + return 0; +} + +static int aspeed_video_set_input(struct file *file, void *fh, unsigned int i) +{ + if (i) + return -EINVAL; + + return 0; +} + +static int aspeed_video_get_parm(struct file *file, void *fh, + struct v4l2_streamparm *a) +{ + struct aspeed_video *video = video_drvdata(file); + + a->parm.capture.capability = V4L2_CAP_TIMEPERFRAME; + a->parm.capture.readbuffers = 3; + a->parm.capture.timeperframe.numerator = 1; + if (!video->frame_rate) + a->parm.capture.timeperframe.denominator = MAX_FRAME_RATE; + else + a->parm.capture.timeperframe.denominator = video->frame_rate; + + return 0; +} + +static int aspeed_video_set_parm(struct file *file, void *fh, + struct v4l2_streamparm *a) +{ + unsigned int frame_rate = 0; + struct aspeed_video *video = video_drvdata(file); + + a->parm.capture.capability = V4L2_CAP_TIMEPERFRAME; + a->parm.capture.readbuffers = 3; + + if (a->parm.capture.timeperframe.numerator) + frame_rate = a->parm.capture.timeperframe.denominator / + a->parm.capture.timeperframe.numerator; + + if (!frame_rate || frame_rate > MAX_FRAME_RATE) { + frame_rate = 0; + a->parm.capture.timeperframe.denominator = MAX_FRAME_RATE; + a->parm.capture.timeperframe.numerator = 1; + } + + if (video->frame_rate != frame_rate) { + video->frame_rate = frame_rate; + aspeed_video_update(video, VE_CTRL, VE_CTRL_FRC, + FIELD_PREP(VE_CTRL_FRC, frame_rate)); + } + + return 0; +} + +static int aspeed_video_enum_framesizes(struct file *file, void *fh, + struct v4l2_frmsizeenum *fsize) +{ + struct aspeed_video *video = video_drvdata(file); + + if (fsize->index) + return -EINVAL; + + if (fsize->pixel_format != V4L2_PIX_FMT_JPEG) + return -EINVAL; + + fsize->discrete.width = video->pix_fmt.width; + fsize->discrete.height = video->pix_fmt.height; + fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE; + + return 0; +} + +static int aspeed_video_enum_frameintervals(struct file *file, void *fh, + struct v4l2_frmivalenum *fival) +{ + struct aspeed_video *video = video_drvdata(file); + + if (fival->index) + return -EINVAL; + + if (fival->width != video->detected_timings.width || + fival->height != video->detected_timings.height) + return -EINVAL; + + if (fival->pixel_format != V4L2_PIX_FMT_JPEG) + return -EINVAL; + + fival->type = V4L2_FRMIVAL_TYPE_CONTINUOUS; + + fival->stepwise.min.denominator = MAX_FRAME_RATE; + fival->stepwise.min.numerator = 1; + fival->stepwise.max.denominator = 1; + fival->stepwise.max.numerator = 1; + fival->stepwise.step = fival->stepwise.max; + + return 0; +} + +static int aspeed_video_set_dv_timings(struct file *file, void *fh, + struct v4l2_dv_timings *timings) +{ + struct aspeed_video *video = video_drvdata(file); + + if (timings->bt.width == video->active_timings.width && + timings->bt.height == video->active_timings.height) + return 0; + + if (vb2_is_busy(&video->queue)) + return -EBUSY; + + video->active_timings = timings->bt; + + aspeed_video_set_resolution(video); + + video->pix_fmt.width = timings->bt.width; + video->pix_fmt.height = timings->bt.height; + video->pix_fmt.sizeimage = video->max_compressed_size; + + timings->type = V4L2_DV_BT_656_1120; + + return 0; +} + +static int aspeed_video_get_dv_timings(struct file *file, void *fh, + struct v4l2_dv_timings *timings) +{ + struct aspeed_video *video = video_drvdata(file); + + timings->type = V4L2_DV_BT_656_1120; + timings->bt = video->active_timings; + + return 0; +} + +static int aspeed_video_query_dv_timings(struct file *file, void *fh, + struct v4l2_dv_timings *timings) +{ + int rc; + struct aspeed_video *video = video_drvdata(file); + + /* + * This blocks only if the driver is currently in the process of + * detecting a new resolution; in the event of no signal or timeout + * this function is woken up. + */ + if (file->f_flags & O_NONBLOCK) { + if (test_bit(VIDEO_RES_CHANGE, &video->flags)) + return -EAGAIN; + } else { + rc = wait_event_interruptible(video->wait, + !test_bit(VIDEO_RES_CHANGE, + &video->flags)); + if (rc) + return -EINTR; + } + + timings->type = V4L2_DV_BT_656_1120; + timings->bt = video->detected_timings; + + return video->v4l2_input_status ? -ENOLINK : 0; +} + +static int aspeed_video_enum_dv_timings(struct file *file, void *fh, + struct v4l2_enum_dv_timings *timings) +{ + return v4l2_enum_dv_timings_cap(timings, &aspeed_video_timings_cap, + NULL, NULL); +} + +static int aspeed_video_dv_timings_cap(struct file *file, void *fh, + struct v4l2_dv_timings_cap *cap) +{ + *cap = aspeed_video_timings_cap; + + return 0; +} + +static int aspeed_video_sub_event(struct v4l2_fh *fh, + const struct v4l2_event_subscription *sub) +{ + switch (sub->type) { + case V4L2_EVENT_SOURCE_CHANGE: + return v4l2_src_change_event_subscribe(fh, sub); + } + + return v4l2_ctrl_subscribe_event(fh, sub); +} + +static const struct v4l2_ioctl_ops aspeed_video_ioctl_ops = { + .vidioc_querycap = aspeed_video_querycap, + + .vidioc_enum_fmt_vid_cap = aspeed_video_enum_format, + .vidioc_g_fmt_vid_cap = aspeed_video_get_format, + .vidioc_s_fmt_vid_cap = aspeed_video_get_format, + .vidioc_try_fmt_vid_cap = aspeed_video_get_format, + + .vidioc_reqbufs = vb2_ioctl_reqbufs, + .vidioc_querybuf = vb2_ioctl_querybuf, + .vidioc_qbuf = vb2_ioctl_qbuf, + .vidioc_expbuf = vb2_ioctl_expbuf, + .vidioc_dqbuf = vb2_ioctl_dqbuf, + .vidioc_create_bufs = vb2_ioctl_create_bufs, + .vidioc_prepare_buf = vb2_ioctl_prepare_buf, + .vidioc_streamon = vb2_ioctl_streamon, + .vidioc_streamoff = vb2_ioctl_streamoff, + + .vidioc_enum_input = aspeed_video_enum_input, + .vidioc_g_input = aspeed_video_get_input, + .vidioc_s_input = aspeed_video_set_input, + + .vidioc_g_parm = aspeed_video_get_parm, + .vidioc_s_parm = aspeed_video_set_parm, + .vidioc_enum_framesizes = aspeed_video_enum_framesizes, + .vidioc_enum_frameintervals = aspeed_video_enum_frameintervals, + + .vidioc_s_dv_timings = aspeed_video_set_dv_timings, + .vidioc_g_dv_timings = aspeed_video_get_dv_timings, + .vidioc_query_dv_timings = aspeed_video_query_dv_timings, + .vidioc_enum_dv_timings = aspeed_video_enum_dv_timings, + .vidioc_dv_timings_cap = aspeed_video_dv_timings_cap, + + .vidioc_subscribe_event = aspeed_video_sub_event, + .vidioc_unsubscribe_event = v4l2_event_unsubscribe, +}; + +static void aspeed_video_update_jpeg_quality(struct aspeed_video *video) +{ + u32 comp_ctrl = FIELD_PREP(VE_COMP_CTRL_DCT_LUM, video->jpeg_quality) | + FIELD_PREP(VE_COMP_CTRL_DCT_CHR, video->jpeg_quality | 0x10); + + aspeed_video_update(video, VE_COMP_CTRL, + VE_COMP_CTRL_DCT_LUM | VE_COMP_CTRL_DCT_CHR, + comp_ctrl); +} + +static void aspeed_video_update_subsampling(struct aspeed_video *video) +{ + if (video->jpeg.virt) + aspeed_video_init_jpeg_table(video->jpeg.virt, video->yuv420); + + if (video->yuv420) + aspeed_video_update(video, VE_SEQ_CTRL, 0, VE_SEQ_CTRL_YUV420); + else + aspeed_video_update(video, VE_SEQ_CTRL, VE_SEQ_CTRL_YUV420, 0); +} + +static int aspeed_video_set_ctrl(struct v4l2_ctrl *ctrl) +{ + struct aspeed_video *video = container_of(ctrl->handler, + struct aspeed_video, + ctrl_handler); + + switch (ctrl->id) { + case V4L2_CID_JPEG_COMPRESSION_QUALITY: + video->jpeg_quality = ctrl->val; + aspeed_video_update_jpeg_quality(video); + break; + case V4L2_CID_JPEG_CHROMA_SUBSAMPLING: + if (ctrl->val == V4L2_JPEG_CHROMA_SUBSAMPLING_420) { + video->yuv420 = true; + aspeed_video_update_subsampling(video); + } else { + video->yuv420 = false; + aspeed_video_update_subsampling(video); + } + break; + default: + return -EINVAL; + } + + return 0; +} + +static const struct v4l2_ctrl_ops aspeed_video_ctrl_ops = { + .s_ctrl = aspeed_video_set_ctrl, +}; + +static void aspeed_video_resolution_work(struct work_struct *work) +{ + struct delayed_work *dwork = to_delayed_work(work); + struct aspeed_video *video = container_of(dwork, struct aspeed_video, + res_work); + u32 input_status = video->v4l2_input_status; + + aspeed_video_on(video); + + /* Exit early in case no clients remain */ + if (test_bit(VIDEO_STOPPED, &video->flags)) + goto done; + + aspeed_video_init_regs(video); + + aspeed_video_get_resolution(video); + + if (video->detected_timings.width != video->active_timings.width || + video->detected_timings.height != video->active_timings.height || + input_status != video->v4l2_input_status) { + static const struct v4l2_event ev = { + .type = V4L2_EVENT_SOURCE_CHANGE, + .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, + }; + + v4l2_event_queue(&video->vdev, &ev); + } else if (test_bit(VIDEO_STREAMING, &video->flags)) { + /* No resolution change so just restart streaming */ + aspeed_video_start_frame(video); + } + +done: + clear_bit(VIDEO_RES_CHANGE, &video->flags); + wake_up_interruptible_all(&video->wait); +} + +static int aspeed_video_open(struct file *file) +{ + int rc; + struct aspeed_video *video = video_drvdata(file); + + mutex_lock(&video->video_lock); + + rc = v4l2_fh_open(file); + if (rc) { + mutex_unlock(&video->video_lock); + return rc; + } + + if (v4l2_fh_is_singular_file(file)) + aspeed_video_start(video); + + mutex_unlock(&video->video_lock); + + return 0; +} + +static int aspeed_video_release(struct file *file) +{ + int rc; + struct aspeed_video *video = video_drvdata(file); + + mutex_lock(&video->video_lock); + + if (v4l2_fh_is_singular_file(file)) + aspeed_video_stop(video); + + rc = _vb2_fop_release(file, NULL); + + mutex_unlock(&video->video_lock); + + return rc; +} + +static const struct v4l2_file_operations aspeed_video_v4l2_fops = { + .owner = THIS_MODULE, + .read = vb2_fop_read, + .poll = vb2_fop_poll, + .unlocked_ioctl = video_ioctl2, + .mmap = vb2_fop_mmap, + .open = aspeed_video_open, + .release = aspeed_video_release, +}; + +static int aspeed_video_queue_setup(struct vb2_queue *q, + unsigned int *num_buffers, + unsigned int *num_planes, + unsigned int sizes[], + struct device *alloc_devs[]) +{ + struct aspeed_video *video = vb2_get_drv_priv(q); + + if (*num_planes) { + if (sizes[0] < video->max_compressed_size) + return -EINVAL; + + return 0; + } + + *num_planes = 1; + sizes[0] = video->max_compressed_size; + + return 0; +} + +static int aspeed_video_buf_prepare(struct vb2_buffer *vb) +{ + struct aspeed_video *video = vb2_get_drv_priv(vb->vb2_queue); + + if (vb2_plane_size(vb, 0) < video->max_compressed_size) + return -EINVAL; + + return 0; +} + +static int aspeed_video_start_streaming(struct vb2_queue *q, + unsigned int count) +{ + int rc; + struct aspeed_video *video = vb2_get_drv_priv(q); + + video->sequence = 0; + + rc = aspeed_video_start_frame(video); + if (rc) { + aspeed_video_bufs_done(video, VB2_BUF_STATE_QUEUED); + return rc; + } + + set_bit(VIDEO_STREAMING, &video->flags); + return 0; +} + +static void aspeed_video_stop_streaming(struct vb2_queue *q) +{ + int rc; + struct aspeed_video *video = vb2_get_drv_priv(q); + + clear_bit(VIDEO_STREAMING, &video->flags); + + rc = wait_event_timeout(video->wait, + !test_bit(VIDEO_FRAME_INPRG, &video->flags), + STOP_TIMEOUT); + if (!rc) { + dev_err(video->dev, "Timed out when stopping streaming\n"); + + /* + * Need to force stop any DMA and try and get HW into a good + * state for future calls to start streaming again. + */ + aspeed_video_reset(video); + aspeed_video_init_regs(video); + + aspeed_video_get_resolution(video); + } + + aspeed_video_bufs_done(video, VB2_BUF_STATE_ERROR); +} + +static void aspeed_video_buf_queue(struct vb2_buffer *vb) +{ + bool empty; + struct aspeed_video *video = vb2_get_drv_priv(vb->vb2_queue); + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); + struct aspeed_video_buffer *avb = to_aspeed_video_buffer(vbuf); + unsigned long flags; + + spin_lock_irqsave(&video->lock, flags); + empty = list_empty(&video->buffers); + list_add_tail(&avb->link, &video->buffers); + spin_unlock_irqrestore(&video->lock, flags); + + if (test_bit(VIDEO_STREAMING, &video->flags) && + !test_bit(VIDEO_FRAME_INPRG, &video->flags) && empty) + aspeed_video_start_frame(video); +} + +static const struct vb2_ops aspeed_video_vb2_ops = { + .queue_setup = aspeed_video_queue_setup, + .wait_prepare = vb2_ops_wait_prepare, + .wait_finish = vb2_ops_wait_finish, + .buf_prepare = aspeed_video_buf_prepare, + .start_streaming = aspeed_video_start_streaming, + .stop_streaming = aspeed_video_stop_streaming, + .buf_queue = aspeed_video_buf_queue, +}; + +static int aspeed_video_setup_video(struct aspeed_video *video) +{ + const u64 mask = ~(BIT(V4L2_JPEG_CHROMA_SUBSAMPLING_444) | + BIT(V4L2_JPEG_CHROMA_SUBSAMPLING_420)); + struct v4l2_device *v4l2_dev = &video->v4l2_dev; + struct vb2_queue *vbq = &video->queue; + struct video_device *vdev = &video->vdev; + int rc; + + video->pix_fmt.pixelformat = V4L2_PIX_FMT_JPEG; + video->pix_fmt.field = V4L2_FIELD_NONE; + video->pix_fmt.colorspace = V4L2_COLORSPACE_SRGB; + video->pix_fmt.quantization = V4L2_QUANTIZATION_FULL_RANGE; + video->v4l2_input_status = V4L2_IN_ST_NO_SIGNAL; + + rc = v4l2_device_register(video->dev, v4l2_dev); + if (rc) { + dev_err(video->dev, "Failed to register v4l2 device\n"); + return rc; + } + + v4l2_ctrl_handler_init(&video->ctrl_handler, 2); + v4l2_ctrl_new_std(&video->ctrl_handler, &aspeed_video_ctrl_ops, + V4L2_CID_JPEG_COMPRESSION_QUALITY, 0, + ASPEED_VIDEO_JPEG_NUM_QUALITIES - 1, 1, 0); + v4l2_ctrl_new_std_menu(&video->ctrl_handler, &aspeed_video_ctrl_ops, + V4L2_CID_JPEG_CHROMA_SUBSAMPLING, + V4L2_JPEG_CHROMA_SUBSAMPLING_420, mask, + V4L2_JPEG_CHROMA_SUBSAMPLING_444); + + if (video->ctrl_handler.error) { + v4l2_ctrl_handler_free(&video->ctrl_handler); + v4l2_device_unregister(v4l2_dev); + + dev_err(video->dev, "Failed to init controls: %d\n", + video->ctrl_handler.error); + return rc; + } + + v4l2_dev->ctrl_handler = &video->ctrl_handler; + + vbq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + vbq->io_modes = VB2_MMAP | VB2_READ | VB2_DMABUF; + vbq->dev = v4l2_dev->dev; + vbq->lock = &video->video_lock; + vbq->ops = &aspeed_video_vb2_ops; + vbq->mem_ops = &vb2_dma_contig_memops; + vbq->drv_priv = video; + vbq->buf_struct_size = sizeof(struct aspeed_video_buffer); + vbq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + vbq->min_buffers_needed = 3; + + rc = vb2_queue_init(vbq); + if (rc) { + v4l2_ctrl_handler_free(&video->ctrl_handler); + v4l2_device_unregister(v4l2_dev); + + dev_err(video->dev, "Failed to init vb2 queue\n"); + return rc; + } + + vdev->queue = vbq; + vdev->fops = &aspeed_video_v4l2_fops; + vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_READWRITE | + V4L2_CAP_STREAMING; + vdev->v4l2_dev = v4l2_dev; + strscpy(vdev->name, DEVICE_NAME, sizeof(vdev->name)); + vdev->vfl_type = VFL_TYPE_GRABBER; + vdev->vfl_dir = VFL_DIR_RX; + vdev->release = video_device_release_empty; + vdev->ioctl_ops = &aspeed_video_ioctl_ops; + vdev->lock = &video->video_lock; + + video_set_drvdata(vdev, video); + rc = video_register_device(vdev, VFL_TYPE_GRABBER, 0); + if (rc) { + vb2_queue_release(vbq); + v4l2_ctrl_handler_free(&video->ctrl_handler); + v4l2_device_unregister(v4l2_dev); + + dev_err(video->dev, "Failed to register video device\n"); + return rc; + } + + return 0; +} + +static int aspeed_video_init(struct aspeed_video *video) +{ + int irq; + int rc; + struct device *dev = video->dev; + + irq = irq_of_parse_and_map(dev->of_node, 0); + if (!irq) { + dev_err(dev, "Unable to find IRQ\n"); + return -ENODEV; + } + + rc = devm_request_irq(dev, irq, aspeed_video_irq, IRQF_SHARED, + DEVICE_NAME, video); + if (rc < 0) { + dev_err(dev, "Unable to request IRQ %d\n", irq); + return rc; + } + + video->eclk = devm_clk_get(dev, "eclk"); + if (IS_ERR(video->eclk)) { + dev_err(dev, "Unable to get ECLK\n"); + return PTR_ERR(video->eclk); + } + + video->vclk = devm_clk_get(dev, "vclk"); + if (IS_ERR(video->vclk)) { + dev_err(dev, "Unable to get VCLK\n"); + return PTR_ERR(video->vclk); + } + + video->rst = devm_reset_control_get_exclusive(dev, NULL); + if (IS_ERR(video->rst)) { + dev_err(dev, "Unable to get VE reset\n"); + return PTR_ERR(video->rst); + } + + rc = of_reserved_mem_device_init(dev); + if (rc) { + dev_err(dev, "Unable to reserve memory\n"); + return rc; + } + + rc = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); + if (rc) { + dev_err(dev, "Failed to set DMA mask\n"); + of_reserved_mem_device_release(dev); + return rc; + } + + if (!aspeed_video_alloc_buf(video, &video->jpeg, + VE_JPEG_HEADER_SIZE)) { + dev_err(dev, "Failed to allocate DMA for JPEG header\n"); + of_reserved_mem_device_release(dev); + return rc; + } + + aspeed_video_init_jpeg_table(video->jpeg.virt, video->yuv420); + + return 0; +} + +static int aspeed_video_probe(struct platform_device *pdev) +{ + int rc; + struct resource *res; + struct aspeed_video *video = kzalloc(sizeof(*video), GFP_KERNEL); + + if (!video) + return -ENOMEM; + + video->frame_rate = 30; + video->dev = &pdev->dev; + mutex_init(&video->video_lock); + init_waitqueue_head(&video->wait); + INIT_DELAYED_WORK(&video->res_work, aspeed_video_resolution_work); + INIT_LIST_HEAD(&video->buffers); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + video->base = devm_ioremap_resource(video->dev, res); + + if (IS_ERR(video->base)) + return PTR_ERR(video->base); + + rc = aspeed_video_init(video); + if (rc) + return rc; + + rc = aspeed_video_setup_video(video); + if (rc) + return rc; + + return 0; +} + +static int aspeed_video_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct v4l2_device *v4l2_dev = dev_get_drvdata(dev); + struct aspeed_video *video = to_aspeed_video(v4l2_dev); + + video_unregister_device(&video->vdev); + + vb2_queue_release(&video->queue); + + v4l2_ctrl_handler_free(&video->ctrl_handler); + + v4l2_device_unregister(v4l2_dev); + + dma_free_coherent(video->dev, VE_JPEG_HEADER_SIZE, video->jpeg.virt, + video->jpeg.dma); + + of_reserved_mem_device_release(dev); + + return 0; +} + +static const struct of_device_id aspeed_video_of_match[] = { + { .compatible = "aspeed,ast2400-video-engine" }, + { .compatible = "aspeed,ast2500-video-engine" }, + {} +}; +MODULE_DEVICE_TABLE(of, aspeed_video_of_match); + +static struct platform_driver aspeed_video_driver = { + .driver = { + .name = DEVICE_NAME, + .of_match_table = aspeed_video_of_match, + }, + .probe = aspeed_video_probe, + .remove = aspeed_video_remove, +}; + +module_platform_driver(aspeed_video_driver); + +MODULE_DESCRIPTION("ASPEED Video Engine Driver"); +MODULE_AUTHOR("Eddie James"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/media/platform/coda/coda-bit.c b/drivers/media/platform/coda/coda-bit.c index d26c2d85a009..8e0194993a52 100644 --- a/drivers/media/platform/coda/coda-bit.c +++ b/drivers/media/platform/coda/coda-bit.c @@ -253,7 +253,6 @@ void coda_fill_bitstream(struct coda_ctx *ctx, struct list_head *buffer_list) { struct vb2_v4l2_buffer *src_buf; struct coda_buffer_meta *meta; - unsigned long flags; u32 start; if (ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG) @@ -269,6 +268,23 @@ void coda_fill_bitstream(struct coda_ctx *ctx, struct list_head *buffer_list) ctx->num_metas > 1) break; + if (ctx->num_internal_frames && + ctx->num_metas >= ctx->num_internal_frames) { + meta = list_first_entry(&ctx->buffer_meta_list, + struct coda_buffer_meta, list); + + /* + * If we managed to fill in at least a full reorder + * window of buffers (num_internal_frames is a + * conservative estimate for this) and the bitstream + * prefetcher has at least 2 256 bytes periods beyond + * the first buffer to fetch, we can safely stop queuing + * in order to limit the decoder drain latency. + */ + if (coda_bitstream_can_fetch_past(ctx, meta->end)) + break; + } + src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); /* Drop frames that do not start/end with a SOI/EOI markers */ @@ -299,8 +315,7 @@ void coda_fill_bitstream(struct coda_ctx *ctx, struct list_head *buffer_list) } /* Buffer start position */ - start = ctx->bitstream_fifo.kfifo.in & - ctx->bitstream_fifo.kfifo.mask; + start = ctx->bitstream_fifo.kfifo.in; if (coda_bitstream_try_queue(ctx, src_buf)) { /* @@ -315,15 +330,12 @@ void coda_fill_bitstream(struct coda_ctx *ctx, struct list_head *buffer_list) meta->timecode = src_buf->timecode; meta->timestamp = src_buf->vb2_buf.timestamp; meta->start = start; - meta->end = ctx->bitstream_fifo.kfifo.in & - ctx->bitstream_fifo.kfifo.mask; - spin_lock_irqsave(&ctx->buffer_meta_lock, - flags); + meta->end = ctx->bitstream_fifo.kfifo.in; + spin_lock(&ctx->buffer_meta_lock); list_add_tail(&meta->list, &ctx->buffer_meta_list); ctx->num_metas++; - spin_unlock_irqrestore(&ctx->buffer_meta_lock, - flags); + spin_unlock(&ctx->buffer_meta_lock); trace_coda_bit_queue(ctx, src_buf, meta); } @@ -713,8 +725,7 @@ static void coda_setup_iram(struct coda_ctx *ctx) out: if (!(iram_info->axi_sram_use & CODA7_USE_HOST_IP_ENABLE)) - v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, - "IRAM smaller than needed\n"); + coda_dbg(1, ctx, "IRAM smaller than needed\n"); if (dev->devtype->product == CODA_HX4 || dev->devtype->product == CODA_7541) { @@ -991,16 +1002,15 @@ static int coda_start_encoding(struct coda_ctx *ctx) else coda_write(dev, CODA_STD_H264, CODA_CMD_ENC_SEQ_COD_STD); - if (ctx->params.h264_deblk_enabled) { - value = ((ctx->params.h264_deblk_alpha & - CODA_264PARAM_DEBLKFILTEROFFSETALPHA_MASK) << - CODA_264PARAM_DEBLKFILTEROFFSETALPHA_OFFSET) | - ((ctx->params.h264_deblk_beta & - CODA_264PARAM_DEBLKFILTEROFFSETBETA_MASK) << - CODA_264PARAM_DEBLKFILTEROFFSETBETA_OFFSET); - } else { - value = 1 << CODA_264PARAM_DISABLEDEBLK_OFFSET; - } + value = ((ctx->params.h264_disable_deblocking_filter_idc & + CODA_264PARAM_DISABLEDEBLK_MASK) << + CODA_264PARAM_DISABLEDEBLK_OFFSET) | + ((ctx->params.h264_slice_alpha_c0_offset_div2 & + CODA_264PARAM_DEBLKFILTEROFFSETALPHA_MASK) << + CODA_264PARAM_DEBLKFILTEROFFSETALPHA_OFFSET) | + ((ctx->params.h264_slice_beta_offset_div2 & + CODA_264PARAM_DEBLKFILTEROFFSETBETA_MASK) << + CODA_264PARAM_DEBLKFILTEROFFSETBETA_OFFSET); coda_write(dev, value, CODA_CMD_ENC_SEQ_264_PARA); break; case V4L2_PIX_FMT_JPEG: @@ -1201,6 +1211,12 @@ static int coda_start_encoding(struct coda_ctx *ctx) goto out; } + coda_dbg(1, ctx, "start encoding %dx%d %4.4s->%4.4s @ %d/%d Hz\n", + q_data_src->rect.width, q_data_src->rect.height, + (char *)&ctx->codec->src_fourcc, (char *)&dst_fourcc, + ctx->params.framerate & 0xffff, + (ctx->params.framerate >> 16) + 1); + /* Save stream headers */ buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx); switch (dst_fourcc) { @@ -1462,8 +1478,7 @@ static void coda_finish_encode(struct coda_ctx *ctx) vb2_set_plane_payload(&dst_buf->vb2_buf, 0, wr_ptr - start_ptr); } - v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, "frame size = %u\n", - wr_ptr - start_ptr); + coda_dbg(1, ctx, "frame size = %u\n", wr_ptr - start_ptr); coda_read(dev, CODA_RET_ENC_PIC_SLICE_NUM); coda_read(dev, CODA_RET_ENC_PIC_FLAG); @@ -1492,11 +1507,9 @@ static void coda_finish_encode(struct coda_ctx *ctx) if (ctx->gopcounter < 0) ctx->gopcounter = ctx->params.gop_size - 1; - v4l2_dbg(1, coda_debug, &dev->v4l2_dev, - "job finished: encoding frame (%d) (%s)\n", - dst_buf->sequence, - (dst_buf->flags & V4L2_BUF_FLAG_KEYFRAME) ? - "KEYFRAME" : "PFRAME"); + coda_dbg(1, ctx, "job finished: encoded %c frame (%d)\n", + (dst_buf->flags & V4L2_BUF_FLAG_KEYFRAME) ? 'I' : 'P', + dst_buf->sequence); } static void coda_seq_end_work(struct work_struct *work) @@ -1510,9 +1523,7 @@ static void coda_seq_end_work(struct work_struct *work) if (ctx->initialized == 0) goto out; - v4l2_dbg(1, coda_debug, &dev->v4l2_dev, - "%d: %s: sent command 'SEQ_END' to coda\n", ctx->idx, - __func__); + coda_dbg(1, ctx, "%s: sent command 'SEQ_END' to coda\n", __func__); if (coda_command_sync(ctx, CODA_COMMAND_SEQ_END)) { v4l2_err(&dev->v4l2_dev, "CODA_COMMAND_SEQ_END failed\n"); @@ -1655,8 +1666,7 @@ static int __coda_start_decoding(struct coda_ctx *ctx) u32 val; int ret; - v4l2_dbg(1, coda_debug, &dev->v4l2_dev, - "Video Data Order Adapter: %s\n", + coda_dbg(1, ctx, "Video Data Order Adapter: %s\n", ctx->use_vdoa ? "Enabled" : "Disabled"); /* Start decoding */ @@ -1736,7 +1746,7 @@ static int __coda_start_decoding(struct coda_ctx *ctx) if (coda_read(dev, CODA_RET_DEC_SEQ_SUCCESS) == 0) { v4l2_err(&dev->v4l2_dev, - "CODA_COMMAND_SEQ_INIT failed, error code = %d\n", + "CODA_COMMAND_SEQ_INIT failed, error code = 0x%x\n", coda_read(dev, CODA_RET_DEC_SEQ_ERR_REASON)); return -EAGAIN; } @@ -1760,8 +1770,7 @@ static int __coda_start_decoding(struct coda_ctx *ctx) width = round_up(width, 16); height = round_up(height, 16); - v4l2_dbg(1, coda_debug, &dev->v4l2_dev, "%s instance %d now: %dx%d\n", - __func__, ctx->idx, width, height); + coda_dbg(1, ctx, "start decoding: %dx%d\n", width, height); ctx->num_internal_frames = coda_read(dev, CODA_RET_DEC_SEQ_FRAME_NEED); /* @@ -1879,7 +1888,6 @@ static int coda_prepare_decode(struct coda_ctx *ctx) struct coda_dev *dev = ctx->dev; struct coda_q_data *q_data_dst; struct coda_buffer_meta *meta; - unsigned long flags; u32 rot_mode = 0; u32 reg_addr, reg_stride; @@ -1893,8 +1901,7 @@ static int coda_prepare_decode(struct coda_ctx *ctx) if (coda_get_bitstream_payload(ctx) < 512 && (!(ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG))) { - v4l2_dbg(1, coda_debug, &dev->v4l2_dev, - "bitstream payload: %d, skipping\n", + coda_dbg(1, ctx, "bitstream payload: %d, skipping\n", coda_get_bitstream_payload(ctx)); v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx); return -EAGAIN; @@ -1973,15 +1980,14 @@ static int coda_prepare_decode(struct coda_ctx *ctx) coda_write(dev, ctx->iram_info.axi_sram_use, CODA7_REG_BIT_AXI_SRAM_USE); - spin_lock_irqsave(&ctx->buffer_meta_lock, flags); + spin_lock(&ctx->buffer_meta_lock); meta = list_first_entry_or_null(&ctx->buffer_meta_list, struct coda_buffer_meta, list); if (meta && ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG) { /* If this is the last buffer in the bitstream, add padding */ - if (meta->end == (ctx->bitstream_fifo.kfifo.in & - ctx->bitstream_fifo.kfifo.mask)) { + if (meta->end == ctx->bitstream_fifo.kfifo.in) { static unsigned char buf[512]; unsigned int pad; @@ -1993,7 +1999,7 @@ static int coda_prepare_decode(struct coda_ctx *ctx) kfifo_in(&ctx->bitstream_fifo, buf, pad); } } - spin_unlock_irqrestore(&ctx->buffer_meta_lock, flags); + spin_unlock(&ctx->buffer_meta_lock); coda_kfifo_sync_to_device_full(ctx); @@ -2015,7 +2021,6 @@ static void coda_finish_decode(struct coda_ctx *ctx) struct vb2_v4l2_buffer *dst_buf; struct coda_buffer_meta *meta; unsigned long payload; - unsigned long flags; int width, height; int decoded_idx; int display_idx; @@ -2100,8 +2105,7 @@ static void coda_finish_decode(struct coda_ctx *ctx) val = coda_read(dev, CODA_RET_DEC_PIC_OPTION); if (val == 0) { /* not enough bitstream data */ - v4l2_dbg(1, coda_debug, &dev->v4l2_dev, - "prescan failed: %d\n", val); + coda_dbg(1, ctx, "prescan failed: %d\n", val); ctx->hold = true; return; } @@ -2147,13 +2151,13 @@ static void coda_finish_decode(struct coda_ctx *ctx) } else { val = coda_read(dev, CODA_RET_DEC_PIC_FRAME_NUM) - 1; val -= ctx->sequence_offset; - spin_lock_irqsave(&ctx->buffer_meta_lock, flags); + spin_lock(&ctx->buffer_meta_lock); if (!list_empty(&ctx->buffer_meta_list)) { meta = list_first_entry(&ctx->buffer_meta_list, struct coda_buffer_meta, list); list_del(&meta->list); ctx->num_metas--; - spin_unlock_irqrestore(&ctx->buffer_meta_lock, flags); + spin_unlock(&ctx->buffer_meta_lock); /* * Clamp counters to 16 bits for comparison, as the HW * counter rolls over at this point for h.264. This @@ -2170,7 +2174,7 @@ static void coda_finish_decode(struct coda_ctx *ctx) ctx->frame_metas[decoded_idx] = *meta; kfree(meta); } else { - spin_unlock_irqrestore(&ctx->buffer_meta_lock, flags); + spin_unlock(&ctx->buffer_meta_lock); v4l2_err(&dev->v4l2_dev, "empty timestamp list!\n"); memset(&ctx->frame_metas[decoded_idx], 0, sizeof(struct coda_buffer_meta)); @@ -2243,18 +2247,28 @@ static void coda_finish_decode(struct coda_ctx *ctx) else coda_m2m_buf_done(ctx, dst_buf, VB2_BUF_STATE_DONE); - v4l2_dbg(1, coda_debug, &dev->v4l2_dev, - "job finished: decoding frame (%d) (%s)\n", - dst_buf->sequence, - (dst_buf->flags & V4L2_BUF_FLAG_KEYFRAME) ? - "KEYFRAME" : "PFRAME"); + coda_dbg(1, ctx, "job finished: decoded %c frame (%u/%u)\n", + (dst_buf->flags & V4L2_BUF_FLAG_KEYFRAME) ? 'I' : + ((dst_buf->flags & V4L2_BUF_FLAG_PFRAME) ? 'P' : 'B'), + dst_buf->sequence, ctx->qsequence); } else { - v4l2_dbg(1, coda_debug, &dev->v4l2_dev, - "job finished: no frame decoded\n"); + coda_dbg(1, ctx, "job finished: no frame decoded (%u/%u)\n", + ctx->osequence, ctx->qsequence); } /* The rotator will copy the current display frame next time */ ctx->display_idx = display_idx; + + /* + * The current decode run might have brought the bitstream fill level + * below the size where we can start the next decode run. As userspace + * might have filled the output queue completely and might thus be + * blocked, we can't rely on the next qbuf to trigger the bitstream + * refill. Check if we have data to refill the bitstream now. + */ + mutex_lock(&ctx->bitstream_mutex); + coda_fill_bitstream(ctx, NULL); + mutex_unlock(&ctx->bitstream_mutex); } static void coda_decode_timeout(struct coda_ctx *ctx) @@ -2308,13 +2322,11 @@ irqreturn_t coda_irq_handler(int irq, void *data) trace_coda_bit_done(ctx); if (ctx->aborting) { - v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, - "task has been aborted\n"); + coda_dbg(1, ctx, "task has been aborted\n"); } if (coda_isbusy(ctx->dev)) { - v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, - "coda is still busy!!!!\n"); + coda_dbg(1, ctx, "coda is still busy!!!!\n"); return IRQ_NONE; } diff --git a/drivers/media/platform/coda/coda-common.c b/drivers/media/platform/coda/coda-common.c index 2848ea5f464d..7518f01c48f7 100644 --- a/drivers/media/platform/coda/coda-common.c +++ b/drivers/media/platform/coda/coda-common.c @@ -17,6 +17,7 @@ #include <linux/firmware.h> #include <linux/gcd.h> #include <linux/genalloc.h> +#include <linux/idr.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/irq.h> @@ -50,8 +51,8 @@ #define CODA_ISRAM_SIZE (2048 * 2) -#define MIN_W 176 -#define MIN_H 144 +#define MIN_W 48 +#define MIN_H 16 #define S_ALIGN 1 /* multiple of 2 */ #define W_ALIGN 1 /* multiple of 2 */ @@ -703,7 +704,8 @@ static int coda_s_fmt(struct coda_ctx *ctx, struct v4l2_format *f, return -EINVAL; if (vb2_is_busy(vq)) { - v4l2_err(&ctx->dev->v4l2_dev, "%s queue busy\n", __func__); + v4l2_err(&ctx->dev->v4l2_dev, "%s: %s queue busy: %d\n", + __func__, v4l2_type_names[f->type], vq->num_buffers); return -EBUSY; } @@ -749,11 +751,10 @@ static int coda_s_fmt(struct coda_ctx *ctx, struct v4l2_format *f, else ctx->use_vdoa = false; - v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, - "Setting format for type %d, wxh: %dx%d, fmt: %4.4s %c\n", - f->type, q_data->width, q_data->height, - (char *)&q_data->fourcc, - (ctx->tiled_map_type == GDI_LINEAR_FRAME_MAP) ? 'L' : 'T'); + coda_dbg(1, ctx, "Setting %s format, wxh: %dx%d, fmt: %4.4s %c\n", + v4l2_type_names[f->type], q_data->width, q_data->height, + (char *)&q_data->fourcc, + (ctx->tiled_map_type == GDI_LINEAR_FRAME_MAP) ? 'L' : 'T'); return 0; } @@ -938,32 +939,42 @@ static int coda_s_selection(struct file *file, void *fh, struct coda_ctx *ctx = fh_to_ctx(fh); struct coda_q_data *q_data; - if (ctx->inst_type == CODA_INST_ENCODER && - s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT && - s->target == V4L2_SEL_TGT_CROP) { - q_data = get_q_data(ctx, s->type); - if (!q_data) - return -EINVAL; + switch (s->target) { + case V4L2_SEL_TGT_CROP: + if (ctx->inst_type == CODA_INST_ENCODER && + s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) { + q_data = get_q_data(ctx, s->type); + if (!q_data) + return -EINVAL; - s->r.left = 0; - s->r.top = 0; - s->r.width = clamp(s->r.width, 2U, q_data->width); - s->r.height = clamp(s->r.height, 2U, q_data->height); + s->r.left = 0; + s->r.top = 0; + s->r.width = clamp(s->r.width, 2U, q_data->width); + s->r.height = clamp(s->r.height, 2U, q_data->height); + + if (s->flags & V4L2_SEL_FLAG_LE) { + s->r.width = round_up(s->r.width, 2); + s->r.height = round_up(s->r.height, 2); + } else { + s->r.width = round_down(s->r.width, 2); + s->r.height = round_down(s->r.height, 2); + } - if (s->flags & V4L2_SEL_FLAG_LE) { - s->r.width = round_up(s->r.width, 2); - s->r.height = round_up(s->r.height, 2); - } else { - s->r.width = round_down(s->r.width, 2); - s->r.height = round_down(s->r.height, 2); - } + q_data->rect = s->r; - q_data->rect = s->r; + coda_dbg(1, ctx, "Setting crop rectangle: %dx%d\n", + s->r.width, s->r.height); - return 0; + return 0; + } + /* else fall through */ + case V4L2_SEL_TGT_NATIVE_SIZE: + case V4L2_SEL_TGT_COMPOSE: + return coda_g_selection(file, fh, s); + default: + /* v4l2-compliance expects this to fail for read-only targets */ + return -EINVAL; } - - return coda_g_selection(file, fh, s); } static int coda_try_encoder_cmd(struct file *file, void *fh, @@ -1044,6 +1055,38 @@ static int coda_decoder_cmd(struct file *file, void *fh, return 0; } +static int coda_enum_frameintervals(struct file *file, void *fh, + struct v4l2_frmivalenum *f) +{ + struct coda_ctx *ctx = fh_to_ctx(fh); + int i; + + if (f->index) + return -EINVAL; + + /* Disallow YUYV if the vdoa is not available */ + if (!ctx->vdoa && f->pixel_format == V4L2_PIX_FMT_YUYV) + return -EINVAL; + + for (i = 0; i < CODA_MAX_FORMATS; i++) { + if (f->pixel_format == ctx->cvd->src_formats[i] || + f->pixel_format == ctx->cvd->dst_formats[i]) + break; + } + if (i == CODA_MAX_FORMATS) + return -EINVAL; + + f->type = V4L2_FRMIVAL_TYPE_CONTINUOUS; + f->stepwise.min.numerator = 1; + f->stepwise.min.denominator = 65535; + f->stepwise.max.numerator = 65536; + f->stepwise.max.denominator = 1; + f->stepwise.step.numerator = 1; + f->stepwise.step.denominator = 1; + + return 0; +} + static int coda_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a) { struct coda_ctx *ctx = fh_to_ctx(fh); @@ -1080,10 +1123,10 @@ static void coda_approximate_timeperframe(struct v4l2_fract *timeperframe) return; } - /* Upper bound is 65536/1, map everything above to infinity */ + /* Upper bound is 65536/1 */ if (s.denominator == 0 || s.numerator / s.denominator > 65536) { - timeperframe->numerator = 1; - timeperframe->denominator = 0; + timeperframe->numerator = 65536; + timeperframe->denominator = 1; return; } @@ -1135,6 +1178,7 @@ static int coda_s_parm(struct file *file, void *fh, struct v4l2_streamparm *a) if (a->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) return -EINVAL; + a->parm.output.capability = V4L2_CAP_TIMEPERFRAME; tpf = &a->parm.output.timeperframe; coda_approximate_timeperframe(tpf); ctx->params.framerate = coda_timeperframe_to_frate(tpf); @@ -1189,6 +1233,8 @@ static const struct v4l2_ioctl_ops coda_ioctl_ops = { .vidioc_g_parm = coda_g_parm, .vidioc_s_parm = coda_s_parm, + .vidioc_enum_frameintervals = coda_enum_frameintervals, + .vidioc_subscribe_event = coda_subscribe_event, .vidioc_unsubscribe_event = v4l2_event_unsubscribe, }; @@ -1257,14 +1303,12 @@ static int coda_job_ready(void *m2m_priv) * the compressed frame can be in the bitstream. */ if (!src_bufs && ctx->inst_type != CODA_INST_DECODER) { - v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, - "not ready: not enough video buffers.\n"); + coda_dbg(1, ctx, "not ready: not enough vid-out buffers.\n"); return 0; } if (!v4l2_m2m_num_dst_bufs_ready(ctx->fh.m2m_ctx)) { - v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, - "not ready: not enough video capture buffers.\n"); + coda_dbg(1, ctx, "not ready: not enough vid-cap buffers.\n"); return 0; } @@ -1272,49 +1316,48 @@ static int coda_job_ready(void *m2m_priv) bool stream_end = ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG; int num_metas = ctx->num_metas; + struct coda_buffer_meta *meta; unsigned int count; count = hweight32(ctx->frm_dis_flg); if (ctx->use_vdoa && count >= (ctx->num_internal_frames - 1)) { - v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, - "%d: not ready: all internal buffers in use: %d/%d (0x%x)", - ctx->idx, count, ctx->num_internal_frames, + coda_dbg(1, ctx, + "not ready: all internal buffers in use: %d/%d (0x%x)", + count, ctx->num_internal_frames, ctx->frm_dis_flg); return 0; } if (ctx->hold && !src_bufs) { - v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, - "%d: not ready: on hold for more buffers.\n", - ctx->idx); + coda_dbg(1, ctx, + "not ready: on hold for more buffers.\n"); return 0; } if (!stream_end && (num_metas + src_bufs) < 2) { - v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, - "%d: not ready: need 2 buffers available (%d, %d)\n", - ctx->idx, num_metas, src_bufs); + coda_dbg(1, ctx, + "not ready: need 2 buffers available (queue:%d + bitstream:%d)\n", + num_metas, src_bufs); return 0; } - - if (!src_bufs && !stream_end && - (coda_get_bitstream_payload(ctx) < 512)) { - v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, - "%d: not ready: not enough bitstream data (%d).\n", - ctx->idx, coda_get_bitstream_payload(ctx)); + meta = list_first_entry(&ctx->buffer_meta_list, + struct coda_buffer_meta, list); + if (!coda_bitstream_can_fetch_past(ctx, meta->end) && + !stream_end) { + coda_dbg(1, ctx, + "not ready: not enough bitstream data to read past %u (%u)\n", + meta->end, ctx->bitstream_fifo.kfifo.in); return 0; } } if (ctx->aborting) { - v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, - "not ready: aborting\n"); + coda_dbg(1, ctx, "not ready: aborting\n"); return 0; } - v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, - "job ready\n"); + coda_dbg(1, ctx, "job ready\n"); return 1; } @@ -1325,8 +1368,7 @@ static void coda_job_abort(void *priv) ctx->aborting = 1; - v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, - "Aborting task\n"); + coda_dbg(1, ctx, "job abort\n"); } static const struct v4l2_m2m_ops coda_m2m_ops = { @@ -1403,8 +1445,8 @@ static int coda_queue_setup(struct vb2_queue *vq, *nplanes = 1; sizes[0] = size; - v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, - "get %d buffer(s) of size %d each.\n", *nbuffers, size); + coda_dbg(1, ctx, "get %d buffer(s) of size %d each.\n", *nbuffers, + size); return 0; } @@ -1469,8 +1511,7 @@ static void coda_update_h264_profile_ctrl(struct coda_ctx *ctx) profile_names = v4l2_ctrl_get_menu(V4L2_CID_MPEG_VIDEO_H264_PROFILE); - v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, "Parsed H264 Profile: %s\n", - profile_names[profile]); + coda_dbg(1, ctx, "Parsed H264 Profile: %s\n", profile_names[profile]); } static void coda_update_h264_level_ctrl(struct coda_ctx *ctx) @@ -1489,8 +1530,7 @@ static void coda_update_h264_level_ctrl(struct coda_ctx *ctx) level_names = v4l2_ctrl_get_menu(V4L2_CID_MPEG_VIDEO_H264_LEVEL); - v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, "Parsed H264 Level: %s\n", - level_names[level]); + coda_dbg(1, ctx, "Parsed H264 Level: %s\n", level_names[level]); } static void coda_buf_queue(struct vb2_buffer *vb) @@ -1595,6 +1635,8 @@ static int coda_start_streaming(struct vb2_queue *q, unsigned int count) if (count < 1) return -EINVAL; + coda_dbg(1, ctx, "start streaming %s\n", v4l2_type_names[q->type]); + INIT_LIST_HEAD(&list); q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT); @@ -1687,14 +1729,13 @@ static void coda_stop_streaming(struct vb2_queue *q) struct coda_ctx *ctx = vb2_get_drv_priv(q); struct coda_dev *dev = ctx->dev; struct vb2_v4l2_buffer *buf; - unsigned long flags; bool stop; stop = ctx->streamon_out && ctx->streamon_cap; + coda_dbg(1, ctx, "stop streaming %s\n", v4l2_type_names[q->type]); + if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) { - v4l2_dbg(1, coda_debug, &dev->v4l2_dev, - "%s: output\n", __func__); ctx->streamon_out = 0; coda_bit_stream_end_flag(ctx); @@ -1704,8 +1745,6 @@ static void coda_stop_streaming(struct vb2_queue *q) while ((buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx))) v4l2_m2m_buf_done(buf, VB2_BUF_STATE_ERROR); } else { - v4l2_dbg(1, coda_debug, &dev->v4l2_dev, - "%s: capture\n", __func__); ctx->streamon_cap = 0; ctx->osequence = 0; @@ -1722,7 +1761,7 @@ static void coda_stop_streaming(struct vb2_queue *q) queue_work(dev->workqueue, &ctx->seq_end_work); flush_work(&ctx->seq_end_work); } - spin_lock_irqsave(&ctx->buffer_meta_lock, flags); + spin_lock(&ctx->buffer_meta_lock); while (!list_empty(&ctx->buffer_meta_list)) { meta = list_first_entry(&ctx->buffer_meta_list, struct coda_buffer_meta, list); @@ -1730,7 +1769,7 @@ static void coda_stop_streaming(struct vb2_queue *q) kfree(meta); } ctx->num_metas = 0; - spin_unlock_irqrestore(&ctx->buffer_meta_lock, flags); + spin_unlock(&ctx->buffer_meta_lock); kfifo_init(&ctx->bitstream_fifo, ctx->bitstream.vaddr, ctx->bitstream.size); ctx->runcounter = 0; @@ -1757,8 +1796,8 @@ static int coda_s_ctrl(struct v4l2_ctrl *ctrl) struct coda_ctx *ctx = container_of(ctrl->handler, struct coda_ctx, ctrls); - v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, - "s_ctrl: id = %d, val = %d\n", ctrl->id, ctrl->val); + coda_dbg(1, ctx, "s_ctrl: id = 0x%x, name = \"%s\", val = %d\n", + ctrl->id, ctrl->name, ctrl->val); switch (ctrl->id) { case V4L2_CID_HFLIP: @@ -1792,14 +1831,13 @@ static int coda_s_ctrl(struct v4l2_ctrl *ctrl) ctx->params.h264_max_qp = ctrl->val; break; case V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA: - ctx->params.h264_deblk_alpha = ctrl->val; + ctx->params.h264_slice_alpha_c0_offset_div2 = ctrl->val; break; case V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA: - ctx->params.h264_deblk_beta = ctrl->val; + ctx->params.h264_slice_beta_offset_div2 = ctrl->val; break; case V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE: - ctx->params.h264_deblk_enabled = (ctrl->val == - V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED); + ctx->params.h264_disable_deblocking_filter_idc = ctrl->val; break; case V4L2_CID_MPEG_VIDEO_H264_PROFILE: /* TODO: switch between baseline and constrained baseline */ @@ -1849,9 +1887,8 @@ static int coda_s_ctrl(struct v4l2_ctrl *ctrl) ctx->params.vbv_size = min(ctrl->val * 8192, 0x7fffffff); break; default: - v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, - "Invalid control, id=%d, val=%d\n", - ctrl->id, ctrl->val); + coda_dbg(1, ctx, "Invalid control, id=%d, val=%d\n", + ctrl->id, ctrl->val); return -EINVAL; } @@ -1881,13 +1918,13 @@ static void coda_encode_ctrls(struct coda_ctx *ctx) v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops, V4L2_CID_MPEG_VIDEO_H264_MAX_QP, 0, 51, 1, 51); v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops, - V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA, 0, 15, 1, 0); + V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA, -6, 6, 1, 0); v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops, - V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA, 0, 15, 1, 0); + V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA, -6, 6, 1, 0); v4l2_ctrl_new_std_menu(&ctx->ctrls, &coda_ctrl_ops, V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE, - V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED, 0x0, - V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED); + V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY, + 0x0, V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED); v4l2_ctrl_new_std_menu(&ctx->ctrls, &coda_ctrl_ops, V4L2_CID_MPEG_VIDEO_H264_PROFILE, V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, 0x0, @@ -2099,17 +2136,6 @@ int coda_decoder_queue_init(void *priv, struct vb2_queue *src_vq, return coda_queue_init(priv, dst_vq); } -static int coda_next_free_instance(struct coda_dev *dev) -{ - int idx = ffz(dev->instance_mask); - - if ((idx < 0) || - (dev->devtype->product == CODA_DX6 && idx > CODADX6_MAX_INSTANCES)) - return -EBUSY; - - return idx; -} - /* * File operations */ @@ -2118,7 +2144,8 @@ static int coda_open(struct file *file) { struct video_device *vdev = video_devdata(file); struct coda_dev *dev = video_get_drvdata(vdev); - struct coda_ctx *ctx = NULL; + struct coda_ctx *ctx; + unsigned int max = ~0; char *name; int ret; int idx; @@ -2127,12 +2154,13 @@ static int coda_open(struct file *file) if (!ctx) return -ENOMEM; - idx = coda_next_free_instance(dev); + if (dev->devtype->product == CODA_DX6) + max = CODADX6_MAX_INSTANCES - 1; + idx = ida_alloc_max(&dev->ida, max, GFP_KERNEL); if (idx < 0) { ret = idx; goto err_coda_max; } - set_bit(idx, &dev->instance_mask); name = kasprintf(GFP_KERNEL, "context%d", idx); if (!name) { @@ -2156,6 +2184,9 @@ static int coda_open(struct file *file) v4l2_fh_add(&ctx->fh); ctx->dev = dev; ctx->idx = idx; + + coda_dbg(1, ctx, "open instance (%p)\n", ctx); + switch (dev->devtype->product) { case CODA_960: /* @@ -2221,13 +2252,6 @@ static int coda_open(struct file *file) INIT_LIST_HEAD(&ctx->buffer_meta_list); spin_lock_init(&ctx->buffer_meta_lock); - mutex_lock(&dev->dev_mutex); - list_add(&ctx->list, &dev->instances); - mutex_unlock(&dev->dev_mutex); - - v4l2_dbg(1, coda_debug, &dev->v4l2_dev, "Created instance %d (%p)\n", - ctx->idx, ctx); - return 0; err_ctrls_setup: @@ -2241,8 +2265,8 @@ err_clk_per: err_pm_get: v4l2_fh_del(&ctx->fh); v4l2_fh_exit(&ctx->fh); - clear_bit(ctx->idx, &dev->instance_mask); err_coda_name_init: + ida_free(&dev->ida, ctx->idx); err_coda_max: kfree(ctx); return ret; @@ -2253,8 +2277,7 @@ static int coda_release(struct file *file) struct coda_dev *dev = video_drvdata(file); struct coda_ctx *ctx = fh_to_ctx(file->private_data); - v4l2_dbg(1, coda_debug, &dev->v4l2_dev, "Releasing instance %p\n", - ctx); + coda_dbg(1, ctx, "release instance (%p)\n", ctx); if (ctx->inst_type == CODA_INST_DECODER && ctx->use_bit) coda_bit_stream_end_flag(ctx); @@ -2271,10 +2294,6 @@ static int coda_release(struct file *file) flush_work(&ctx->seq_end_work); } - mutex_lock(&dev->dev_mutex); - list_del(&ctx->list); - mutex_unlock(&dev->dev_mutex); - if (ctx->dev->devtype->product == CODA_DX6) coda_free_aux_buf(dev, &ctx->workbuf); @@ -2284,7 +2303,7 @@ static int coda_release(struct file *file) pm_runtime_put_sync(&dev->plat_dev->dev); v4l2_fh_del(&ctx->fh); v4l2_fh_exit(&ctx->fh); - clear_bit(ctx->idx, &dev->instance_mask); + ida_free(&dev->ida, ctx->idx); if (ctx->ops->release) ctx->ops->release(ctx); debugfs_remove_recursive(ctx->debugfs_entry); @@ -2679,7 +2698,6 @@ static int coda_probe(struct platform_device *pdev) return -EINVAL; spin_lock_init(&dev->irqlock); - INIT_LIST_HEAD(&dev->instances); dev->plat_dev = pdev; dev->clk_per = devm_clk_get(&pdev->dev, "per"); @@ -2745,6 +2763,7 @@ static int coda_probe(struct platform_device *pdev) mutex_init(&dev->dev_mutex); mutex_init(&dev->coda_mutex); + ida_init(&dev->ida); dev->debugfs_root = debugfs_create_dir("coda", NULL); if (!dev->debugfs_root) @@ -2832,6 +2851,7 @@ static int coda_remove(struct platform_device *pdev) coda_free_aux_buf(dev, &dev->tempbuf); coda_free_aux_buf(dev, &dev->workbuf); debugfs_remove_recursive(dev->debugfs_root); + ida_destroy(&dev->ida); return 0; } diff --git a/drivers/media/platform/coda/coda.h b/drivers/media/platform/coda/coda.h index 19ac0b9dc6eb..31cea72f5b2a 100644 --- a/drivers/media/platform/coda/coda.h +++ b/drivers/media/platform/coda/coda.h @@ -16,6 +16,7 @@ #define __CODA_H__ #include <linux/debugfs.h> +#include <linux/idr.h> #include <linux/irqreturn.h> #include <linux/mutex.h> #include <linux/kfifo.h> @@ -94,8 +95,7 @@ struct coda_dev { struct mutex coda_mutex; struct workqueue_struct *workqueue; struct v4l2_m2m_dev *m2m_dev; - struct list_head instances; - unsigned long instance_mask; + struct ida ida; struct dentry *debugfs_root; }; @@ -115,9 +115,9 @@ struct coda_params { u8 h264_inter_qp; u8 h264_min_qp; u8 h264_max_qp; - u8 h264_deblk_enabled; - u8 h264_deblk_alpha; - u8 h264_deblk_beta; + u8 h264_disable_deblocking_filter_idc; + s8 h264_slice_alpha_c0_offset_div2; + s8 h264_slice_beta_offset_div2; u8 h264_profile_idc; u8 h264_level_idc; u8 mpeg4_intra_qp; @@ -144,8 +144,8 @@ struct coda_buffer_meta { u32 sequence; struct v4l2_timecode timecode; u64 timestamp; - u32 start; - u32 end; + unsigned int start; + unsigned int end; }; /* Per-queue, driver-specific private data */ @@ -192,7 +192,6 @@ struct coda_context_ops { struct coda_ctx { struct coda_dev *dev; struct mutex buffer_mutex; - struct list_head list; struct work_struct pic_run_work; struct work_struct seq_end_work; struct completion completion; @@ -253,6 +252,13 @@ struct coda_ctx { extern int coda_debug; +#define coda_dbg(level, ctx, fmt, arg...) \ + do { \ + if (coda_debug >= (level)) \ + v4l2_dbg((level), coda_debug, &(ctx)->dev->v4l2_dev, \ + "%u: " fmt, (ctx)->idx, ##arg); \ + } while (0) + void coda_write(struct coda_dev *dev, u32 data, u32 reg); unsigned int coda_read(struct coda_dev *dev, u32 reg); void coda_write_base(struct coda_ctx *ctx, struct coda_q_data *q_data, @@ -295,6 +301,18 @@ static inline unsigned int coda_get_bitstream_payload(struct coda_ctx *ctx) return kfifo_len(&ctx->bitstream_fifo); } +/* + * The bitstream prefetcher needs to read at least 2 256 byte periods past + * the desired bitstream position for all data to reach the decoder. + */ +static inline bool coda_bitstream_can_fetch_past(struct coda_ctx *ctx, + unsigned int pos) +{ + return (int)(ctx->bitstream_fifo.kfifo.in - ALIGN(pos, 256)) > 512; +} + +bool coda_bitstream_can_fetch_past(struct coda_ctx *ctx, unsigned int pos); + void coda_bit_stream_end_flag(struct coda_ctx *ctx); void coda_m2m_buf_done(struct coda_ctx *ctx, struct vb2_v4l2_buffer *buf, diff --git a/drivers/media/platform/coda/coda_regs.h b/drivers/media/platform/coda/coda_regs.h index 5e7b00a97671..e675e38f3475 100644 --- a/drivers/media/platform/coda/coda_regs.h +++ b/drivers/media/platform/coda/coda_regs.h @@ -292,7 +292,7 @@ #define CODA_264PARAM_DEBLKFILTEROFFSETALPHA_OFFSET 8 #define CODA_264PARAM_DEBLKFILTEROFFSETALPHA_MASK 0x0f #define CODA_264PARAM_DISABLEDEBLK_OFFSET 6 -#define CODA_264PARAM_DISABLEDEBLK_MASK 0x01 +#define CODA_264PARAM_DISABLEDEBLK_MASK 0x03 #define CODA_264PARAM_CONSTRAINEDINTRAPREDFLAG_OFFSET 5 #define CODA_264PARAM_CONSTRAINEDINTRAPREDFLAG_MASK 0x01 #define CODA_264PARAM_CHROMAQPOFFSET_OFFSET 0 diff --git a/drivers/media/platform/coda/trace.h b/drivers/media/platform/coda/trace.h index ca671e315ad0..a672bfc4c6ba 100644 --- a/drivers/media/platform/coda/trace.h +++ b/drivers/media/platform/coda/trace.h @@ -97,8 +97,8 @@ DECLARE_EVENT_CLASS(coda_buf_meta_class, TP_fast_assign( __entry->minor = ctx->fh.vdev->minor; __entry->index = buf->vb2_buf.index; - __entry->start = meta->start; - __entry->end = meta->end; + __entry->start = meta->start & ctx->bitstream_fifo.kfifo.mask; + __entry->end = meta->end & ctx->bitstream_fifo.kfifo.mask; __entry->ctx = ctx->idx; ), @@ -127,8 +127,10 @@ DECLARE_EVENT_CLASS(coda_meta_class, TP_fast_assign( __entry->minor = ctx->fh.vdev->minor; - __entry->start = meta ? meta->start : 0; - __entry->end = meta ? meta->end : 0; + __entry->start = meta ? (meta->start & + ctx->bitstream_fifo.kfifo.mask) : 0; + __entry->end = meta ? (meta->end & + ctx->bitstream_fifo.kfifo.mask) : 0; __entry->ctx = ctx->idx; ), diff --git a/drivers/media/platform/davinci/vpbe.c b/drivers/media/platform/davinci/vpbe.c index 18c035ef84cf..4766a7a23d16 100644 --- a/drivers/media/platform/davinci/vpbe.c +++ b/drivers/media/platform/davinci/vpbe.c @@ -93,28 +93,6 @@ static int vpbe_find_encoder_sd_index(struct vpbe_config *cfg, } /** - * vpbe_g_cropcap - Get crop capabilities of the display - * @vpbe_dev: vpbe device ptr - * @cropcap: cropcap is a ptr to struct v4l2_cropcap - * - * Update the crop capabilities in crop cap for current - * mode - */ -static int vpbe_g_cropcap(struct vpbe_device *vpbe_dev, - struct v4l2_cropcap *cropcap) -{ - if (!cropcap) - return -EINVAL; - cropcap->bounds.left = 0; - cropcap->bounds.top = 0; - cropcap->bounds.width = vpbe_dev->current_timings.xres; - cropcap->bounds.height = vpbe_dev->current_timings.yres; - cropcap->defrect = cropcap->bounds; - - return 0; -} - -/** * vpbe_enum_outputs - enumerate outputs * @vpbe_dev: vpbe device ptr * @output: ptr to v4l2_output structure @@ -740,7 +718,7 @@ static int vpbe_initialize(struct device *dev, struct vpbe_device *vpbe_dev) if (ret) { v4l2_err(&vpbe_dev->v4l2_dev, "Failed to set default output %s", def_output); - return ret; + goto fail_kfree_amp; } printk(KERN_NOTICE "Setting default mode to %s\n", def_mode); @@ -748,12 +726,15 @@ static int vpbe_initialize(struct device *dev, struct vpbe_device *vpbe_dev) if (ret) { v4l2_err(&vpbe_dev->v4l2_dev, "Failed to set default mode %s", def_mode); - return ret; + goto fail_kfree_amp; } vpbe_dev->initialized = 1; /* TBD handling of bootargs for default output and mode */ return 0; +fail_kfree_amp: + mutex_lock(&vpbe_dev->lock); + kfree(vpbe_dev->amp); fail_kfree_encoders: kfree(vpbe_dev->encoders); fail_dev_unregister: @@ -793,7 +774,6 @@ static void vpbe_deinitialize(struct device *dev, struct vpbe_device *vpbe_dev) } static const struct vpbe_device_ops vpbe_dev_ops = { - .g_cropcap = vpbe_g_cropcap, .enum_outputs = vpbe_enum_outputs, .set_output = vpbe_set_output, .get_output = vpbe_get_output, diff --git a/drivers/media/platform/davinci/vpbe_display.c b/drivers/media/platform/davinci/vpbe_display.c index 5c235898af7b..9e86b0d36640 100644 --- a/drivers/media/platform/davinci/vpbe_display.c +++ b/drivers/media/platform/davinci/vpbe_display.c @@ -759,18 +759,18 @@ static int vpbe_display_g_selection(struct file *file, void *priv, return 0; } -static int vpbe_display_cropcap(struct file *file, void *priv, - struct v4l2_cropcap *cropcap) +static int vpbe_display_g_pixelaspect(struct file *file, void *priv, + int type, struct v4l2_fract *f) { struct vpbe_layer *layer = video_drvdata(file); struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev; v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev, "VIDIOC_CROPCAP ioctl\n"); - if (cropcap->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) + if (type != V4L2_BUF_TYPE_VIDEO_OUTPUT) return -EINVAL; - cropcap->pixelaspect = vpbe_dev->current_timings.aspect; + *f = vpbe_dev->current_timings.aspect; return 0; } @@ -1263,7 +1263,7 @@ static const struct v4l2_ioctl_ops vpbe_ioctl_ops = { .vidioc_streamoff = vb2_ioctl_streamoff, .vidioc_expbuf = vb2_ioctl_expbuf, - .vidioc_cropcap = vpbe_display_cropcap, + .vidioc_g_pixelaspect = vpbe_display_g_pixelaspect, .vidioc_g_selection = vpbe_display_g_selection, .vidioc_s_selection = vpbe_display_s_selection, diff --git a/drivers/media/platform/davinci/vpfe_capture.c b/drivers/media/platform/davinci/vpfe_capture.c index ea3ddd5a42bd..9996bab98fe3 100644 --- a/drivers/media/platform/davinci/vpfe_capture.c +++ b/drivers/media/platform/davinci/vpfe_capture.c @@ -1558,20 +1558,20 @@ static int vpfe_streamoff(struct file *file, void *priv, return ret; } -static int vpfe_cropcap(struct file *file, void *priv, - struct v4l2_cropcap *crop) +static int vpfe_g_pixelaspect(struct file *file, void *priv, + int type, struct v4l2_fract *f) { struct vpfe_device *vpfe_dev = video_drvdata(file); - v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_cropcap\n"); + v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_g_pixelaspect\n"); - if (crop->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + if (type != V4L2_BUF_TYPE_VIDEO_CAPTURE) return -EINVAL; /* If std_index is invalid, then just return (== 1:1 aspect) */ if (vpfe_dev->std_index >= ARRAY_SIZE(vpfe_standards)) return 0; - crop->pixelaspect = vpfe_standards[vpfe_dev->std_index].pixelaspect; + *f = vpfe_standards[vpfe_dev->std_index].pixelaspect; return 0; } @@ -1677,7 +1677,7 @@ static const struct v4l2_ioctl_ops vpfe_ioctl_ops = { .vidioc_dqbuf = vpfe_dqbuf, .vidioc_streamon = vpfe_streamon, .vidioc_streamoff = vpfe_streamoff, - .vidioc_cropcap = vpfe_cropcap, + .vidioc_g_pixelaspect = vpfe_g_pixelaspect, .vidioc_g_selection = vpfe_g_selection, .vidioc_s_selection = vpfe_s_selection, }; diff --git a/drivers/media/platform/exynos-gsc/gsc-core.c b/drivers/media/platform/exynos-gsc/gsc-core.c index 838c5c53de37..0fa3ec04ab7b 100644 --- a/drivers/media/platform/exynos-gsc/gsc-core.c +++ b/drivers/media/platform/exynos-gsc/gsc-core.c @@ -541,20 +541,7 @@ void gsc_check_crop_change(u32 tmp_w, u32 tmp_h, u32 *w, u32 *h) } } -int gsc_g_crop(struct gsc_ctx *ctx, struct v4l2_crop *cr) -{ - struct gsc_frame *frame; - - frame = ctx_get_frame(ctx, cr->type); - if (IS_ERR(frame)) - return PTR_ERR(frame); - - cr->c = frame->crop; - - return 0; -} - -int gsc_try_crop(struct gsc_ctx *ctx, struct v4l2_crop *cr) +int gsc_try_selection(struct gsc_ctx *ctx, struct v4l2_selection *s) { struct gsc_frame *f; struct gsc_dev *gsc = ctx->gsc_dev; @@ -562,25 +549,25 @@ int gsc_try_crop(struct gsc_ctx *ctx, struct v4l2_crop *cr) u32 mod_x = 0, mod_y = 0, tmp_w, tmp_h; u32 min_w, min_h, max_w, max_h; - if (cr->c.top < 0 || cr->c.left < 0) { + if (s->r.top < 0 || s->r.left < 0) { pr_err("doesn't support negative values for top & left\n"); return -EINVAL; } - pr_debug("user put w: %d, h: %d", cr->c.width, cr->c.height); + pr_debug("user put w: %d, h: %d", s->r.width, s->r.height); - if (cr->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) + if (s->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) f = &ctx->d_frame; - else if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) + else if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) f = &ctx->s_frame; else return -EINVAL; max_w = f->f_width; max_h = f->f_height; - tmp_w = cr->c.width; - tmp_h = cr->c.height; + tmp_w = s->r.width; + tmp_h = s->r.height; - if (V4L2_TYPE_IS_OUTPUT(cr->type)) { + if (V4L2_TYPE_IS_OUTPUT(s->type)) { if ((is_yuv422(f->fmt->color) && f->fmt->num_comp == 1) || is_rgb(f->fmt->color)) min_w = 32; @@ -602,8 +589,8 @@ int gsc_try_crop(struct gsc_ctx *ctx, struct v4l2_crop *cr) max_h = f->f_width; min_w = variant->pix_min->target_rot_en_w; min_h = variant->pix_min->target_rot_en_h; - tmp_w = cr->c.height; - tmp_h = cr->c.width; + tmp_w = s->r.height; + tmp_h = s->r.width; } else { min_w = variant->pix_min->target_rot_dis_w; min_h = variant->pix_min->target_rot_dis_h; @@ -616,29 +603,29 @@ int gsc_try_crop(struct gsc_ctx *ctx, struct v4l2_crop *cr) v4l_bound_align_image(&tmp_w, min_w, max_w, mod_x, &tmp_h, min_h, max_h, mod_y, 0); - if (!V4L2_TYPE_IS_OUTPUT(cr->type) && - (ctx->gsc_ctrls.rotate->val == 90 || - ctx->gsc_ctrls.rotate->val == 270)) + if (!V4L2_TYPE_IS_OUTPUT(s->type) && + (ctx->gsc_ctrls.rotate->val == 90 || + ctx->gsc_ctrls.rotate->val == 270)) gsc_check_crop_change(tmp_h, tmp_w, - &cr->c.width, &cr->c.height); + &s->r.width, &s->r.height); else gsc_check_crop_change(tmp_w, tmp_h, - &cr->c.width, &cr->c.height); + &s->r.width, &s->r.height); /* adjust left/top if cropping rectangle is out of bounds */ /* Need to add code to algin left value with 2's multiple */ - if (cr->c.left + tmp_w > max_w) - cr->c.left = max_w - tmp_w; - if (cr->c.top + tmp_h > max_h) - cr->c.top = max_h - tmp_h; + if (s->r.left + tmp_w > max_w) + s->r.left = max_w - tmp_w; + if (s->r.top + tmp_h > max_h) + s->r.top = max_h - tmp_h; if ((is_yuv420(f->fmt->color) || is_yuv422(f->fmt->color)) && - cr->c.left & 1) - cr->c.left -= 1; + s->r.left & 1) + s->r.left -= 1; pr_debug("Aligned l:%d, t:%d, w:%d, h:%d, f_w: %d, f_h: %d", - cr->c.left, cr->c.top, cr->c.width, cr->c.height, max_w, max_h); + s->r.left, s->r.top, s->r.width, s->r.height, max_w, max_h); return 0; } diff --git a/drivers/media/platform/exynos-gsc/gsc-core.h b/drivers/media/platform/exynos-gsc/gsc-core.h index 715d9c9d8d30..c81f0a17d286 100644 --- a/drivers/media/platform/exynos-gsc/gsc-core.h +++ b/drivers/media/platform/exynos-gsc/gsc-core.h @@ -392,8 +392,7 @@ int gsc_try_fmt_mplane(struct gsc_ctx *ctx, struct v4l2_format *f); void gsc_set_frame_size(struct gsc_frame *frame, int width, int height); int gsc_g_fmt_mplane(struct gsc_ctx *ctx, struct v4l2_format *f); void gsc_check_crop_change(u32 tmp_w, u32 tmp_h, u32 *w, u32 *h); -int gsc_g_crop(struct gsc_ctx *ctx, struct v4l2_crop *cr); -int gsc_try_crop(struct gsc_ctx *ctx, struct v4l2_crop *cr); +int gsc_try_selection(struct gsc_ctx *ctx, struct v4l2_selection *s); int gsc_cal_prescaler_ratio(struct gsc_variant *var, u32 src, u32 dst, u32 *ratio); void gsc_get_prescaler_shfactor(u32 hratio, u32 vratio, u32 *sh); diff --git a/drivers/media/platform/exynos-gsc/gsc-m2m.c b/drivers/media/platform/exynos-gsc/gsc-m2m.c index cc5d690818e1..c757f5d98bcc 100644 --- a/drivers/media/platform/exynos-gsc/gsc-m2m.c +++ b/drivers/media/platform/exynos-gsc/gsc-m2m.c @@ -494,30 +494,27 @@ static int gsc_m2m_s_selection(struct file *file, void *fh, { struct gsc_frame *frame; struct gsc_ctx *ctx = fh_to_ctx(fh); - struct v4l2_crop cr; struct gsc_variant *variant = ctx->gsc_dev->variant; + struct v4l2_selection sel = *s; int ret; - cr.type = s->type; - cr.c = s->r; - if ((s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) && (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)) return -EINVAL; - ret = gsc_try_crop(ctx, &cr); + ret = gsc_try_selection(ctx, &sel); if (ret) return ret; if (s->flags & V4L2_SEL_FLAG_LE && - !is_rectangle_enclosed(&cr.c, &s->r)) + !is_rectangle_enclosed(&sel.r, &s->r)) return -ERANGE; if (s->flags & V4L2_SEL_FLAG_GE && - !is_rectangle_enclosed(&s->r, &cr.c)) + !is_rectangle_enclosed(&s->r, &sel.r)) return -ERANGE; - s->r = cr.c; + s->r = sel.r; switch (s->target) { case V4L2_SEL_TGT_COMPOSE_BOUNDS: @@ -539,15 +536,15 @@ static int gsc_m2m_s_selection(struct file *file, void *fh, /* Check to see if scaling ratio is within supported range */ if (gsc_ctx_state_is_set(GSC_DST_FMT | GSC_SRC_FMT, ctx)) { if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { - ret = gsc_check_scaler_ratio(variant, cr.c.width, - cr.c.height, ctx->d_frame.crop.width, + ret = gsc_check_scaler_ratio(variant, sel.r.width, + sel.r.height, ctx->d_frame.crop.width, ctx->d_frame.crop.height, ctx->gsc_ctrls.rotate->val, ctx->out_path); } else { ret = gsc_check_scaler_ratio(variant, ctx->s_frame.crop.width, - ctx->s_frame.crop.height, cr.c.width, - cr.c.height, ctx->gsc_ctrls.rotate->val, + ctx->s_frame.crop.height, sel.r.width, + sel.r.height, ctx->gsc_ctrls.rotate->val, ctx->out_path); } @@ -557,7 +554,7 @@ static int gsc_m2m_s_selection(struct file *file, void *fh, } } - frame->crop = cr.c; + frame->crop = sel.r; gsc_ctx_state_lock_set(GSC_PARAMS, ctx); return 0; diff --git a/drivers/media/platform/exynos4-is/fimc-core.h b/drivers/media/platform/exynos4-is/fimc-core.h index 82d514df97f0..9f751a5efd64 100644 --- a/drivers/media/platform/exynos4-is/fimc-core.h +++ b/drivers/media/platform/exynos4-is/fimc-core.h @@ -596,12 +596,14 @@ static inline struct fimc_frame *ctx_get_frame(struct fimc_ctx *ctx, { struct fimc_frame *frame; - if (V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE == type) { + if (type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE || + type == V4L2_BUF_TYPE_VIDEO_OUTPUT) { if (fimc_ctx_state_is_set(FIMC_CTX_M2M, ctx)) frame = &ctx->s_frame; else return ERR_PTR(-EINVAL); - } else if (V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE == type) { + } else if (type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE || + type == V4L2_BUF_TYPE_VIDEO_CAPTURE) { frame = &ctx->d_frame; } else { v4l2_err(ctx->fimc_dev->v4l2_dev, diff --git a/drivers/media/platform/exynos4-is/fimc-is-errno.c b/drivers/media/platform/exynos4-is/fimc-is-errno.c index e050e63fe358..bbb08576492e 100644 --- a/drivers/media/platform/exynos4-is/fimc-is-errno.c +++ b/drivers/media/platform/exynos4-is/fimc-is-errno.c @@ -90,8 +90,8 @@ const char *fimc_is_param_strerr(unsigned int error) return "ERROR_SENSOR_INVALID_SIZE"; case ERROR_SENSOR_INVALID_SETTING: return "ERROR_SENSOR_INVALID_SETTING"; - case ERROR_SENSOR_ACTURATOR_INIT_FAIL: - return "ERROR_SENSOR_ACTURATOR_INIT_FAIL"; + case ERROR_SENSOR_ACTUATOR_INIT_FAIL: + return "ERROR_SENSOR_ACTUATOR_INIT_FAIL"; case ERROR_SENSOR_INVALID_AF_POS: return "ERROR_SENSOR_INVALID_AF_POS"; case ERROR_SENSOR_UNSUPPORT_FUNC: diff --git a/drivers/media/platform/exynos4-is/fimc-is-errno.h b/drivers/media/platform/exynos4-is/fimc-is-errno.h index ef981e74513a..77f4fc860be5 100644 --- a/drivers/media/platform/exynos4-is/fimc-is-errno.h +++ b/drivers/media/platform/exynos4-is/fimc-is-errno.h @@ -189,7 +189,7 @@ enum fimc_is_error { ERROR_SENSOR_INVALID_EXPOSURETIME, ERROR_SENSOR_INVALID_SIZE, ERROR_SENSOR_INVALID_SETTING, - ERROR_SENSOR_ACTURATOR_INIT_FAIL, + ERROR_SENSOR_ACTUATOR_INIT_FAIL, ERROR_SENSOR_INVALID_AF_POS, ERROR_SENSOR_UNSUPPORT_FUNC, ERROR_SENSOR_UNSUPPORT_PERI, diff --git a/drivers/media/platform/exynos4-is/fimc-m2m.c b/drivers/media/platform/exynos4-is/fimc-m2m.c index a19f8b164a47..61c8177409cf 100644 --- a/drivers/media/platform/exynos4-is/fimc-m2m.c +++ b/drivers/media/platform/exynos4-is/fimc-m2m.c @@ -383,60 +383,80 @@ static int fimc_m2m_s_fmt_mplane(struct file *file, void *fh, return 0; } -static int fimc_m2m_cropcap(struct file *file, void *fh, - struct v4l2_cropcap *cr) +static int fimc_m2m_g_selection(struct file *file, void *fh, + struct v4l2_selection *s) { struct fimc_ctx *ctx = fh_to_ctx(fh); struct fimc_frame *frame; - frame = ctx_get_frame(ctx, cr->type); + frame = ctx_get_frame(ctx, s->type); if (IS_ERR(frame)) return PTR_ERR(frame); - cr->bounds.left = 0; - cr->bounds.top = 0; - cr->bounds.width = frame->o_width; - cr->bounds.height = frame->o_height; - cr->defrect = cr->bounds; - - return 0; -} - -static int fimc_m2m_g_crop(struct file *file, void *fh, struct v4l2_crop *cr) -{ - struct fimc_ctx *ctx = fh_to_ctx(fh); - struct fimc_frame *frame; - - frame = ctx_get_frame(ctx, cr->type); - if (IS_ERR(frame)) - return PTR_ERR(frame); - - cr->c.left = frame->offs_h; - cr->c.top = frame->offs_v; - cr->c.width = frame->width; - cr->c.height = frame->height; + switch (s->target) { + case V4L2_SEL_TGT_CROP: + case V4L2_SEL_TGT_CROP_DEFAULT: + case V4L2_SEL_TGT_CROP_BOUNDS: + if (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) + return -EINVAL; + break; + case V4L2_SEL_TGT_COMPOSE: + case V4L2_SEL_TGT_COMPOSE_DEFAULT: + case V4L2_SEL_TGT_COMPOSE_BOUNDS: + if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + break; + default: + return -EINVAL; + } + switch (s->target) { + case V4L2_SEL_TGT_CROP: + case V4L2_SEL_TGT_COMPOSE: + s->r.left = frame->offs_h; + s->r.top = frame->offs_v; + s->r.width = frame->width; + s->r.height = frame->height; + break; + case V4L2_SEL_TGT_CROP_DEFAULT: + case V4L2_SEL_TGT_CROP_BOUNDS: + case V4L2_SEL_TGT_COMPOSE_DEFAULT: + case V4L2_SEL_TGT_COMPOSE_BOUNDS: + s->r.left = 0; + s->r.top = 0; + s->r.width = frame->o_width; + s->r.height = frame->o_height; + break; + default: + return -EINVAL; + } return 0; } -static int fimc_m2m_try_crop(struct fimc_ctx *ctx, struct v4l2_crop *cr) +static int fimc_m2m_try_selection(struct fimc_ctx *ctx, + struct v4l2_selection *s) { struct fimc_dev *fimc = ctx->fimc_dev; struct fimc_frame *f; u32 min_size, halign, depth = 0; int i; - if (cr->c.top < 0 || cr->c.left < 0) { + if (s->r.top < 0 || s->r.left < 0) { v4l2_err(&fimc->m2m.vfd, "doesn't support negative values for top & left\n"); return -EINVAL; } - if (cr->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) + if (s->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) { f = &ctx->d_frame; - else if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) + if (s->target != V4L2_SEL_TGT_COMPOSE) + return -EINVAL; + } else if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) { f = &ctx->s_frame; - else + if (s->target != V4L2_SEL_TGT_CROP) + return -EINVAL; + } else { return -EINVAL; + } min_size = (f == &ctx->s_frame) ? fimc->variant->min_inp_pixsize : fimc->variant->min_out_pixsize; @@ -450,61 +470,61 @@ static int fimc_m2m_try_crop(struct fimc_ctx *ctx, struct v4l2_crop *cr) for (i = 0; i < f->fmt->memplanes; i++) depth += f->fmt->depth[i]; - v4l_bound_align_image(&cr->c.width, min_size, f->o_width, + v4l_bound_align_image(&s->r.width, min_size, f->o_width, ffs(min_size) - 1, - &cr->c.height, min_size, f->o_height, + &s->r.height, min_size, f->o_height, halign, 64/(ALIGN(depth, 8))); /* adjust left/top if cropping rectangle is out of bounds */ - if (cr->c.left + cr->c.width > f->o_width) - cr->c.left = f->o_width - cr->c.width; - if (cr->c.top + cr->c.height > f->o_height) - cr->c.top = f->o_height - cr->c.height; + if (s->r.left + s->r.width > f->o_width) + s->r.left = f->o_width - s->r.width; + if (s->r.top + s->r.height > f->o_height) + s->r.top = f->o_height - s->r.height; - cr->c.left = round_down(cr->c.left, min_size); - cr->c.top = round_down(cr->c.top, fimc->variant->hor_offs_align); + s->r.left = round_down(s->r.left, min_size); + s->r.top = round_down(s->r.top, fimc->variant->hor_offs_align); dbg("l:%d, t:%d, w:%d, h:%d, f_w: %d, f_h: %d", - cr->c.left, cr->c.top, cr->c.width, cr->c.height, + s->r.left, s->r.top, s->r.width, s->r.height, f->f_width, f->f_height); return 0; } -static int fimc_m2m_s_crop(struct file *file, void *fh, const struct v4l2_crop *crop) +static int fimc_m2m_s_selection(struct file *file, void *fh, + struct v4l2_selection *s) { struct fimc_ctx *ctx = fh_to_ctx(fh); struct fimc_dev *fimc = ctx->fimc_dev; - struct v4l2_crop cr = *crop; struct fimc_frame *f; int ret; - ret = fimc_m2m_try_crop(ctx, &cr); + ret = fimc_m2m_try_selection(ctx, s); if (ret) return ret; - f = (cr.type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) ? + f = (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) ? &ctx->s_frame : &ctx->d_frame; /* Check to see if scaling ratio is within supported range */ - if (cr.type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { - ret = fimc_check_scaler_ratio(ctx, cr.c.width, - cr.c.height, ctx->d_frame.width, + if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) { + ret = fimc_check_scaler_ratio(ctx, s->r.width, + s->r.height, ctx->d_frame.width, ctx->d_frame.height, ctx->rotation); } else { ret = fimc_check_scaler_ratio(ctx, ctx->s_frame.width, - ctx->s_frame.height, cr.c.width, - cr.c.height, ctx->rotation); + ctx->s_frame.height, s->r.width, + s->r.height, ctx->rotation); } if (ret) { v4l2_err(&fimc->m2m.vfd, "Out of scaler range\n"); return -EINVAL; } - f->offs_h = cr.c.left; - f->offs_v = cr.c.top; - f->width = cr.c.width; - f->height = cr.c.height; + f->offs_h = s->r.left; + f->offs_v = s->r.top; + f->width = s->r.width; + f->height = s->r.height; fimc_ctx_state_set(FIMC_PARAMS, ctx); @@ -528,9 +548,8 @@ static const struct v4l2_ioctl_ops fimc_m2m_ioctl_ops = { .vidioc_expbuf = v4l2_m2m_ioctl_expbuf, .vidioc_streamon = v4l2_m2m_ioctl_streamon, .vidioc_streamoff = v4l2_m2m_ioctl_streamoff, - .vidioc_g_crop = fimc_m2m_g_crop, - .vidioc_s_crop = fimc_m2m_s_crop, - .vidioc_cropcap = fimc_m2m_cropcap + .vidioc_g_selection = fimc_m2m_g_selection, + .vidioc_s_selection = fimc_m2m_s_selection, }; @@ -717,6 +736,7 @@ int fimc_register_m2m_device(struct fimc_dev *fimc, vfd->release = video_device_release_empty; vfd->lock = &fimc->lock; vfd->vfl_dir = VFL_DIR_M2M; + set_bit(V4L2_FL_QUIRK_INVERTED_CROP, &vfd->flags); snprintf(vfd->name, sizeof(vfd->name), "fimc.%d.m2m", fimc->id); video_set_drvdata(vfd, fimc); diff --git a/drivers/media/platform/exynos4-is/media-dev.c b/drivers/media/platform/exynos4-is/media-dev.c index 870501b0f351..463f2d84553e 100644 --- a/drivers/media/platform/exynos4-is/media-dev.c +++ b/drivers/media/platform/exynos4-is/media-dev.c @@ -445,7 +445,7 @@ static int fimc_md_parse_port_node(struct fimc_md *fmd, */ np = of_get_parent(rem); - if (np && !of_node_cmp(np->name, "i2c-isp")) + if (of_node_name_eq(np, "i2c-isp")) pd->fimc_bus_type = FIMC_BUS_TYPE_ISP_WRITEBACK; else pd->fimc_bus_type = pd->sensor_bus_type; @@ -495,7 +495,7 @@ static int fimc_md_register_sensor_entities(struct fimc_md *fmd) for_each_available_child_of_node(parent, node) { struct device_node *port; - if (of_node_cmp(node->name, "csis")) + if (!of_node_name_eq(node, "csis")) continue; /* The csis node can have only port subnode. */ port = of_get_next_child(node, NULL); @@ -720,13 +720,13 @@ static int fimc_md_register_platform_entities(struct fimc_md *fmd, continue; /* If driver of any entity isn't ready try all again later. */ - if (!strcmp(node->name, CSIS_OF_NODE_NAME)) + if (of_node_name_eq(node, CSIS_OF_NODE_NAME)) plat_entity = IDX_CSIS; - else if (!strcmp(node->name, FIMC_IS_OF_NODE_NAME)) + else if (of_node_name_eq(node, FIMC_IS_OF_NODE_NAME)) plat_entity = IDX_IS_ISP; - else if (!strcmp(node->name, FIMC_LITE_OF_NODE_NAME)) + else if (of_node_name_eq(node, FIMC_LITE_OF_NODE_NAME)) plat_entity = IDX_FLITE; - else if (!strcmp(node->name, FIMC_OF_NODE_NAME) && + else if (of_node_name_eq(node, FIMC_OF_NODE_NAME) && !of_property_read_bool(node, "samsung,lcd-wb")) plat_entity = IDX_FIMC; diff --git a/drivers/media/platform/imx-pxp.c b/drivers/media/platform/imx-pxp.c index b76cd0e8313c..c1c255408d16 100644 --- a/drivers/media/platform/imx-pxp.c +++ b/drivers/media/platform/imx-pxp.c @@ -16,7 +16,6 @@ #include <linux/interrupt.h> #include <linux/io.h> #include <linux/iopoll.h> -#include <linux/interrupt.h> #include <linux/module.h> #include <linux/of.h> #include <linux/sched.h> @@ -1607,7 +1606,7 @@ static const struct v4l2_m2m_ops m2m_ops = { .job_abort = pxp_job_abort, }; -static void pxp_soft_reset(struct pxp_dev *dev) +static int pxp_soft_reset(struct pxp_dev *dev) { int ret; u32 val; @@ -1620,10 +1619,12 @@ static void pxp_soft_reset(struct pxp_dev *dev) ret = readl_poll_timeout(dev->mmio + HW_PXP_CTRL, val, val & BM_PXP_CTRL_CLKGATE, 0, 100); if (ret < 0) - pr_err("PXP reset timeout\n"); + return ret; writel(BM_PXP_CTRL_SFTRST, dev->mmio + HW_PXP_CTRL_CLR); writel(BM_PXP_CTRL_CLKGATE, dev->mmio + HW_PXP_CTRL_CLR); + + return 0; } static int pxp_probe(struct platform_device *pdev) @@ -1666,8 +1667,15 @@ static int pxp_probe(struct platform_device *pdev) return ret; } - clk_prepare_enable(dev->clk); - pxp_soft_reset(dev); + ret = clk_prepare_enable(dev->clk); + if (ret < 0) + return ret; + + ret = pxp_soft_reset(dev); + if (ret < 0) { + dev_err(&pdev->dev, "PXP reset timeout: %d\n", ret); + goto err_clk; + } spin_lock_init(&dev->irqlock); diff --git a/drivers/media/platform/marvell-ccic/cafe-driver.c b/drivers/media/platform/marvell-ccic/cafe-driver.c index 2986cb4b88d0..8d00d9d8adff 100644 --- a/drivers/media/platform/marvell-ccic/cafe-driver.c +++ b/drivers/media/platform/marvell-ccic/cafe-driver.c @@ -4,7 +4,7 @@ * sensor. * * The data sheet for this device can be found at: - * http://www.marvell.com/products/pc_connectivity/88alp01/ + * http://wiki.laptop.org/images/5/5c/88ALP01_Datasheet_July_2007.pdf * * Copyright 2006-11 One Laptop Per Child Association, Inc. * Copyright 2006-11 Jonathan Corbet <corbet@lwn.net> diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c index 54631ad1c71e..d1f12257bf66 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c @@ -1087,7 +1087,6 @@ static void mtk_venc_worker(struct work_struct *work) src_buf = v4l2_m2m_src_buf_remove(ctx->m2m_ctx); memset(&frm_buf, 0, sizeof(frm_buf)); for (i = 0; i < src_buf->num_planes ; i++) { - frm_buf.fb_addr[i].va = vb2_plane_vaddr(src_buf, i); frm_buf.fb_addr[i].dma_addr = vb2_dma_contig_plane_dma_addr(src_buf, i); frm_buf.fb_addr[i].size = @@ -1098,14 +1097,11 @@ static void mtk_venc_worker(struct work_struct *work) bs_buf.size = (size_t)dst_buf->planes[0].length; mtk_v4l2_debug(2, - "Framebuf VA=%p PA=%llx Size=0x%zx;VA=%p PA=0x%llx Size=0x%zx;VA=%p PA=0x%llx Size=%zu", - frm_buf.fb_addr[0].va, + "Framebuf PA=%llx Size=0x%zx;PA=0x%llx Size=0x%zx;PA=0x%llx Size=%zu", (u64)frm_buf.fb_addr[0].dma_addr, frm_buf.fb_addr[0].size, - frm_buf.fb_addr[1].va, (u64)frm_buf.fb_addr[1].dma_addr, frm_buf.fb_addr[1].size, - frm_buf.fb_addr[2].va, (u64)frm_buf.fb_addr[2].dma_addr, frm_buf.fb_addr[2].size); diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_pm.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_pm.c index 3e73e9db781f..7c025045ea90 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_pm.c +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_pm.c @@ -41,25 +41,27 @@ int mtk_vcodec_init_enc_pm(struct mtk_vcodec_dev *mtkdev) node = of_parse_phandle(dev->of_node, "mediatek,larb", 0); if (!node) { mtk_v4l2_err("no mediatek,larb found"); - return -1; + return -ENODEV; } pdev = of_find_device_by_node(node); + of_node_put(node); if (!pdev) { mtk_v4l2_err("no mediatek,larb device found"); - return -1; + return -ENODEV; } pm->larbvenc = &pdev->dev; node = of_parse_phandle(dev->of_node, "mediatek,larb", 1); if (!node) { mtk_v4l2_err("no mediatek,larb found"); - return -1; + return -ENODEV; } pdev = of_find_device_by_node(node); + of_node_put(node); if (!pdev) { mtk_v4l2_err("no mediatek,larb device found"); - return -1; + return -ENODEV; } pm->larbvenclt = &pdev->dev; diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_util.h b/drivers/media/platform/mtk-vcodec/mtk_vcodec_util.h index 06c254f5c171..9bf6e8d1b9c9 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_util.h +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_util.h @@ -25,6 +25,11 @@ struct mtk_vcodec_mem { dma_addr_t dma_addr; }; +struct mtk_vcodec_fb { + size_t size; + dma_addr_t dma_addr; +}; + struct mtk_vcodec_ctx; struct mtk_vcodec_dev; diff --git a/drivers/media/platform/mtk-vcodec/venc_drv_if.h b/drivers/media/platform/mtk-vcodec/venc_drv_if.h index a6e7d32e55cb..55ecda844894 100644 --- a/drivers/media/platform/mtk-vcodec/venc_drv_if.h +++ b/drivers/media/platform/mtk-vcodec/venc_drv_if.h @@ -106,7 +106,7 @@ struct venc_enc_param { * @fb_addr: plane frame buffer addresses */ struct venc_frm_buf { - struct mtk_vcodec_mem fb_addr[MTK_VCODEC_MAX_PLANES]; + struct mtk_vcodec_fb fb_addr[MTK_VCODEC_MAX_PLANES]; }; /* diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c index ed6a557de65d..a8c542fa647d 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe.c +++ b/drivers/media/platform/qcom/camss/camss-vfe.c @@ -37,9 +37,9 @@ /* VFE halt timeout */ #define VFE_HALT_TIMEOUT_MS 100 /* Max number of frame drop updates per frame */ -#define VFE_FRAME_DROP_UPDATES 5 -/* Frame drop value. NOTE: VAL + UPDATES should not exceed 31 */ -#define VFE_FRAME_DROP_VAL 20 +#define VFE_FRAME_DROP_UPDATES 2 +/* Frame drop value. VAL + UPDATES - 1 should not exceed 31 */ +#define VFE_FRAME_DROP_VAL 30 #define VFE_NEXT_SOF_MS 500 @@ -659,7 +659,9 @@ static int vfe_enable_output(struct vfe_line *line) struct vfe_device *vfe = to_vfe(line); struct vfe_output *output = &line->output; const struct vfe_hw_ops *ops = vfe->ops; + struct media_entity *sensor; unsigned long flags; + unsigned int frame_skip = 0; unsigned int i; u16 ub_size; @@ -667,6 +669,17 @@ static int vfe_enable_output(struct vfe_line *line) if (!ub_size) return -EINVAL; + sensor = camss_find_sensor(&line->subdev.entity); + if (sensor) { + struct v4l2_subdev *subdev = + media_entity_to_v4l2_subdev(sensor); + + v4l2_subdev_call(subdev, sensor, g_skip_frames, &frame_skip); + /* Max frame skip is 29 frames */ + if (frame_skip > VFE_FRAME_DROP_VAL - 1) + frame_skip = VFE_FRAME_DROP_VAL - 1; + } + spin_lock_irqsave(&vfe->output_lock, flags); ops->reg_update_clear(vfe, line->id); @@ -695,10 +708,10 @@ static int vfe_enable_output(struct vfe_line *line) switch (output->state) { case VFE_OUTPUT_SINGLE: - vfe_output_frame_drop(vfe, output, 1); + vfe_output_frame_drop(vfe, output, 1 << frame_skip); break; case VFE_OUTPUT_CONTINUOUS: - vfe_output_frame_drop(vfe, output, 3); + vfe_output_frame_drop(vfe, output, 3 << frame_skip); break; default: vfe_output_frame_drop(vfe, output, 0); diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index 45978db3b0be..63da18773d24 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -346,7 +346,7 @@ void camss_disable_clocks(int nclocks, struct camss_clock *clock) * * Return a pointer to sensor media entity or NULL if not found */ -static struct media_entity *camss_find_sensor(struct media_entity *entity) +struct media_entity *camss_find_sensor(struct media_entity *entity) { struct media_pad *pad; diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h index 57b269ca93fd..1376b07889bf 100644 --- a/drivers/media/platform/qcom/camss/camss.h +++ b/drivers/media/platform/qcom/camss/camss.h @@ -106,6 +106,7 @@ void camss_add_clock_margin(u64 *rate); int camss_enable_clocks(int nclocks, struct camss_clock *clock, struct device *dev); void camss_disable_clocks(int nclocks, struct camss_clock *clock); +struct media_entity *camss_find_sensor(struct media_entity *entity); int camss_get_pixel_clock(struct media_entity *entity, u32 *pixel_clock); int camss_pm_domain_on(struct camss *camss, int id); void camss_pm_domain_off(struct camss *camss, int id); diff --git a/drivers/media/platform/qcom/venus/core.c b/drivers/media/platform/qcom/venus/core.c index bb6add9d340e..cb411eb85ee4 100644 --- a/drivers/media/platform/qcom/venus/core.c +++ b/drivers/media/platform/qcom/venus/core.c @@ -76,7 +76,7 @@ static void venus_sys_error_handler(struct work_struct *work) hfi_core_deinit(core, true); hfi_destroy(core); mutex_lock(&core->lock); - venus_shutdown(core->dev); + venus_shutdown(core); pm_runtime_put_sync(core->dev); @@ -84,7 +84,7 @@ static void venus_sys_error_handler(struct work_struct *work) pm_runtime_get_sync(core->dev); - ret |= venus_boot(core->dev, core->res->fwname); + ret |= venus_boot(core); ret |= hfi_core_resume(core, true); @@ -264,6 +264,14 @@ static int venus_probe(struct platform_device *pdev) if (ret) return ret; + if (!dev->dma_parms) { + dev->dma_parms = devm_kzalloc(dev, sizeof(*dev->dma_parms), + GFP_KERNEL); + if (!dev->dma_parms) + return -ENOMEM; + } + dma_set_max_seg_size(dev, DMA_BIT_MASK(32)); + INIT_LIST_HEAD(&core->instances); mutex_init(&core->lock); INIT_DELAYED_WORK(&core->work, venus_sys_error_handler); @@ -284,7 +292,15 @@ static int venus_probe(struct platform_device *pdev) if (ret < 0) goto err_runtime_disable; - ret = venus_boot(dev, core->res->fwname); + ret = of_platform_populate(dev->of_node, NULL, NULL, dev); + if (ret) + goto err_runtime_disable; + + ret = venus_firmware_init(core); + if (ret) + goto err_runtime_disable; + + ret = venus_boot(core); if (ret) goto err_runtime_disable; @@ -308,10 +324,6 @@ static int venus_probe(struct platform_device *pdev) if (ret) goto err_core_deinit; - ret = of_platform_populate(dev->of_node, NULL, NULL, dev); - if (ret) - goto err_dev_unregister; - ret = pm_runtime_put_sync(dev); if (ret) goto err_dev_unregister; @@ -323,7 +335,7 @@ err_dev_unregister: err_core_deinit: hfi_core_deinit(core, false); err_venus_shutdown: - venus_shutdown(dev); + venus_shutdown(core); err_runtime_disable: pm_runtime_set_suspended(dev); pm_runtime_disable(dev); @@ -344,9 +356,11 @@ static int venus_remove(struct platform_device *pdev) WARN_ON(ret); hfi_destroy(core); - venus_shutdown(dev); + venus_shutdown(core); of_platform_depopulate(dev); + venus_firmware_deinit(core); + pm_runtime_put_sync(dev); pm_runtime_disable(dev); diff --git a/drivers/media/platform/qcom/venus/core.h b/drivers/media/platform/qcom/venus/core.h index 2f02365f4818..6382cea29185 100644 --- a/drivers/media/platform/qcom/venus/core.h +++ b/drivers/media/platform/qcom/venus/core.h @@ -98,6 +98,7 @@ struct venus_caps { * @dev: convenience struct device pointer * @dev_dec: convenience struct device pointer for decoder device * @dev_enc: convenience struct device pointer for encoder device + * @use_tz: a flag that suggests presence of trustzone * @lock: a lock for this strucure * @instances: a list_head of all instances * @insts_count: num of instances @@ -129,6 +130,11 @@ struct venus_core { struct device *dev; struct device *dev_dec; struct device *dev_enc; + unsigned int use_tz; + struct video_firmware { + struct device *dev; + struct iommu_domain *iommu_domain; + } fw; struct mutex lock; struct list_head instances; atomic_t insts_count; diff --git a/drivers/media/platform/qcom/venus/firmware.c b/drivers/media/platform/qcom/venus/firmware.c index c4a577848dd7..c29acfd70c1b 100644 --- a/drivers/media/platform/qcom/venus/firmware.c +++ b/drivers/media/platform/qcom/venus/firmware.c @@ -15,32 +15,66 @@ #include <linux/device.h> #include <linux/firmware.h> #include <linux/kernel.h> +#include <linux/iommu.h> #include <linux/io.h> #include <linux/of.h> #include <linux/of_address.h> +#include <linux/platform_device.h> +#include <linux/of_device.h> #include <linux/qcom_scm.h> #include <linux/sizes.h> #include <linux/soc/qcom/mdt_loader.h> +#include "core.h" #include "firmware.h" +#include "hfi_venus_io.h" #define VENUS_PAS_ID 9 #define VENUS_FW_MEM_SIZE (6 * SZ_1M) +#define VENUS_FW_START_ADDR 0x0 -int venus_boot(struct device *dev, const char *fwname) +static void venus_reset_cpu(struct venus_core *core) +{ + void __iomem *base = core->base; + + writel(0, base + WRAPPER_FW_START_ADDR); + writel(VENUS_FW_MEM_SIZE, base + WRAPPER_FW_END_ADDR); + writel(0, base + WRAPPER_CPA_START_ADDR); + writel(VENUS_FW_MEM_SIZE, base + WRAPPER_CPA_END_ADDR); + writel(VENUS_FW_MEM_SIZE, base + WRAPPER_NONPIX_START_ADDR); + writel(VENUS_FW_MEM_SIZE, base + WRAPPER_NONPIX_END_ADDR); + writel(0x0, base + WRAPPER_CPU_CGC_DIS); + writel(0x0, base + WRAPPER_CPU_CLOCK_CONFIG); + + /* Bring ARM9 out of reset */ + writel(0, base + WRAPPER_A9SS_SW_RESET); +} + +int venus_set_hw_state(struct venus_core *core, bool resume) +{ + if (core->use_tz) + return qcom_scm_set_remote_state(resume, 0); + + if (resume) + venus_reset_cpu(core); + else + writel(1, core->base + WRAPPER_A9SS_SW_RESET); + + return 0; +} + +static int venus_load_fw(struct venus_core *core, const char *fwname, + phys_addr_t *mem_phys, size_t *mem_size) { const struct firmware *mdt; struct device_node *node; - phys_addr_t mem_phys; + struct device *dev; struct resource r; ssize_t fw_size; - size_t mem_size; void *mem_va; int ret; - if (!IS_ENABLED(CONFIG_QCOM_MDT_LOADER) || !qcom_scm_is_available()) - return -EPROBE_DEFER; - + dev = core->dev; node = of_parse_phandle(dev->of_node, "memory-region", 0); if (!node) { dev_err(dev, "no memory-region specified\n"); @@ -51,16 +85,16 @@ int venus_boot(struct device *dev, const char *fwname) if (ret) return ret; - mem_phys = r.start; - mem_size = resource_size(&r); + *mem_phys = r.start; + *mem_size = resource_size(&r); - if (mem_size < VENUS_FW_MEM_SIZE) + if (*mem_size < VENUS_FW_MEM_SIZE) return -EINVAL; - mem_va = memremap(r.start, mem_size, MEMREMAP_WC); + mem_va = memremap(r.start, *mem_size, MEMREMAP_WC); if (!mem_va) { dev_err(dev, "unable to map memory region: %pa+%zx\n", - &r.start, mem_size); + &r.start, *mem_size); return -ENOMEM; } @@ -75,24 +109,181 @@ int venus_boot(struct device *dev, const char *fwname) goto err_unmap; } - ret = qcom_mdt_load(dev, mdt, fwname, VENUS_PAS_ID, mem_va, mem_phys, - mem_size, NULL); + if (core->use_tz) + ret = qcom_mdt_load(dev, mdt, fwname, VENUS_PAS_ID, + mem_va, *mem_phys, *mem_size, NULL); + else + ret = qcom_mdt_load_no_init(dev, mdt, fwname, VENUS_PAS_ID, + mem_va, *mem_phys, *mem_size, NULL); release_firmware(mdt); - if (ret) - goto err_unmap; - - ret = qcom_scm_pas_auth_and_reset(VENUS_PAS_ID); - if (ret) - goto err_unmap; - err_unmap: memunmap(mem_va); return ret; } -int venus_shutdown(struct device *dev) +static int venus_boot_no_tz(struct venus_core *core, phys_addr_t mem_phys, + size_t mem_size) +{ + struct iommu_domain *iommu; + struct device *dev; + int ret; + + dev = core->fw.dev; + if (!dev) + return -EPROBE_DEFER; + + iommu = core->fw.iommu_domain; + + ret = iommu_map(iommu, VENUS_FW_START_ADDR, mem_phys, mem_size, + IOMMU_READ | IOMMU_WRITE | IOMMU_PRIV); + if (ret) { + dev_err(dev, "could not map video firmware region\n"); + return ret; + } + + venus_reset_cpu(core); + + return 0; +} + +static int venus_shutdown_no_tz(struct venus_core *core) +{ + struct iommu_domain *iommu; + size_t unmapped; + u32 reg; + struct device *dev = core->fw.dev; + void __iomem *base = core->base; + + /* Assert the reset to ARM9 */ + reg = readl_relaxed(base + WRAPPER_A9SS_SW_RESET); + reg |= WRAPPER_A9SS_SW_RESET_BIT; + writel_relaxed(reg, base + WRAPPER_A9SS_SW_RESET); + + /* Make sure reset is asserted before the mapping is removed */ + mb(); + + iommu = core->fw.iommu_domain; + + unmapped = iommu_unmap(iommu, VENUS_FW_START_ADDR, VENUS_FW_MEM_SIZE); + if (unmapped != VENUS_FW_MEM_SIZE) + dev_err(dev, "failed to unmap firmware\n"); + + return 0; +} + +int venus_boot(struct venus_core *core) { - return qcom_scm_pas_shutdown(VENUS_PAS_ID); + struct device *dev = core->dev; + phys_addr_t mem_phys; + size_t mem_size; + int ret; + + if (!IS_ENABLED(CONFIG_QCOM_MDT_LOADER) || + (core->use_tz && !qcom_scm_is_available())) + return -EPROBE_DEFER; + + ret = venus_load_fw(core, core->res->fwname, &mem_phys, &mem_size); + if (ret) { + dev_err(dev, "fail to load video firmware\n"); + return -EINVAL; + } + + if (core->use_tz) + ret = qcom_scm_pas_auth_and_reset(VENUS_PAS_ID); + else + ret = venus_boot_no_tz(core, mem_phys, mem_size); + + return ret; +} + +int venus_shutdown(struct venus_core *core) +{ + int ret; + + if (core->use_tz) + ret = qcom_scm_pas_shutdown(VENUS_PAS_ID); + else + ret = venus_shutdown_no_tz(core); + + return ret; +} + +int venus_firmware_init(struct venus_core *core) +{ + struct platform_device_info info; + struct iommu_domain *iommu_dom; + struct platform_device *pdev; + struct device_node *np; + int ret; + + np = of_get_child_by_name(core->dev->of_node, "video-firmware"); + if (!np) { + core->use_tz = true; + return 0; + } + + memset(&info, 0, sizeof(info)); + info.fwnode = &np->fwnode; + info.parent = core->dev; + info.name = np->name; + info.dma_mask = DMA_BIT_MASK(32); + + pdev = platform_device_register_full(&info); + if (IS_ERR(pdev)) { + of_node_put(np); + return PTR_ERR(pdev); + } + + pdev->dev.of_node = np; + + ret = of_dma_configure(&pdev->dev, np, true); + if (ret) { + dev_err(core->dev, "dma configure fail\n"); + goto err_unregister; + } + + core->fw.dev = &pdev->dev; + + iommu_dom = iommu_domain_alloc(&platform_bus_type); + if (!iommu_dom) { + dev_err(core->fw.dev, "Failed to allocate iommu domain\n"); + ret = -ENOMEM; + goto err_unregister; + } + + ret = iommu_attach_device(iommu_dom, core->fw.dev); + if (ret) { + dev_err(core->fw.dev, "could not attach device\n"); + goto err_iommu_free; + } + + core->fw.iommu_domain = iommu_dom; + + of_node_put(np); + + return 0; + +err_iommu_free: + iommu_domain_free(iommu_dom); +err_unregister: + platform_device_unregister(pdev); + of_node_put(np); + return ret; +} + +void venus_firmware_deinit(struct venus_core *core) +{ + struct iommu_domain *iommu; + + if (!core->fw.dev) + return; + + iommu = core->fw.iommu_domain; + + iommu_detach_device(iommu, core->fw.dev); + iommu_domain_free(iommu); + + platform_device_unregister(to_platform_device(core->fw.dev)); } diff --git a/drivers/media/platform/qcom/venus/firmware.h b/drivers/media/platform/qcom/venus/firmware.h index 428efb56d339..119a9a4fc1a2 100644 --- a/drivers/media/platform/qcom/venus/firmware.h +++ b/drivers/media/platform/qcom/venus/firmware.h @@ -16,7 +16,20 @@ struct device; -int venus_boot(struct device *dev, const char *fwname); -int venus_shutdown(struct device *dev); +int venus_firmware_init(struct venus_core *core); +void venus_firmware_deinit(struct venus_core *core); +int venus_boot(struct venus_core *core); +int venus_shutdown(struct venus_core *core); +int venus_set_hw_state(struct venus_core *core, bool suspend); + +static inline int venus_set_hw_state_suspend(struct venus_core *core) +{ + return venus_set_hw_state(core, false); +} + +static inline int venus_set_hw_state_resume(struct venus_core *core) +{ + return venus_set_hw_state(core, true); +} #endif diff --git a/drivers/media/platform/qcom/venus/hfi_cmds.c b/drivers/media/platform/qcom/venus/hfi_cmds.c index e8389d8d8c48..87a441488e15 100644 --- a/drivers/media/platform/qcom/venus/hfi_cmds.c +++ b/drivers/media/platform/qcom/venus/hfi_cmds.c @@ -1215,7 +1215,7 @@ pkt_session_set_property_4xx(struct hfi_session_set_property_pkt *pkt, } case HFI_PROPERTY_CONFIG_VENC_MAX_BITRATE: /* not implemented on Venus 4xx */ - break; + return -ENOTSUPP; default: return pkt_session_set_property_3xx(pkt, cookie, ptype, pdata); } diff --git a/drivers/media/platform/qcom/venus/hfi_venus.c b/drivers/media/platform/qcom/venus/hfi_venus.c index 124085556b94..5c1e5b4f767a 100644 --- a/drivers/media/platform/qcom/venus/hfi_venus.c +++ b/drivers/media/platform/qcom/venus/hfi_venus.c @@ -19,7 +19,6 @@ #include <linux/interrupt.h> #include <linux/iopoll.h> #include <linux/kernel.h> -#include <linux/qcom_scm.h> #include <linux/slab.h> #include "core.h" @@ -27,6 +26,7 @@ #include "hfi_msgs.h" #include "hfi_venus.h" #include "hfi_venus_io.h" +#include "firmware.h" #define HFI_MASK_QHDR_TX_TYPE 0xff000000 #define HFI_MASK_QHDR_RX_TYPE 0x00ff0000 @@ -55,11 +55,6 @@ #define IFACEQ_VAR_LARGE_PKT_SIZE 512 #define IFACEQ_VAR_HUGE_PKT_SIZE (1024 * 12) -enum tzbsp_video_state { - TZBSP_VIDEO_STATE_SUSPEND = 0, - TZBSP_VIDEO_STATE_RESUME -}; - struct hfi_queue_table_header { u32 version; u32 size; @@ -575,7 +570,7 @@ static int venus_power_off(struct venus_hfi_device *hdev) if (!hdev->power_enabled) return 0; - ret = qcom_scm_set_remote_state(TZBSP_VIDEO_STATE_SUSPEND, 0); + ret = venus_set_hw_state_suspend(hdev->core); if (ret) return ret; @@ -595,7 +590,7 @@ static int venus_power_on(struct venus_hfi_device *hdev) if (hdev->power_enabled) return 0; - ret = qcom_scm_set_remote_state(TZBSP_VIDEO_STATE_RESUME, 0); + ret = venus_set_hw_state_resume(hdev->core); if (ret) goto err; @@ -608,7 +603,7 @@ static int venus_power_on(struct venus_hfi_device *hdev) return 0; err_suspend: - qcom_scm_set_remote_state(TZBSP_VIDEO_STATE_SUSPEND, 0); + venus_set_hw_state_suspend(hdev->core); err: hdev->power_enabled = false; return ret; @@ -1355,6 +1350,8 @@ static int venus_session_set_property(struct venus_inst *inst, u32 ptype, pkt = (struct hfi_session_set_property_pkt *)packet; ret = pkt_session_set_property(pkt, inst, ptype, pdata); + if (ret == -ENOTSUPP) + return 0; if (ret) return ret; diff --git a/drivers/media/platform/qcom/venus/hfi_venus_io.h b/drivers/media/platform/qcom/venus/hfi_venus_io.h index def0926a6dee..ef0c72a0c892 100644 --- a/drivers/media/platform/qcom/venus/hfi_venus_io.h +++ b/drivers/media/platform/qcom/venus/hfi_venus_io.h @@ -112,6 +112,14 @@ #define WRAPPER_CPU_STATUS (WRAPPER_BASE + 0x2014) #define WRAPPER_CPU_STATUS_WFI BIT(0) #define WRAPPER_SW_RESET (WRAPPER_BASE + 0x3000) +#define WRAPPER_CPA_START_ADDR (WRAPPER_BASE + 0x1020) +#define WRAPPER_CPA_END_ADDR (WRAPPER_BASE + 0x1024) +#define WRAPPER_FW_START_ADDR (WRAPPER_BASE + 0x1028) +#define WRAPPER_FW_END_ADDR (WRAPPER_BASE + 0x102C) +#define WRAPPER_NONPIX_START_ADDR (WRAPPER_BASE + 0x1030) +#define WRAPPER_NONPIX_END_ADDR (WRAPPER_BASE + 0x1034) +#define WRAPPER_A9SS_SW_RESET (WRAPPER_BASE + 0x3000) +#define WRAPPER_A9SS_SW_RESET_BIT BIT(4) /* Venus 4xx */ #define WRAPPER_VCODEC0_MMCC_POWER_STATUS (WRAPPER_BASE + 0x90) diff --git a/drivers/media/platform/qcom/venus/vdec.c b/drivers/media/platform/qcom/venus/vdec.c index 189ec975c6bb..282de21cf2e1 100644 --- a/drivers/media/platform/qcom/venus/vdec.c +++ b/drivers/media/platform/qcom/venus/vdec.c @@ -885,10 +885,8 @@ static void vdec_buf_done(struct venus_inst *inst, unsigned int buf_type, vbuf->field = V4L2_FIELD_NONE; if (type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { - unsigned int opb_sz = venus_helper_get_opb_size(inst); - vb = &vbuf->vb2_buf; - vb2_set_plane_payload(vb, 0, bytesused ? : opb_sz); + vb2_set_plane_payload(vb, 0, bytesused); vb->planes[0].data_offset = data_offset; vb->timestamp = timestamp_us * NSEC_PER_USEC; vbuf->sequence = inst->sequence_cap++; diff --git a/drivers/media/platform/qcom/venus/venc.c b/drivers/media/platform/qcom/venus/venc.c index ce85962b6adc..32cff294582f 100644 --- a/drivers/media/platform/qcom/venus/venc.c +++ b/drivers/media/platform/qcom/venus/venc.c @@ -651,6 +651,8 @@ static int venc_set_properties(struct venus_inst *inst) struct hfi_framerate frate; struct hfi_bitrate brate; struct hfi_idr_period idrp; + struct hfi_quantization quant; + struct hfi_quantization_range quant_range; u32 ptype, rate_control, bitrate, profile = 0, level = 0; int ret; @@ -770,6 +772,23 @@ static int venc_set_properties(struct venus_inst *inst) if (ret) return ret; + ptype = HFI_PROPERTY_PARAM_VENC_SESSION_QP; + quant.qp_i = ctr->h264_i_qp; + quant.qp_p = ctr->h264_p_qp; + quant.qp_b = ctr->h264_b_qp; + quant.layer_id = 0; + ret = hfi_session_set_property(inst, ptype, &quant); + if (ret) + return ret; + + ptype = HFI_PROPERTY_PARAM_VENC_SESSION_QP_RANGE; + quant_range.min_qp = ctr->h264_min_qp; + quant_range.max_qp = ctr->h264_max_qp; + quant_range.layer_id = 0; + ret = hfi_session_set_property(inst, ptype, &quant_range); + if (ret) + return ret; + if (inst->fmt_cap->pixfmt == V4L2_PIX_FMT_H264) { profile = venc_v4l2_to_hfi(V4L2_CID_MPEG_VIDEO_H264_PROFILE, ctr->profile.h264); @@ -1074,7 +1093,7 @@ static int m2m_queue_init(void *priv, struct vb2_queue *src_vq, int ret; src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; - src_vq->io_modes = VB2_MMAP | VB2_DMABUF; + src_vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF; src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; src_vq->ops = &venc_vb2_ops; src_vq->mem_ops = &vb2_dma_sg_memops; @@ -1090,7 +1109,7 @@ static int m2m_queue_init(void *priv, struct vb2_queue *src_vq, return ret; dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; - dst_vq->io_modes = VB2_MMAP | VB2_DMABUF; + dst_vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF; dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; dst_vq->ops = &venc_vb2_ops; dst_vq->mem_ops = &vb2_dma_sg_memops; diff --git a/drivers/media/platform/qcom/venus/venc_ctrls.c b/drivers/media/platform/qcom/venus/venc_ctrls.c index 459101728d26..ac1e1d26f341 100644 --- a/drivers/media/platform/qcom/venus/venc_ctrls.c +++ b/drivers/media/platform/qcom/venus/venc_ctrls.c @@ -79,7 +79,10 @@ static int venc_op_s_ctrl(struct v4l2_ctrl *ctrl) { struct venus_inst *inst = ctrl_to_inst(ctrl); struct venc_controls *ctr = &inst->controls.enc; + struct hfi_enable en = { .enable = 1 }; + struct hfi_bitrate brate; u32 bframes; + u32 ptype; int ret; switch (ctrl->id) { @@ -88,6 +91,19 @@ static int venc_op_s_ctrl(struct v4l2_ctrl *ctrl) break; case V4L2_CID_MPEG_VIDEO_BITRATE: ctr->bitrate = ctrl->val; + mutex_lock(&inst->lock); + if (inst->streamon_out && inst->streamon_cap) { + ptype = HFI_PROPERTY_CONFIG_VENC_TARGET_BITRATE; + brate.bitrate = ctr->bitrate; + brate.layer_id = 0; + + ret = hfi_session_set_property(inst, ptype, &brate); + if (ret) { + mutex_unlock(&inst->lock); + return ret; + } + } + mutex_unlock(&inst->lock); break; case V4L2_CID_MPEG_VIDEO_BITRATE_PEAK: ctr->bitrate_peak = ctrl->val; @@ -173,6 +189,19 @@ static int venc_op_s_ctrl(struct v4l2_ctrl *ctrl) ctr->num_b_frames = bframes; break; + case V4L2_CID_MPEG_VIDEO_FORCE_KEY_FRAME: + mutex_lock(&inst->lock); + if (inst->streamon_out && inst->streamon_cap) { + ptype = HFI_PROPERTY_CONFIG_VENC_REQUEST_SYNC_FRAME; + ret = hfi_session_set_property(inst, ptype, &en); + + if (ret) { + mutex_unlock(&inst->lock); + return ret; + } + } + mutex_unlock(&inst->lock); + break; default: return -EINVAL; } @@ -188,7 +217,7 @@ int venc_ctrl_init(struct venus_inst *inst) { int ret; - ret = v4l2_ctrl_handler_init(&inst->ctrl_handler, 27); + ret = v4l2_ctrl_handler_init(&inst->ctrl_handler, 28); if (ret) return ret; @@ -295,7 +324,7 @@ int venc_ctrl_init(struct venus_inst *inst) 0, INTRA_REFRESH_MBS_MAX, 1, 0); v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops, - V4L2_CID_MPEG_VIDEO_GOP_SIZE, 0, (1 << 16) - 1, 1, 12); + V4L2_CID_MPEG_VIDEO_GOP_SIZE, 0, (1 << 16) - 1, 1, 30); v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops, V4L2_CID_MPEG_VIDEO_VPX_MIN_QP, 1, 128, 1, 1); @@ -309,6 +338,9 @@ int venc_ctrl_init(struct venus_inst *inst) v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops, V4L2_CID_MPEG_VIDEO_H264_I_PERIOD, 0, (1 << 16) - 1, 1, 0); + v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_FORCE_KEY_FRAME, 0, 0, 0, 0); + ret = inst->ctrl_handler.error; if (ret) goto err; diff --git a/drivers/media/platform/rcar-vin/rcar-core.c b/drivers/media/platform/rcar-vin/rcar-core.c index f476b2f1eb35..f0719ce24b97 100644 --- a/drivers/media/platform/rcar-vin/rcar-core.c +++ b/drivers/media/platform/rcar-vin/rcar-core.c @@ -1088,6 +1088,50 @@ static const struct rvin_info rcar_info_r8a77970 = { .routes = rcar_info_r8a77970_routes, }; +static const struct rvin_group_route rcar_info_r8a77980_routes[] = { + { .csi = RVIN_CSI40, .channel = 0, .vin = 0, .mask = BIT(0) | BIT(3) }, + { .csi = RVIN_CSI40, .channel = 1, .vin = 0, .mask = BIT(2) }, + { .csi = RVIN_CSI40, .channel = 0, .vin = 1, .mask = BIT(2) }, + { .csi = RVIN_CSI40, .channel = 1, .vin = 1, .mask = BIT(1) | BIT(3) }, + { .csi = RVIN_CSI40, .channel = 0, .vin = 2, .mask = BIT(1) }, + { .csi = RVIN_CSI40, .channel = 2, .vin = 2, .mask = BIT(3) }, + { .csi = RVIN_CSI40, .channel = 1, .vin = 3, .mask = BIT(0) }, + { .csi = RVIN_CSI40, .channel = 3, .vin = 3, .mask = BIT(3) }, + { .csi = RVIN_CSI41, .channel = 0, .vin = 4, .mask = BIT(0) | BIT(3) }, + { .csi = RVIN_CSI41, .channel = 1, .vin = 4, .mask = BIT(2) }, + { .csi = RVIN_CSI41, .channel = 0, .vin = 5, .mask = BIT(2) }, + { .csi = RVIN_CSI41, .channel = 1, .vin = 5, .mask = BIT(1) | BIT(3) }, + { .csi = RVIN_CSI41, .channel = 0, .vin = 6, .mask = BIT(1) }, + { .csi = RVIN_CSI41, .channel = 2, .vin = 6, .mask = BIT(3) }, + { .csi = RVIN_CSI41, .channel = 1, .vin = 7, .mask = BIT(0) }, + { .csi = RVIN_CSI41, .channel = 3, .vin = 7, .mask = BIT(3) }, + { /* Sentinel */ } +}; + +static const struct rvin_info rcar_info_r8a77980 = { + .model = RCAR_GEN3, + .use_mc = true, + .max_width = 4096, + .max_height = 4096, + .routes = rcar_info_r8a77980_routes, +}; + +static const struct rvin_group_route rcar_info_r8a77990_routes[] = { + { .csi = RVIN_CSI40, .channel = 0, .vin = 4, .mask = BIT(0) | BIT(3) }, + { .csi = RVIN_CSI40, .channel = 0, .vin = 5, .mask = BIT(2) }, + { .csi = RVIN_CSI40, .channel = 1, .vin = 4, .mask = BIT(2) }, + { .csi = RVIN_CSI40, .channel = 1, .vin = 5, .mask = BIT(1) | BIT(3) }, + { /* Sentinel */ } +}; + +static const struct rvin_info rcar_info_r8a77990 = { + .model = RCAR_GEN3, + .use_mc = true, + .max_width = 4096, + .max_height = 4096, + .routes = rcar_info_r8a77990_routes, +}; + static const struct rvin_group_route rcar_info_r8a77995_routes[] = { { /* Sentinel */ } }; @@ -1146,6 +1190,14 @@ static const struct of_device_id rvin_of_id_table[] = { .data = &rcar_info_r8a77970, }, { + .compatible = "renesas,vin-r8a77980", + .data = &rcar_info_r8a77980, + }, + { + .compatible = "renesas,vin-r8a77990", + .data = &rcar_info_r8a77990, + }, + { .compatible = "renesas,vin-r8a77995", .data = &rcar_info_r8a77995, }, diff --git a/drivers/media/platform/rcar-vin/rcar-csi2.c b/drivers/media/platform/rcar-vin/rcar-csi2.c index b0044a08e71e..6d356f5a9456 100644 --- a/drivers/media/platform/rcar-vin/rcar-csi2.c +++ b/drivers/media/platform/rcar-vin/rcar-csi2.c @@ -152,37 +152,37 @@ static const struct rcsi2_mbps_reg phtw_mbps_h3_v3h_m3n[] = { }; static const struct rcsi2_mbps_reg phtw_mbps_v3m_e3[] = { - { .mbps = 80, .reg = 0x00 }, - { .mbps = 90, .reg = 0x20 }, - { .mbps = 100, .reg = 0x40 }, - { .mbps = 110, .reg = 0x02 }, - { .mbps = 130, .reg = 0x22 }, - { .mbps = 140, .reg = 0x42 }, - { .mbps = 150, .reg = 0x04 }, - { .mbps = 170, .reg = 0x24 }, - { .mbps = 180, .reg = 0x44 }, - { .mbps = 200, .reg = 0x06 }, - { .mbps = 220, .reg = 0x26 }, - { .mbps = 240, .reg = 0x46 }, - { .mbps = 250, .reg = 0x08 }, - { .mbps = 270, .reg = 0x28 }, - { .mbps = 300, .reg = 0x0a }, - { .mbps = 330, .reg = 0x2a }, - { .mbps = 360, .reg = 0x4a }, - { .mbps = 400, .reg = 0x0c }, - { .mbps = 450, .reg = 0x2c }, - { .mbps = 500, .reg = 0x0e }, - { .mbps = 550, .reg = 0x2e }, - { .mbps = 600, .reg = 0x10 }, - { .mbps = 650, .reg = 0x30 }, - { .mbps = 700, .reg = 0x12 }, - { .mbps = 750, .reg = 0x32 }, - { .mbps = 800, .reg = 0x52 }, - { .mbps = 850, .reg = 0x72 }, - { .mbps = 900, .reg = 0x14 }, - { .mbps = 950, .reg = 0x34 }, - { .mbps = 1000, .reg = 0x54 }, - { .mbps = 1050, .reg = 0x74 }, + { .mbps = 89, .reg = 0x00 }, + { .mbps = 99, .reg = 0x20 }, + { .mbps = 109, .reg = 0x40 }, + { .mbps = 129, .reg = 0x02 }, + { .mbps = 139, .reg = 0x22 }, + { .mbps = 149, .reg = 0x42 }, + { .mbps = 169, .reg = 0x04 }, + { .mbps = 179, .reg = 0x24 }, + { .mbps = 199, .reg = 0x44 }, + { .mbps = 219, .reg = 0x06 }, + { .mbps = 239, .reg = 0x26 }, + { .mbps = 249, .reg = 0x46 }, + { .mbps = 269, .reg = 0x08 }, + { .mbps = 299, .reg = 0x28 }, + { .mbps = 329, .reg = 0x0a }, + { .mbps = 359, .reg = 0x2a }, + { .mbps = 399, .reg = 0x4a }, + { .mbps = 449, .reg = 0x0c }, + { .mbps = 499, .reg = 0x2c }, + { .mbps = 549, .reg = 0x0e }, + { .mbps = 599, .reg = 0x2e }, + { .mbps = 649, .reg = 0x10 }, + { .mbps = 699, .reg = 0x30 }, + { .mbps = 749, .reg = 0x12 }, + { .mbps = 799, .reg = 0x32 }, + { .mbps = 849, .reg = 0x52 }, + { .mbps = 899, .reg = 0x72 }, + { .mbps = 949, .reg = 0x14 }, + { .mbps = 999, .reg = 0x34 }, + { .mbps = 1049, .reg = 0x54 }, + { .mbps = 1099, .reg = 0x74 }, { .mbps = 1125, .reg = 0x16 }, { /* sentinel */ }, }; @@ -342,6 +342,7 @@ struct rcar_csi2_info { int (*confirm_start)(struct rcar_csi2 *priv); const struct rcsi2_mbps_reg *hsfreqrange; unsigned int csi0clkfreqrange; + unsigned int num_channels; bool clear_ulps; }; @@ -476,13 +477,14 @@ static int rcsi2_start(struct rcar_csi2 *priv) format = rcsi2_code_to_fmt(priv->mf.code); /* - * Enable all Virtual Channels. + * Enable all supported CSI-2 channels with virtual channel and + * data type matching. * * NOTE: It's not possible to get individual datatype for each * source virtual channel. Once this is possible in V4L2 * it should be used here. */ - for (i = 0; i < 4; i++) { + for (i = 0; i < priv->info->num_channels; i++) { u32 vcdt_part; vcdt_part = VCDT_SEL_VC(i) | VCDT_VCDTN_EN | VCDT_SEL_DTN_ON | @@ -511,7 +513,8 @@ static int rcsi2_start(struct rcar_csi2 *priv) rcsi2_write(priv, FLD_REG, FLD_FLD_NUM(2) | FLD_FLD_EN4 | FLD_FLD_EN3 | FLD_FLD_EN2 | FLD_FLD_EN); rcsi2_write(priv, VCDT_REG, vcdt); - rcsi2_write(priv, VCDT2_REG, vcdt2); + if (vcdt2) + rcsi2_write(priv, VCDT2_REG, vcdt2); /* Lanes are zero indexed. */ rcsi2_write(priv, LSWAP_REG, LSWAP_L0SEL(priv->lane_swap[0] - 1) | @@ -940,27 +943,45 @@ static const struct rcar_csi2_info rcar_csi2_info_r8a7795 = { .init_phtw = rcsi2_init_phtw_h3_v3h_m3n, .hsfreqrange = hsfreqrange_h3_v3h_m3n, .csi0clkfreqrange = 0x20, + .num_channels = 4, .clear_ulps = true, }; static const struct rcar_csi2_info rcar_csi2_info_r8a7795es1 = { .hsfreqrange = hsfreqrange_m3w_h3es1, + .num_channels = 4, }; static const struct rcar_csi2_info rcar_csi2_info_r8a7796 = { .hsfreqrange = hsfreqrange_m3w_h3es1, + .num_channels = 4, }; static const struct rcar_csi2_info rcar_csi2_info_r8a77965 = { .init_phtw = rcsi2_init_phtw_h3_v3h_m3n, .hsfreqrange = hsfreqrange_h3_v3h_m3n, .csi0clkfreqrange = 0x20, + .num_channels = 4, .clear_ulps = true, }; static const struct rcar_csi2_info rcar_csi2_info_r8a77970 = { .init_phtw = rcsi2_init_phtw_v3m_e3, .confirm_start = rcsi2_confirm_start_v3m_e3, + .num_channels = 4, +}; + +static const struct rcar_csi2_info rcar_csi2_info_r8a77980 = { + .init_phtw = rcsi2_init_phtw_h3_v3h_m3n, + .hsfreqrange = hsfreqrange_h3_v3h_m3n, + .csi0clkfreqrange = 0x20, + .clear_ulps = true, +}; + +static const struct rcar_csi2_info rcar_csi2_info_r8a77990 = { + .init_phtw = rcsi2_init_phtw_v3m_e3, + .confirm_start = rcsi2_confirm_start_v3m_e3, + .num_channels = 2, }; static const struct of_device_id rcar_csi2_of_table[] = { @@ -980,6 +1001,14 @@ static const struct of_device_id rcar_csi2_of_table[] = { .compatible = "renesas,r8a77970-csi2", .data = &rcar_csi2_info_r8a77970, }, + { + .compatible = "renesas,r8a77980-csi2", + .data = &rcar_csi2_info_r8a77980, + }, + { + .compatible = "renesas,r8a77990-csi2", + .data = &rcar_csi2_info_r8a77990, + }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, rcar_csi2_of_table); diff --git a/drivers/media/platform/rcar-vin/rcar-v4l2.c b/drivers/media/platform/rcar-vin/rcar-v4l2.c index dc77682b4785..7a2851790b91 100644 --- a/drivers/media/platform/rcar-vin/rcar-v4l2.c +++ b/drivers/media/platform/rcar-vin/rcar-v4l2.c @@ -404,16 +404,16 @@ static int rvin_s_selection(struct file *file, void *fh, return 0; } -static int rvin_cropcap(struct file *file, void *priv, - struct v4l2_cropcap *crop) +static int rvin_g_pixelaspect(struct file *file, void *priv, + int type, struct v4l2_fract *f) { struct rvin_dev *vin = video_drvdata(file); struct v4l2_subdev *sd = vin_to_source(vin); - if (crop->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + if (type != V4L2_BUF_TYPE_VIDEO_CAPTURE) return -EINVAL; - return v4l2_subdev_call(sd, video, g_pixelaspect, &crop->pixelaspect); + return v4l2_subdev_call(sd, video, g_pixelaspect, f); } static int rvin_enum_input(struct file *file, void *priv, @@ -620,7 +620,7 @@ static const struct v4l2_ioctl_ops rvin_ioctl_ops = { .vidioc_g_selection = rvin_g_selection, .vidioc_s_selection = rvin_s_selection, - .vidioc_cropcap = rvin_cropcap, + .vidioc_g_pixelaspect = rvin_g_pixelaspect, .vidioc_enum_input = rvin_enum_input, .vidioc_g_input = rvin_g_input, diff --git a/drivers/media/platform/rockchip/rga/rga.c b/drivers/media/platform/rockchip/rga/rga.c index 9cc9db083870..5c653287185f 100644 --- a/drivers/media/platform/rockchip/rga/rga.c +++ b/drivers/media/platform/rockchip/rga/rga.c @@ -97,7 +97,7 @@ static irqreturn_t rga_isr(int irq, void *prv) return IRQ_HANDLED; } -static struct v4l2_m2m_ops rga_m2m_ops = { +static const struct v4l2_m2m_ops rga_m2m_ops = { .device_run = device_run, }; @@ -700,7 +700,7 @@ static const struct v4l2_ioctl_ops rga_ioctl_ops = { .vidioc_s_selection = vidioc_s_selection, }; -static struct video_device rga_videodev = { +static const struct video_device rga_videodev = { .name = "rockchip-rga", .fops = &rga_fops, .ioctl_ops = &rga_ioctl_ops, diff --git a/drivers/media/platform/s5p-g2d/g2d.c b/drivers/media/platform/s5p-g2d/g2d.c index e901201b6fcc..57ab1d1085d1 100644 --- a/drivers/media/platform/s5p-g2d/g2d.c +++ b/drivers/media/platform/s5p-g2d/g2d.c @@ -89,7 +89,7 @@ static struct g2d_fmt *find_fmt(struct v4l2_format *f) static struct g2d_frame *get_frame(struct g2d_ctx *ctx, - enum v4l2_buf_type type) + enum v4l2_buf_type type) { switch (type) { case V4L2_BUF_TYPE_VIDEO_OUTPUT: @@ -408,51 +408,76 @@ static int vidioc_s_fmt(struct file *file, void *prv, struct v4l2_format *f) return 0; } -static int vidioc_cropcap(struct file *file, void *priv, - struct v4l2_cropcap *cr) -{ - struct g2d_ctx *ctx = priv; - struct g2d_frame *f; - - f = get_frame(ctx, cr->type); - if (IS_ERR(f)) - return PTR_ERR(f); - - cr->bounds.left = 0; - cr->bounds.top = 0; - cr->bounds.width = f->width; - cr->bounds.height = f->height; - cr->defrect = cr->bounds; - return 0; -} - -static int vidioc_g_crop(struct file *file, void *prv, struct v4l2_crop *cr) +static int vidioc_g_selection(struct file *file, void *prv, + struct v4l2_selection *s) { struct g2d_ctx *ctx = prv; struct g2d_frame *f; - f = get_frame(ctx, cr->type); + f = get_frame(ctx, s->type); if (IS_ERR(f)) return PTR_ERR(f); - cr->c.left = f->o_height; - cr->c.top = f->o_width; - cr->c.width = f->c_width; - cr->c.height = f->c_height; + switch (s->target) { + case V4L2_SEL_TGT_CROP: + case V4L2_SEL_TGT_CROP_DEFAULT: + case V4L2_SEL_TGT_CROP_BOUNDS: + if (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) + return -EINVAL; + break; + case V4L2_SEL_TGT_COMPOSE: + case V4L2_SEL_TGT_COMPOSE_DEFAULT: + case V4L2_SEL_TGT_COMPOSE_BOUNDS: + if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + break; + default: + return -EINVAL; + } + + switch (s->target) { + case V4L2_SEL_TGT_CROP: + case V4L2_SEL_TGT_COMPOSE: + s->r.left = f->o_height; + s->r.top = f->o_width; + s->r.width = f->c_width; + s->r.height = f->c_height; + break; + case V4L2_SEL_TGT_CROP_DEFAULT: + case V4L2_SEL_TGT_CROP_BOUNDS: + case V4L2_SEL_TGT_COMPOSE_DEFAULT: + case V4L2_SEL_TGT_COMPOSE_BOUNDS: + s->r.left = 0; + s->r.top = 0; + s->r.width = f->width; + s->r.height = f->height; + break; + default: + return -EINVAL; + } return 0; } -static int vidioc_try_crop(struct file *file, void *prv, const struct v4l2_crop *cr) +static int vidioc_try_selection(struct file *file, void *prv, + const struct v4l2_selection *s) { struct g2d_ctx *ctx = prv; struct g2d_dev *dev = ctx->dev; struct g2d_frame *f; - f = get_frame(ctx, cr->type); + f = get_frame(ctx, s->type); if (IS_ERR(f)) return PTR_ERR(f); - if (cr->c.top < 0 || cr->c.left < 0) { + if (s->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) { + if (s->target != V4L2_SEL_TGT_COMPOSE) + return -EINVAL; + } else if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) { + if (s->target != V4L2_SEL_TGT_CROP) + return -EINVAL; + } + + if (s->r.top < 0 || s->r.left < 0) { v4l2_err(&dev->v4l2_dev, "doesn't support negative values for top & left\n"); return -EINVAL; @@ -461,23 +486,24 @@ static int vidioc_try_crop(struct file *file, void *prv, const struct v4l2_crop return 0; } -static int vidioc_s_crop(struct file *file, void *prv, const struct v4l2_crop *cr) +static int vidioc_s_selection(struct file *file, void *prv, + struct v4l2_selection *s) { struct g2d_ctx *ctx = prv; struct g2d_frame *f; int ret; - ret = vidioc_try_crop(file, prv, cr); + ret = vidioc_try_selection(file, prv, s); if (ret) return ret; - f = get_frame(ctx, cr->type); + f = get_frame(ctx, s->type); if (IS_ERR(f)) return PTR_ERR(f); - f->c_width = cr->c.width; - f->c_height = cr->c.height; - f->o_width = cr->c.left; - f->o_height = cr->c.top; + f->c_width = s->r.width; + f->c_height = s->r.height; + f->o_width = s->r.left; + f->o_height = s->r.top; f->bottom = f->o_height + f->c_height; f->right = f->o_width + f->c_width; return 0; @@ -585,9 +611,8 @@ static const struct v4l2_ioctl_ops g2d_ioctl_ops = { .vidioc_streamon = v4l2_m2m_ioctl_streamon, .vidioc_streamoff = v4l2_m2m_ioctl_streamoff, - .vidioc_g_crop = vidioc_g_crop, - .vidioc_s_crop = vidioc_s_crop, - .vidioc_cropcap = vidioc_cropcap, + .vidioc_g_selection = vidioc_g_selection, + .vidioc_s_selection = vidioc_s_selection, }; static const struct video_device g2d_videodev = { @@ -680,6 +705,7 @@ static int g2d_probe(struct platform_device *pdev) goto unreg_v4l2_dev; } *vfd = g2d_videodev; + set_bit(V4L2_FL_QUIRK_INVERTED_CROP, &vfd->flags); vfd->lock = &dev->mutex; vfd->v4l2_dev = &dev->v4l2_dev; ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0); diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc.c b/drivers/media/platform/s5p-mfc/s5p_mfc.c index 927a1235408d..8a5ba3bec3af 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc.c +++ b/drivers/media/platform/s5p-mfc/s5p_mfc.c @@ -1342,6 +1342,7 @@ static int s5p_mfc_probe(struct platform_device *pdev) vfd->lock = &dev->mfc_mutex; vfd->v4l2_dev = &dev->v4l2_dev; vfd->vfl_dir = VFL_DIR_M2M; + set_bit(V4L2_FL_QUIRK_INVERTED_CROP, &vfd->flags); snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME); dev->vfd_dec = vfd; video_set_drvdata(vfd, dev); diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c b/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c index ece59ce1b149..f4c0e3a8f27d 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c @@ -773,19 +773,23 @@ static const struct v4l2_ctrl_ops s5p_mfc_dec_ctrl_ops = { .g_volatile_ctrl = s5p_mfc_dec_g_v_ctrl, }; -/* Get cropping information */ -static int vidioc_g_crop(struct file *file, void *priv, - struct v4l2_crop *cr) +/* Get compose information */ +static int vidioc_g_selection(struct file *file, void *priv, + struct v4l2_selection *s) { struct s5p_mfc_ctx *ctx = fh_to_ctx(priv); struct s5p_mfc_dev *dev = ctx->dev; u32 left, right, top, bottom; + u32 width, height; + + if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; if (ctx->state != MFCINST_HEAD_PARSED && ctx->state != MFCINST_RUNNING && ctx->state != MFCINST_FINISHING && ctx->state != MFCINST_FINISHED) { - mfc_err("Can not get crop information\n"); + mfc_err("Can not get compose information\n"); return -EINVAL; } if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_H264) { @@ -795,22 +799,33 @@ static int vidioc_g_crop(struct file *file, void *priv, top = s5p_mfc_hw_call(dev->mfc_ops, get_crop_info_v, ctx); bottom = top >> S5P_FIMV_SHARED_CROP_BOTTOM_SHIFT; top = top & S5P_FIMV_SHARED_CROP_TOP_MASK; - cr->c.left = left; - cr->c.top = top; - cr->c.width = ctx->img_width - left - right; - cr->c.height = ctx->img_height - top - bottom; - mfc_debug(2, "Cropping info [h264]: l=%d t=%d w=%d h=%d (r=%d b=%d fw=%d fh=%d\n", - left, top, cr->c.width, cr->c.height, right, bottom, + width = ctx->img_width - left - right; + height = ctx->img_height - top - bottom; + mfc_debug(2, "Composing info [h264]: l=%d t=%d w=%d h=%d (r=%d b=%d fw=%d fh=%d\n", + left, top, s->r.width, s->r.height, right, bottom, ctx->buf_width, ctx->buf_height); } else { - cr->c.left = 0; - cr->c.top = 0; - cr->c.width = ctx->img_width; - cr->c.height = ctx->img_height; - mfc_debug(2, "Cropping info: w=%d h=%d fw=%d fh=%d\n", - cr->c.width, cr->c.height, ctx->buf_width, + left = 0; + top = 0; + width = ctx->img_width; + height = ctx->img_height; + mfc_debug(2, "Composing info: w=%d h=%d fw=%d fh=%d\n", + s->r.width, s->r.height, ctx->buf_width, ctx->buf_height); } + + switch (s->target) { + case V4L2_SEL_TGT_COMPOSE: + case V4L2_SEL_TGT_COMPOSE_DEFAULT: + case V4L2_SEL_TGT_COMPOSE_BOUNDS: + s->r.left = left; + s->r.top = top; + s->r.width = width; + s->r.height = height; + break; + default: + return -EINVAL; + } return 0; } @@ -887,7 +902,7 @@ static const struct v4l2_ioctl_ops s5p_mfc_dec_ioctl_ops = { .vidioc_expbuf = vidioc_expbuf, .vidioc_streamon = vidioc_streamon, .vidioc_streamoff = vidioc_streamoff, - .vidioc_g_crop = vidioc_g_crop, + .vidioc_g_selection = vidioc_g_selection, .vidioc_decoder_cmd = vidioc_decoder_cmd, .vidioc_subscribe_event = vidioc_subscribe_event, .vidioc_unsubscribe_event = v4l2_event_unsubscribe, diff --git a/drivers/media/platform/seco-cec/Makefile b/drivers/media/platform/seco-cec/Makefile new file mode 100644 index 000000000000..a3f2c6bd3ac0 --- /dev/null +++ b/drivers/media/platform/seco-cec/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_VIDEO_SECO_CEC) += seco-cec.o diff --git a/drivers/media/platform/seco-cec/seco-cec.c b/drivers/media/platform/seco-cec/seco-cec.c new file mode 100644 index 000000000000..a425a10540c1 --- /dev/null +++ b/drivers/media/platform/seco-cec/seco-cec.c @@ -0,0 +1,796 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/* + * CEC driver for SECO X86 Boards + * + * Author: Ettore Chimenti <ek5.chimenti@gmail.com> + * Copyright (C) 2018, SECO SpA. + * Copyright (C) 2018, Aidilab Srl. + */ + +#include <linux/module.h> +#include <linux/acpi.h> +#include <linux/delay.h> +#include <linux/dmi.h> +#include <linux/gpio/consumer.h> +#include <linux/gpio.h> +#include <linux/interrupt.h> +#include <linux/pci.h> +#include <linux/platform_device.h> + +/* CEC Framework */ +#include <media/cec.h> + +#include "seco-cec.h" + +struct secocec_data { + struct device *dev; + struct platform_device *pdev; + struct cec_adapter *cec_adap; + struct cec_notifier *notifier; + struct rc_dev *ir; + char ir_input_phys[32]; + int irq; +}; + +#define smb_wr16(cmd, data) smb_word_op(CMD_WORD_DATA, SECOCEC_MICRO_ADDRESS, \ + cmd, data, SMBUS_WRITE, NULL) +#define smb_rd16(cmd, res) smb_word_op(CMD_WORD_DATA, SECOCEC_MICRO_ADDRESS, \ + cmd, 0, SMBUS_READ, res) + +static int smb_word_op(short data_format, u16 slave_addr, u8 cmd, u16 data, + u8 operation, u16 *result) +{ + unsigned int count; + short _data_format; + int status = 0; + + switch (data_format) { + case CMD_BYTE_DATA: + _data_format = BRA_SMB_CMD_BYTE_DATA; + break; + case CMD_WORD_DATA: + _data_format = BRA_SMB_CMD_WORD_DATA; + break; + default: + return -EINVAL; + } + + /* Active wait until ready */ + for (count = 0; count <= SMBTIMEOUT; ++count) { + if (!(inb(HSTS) & BRA_INUSE_STS)) + break; + udelay(SMB_POLL_UDELAY); + } + + if (count > SMBTIMEOUT) + /* Reset the lock instead of failing */ + outb(0xff, HSTS); + + outb(0x00, HCNT); + outb((u8)(slave_addr & 0xfe) | operation, XMIT_SLVA); + outb(cmd, HCMD); + inb(HCNT); + + if (operation == SMBUS_WRITE) { + outb((u8)data, HDAT0); + outb((u8)(data >> 8), HDAT1); + } + + outb(BRA_START + _data_format, HCNT); + + for (count = 0; count <= SMBTIMEOUT; count++) { + if (!(inb(HSTS) & BRA_HOST_BUSY)) + break; + udelay(SMB_POLL_UDELAY); + } + + if (count > SMBTIMEOUT) { + status = -EBUSY; + goto err; + } + + if (inb(HSTS) & BRA_HSTS_ERR_MASK) { + status = -EIO; + goto err; + } + + if (operation == SMBUS_READ) + *result = ((inb(HDAT0) & 0xff) + ((inb(HDAT1) & 0xff) << 8)); + +err: + outb(0xff, HSTS); + return status; +} + +static int secocec_adap_enable(struct cec_adapter *adap, bool enable) +{ + struct secocec_data *cec = cec_get_drvdata(adap); + struct device *dev = cec->dev; + u16 val = 0; + int status; + + if (enable) { + /* Clear the status register */ + status = smb_rd16(SECOCEC_STATUS_REG_1, &val); + if (status) + goto err; + + status = smb_wr16(SECOCEC_STATUS_REG_1, val); + if (status) + goto err; + + /* Enable the interrupts */ + status = smb_rd16(SECOCEC_ENABLE_REG_1, &val); + if (status) + goto err; + + status = smb_wr16(SECOCEC_ENABLE_REG_1, + val | SECOCEC_ENABLE_REG_1_CEC); + if (status) + goto err; + + dev_dbg(dev, "Device enabled"); + } else { + /* Clear the status register */ + status = smb_rd16(SECOCEC_STATUS_REG_1, &val); + status = smb_wr16(SECOCEC_STATUS_REG_1, val); + + /* Disable the interrupts */ + status = smb_rd16(SECOCEC_ENABLE_REG_1, &val); + status = smb_wr16(SECOCEC_ENABLE_REG_1, val & + ~SECOCEC_ENABLE_REG_1_CEC & + ~SECOCEC_ENABLE_REG_1_IR); + + dev_dbg(dev, "Device disabled"); + } + + return 0; +err: + return status; +} + +static int secocec_adap_log_addr(struct cec_adapter *adap, u8 logical_addr) +{ + u16 enable_val = 0; + int status; + + /* Disable device */ + status = smb_rd16(SECOCEC_ENABLE_REG_1, &enable_val); + if (status) + return status; + + status = smb_wr16(SECOCEC_ENABLE_REG_1, + enable_val & ~SECOCEC_ENABLE_REG_1_CEC); + if (status) + return status; + + /* Write logical address + * NOTE: CEC_LOG_ADDR_INVALID is mapped to the 'Unregistered' LA + */ + status = smb_wr16(SECOCEC_DEVICE_LA, logical_addr & 0xf); + if (status) + return status; + + /* Re-enable device */ + status = smb_wr16(SECOCEC_ENABLE_REG_1, + enable_val | SECOCEC_ENABLE_REG_1_CEC); + if (status) + return status; + + return 0; +} + +static int secocec_adap_transmit(struct cec_adapter *adap, u8 attempts, + u32 signal_free_time, struct cec_msg *msg) +{ + u16 payload_len, payload_id_len, destination, val = 0; + u8 *payload_msg; + int status; + u8 i; + + /* Device msg len already accounts for header */ + payload_id_len = msg->len - 1; + + /* Send data length */ + status = smb_wr16(SECOCEC_WRITE_DATA_LENGTH, payload_id_len); + if (status) + goto err; + + /* Send Operation ID if present */ + if (payload_id_len > 0) { + status = smb_wr16(SECOCEC_WRITE_OPERATION_ID, msg->msg[1]); + if (status) + goto err; + } + /* Send data if present */ + if (payload_id_len > 1) { + /* Only data; */ + payload_len = msg->len - 2; + payload_msg = &msg->msg[2]; + + /* Copy message into registers */ + for (i = 0; i < payload_len; i += 2) { + /* hi byte */ + val = payload_msg[i + 1] << 8; + + /* lo byte */ + val |= payload_msg[i]; + + status = smb_wr16(SECOCEC_WRITE_DATA_00 + i / 2, val); + if (status) + goto err; + } + } + /* Send msg source/destination and fire msg */ + destination = msg->msg[0]; + status = smb_wr16(SECOCEC_WRITE_BYTE0, destination); + if (status) + goto err; + + return 0; + +err: + return status; +} + +static void secocec_tx_done(struct cec_adapter *adap, u16 status_val) +{ + if (status_val & SECOCEC_STATUS_TX_ERROR_MASK) { + if (status_val & SECOCEC_STATUS_TX_NACK_ERROR) + cec_transmit_attempt_done(adap, CEC_TX_STATUS_NACK); + else + cec_transmit_attempt_done(adap, CEC_TX_STATUS_ERROR); + } else { + cec_transmit_attempt_done(adap, CEC_TX_STATUS_OK); + } + + /* Reset status reg */ + status_val = SECOCEC_STATUS_TX_ERROR_MASK | + SECOCEC_STATUS_MSG_SENT_MASK | + SECOCEC_STATUS_TX_NACK_ERROR; + smb_wr16(SECOCEC_STATUS, status_val); +} + +static void secocec_rx_done(struct cec_adapter *adap, u16 status_val) +{ + struct secocec_data *cec = cec_get_drvdata(adap); + struct device *dev = cec->dev; + struct cec_msg msg = { }; + bool flag_overflow = false; + u8 payload_len, i = 0; + u8 *payload_msg; + u16 val = 0; + int status; + + if (status_val & SECOCEC_STATUS_RX_OVERFLOW_MASK) { + /* NOTE: Untested, it also might not be necessary */ + dev_warn(dev, "Received more than 16 bytes. Discarding"); + flag_overflow = true; + } + + if (status_val & SECOCEC_STATUS_RX_ERROR_MASK) { + dev_warn(dev, "Message received with errors. Discarding"); + status = -EIO; + goto rxerr; + } + + /* Read message length */ + status = smb_rd16(SECOCEC_READ_DATA_LENGTH, &val); + if (status) + return; + + /* Device msg len already accounts for the header */ + msg.len = min(val + 1, CEC_MAX_MSG_SIZE); + + /* Read logical address */ + status = smb_rd16(SECOCEC_READ_BYTE0, &val); + if (status) + return; + + /* device stores source LA and destination */ + msg.msg[0] = val; + + /* Read operation ID */ + status = smb_rd16(SECOCEC_READ_OPERATION_ID, &val); + if (status) + return; + + msg.msg[1] = val; + + /* Read data if present */ + if (msg.len > 1) { + payload_len = msg.len - 2; + payload_msg = &msg.msg[2]; + + /* device stores 2 bytes in every 16-bit val */ + for (i = 0; i < payload_len; i += 2) { + status = smb_rd16(SECOCEC_READ_DATA_00 + i / 2, &val); + if (status) + return; + + /* low byte, skipping header */ + payload_msg[i] = val & 0x00ff; + + /* hi byte */ + payload_msg[i + 1] = (val & 0xff00) >> 8; + } + } + + cec_received_msg(cec->cec_adap, &msg); + + /* Reset status reg */ + status_val = SECOCEC_STATUS_MSG_RECEIVED_MASK; + if (flag_overflow) + status_val |= SECOCEC_STATUS_RX_OVERFLOW_MASK; + + status = smb_wr16(SECOCEC_STATUS, status_val); + + return; + +rxerr: + /* Reset error reg */ + status_val = SECOCEC_STATUS_MSG_RECEIVED_MASK | + SECOCEC_STATUS_RX_ERROR_MASK; + if (flag_overflow) + status_val |= SECOCEC_STATUS_RX_OVERFLOW_MASK; + smb_wr16(SECOCEC_STATUS, status_val); +} + +static const struct cec_adap_ops secocec_cec_adap_ops = { + /* Low-level callbacks */ + .adap_enable = secocec_adap_enable, + .adap_log_addr = secocec_adap_log_addr, + .adap_transmit = secocec_adap_transmit, +}; + +#ifdef CONFIG_VIDEO_SECO_RC +static int secocec_ir_probe(void *priv) +{ + struct secocec_data *cec = priv; + struct device *dev = cec->dev; + int status; + u16 val; + + /* Prepare the RC input device */ + cec->ir = devm_rc_allocate_device(dev, RC_DRIVER_SCANCODE); + if (!cec->ir) + return -ENOMEM; + + snprintf(cec->ir_input_phys, sizeof(cec->ir_input_phys), + "%s/input0", dev_name(dev)); + + cec->ir->device_name = dev_name(dev); + cec->ir->input_phys = cec->ir_input_phys; + cec->ir->input_id.bustype = BUS_HOST; + cec->ir->input_id.vendor = 0; + cec->ir->input_id.product = 0; + cec->ir->input_id.version = 1; + cec->ir->driver_name = SECOCEC_DEV_NAME; + cec->ir->allowed_protocols = RC_PROTO_BIT_RC5; + cec->ir->priv = cec; + cec->ir->map_name = RC_MAP_HAUPPAUGE; + cec->ir->timeout = MS_TO_NS(100); + + /* Clear the status register */ + status = smb_rd16(SECOCEC_STATUS_REG_1, &val); + if (status != 0) + goto err; + + status = smb_wr16(SECOCEC_STATUS_REG_1, val); + if (status != 0) + goto err; + + /* Enable the interrupts */ + status = smb_rd16(SECOCEC_ENABLE_REG_1, &val); + if (status != 0) + goto err; + + status = smb_wr16(SECOCEC_ENABLE_REG_1, + val | SECOCEC_ENABLE_REG_1_IR); + if (status != 0) + goto err; + + dev_dbg(dev, "IR enabled"); + + status = devm_rc_register_device(dev, cec->ir); + + if (status) { + dev_err(dev, "Failed to prepare input device"); + cec->ir = NULL; + goto err; + } + + return 0; + +err: + smb_rd16(SECOCEC_ENABLE_REG_1, &val); + + smb_wr16(SECOCEC_ENABLE_REG_1, + val & ~SECOCEC_ENABLE_REG_1_IR); + + dev_dbg(dev, "IR disabled"); + return status; +} + +static int secocec_ir_rx(struct secocec_data *priv) +{ + struct secocec_data *cec = priv; + struct device *dev = cec->dev; + u16 val, status, key, addr, toggle; + + if (!cec->ir) + return -ENODEV; + + status = smb_rd16(SECOCEC_IR_READ_DATA, &val); + if (status != 0) + goto err; + + key = val & SECOCEC_IR_COMMAND_MASK; + addr = (val & SECOCEC_IR_ADDRESS_MASK) >> SECOCEC_IR_ADDRESS_SHL; + toggle = (val & SECOCEC_IR_TOGGLE_MASK) >> SECOCEC_IR_TOGGLE_SHL; + + rc_keydown(cec->ir, RC_PROTO_RC5, RC_SCANCODE_RC5(addr, key), toggle); + + dev_dbg(dev, "IR key pressed: 0x%02x addr 0x%02x toggle 0x%02x", key, + addr, toggle); + + return 0; + +err: + dev_err(dev, "IR Receive message failed (%d)", status); + return -EIO; +} +#else +static void secocec_ir_rx(struct secocec_data *priv) +{ +} + +static int secocec_ir_probe(void *priv) +{ + return 0; +} +#endif + +static irqreturn_t secocec_irq_handler(int irq, void *priv) +{ + struct secocec_data *cec = priv; + struct device *dev = cec->dev; + u16 status_val, cec_val, val = 0; + int status; + + /* Read status register */ + status = smb_rd16(SECOCEC_STATUS_REG_1, &status_val); + if (status) + goto err; + + if (status_val & SECOCEC_STATUS_REG_1_CEC) { + /* Read CEC status register */ + status = smb_rd16(SECOCEC_STATUS, &cec_val); + if (status) + goto err; + + if (cec_val & SECOCEC_STATUS_MSG_RECEIVED_MASK) + secocec_rx_done(cec->cec_adap, cec_val); + + if (cec_val & SECOCEC_STATUS_MSG_SENT_MASK) + secocec_tx_done(cec->cec_adap, cec_val); + + if ((~cec_val & SECOCEC_STATUS_MSG_SENT_MASK) && + (~cec_val & SECOCEC_STATUS_MSG_RECEIVED_MASK)) + dev_warn_once(dev, + "Message not received or sent, but interrupt fired"); + + val = SECOCEC_STATUS_REG_1_CEC; + } + + if (status_val & SECOCEC_STATUS_REG_1_IR) { + val |= SECOCEC_STATUS_REG_1_IR; + + secocec_ir_rx(cec); + } + + /* Reset status register */ + status = smb_wr16(SECOCEC_STATUS_REG_1, val); + if (status) + goto err; + + return IRQ_HANDLED; + +err: + dev_err_once(dev, "IRQ: R/W SMBus operation failed (%d)", status); + + /* Reset status register */ + val = SECOCEC_STATUS_REG_1_CEC | SECOCEC_STATUS_REG_1_IR; + smb_wr16(SECOCEC_STATUS_REG_1, val); + + return IRQ_HANDLED; +} + +struct cec_dmi_match { + char *sys_vendor; + char *product_name; + char *devname; + char *conn; +}; + +static const struct cec_dmi_match secocec_dmi_match_table[] = { + /* UDOO X86 */ + { "SECO", "UDOO x86", "0000:00:02.0", "Port B" }, +}; + +static int secocec_cec_get_notifier(struct cec_notifier **notify) +{ + int i; + + for (i = 0 ; i < ARRAY_SIZE(secocec_dmi_match_table) ; ++i) { + const struct cec_dmi_match *m = &secocec_dmi_match_table[i]; + + if (dmi_match(DMI_SYS_VENDOR, m->sys_vendor) && + dmi_match(DMI_PRODUCT_NAME, m->product_name)) { + struct device *d; + + /* Find the device, bail out if not yet registered */ + d = bus_find_device_by_name(&pci_bus_type, NULL, + m->devname); + if (!d) + return -EPROBE_DEFER; + + *notify = cec_notifier_get_conn(d, m->conn); + + return 0; + } + } + + return -EINVAL; +} + +static int secocec_acpi_probe(struct secocec_data *sdev) +{ + struct device *dev = sdev->dev; + struct gpio_desc *gpio; + int irq = 0; + + gpio = devm_gpiod_get(dev, NULL, GPIOF_IN); + if (IS_ERR(gpio)) { + dev_err(dev, "Cannot request interrupt gpio"); + return PTR_ERR(gpio); + } + + irq = gpiod_to_irq(gpio); + if (irq < 0) { + dev_err(dev, "Cannot find valid irq"); + return -ENODEV; + } + dev_dbg(dev, "irq-gpio is bound to IRQ %d", irq); + + sdev->irq = irq; + + return 0; +} + +static int secocec_probe(struct platform_device *pdev) +{ + struct secocec_data *secocec; + struct device *dev = &pdev->dev; + int ret; + u16 val; + + secocec = devm_kzalloc(dev, sizeof(*secocec), GFP_KERNEL); + if (!secocec) + return -ENOMEM; + + dev_set_drvdata(dev, secocec); + + /* Request SMBus regions */ + if (!request_muxed_region(BRA_SMB_BASE_ADDR, 7, "CEC00001")) { + dev_err(dev, "Request memory region failed"); + return -ENXIO; + } + + secocec->pdev = pdev; + secocec->dev = dev; + + if (!has_acpi_companion(dev)) { + dev_dbg(dev, "Cannot find any ACPI companion"); + ret = -ENODEV; + goto err; + } + + ret = secocec_acpi_probe(secocec); + if (ret) { + dev_err(dev, "Cannot assign gpio to IRQ"); + ret = -ENODEV; + goto err; + } + + /* Firmware version check */ + ret = smb_rd16(SECOCEC_VERSION, &val); + if (ret) { + dev_err(dev, "Cannot check fw version"); + goto err; + } + if (val < SECOCEC_LATEST_FW) { + dev_err(dev, "CEC Firmware not supported (v.%04x). Use ver > v.%04x", + val, SECOCEC_LATEST_FW); + ret = -EINVAL; + goto err; + } + + ret = secocec_cec_get_notifier(&secocec->notifier); + if (ret) { + dev_err(dev, "no CEC notifier available\n"); + goto err; + } + + ret = devm_request_threaded_irq(dev, + secocec->irq, + NULL, + secocec_irq_handler, + IRQF_TRIGGER_RISING | IRQF_ONESHOT, + dev_name(&pdev->dev), secocec); + + if (ret) { + dev_err(dev, "Cannot request IRQ %d", secocec->irq); + ret = -EIO; + goto err; + } + + /* Allocate CEC adapter */ + secocec->cec_adap = cec_allocate_adapter(&secocec_cec_adap_ops, + secocec, + dev_name(dev), + CEC_CAP_DEFAULTS, + SECOCEC_MAX_ADDRS); + + if (IS_ERR(secocec->cec_adap)) { + ret = PTR_ERR(secocec->cec_adap); + goto err; + } + + ret = cec_register_adapter(secocec->cec_adap, dev); + if (ret) + goto err_delete_adapter; + + if (secocec->notifier) + cec_register_cec_notifier(secocec->cec_adap, secocec->notifier); + + ret = secocec_ir_probe(secocec); + if (ret) + goto err_delete_adapter; + + platform_set_drvdata(pdev, secocec); + + dev_dbg(dev, "Device registered"); + + return ret; + +err_delete_adapter: + cec_delete_adapter(secocec->cec_adap); +err: + dev_err(dev, "%s device probe failed\n", dev_name(dev)); + + return ret; +} + +static int secocec_remove(struct platform_device *pdev) +{ + struct secocec_data *secocec = platform_get_drvdata(pdev); + u16 val; + + if (secocec->ir) { + smb_rd16(SECOCEC_ENABLE_REG_1, &val); + + smb_wr16(SECOCEC_ENABLE_REG_1, val & ~SECOCEC_ENABLE_REG_1_IR); + + dev_dbg(&pdev->dev, "IR disabled"); + } + cec_unregister_adapter(secocec->cec_adap); + + if (secocec->notifier) + cec_notifier_put(secocec->notifier); + + release_region(BRA_SMB_BASE_ADDR, 7); + + dev_dbg(&pdev->dev, "CEC device removed"); + + return 0; +} + +#ifdef CONFIG_PM_SLEEP +static int secocec_suspend(struct device *dev) +{ + int status; + u16 val; + + dev_dbg(dev, "Device going to suspend, disabling"); + + /* Clear the status register */ + status = smb_rd16(SECOCEC_STATUS_REG_1, &val); + if (status) + goto err; + + status = smb_wr16(SECOCEC_STATUS_REG_1, val); + if (status) + goto err; + + /* Disable the interrupts */ + status = smb_rd16(SECOCEC_ENABLE_REG_1, &val); + if (status) + goto err; + + status = smb_wr16(SECOCEC_ENABLE_REG_1, val & + ~SECOCEC_ENABLE_REG_1_CEC & ~SECOCEC_ENABLE_REG_1_IR); + if (status) + goto err; + + return 0; + +err: + dev_err(dev, "Suspend failed (err: %d)", status); + return status; +} + +static int secocec_resume(struct device *dev) +{ + int status; + u16 val; + + dev_dbg(dev, "Resuming device from suspend"); + + /* Clear the status register */ + status = smb_rd16(SECOCEC_STATUS_REG_1, &val); + if (status) + goto err; + + status = smb_wr16(SECOCEC_STATUS_REG_1, val); + if (status) + goto err; + + /* Enable the interrupts */ + status = smb_rd16(SECOCEC_ENABLE_REG_1, &val); + if (status) + goto err; + + status = smb_wr16(SECOCEC_ENABLE_REG_1, val | SECOCEC_ENABLE_REG_1_CEC); + if (status) + goto err; + + dev_dbg(dev, "Device resumed from suspend"); + + return 0; + +err: + dev_err(dev, "Resume failed (err: %d)", status); + return status; +} + +static SIMPLE_DEV_PM_OPS(secocec_pm_ops, secocec_suspend, secocec_resume); +#define SECOCEC_PM_OPS (&secocec_pm_ops) +#else +#define SECOCEC_PM_OPS NULL +#endif + +#ifdef CONFIG_ACPI +static const struct acpi_device_id secocec_acpi_match[] = { + {"CEC00001", 0}, + {}, +}; + +MODULE_DEVICE_TABLE(acpi, secocec_acpi_match); +#endif + +static struct platform_driver secocec_driver = { + .driver = { + .name = SECOCEC_DEV_NAME, + .acpi_match_table = ACPI_PTR(secocec_acpi_match), + .pm = SECOCEC_PM_OPS, + }, + .probe = secocec_probe, + .remove = secocec_remove, +}; + +module_platform_driver(secocec_driver); + +MODULE_DESCRIPTION("SECO CEC X86 Driver"); +MODULE_AUTHOR("Ettore Chimenti <ek5.chimenti@gmail.com>"); +MODULE_LICENSE("Dual BSD/GPL"); diff --git a/drivers/media/platform/seco-cec/seco-cec.h b/drivers/media/platform/seco-cec/seco-cec.h new file mode 100644 index 000000000000..e632c4a2a044 --- /dev/null +++ b/drivers/media/platform/seco-cec/seco-cec.h @@ -0,0 +1,141 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ +/* + * SECO X86 Boards CEC register defines + * + * Author: Ettore Chimenti <ek5.chimenti@gmail.com> + * Copyright (C) 2018, SECO Spa. + * Copyright (C) 2018, Aidilab Srl. + */ + +#ifndef __SECO_CEC_H__ +#define __SECO_CEC_H__ + +#define SECOCEC_MAX_ADDRS 1 +#define SECOCEC_DEV_NAME "secocec" +#define SECOCEC_LATEST_FW 0x0f0b + +#define SMBTIMEOUT 0xfff +#define SMB_POLL_UDELAY 10 + +#define SMBUS_WRITE 0 +#define SMBUS_READ 1 + +#define CMD_BYTE_DATA 0 +#define CMD_WORD_DATA 1 + +/* + * SMBus definitons for Braswell + */ + +#define BRA_DONE_STATUS BIT(7) +#define BRA_INUSE_STS BIT(6) +#define BRA_FAILED_OP BIT(4) +#define BRA_BUS_ERR BIT(3) +#define BRA_DEV_ERR BIT(2) +#define BRA_INTR BIT(1) +#define BRA_HOST_BUSY BIT(0) +#define BRA_HSTS_ERR_MASK (BRA_FAILED_OP | BRA_BUS_ERR | BRA_DEV_ERR) + +#define BRA_PEC_EN BIT(7) +#define BRA_START BIT(6) +#define BRA_LAST__BYTE BIT(5) +#define BRA_INTREN BIT(0) +#define BRA_SMB_CMD (7 << 2) +#define BRA_SMB_CMD_QUICK (0 << 2) +#define BRA_SMB_CMD_BYTE (1 << 2) +#define BRA_SMB_CMD_BYTE_DATA (2 << 2) +#define BRA_SMB_CMD_WORD_DATA (3 << 2) +#define BRA_SMB_CMD_PROCESS_CALL (4 << 2) +#define BRA_SMB_CMD_BLOCK (5 << 2) +#define BRA_SMB_CMD_I2CREAD (6 << 2) +#define BRA_SMB_CMD_BLOCK_PROCESS (7 << 2) + +#define BRA_SMB_BASE_ADDR 0x2040 +#define HSTS (BRA_SMB_BASE_ADDR + 0) +#define HCNT (BRA_SMB_BASE_ADDR + 2) +#define HCMD (BRA_SMB_BASE_ADDR + 3) +#define XMIT_SLVA (BRA_SMB_BASE_ADDR + 4) +#define HDAT0 (BRA_SMB_BASE_ADDR + 5) +#define HDAT1 (BRA_SMB_BASE_ADDR + 6) + +/* + * Microcontroller Address + */ + +#define SECOCEC_MICRO_ADDRESS 0x40 + +/* + * STM32 SMBus Registers + */ + +#define SECOCEC_VERSION 0x00 +#define SECOCEC_ENABLE_REG_1 0x01 +#define SECOCEC_ENABLE_REG_2 0x02 +#define SECOCEC_STATUS_REG_1 0x03 +#define SECOCEC_STATUS_REG_2 0x04 + +#define SECOCEC_STATUS 0x28 +#define SECOCEC_DEVICE_LA 0x29 +#define SECOCEC_READ_OPERATION_ID 0x2a +#define SECOCEC_READ_DATA_LENGTH 0x2b +#define SECOCEC_READ_DATA_00 0x2c +#define SECOCEC_READ_DATA_02 0x2d +#define SECOCEC_READ_DATA_04 0x2e +#define SECOCEC_READ_DATA_06 0x2f +#define SECOCEC_READ_DATA_08 0x30 +#define SECOCEC_READ_DATA_10 0x31 +#define SECOCEC_READ_DATA_12 0x32 +#define SECOCEC_READ_BYTE0 0x33 +#define SECOCEC_WRITE_OPERATION_ID 0x34 +#define SECOCEC_WRITE_DATA_LENGTH 0x35 +#define SECOCEC_WRITE_DATA_00 0x36 +#define SECOCEC_WRITE_DATA_02 0x37 +#define SECOCEC_WRITE_DATA_04 0x38 +#define SECOCEC_WRITE_DATA_06 0x39 +#define SECOCEC_WRITE_DATA_08 0x3a +#define SECOCEC_WRITE_DATA_10 0x3b +#define SECOCEC_WRITE_DATA_12 0x3c +#define SECOCEC_WRITE_BYTE0 0x3d + +#define SECOCEC_IR_READ_DATA 0x3e + +/* + * IR + */ + +#define SECOCEC_IR_COMMAND_MASK 0x007F +#define SECOCEC_IR_COMMAND_SHL 0 +#define SECOCEC_IR_ADDRESS_MASK 0x1F00 +#define SECOCEC_IR_ADDRESS_SHL 7 +#define SECOCEC_IR_TOGGLE_MASK 0x8000 +#define SECOCEC_IR_TOGGLE_SHL 15 + +/* + * Enabling register + */ + +#define SECOCEC_ENABLE_REG_1_CEC 0x1000 +#define SECOCEC_ENABLE_REG_1_IR 0x2000 +#define SECOCEC_ENABLE_REG_1_IR_PASSTHROUGH 0x4000 + +/* + * Status register + */ + +#define SECOCEC_STATUS_REG_1_CEC SECOCEC_ENABLE_REG_1_CEC +#define SECOCEC_STATUS_REG_1_IR SECOCEC_ENABLE_REG_1_IR +#define SECOCEC_STATUS_REG_1_IR_PASSTHR SECOCEC_ENABLE_REG_1_IR_PASSTHR + +/* + * Status data + */ + +#define SECOCEC_STATUS_MSG_RECEIVED_MASK BIT(0) +#define SECOCEC_STATUS_RX_ERROR_MASK BIT(1) +#define SECOCEC_STATUS_MSG_SENT_MASK BIT(2) +#define SECOCEC_STATUS_TX_ERROR_MASK BIT(3) + +#define SECOCEC_STATUS_TX_NACK_ERROR BIT(4) +#define SECOCEC_STATUS_RX_OVERFLOW_MASK BIT(5) + +#endif /* __SECO_CEC_H__ */ diff --git a/drivers/media/platform/sh_vou.c b/drivers/media/platform/sh_vou.c index cee58b125548..5799aa4b9323 100644 --- a/drivers/media/platform/sh_vou.c +++ b/drivers/media/platform/sh_vou.c @@ -1007,7 +1007,7 @@ static int sh_vou_s_selection(struct file *file, void *fh, /* * No down-scaling. According to the API, current call has precedence: - * http://v4l2spec.bytesex.org/spec/x1904.htm#AEN1954 paragraph two. + * https://linuxtv.org/downloads/v4l-dvb-apis/uapi/v4l/crop.html#cropping-structures */ vou_adjust_input(&geo, vou_dev->std); diff --git a/drivers/media/platform/sti/bdisp/bdisp-hw.c b/drivers/media/platform/sti/bdisp/bdisp-hw.c index 26d9fa7aeb5f..4372abbb5950 100644 --- a/drivers/media/platform/sti/bdisp/bdisp-hw.c +++ b/drivers/media/platform/sti/bdisp/bdisp-hw.c @@ -510,7 +510,7 @@ int bdisp_hw_alloc_filters(struct device *dev) /* Allocate all the filters within a single memory page */ size = (BDISP_HF_NB * NB_H_FILTER) + (BDISP_VF_NB * NB_V_FILTER); - base = dma_alloc_attrs(dev, size, &paddr, GFP_KERNEL | GFP_DMA, + base = dma_alloc_attrs(dev, size, &paddr, GFP_KERNEL, DMA_ATTR_WRITE_COMBINE); if (!base) return -ENOMEM; diff --git a/drivers/media/platform/sunxi/sun6i-csi/Kconfig b/drivers/media/platform/sunxi/sun6i-csi/Kconfig new file mode 100644 index 000000000000..018e3ec788c0 --- /dev/null +++ b/drivers/media/platform/sunxi/sun6i-csi/Kconfig @@ -0,0 +1,9 @@ +config VIDEO_SUN6I_CSI + tristate "Allwinner V3s Camera Sensor Interface driver" + depends on VIDEO_V4L2 && COMMON_CLK && VIDEO_V4L2_SUBDEV_API && HAS_DMA + depends on ARCH_SUNXI || COMPILE_TEST + select VIDEOBUF2_DMA_CONTIG + select REGMAP_MMIO + select V4L2_FWNODE + help + Support for the Allwinner Camera Sensor Interface Controller on V3s. diff --git a/drivers/media/platform/sunxi/sun6i-csi/Makefile b/drivers/media/platform/sunxi/sun6i-csi/Makefile new file mode 100644 index 000000000000..213cb6be9e9c --- /dev/null +++ b/drivers/media/platform/sunxi/sun6i-csi/Makefile @@ -0,0 +1,3 @@ +sun6i-csi-y += sun6i_video.o sun6i_csi.o + +obj-$(CONFIG_VIDEO_SUN6I_CSI) += sun6i-csi.o diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c new file mode 100644 index 000000000000..6950585edb5a --- /dev/null +++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c @@ -0,0 +1,913 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2011-2018 Magewell Electronics Co., Ltd. (Nanjing) + * All rights reserved. + * Author: Yong Deng <yong.deng@magewell.com> + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/dma-mapping.h> +#include <linux/err.h> +#include <linux/fs.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/ioctl.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> +#include <linux/regmap.h> +#include <linux/reset.h> +#include <linux/sched.h> +#include <linux/sizes.h> +#include <linux/slab.h> + +#include "sun6i_csi.h" +#include "sun6i_csi_reg.h" + +#define MODULE_NAME "sun6i-csi" + +struct sun6i_csi_dev { + struct sun6i_csi csi; + struct device *dev; + + struct regmap *regmap; + struct clk *clk_mod; + struct clk *clk_ram; + struct reset_control *rstc_bus; + + int planar_offset[3]; +}; + +static inline struct sun6i_csi_dev *sun6i_csi_to_dev(struct sun6i_csi *csi) +{ + return container_of(csi, struct sun6i_csi_dev, csi); +} + +/* TODO add 10&12 bit YUV, RGB support */ +bool sun6i_csi_is_format_supported(struct sun6i_csi *csi, + u32 pixformat, u32 mbus_code) +{ + struct sun6i_csi_dev *sdev = sun6i_csi_to_dev(csi); + + /* + * Some video receivers have the ability to be compatible with + * 8bit and 16bit bus width. + * Identify the media bus format from device tree. + */ + if ((sdev->csi.v4l2_ep.bus_type == V4L2_MBUS_PARALLEL + || sdev->csi.v4l2_ep.bus_type == V4L2_MBUS_BT656) + && sdev->csi.v4l2_ep.bus.parallel.bus_width == 16) { + switch (pixformat) { + case V4L2_PIX_FMT_HM12: + case V4L2_PIX_FMT_NV12: + case V4L2_PIX_FMT_NV21: + case V4L2_PIX_FMT_NV16: + case V4L2_PIX_FMT_NV61: + case V4L2_PIX_FMT_YUV420: + case V4L2_PIX_FMT_YVU420: + case V4L2_PIX_FMT_YUV422P: + switch (mbus_code) { + case MEDIA_BUS_FMT_UYVY8_1X16: + case MEDIA_BUS_FMT_VYUY8_1X16: + case MEDIA_BUS_FMT_YUYV8_1X16: + case MEDIA_BUS_FMT_YVYU8_1X16: + return true; + default: + dev_dbg(sdev->dev, "Unsupported mbus code: 0x%x\n", + mbus_code); + break; + } + break; + default: + dev_dbg(sdev->dev, "Unsupported pixformat: 0x%x\n", + pixformat); + break; + } + return false; + } + + switch (pixformat) { + case V4L2_PIX_FMT_SBGGR8: + return (mbus_code == MEDIA_BUS_FMT_SBGGR8_1X8); + case V4L2_PIX_FMT_SGBRG8: + return (mbus_code == MEDIA_BUS_FMT_SGBRG8_1X8); + case V4L2_PIX_FMT_SGRBG8: + return (mbus_code == MEDIA_BUS_FMT_SGRBG8_1X8); + case V4L2_PIX_FMT_SRGGB8: + return (mbus_code == MEDIA_BUS_FMT_SRGGB8_1X8); + case V4L2_PIX_FMT_SBGGR10: + return (mbus_code == MEDIA_BUS_FMT_SBGGR10_1X10); + case V4L2_PIX_FMT_SGBRG10: + return (mbus_code == MEDIA_BUS_FMT_SGBRG10_1X10); + case V4L2_PIX_FMT_SGRBG10: + return (mbus_code == MEDIA_BUS_FMT_SGRBG10_1X10); + case V4L2_PIX_FMT_SRGGB10: + return (mbus_code == MEDIA_BUS_FMT_SRGGB10_1X10); + case V4L2_PIX_FMT_SBGGR12: + return (mbus_code == MEDIA_BUS_FMT_SBGGR12_1X12); + case V4L2_PIX_FMT_SGBRG12: + return (mbus_code == MEDIA_BUS_FMT_SGBRG12_1X12); + case V4L2_PIX_FMT_SGRBG12: + return (mbus_code == MEDIA_BUS_FMT_SGRBG12_1X12); + case V4L2_PIX_FMT_SRGGB12: + return (mbus_code == MEDIA_BUS_FMT_SRGGB12_1X12); + + case V4L2_PIX_FMT_YUYV: + return (mbus_code == MEDIA_BUS_FMT_YUYV8_2X8); + case V4L2_PIX_FMT_YVYU: + return (mbus_code == MEDIA_BUS_FMT_YVYU8_2X8); + case V4L2_PIX_FMT_UYVY: + return (mbus_code == MEDIA_BUS_FMT_UYVY8_2X8); + case V4L2_PIX_FMT_VYUY: + return (mbus_code == MEDIA_BUS_FMT_VYUY8_2X8); + + case V4L2_PIX_FMT_HM12: + case V4L2_PIX_FMT_NV12: + case V4L2_PIX_FMT_NV21: + case V4L2_PIX_FMT_NV16: + case V4L2_PIX_FMT_NV61: + case V4L2_PIX_FMT_YUV420: + case V4L2_PIX_FMT_YVU420: + case V4L2_PIX_FMT_YUV422P: + switch (mbus_code) { + case MEDIA_BUS_FMT_UYVY8_2X8: + case MEDIA_BUS_FMT_VYUY8_2X8: + case MEDIA_BUS_FMT_YUYV8_2X8: + case MEDIA_BUS_FMT_YVYU8_2X8: + return true; + default: + dev_dbg(sdev->dev, "Unsupported mbus code: 0x%x\n", + mbus_code); + break; + } + break; + default: + dev_dbg(sdev->dev, "Unsupported pixformat: 0x%x\n", pixformat); + break; + } + + return false; +} + +int sun6i_csi_set_power(struct sun6i_csi *csi, bool enable) +{ + struct sun6i_csi_dev *sdev = sun6i_csi_to_dev(csi); + struct regmap *regmap = sdev->regmap; + int ret; + + if (!enable) { + regmap_update_bits(regmap, CSI_EN_REG, CSI_EN_CSI_EN, 0); + + clk_disable_unprepare(sdev->clk_ram); + clk_disable_unprepare(sdev->clk_mod); + reset_control_assert(sdev->rstc_bus); + return 0; + } + + ret = clk_prepare_enable(sdev->clk_mod); + if (ret) { + dev_err(sdev->dev, "Enable csi clk err %d\n", ret); + return ret; + } + + ret = clk_prepare_enable(sdev->clk_ram); + if (ret) { + dev_err(sdev->dev, "Enable clk_dram_csi clk err %d\n", ret); + goto clk_mod_disable; + } + + ret = reset_control_deassert(sdev->rstc_bus); + if (ret) { + dev_err(sdev->dev, "reset err %d\n", ret); + goto clk_ram_disable; + } + + regmap_update_bits(regmap, CSI_EN_REG, CSI_EN_CSI_EN, CSI_EN_CSI_EN); + + return 0; + +clk_ram_disable: + clk_disable_unprepare(sdev->clk_ram); +clk_mod_disable: + clk_disable_unprepare(sdev->clk_mod); + return ret; +} + +static enum csi_input_fmt get_csi_input_format(struct sun6i_csi_dev *sdev, + u32 mbus_code, u32 pixformat) +{ + /* bayer */ + if ((mbus_code & 0xF000) == 0x3000) + return CSI_INPUT_FORMAT_RAW; + + switch (pixformat) { + case V4L2_PIX_FMT_YUYV: + case V4L2_PIX_FMT_YVYU: + case V4L2_PIX_FMT_UYVY: + case V4L2_PIX_FMT_VYUY: + return CSI_INPUT_FORMAT_RAW; + default: + break; + } + + /* not support YUV420 input format yet */ + dev_dbg(sdev->dev, "Select YUV422 as default input format of CSI.\n"); + return CSI_INPUT_FORMAT_YUV422; +} + +static enum csi_output_fmt get_csi_output_format(struct sun6i_csi_dev *sdev, + u32 pixformat, u32 field) +{ + bool buf_interlaced = false; + + if (field == V4L2_FIELD_INTERLACED + || field == V4L2_FIELD_INTERLACED_TB + || field == V4L2_FIELD_INTERLACED_BT) + buf_interlaced = true; + + switch (pixformat) { + case V4L2_PIX_FMT_SBGGR8: + case V4L2_PIX_FMT_SGBRG8: + case V4L2_PIX_FMT_SGRBG8: + case V4L2_PIX_FMT_SRGGB8: + return buf_interlaced ? CSI_FRAME_RAW_8 : CSI_FIELD_RAW_8; + case V4L2_PIX_FMT_SBGGR10: + case V4L2_PIX_FMT_SGBRG10: + case V4L2_PIX_FMT_SGRBG10: + case V4L2_PIX_FMT_SRGGB10: + return buf_interlaced ? CSI_FRAME_RAW_10 : CSI_FIELD_RAW_10; + case V4L2_PIX_FMT_SBGGR12: + case V4L2_PIX_FMT_SGBRG12: + case V4L2_PIX_FMT_SGRBG12: + case V4L2_PIX_FMT_SRGGB12: + return buf_interlaced ? CSI_FRAME_RAW_12 : CSI_FIELD_RAW_12; + + case V4L2_PIX_FMT_YUYV: + case V4L2_PIX_FMT_YVYU: + case V4L2_PIX_FMT_UYVY: + case V4L2_PIX_FMT_VYUY: + return buf_interlaced ? CSI_FRAME_RAW_8 : CSI_FIELD_RAW_8; + + case V4L2_PIX_FMT_HM12: + return buf_interlaced ? CSI_FRAME_MB_YUV420 : + CSI_FIELD_MB_YUV420; + case V4L2_PIX_FMT_NV12: + case V4L2_PIX_FMT_NV21: + return buf_interlaced ? CSI_FRAME_UV_CB_YUV420 : + CSI_FIELD_UV_CB_YUV420; + case V4L2_PIX_FMT_YUV420: + case V4L2_PIX_FMT_YVU420: + return buf_interlaced ? CSI_FRAME_PLANAR_YUV420 : + CSI_FIELD_PLANAR_YUV420; + case V4L2_PIX_FMT_NV16: + case V4L2_PIX_FMT_NV61: + return buf_interlaced ? CSI_FRAME_UV_CB_YUV422 : + CSI_FIELD_UV_CB_YUV422; + case V4L2_PIX_FMT_YUV422P: + return buf_interlaced ? CSI_FRAME_PLANAR_YUV422 : + CSI_FIELD_PLANAR_YUV422; + default: + dev_warn(sdev->dev, "Unsupported pixformat: 0x%x\n", pixformat); + break; + } + + return CSI_FIELD_RAW_8; +} + +static enum csi_input_seq get_csi_input_seq(struct sun6i_csi_dev *sdev, + u32 mbus_code, u32 pixformat) +{ + switch (pixformat) { + case V4L2_PIX_FMT_HM12: + case V4L2_PIX_FMT_NV12: + case V4L2_PIX_FMT_NV16: + case V4L2_PIX_FMT_YUV420: + case V4L2_PIX_FMT_YUV422P: + switch (mbus_code) { + case MEDIA_BUS_FMT_UYVY8_2X8: + case MEDIA_BUS_FMT_UYVY8_1X16: + return CSI_INPUT_SEQ_UYVY; + case MEDIA_BUS_FMT_VYUY8_2X8: + case MEDIA_BUS_FMT_VYUY8_1X16: + return CSI_INPUT_SEQ_VYUY; + case MEDIA_BUS_FMT_YUYV8_2X8: + case MEDIA_BUS_FMT_YUYV8_1X16: + return CSI_INPUT_SEQ_YUYV; + case MEDIA_BUS_FMT_YVYU8_1X16: + case MEDIA_BUS_FMT_YVYU8_2X8: + return CSI_INPUT_SEQ_YVYU; + default: + dev_warn(sdev->dev, "Unsupported mbus code: 0x%x\n", + mbus_code); + break; + } + break; + case V4L2_PIX_FMT_NV21: + case V4L2_PIX_FMT_NV61: + case V4L2_PIX_FMT_YVU420: + switch (mbus_code) { + case MEDIA_BUS_FMT_UYVY8_2X8: + case MEDIA_BUS_FMT_UYVY8_1X16: + return CSI_INPUT_SEQ_VYUY; + case MEDIA_BUS_FMT_VYUY8_2X8: + case MEDIA_BUS_FMT_VYUY8_1X16: + return CSI_INPUT_SEQ_UYVY; + case MEDIA_BUS_FMT_YUYV8_2X8: + case MEDIA_BUS_FMT_YUYV8_1X16: + return CSI_INPUT_SEQ_YVYU; + case MEDIA_BUS_FMT_YVYU8_1X16: + case MEDIA_BUS_FMT_YVYU8_2X8: + return CSI_INPUT_SEQ_YUYV; + default: + dev_warn(sdev->dev, "Unsupported mbus code: 0x%x\n", + mbus_code); + break; + } + break; + + case V4L2_PIX_FMT_YUYV: + return CSI_INPUT_SEQ_YUYV; + + default: + dev_warn(sdev->dev, "Unsupported pixformat: 0x%x, defaulting to YUYV\n", + pixformat); + break; + } + + return CSI_INPUT_SEQ_YUYV; +} + +static void sun6i_csi_setup_bus(struct sun6i_csi_dev *sdev) +{ + struct v4l2_fwnode_endpoint *endpoint = &sdev->csi.v4l2_ep; + struct sun6i_csi *csi = &sdev->csi; + unsigned char bus_width; + u32 flags; + u32 cfg; + bool input_interlaced = false; + + if (csi->config.field == V4L2_FIELD_INTERLACED + || csi->config.field == V4L2_FIELD_INTERLACED_TB + || csi->config.field == V4L2_FIELD_INTERLACED_BT) + input_interlaced = true; + + bus_width = endpoint->bus.parallel.bus_width; + + regmap_read(sdev->regmap, CSI_IF_CFG_REG, &cfg); + + cfg &= ~(CSI_IF_CFG_CSI_IF_MASK | CSI_IF_CFG_MIPI_IF_MASK | + CSI_IF_CFG_IF_DATA_WIDTH_MASK | + CSI_IF_CFG_CLK_POL_MASK | CSI_IF_CFG_VREF_POL_MASK | + CSI_IF_CFG_HREF_POL_MASK | CSI_IF_CFG_FIELD_MASK | + CSI_IF_CFG_SRC_TYPE_MASK); + + if (input_interlaced) + cfg |= CSI_IF_CFG_SRC_TYPE_INTERLACED; + else + cfg |= CSI_IF_CFG_SRC_TYPE_PROGRESSED; + + switch (endpoint->bus_type) { + case V4L2_MBUS_PARALLEL: + cfg |= CSI_IF_CFG_MIPI_IF_CSI; + + flags = endpoint->bus.parallel.flags; + + cfg |= (bus_width == 16) ? CSI_IF_CFG_CSI_IF_YUV422_16BIT : + CSI_IF_CFG_CSI_IF_YUV422_INTLV; + + if (flags & V4L2_MBUS_FIELD_EVEN_LOW) + cfg |= CSI_IF_CFG_FIELD_POSITIVE; + + if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW) + cfg |= CSI_IF_CFG_VREF_POL_POSITIVE; + if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW) + cfg |= CSI_IF_CFG_HREF_POL_POSITIVE; + + if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING) + cfg |= CSI_IF_CFG_CLK_POL_FALLING_EDGE; + break; + case V4L2_MBUS_BT656: + cfg |= CSI_IF_CFG_MIPI_IF_CSI; + + flags = endpoint->bus.parallel.flags; + + cfg |= (bus_width == 16) ? CSI_IF_CFG_CSI_IF_BT1120 : + CSI_IF_CFG_CSI_IF_BT656; + + if (flags & V4L2_MBUS_FIELD_EVEN_LOW) + cfg |= CSI_IF_CFG_FIELD_POSITIVE; + + if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING) + cfg |= CSI_IF_CFG_CLK_POL_FALLING_EDGE; + break; + default: + dev_warn(sdev->dev, "Unsupported bus type: %d\n", + endpoint->bus_type); + break; + } + + switch (bus_width) { + case 8: + cfg |= CSI_IF_CFG_IF_DATA_WIDTH_8BIT; + break; + case 10: + cfg |= CSI_IF_CFG_IF_DATA_WIDTH_10BIT; + break; + case 12: + cfg |= CSI_IF_CFG_IF_DATA_WIDTH_12BIT; + break; + case 16: /* No need to configure DATA_WIDTH for 16bit */ + break; + default: + dev_warn(sdev->dev, "Unsupported bus width: %u\n", bus_width); + break; + } + + regmap_write(sdev->regmap, CSI_IF_CFG_REG, cfg); +} + +static void sun6i_csi_set_format(struct sun6i_csi_dev *sdev) +{ + struct sun6i_csi *csi = &sdev->csi; + u32 cfg; + u32 val; + + regmap_read(sdev->regmap, CSI_CH_CFG_REG, &cfg); + + cfg &= ~(CSI_CH_CFG_INPUT_FMT_MASK | + CSI_CH_CFG_OUTPUT_FMT_MASK | CSI_CH_CFG_VFLIP_EN | + CSI_CH_CFG_HFLIP_EN | CSI_CH_CFG_FIELD_SEL_MASK | + CSI_CH_CFG_INPUT_SEQ_MASK); + + val = get_csi_input_format(sdev, csi->config.code, + csi->config.pixelformat); + cfg |= CSI_CH_CFG_INPUT_FMT(val); + + val = get_csi_output_format(sdev, csi->config.pixelformat, + csi->config.field); + cfg |= CSI_CH_CFG_OUTPUT_FMT(val); + + val = get_csi_input_seq(sdev, csi->config.code, + csi->config.pixelformat); + cfg |= CSI_CH_CFG_INPUT_SEQ(val); + + if (csi->config.field == V4L2_FIELD_TOP) + cfg |= CSI_CH_CFG_FIELD_SEL_FIELD0; + else if (csi->config.field == V4L2_FIELD_BOTTOM) + cfg |= CSI_CH_CFG_FIELD_SEL_FIELD1; + else + cfg |= CSI_CH_CFG_FIELD_SEL_BOTH; + + regmap_write(sdev->regmap, CSI_CH_CFG_REG, cfg); +} + +static void sun6i_csi_set_window(struct sun6i_csi_dev *sdev) +{ + struct sun6i_csi_config *config = &sdev->csi.config; + u32 bytesperline_y; + u32 bytesperline_c; + int *planar_offset = sdev->planar_offset; + u32 width = config->width; + u32 height = config->height; + u32 hor_len = width; + + switch (config->pixelformat) { + case V4L2_PIX_FMT_YUYV: + case V4L2_PIX_FMT_YVYU: + case V4L2_PIX_FMT_UYVY: + case V4L2_PIX_FMT_VYUY: + dev_dbg(sdev->dev, + "Horizontal length should be 2 times of width for packed YUV formats!\n"); + hor_len = width * 2; + break; + default: + break; + } + + regmap_write(sdev->regmap, CSI_CH_HSIZE_REG, + CSI_CH_HSIZE_HOR_LEN(hor_len) | + CSI_CH_HSIZE_HOR_START(0)); + regmap_write(sdev->regmap, CSI_CH_VSIZE_REG, + CSI_CH_VSIZE_VER_LEN(height) | + CSI_CH_VSIZE_VER_START(0)); + + planar_offset[0] = 0; + switch (config->pixelformat) { + case V4L2_PIX_FMT_HM12: + case V4L2_PIX_FMT_NV12: + case V4L2_PIX_FMT_NV21: + case V4L2_PIX_FMT_NV16: + case V4L2_PIX_FMT_NV61: + bytesperline_y = width; + bytesperline_c = width; + planar_offset[1] = bytesperline_y * height; + planar_offset[2] = -1; + break; + case V4L2_PIX_FMT_YUV420: + case V4L2_PIX_FMT_YVU420: + bytesperline_y = width; + bytesperline_c = width / 2; + planar_offset[1] = bytesperline_y * height; + planar_offset[2] = planar_offset[1] + + bytesperline_c * height / 2; + break; + case V4L2_PIX_FMT_YUV422P: + bytesperline_y = width; + bytesperline_c = width / 2; + planar_offset[1] = bytesperline_y * height; + planar_offset[2] = planar_offset[1] + + bytesperline_c * height; + break; + default: /* raw */ + dev_dbg(sdev->dev, + "Calculating pixelformat(0x%x)'s bytesperline as a packed format\n", + config->pixelformat); + bytesperline_y = (sun6i_csi_get_bpp(config->pixelformat) * + config->width) / 8; + bytesperline_c = 0; + planar_offset[1] = -1; + planar_offset[2] = -1; + break; + } + + regmap_write(sdev->regmap, CSI_CH_BUF_LEN_REG, + CSI_CH_BUF_LEN_BUF_LEN_C(bytesperline_c) | + CSI_CH_BUF_LEN_BUF_LEN_Y(bytesperline_y)); +} + +int sun6i_csi_update_config(struct sun6i_csi *csi, + struct sun6i_csi_config *config) +{ + struct sun6i_csi_dev *sdev = sun6i_csi_to_dev(csi); + + if (!config) + return -EINVAL; + + memcpy(&csi->config, config, sizeof(csi->config)); + + sun6i_csi_setup_bus(sdev); + sun6i_csi_set_format(sdev); + sun6i_csi_set_window(sdev); + + return 0; +} + +void sun6i_csi_update_buf_addr(struct sun6i_csi *csi, dma_addr_t addr) +{ + struct sun6i_csi_dev *sdev = sun6i_csi_to_dev(csi); + + regmap_write(sdev->regmap, CSI_CH_F0_BUFA_REG, + (addr + sdev->planar_offset[0]) >> 2); + if (sdev->planar_offset[1] != -1) + regmap_write(sdev->regmap, CSI_CH_F1_BUFA_REG, + (addr + sdev->planar_offset[1]) >> 2); + if (sdev->planar_offset[2] != -1) + regmap_write(sdev->regmap, CSI_CH_F2_BUFA_REG, + (addr + sdev->planar_offset[2]) >> 2); +} + +void sun6i_csi_set_stream(struct sun6i_csi *csi, bool enable) +{ + struct sun6i_csi_dev *sdev = sun6i_csi_to_dev(csi); + struct regmap *regmap = sdev->regmap; + + if (!enable) { + regmap_update_bits(regmap, CSI_CAP_REG, CSI_CAP_CH0_VCAP_ON, 0); + regmap_write(regmap, CSI_CH_INT_EN_REG, 0); + return; + } + + regmap_write(regmap, CSI_CH_INT_STA_REG, 0xFF); + regmap_write(regmap, CSI_CH_INT_EN_REG, + CSI_CH_INT_EN_HB_OF_INT_EN | + CSI_CH_INT_EN_FIFO2_OF_INT_EN | + CSI_CH_INT_EN_FIFO1_OF_INT_EN | + CSI_CH_INT_EN_FIFO0_OF_INT_EN | + CSI_CH_INT_EN_FD_INT_EN | + CSI_CH_INT_EN_CD_INT_EN); + + regmap_update_bits(regmap, CSI_CAP_REG, CSI_CAP_CH0_VCAP_ON, + CSI_CAP_CH0_VCAP_ON); +} + +/* ----------------------------------------------------------------------------- + * Media Controller and V4L2 + */ +static int sun6i_csi_link_entity(struct sun6i_csi *csi, + struct media_entity *entity, + struct fwnode_handle *fwnode) +{ + struct media_entity *sink; + struct media_pad *sink_pad; + int src_pad_index; + int ret; + + ret = media_entity_get_fwnode_pad(entity, fwnode, MEDIA_PAD_FL_SOURCE); + if (ret < 0) { + dev_err(csi->dev, "%s: no source pad in external entity %s\n", + __func__, entity->name); + return -EINVAL; + } + + src_pad_index = ret; + + sink = &csi->video.vdev.entity; + sink_pad = &csi->video.pad; + + dev_dbg(csi->dev, "creating %s:%u -> %s:%u link\n", + entity->name, src_pad_index, sink->name, sink_pad->index); + ret = media_create_pad_link(entity, src_pad_index, sink, + sink_pad->index, + MEDIA_LNK_FL_ENABLED | + MEDIA_LNK_FL_IMMUTABLE); + if (ret < 0) { + dev_err(csi->dev, "failed to create %s:%u -> %s:%u link\n", + entity->name, src_pad_index, + sink->name, sink_pad->index); + return ret; + } + + return 0; +} + +static int sun6i_subdev_notify_complete(struct v4l2_async_notifier *notifier) +{ + struct sun6i_csi *csi = container_of(notifier, struct sun6i_csi, + notifier); + struct v4l2_device *v4l2_dev = &csi->v4l2_dev; + struct v4l2_subdev *sd; + int ret; + + dev_dbg(csi->dev, "notify complete, all subdevs registered\n"); + + sd = list_first_entry(&v4l2_dev->subdevs, struct v4l2_subdev, list); + if (!sd) + return -EINVAL; + + ret = sun6i_csi_link_entity(csi, &sd->entity, sd->fwnode); + if (ret < 0) + return ret; + + ret = v4l2_device_register_subdev_nodes(&csi->v4l2_dev); + if (ret < 0) + return ret; + + return media_device_register(&csi->media_dev); +} + +static const struct v4l2_async_notifier_operations sun6i_csi_async_ops = { + .complete = sun6i_subdev_notify_complete, +}; + +static int sun6i_csi_fwnode_parse(struct device *dev, + struct v4l2_fwnode_endpoint *vep, + struct v4l2_async_subdev *asd) +{ + struct sun6i_csi *csi = dev_get_drvdata(dev); + + if (vep->base.port || vep->base.id) { + dev_warn(dev, "Only support a single port with one endpoint\n"); + return -ENOTCONN; + } + + switch (vep->bus_type) { + case V4L2_MBUS_PARALLEL: + case V4L2_MBUS_BT656: + csi->v4l2_ep = *vep; + return 0; + default: + dev_err(dev, "Unsupported media bus type\n"); + return -ENOTCONN; + } +} + +static void sun6i_csi_v4l2_cleanup(struct sun6i_csi *csi) +{ + media_device_unregister(&csi->media_dev); + v4l2_async_notifier_unregister(&csi->notifier); + v4l2_async_notifier_cleanup(&csi->notifier); + sun6i_video_cleanup(&csi->video); + v4l2_device_unregister(&csi->v4l2_dev); + v4l2_ctrl_handler_free(&csi->ctrl_handler); + media_device_cleanup(&csi->media_dev); +} + +static int sun6i_csi_v4l2_init(struct sun6i_csi *csi) +{ + int ret; + + csi->media_dev.dev = csi->dev; + strscpy(csi->media_dev.model, "Allwinner Video Capture Device", + sizeof(csi->media_dev.model)); + csi->media_dev.hw_revision = 0; + + media_device_init(&csi->media_dev); + v4l2_async_notifier_init(&csi->notifier); + + ret = v4l2_ctrl_handler_init(&csi->ctrl_handler, 0); + if (ret) { + dev_err(csi->dev, "V4L2 controls handler init failed (%d)\n", + ret); + goto clean_media; + } + + csi->v4l2_dev.mdev = &csi->media_dev; + csi->v4l2_dev.ctrl_handler = &csi->ctrl_handler; + ret = v4l2_device_register(csi->dev, &csi->v4l2_dev); + if (ret) { + dev_err(csi->dev, "V4L2 device registration failed (%d)\n", + ret); + goto free_ctrl; + } + + ret = sun6i_video_init(&csi->video, csi, "sun6i-csi"); + if (ret) + goto unreg_v4l2; + + ret = v4l2_async_notifier_parse_fwnode_endpoints(csi->dev, + &csi->notifier, + sizeof(struct v4l2_async_subdev), + sun6i_csi_fwnode_parse); + if (ret) + goto clean_video; + + csi->notifier.ops = &sun6i_csi_async_ops; + + ret = v4l2_async_notifier_register(&csi->v4l2_dev, &csi->notifier); + if (ret) { + dev_err(csi->dev, "notifier registration failed\n"); + goto clean_video; + } + + return 0; + +clean_video: + sun6i_video_cleanup(&csi->video); +unreg_v4l2: + v4l2_device_unregister(&csi->v4l2_dev); +free_ctrl: + v4l2_ctrl_handler_free(&csi->ctrl_handler); +clean_media: + v4l2_async_notifier_cleanup(&csi->notifier); + media_device_cleanup(&csi->media_dev); + + return ret; +} + +/* ----------------------------------------------------------------------------- + * Resources and IRQ + */ +static irqreturn_t sun6i_csi_isr(int irq, void *dev_id) +{ + struct sun6i_csi_dev *sdev = (struct sun6i_csi_dev *)dev_id; + struct regmap *regmap = sdev->regmap; + u32 status; + + regmap_read(regmap, CSI_CH_INT_STA_REG, &status); + + if (!(status & 0xFF)) + return IRQ_NONE; + + if ((status & CSI_CH_INT_STA_FIFO0_OF_PD) || + (status & CSI_CH_INT_STA_FIFO1_OF_PD) || + (status & CSI_CH_INT_STA_FIFO2_OF_PD) || + (status & CSI_CH_INT_STA_HB_OF_PD)) { + regmap_write(regmap, CSI_CH_INT_STA_REG, status); + regmap_update_bits(regmap, CSI_EN_REG, CSI_EN_CSI_EN, 0); + regmap_update_bits(regmap, CSI_EN_REG, CSI_EN_CSI_EN, + CSI_EN_CSI_EN); + return IRQ_HANDLED; + } + + if (status & CSI_CH_INT_STA_FD_PD) + sun6i_video_frame_done(&sdev->csi.video); + + regmap_write(regmap, CSI_CH_INT_STA_REG, status); + + return IRQ_HANDLED; +} + +static const struct regmap_config sun6i_csi_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1000, +}; + +static int sun6i_csi_resource_request(struct sun6i_csi_dev *sdev, + struct platform_device *pdev) +{ + struct resource *res; + void __iomem *io_base; + int ret; + int irq; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + io_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(io_base)) + return PTR_ERR(io_base); + + sdev->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "bus", io_base, + &sun6i_csi_regmap_config); + if (IS_ERR(sdev->regmap)) { + dev_err(&pdev->dev, "Failed to init register map\n"); + return PTR_ERR(sdev->regmap); + } + + sdev->clk_mod = devm_clk_get(&pdev->dev, "mod"); + if (IS_ERR(sdev->clk_mod)) { + dev_err(&pdev->dev, "Unable to acquire csi clock\n"); + return PTR_ERR(sdev->clk_mod); + } + + sdev->clk_ram = devm_clk_get(&pdev->dev, "ram"); + if (IS_ERR(sdev->clk_ram)) { + dev_err(&pdev->dev, "Unable to acquire dram-csi clock\n"); + return PTR_ERR(sdev->clk_ram); + } + + sdev->rstc_bus = devm_reset_control_get_shared(&pdev->dev, NULL); + if (IS_ERR(sdev->rstc_bus)) { + dev_err(&pdev->dev, "Cannot get reset controller\n"); + return PTR_ERR(sdev->rstc_bus); + } + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(&pdev->dev, "No csi IRQ specified\n"); + ret = -ENXIO; + return ret; + } + + ret = devm_request_irq(&pdev->dev, irq, sun6i_csi_isr, 0, MODULE_NAME, + sdev); + if (ret) { + dev_err(&pdev->dev, "Cannot request csi IRQ\n"); + return ret; + } + + return 0; +} + +/* + * PHYS_OFFSET isn't available on all architectures. In order to + * accommodate for COMPILE_TEST, let's define it to something dumb. + */ +#if defined(CONFIG_COMPILE_TEST) && !defined(PHYS_OFFSET) +#define PHYS_OFFSET 0 +#endif + +static int sun6i_csi_probe(struct platform_device *pdev) +{ + struct sun6i_csi_dev *sdev; + int ret; + + sdev = devm_kzalloc(&pdev->dev, sizeof(*sdev), GFP_KERNEL); + if (!sdev) + return -ENOMEM; + + sdev->dev = &pdev->dev; + /* The DMA bus has the memory mapped at 0 */ + sdev->dev->dma_pfn_offset = PHYS_OFFSET >> PAGE_SHIFT; + + ret = sun6i_csi_resource_request(sdev, pdev); + if (ret) + return ret; + + platform_set_drvdata(pdev, sdev); + + sdev->csi.dev = &pdev->dev; + return sun6i_csi_v4l2_init(&sdev->csi); +} + +static int sun6i_csi_remove(struct platform_device *pdev) +{ + struct sun6i_csi_dev *sdev = platform_get_drvdata(pdev); + + sun6i_csi_v4l2_cleanup(&sdev->csi); + + return 0; +} + +static const struct of_device_id sun6i_csi_of_match[] = { + { .compatible = "allwinner,sun6i-a31-csi", }, + { .compatible = "allwinner,sun8i-v3s-csi", }, + {}, +}; +MODULE_DEVICE_TABLE(of, sun6i_csi_of_match); + +static struct platform_driver sun6i_csi_platform_driver = { + .probe = sun6i_csi_probe, + .remove = sun6i_csi_remove, + .driver = { + .name = MODULE_NAME, + .of_match_table = of_match_ptr(sun6i_csi_of_match), + }, +}; +module_platform_driver(sun6i_csi_platform_driver); + +MODULE_DESCRIPTION("Allwinner V3s Camera Sensor Interface driver"); +MODULE_AUTHOR("Yong Deng <yong.deng@magewell.com>"); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h new file mode 100644 index 000000000000..0bb000712c33 --- /dev/null +++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h @@ -0,0 +1,135 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2011-2018 Magewell Electronics Co., Ltd. (Nanjing) + * All rights reserved. + * Author: Yong Deng <yong.deng@magewell.com> + */ + +#ifndef __SUN6I_CSI_H__ +#define __SUN6I_CSI_H__ + +#include <media/v4l2-ctrls.h> +#include <media/v4l2-device.h> +#include <media/v4l2-fwnode.h> + +#include "sun6i_video.h" + +struct sun6i_csi; + +/** + * struct sun6i_csi_config - configs for sun6i csi + * @pixelformat: v4l2 pixel format (V4L2_PIX_FMT_*) + * @code: media bus format code (MEDIA_BUS_FMT_*) + * @field: used interlacing type (enum v4l2_field) + * @width: frame width + * @height: frame height + */ +struct sun6i_csi_config { + u32 pixelformat; + u32 code; + u32 field; + u32 width; + u32 height; +}; + +struct sun6i_csi { + struct device *dev; + struct v4l2_ctrl_handler ctrl_handler; + struct v4l2_device v4l2_dev; + struct media_device media_dev; + + struct v4l2_async_notifier notifier; + + /* video port settings */ + struct v4l2_fwnode_endpoint v4l2_ep; + + struct sun6i_csi_config config; + + struct sun6i_video video; +}; + +/** + * sun6i_csi_is_format_supported() - check if the format supported by csi + * @csi: pointer to the csi + * @pixformat: v4l2 pixel format (V4L2_PIX_FMT_*) + * @mbus_code: media bus format code (MEDIA_BUS_FMT_*) + */ +bool sun6i_csi_is_format_supported(struct sun6i_csi *csi, u32 pixformat, + u32 mbus_code); + +/** + * sun6i_csi_set_power() - power on/off the csi + * @csi: pointer to the csi + * @enable: on/off + */ +int sun6i_csi_set_power(struct sun6i_csi *csi, bool enable); + +/** + * sun6i_csi_update_config() - update the csi register setttings + * @csi: pointer to the csi + * @config: see struct sun6i_csi_config + */ +int sun6i_csi_update_config(struct sun6i_csi *csi, + struct sun6i_csi_config *config); + +/** + * sun6i_csi_update_buf_addr() - update the csi frame buffer address + * @csi: pointer to the csi + * @addr: frame buffer's physical address + */ +void sun6i_csi_update_buf_addr(struct sun6i_csi *csi, dma_addr_t addr); + +/** + * sun6i_csi_set_stream() - start/stop csi streaming + * @csi: pointer to the csi + * @enable: start/stop + */ +void sun6i_csi_set_stream(struct sun6i_csi *csi, bool enable); + +/* get bpp form v4l2 pixformat */ +static inline int sun6i_csi_get_bpp(unsigned int pixformat) +{ + switch (pixformat) { + case V4L2_PIX_FMT_SBGGR8: + case V4L2_PIX_FMT_SGBRG8: + case V4L2_PIX_FMT_SGRBG8: + case V4L2_PIX_FMT_SRGGB8: + return 8; + case V4L2_PIX_FMT_SBGGR10: + case V4L2_PIX_FMT_SGBRG10: + case V4L2_PIX_FMT_SGRBG10: + case V4L2_PIX_FMT_SRGGB10: + return 10; + case V4L2_PIX_FMT_SBGGR12: + case V4L2_PIX_FMT_SGBRG12: + case V4L2_PIX_FMT_SGRBG12: + case V4L2_PIX_FMT_SRGGB12: + case V4L2_PIX_FMT_HM12: + case V4L2_PIX_FMT_NV12: + case V4L2_PIX_FMT_NV21: + case V4L2_PIX_FMT_YUV420: + case V4L2_PIX_FMT_YVU420: + return 12; + case V4L2_PIX_FMT_YUYV: + case V4L2_PIX_FMT_YVYU: + case V4L2_PIX_FMT_UYVY: + case V4L2_PIX_FMT_VYUY: + case V4L2_PIX_FMT_NV16: + case V4L2_PIX_FMT_NV61: + case V4L2_PIX_FMT_YUV422P: + return 16; + case V4L2_PIX_FMT_RGB24: + case V4L2_PIX_FMT_BGR24: + return 24; + case V4L2_PIX_FMT_RGB32: + case V4L2_PIX_FMT_BGR32: + return 32; + default: + WARN(1, "Unsupported pixformat: 0x%x\n", pixformat); + break; + } + + return 0; +} + +#endif /* __SUN6I_CSI_H__ */ diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h new file mode 100644 index 000000000000..703fa14bb313 --- /dev/null +++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h @@ -0,0 +1,196 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2011-2018 Magewell Electronics Co., Ltd. (Nanjing) + * All rights reserved. + * Author: Yong Deng <yong.deng@magewell.com> + */ + +#ifndef __SUN6I_CSI_REG_H__ +#define __SUN6I_CSI_REG_H__ + +#include <linux/kernel.h> + +#define CSI_EN_REG 0x0 +#define CSI_EN_VER_EN BIT(30) +#define CSI_EN_CSI_EN BIT(0) + +#define CSI_IF_CFG_REG 0x4 +#define CSI_IF_CFG_SRC_TYPE_MASK BIT(21) +#define CSI_IF_CFG_SRC_TYPE_PROGRESSED ((0 << 21) & CSI_IF_CFG_SRC_TYPE_MASK) +#define CSI_IF_CFG_SRC_TYPE_INTERLACED ((1 << 21) & CSI_IF_CFG_SRC_TYPE_MASK) +#define CSI_IF_CFG_FPS_DS_EN BIT(20) +#define CSI_IF_CFG_FIELD_MASK BIT(19) +#define CSI_IF_CFG_FIELD_NEGATIVE ((0 << 19) & CSI_IF_CFG_FIELD_MASK) +#define CSI_IF_CFG_FIELD_POSITIVE ((1 << 19) & CSI_IF_CFG_FIELD_MASK) +#define CSI_IF_CFG_VREF_POL_MASK BIT(18) +#define CSI_IF_CFG_VREF_POL_NEGATIVE ((0 << 18) & CSI_IF_CFG_VREF_POL_MASK) +#define CSI_IF_CFG_VREF_POL_POSITIVE ((1 << 18) & CSI_IF_CFG_VREF_POL_MASK) +#define CSI_IF_CFG_HREF_POL_MASK BIT(17) +#define CSI_IF_CFG_HREF_POL_NEGATIVE ((0 << 17) & CSI_IF_CFG_HREF_POL_MASK) +#define CSI_IF_CFG_HREF_POL_POSITIVE ((1 << 17) & CSI_IF_CFG_HREF_POL_MASK) +#define CSI_IF_CFG_CLK_POL_MASK BIT(16) +#define CSI_IF_CFG_CLK_POL_RISING_EDGE ((0 << 16) & CSI_IF_CFG_CLK_POL_MASK) +#define CSI_IF_CFG_CLK_POL_FALLING_EDGE ((1 << 16) & CSI_IF_CFG_CLK_POL_MASK) +#define CSI_IF_CFG_IF_DATA_WIDTH_MASK GENMASK(10, 8) +#define CSI_IF_CFG_IF_DATA_WIDTH_8BIT ((0 << 8) & CSI_IF_CFG_IF_DATA_WIDTH_MASK) +#define CSI_IF_CFG_IF_DATA_WIDTH_10BIT ((1 << 8) & CSI_IF_CFG_IF_DATA_WIDTH_MASK) +#define CSI_IF_CFG_IF_DATA_WIDTH_12BIT ((2 << 8) & CSI_IF_CFG_IF_DATA_WIDTH_MASK) +#define CSI_IF_CFG_MIPI_IF_MASK BIT(7) +#define CSI_IF_CFG_MIPI_IF_CSI (0 << 7) +#define CSI_IF_CFG_MIPI_IF_MIPI BIT(7) +#define CSI_IF_CFG_CSI_IF_MASK GENMASK(4, 0) +#define CSI_IF_CFG_CSI_IF_YUV422_INTLV ((0 << 0) & CSI_IF_CFG_CSI_IF_MASK) +#define CSI_IF_CFG_CSI_IF_YUV422_16BIT ((1 << 0) & CSI_IF_CFG_CSI_IF_MASK) +#define CSI_IF_CFG_CSI_IF_BT656 ((4 << 0) & CSI_IF_CFG_CSI_IF_MASK) +#define CSI_IF_CFG_CSI_IF_BT1120 ((5 << 0) & CSI_IF_CFG_CSI_IF_MASK) + +#define CSI_CAP_REG 0x8 +#define CSI_CAP_CH0_CAP_MASK_MASK GENMASK(5, 2) +#define CSI_CAP_CH0_CAP_MASK(count) (((count) << 2) & CSI_CAP_CH0_CAP_MASK_MASK) +#define CSI_CAP_CH0_VCAP_ON BIT(1) +#define CSI_CAP_CH0_SCAP_ON BIT(0) + +#define CSI_SYNC_CNT_REG 0xc +#define CSI_FIFO_THRS_REG 0x10 +#define CSI_BT656_HEAD_CFG_REG 0x14 +#define CSI_PTN_LEN_REG 0x30 +#define CSI_PTN_ADDR_REG 0x34 +#define CSI_VER_REG 0x3c + +#define CSI_CH_CFG_REG 0x44 +#define CSI_CH_CFG_INPUT_FMT_MASK GENMASK(23, 20) +#define CSI_CH_CFG_INPUT_FMT(fmt) (((fmt) << 20) & CSI_CH_CFG_INPUT_FMT_MASK) +#define CSI_CH_CFG_OUTPUT_FMT_MASK GENMASK(19, 16) +#define CSI_CH_CFG_OUTPUT_FMT(fmt) (((fmt) << 16) & CSI_CH_CFG_OUTPUT_FMT_MASK) +#define CSI_CH_CFG_VFLIP_EN BIT(13) +#define CSI_CH_CFG_HFLIP_EN BIT(12) +#define CSI_CH_CFG_FIELD_SEL_MASK GENMASK(11, 10) +#define CSI_CH_CFG_FIELD_SEL_FIELD0 ((0 << 10) & CSI_CH_CFG_FIELD_SEL_MASK) +#define CSI_CH_CFG_FIELD_SEL_FIELD1 ((1 << 10) & CSI_CH_CFG_FIELD_SEL_MASK) +#define CSI_CH_CFG_FIELD_SEL_BOTH ((2 << 10) & CSI_CH_CFG_FIELD_SEL_MASK) +#define CSI_CH_CFG_INPUT_SEQ_MASK GENMASK(9, 8) +#define CSI_CH_CFG_INPUT_SEQ(seq) (((seq) << 8) & CSI_CH_CFG_INPUT_SEQ_MASK) + +#define CSI_CH_SCALE_REG 0x4c +#define CSI_CH_SCALE_QUART_EN BIT(0) + +#define CSI_CH_F0_BUFA_REG 0x50 + +#define CSI_CH_F1_BUFA_REG 0x58 + +#define CSI_CH_F2_BUFA_REG 0x60 + +#define CSI_CH_STA_REG 0x6c +#define CSI_CH_STA_FIELD_STA_MASK BIT(2) +#define CSI_CH_STA_FIELD_STA_FIELD0 ((0 << 2) & CSI_CH_STA_FIELD_STA_MASK) +#define CSI_CH_STA_FIELD_STA_FIELD1 ((1 << 2) & CSI_CH_STA_FIELD_STA_MASK) +#define CSI_CH_STA_VCAP_STA BIT(1) +#define CSI_CH_STA_SCAP_STA BIT(0) + +#define CSI_CH_INT_EN_REG 0x70 +#define CSI_CH_INT_EN_VS_INT_EN BIT(7) +#define CSI_CH_INT_EN_HB_OF_INT_EN BIT(6) +#define CSI_CH_INT_EN_MUL_ERR_INT_EN BIT(5) +#define CSI_CH_INT_EN_FIFO2_OF_INT_EN BIT(4) +#define CSI_CH_INT_EN_FIFO1_OF_INT_EN BIT(3) +#define CSI_CH_INT_EN_FIFO0_OF_INT_EN BIT(2) +#define CSI_CH_INT_EN_FD_INT_EN BIT(1) +#define CSI_CH_INT_EN_CD_INT_EN BIT(0) + +#define CSI_CH_INT_STA_REG 0x74 +#define CSI_CH_INT_STA_VS_PD BIT(7) +#define CSI_CH_INT_STA_HB_OF_PD BIT(6) +#define CSI_CH_INT_STA_MUL_ERR_PD BIT(5) +#define CSI_CH_INT_STA_FIFO2_OF_PD BIT(4) +#define CSI_CH_INT_STA_FIFO1_OF_PD BIT(3) +#define CSI_CH_INT_STA_FIFO0_OF_PD BIT(2) +#define CSI_CH_INT_STA_FD_PD BIT(1) +#define CSI_CH_INT_STA_CD_PD BIT(0) + +#define CSI_CH_FLD1_VSIZE_REG 0x78 + +#define CSI_CH_HSIZE_REG 0x80 +#define CSI_CH_HSIZE_HOR_LEN_MASK GENMASK(28, 16) +#define CSI_CH_HSIZE_HOR_LEN(len) (((len) << 16) & CSI_CH_HSIZE_HOR_LEN_MASK) +#define CSI_CH_HSIZE_HOR_START_MASK GENMASK(12, 0) +#define CSI_CH_HSIZE_HOR_START(start) (((start) << 0) & CSI_CH_HSIZE_HOR_START_MASK) + +#define CSI_CH_VSIZE_REG 0x84 +#define CSI_CH_VSIZE_VER_LEN_MASK GENMASK(28, 16) +#define CSI_CH_VSIZE_VER_LEN(len) (((len) << 16) & CSI_CH_VSIZE_VER_LEN_MASK) +#define CSI_CH_VSIZE_VER_START_MASK GENMASK(12, 0) +#define CSI_CH_VSIZE_VER_START(start) (((start) << 0) & CSI_CH_VSIZE_VER_START_MASK) + +#define CSI_CH_BUF_LEN_REG 0x88 +#define CSI_CH_BUF_LEN_BUF_LEN_C_MASK GENMASK(29, 16) +#define CSI_CH_BUF_LEN_BUF_LEN_C(len) (((len) << 16) & CSI_CH_BUF_LEN_BUF_LEN_C_MASK) +#define CSI_CH_BUF_LEN_BUF_LEN_Y_MASK GENMASK(13, 0) +#define CSI_CH_BUF_LEN_BUF_LEN_Y(len) (((len) << 0) & CSI_CH_BUF_LEN_BUF_LEN_Y_MASK) + +#define CSI_CH_FLIP_SIZE_REG 0x8c +#define CSI_CH_FLIP_SIZE_VER_LEN_MASK GENMASK(28, 16) +#define CSI_CH_FLIP_SIZE_VER_LEN(len) (((len) << 16) & CSI_CH_FLIP_SIZE_VER_LEN_MASK) +#define CSI_CH_FLIP_SIZE_VALID_LEN_MASK GENMASK(12, 0) +#define CSI_CH_FLIP_SIZE_VALID_LEN(len) (((len) << 0) & CSI_CH_FLIP_SIZE_VALID_LEN_MASK) + +#define CSI_CH_FRM_CLK_CNT_REG 0x90 +#define CSI_CH_ACC_ITNL_CLK_CNT_REG 0x94 +#define CSI_CH_FIFO_STAT_REG 0x98 +#define CSI_CH_PCLK_STAT_REG 0x9c + +/* + * csi input data format + */ +enum csi_input_fmt { + CSI_INPUT_FORMAT_RAW = 0, + CSI_INPUT_FORMAT_YUV422 = 3, + CSI_INPUT_FORMAT_YUV420 = 4, +}; + +/* + * csi output data format + */ +enum csi_output_fmt { + /* only when input format is RAW */ + CSI_FIELD_RAW_8 = 0, + CSI_FIELD_RAW_10 = 1, + CSI_FIELD_RAW_12 = 2, + CSI_FIELD_RGB565 = 4, + CSI_FIELD_RGB888 = 5, + CSI_FIELD_PRGB888 = 6, + CSI_FRAME_RAW_8 = 8, + CSI_FRAME_RAW_10 = 9, + CSI_FRAME_RAW_12 = 10, + CSI_FRAME_RGB565 = 12, + CSI_FRAME_RGB888 = 13, + CSI_FRAME_PRGB888 = 14, + + /* only when input format is YUV422 */ + CSI_FIELD_PLANAR_YUV422 = 0, + CSI_FIELD_PLANAR_YUV420 = 1, + CSI_FRAME_PLANAR_YUV420 = 2, + CSI_FRAME_PLANAR_YUV422 = 3, + CSI_FIELD_UV_CB_YUV422 = 4, + CSI_FIELD_UV_CB_YUV420 = 5, + CSI_FRAME_UV_CB_YUV420 = 6, + CSI_FRAME_UV_CB_YUV422 = 7, + CSI_FIELD_MB_YUV422 = 8, + CSI_FIELD_MB_YUV420 = 9, + CSI_FRAME_MB_YUV420 = 10, + CSI_FRAME_MB_YUV422 = 11, + CSI_FIELD_UV_CB_YUV422_10 = 12, + CSI_FIELD_UV_CB_YUV420_10 = 13, +}; + +/* + * csi YUV input data sequence + */ +enum csi_input_seq { + /* only when input format is YUV422 */ + CSI_INPUT_SEQ_YUYV = 0, + CSI_INPUT_SEQ_YVYU, + CSI_INPUT_SEQ_UYVY, + CSI_INPUT_SEQ_VYUY, +}; + +#endif /* __SUN6I_CSI_REG_H__ */ diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_video.c b/drivers/media/platform/sunxi/sun6i-csi/sun6i_video.c new file mode 100644 index 000000000000..b04300c3811f --- /dev/null +++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_video.c @@ -0,0 +1,679 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2011-2018 Magewell Electronics Co., Ltd. (Nanjing) + * All rights reserved. + * Author: Yong Deng <yong.deng@magewell.com> + */ + +#include <linux/of.h> + +#include <media/v4l2-device.h> +#include <media/v4l2-event.h> +#include <media/v4l2-ioctl.h> +#include <media/v4l2-mc.h> +#include <media/videobuf2-dma-contig.h> +#include <media/videobuf2-v4l2.h> + +#include "sun6i_csi.h" +#include "sun6i_video.h" + +/* This is got from BSP sources. */ +#define MIN_WIDTH (32) +#define MIN_HEIGHT (32) +#define MAX_WIDTH (4800) +#define MAX_HEIGHT (4800) + +struct sun6i_csi_buffer { + struct vb2_v4l2_buffer vb; + struct list_head list; + + dma_addr_t dma_addr; + bool queued_to_csi; +}; + +static const u32 supported_pixformats[] = { + V4L2_PIX_FMT_SBGGR8, + V4L2_PIX_FMT_SGBRG8, + V4L2_PIX_FMT_SGRBG8, + V4L2_PIX_FMT_SRGGB8, + V4L2_PIX_FMT_SBGGR10, + V4L2_PIX_FMT_SGBRG10, + V4L2_PIX_FMT_SGRBG10, + V4L2_PIX_FMT_SRGGB10, + V4L2_PIX_FMT_SBGGR12, + V4L2_PIX_FMT_SGBRG12, + V4L2_PIX_FMT_SGRBG12, + V4L2_PIX_FMT_SRGGB12, + V4L2_PIX_FMT_YUYV, + V4L2_PIX_FMT_YVYU, + V4L2_PIX_FMT_UYVY, + V4L2_PIX_FMT_VYUY, + V4L2_PIX_FMT_HM12, + V4L2_PIX_FMT_NV12, + V4L2_PIX_FMT_NV21, + V4L2_PIX_FMT_YUV420, + V4L2_PIX_FMT_YVU420, + V4L2_PIX_FMT_NV16, + V4L2_PIX_FMT_NV61, + V4L2_PIX_FMT_YUV422P, +}; + +static bool is_pixformat_valid(unsigned int pixformat) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(supported_pixformats); i++) + if (supported_pixformats[i] == pixformat) + return true; + + return false; +} + +static struct v4l2_subdev * +sun6i_video_remote_subdev(struct sun6i_video *video, u32 *pad) +{ + struct media_pad *remote; + + remote = media_entity_remote_pad(&video->pad); + + if (!remote || !is_media_entity_v4l2_subdev(remote->entity)) + return NULL; + + if (pad) + *pad = remote->index; + + return media_entity_to_v4l2_subdev(remote->entity); +} + +static int sun6i_video_queue_setup(struct vb2_queue *vq, + unsigned int *nbuffers, + unsigned int *nplanes, + unsigned int sizes[], + struct device *alloc_devs[]) +{ + struct sun6i_video *video = vb2_get_drv_priv(vq); + unsigned int size = video->fmt.fmt.pix.sizeimage; + + if (*nplanes) + return sizes[0] < size ? -EINVAL : 0; + + *nplanes = 1; + sizes[0] = size; + + return 0; +} + +static int sun6i_video_buffer_prepare(struct vb2_buffer *vb) +{ + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); + struct sun6i_csi_buffer *buf = + container_of(vbuf, struct sun6i_csi_buffer, vb); + struct sun6i_video *video = vb2_get_drv_priv(vb->vb2_queue); + unsigned long size = video->fmt.fmt.pix.sizeimage; + + if (vb2_plane_size(vb, 0) < size) { + v4l2_err(video->vdev.v4l2_dev, "buffer too small (%lu < %lu)\n", + vb2_plane_size(vb, 0), size); + return -EINVAL; + } + + vb2_set_plane_payload(vb, 0, size); + + buf->dma_addr = vb2_dma_contig_plane_dma_addr(vb, 0); + + vbuf->field = video->fmt.fmt.pix.field; + + return 0; +} + +static int sun6i_video_start_streaming(struct vb2_queue *vq, unsigned int count) +{ + struct sun6i_video *video = vb2_get_drv_priv(vq); + struct sun6i_csi_buffer *buf; + struct sun6i_csi_buffer *next_buf; + struct sun6i_csi_config config; + struct v4l2_subdev *subdev; + unsigned long flags; + int ret; + + video->sequence = 0; + + ret = media_pipeline_start(&video->vdev.entity, &video->vdev.pipe); + if (ret < 0) + goto clear_dma_queue; + + if (video->mbus_code == 0) { + ret = -EINVAL; + goto stop_media_pipeline; + } + + subdev = sun6i_video_remote_subdev(video, NULL); + if (!subdev) + goto stop_media_pipeline; + + config.pixelformat = video->fmt.fmt.pix.pixelformat; + config.code = video->mbus_code; + config.field = video->fmt.fmt.pix.field; + config.width = video->fmt.fmt.pix.width; + config.height = video->fmt.fmt.pix.height; + + ret = sun6i_csi_update_config(video->csi, &config); + if (ret < 0) + goto stop_media_pipeline; + + spin_lock_irqsave(&video->dma_queue_lock, flags); + + buf = list_first_entry(&video->dma_queue, + struct sun6i_csi_buffer, list); + buf->queued_to_csi = true; + sun6i_csi_update_buf_addr(video->csi, buf->dma_addr); + + sun6i_csi_set_stream(video->csi, true); + + /* + * CSI will lookup the next dma buffer for next frame before the + * the current frame done IRQ triggered. This is not documented + * but reported by OndÅ™ej Jirman. + * The BSP code has workaround for this too. It skip to mark the + * first buffer as frame done for VB2 and pass the second buffer + * to CSI in the first frame done ISR call. Then in second frame + * done ISR call, it mark the first buffer as frame done for VB2 + * and pass the third buffer to CSI. And so on. The bad thing is + * that the first buffer will be written twice and the first frame + * is dropped even the queued buffer is sufficient. + * So, I make some improvement here. Pass the next buffer to CSI + * just follow starting the CSI. In this case, the first frame + * will be stored in first buffer, second frame in second buffer. + * This method is used to avoid dropping the first frame, it + * would also drop frame when lacking of queued buffer. + */ + next_buf = list_next_entry(buf, list); + next_buf->queued_to_csi = true; + sun6i_csi_update_buf_addr(video->csi, next_buf->dma_addr); + + spin_unlock_irqrestore(&video->dma_queue_lock, flags); + + ret = v4l2_subdev_call(subdev, video, s_stream, 1); + if (ret && ret != -ENOIOCTLCMD) + goto stop_csi_stream; + + return 0; + +stop_csi_stream: + sun6i_csi_set_stream(video->csi, false); +stop_media_pipeline: + media_pipeline_stop(&video->vdev.entity); +clear_dma_queue: + spin_lock_irqsave(&video->dma_queue_lock, flags); + list_for_each_entry(buf, &video->dma_queue, list) + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED); + INIT_LIST_HEAD(&video->dma_queue); + spin_unlock_irqrestore(&video->dma_queue_lock, flags); + + return ret; +} + +static void sun6i_video_stop_streaming(struct vb2_queue *vq) +{ + struct sun6i_video *video = vb2_get_drv_priv(vq); + struct v4l2_subdev *subdev; + unsigned long flags; + struct sun6i_csi_buffer *buf; + + subdev = sun6i_video_remote_subdev(video, NULL); + if (subdev) + v4l2_subdev_call(subdev, video, s_stream, 0); + + sun6i_csi_set_stream(video->csi, false); + + media_pipeline_stop(&video->vdev.entity); + + /* Release all active buffers */ + spin_lock_irqsave(&video->dma_queue_lock, flags); + list_for_each_entry(buf, &video->dma_queue, list) + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); + INIT_LIST_HEAD(&video->dma_queue); + spin_unlock_irqrestore(&video->dma_queue_lock, flags); +} + +static void sun6i_video_buffer_queue(struct vb2_buffer *vb) +{ + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); + struct sun6i_csi_buffer *buf = + container_of(vbuf, struct sun6i_csi_buffer, vb); + struct sun6i_video *video = vb2_get_drv_priv(vb->vb2_queue); + unsigned long flags; + + spin_lock_irqsave(&video->dma_queue_lock, flags); + buf->queued_to_csi = false; + list_add_tail(&buf->list, &video->dma_queue); + spin_unlock_irqrestore(&video->dma_queue_lock, flags); +} + +void sun6i_video_frame_done(struct sun6i_video *video) +{ + struct sun6i_csi_buffer *buf; + struct sun6i_csi_buffer *next_buf; + struct vb2_v4l2_buffer *vbuf; + + spin_lock(&video->dma_queue_lock); + + buf = list_first_entry(&video->dma_queue, + struct sun6i_csi_buffer, list); + if (list_is_last(&buf->list, &video->dma_queue)) { + dev_dbg(video->csi->dev, "Frame dropped!\n"); + goto unlock; + } + + next_buf = list_next_entry(buf, list); + /* If a new buffer (#next_buf) had not been queued to CSI, the old + * buffer (#buf) is still holding by CSI for storing the next + * frame. So, we queue a new buffer (#next_buf) to CSI then wait + * for next ISR call. + */ + if (!next_buf->queued_to_csi) { + next_buf->queued_to_csi = true; + sun6i_csi_update_buf_addr(video->csi, next_buf->dma_addr); + dev_dbg(video->csi->dev, "Frame dropped!\n"); + goto unlock; + } + + list_del(&buf->list); + vbuf = &buf->vb; + vbuf->vb2_buf.timestamp = ktime_get_ns(); + vbuf->sequence = video->sequence; + vb2_buffer_done(&vbuf->vb2_buf, VB2_BUF_STATE_DONE); + + /* Prepare buffer for next frame but one. */ + if (!list_is_last(&next_buf->list, &video->dma_queue)) { + next_buf = list_next_entry(next_buf, list); + next_buf->queued_to_csi = true; + sun6i_csi_update_buf_addr(video->csi, next_buf->dma_addr); + } else { + dev_dbg(video->csi->dev, "Next frame will be dropped!\n"); + } + +unlock: + video->sequence++; + spin_unlock(&video->dma_queue_lock); +} + +static const struct vb2_ops sun6i_csi_vb2_ops = { + .queue_setup = sun6i_video_queue_setup, + .wait_prepare = vb2_ops_wait_prepare, + .wait_finish = vb2_ops_wait_finish, + .buf_prepare = sun6i_video_buffer_prepare, + .start_streaming = sun6i_video_start_streaming, + .stop_streaming = sun6i_video_stop_streaming, + .buf_queue = sun6i_video_buffer_queue, +}; + +static int vidioc_querycap(struct file *file, void *priv, + struct v4l2_capability *cap) +{ + struct sun6i_video *video = video_drvdata(file); + + strscpy(cap->driver, "sun6i-video", sizeof(cap->driver)); + strscpy(cap->card, video->vdev.name, sizeof(cap->card)); + snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s", + video->csi->dev->of_node->name); + + return 0; +} + +static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_fmtdesc *f) +{ + u32 index = f->index; + + if (index >= ARRAY_SIZE(supported_pixformats)) + return -EINVAL; + + f->pixelformat = supported_pixformats[index]; + + return 0; +} + +static int vidioc_g_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *fmt) +{ + struct sun6i_video *video = video_drvdata(file); + + *fmt = video->fmt; + + return 0; +} + +static int sun6i_video_try_fmt(struct sun6i_video *video, + struct v4l2_format *f) +{ + struct v4l2_pix_format *pixfmt = &f->fmt.pix; + int bpp; + + if (!is_pixformat_valid(pixfmt->pixelformat)) + pixfmt->pixelformat = supported_pixformats[0]; + + v4l_bound_align_image(&pixfmt->width, MIN_WIDTH, MAX_WIDTH, 1, + &pixfmt->height, MIN_HEIGHT, MAX_WIDTH, 1, 1); + + bpp = sun6i_csi_get_bpp(pixfmt->pixelformat); + pixfmt->bytesperline = (pixfmt->width * bpp) >> 3; + pixfmt->sizeimage = pixfmt->bytesperline * pixfmt->height; + + if (pixfmt->field == V4L2_FIELD_ANY) + pixfmt->field = V4L2_FIELD_NONE; + + pixfmt->colorspace = V4L2_COLORSPACE_RAW; + pixfmt->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; + pixfmt->quantization = V4L2_QUANTIZATION_DEFAULT; + pixfmt->xfer_func = V4L2_XFER_FUNC_DEFAULT; + + return 0; +} + +static int sun6i_video_set_fmt(struct sun6i_video *video, struct v4l2_format *f) +{ + int ret; + + ret = sun6i_video_try_fmt(video, f); + if (ret) + return ret; + + video->fmt = *f; + + return 0; +} + +static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct sun6i_video *video = video_drvdata(file); + + if (vb2_is_busy(&video->vb2_vidq)) + return -EBUSY; + + return sun6i_video_set_fmt(video, f); +} + +static int vidioc_try_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct sun6i_video *video = video_drvdata(file); + + return sun6i_video_try_fmt(video, f); +} + +static int vidioc_enum_input(struct file *file, void *fh, + struct v4l2_input *inp) +{ + if (inp->index != 0) + return -EINVAL; + + strlcpy(inp->name, "camera", sizeof(inp->name)); + inp->type = V4L2_INPUT_TYPE_CAMERA; + + return 0; +} + +static int vidioc_g_input(struct file *file, void *fh, unsigned int *i) +{ + *i = 0; + + return 0; +} + +static int vidioc_s_input(struct file *file, void *fh, unsigned int i) +{ + if (i != 0) + return -EINVAL; + + return 0; +} + +static const struct v4l2_ioctl_ops sun6i_video_ioctl_ops = { + .vidioc_querycap = vidioc_querycap, + .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, + .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, + .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, + .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, + + .vidioc_enum_input = vidioc_enum_input, + .vidioc_s_input = vidioc_s_input, + .vidioc_g_input = vidioc_g_input, + + .vidioc_reqbufs = vb2_ioctl_reqbufs, + .vidioc_querybuf = vb2_ioctl_querybuf, + .vidioc_qbuf = vb2_ioctl_qbuf, + .vidioc_expbuf = vb2_ioctl_expbuf, + .vidioc_dqbuf = vb2_ioctl_dqbuf, + .vidioc_create_bufs = vb2_ioctl_create_bufs, + .vidioc_prepare_buf = vb2_ioctl_prepare_buf, + .vidioc_streamon = vb2_ioctl_streamon, + .vidioc_streamoff = vb2_ioctl_streamoff, + + .vidioc_log_status = v4l2_ctrl_log_status, + .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, + .vidioc_unsubscribe_event = v4l2_event_unsubscribe, +}; + +/* ----------------------------------------------------------------------------- + * V4L2 file operations + */ +static int sun6i_video_open(struct file *file) +{ + struct sun6i_video *video = video_drvdata(file); + int ret; + + if (mutex_lock_interruptible(&video->lock)) + return -ERESTARTSYS; + + ret = v4l2_fh_open(file); + if (ret < 0) + goto unlock; + + ret = v4l2_pipeline_pm_use(&video->vdev.entity, 1); + if (ret < 0) + goto fh_release; + + /* check if already powered */ + if (!v4l2_fh_is_singular_file(file)) + goto unlock; + + ret = sun6i_csi_set_power(video->csi, true); + if (ret < 0) + goto fh_release; + + mutex_unlock(&video->lock); + return 0; + +fh_release: + v4l2_fh_release(file); +unlock: + mutex_unlock(&video->lock); + return ret; +} + +static int sun6i_video_close(struct file *file) +{ + struct sun6i_video *video = video_drvdata(file); + bool last_fh; + + mutex_lock(&video->lock); + + last_fh = v4l2_fh_is_singular_file(file); + + _vb2_fop_release(file, NULL); + + v4l2_pipeline_pm_use(&video->vdev.entity, 0); + + if (last_fh) + sun6i_csi_set_power(video->csi, false); + + mutex_unlock(&video->lock); + + return 0; +} + +static const struct v4l2_file_operations sun6i_video_fops = { + .owner = THIS_MODULE, + .open = sun6i_video_open, + .release = sun6i_video_close, + .unlocked_ioctl = video_ioctl2, + .mmap = vb2_fop_mmap, + .poll = vb2_fop_poll +}; + +/* ----------------------------------------------------------------------------- + * Media Operations + */ +static int sun6i_video_link_validate_get_format(struct media_pad *pad, + struct v4l2_subdev_format *fmt) +{ + if (is_media_entity_v4l2_subdev(pad->entity)) { + struct v4l2_subdev *sd = + media_entity_to_v4l2_subdev(pad->entity); + + fmt->which = V4L2_SUBDEV_FORMAT_ACTIVE; + fmt->pad = pad->index; + return v4l2_subdev_call(sd, pad, get_fmt, NULL, fmt); + } + + return -EINVAL; +} + +static int sun6i_video_link_validate(struct media_link *link) +{ + struct video_device *vdev = container_of(link->sink->entity, + struct video_device, entity); + struct sun6i_video *video = video_get_drvdata(vdev); + struct v4l2_subdev_format source_fmt; + int ret; + + video->mbus_code = 0; + + if (!media_entity_remote_pad(link->sink->entity->pads)) { + dev_info(video->csi->dev, + "video node %s pad not connected\n", vdev->name); + return -ENOLINK; + } + + ret = sun6i_video_link_validate_get_format(link->source, &source_fmt); + if (ret < 0) + return ret; + + if (!sun6i_csi_is_format_supported(video->csi, + video->fmt.fmt.pix.pixelformat, + source_fmt.format.code)) { + dev_err(video->csi->dev, + "Unsupported pixformat: 0x%x with mbus code: 0x%x!\n", + video->fmt.fmt.pix.pixelformat, + source_fmt.format.code); + return -EPIPE; + } + + if (source_fmt.format.width != video->fmt.fmt.pix.width || + source_fmt.format.height != video->fmt.fmt.pix.height) { + dev_err(video->csi->dev, + "Wrong width or height %ux%u (%ux%u expected)\n", + video->fmt.fmt.pix.width, video->fmt.fmt.pix.height, + source_fmt.format.width, source_fmt.format.height); + return -EPIPE; + } + + video->mbus_code = source_fmt.format.code; + + return 0; +} + +static const struct media_entity_operations sun6i_video_media_ops = { + .link_validate = sun6i_video_link_validate +}; + +int sun6i_video_init(struct sun6i_video *video, struct sun6i_csi *csi, + const char *name) +{ + struct video_device *vdev = &video->vdev; + struct vb2_queue *vidq = &video->vb2_vidq; + struct v4l2_format fmt = { 0 }; + int ret; + + video->csi = csi; + + /* Initialize the media entity... */ + video->pad.flags = MEDIA_PAD_FL_SINK | MEDIA_PAD_FL_MUST_CONNECT; + vdev->entity.ops = &sun6i_video_media_ops; + ret = media_entity_pads_init(&vdev->entity, 1, &video->pad); + if (ret < 0) + return ret; + + mutex_init(&video->lock); + + INIT_LIST_HEAD(&video->dma_queue); + spin_lock_init(&video->dma_queue_lock); + + video->sequence = 0; + + /* Setup default format */ + fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + fmt.fmt.pix.pixelformat = supported_pixformats[0]; + fmt.fmt.pix.width = 1280; + fmt.fmt.pix.height = 720; + fmt.fmt.pix.field = V4L2_FIELD_NONE; + sun6i_video_set_fmt(video, &fmt); + + /* Initialize videobuf2 queue */ + vidq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + vidq->io_modes = VB2_MMAP | VB2_DMABUF; + vidq->drv_priv = video; + vidq->buf_struct_size = sizeof(struct sun6i_csi_buffer); + vidq->ops = &sun6i_csi_vb2_ops; + vidq->mem_ops = &vb2_dma_contig_memops; + vidq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + vidq->lock = &video->lock; + /* Make sure non-dropped frame */ + vidq->min_buffers_needed = 3; + vidq->dev = csi->dev; + + ret = vb2_queue_init(vidq); + if (ret) { + v4l2_err(&csi->v4l2_dev, "vb2_queue_init failed: %d\n", ret); + goto clean_entity; + } + + /* Register video device */ + strlcpy(vdev->name, name, sizeof(vdev->name)); + vdev->release = video_device_release_empty; + vdev->fops = &sun6i_video_fops; + vdev->ioctl_ops = &sun6i_video_ioctl_ops; + vdev->vfl_type = VFL_TYPE_GRABBER; + vdev->vfl_dir = VFL_DIR_RX; + vdev->v4l2_dev = &csi->v4l2_dev; + vdev->queue = vidq; + vdev->lock = &video->lock; + vdev->device_caps = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_CAPTURE; + video_set_drvdata(vdev, video); + + ret = video_register_device(vdev, VFL_TYPE_GRABBER, -1); + if (ret < 0) { + v4l2_err(&csi->v4l2_dev, + "video_register_device failed: %d\n", ret); + goto release_vb2; + } + + return 0; + +release_vb2: + vb2_queue_release(&video->vb2_vidq); +clean_entity: + media_entity_cleanup(&video->vdev.entity); + mutex_destroy(&video->lock); + return ret; +} + +void sun6i_video_cleanup(struct sun6i_video *video) +{ + video_unregister_device(&video->vdev); + media_entity_cleanup(&video->vdev.entity); + vb2_queue_release(&video->vb2_vidq); + mutex_destroy(&video->lock); +} diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_video.h b/drivers/media/platform/sunxi/sun6i-csi/sun6i_video.h new file mode 100644 index 000000000000..b9cd919c24ac --- /dev/null +++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_video.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2011-2018 Magewell Electronics Co., Ltd. (Nanjing) + * All rights reserved. + * Author: Yong Deng <yong.deng@magewell.com> + */ + +#ifndef __SUN6I_VIDEO_H__ +#define __SUN6I_VIDEO_H__ + +#include <media/v4l2-dev.h> +#include <media/videobuf2-core.h> + +struct sun6i_csi; + +struct sun6i_video { + struct video_device vdev; + struct media_pad pad; + struct sun6i_csi *csi; + + struct mutex lock; + + struct vb2_queue vb2_vidq; + spinlock_t dma_queue_lock; + struct list_head dma_queue; + + unsigned int sequence; + struct v4l2_format fmt; + u32 mbus_code; +}; + +int sun6i_video_init(struct sun6i_video *video, struct sun6i_csi *csi, + const char *name); +void sun6i_video_cleanup(struct sun6i_video *video); + +void sun6i_video_frame_done(struct sun6i_video *video); + +#endif /* __SUN6I_VIDEO_H__ */ diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c index 95a093f41905..fc3c212b96e1 100644 --- a/drivers/media/platform/ti-vpe/cal.c +++ b/drivers/media/platform/ti-vpe/cal.c @@ -1615,7 +1615,7 @@ of_get_next_port(const struct device_node *parent, return NULL; } prev = port; - } while (of_node_cmp(port->name, "port") != 0); + } while (!of_node_name_eq(port, "port")); } return port; @@ -1635,7 +1635,7 @@ of_get_next_endpoint(const struct device_node *parent, if (!ep) return NULL; prev = ep; - } while (of_node_cmp(ep->name, "endpoint") != 0); + } while (!of_node_name_eq(ep, "endpoint")); return ep; } diff --git a/drivers/media/platform/vicodec/codec-fwht.c b/drivers/media/platform/vicodec/codec-fwht.c index 36656031b295..5630f1dc45e6 100644 --- a/drivers/media/platform/vicodec/codec-fwht.c +++ b/drivers/media/platform/vicodec/codec-fwht.c @@ -753,31 +753,49 @@ u32 fwht_encode_frame(struct fwht_raw_frame *frm, __be16 *rlco = cf->rlc_data; __be16 *rlco_max; u32 encoding; - u32 chroma_h = frm->height / frm->height_div; - u32 chroma_w = frm->width / frm->width_div; - unsigned int chroma_size = chroma_h * chroma_w; rlco_max = rlco + size / 2 - 256; encoding = encode_plane(frm->luma, ref_frm->luma, &rlco, rlco_max, cf, frm->height, frm->width, - frm->luma_step, is_intra, next_is_intra); + frm->luma_alpha_step, is_intra, next_is_intra); if (encoding & FWHT_FRAME_UNENCODED) encoding |= FWHT_LUMA_UNENCODED; encoding &= ~FWHT_FRAME_UNENCODED; - rlco_max = rlco + chroma_size / 2 - 256; - encoding |= encode_plane(frm->cb, ref_frm->cb, &rlco, rlco_max, cf, - chroma_h, chroma_w, - frm->chroma_step, is_intra, next_is_intra); - if (encoding & FWHT_FRAME_UNENCODED) - encoding |= FWHT_CB_UNENCODED; - encoding &= ~FWHT_FRAME_UNENCODED; - rlco_max = rlco + chroma_size / 2 - 256; - encoding |= encode_plane(frm->cr, ref_frm->cr, &rlco, rlco_max, cf, - chroma_h, chroma_w, - frm->chroma_step, is_intra, next_is_intra); - if (encoding & FWHT_FRAME_UNENCODED) - encoding |= FWHT_CR_UNENCODED; - encoding &= ~FWHT_FRAME_UNENCODED; + + if (frm->components_num >= 3) { + u32 chroma_h = frm->height / frm->height_div; + u32 chroma_w = frm->width / frm->width_div; + unsigned int chroma_size = chroma_h * chroma_w; + + rlco_max = rlco + chroma_size / 2 - 256; + encoding |= encode_plane(frm->cb, ref_frm->cb, &rlco, rlco_max, + cf, chroma_h, chroma_w, + frm->chroma_step, + is_intra, next_is_intra); + if (encoding & FWHT_FRAME_UNENCODED) + encoding |= FWHT_CB_UNENCODED; + encoding &= ~FWHT_FRAME_UNENCODED; + rlco_max = rlco + chroma_size / 2 - 256; + encoding |= encode_plane(frm->cr, ref_frm->cr, &rlco, rlco_max, + cf, chroma_h, chroma_w, + frm->chroma_step, + is_intra, next_is_intra); + if (encoding & FWHT_FRAME_UNENCODED) + encoding |= FWHT_CR_UNENCODED; + encoding &= ~FWHT_FRAME_UNENCODED; + } + + if (frm->components_num == 4) { + rlco_max = rlco + size / 2 - 256; + encoding = encode_plane(frm->alpha, ref_frm->alpha, &rlco, + rlco_max, cf, frm->height, frm->width, + frm->luma_alpha_step, + is_intra, next_is_intra); + if (encoding & FWHT_FRAME_UNENCODED) + encoding |= FWHT_ALPHA_UNENCODED; + encoding &= ~FWHT_FRAME_UNENCODED; + } + cf->size = (rlco - cf->rlc_data) * sizeof(*rlco); return encoding; } @@ -836,20 +854,28 @@ static void decode_plane(struct fwht_cframe *cf, const __be16 **rlco, u8 *ref, } void fwht_decode_frame(struct fwht_cframe *cf, struct fwht_raw_frame *ref, - u32 hdr_flags) + u32 hdr_flags, unsigned int components_num) { const __be16 *rlco = cf->rlc_data; - u32 h = cf->height / 2; - u32 w = cf->width / 2; - if (hdr_flags & FWHT_FL_CHROMA_FULL_HEIGHT) - h *= 2; - if (hdr_flags & FWHT_FL_CHROMA_FULL_WIDTH) - w *= 2; decode_plane(cf, &rlco, ref->luma, cf->height, cf->width, hdr_flags & FWHT_FL_LUMA_IS_UNCOMPRESSED); - decode_plane(cf, &rlco, ref->cb, h, w, - hdr_flags & FWHT_FL_CB_IS_UNCOMPRESSED); - decode_plane(cf, &rlco, ref->cr, h, w, - hdr_flags & FWHT_FL_CR_IS_UNCOMPRESSED); + + if (components_num >= 3) { + u32 h = cf->height; + u32 w = cf->width; + + if (!(hdr_flags & FWHT_FL_CHROMA_FULL_HEIGHT)) + h /= 2; + if (!(hdr_flags & FWHT_FL_CHROMA_FULL_WIDTH)) + w /= 2; + decode_plane(cf, &rlco, ref->cb, h, w, + hdr_flags & FWHT_FL_CB_IS_UNCOMPRESSED); + decode_plane(cf, &rlco, ref->cr, h, w, + hdr_flags & FWHT_FL_CR_IS_UNCOMPRESSED); + } + + if (components_num == 4) + decode_plane(cf, &rlco, ref->alpha, cf->height, cf->width, + hdr_flags & FWHT_FL_ALPHA_IS_UNCOMPRESSED); } diff --git a/drivers/media/platform/vicodec/codec-fwht.h b/drivers/media/platform/vicodec/codec-fwht.h index 3e9391fec5fe..90ff8962fca7 100644 --- a/drivers/media/platform/vicodec/codec-fwht.h +++ b/drivers/media/platform/vicodec/codec-fwht.h @@ -56,7 +56,7 @@ #define FWHT_MAGIC1 0x4f4f4f4f #define FWHT_MAGIC2 0xffffffff -#define FWHT_VERSION 1 +#define FWHT_VERSION 2 /* Set if this is an interlaced format */ #define FWHT_FL_IS_INTERLACED BIT(0) @@ -75,6 +75,11 @@ #define FWHT_FL_CR_IS_UNCOMPRESSED BIT(6) #define FWHT_FL_CHROMA_FULL_HEIGHT BIT(7) #define FWHT_FL_CHROMA_FULL_WIDTH BIT(8) +#define FWHT_FL_ALPHA_IS_UNCOMPRESSED BIT(9) + +/* A 4-values flag - the number of components - 1 */ +#define FWHT_FL_COMPONENTS_NUM_MSK GENMASK(17, 16) +#define FWHT_FL_COMPONENTS_NUM_OFFSET 16 struct fwht_cframe_hdr { u32 magic1; @@ -104,9 +109,10 @@ struct fwht_raw_frame { unsigned int width, height; unsigned int width_div; unsigned int height_div; - unsigned int luma_step; + unsigned int luma_alpha_step; unsigned int chroma_step; - u8 *luma, *cb, *cr; + unsigned int components_num; + u8 *luma, *cb, *cr, *alpha; }; #define FWHT_FRAME_PCODED BIT(0) @@ -114,12 +120,13 @@ struct fwht_raw_frame { #define FWHT_LUMA_UNENCODED BIT(2) #define FWHT_CB_UNENCODED BIT(3) #define FWHT_CR_UNENCODED BIT(4) +#define FWHT_ALPHA_UNENCODED BIT(5) u32 fwht_encode_frame(struct fwht_raw_frame *frm, struct fwht_raw_frame *ref_frm, struct fwht_cframe *cf, bool is_intra, bool next_is_intra); void fwht_decode_frame(struct fwht_cframe *cf, struct fwht_raw_frame *ref, - u32 hdr_flags); + u32 hdr_flags, unsigned int components_num); #endif diff --git a/drivers/media/platform/vicodec/codec-v4l2-fwht.c b/drivers/media/platform/vicodec/codec-v4l2-fwht.c index e5b68fb38aac..8cb0212df67f 100644 --- a/drivers/media/platform/vicodec/codec-v4l2-fwht.c +++ b/drivers/media/platform/vicodec/codec-v4l2-fwht.c @@ -11,27 +11,30 @@ #include "codec-v4l2-fwht.h" static const struct v4l2_fwht_pixfmt_info v4l2_fwht_pixfmts[] = { - { V4L2_PIX_FMT_YUV420, 1, 3, 2, 1, 1, 2, 2 }, - { V4L2_PIX_FMT_YVU420, 1, 3, 2, 1, 1, 2, 2 }, - { V4L2_PIX_FMT_YUV422P, 1, 2, 1, 1, 1, 2, 1 }, - { V4L2_PIX_FMT_NV12, 1, 3, 2, 1, 2, 2, 2 }, - { V4L2_PIX_FMT_NV21, 1, 3, 2, 1, 2, 2, 2 }, - { V4L2_PIX_FMT_NV16, 1, 2, 1, 1, 2, 2, 1 }, - { V4L2_PIX_FMT_NV61, 1, 2, 1, 1, 2, 2, 1 }, - { V4L2_PIX_FMT_NV24, 1, 3, 1, 1, 2, 1, 1 }, - { V4L2_PIX_FMT_NV42, 1, 3, 1, 1, 2, 1, 1 }, - { V4L2_PIX_FMT_YUYV, 2, 2, 1, 2, 4, 2, 1 }, - { V4L2_PIX_FMT_YVYU, 2, 2, 1, 2, 4, 2, 1 }, - { V4L2_PIX_FMT_UYVY, 2, 2, 1, 2, 4, 2, 1 }, - { V4L2_PIX_FMT_VYUY, 2, 2, 1, 2, 4, 2, 1 }, - { V4L2_PIX_FMT_BGR24, 3, 3, 1, 3, 3, 1, 1 }, - { V4L2_PIX_FMT_RGB24, 3, 3, 1, 3, 3, 1, 1 }, - { V4L2_PIX_FMT_HSV24, 3, 3, 1, 3, 3, 1, 1 }, - { V4L2_PIX_FMT_BGR32, 4, 4, 1, 4, 4, 1, 1 }, - { V4L2_PIX_FMT_XBGR32, 4, 4, 1, 4, 4, 1, 1 }, - { V4L2_PIX_FMT_RGB32, 4, 4, 1, 4, 4, 1, 1 }, - { V4L2_PIX_FMT_XRGB32, 4, 4, 1, 4, 4, 1, 1 }, - { V4L2_PIX_FMT_HSV32, 4, 4, 1, 4, 4, 1, 1 }, + { V4L2_PIX_FMT_YUV420, 1, 3, 2, 1, 1, 2, 2, 3}, + { V4L2_PIX_FMT_YVU420, 1, 3, 2, 1, 1, 2, 2, 3}, + { V4L2_PIX_FMT_YUV422P, 1, 2, 1, 1, 1, 2, 1, 3}, + { V4L2_PIX_FMT_NV12, 1, 3, 2, 1, 2, 2, 2, 3}, + { V4L2_PIX_FMT_NV21, 1, 3, 2, 1, 2, 2, 2, 3}, + { V4L2_PIX_FMT_NV16, 1, 2, 1, 1, 2, 2, 1, 3}, + { V4L2_PIX_FMT_NV61, 1, 2, 1, 1, 2, 2, 1, 3}, + { V4L2_PIX_FMT_NV24, 1, 3, 1, 1, 2, 1, 1, 3}, + { V4L2_PIX_FMT_NV42, 1, 3, 1, 1, 2, 1, 1, 3}, + { V4L2_PIX_FMT_YUYV, 2, 2, 1, 2, 4, 2, 1, 3}, + { V4L2_PIX_FMT_YVYU, 2, 2, 1, 2, 4, 2, 1, 3}, + { V4L2_PIX_FMT_UYVY, 2, 2, 1, 2, 4, 2, 1, 3}, + { V4L2_PIX_FMT_VYUY, 2, 2, 1, 2, 4, 2, 1, 3}, + { V4L2_PIX_FMT_BGR24, 3, 3, 1, 3, 3, 1, 1, 3}, + { V4L2_PIX_FMT_RGB24, 3, 3, 1, 3, 3, 1, 1, 3}, + { V4L2_PIX_FMT_HSV24, 3, 3, 1, 3, 3, 1, 1, 3}, + { V4L2_PIX_FMT_BGR32, 4, 4, 1, 4, 4, 1, 1, 3}, + { V4L2_PIX_FMT_XBGR32, 4, 4, 1, 4, 4, 1, 1, 3}, + { V4L2_PIX_FMT_RGB32, 4, 4, 1, 4, 4, 1, 1, 3}, + { V4L2_PIX_FMT_XRGB32, 4, 4, 1, 4, 4, 1, 1, 3}, + { V4L2_PIX_FMT_HSV32, 4, 4, 1, 4, 4, 1, 1, 3}, + { V4L2_PIX_FMT_ARGB32, 4, 4, 1, 4, 4, 1, 1, 4}, + { V4L2_PIX_FMT_ABGR32, 4, 4, 1, 4, 4, 1, 1, 4}, + { V4L2_PIX_FMT_GREY, 1, 1, 1, 1, 0, 1, 1, 1}, }; const struct v4l2_fwht_pixfmt_info *v4l2_fwht_find_pixfmt(u32 pixelformat) @@ -68,10 +71,16 @@ int v4l2_fwht_encode(struct v4l2_fwht_state *state, u8 *p_in, u8 *p_out) rf.luma = p_in; rf.width_div = info->width_div; rf.height_div = info->height_div; - rf.luma_step = info->luma_step; + rf.luma_alpha_step = info->luma_alpha_step; rf.chroma_step = info->chroma_step; + rf.alpha = NULL; + rf.components_num = info->components_num; switch (info->id) { + case V4L2_PIX_FMT_GREY: + rf.cb = NULL; + rf.cr = NULL; + break; case V4L2_PIX_FMT_YUV420: rf.cb = rf.luma + size; rf.cr = rf.cb + size / 4; @@ -138,6 +147,18 @@ int v4l2_fwht_encode(struct v4l2_fwht_state *state, u8 *p_in, u8 *p_out) rf.cr = rf.cb + 2; rf.luma++; break; + case V4L2_PIX_FMT_ARGB32: + rf.alpha = rf.luma; + rf.cr = rf.luma + 1; + rf.cb = rf.cr + 2; + rf.luma += 2; + break; + case V4L2_PIX_FMT_ABGR32: + rf.cb = rf.luma; + rf.cr = rf.cb + 2; + rf.luma++; + rf.alpha = rf.cr + 1; + break; default: return -EINVAL; } @@ -162,12 +183,15 @@ int v4l2_fwht_encode(struct v4l2_fwht_state *state, u8 *p_in, u8 *p_out) p_hdr->version = htonl(FWHT_VERSION); p_hdr->width = htonl(cf.width); p_hdr->height = htonl(cf.height); + flags |= (info->components_num - 1) << FWHT_FL_COMPONENTS_NUM_OFFSET; if (encoding & FWHT_LUMA_UNENCODED) flags |= FWHT_FL_LUMA_IS_UNCOMPRESSED; if (encoding & FWHT_CB_UNENCODED) flags |= FWHT_FL_CB_IS_UNCOMPRESSED; if (encoding & FWHT_CR_UNENCODED) flags |= FWHT_FL_CR_IS_UNCOMPRESSED; + if (encoding & FWHT_ALPHA_UNENCODED) + flags |= FWHT_FL_ALPHA_IS_UNCOMPRESSED; if (rf.height_div == 1) flags |= FWHT_FL_CHROMA_FULL_HEIGHT; if (rf.width_div == 1) @@ -192,6 +216,8 @@ int v4l2_fwht_decode(struct v4l2_fwht_state *state, u8 *p_in, u8 *p_out) struct fwht_cframe_hdr *p_hdr; struct fwht_cframe cf; u8 *p; + unsigned int components_num = 3; + unsigned int version; if (!state->info) return -EINVAL; @@ -199,16 +225,16 @@ int v4l2_fwht_decode(struct v4l2_fwht_state *state, u8 *p_in, u8 *p_out) p_hdr = (struct fwht_cframe_hdr *)p_in; cf.width = ntohl(p_hdr->width); cf.height = ntohl(p_hdr->height); - flags = ntohl(p_hdr->flags); - state->colorspace = ntohl(p_hdr->colorspace); - state->xfer_func = ntohl(p_hdr->xfer_func); - state->ycbcr_enc = ntohl(p_hdr->ycbcr_enc); - state->quantization = ntohl(p_hdr->quantization); - cf.rlc_data = (__be16 *)(p_in + sizeof(*p_hdr)); + + version = ntohl(p_hdr->version); + if (!version || version > FWHT_VERSION) { + pr_err("version %d is not supported, current version is %d\n", + version, FWHT_VERSION); + return -EINVAL; + } if (p_hdr->magic1 != FWHT_MAGIC1 || p_hdr->magic2 != FWHT_MAGIC2 || - ntohl(p_hdr->version) != FWHT_VERSION || (cf.width & 7) || (cf.height & 7)) return -EINVAL; @@ -216,14 +242,34 @@ int v4l2_fwht_decode(struct v4l2_fwht_state *state, u8 *p_in, u8 *p_out) if (cf.width != state->width || cf.height != state->height) return -EINVAL; + flags = ntohl(p_hdr->flags); + + if (version == FWHT_VERSION) { + components_num = 1 + ((flags & FWHT_FL_COMPONENTS_NUM_MSK) >> + FWHT_FL_COMPONENTS_NUM_OFFSET); + } + + state->colorspace = ntohl(p_hdr->colorspace); + state->xfer_func = ntohl(p_hdr->xfer_func); + state->ycbcr_enc = ntohl(p_hdr->ycbcr_enc); + state->quantization = ntohl(p_hdr->quantization); + cf.rlc_data = (__be16 *)(p_in + sizeof(*p_hdr)); + if (!(flags & FWHT_FL_CHROMA_FULL_WIDTH)) chroma_size /= 2; if (!(flags & FWHT_FL_CHROMA_FULL_HEIGHT)) chroma_size /= 2; - fwht_decode_frame(&cf, &state->ref_frame, flags); + fwht_decode_frame(&cf, &state->ref_frame, flags, components_num); + /* + * TODO - handle the case where the compressed stream encodes a + * different format than the requested decoded format. + */ switch (state->info->id) { + case V4L2_PIX_FMT_GREY: + memcpy(p_out, state->ref_frame.luma, size); + break; case V4L2_PIX_FMT_YUV420: case V4L2_PIX_FMT_YUV422P: memcpy(p_out, state->ref_frame.luma, size); @@ -325,6 +371,22 @@ int v4l2_fwht_decode(struct v4l2_fwht_state *state, u8 *p_in, u8 *p_out) *p++ = 0; } break; + case V4L2_PIX_FMT_ARGB32: + for (i = 0, p = p_out; i < size; i++) { + *p++ = state->ref_frame.alpha[i]; + *p++ = state->ref_frame.cr[i]; + *p++ = state->ref_frame.luma[i]; + *p++ = state->ref_frame.cb[i]; + } + break; + case V4L2_PIX_FMT_ABGR32: + for (i = 0, p = p_out; i < size; i++) { + *p++ = state->ref_frame.cb[i]; + *p++ = state->ref_frame.luma[i]; + *p++ = state->ref_frame.cr[i]; + *p++ = state->ref_frame.alpha[i]; + } + break; default: return -EINVAL; } diff --git a/drivers/media/platform/vicodec/codec-v4l2-fwht.h b/drivers/media/platform/vicodec/codec-v4l2-fwht.h index 162465b78067..ed53e28d4f9c 100644 --- a/drivers/media/platform/vicodec/codec-v4l2-fwht.h +++ b/drivers/media/platform/vicodec/codec-v4l2-fwht.h @@ -13,11 +13,12 @@ struct v4l2_fwht_pixfmt_info { unsigned int bytesperline_mult; unsigned int sizeimage_mult; unsigned int sizeimage_div; - unsigned int luma_step; + unsigned int luma_alpha_step; unsigned int chroma_step; /* Chroma plane subsampling */ unsigned int width_div; unsigned int height_div; + unsigned int components_num; }; struct v4l2_fwht_state { diff --git a/drivers/media/platform/vicodec/vicodec-core.c b/drivers/media/platform/vicodec/vicodec-core.c index 13fb69c58967..0d7876f5acf0 100644 --- a/drivers/media/platform/vicodec/vicodec-core.c +++ b/drivers/media/platform/vicodec/vicodec-core.c @@ -61,7 +61,7 @@ struct pixfmt_info { }; static const struct v4l2_fwht_pixfmt_info pixfmt_fwht = { - V4L2_PIX_FMT_FWHT, 0, 3, 1, 1, 1, 1, 1 + V4L2_PIX_FMT_FWHT, 0, 3, 1, 1, 1, 1, 1, 0 }; static void vicodec_dev_release(struct device *dev) @@ -151,52 +151,52 @@ static struct vicodec_q_data *get_q_data(struct vicodec_ctx *ctx, } static int device_process(struct vicodec_ctx *ctx, - struct vb2_v4l2_buffer *in_vb, - struct vb2_v4l2_buffer *out_vb) + struct vb2_v4l2_buffer *src_vb, + struct vb2_v4l2_buffer *dst_vb) { struct vicodec_dev *dev = ctx->dev; - struct vicodec_q_data *q_cap; + struct vicodec_q_data *q_dst; struct v4l2_fwht_state *state = &ctx->state; - u8 *p_in, *p_out; + u8 *p_src, *p_dst; int ret; - q_cap = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE); + q_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE); if (ctx->is_enc) - p_in = vb2_plane_vaddr(&in_vb->vb2_buf, 0); + p_src = vb2_plane_vaddr(&src_vb->vb2_buf, 0); else - p_in = state->compressed_frame; - p_out = vb2_plane_vaddr(&out_vb->vb2_buf, 0); - if (!p_in || !p_out) { + p_src = state->compressed_frame; + p_dst = vb2_plane_vaddr(&dst_vb->vb2_buf, 0); + if (!p_src || !p_dst) { v4l2_err(&dev->v4l2_dev, "Acquiring kernel pointers to buffers failed\n"); return -EFAULT; } if (ctx->is_enc) { - struct vicodec_q_data *q_out; + struct vicodec_q_data *q_src; - q_out = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT); - state->info = q_out->info; - ret = v4l2_fwht_encode(state, p_in, p_out); + q_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT); + state->info = q_src->info; + ret = v4l2_fwht_encode(state, p_src, p_dst); if (ret < 0) return ret; - vb2_set_plane_payload(&out_vb->vb2_buf, 0, ret); + vb2_set_plane_payload(&dst_vb->vb2_buf, 0, ret); } else { - state->info = q_cap->info; - ret = v4l2_fwht_decode(state, p_in, p_out); + state->info = q_dst->info; + ret = v4l2_fwht_decode(state, p_src, p_dst); if (ret < 0) return ret; - vb2_set_plane_payload(&out_vb->vb2_buf, 0, q_cap->sizeimage); + vb2_set_plane_payload(&dst_vb->vb2_buf, 0, q_dst->sizeimage); } - out_vb->sequence = q_cap->sequence++; - out_vb->vb2_buf.timestamp = in_vb->vb2_buf.timestamp; + dst_vb->sequence = q_dst->sequence++; + dst_vb->vb2_buf.timestamp = src_vb->vb2_buf.timestamp; - if (in_vb->flags & V4L2_BUF_FLAG_TIMECODE) - out_vb->timecode = in_vb->timecode; - out_vb->field = in_vb->field; - out_vb->flags &= ~V4L2_BUF_FLAG_LAST; - out_vb->flags |= in_vb->flags & + if (src_vb->flags & V4L2_BUF_FLAG_TIMECODE) + dst_vb->timecode = src_vb->timecode; + dst_vb->field = src_vb->field; + dst_vb->flags &= ~V4L2_BUF_FLAG_LAST; + dst_vb->flags |= src_vb->flags & (V4L2_BUF_FLAG_TIMECODE | V4L2_BUF_FLAG_KEYFRAME | V4L2_BUF_FLAG_PFRAME | @@ -219,12 +219,12 @@ static void device_run(void *priv) struct vicodec_ctx *ctx = priv; struct vicodec_dev *dev = ctx->dev; struct vb2_v4l2_buffer *src_buf, *dst_buf; - struct vicodec_q_data *q_out; + struct vicodec_q_data *q_src; u32 state; src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); - q_out = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT); + q_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT); state = VB2_BUF_STATE_DONE; if (device_process(ctx, src_buf, dst_buf)) @@ -237,11 +237,11 @@ static void device_run(void *priv) v4l2_event_queue_fh(&ctx->fh, &eos_event); } if (ctx->is_enc) { - src_buf->sequence = q_out->sequence++; + src_buf->sequence = q_src->sequence++; src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); v4l2_m2m_buf_done(src_buf, state); } else if (vb2_get_plane_payload(&src_buf->vb2_buf, 0) == ctx->cur_buf_offset) { - src_buf->sequence = q_out->sequence++; + src_buf->sequence = q_src->sequence++; src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); v4l2_m2m_buf_done(src_buf, state); ctx->cur_buf_offset = 0; @@ -259,15 +259,15 @@ static void device_run(void *priv) v4l2_m2m_job_finish(dev->dec_dev, ctx->fh.m2m_ctx); } -static void job_remove_out_buf(struct vicodec_ctx *ctx, u32 state) +static void job_remove_src_buf(struct vicodec_ctx *ctx, u32 state) { struct vb2_v4l2_buffer *src_buf; - struct vicodec_q_data *q_out; + struct vicodec_q_data *q_src; - q_out = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT); + q_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT); spin_lock(ctx->lock); src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); - src_buf->sequence = q_out->sequence++; + src_buf->sequence = q_src->sequence++; v4l2_m2m_buf_done(src_buf, state); ctx->cur_buf_offset = 0; spin_unlock(ctx->lock); @@ -280,7 +280,7 @@ static int job_ready(void *priv) }; struct vicodec_ctx *ctx = priv; struct vb2_v4l2_buffer *src_buf; - u8 *p_out; + u8 *p_src; u8 *p; u32 sz; u32 state; @@ -293,26 +293,27 @@ restart: src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); if (!src_buf) return 0; - p_out = vb2_plane_vaddr(&src_buf->vb2_buf, 0); + p_src = vb2_plane_vaddr(&src_buf->vb2_buf, 0); sz = vb2_get_plane_payload(&src_buf->vb2_buf, 0); - p = p_out + ctx->cur_buf_offset; + p = p_src + ctx->cur_buf_offset; state = VB2_BUF_STATE_DONE; if (!ctx->comp_size) { state = VB2_BUF_STATE_ERROR; - for (; p < p_out + sz; p++) { + for (; p < p_src + sz; p++) { u32 copy; p = memchr(p, magic[ctx->comp_magic_cnt], - p_out + sz - p); + p_src + sz - p); if (!p) { ctx->comp_magic_cnt = 0; break; } copy = sizeof(magic) - ctx->comp_magic_cnt; - if (p_out + sz - p < copy) - copy = p_out + sz - p; + if (p_src + sz - p < copy) + copy = p_src + sz - p; + memcpy(ctx->state.compressed_frame + ctx->comp_magic_cnt, p, copy); ctx->comp_magic_cnt += copy; @@ -325,7 +326,7 @@ restart: ctx->comp_magic_cnt = 0; } if (ctx->comp_magic_cnt < sizeof(magic)) { - job_remove_out_buf(ctx, state); + job_remove_src_buf(ctx, state); goto restart; } ctx->comp_size = sizeof(magic); @@ -335,14 +336,14 @@ restart: (struct fwht_cframe_hdr *)ctx->state.compressed_frame; u32 copy = sizeof(struct fwht_cframe_hdr) - ctx->comp_size; - if (copy > p_out + sz - p) - copy = p_out + sz - p; + if (copy > p_src + sz - p) + copy = p_src + sz - p; memcpy(ctx->state.compressed_frame + ctx->comp_size, p, copy); p += copy; ctx->comp_size += copy; if (ctx->comp_size < sizeof(struct fwht_cframe_hdr)) { - job_remove_out_buf(ctx, state); + job_remove_src_buf(ctx, state); goto restart; } ctx->comp_frame_size = ntohl(p_hdr->size) + sizeof(*p_hdr); @@ -352,18 +353,19 @@ restart: if (ctx->comp_size < ctx->comp_frame_size) { u32 copy = ctx->comp_frame_size - ctx->comp_size; - if (copy > p_out + sz - p) - copy = p_out + sz - p; + if (copy > p_src + sz - p) + copy = p_src + sz - p; + memcpy(ctx->state.compressed_frame + ctx->comp_size, p, copy); p += copy; ctx->comp_size += copy; if (ctx->comp_size < ctx->comp_frame_size) { - job_remove_out_buf(ctx, state); + job_remove_src_buf(ctx, state); goto restart; } } - ctx->cur_buf_offset = p - p_out; + ctx->cur_buf_offset = p - p_src; ctx->comp_has_frame = true; ctx->comp_has_next_frame = false; if (sz - ctx->cur_buf_offset >= sizeof(struct fwht_cframe_hdr)) { @@ -398,11 +400,6 @@ static int vidioc_querycap(struct file *file, void *priv, strncpy(cap->card, VICODEC_NAME, sizeof(cap->card) - 1); snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s", VICODEC_NAME); - cap->device_caps = V4L2_CAP_STREAMING | - (multiplanar ? - V4L2_CAP_VIDEO_M2M_MPLANE : - V4L2_CAP_VIDEO_M2M); - cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS; return 0; } @@ -994,6 +991,18 @@ static int vicodec_start_streaming(struct vb2_queue *q, unsigned int size = q_data->width * q_data->height; const struct v4l2_fwht_pixfmt_info *info = q_data->info; unsigned int chroma_div = info->width_div * info->height_div; + unsigned int total_planes_size; + + /* + * we don't know ahead how many components are in the encoding type + * V4L2_PIX_FMT_FWHT, so we will allocate space for 4 planes. + */ + if (info->id == V4L2_PIX_FMT_FWHT || info->components_num == 4) + total_planes_size = 2 * size + 2 * (size / chroma_div); + else if (info->components_num == 3) + total_planes_size = size + 2 * (size / chroma_div); + else + total_planes_size = size; q_data->sequence = 0; @@ -1010,10 +1019,8 @@ static int vicodec_start_streaming(struct vb2_queue *q, state->height = q_data->height; } state->ref_frame.width = state->ref_frame.height = 0; - state->ref_frame.luma = kvmalloc(size + 2 * size / chroma_div, - GFP_KERNEL); - ctx->comp_max_size = size + 2 * size / chroma_div + - sizeof(struct fwht_cframe_hdr); + state->ref_frame.luma = kvmalloc(total_planes_size, GFP_KERNEL); + ctx->comp_max_size = total_planes_size + sizeof(struct fwht_cframe_hdr); state->compressed_frame = kvmalloc(ctx->comp_max_size, GFP_KERNEL); if (!state->ref_frame.luma || !state->compressed_frame) { kvfree(state->ref_frame.luma); @@ -1021,8 +1028,20 @@ static int vicodec_start_streaming(struct vb2_queue *q, vicodec_return_bufs(q, VB2_BUF_STATE_QUEUED); return -ENOMEM; } - state->ref_frame.cb = state->ref_frame.luma + size; - state->ref_frame.cr = state->ref_frame.cb + size / chroma_div; + if (info->id == V4L2_PIX_FMT_FWHT || info->components_num >= 3) { + state->ref_frame.cb = state->ref_frame.luma + size; + state->ref_frame.cr = state->ref_frame.cb + size / chroma_div; + } else { + state->ref_frame.cb = NULL; + state->ref_frame.cr = NULL; + } + + if (info->id == V4L2_PIX_FMT_FWHT || info->components_num == 4) + state->ref_frame.alpha = + state->ref_frame.cr + size / chroma_div; + else + state->ref_frame.alpha = NULL; + ctx->last_src_buf = NULL; ctx->last_dst_buf = NULL; state->gop_cnt = 0; @@ -1116,7 +1135,7 @@ static int vicodec_s_ctrl(struct v4l2_ctrl *ctrl) return -EINVAL; } -static struct v4l2_ctrl_ops vicodec_ctrl_ops = { +static const struct v4l2_ctrl_ops vicodec_ctrl_ops = { .s_ctrl = vicodec_s_ctrl, }; @@ -1319,6 +1338,8 @@ static int vicodec_probe(struct platform_device *pdev) vfd->lock = &dev->enc_mutex; vfd->v4l2_dev = &dev->v4l2_dev; strscpy(vfd->name, "vicodec-enc", sizeof(vfd->name)); + vfd->device_caps = V4L2_CAP_STREAMING | + (multiplanar ? V4L2_CAP_VIDEO_M2M_MPLANE : V4L2_CAP_VIDEO_M2M); v4l2_disable_ioctl(vfd, VIDIOC_DECODER_CMD); v4l2_disable_ioctl(vfd, VIDIOC_TRY_DECODER_CMD); video_set_drvdata(vfd, dev); @@ -1335,6 +1356,8 @@ static int vicodec_probe(struct platform_device *pdev) vfd = &dev->dec_vfd; vfd->lock = &dev->dec_mutex; vfd->v4l2_dev = &dev->v4l2_dev; + vfd->device_caps = V4L2_CAP_STREAMING | + (multiplanar ? V4L2_CAP_VIDEO_M2M_MPLANE : V4L2_CAP_VIDEO_M2M); strscpy(vfd->name, "vicodec-dec", sizeof(vfd->name)); v4l2_disable_ioctl(vfd, VIDIOC_ENCODER_CMD); v4l2_disable_ioctl(vfd, VIDIOC_TRY_ENCODER_CMD); diff --git a/drivers/media/platform/vim2m.c b/drivers/media/platform/vim2m.c index d82db738f174..d01821a6906a 100644 --- a/drivers/media/platform/vim2m.c +++ b/drivers/media/platform/vim2m.c @@ -438,8 +438,6 @@ static int vidioc_querycap(struct file *file, void *priv, strncpy(cap->card, MEM2MEM_NAME, sizeof(cap->card) - 1); snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s", MEM2MEM_NAME); - cap->device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING; - cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS; return 0; } @@ -805,10 +803,11 @@ static int vim2m_start_streaming(struct vb2_queue *q, unsigned count) static void vim2m_stop_streaming(struct vb2_queue *q) { struct vim2m_ctx *ctx = vb2_get_drv_priv(q); + struct vim2m_dev *dev = ctx->dev; struct vb2_v4l2_buffer *vbuf; unsigned long flags; - flush_scheduled_work(); + cancel_delayed_work_sync(&dev->work_run); for (;;) { if (V4L2_TYPE_IS_OUTPUT(q->type)) vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); @@ -999,6 +998,7 @@ static const struct video_device vim2m_videodev = { .ioctl_ops = &vim2m_ioctl_ops, .minor = -1, .release = video_device_release_empty, + .device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING, }; static const struct v4l2_m2m_ops m2m_ops = { diff --git a/drivers/media/platform/vimc/vimc-common.c b/drivers/media/platform/vimc/vimc-common.c index dee1b9dfc4f6..867e24dbd6b5 100644 --- a/drivers/media/platform/vimc/vimc-common.c +++ b/drivers/media/platform/vimc/vimc-common.c @@ -276,6 +276,8 @@ int vimc_pipeline_s_stream(struct media_entity *ent, int enable) /* Start the stream in the subdevice direct connected */ pad = media_entity_remote_pad(&ent->pads[i]); + if (!pad) + continue; if (!is_media_entity_v4l2_subdev(pad->entity)) return -EINVAL; diff --git a/drivers/media/platform/vimc/vimc-sensor.c b/drivers/media/platform/vimc/vimc-sensor.c index edf4c85ae63d..32ca9c6172b1 100644 --- a/drivers/media/platform/vimc/vimc-sensor.c +++ b/drivers/media/platform/vimc/vimc-sensor.c @@ -286,7 +286,7 @@ static int vimc_sen_s_stream(struct v4l2_subdev *sd, int enable) return 0; } -static struct v4l2_subdev_core_ops vimc_sen_core_ops = { +static const struct v4l2_subdev_core_ops vimc_sen_core_ops = { .log_status = v4l2_ctrl_subdev_log_status, .subscribe_event = v4l2_ctrl_subdev_subscribe_event, .unsubscribe_event = v4l2_event_subdev_unsubscribe, diff --git a/drivers/media/platform/vivid/vivid-core.c b/drivers/media/platform/vivid/vivid-core.c index 626e2b24a403..c931f007e5b0 100644 --- a/drivers/media/platform/vivid/vivid-core.c +++ b/drivers/media/platform/vivid/vivid-core.c @@ -324,13 +324,14 @@ static int vidioc_s_dv_timings(struct file *file, void *fh, struct v4l2_dv_timin return vivid_vid_out_s_dv_timings(file, fh, timings); } -static int vidioc_cropcap(struct file *file, void *fh, struct v4l2_cropcap *cc) +static int vidioc_g_pixelaspect(struct file *file, void *fh, + int type, struct v4l2_fract *f) { struct video_device *vdev = video_devdata(file); if (vdev->vfl_dir == VFL_DIR_RX) - return vivid_vid_cap_cropcap(file, fh, cc); - return vivid_vid_out_cropcap(file, fh, cc); + return vivid_vid_cap_g_pixelaspect(file, fh, type, f); + return vivid_vid_out_g_pixelaspect(file, fh, type, f); } static int vidioc_g_selection(struct file *file, void *fh, @@ -519,7 +520,7 @@ static const struct v4l2_ioctl_ops vivid_ioctl_ops = { .vidioc_g_selection = vidioc_g_selection, .vidioc_s_selection = vidioc_s_selection, - .vidioc_cropcap = vidioc_cropcap, + .vidioc_g_pixelaspect = vidioc_g_pixelaspect, .vidioc_g_fmt_vbi_cap = vidioc_g_fmt_vbi_cap, .vidioc_try_fmt_vbi_cap = vidioc_g_fmt_vbi_cap, @@ -624,12 +625,24 @@ static void vivid_dev_release(struct v4l2_device *v4l2_dev) vfree(dev->bitmap_out); tpg_free(&dev->tpg); kfree(dev->query_dv_timings_qmenu); + kfree(dev->query_dv_timings_qmenu_strings); kfree(dev); } #ifdef CONFIG_MEDIA_CONTROLLER +static int vivid_req_validate(struct media_request *req) +{ + struct vivid_dev *dev = container_of(req->mdev, struct vivid_dev, mdev); + + if (dev->req_validate_error) { + dev->req_validate_error = false; + return -EINVAL; + } + return vb2_request_validate(req); +} + static const struct media_device_ops vivid_media_ops = { - .req_validate = vb2_request_validate, + .req_validate = vivid_req_validate, .req_queue = vb2_request_queue, }; #endif @@ -669,6 +682,8 @@ static int vivid_create_instance(struct platform_device *pdev, int inst) /* Initialize media device */ strlcpy(dev->mdev.model, VIVID_MODULE_NAME, sizeof(dev->mdev.model)); + snprintf(dev->mdev.bus_info, sizeof(dev->mdev.bus_info), + "platform:%s-%03d", VIVID_MODULE_NAME, inst); dev->mdev.dev = &pdev->dev; media_device_init(&dev->mdev); dev->mdev.ops = &vivid_media_ops; @@ -873,20 +888,31 @@ static int vivid_create_instance(struct platform_device *pdev, int inst) if (!dev->edid) goto free_dev; - /* create a string array containing the names of all the preset timings */ while (v4l2_dv_timings_presets[dev->query_dv_timings_size].bt.width) dev->query_dv_timings_size++; + + /* + * Create a char pointer array that points to the names of all the + * preset timings + */ dev->query_dv_timings_qmenu = kmalloc_array(dev->query_dv_timings_size, - (sizeof(void *) + 32), - GFP_KERNEL); - if (dev->query_dv_timings_qmenu == NULL) + sizeof(char *), GFP_KERNEL); + /* + * Create a string array containing the names of all the preset + * timings. Each name is max 31 chars long (+ terminating 0). + */ + dev->query_dv_timings_qmenu_strings = + kmalloc_array(dev->query_dv_timings_size, 32, GFP_KERNEL); + + if (!dev->query_dv_timings_qmenu || + !dev->query_dv_timings_qmenu_strings) goto free_dev; + for (i = 0; i < dev->query_dv_timings_size; i++) { const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt; - char *p = (char *)&dev->query_dv_timings_qmenu[dev->query_dv_timings_size]; + char *p = dev->query_dv_timings_qmenu_strings + i * 32; u32 htot, vtot; - p += i * 32; dev->query_dv_timings_qmenu[i] = p; htot = V4L2_DV_BT_FRAME_WIDTH(bt); diff --git a/drivers/media/platform/vivid/vivid-core.h b/drivers/media/platform/vivid/vivid-core.h index 1891254c8f0b..6697c7009629 100644 --- a/drivers/media/platform/vivid/vivid-core.h +++ b/drivers/media/platform/vivid/vivid-core.h @@ -294,6 +294,7 @@ struct vivid_dev { bool buf_prepare_error; bool start_streaming_error; bool dqbuf_error; + bool req_validate_error; bool seq_wrap; bool time_wrap; u64 time_wrap_offset; @@ -305,6 +306,7 @@ struct vivid_dev { enum vivid_signal_mode dv_timings_signal_mode; char **query_dv_timings_qmenu; + char *query_dv_timings_qmenu_strings; unsigned query_dv_timings_size; unsigned query_dv_timings_last; unsigned query_dv_timings; @@ -392,6 +394,9 @@ struct vivid_dev { /* thread for generating video capture stream */ struct task_struct *kthread_vid_cap; unsigned long jiffies_vid_cap; + u64 cap_stream_start; + u64 cap_frame_period; + u64 cap_frame_eof_offset; u32 cap_seq_offset; u32 cap_seq_count; bool cap_seq_resync; diff --git a/drivers/media/platform/vivid/vivid-ctrls.c b/drivers/media/platform/vivid/vivid-ctrls.c index bfffeda12f14..4cd526ff248b 100644 --- a/drivers/media/platform/vivid/vivid-ctrls.c +++ b/drivers/media/platform/vivid/vivid-ctrls.c @@ -81,6 +81,7 @@ #define VIVID_CID_START_STR_ERROR (VIVID_CID_VIVID_BASE + 69) #define VIVID_CID_QUEUE_ERROR (VIVID_CID_VIVID_BASE + 70) #define VIVID_CID_CLEAR_FB (VIVID_CID_VIVID_BASE + 71) +#define VIVID_CID_REQ_VALIDATE_ERROR (VIVID_CID_VIVID_BASE + 72) #define VIVID_CID_RADIO_SEEK_MODE (VIVID_CID_VIVID_BASE + 90) #define VIVID_CID_RADIO_SEEK_PROG_LIM (VIVID_CID_VIVID_BASE + 91) @@ -1002,6 +1003,9 @@ static int vivid_streaming_s_ctrl(struct v4l2_ctrl *ctrl) case VIVID_CID_START_STR_ERROR: dev->start_streaming_error = true; break; + case VIVID_CID_REQ_VALIDATE_ERROR: + dev->req_validate_error = true; + break; case VIVID_CID_QUEUE_ERROR: if (vb2_start_streaming_called(&dev->vb_vid_cap_q)) vb2_queue_error(&dev->vb_vid_cap_q); @@ -1087,6 +1091,15 @@ static const struct v4l2_ctrl_config vivid_ctrl_queue_error = { .type = V4L2_CTRL_TYPE_BUTTON, }; +#ifdef CONFIG_MEDIA_CONTROLLER +static const struct v4l2_ctrl_config vivid_ctrl_req_validate_error = { + .ops = &vivid_streaming_ctrl_ops, + .id = VIVID_CID_REQ_VALIDATE_ERROR, + .name = "Inject req_validate() Error", + .type = V4L2_CTRL_TYPE_BUTTON, +}; +#endif + static const struct v4l2_ctrl_config vivid_ctrl_seq_wrap = { .ops = &vivid_streaming_ctrl_ops, .id = VIVID_CID_SEQ_WRAP, @@ -1516,6 +1529,9 @@ int vivid_create_controls(struct vivid_dev *dev, bool show_ccs_cap, v4l2_ctrl_new_custom(hdl_streaming, &vivid_ctrl_buf_prepare_error, NULL); v4l2_ctrl_new_custom(hdl_streaming, &vivid_ctrl_start_streaming_error, NULL); v4l2_ctrl_new_custom(hdl_streaming, &vivid_ctrl_queue_error, NULL); +#ifdef CONFIG_MEDIA_CONTROLLER + v4l2_ctrl_new_custom(hdl_streaming, &vivid_ctrl_req_validate_error, NULL); +#endif v4l2_ctrl_new_custom(hdl_streaming, &vivid_ctrl_seq_wrap, NULL); v4l2_ctrl_new_custom(hdl_streaming, &vivid_ctrl_time_wrap, NULL); } diff --git a/drivers/media/platform/vivid/vivid-kthread-cap.c b/drivers/media/platform/vivid/vivid-kthread-cap.c index eebfff2126be..f8006a30c12f 100644 --- a/drivers/media/platform/vivid/vivid-kthread-cap.c +++ b/drivers/media/platform/vivid/vivid-kthread-cap.c @@ -425,12 +425,6 @@ static void vivid_fillbuff(struct vivid_dev *dev, struct vivid_buffer *buf) is_loop = true; buf->vb.sequence = dev->vid_cap_seq_count; - /* - * Take the timestamp now if the timestamp source is set to - * "Start of Exposure". - */ - if (dev->tstamp_src_is_soe) - buf->vb.vb2_buf.timestamp = ktime_get_ns(); if (dev->field_cap == V4L2_FIELD_ALTERNATE) { /* * 60 Hz standards start with the bottom field, 50 Hz standards @@ -554,14 +548,6 @@ static void vivid_fillbuff(struct vivid_dev *dev, struct vivid_buffer *buf) } } } - - /* - * If "End of Frame" is specified at the timestamp source, then take - * the timestamp now. - */ - if (!dev->tstamp_src_is_soe) - buf->vb.vb2_buf.timestamp = ktime_get_ns(); - buf->vb.vb2_buf.timestamp += dev->time_wrap_offset; } /* @@ -667,10 +653,28 @@ static void vivid_overlay(struct vivid_dev *dev, struct vivid_buffer *buf) } } +static void vivid_cap_update_frame_period(struct vivid_dev *dev) +{ + u64 f_period; + + f_period = (u64)dev->timeperframe_vid_cap.numerator * 1000000000; + do_div(f_period, dev->timeperframe_vid_cap.denominator); + if (dev->field_cap == V4L2_FIELD_ALTERNATE) + f_period >>= 1; + /* + * If "End of Frame", then offset the exposure time by 0.9 + * of the frame period. + */ + dev->cap_frame_eof_offset = f_period * 9; + do_div(dev->cap_frame_eof_offset, 10); + dev->cap_frame_period = f_period; +} + static void vivid_thread_vid_cap_tick(struct vivid_dev *dev, int dropped_bufs) { struct vivid_buffer *vid_cap_buf = NULL; struct vivid_buffer *vbi_cap_buf = NULL; + u64 f_time = 0; dprintk(dev, 1, "Video Capture Thread Tick\n"); @@ -702,6 +706,11 @@ static void vivid_thread_vid_cap_tick(struct vivid_dev *dev, int dropped_bufs) if (!vid_cap_buf && !vbi_cap_buf) goto update_mv; + f_time = dev->cap_frame_period * dev->vid_cap_seq_count + + dev->cap_stream_start + dev->time_wrap_offset; + if (!dev->tstamp_src_is_soe) + f_time += dev->cap_frame_eof_offset; + if (vid_cap_buf) { v4l2_ctrl_request_setup(vid_cap_buf->vb.vb2_buf.req_obj.req, &dev->ctrl_hdl_vid_cap); @@ -721,9 +730,13 @@ static void vivid_thread_vid_cap_tick(struct vivid_dev *dev, int dropped_bufs) VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE); dprintk(dev, 2, "vid_cap buffer %d done\n", vid_cap_buf->vb.vb2_buf.index); + + vid_cap_buf->vb.vb2_buf.timestamp = f_time; } if (vbi_cap_buf) { + u64 vbi_period; + v4l2_ctrl_request_setup(vbi_cap_buf->vb.vb2_buf.req_obj.req, &dev->ctrl_hdl_vbi_cap); if (dev->stream_sliced_vbi_cap) @@ -736,6 +749,11 @@ static void vivid_thread_vid_cap_tick(struct vivid_dev *dev, int dropped_bufs) VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE); dprintk(dev, 2, "vbi_cap %d done\n", vbi_cap_buf->vb.vb2_buf.index); + + /* If capturing a VBI, offset by 0.05 */ + vbi_period = dev->cap_frame_period * 5; + do_div(vbi_period, 100); + vbi_cap_buf->vb.vb2_buf.timestamp = f_time + vbi_period; } dev->dqbuf_error = false; @@ -767,6 +785,8 @@ static int vivid_thread_vid_cap(void *data) dev->cap_seq_count = 0; dev->cap_seq_resync = false; dev->jiffies_vid_cap = jiffies; + dev->cap_stream_start = ktime_get_ns(); + vivid_cap_update_frame_period(dev); for (;;) { try_to_freeze(); @@ -779,6 +799,9 @@ static int vivid_thread_vid_cap(void *data) dev->jiffies_vid_cap = cur_jiffies; dev->cap_seq_offset = dev->cap_seq_count + 1; dev->cap_seq_count = 0; + dev->cap_stream_start += dev->cap_frame_period * + dev->cap_seq_offset; + vivid_cap_update_frame_period(dev); dev->cap_seq_resync = false; } numerator = dev->timeperframe_vid_cap.numerator; @@ -873,8 +896,11 @@ int vivid_start_generating_vid_cap(struct vivid_dev *dev, bool *pstreaming) "%s-vid-cap", dev->v4l2_dev.name); if (IS_ERR(dev->kthread_vid_cap)) { + int err = PTR_ERR(dev->kthread_vid_cap); + + dev->kthread_vid_cap = NULL; v4l2_err(&dev->v4l2_dev, "kernel_thread() failed\n"); - return PTR_ERR(dev->kthread_vid_cap); + return err; } *pstreaming = true; vivid_grab_controls(dev, true); diff --git a/drivers/media/platform/vivid/vivid-kthread-out.c b/drivers/media/platform/vivid/vivid-kthread-out.c index 5a14810eeb69..ce5bcda2348c 100644 --- a/drivers/media/platform/vivid/vivid-kthread-out.c +++ b/drivers/media/platform/vivid/vivid-kthread-out.c @@ -244,8 +244,11 @@ int vivid_start_generating_vid_out(struct vivid_dev *dev, bool *pstreaming) "%s-vid-out", dev->v4l2_dev.name); if (IS_ERR(dev->kthread_vid_out)) { + int err = PTR_ERR(dev->kthread_vid_out); + + dev->kthread_vid_out = NULL; v4l2_err(&dev->v4l2_dev, "kernel_thread() failed\n"); - return PTR_ERR(dev->kthread_vid_out); + return err; } *pstreaming = true; vivid_grab_controls(dev, true); diff --git a/drivers/media/platform/vivid/vivid-vbi-cap.c b/drivers/media/platform/vivid/vivid-vbi-cap.c index d666271bdaed..40ecd7902b56 100644 --- a/drivers/media/platform/vivid/vivid-vbi-cap.c +++ b/drivers/media/platform/vivid/vivid-vbi-cap.c @@ -95,8 +95,6 @@ void vivid_raw_vbi_cap_process(struct vivid_dev *dev, struct vivid_buffer *buf) if (!VIVID_INVALID_SIGNAL(dev->std_signal_mode)) vivid_vbi_gen_raw(&dev->vbi_gen, &vbi, vbuf); - - buf->vb.vb2_buf.timestamp = ktime_get_ns() + dev->time_wrap_offset; } @@ -119,8 +117,6 @@ void vivid_sliced_vbi_cap_process(struct vivid_dev *dev, for (i = 0; i < 25; i++) vbuf[i] = dev->vbi_gen.data[i]; } - - buf->vb.vb2_buf.timestamp = ktime_get_ns() + dev->time_wrap_offset; } static int vbi_cap_queue_setup(struct vb2_queue *vq, diff --git a/drivers/media/platform/vivid/vivid-vid-cap.c b/drivers/media/platform/vivid/vivid-vid-cap.c index 673772cd17d6..c059fc12668a 100644 --- a/drivers/media/platform/vivid/vivid-vid-cap.c +++ b/drivers/media/platform/vivid/vivid-vid-cap.c @@ -449,6 +449,8 @@ void vivid_update_format_cap(struct vivid_dev *dev, bool keep_controls) tpg_s_rgb_range(&dev->tpg, v4l2_ctrl_g_ctrl(dev->rgb_range_cap)); break; } + vfree(dev->bitmap_cap); + dev->bitmap_cap = NULL; vivid_update_quality(dev); tpg_reset_source(&dev->tpg, dev->src_rect.width, dev->src_rect.height, dev->field_cap); dev->crop_cap = dev->src_rect; @@ -1014,26 +1016,24 @@ int vivid_vid_cap_s_selection(struct file *file, void *fh, struct v4l2_selection return 0; } -int vivid_vid_cap_cropcap(struct file *file, void *priv, - struct v4l2_cropcap *cap) +int vivid_vid_cap_g_pixelaspect(struct file *file, void *priv, + int type, struct v4l2_fract *f) { struct vivid_dev *dev = video_drvdata(file); - if (cap->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + if (type != V4L2_BUF_TYPE_VIDEO_CAPTURE) return -EINVAL; switch (vivid_get_pixel_aspect(dev)) { case TPG_PIXEL_ASPECT_NTSC: - cap->pixelaspect.numerator = 11; - cap->pixelaspect.denominator = 10; + f->numerator = 11; + f->denominator = 10; break; case TPG_PIXEL_ASPECT_PAL: - cap->pixelaspect.numerator = 54; - cap->pixelaspect.denominator = 59; + f->numerator = 54; + f->denominator = 59; break; - case TPG_PIXEL_ASPECT_SQUARE: - cap->pixelaspect.numerator = 1; - cap->pixelaspect.denominator = 1; + default: break; } return 0; @@ -1835,9 +1835,6 @@ int vivid_vid_cap_g_parm(struct file *file, void *priv, return 0; } -#define FRACT_CMP(a, OP, b) \ - ((u64)(a).numerator * (b).denominator OP (u64)(b).numerator * (a).denominator) - int vivid_vid_cap_s_parm(struct file *file, void *priv, struct v4l2_streamparm *parm) { @@ -1858,14 +1855,14 @@ int vivid_vid_cap_s_parm(struct file *file, void *priv, if (tpf.denominator == 0) tpf = webcam_intervals[ival_sz - 1]; for (i = 0; i < ival_sz; i++) - if (FRACT_CMP(tpf, >=, webcam_intervals[i])) + if (V4L2_FRACT_COMPARE(tpf, >=, webcam_intervals[i])) break; if (i == ival_sz) i = ival_sz - 1; dev->webcam_ival_idx = i; tpf = webcam_intervals[dev->webcam_ival_idx]; - tpf = FRACT_CMP(tpf, <, tpf_min) ? tpf_min : tpf; - tpf = FRACT_CMP(tpf, >, tpf_max) ? tpf_max : tpf; + tpf = V4L2_FRACT_COMPARE(tpf, <, tpf_min) ? tpf_min : tpf; + tpf = V4L2_FRACT_COMPARE(tpf, >, tpf_max) ? tpf_max : tpf; /* resync the thread's timings */ dev->cap_seq_resync = true; diff --git a/drivers/media/platform/vivid/vivid-vid-cap.h b/drivers/media/platform/vivid/vivid-vid-cap.h index 47d8b48820df..1e422a59eeab 100644 --- a/drivers/media/platform/vivid/vivid-vid-cap.h +++ b/drivers/media/platform/vivid/vivid-vid-cap.h @@ -28,7 +28,7 @@ int vidioc_try_fmt_vid_cap(struct file *file, void *priv, struct v4l2_format *f) int vidioc_s_fmt_vid_cap(struct file *file, void *priv, struct v4l2_format *f); int vivid_vid_cap_g_selection(struct file *file, void *priv, struct v4l2_selection *sel); int vivid_vid_cap_s_selection(struct file *file, void *fh, struct v4l2_selection *s); -int vivid_vid_cap_cropcap(struct file *file, void *priv, struct v4l2_cropcap *cap); +int vivid_vid_cap_g_pixelaspect(struct file *file, void *priv, int type, struct v4l2_fract *f); int vidioc_enum_fmt_vid_overlay(struct file *file, void *priv, struct v4l2_fmtdesc *f); int vidioc_g_fmt_vid_overlay(struct file *file, void *priv, struct v4l2_format *f); int vidioc_try_fmt_vid_overlay(struct file *file, void *priv, struct v4l2_format *f); diff --git a/drivers/media/platform/vivid/vivid-vid-common.c b/drivers/media/platform/vivid/vivid-vid-common.c index 9645a91b8782..661f4015fba1 100644 --- a/drivers/media/platform/vivid/vivid-vid-common.c +++ b/drivers/media/platform/vivid/vivid-vid-common.c @@ -21,7 +21,7 @@ const struct v4l2_dv_timings_cap vivid_dv_timings_cap = { .type = V4L2_DV_BT_656_1120, /* keep this initialization for compatibility with GCC < 4.4.6 */ .reserved = { 0 }, - V4L2_INIT_BT_TIMINGS(0, MAX_WIDTH, 0, MAX_HEIGHT, 14000000, 775000000, + V4L2_INIT_BT_TIMINGS(16, MAX_WIDTH, 16, MAX_HEIGHT, 14000000, 775000000, V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT | V4L2_DV_BT_STD_GTF, V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_INTERLACED) diff --git a/drivers/media/platform/vivid/vivid-vid-out.c b/drivers/media/platform/vivid/vivid-vid-out.c index 628eae154ee7..ea250aee2b2e 100644 --- a/drivers/media/platform/vivid/vivid-vid-out.c +++ b/drivers/media/platform/vivid/vivid-vid-out.c @@ -793,26 +793,24 @@ int vivid_vid_out_s_selection(struct file *file, void *fh, struct v4l2_selection return 0; } -int vivid_vid_out_cropcap(struct file *file, void *priv, - struct v4l2_cropcap *cap) +int vivid_vid_out_g_pixelaspect(struct file *file, void *priv, + int type, struct v4l2_fract *f) { struct vivid_dev *dev = video_drvdata(file); - if (cap->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) + if (type != V4L2_BUF_TYPE_VIDEO_OUTPUT) return -EINVAL; switch (vivid_get_pixel_aspect(dev)) { case TPG_PIXEL_ASPECT_NTSC: - cap->pixelaspect.numerator = 11; - cap->pixelaspect.denominator = 10; + f->numerator = 11; + f->denominator = 10; break; case TPG_PIXEL_ASPECT_PAL: - cap->pixelaspect.numerator = 54; - cap->pixelaspect.denominator = 59; + f->numerator = 54; + f->denominator = 59; break; - case TPG_PIXEL_ASPECT_SQUARE: - cap->pixelaspect.numerator = 1; - cap->pixelaspect.denominator = 1; + default: break; } return 0; diff --git a/drivers/media/platform/vivid/vivid-vid-out.h b/drivers/media/platform/vivid/vivid-vid-out.h index e87aacf843c5..8d56314f4ea1 100644 --- a/drivers/media/platform/vivid/vivid-vid-out.h +++ b/drivers/media/platform/vivid/vivid-vid-out.h @@ -23,7 +23,7 @@ int vidioc_try_fmt_vid_out(struct file *file, void *priv, struct v4l2_format *f) int vidioc_s_fmt_vid_out(struct file *file, void *priv, struct v4l2_format *f); int vivid_vid_out_g_selection(struct file *file, void *priv, struct v4l2_selection *sel); int vivid_vid_out_s_selection(struct file *file, void *fh, struct v4l2_selection *s); -int vivid_vid_out_cropcap(struct file *file, void *fh, struct v4l2_cropcap *cap); +int vivid_vid_out_g_pixelaspect(struct file *file, void *priv, int type, struct v4l2_fract *f); int vidioc_enum_fmt_vid_out_overlay(struct file *file, void *priv, struct v4l2_fmtdesc *f); int vidioc_g_fmt_vid_out_overlay(struct file *file, void *priv, struct v4l2_format *f); int vidioc_try_fmt_vid_out_overlay(struct file *file, void *priv, struct v4l2_format *f); diff --git a/drivers/media/platform/xilinx/Kconfig b/drivers/media/platform/xilinx/Kconfig index a5d21b7c6e0b..74ec8aaa5ae0 100644 --- a/drivers/media/platform/xilinx/Kconfig +++ b/drivers/media/platform/xilinx/Kconfig @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 + config VIDEO_XILINX tristate "Xilinx Video IP (EXPERIMENTAL)" depends on VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API && OF && HAS_DMA diff --git a/drivers/media/platform/xilinx/Makefile b/drivers/media/platform/xilinx/Makefile index e8a0f2a9f733..4cdc0b1ec7a5 100644 --- a/drivers/media/platform/xilinx/Makefile +++ b/drivers/media/platform/xilinx/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 + xilinx-video-objs += xilinx-dma.o xilinx-vip.o xilinx-vipp.o obj-$(CONFIG_VIDEO_XILINX) += xilinx-video.o diff --git a/drivers/media/platform/xilinx/xilinx-dma.c b/drivers/media/platform/xilinx/xilinx-dma.c index 4ae9d38c9433..c9d5fdb2d407 100644 --- a/drivers/media/platform/xilinx/xilinx-dma.c +++ b/drivers/media/platform/xilinx/xilinx-dma.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Xilinx Video DMA * @@ -6,10 +7,6 @@ * * Contacts: Hyun Kwon <hyun.kwon@xilinx.com> * Laurent Pinchart <laurent.pinchart@ideasonboard.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include <linux/dma/xilinx_dma.h> diff --git a/drivers/media/platform/xilinx/xilinx-dma.h b/drivers/media/platform/xilinx/xilinx-dma.h index e95d136c153a..5aec4d17eb21 100644 --- a/drivers/media/platform/xilinx/xilinx-dma.h +++ b/drivers/media/platform/xilinx/xilinx-dma.h @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Xilinx Video DMA * @@ -6,10 +7,6 @@ * * Contacts: Hyun Kwon <hyun.kwon@xilinx.com> * Laurent Pinchart <laurent.pinchart@ideasonboard.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #ifndef __XILINX_VIP_DMA_H__ diff --git a/drivers/media/platform/xilinx/xilinx-tpg.c b/drivers/media/platform/xilinx/xilinx-tpg.c index 851d20dcd550..ed01bedb5db6 100644 --- a/drivers/media/platform/xilinx/xilinx-tpg.c +++ b/drivers/media/platform/xilinx/xilinx-tpg.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Xilinx Test Pattern Generator * @@ -6,10 +7,6 @@ * * Contacts: Hyun Kwon <hyun.kwon@xilinx.com> * Laurent Pinchart <laurent.pinchart@ideasonboard.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include <linux/device.h> @@ -725,7 +722,7 @@ static int xtpg_parse_of(struct xtpg_device *xtpg) const struct xvip_video_format *format; struct device_node *endpoint; - if (!port->name || of_node_cmp(port->name, "port")) + if (!of_node_name_eq(port, "port")) continue; format = xvip_of_get_format(port); diff --git a/drivers/media/platform/xilinx/xilinx-vip.c b/drivers/media/platform/xilinx/xilinx-vip.c index 311259129504..18f98838111b 100644 --- a/drivers/media/platform/xilinx/xilinx-vip.c +++ b/drivers/media/platform/xilinx/xilinx-vip.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Xilinx Video IP Core * @@ -6,10 +7,6 @@ * * Contacts: Hyun Kwon <hyun.kwon@xilinx.com> * Laurent Pinchart <laurent.pinchart@ideasonboard.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include <linux/clk.h> @@ -36,7 +33,7 @@ static const struct xvip_video_format xvip_video_formats[] = { { XVIP_VF_MONO_SENSOR, 8, "mono", MEDIA_BUS_FMT_Y8_1X8, 1, V4L2_PIX_FMT_GREY, "Greyscale 8-bit" }, { XVIP_VF_MONO_SENSOR, 8, "rggb", MEDIA_BUS_FMT_SRGGB8_1X8, - 1, V4L2_PIX_FMT_SGRBG8, "Bayer 8-bit RGGB" }, + 1, V4L2_PIX_FMT_SRGGB8, "Bayer 8-bit RGGB" }, { XVIP_VF_MONO_SENSOR, 8, "grbg", MEDIA_BUS_FMT_SGRBG8_1X8, 1, V4L2_PIX_FMT_SGRBG8, "Bayer 8-bit GRBG" }, { XVIP_VF_MONO_SENSOR, 8, "gbrg", MEDIA_BUS_FMT_SGBRG8_1X8, diff --git a/drivers/media/platform/xilinx/xilinx-vip.h b/drivers/media/platform/xilinx/xilinx-vip.h index 42fee2026815..ba939dd52818 100644 --- a/drivers/media/platform/xilinx/xilinx-vip.h +++ b/drivers/media/platform/xilinx/xilinx-vip.h @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Xilinx Video IP Core * @@ -6,10 +7,6 @@ * * Contacts: Hyun Kwon <hyun.kwon@xilinx.com> * Laurent Pinchart <laurent.pinchart@ideasonboard.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #ifndef __XILINX_VIP_H__ diff --git a/drivers/media/platform/xilinx/xilinx-vipp.c b/drivers/media/platform/xilinx/xilinx-vipp.c index 99e016d35d91..edce0402155d 100644 --- a/drivers/media/platform/xilinx/xilinx-vipp.c +++ b/drivers/media/platform/xilinx/xilinx-vipp.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Xilinx Video IP Composite Device * @@ -6,10 +7,6 @@ * * Contacts: Hyun Kwon <hyun.kwon@xilinx.com> * Laurent Pinchart <laurent.pinchart@ideasonboard.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include <linux/list.h> diff --git a/drivers/media/platform/xilinx/xilinx-vipp.h b/drivers/media/platform/xilinx/xilinx-vipp.h index 7e9c4cff33b4..e65fce9538f9 100644 --- a/drivers/media/platform/xilinx/xilinx-vipp.h +++ b/drivers/media/platform/xilinx/xilinx-vipp.h @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Xilinx Video IP Composite Device * @@ -6,10 +7,6 @@ * * Contacts: Hyun Kwon <hyun.kwon@xilinx.com> * Laurent Pinchart <laurent.pinchart@ideasonboard.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #ifndef __XILINX_VIPP_H__ diff --git a/drivers/media/platform/xilinx/xilinx-vtc.c b/drivers/media/platform/xilinx/xilinx-vtc.c index 01c750edcac5..0ae0208d7529 100644 --- a/drivers/media/platform/xilinx/xilinx-vtc.c +++ b/drivers/media/platform/xilinx/xilinx-vtc.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Xilinx Video Timing Controller * @@ -6,10 +7,6 @@ * * Contacts: Hyun Kwon <hyun.kwon@xilinx.com> * Laurent Pinchart <laurent.pinchart@ideasonboard.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include <linux/clk.h> diff --git a/drivers/media/platform/xilinx/xilinx-vtc.h b/drivers/media/platform/xilinx/xilinx-vtc.h index e1bb2cfcf428..90cf44245283 100644 --- a/drivers/media/platform/xilinx/xilinx-vtc.h +++ b/drivers/media/platform/xilinx/xilinx-vtc.h @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Xilinx Video Timing Controller * @@ -6,10 +7,6 @@ * * Contacts: Hyun Kwon <hyun.kwon@xilinx.com> * Laurent Pinchart <laurent.pinchart@ideasonboard.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #ifndef __XILINX_VTC_H__ diff --git a/drivers/media/rc/Kconfig b/drivers/media/rc/Kconfig index 1021c08a9ba4..8a216068a35a 100644 --- a/drivers/media/rc/Kconfig +++ b/drivers/media/rc/Kconfig @@ -493,6 +493,18 @@ config IR_TANGO The HW decoder supports NEC, RC-5, RC-6 IR protocols. When compiled as a module, look for tango-ir. +config RC_XBOX_DVD + tristate "Xbox DVD Movie Playback Kit" + depends on RC_CORE + depends on USB_ARCH_HAS_HCD + select USB + help + Say Y here if you want to use the Xbox DVD Movie Playback Kit. + These are IR remotes with USB receivers for the Original Xbox (2001). + + To compile this driver as a module, choose M here: the module will be + called xbox_remote. + config IR_ZX tristate "ZTE ZX IR remote control" depends on RC_CORE diff --git a/drivers/media/rc/Makefile b/drivers/media/rc/Makefile index e0340d043fe8..92c163816849 100644 --- a/drivers/media/rc/Makefile +++ b/drivers/media/rc/Makefile @@ -48,3 +48,4 @@ obj-$(CONFIG_IR_SIR) += sir_ir.o obj-$(CONFIG_IR_MTK) += mtk-cir.o obj-$(CONFIG_IR_ZX) += zx-irdec.o obj-$(CONFIG_IR_TANGO) += tango-ir.o +obj-$(CONFIG_RC_XBOX_DVD) += xbox_remote.o diff --git a/drivers/media/rc/imon.c b/drivers/media/rc/imon.c index 1041c056854d..989d2554ec72 100644 --- a/drivers/media/rc/imon.c +++ b/drivers/media/rc/imon.c @@ -772,9 +772,9 @@ static ssize_t show_associate_remote(struct device *d, mutex_lock(&ictx->lock); if (ictx->rf_isassociating) - strcpy(buf, "associating\n"); + strscpy(buf, "associating\n", PAGE_SIZE); else - strcpy(buf, "closed\n"); + strscpy(buf, "closed\n", PAGE_SIZE); dev_info(d, "Visit http://www.lirc.org/html/imon-24g.html for instructions on how to associate your iMON 2.4G DT/LT remote\n"); mutex_unlock(&ictx->lock); diff --git a/drivers/media/rc/imon_raw.c b/drivers/media/rc/imon_raw.c index 7796098d9c30..25e56c5b13c0 100644 --- a/drivers/media/rc/imon_raw.c +++ b/drivers/media/rc/imon_raw.c @@ -14,51 +14,50 @@ struct imon { struct device *dev; struct urb *ir_urb; struct rc_dev *rcdev; - u8 ir_buf[8]; + u8 ir_buf[8] __aligned(__alignof__(u64)); char phys[64]; }; /* - * ffs/find_next_bit() searches in the wrong direction, so open-code our own. + * The first 5 bytes of data represent IR pulse or space. Each bit, starting + * from highest bit in the first byte, represents 250µs of data. It is 1 + * for space and 0 for pulse. + * + * The station sends 10 packets, and the 7th byte will be number 1 to 10, so + * when we receive 10 we assume all the data has arrived. */ -static inline int is_bit_set(const u8 *buf, int bit) -{ - return buf[bit / 8] & (0x80 >> (bit & 7)); -} - static void imon_ir_data(struct imon *imon) { struct ir_raw_event rawir = {}; - int offset = 0, size = 5 * 8; + u64 d = be64_to_cpup((__be64 *)imon->ir_buf) >> 24; + int offset = 40; int bit; dev_dbg(imon->dev, "data: %*ph", 8, imon->ir_buf); - while (offset < size) { - bit = offset; - while (!is_bit_set(imon->ir_buf, bit) && bit < size) - bit++; - dev_dbg(imon->dev, "pulse: %d bits", bit - offset); - if (bit > offset) { + do { + bit = fls64(d & (BIT_ULL(offset) - 1)); + if (bit < offset) { + dev_dbg(imon->dev, "pulse: %d bits", offset - bit); rawir.pulse = true; - rawir.duration = (bit - offset) * BIT_DURATION; + rawir.duration = (offset - bit) * BIT_DURATION; ir_raw_event_store_with_filter(imon->rcdev, &rawir); - } - if (bit >= size) - break; + if (bit == 0) + break; - offset = bit; - while (is_bit_set(imon->ir_buf, bit) && bit < size) - bit++; - dev_dbg(imon->dev, "space: %d bits", bit - offset); + offset = bit; + } + + bit = fls64(~d & (BIT_ULL(offset) - 1)); + dev_dbg(imon->dev, "space: %d bits", offset - bit); rawir.pulse = false; - rawir.duration = (bit - offset) * BIT_DURATION; + rawir.duration = (offset - bit) * BIT_DURATION; ir_raw_event_store_with_filter(imon->rcdev, &rawir); offset = bit; - } + } while (offset > 0); if (imon->ir_buf[7] == 0x0a) { ir_raw_event_set_idle(imon->rcdev, true); diff --git a/drivers/media/rc/keymaps/Makefile b/drivers/media/rc/keymaps/Makefile index d6b913a3032d..5b1399af6b3a 100644 --- a/drivers/media/rc/keymaps/Makefile +++ b/drivers/media/rc/keymaps/Makefile @@ -116,4 +116,5 @@ obj-$(CONFIG_RC_MAP) += rc-adstech-dvb-t-pci.o \ rc-winfast.o \ rc-winfast-usbii-deluxe.o \ rc-su3000.o \ + rc-xbox-dvd.o \ rc-zx-irdec.o diff --git a/drivers/media/rc/keymaps/rc-xbox-dvd.c b/drivers/media/rc/keymaps/rc-xbox-dvd.c new file mode 100644 index 000000000000..af387244636b --- /dev/null +++ b/drivers/media/rc/keymaps/rc-xbox-dvd.c @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Keytable for Xbox DVD remote +// Copyright (c) 2018 by Benjamin Valentin <benpicco@googlemail.com> + +#include <media/rc-map.h> +#include <linux/module.h> + +/* based on lircd.conf.xbox */ +static struct rc_map_table xbox_dvd[] = { + {0xa0b, KEY_OK}, + {0xaa6, KEY_UP}, + {0xaa7, KEY_DOWN}, + {0xaa8, KEY_RIGHT}, + {0xaa9, KEY_LEFT}, + {0xac3, KEY_INFO}, + + {0xac6, KEY_9}, + {0xac7, KEY_8}, + {0xac8, KEY_7}, + {0xac9, KEY_6}, + {0xaca, KEY_5}, + {0xacb, KEY_4}, + {0xacc, KEY_3}, + {0xacd, KEY_2}, + {0xace, KEY_1}, + {0xacf, KEY_0}, + + {0xad5, KEY_ANGLE}, + {0xad8, KEY_BACK}, + {0xadd, KEY_PREVIOUSSONG}, + {0xadf, KEY_NEXTSONG}, + {0xae0, KEY_STOP}, + {0xae2, KEY_REWIND}, + {0xae3, KEY_FASTFORWARD}, + {0xae5, KEY_TITLE}, + {0xae6, KEY_PAUSE}, + {0xaea, KEY_PLAY}, + {0xaf7, KEY_MENU}, +}; + +static struct rc_map_list xbox_dvd_map = { + .map = { + .scan = xbox_dvd, + .size = ARRAY_SIZE(xbox_dvd), + .rc_proto = RC_PROTO_UNKNOWN, + .name = RC_MAP_XBOX_DVD, + } +}; + +static int __init init_rc_map(void) +{ + return rc_map_register(&xbox_dvd_map); +} + +static void __exit exit_rc_map(void) +{ + rc_map_unregister(&xbox_dvd_map); +} + +module_init(init_rc_map) +module_exit(exit_rc_map) + +MODULE_LICENSE("GPL"); diff --git a/drivers/media/rc/mceusb.c b/drivers/media/rc/mceusb.c index c9293696dc2d..8d7d3ef88862 100644 --- a/drivers/media/rc/mceusb.c +++ b/drivers/media/rc/mceusb.c @@ -432,6 +432,15 @@ static const struct usb_device_id mceusb_dev_table[] = { .driver_info = HAUPPAUGE_CX_HYBRID_TV }, { USB_DEVICE(VENDOR_HAUPPAUGE, 0xb139), .driver_info = HAUPPAUGE_CX_HYBRID_TV }, + /* Hauppauge WinTV-HVR-935C - based on cx231xx */ + { USB_DEVICE(VENDOR_HAUPPAUGE, 0xb151), + .driver_info = HAUPPAUGE_CX_HYBRID_TV }, + /* Hauppauge WinTV-HVR-955Q - based on cx231xx */ + { USB_DEVICE(VENDOR_HAUPPAUGE, 0xb123), + .driver_info = HAUPPAUGE_CX_HYBRID_TV }, + /* Hauppauge WinTV-HVR-975 - based on cx231xx */ + { USB_DEVICE(VENDOR_HAUPPAUGE, 0xb150), + .driver_info = HAUPPAUGE_CX_HYBRID_TV }, { USB_DEVICE(VENDOR_PCTV, 0x0259), .driver_info = HAUPPAUGE_CX_HYBRID_TV }, { USB_DEVICE(VENDOR_PCTV, 0x025e), diff --git a/drivers/media/rc/rc-main.c b/drivers/media/rc/rc-main.c index 552bbe82a160..66a174979b3c 100644 --- a/drivers/media/rc/rc-main.c +++ b/drivers/media/rc/rc-main.c @@ -695,7 +695,8 @@ void rc_repeat(struct rc_dev *dev) (dev->last_toggle ? LIRC_SCANCODE_FLAG_TOGGLE : 0) }; - ir_lirc_scancode_event(dev, &sc); + if (dev->allowed_protocols != RC_PROTO_BIT_CEC) + ir_lirc_scancode_event(dev, &sc); spin_lock_irqsave(&dev->keylock, flags); @@ -735,7 +736,8 @@ static void ir_do_keydown(struct rc_dev *dev, enum rc_proto protocol, .keycode = keycode }; - ir_lirc_scancode_event(dev, &sc); + if (dev->allowed_protocols != RC_PROTO_BIT_CEC) + ir_lirc_scancode_event(dev, &sc); if (new_event && dev->keypressed) ir_do_keyup(dev, false); @@ -1950,6 +1952,8 @@ void rc_unregister_device(struct rc_dev *dev) rc_free_rx_device(dev); mutex_lock(&dev->lock); + if (dev->users && dev->close) + dev->close(dev); dev->registered = false; mutex_unlock(&dev->lock); diff --git a/drivers/media/rc/xbox_remote.c b/drivers/media/rc/xbox_remote.c new file mode 100644 index 000000000000..f959cbb94744 --- /dev/null +++ b/drivers/media/rc/xbox_remote.c @@ -0,0 +1,306 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Driver for Xbox DVD Movie Playback Kit +// Copyright (c) 2018 by Benjamin Valentin <benpicco@googlemail.com> + +/* + * Xbox DVD Movie Playback Kit USB IR dongle support + * + * The driver was derived from the ati_remote driver 2.2.1 + * and used information from lirc_xbox.c + * + * Copyright (c) 2011, 2012 Anssi Hannula <anssi.hannula@iki.fi> + * Copyright (c) 2004 Torrey Hoffman <thoffman@arnor.net> + * Copyright (c) 2002 Vladimir Dergachev + * Copyright (c) 2003-2004 Paul Miller <pmiller9@users.sourceforge.net> + */ + +#include <linux/slab.h> +#include <linux/module.h> +#include <linux/usb/input.h> +#include <media/rc-core.h> + +/* + * Module and Version Information + */ +#define DRIVER_VERSION "1.0.0" +#define DRIVER_AUTHOR "Benjamin Valentin <benpicco@googlemail.com>" +#define DRIVER_DESC "Xbox DVD USB Remote Control" + +#define NAME_BUFSIZE 80 /* size of product name, path buffers */ +#define DATA_BUFSIZE 8 /* size of URB data buffers */ + +/* + * USB vendor ids for XBOX DVD Dongles + */ +#define VENDOR_GAMESTER 0x040b +#define VENDOR_MICROSOFT 0x045e + +static const struct usb_device_id xbox_remote_table[] = { + /* Gamester Xbox DVD Movie Playback Kit IR */ + { + USB_DEVICE(VENDOR_GAMESTER, 0x6521), + }, + /* Microsoft Xbox DVD Movie Playback Kit IR */ + { + USB_DEVICE(VENDOR_MICROSOFT, 0x0284), + }, + {} /* Terminating entry */ +}; + +MODULE_DEVICE_TABLE(usb, xbox_remote_table); + +struct xbox_remote { + struct rc_dev *rdev; + struct usb_device *udev; + struct usb_interface *interface; + + struct urb *irq_urb; + unsigned char inbuf[DATA_BUFSIZE] __aligned(sizeof(u16)); + + char rc_name[NAME_BUFSIZE]; + char rc_phys[NAME_BUFSIZE]; +}; + +static int xbox_remote_rc_open(struct rc_dev *rdev) +{ + struct xbox_remote *xbox_remote = rdev->priv; + + /* On first open, submit the read urb which was set up previously. */ + xbox_remote->irq_urb->dev = xbox_remote->udev; + if (usb_submit_urb(xbox_remote->irq_urb, GFP_KERNEL)) { + dev_err(&xbox_remote->interface->dev, + "%s: usb_submit_urb failed!\n", __func__); + return -EIO; + } + + return 0; +} + +static void xbox_remote_rc_close(struct rc_dev *rdev) +{ + struct xbox_remote *xbox_remote = rdev->priv; + + usb_kill_urb(xbox_remote->irq_urb); +} + +/* + * xbox_remote_report_input + */ +static void xbox_remote_input_report(struct urb *urb) +{ + struct xbox_remote *xbox_remote = urb->context; + unsigned char *data = xbox_remote->inbuf; + + /* + * data[0] = 0x00 + * data[1] = length - always 0x06 + * data[2] = the key code + * data[3] = high part of key code + * data[4] = last_press_ms (low) + * data[5] = last_press_ms (high) + */ + + /* Deal with strange looking inputs */ + if (urb->actual_length != 6 || urb->actual_length != data[1]) { + dev_warn(&urb->dev->dev, "Weird data, len=%d: %*ph\n", + urb->actual_length, urb->actual_length, data); + return; + } + + rc_keydown(xbox_remote->rdev, RC_PROTO_UNKNOWN, + le16_to_cpup((__le16 *)(data + 2)), 0); +} + +/* + * xbox_remote_irq_in + */ +static void xbox_remote_irq_in(struct urb *urb) +{ + struct xbox_remote *xbox_remote = urb->context; + int retval; + + switch (urb->status) { + case 0: /* success */ + xbox_remote_input_report(urb); + break; + case -ECONNRESET: /* unlink */ + case -ENOENT: + case -ESHUTDOWN: + dev_dbg(&xbox_remote->interface->dev, + "%s: urb error status, unlink?\n", + __func__); + return; + default: /* error */ + dev_dbg(&xbox_remote->interface->dev, + "%s: Nonzero urb status %d\n", + __func__, urb->status); + } + + retval = usb_submit_urb(urb, GFP_ATOMIC); + if (retval) + dev_err(&xbox_remote->interface->dev, + "%s: usb_submit_urb()=%d\n", + __func__, retval); +} + +static void xbox_remote_rc_init(struct xbox_remote *xbox_remote) +{ + struct rc_dev *rdev = xbox_remote->rdev; + + rdev->priv = xbox_remote; + rdev->allowed_protocols = RC_PROTO_BIT_UNKNOWN; + rdev->driver_name = "xbox_remote"; + + rdev->open = xbox_remote_rc_open; + rdev->close = xbox_remote_rc_close; + + rdev->device_name = xbox_remote->rc_name; + rdev->input_phys = xbox_remote->rc_phys; + + usb_to_input_id(xbox_remote->udev, &rdev->input_id); + rdev->dev.parent = &xbox_remote->interface->dev; +} + +static int xbox_remote_initialize(struct xbox_remote *xbox_remote, + struct usb_endpoint_descriptor *endpoint_in) +{ + struct usb_device *udev = xbox_remote->udev; + int pipe, maxp; + + /* Set up irq_urb */ + pipe = usb_rcvintpipe(udev, endpoint_in->bEndpointAddress); + maxp = usb_maxpacket(udev, pipe, usb_pipeout(pipe)); + maxp = (maxp > DATA_BUFSIZE) ? DATA_BUFSIZE : maxp; + + usb_fill_int_urb(xbox_remote->irq_urb, udev, pipe, xbox_remote->inbuf, + maxp, xbox_remote_irq_in, xbox_remote, + endpoint_in->bInterval); + + return 0; +} + +/* + * xbox_remote_probe + */ +static int xbox_remote_probe(struct usb_interface *interface, + const struct usb_device_id *id) +{ + struct usb_device *udev = interface_to_usbdev(interface); + struct usb_host_interface *iface_host = interface->cur_altsetting; + struct usb_endpoint_descriptor *endpoint_in; + struct xbox_remote *xbox_remote; + struct rc_dev *rc_dev; + int err = -ENOMEM; + + // why is there also a device with no endpoints? + if (iface_host->desc.bNumEndpoints == 0) + return -ENODEV; + + if (iface_host->desc.bNumEndpoints != 1) { + pr_err("%s: Unexpected desc.bNumEndpoints: %d\n", + __func__, iface_host->desc.bNumEndpoints); + return -ENODEV; + } + + endpoint_in = &iface_host->endpoint[0].desc; + + if (!usb_endpoint_is_int_in(endpoint_in)) { + pr_err("%s: Unexpected endpoint_in\n", __func__); + return -ENODEV; + } + if (le16_to_cpu(endpoint_in->wMaxPacketSize) == 0) { + pr_err("%s: endpoint_in message size==0?\n", __func__); + return -ENODEV; + } + + xbox_remote = kzalloc(sizeof(*xbox_remote), GFP_KERNEL); + rc_dev = rc_allocate_device(RC_DRIVER_SCANCODE); + if (!xbox_remote || !rc_dev) + goto exit_free_dev_rdev; + + /* Allocate URB buffer */ + xbox_remote->irq_urb = usb_alloc_urb(0, GFP_KERNEL); + if (!xbox_remote->irq_urb) + goto exit_free_buffers; + + xbox_remote->udev = udev; + xbox_remote->rdev = rc_dev; + xbox_remote->interface = interface; + + usb_make_path(udev, xbox_remote->rc_phys, sizeof(xbox_remote->rc_phys)); + + strlcat(xbox_remote->rc_phys, "/input0", sizeof(xbox_remote->rc_phys)); + + snprintf(xbox_remote->rc_name, sizeof(xbox_remote->rc_name), "%s%s%s", + udev->manufacturer ?: "", + udev->manufacturer && udev->product ? " " : "", + udev->product ?: ""); + + if (!strlen(xbox_remote->rc_name)) + snprintf(xbox_remote->rc_name, sizeof(xbox_remote->rc_name), + DRIVER_DESC "(%04x,%04x)", + le16_to_cpu(xbox_remote->udev->descriptor.idVendor), + le16_to_cpu(xbox_remote->udev->descriptor.idProduct)); + + rc_dev->map_name = RC_MAP_XBOX_DVD; /* default map */ + + xbox_remote_rc_init(xbox_remote); + + /* Device Hardware Initialization */ + err = xbox_remote_initialize(xbox_remote, endpoint_in); + if (err) + goto exit_kill_urbs; + + /* Set up and register rc device */ + err = rc_register_device(xbox_remote->rdev); + if (err) + goto exit_kill_urbs; + + usb_set_intfdata(interface, xbox_remote); + + return 0; + +exit_kill_urbs: + usb_kill_urb(xbox_remote->irq_urb); +exit_free_buffers: + usb_free_urb(xbox_remote->irq_urb); +exit_free_dev_rdev: + rc_free_device(rc_dev); + kfree(xbox_remote); + + return err; +} + +/* + * xbox_remote_disconnect + */ +static void xbox_remote_disconnect(struct usb_interface *interface) +{ + struct xbox_remote *xbox_remote; + + xbox_remote = usb_get_intfdata(interface); + usb_set_intfdata(interface, NULL); + if (!xbox_remote) { + dev_warn(&interface->dev, "%s - null device?\n", __func__); + return; + } + + usb_kill_urb(xbox_remote->irq_urb); + rc_unregister_device(xbox_remote->rdev); + usb_free_urb(xbox_remote->irq_urb); + kfree(xbox_remote); +} + +/* usb specific object to register with the usb subsystem */ +static struct usb_driver xbox_remote_driver = { + .name = "xbox_remote", + .probe = xbox_remote_probe, + .disconnect = xbox_remote_disconnect, + .id_table = xbox_remote_table, +}; + +module_usb_driver(xbox_remote_driver); + +MODULE_AUTHOR(DRIVER_AUTHOR); +MODULE_DESCRIPTION(DRIVER_DESC); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/spi/cxd2880-spi.c b/drivers/media/spi/cxd2880-spi.c index 11ce5101e19f..d5c433e20d4a 100644 --- a/drivers/media/spi/cxd2880-spi.c +++ b/drivers/media/spi/cxd2880-spi.c @@ -10,6 +10,7 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": %s: " fmt, __func__ #include <linux/spi/spi.h> +#include <linux/regulator/consumer.h> #include <linux/ktime.h> #include <media/dvb_demux.h> @@ -51,6 +52,7 @@ struct cxd2880_dvb_spi { struct mutex spi_mutex; /* For SPI access exclusive control */ int feed_count; int all_pid_feed_count; + struct regulator *vcc_supply; u8 *ts_buf; struct cxd2880_pid_filter_config filter_config; }; @@ -518,6 +520,17 @@ cxd2880_spi_probe(struct spi_device *spi) if (!dvb_spi) return -ENOMEM; + dvb_spi->vcc_supply = devm_regulator_get_optional(&spi->dev, "vcc"); + if (IS_ERR(dvb_spi->vcc_supply)) { + if (PTR_ERR(dvb_spi->vcc_supply) == -EPROBE_DEFER) + return -EPROBE_DEFER; + dvb_spi->vcc_supply = NULL; + } else { + ret = regulator_enable(dvb_spi->vcc_supply); + if (ret) + return ret; + } + dvb_spi->spi = spi; mutex_init(&dvb_spi->spi_mutex); dev_set_drvdata(&spi->dev, dvb_spi); @@ -536,6 +549,7 @@ cxd2880_spi_probe(struct spi_device *spi) if (!dvb_attach(cxd2880_attach, &dvb_spi->dvb_fe, &config)) { pr_err("cxd2880_attach failed\n"); + ret = -ENODEV; goto fail_attach; } @@ -630,6 +644,9 @@ cxd2880_spi_remove(struct spi_device *spi) dvb_frontend_detach(&dvb_spi->dvb_fe); dvb_unregister_adapter(&dvb_spi->adapter); + if (dvb_spi->vcc_supply) + regulator_disable(dvb_spi->vcc_supply); + kfree(dvb_spi); pr_info("cxd2880_spi remove ok.\n"); diff --git a/drivers/media/usb/au0828/au0828-video.c b/drivers/media/usb/au0828/au0828-video.c index efbf210147c7..7876c897cc1d 100644 --- a/drivers/media/usb/au0828/au0828-video.c +++ b/drivers/media/usb/au0828/au0828-video.c @@ -1616,27 +1616,42 @@ static int vidioc_g_fmt_vbi_cap(struct file *file, void *priv, return 0; } -static int vidioc_cropcap(struct file *file, void *priv, - struct v4l2_cropcap *cc) +static int vidioc_g_pixelaspect(struct file *file, void *priv, + int type, struct v4l2_fract *f) { struct au0828_dev *dev = video_drvdata(file); - if (cc->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + if (type != V4L2_BUF_TYPE_VIDEO_CAPTURE) return -EINVAL; dprintk(1, "%s called std_set %d dev_state %ld\n", __func__, dev->std_set_in_tuner_core, dev->dev_state); - cc->bounds.left = 0; - cc->bounds.top = 0; - cc->bounds.width = dev->width; - cc->bounds.height = dev->height; + f->numerator = 54; + f->denominator = 59; - cc->defrect = cc->bounds; + return 0; +} + +static int vidioc_g_selection(struct file *file, void *priv, + struct v4l2_selection *s) +{ + struct au0828_dev *dev = video_drvdata(file); - cc->pixelaspect.numerator = 54; - cc->pixelaspect.denominator = 59; + if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + switch (s->target) { + case V4L2_SEL_TGT_CROP_BOUNDS: + case V4L2_SEL_TGT_CROP_DEFAULT: + s->r.left = 0; + s->r.top = 0; + s->r.width = dev->width; + s->r.height = dev->height; + break; + default: + return -EINVAL; + } return 0; } @@ -1762,7 +1777,8 @@ static const struct v4l2_ioctl_ops video_ioctl_ops = { .vidioc_enumaudio = vidioc_enumaudio, .vidioc_g_audio = vidioc_g_audio, .vidioc_s_audio = vidioc_s_audio, - .vidioc_cropcap = vidioc_cropcap, + .vidioc_g_pixelaspect = vidioc_g_pixelaspect, + .vidioc_g_selection = vidioc_g_selection, .vidioc_reqbufs = vb2_ioctl_reqbufs, .vidioc_create_bufs = vb2_ioctl_create_bufs, diff --git a/drivers/media/usb/cpia2/cpia2_v4l.c b/drivers/media/usb/cpia2/cpia2_v4l.c index 3f401fbd0ecc..748739c2b8b2 100644 --- a/drivers/media/usb/cpia2/cpia2_v4l.c +++ b/drivers/media/usb/cpia2/cpia2_v4l.c @@ -479,24 +479,25 @@ static int cpia2_g_fmt_vid_cap(struct file *file, void *fh, * *****************************************************************************/ -static int cpia2_cropcap(struct file *file, void *fh, struct v4l2_cropcap *c) +static int cpia2_g_selection(struct file *file, void *fh, + struct v4l2_selection *s) { struct camera_data *cam = video_drvdata(file); - if (c->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) - return -EINVAL; - - c->bounds.left = 0; - c->bounds.top = 0; - c->bounds.width = cam->width; - c->bounds.height = cam->height; - c->defrect.left = 0; - c->defrect.top = 0; - c->defrect.width = cam->width; - c->defrect.height = cam->height; - c->pixelaspect.numerator = 1; - c->pixelaspect.denominator = 1; + if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + switch (s->target) { + case V4L2_SEL_TGT_CROP_BOUNDS: + case V4L2_SEL_TGT_CROP_DEFAULT: + s->r.left = 0; + s->r.top = 0; + s->r.width = cam->width; + s->r.height = cam->height; + break; + default: + return -EINVAL; + } return 0; } @@ -1047,7 +1048,7 @@ static const struct v4l2_ioctl_ops cpia2_ioctl_ops = { .vidioc_try_fmt_vid_cap = cpia2_try_fmt_vid_cap, .vidioc_g_jpegcomp = cpia2_g_jpegcomp, .vidioc_s_jpegcomp = cpia2_s_jpegcomp, - .vidioc_cropcap = cpia2_cropcap, + .vidioc_g_selection = cpia2_g_selection, .vidioc_reqbufs = cpia2_reqbufs, .vidioc_querybuf = cpia2_querybuf, .vidioc_qbuf = cpia2_qbuf, diff --git a/drivers/media/usb/cx231xx/cx231xx-417.c b/drivers/media/usb/cx231xx/cx231xx-417.c index 2641e23d946b..1c48c497bd6a 100644 --- a/drivers/media/usb/cx231xx/cx231xx-417.c +++ b/drivers/media/usb/cx231xx/cx231xx-417.c @@ -1500,27 +1500,45 @@ static const struct videobuf_queue_ops cx231xx_qops = { /* ------------------------------------------------------------------ */ -static int vidioc_cropcap(struct file *file, void *priv, - struct v4l2_cropcap *cc) +static int vidioc_g_pixelaspect(struct file *file, void *priv, + int type, struct v4l2_fract *f) { struct cx231xx_fh *fh = priv; struct cx231xx *dev = fh->dev; bool is_50hz = dev->encodernorm.id & V4L2_STD_625_50; - if (cc->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + if (type != V4L2_BUF_TYPE_VIDEO_CAPTURE) return -EINVAL; - cc->bounds.left = 0; - cc->bounds.top = 0; - cc->bounds.width = dev->ts1.width; - cc->bounds.height = dev->ts1.height; - cc->defrect = cc->bounds; - cc->pixelaspect.numerator = is_50hz ? 54 : 11; - cc->pixelaspect.denominator = is_50hz ? 59 : 10; + f->numerator = is_50hz ? 54 : 11; + f->denominator = is_50hz ? 59 : 10; return 0; } +static int vidioc_g_selection(struct file *file, void *priv, + struct v4l2_selection *s) +{ + struct cx231xx_fh *fh = priv; + struct cx231xx *dev = fh->dev; + + if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + + switch (s->target) { + case V4L2_SEL_TGT_CROP_BOUNDS: + case V4L2_SEL_TGT_CROP_DEFAULT: + s->r.left = 0; + s->r.top = 0; + s->r.width = dev->ts1.width; + s->r.height = dev->ts1.height; + break; + default: + return -EINVAL; + } + return 0; +} + static int vidioc_g_std(struct file *file, void *fh0, v4l2_std_id *norm) { struct cx231xx_fh *fh = file->private_data; @@ -1865,7 +1883,8 @@ static const struct v4l2_ioctl_ops mpeg_ioctl_ops = { .vidioc_g_input = cx231xx_g_input, .vidioc_s_input = cx231xx_s_input, .vidioc_s_ctrl = vidioc_s_ctrl, - .vidioc_cropcap = vidioc_cropcap, + .vidioc_g_pixelaspect = vidioc_g_pixelaspect, + .vidioc_g_selection = vidioc_g_selection, .vidioc_querycap = cx231xx_querycap, .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, diff --git a/drivers/media/usb/cx231xx/cx231xx-video.c b/drivers/media/usb/cx231xx/cx231xx-video.c index c990f70c0ea6..0d451c4ea3b9 100644 --- a/drivers/media/usb/cx231xx/cx231xx-video.c +++ b/drivers/media/usb/cx231xx/cx231xx-video.c @@ -1482,27 +1482,45 @@ int cx231xx_s_register(struct file *file, void *priv, } #endif -static int vidioc_cropcap(struct file *file, void *priv, - struct v4l2_cropcap *cc) +static int vidioc_g_pixelaspect(struct file *file, void *priv, + int type, struct v4l2_fract *f) { struct cx231xx_fh *fh = priv; struct cx231xx *dev = fh->dev; bool is_50hz = dev->norm & V4L2_STD_625_50; - if (cc->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + if (type != V4L2_BUF_TYPE_VIDEO_CAPTURE) return -EINVAL; - cc->bounds.left = 0; - cc->bounds.top = 0; - cc->bounds.width = dev->width; - cc->bounds.height = dev->height; - cc->defrect = cc->bounds; - cc->pixelaspect.numerator = is_50hz ? 54 : 11; - cc->pixelaspect.denominator = is_50hz ? 59 : 10; + f->numerator = is_50hz ? 54 : 11; + f->denominator = is_50hz ? 59 : 10; return 0; } +static int vidioc_g_selection(struct file *file, void *priv, + struct v4l2_selection *s) +{ + struct cx231xx_fh *fh = priv; + struct cx231xx *dev = fh->dev; + + if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + + switch (s->target) { + case V4L2_SEL_TGT_CROP_BOUNDS: + case V4L2_SEL_TGT_CROP_DEFAULT: + s->r.left = 0; + s->r.top = 0; + s->r.width = dev->width; + s->r.height = dev->height; + break; + default: + return -EINVAL; + } + return 0; +} + static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type type) { @@ -2093,7 +2111,8 @@ static const struct v4l2_ioctl_ops video_ioctl_ops = { .vidioc_g_fmt_vbi_cap = vidioc_g_fmt_vbi_cap, .vidioc_try_fmt_vbi_cap = vidioc_try_fmt_vbi_cap, .vidioc_s_fmt_vbi_cap = vidioc_s_fmt_vbi_cap, - .vidioc_cropcap = vidioc_cropcap, + .vidioc_g_pixelaspect = vidioc_g_pixelaspect, + .vidioc_g_selection = vidioc_g_selection, .vidioc_reqbufs = vidioc_reqbufs, .vidioc_querybuf = vidioc_querybuf, .vidioc_qbuf = vidioc_qbuf, diff --git a/drivers/media/usb/dvb-usb-v2/Kconfig b/drivers/media/usb/dvb-usb-v2/Kconfig index df4412245a8a..511e3f270308 100644 --- a/drivers/media/usb/dvb-usb-v2/Kconfig +++ b/drivers/media/usb/dvb-usb-v2/Kconfig @@ -133,6 +133,7 @@ config DVB_USB_RTL28XXU depends on DVB_USB_V2 && I2C_MUX select DVB_MN88472 if MEDIA_SUBDRV_AUTOSELECT select DVB_MN88473 if MEDIA_SUBDRV_AUTOSELECT + select DVB_CXD2841ER if MEDIA_SUBDRV_AUTOSELECT select DVB_RTL2830 select DVB_RTL2832 select DVB_RTL2832_SDR if (MEDIA_SUBDRV_AUTOSELECT && MEDIA_SDR_SUPPORT) diff --git a/drivers/media/usb/dvb-usb-v2/dvb_usb_core.c b/drivers/media/usb/dvb-usb-v2/dvb_usb_core.c index 3b8f7931b730..d55ef016d418 100644 --- a/drivers/media/usb/dvb-usb-v2/dvb_usb_core.c +++ b/drivers/media/usb/dvb-usb-v2/dvb_usb_core.c @@ -957,9 +957,7 @@ int dvb_usbv2_probe(struct usb_interface *intf, if (d->props->identify_state) { const char *name = NULL; ret = d->props->identify_state(d, &name); - if (ret == 0) { - ; - } else if (ret == COLD) { + if (ret == COLD) { dev_info(&d->udev->dev, "%s: found a '%s' in cold state\n", KBUILD_MODNAME, d->name); @@ -984,7 +982,7 @@ int dvb_usbv2_probe(struct usb_interface *intf, } else { goto err_free_all; } - } else { + } else if (ret != WARM) { goto err_free_all; } } diff --git a/drivers/media/usb/dvb-usb-v2/gl861.c b/drivers/media/usb/dvb-usb-v2/gl861.c index 0559417c8af4..80fed4494736 100644 --- a/drivers/media/usb/dvb-usb-v2/gl861.c +++ b/drivers/media/usb/dvb-usb-v2/gl861.c @@ -200,11 +200,10 @@ gl861_i2c_write_ex(struct dvb_usb_device *d, u8 addr, u8 *wbuf, u16 wlen) u8 *buf; int ret; - buf = kmalloc(wlen, GFP_KERNEL); + buf = kmemdup(wbuf, wlen, GFP_KERNEL); if (!buf) return -ENOMEM; - memcpy(buf, wbuf, wlen); ret = usb_control_msg(d->udev, usb_sndctrlpipe(d->udev, 0), GL861_REQ_I2C_RAW, GL861_WRITE, addr << (8 + 1), 0x0100, buf, wlen, 2000); diff --git a/drivers/media/usb/dvb-usb-v2/lmedm04.c b/drivers/media/usb/dvb-usb-v2/lmedm04.c index f109c04f05ae..602013cf3e69 100644 --- a/drivers/media/usb/dvb-usb-v2/lmedm04.c +++ b/drivers/media/usb/dvb-usb-v2/lmedm04.c @@ -134,9 +134,9 @@ struct lme2510_state { u8 stream_on; u8 pid_size; u8 pid_off; - void *buffer; + u8 int_buffer[128]; struct urb *lme_urb; - void *usb_buffer; + u8 usb_buffer[64]; /* Frontend original calls */ int (*fe_read_status)(struct dvb_frontend *, enum fe_status *); int (*fe_read_signal_strength)(struct dvb_frontend *, u16 *); @@ -147,59 +147,30 @@ struct lme2510_state { u8 dvb_usb_lme2510_firmware; }; -static int lme2510_bulk_write(struct usb_device *dev, - u8 *snd, int len, u8 pipe) -{ - int actual_l; - - return usb_bulk_msg(dev, usb_sndbulkpipe(dev, pipe), - snd, len, &actual_l, 100); -} - -static int lme2510_bulk_read(struct usb_device *dev, - u8 *rev, int len, u8 pipe) -{ - int actual_l; - - return usb_bulk_msg(dev, usb_rcvbulkpipe(dev, pipe), - rev, len, &actual_l, 200); -} - static int lme2510_usb_talk(struct dvb_usb_device *d, - u8 *wbuf, int wlen, u8 *rbuf, int rlen) + u8 *wbuf, int wlen, u8 *rbuf, int rlen) { struct lme2510_state *st = d->priv; - u8 *buff; int ret = 0; - if (st->usb_buffer == NULL) { - st->usb_buffer = kmalloc(64, GFP_KERNEL); - if (st->usb_buffer == NULL) { - info("MEM Error no memory"); - return -ENOMEM; - } - } - buff = st->usb_buffer; + if (max(wlen, rlen) > sizeof(st->usb_buffer)) + return -EINVAL; ret = mutex_lock_interruptible(&d->usb_mutex); - if (ret < 0) return -EAGAIN; - /* the read/write capped at 64 */ - memcpy(buff, wbuf, (wlen < 64) ? wlen : 64); + memcpy(st->usb_buffer, wbuf, wlen); - ret |= lme2510_bulk_write(d->udev, buff, wlen , 0x01); + ret = dvb_usbv2_generic_rw_locked(d, st->usb_buffer, wlen, + st->usb_buffer, rlen); - ret |= lme2510_bulk_read(d->udev, buff, (rlen < 64) ? - rlen : 64 , 0x01); - - if (rlen > 0) - memcpy(rbuf, buff, rlen); + if (rlen) + memcpy(rbuf, st->usb_buffer, rlen); mutex_unlock(&d->usb_mutex); - return (ret < 0) ? -ENODEV : 0; + return ret; } static int lme2510_stream_restart(struct dvb_usb_device *d) @@ -417,20 +388,14 @@ static int lme2510_int_read(struct dvb_usb_adapter *adap) if (lme_int->lme_urb == NULL) return -ENOMEM; - lme_int->buffer = usb_alloc_coherent(d->udev, 128, GFP_ATOMIC, - &lme_int->lme_urb->transfer_dma); - - if (lme_int->buffer == NULL) - return -ENOMEM; - usb_fill_int_urb(lme_int->lme_urb, - d->udev, - usb_rcvintpipe(d->udev, 0xa), - lme_int->buffer, - 128, - lme2510_int_response, - adap, - 8); + d->udev, + usb_rcvintpipe(d->udev, 0xa), + lme_int->int_buffer, + sizeof(lme_int->int_buffer), + lme2510_int_response, + adap, + 8); /* Quirk of pipe reporting PIPE_BULK but behaves as interrupt */ ep = usb_pipe_endpoint(d->udev, lme_int->lme_urb->pipe); @@ -438,8 +403,6 @@ static int lme2510_int_read(struct dvb_usb_adapter *adap) if (usb_endpoint_type(&ep->desc) == USB_ENDPOINT_XFER_BULK) lme_int->lme_urb->pipe = usb_rcvbulkpipe(d->udev, 0xa), - lme_int->lme_urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP; - usb_submit_urb(lme_int->lme_urb, GFP_ATOMIC); info("INT Interrupt Service Started"); @@ -1245,41 +1208,20 @@ static int lme2510_get_rc_config(struct dvb_usb_device *d, return 0; } -static void *lme2510_exit_int(struct dvb_usb_device *d) +static void lme2510_exit(struct dvb_usb_device *d) { struct lme2510_state *st = d->priv; struct dvb_usb_adapter *adap = &d->adapter[0]; - void *buffer = NULL; if (adap != NULL) { lme2510_kill_urb(&adap->stream); } - if (st->usb_buffer != NULL) { - st->i2c_talk_onoff = 1; - st->signal_level = 0; - st->signal_sn = 0; - buffer = st->usb_buffer; - } - - if (st->lme_urb != NULL) { + if (st->lme_urb) { usb_kill_urb(st->lme_urb); - usb_free_coherent(d->udev, 128, st->buffer, - st->lme_urb->transfer_dma); + usb_free_urb(st->lme_urb); info("Interrupt Service Stopped"); } - - return buffer; -} - -static void lme2510_exit(struct dvb_usb_device *d) -{ - void *usb_buffer; - - if (d != NULL) { - usb_buffer = lme2510_exit_int(d); - kfree(usb_buffer); - } } static struct dvb_usb_device_properties lme2510_props = { @@ -1288,6 +1230,8 @@ static struct dvb_usb_device_properties lme2510_props = { .bInterfaceNumber = 0, .adapter_nr = adapter_nr, .size_of_priv = sizeof(struct lme2510_state), + .generic_bulk_ctrl_endpoint = 0x01, + .generic_bulk_ctrl_endpoint_response = 0x01, .download_firmware = lme2510_download_firmware, diff --git a/drivers/media/usb/dvb-usb-v2/rtl28xxu.c b/drivers/media/usb/dvb-usb-v2/rtl28xxu.c index 8a83b10e50e0..d0075cb743b2 100644 --- a/drivers/media/usb/dvb-usb-v2/rtl28xxu.c +++ b/drivers/media/usb/dvb-usb-v2/rtl28xxu.c @@ -384,6 +384,7 @@ static int rtl2832u_read_config(struct dvb_usb_device *d) struct rtl28xxu_req req_r828d = {0x0074, CMD_I2C_RD, 1, buf}; struct rtl28xxu_req req_mn88472 = {0xff38, CMD_I2C_RD, 1, buf}; struct rtl28xxu_req req_mn88473 = {0xff38, CMD_I2C_RD, 1, buf}; + struct rtl28xxu_req req_cxd2837er = {0xfdd8, CMD_I2C_RD, 1, buf}; struct rtl28xxu_req req_si2157 = {0x00c0, CMD_I2C_RD, 1, buf}; struct rtl28xxu_req req_si2168 = {0x00c8, CMD_I2C_RD, 1, buf}; @@ -540,7 +541,18 @@ tuner_found: /* probe slave demod */ if (dev->tuner == TUNER_RTL2832_R828D) { - /* power on MN88472 demod on GPIO0 */ + /* power off slave demod on GPIO0 to reset CXD2837ER */ + ret = rtl28xxu_wr_reg_mask(d, SYS_GPIO_OUT_VAL, 0x00, 0x01); + if (ret) + goto err; + + ret = rtl28xxu_wr_reg_mask(d, SYS_GPIO_OUT_EN, 0x00, 0x01); + if (ret) + goto err; + + msleep(50); + + /* power on slave demod on GPIO0 */ ret = rtl28xxu_wr_reg_mask(d, SYS_GPIO_OUT_VAL, 0x01, 0x01); if (ret) goto err; @@ -553,7 +565,7 @@ tuner_found: if (ret) goto err; - /* check MN88472 answers */ + /* check slave answers */ ret = rtl28xxu_ctrl_msg(d, &req_mn88472); if (ret == 0 && buf[0] == 0x02) { dev_dbg(&d->intf->dev, "MN88472 found\n"); @@ -567,6 +579,13 @@ tuner_found: dev->slave_demod = SLAVE_DEMOD_MN88473; goto demod_found; } + + ret = rtl28xxu_ctrl_msg(d, &req_cxd2837er); + if (ret == 0 && buf[0] == 0xb1) { + dev_dbg(&d->intf->dev, "CXD2837ER found\n"); + dev->slave_demod = SLAVE_DEMOD_CXD2837ER; + goto demod_found; + } } if (dev->tuner == TUNER_RTL2832_SI2157) { /* check Si2168 ID register; reg=c8 val=80 */ @@ -989,6 +1008,23 @@ static int rtl2832u_frontend_attach(struct dvb_usb_adapter *adap) } dev->i2c_client_slave_demod = client; + } else if (dev->slave_demod == SLAVE_DEMOD_CXD2837ER) { + struct cxd2841er_config cxd2837er_config = {}; + + cxd2837er_config.i2c_addr = 0xd8; + cxd2837er_config.xtal = SONY_XTAL_20500; + cxd2837er_config.flags = (CXD2841ER_AUTO_IFHZ | + CXD2841ER_NO_AGCNEG | CXD2841ER_TSBITS | + CXD2841ER_EARLY_TUNE | CXD2841ER_TS_SERIAL); + adap->fe[1] = dvb_attach(cxd2841er_attach_t_c, + &cxd2837er_config, + &d->i2c_adap); + if (!adap->fe[1]) { + dev->slave_demod = SLAVE_DEMOD_NONE; + goto err_slave_demod_failed; + } + adap->fe[1]->id = 1; + dev->i2c_client_slave_demod = NULL; } else { struct si2168_config si2168_config = {}; struct i2c_adapter *adapter; diff --git a/drivers/media/usb/dvb-usb-v2/rtl28xxu.h b/drivers/media/usb/dvb-usb-v2/rtl28xxu.h index 138062960a73..197f4e339605 100644 --- a/drivers/media/usb/dvb-usb-v2/rtl28xxu.h +++ b/drivers/media/usb/dvb-usb-v2/rtl28xxu.h @@ -31,6 +31,7 @@ #include "rtl2832_sdr.h" #include "mn88472.h" #include "mn88473.h" +#include "cxd2841er.h" #include "qt1010.h" #include "mt2060.h" @@ -87,7 +88,8 @@ struct rtl28xxu_dev { #define SLAVE_DEMOD_MN88472 1 #define SLAVE_DEMOD_MN88473 2 #define SLAVE_DEMOD_SI2168 3 - unsigned int slave_demod:2; + #define SLAVE_DEMOD_CXD2837ER 4 + unsigned int slave_demod:3; union { struct rtl2830_platform_data rtl2830_platform_data; struct rtl2832_platform_data rtl2832_platform_data; diff --git a/drivers/media/usb/dvb-usb-v2/usb_urb.c b/drivers/media/usb/dvb-usb-v2/usb_urb.c index 024c751eb165..2ad2ddeaff51 100644 --- a/drivers/media/usb/dvb-usb-v2/usb_urb.c +++ b/drivers/media/usb/dvb-usb-v2/usb_urb.c @@ -155,7 +155,6 @@ static int usb_urb_alloc_bulk_urbs(struct usb_data_stream *stream) stream->props.u.bulk.buffersize, usb_urb_complete, stream); - stream->urb_list[i]->transfer_flags = URB_FREE_BUFFER; stream->urbs_initialized++; } return 0; @@ -186,7 +185,7 @@ static int usb_urb_alloc_isoc_urbs(struct usb_data_stream *stream) urb->complete = usb_urb_complete; urb->pipe = usb_rcvisocpipe(stream->udev, stream->props.endpoint); - urb->transfer_flags = URB_ISO_ASAP | URB_FREE_BUFFER; + urb->transfer_flags = URB_ISO_ASAP; urb->interval = stream->props.u.isoc.interval; urb->number_of_packets = stream->props.u.isoc.framesperurb; urb->transfer_buffer_length = stream->props.u.isoc.framesize * @@ -210,7 +209,7 @@ static int usb_free_stream_buffers(struct usb_data_stream *stream) if (stream->state & USB_STATE_URB_BUF) { while (stream->buf_num) { stream->buf_num--; - stream->buf_list[stream->buf_num] = NULL; + kfree(stream->buf_list[stream->buf_num]); } } diff --git a/drivers/media/usb/dvb-usb/dib0700_devices.c b/drivers/media/usb/dvb-usb/dib0700_devices.c index 7551dce96f64..9311f7d4bba5 100644 --- a/drivers/media/usb/dvb-usb/dib0700_devices.c +++ b/drivers/media/usb/dvb-usb/dib0700_devices.c @@ -29,7 +29,7 @@ static int force_lna_activation; module_param(force_lna_activation, int, 0644); -MODULE_PARM_DESC(force_lna_activation, "force the activation of Low-Noise-Amplifyer(s) (LNA), if applicable for the device (default: 0=automatic/off)."); +MODULE_PARM_DESC(force_lna_activation, "force the activation of Low-Noise-Amplifier(s) (LNA), if applicable for the device (default: 0=automatic/off)."); struct dib0700_adapter_state { int (*set_param_save) (struct dvb_frontend *); diff --git a/drivers/media/usb/dvb-usb/friio-fe.c b/drivers/media/usb/dvb-usb/friio-fe.c deleted file mode 100644 index e6bd0ed8d789..000000000000 --- a/drivers/media/usb/dvb-usb/friio-fe.c +++ /dev/null @@ -1,440 +0,0 @@ -/* DVB USB compliant Linux driver for the Friio USB2.0 ISDB-T receiver. - * - * Copyright (C) 2009 Akihiro Tsukada <tskd2@yahoo.co.jp> - * - * This module is based off the the gl861 and vp702x modules. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the Free - * Software Foundation, version 2. - * - * see Documentation/media/dvb-drivers/dvb-usb.rst for more information - */ -#include <linux/init.h> -#include <linux/string.h> -#include <linux/slab.h> -#include <linux/kernel.h> - -#include "friio.h" - -struct jdvbt90502_state { - struct i2c_adapter *i2c; - struct dvb_frontend frontend; - struct jdvbt90502_config config; -}; - -/* NOTE: TC90502 has 16bit register-address? */ -/* register 0x0100 is used for reading PLL status, so reg is u16 here */ -static int jdvbt90502_reg_read(struct jdvbt90502_state *state, - const u16 reg, u8 *buf, const size_t count) -{ - int ret; - u8 wbuf[3]; - struct i2c_msg msg[2]; - - wbuf[0] = reg & 0xFF; - wbuf[1] = 0; - wbuf[2] = reg >> 8; - - msg[0].addr = state->config.demod_address; - msg[0].flags = 0; - msg[0].buf = wbuf; - msg[0].len = sizeof(wbuf); - - msg[1].addr = msg[0].addr; - msg[1].flags = I2C_M_RD; - msg[1].buf = buf; - msg[1].len = count; - - ret = i2c_transfer(state->i2c, msg, 2); - if (ret != 2) { - deb_fe(" reg read failed.\n"); - return -EREMOTEIO; - } - return 0; -} - -/* currently 16bit register-address is not used, so reg is u8 here */ -static int jdvbt90502_single_reg_write(struct jdvbt90502_state *state, - const u8 reg, const u8 val) -{ - struct i2c_msg msg; - u8 wbuf[2]; - - wbuf[0] = reg; - wbuf[1] = val; - - msg.addr = state->config.demod_address; - msg.flags = 0; - msg.buf = wbuf; - msg.len = sizeof(wbuf); - - if (i2c_transfer(state->i2c, &msg, 1) != 1) { - deb_fe(" reg write failed."); - return -EREMOTEIO; - } - return 0; -} - -static int _jdvbt90502_write(struct dvb_frontend *fe, const u8 buf[], int len) -{ - struct jdvbt90502_state *state = fe->demodulator_priv; - int err, i; - for (i = 0; i < len - 1; i++) { - err = jdvbt90502_single_reg_write(state, - buf[0] + i, buf[i + 1]); - if (err) - return err; - } - - return 0; -} - -/* read pll status byte via the demodulator's I2C register */ -/* note: Win box reads it by 8B block at the I2C addr 0x30 from reg:0x80 */ -static int jdvbt90502_pll_read(struct jdvbt90502_state *state, u8 *result) -{ - int ret; - - /* +1 for reading */ - u8 pll_addr_byte = (state->config.pll_address << 1) + 1; - - *result = 0; - - ret = jdvbt90502_single_reg_write(state, JDVBT90502_2ND_I2C_REG, - pll_addr_byte); - if (ret) - goto error; - - ret = jdvbt90502_reg_read(state, 0x0100, result, 1); - if (ret) - goto error; - - deb_fe("PLL read val:%02x\n", *result); - return 0; - -error: - deb_fe("%s:ret == %d\n", __func__, ret); - return -EREMOTEIO; -} - - -/* set pll frequency via the demodulator's I2C register */ -static int jdvbt90502_pll_set_freq(struct jdvbt90502_state *state, u32 freq) -{ - int ret; - int retry; - u8 res1; - u8 res2[9]; - - u8 pll_freq_cmd[PLL_CMD_LEN]; - u8 pll_agc_cmd[PLL_CMD_LEN]; - struct i2c_msg msg[2]; - u32 f; - - deb_fe("%s: freq=%d, step=%d\n", __func__, freq, - state->frontend.ops.info.frequency_stepsize_hz); - /* freq -> oscilator frequency conversion. */ - /* freq: 473,000,000 + n*6,000,000 [+ 142857 (center freq. shift)] */ - f = freq / state->frontend.ops.info.frequency_stepsize_hz; - /* add 399[1/7 MHZ] = 57MHz for the IF */ - f += 399; - /* add center frequency shift if necessary */ - if (f % 7 == 0) - f++; - pll_freq_cmd[DEMOD_REDIRECT_REG] = JDVBT90502_2ND_I2C_REG; /* 0xFE */ - pll_freq_cmd[ADDRESS_BYTE] = state->config.pll_address << 1; - pll_freq_cmd[DIVIDER_BYTE1] = (f >> 8) & 0x7F; - pll_freq_cmd[DIVIDER_BYTE2] = f & 0xFF; - pll_freq_cmd[CONTROL_BYTE] = 0xB2; /* ref.divider:28, 4MHz/28=1/7MHz */ - pll_freq_cmd[BANDSWITCH_BYTE] = 0x08; /* UHF band */ - - msg[0].addr = state->config.demod_address; - msg[0].flags = 0; - msg[0].buf = pll_freq_cmd; - msg[0].len = sizeof(pll_freq_cmd); - - ret = i2c_transfer(state->i2c, &msg[0], 1); - if (ret != 1) - goto error; - - udelay(50); - - pll_agc_cmd[DEMOD_REDIRECT_REG] = pll_freq_cmd[DEMOD_REDIRECT_REG]; - pll_agc_cmd[ADDRESS_BYTE] = pll_freq_cmd[ADDRESS_BYTE]; - pll_agc_cmd[DIVIDER_BYTE1] = pll_freq_cmd[DIVIDER_BYTE1]; - pll_agc_cmd[DIVIDER_BYTE2] = pll_freq_cmd[DIVIDER_BYTE2]; - pll_agc_cmd[CONTROL_BYTE] = 0x9A; /* AGC_CTRL instead of BANDSWITCH */ - pll_agc_cmd[AGC_CTRL_BYTE] = 0x50; - /* AGC Time Constant 2s, AGC take-over point:103dBuV(lowest) */ - - msg[1].addr = msg[0].addr; - msg[1].flags = 0; - msg[1].buf = pll_agc_cmd; - msg[1].len = sizeof(pll_agc_cmd); - - ret = i2c_transfer(state->i2c, &msg[1], 1); - if (ret != 1) - goto error; - - /* I don't know what these cmds are for, */ - /* but the USB log on a windows box contains them */ - ret = jdvbt90502_single_reg_write(state, 0x01, 0x40); - ret |= jdvbt90502_single_reg_write(state, 0x01, 0x00); - if (ret) - goto error; - udelay(100); - - /* wait for the demod to be ready? */ -#define RETRY_COUNT 5 - for (retry = 0; retry < RETRY_COUNT; retry++) { - ret = jdvbt90502_reg_read(state, 0x0096, &res1, 1); - if (ret) - goto error; - /* if (res1 != 0x00) goto error; */ - ret = jdvbt90502_reg_read(state, 0x00B0, res2, sizeof(res2)); - if (ret) - goto error; - if (res2[0] >= 0xA7) - break; - msleep(100); - } - if (retry >= RETRY_COUNT) { - deb_fe("%s: FE does not get ready after freq setting.\n", - __func__); - return -EREMOTEIO; - } - - return 0; -error: - deb_fe("%s:ret == %d\n", __func__, ret); - return -EREMOTEIO; -} - -static int jdvbt90502_read_status(struct dvb_frontend *fe, - enum fe_status *state) -{ - u8 result; - int ret; - - *state = FE_HAS_SIGNAL; - - ret = jdvbt90502_pll_read(fe->demodulator_priv, &result); - if (ret) { - deb_fe("%s:ret == %d\n", __func__, ret); - return -EREMOTEIO; - } - - *state = FE_HAS_SIGNAL - | FE_HAS_CARRIER - | FE_HAS_VITERBI - | FE_HAS_SYNC; - - if (result & PLL_STATUS_LOCKED) - *state |= FE_HAS_LOCK; - - return 0; -} - -static int jdvbt90502_read_signal_strength(struct dvb_frontend *fe, - u16 *strength) -{ - int ret; - u8 rbuf[37]; - - *strength = 0; - - /* status register (incl. signal strength) : 0x89 */ - /* TODO: read just the necessary registers [0x8B..0x8D]? */ - ret = jdvbt90502_reg_read(fe->demodulator_priv, 0x0089, - rbuf, sizeof(rbuf)); - - if (ret) { - deb_fe("%s:ret == %d\n", __func__, ret); - return -EREMOTEIO; - } - - /* signal_strength: rbuf[2-4] (24bit BE), use lower 16bit for now. */ - *strength = (rbuf[3] << 8) + rbuf[4]; - if (rbuf[2]) - *strength = 0xffff; - - return 0; -} - -static int jdvbt90502_set_frontend(struct dvb_frontend *fe) -{ - struct dtv_frontend_properties *p = &fe->dtv_property_cache; - - /** - * NOTE: ignore all the parameters except frequency. - * others should be fixed to the proper value for ISDB-T, - * but don't check here. - */ - - struct jdvbt90502_state *state = fe->demodulator_priv; - int ret; - - deb_fe("%s: Freq:%d\n", __func__, p->frequency); - - /* This driver only works on auto mode */ - p->inversion = INVERSION_AUTO; - p->bandwidth_hz = 6000000; - p->code_rate_HP = FEC_AUTO; - p->code_rate_LP = FEC_AUTO; - p->modulation = QAM_64; - p->transmission_mode = TRANSMISSION_MODE_AUTO; - p->guard_interval = GUARD_INTERVAL_AUTO; - p->hierarchy = HIERARCHY_AUTO; - p->delivery_system = SYS_ISDBT; - - ret = jdvbt90502_pll_set_freq(state, p->frequency); - if (ret) { - deb_fe("%s:ret == %d\n", __func__, ret); - return -EREMOTEIO; - } - - return 0; -} - - -/* - * (reg, val) commad list to initialize this module. - * captured on a Windows box. - */ -static u8 init_code[][2] = { - {0x01, 0x40}, - {0x04, 0x38}, - {0x05, 0x40}, - {0x07, 0x40}, - {0x0F, 0x4F}, - {0x11, 0x21}, - {0x12, 0x0B}, - {0x13, 0x2F}, - {0x14, 0x31}, - {0x16, 0x02}, - {0x21, 0xC4}, - {0x22, 0x20}, - {0x2C, 0x79}, - {0x2D, 0x34}, - {0x2F, 0x00}, - {0x30, 0x28}, - {0x31, 0x31}, - {0x32, 0xDF}, - {0x38, 0x01}, - {0x39, 0x78}, - {0x3B, 0x33}, - {0x3C, 0x33}, - {0x48, 0x90}, - {0x51, 0x68}, - {0x5E, 0x38}, - {0x71, 0x00}, - {0x72, 0x08}, - {0x77, 0x00}, - {0xC0, 0x21}, - {0xC1, 0x10}, - {0xE4, 0x1A}, - {0xEA, 0x1F}, - {0x77, 0x00}, - {0x71, 0x00}, - {0x71, 0x00}, - {0x76, 0x0C}, -}; - -static int jdvbt90502_init(struct dvb_frontend *fe) -{ - int i = -1; - int ret; - struct i2c_msg msg; - - struct jdvbt90502_state *state = fe->demodulator_priv; - - deb_fe("%s called.\n", __func__); - - msg.addr = state->config.demod_address; - msg.flags = 0; - msg.len = 2; - for (i = 0; i < ARRAY_SIZE(init_code); i++) { - msg.buf = init_code[i]; - ret = i2c_transfer(state->i2c, &msg, 1); - if (ret != 1) - goto error; - } - fe->dtv_property_cache.delivery_system = SYS_ISDBT; - msleep(100); - - return 0; - -error: - deb_fe("%s: init_code[%d] failed. ret==%d\n", __func__, i, ret); - return -EREMOTEIO; -} - - -static void jdvbt90502_release(struct dvb_frontend *fe) -{ - struct jdvbt90502_state *state = fe->demodulator_priv; - kfree(state); -} - - -static const struct dvb_frontend_ops jdvbt90502_ops; - -struct dvb_frontend *jdvbt90502_attach(struct dvb_usb_device *d) -{ - struct jdvbt90502_state *state = NULL; - - deb_info("%s called.\n", __func__); - - /* allocate memory for the internal state */ - state = kzalloc(sizeof(struct jdvbt90502_state), GFP_KERNEL); - if (state == NULL) - goto error; - - /* setup the state */ - state->i2c = &d->i2c_adap; - state->config = friio_fe_config; - - /* create dvb_frontend */ - state->frontend.ops = jdvbt90502_ops; - state->frontend.demodulator_priv = state; - - if (jdvbt90502_init(&state->frontend) < 0) - goto error; - - return &state->frontend; - -error: - kfree(state); - return NULL; -} - -static const struct dvb_frontend_ops jdvbt90502_ops = { - .delsys = { SYS_ISDBT }, - .info = { - .name = "Comtech JDVBT90502 ISDB-T", - .frequency_min_hz = 473000000, /* UHF 13ch, center */ - .frequency_max_hz = 767142857, /* UHF 62ch, center */ - .frequency_stepsize_hz = JDVBT90502_PLL_CLK / JDVBT90502_PLL_DIVIDER, - - /* NOTE: this driver ignores all parameters but frequency. */ - .caps = FE_CAN_INVERSION_AUTO | - FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | - FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 | - FE_CAN_FEC_7_8 | FE_CAN_FEC_8_9 | FE_CAN_FEC_AUTO | - FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | - FE_CAN_TRANSMISSION_MODE_AUTO | - FE_CAN_GUARD_INTERVAL_AUTO | - FE_CAN_HIERARCHY_AUTO, - }, - - .release = jdvbt90502_release, - - .init = jdvbt90502_init, - .write = _jdvbt90502_write, - - .set_frontend = jdvbt90502_set_frontend, - - .read_status = jdvbt90502_read_status, - .read_signal_strength = jdvbt90502_read_signal_strength, -}; diff --git a/drivers/media/usb/dvb-usb/friio.c b/drivers/media/usb/dvb-usb/friio.c deleted file mode 100644 index fe799a7ad44b..000000000000 --- a/drivers/media/usb/dvb-usb/friio.c +++ /dev/null @@ -1,522 +0,0 @@ -/* DVB USB compliant Linux driver for the Friio USB2.0 ISDB-T receiver. - * - * Copyright (C) 2009 Akihiro Tsukada <tskd2@yahoo.co.jp> - * - * This module is based off the the gl861 and vp702x modules. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the Free - * Software Foundation, version 2. - * - * see Documentation/media/dvb-drivers/dvb-usb.rst for more information - */ -#include "friio.h" - -/* debug */ -int dvb_usb_friio_debug; -module_param_named(debug, dvb_usb_friio_debug, int, 0644); -MODULE_PARM_DESC(debug, - "set debugging level (1=info,2=xfer,4=rc,8=fe (or-able))." - DVB_USB_DEBUG_STATUS); - -DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); - -/* - * Indirect I2C access to the PLL via FE. - * whole I2C protocol data to the PLL is sent via the FE's I2C register. - * This is done by a control msg to the FE with the I2C data accompanied, and - * a specific USB request number is assigned for that purpose. - * - * this func sends wbuf[1..] to the I2C register wbuf[0] at addr (= at FE). - * TODO: refoctored, smarter i2c functions. - */ -static int gl861_i2c_ctrlmsg_data(struct dvb_usb_device *d, u8 addr, - u8 *wbuf, u16 wlen, u8 *rbuf, u16 rlen) -{ - u16 index = wbuf[0]; /* must be JDVBT90502_2ND_I2C_REG(=0xFE) */ - u16 value = addr << (8 + 1); - int wo = (rbuf == NULL || rlen == 0); /* write only */ - u8 req, type; - - deb_xfer("write to PLL:0x%02x via FE reg:0x%02x, len:%d\n", - wbuf[1], wbuf[0], wlen - 1); - - if (wo && wlen >= 2) { - req = GL861_REQ_I2C_DATA_CTRL_WRITE; - type = GL861_WRITE; - udelay(20); - return usb_control_msg(d->udev, usb_sndctrlpipe(d->udev, 0), - req, type, value, index, - &wbuf[1], wlen - 1, 2000); - } - - deb_xfer("not supported ctrl-msg, aborting."); - return -EINVAL; -} - -/* normal I2C access (without extra data arguments). - * write to the register wbuf[0] at I2C address addr with the value wbuf[1], - * or read from the register wbuf[0]. - * register address can be 16bit (wbuf[2]<<8 | wbuf[0]) if wlen==3 - */ -static int gl861_i2c_msg(struct dvb_usb_device *d, u8 addr, - u8 *wbuf, u16 wlen, u8 *rbuf, u16 rlen) -{ - u16 index; - u16 value = addr << (8 + 1); - int wo = (rbuf == NULL || rlen == 0); /* write-only */ - u8 req, type; - unsigned int pipe; - - /* special case for the indirect I2C access to the PLL via FE, */ - if (addr == friio_fe_config.demod_address && - wbuf[0] == JDVBT90502_2ND_I2C_REG) - return gl861_i2c_ctrlmsg_data(d, addr, wbuf, wlen, rbuf, rlen); - - if (wo) { - req = GL861_REQ_I2C_WRITE; - type = GL861_WRITE; - pipe = usb_sndctrlpipe(d->udev, 0); - } else { /* rw */ - req = GL861_REQ_I2C_READ; - type = GL861_READ; - pipe = usb_rcvctrlpipe(d->udev, 0); - } - - switch (wlen) { - case 1: - index = wbuf[0]; - break; - case 2: - index = wbuf[0]; - value = value + wbuf[1]; - break; - case 3: - /* special case for 16bit register-address */ - index = (wbuf[2] << 8) | wbuf[0]; - value = value + wbuf[1]; - break; - default: - deb_xfer("wlen = %x, aborting.", wlen); - return -EINVAL; - } - msleep(1); - return usb_control_msg(d->udev, pipe, req, type, - value, index, rbuf, rlen, 2000); -} - -/* I2C */ -static int gl861_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msg[], - int num) -{ - struct dvb_usb_device *d = i2c_get_adapdata(adap); - int i; - - - if (num > 2) - return -EINVAL; - - if (mutex_lock_interruptible(&d->i2c_mutex) < 0) - return -EAGAIN; - - for (i = 0; i < num; i++) { - /* write/read request */ - if (i + 1 < num && (msg[i + 1].flags & I2C_M_RD)) { - if (gl861_i2c_msg(d, msg[i].addr, - msg[i].buf, msg[i].len, - msg[i + 1].buf, msg[i + 1].len) < 0) - break; - i++; - } else - if (gl861_i2c_msg(d, msg[i].addr, msg[i].buf, - msg[i].len, NULL, 0) < 0) - break; - } - - mutex_unlock(&d->i2c_mutex); - return i; -} - -static u32 gl861_i2c_func(struct i2c_adapter *adapter) -{ - return I2C_FUNC_I2C; -} - -static int friio_ext_ctl(struct dvb_usb_adapter *adap, - u32 sat_color, int lnb_on) -{ - int i; - int ret; - struct i2c_msg msg; - u8 *buf; - u32 mask; - u8 lnb = (lnb_on) ? FRIIO_CTL_LNB : 0; - - buf = kmalloc(2, GFP_KERNEL); - if (!buf) - return -ENOMEM; - - msg.addr = 0x00; - msg.flags = 0; - msg.len = 2; - msg.buf = buf; - - buf[0] = 0x00; - - /* send 2bit header (&B10) */ - buf[1] = lnb | FRIIO_CTL_LED | FRIIO_CTL_STROBE; - ret = gl861_i2c_xfer(&adap->dev->i2c_adap, &msg, 1); - buf[1] |= FRIIO_CTL_CLK; - ret += gl861_i2c_xfer(&adap->dev->i2c_adap, &msg, 1); - - buf[1] = lnb | FRIIO_CTL_STROBE; - ret += gl861_i2c_xfer(&adap->dev->i2c_adap, &msg, 1); - buf[1] |= FRIIO_CTL_CLK; - ret += gl861_i2c_xfer(&adap->dev->i2c_adap, &msg, 1); - - /* send 32bit(satur, R, G, B) data in serial */ - mask = 1 << 31; - for (i = 0; i < 32; i++) { - buf[1] = lnb | FRIIO_CTL_STROBE; - if (sat_color & mask) - buf[1] |= FRIIO_CTL_LED; - ret += gl861_i2c_xfer(&adap->dev->i2c_adap, &msg, 1); - buf[1] |= FRIIO_CTL_CLK; - ret += gl861_i2c_xfer(&adap->dev->i2c_adap, &msg, 1); - mask >>= 1; - } - - /* set the strobe off */ - buf[1] = lnb; - ret += gl861_i2c_xfer(&adap->dev->i2c_adap, &msg, 1); - buf[1] |= FRIIO_CTL_CLK; - ret += gl861_i2c_xfer(&adap->dev->i2c_adap, &msg, 1); - - kfree(buf); - return (ret == 70); -} - - -static int friio_streaming_ctrl(struct dvb_usb_adapter *adap, int onoff); - -/* TODO: move these init cmds to the FE's init routine? */ -static u8 streaming_init_cmds[][2] = { - {0x33, 0x08}, - {0x37, 0x40}, - {0x3A, 0x1F}, - {0x3B, 0xFF}, - {0x3C, 0x1F}, - {0x3D, 0xFF}, - {0x38, 0x00}, - {0x35, 0x00}, - {0x39, 0x00}, - {0x36, 0x00}, -}; -static int cmdlen = sizeof(streaming_init_cmds) / 2; - -/* - * Command sequence in this init function is a replay - * of the captured USB commands from the Windows proprietary driver. - */ -static int friio_initialize(struct dvb_usb_device *d) -{ - int ret; - int i; - int retry = 0; - u8 *rbuf, *wbuf; - - deb_info("%s called.\n", __func__); - - wbuf = kmalloc(3, GFP_KERNEL); - if (!wbuf) - return -ENOMEM; - - rbuf = kmalloc(2, GFP_KERNEL); - if (!rbuf) { - kfree(wbuf); - return -ENOMEM; - } - - /* use gl861_i2c_msg instead of gl861_i2c_xfer(), */ - /* because the i2c device is not set up yet. */ - wbuf[0] = 0x11; - wbuf[1] = 0x02; - ret = gl861_i2c_msg(d, 0x00, wbuf, 2, NULL, 0); - if (ret < 0) - goto error; - msleep(2); - - wbuf[0] = 0x11; - wbuf[1] = 0x00; - ret = gl861_i2c_msg(d, 0x00, wbuf, 2, NULL, 0); - if (ret < 0) - goto error; - msleep(1); - - /* following msgs should be in the FE's init code? */ - /* cmd sequence to identify the device type? (friio black/white) */ - wbuf[0] = 0x03; - wbuf[1] = 0x80; - /* can't use gl861_i2c_cmd, as the register-addr is 16bit(0x0100) */ - ret = usb_control_msg(d->udev, usb_sndctrlpipe(d->udev, 0), - GL861_REQ_I2C_DATA_CTRL_WRITE, GL861_WRITE, - 0x1200, 0x0100, wbuf, 2, 2000); - if (ret < 0) - goto error; - - msleep(2); - wbuf[0] = 0x00; - wbuf[2] = 0x01; /* reg.0x0100 */ - wbuf[1] = 0x00; - ret = gl861_i2c_msg(d, 0x12 >> 1, wbuf, 3, rbuf, 2); - /* my Friio White returns 0xffff. */ - if (ret < 0 || rbuf[0] != 0xff || rbuf[1] != 0xff) - goto error; - - msleep(2); - wbuf[0] = 0x03; - wbuf[1] = 0x80; - ret = usb_control_msg(d->udev, usb_sndctrlpipe(d->udev, 0), - GL861_REQ_I2C_DATA_CTRL_WRITE, GL861_WRITE, - 0x9000, 0x0100, wbuf, 2, 2000); - if (ret < 0) - goto error; - - msleep(2); - wbuf[0] = 0x00; - wbuf[2] = 0x01; /* reg.0x0100 */ - wbuf[1] = 0x00; - ret = gl861_i2c_msg(d, 0x90 >> 1, wbuf, 3, rbuf, 2); - /* my Friio White returns 0xffff again. */ - if (ret < 0 || rbuf[0] != 0xff || rbuf[1] != 0xff) - goto error; - - msleep(1); - -restart: - /* ============ start DEMOD init cmds ================== */ - /* read PLL status to clear the POR bit */ - wbuf[0] = JDVBT90502_2ND_I2C_REG; - wbuf[1] = (FRIIO_PLL_ADDR << 1) + 1; /* +1 for reading */ - ret = gl861_i2c_msg(d, FRIIO_DEMOD_ADDR, wbuf, 2, NULL, 0); - if (ret < 0) - goto error; - - msleep(5); - /* note: DEMODULATOR has 16bit register-address. */ - wbuf[0] = 0x00; - wbuf[2] = 0x01; /* reg addr: 0x0100 */ - wbuf[1] = 0x00; /* val: not used */ - ret = gl861_i2c_msg(d, FRIIO_DEMOD_ADDR, wbuf, 3, rbuf, 1); - if (ret < 0) - goto error; -/* - msleep(1); - wbuf[0] = 0x80; - wbuf[1] = 0x00; - ret = gl861_i2c_msg(d, FRIIO_DEMOD_ADDR, wbuf, 2, rbuf, 1); - if (ret < 0) - goto error; - */ - if (rbuf[0] & 0x80) { /* still in PowerOnReset state? */ - if (++retry > 3) { - deb_info("failed to get the correct FE demod status:0x%02x\n", - rbuf[0]); - goto error; - } - msleep(100); - goto restart; - } - - /* TODO: check return value in rbuf */ - /* =========== end DEMOD init cmds ===================== */ - msleep(1); - - wbuf[0] = 0x30; - wbuf[1] = 0x04; - ret = gl861_i2c_msg(d, 0x00, wbuf, 2, NULL, 0); - if (ret < 0) - goto error; - - msleep(2); - /* following 2 cmds unnecessary? */ - wbuf[0] = 0x00; - wbuf[1] = 0x01; - ret = gl861_i2c_msg(d, 0x00, wbuf, 2, NULL, 0); - if (ret < 0) - goto error; - - wbuf[0] = 0x06; - wbuf[1] = 0x0F; - ret = gl861_i2c_msg(d, 0x00, wbuf, 2, NULL, 0); - if (ret < 0) - goto error; - - /* some streaming ctl cmds (maybe) */ - msleep(10); - for (i = 0; i < cmdlen; i++) { - ret = gl861_i2c_msg(d, 0x00, streaming_init_cmds[i], 2, - NULL, 0); - if (ret < 0) - goto error; - msleep(1); - } - msleep(20); - - /* change the LED color etc. */ - ret = friio_streaming_ctrl(&d->adapter[0], 0); - if (ret < 0) - goto error; - - return 0; - -error: - kfree(wbuf); - kfree(rbuf); - deb_info("%s:ret == %d\n", __func__, ret); - return -EIO; -} - -/* Callbacks for DVB USB */ - -static int friio_streaming_ctrl(struct dvb_usb_adapter *adap, int onoff) -{ - int ret; - - deb_info("%s called.(%d)\n", __func__, onoff); - - /* set the LED color and saturation (and LNB on) */ - if (onoff) - ret = friio_ext_ctl(adap, 0x6400ff64, 1); - else - ret = friio_ext_ctl(adap, 0x96ff00ff, 1); - - if (ret != 1) { - deb_info("%s failed to send cmdx. ret==%d\n", __func__, ret); - return -EREMOTEIO; - } - return 0; -} - -static int friio_frontend_attach(struct dvb_usb_adapter *adap) -{ - if (friio_initialize(adap->dev) < 0) - return -EIO; - - adap->fe_adap[0].fe = jdvbt90502_attach(adap->dev); - if (adap->fe_adap[0].fe == NULL) - return -EIO; - - return 0; -} - -/* DVB USB Driver stuff */ -static struct dvb_usb_device_properties friio_properties; - -static int friio_probe(struct usb_interface *intf, - const struct usb_device_id *id) -{ - struct dvb_usb_device *d; - struct usb_host_interface *alt; - int ret; - - if (intf->num_altsetting < GL861_ALTSETTING_COUNT) - return -ENODEV; - - alt = usb_altnum_to_altsetting(intf, FRIIO_BULK_ALTSETTING); - if (alt == NULL) { - deb_rc("not alt found!\n"); - return -ENODEV; - } - ret = usb_set_interface(interface_to_usbdev(intf), - alt->desc.bInterfaceNumber, - alt->desc.bAlternateSetting); - if (ret != 0) { - deb_rc("failed to set alt-setting!\n"); - return ret; - } - - ret = dvb_usb_device_init(intf, &friio_properties, - THIS_MODULE, &d, adapter_nr); - if (ret == 0) - friio_streaming_ctrl(&d->adapter[0], 1); - - return ret; -} - - -struct jdvbt90502_config friio_fe_config = { - .demod_address = FRIIO_DEMOD_ADDR, - .pll_address = FRIIO_PLL_ADDR, -}; - -static struct i2c_algorithm gl861_i2c_algo = { - .master_xfer = gl861_i2c_xfer, - .functionality = gl861_i2c_func, -}; - -static struct usb_device_id friio_table[] = { - { USB_DEVICE(USB_VID_774, USB_PID_FRIIO_WHITE) }, - { } /* Terminating entry */ -}; -MODULE_DEVICE_TABLE(usb, friio_table); - - -static struct dvb_usb_device_properties friio_properties = { - .caps = DVB_USB_IS_AN_I2C_ADAPTER, - .usb_ctrl = DEVICE_SPECIFIC, - - .size_of_priv = 0, - - .num_adapters = 1, - .adapter = { - /* caps:0 => no pid filter, 188B TS packet */ - /* GL861 has a HW pid filter, but no info available. */ - { - .num_frontends = 1, - .fe = {{ - .caps = 0, - - .frontend_attach = friio_frontend_attach, - .streaming_ctrl = friio_streaming_ctrl, - - .stream = { - .type = USB_BULK, - /* count <= MAX_NO_URBS_FOR_DATA_STREAM(10) */ - .count = 8, - .endpoint = 0x01, - .u = { - /* GL861 has 6KB buf inside */ - .bulk = { - .buffersize = 16384, - } - } - }, - }}, - } - }, - .i2c_algo = &gl861_i2c_algo, - - .num_device_descs = 1, - .devices = { - { - .name = "774 Friio ISDB-T USB2.0", - .cold_ids = { NULL }, - .warm_ids = { &friio_table[0], NULL }, - }, - } -}; - -static struct usb_driver friio_driver = { - .name = "dvb_usb_friio", - .probe = friio_probe, - .disconnect = dvb_usb_device_exit, - .id_table = friio_table, -}; - -module_usb_driver(friio_driver); - -MODULE_AUTHOR("Akihiro Tsukada <tskd2@yahoo.co.jp>"); -MODULE_DESCRIPTION("Driver for Friio ISDB-T USB2.0 Receiver"); -MODULE_VERSION("0.2"); -MODULE_LICENSE("GPL"); diff --git a/drivers/media/usb/dvb-usb/friio.h b/drivers/media/usb/dvb-usb/friio.h deleted file mode 100644 index a53af56d035c..000000000000 --- a/drivers/media/usb/dvb-usb/friio.h +++ /dev/null @@ -1,99 +0,0 @@ -/* DVB USB compliant Linux driver for the Friio USB2.0 ISDB-T receiver. - * - * Copyright (C) 2009 Akihiro Tsukada <tskd2@yahoo.co.jp> - * - * This module is based off the the gl861 and vp702x modules. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the Free - * Software Foundation, version 2. - * - * see Documentation/media/dvb-drivers/dvb-usb.rst for more information - */ -#ifndef _DVB_USB_FRIIO_H_ -#define _DVB_USB_FRIIO_H_ - -/** - * Friio Components - * USB hub: AU4254 - * USB controller(+ TS dmx & streaming): GL861 - * Frontend: comtech JDVBT-90502 - * (tuner PLL: tua6034, I2C addr:(0xC0 >> 1)) - * (OFDM demodulator: TC90502, I2C addr:(0x30 >> 1)) - * LED x3 (+LNB) control: PIC 16F676 - * EEPROM: 24C08 - * - * (USB smart card reader: AU9522) - * - */ - -#define DVB_USB_LOG_PREFIX "friio" -#include "dvb-usb.h" - -extern int dvb_usb_friio_debug; -#define deb_info(args...) dprintk(dvb_usb_friio_debug, 0x01, args) -#define deb_xfer(args...) dprintk(dvb_usb_friio_debug, 0x02, args) -#define deb_rc(args...) dprintk(dvb_usb_friio_debug, 0x04, args) -#define deb_fe(args...) dprintk(dvb_usb_friio_debug, 0x08, args) - -/* Vendor requests */ -#define GL861_WRITE 0x40 -#define GL861_READ 0xc0 - -/* command bytes */ -#define GL861_REQ_I2C_WRITE 0x01 -#define GL861_REQ_I2C_READ 0x02 -/* For control msg with data argument */ -/* Used for accessing the PLL on the secondary I2C bus of FE via GL861 */ -#define GL861_REQ_I2C_DATA_CTRL_WRITE 0x03 - -#define GL861_ALTSETTING_COUNT 2 -#define FRIIO_BULK_ALTSETTING 0 -#define FRIIO_ISOC_ALTSETTING 1 - -/* LED & LNB control via PIC. */ -/* basically, it's serial control with clock and strobe. */ -/* write the below 4bit control data to the reg 0x00 at the I2C addr 0x00 */ -/* when controlling the LEDs, 32bit(saturation, R, G, B) is sent on the bit3*/ -#define FRIIO_CTL_LNB (1 << 0) -#define FRIIO_CTL_STROBE (1 << 1) -#define FRIIO_CTL_CLK (1 << 2) -#define FRIIO_CTL_LED (1 << 3) - -/* Front End related */ - -#define FRIIO_DEMOD_ADDR (0x30 >> 1) -#define FRIIO_PLL_ADDR (0xC0 >> 1) - -#define JDVBT90502_PLL_CLK 4000000 -#define JDVBT90502_PLL_DIVIDER 28 - -#define JDVBT90502_2ND_I2C_REG 0xFE - -/* byte index for pll i2c command data structure*/ -/* see datasheet for tua6034 */ -#define DEMOD_REDIRECT_REG 0 -#define ADDRESS_BYTE 1 -#define DIVIDER_BYTE1 2 -#define DIVIDER_BYTE2 3 -#define CONTROL_BYTE 4 -#define BANDSWITCH_BYTE 5 -#define AGC_CTRL_BYTE 5 -#define PLL_CMD_LEN 6 - -/* bit masks for PLL STATUS response */ -#define PLL_STATUS_POR_MODE 0x80 /* 1: Power on Reset (test) Mode */ -#define PLL_STATUS_LOCKED 0x40 /* 1: locked */ -#define PLL_STATUS_AGC_ACTIVE 0x08 /* 1:active */ -#define PLL_STATUS_TESTMODE 0x07 /* digital output level (5 level) */ - /* 0.15Vcc step 0x00: < 0.15Vcc, ..., 0x04: >= 0.6Vcc (<= 1Vcc) */ - - -struct jdvbt90502_config { - u8 demod_address; /* i2c addr for demodulator IC */ - u8 pll_address; /* PLL addr on the secondary i2c*/ -}; -extern struct jdvbt90502_config friio_fe_config; - -extern struct dvb_frontend *jdvbt90502_attach(struct dvb_usb_device *d); -#endif diff --git a/drivers/media/usb/em28xx/em28xx-cards.c b/drivers/media/usb/em28xx/em28xx-cards.c index 87b887b7604e..1283c7ca9ad5 100644 --- a/drivers/media/usb/em28xx/em28xx-cards.c +++ b/drivers/media/usb/em28xx/em28xx-cards.c @@ -1958,7 +1958,7 @@ const struct em28xx_board em28xx_boards[] = { } }, }, [EM2882_BOARD_TERRATEC_HYBRID_XS] = { - .name = "Terratec Cinnergy Hybrid T USB XS (em2882)", + .name = "Terratec Cinergy Hybrid T USB XS (em2882)", .tuner_type = TUNER_XC2028, .tuner_gpio = default_tuner_gpio, .mts_firmware = 1, diff --git a/drivers/media/usb/pulse8-cec/pulse8-cec.c b/drivers/media/usb/pulse8-cec/pulse8-cec.c index 365c78b748dd..b085b14f3f87 100644 --- a/drivers/media/usb/pulse8-cec/pulse8-cec.c +++ b/drivers/media/usb/pulse8-cec/pulse8-cec.c @@ -586,7 +586,7 @@ unlock: else pulse8->config_pending = true; mutex_unlock(&pulse8->config_lock); - return err; + return log_addr == CEC_LOG_ADDR_INVALID ? 0 : err; } static int pulse8_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, diff --git a/drivers/media/usb/pvrusb2/pvrusb2-hdw.c b/drivers/media/usb/pvrusb2/pvrusb2-hdw.c index 7702285c1519..446a999dd2ce 100644 --- a/drivers/media/usb/pvrusb2/pvrusb2-hdw.c +++ b/drivers/media/usb/pvrusb2/pvrusb2-hdw.c @@ -1698,7 +1698,7 @@ static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw) if (!hdw->flag_tripped) return 0; hdw->flag_tripped = 0; pvr2_trace(PVR2_TRACE_ERROR_LEGS, - "Clearing driver error statuss"); + "Clearing driver error status"); return !0; } diff --git a/drivers/media/usb/pvrusb2/pvrusb2-v4l2.c b/drivers/media/usb/pvrusb2/pvrusb2-v4l2.c index 97a93ed4bcda..08d5b7aa3537 100644 --- a/drivers/media/usb/pvrusb2/pvrusb2-v4l2.c +++ b/drivers/media/usb/pvrusb2/pvrusb2-v4l2.c @@ -703,16 +703,19 @@ static int pvr2_try_ext_ctrls(struct file *file, void *priv, return 0; } -static int pvr2_cropcap(struct file *file, void *priv, struct v4l2_cropcap *cap) +static int pvr2_g_pixelaspect(struct file *file, void *priv, + int type, struct v4l2_fract *f) { struct pvr2_v4l2_fh *fh = file->private_data; struct pvr2_hdw *hdw = fh->channel.mc_head->hdw; + struct v4l2_cropcap cap = { .type = type }; int ret; - if (cap->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + if (type != V4L2_BUF_TYPE_VIDEO_CAPTURE) return -EINVAL; - ret = pvr2_hdw_get_cropcap(hdw, cap); - cap->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; /* paranoia */ + ret = pvr2_hdw_get_cropcap(hdw, &cap); + if (!ret) + *f = cap.pixelaspect; return ret; } @@ -815,7 +818,7 @@ static const struct v4l2_ioctl_ops pvr2_ioctl_ops = { .vidioc_g_audio = pvr2_g_audio, .vidioc_enumaudio = pvr2_enumaudio, .vidioc_enum_input = pvr2_enum_input, - .vidioc_cropcap = pvr2_cropcap, + .vidioc_g_pixelaspect = pvr2_g_pixelaspect, .vidioc_s_selection = pvr2_s_selection, .vidioc_g_selection = pvr2_g_selection, .vidioc_g_input = pvr2_g_input, diff --git a/drivers/media/usb/siano/smsusb.c b/drivers/media/usb/siano/smsusb.c index be3634407f1f..2ffded08407b 100644 --- a/drivers/media/usb/siano/smsusb.c +++ b/drivers/media/usb/siano/smsusb.c @@ -225,10 +225,9 @@ static int smsusb_sendrequest(void *context, void *buffer, size_t size) return -ENOENT; } - phdr = kmalloc(size, GFP_KERNEL); + phdr = kmemdup(buffer, size, GFP_KERNEL); if (!phdr) return -ENOMEM; - memcpy(phdr, buffer, size); pr_debug("sending %s(%d) size: %d\n", smscore_translate_msg(phdr->msg_type), phdr->msg_type, diff --git a/drivers/media/usb/stkwebcam/stk-webcam.c b/drivers/media/usb/stkwebcam/stk-webcam.c index e11d5d5b7c26..b8ec74d98e8d 100644 --- a/drivers/media/usb/stkwebcam/stk-webcam.c +++ b/drivers/media/usb/stkwebcam/stk-webcam.c @@ -116,6 +116,13 @@ static const struct dmi_system_id stk_upside_down_dmi_table[] = { DMI_MATCH(DMI_PRODUCT_NAME, "T12Rg-H") } }, + { + .ident = "ASUS A6VM", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."), + DMI_MATCH(DMI_PRODUCT_NAME, "A6VM") + } + }, {} }; @@ -164,7 +171,11 @@ int stk_camera_read_reg(struct stk_camera *dev, u16 index, u8 *value) *value = *buf; kfree(buf); - return ret; + + if (ret < 0) + return ret; + else + return 0; } static int stk_start_stream(struct stk_camera *dev) diff --git a/drivers/media/usb/uvc/uvc_driver.c b/drivers/media/usb/uvc/uvc_driver.c index bc369a0934a3..b62cbd800111 100644 --- a/drivers/media/usb/uvc/uvc_driver.c +++ b/drivers/media/usb/uvc/uvc_driver.c @@ -214,6 +214,11 @@ static struct uvc_format_desc uvc_fmts[] = { .guid = UVC_GUID_FORMAT_INZI, .fcc = V4L2_PIX_FMT_INZI, }, + { + .name = "4-bit Depth Confidence (Packed)", + .guid = UVC_GUID_FORMAT_CNF4, + .fcc = V4L2_PIX_FMT_CNF4, + }, }; /* ------------------------------------------------------------------------ @@ -391,6 +396,50 @@ static struct uvc_streaming *uvc_stream_by_id(struct uvc_device *dev, int id) } /* ------------------------------------------------------------------------ + * Streaming Object Management + */ + +static void uvc_stream_delete(struct uvc_streaming *stream) +{ + if (stream->async_wq) + destroy_workqueue(stream->async_wq); + + mutex_destroy(&stream->mutex); + + usb_put_intf(stream->intf); + + kfree(stream->format); + kfree(stream->header.bmaControls); + kfree(stream); +} + +static struct uvc_streaming *uvc_stream_new(struct uvc_device *dev, + struct usb_interface *intf) +{ + struct uvc_streaming *stream; + + stream = kzalloc(sizeof(*stream), GFP_KERNEL); + if (stream == NULL) + return NULL; + + mutex_init(&stream->mutex); + + stream->dev = dev; + stream->intf = usb_get_intf(intf); + stream->intfnum = intf->cur_altsetting->desc.bInterfaceNumber; + + /* Allocate a stream specific work queue for asynchronous tasks. */ + stream->async_wq = alloc_workqueue("uvcvideo", WQ_UNBOUND | WQ_HIGHPRI, + 0); + if (!stream->async_wq) { + uvc_stream_delete(stream); + return NULL; + } + + return stream; +} + +/* ------------------------------------------------------------------------ * Descriptors parsing */ @@ -682,17 +731,12 @@ static int uvc_parse_streaming(struct uvc_device *dev, return -EINVAL; } - streaming = kzalloc(sizeof(*streaming), GFP_KERNEL); + streaming = uvc_stream_new(dev, intf); if (streaming == NULL) { usb_driver_release_interface(&uvc_driver.driver, intf); - return -EINVAL; + return -ENOMEM; } - mutex_init(&streaming->mutex); - streaming->dev = dev; - streaming->intf = usb_get_intf(intf); - streaming->intfnum = intf->cur_altsetting->desc.bInterfaceNumber; - /* The Pico iMage webcam has its class-specific interface descriptors * after the endpoint descriptors. */ @@ -899,10 +943,7 @@ static int uvc_parse_streaming(struct uvc_device *dev, error: usb_driver_release_interface(&uvc_driver.driver, intf); - usb_put_intf(intf); - kfree(streaming->format); - kfree(streaming->header.bmaControls); - kfree(streaming); + uvc_stream_delete(streaming); return ret; } @@ -1810,7 +1851,7 @@ static int uvc_scan_device(struct uvc_device *dev) * is released. * * As this function is called after or during disconnect(), all URBs have - * already been canceled by the USB core. There is no need to kill the + * already been cancelled by the USB core. There is no need to kill the * interrupt URB manually. */ static void uvc_delete(struct kref *kref) @@ -1824,11 +1865,7 @@ static void uvc_delete(struct kref *kref) usb_put_intf(dev->intf); usb_put_dev(dev->udev); - if (dev->vdev.dev) - v4l2_device_unregister(&dev->vdev); #ifdef CONFIG_MEDIA_CONTROLLER - if (media_devnode_is_registered(dev->mdev.devnode)) - media_device_unregister(&dev->mdev); media_device_cleanup(&dev->mdev); #endif @@ -1852,10 +1889,7 @@ static void uvc_delete(struct kref *kref) streaming = list_entry(p, struct uvc_streaming, list); usb_driver_release_interface(&uvc_driver.driver, streaming->intf); - usb_put_intf(streaming->intf); - kfree(streaming->format); - kfree(streaming->header.bmaControls); - kfree(streaming); + uvc_stream_delete(streaming); } kfree(dev); @@ -1885,6 +1919,15 @@ static void uvc_unregister_video(struct uvc_device *dev) uvc_debugfs_cleanup_stream(stream); } + + uvc_status_unregister(dev); + + if (dev->vdev.dev) + v4l2_device_unregister(&dev->vdev); +#ifdef CONFIG_MEDIA_CONTROLLER + if (media_devnode_is_registered(dev->mdev.devnode)) + media_device_unregister(&dev->mdev); +#endif } int uvc_register_video_device(struct uvc_device *dev, diff --git a/drivers/media/usb/uvc/uvc_isight.c b/drivers/media/usb/uvc/uvc_isight.c index 81e6f2187bfb..39a4e4482b23 100644 --- a/drivers/media/usb/uvc/uvc_isight.c +++ b/drivers/media/usb/uvc/uvc_isight.c @@ -99,9 +99,11 @@ static int isight_decode(struct uvc_video_queue *queue, struct uvc_buffer *buf, return 0; } -void uvc_video_decode_isight(struct urb *urb, struct uvc_streaming *stream, - struct uvc_buffer *buf, struct uvc_buffer *meta_buf) +void uvc_video_decode_isight(struct uvc_urb *uvc_urb, struct uvc_buffer *buf, + struct uvc_buffer *meta_buf) { + struct urb *urb = uvc_urb->urb; + struct uvc_streaming *stream = uvc_urb->stream; int ret, i; for (i = 0; i < urb->number_of_packets; ++i) { diff --git a/drivers/media/usb/uvc/uvc_queue.c b/drivers/media/usb/uvc/uvc_queue.c index 8964e16f2b22..682698ec1118 100644 --- a/drivers/media/usb/uvc/uvc_queue.c +++ b/drivers/media/usb/uvc/uvc_queue.c @@ -142,6 +142,7 @@ static void uvc_buffer_queue(struct vb2_buffer *vb) spin_lock_irqsave(&queue->irqlock, flags); if (likely(!(queue->flags & UVC_QUEUE_DISCONNECTED))) { + kref_init(&buf->ref); list_add_tail(&buf->queue, &queue->irqqueue); } else { /* If the device is disconnected return the buffer to userspace @@ -169,18 +170,19 @@ static int uvc_start_streaming(struct vb2_queue *vq, unsigned int count) { struct uvc_video_queue *queue = vb2_get_drv_priv(vq); struct uvc_streaming *stream = uvc_queue_to_stream(queue); - unsigned long flags; int ret; + lockdep_assert_irqs_enabled(); + queue->buf_used = 0; - ret = uvc_video_enable(stream, 1); + ret = uvc_video_start_streaming(stream); if (ret == 0) return 0; - spin_lock_irqsave(&queue->irqlock, flags); + spin_lock_irq(&queue->irqlock); uvc_queue_return_buffers(queue, UVC_BUF_STATE_QUEUED); - spin_unlock_irqrestore(&queue->irqlock, flags); + spin_unlock_irq(&queue->irqlock); return ret; } @@ -188,14 +190,15 @@ static int uvc_start_streaming(struct vb2_queue *vq, unsigned int count) static void uvc_stop_streaming(struct vb2_queue *vq) { struct uvc_video_queue *queue = vb2_get_drv_priv(vq); - unsigned long flags; + + lockdep_assert_irqs_enabled(); if (vq->type != V4L2_BUF_TYPE_META_CAPTURE) - uvc_video_enable(uvc_queue_to_stream(queue), 0); + uvc_video_stop_streaming(uvc_queue_to_stream(queue)); - spin_lock_irqsave(&queue->irqlock, flags); + spin_lock_irq(&queue->irqlock); uvc_queue_return_buffers(queue, UVC_BUF_STATE_ERROR); - spin_unlock_irqrestore(&queue->irqlock, flags); + spin_unlock_irq(&queue->irqlock); } static const struct vb2_ops uvc_queue_qops = { @@ -430,32 +433,93 @@ void uvc_queue_cancel(struct uvc_video_queue *queue, int disconnect) spin_unlock_irqrestore(&queue->irqlock, flags); } -struct uvc_buffer *uvc_queue_next_buffer(struct uvc_video_queue *queue, - struct uvc_buffer *buf) +/* + * uvc_queue_get_current_buffer: Obtain the current working output buffer + * + * Buffers may span multiple packets, and even URBs, therefore the active buffer + * remains on the queue until the EOF marker. + */ +static struct uvc_buffer * +__uvc_queue_get_current_buffer(struct uvc_video_queue *queue) +{ + if (list_empty(&queue->irqqueue)) + return NULL; + + return list_first_entry(&queue->irqqueue, struct uvc_buffer, queue); +} + +struct uvc_buffer *uvc_queue_get_current_buffer(struct uvc_video_queue *queue) { struct uvc_buffer *nextbuf; unsigned long flags; + spin_lock_irqsave(&queue->irqlock, flags); + nextbuf = __uvc_queue_get_current_buffer(queue); + spin_unlock_irqrestore(&queue->irqlock, flags); + + return nextbuf; +} + +/* + * uvc_queue_buffer_requeue: Requeue a buffer on our internal irqqueue + * + * Reuse a buffer through our internal queue without the need to 'prepare'. + * The buffer will be returned to userspace through the uvc_buffer_queue call if + * the device has been disconnected. + */ +static void uvc_queue_buffer_requeue(struct uvc_video_queue *queue, + struct uvc_buffer *buf) +{ + buf->error = 0; + buf->state = UVC_BUF_STATE_QUEUED; + buf->bytesused = 0; + vb2_set_plane_payload(&buf->buf.vb2_buf, 0, 0); + + uvc_buffer_queue(&buf->buf.vb2_buf); +} + +static void uvc_queue_buffer_complete(struct kref *ref) +{ + struct uvc_buffer *buf = container_of(ref, struct uvc_buffer, ref); + struct vb2_buffer *vb = &buf->buf.vb2_buf; + struct uvc_video_queue *queue = vb2_get_drv_priv(vb->vb2_queue); + if ((queue->flags & UVC_QUEUE_DROP_CORRUPTED) && buf->error) { - buf->error = 0; - buf->state = UVC_BUF_STATE_QUEUED; - buf->bytesused = 0; - vb2_set_plane_payload(&buf->buf.vb2_buf, 0, 0); - return buf; + uvc_queue_buffer_requeue(queue, buf); + return; } + buf->state = buf->error ? UVC_BUF_STATE_ERROR : UVC_BUF_STATE_DONE; + vb2_set_plane_payload(&buf->buf.vb2_buf, 0, buf->bytesused); + vb2_buffer_done(&buf->buf.vb2_buf, VB2_BUF_STATE_DONE); +} + +/* + * Release a reference on the buffer. Complete the buffer when the last + * reference is released. + */ +void uvc_queue_buffer_release(struct uvc_buffer *buf) +{ + kref_put(&buf->ref, uvc_queue_buffer_complete); +} + +/* + * Remove this buffer from the queue. Lifetime will persist while async actions + * are still running (if any), and uvc_queue_buffer_release will give the buffer + * back to VB2 when all users have completed. + */ +struct uvc_buffer *uvc_queue_next_buffer(struct uvc_video_queue *queue, + struct uvc_buffer *buf) +{ + struct uvc_buffer *nextbuf; + unsigned long flags; + spin_lock_irqsave(&queue->irqlock, flags); list_del(&buf->queue); - if (!list_empty(&queue->irqqueue)) - nextbuf = list_first_entry(&queue->irqqueue, struct uvc_buffer, - queue); - else - nextbuf = NULL; + nextbuf = __uvc_queue_get_current_buffer(queue); spin_unlock_irqrestore(&queue->irqlock, flags); - buf->state = buf->error ? UVC_BUF_STATE_ERROR : UVC_BUF_STATE_DONE; - vb2_set_plane_payload(&buf->buf.vb2_buf, 0, buf->bytesused); - vb2_buffer_done(&buf->buf.vb2_buf, VB2_BUF_STATE_DONE); + uvc_queue_buffer_release(buf); return nextbuf; } diff --git a/drivers/media/usb/uvc/uvc_status.c b/drivers/media/usb/uvc/uvc_status.c index 0722dc684378..883e4cab45e7 100644 --- a/drivers/media/usb/uvc/uvc_status.c +++ b/drivers/media/usb/uvc/uvc_status.c @@ -54,7 +54,7 @@ error: return ret; } -static void uvc_input_cleanup(struct uvc_device *dev) +static void uvc_input_unregister(struct uvc_device *dev) { if (dev->input) input_unregister_device(dev->input); @@ -71,7 +71,7 @@ static void uvc_input_report_key(struct uvc_device *dev, unsigned int code, #else #define uvc_input_init(dev) -#define uvc_input_cleanup(dev) +#define uvc_input_unregister(dev) #define uvc_input_report_key(dev, code, value) #endif /* CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV */ @@ -292,12 +292,16 @@ int uvc_status_init(struct uvc_device *dev) return 0; } -void uvc_status_cleanup(struct uvc_device *dev) +void uvc_status_unregister(struct uvc_device *dev) { usb_kill_urb(dev->int_urb); + uvc_input_unregister(dev); +} + +void uvc_status_cleanup(struct uvc_device *dev) +{ usb_free_urb(dev->int_urb); kfree(dev->status); - uvc_input_cleanup(dev); } int uvc_status_start(struct uvc_device *dev, gfp_t flags) diff --git a/drivers/media/usb/uvc/uvc_video.c b/drivers/media/usb/uvc/uvc_video.c index 86a99f461fd8..84525ff04745 100644 --- a/drivers/media/usb/uvc/uvc_video.c +++ b/drivers/media/usb/uvc/uvc_video.c @@ -1094,21 +1094,54 @@ static int uvc_video_decode_start(struct uvc_streaming *stream, return data[0]; } -static void uvc_video_decode_data(struct uvc_streaming *stream, +/* + * uvc_video_decode_data_work: Asynchronous memcpy processing + * + * Copy URB data to video buffers in process context, releasing buffer + * references and requeuing the URB when done. + */ +static void uvc_video_copy_data_work(struct work_struct *work) +{ + struct uvc_urb *uvc_urb = container_of(work, struct uvc_urb, work); + unsigned int i; + int ret; + + for (i = 0; i < uvc_urb->async_operations; i++) { + struct uvc_copy_op *op = &uvc_urb->copy_operations[i]; + + memcpy(op->dst, op->src, op->len); + + /* Release reference taken on this buffer. */ + uvc_queue_buffer_release(op->buf); + } + + ret = usb_submit_urb(uvc_urb->urb, GFP_KERNEL); + if (ret < 0) + uvc_printk(KERN_ERR, "Failed to resubmit video URB (%d).\n", + ret); +} + +static void uvc_video_decode_data(struct uvc_urb *uvc_urb, struct uvc_buffer *buf, const u8 *data, int len) { - unsigned int maxlen, nbytes; - void *mem; + unsigned int active_op = uvc_urb->async_operations; + struct uvc_copy_op *op = &uvc_urb->copy_operations[active_op]; + unsigned int maxlen; if (len <= 0) return; - /* Copy the video data to the buffer. */ maxlen = buf->length - buf->bytesused; - mem = buf->mem + buf->bytesused; - nbytes = min((unsigned int)len, maxlen); - memcpy(mem, data, nbytes); - buf->bytesused += nbytes; + + /* Take a buffer reference for async work. */ + kref_get(&buf->ref); + + op->buf = buf; + op->src = data; + op->dst = buf->mem + buf->bytesused; + op->len = min_t(unsigned int, len, maxlen); + + buf->bytesused += op->len; /* Complete the current frame if the buffer size was exceeded. */ if (len > maxlen) { @@ -1116,6 +1149,8 @@ static void uvc_video_decode_data(struct uvc_streaming *stream, buf->error = 1; buf->state = UVC_BUF_STATE_READY; } + + uvc_urb->async_operations++; } static void uvc_video_decode_end(struct uvc_streaming *stream, @@ -1291,9 +1326,11 @@ static void uvc_video_next_buffers(struct uvc_streaming *stream, *video_buf = uvc_queue_next_buffer(&stream->queue, *video_buf); } -static void uvc_video_decode_isoc(struct urb *urb, struct uvc_streaming *stream, +static void uvc_video_decode_isoc(struct uvc_urb *uvc_urb, struct uvc_buffer *buf, struct uvc_buffer *meta_buf) { + struct urb *urb = uvc_urb->urb; + struct uvc_streaming *stream = uvc_urb->stream; u8 *mem; int ret, i; @@ -1322,7 +1359,7 @@ static void uvc_video_decode_isoc(struct urb *urb, struct uvc_streaming *stream, uvc_video_decode_meta(stream, meta_buf, mem, ret); /* Decode the payload data. */ - uvc_video_decode_data(stream, buf, mem + ret, + uvc_video_decode_data(uvc_urb, buf, mem + ret, urb->iso_frame_desc[i].actual_length - ret); /* Process the header again. */ @@ -1334,9 +1371,11 @@ static void uvc_video_decode_isoc(struct urb *urb, struct uvc_streaming *stream, } } -static void uvc_video_decode_bulk(struct urb *urb, struct uvc_streaming *stream, +static void uvc_video_decode_bulk(struct uvc_urb *uvc_urb, struct uvc_buffer *buf, struct uvc_buffer *meta_buf) { + struct urb *urb = uvc_urb->urb; + struct uvc_streaming *stream = uvc_urb->stream; u8 *mem; int len, ret; @@ -1380,9 +1419,9 @@ static void uvc_video_decode_bulk(struct urb *urb, struct uvc_streaming *stream, * sure buf is never dereferenced if NULL. */ - /* Process video data. */ + /* Prepare video data for processing. */ if (!stream->bulk.skip_payload && buf != NULL) - uvc_video_decode_data(stream, buf, mem, len); + uvc_video_decode_data(uvc_urb, buf, mem, len); /* Detect the payload end by a URB smaller than the maximum size (or * a payload size equal to the maximum) and process the header again. @@ -1402,9 +1441,12 @@ static void uvc_video_decode_bulk(struct urb *urb, struct uvc_streaming *stream, } } -static void uvc_video_encode_bulk(struct urb *urb, struct uvc_streaming *stream, +static void uvc_video_encode_bulk(struct uvc_urb *uvc_urb, struct uvc_buffer *buf, struct uvc_buffer *meta_buf) { + struct urb *urb = uvc_urb->urb; + struct uvc_streaming *stream = uvc_urb->stream; + u8 *mem = urb->transfer_buffer; int len = stream->urb_size, ret; @@ -1447,7 +1489,8 @@ static void uvc_video_encode_bulk(struct urb *urb, struct uvc_streaming *stream, static void uvc_video_complete(struct urb *urb) { - struct uvc_streaming *stream = urb->context; + struct uvc_urb *uvc_urb = urb->context; + struct uvc_streaming *stream = uvc_urb->stream; struct uvc_video_queue *queue = &stream->queue; struct uvc_video_queue *qmeta = &stream->meta.queue; struct vb2_queue *vb2_qmeta = stream->meta.vdev.queue; @@ -1464,7 +1507,7 @@ static void uvc_video_complete(struct urb *urb) uvc_printk(KERN_WARNING, "Non-zero status (%d) in video " "completion handler.\n", urb->status); /* fall through */ - case -ENOENT: /* usb_kill_urb() called. */ + case -ENOENT: /* usb_poison_urb() called. */ if (stream->frozen) return; /* fall through */ @@ -1476,11 +1519,7 @@ static void uvc_video_complete(struct urb *urb) return; } - spin_lock_irqsave(&queue->irqlock, flags); - if (!list_empty(&queue->irqqueue)) - buf = list_first_entry(&queue->irqqueue, struct uvc_buffer, - queue); - spin_unlock_irqrestore(&queue->irqlock, flags); + buf = uvc_queue_get_current_buffer(queue); if (vb2_qmeta) { spin_lock_irqsave(&qmeta->irqlock, flags); @@ -1490,12 +1529,26 @@ static void uvc_video_complete(struct urb *urb) spin_unlock_irqrestore(&qmeta->irqlock, flags); } - stream->decode(urb, stream, buf, buf_meta); + /* Re-initialise the URB async work. */ + uvc_urb->async_operations = 0; - if ((ret = usb_submit_urb(urb, GFP_ATOMIC)) < 0) { - uvc_printk(KERN_ERR, "Failed to resubmit video URB (%d).\n", - ret); + /* + * Process the URB headers, and optionally queue expensive memcpy tasks + * to be deferred to a work queue. + */ + stream->decode(uvc_urb, buf, buf_meta); + + /* If no async work is needed, resubmit the URB immediately. */ + if (!uvc_urb->async_operations) { + ret = usb_submit_urb(uvc_urb->urb, GFP_ATOMIC); + if (ret < 0) + uvc_printk(KERN_ERR, + "Failed to resubmit video URB (%d).\n", + ret); + return; } + + queue_work(stream->async_wq, &uvc_urb->work); } /* @@ -1503,18 +1556,19 @@ static void uvc_video_complete(struct urb *urb) */ static void uvc_free_urb_buffers(struct uvc_streaming *stream) { - unsigned int i; + struct uvc_urb *uvc_urb; + + for_each_uvc_urb(uvc_urb, stream) { + if (!uvc_urb->buffer) + continue; - for (i = 0; i < UVC_URBS; ++i) { - if (stream->urb_buffer[i]) { #ifndef CONFIG_DMA_NONCOHERENT - usb_free_coherent(stream->dev->udev, stream->urb_size, - stream->urb_buffer[i], stream->urb_dma[i]); + usb_free_coherent(stream->dev->udev, stream->urb_size, + uvc_urb->buffer, uvc_urb->dma); #else - kfree(stream->urb_buffer[i]); + kfree(uvc_urb->buffer); #endif - stream->urb_buffer[i] = NULL; - } + uvc_urb->buffer = NULL; } stream->urb_size = 0; @@ -1551,19 +1605,23 @@ static int uvc_alloc_urb_buffers(struct uvc_streaming *stream, /* Retry allocations until one succeed. */ for (; npackets > 1; npackets /= 2) { for (i = 0; i < UVC_URBS; ++i) { + struct uvc_urb *uvc_urb = &stream->uvc_urb[i]; + stream->urb_size = psize * npackets; #ifndef CONFIG_DMA_NONCOHERENT - stream->urb_buffer[i] = usb_alloc_coherent( + uvc_urb->buffer = usb_alloc_coherent( stream->dev->udev, stream->urb_size, - gfp_flags | __GFP_NOWARN, &stream->urb_dma[i]); + gfp_flags | __GFP_NOWARN, &uvc_urb->dma); #else - stream->urb_buffer[i] = + uvc_urb->buffer = kmalloc(stream->urb_size, gfp_flags | __GFP_NOWARN); #endif - if (!stream->urb_buffer[i]) { + if (!uvc_urb->buffer) { uvc_free_urb_buffers(stream); break; } + + uvc_urb->stream = stream; } if (i == UVC_URBS) { @@ -1582,21 +1640,26 @@ static int uvc_alloc_urb_buffers(struct uvc_streaming *stream, /* * Uninitialize isochronous/bulk URBs and free transfer buffers. */ -static void uvc_uninit_video(struct uvc_streaming *stream, int free_buffers) +static void uvc_video_stop_transfer(struct uvc_streaming *stream, + int free_buffers) { - struct urb *urb; - unsigned int i; + struct uvc_urb *uvc_urb; uvc_video_stats_stop(stream); - for (i = 0; i < UVC_URBS; ++i) { - urb = stream->urb[i]; - if (urb == NULL) - continue; + /* + * We must poison the URBs rather than kill them to ensure that even + * after the completion handler returns, any asynchronous workqueues + * will be prevented from resubmitting the URBs. + */ + for_each_uvc_urb(uvc_urb, stream) + usb_poison_urb(uvc_urb->urb); - usb_kill_urb(urb); - usb_free_urb(urb); - stream->urb[i] = NULL; + flush_workqueue(stream->async_wq); + + for_each_uvc_urb(uvc_urb, stream) { + usb_free_urb(uvc_urb->urb); + uvc_urb->urb = NULL; } if (free_buffers) @@ -1637,7 +1700,8 @@ static int uvc_init_video_isoc(struct uvc_streaming *stream, struct usb_host_endpoint *ep, gfp_t gfp_flags) { struct urb *urb; - unsigned int npackets, i, j; + struct uvc_urb *uvc_urb; + unsigned int npackets, i; u16 psize; u32 size; @@ -1650,35 +1714,35 @@ static int uvc_init_video_isoc(struct uvc_streaming *stream, size = npackets * psize; - for (i = 0; i < UVC_URBS; ++i) { + for_each_uvc_urb(uvc_urb, stream) { urb = usb_alloc_urb(npackets, gfp_flags); if (urb == NULL) { - uvc_uninit_video(stream, 1); + uvc_video_stop_transfer(stream, 1); return -ENOMEM; } urb->dev = stream->dev->udev; - urb->context = stream; + urb->context = uvc_urb; urb->pipe = usb_rcvisocpipe(stream->dev->udev, ep->desc.bEndpointAddress); #ifndef CONFIG_DMA_NONCOHERENT urb->transfer_flags = URB_ISO_ASAP | URB_NO_TRANSFER_DMA_MAP; - urb->transfer_dma = stream->urb_dma[i]; + urb->transfer_dma = uvc_urb->dma; #else urb->transfer_flags = URB_ISO_ASAP; #endif urb->interval = ep->desc.bInterval; - urb->transfer_buffer = stream->urb_buffer[i]; + urb->transfer_buffer = uvc_urb->buffer; urb->complete = uvc_video_complete; urb->number_of_packets = npackets; urb->transfer_buffer_length = size; - for (j = 0; j < npackets; ++j) { - urb->iso_frame_desc[j].offset = j * psize; - urb->iso_frame_desc[j].length = psize; + for (i = 0; i < npackets; ++i) { + urb->iso_frame_desc[i].offset = i * psize; + urb->iso_frame_desc[i].length = psize; } - stream->urb[i] = urb; + uvc_urb->urb = urb; } return 0; @@ -1692,7 +1756,8 @@ static int uvc_init_video_bulk(struct uvc_streaming *stream, struct usb_host_endpoint *ep, gfp_t gfp_flags) { struct urb *urb; - unsigned int npackets, pipe, i; + struct uvc_urb *uvc_urb; + unsigned int npackets, pipe; u16 psize; u32 size; @@ -1716,22 +1781,21 @@ static int uvc_init_video_bulk(struct uvc_streaming *stream, if (stream->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) size = 0; - for (i = 0; i < UVC_URBS; ++i) { + for_each_uvc_urb(uvc_urb, stream) { urb = usb_alloc_urb(0, gfp_flags); if (urb == NULL) { - uvc_uninit_video(stream, 1); + uvc_video_stop_transfer(stream, 1); return -ENOMEM; } - usb_fill_bulk_urb(urb, stream->dev->udev, pipe, - stream->urb_buffer[i], size, uvc_video_complete, - stream); + usb_fill_bulk_urb(urb, stream->dev->udev, pipe, uvc_urb->buffer, + size, uvc_video_complete, uvc_urb); #ifndef CONFIG_DMA_NONCOHERENT urb->transfer_flags = URB_NO_TRANSFER_DMA_MAP; - urb->transfer_dma = stream->urb_dma[i]; + urb->transfer_dma = uvc_urb->dma; #endif - stream->urb[i] = urb; + uvc_urb->urb = urb; } return 0; @@ -1740,10 +1804,12 @@ static int uvc_init_video_bulk(struct uvc_streaming *stream, /* * Initialize isochronous/bulk URBs and allocate transfer buffers. */ -static int uvc_init_video(struct uvc_streaming *stream, gfp_t gfp_flags) +static int uvc_video_start_transfer(struct uvc_streaming *stream, + gfp_t gfp_flags) { struct usb_interface *intf = stream->intf; struct usb_host_endpoint *ep; + struct uvc_urb *uvc_urb; unsigned int i; int ret; @@ -1821,12 +1887,12 @@ static int uvc_init_video(struct uvc_streaming *stream, gfp_t gfp_flags) return ret; /* Submit the URBs. */ - for (i = 0; i < UVC_URBS; ++i) { - ret = usb_submit_urb(stream->urb[i], gfp_flags); + for_each_uvc_urb(uvc_urb, stream) { + ret = usb_submit_urb(uvc_urb->urb, gfp_flags); if (ret < 0) { - uvc_printk(KERN_ERR, "Failed to submit URB %u " - "(%d).\n", i, ret); - uvc_uninit_video(stream, 1); + uvc_printk(KERN_ERR, "Failed to submit URB %u (%d).\n", + uvc_urb_index(uvc_urb), ret); + uvc_video_stop_transfer(stream, 1); return ret; } } @@ -1857,7 +1923,7 @@ int uvc_video_suspend(struct uvc_streaming *stream) return 0; stream->frozen = 1; - uvc_uninit_video(stream, 0); + uvc_video_stop_transfer(stream, 0); usb_set_interface(stream->dev->udev, stream->intfnum, 0); return 0; } @@ -1893,7 +1959,7 @@ int uvc_video_resume(struct uvc_streaming *stream, int reset) if (ret < 0) return ret; - return uvc_init_video(stream, GFP_NOIO); + return uvc_video_start_transfer(stream, GFP_NOIO); } /* ------------------------------------------------------------------------ @@ -1915,6 +1981,7 @@ int uvc_video_init(struct uvc_streaming *stream) struct uvc_streaming_control *probe = &stream->ctrl; struct uvc_format *format = NULL; struct uvc_frame *frame = NULL; + struct uvc_urb *uvc_urb; unsigned int i; int ret; @@ -2000,41 +2067,17 @@ int uvc_video_init(struct uvc_streaming *stream) } } + /* Prepare asynchronous work items. */ + for_each_uvc_urb(uvc_urb, stream) + INIT_WORK(&uvc_urb->work, uvc_video_copy_data_work); + return 0; } -/* - * Enable or disable the video stream. - */ -int uvc_video_enable(struct uvc_streaming *stream, int enable) +int uvc_video_start_streaming(struct uvc_streaming *stream) { int ret; - if (!enable) { - uvc_uninit_video(stream, 1); - if (stream->intf->num_altsetting > 1) { - usb_set_interface(stream->dev->udev, - stream->intfnum, 0); - } else { - /* UVC doesn't specify how to inform a bulk-based device - * when the video stream is stopped. Windows sends a - * CLEAR_FEATURE(HALT) request to the video streaming - * bulk endpoint, mimic the same behaviour. - */ - unsigned int epnum = stream->header.bEndpointAddress - & USB_ENDPOINT_NUMBER_MASK; - unsigned int dir = stream->header.bEndpointAddress - & USB_ENDPOINT_DIR_MASK; - unsigned int pipe; - - pipe = usb_sndbulkpipe(stream->dev->udev, epnum) | dir; - usb_clear_halt(stream->dev->udev, pipe); - } - - uvc_video_clock_cleanup(stream); - return 0; - } - ret = uvc_video_clock_init(stream); if (ret < 0) return ret; @@ -2044,7 +2087,7 @@ int uvc_video_enable(struct uvc_streaming *stream, int enable) if (ret < 0) goto error_commit; - ret = uvc_init_video(stream, GFP_KERNEL); + ret = uvc_video_start_transfer(stream, GFP_KERNEL); if (ret < 0) goto error_video; @@ -2057,3 +2100,28 @@ error_commit: return ret; } + +void uvc_video_stop_streaming(struct uvc_streaming *stream) +{ + uvc_video_stop_transfer(stream, 1); + + if (stream->intf->num_altsetting > 1) { + usb_set_interface(stream->dev->udev, stream->intfnum, 0); + } else { + /* UVC doesn't specify how to inform a bulk-based device + * when the video stream is stopped. Windows sends a + * CLEAR_FEATURE(HALT) request to the video streaming + * bulk endpoint, mimic the same behaviour. + */ + unsigned int epnum = stream->header.bEndpointAddress + & USB_ENDPOINT_NUMBER_MASK; + unsigned int dir = stream->header.bEndpointAddress + & USB_ENDPOINT_DIR_MASK; + unsigned int pipe; + + pipe = usb_sndbulkpipe(stream->dev->udev, epnum) | dir; + usb_clear_halt(stream->dev->udev, pipe); + } + + uvc_video_clock_cleanup(stream); +} diff --git a/drivers/media/usb/uvc/uvcvideo.h b/drivers/media/usb/uvc/uvcvideo.h index c0cbd833d0a4..9b41b14ce076 100644 --- a/drivers/media/usb/uvc/uvcvideo.h +++ b/drivers/media/usb/uvc/uvcvideo.h @@ -154,6 +154,9 @@ #define UVC_GUID_FORMAT_INVI \ { 'I', 'N', 'V', 'I', 0xdb, 0x57, 0x49, 0x5e, \ 0x8e, 0x3f, 0xf4, 0x79, 0x53, 0x2b, 0x94, 0x6f} +#define UVC_GUID_FORMAT_CNF4 \ + { 'C', ' ', ' ', ' ', 0x00, 0x00, 0x10, 0x00, \ + 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71} #define UVC_GUID_FORMAT_D3DFMT_L8 \ {0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, \ @@ -410,6 +413,9 @@ struct uvc_buffer { unsigned int bytesused; u32 pts; + + /* Asynchronous buffer handling. */ + struct kref ref; }; #define UVC_QUEUE_DISCONNECTED (1 << 0) @@ -487,6 +493,44 @@ struct uvc_stats_stream { #define UVC_METATADA_BUF_SIZE 1024 +/** + * struct uvc_copy_op: Context structure to schedule asynchronous memcpy + * + * @buf: active buf object for this operation + * @dst: copy destination address + * @src: copy source address + * @len: copy length + */ +struct uvc_copy_op { + struct uvc_buffer *buf; + void *dst; + const __u8 *src; + size_t len; +}; + +/** + * struct uvc_urb - URB context management structure + * + * @urb: the URB described by this context structure + * @stream: UVC streaming context + * @buffer: memory storage for the URB + * @dma: DMA coherent addressing for the urb_buffer + * @async_operations: counter to indicate the number of copy operations + * @copy_operations: work descriptors for asynchronous copy operations + * @work: work queue entry for asynchronous decode + */ +struct uvc_urb { + struct urb *urb; + struct uvc_streaming *stream; + + char *buffer; + dma_addr_t dma; + + unsigned int async_operations; + struct uvc_copy_op copy_operations[UVC_MAX_PACKETS]; + struct work_struct work; +}; + struct uvc_streaming { struct list_head list; struct uvc_device *dev; @@ -517,8 +561,9 @@ struct uvc_streaming { /* Buffers queue. */ unsigned int frozen : 1; struct uvc_video_queue queue; - void (*decode) (struct urb *urb, struct uvc_streaming *video, - struct uvc_buffer *buf, struct uvc_buffer *meta_buf); + struct workqueue_struct *async_wq; + void (*decode)(struct uvc_urb *uvc_urb, struct uvc_buffer *buf, + struct uvc_buffer *meta_buf); struct { struct video_device vdev; @@ -535,9 +580,7 @@ struct uvc_streaming { u32 max_payload_size; } bulk; - struct urb *urb[UVC_URBS]; - char *urb_buffer[UVC_URBS]; - dma_addr_t urb_dma[UVC_URBS]; + struct uvc_urb uvc_urb[UVC_URBS]; unsigned int urb_size; u32 sequence; @@ -572,6 +615,14 @@ struct uvc_streaming { } clock; }; +#define for_each_uvc_urb(uvc_urb, uvc_streaming) \ + for ((uvc_urb) = &(uvc_streaming)->uvc_urb[0]; \ + (uvc_urb) < &(uvc_streaming)->uvc_urb[UVC_URBS]; \ + ++(uvc_urb)) + +#define uvc_urb_index(uvc_urb) \ + (unsigned int)((uvc_urb) - (&(uvc_urb)->stream->uvc_urb[0])) + struct uvc_device_info { u32 quirks; u32 meta_format; @@ -711,6 +762,8 @@ int uvc_queue_streamoff(struct uvc_video_queue *queue, enum v4l2_buf_type type); void uvc_queue_cancel(struct uvc_video_queue *queue, int disconnect); struct uvc_buffer *uvc_queue_next_buffer(struct uvc_video_queue *queue, struct uvc_buffer *buf); +struct uvc_buffer *uvc_queue_get_current_buffer(struct uvc_video_queue *queue); +void uvc_queue_buffer_release(struct uvc_buffer *buf); int uvc_queue_mmap(struct uvc_video_queue *queue, struct vm_area_struct *vma); __poll_t uvc_queue_poll(struct uvc_video_queue *queue, struct file *file, @@ -737,7 +790,8 @@ void uvc_mc_cleanup_entity(struct uvc_entity *entity); int uvc_video_init(struct uvc_streaming *stream); int uvc_video_suspend(struct uvc_streaming *stream); int uvc_video_resume(struct uvc_streaming *stream, int reset); -int uvc_video_enable(struct uvc_streaming *stream, int enable); +int uvc_video_start_streaming(struct uvc_streaming *stream); +void uvc_video_stop_streaming(struct uvc_streaming *stream); int uvc_probe_video(struct uvc_streaming *stream, struct uvc_streaming_control *probe); int uvc_query_ctrl(struct uvc_device *dev, u8 query, u8 unit, @@ -757,6 +811,7 @@ int uvc_register_video_device(struct uvc_device *dev, /* Status */ int uvc_status_init(struct uvc_device *dev); +void uvc_status_unregister(struct uvc_device *dev); void uvc_status_cleanup(struct uvc_device *dev); int uvc_status_start(struct uvc_device *dev, gfp_t flags); void uvc_status_stop(struct uvc_device *dev); @@ -806,7 +861,7 @@ struct usb_host_endpoint *uvc_find_endpoint(struct usb_host_interface *alts, u8 epaddr); /* Quirks support */ -void uvc_video_decode_isight(struct urb *urb, struct uvc_streaming *stream, +void uvc_video_decode_isight(struct uvc_urb *uvc_urb, struct uvc_buffer *buf, struct uvc_buffer *meta_buf); diff --git a/drivers/media/v4l2-core/Kconfig b/drivers/media/v4l2-core/Kconfig index b97090e85996..c0940f5c69b4 100644 --- a/drivers/media/v4l2-core/Kconfig +++ b/drivers/media/v4l2-core/Kconfig @@ -30,6 +30,7 @@ config VIDEO_FIXED_MINOR_RANGES config VIDEO_PCI_SKELETON tristate "Skeleton PCI V4L2 driver" depends on PCI + depends on SAMPLES depends on VIDEO_V4L2 && VIDEOBUF2_CORE depends on VIDEOBUF2_MEMOPS && VIDEOBUF2_DMA_CONTIG ---help--- diff --git a/drivers/media/v4l2-core/v4l2-async.c b/drivers/media/v4l2-core/v4l2-async.c index a6d91370838d..15b0c44a76e7 100644 --- a/drivers/media/v4l2-core/v4l2-async.c +++ b/drivers/media/v4l2-core/v4l2-async.c @@ -424,11 +424,7 @@ static int v4l2_async_notifier_asd_valid(struct v4l2_async_notifier *notifier, void v4l2_async_notifier_init(struct v4l2_async_notifier *notifier) { - mutex_lock(&list_lock); - INIT_LIST_HEAD(¬ifier->asd_list); - - mutex_unlock(&list_lock); } EXPORT_SYMBOL(v4l2_async_notifier_init); diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c index 10b8d94edbef..5e3806feb5d7 100644 --- a/drivers/media/v4l2-core/v4l2-ctrls.c +++ b/drivers/media/v4l2-core/v4l2-ctrls.c @@ -1636,7 +1636,8 @@ static int std_validate(const struct v4l2_ctrl *ctrl, u32 idx, switch (p_mpeg2_slice_params->picture.intra_dc_precision) { case 0: /* 8 bits */ case 1: /* 9 bits */ - case 11: /* 11 bits */ + case 2: /* 10 bits */ + case 3: /* 11 bits */ break; default: return -EINVAL; diff --git a/drivers/media/v4l2-core/v4l2-dev.c b/drivers/media/v4l2-core/v4l2-dev.c index feb749aaaa42..2130e3a0f4da 100644 --- a/drivers/media/v4l2-core/v4l2-dev.c +++ b/drivers/media/v4l2-core/v4l2-dev.c @@ -635,14 +635,14 @@ static void determine_valid_ioctls(struct video_device *vdev) SET_VALID_IOCTL(ops, VIDIOC_TRY_DECODER_CMD, vidioc_try_decoder_cmd); SET_VALID_IOCTL(ops, VIDIOC_ENUM_FRAMESIZES, vidioc_enum_framesizes); SET_VALID_IOCTL(ops, VIDIOC_ENUM_FRAMEINTERVALS, vidioc_enum_frameintervals); - if (ops->vidioc_g_crop || ops->vidioc_g_selection) + if (ops->vidioc_g_selection) { set_bit(_IOC_NR(VIDIOC_G_CROP), valid_ioctls); - if (ops->vidioc_s_crop || ops->vidioc_s_selection) + set_bit(_IOC_NR(VIDIOC_CROPCAP), valid_ioctls); + } + if (ops->vidioc_s_selection) set_bit(_IOC_NR(VIDIOC_S_CROP), valid_ioctls); SET_VALID_IOCTL(ops, VIDIOC_G_SELECTION, vidioc_g_selection); SET_VALID_IOCTL(ops, VIDIOC_S_SELECTION, vidioc_s_selection); - if (ops->vidioc_cropcap || ops->vidioc_g_selection) - set_bit(_IOC_NR(VIDIOC_CROPCAP), valid_ioctls); } else if (is_vbi) { /* vbi specific ioctls */ if ((is_rx && (ops->vidioc_g_fmt_vbi_cap || diff --git a/drivers/media/v4l2-core/v4l2-device.c b/drivers/media/v4l2-core/v4l2-device.c index df0ac38c4050..e0ddb9a52bd1 100644 --- a/drivers/media/v4l2-core/v4l2-device.c +++ b/drivers/media/v4l2-core/v4l2-device.c @@ -247,6 +247,7 @@ int v4l2_device_register_subdev_nodes(struct v4l2_device *v4l2_dev) video_set_drvdata(vdev, sd); strscpy(vdev->name, sd->name, sizeof(vdev->name)); + vdev->dev_parent = sd->dev; vdev->v4l2_dev = v4l2_dev; vdev->fops = &v4l2_subdev_fops; vdev->release = v4l2_device_release_subdev_node; diff --git a/drivers/media/v4l2-core/v4l2-fwnode.c b/drivers/media/v4l2-core/v4l2-fwnode.c index 218f0da0ce76..f0a6c0c6f162 100644 --- a/drivers/media/v4l2-core/v4l2-fwnode.c +++ b/drivers/media/v4l2-core/v4l2-fwnode.c @@ -564,8 +564,7 @@ int v4l2_fwnode_parse_link(struct fwnode_handle *__fwnode, fwnode = fwnode_get_parent(__fwnode); fwnode_property_read_u32(fwnode, port_prop, &link->local_port); fwnode = fwnode_get_next_parent(fwnode); - if (is_of_node(fwnode) && - of_node_cmp(to_of_node(fwnode)->name, "ports") == 0) + if (is_of_node(fwnode) && of_node_name_eq(to_of_node(fwnode), "ports")) fwnode = fwnode_get_next_parent(fwnode); link->local_node = fwnode; @@ -578,8 +577,7 @@ int v4l2_fwnode_parse_link(struct fwnode_handle *__fwnode, fwnode = fwnode_get_parent(fwnode); fwnode_property_read_u32(fwnode, port_prop, &link->remote_port); fwnode = fwnode_get_next_parent(fwnode); - if (is_of_node(fwnode) && - of_node_cmp(to_of_node(fwnode)->name, "ports") == 0) + if (is_of_node(fwnode) && of_node_name_eq(to_of_node(fwnode), "ports")) fwnode = fwnode_get_next_parent(fwnode); link->remote_node = fwnode; @@ -613,7 +611,7 @@ v4l2_async_notifier_fwnode_parse_endpoint(struct device *dev, asd->match.fwnode = fwnode_graph_get_remote_port_parent(endpoint); if (!asd->match.fwnode) { - dev_warn(dev, "bad remote port parent\n"); + dev_dbg(dev, "no remote endpoint found\n"); ret = -ENOTCONN; goto out_err; } diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c index c63746968fa3..ef58bc31bfde 100644 --- a/drivers/media/v4l2-core/v4l2-ioctl.c +++ b/drivers/media/v4l2-core/v4l2-ioctl.c @@ -1189,6 +1189,7 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) case V4L2_PIX_FMT_Y12I: descr = "Interleaved 12-bit Greyscale"; break; case V4L2_PIX_FMT_Z16: descr = "16-bit Depth"; break; case V4L2_PIX_FMT_INZI: descr = "Planar 10:16 Greyscale Depth"; break; + case V4L2_PIX_FMT_CNF4: descr = "4-bit Depth Confidence (Packed)"; break; case V4L2_PIX_FMT_PAL8: descr = "8-bit Palette"; break; case V4L2_PIX_FMT_UV8: descr = "8-bit Chrominance UV 4-4"; break; case V4L2_PIX_FMT_YVU410: descr = "Planar YVU 4:1:0"; break; @@ -1339,9 +1340,9 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) case V4L2_PIX_FMT_MT21C: descr = "Mediatek Compressed Format"; break; case V4L2_PIX_FMT_SUNXI_TILED_NV12: descr = "Sunxi Tiled NV12 Format"; break; default: - WARN(1, "Unknown pixelformat 0x%08x\n", fmt->pixelformat); if (fmt->description[0]) return; + WARN(1, "Unknown pixelformat 0x%08x\n", fmt->pixelformat); flags = 0; snprintf(fmt->description, sz, "%c%c%c%c%s", (char)(fmt->pixelformat & 0x7f), @@ -1512,6 +1513,7 @@ static int v4l_s_fmt(const struct v4l2_ioctl_ops *ops, struct v4l2_format *p = arg; struct video_device *vfd = video_devdata(file); int ret = check_fmt(file, p->type); + unsigned int i; if (ret) return ret; @@ -1536,6 +1538,8 @@ static int v4l_s_fmt(const struct v4l2_ioctl_ops *ops, if (unlikely(!ops->vidioc_s_fmt_vid_cap_mplane)) break; CLEAR_AFTER_FIELD(p, fmt.pix_mp.xfer_func); + for (i = 0; i < p->fmt.pix_mp.num_planes; i++) + CLEAR_AFTER_FIELD(p, fmt.pix_mp.plane_fmt[i].bytesperline); return ops->vidioc_s_fmt_vid_cap_mplane(file, fh, arg); case V4L2_BUF_TYPE_VIDEO_OVERLAY: if (unlikely(!ops->vidioc_s_fmt_vid_overlay)) @@ -1564,6 +1568,8 @@ static int v4l_s_fmt(const struct v4l2_ioctl_ops *ops, if (unlikely(!ops->vidioc_s_fmt_vid_out_mplane)) break; CLEAR_AFTER_FIELD(p, fmt.pix_mp.xfer_func); + for (i = 0; i < p->fmt.pix_mp.num_planes; i++) + CLEAR_AFTER_FIELD(p, fmt.pix_mp.plane_fmt[i].bytesperline); return ops->vidioc_s_fmt_vid_out_mplane(file, fh, arg); case V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY: if (unlikely(!ops->vidioc_s_fmt_vid_out_overlay)) @@ -1604,6 +1610,7 @@ static int v4l_try_fmt(const struct v4l2_ioctl_ops *ops, { struct v4l2_format *p = arg; int ret = check_fmt(file, p->type); + unsigned int i; if (ret) return ret; @@ -1623,6 +1630,8 @@ static int v4l_try_fmt(const struct v4l2_ioctl_ops *ops, if (unlikely(!ops->vidioc_try_fmt_vid_cap_mplane)) break; CLEAR_AFTER_FIELD(p, fmt.pix_mp.xfer_func); + for (i = 0; i < p->fmt.pix_mp.num_planes; i++) + CLEAR_AFTER_FIELD(p, fmt.pix_mp.plane_fmt[i].bytesperline); return ops->vidioc_try_fmt_vid_cap_mplane(file, fh, arg); case V4L2_BUF_TYPE_VIDEO_OVERLAY: if (unlikely(!ops->vidioc_try_fmt_vid_overlay)) @@ -1651,6 +1660,8 @@ static int v4l_try_fmt(const struct v4l2_ioctl_ops *ops, if (unlikely(!ops->vidioc_try_fmt_vid_out_mplane)) break; CLEAR_AFTER_FIELD(p, fmt.pix_mp.xfer_func); + for (i = 0; i < p->fmt.pix_mp.num_planes; i++) + CLEAR_AFTER_FIELD(p, fmt.pix_mp.plane_fmt[i].bytesperline); return ops->vidioc_try_fmt_vid_out_mplane(file, fh, arg); case V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY: if (unlikely(!ops->vidioc_try_fmt_vid_out_overlay)) @@ -2202,21 +2213,24 @@ static int v4l_s_selection(const struct v4l2_ioctl_ops *ops, static int v4l_g_crop(const struct v4l2_ioctl_ops *ops, struct file *file, void *fh, void *arg) { + struct video_device *vfd = video_devdata(file); struct v4l2_crop *p = arg; struct v4l2_selection s = { .type = p->type, }; int ret; - if (ops->vidioc_g_crop) - return ops->vidioc_g_crop(file, fh, p); /* simulate capture crop using selection api */ /* crop means compose for output devices */ if (V4L2_TYPE_IS_OUTPUT(p->type)) - s.target = V4L2_SEL_TGT_COMPOSE_ACTIVE; + s.target = V4L2_SEL_TGT_COMPOSE; else - s.target = V4L2_SEL_TGT_CROP_ACTIVE; + s.target = V4L2_SEL_TGT_CROP; + + if (test_bit(V4L2_FL_QUIRK_INVERTED_CROP, &vfd->flags)) + s.target = s.target == V4L2_SEL_TGT_COMPOSE ? + V4L2_SEL_TGT_CROP : V4L2_SEL_TGT_COMPOSE; ret = v4l_g_selection(ops, file, fh, &s); @@ -2229,21 +2243,24 @@ static int v4l_g_crop(const struct v4l2_ioctl_ops *ops, static int v4l_s_crop(const struct v4l2_ioctl_ops *ops, struct file *file, void *fh, void *arg) { + struct video_device *vfd = video_devdata(file); struct v4l2_crop *p = arg; struct v4l2_selection s = { .type = p->type, .r = p->c, }; - if (ops->vidioc_s_crop) - return ops->vidioc_s_crop(file, fh, p); /* simulate capture crop using selection api */ /* crop means compose for output devices */ if (V4L2_TYPE_IS_OUTPUT(p->type)) - s.target = V4L2_SEL_TGT_COMPOSE_ACTIVE; + s.target = V4L2_SEL_TGT_COMPOSE; else - s.target = V4L2_SEL_TGT_CROP_ACTIVE; + s.target = V4L2_SEL_TGT_CROP; + + if (test_bit(V4L2_FL_QUIRK_INVERTED_CROP, &vfd->flags)) + s.target = s.target == V4L2_SEL_TGT_COMPOSE ? + V4L2_SEL_TGT_CROP : V4L2_SEL_TGT_COMPOSE; return v4l_s_selection(ops, file, fh, &s); } @@ -2251,6 +2268,7 @@ static int v4l_s_crop(const struct v4l2_ioctl_ops *ops, static int v4l_cropcap(const struct v4l2_ioctl_ops *ops, struct file *file, void *fh, void *arg) { + struct video_device *vfd = video_devdata(file); struct v4l2_cropcap *p = arg; struct v4l2_selection s = { .type = p->type }; int ret = 0; @@ -2259,18 +2277,21 @@ static int v4l_cropcap(const struct v4l2_ioctl_ops *ops, p->pixelaspect.numerator = 1; p->pixelaspect.denominator = 1; + if (s.type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) + s.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + else if (s.type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) + s.type = V4L2_BUF_TYPE_VIDEO_OUTPUT; + /* * The determine_valid_ioctls() call already should ensure * that this can never happen, but just in case... */ - if (WARN_ON(!ops->vidioc_cropcap && !ops->vidioc_g_selection)) + if (WARN_ON(!ops->vidioc_g_selection)) return -ENOTTY; - if (ops->vidioc_cropcap) - ret = ops->vidioc_cropcap(file, fh, p); - - if (!ops->vidioc_g_selection) - return ret; + if (ops->vidioc_g_pixelaspect) + ret = ops->vidioc_g_pixelaspect(file, fh, s.type, + &p->pixelaspect); /* * Ignore ENOTTY or ENOIOCTLCMD error returns, just use the @@ -2287,13 +2308,17 @@ static int v4l_cropcap(const struct v4l2_ioctl_ops *ops, else s.target = V4L2_SEL_TGT_CROP_BOUNDS; + if (test_bit(V4L2_FL_QUIRK_INVERTED_CROP, &vfd->flags)) + s.target = s.target == V4L2_SEL_TGT_COMPOSE_BOUNDS ? + V4L2_SEL_TGT_CROP_BOUNDS : V4L2_SEL_TGT_COMPOSE_BOUNDS; + ret = v4l_g_selection(ops, file, fh, &s); if (ret) return ret; p->bounds = s.r; /* obtaining defrect */ - if (V4L2_TYPE_IS_OUTPUT(p->type)) + if (s.target == V4L2_SEL_TGT_COMPOSE_BOUNDS) s.target = V4L2_SEL_TGT_COMPOSE_DEFAULT; else s.target = V4L2_SEL_TGT_CROP_DEFAULT; @@ -2586,7 +2611,7 @@ DEFINE_V4L_STUB_FUNC(enum_dv_timings) DEFINE_V4L_STUB_FUNC(query_dv_timings) DEFINE_V4L_STUB_FUNC(dv_timings_cap) -static struct v4l2_ioctl_info v4l2_ioctls[] = { +static const struct v4l2_ioctl_info v4l2_ioctls[] = { IOCTL_INFO(VIDIOC_QUERYCAP, v4l_querycap, v4l_print_querycap, 0), IOCTL_INFO(VIDIOC_ENUM_FMT, v4l_enum_fmt, v4l_print_fmtdesc, INFO_FL_CLEAR(v4l2_fmtdesc, type)), IOCTL_INFO(VIDIOC_G_FMT, v4l_g_fmt, v4l_print_format, 0), @@ -2679,45 +2704,6 @@ static bool v4l2_is_known_ioctl(unsigned int cmd) return v4l2_ioctls[_IOC_NR(cmd)].ioctl == cmd; } -#if IS_ENABLED(CONFIG_V4L2_MEM2MEM_DEV) -static bool v4l2_ioctl_m2m_queue_is_output(unsigned int cmd, void *arg) -{ - switch (cmd) { - case VIDIOC_CREATE_BUFS: { - struct v4l2_create_buffers *cbufs = arg; - - return V4L2_TYPE_IS_OUTPUT(cbufs->format.type); - } - case VIDIOC_REQBUFS: { - struct v4l2_requestbuffers *rbufs = arg; - - return V4L2_TYPE_IS_OUTPUT(rbufs->type); - } - case VIDIOC_QBUF: - case VIDIOC_DQBUF: - case VIDIOC_QUERYBUF: - case VIDIOC_PREPARE_BUF: { - struct v4l2_buffer *buf = arg; - - return V4L2_TYPE_IS_OUTPUT(buf->type); - } - case VIDIOC_EXPBUF: { - struct v4l2_exportbuffer *expbuf = arg; - - return V4L2_TYPE_IS_OUTPUT(expbuf->type); - } - case VIDIOC_STREAMON: - case VIDIOC_STREAMOFF: { - int *type = arg; - - return V4L2_TYPE_IS_OUTPUT(*type); - } - default: - return false; - } -} -#endif - static struct mutex *v4l2_ioctl_get_lock(struct video_device *vdev, struct v4l2_fh *vfh, unsigned int cmd, void *arg) @@ -2727,12 +2713,8 @@ static struct mutex *v4l2_ioctl_get_lock(struct video_device *vdev, #if IS_ENABLED(CONFIG_V4L2_MEM2MEM_DEV) if (vfh && vfh->m2m_ctx && (v4l2_ioctls[_IOC_NR(cmd)].flags & INFO_FL_QUEUE)) { - bool is_output = v4l2_ioctl_m2m_queue_is_output(cmd, arg); - struct v4l2_m2m_queue_ctx *ctx = is_output ? - &vfh->m2m_ctx->out_q_ctx : &vfh->m2m_ctx->cap_q_ctx; - - if (ctx->q.lock) - return ctx->q.lock; + if (vfh->m2m_ctx->q_lock) + return vfh->m2m_ctx->q_lock; } #endif if (vdev->queue && vdev->queue->lock && diff --git a/drivers/media/v4l2-core/v4l2-mem2mem.c b/drivers/media/v4l2-core/v4l2-mem2mem.c index 1ed2465972ac..5bbdec55b7d7 100644 --- a/drivers/media/v4l2-core/v4l2-mem2mem.c +++ b/drivers/media/v4l2-core/v4l2-mem2mem.c @@ -87,6 +87,7 @@ static const char * const m2m_entity_name[] = { * @curr_ctx: currently running instance * @job_queue: instances queued to run * @job_spinlock: protects job_queue + * @job_work: worker to run queued jobs. * @m2m_ops: driver callbacks */ struct v4l2_m2m_dev { @@ -103,6 +104,7 @@ struct v4l2_m2m_dev { struct list_head job_queue; spinlock_t job_spinlock; + struct work_struct job_work; const struct v4l2_m2m_ops *m2m_ops; }; @@ -244,6 +246,9 @@ EXPORT_SYMBOL(v4l2_m2m_get_curr_priv); * @m2m_dev: per-device context * * Get next transaction (if present) from the waiting jobs list and run it. + * + * Note that this function can run on a given v4l2_m2m_ctx context, + * but call .device_run for another context. */ static void v4l2_m2m_try_run(struct v4l2_m2m_dev *m2m_dev) { @@ -297,51 +302,48 @@ static void __v4l2_m2m_try_queue(struct v4l2_m2m_dev *m2m_dev, /* If the context is aborted then don't schedule it */ if (m2m_ctx->job_flags & TRANS_ABORT) { - spin_unlock_irqrestore(&m2m_dev->job_spinlock, flags_job); dprintk("Aborted context\n"); - return; + goto job_unlock; } if (m2m_ctx->job_flags & TRANS_QUEUED) { - spin_unlock_irqrestore(&m2m_dev->job_spinlock, flags_job); dprintk("On job queue already\n"); - return; + goto job_unlock; } spin_lock_irqsave(&m2m_ctx->out_q_ctx.rdy_spinlock, flags_out); if (list_empty(&m2m_ctx->out_q_ctx.rdy_queue) && !m2m_ctx->out_q_ctx.buffered) { - spin_unlock_irqrestore(&m2m_ctx->out_q_ctx.rdy_spinlock, - flags_out); - spin_unlock_irqrestore(&m2m_dev->job_spinlock, flags_job); dprintk("No input buffers available\n"); - return; + goto out_unlock; } spin_lock_irqsave(&m2m_ctx->cap_q_ctx.rdy_spinlock, flags_cap); if (list_empty(&m2m_ctx->cap_q_ctx.rdy_queue) && !m2m_ctx->cap_q_ctx.buffered) { - spin_unlock_irqrestore(&m2m_ctx->cap_q_ctx.rdy_spinlock, - flags_cap); - spin_unlock_irqrestore(&m2m_ctx->out_q_ctx.rdy_spinlock, - flags_out); - spin_unlock_irqrestore(&m2m_dev->job_spinlock, flags_job); dprintk("No output buffers available\n"); - return; + goto cap_unlock; } spin_unlock_irqrestore(&m2m_ctx->cap_q_ctx.rdy_spinlock, flags_cap); spin_unlock_irqrestore(&m2m_ctx->out_q_ctx.rdy_spinlock, flags_out); if (m2m_dev->m2m_ops->job_ready && (!m2m_dev->m2m_ops->job_ready(m2m_ctx->priv))) { - spin_unlock_irqrestore(&m2m_dev->job_spinlock, flags_job); dprintk("Driver not ready\n"); - return; + goto job_unlock; } list_add_tail(&m2m_ctx->queue, &m2m_dev->job_queue); m2m_ctx->job_flags |= TRANS_QUEUED; spin_unlock_irqrestore(&m2m_dev->job_spinlock, flags_job); + return; + +cap_unlock: + spin_unlock_irqrestore(&m2m_ctx->cap_q_ctx.rdy_spinlock, flags_cap); +out_unlock: + spin_unlock_irqrestore(&m2m_ctx->out_q_ctx.rdy_spinlock, flags_out); +job_unlock: + spin_unlock_irqrestore(&m2m_dev->job_spinlock, flags_job); } /** @@ -366,6 +368,18 @@ void v4l2_m2m_try_schedule(struct v4l2_m2m_ctx *m2m_ctx) EXPORT_SYMBOL_GPL(v4l2_m2m_try_schedule); /** + * v4l2_m2m_device_run_work() - run pending jobs for the context + * @work: Work structure used for scheduling the execution of this function. + */ +static void v4l2_m2m_device_run_work(struct work_struct *work) +{ + struct v4l2_m2m_dev *m2m_dev = + container_of(work, struct v4l2_m2m_dev, job_work); + + v4l2_m2m_try_run(m2m_dev); +} + +/** * v4l2_m2m_cancel_job() - cancel pending jobs for the context * @m2m_ctx: m2m context with jobs to be canceled * @@ -424,7 +438,12 @@ void v4l2_m2m_job_finish(struct v4l2_m2m_dev *m2m_dev, /* This instance might have more buffers ready, but since we do not * allow more than one job on the job_queue per instance, each has * to be scheduled separately after the previous one finishes. */ - v4l2_m2m_try_schedule(m2m_ctx); + __v4l2_m2m_try_queue(m2m_dev, m2m_ctx); + + /* We might be running in atomic context, + * but the job must be run in non-atomic context. + */ + schedule_work(&m2m_dev->job_work); } EXPORT_SYMBOL(v4l2_m2m_job_finish); @@ -866,6 +885,7 @@ struct v4l2_m2m_dev *v4l2_m2m_init(const struct v4l2_m2m_ops *m2m_ops) m2m_dev->m2m_ops = m2m_ops; INIT_LIST_HEAD(&m2m_dev->job_queue); spin_lock_init(&m2m_dev->job_spinlock); + INIT_WORK(&m2m_dev->job_work, v4l2_m2m_device_run_work); return m2m_dev; } @@ -908,12 +928,14 @@ struct v4l2_m2m_ctx *v4l2_m2m_ctx_init(struct v4l2_m2m_dev *m2m_dev, if (ret) goto err; /* - * If both queues use same mutex assign it as the common buffer - * queues lock to the m2m context. This lock is used in the - * v4l2_m2m_ioctl_* helpers. + * Both queues should use same the mutex to lock the m2m context. + * This lock is used in some v4l2_m2m_* helpers. */ - if (out_q_ctx->q.lock == cap_q_ctx->q.lock) - m2m_ctx->q_lock = out_q_ctx->q.lock; + if (WARN_ON(out_q_ctx->q.lock != cap_q_ctx->q.lock)) { + ret = -EINVAL; + goto err; + } + m2m_ctx->q_lock = out_q_ctx->q.lock; return m2m_ctx; err: diff --git a/drivers/staging/media/Kconfig b/drivers/staging/media/Kconfig index b3620a8f2d9f..c6f3404dea43 100644 --- a/drivers/staging/media/Kconfig +++ b/drivers/staging/media/Kconfig @@ -31,6 +31,8 @@ source "drivers/staging/media/mt9t031/Kconfig" source "drivers/staging/media/omap4iss/Kconfig" +source "drivers/staging/media/rockchip/vpu/Kconfig" + source "drivers/staging/media/sunxi/Kconfig" source "drivers/staging/media/tegra-vde/Kconfig" diff --git a/drivers/staging/media/Makefile b/drivers/staging/media/Makefile index 42948f805548..43c7bee1fc8c 100644 --- a/drivers/staging/media/Makefile +++ b/drivers/staging/media/Makefile @@ -8,3 +8,4 @@ obj-$(CONFIG_VIDEO_OMAP4) += omap4iss/ obj-$(CONFIG_VIDEO_SUNXI) += sunxi/ obj-$(CONFIG_TEGRA_VDE) += tegra-vde/ obj-$(CONFIG_VIDEO_ZORAN) += zoran/ +obj-$(CONFIG_VIDEO_ROCKCHIP_VPU) += rockchip/vpu/ diff --git a/drivers/staging/media/bcm2048/radio-bcm2048.c b/drivers/staging/media/bcm2048/radio-bcm2048.c index 874d290f9622..debd1122875d 100644 --- a/drivers/staging/media/bcm2048/radio-bcm2048.c +++ b/drivers/staging/media/bcm2048/radio-bcm2048.c @@ -2574,8 +2574,7 @@ static const struct video_device bcm2048_viddev_template = { /* * I2C driver interface */ -static int bcm2048_i2c_driver_probe(struct i2c_client *client, - const struct i2c_device_id *id) +static int bcm2048_i2c_driver_probe(struct i2c_client *client) { struct bcm2048_device *bdev; int err; @@ -2679,7 +2678,7 @@ static struct i2c_driver bcm2048_i2c_driver = { .driver = { .name = BCM2048_DRIVER_NAME, }, - .probe = bcm2048_i2c_driver_probe, + .probe_new = bcm2048_i2c_driver_probe, .remove = bcm2048_i2c_driver_remove, .id_table = bcm2048_id, }; diff --git a/drivers/staging/media/imx/imx-media-of.c b/drivers/staging/media/imx/imx-media-of.c index b2e840f96c50..a01327f6e045 100644 --- a/drivers/staging/media/imx/imx-media-of.c +++ b/drivers/staging/media/imx/imx-media-of.c @@ -162,7 +162,7 @@ int imx_media_create_csi_of_links(struct imx_media_dev *imxmd, fwnode_property_read_u32(fwnode, "reg", &link.remote_port); fwnode = fwnode_get_next_parent(fwnode); if (is_of_node(fwnode) && - of_node_cmp(to_of_node(fwnode)->name, "ports") == 0) + of_node_name_eq(to_of_node(fwnode), "ports")) fwnode = fwnode_get_next_parent(fwnode); link.remote_node = fwnode; diff --git a/drivers/staging/media/rockchip/vpu/Kconfig b/drivers/staging/media/rockchip/vpu/Kconfig new file mode 100644 index 000000000000..9a6fc1378242 --- /dev/null +++ b/drivers/staging/media/rockchip/vpu/Kconfig @@ -0,0 +1,13 @@ +config VIDEO_ROCKCHIP_VPU + tristate "Rockchip VPU driver" + depends on ARCH_ROCKCHIP || COMPILE_TEST + depends on VIDEO_DEV && VIDEO_V4L2 && MEDIA_CONTROLLER + select VIDEOBUF2_DMA_CONTIG + select VIDEOBUF2_VMALLOC + select V4L2_MEM2MEM_DEV + default n + help + Support for the Video Processing Unit present on Rockchip SoC, + which accelerates video and image encoding and decoding. + To compile this driver as a module, choose M here: the module + will be called rockchip-vpu. diff --git a/drivers/staging/media/rockchip/vpu/Makefile b/drivers/staging/media/rockchip/vpu/Makefile new file mode 100644 index 000000000000..e9d733bb7632 --- /dev/null +++ b/drivers/staging/media/rockchip/vpu/Makefile @@ -0,0 +1,10 @@ +obj-$(CONFIG_VIDEO_ROCKCHIP_VPU) += rockchip-vpu.o + +rockchip-vpu-y += \ + rockchip_vpu_drv.o \ + rockchip_vpu_enc.o \ + rk3288_vpu_hw.o \ + rk3288_vpu_hw_jpeg_enc.o \ + rk3399_vpu_hw.o \ + rk3399_vpu_hw_jpeg_enc.o \ + rockchip_vpu_jpeg.o diff --git a/drivers/staging/media/rockchip/vpu/TODO b/drivers/staging/media/rockchip/vpu/TODO new file mode 100644 index 000000000000..fa0c94057007 --- /dev/null +++ b/drivers/staging/media/rockchip/vpu/TODO @@ -0,0 +1,13 @@ +* Support for VP8, VP9 and H264 is planned for this driver. + + Given the V4L controls for those CODECs will be part of + the uABI, it will be required to have the driver in staging. + + For this reason, we are keeping this driver in staging for now. + +* Add support for the S_SELECTION API. + See the comment for VEPU_REG_ENC_OVER_FILL_STRM_OFFSET. + +* Instead of having a DMA bounce buffer, it could be possible to use a + normal buffer and memmove() the payload to make space for the header. + This might need to use extra JPEG markers for padding reasons. diff --git a/drivers/staging/media/rockchip/vpu/rk3288_vpu_hw.c b/drivers/staging/media/rockchip/vpu/rk3288_vpu_hw.c new file mode 100644 index 000000000000..a5e9d183fffd --- /dev/null +++ b/drivers/staging/media/rockchip/vpu/rk3288_vpu_hw.c @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Rockchip VPU codec driver + * + * Copyright (C) 2018 Rockchip Electronics Co., Ltd. + * Jeffy Chen <jeffy.chen@rock-chips.com> + */ + +#include <linux/clk.h> + +#include "rockchip_vpu.h" +#include "rockchip_vpu_jpeg.h" +#include "rk3288_vpu_regs.h" + +#define RK3288_ACLK_MAX_FREQ (400 * 1000 * 1000) + +/* + * Supported formats. + */ + +static const struct rockchip_vpu_fmt rk3288_vpu_enc_fmts[] = { + { + .fourcc = V4L2_PIX_FMT_YUV420M, + .codec_mode = RK_VPU_MODE_NONE, + .enc_fmt = RK3288_VPU_ENC_FMT_YUV420P, + }, + { + .fourcc = V4L2_PIX_FMT_NV12M, + .codec_mode = RK_VPU_MODE_NONE, + .enc_fmt = RK3288_VPU_ENC_FMT_YUV420SP, + }, + { + .fourcc = V4L2_PIX_FMT_YUYV, + .codec_mode = RK_VPU_MODE_NONE, + .enc_fmt = RK3288_VPU_ENC_FMT_YUYV422, + }, + { + .fourcc = V4L2_PIX_FMT_UYVY, + .codec_mode = RK_VPU_MODE_NONE, + .enc_fmt = RK3288_VPU_ENC_FMT_UYVY422, + }, + { + .fourcc = V4L2_PIX_FMT_JPEG, + .codec_mode = RK_VPU_MODE_JPEG_ENC, + .max_depth = 2, + .header_size = JPEG_HEADER_SIZE, + .frmsize = { + .min_width = 96, + .max_width = 8192, + .step_width = JPEG_MB_DIM, + .min_height = 32, + .max_height = 8192, + .step_height = JPEG_MB_DIM, + }, + }, +}; + +static irqreturn_t rk3288_vepu_irq(int irq, void *dev_id) +{ + struct rockchip_vpu_dev *vpu = dev_id; + enum vb2_buffer_state state; + u32 status, bytesused; + + status = vepu_read(vpu, VEPU_REG_INTERRUPT); + bytesused = vepu_read(vpu, VEPU_REG_STR_BUF_LIMIT) / 8; + state = (status & VEPU_REG_INTERRUPT_FRAME_RDY) ? + VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR; + + vepu_write(vpu, 0, VEPU_REG_INTERRUPT); + vepu_write(vpu, 0, VEPU_REG_AXI_CTRL); + + rockchip_vpu_irq_done(vpu, bytesused, state); + + return IRQ_HANDLED; +} + +static int rk3288_vpu_hw_init(struct rockchip_vpu_dev *vpu) +{ + /* Bump ACLK to max. possible freq. to improve performance. */ + clk_set_rate(vpu->clocks[0].clk, RK3288_ACLK_MAX_FREQ); + return 0; +} + +static void rk3288_vpu_enc_reset(struct rockchip_vpu_ctx *ctx) +{ + struct rockchip_vpu_dev *vpu = ctx->dev; + + vepu_write(vpu, VEPU_REG_INTERRUPT_DIS_BIT, VEPU_REG_INTERRUPT); + vepu_write(vpu, 0, VEPU_REG_ENC_CTRL); + vepu_write(vpu, 0, VEPU_REG_AXI_CTRL); +} + +/* + * Supported codec ops. + */ + +static const struct rockchip_vpu_codec_ops rk3288_vpu_codec_ops[] = { + [RK_VPU_MODE_JPEG_ENC] = { + .run = rk3288_vpu_jpeg_enc_run, + .reset = rk3288_vpu_enc_reset, + }, +}; + +/* + * VPU variant. + */ + +const struct rockchip_vpu_variant rk3288_vpu_variant = { + .enc_offset = 0x0, + .enc_fmts = rk3288_vpu_enc_fmts, + .num_enc_fmts = ARRAY_SIZE(rk3288_vpu_enc_fmts), + .codec_ops = rk3288_vpu_codec_ops, + .codec = RK_VPU_CODEC_JPEG, + .vepu_irq = rk3288_vepu_irq, + .init = rk3288_vpu_hw_init, + .clk_names = {"aclk", "hclk"}, + .num_clocks = 2 +}; diff --git a/drivers/staging/media/rockchip/vpu/rk3288_vpu_hw_jpeg_enc.c b/drivers/staging/media/rockchip/vpu/rk3288_vpu_hw_jpeg_enc.c new file mode 100644 index 000000000000..5282236d1bb1 --- /dev/null +++ b/drivers/staging/media/rockchip/vpu/rk3288_vpu_hw_jpeg_enc.c @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Rockchip VPU codec driver + * + * Copyright (C) 2018 Rockchip Electronics Co., Ltd. + */ + +#include <asm/unaligned.h> +#include <media/v4l2-mem2mem.h> +#include "rockchip_vpu_jpeg.h" +#include "rockchip_vpu.h" +#include "rockchip_vpu_common.h" +#include "rockchip_vpu_hw.h" +#include "rk3288_vpu_regs.h" + +#define VEPU_JPEG_QUANT_TABLE_COUNT 16 + +static void rk3288_vpu_set_src_img_ctrl(struct rockchip_vpu_dev *vpu, + struct rockchip_vpu_ctx *ctx) +{ + struct v4l2_pix_format_mplane *pix_fmt = &ctx->src_fmt; + u32 reg; + + reg = VEPU_REG_IN_IMG_CTRL_ROW_LEN(pix_fmt->width) + | VEPU_REG_IN_IMG_CTRL_OVRFLR_D4(0) + | VEPU_REG_IN_IMG_CTRL_OVRFLB_D4(0) + | VEPU_REG_IN_IMG_CTRL_FMT(ctx->vpu_src_fmt->enc_fmt); + vepu_write_relaxed(vpu, reg, VEPU_REG_IN_IMG_CTRL); +} + +static void rk3288_vpu_jpeg_enc_set_buffers(struct rockchip_vpu_dev *vpu, + struct rockchip_vpu_ctx *ctx, + struct vb2_buffer *src_buf) +{ + struct v4l2_pix_format_mplane *pix_fmt = &ctx->src_fmt; + dma_addr_t src[3]; + + WARN_ON(pix_fmt->num_planes > 3); + + vepu_write_relaxed(vpu, ctx->bounce_dma_addr, + VEPU_REG_ADDR_OUTPUT_STREAM); + vepu_write_relaxed(vpu, ctx->bounce_size, + VEPU_REG_STR_BUF_LIMIT); + + if (pix_fmt->num_planes == 1) { + src[0] = vb2_dma_contig_plane_dma_addr(src_buf, 0); + /* single plane formats we supported are all interlaced */ + vepu_write_relaxed(vpu, src[0], VEPU_REG_ADDR_IN_PLANE_0); + } else if (pix_fmt->num_planes == 2) { + src[0] = vb2_dma_contig_plane_dma_addr(src_buf, 0); + src[1] = vb2_dma_contig_plane_dma_addr(src_buf, 1); + vepu_write_relaxed(vpu, src[0], VEPU_REG_ADDR_IN_PLANE_0); + vepu_write_relaxed(vpu, src[1], VEPU_REG_ADDR_IN_PLANE_1); + } else { + src[0] = vb2_dma_contig_plane_dma_addr(src_buf, 0); + src[1] = vb2_dma_contig_plane_dma_addr(src_buf, 1); + src[2] = vb2_dma_contig_plane_dma_addr(src_buf, 2); + vepu_write_relaxed(vpu, src[0], VEPU_REG_ADDR_IN_PLANE_0); + vepu_write_relaxed(vpu, src[1], VEPU_REG_ADDR_IN_PLANE_1); + vepu_write_relaxed(vpu, src[2], VEPU_REG_ADDR_IN_PLANE_2); + } +} + +static void +rk3288_vpu_jpeg_enc_set_qtable(struct rockchip_vpu_dev *vpu, + unsigned char *luma_qtable, + unsigned char *chroma_qtable) +{ + u32 reg, i; + + for (i = 0; i < VEPU_JPEG_QUANT_TABLE_COUNT; i++) { + reg = get_unaligned_be32(&luma_qtable[i]); + vepu_write_relaxed(vpu, reg, VEPU_REG_JPEG_LUMA_QUAT(i)); + + reg = get_unaligned_be32(&chroma_qtable[i]); + vepu_write_relaxed(vpu, reg, VEPU_REG_JPEG_CHROMA_QUAT(i)); + } +} + +void rk3288_vpu_jpeg_enc_run(struct rockchip_vpu_ctx *ctx) +{ + struct rockchip_vpu_dev *vpu = ctx->dev; + struct vb2_buffer *src_buf, *dst_buf; + struct rockchip_vpu_jpeg_ctx jpeg_ctx; + u32 reg; + + src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); + dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx); + + memset(&jpeg_ctx, 0, sizeof(jpeg_ctx)); + jpeg_ctx.buffer = vb2_plane_vaddr(dst_buf, 0); + jpeg_ctx.width = ctx->dst_fmt.width; + jpeg_ctx.height = ctx->dst_fmt.height; + jpeg_ctx.quality = ctx->jpeg_quality; + rockchip_vpu_jpeg_header_assemble(&jpeg_ctx); + + /* Switch to JPEG encoder mode before writing registers */ + vepu_write_relaxed(vpu, VEPU_REG_ENC_CTRL_ENC_MODE_JPEG, + VEPU_REG_ENC_CTRL); + + rk3288_vpu_set_src_img_ctrl(vpu, ctx); + rk3288_vpu_jpeg_enc_set_buffers(vpu, ctx, src_buf); + rk3288_vpu_jpeg_enc_set_qtable(vpu, + rockchip_vpu_jpeg_get_qtable(&jpeg_ctx, 0), + rockchip_vpu_jpeg_get_qtable(&jpeg_ctx, 1)); + + reg = VEPU_REG_AXI_CTRL_OUTPUT_SWAP16 + | VEPU_REG_AXI_CTRL_INPUT_SWAP16 + | VEPU_REG_AXI_CTRL_BURST_LEN(16) + | VEPU_REG_AXI_CTRL_OUTPUT_SWAP32 + | VEPU_REG_AXI_CTRL_INPUT_SWAP32 + | VEPU_REG_AXI_CTRL_OUTPUT_SWAP8 + | VEPU_REG_AXI_CTRL_INPUT_SWAP8; + /* Make sure that all registers are written at this point. */ + vepu_write(vpu, reg, VEPU_REG_AXI_CTRL); + + reg = VEPU_REG_ENC_CTRL_WIDTH(JPEG_MB_WIDTH(ctx->src_fmt.width)) + | VEPU_REG_ENC_CTRL_HEIGHT(JPEG_MB_HEIGHT(ctx->src_fmt.height)) + | VEPU_REG_ENC_CTRL_ENC_MODE_JPEG + | VEPU_REG_ENC_PIC_INTRA + | VEPU_REG_ENC_CTRL_EN_BIT; + /* Kick the watchdog and start encoding */ + schedule_delayed_work(&vpu->watchdog_work, msecs_to_jiffies(2000)); + vepu_write(vpu, reg, VEPU_REG_ENC_CTRL); +} diff --git a/drivers/staging/media/rockchip/vpu/rk3288_vpu_regs.h b/drivers/staging/media/rockchip/vpu/rk3288_vpu_regs.h new file mode 100644 index 000000000000..9d0b9bdf3297 --- /dev/null +++ b/drivers/staging/media/rockchip/vpu/rk3288_vpu_regs.h @@ -0,0 +1,442 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Rockchip VPU codec driver + * + * Copyright 2018 Google LLC. + * Tomasz Figa <tfiga@chromium.org> + */ + +#ifndef RK3288_VPU_REGS_H_ +#define RK3288_VPU_REGS_H_ + +/* Encoder registers. */ +#define VEPU_REG_INTERRUPT 0x004 +#define VEPU_REG_INTERRUPT_FRAME_RDY BIT(2) +#define VEPU_REG_INTERRUPT_DIS_BIT BIT(1) +#define VEPU_REG_INTERRUPT_BIT BIT(0) +#define VEPU_REG_AXI_CTRL 0x008 +#define VEPU_REG_AXI_CTRL_OUTPUT_SWAP16 BIT(15) +#define VEPU_REG_AXI_CTRL_INPUT_SWAP16 BIT(14) +#define VEPU_REG_AXI_CTRL_BURST_LEN(x) ((x) << 8) +#define VEPU_REG_AXI_CTRL_GATE_BIT BIT(4) +#define VEPU_REG_AXI_CTRL_OUTPUT_SWAP32 BIT(3) +#define VEPU_REG_AXI_CTRL_INPUT_SWAP32 BIT(2) +#define VEPU_REG_AXI_CTRL_OUTPUT_SWAP8 BIT(1) +#define VEPU_REG_AXI_CTRL_INPUT_SWAP8 BIT(0) +#define VEPU_REG_ADDR_OUTPUT_STREAM 0x014 +#define VEPU_REG_ADDR_OUTPUT_CTRL 0x018 +#define VEPU_REG_ADDR_REF_LUMA 0x01c +#define VEPU_REG_ADDR_REF_CHROMA 0x020 +#define VEPU_REG_ADDR_REC_LUMA 0x024 +#define VEPU_REG_ADDR_REC_CHROMA 0x028 +#define VEPU_REG_ADDR_IN_PLANE_0 0x02c +#define VEPU_REG_ADDR_IN_PLANE_1 0x030 +#define VEPU_REG_ADDR_IN_PLANE_2 0x034 +#define VEPU_REG_ENC_CTRL 0x038 +#define VEPU_REG_ENC_CTRL_TIMEOUT_EN BIT(31) +#define VEPU_REG_ENC_CTRL_NAL_MODE_BIT BIT(29) +#define VEPU_REG_ENC_CTRL_WIDTH(w) ((w) << 19) +#define VEPU_REG_ENC_CTRL_HEIGHT(h) ((h) << 10) +#define VEPU_REG_ENC_PIC_INTER (0x0 << 3) +#define VEPU_REG_ENC_PIC_INTRA (0x1 << 3) +#define VEPU_REG_ENC_PIC_MVCINTER (0x2 << 3) +#define VEPU_REG_ENC_CTRL_ENC_MODE_H264 (0x3 << 1) +#define VEPU_REG_ENC_CTRL_ENC_MODE_JPEG (0x2 << 1) +#define VEPU_REG_ENC_CTRL_ENC_MODE_VP8 (0x1 << 1) +#define VEPU_REG_ENC_CTRL_EN_BIT BIT(0) +#define VEPU_REG_IN_IMG_CTRL 0x03c +#define VEPU_REG_IN_IMG_CTRL_ROW_LEN(x) ((x) << 12) +#define VEPU_REG_IN_IMG_CTRL_OVRFLR_D4(x) ((x) << 10) +#define VEPU_REG_IN_IMG_CTRL_OVRFLB_D4(x) ((x) << 6) +#define VEPU_REG_IN_IMG_CTRL_FMT(x) ((x) << 2) +#define VEPU_REG_ENC_CTRL0 0x040 +#define VEPU_REG_ENC_CTRL0_INIT_QP(x) ((x) << 26) +#define VEPU_REG_ENC_CTRL0_SLICE_ALPHA(x) ((x) << 22) +#define VEPU_REG_ENC_CTRL0_SLICE_BETA(x) ((x) << 18) +#define VEPU_REG_ENC_CTRL0_CHROMA_QP_OFFSET(x) ((x) << 13) +#define VEPU_REG_ENC_CTRL0_FILTER_DIS(x) ((x) << 5) +#define VEPU_REG_ENC_CTRL0_IDR_PICID(x) ((x) << 1) +#define VEPU_REG_ENC_CTRL0_CONSTR_INTRA_PRED BIT(0) +#define VEPU_REG_ENC_CTRL1 0x044 +#define VEPU_REG_ENC_CTRL1_PPS_ID(x) ((x) << 24) +#define VEPU_REG_ENC_CTRL1_INTRA_PRED_MODE(x) ((x) << 16) +#define VEPU_REG_ENC_CTRL1_FRAME_NUM(x) ((x)) +#define VEPU_REG_ENC_CTRL2 0x048 +#define VEPU_REG_ENC_CTRL2_DEBLOCKING_FILETER_MODE(x) ((x) << 30) +#define VEPU_REG_ENC_CTRL2_H264_SLICE_SIZE(x) ((x) << 23) +#define VEPU_REG_ENC_CTRL2_DISABLE_QUARTER_PIXMV BIT(22) +#define VEPU_REG_ENC_CTRL2_TRANS8X8_MODE_EN BIT(21) +#define VEPU_REG_ENC_CTRL2_CABAC_INIT_IDC(x) ((x) << 19) +#define VEPU_REG_ENC_CTRL2_ENTROPY_CODING_MODE BIT(18) +#define VEPU_REG_ENC_CTRL2_H264_INTER4X4_MODE BIT(17) +#define VEPU_REG_ENC_CTRL2_H264_STREAM_MODE BIT(16) +#define VEPU_REG_ENC_CTRL2_INTRA16X16_MODE(x) ((x)) +#define VEPU_REG_ENC_CTRL3 0x04c +#define VEPU_REG_ENC_CTRL3_MUTIMV_EN BIT(30) +#define VEPU_REG_ENC_CTRL3_MV_PENALTY_1_4P(x) ((x) << 20) +#define VEPU_REG_ENC_CTRL3_MV_PENALTY_4P(x) ((x) << 10) +#define VEPU_REG_ENC_CTRL3_MV_PENALTY_1P(x) ((x)) +#define VEPU_REG_ENC_CTRL4 0x050 +#define VEPU_REG_ENC_CTRL4_MV_PENALTY_16X8_8X16(x) ((x) << 20) +#define VEPU_REG_ENC_CTRL4_MV_PENALTY_8X8(x) ((x) << 10) +#define VEPU_REG_ENC_CTRL4_8X4_4X8(x) ((x)) +#define VEPU_REG_ENC_CTRL5 0x054 +#define VEPU_REG_ENC_CTRL5_MACROBLOCK_PENALTY(x) ((x) << 24) +#define VEPU_REG_ENC_CTRL5_COMPLETE_SLICES(x) ((x) << 16) +#define VEPU_REG_ENC_CTRL5_INTER_MODE(x) ((x)) +#define VEPU_REG_STR_HDR_REM_MSB 0x058 +#define VEPU_REG_STR_HDR_REM_LSB 0x05c +#define VEPU_REG_STR_BUF_LIMIT 0x060 +#define VEPU_REG_MAD_CTRL 0x064 +#define VEPU_REG_MAD_CTRL_QP_ADJUST(x) ((x) << 28) +#define VEPU_REG_MAD_CTRL_MAD_THREDHOLD(x) ((x) << 22) +#define VEPU_REG_MAD_CTRL_QP_SUM_DIV2(x) ((x)) +#define VEPU_REG_ADDR_VP8_PROB_CNT 0x068 +#define VEPU_REG_QP_VAL 0x06c +#define VEPU_REG_QP_VAL_LUM(x) ((x) << 26) +#define VEPU_REG_QP_VAL_MAX(x) ((x) << 20) +#define VEPU_REG_QP_VAL_MIN(x) ((x) << 14) +#define VEPU_REG_QP_VAL_CHECKPOINT_DISTAN(x) ((x)) +#define VEPU_REG_VP8_QP_VAL(i) (0x06c + ((i) * 0x4)) +#define VEPU_REG_CHECKPOINT(i) (0x070 + ((i) * 0x4)) +#define VEPU_REG_CHECKPOINT_CHECK0(x) (((x) & 0xffff)) +#define VEPU_REG_CHECKPOINT_CHECK1(x) (((x) & 0xffff) << 16) +#define VEPU_REG_CHECKPOINT_RESULT(x) ((((x) >> (16 - 16 \ + * (i & 1))) & 0xffff) \ + * 32) +#define VEPU_REG_CHKPT_WORD_ERR(i) (0x084 + ((i) * 0x4)) +#define VEPU_REG_CHKPT_WORD_ERR_CHK0(x) (((x) & 0xffff)) +#define VEPU_REG_CHKPT_WORD_ERR_CHK1(x) (((x) & 0xffff) << 16) +#define VEPU_REG_VP8_BOOL_ENC 0x08c +#define VEPU_REG_CHKPT_DELTA_QP 0x090 +#define VEPU_REG_CHKPT_DELTA_QP_CHK0(x) (((x) & 0x0f) << 0) +#define VEPU_REG_CHKPT_DELTA_QP_CHK1(x) (((x) & 0x0f) << 4) +#define VEPU_REG_CHKPT_DELTA_QP_CHK2(x) (((x) & 0x0f) << 8) +#define VEPU_REG_CHKPT_DELTA_QP_CHK3(x) (((x) & 0x0f) << 12) +#define VEPU_REG_CHKPT_DELTA_QP_CHK4(x) (((x) & 0x0f) << 16) +#define VEPU_REG_CHKPT_DELTA_QP_CHK5(x) (((x) & 0x0f) << 20) +#define VEPU_REG_CHKPT_DELTA_QP_CHK6(x) (((x) & 0x0f) << 24) +#define VEPU_REG_VP8_CTRL0 0x090 +#define VEPU_REG_RLC_CTRL 0x094 +#define VEPU_REG_RLC_CTRL_STR_OFFS_SHIFT 23 +#define VEPU_REG_RLC_CTRL_STR_OFFS_MASK (0x3f << 23) +#define VEPU_REG_RLC_CTRL_RLC_SUM(x) ((x)) +#define VEPU_REG_MB_CTRL 0x098 +#define VEPU_REG_MB_CNT_OUT(x) (((x) & 0xffff)) +#define VEPU_REG_MB_CNT_SET(x) (((x) & 0xffff) << 16) +#define VEPU_REG_ADDR_NEXT_PIC 0x09c +#define VEPU_REG_JPEG_LUMA_QUAT(i) (0x100 + ((i) * 0x4)) +#define VEPU_REG_JPEG_CHROMA_QUAT(i) (0x140 + ((i) * 0x4)) +#define VEPU_REG_STABILIZATION_OUTPUT 0x0A0 +#define VEPU_REG_ADDR_CABAC_TBL 0x0cc +#define VEPU_REG_ADDR_MV_OUT 0x0d0 +#define VEPU_REG_RGB_YUV_COEFF(i) (0x0d4 + ((i) * 0x4)) +#define VEPU_REG_RGB_MASK_MSB 0x0dc +#define VEPU_REG_INTRA_AREA_CTRL 0x0e0 +#define VEPU_REG_CIR_INTRA_CTRL 0x0e4 +#define VEPU_REG_INTRA_SLICE_BITMAP(i) (0x0e8 + ((i) * 0x4)) +#define VEPU_REG_ADDR_VP8_DCT_PART(i) (0x0e8 + ((i) * 0x4)) +#define VEPU_REG_FIRST_ROI_AREA 0x0f0 +#define VEPU_REG_SECOND_ROI_AREA 0x0f4 +#define VEPU_REG_MVC_CTRL 0x0f8 +#define VEPU_REG_MVC_CTRL_MV16X16_FAVOR(x) ((x) << 28) +#define VEPU_REG_VP8_INTRA_PENALTY(i) (0x100 + ((i) * 0x4)) +#define VEPU_REG_ADDR_VP8_SEG_MAP 0x11c +#define VEPU_REG_VP8_SEG_QP(i) (0x120 + ((i) * 0x4)) +#define VEPU_REG_DMV_4P_1P_PENALTY(i) (0x180 + ((i) * 0x4)) +#define VEPU_REG_DMV_4P_1P_PENALTY_BIT(x, i) ((x) << (i) * 8) +#define VEPU_REG_DMV_QPEL_PENALTY(i) (0x200 + ((i) * 0x4)) +#define VEPU_REG_DMV_QPEL_PENALTY_BIT(x, i) ((x) << (i) * 8) +#define VEPU_REG_VP8_CTRL1 0x280 +#define VEPU_REG_VP8_BIT_COST_GOLDEN 0x284 +#define VEPU_REG_VP8_LOOP_FLT_DELTA(i) (0x288 + ((i) * 0x4)) + +/* Decoder registers. */ +#define VDPU_REG_INTERRUPT 0x004 +#define VDPU_REG_INTERRUPT_DEC_PIC_INF BIT(24) +#define VDPU_REG_INTERRUPT_DEC_TIMEOUT BIT(18) +#define VDPU_REG_INTERRUPT_DEC_SLICE_INT BIT(17) +#define VDPU_REG_INTERRUPT_DEC_ERROR_INT BIT(16) +#define VDPU_REG_INTERRUPT_DEC_ASO_INT BIT(15) +#define VDPU_REG_INTERRUPT_DEC_BUFFER_INT BIT(14) +#define VDPU_REG_INTERRUPT_DEC_BUS_INT BIT(13) +#define VDPU_REG_INTERRUPT_DEC_RDY_INT BIT(12) +#define VDPU_REG_INTERRUPT_DEC_IRQ BIT(8) +#define VDPU_REG_INTERRUPT_DEC_IRQ_DIS BIT(4) +#define VDPU_REG_INTERRUPT_DEC_E BIT(0) +#define VDPU_REG_CONFIG 0x008 +#define VDPU_REG_CONFIG_DEC_AXI_RD_ID(x) (((x) & 0xff) << 24) +#define VDPU_REG_CONFIG_DEC_TIMEOUT_E BIT(23) +#define VDPU_REG_CONFIG_DEC_STRSWAP32_E BIT(22) +#define VDPU_REG_CONFIG_DEC_STRENDIAN_E BIT(21) +#define VDPU_REG_CONFIG_DEC_INSWAP32_E BIT(20) +#define VDPU_REG_CONFIG_DEC_OUTSWAP32_E BIT(19) +#define VDPU_REG_CONFIG_DEC_DATA_DISC_E BIT(18) +#define VDPU_REG_CONFIG_TILED_MODE_MSB BIT(17) +#define VDPU_REG_CONFIG_DEC_OUT_TILED_E BIT(17) +#define VDPU_REG_CONFIG_DEC_LATENCY(x) (((x) & 0x3f) << 11) +#define VDPU_REG_CONFIG_DEC_CLK_GATE_E BIT(10) +#define VDPU_REG_CONFIG_DEC_IN_ENDIAN BIT(9) +#define VDPU_REG_CONFIG_DEC_OUT_ENDIAN BIT(8) +#define VDPU_REG_CONFIG_PRIORITY_MODE(x) (((x) & 0x7) << 5) +#define VDPU_REG_CONFIG_TILED_MODE_LSB BIT(7) +#define VDPU_REG_CONFIG_DEC_ADV_PRE_DIS BIT(6) +#define VDPU_REG_CONFIG_DEC_SCMD_DIS BIT(5) +#define VDPU_REG_CONFIG_DEC_MAX_BURST(x) (((x) & 0x1f) << 0) +#define VDPU_REG_DEC_CTRL0 0x00c +#define VDPU_REG_DEC_CTRL0_DEC_MODE(x) (((x) & 0xf) << 28) +#define VDPU_REG_DEC_CTRL0_RLC_MODE_E BIT(27) +#define VDPU_REG_DEC_CTRL0_SKIP_MODE BIT(26) +#define VDPU_REG_DEC_CTRL0_DIVX3_E BIT(25) +#define VDPU_REG_DEC_CTRL0_PJPEG_E BIT(24) +#define VDPU_REG_DEC_CTRL0_PIC_INTERLACE_E BIT(23) +#define VDPU_REG_DEC_CTRL0_PIC_FIELDMODE_E BIT(22) +#define VDPU_REG_DEC_CTRL0_PIC_B_E BIT(21) +#define VDPU_REG_DEC_CTRL0_PIC_INTER_E BIT(20) +#define VDPU_REG_DEC_CTRL0_PIC_TOPFIELD_E BIT(19) +#define VDPU_REG_DEC_CTRL0_FWD_INTERLACE_E BIT(18) +#define VDPU_REG_DEC_CTRL0_SORENSON_E BIT(17) +#define VDPU_REG_DEC_CTRL0_REF_TOPFIELD_E BIT(16) +#define VDPU_REG_DEC_CTRL0_DEC_OUT_DIS BIT(15) +#define VDPU_REG_DEC_CTRL0_FILTERING_DIS BIT(14) +#define VDPU_REG_DEC_CTRL0_WEBP_E BIT(13) +#define VDPU_REG_DEC_CTRL0_MVC_E BIT(13) +#define VDPU_REG_DEC_CTRL0_PIC_FIXED_QUANT BIT(13) +#define VDPU_REG_DEC_CTRL0_WRITE_MVS_E BIT(12) +#define VDPU_REG_DEC_CTRL0_REFTOPFIRST_E BIT(11) +#define VDPU_REG_DEC_CTRL0_SEQ_MBAFF_E BIT(10) +#define VDPU_REG_DEC_CTRL0_PICORD_COUNT_E BIT(9) +#define VDPU_REG_DEC_CTRL0_DEC_AHB_HLOCK_E BIT(8) +#define VDPU_REG_DEC_CTRL0_DEC_AXI_WR_ID(x) (((x) & 0xff) << 0) +#define VDPU_REG_DEC_CTRL1 0x010 +#define VDPU_REG_DEC_CTRL1_PIC_MB_WIDTH(x) (((x) & 0x1ff) << 23) +#define VDPU_REG_DEC_CTRL1_MB_WIDTH_OFF(x) (((x) & 0xf) << 19) +#define VDPU_REG_DEC_CTRL1_PIC_MB_HEIGHT_P(x) (((x) & 0xff) << 11) +#define VDPU_REG_DEC_CTRL1_MB_HEIGHT_OFF(x) (((x) & 0xf) << 7) +#define VDPU_REG_DEC_CTRL1_ALT_SCAN_E BIT(6) +#define VDPU_REG_DEC_CTRL1_TOPFIELDFIRST_E BIT(5) +#define VDPU_REG_DEC_CTRL1_REF_FRAMES(x) (((x) & 0x1f) << 0) +#define VDPU_REG_DEC_CTRL1_PIC_MB_W_EXT(x) (((x) & 0x7) << 3) +#define VDPU_REG_DEC_CTRL1_PIC_MB_H_EXT(x) (((x) & 0x7) << 0) +#define VDPU_REG_DEC_CTRL1_PIC_REFER_FLAG BIT(0) +#define VDPU_REG_DEC_CTRL2 0x014 +#define VDPU_REG_DEC_CTRL2_STRM_START_BIT(x) (((x) & 0x3f) << 26) +#define VDPU_REG_DEC_CTRL2_SYNC_MARKER_E BIT(25) +#define VDPU_REG_DEC_CTRL2_TYPE1_QUANT_E BIT(24) +#define VDPU_REG_DEC_CTRL2_CH_QP_OFFSET(x) (((x) & 0x1f) << 19) +#define VDPU_REG_DEC_CTRL2_CH_QP_OFFSET2(x) (((x) & 0x1f) << 14) +#define VDPU_REG_DEC_CTRL2_FIELDPIC_FLAG_E BIT(0) +#define VDPU_REG_DEC_CTRL2_INTRADC_VLC_THR(x) (((x) & 0x7) << 16) +#define VDPU_REG_DEC_CTRL2_VOP_TIME_INCR(x) (((x) & 0xffff) << 0) +#define VDPU_REG_DEC_CTRL2_DQ_PROFILE BIT(24) +#define VDPU_REG_DEC_CTRL2_DQBI_LEVEL BIT(23) +#define VDPU_REG_DEC_CTRL2_RANGE_RED_FRM_E BIT(22) +#define VDPU_REG_DEC_CTRL2_FAST_UVMC_E BIT(20) +#define VDPU_REG_DEC_CTRL2_TRANSDCTAB BIT(17) +#define VDPU_REG_DEC_CTRL2_TRANSACFRM(x) (((x) & 0x3) << 15) +#define VDPU_REG_DEC_CTRL2_TRANSACFRM2(x) (((x) & 0x3) << 13) +#define VDPU_REG_DEC_CTRL2_MB_MODE_TAB(x) (((x) & 0x7) << 10) +#define VDPU_REG_DEC_CTRL2_MVTAB(x) (((x) & 0x7) << 7) +#define VDPU_REG_DEC_CTRL2_CBPTAB(x) (((x) & 0x7) << 4) +#define VDPU_REG_DEC_CTRL2_2MV_BLK_PAT_TAB(x) (((x) & 0x3) << 2) +#define VDPU_REG_DEC_CTRL2_4MV_BLK_PAT_TAB(x) (((x) & 0x3) << 0) +#define VDPU_REG_DEC_CTRL2_QSCALE_TYPE BIT(24) +#define VDPU_REG_DEC_CTRL2_CON_MV_E BIT(4) +#define VDPU_REG_DEC_CTRL2_INTRA_DC_PREC(x) (((x) & 0x3) << 2) +#define VDPU_REG_DEC_CTRL2_INTRA_VLC_TAB BIT(1) +#define VDPU_REG_DEC_CTRL2_FRAME_PRED_DCT BIT(0) +#define VDPU_REG_DEC_CTRL2_JPEG_QTABLES(x) (((x) & 0x3) << 11) +#define VDPU_REG_DEC_CTRL2_JPEG_MODE(x) (((x) & 0x7) << 8) +#define VDPU_REG_DEC_CTRL2_JPEG_FILRIGHT_E BIT(7) +#define VDPU_REG_DEC_CTRL2_JPEG_STREAM_ALL BIT(6) +#define VDPU_REG_DEC_CTRL2_CR_AC_VLCTABLE BIT(5) +#define VDPU_REG_DEC_CTRL2_CB_AC_VLCTABLE BIT(4) +#define VDPU_REG_DEC_CTRL2_CR_DC_VLCTABLE BIT(3) +#define VDPU_REG_DEC_CTRL2_CB_DC_VLCTABLE BIT(2) +#define VDPU_REG_DEC_CTRL2_CR_DC_VLCTABLE3 BIT(1) +#define VDPU_REG_DEC_CTRL2_CB_DC_VLCTABLE3 BIT(0) +#define VDPU_REG_DEC_CTRL2_STRM1_START_BIT(x) (((x) & 0x3f) << 18) +#define VDPU_REG_DEC_CTRL2_HUFFMAN_E BIT(17) +#define VDPU_REG_DEC_CTRL2_MULTISTREAM_E BIT(16) +#define VDPU_REG_DEC_CTRL2_BOOLEAN_VALUE(x) (((x) & 0xff) << 8) +#define VDPU_REG_DEC_CTRL2_BOOLEAN_RANGE(x) (((x) & 0xff) << 0) +#define VDPU_REG_DEC_CTRL2_ALPHA_OFFSET(x) (((x) & 0x1f) << 5) +#define VDPU_REG_DEC_CTRL2_BETA_OFFSET(x) (((x) & 0x1f) << 0) +#define VDPU_REG_DEC_CTRL3 0x018 +#define VDPU_REG_DEC_CTRL3_START_CODE_E BIT(31) +#define VDPU_REG_DEC_CTRL3_INIT_QP(x) (((x) & 0x3f) << 25) +#define VDPU_REG_DEC_CTRL3_CH_8PIX_ILEAV_E BIT(24) +#define VDPU_REG_DEC_CTRL3_STREAM_LEN_EXT(x) (((x) & 0xff) << 24) +#define VDPU_REG_DEC_CTRL3_STREAM_LEN(x) (((x) & 0xffffff) << 0) +#define VDPU_REG_DEC_CTRL4 0x01c +#define VDPU_REG_DEC_CTRL4_CABAC_E BIT(31) +#define VDPU_REG_DEC_CTRL4_BLACKWHITE_E BIT(30) +#define VDPU_REG_DEC_CTRL4_DIR_8X8_INFER_E BIT(29) +#define VDPU_REG_DEC_CTRL4_WEIGHT_PRED_E BIT(28) +#define VDPU_REG_DEC_CTRL4_WEIGHT_BIPR_IDC(x) (((x) & 0x3) << 26) +#define VDPU_REG_DEC_CTRL4_AVS_H264_H_EXT BIT(25) +#define VDPU_REG_DEC_CTRL4_FRAMENUM_LEN(x) (((x) & 0x1f) << 16) +#define VDPU_REG_DEC_CTRL4_FRAMENUM(x) (((x) & 0xffff) << 0) +#define VDPU_REG_DEC_CTRL4_BITPLANE0_E BIT(31) +#define VDPU_REG_DEC_CTRL4_BITPLANE1_E BIT(30) +#define VDPU_REG_DEC_CTRL4_BITPLANE2_E BIT(29) +#define VDPU_REG_DEC_CTRL4_ALT_PQUANT(x) (((x) & 0x1f) << 24) +#define VDPU_REG_DEC_CTRL4_DQ_EDGES(x) (((x) & 0xf) << 20) +#define VDPU_REG_DEC_CTRL4_TTMBF BIT(19) +#define VDPU_REG_DEC_CTRL4_PQINDEX(x) (((x) & 0x1f) << 14) +#define VDPU_REG_DEC_CTRL4_VC1_HEIGHT_EXT BIT(13) +#define VDPU_REG_DEC_CTRL4_BILIN_MC_E BIT(12) +#define VDPU_REG_DEC_CTRL4_UNIQP_E BIT(11) +#define VDPU_REG_DEC_CTRL4_HALFQP_E BIT(10) +#define VDPU_REG_DEC_CTRL4_TTFRM(x) (((x) & 0x3) << 8) +#define VDPU_REG_DEC_CTRL4_2ND_BYTE_EMUL_E BIT(7) +#define VDPU_REG_DEC_CTRL4_DQUANT_E BIT(6) +#define VDPU_REG_DEC_CTRL4_VC1_ADV_E BIT(5) +#define VDPU_REG_DEC_CTRL4_PJPEG_FILDOWN_E BIT(26) +#define VDPU_REG_DEC_CTRL4_PJPEG_WDIV8 BIT(25) +#define VDPU_REG_DEC_CTRL4_PJPEG_HDIV8 BIT(24) +#define VDPU_REG_DEC_CTRL4_PJPEG_AH(x) (((x) & 0xf) << 20) +#define VDPU_REG_DEC_CTRL4_PJPEG_AL(x) (((x) & 0xf) << 16) +#define VDPU_REG_DEC_CTRL4_PJPEG_SS(x) (((x) & 0xff) << 8) +#define VDPU_REG_DEC_CTRL4_PJPEG_SE(x) (((x) & 0xff) << 0) +#define VDPU_REG_DEC_CTRL4_DCT1_START_BIT(x) (((x) & 0x3f) << 26) +#define VDPU_REG_DEC_CTRL4_DCT2_START_BIT(x) (((x) & 0x3f) << 20) +#define VDPU_REG_DEC_CTRL4_CH_MV_RES BIT(13) +#define VDPU_REG_DEC_CTRL4_INIT_DC_MATCH0(x) (((x) & 0x7) << 9) +#define VDPU_REG_DEC_CTRL4_INIT_DC_MATCH1(x) (((x) & 0x7) << 6) +#define VDPU_REG_DEC_CTRL4_VP7_VERSION BIT(5) +#define VDPU_REG_DEC_CTRL5 0x020 +#define VDPU_REG_DEC_CTRL5_CONST_INTRA_E BIT(31) +#define VDPU_REG_DEC_CTRL5_FILT_CTRL_PRES BIT(30) +#define VDPU_REG_DEC_CTRL5_RDPIC_CNT_PRES BIT(29) +#define VDPU_REG_DEC_CTRL5_8X8TRANS_FLAG_E BIT(28) +#define VDPU_REG_DEC_CTRL5_REFPIC_MK_LEN(x) (((x) & 0x7ff) << 17) +#define VDPU_REG_DEC_CTRL5_IDR_PIC_E BIT(16) +#define VDPU_REG_DEC_CTRL5_IDR_PIC_ID(x) (((x) & 0xffff) << 0) +#define VDPU_REG_DEC_CTRL5_MV_SCALEFACTOR(x) (((x) & 0xff) << 24) +#define VDPU_REG_DEC_CTRL5_REF_DIST_FWD(x) (((x) & 0x1f) << 19) +#define VDPU_REG_DEC_CTRL5_REF_DIST_BWD(x) (((x) & 0x1f) << 14) +#define VDPU_REG_DEC_CTRL5_LOOP_FILT_LIMIT(x) (((x) & 0xf) << 14) +#define VDPU_REG_DEC_CTRL5_VARIANCE_TEST_E BIT(13) +#define VDPU_REG_DEC_CTRL5_MV_THRESHOLD(x) (((x) & 0x7) << 10) +#define VDPU_REG_DEC_CTRL5_VAR_THRESHOLD(x) (((x) & 0x3ff) << 0) +#define VDPU_REG_DEC_CTRL5_DIVX_IDCT_E BIT(8) +#define VDPU_REG_DEC_CTRL5_DIVX3_SLICE_SIZE(x) (((x) & 0xff) << 0) +#define VDPU_REG_DEC_CTRL5_PJPEG_REST_FREQ(x) (((x) & 0xffff) << 0) +#define VDPU_REG_DEC_CTRL5_RV_PROFILE(x) (((x) & 0x3) << 30) +#define VDPU_REG_DEC_CTRL5_RV_OSV_QUANT(x) (((x) & 0x3) << 28) +#define VDPU_REG_DEC_CTRL5_RV_FWD_SCALE(x) (((x) & 0x3fff) << 14) +#define VDPU_REG_DEC_CTRL5_RV_BWD_SCALE(x) (((x) & 0x3fff) << 0) +#define VDPU_REG_DEC_CTRL5_INIT_DC_COMP0(x) (((x) & 0xffff) << 16) +#define VDPU_REG_DEC_CTRL5_INIT_DC_COMP1(x) (((x) & 0xffff) << 0) +#define VDPU_REG_DEC_CTRL6 0x024 +#define VDPU_REG_DEC_CTRL6_PPS_ID(x) (((x) & 0xff) << 24) +#define VDPU_REG_DEC_CTRL6_REFIDX1_ACTIVE(x) (((x) & 0x1f) << 19) +#define VDPU_REG_DEC_CTRL6_REFIDX0_ACTIVE(x) (((x) & 0x1f) << 14) +#define VDPU_REG_DEC_CTRL6_POC_LENGTH(x) (((x) & 0xff) << 0) +#define VDPU_REG_DEC_CTRL6_ICOMP0_E BIT(24) +#define VDPU_REG_DEC_CTRL6_ISCALE0(x) (((x) & 0xff) << 16) +#define VDPU_REG_DEC_CTRL6_ISHIFT0(x) (((x) & 0xffff) << 0) +#define VDPU_REG_DEC_CTRL6_STREAM1_LEN(x) (((x) & 0xffffff) << 0) +#define VDPU_REG_DEC_CTRL6_PIC_SLICE_AM(x) (((x) & 0x1fff) << 0) +#define VDPU_REG_DEC_CTRL6_COEFFS_PART_AM(x) (((x) & 0xf) << 24) +#define VDPU_REG_FWD_PIC(i) (0x028 + ((i) * 0x4)) +#define VDPU_REG_FWD_PIC_PINIT_RLIST_F5(x) (((x) & 0x1f) << 25) +#define VDPU_REG_FWD_PIC_PINIT_RLIST_F4(x) (((x) & 0x1f) << 20) +#define VDPU_REG_FWD_PIC_PINIT_RLIST_F3(x) (((x) & 0x1f) << 15) +#define VDPU_REG_FWD_PIC_PINIT_RLIST_F2(x) (((x) & 0x1f) << 10) +#define VDPU_REG_FWD_PIC_PINIT_RLIST_F1(x) (((x) & 0x1f) << 5) +#define VDPU_REG_FWD_PIC_PINIT_RLIST_F0(x) (((x) & 0x1f) << 0) +#define VDPU_REG_FWD_PIC1_ICOMP1_E BIT(24) +#define VDPU_REG_FWD_PIC1_ISCALE1(x) (((x) & 0xff) << 16) +#define VDPU_REG_FWD_PIC1_ISHIFT1(x) (((x) & 0xffff) << 0) +#define VDPU_REG_FWD_PIC1_SEGMENT_BASE(x) ((x) << 0) +#define VDPU_REG_FWD_PIC1_SEGMENT_UPD_E BIT(1) +#define VDPU_REG_FWD_PIC1_SEGMENT_E BIT(0) +#define VDPU_REG_DEC_CTRL7 0x02c +#define VDPU_REG_DEC_CTRL7_PINIT_RLIST_F15(x) (((x) & 0x1f) << 25) +#define VDPU_REG_DEC_CTRL7_PINIT_RLIST_F14(x) (((x) & 0x1f) << 20) +#define VDPU_REG_DEC_CTRL7_PINIT_RLIST_F13(x) (((x) & 0x1f) << 15) +#define VDPU_REG_DEC_CTRL7_PINIT_RLIST_F12(x) (((x) & 0x1f) << 10) +#define VDPU_REG_DEC_CTRL7_PINIT_RLIST_F11(x) (((x) & 0x1f) << 5) +#define VDPU_REG_DEC_CTRL7_PINIT_RLIST_F10(x) (((x) & 0x1f) << 0) +#define VDPU_REG_DEC_CTRL7_ICOMP2_E BIT(24) +#define VDPU_REG_DEC_CTRL7_ISCALE2(x) (((x) & 0xff) << 16) +#define VDPU_REG_DEC_CTRL7_ISHIFT2(x) (((x) & 0xffff) << 0) +#define VDPU_REG_DEC_CTRL7_DCT3_START_BIT(x) (((x) & 0x3f) << 24) +#define VDPU_REG_DEC_CTRL7_DCT4_START_BIT(x) (((x) & 0x3f) << 18) +#define VDPU_REG_DEC_CTRL7_DCT5_START_BIT(x) (((x) & 0x3f) << 12) +#define VDPU_REG_DEC_CTRL7_DCT6_START_BIT(x) (((x) & 0x3f) << 6) +#define VDPU_REG_DEC_CTRL7_DCT7_START_BIT(x) (((x) & 0x3f) << 0) +#define VDPU_REG_ADDR_STR 0x030 +#define VDPU_REG_ADDR_DST 0x034 +#define VDPU_REG_ADDR_REF(i) (0x038 + ((i) * 0x4)) +#define VDPU_REG_ADDR_REF_FIELD_E BIT(1) +#define VDPU_REG_ADDR_REF_TOPC_E BIT(0) +#define VDPU_REG_REF_PIC(i) (0x078 + ((i) * 0x4)) +#define VDPU_REG_REF_PIC_FILT_TYPE_E BIT(31) +#define VDPU_REG_REF_PIC_FILT_SHARPNESS(x) (((x) & 0x7) << 28) +#define VDPU_REG_REF_PIC_MB_ADJ_0(x) (((x) & 0x7f) << 21) +#define VDPU_REG_REF_PIC_MB_ADJ_1(x) (((x) & 0x7f) << 14) +#define VDPU_REG_REF_PIC_MB_ADJ_2(x) (((x) & 0x7f) << 7) +#define VDPU_REG_REF_PIC_MB_ADJ_3(x) (((x) & 0x7f) << 0) +#define VDPU_REG_REF_PIC_REFER1_NBR(x) (((x) & 0xffff) << 16) +#define VDPU_REG_REF_PIC_REFER0_NBR(x) (((x) & 0xffff) << 0) +#define VDPU_REG_REF_PIC_LF_LEVEL_0(x) (((x) & 0x3f) << 18) +#define VDPU_REG_REF_PIC_LF_LEVEL_1(x) (((x) & 0x3f) << 12) +#define VDPU_REG_REF_PIC_LF_LEVEL_2(x) (((x) & 0x3f) << 6) +#define VDPU_REG_REF_PIC_LF_LEVEL_3(x) (((x) & 0x3f) << 0) +#define VDPU_REG_REF_PIC_QUANT_DELTA_0(x) (((x) & 0x1f) << 27) +#define VDPU_REG_REF_PIC_QUANT_DELTA_1(x) (((x) & 0x1f) << 22) +#define VDPU_REG_REF_PIC_QUANT_0(x) (((x) & 0x7ff) << 11) +#define VDPU_REG_REF_PIC_QUANT_1(x) (((x) & 0x7ff) << 0) +#define VDPU_REG_LT_REF 0x098 +#define VDPU_REG_VALID_REF 0x09c +#define VDPU_REG_ADDR_QTABLE 0x0a0 +#define VDPU_REG_ADDR_DIR_MV 0x0a4 +#define VDPU_REG_BD_REF_PIC(i) (0x0a8 + ((i) * 0x4)) +#define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B2(x) (((x) & 0x1f) << 25) +#define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F2(x) (((x) & 0x1f) << 20) +#define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B1(x) (((x) & 0x1f) << 15) +#define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F1(x) (((x) & 0x1f) << 10) +#define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B0(x) (((x) & 0x1f) << 5) +#define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F0(x) (((x) & 0x1f) << 0) +#define VDPU_REG_BD_REF_PIC_PRED_TAP_2_M1(x) (((x) & 0x3) << 10) +#define VDPU_REG_BD_REF_PIC_PRED_TAP_2_4(x) (((x) & 0x3) << 8) +#define VDPU_REG_BD_REF_PIC_PRED_TAP_4_M1(x) (((x) & 0x3) << 6) +#define VDPU_REG_BD_REF_PIC_PRED_TAP_4_4(x) (((x) & 0x3) << 4) +#define VDPU_REG_BD_REF_PIC_PRED_TAP_6_M1(x) (((x) & 0x3) << 2) +#define VDPU_REG_BD_REF_PIC_PRED_TAP_6_4(x) (((x) & 0x3) << 0) +#define VDPU_REG_BD_REF_PIC_QUANT_DELTA_2(x) (((x) & 0x1f) << 27) +#define VDPU_REG_BD_REF_PIC_QUANT_DELTA_3(x) (((x) & 0x1f) << 22) +#define VDPU_REG_BD_REF_PIC_QUANT_2(x) (((x) & 0x7ff) << 11) +#define VDPU_REG_BD_REF_PIC_QUANT_3(x) (((x) & 0x7ff) << 0) +#define VDPU_REG_BD_P_REF_PIC 0x0bc +#define VDPU_REG_BD_P_REF_PIC_QUANT_DELTA_4(x) (((x) & 0x1f) << 27) +#define VDPU_REG_BD_P_REF_PIC_PINIT_RLIST_F3(x) (((x) & 0x1f) << 25) +#define VDPU_REG_BD_P_REF_PIC_PINIT_RLIST_F2(x) (((x) & 0x1f) << 20) +#define VDPU_REG_BD_P_REF_PIC_PINIT_RLIST_F1(x) (((x) & 0x1f) << 15) +#define VDPU_REG_BD_P_REF_PIC_PINIT_RLIST_F0(x) (((x) & 0x1f) << 10) +#define VDPU_REG_BD_P_REF_PIC_BINIT_RLIST_B15(x) (((x) & 0x1f) << 5) +#define VDPU_REG_BD_P_REF_PIC_BINIT_RLIST_F15(x) (((x) & 0x1f) << 0) +#define VDPU_REG_ERR_CONC 0x0c0 +#define VDPU_REG_ERR_CONC_STARTMB_X(x) (((x) & 0x1ff) << 23) +#define VDPU_REG_ERR_CONC_STARTMB_Y(x) (((x) & 0xff) << 15) +#define VDPU_REG_PRED_FLT 0x0c4 +#define VDPU_REG_PRED_FLT_PRED_BC_TAP_0_0(x) (((x) & 0x3ff) << 22) +#define VDPU_REG_PRED_FLT_PRED_BC_TAP_0_1(x) (((x) & 0x3ff) << 12) +#define VDPU_REG_PRED_FLT_PRED_BC_TAP_0_2(x) (((x) & 0x3ff) << 2) +#define VDPU_REG_REF_BUF_CTRL 0x0cc +#define VDPU_REG_REF_BUF_CTRL_REFBU_E BIT(31) +#define VDPU_REG_REF_BUF_CTRL_REFBU_THR(x) (((x) & 0xfff) << 19) +#define VDPU_REG_REF_BUF_CTRL_REFBU_PICID(x) (((x) & 0x1f) << 14) +#define VDPU_REG_REF_BUF_CTRL_REFBU_EVAL_E BIT(13) +#define VDPU_REG_REF_BUF_CTRL_REFBU_FPARMOD_E BIT(12) +#define VDPU_REG_REF_BUF_CTRL_REFBU_Y_OFFSET(x) (((x) & 0x1ff) << 0) +#define VDPU_REG_REF_BUF_CTRL2 0x0dc +#define VDPU_REG_REF_BUF_CTRL2_REFBU2_BUF_E BIT(31) +#define VDPU_REG_REF_BUF_CTRL2_REFBU2_THR(x) (((x) & 0xfff) << 19) +#define VDPU_REG_REF_BUF_CTRL2_REFBU2_PICID(x) (((x) & 0x1f) << 14) +#define VDPU_REG_REF_BUF_CTRL2_APF_THRESHOLD(x) (((x) & 0x3fff) << 0) + +#endif /* RK3288_VPU_REGS_H_ */ diff --git a/drivers/staging/media/rockchip/vpu/rk3399_vpu_hw.c b/drivers/staging/media/rockchip/vpu/rk3399_vpu_hw.c new file mode 100644 index 000000000000..6fdef61e2127 --- /dev/null +++ b/drivers/staging/media/rockchip/vpu/rk3399_vpu_hw.c @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Rockchip VPU codec driver + * + * Copyright (C) 2018 Rockchip Electronics Co., Ltd. + * Jeffy Chen <jeffy.chen@rock-chips.com> + */ + +#include <linux/clk.h> + +#include "rockchip_vpu.h" +#include "rockchip_vpu_jpeg.h" +#include "rk3399_vpu_regs.h" + +#define RK3399_ACLK_MAX_FREQ (400 * 1000 * 1000) + +/* + * Supported formats. + */ + +static const struct rockchip_vpu_fmt rk3399_vpu_enc_fmts[] = { + { + .fourcc = V4L2_PIX_FMT_YUV420M, + .codec_mode = RK_VPU_MODE_NONE, + .enc_fmt = RK3288_VPU_ENC_FMT_YUV420P, + }, + { + .fourcc = V4L2_PIX_FMT_NV12M, + .codec_mode = RK_VPU_MODE_NONE, + .enc_fmt = RK3288_VPU_ENC_FMT_YUV420SP, + }, + { + .fourcc = V4L2_PIX_FMT_YUYV, + .codec_mode = RK_VPU_MODE_NONE, + .enc_fmt = RK3288_VPU_ENC_FMT_YUYV422, + }, + { + .fourcc = V4L2_PIX_FMT_UYVY, + .codec_mode = RK_VPU_MODE_NONE, + .enc_fmt = RK3288_VPU_ENC_FMT_UYVY422, + }, + { + .fourcc = V4L2_PIX_FMT_JPEG, + .codec_mode = RK_VPU_MODE_JPEG_ENC, + .max_depth = 2, + .header_size = JPEG_HEADER_SIZE, + .frmsize = { + .min_width = 96, + .max_width = 8192, + .step_width = JPEG_MB_DIM, + .min_height = 32, + .max_height = 8192, + .step_height = JPEG_MB_DIM, + }, + }, +}; + +static irqreturn_t rk3399_vepu_irq(int irq, void *dev_id) +{ + struct rockchip_vpu_dev *vpu = dev_id; + enum vb2_buffer_state state; + u32 status, bytesused; + + status = vepu_read(vpu, VEPU_REG_INTERRUPT); + bytesused = vepu_read(vpu, VEPU_REG_STR_BUF_LIMIT) / 8; + state = (status & VEPU_REG_INTERRUPT_FRAME_READY) ? + VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR; + + vepu_write(vpu, 0, VEPU_REG_INTERRUPT); + vepu_write(vpu, 0, VEPU_REG_AXI_CTRL); + + rockchip_vpu_irq_done(vpu, bytesused, state); + + return IRQ_HANDLED; +} + +static int rk3399_vpu_hw_init(struct rockchip_vpu_dev *vpu) +{ + /* Bump ACLK to max. possible freq. to improve performance. */ + clk_set_rate(vpu->clocks[0].clk, RK3399_ACLK_MAX_FREQ); + return 0; +} + +static void rk3399_vpu_enc_reset(struct rockchip_vpu_ctx *ctx) +{ + struct rockchip_vpu_dev *vpu = ctx->dev; + + vepu_write(vpu, VEPU_REG_INTERRUPT_DIS_BIT, VEPU_REG_INTERRUPT); + vepu_write(vpu, 0, VEPU_REG_ENCODE_START); + vepu_write(vpu, 0, VEPU_REG_AXI_CTRL); +} + +/* + * Supported codec ops. + */ + +static const struct rockchip_vpu_codec_ops rk3399_vpu_codec_ops[] = { + [RK_VPU_MODE_JPEG_ENC] = { + .run = rk3399_vpu_jpeg_enc_run, + .reset = rk3399_vpu_enc_reset, + }, +}; + +/* + * VPU variant. + */ + +const struct rockchip_vpu_variant rk3399_vpu_variant = { + .enc_offset = 0x0, + .enc_fmts = rk3399_vpu_enc_fmts, + .num_enc_fmts = ARRAY_SIZE(rk3399_vpu_enc_fmts), + .codec = RK_VPU_CODEC_JPEG, + .codec_ops = rk3399_vpu_codec_ops, + .vepu_irq = rk3399_vepu_irq, + .init = rk3399_vpu_hw_init, + .clk_names = {"aclk", "hclk"}, + .num_clocks = 2 +}; diff --git a/drivers/staging/media/rockchip/vpu/rk3399_vpu_hw_jpeg_enc.c b/drivers/staging/media/rockchip/vpu/rk3399_vpu_hw_jpeg_enc.c new file mode 100644 index 000000000000..dbc86d95fe3b --- /dev/null +++ b/drivers/staging/media/rockchip/vpu/rk3399_vpu_hw_jpeg_enc.c @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Rockchip VPU codec driver + * + * Copyright (C) 2018 Rockchip Electronics Co., Ltd. + * + * JPEG encoder + * ------------ + * The VPU JPEG encoder produces JPEG baseline sequential format. + * The quantization coefficients are 8-bit values, complying with + * the baseline specification. Therefore, it requires + * luma and chroma quantization tables. The hardware does entropy + * encoding using internal Huffman tables, as specified in the JPEG + * specification. + * + * In other words, only the luma and chroma quantization tables are + * required for the encoding operation. + * + * Quantization luma table values are written to registers + * VEPU_swreg_0-VEPU_swreg_15, and chroma table values to + * VEPU_swreg_16-VEPU_swreg_31. + * + * JPEG zigzag order is expected on the quantization tables. + */ + +#include <asm/unaligned.h> +#include <media/v4l2-mem2mem.h> +#include "rockchip_vpu_jpeg.h" +#include "rockchip_vpu.h" +#include "rockchip_vpu_common.h" +#include "rockchip_vpu_hw.h" +#include "rk3399_vpu_regs.h" + +#define VEPU_JPEG_QUANT_TABLE_COUNT 16 + +static void rk3399_vpu_set_src_img_ctrl(struct rockchip_vpu_dev *vpu, + struct rockchip_vpu_ctx *ctx) +{ + struct v4l2_pix_format_mplane *pix_fmt = &ctx->src_fmt; + u32 reg; + + /* + * The pix fmt width/height are already macroblock aligned + * by .vidioc_s_fmt_vid_cap_mplane() callback + */ + reg = VEPU_REG_IN_IMG_CTRL_ROW_LEN(pix_fmt->width); + vepu_write_relaxed(vpu, reg, VEPU_REG_INPUT_LUMA_INFO); + + reg = VEPU_REG_IN_IMG_CTRL_OVRFLR_D4(0) | + VEPU_REG_IN_IMG_CTRL_OVRFLB(0); + /* + * This register controls the input crop, as the offset + * from the right/bottom within the last macroblock. The offset from the + * right must be divided by 4 and so the crop must be aligned to 4 pixels + * horizontally. + */ + vepu_write_relaxed(vpu, reg, VEPU_REG_ENC_OVER_FILL_STRM_OFFSET); + + reg = VEPU_REG_IN_IMG_CTRL_FMT(ctx->vpu_src_fmt->enc_fmt); + vepu_write_relaxed(vpu, reg, VEPU_REG_ENC_CTRL1); +} + +static void rk3399_vpu_jpeg_enc_set_buffers(struct rockchip_vpu_dev *vpu, + struct rockchip_vpu_ctx *ctx, + struct vb2_buffer *src_buf) +{ + struct v4l2_pix_format_mplane *pix_fmt = &ctx->src_fmt; + dma_addr_t src[3]; + + WARN_ON(pix_fmt->num_planes > 3); + + vepu_write_relaxed(vpu, ctx->bounce_dma_addr, + VEPU_REG_ADDR_OUTPUT_STREAM); + vepu_write_relaxed(vpu, ctx->bounce_size, + VEPU_REG_STR_BUF_LIMIT); + + if (pix_fmt->num_planes == 1) { + src[0] = vb2_dma_contig_plane_dma_addr(src_buf, 0); + vepu_write_relaxed(vpu, src[0], VEPU_REG_ADDR_IN_PLANE_0); + } else if (pix_fmt->num_planes == 2) { + src[0] = vb2_dma_contig_plane_dma_addr(src_buf, 0); + src[1] = vb2_dma_contig_plane_dma_addr(src_buf, 1); + vepu_write_relaxed(vpu, src[0], VEPU_REG_ADDR_IN_PLANE_0); + vepu_write_relaxed(vpu, src[1], VEPU_REG_ADDR_IN_PLANE_1); + } else { + src[0] = vb2_dma_contig_plane_dma_addr(src_buf, 0); + src[1] = vb2_dma_contig_plane_dma_addr(src_buf, 1); + src[2] = vb2_dma_contig_plane_dma_addr(src_buf, 2); + vepu_write_relaxed(vpu, src[0], VEPU_REG_ADDR_IN_PLANE_0); + vepu_write_relaxed(vpu, src[1], VEPU_REG_ADDR_IN_PLANE_1); + vepu_write_relaxed(vpu, src[2], VEPU_REG_ADDR_IN_PLANE_2); + } +} + +static void +rk3399_vpu_jpeg_enc_set_qtable(struct rockchip_vpu_dev *vpu, + unsigned char *luma_qtable, + unsigned char *chroma_qtable) +{ + u32 reg, i; + + for (i = 0; i < VEPU_JPEG_QUANT_TABLE_COUNT; i++) { + reg = get_unaligned_be32(&luma_qtable[i]); + vepu_write_relaxed(vpu, reg, VEPU_REG_JPEG_LUMA_QUAT(i)); + + reg = get_unaligned_be32(&chroma_qtable[i]); + vepu_write_relaxed(vpu, reg, VEPU_REG_JPEG_CHROMA_QUAT(i)); + } +} + +void rk3399_vpu_jpeg_enc_run(struct rockchip_vpu_ctx *ctx) +{ + struct rockchip_vpu_dev *vpu = ctx->dev; + struct vb2_buffer *src_buf, *dst_buf; + struct rockchip_vpu_jpeg_ctx jpeg_ctx; + u32 reg; + + src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); + dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx); + + memset(&jpeg_ctx, 0, sizeof(jpeg_ctx)); + jpeg_ctx.buffer = vb2_plane_vaddr(dst_buf, 0); + jpeg_ctx.width = ctx->dst_fmt.width; + jpeg_ctx.height = ctx->dst_fmt.height; + jpeg_ctx.quality = ctx->jpeg_quality; + rockchip_vpu_jpeg_header_assemble(&jpeg_ctx); + + /* Switch to JPEG encoder mode before writing registers */ + vepu_write_relaxed(vpu, VEPU_REG_ENCODE_FORMAT_JPEG, + VEPU_REG_ENCODE_START); + + rk3399_vpu_set_src_img_ctrl(vpu, ctx); + rk3399_vpu_jpeg_enc_set_buffers(vpu, ctx, src_buf); + rk3399_vpu_jpeg_enc_set_qtable(vpu, + rockchip_vpu_jpeg_get_qtable(&jpeg_ctx, 0), + rockchip_vpu_jpeg_get_qtable(&jpeg_ctx, 1)); + + reg = VEPU_REG_OUTPUT_SWAP32 + | VEPU_REG_OUTPUT_SWAP16 + | VEPU_REG_OUTPUT_SWAP8 + | VEPU_REG_INPUT_SWAP8 + | VEPU_REG_INPUT_SWAP16 + | VEPU_REG_INPUT_SWAP32; + /* Make sure that all registers are written at this point. */ + vepu_write(vpu, reg, VEPU_REG_DATA_ENDIAN); + + reg = VEPU_REG_AXI_CTRL_BURST_LEN(16); + vepu_write_relaxed(vpu, reg, VEPU_REG_AXI_CTRL); + + reg = VEPU_REG_MB_WIDTH(JPEG_MB_WIDTH(ctx->src_fmt.width)) + | VEPU_REG_MB_HEIGHT(JPEG_MB_HEIGHT(ctx->src_fmt.height)) + | VEPU_REG_FRAME_TYPE_INTRA + | VEPU_REG_ENCODE_FORMAT_JPEG + | VEPU_REG_ENCODE_ENABLE; + + /* Kick the watchdog and start encoding */ + schedule_delayed_work(&vpu->watchdog_work, msecs_to_jiffies(2000)); + vepu_write(vpu, reg, VEPU_REG_ENCODE_START); +} diff --git a/drivers/staging/media/rockchip/vpu/rk3399_vpu_regs.h b/drivers/staging/media/rockchip/vpu/rk3399_vpu_regs.h new file mode 100644 index 000000000000..fbe294177ec9 --- /dev/null +++ b/drivers/staging/media/rockchip/vpu/rk3399_vpu_regs.h @@ -0,0 +1,600 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Rockchip VPU codec driver + * + * Copyright (C) 2018 Rockchip Electronics Co., Ltd. + * Alpha Lin <alpha.lin@rock-chips.com> + */ + +#ifndef RK3399_VPU_REGS_H_ +#define RK3399_VPU_REGS_H_ + +/* Encoder registers. */ +#define VEPU_REG_VP8_QUT_1ST(i) (0x000 + ((i) * 0x24)) +#define VEPU_REG_VP8_QUT_DC_Y2(x) (((x) & 0x3fff) << 16) +#define VEPU_REG_VP8_QUT_DC_Y1(x) (((x) & 0x3fff) << 0) +#define VEPU_REG_VP8_QUT_2ND(i) (0x004 + ((i) * 0x24)) +#define VEPU_REG_VP8_QUT_AC_Y1(x) (((x) & 0x3fff) << 16) +#define VEPU_REG_VP8_QUT_DC_CHR(x) (((x) & 0x3fff) << 0) +#define VEPU_REG_VP8_QUT_3RD(i) (0x008 + ((i) * 0x24)) +#define VEPU_REG_VP8_QUT_AC_CHR(x) (((x) & 0x3fff) << 16) +#define VEPU_REG_VP8_QUT_AC_Y2(x) (((x) & 0x3fff) << 0) +#define VEPU_REG_VP8_QUT_4TH(i) (0x00c + ((i) * 0x24)) +#define VEPU_REG_VP8_QUT_ZB_DC_CHR(x) (((x) & 0x1ff) << 18) +#define VEPU_REG_VP8_QUT_ZB_DC_Y2(x) (((x) & 0x1ff) << 9) +#define VEPU_REG_VP8_QUT_ZB_DC_Y1(x) (((x) & 0x1ff) << 0) +#define VEPU_REG_VP8_QUT_5TH(i) (0x010 + ((i) * 0x24)) +#define VEPU_REG_VP8_QUT_ZB_AC_CHR(x) (((x) & 0x1ff) << 18) +#define VEPU_REG_VP8_QUT_ZB_AC_Y2(x) (((x) & 0x1ff) << 9) +#define VEPU_REG_VP8_QUT_ZB_AC_Y1(x) (((x) & 0x1ff) << 0) +#define VEPU_REG_VP8_QUT_6TH(i) (0x014 + ((i) * 0x24)) +#define VEPU_REG_VP8_QUT_RND_DC_CHR(x) (((x) & 0xff) << 16) +#define VEPU_REG_VP8_QUT_RND_DC_Y2(x) (((x) & 0xff) << 8) +#define VEPU_REG_VP8_QUT_RND_DC_Y1(x) (((x) & 0xff) << 0) +#define VEPU_REG_VP8_QUT_7TH(i) (0x018 + ((i) * 0x24)) +#define VEPU_REG_VP8_QUT_RND_AC_CHR(x) (((x) & 0xff) << 16) +#define VEPU_REG_VP8_QUT_RND_AC_Y2(x) (((x) & 0xff) << 8) +#define VEPU_REG_VP8_QUT_RND_AC_Y1(x) (((x) & 0xff) << 0) +#define VEPU_REG_VP8_QUT_8TH(i) (0x01c + ((i) * 0x24)) +#define VEPU_REG_VP8_SEG_FILTER_LEVEL(x) (((x) & 0x3f) << 25) +#define VEPU_REG_VP8_DEQUT_DC_CHR(x) (((x) & 0xff) << 17) +#define VEPU_REG_VP8_DEQUT_DC_Y2(x) (((x) & 0x1ff) << 8) +#define VEPU_REG_VP8_DEQUT_DC_Y1(x) (((x) & 0xff) << 0) +#define VEPU_REG_VP8_QUT_9TH(i) (0x020 + ((i) * 0x24)) +#define VEPU_REG_VP8_DEQUT_AC_CHR(x) (((x) & 0x1ff) << 18) +#define VEPU_REG_VP8_DEQUT_AC_Y2(x) (((x) & 0x1ff) << 9) +#define VEPU_REG_VP8_DEQUT_AC_Y1(x) (((x) & 0x1ff) << 0) +#define VEPU_REG_ADDR_VP8_SEG_MAP 0x06c +#define VEPU_REG_VP8_INTRA_4X4_PENALTY(i) (0x070 + ((i) * 0x4)) +#define VEPU_REG_VP8_INTRA_4X4_PENALTY_0(x) (((x) & 0xfff) << 0) +#define VEPU_REG_VP8_INTRA_4x4_PENALTY_1(x) (((x) & 0xfff) << 16) +#define VEPU_REG_VP8_INTRA_16X16_PENALTY(i) (0x084 + ((i) * 0x4)) +#define VEPU_REG_VP8_INTRA_16X16_PENALTY_0(x) (((x) & 0xfff) << 0) +#define VEPU_REG_VP8_INTRA_16X16_PENALTY_1(x) (((x) & 0xfff) << 16) +#define VEPU_REG_VP8_CONTROL 0x0a0 +#define VEPU_REG_VP8_LF_MODE_DELTA_BPRED(x) (((x) & 0x1f) << 24) +#define VEPU_REG_VP8_LF_REF_DELTA_INTRA_MB(x) (((x) & 0x7f) << 16) +#define VEPU_REG_VP8_INTER_TYPE_BIT_COST(x) (((x) & 0xfff) << 0) +#define VEPU_REG_VP8_REF_FRAME_VAL 0x0a4 +#define VEPU_REG_VP8_COEF_DMV_PENALTY(x) (((x) & 0xfff) << 16) +#define VEPU_REG_VP8_REF_FRAME(x) (((x) & 0xfff) << 0) +#define VEPU_REG_VP8_LOOP_FILTER_REF_DELTA 0x0a8 +#define VEPU_REG_VP8_LF_REF_DELTA_ALT_REF(x) (((x) & 0x7f) << 16) +#define VEPU_REG_VP8_LF_REF_DELTA_LAST_REF(x) (((x) & 0x7f) << 8) +#define VEPU_REG_VP8_LF_REF_DELTA_GOLDEN(x) (((x) & 0x7f) << 0) +#define VEPU_REG_VP8_LOOP_FILTER_MODE_DELTA 0x0ac +#define VEPU_REG_VP8_LF_MODE_DELTA_SPLITMV(x) (((x) & 0x7f) << 16) +#define VEPU_REG_VP8_LF_MODE_DELTA_ZEROMV(x) (((x) & 0x7f) << 8) +#define VEPU_REG_VP8_LF_MODE_DELTA_NEWMV(x) (((x) & 0x7f) << 0) +#define VEPU_REG_JPEG_LUMA_QUAT(i) (0x000 + ((i) * 0x4)) +#define VEPU_REG_JPEG_CHROMA_QUAT(i) (0x040 + ((i) * 0x4)) +#define VEPU_REG_INTRA_SLICE_BITMAP(i) (0x0b0 + ((i) * 0x4)) +#define VEPU_REG_ADDR_VP8_DCT_PART(i) (0x0b0 + ((i) * 0x4)) +#define VEPU_REG_INTRA_AREA_CTRL 0x0b8 +#define VEPU_REG_INTRA_AREA_TOP(x) (((x) & 0xff) << 24) +#define VEPU_REG_INTRA_AREA_BOTTOM(x) (((x) & 0xff) << 16) +#define VEPU_REG_INTRA_AREA_LEFT(x) (((x) & 0xff) << 8) +#define VEPU_REG_INTRA_AREA_RIGHT(x) (((x) & 0xff) << 0) +#define VEPU_REG_CIR_INTRA_CTRL 0x0bc +#define VEPU_REG_CIR_INTRA_FIRST_MB(x) (((x) & 0xffff) << 16) +#define VEPU_REG_CIR_INTRA_INTERVAL(x) (((x) & 0xffff) << 0) +#define VEPU_REG_ADDR_IN_PLANE_0 0x0c0 +#define VEPU_REG_ADDR_IN_PLANE_1 0x0c4 +#define VEPU_REG_ADDR_IN_PLANE_2 0x0c8 +#define VEPU_REG_STR_HDR_REM_MSB 0x0cc +#define VEPU_REG_STR_HDR_REM_LSB 0x0d0 +#define VEPU_REG_STR_BUF_LIMIT 0x0d4 +#define VEPU_REG_AXI_CTRL 0x0d8 +#define VEPU_REG_AXI_CTRL_READ_ID(x) (((x) & 0xff) << 24) +#define VEPU_REG_AXI_CTRL_WRITE_ID(x) (((x) & 0xff) << 16) +#define VEPU_REG_AXI_CTRL_BURST_LEN(x) (((x) & 0x3f) << 8) +#define VEPU_REG_AXI_CTRL_INCREMENT_MODE(x) (((x) & 0x01) << 2) +#define VEPU_REG_AXI_CTRL_BIRST_DISCARD(x) (((x) & 0x01) << 1) +#define VEPU_REG_AXI_CTRL_BIRST_DISABLE BIT(0) +#define VEPU_QP_ADJUST_MAD_DELTA_ROI 0x0dc +#define VEPU_REG_ROI_QP_DELTA_1 (((x) & 0xf) << 12) +#define VEPU_REG_ROI_QP_DELTA_2 (((x) & 0xf) << 8) +#define VEPU_REG_MAD_QP_ADJUSTMENT (((x) & 0xf) << 0) +#define VEPU_REG_ADDR_REF_LUMA 0x0e0 +#define VEPU_REG_ADDR_REF_CHROMA 0x0e4 +#define VEPU_REG_QP_SUM_DIV2 0x0e8 +#define VEPU_REG_QP_SUM(x) (((x) & 0x001fffff) * 2) +#define VEPU_REG_ENC_CTRL0 0x0ec +#define VEPU_REG_DISABLE_QUARTER_PIXEL_MV BIT(28) +#define VEPU_REG_DEBLOCKING_FILTER_MODE(x) (((x) & 0x3) << 24) +#define VEPU_REG_CABAC_INIT_IDC(x) (((x) & 0x3) << 21) +#define VEPU_REG_ENTROPY_CODING_MODE BIT(20) +#define VEPU_REG_H264_TRANS8X8_MODE BIT(17) +#define VEPU_REG_H264_INTER4X4_MODE BIT(16) +#define VEPU_REG_H264_STREAM_MODE BIT(15) +#define VEPU_REG_H264_SLICE_SIZE(x) (((x) & 0x7f) << 8) +#define VEPU_REG_ENC_OVER_FILL_STRM_OFFSET 0x0f0 +#define VEPU_REG_STREAM_START_OFFSET(x) (((x) & 0x3f) << 16) +#define VEPU_REG_SKIP_MACROBLOCK_PENALTY(x) (((x) & 0xff) << 8) +#define VEPU_REG_IN_IMG_CTRL_OVRFLR_D4(x) (((x) & 0x3) << 4) +#define VEPU_REG_IN_IMG_CTRL_OVRFLB(x) (((x) & 0xf) << 0) +#define VEPU_REG_INPUT_LUMA_INFO 0x0f4 +#define VEPU_REG_IN_IMG_CHROMA_OFFSET(x) (((x) & 0x7) << 20) +#define VEPU_REG_IN_IMG_LUMA_OFFSET(x) (((x) & 0x7) << 16) +#define VEPU_REG_IN_IMG_CTRL_ROW_LEN(x) (((x) & 0x3fff) << 0) +#define VEPU_REG_RLC_SUM 0x0f8 +#define VEPU_REG_RLC_SUM_OUT(x) (((x) & 0x007fffff) * 4) +#define VEPU_REG_SPLIT_PENALTY_4X4 0x0f8 +#define VEPU_REG_VP8_SPLIT_PENALTY_4X4 (((x) & 0x1ff) << 19) +#define VEPU_REG_ADDR_REC_LUMA 0x0fc +#define VEPU_REG_ADDR_REC_CHROMA 0x100 +#define VEPU_REG_CHECKPOINT(i) (0x104 + ((i) * 0x4)) +#define VEPU_REG_CHECKPOINT_CHECK0(x) (((x) & 0xffff)) +#define VEPU_REG_CHECKPOINT_CHECK1(x) (((x) & 0xffff) << 16) +#define VEPU_REG_CHECKPOINT_RESULT(x) \ + ((((x) >> (16 - 16 * ((i) & 1))) & 0xffff) * 32) +#define VEPU_REG_VP8_SEG0_QUANT_AC_Y1 0x104 +#define VEPU_REG_VP8_SEG0_RND_AC_Y1(x) (((x) & 0xff) << 23) +#define VEPU_REG_VP8_SEG0_ZBIN_AC_Y1(x) (((x) & 0x1ff) << 14) +#define VEPU_REG_VP8_SEG0_QUT_AC_Y1(x) (((x) & 0x3fff) << 0) +#define VEPU_REG_VP8_SEG0_QUANT_DC_Y2 0x108 +#define VEPU_REG_VP8_SEG0_RND_DC_Y2(x) (((x) & 0xff) << 23) +#define VEPU_REG_VP8_SEG0_ZBIN_DC_Y2(x) (((x) & 0x1ff) << 14) +#define VEPU_REG_VP8_SEG0_QUT_DC_Y2(x) (((x) & 0x3fff) << 0) +#define VEPU_REG_VP8_SEG0_QUANT_AC_Y2 0x10c +#define VEPU_REG_VP8_SEG0_RND_AC_Y2(x) (((x) & 0xff) << 23) +#define VEPU_REG_VP8_SEG0_ZBIN_AC_Y2(x) (((x) & 0x1ff) << 14) +#define VEPU_REG_VP8_SEG0_QUT_AC_Y2(x) (((x) & 0x3fff) << 0) +#define VEPU_REG_VP8_SEG0_QUANT_DC_CHR 0x110 +#define VEPU_REG_VP8_SEG0_RND_DC_CHR(x) (((x) & 0xff) << 23) +#define VEPU_REG_VP8_SEG0_ZBIN_DC_CHR(x) (((x) & 0x1ff) << 14) +#define VEPU_REG_VP8_SEG0_QUT_DC_CHR(x) (((x) & 0x3fff) << 0) +#define VEPU_REG_VP8_SEG0_QUANT_AC_CHR 0x114 +#define VEPU_REG_VP8_SEG0_RND_AC_CHR(x) (((x) & 0xff) << 23) +#define VEPU_REG_VP8_SEG0_ZBIN_AC_CHR(x) (((x) & 0x1ff) << 14) +#define VEPU_REG_VP8_SEG0_QUT_AC_CHR(x) (((x) & 0x3fff) << 0) +#define VEPU_REG_VP8_SEG0_QUANT_DQUT 0x118 +#define VEPU_REG_VP8_MV_REF_IDX1(x) (((x) & 0x03) << 26) +#define VEPU_REG_VP8_SEG0_DQUT_DC_Y2(x) (((x) & 0x1ff) << 17) +#define VEPU_REG_VP8_SEG0_DQUT_AC_Y1(x) (((x) & 0x1ff) << 8) +#define VEPU_REG_VP8_SEG0_DQUT_DC_Y1(x) (((x) & 0xff) << 0) +#define VEPU_REG_CHKPT_WORD_ERR(i) (0x118 + ((i) * 0x4)) +#define VEPU_REG_CHKPT_WORD_ERR_CHK0(x) (((x) & 0xffff)) +#define VEPU_REG_CHKPT_WORD_ERR_CHK1(x) (((x) & 0xffff) << 16) +#define VEPU_REG_VP8_SEG0_QUANT_DQUT_1 0x11c +#define VEPU_REG_VP8_SEGMENT_MAP_UPDATE BIT(30) +#define VEPU_REG_VP8_SEGMENT_EN BIT(29) +#define VEPU_REG_VP8_MV_REF_IDX2_EN BIT(28) +#define VEPU_REG_VP8_MV_REF_IDX2(x) (((x) & 0x03) << 26) +#define VEPU_REG_VP8_SEG0_DQUT_AC_CHR(x) (((x) & 0x1ff) << 17) +#define VEPU_REG_VP8_SEG0_DQUT_DC_CHR(x) (((x) & 0xff) << 9) +#define VEPU_REG_VP8_SEG0_DQUT_AC_Y2(x) (((x) & 0x1ff) << 0) +#define VEPU_REG_VP8_BOOL_ENC_VALUE 0x120 +#define VEPU_REG_CHKPT_DELTA_QP 0x124 +#define VEPU_REG_CHKPT_DELTA_QP_CHK0(x) (((x) & 0x0f) << 0) +#define VEPU_REG_CHKPT_DELTA_QP_CHK1(x) (((x) & 0x0f) << 4) +#define VEPU_REG_CHKPT_DELTA_QP_CHK2(x) (((x) & 0x0f) << 8) +#define VEPU_REG_CHKPT_DELTA_QP_CHK3(x) (((x) & 0x0f) << 12) +#define VEPU_REG_CHKPT_DELTA_QP_CHK4(x) (((x) & 0x0f) << 16) +#define VEPU_REG_CHKPT_DELTA_QP_CHK5(x) (((x) & 0x0f) << 20) +#define VEPU_REG_CHKPT_DELTA_QP_CHK6(x) (((x) & 0x0f) << 24) +#define VEPU_REG_VP8_ENC_CTRL2 0x124 +#define VEPU_REG_VP8_ZERO_MV_PENALTY_FOR_REF2(x) (((x) & 0xff) << 24) +#define VEPU_REG_VP8_FILTER_SHARPNESS(x) (((x) & 0x07) << 21) +#define VEPU_REG_VP8_FILTER_LEVEL(x) (((x) & 0x3f) << 15) +#define VEPU_REG_VP8_DCT_PARTITION_CNT(x) (((x) & 0x03) << 13) +#define VEPU_REG_VP8_BOOL_ENC_VALUE_BITS(x) (((x) & 0x1f) << 8) +#define VEPU_REG_VP8_BOOL_ENC_RANGE(x) (((x) & 0xff) << 0) +#define VEPU_REG_ENC_CTRL1 0x128 +#define VEPU_REG_MAD_THRESHOLD(x) (((x) & 0x3f) << 24) +#define VEPU_REG_COMPLETED_SLICES(x) (((x) & 0xff) << 16) +#define VEPU_REG_IN_IMG_CTRL_FMT(x) (((x) & 0xf) << 4) +#define VEPU_REG_IN_IMG_ROTATE_MODE(x) (((x) & 0x3) << 2) +#define VEPU_REG_SIZE_TABLE_PRESENT BIT(0) +#define VEPU_REG_INTRA_INTER_MODE 0x12c +#define VEPU_REG_INTRA16X16_MODE(x) (((x) & 0xffff) << 16) +#define VEPU_REG_INTER_MODE(x) (((x) & 0xffff) << 0) +#define VEPU_REG_ENC_CTRL2 0x130 +#define VEPU_REG_PPS_INIT_QP(x) (((x) & 0x3f) << 26) +#define VEPU_REG_SLICE_FILTER_ALPHA(x) (((x) & 0xf) << 22) +#define VEPU_REG_SLICE_FILTER_BETA(x) (((x) & 0xf) << 18) +#define VEPU_REG_CHROMA_QP_OFFSET(x) (((x) & 0x1f) << 13) +#define VEPU_REG_FILTER_DISABLE BIT(5) +#define VEPU_REG_IDR_PIC_ID(x) (((x) & 0xf) << 1) +#define VEPU_REG_CONSTRAINED_INTRA_PREDICTION BIT(0) +#define VEPU_REG_ADDR_OUTPUT_STREAM 0x134 +#define VEPU_REG_ADDR_OUTPUT_CTRL 0x138 +#define VEPU_REG_ADDR_NEXT_PIC 0x13c +#define VEPU_REG_ADDR_MV_OUT 0x140 +#define VEPU_REG_ADDR_CABAC_TBL 0x144 +#define VEPU_REG_ROI1 0x148 +#define VEPU_REG_ROI1_TOP_MB(x) (((x) & 0xff) << 24) +#define VEPU_REG_ROI1_BOTTOM_MB(x) (((x) & 0xff) << 16) +#define VEPU_REG_ROI1_LEFT_MB(x) (((x) & 0xff) << 8) +#define VEPU_REG_ROI1_RIGHT_MB(x) (((x) & 0xff) << 0) +#define VEPU_REG_ROI2 0x14c +#define VEPU_REG_ROI2_TOP_MB(x) (((x) & 0xff) << 24) +#define VEPU_REG_ROI2_BOTTOM_MB(x) (((x) & 0xff) << 16) +#define VEPU_REG_ROI2_LEFT_MB(x) (((x) & 0xff) << 8) +#define VEPU_REG_ROI2_RIGHT_MB(x) (((x) & 0xff) << 0) +#define VEPU_REG_STABLE_MATRIX(i) (0x150 + ((i) * 0x4)) +#define VEPU_REG_STABLE_MOTION_SUM 0x174 +#define VEPU_REG_STABILIZATION_OUTPUT 0x178 +#define VEPU_REG_STABLE_MIN_VALUE(x) (((x) & 0xffffff) << 8) +#define VEPU_REG_STABLE_MODE_SEL(x) (((x) & 0x3) << 6) +#define VEPU_REG_STABLE_HOR_GMV(x) (((x) & 0x3f) << 0) +#define VEPU_REG_RGB2YUV_CONVERSION_COEF1 0x17c +#define VEPU_REG_RGB2YUV_CONVERSION_COEFB(x) (((x) & 0xffff) << 16) +#define VEPU_REG_RGB2YUV_CONVERSION_COEFA(x) (((x) & 0xffff) << 0) +#define VEPU_REG_RGB2YUV_CONVERSION_COEF2 0x180 +#define VEPU_REG_RGB2YUV_CONVERSION_COEFE(x) (((x) & 0xffff) << 16) +#define VEPU_REG_RGB2YUV_CONVERSION_COEFC(x) (((x) & 0xffff) << 0) +#define VEPU_REG_RGB2YUV_CONVERSION_COEF3 0x184 +#define VEPU_REG_RGB2YUV_CONVERSION_COEFF(x) (((x) & 0xffff) << 0) +#define VEPU_REG_RGB_MASK_MSB 0x188 +#define VEPU_REG_RGB_MASK_B_MSB(x) (((x) & 0x1f) << 16) +#define VEPU_REG_RGB_MASK_G_MSB(x) (((x) & 0x1f) << 8) +#define VEPU_REG_RGB_MASK_R_MSB(x) (((x) & 0x1f) << 0) +#define VEPU_REG_MV_PENALTY 0x18c +#define VEPU_REG_1MV_PENALTY(x) (((x) & 0x3ff) << 21) +#define VEPU_REG_QMV_PENALTY(x) (((x) & 0x3ff) << 11) +#define VEPU_REG_4MV_PENALTY(x) (((x) & 0x3ff) << 1) +#define VEPU_REG_SPLIT_MV_MODE_EN BIT(0) +#define VEPU_REG_QP_VAL 0x190 +#define VEPU_REG_H264_LUMA_INIT_QP(x) (((x) & 0x3f) << 26) +#define VEPU_REG_H264_QP_MAX(x) (((x) & 0x3f) << 20) +#define VEPU_REG_H264_QP_MIN(x) (((x) & 0x3f) << 14) +#define VEPU_REG_H264_CHKPT_DISTANCE(x) (((x) & 0xfff) << 0) +#define VEPU_REG_VP8_SEG0_QUANT_DC_Y1 0x190 +#define VEPU_REG_VP8_SEG0_RND_DC_Y1(x) (((x) & 0xff) << 23) +#define VEPU_REG_VP8_SEG0_ZBIN_DC_Y1(x) (((x) & 0x1ff) << 14) +#define VEPU_REG_VP8_SEG0_QUT_DC_Y1(x) (((x) & 0x3fff) << 0) +#define VEPU_REG_MVC_RELATE 0x198 +#define VEPU_REG_ZERO_MV_FAVOR_D2(x) (((x) & 0xf) << 20) +#define VEPU_REG_PENALTY_4X4MV(x) (((x) & 0x1ff) << 11) +#define VEPU_REG_MVC_VIEW_ID(x) (((x) & 0x7) << 8) +#define VEPU_REG_MVC_ANCHOR_PIC_FLAG BIT(7) +#define VEPU_REG_MVC_PRIORITY_ID(x) (((x) & 0x7) << 4) +#define VEPU_REG_MVC_TEMPORAL_ID(x) (((x) & 0x7) << 1) +#define VEPU_REG_MVC_INTER_VIEW_FLAG BIT(0) +#define VEPU_REG_ENCODE_START 0x19c +#define VEPU_REG_MB_HEIGHT(x) (((x) & 0x1ff) << 20) +#define VEPU_REG_MB_WIDTH(x) (((x) & 0x1ff) << 8) +#define VEPU_REG_FRAME_TYPE_INTER (0x0 << 6) +#define VEPU_REG_FRAME_TYPE_INTRA (0x1 << 6) +#define VEPU_REG_FRAME_TYPE_MVCINTER (0x2 << 6) +#define VEPU_REG_ENCODE_FORMAT_JPEG (0x2 << 4) +#define VEPU_REG_ENCODE_FORMAT_H264 (0x3 << 4) +#define VEPU_REG_ENCODE_ENABLE BIT(0) +#define VEPU_REG_MB_CTRL 0x1a0 +#define VEPU_REG_MB_CNT_OUT(x) (((x) & 0xffff) << 16) +#define VEPU_REG_MB_CNT_SET(x) (((x) & 0xffff) << 0) +#define VEPU_REG_DATA_ENDIAN 0x1a4 +#define VEPU_REG_INPUT_SWAP8 BIT(31) +#define VEPU_REG_INPUT_SWAP16 BIT(30) +#define VEPU_REG_INPUT_SWAP32 BIT(29) +#define VEPU_REG_OUTPUT_SWAP8 BIT(28) +#define VEPU_REG_OUTPUT_SWAP16 BIT(27) +#define VEPU_REG_OUTPUT_SWAP32 BIT(26) +#define VEPU_REG_TEST_IRQ BIT(24) +#define VEPU_REG_TEST_COUNTER(x) (((x) & 0xf) << 20) +#define VEPU_REG_TEST_REG BIT(19) +#define VEPU_REG_TEST_MEMORY BIT(18) +#define VEPU_REG_TEST_LEN(x) (((x) & 0x3ffff) << 0) +#define VEPU_REG_ENC_CTRL3 0x1a8 +#define VEPU_REG_PPS_ID(x) (((x) & 0xff) << 24) +#define VEPU_REG_INTRA_PRED_MODE(x) (((x) & 0xff) << 16) +#define VEPU_REG_FRAME_NUM(x) (((x) & 0xffff) << 0) +#define VEPU_REG_ENC_CTRL4 0x1ac +#define VEPU_REG_MV_PENALTY_16X8_8X16(x) (((x) & 0x3ff) << 20) +#define VEPU_REG_MV_PENALTY_8X8(x) (((x) & 0x3ff) << 10) +#define VEPU_REG_MV_PENALTY_8X4_4X8(x) (((x) & 0x3ff) << 0) +#define VEPU_REG_ADDR_VP8_PROB_CNT 0x1b0 +#define VEPU_REG_INTERRUPT 0x1b4 +#define VEPU_REG_INTERRUPT_NON BIT(28) +#define VEPU_REG_MV_WRITE_EN BIT(24) +#define VEPU_REG_RECON_WRITE_DIS BIT(20) +#define VEPU_REG_INTERRUPT_SLICE_READY_EN BIT(16) +#define VEPU_REG_CLK_GATING_EN BIT(12) +#define VEPU_REG_INTERRUPT_TIMEOUT_EN BIT(10) +#define VEPU_REG_INTERRUPT_RESET BIT(9) +#define VEPU_REG_INTERRUPT_DIS_BIT BIT(8) +#define VEPU_REG_INTERRUPT_TIMEOUT BIT(6) +#define VEPU_REG_INTERRUPT_BUFFER_FULL BIT(5) +#define VEPU_REG_INTERRUPT_BUS_ERROR BIT(4) +#define VEPU_REG_INTERRUPT_FUSE BIT(3) +#define VEPU_REG_INTERRUPT_SLICE_READY BIT(2) +#define VEPU_REG_INTERRUPT_FRAME_READY BIT(1) +#define VEPU_REG_INTERRUPT_BIT BIT(0) +#define VEPU_REG_DMV_PENALTY_TBL(i) (0x1E0 + ((i) * 0x4)) +#define VEPU_REG_DMV_PENALTY_TABLE_BIT(x, i) ((x) << (i) * 8) +#define VEPU_REG_DMV_Q_PIXEL_PENALTY_TBL(i) (0x260 + ((i) * 0x4)) +#define VEPU_REG_DMV_Q_PIXEL_PENALTY_TABLE_BIT(x, i) ((x) << (i) * 8) + +/* vpu decoder register */ +#define VDPU_REG_DEC_CTRL0 0x0c8 // 50 +#define VDPU_REG_REF_BUF_CTRL2_REFBU2_PICID(x) (((x) & 0x1f) << 25) +#define VDPU_REG_REF_BUF_CTRL2_REFBU2_THR(x) (((x) & 0xfff) << 13) +#define VDPU_REG_CONFIG_TILED_MODE_LSB BIT(12) +#define VDPU_REG_CONFIG_DEC_ADV_PRE_DIS BIT(11) +#define VDPU_REG_CONFIG_DEC_SCMD_DIS BIT(10) +#define VDPU_REG_DEC_CTRL0_SKIP_MODE BIT(9) +#define VDPU_REG_DEC_CTRL0_FILTERING_DIS BIT(8) +#define VDPU_REG_DEC_CTRL0_PIC_FIXED_QUANT BIT(7) +#define VDPU_REG_CONFIG_DEC_LATENCY(x) (((x) & 0x3f) << 1) +#define VDPU_REG_CONFIG_TILED_MODE_MSB(x) BIT(0) +#define VDPU_REG_CONFIG_DEC_OUT_TILED_E BIT(0) +#define VDPU_REG_STREAM_LEN 0x0cc +#define VDPU_REG_DEC_CTRL3_INIT_QP(x) (((x) & 0x3f) << 25) +#define VDPU_REG_DEC_STREAM_LEN_HI BIT(24) +#define VDPU_REG_DEC_CTRL3_STREAM_LEN(x) (((x) & 0xffffff) << 0) +#define VDPU_REG_ERROR_CONCEALMENT 0x0d0 +#define VDPU_REG_REF_BUF_CTRL2_APF_THRESHOLD(x) (((x) & 0x3fff) << 17) +#define VDPU_REG_ERR_CONC_STARTMB_X(x) (((x) & 0x1ff) << 8) +#define VDPU_REG_ERR_CONC_STARTMB_Y(x) (((x) & 0xff) << 0) +#define VDPU_REG_DEC_FORMAT 0x0d4 +#define VDPU_REG_DEC_CTRL0_DEC_MODE(x) (((x) & 0xf) << 0) +#define VDPU_REG_DATA_ENDIAN 0x0d8 +#define VDPU_REG_CONFIG_DEC_STRENDIAN_E BIT(5) +#define VDPU_REG_CONFIG_DEC_STRSWAP32_E BIT(4) +#define VDPU_REG_CONFIG_DEC_OUTSWAP32_E BIT(3) +#define VDPU_REG_CONFIG_DEC_INSWAP32_E BIT(2) +#define VDPU_REG_CONFIG_DEC_OUT_ENDIAN BIT(1) +#define VDPU_REG_CONFIG_DEC_IN_ENDIAN BIT(0) +#define VDPU_REG_INTERRUPT 0x0dc +#define VDPU_REG_INTERRUPT_DEC_TIMEOUT BIT(13) +#define VDPU_REG_INTERRUPT_DEC_ERROR_INT BIT(12) +#define VDPU_REG_INTERRUPT_DEC_PIC_INF BIT(10) +#define VDPU_REG_INTERRUPT_DEC_SLICE_INT BIT(9) +#define VDPU_REG_INTERRUPT_DEC_ASO_INT BIT(8) +#define VDPU_REG_INTERRUPT_DEC_BUFFER_INT BIT(6) +#define VDPU_REG_INTERRUPT_DEC_BUS_INT BIT(5) +#define VDPU_REG_INTERRUPT_DEC_RDY_INT BIT(4) +#define VDPU_REG_INTERRUPT_DEC_IRQ_DIS BIT(1) +#define VDPU_REG_INTERRUPT_DEC_IRQ BIT(0) +#define VDPU_REG_AXI_CTRL 0x0e0 +#define VDPU_REG_AXI_DEC_SEL BIT(23) +#define VDPU_REG_CONFIG_DEC_DATA_DISC_E BIT(22) +#define VDPU_REG_PARAL_BUS_E(x) BIT(21) +#define VDPU_REG_CONFIG_DEC_MAX_BURST(x) (((x) & 0x1f) << 16) +#define VDPU_REG_DEC_CTRL0_DEC_AXI_WR_ID(x) (((x) & 0xff) << 8) +#define VDPU_REG_CONFIG_DEC_AXI_RD_ID(x) (((x) & 0xff) << 0) +#define VDPU_REG_EN_FLAGS 0x0e4 +#define VDPU_REG_AHB_HLOCK_E BIT(31) +#define VDPU_REG_CACHE_E BIT(29) +#define VDPU_REG_PREFETCH_SINGLE_CHANNEL_E BIT(28) +#define VDPU_REG_INTRA_3_CYCLE_ENHANCE BIT(27) +#define VDPU_REG_INTRA_DOUBLE_SPEED BIT(26) +#define VDPU_REG_INTER_DOUBLE_SPEED BIT(25) +#define VDPU_REG_DEC_CTRL3_START_CODE_E BIT(22) +#define VDPU_REG_DEC_CTRL3_CH_8PIX_ILEAV_E BIT(21) +#define VDPU_REG_DEC_CTRL0_RLC_MODE_E BIT(20) +#define VDPU_REG_DEC_CTRL0_DIVX3_E BIT(19) +#define VDPU_REG_DEC_CTRL0_PJPEG_E BIT(18) +#define VDPU_REG_DEC_CTRL0_PIC_INTERLACE_E BIT(17) +#define VDPU_REG_DEC_CTRL0_PIC_FIELDMODE_E BIT(16) +#define VDPU_REG_DEC_CTRL0_PIC_B_E BIT(15) +#define VDPU_REG_DEC_CTRL0_PIC_INTER_E BIT(14) +#define VDPU_REG_DEC_CTRL0_PIC_TOPFIELD_E BIT(13) +#define VDPU_REG_DEC_CTRL0_FWD_INTERLACE_E BIT(12) +#define VDPU_REG_DEC_CTRL0_SORENSON_E BIT(11) +#define VDPU_REG_DEC_CTRL0_WRITE_MVS_E BIT(10) +#define VDPU_REG_DEC_CTRL0_REF_TOPFIELD_E BIT(9) +#define VDPU_REG_DEC_CTRL0_REFTOPFIRST_E BIT(8) +#define VDPU_REG_DEC_CTRL0_SEQ_MBAFF_E BIT(7) +#define VDPU_REG_DEC_CTRL0_PICORD_COUNT_E BIT(6) +#define VDPU_REG_CONFIG_DEC_TIMEOUT_E BIT(5) +#define VDPU_REG_CONFIG_DEC_CLK_GATE_E BIT(4) +#define VDPU_REG_DEC_CTRL0_DEC_OUT_DIS BIT(2) +#define VDPU_REG_REF_BUF_CTRL2_REFBU2_BUF_E BIT(1) +#define VDPU_REG_INTERRUPT_DEC_E BIT(0) +#define VDPU_REG_SOFT_RESET 0x0e8 +#define VDPU_REG_PRED_FLT 0x0ec +#define VDPU_REG_PRED_FLT_PRED_BC_TAP_0_0(x) (((x) & 0x3ff) << 22) +#define VDPU_REG_PRED_FLT_PRED_BC_TAP_0_1(x) (((x) & 0x3ff) << 12) +#define VDPU_REG_PRED_FLT_PRED_BC_TAP_0_2(x) (((x) & 0x3ff) << 2) +#define VDPU_REG_ADDITIONAL_CHROMA_ADDRESS 0x0f0 +#define VDPU_REG_ADDR_QTABLE 0x0f4 +#define VDPU_REG_DIRECT_MV_ADDR 0x0f8 +#define VDPU_REG_ADDR_DST 0x0fc +#define VDPU_REG_ADDR_STR 0x100 +#define VDPU_REG_REFBUF_RELATED 0x104 +#define VDPU_REG_FWD_PIC(i) (0x128 + ((i) * 0x4)) +#define VDPU_REG_FWD_PIC_PINIT_RLIST_F5(x) (((x) & 0x1f) << 25) +#define VDPU_REG_FWD_PIC_PINIT_RLIST_F4(x) (((x) & 0x1f) << 20) +#define VDPU_REG_FWD_PIC_PINIT_RLIST_F3(x) (((x) & 0x1f) << 15) +#define VDPU_REG_FWD_PIC_PINIT_RLIST_F2(x) (((x) & 0x1f) << 10) +#define VDPU_REG_FWD_PIC_PINIT_RLIST_F1(x) (((x) & 0x1f) << 5) +#define VDPU_REG_FWD_PIC_PINIT_RLIST_F0(x) (((x) & 0x1f) << 0) +#define VDPU_REG_REF_PIC(i) (0x130 + ((i) * 0x4)) +#define VDPU_REG_REF_PIC_REFER1_NBR(x) (((x) & 0xffff) << 16) +#define VDPU_REG_REF_PIC_REFER0_NBR(x) (((x) & 0xffff) << 0) +#define VDPU_REG_H264_ADDR_REF(i) (0x150 + ((i) * 0x4)) +#define VDPU_REG_ADDR_REF_FIELD_E BIT(1) +#define VDPU_REG_ADDR_REF_TOPC_E BIT(0) +#define VDPU_REG_INITIAL_REF_PIC_LIST0 0x190 +#define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F5(x) (((x) & 0x1f) << 25) +#define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F4(x) (((x) & 0x1f) << 20) +#define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F3(x) (((x) & 0x1f) << 15) +#define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F2(x) (((x) & 0x1f) << 10) +#define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F1(x) (((x) & 0x1f) << 5) +#define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F0(x) (((x) & 0x1f) << 0) +#define VDPU_REG_INITIAL_REF_PIC_LIST1 0x194 +#define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F11(x) (((x) & 0x1f) << 25) +#define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F10(x) (((x) & 0x1f) << 20) +#define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F9(x) (((x) & 0x1f) << 15) +#define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F8(x) (((x) & 0x1f) << 10) +#define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F7(x) (((x) & 0x1f) << 5) +#define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F6(x) (((x) & 0x1f) << 0) +#define VDPU_REG_INITIAL_REF_PIC_LIST2 0x198 +#define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F15(x) (((x) & 0x1f) << 15) +#define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F14(x) (((x) & 0x1f) << 10) +#define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F13(x) (((x) & 0x1f) << 5) +#define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F12(x) (((x) & 0x1f) << 0) +#define VDPU_REG_INITIAL_REF_PIC_LIST3 0x19c +#define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B5(x) (((x) & 0x1f) << 25) +#define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B4(x) (((x) & 0x1f) << 20) +#define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B3(x) (((x) & 0x1f) << 15) +#define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B2(x) (((x) & 0x1f) << 10) +#define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B1(x) (((x) & 0x1f) << 5) +#define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B0(x) (((x) & 0x1f) << 0) +#define VDPU_REG_INITIAL_REF_PIC_LIST4 0x1a0 +#define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B11(x) (((x) & 0x1f) << 25) +#define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B10(x) (((x) & 0x1f) << 20) +#define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B9(x) (((x) & 0x1f) << 15) +#define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B8(x) (((x) & 0x1f) << 10) +#define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B7(x) (((x) & 0x1f) << 5) +#define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B6(x) (((x) & 0x1f) << 0) +#define VDPU_REG_INITIAL_REF_PIC_LIST5 0x1a4 +#define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B15(x) (((x) & 0x1f) << 15) +#define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B14(x) (((x) & 0x1f) << 10) +#define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B13(x) (((x) & 0x1f) << 5) +#define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B12(x) (((x) & 0x1f) << 0) +#define VDPU_REG_INITIAL_REF_PIC_LIST6 0x1a8 +#define VDPU_REG_BD_P_REF_PIC_PINIT_RLIST_F3(x) (((x) & 0x1f) << 15) +#define VDPU_REG_BD_P_REF_PIC_PINIT_RLIST_F2(x) (((x) & 0x1f) << 10) +#define VDPU_REG_BD_P_REF_PIC_PINIT_RLIST_F1(x) (((x) & 0x1f) << 5) +#define VDPU_REG_BD_P_REF_PIC_PINIT_RLIST_F0(x) (((x) & 0x1f) << 0) +#define VDPU_REG_LT_REF 0x1ac +#define VDPU_REG_VALID_REF 0x1b0 +#define VDPU_REG_H264_PIC_MB_SIZE 0x1b8 +#define VDPU_REG_DEC_CTRL2_CH_QP_OFFSET2(x) (((x) & 0x1f) << 22) +#define VDPU_REG_DEC_CTRL2_CH_QP_OFFSET(x) (((x) & 0x1f) << 17) +#define VDPU_REG_DEC_CTRL1_PIC_MB_HEIGHT_P(x) (((x) & 0xff) << 9) +#define VDPU_REG_DEC_CTRL1_PIC_MB_WIDTH(x) (((x) & 0x1ff) << 0) +#define VDPU_REG_H264_CTRL 0x1bc +#define VDPU_REG_DEC_CTRL4_WEIGHT_BIPR_IDC(x) (((x) & 0x3) << 16) +#define VDPU_REG_DEC_CTRL1_REF_FRAMES(x) (((x) & 0x1f) << 0) +#define VDPU_REG_CURRENT_FRAME 0x1c0 +#define VDPU_REG_DEC_CTRL5_FILT_CTRL_PRES BIT(31) +#define VDPU_REG_DEC_CTRL5_RDPIC_CNT_PRES BIT(30) +#define VDPU_REG_DEC_CTRL4_FRAMENUM_LEN(x) (((x) & 0x1f) << 16) +#define VDPU_REG_DEC_CTRL4_FRAMENUM(x) (((x) & 0xffff) << 0) +#define VDPU_REG_REF_FRAME 0x1c4 +#define VDPU_REG_DEC_CTRL5_REFPIC_MK_LEN(x) (((x) & 0x7ff) << 16) +#define VDPU_REG_DEC_CTRL5_IDR_PIC_ID(x) (((x) & 0xffff) << 0) +#define VDPU_REG_DEC_CTRL6 0x1c8 +#define VDPU_REG_DEC_CTRL6_PPS_ID(x) (((x) & 0xff) << 24) +#define VDPU_REG_DEC_CTRL6_REFIDX1_ACTIVE(x) (((x) & 0x1f) << 19) +#define VDPU_REG_DEC_CTRL6_REFIDX0_ACTIVE(x) (((x) & 0x1f) << 14) +#define VDPU_REG_DEC_CTRL6_POC_LENGTH(x) (((x) & 0xff) << 0) +#define VDPU_REG_ENABLE_FLAG 0x1cc +#define VDPU_REG_DEC_CTRL5_IDR_PIC_E BIT(8) +#define VDPU_REG_DEC_CTRL4_DIR_8X8_INFER_E BIT(7) +#define VDPU_REG_DEC_CTRL4_BLACKWHITE_E BIT(6) +#define VDPU_REG_DEC_CTRL4_CABAC_E BIT(5) +#define VDPU_REG_DEC_CTRL4_WEIGHT_PRED_E BIT(4) +#define VDPU_REG_DEC_CTRL5_CONST_INTRA_E BIT(3) +#define VDPU_REG_DEC_CTRL5_8X8TRANS_FLAG_E BIT(2) +#define VDPU_REG_DEC_CTRL2_TYPE1_QUANT_E BIT(1) +#define VDPU_REG_DEC_CTRL2_FIELDPIC_FLAG_E BIT(0) +#define VDPU_REG_VP8_PIC_MB_SIZE 0x1e0 +#define VDPU_REG_DEC_PIC_MB_WIDTH(x) (((x) & 0x1ff) << 23) +#define VDPU_REG_DEC_MB_WIDTH_OFF(x) (((x) & 0xf) << 19) +#define VDPU_REG_DEC_PIC_MB_HEIGHT_P(x) (((x) & 0xff) << 11) +#define VDPU_REG_DEC_MB_HEIGHT_OFF(x) (((x) & 0xf) << 7) +#define VDPU_REG_DEC_CTRL1_PIC_MB_W_EXT(x) (((x) & 0x7) << 3) +#define VDPU_REG_DEC_CTRL1_PIC_MB_H_EXT(x) (((x) & 0x7) << 0) +#define VDPU_REG_VP8_DCT_START_BIT 0x1e4 +#define VDPU_REG_DEC_CTRL4_DCT1_START_BIT(x) (((x) & 0x3f) << 26) +#define VDPU_REG_DEC_CTRL4_DCT2_START_BIT(x) (((x) & 0x3f) << 20) +#define VDPU_REG_DEC_CTRL4_VC1_HEIGHT_EXT BIT(13) +#define VDPU_REG_DEC_CTRL4_BILIN_MC_E BIT(12) +#define VDPU_REG_VP8_CTRL0 0x1e8 +#define VDPU_REG_DEC_CTRL2_STRM_START_BIT(x) (((x) & 0x3f) << 26) +#define VDPU_REG_DEC_CTRL2_STRM1_START_BIT(x) (((x) & 0x3f) << 18) +#define VDPU_REG_DEC_CTRL2_BOOLEAN_VALUE(x) (((x) & 0xff) << 8) +#define VDPU_REG_DEC_CTRL2_BOOLEAN_RANGE(x) (((x) & 0xff) << 0) +#define VDPU_REG_VP8_DATA_VAL 0x1f0 +#define VDPU_REG_DEC_CTRL6_COEFFS_PART_AM(x) (((x) & 0xf) << 24) +#define VDPU_REG_DEC_CTRL6_STREAM1_LEN(x) (((x) & 0xffffff) << 0) +#define VDPU_REG_PRED_FLT7 0x1f4 +#define VDPU_REG_PRED_FLT_PRED_BC_TAP_5_1(x) (((x) & 0x3ff) << 22) +#define VDPU_REG_PRED_FLT_PRED_BC_TAP_5_2(x) (((x) & 0x3ff) << 12) +#define VDPU_REG_PRED_FLT_PRED_BC_TAP_5_3(x) (((x) & 0x3ff) << 2) +#define VDPU_REG_PRED_FLT8 0x1f8 +#define VDPU_REG_PRED_FLT_PRED_BC_TAP_6_0(x) (((x) & 0x3ff) << 22) +#define VDPU_REG_PRED_FLT_PRED_BC_TAP_6_1(x) (((x) & 0x3ff) << 12) +#define VDPU_REG_PRED_FLT_PRED_BC_TAP_6_2(x) (((x) & 0x3ff) << 2) +#define VDPU_REG_PRED_FLT9 0x1fc +#define VDPU_REG_PRED_FLT_PRED_BC_TAP_6_3(x) (((x) & 0x3ff) << 22) +#define VDPU_REG_PRED_FLT_PRED_BC_TAP_7_0(x) (((x) & 0x3ff) << 12) +#define VDPU_REG_PRED_FLT_PRED_BC_TAP_7_1(x) (((x) & 0x3ff) << 2) +#define VDPU_REG_PRED_FLT10 0x200 +#define VDPU_REG_PRED_FLT_PRED_BC_TAP_7_2(x) (((x) & 0x3ff) << 22) +#define VDPU_REG_PRED_FLT_PRED_BC_TAP_7_3(x) (((x) & 0x3ff) << 12) +#define VDPU_REG_BD_REF_PIC_PRED_TAP_2_M1(x) (((x) & 0x3) << 10) +#define VDPU_REG_BD_REF_PIC_PRED_TAP_2_4(x) (((x) & 0x3) << 8) +#define VDPU_REG_BD_REF_PIC_PRED_TAP_4_M1(x) (((x) & 0x3) << 6) +#define VDPU_REG_BD_REF_PIC_PRED_TAP_4_4(x) (((x) & 0x3) << 4) +#define VDPU_REG_BD_REF_PIC_PRED_TAP_6_M1(x) (((x) & 0x3) << 2) +#define VDPU_REG_BD_REF_PIC_PRED_TAP_6_4(x) (((x) & 0x3) << 0) +#define VDPU_REG_FILTER_LEVEL 0x204 +#define VDPU_REG_REF_PIC_LF_LEVEL_0(x) (((x) & 0x3f) << 18) +#define VDPU_REG_REF_PIC_LF_LEVEL_1(x) (((x) & 0x3f) << 12) +#define VDPU_REG_REF_PIC_LF_LEVEL_2(x) (((x) & 0x3f) << 6) +#define VDPU_REG_REF_PIC_LF_LEVEL_3(x) (((x) & 0x3f) << 0) +#define VDPU_REG_VP8_QUANTER0 0x208 +#define VDPU_REG_REF_PIC_QUANT_DELTA_0(x) (((x) & 0x1f) << 27) +#define VDPU_REG_REF_PIC_QUANT_DELTA_1(x) (((x) & 0x1f) << 22) +#define VDPU_REG_REF_PIC_QUANT_0(x) (((x) & 0x7ff) << 11) +#define VDPU_REG_REF_PIC_QUANT_1(x) (((x) & 0x7ff) << 0) +#define VDPU_REG_VP8_ADDR_REF0 0x20c +#define VDPU_REG_FILTER_MB_ADJ 0x210 +#define VDPU_REG_REF_PIC_FILT_TYPE_E BIT(31) +#define VDPU_REG_REF_PIC_FILT_SHARPNESS(x) (((x) & 0x7) << 28) +#define VDPU_REG_FILT_MB_ADJ_0(x) (((x) & 0x7f) << 21) +#define VDPU_REG_FILT_MB_ADJ_1(x) (((x) & 0x7f) << 14) +#define VDPU_REG_FILT_MB_ADJ_2(x) (((x) & 0x7f) << 7) +#define VDPU_REG_FILT_MB_ADJ_3(x) (((x) & 0x7f) << 0) +#define VDPU_REG_FILTER_REF_ADJ 0x214 +#define VDPU_REG_REF_PIC_ADJ_0(x) (((x) & 0x7f) << 21) +#define VDPU_REG_REF_PIC_ADJ_1(x) (((x) & 0x7f) << 14) +#define VDPU_REG_REF_PIC_ADJ_2(x) (((x) & 0x7f) << 7) +#define VDPU_REG_REF_PIC_ADJ_3(x) (((x) & 0x7f) << 0) +#define VDPU_REG_VP8_ADDR_REF2_5(i) (0x218 + ((i) * 0x4)) +#define VDPU_REG_VP8_GREF_SIGN_BIAS BIT(0) +#define VDPU_REG_VP8_AREF_SIGN_BIAS BIT(0) +#define VDPU_REG_VP8_DCT_BASE(i) (0x230 + ((i) * 0x4)) +#define VDPU_REG_VP8_ADDR_CTRL_PART 0x244 +#define VDPU_REG_VP8_ADDR_REF1 0x250 +#define VDPU_REG_VP8_SEGMENT_VAL 0x254 +#define VDPU_REG_FWD_PIC1_SEGMENT_BASE(x) ((x) << 0) +#define VDPU_REG_FWD_PIC1_SEGMENT_UPD_E BIT(1) +#define VDPU_REG_FWD_PIC1_SEGMENT_E BIT(0) +#define VDPU_REG_VP8_DCT_START_BIT2 0x258 +#define VDPU_REG_DEC_CTRL7_DCT3_START_BIT(x) (((x) & 0x3f) << 24) +#define VDPU_REG_DEC_CTRL7_DCT4_START_BIT(x) (((x) & 0x3f) << 18) +#define VDPU_REG_DEC_CTRL7_DCT5_START_BIT(x) (((x) & 0x3f) << 12) +#define VDPU_REG_DEC_CTRL7_DCT6_START_BIT(x) (((x) & 0x3f) << 6) +#define VDPU_REG_DEC_CTRL7_DCT7_START_BIT(x) (((x) & 0x3f) << 0) +#define VDPU_REG_VP8_QUANTER1 0x25c +#define VDPU_REG_REF_PIC_QUANT_DELTA_2(x) (((x) & 0x1f) << 27) +#define VDPU_REG_REF_PIC_QUANT_DELTA_3(x) (((x) & 0x1f) << 22) +#define VDPU_REG_REF_PIC_QUANT_2(x) (((x) & 0x7ff) << 11) +#define VDPU_REG_REF_PIC_QUANT_3(x) (((x) & 0x7ff) << 0) +#define VDPU_REG_VP8_QUANTER2 0x260 +#define VDPU_REG_REF_PIC_QUANT_DELTA_4(x) (((x) & 0x1f) << 27) +#define VDPU_REG_REF_PIC_QUANT_4(x) (((x) & 0x7ff) << 11) +#define VDPU_REG_REF_PIC_QUANT_5(x) (((x) & 0x7ff) << 0) +#define VDPU_REG_PRED_FLT1 0x264 +#define VDPU_REG_PRED_FLT_PRED_BC_TAP_0_3(x) (((x) & 0x3ff) << 22) +#define VDPU_REG_PRED_FLT_PRED_BC_TAP_1_0(x) (((x) & 0x3ff) << 12) +#define VDPU_REG_PRED_FLT_PRED_BC_TAP_1_1(x) (((x) & 0x3ff) << 2) +#define VDPU_REG_PRED_FLT2 0x268 +#define VDPU_REG_PRED_FLT_PRED_BC_TAP_1_2(x) (((x) & 0x3ff) << 22) +#define VDPU_REG_PRED_FLT_PRED_BC_TAP_1_3(x) (((x) & 0x3ff) << 12) +#define VDPU_REG_PRED_FLT_PRED_BC_TAP_2_0(x) (((x) & 0x3ff) << 2) +#define VDPU_REG_PRED_FLT3 0x26c +#define VDPU_REG_PRED_FLT_PRED_BC_TAP_2_1(x) (((x) & 0x3ff) << 22) +#define VDPU_REG_PRED_FLT_PRED_BC_TAP_2_2(x) (((x) & 0x3ff) << 12) +#define VDPU_REG_PRED_FLT_PRED_BC_TAP_2_3(x) (((x) & 0x3ff) << 2) +#define VDPU_REG_PRED_FLT4 0x270 +#define VDPU_REG_PRED_FLT_PRED_BC_TAP_3_0(x) (((x) & 0x3ff) << 22) +#define VDPU_REG_PRED_FLT_PRED_BC_TAP_3_1(x) (((x) & 0x3ff) << 12) +#define VDPU_REG_PRED_FLT_PRED_BC_TAP_3_2(x) (((x) & 0x3ff) << 2) +#define VDPU_REG_PRED_FLT5 0x274 +#define VDPU_REG_PRED_FLT_PRED_BC_TAP_3_3(x) (((x) & 0x3ff) << 22) +#define VDPU_REG_PRED_FLT_PRED_BC_TAP_4_0(x) (((x) & 0x3ff) << 12) +#define VDPU_REG_PRED_FLT_PRED_BC_TAP_4_1(x) (((x) & 0x3ff) << 2) +#define VDPU_REG_PRED_FLT6 0x278 +#define VDPU_REG_PRED_FLT_PRED_BC_TAP_4_2(x) (((x) & 0x3ff) << 22) +#define VDPU_REG_PRED_FLT_PRED_BC_TAP_4_3(x) (((x) & 0x3ff) << 12) +#define VDPU_REG_PRED_FLT_PRED_BC_TAP_5_0(x) (((x) & 0x3ff) << 2) + +#endif /* RK3399_VPU_REGS_H_ */ diff --git a/drivers/staging/media/rockchip/vpu/rockchip_vpu.h b/drivers/staging/media/rockchip/vpu/rockchip_vpu.h new file mode 100644 index 000000000000..1ec2be483e27 --- /dev/null +++ b/drivers/staging/media/rockchip/vpu/rockchip_vpu.h @@ -0,0 +1,232 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Rockchip VPU codec driver + * + * Copyright 2018 Google LLC. + * Tomasz Figa <tfiga@chromium.org> + * + * Based on s5p-mfc driver by Samsung Electronics Co., Ltd. + * Copyright (C) 2011 Samsung Electronics Co., Ltd. + */ + +#ifndef ROCKCHIP_VPU_H_ +#define ROCKCHIP_VPU_H_ + +#include <linux/platform_device.h> +#include <linux/videodev2.h> +#include <linux/wait.h> +#include <linux/clk.h> + +#include <media/v4l2-ctrls.h> +#include <media/v4l2-device.h> +#include <media/v4l2-ioctl.h> +#include <media/videobuf2-core.h> +#include <media/videobuf2-dma-contig.h> + +#include "rockchip_vpu_hw.h" + +#define ROCKCHIP_VPU_MAX_CLOCKS 4 + +#define JPEG_MB_DIM 16 +#define JPEG_MB_WIDTH(w) DIV_ROUND_UP(w, JPEG_MB_DIM) +#define JPEG_MB_HEIGHT(h) DIV_ROUND_UP(h, JPEG_MB_DIM) + +struct rockchip_vpu_ctx; +struct rockchip_vpu_codec_ops; + +#define RK_VPU_CODEC_JPEG BIT(0) + +/** + * struct rockchip_vpu_variant - information about VPU hardware variant + * + * @enc_offset: Offset from VPU base to encoder registers. + * @enc_fmts: Encoder formats. + * @num_enc_fmts: Number of encoder formats. + * @codec: Supported codecs + * @codec_ops: Codec ops. + * @init: Initialize hardware. + * @vepu_irq: encoder interrupt handler + * @clk_names: array of clock names + * @num_clocks: number of clocks in the array + */ +struct rockchip_vpu_variant { + unsigned int enc_offset; + const struct rockchip_vpu_fmt *enc_fmts; + unsigned int num_enc_fmts; + unsigned int codec; + const struct rockchip_vpu_codec_ops *codec_ops; + int (*init)(struct rockchip_vpu_dev *vpu); + irqreturn_t (*vepu_irq)(int irq, void *priv); + const char *clk_names[ROCKCHIP_VPU_MAX_CLOCKS]; + int num_clocks; +}; + +/** + * enum rockchip_vpu_codec_mode - codec operating mode. + * @RK_VPU_MODE_NONE: No operating mode. Used for RAW video formats. + * @RK_VPU_MODE_JPEG_ENC: JPEG encoder. + */ +enum rockchip_vpu_codec_mode { + RK_VPU_MODE_NONE = -1, + RK_VPU_MODE_JPEG_ENC, +}; + +/** + * struct rockchip_vpu_dev - driver data + * @v4l2_dev: V4L2 device to register video devices for. + * @m2m_dev: mem2mem device associated to this device. + * @mdev: media device associated to this device. + * @vfd_enc: Video device for encoder. + * @pdev: Pointer to VPU platform device. + * @dev: Pointer to device for convenient logging using + * dev_ macros. + * @clocks: Array of clock handles. + * @base: Mapped address of VPU registers. + * @enc_base: Mapped address of VPU encoder register for convenience. + * @vpu_mutex: Mutex to synchronize V4L2 calls. + * @irqlock: Spinlock to synchronize access to data structures + * shared with interrupt handlers. + * @variant: Hardware variant-specific parameters. + * @watchdog_work: Delayed work for hardware timeout handling. + */ +struct rockchip_vpu_dev { + struct v4l2_device v4l2_dev; + struct v4l2_m2m_dev *m2m_dev; + struct media_device mdev; + struct video_device *vfd_enc; + struct platform_device *pdev; + struct device *dev; + struct clk_bulk_data clocks[ROCKCHIP_VPU_MAX_CLOCKS]; + void __iomem *base; + void __iomem *enc_base; + + struct mutex vpu_mutex; /* video_device lock */ + spinlock_t irqlock; + const struct rockchip_vpu_variant *variant; + struct delayed_work watchdog_work; +}; + +/** + * struct rockchip_vpu_ctx - Context (instance) private data. + * + * @dev: VPU driver data to which the context belongs. + * @fh: V4L2 file handler. + * + * @sequence_cap: Sequence counter for capture queue + * @sequence_out: Sequence counter for output queue + * + * @vpu_src_fmt: Descriptor of active source format. + * @src_fmt: V4L2 pixel format of active source format. + * @vpu_dst_fmt: Descriptor of active destination format. + * @dst_fmt: V4L2 pixel format of active destination format. + * + * @ctrl_handler: Control handler used to register controls. + * @jpeg_quality: User-specified JPEG compression quality. + * + * @codec_ops: Set of operations related to codec mode. + * + * @bounce_dma_addr: Bounce buffer bus address. + * @bounce_buf: Bounce buffer pointer. + * @bounce_size: Bounce buffer size. + */ +struct rockchip_vpu_ctx { + struct rockchip_vpu_dev *dev; + struct v4l2_fh fh; + + u32 sequence_cap; + u32 sequence_out; + + const struct rockchip_vpu_fmt *vpu_src_fmt; + struct v4l2_pix_format_mplane src_fmt; + const struct rockchip_vpu_fmt *vpu_dst_fmt; + struct v4l2_pix_format_mplane dst_fmt; + + struct v4l2_ctrl_handler ctrl_handler; + int jpeg_quality; + + const struct rockchip_vpu_codec_ops *codec_ops; + + dma_addr_t bounce_dma_addr; + void *bounce_buf; + size_t bounce_size; +}; + +/** + * struct rockchip_vpu_fmt - information about supported video formats. + * @name: Human readable name of the format. + * @fourcc: FourCC code of the format. See V4L2_PIX_FMT_*. + * @codec_mode: Codec mode related to this format. See + * enum rockchip_vpu_codec_mode. + * @header_size: Optional header size. Currently used by JPEG encoder. + * @max_depth: Maximum depth, for bitstream formats + * @enc_fmt: Format identifier for encoder registers. + * @frmsize: Supported range of frame sizes (only for bitstream formats). + */ +struct rockchip_vpu_fmt { + char *name; + u32 fourcc; + enum rockchip_vpu_codec_mode codec_mode; + int header_size; + int max_depth; + enum rockchip_vpu_enc_fmt enc_fmt; + struct v4l2_frmsize_stepwise frmsize; +}; + +/* Logging helpers */ + +/** + * debug - Module parameter to control level of debugging messages. + * + * Level of debugging messages can be controlled by bits of + * module parameter called "debug". Meaning of particular + * bits is as follows: + * + * bit 0 - global information: mode, size, init, release + * bit 1 - each run start/result information + * bit 2 - contents of small controls from userspace + * bit 3 - contents of big controls from userspace + * bit 4 - detail fmt, ctrl, buffer q/dq information + * bit 5 - detail function enter/leave trace information + * bit 6 - register write/read information + */ +extern int rockchip_vpu_debug; + +#define vpu_debug(level, fmt, args...) \ + do { \ + if (rockchip_vpu_debug & BIT(level)) \ + pr_info("%s:%d: " fmt, \ + __func__, __LINE__, ##args); \ + } while (0) + +#define vpu_err(fmt, args...) \ + pr_err("%s:%d: " fmt, __func__, __LINE__, ##args) + +/* Structure access helpers. */ +static inline struct rockchip_vpu_ctx *fh_to_ctx(struct v4l2_fh *fh) +{ + return container_of(fh, struct rockchip_vpu_ctx, fh); +} + +/* Register accessors. */ +static inline void vepu_write_relaxed(struct rockchip_vpu_dev *vpu, + u32 val, u32 reg) +{ + vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val); + writel_relaxed(val, vpu->enc_base + reg); +} + +static inline void vepu_write(struct rockchip_vpu_dev *vpu, u32 val, u32 reg) +{ + vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val); + writel(val, vpu->enc_base + reg); +} + +static inline u32 vepu_read(struct rockchip_vpu_dev *vpu, u32 reg) +{ + u32 val = readl(vpu->enc_base + reg); + + vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val); + return val; +} + +#endif /* ROCKCHIP_VPU_H_ */ diff --git a/drivers/staging/media/rockchip/vpu/rockchip_vpu_common.h b/drivers/staging/media/rockchip/vpu/rockchip_vpu_common.h new file mode 100644 index 000000000000..ca77668d9579 --- /dev/null +++ b/drivers/staging/media/rockchip/vpu/rockchip_vpu_common.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Rockchip VPU codec driver + * + * Copyright (C) 2018 Rockchip Electronics Co., Ltd. + * Alpha Lin <Alpha.Lin@rock-chips.com> + * Jeffy Chen <jeffy.chen@rock-chips.com> + * + * Copyright 2018 Google LLC. + * Tomasz Figa <tfiga@chromium.org> + * + * Based on s5p-mfc driver by Samsung Electronics Co., Ltd. + * Copyright (C) 2011 Samsung Electronics Co., Ltd. + */ + +#ifndef ROCKCHIP_VPU_COMMON_H_ +#define ROCKCHIP_VPU_COMMON_H_ + +#include "rockchip_vpu.h" + +extern const struct v4l2_ioctl_ops rockchip_vpu_enc_ioctl_ops; +extern const struct vb2_ops rockchip_vpu_enc_queue_ops; + +void rockchip_vpu_enc_reset_src_fmt(struct rockchip_vpu_dev *vpu, + struct rockchip_vpu_ctx *ctx); +void rockchip_vpu_enc_reset_dst_fmt(struct rockchip_vpu_dev *vpu, + struct rockchip_vpu_ctx *ctx); + +#endif /* ROCKCHIP_VPU_COMMON_H_ */ diff --git a/drivers/staging/media/rockchip/vpu/rockchip_vpu_drv.c b/drivers/staging/media/rockchip/vpu/rockchip_vpu_drv.c new file mode 100644 index 000000000000..962412c79b91 --- /dev/null +++ b/drivers/staging/media/rockchip/vpu/rockchip_vpu_drv.c @@ -0,0 +1,537 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Rockchip VPU codec driver + * + * Copyright (C) 2018 Collabora, Ltd. + * Copyright 2018 Google LLC. + * Tomasz Figa <tfiga@chromium.org> + * + * Based on s5p-mfc driver by Samsung Electronics Co., Ltd. + * Copyright (C) 2011 Samsung Electronics Co., Ltd. + */ + +#include <linux/clk.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pm.h> +#include <linux/pm_runtime.h> +#include <linux/slab.h> +#include <linux/videodev2.h> +#include <linux/workqueue.h> +#include <media/v4l2-event.h> +#include <media/v4l2-mem2mem.h> +#include <media/videobuf2-core.h> +#include <media/videobuf2-core.h> +#include <media/videobuf2-vmalloc.h> + +#include "rockchip_vpu_common.h" +#include "rockchip_vpu.h" +#include "rockchip_vpu_hw.h" + +#define DRIVER_NAME "rockchip-vpu" + +int rockchip_vpu_debug; +module_param_named(debug, rockchip_vpu_debug, int, 0644); +MODULE_PARM_DESC(debug, + "Debug level - higher value produces more verbose messages"); + +static void rockchip_vpu_job_finish(struct rockchip_vpu_dev *vpu, + struct rockchip_vpu_ctx *ctx, + unsigned int bytesused, + enum vb2_buffer_state result) +{ + struct vb2_v4l2_buffer *src, *dst; + size_t avail_size; + + pm_runtime_mark_last_busy(vpu->dev); + pm_runtime_put_autosuspend(vpu->dev); + clk_bulk_disable(vpu->variant->num_clocks, vpu->clocks); + + src = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); + dst = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); + + if (WARN_ON(!src)) + return; + if (WARN_ON(!dst)) + return; + + src->sequence = ctx->sequence_out++; + dst->sequence = ctx->sequence_cap++; + + dst->field = src->field; + if (src->flags & V4L2_BUF_FLAG_TIMECODE) + dst->timecode = src->timecode; + dst->vb2_buf.timestamp = src->vb2_buf.timestamp; + dst->flags &= ~(V4L2_BUF_FLAG_TSTAMP_SRC_MASK | + V4L2_BUF_FLAG_TIMECODE); + dst->flags |= src->flags & (V4L2_BUF_FLAG_TSTAMP_SRC_MASK | + V4L2_BUF_FLAG_TIMECODE); + + avail_size = vb2_plane_size(&dst->vb2_buf, 0) - + ctx->vpu_dst_fmt->header_size; + if (bytesused <= avail_size) { + if (ctx->bounce_buf) { + memcpy(vb2_plane_vaddr(&dst->vb2_buf, 0) + + ctx->vpu_dst_fmt->header_size, + ctx->bounce_buf, bytesused); + } + dst->vb2_buf.planes[0].bytesused = + ctx->vpu_dst_fmt->header_size + bytesused; + } else { + result = VB2_BUF_STATE_ERROR; + } + + v4l2_m2m_buf_done(src, result); + v4l2_m2m_buf_done(dst, result); + + v4l2_m2m_job_finish(vpu->m2m_dev, ctx->fh.m2m_ctx); +} + +void rockchip_vpu_irq_done(struct rockchip_vpu_dev *vpu, + unsigned int bytesused, + enum vb2_buffer_state result) +{ + struct rockchip_vpu_ctx *ctx = + v4l2_m2m_get_curr_priv(vpu->m2m_dev); + + /* + * If cancel_delayed_work returns false + * the timeout expired. The watchdog is running, + * and will take care of finishing the job. + */ + if (cancel_delayed_work(&vpu->watchdog_work)) + rockchip_vpu_job_finish(vpu, ctx, bytesused, result); +} + +void rockchip_vpu_watchdog(struct work_struct *work) +{ + struct rockchip_vpu_dev *vpu; + struct rockchip_vpu_ctx *ctx; + + vpu = container_of(to_delayed_work(work), + struct rockchip_vpu_dev, watchdog_work); + ctx = v4l2_m2m_get_curr_priv(vpu->m2m_dev); + if (ctx) { + vpu_err("frame processing timed out!\n"); + ctx->codec_ops->reset(ctx); + rockchip_vpu_job_finish(vpu, ctx, 0, VB2_BUF_STATE_ERROR); + } +} + +static void device_run(void *priv) +{ + struct rockchip_vpu_ctx *ctx = priv; + int ret; + + ret = clk_bulk_enable(ctx->dev->variant->num_clocks, ctx->dev->clocks); + if (ret) + goto err_cancel_job; + ret = pm_runtime_get_sync(ctx->dev->dev); + if (ret < 0) + goto err_cancel_job; + + ctx->codec_ops->run(ctx); + return; + +err_cancel_job: + rockchip_vpu_job_finish(ctx->dev, ctx, 0, VB2_BUF_STATE_ERROR); +} + +static struct v4l2_m2m_ops vpu_m2m_ops = { + .device_run = device_run, +}; + +static int +enc_queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq) +{ + struct rockchip_vpu_ctx *ctx = priv; + int ret; + + src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; + src_vq->io_modes = VB2_MMAP | VB2_DMABUF; + src_vq->drv_priv = ctx; + src_vq->ops = &rockchip_vpu_enc_queue_ops; + src_vq->mem_ops = &vb2_dma_contig_memops; + + /* + * Driver does mostly sequential access, so sacrifice TLB efficiency + * for faster allocation. Also, no CPU access on the source queue, + * so no kernel mapping needed. + */ + src_vq->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES | + DMA_ATTR_NO_KERNEL_MAPPING; + src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); + src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; + src_vq->lock = &ctx->dev->vpu_mutex; + src_vq->dev = ctx->dev->v4l2_dev.dev; + + ret = vb2_queue_init(src_vq); + if (ret) + return ret; + + /* + * The CAPTURE queue doesn't need dma memory, + * as the CPU needs to create the JPEG frames, + * from the hardware-produced JPEG payload. + * + * For the DMA destination buffer, we use + * a bounce buffer. + */ + dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; + dst_vq->io_modes = VB2_MMAP | VB2_DMABUF; + dst_vq->drv_priv = ctx; + dst_vq->ops = &rockchip_vpu_enc_queue_ops; + dst_vq->mem_ops = &vb2_vmalloc_memops; + dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); + dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; + dst_vq->lock = &ctx->dev->vpu_mutex; + dst_vq->dev = ctx->dev->v4l2_dev.dev; + + return vb2_queue_init(dst_vq); +} + +static int rockchip_vpu_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct rockchip_vpu_ctx *ctx; + + ctx = container_of(ctrl->handler, + struct rockchip_vpu_ctx, ctrl_handler); + + vpu_debug(1, "s_ctrl: id = %d, val = %d\n", ctrl->id, ctrl->val); + + switch (ctrl->id) { + case V4L2_CID_JPEG_COMPRESSION_QUALITY: + ctx->jpeg_quality = ctrl->val; + break; + default: + return -EINVAL; + } + + return 0; +} + +static const struct v4l2_ctrl_ops rockchip_vpu_ctrl_ops = { + .s_ctrl = rockchip_vpu_s_ctrl, +}; + +static int rockchip_vpu_ctrls_setup(struct rockchip_vpu_dev *vpu, + struct rockchip_vpu_ctx *ctx) +{ + v4l2_ctrl_handler_init(&ctx->ctrl_handler, 1); + if (vpu->variant->codec & RK_VPU_CODEC_JPEG) { + v4l2_ctrl_new_std(&ctx->ctrl_handler, &rockchip_vpu_ctrl_ops, + V4L2_CID_JPEG_COMPRESSION_QUALITY, + 5, 100, 1, 50); + if (ctx->ctrl_handler.error) { + vpu_err("Adding JPEG control failed %d\n", + ctx->ctrl_handler.error); + v4l2_ctrl_handler_free(&ctx->ctrl_handler); + return ctx->ctrl_handler.error; + } + } + + return v4l2_ctrl_handler_setup(&ctx->ctrl_handler); +} + +/* + * V4L2 file operations. + */ + +static int rockchip_vpu_open(struct file *filp) +{ + struct rockchip_vpu_dev *vpu = video_drvdata(filp); + struct video_device *vdev = video_devdata(filp); + struct rockchip_vpu_ctx *ctx; + int ret; + + /* + * We do not need any extra locking here, because we operate only + * on local data here, except reading few fields from dev, which + * do not change through device's lifetime (which is guaranteed by + * reference on module from open()) and V4L2 internal objects (such + * as vdev and ctx->fh), which have proper locking done in respective + * helper functions used here. + */ + + ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + ctx->dev = vpu; + if (vdev == vpu->vfd_enc) + ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(vpu->m2m_dev, ctx, + &enc_queue_init); + else + ctx->fh.m2m_ctx = ERR_PTR(-ENODEV); + if (IS_ERR(ctx->fh.m2m_ctx)) { + ret = PTR_ERR(ctx->fh.m2m_ctx); + kfree(ctx); + return ret; + } + + v4l2_fh_init(&ctx->fh, vdev); + filp->private_data = &ctx->fh; + v4l2_fh_add(&ctx->fh); + + if (vdev == vpu->vfd_enc) { + rockchip_vpu_enc_reset_dst_fmt(vpu, ctx); + rockchip_vpu_enc_reset_src_fmt(vpu, ctx); + } + + ret = rockchip_vpu_ctrls_setup(vpu, ctx); + if (ret) { + vpu_err("Failed to set up controls\n"); + goto err_fh_free; + } + ctx->fh.ctrl_handler = &ctx->ctrl_handler; + + return 0; + +err_fh_free: + v4l2_fh_del(&ctx->fh); + v4l2_fh_exit(&ctx->fh); + kfree(ctx); + return ret; +} + +static int rockchip_vpu_release(struct file *filp) +{ + struct rockchip_vpu_ctx *ctx = + container_of(filp->private_data, struct rockchip_vpu_ctx, fh); + + /* + * No need for extra locking because this was the last reference + * to this file. + */ + v4l2_m2m_ctx_release(ctx->fh.m2m_ctx); + v4l2_fh_del(&ctx->fh); + v4l2_fh_exit(&ctx->fh); + v4l2_ctrl_handler_free(&ctx->ctrl_handler); + kfree(ctx); + + return 0; +} + +static const struct v4l2_file_operations rockchip_vpu_fops = { + .owner = THIS_MODULE, + .open = rockchip_vpu_open, + .release = rockchip_vpu_release, + .poll = v4l2_m2m_fop_poll, + .unlocked_ioctl = video_ioctl2, + .mmap = v4l2_m2m_fop_mmap, +}; + +static const struct of_device_id of_rockchip_vpu_match[] = { + { .compatible = "rockchip,rk3399-vpu", .data = &rk3399_vpu_variant, }, + { .compatible = "rockchip,rk3288-vpu", .data = &rk3288_vpu_variant, }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_rockchip_vpu_match); + +static int rockchip_vpu_video_device_register(struct rockchip_vpu_dev *vpu) +{ + const struct of_device_id *match; + struct video_device *vfd; + int function, ret; + + match = of_match_node(of_rockchip_vpu_match, vpu->dev->of_node); + vfd = video_device_alloc(); + if (!vfd) { + v4l2_err(&vpu->v4l2_dev, "Failed to allocate video device\n"); + return -ENOMEM; + } + + vfd->fops = &rockchip_vpu_fops; + vfd->release = video_device_release; + vfd->lock = &vpu->vpu_mutex; + vfd->v4l2_dev = &vpu->v4l2_dev; + vfd->vfl_dir = VFL_DIR_M2M; + vfd->device_caps = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_M2M_MPLANE; + vfd->ioctl_ops = &rockchip_vpu_enc_ioctl_ops; + snprintf(vfd->name, sizeof(vfd->name), "%s-enc", match->compatible); + vpu->vfd_enc = vfd; + video_set_drvdata(vfd, vpu); + + ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0); + if (ret) { + v4l2_err(&vpu->v4l2_dev, "Failed to register video device\n"); + goto err_free_dev; + } + v4l2_info(&vpu->v4l2_dev, "registered as /dev/video%d\n", vfd->num); + + function = MEDIA_ENT_F_PROC_VIDEO_ENCODER; + ret = v4l2_m2m_register_media_controller(vpu->m2m_dev, vfd, function); + if (ret) { + v4l2_err(&vpu->v4l2_dev, "Failed to init mem2mem media controller\n"); + goto err_unreg_video; + } + return 0; + +err_unreg_video: + video_unregister_device(vfd); +err_free_dev: + video_device_release(vfd); + return ret; +} + +static int rockchip_vpu_probe(struct platform_device *pdev) +{ + const struct of_device_id *match; + struct rockchip_vpu_dev *vpu; + struct resource *res; + int i, ret; + + vpu = devm_kzalloc(&pdev->dev, sizeof(*vpu), GFP_KERNEL); + if (!vpu) + return -ENOMEM; + + vpu->dev = &pdev->dev; + vpu->pdev = pdev; + mutex_init(&vpu->vpu_mutex); + spin_lock_init(&vpu->irqlock); + + match = of_match_node(of_rockchip_vpu_match, pdev->dev.of_node); + vpu->variant = match->data; + + INIT_DELAYED_WORK(&vpu->watchdog_work, rockchip_vpu_watchdog); + + for (i = 0; i < vpu->variant->num_clocks; i++) + vpu->clocks[i].id = vpu->variant->clk_names[i]; + ret = devm_clk_bulk_get(&pdev->dev, vpu->variant->num_clocks, + vpu->clocks); + if (ret) + return ret; + + res = platform_get_resource(vpu->pdev, IORESOURCE_MEM, 0); + vpu->base = devm_ioremap_resource(vpu->dev, res); + if (IS_ERR(vpu->base)) + return PTR_ERR(vpu->base); + vpu->enc_base = vpu->base + vpu->variant->enc_offset; + + ret = dma_set_coherent_mask(vpu->dev, DMA_BIT_MASK(32)); + if (ret) { + dev_err(vpu->dev, "Could not set DMA coherent mask.\n"); + return ret; + } + + if (vpu->variant->vepu_irq) { + int irq; + + irq = platform_get_irq_byname(vpu->pdev, "vepu"); + if (irq <= 0) { + dev_err(vpu->dev, "Could not get vepu IRQ.\n"); + return -ENXIO; + } + + ret = devm_request_irq(vpu->dev, irq, vpu->variant->vepu_irq, + 0, dev_name(vpu->dev), vpu); + if (ret) { + dev_err(vpu->dev, "Could not request vepu IRQ.\n"); + return ret; + } + } + + ret = vpu->variant->init(vpu); + if (ret) { + dev_err(&pdev->dev, "Failed to init VPU hardware\n"); + return ret; + } + + pm_runtime_set_autosuspend_delay(vpu->dev, 100); + pm_runtime_use_autosuspend(vpu->dev); + pm_runtime_enable(vpu->dev); + + ret = clk_bulk_prepare(vpu->variant->num_clocks, vpu->clocks); + if (ret) { + dev_err(&pdev->dev, "Failed to prepare clocks\n"); + return ret; + } + + ret = v4l2_device_register(&pdev->dev, &vpu->v4l2_dev); + if (ret) { + dev_err(&pdev->dev, "Failed to register v4l2 device\n"); + goto err_clk_unprepare; + } + platform_set_drvdata(pdev, vpu); + + vpu->m2m_dev = v4l2_m2m_init(&vpu_m2m_ops); + if (IS_ERR(vpu->m2m_dev)) { + v4l2_err(&vpu->v4l2_dev, "Failed to init mem2mem device\n"); + ret = PTR_ERR(vpu->m2m_dev); + goto err_v4l2_unreg; + } + + vpu->mdev.dev = vpu->dev; + strlcpy(vpu->mdev.model, DRIVER_NAME, sizeof(vpu->mdev.model)); + media_device_init(&vpu->mdev); + vpu->v4l2_dev.mdev = &vpu->mdev; + + ret = rockchip_vpu_video_device_register(vpu); + if (ret) { + dev_err(&pdev->dev, "Failed to register encoder\n"); + goto err_m2m_rel; + } + + ret = media_device_register(&vpu->mdev); + if (ret) { + v4l2_err(&vpu->v4l2_dev, "Failed to register mem2mem media device\n"); + goto err_video_dev_unreg; + } + return 0; +err_video_dev_unreg: + if (vpu->vfd_enc) { + video_unregister_device(vpu->vfd_enc); + video_device_release(vpu->vfd_enc); + } +err_m2m_rel: + v4l2_m2m_release(vpu->m2m_dev); +err_v4l2_unreg: + v4l2_device_unregister(&vpu->v4l2_dev); +err_clk_unprepare: + clk_bulk_unprepare(vpu->variant->num_clocks, vpu->clocks); + pm_runtime_disable(vpu->dev); + return ret; +} + +static int rockchip_vpu_remove(struct platform_device *pdev) +{ + struct rockchip_vpu_dev *vpu = platform_get_drvdata(pdev); + + v4l2_info(&vpu->v4l2_dev, "Removing %s\n", pdev->name); + + media_device_unregister(&vpu->mdev); + v4l2_m2m_unregister_media_controller(vpu->m2m_dev); + v4l2_m2m_release(vpu->m2m_dev); + media_device_cleanup(&vpu->mdev); + if (vpu->vfd_enc) { + video_unregister_device(vpu->vfd_enc); + video_device_release(vpu->vfd_enc); + } + v4l2_device_unregister(&vpu->v4l2_dev); + clk_bulk_unprepare(vpu->variant->num_clocks, vpu->clocks); + pm_runtime_disable(vpu->dev); + return 0; +} + +static const struct dev_pm_ops rockchip_vpu_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) +}; + +static struct platform_driver rockchip_vpu_driver = { + .probe = rockchip_vpu_probe, + .remove = rockchip_vpu_remove, + .driver = { + .name = DRIVER_NAME, + .of_match_table = of_match_ptr(of_rockchip_vpu_match), + .pm = &rockchip_vpu_pm_ops, + }, +}; +module_platform_driver(rockchip_vpu_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Alpha Lin <Alpha.Lin@Rock-Chips.com>"); +MODULE_AUTHOR("Tomasz Figa <tfiga@chromium.org>"); +MODULE_AUTHOR("Ezequiel Garcia <ezequiel@collabora.com>"); +MODULE_DESCRIPTION("Rockchip VPU codec driver"); diff --git a/drivers/staging/media/rockchip/vpu/rockchip_vpu_enc.c b/drivers/staging/media/rockchip/vpu/rockchip_vpu_enc.c new file mode 100644 index 000000000000..ab0fb2053620 --- /dev/null +++ b/drivers/staging/media/rockchip/vpu/rockchip_vpu_enc.c @@ -0,0 +1,670 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Rockchip VPU codec driver + * + * Copyright (C) 2018 Collabora, Ltd. + * Copyright (C) 2018 Rockchip Electronics Co., Ltd. + * Alpha Lin <Alpha.Lin@rock-chips.com> + * Jeffy Chen <jeffy.chen@rock-chips.com> + * + * Copyright 2018 Google LLC. + * Tomasz Figa <tfiga@chromium.org> + * + * Based on s5p-mfc driver by Samsung Electronics Co., Ltd. + * Copyright (C) 2010-2011 Samsung Electronics Co., Ltd. + */ + +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/pm_runtime.h> +#include <linux/videodev2.h> +#include <linux/workqueue.h> +#include <media/v4l2-ctrls.h> +#include <media/v4l2-event.h> +#include <media/v4l2-mem2mem.h> +#include <media/videobuf2-core.h> +#include <media/videobuf2-dma-sg.h> + +#include "rockchip_vpu.h" +#include "rockchip_vpu_hw.h" +#include "rockchip_vpu_common.h" + +/** + * struct v4l2_format_info - information about a V4L2 format + * @format: 4CC format identifier (V4L2_PIX_FMT_*) + * @header_size: Size of header, optional and used by compressed formats + * @num_planes: Number of planes (1 to 3) + * @cpp: Number of bytes per pixel (per plane) + * @hsub: Horizontal chroma subsampling factor + * @vsub: Vertical chroma subsampling factor + * @is_compressed: Is it a compressed format? + * @multiplanar: Is it a multiplanar variant format? (e.g. NV12M) + */ +struct v4l2_format_info { + u32 format; + u32 header_size; + u8 num_planes; + u8 cpp[3]; + u8 hsub; + u8 vsub; + u8 is_compressed; + u8 multiplanar; +}; + +static const struct v4l2_format_info * +v4l2_format_info(u32 format) +{ + static const struct v4l2_format_info formats[] = { + { .format = V4L2_PIX_FMT_YUV420M, .num_planes = 3, .cpp = { 1, 1, 1 }, .hsub = 2, .vsub = 2, .multiplanar = 1 }, + { .format = V4L2_PIX_FMT_NV12M, .num_planes = 2, .cpp = { 1, 2, 0 }, .hsub = 2, .vsub = 2, .multiplanar = 1 }, + { .format = V4L2_PIX_FMT_YUYV, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 }, + { .format = V4L2_PIX_FMT_UYVY, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 }, + }; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(formats); ++i) { + if (formats[i].format == format) + return &formats[i]; + } + + vpu_err("Unsupported V4L 4CC format (%08x)\n", format); + return NULL; +} + +static void +fill_pixfmt_mp(struct v4l2_pix_format_mplane *pixfmt, + int pixelformat, int width, int height) +{ + const struct v4l2_format_info *info; + struct v4l2_plane_pix_format *plane; + int i; + + info = v4l2_format_info(pixelformat); + if (!info) + return; + + pixfmt->width = width; + pixfmt->height = height; + pixfmt->pixelformat = pixelformat; + + if (!info->multiplanar) { + pixfmt->num_planes = 1; + plane = &pixfmt->plane_fmt[0]; + plane->bytesperline = info->is_compressed ? + 0 : width * info->cpp[0]; + plane->sizeimage = info->header_size; + for (i = 0; i < info->num_planes; i++) { + unsigned int hsub = (i == 0) ? 1 : info->hsub; + unsigned int vsub = (i == 0) ? 1 : info->vsub; + + plane->sizeimage += info->cpp[i] * + DIV_ROUND_UP(width, hsub) * + DIV_ROUND_UP(height, vsub); + } + } else { + pixfmt->num_planes = info->num_planes; + for (i = 0; i < info->num_planes; i++) { + unsigned int hsub = (i == 0) ? 1 : info->hsub; + unsigned int vsub = (i == 0) ? 1 : info->vsub; + + plane = &pixfmt->plane_fmt[i]; + plane->bytesperline = + info->cpp[i] * DIV_ROUND_UP(width, hsub); + plane->sizeimage = + plane->bytesperline * DIV_ROUND_UP(height, vsub); + } + } +} + +static const struct rockchip_vpu_fmt * +rockchip_vpu_find_format(struct rockchip_vpu_ctx *ctx, u32 fourcc) +{ + struct rockchip_vpu_dev *dev = ctx->dev; + const struct rockchip_vpu_fmt *formats; + unsigned int num_fmts, i; + + formats = dev->variant->enc_fmts; + num_fmts = dev->variant->num_enc_fmts; + for (i = 0; i < num_fmts; i++) + if (formats[i].fourcc == fourcc) + return &formats[i]; + return NULL; +} + +static const struct rockchip_vpu_fmt * +rockchip_vpu_get_default_fmt(struct rockchip_vpu_ctx *ctx, bool bitstream) +{ + struct rockchip_vpu_dev *dev = ctx->dev; + const struct rockchip_vpu_fmt *formats; + unsigned int num_fmts, i; + + formats = dev->variant->enc_fmts; + num_fmts = dev->variant->num_enc_fmts; + for (i = 0; i < num_fmts; i++) { + if (bitstream == (formats[i].codec_mode != RK_VPU_MODE_NONE)) + return &formats[i]; + } + return NULL; +} + +static int vidioc_querycap(struct file *file, void *priv, + struct v4l2_capability *cap) +{ + struct rockchip_vpu_dev *vpu = video_drvdata(file); + + strscpy(cap->driver, vpu->dev->driver->name, sizeof(cap->driver)); + strscpy(cap->card, vpu->vfd_enc->name, sizeof(cap->card)); + snprintf(cap->bus_info, sizeof(cap->bus_info), "platform: %s", + vpu->dev->driver->name); + return 0; +} + +static int vidioc_enum_framesizes(struct file *file, void *priv, + struct v4l2_frmsizeenum *fsize) +{ + struct rockchip_vpu_ctx *ctx = fh_to_ctx(priv); + const struct rockchip_vpu_fmt *fmt; + + if (fsize->index != 0) { + vpu_debug(0, "invalid frame size index (expected 0, got %d)\n", + fsize->index); + return -EINVAL; + } + + fmt = rockchip_vpu_find_format(ctx, fsize->pixel_format); + if (!fmt) { + vpu_debug(0, "unsupported bitstream format (%08x)\n", + fsize->pixel_format); + return -EINVAL; + } + + /* This only makes sense for coded formats */ + if (fmt->codec_mode == RK_VPU_MODE_NONE) + return -EINVAL; + + fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE; + fsize->stepwise = fmt->frmsize; + + return 0; +} + +static int vidioc_enum_fmt_vid_cap_mplane(struct file *file, void *priv, + struct v4l2_fmtdesc *f) +{ + struct rockchip_vpu_dev *dev = video_drvdata(file); + const struct rockchip_vpu_fmt *fmt; + const struct rockchip_vpu_fmt *formats; + int num_fmts, i, j = 0; + + formats = dev->variant->enc_fmts; + num_fmts = dev->variant->num_enc_fmts; + for (i = 0; i < num_fmts; i++) { + /* Skip uncompressed formats */ + if (formats[i].codec_mode == RK_VPU_MODE_NONE) + continue; + if (j == f->index) { + fmt = &formats[i]; + f->pixelformat = fmt->fourcc; + return 0; + } + ++j; + } + return -EINVAL; +} + +static int vidioc_enum_fmt_vid_out_mplane(struct file *file, void *priv, + struct v4l2_fmtdesc *f) +{ + struct rockchip_vpu_dev *dev = video_drvdata(file); + const struct rockchip_vpu_fmt *formats; + const struct rockchip_vpu_fmt *fmt; + int num_fmts, i, j = 0; + + formats = dev->variant->enc_fmts; + num_fmts = dev->variant->num_enc_fmts; + for (i = 0; i < num_fmts; i++) { + if (formats[i].codec_mode != RK_VPU_MODE_NONE) + continue; + if (j == f->index) { + fmt = &formats[i]; + f->pixelformat = fmt->fourcc; + return 0; + } + ++j; + } + return -EINVAL; +} + +static int vidioc_g_fmt_out_mplane(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp; + struct rockchip_vpu_ctx *ctx = fh_to_ctx(priv); + + vpu_debug(4, "f->type = %d\n", f->type); + + *pix_mp = ctx->src_fmt; + + return 0; +} + +static int vidioc_g_fmt_cap_mplane(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp; + struct rockchip_vpu_ctx *ctx = fh_to_ctx(priv); + + vpu_debug(4, "f->type = %d\n", f->type); + + *pix_mp = ctx->dst_fmt; + + return 0; +} + +static int +vidioc_try_fmt_cap_mplane(struct file *file, void *priv, struct v4l2_format *f) +{ + struct rockchip_vpu_ctx *ctx = fh_to_ctx(priv); + struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp; + const struct rockchip_vpu_fmt *fmt; + + vpu_debug(4, "%c%c%c%c\n", + (pix_mp->pixelformat & 0x7f), + (pix_mp->pixelformat >> 8) & 0x7f, + (pix_mp->pixelformat >> 16) & 0x7f, + (pix_mp->pixelformat >> 24) & 0x7f); + + fmt = rockchip_vpu_find_format(ctx, pix_mp->pixelformat); + if (!fmt) { + fmt = rockchip_vpu_get_default_fmt(ctx, true); + f->fmt.pix.pixelformat = fmt->fourcc; + } + + pix_mp->num_planes = 1; + pix_mp->field = V4L2_FIELD_NONE; + pix_mp->width = clamp(pix_mp->width, + fmt->frmsize.min_width, + fmt->frmsize.max_width); + pix_mp->height = clamp(pix_mp->height, + fmt->frmsize.min_height, + fmt->frmsize.max_height); + /* Round up to macroblocks. */ + pix_mp->width = round_up(pix_mp->width, JPEG_MB_DIM); + pix_mp->height = round_up(pix_mp->height, JPEG_MB_DIM); + + /* + * For compressed formats the application can specify + * sizeimage. If the application passes a zero sizeimage, + * let's default to the maximum frame size. + */ + if (!pix_mp->plane_fmt[0].sizeimage) + pix_mp->plane_fmt[0].sizeimage = fmt->header_size + + pix_mp->width * pix_mp->height * fmt->max_depth; + memset(pix_mp->plane_fmt[0].reserved, 0, + sizeof(pix_mp->plane_fmt[0].reserved)); + return 0; +} + +static int +vidioc_try_fmt_out_mplane(struct file *file, void *priv, struct v4l2_format *f) +{ + struct rockchip_vpu_ctx *ctx = fh_to_ctx(priv); + struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp; + const struct rockchip_vpu_fmt *fmt; + unsigned int width, height; + int i; + + vpu_debug(4, "%c%c%c%c\n", + (pix_mp->pixelformat & 0x7f), + (pix_mp->pixelformat >> 8) & 0x7f, + (pix_mp->pixelformat >> 16) & 0x7f, + (pix_mp->pixelformat >> 24) & 0x7f); + + fmt = rockchip_vpu_find_format(ctx, pix_mp->pixelformat); + if (!fmt) { + fmt = rockchip_vpu_get_default_fmt(ctx, false); + f->fmt.pix.pixelformat = fmt->fourcc; + } + + pix_mp->field = V4L2_FIELD_NONE; + width = clamp(pix_mp->width, + ctx->vpu_dst_fmt->frmsize.min_width, + ctx->vpu_dst_fmt->frmsize.max_width); + height = clamp(pix_mp->height, + ctx->vpu_dst_fmt->frmsize.min_height, + ctx->vpu_dst_fmt->frmsize.max_height); + /* Round up to macroblocks. */ + width = round_up(width, JPEG_MB_DIM); + height = round_up(height, JPEG_MB_DIM); + + /* Fill remaining fields */ + fill_pixfmt_mp(pix_mp, fmt->fourcc, width, height); + + for (i = 0; i < pix_mp->num_planes; i++) { + memset(pix_mp->plane_fmt[i].reserved, 0, + sizeof(pix_mp->plane_fmt[i].reserved)); + } + return 0; +} + +void rockchip_vpu_enc_reset_dst_fmt(struct rockchip_vpu_dev *vpu, + struct rockchip_vpu_ctx *ctx) +{ + struct v4l2_pix_format_mplane *fmt = &ctx->dst_fmt; + + ctx->vpu_dst_fmt = rockchip_vpu_get_default_fmt(ctx, true); + + memset(fmt, 0, sizeof(*fmt)); + + fmt->num_planes = 1; + fmt->width = clamp(fmt->width, ctx->vpu_dst_fmt->frmsize.min_width, + ctx->vpu_dst_fmt->frmsize.max_width); + fmt->height = clamp(fmt->height, ctx->vpu_dst_fmt->frmsize.min_height, + ctx->vpu_dst_fmt->frmsize.max_height); + fmt->pixelformat = ctx->vpu_dst_fmt->fourcc; + fmt->field = V4L2_FIELD_NONE; + fmt->colorspace = V4L2_COLORSPACE_JPEG, + fmt->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; + fmt->quantization = V4L2_QUANTIZATION_DEFAULT; + fmt->xfer_func = V4L2_XFER_FUNC_DEFAULT; + + fmt->plane_fmt[0].sizeimage = ctx->vpu_dst_fmt->header_size + + fmt->width * fmt->height * ctx->vpu_dst_fmt->max_depth; +} + +void rockchip_vpu_enc_reset_src_fmt(struct rockchip_vpu_dev *vpu, + struct rockchip_vpu_ctx *ctx) +{ + struct v4l2_pix_format_mplane *fmt = &ctx->src_fmt; + unsigned int width, height; + + ctx->vpu_src_fmt = rockchip_vpu_get_default_fmt(ctx, false); + + memset(fmt, 0, sizeof(*fmt)); + + width = clamp(fmt->width, ctx->vpu_dst_fmt->frmsize.min_width, + ctx->vpu_dst_fmt->frmsize.max_width); + height = clamp(fmt->height, ctx->vpu_dst_fmt->frmsize.min_height, + ctx->vpu_dst_fmt->frmsize.max_height); + fmt->field = V4L2_FIELD_NONE; + fmt->colorspace = V4L2_COLORSPACE_JPEG, + fmt->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; + fmt->quantization = V4L2_QUANTIZATION_DEFAULT; + fmt->xfer_func = V4L2_XFER_FUNC_DEFAULT; + + fill_pixfmt_mp(fmt, ctx->vpu_src_fmt->fourcc, width, height); +} + +static int +vidioc_s_fmt_out_mplane(struct file *file, void *priv, struct v4l2_format *f) +{ + struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp; + struct rockchip_vpu_ctx *ctx = fh_to_ctx(priv); + struct vb2_queue *vq; + int ret; + + /* Change not allowed if queue is streaming. */ + vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type); + if (vb2_is_streaming(vq)) + return -EBUSY; + + ret = vidioc_try_fmt_out_mplane(file, priv, f); + if (ret) + return ret; + + ctx->vpu_src_fmt = rockchip_vpu_find_format(ctx, pix_mp->pixelformat); + ctx->src_fmt = *pix_mp; + + /* Propagate to the CAPTURE format */ + ctx->dst_fmt.colorspace = pix_mp->colorspace; + ctx->dst_fmt.ycbcr_enc = pix_mp->ycbcr_enc; + ctx->dst_fmt.xfer_func = pix_mp->xfer_func; + ctx->dst_fmt.quantization = pix_mp->quantization; + ctx->dst_fmt.width = pix_mp->width; + ctx->dst_fmt.height = pix_mp->height; + + vpu_debug(0, "OUTPUT codec mode: %d\n", ctx->vpu_src_fmt->codec_mode); + vpu_debug(0, "fmt - w: %d, h: %d, mb - w: %d, h: %d\n", + pix_mp->width, pix_mp->height, + JPEG_MB_WIDTH(pix_mp->width), + JPEG_MB_HEIGHT(pix_mp->height)); + return 0; +} + +static int +vidioc_s_fmt_cap_mplane(struct file *file, void *priv, struct v4l2_format *f) +{ + struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp; + struct rockchip_vpu_ctx *ctx = fh_to_ctx(priv); + struct rockchip_vpu_dev *vpu = ctx->dev; + struct vb2_queue *vq, *peer_vq; + int ret; + + /* Change not allowed if queue is streaming. */ + vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type); + if (vb2_is_streaming(vq)) + return -EBUSY; + + /* + * Since format change on the CAPTURE queue will reset + * the OUTPUT queue, we can't allow doing so + * when the OUTPUT queue has buffers allocated. + */ + peer_vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, + V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); + if (vb2_is_busy(peer_vq) && + (pix_mp->pixelformat != ctx->dst_fmt.pixelformat || + pix_mp->height != ctx->dst_fmt.height || + pix_mp->width != ctx->dst_fmt.width)) + return -EBUSY; + + ret = vidioc_try_fmt_cap_mplane(file, priv, f); + if (ret) + return ret; + + ctx->vpu_dst_fmt = rockchip_vpu_find_format(ctx, pix_mp->pixelformat); + ctx->dst_fmt = *pix_mp; + + vpu_debug(0, "CAPTURE codec mode: %d\n", ctx->vpu_dst_fmt->codec_mode); + vpu_debug(0, "fmt - w: %d, h: %d, mb - w: %d, h: %d\n", + pix_mp->width, pix_mp->height, + JPEG_MB_WIDTH(pix_mp->width), + JPEG_MB_HEIGHT(pix_mp->height)); + + /* + * Current raw format might have become invalid with newly + * selected codec, so reset it to default just to be safe and + * keep internal driver state sane. User is mandated to set + * the raw format again after we return, so we don't need + * anything smarter. + */ + rockchip_vpu_enc_reset_src_fmt(vpu, ctx); + return 0; +} + +const struct v4l2_ioctl_ops rockchip_vpu_enc_ioctl_ops = { + .vidioc_querycap = vidioc_querycap, + .vidioc_enum_framesizes = vidioc_enum_framesizes, + + .vidioc_try_fmt_vid_cap_mplane = vidioc_try_fmt_cap_mplane, + .vidioc_try_fmt_vid_out_mplane = vidioc_try_fmt_out_mplane, + .vidioc_s_fmt_vid_out_mplane = vidioc_s_fmt_out_mplane, + .vidioc_s_fmt_vid_cap_mplane = vidioc_s_fmt_cap_mplane, + .vidioc_g_fmt_vid_out_mplane = vidioc_g_fmt_out_mplane, + .vidioc_g_fmt_vid_cap_mplane = vidioc_g_fmt_cap_mplane, + .vidioc_enum_fmt_vid_out_mplane = vidioc_enum_fmt_vid_out_mplane, + .vidioc_enum_fmt_vid_cap_mplane = vidioc_enum_fmt_vid_cap_mplane, + + .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs, + .vidioc_querybuf = v4l2_m2m_ioctl_querybuf, + .vidioc_qbuf = v4l2_m2m_ioctl_qbuf, + .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf, + .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf, + .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs, + .vidioc_expbuf = v4l2_m2m_ioctl_expbuf, + + .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, + .vidioc_unsubscribe_event = v4l2_event_unsubscribe, + + .vidioc_streamon = v4l2_m2m_ioctl_streamon, + .vidioc_streamoff = v4l2_m2m_ioctl_streamoff, +}; + +static int +rockchip_vpu_queue_setup(struct vb2_queue *vq, + unsigned int *num_buffers, + unsigned int *num_planes, + unsigned int sizes[], + struct device *alloc_devs[]) +{ + struct rockchip_vpu_ctx *ctx = vb2_get_drv_priv(vq); + struct v4l2_pix_format_mplane *pixfmt; + int i; + + switch (vq->type) { + case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE: + pixfmt = &ctx->dst_fmt; + break; + case V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE: + pixfmt = &ctx->src_fmt; + break; + default: + vpu_err("invalid queue type: %d\n", vq->type); + return -EINVAL; + } + + if (*num_planes) { + if (*num_planes != pixfmt->num_planes) + return -EINVAL; + for (i = 0; i < pixfmt->num_planes; ++i) + if (sizes[i] < pixfmt->plane_fmt[i].sizeimage) + return -EINVAL; + return 0; + } + + *num_planes = pixfmt->num_planes; + for (i = 0; i < pixfmt->num_planes; ++i) + sizes[i] = pixfmt->plane_fmt[i].sizeimage; + return 0; +} + +static int rockchip_vpu_buf_prepare(struct vb2_buffer *vb) +{ + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); + struct vb2_queue *vq = vb->vb2_queue; + struct rockchip_vpu_ctx *ctx = vb2_get_drv_priv(vq); + struct v4l2_pix_format_mplane *pixfmt; + unsigned int sz; + int ret = 0; + int i; + + switch (vq->type) { + case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE: + pixfmt = &ctx->dst_fmt; + break; + case V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE: + pixfmt = &ctx->src_fmt; + + if (vbuf->field == V4L2_FIELD_ANY) + vbuf->field = V4L2_FIELD_NONE; + if (vbuf->field != V4L2_FIELD_NONE) { + vpu_debug(4, "field %d not supported\n", + vbuf->field); + return -EINVAL; + } + break; + default: + vpu_err("invalid queue type: %d\n", vq->type); + return -EINVAL; + } + + for (i = 0; i < pixfmt->num_planes; ++i) { + sz = pixfmt->plane_fmt[i].sizeimage; + vpu_debug(4, "plane %d size: %ld, sizeimage: %u\n", + i, vb2_plane_size(vb, i), sz); + if (vb2_plane_size(vb, i) < sz) { + vpu_err("plane %d is too small\n", i); + ret = -EINVAL; + break; + } + } + + return ret; +} + +static void rockchip_vpu_buf_queue(struct vb2_buffer *vb) +{ + struct rockchip_vpu_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); + + v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf); +} + +static int rockchip_vpu_start_streaming(struct vb2_queue *q, unsigned int count) +{ + struct rockchip_vpu_ctx *ctx = vb2_get_drv_priv(q); + enum rockchip_vpu_codec_mode codec_mode; + + if (V4L2_TYPE_IS_OUTPUT(q->type)) + ctx->sequence_out = 0; + else + ctx->sequence_cap = 0; + + /* Set codec_ops for the chosen destination format */ + codec_mode = ctx->vpu_dst_fmt->codec_mode; + + vpu_debug(4, "Codec mode = %d\n", codec_mode); + ctx->codec_ops = &ctx->dev->variant->codec_ops[codec_mode]; + + /* A bounce buffer is needed for the JPEG payload */ + if (!V4L2_TYPE_IS_OUTPUT(q->type)) { + ctx->bounce_size = ctx->dst_fmt.plane_fmt[0].sizeimage - + ctx->vpu_dst_fmt->header_size; + ctx->bounce_buf = dma_alloc_attrs(ctx->dev->dev, + ctx->bounce_size, + &ctx->bounce_dma_addr, + GFP_KERNEL, + DMA_ATTR_ALLOC_SINGLE_PAGES); + } + return 0; +} + +static void rockchip_vpu_stop_streaming(struct vb2_queue *q) +{ + struct rockchip_vpu_ctx *ctx = vb2_get_drv_priv(q); + + if (!V4L2_TYPE_IS_OUTPUT(q->type)) + dma_free_attrs(ctx->dev->dev, + ctx->bounce_size, + ctx->bounce_buf, + ctx->bounce_dma_addr, + DMA_ATTR_ALLOC_SINGLE_PAGES); + + /* + * The mem2mem framework calls v4l2_m2m_cancel_job before + * .stop_streaming, so there isn't any job running and + * it is safe to return all the buffers. + */ + for (;;) { + struct vb2_v4l2_buffer *vbuf; + + if (V4L2_TYPE_IS_OUTPUT(q->type)) + vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); + else + vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); + if (!vbuf) + break; + v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_ERROR); + } +} + +const struct vb2_ops rockchip_vpu_enc_queue_ops = { + .queue_setup = rockchip_vpu_queue_setup, + .buf_prepare = rockchip_vpu_buf_prepare, + .buf_queue = rockchip_vpu_buf_queue, + .start_streaming = rockchip_vpu_start_streaming, + .stop_streaming = rockchip_vpu_stop_streaming, + .wait_prepare = vb2_ops_wait_prepare, + .wait_finish = vb2_ops_wait_finish, +}; diff --git a/drivers/staging/media/rockchip/vpu/rockchip_vpu_hw.h b/drivers/staging/media/rockchip/vpu/rockchip_vpu_hw.h new file mode 100644 index 000000000000..2b955da1be1a --- /dev/null +++ b/drivers/staging/media/rockchip/vpu/rockchip_vpu_hw.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Rockchip VPU codec driver + * + * Copyright 2018 Google LLC. + * Tomasz Figa <tfiga@chromium.org> + */ + +#ifndef ROCKCHIP_VPU_HW_H_ +#define ROCKCHIP_VPU_HW_H_ + +#include <linux/interrupt.h> +#include <linux/v4l2-controls.h> +#include <media/videobuf2-core.h> + +struct rockchip_vpu_dev; +struct rockchip_vpu_ctx; +struct rockchip_vpu_buf; +struct rockchip_vpu_variant; + +/** + * struct rockchip_vpu_codec_ops - codec mode specific operations + * + * @run: Start single {en,de)coding job. Called from atomic context + * to indicate that a pair of buffers is ready and the hardware + * should be programmed and started. + * @done: Read back processing results and additional data from hardware. + * @reset: Reset the hardware in case of a timeout. + */ +struct rockchip_vpu_codec_ops { + void (*run)(struct rockchip_vpu_ctx *ctx); + void (*done)(struct rockchip_vpu_ctx *ctx, enum vb2_buffer_state); + void (*reset)(struct rockchip_vpu_ctx *ctx); +}; + +/** + * enum rockchip_vpu_enc_fmt - source format ID for hardware registers. + */ +enum rockchip_vpu_enc_fmt { + RK3288_VPU_ENC_FMT_YUV420P = 0, + RK3288_VPU_ENC_FMT_YUV420SP = 1, + RK3288_VPU_ENC_FMT_YUYV422 = 2, + RK3288_VPU_ENC_FMT_UYVY422 = 3, +}; + +extern const struct rockchip_vpu_variant rk3399_vpu_variant; +extern const struct rockchip_vpu_variant rk3288_vpu_variant; + +void rockchip_vpu_watchdog(struct work_struct *work); +void rockchip_vpu_run(struct rockchip_vpu_ctx *ctx); +void rockchip_vpu_irq_done(struct rockchip_vpu_dev *vpu, + unsigned int bytesused, + enum vb2_buffer_state result); + +void rk3288_vpu_jpeg_enc_run(struct rockchip_vpu_ctx *ctx); +void rk3399_vpu_jpeg_enc_run(struct rockchip_vpu_ctx *ctx); + +#endif /* ROCKCHIP_VPU_HW_H_ */ diff --git a/drivers/staging/media/rockchip/vpu/rockchip_vpu_jpeg.c b/drivers/staging/media/rockchip/vpu/rockchip_vpu_jpeg.c new file mode 100644 index 000000000000..0ff0badc1f7a --- /dev/null +++ b/drivers/staging/media/rockchip/vpu/rockchip_vpu_jpeg.c @@ -0,0 +1,290 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) Collabora, Ltd. + * + * Based on GSPCA and CODA drivers: + * Copyright (C) Jean-Francois Moine (http://moinejf.free.fr) + * Copyright (C) 2014 Philipp Zabel, Pengutronix + */ +#include <linux/kernel.h> +#include <linux/string.h> +#include "rockchip_vpu_jpeg.h" + +#define LUMA_QUANT_OFF 7 +#define CHROMA_QUANT_OFF 72 +#define HEIGHT_OFF 141 +#define WIDTH_OFF 143 + +#define HUFF_LUMA_DC_OFF 160 +#define HUFF_LUMA_AC_OFF 193 +#define HUFF_CHROMA_DC_OFF 376 +#define HUFF_CHROMA_AC_OFF 409 + +/* Default tables from JPEG ITU-T.81 + * (ISO/IEC 10918-1) Annex K.3, I + */ +static const unsigned char luma_q_table[] = { + 0x10, 0x0b, 0x0a, 0x10, 0x7c, 0x8c, 0x97, 0xa1, + 0x0c, 0x0c, 0x0e, 0x13, 0x7e, 0x9e, 0xa0, 0x9b, + 0x0e, 0x0d, 0x10, 0x18, 0x8c, 0x9d, 0xa9, 0x9c, + 0x0e, 0x11, 0x16, 0x1d, 0x97, 0xbb, 0xb4, 0xa2, + 0x12, 0x16, 0x25, 0x38, 0xa8, 0x6d, 0x67, 0xb1, + 0x18, 0x23, 0x37, 0x40, 0xb5, 0x68, 0x71, 0xc0, + 0x31, 0x40, 0x4e, 0x57, 0x67, 0x79, 0x78, 0x65, + 0x48, 0x5c, 0x5f, 0x62, 0x70, 0x64, 0x67, 0xc7, +}; + +static const unsigned char chroma_q_table[] = { + 0x11, 0x12, 0x18, 0x2f, 0x63, 0x63, 0x63, 0x63, + 0x12, 0x15, 0x1a, 0x42, 0x63, 0x63, 0x63, 0x63, + 0x18, 0x1a, 0x38, 0x63, 0x63, 0x63, 0x63, 0x63, + 0x2f, 0x42, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, + 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, + 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, + 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, + 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63 +}; + +/* Huffman tables are shared with CODA */ +static const unsigned char luma_dc_table[] = { + 0x00, 0x01, 0x05, 0x01, 0x01, 0x01, 0x01, 0x01, + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0a, 0x0b, +}; + +static const unsigned char chroma_dc_table[] = { + 0x00, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, + 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0a, 0x0b, +}; + +static const unsigned char luma_ac_table[] = { + 0x00, 0x02, 0x01, 0x03, 0x03, 0x02, 0x04, 0x03, + 0x05, 0x05, 0x04, 0x04, 0x00, 0x00, 0x01, 0x7d, + 0x01, 0x02, 0x03, 0x00, 0x04, 0x11, 0x05, 0x12, + 0x21, 0x31, 0x41, 0x06, 0x13, 0x51, 0x61, 0x07, + 0x22, 0x71, 0x14, 0x32, 0x81, 0x91, 0xa1, 0x08, + 0x23, 0x42, 0xb1, 0xc1, 0x15, 0x52, 0xd1, 0xf0, + 0x24, 0x33, 0x62, 0x72, 0x82, 0x09, 0x0a, 0x16, + 0x17, 0x18, 0x19, 0x1a, 0x25, 0x26, 0x27, 0x28, + 0x29, 0x2a, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, + 0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, + 0x4a, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, + 0x5a, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, + 0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, + 0x7a, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, + 0x8a, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, + 0x99, 0x9a, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, + 0xa8, 0xa9, 0xaa, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, + 0xb7, 0xb8, 0xb9, 0xba, 0xc2, 0xc3, 0xc4, 0xc5, + 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2, 0xd3, 0xd4, + 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda, 0xe1, 0xe2, + 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, 0xea, + 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, + 0xf9, 0xfa, +}; + +static const unsigned char chroma_ac_table[] = { + 0x00, 0x02, 0x01, 0x02, 0x04, 0x04, 0x03, 0x04, + 0x07, 0x05, 0x04, 0x04, 0x00, 0x01, 0x02, 0x77, + 0x00, 0x01, 0x02, 0x03, 0x11, 0x04, 0x05, 0x21, + 0x31, 0x06, 0x12, 0x41, 0x51, 0x07, 0x61, 0x71, + 0x13, 0x22, 0x32, 0x81, 0x08, 0x14, 0x42, 0x91, + 0xa1, 0xb1, 0xc1, 0x09, 0x23, 0x33, 0x52, 0xf0, + 0x15, 0x62, 0x72, 0xd1, 0x0a, 0x16, 0x24, 0x34, + 0xe1, 0x25, 0xf1, 0x17, 0x18, 0x19, 0x1a, 0x26, + 0x27, 0x28, 0x29, 0x2a, 0x35, 0x36, 0x37, 0x38, + 0x39, 0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, + 0x49, 0x4a, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, + 0x59, 0x5a, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, + 0x69, 0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, + 0x79, 0x7a, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, + 0x88, 0x89, 0x8a, 0x92, 0x93, 0x94, 0x95, 0x96, + 0x97, 0x98, 0x99, 0x9a, 0xa2, 0xa3, 0xa4, 0xa5, + 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xb2, 0xb3, 0xb4, + 0xb5, 0xb6, 0xb7, 0xb8, 0xb9, 0xba, 0xc2, 0xc3, + 0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2, + 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda, + 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, + 0xea, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, + 0xf9, 0xfa, +}; + +/* For simplicity, we keep a pre-formatted JPEG header, + * and we'll use fixed offsets to change the width, height + * quantization tables, etc. + */ +static const unsigned char rockchip_vpu_jpeg_header[JPEG_HEADER_SIZE] = { + /* SOI */ + 0xff, 0xd8, + + /* DQT */ + 0xff, 0xdb, 0x00, 0x84, + + 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + + 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + + /* SOF */ + 0xff, 0xc0, 0x00, 0x11, 0x08, 0x00, 0xf0, 0x01, + 0x40, 0x03, 0x01, 0x22, 0x00, 0x02, 0x11, 0x01, + 0x03, 0x11, 0x01, + + /* DHT */ + 0xff, 0xc4, 0x00, 0x1f, 0x00, + + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + /* DHT */ + 0xff, 0xc4, 0x00, 0xb5, 0x10, + + 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + + /* DHT */ + 0xff, 0xc4, 0x00, 0x1f, 0x01, + + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + /* DHT */ + 0xff, 0xc4, 0x00, 0xb5, 0x11, + + 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + + /* SOS */ + 0xff, 0xda, 0x00, 0x0c, 0x03, 0x01, 0x00, 0x02, + 0x11, 0x03, 0x11, 0x00, 0x3f, 0x00, +}; + +static void +jpeg_scale_quant_table(unsigned char *q_tab, + const unsigned char *tab, int scale) +{ + unsigned int temp; + int i; + + for (i = 0; i < 64; i++) { + temp = DIV_ROUND_CLOSEST((unsigned int)tab[i] * scale, 100); + if (temp <= 0) + temp = 1; + if (temp > 255) + temp = 255; + q_tab[i] = (unsigned char)temp; + } +} + +static void jpeg_set_quality(unsigned char *buffer, int quality) +{ + int scale; + + /* + * Non-linear scaling factor: + * [5,50] -> [1000..100], [51,100] -> [98..0] + */ + if (quality < 50) + scale = 5000 / quality; + else + scale = 200 - 2 * quality; + + jpeg_scale_quant_table(buffer + LUMA_QUANT_OFF, + luma_q_table, scale); + jpeg_scale_quant_table(buffer + CHROMA_QUANT_OFF, + chroma_q_table, scale); +} + +unsigned char * +rockchip_vpu_jpeg_get_qtable(struct rockchip_vpu_jpeg_ctx *ctx, int index) +{ + if (index == 0) + return ctx->buffer + LUMA_QUANT_OFF; + return ctx->buffer + CHROMA_QUANT_OFF; +} + +void rockchip_vpu_jpeg_header_assemble(struct rockchip_vpu_jpeg_ctx *ctx) +{ + char *buf = ctx->buffer; + + memcpy(buf, rockchip_vpu_jpeg_header, + sizeof(rockchip_vpu_jpeg_header)); + + buf[HEIGHT_OFF + 0] = ctx->height >> 8; + buf[HEIGHT_OFF + 1] = ctx->height; + buf[WIDTH_OFF + 0] = ctx->width >> 8; + buf[WIDTH_OFF + 1] = ctx->width; + + memcpy(buf + HUFF_LUMA_DC_OFF, luma_dc_table, sizeof(luma_dc_table)); + memcpy(buf + HUFF_LUMA_AC_OFF, luma_ac_table, sizeof(luma_ac_table)); + memcpy(buf + HUFF_CHROMA_DC_OFF, chroma_dc_table, + sizeof(chroma_dc_table)); + memcpy(buf + HUFF_CHROMA_AC_OFF, chroma_ac_table, + sizeof(chroma_ac_table)); + + jpeg_set_quality(buf, ctx->quality); +} diff --git a/drivers/staging/media/rockchip/vpu/rockchip_vpu_jpeg.h b/drivers/staging/media/rockchip/vpu/rockchip_vpu_jpeg.h new file mode 100644 index 000000000000..72645d8e2ade --- /dev/null +++ b/drivers/staging/media/rockchip/vpu/rockchip_vpu_jpeg.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#define JPEG_HEADER_SIZE 601 + +struct rockchip_vpu_jpeg_ctx { + int width; + int height; + int quality; + unsigned char *buffer; +}; + +unsigned char * +rockchip_vpu_jpeg_get_qtable(struct rockchip_vpu_jpeg_ctx *ctx, int index); +void rockchip_vpu_jpeg_header_assemble(struct rockchip_vpu_jpeg_ctx *ctx); diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c index c912c70b3ef7..ff11cbeba205 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus.c @@ -72,10 +72,11 @@ static int cedrus_init_ctrls(struct cedrus_dev *dev, struct cedrus_ctx *ctx) ctrl_size = sizeof(ctrl) * CEDRUS_CONTROLS_COUNT + 1; ctx->ctrls = kzalloc(ctrl_size, GFP_KERNEL); - memset(ctx->ctrls, 0, ctrl_size); + if (!ctx->ctrls) + return -ENOMEM; for (i = 0; i < CEDRUS_CONTROLS_COUNT; i++) { - struct v4l2_ctrl_config cfg = { 0 }; + struct v4l2_ctrl_config cfg = {}; cfg.elem_size = cedrus_controls[i].elem_size; cfg.id = cedrus_controls[i].id; @@ -279,7 +280,6 @@ static int cedrus_probe(struct platform_device *pdev) dev->dec_ops[CEDRUS_CODEC_MPEG2] = &cedrus_dec_ops_mpeg2; mutex_init(&dev->dev_mutex); - spin_lock_init(&dev->irq_lock); ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev); if (ret) { @@ -388,6 +388,14 @@ static const struct cedrus_variant sun8i_h3_cedrus_variant = { .capabilities = CEDRUS_CAPABILITY_UNTILED, }; +static const struct cedrus_variant sun50i_a64_cedrus_variant = { + .capabilities = CEDRUS_CAPABILITY_UNTILED, +}; + +static const struct cedrus_variant sun50i_h5_cedrus_variant = { + .capabilities = CEDRUS_CAPABILITY_UNTILED, +}; + static const struct of_device_id cedrus_dt_match[] = { { .compatible = "allwinner,sun4i-a10-video-engine", @@ -409,6 +417,14 @@ static const struct of_device_id cedrus_dt_match[] = { .compatible = "allwinner,sun8i-h3-video-engine", .data = &sun8i_h3_cedrus_variant, }, + { + .compatible = "allwinner,sun50i-a64-video-engine", + .data = &sun50i_a64_cedrus_variant, + }, + { + .compatible = "allwinner,sun50i-h5-video-engine", + .data = &sun50i_h5_cedrus_variant, + }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, cedrus_dt_match); @@ -418,7 +434,6 @@ static struct platform_driver cedrus_driver = { .remove = cedrus_remove, .driver = { .name = CEDRUS_NAME, - .owner = THIS_MODULE, .of_match_table = of_match_ptr(cedrus_dt_match), }, }; diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h index 3f61248c57ac..3acfdcf83691 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus.h +++ b/drivers/staging/media/sunxi/cedrus/cedrus.h @@ -105,8 +105,6 @@ struct cedrus_dev { /* Device file mutex */ struct mutex dev_mutex; - /* Interrupt spinlock */ - spinlock_t irq_lock; void __iomem *base; diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c index e40180a33951..591d191d4286 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c @@ -26,9 +26,8 @@ void cedrus_device_run(void *priv) { struct cedrus_ctx *ctx = priv; struct cedrus_dev *dev = ctx->dev; - struct cedrus_run run = { 0 }; + struct cedrus_run run = {}; struct media_request *src_req; - unsigned long flags; run.src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); run.dst = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx); @@ -39,8 +38,6 @@ void cedrus_device_run(void *priv) if (src_req) v4l2_ctrl_request_setup(src_req, &ctx->hdl); - spin_lock_irqsave(&ctx->dev->irq_lock, flags); - switch (ctx->src_fmt.pixelformat) { case V4L2_PIX_FMT_MPEG2_SLICE: run.mpeg2.slice_params = cedrus_find_control_data(ctx, @@ -55,16 +52,10 @@ void cedrus_device_run(void *priv) dev->dec_ops[ctx->current_codec]->setup(ctx, &run); - spin_unlock_irqrestore(&ctx->dev->irq_lock, flags); - /* Complete request(s) controls if needed. */ if (src_req) v4l2_ctrl_request_complete(src_req, &ctx->hdl); - spin_lock_irqsave(&ctx->dev->irq_lock, flags); - dev->dec_ops[ctx->current_codec]->trigger(ctx); - - spin_unlock_irqrestore(&ctx->dev->irq_lock, flags); } diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c index 07520a2ce179..300339fee1bc 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c @@ -98,23 +98,6 @@ void cedrus_dst_format_set(struct cedrus_dev *dev, } } -static irqreturn_t cedrus_bh(int irq, void *data) -{ - struct cedrus_dev *dev = data; - struct cedrus_ctx *ctx; - - ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev); - if (!ctx) { - v4l2_err(&dev->v4l2_dev, - "Instance released before the end of transaction\n"); - return IRQ_HANDLED; - } - - v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx); - - return IRQ_HANDLED; -} - static irqreturn_t cedrus_irq(int irq, void *data) { struct cedrus_dev *dev = data; @@ -122,24 +105,17 @@ static irqreturn_t cedrus_irq(int irq, void *data) struct vb2_v4l2_buffer *src_buf, *dst_buf; enum vb2_buffer_state state; enum cedrus_irq_status status; - unsigned long flags; - - spin_lock_irqsave(&dev->irq_lock, flags); ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev); if (!ctx) { v4l2_err(&dev->v4l2_dev, "Instance released before the end of transaction\n"); - spin_unlock_irqrestore(&dev->irq_lock, flags); - return IRQ_NONE; } status = dev->dec_ops[ctx->current_codec]->irq_status(ctx); - if (status == CEDRUS_IRQ_NONE) { - spin_unlock_irqrestore(&dev->irq_lock, flags); + if (status == CEDRUS_IRQ_NONE) return IRQ_NONE; - } dev->dec_ops[ctx->current_codec]->irq_disable(ctx); dev->dec_ops[ctx->current_codec]->irq_clear(ctx); @@ -150,8 +126,6 @@ static irqreturn_t cedrus_irq(int irq, void *data) if (!src_buf || !dst_buf) { v4l2_err(&dev->v4l2_dev, "Missing source and/or destination buffers\n"); - spin_unlock_irqrestore(&dev->irq_lock, flags); - return IRQ_HANDLED; } @@ -163,9 +137,9 @@ static irqreturn_t cedrus_irq(int irq, void *data) v4l2_m2m_buf_done(src_buf, state); v4l2_m2m_buf_done(dst_buf, state); - spin_unlock_irqrestore(&dev->irq_lock, flags); + v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx); - return IRQ_WAKE_THREAD; + return IRQ_HANDLED; } int cedrus_hw_probe(struct cedrus_dev *dev) @@ -187,9 +161,8 @@ int cedrus_hw_probe(struct cedrus_dev *dev) return irq_dec; } - ret = devm_request_threaded_irq(dev->dev, irq_dec, cedrus_irq, - cedrus_bh, 0, dev_name(dev->dev), - dev); + ret = devm_request_irq(dev->dev, irq_dec, cedrus_irq, + 0, dev_name(dev->dev), dev); if (ret) { v4l2_err(&dev->v4l2_dev, "Failed to request IRQ\n"); diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_video.c b/drivers/staging/media/sunxi/cedrus/cedrus_video.c index 5c5fce678b93..8721b4a7d496 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c @@ -380,18 +380,13 @@ static void cedrus_queue_cleanup(struct vb2_queue *vq, u32 state) { struct cedrus_ctx *ctx = vb2_get_drv_priv(vq); struct vb2_v4l2_buffer *vbuf; - unsigned long flags; for (;;) { - spin_lock_irqsave(&ctx->dev->irq_lock, flags); - if (V4L2_TYPE_IS_OUTPUT(vq->type)) vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); else vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); - spin_unlock_irqrestore(&ctx->dev->irq_lock, flags); - if (!vbuf) return; diff --git a/drivers/staging/media/tegra-vde/tegra-vde.c b/drivers/staging/media/tegra-vde/tegra-vde.c index 6f06061a40d9..aa6c6bba961e 100644 --- a/drivers/staging/media/tegra-vde/tegra-vde.c +++ b/drivers/staging/media/tegra-vde/tegra-vde.c @@ -35,14 +35,6 @@ #define BSE_ICMDQUE_EMPTY BIT(3) #define BSE_DMA_BUSY BIT(23) -#define VDE_WR(__data, __addr) \ -do { \ - dev_dbg(vde->miscdev.parent, \ - "%s: %d: 0x%08X => " #__addr ")\n", \ - __func__, __LINE__, (u32)(__data)); \ - writel_relaxed(__data, __addr); \ -} while (0) - struct video_frame { struct dma_buf_attachment *y_dmabuf_attachment; struct dma_buf_attachment *cb_dmabuf_attachment; @@ -81,12 +73,66 @@ struct tegra_vde { u32 *iram; }; +static __maybe_unused char const * +tegra_vde_reg_base_name(struct tegra_vde *vde, void __iomem *base) +{ + if (vde->sxe == base) + return "SXE"; + + if (vde->bsev == base) + return "BSEV"; + + if (vde->mbe == base) + return "MBE"; + + if (vde->ppe == base) + return "PPE"; + + if (vde->mce == base) + return "MCE"; + + if (vde->tfe == base) + return "TFE"; + + if (vde->ppb == base) + return "PPB"; + + if (vde->vdma == base) + return "VDMA"; + + if (vde->frameid == base) + return "FRAMEID"; + + return "???"; +} + +#define CREATE_TRACE_POINTS +#include "trace.h" + +static void tegra_vde_writel(struct tegra_vde *vde, + u32 value, void __iomem *base, u32 offset) +{ + trace_vde_writel(vde, base, offset, value); + + writel_relaxed(value, base + offset); +} + +static u32 tegra_vde_readl(struct tegra_vde *vde, + void __iomem *base, u32 offset) +{ + u32 value = readl_relaxed(base + offset); + + trace_vde_readl(vde, base, offset, value); + + return value; +} + static void tegra_vde_set_bits(struct tegra_vde *vde, - u32 mask, void __iomem *regs) + u32 mask, void __iomem *base, u32 offset) { - u32 value = readl_relaxed(regs); + u32 value = tegra_vde_readl(vde, base, offset); - VDE_WR(value | mask, regs); + tegra_vde_writel(vde, value | mask, base, offset); } static int tegra_vde_wait_mbe(struct tegra_vde *vde) @@ -107,8 +153,8 @@ static int tegra_vde_setup_mbe_frame_idx(struct tegra_vde *vde, unsigned int idx; int err; - VDE_WR(0xD0000000 | (0 << 23), vde->mbe + 0x80); - VDE_WR(0xD0200000 | (0 << 23), vde->mbe + 0x80); + tegra_vde_writel(vde, 0xD0000000 | (0 << 23), vde->mbe, 0x80); + tegra_vde_writel(vde, 0xD0200000 | (0 << 23), vde->mbe, 0x80); err = tegra_vde_wait_mbe(vde); if (err) @@ -118,8 +164,10 @@ static int tegra_vde_setup_mbe_frame_idx(struct tegra_vde *vde, return 0; for (idx = 0, frame_idx = 1; idx < refs_nb; idx++, frame_idx++) { - VDE_WR(0xD0000000 | (frame_idx << 23), vde->mbe + 0x80); - VDE_WR(0xD0200000 | (frame_idx << 23), vde->mbe + 0x80); + tegra_vde_writel(vde, 0xD0000000 | (frame_idx << 23), + vde->mbe, 0x80); + tegra_vde_writel(vde, 0xD0200000 | (frame_idx << 23), + vde->mbe, 0x80); frame_idx_enb_mask |= frame_idx << (6 * (idx % 4)); @@ -128,7 +176,7 @@ static int tegra_vde_setup_mbe_frame_idx(struct tegra_vde *vde, value |= (idx >> 2) << 24; value |= frame_idx_enb_mask; - VDE_WR(value, vde->mbe + 0x80); + tegra_vde_writel(vde, value, vde->mbe, 0x80); err = tegra_vde_wait_mbe(vde); if (err) @@ -143,8 +191,10 @@ static int tegra_vde_setup_mbe_frame_idx(struct tegra_vde *vde, static void tegra_vde_mbe_set_0xa_reg(struct tegra_vde *vde, int reg, u32 val) { - VDE_WR(0xA0000000 | (reg << 24) | (val & 0xFFFF), vde->mbe + 0x80); - VDE_WR(0xA0000000 | ((reg + 1) << 24) | (val >> 16), vde->mbe + 0x80); + tegra_vde_writel(vde, 0xA0000000 | (reg << 24) | (val & 0xFFFF), + vde->mbe, 0x80); + tegra_vde_writel(vde, 0xA0000000 | ((reg + 1) << 24) | (val >> 16), + vde->mbe, 0x80); } static int tegra_vde_wait_bsev(struct tegra_vde *vde, bool wait_dma) @@ -183,7 +233,7 @@ static int tegra_vde_wait_bsev(struct tegra_vde *vde, bool wait_dma) static int tegra_vde_push_to_bsev_icmdqueue(struct tegra_vde *vde, u32 value, bool wait_dma) { - VDE_WR(value, vde->bsev + ICMDQUE_WR); + tegra_vde_writel(vde, value, vde->bsev, ICMDQUE_WR); return tegra_vde_wait_bsev(vde, wait_dma); } @@ -199,11 +249,11 @@ static void tegra_vde_setup_frameid(struct tegra_vde *vde, u32 value1 = frame ? ((mbs_width << 16) | mbs_height) : 0; u32 value2 = frame ? ((((mbs_width + 1) >> 1) << 6) | 1) : 0; - VDE_WR(y_addr >> 8, vde->frameid + 0x000 + frameid * 4); - VDE_WR(cb_addr >> 8, vde->frameid + 0x100 + frameid * 4); - VDE_WR(cr_addr >> 8, vde->frameid + 0x180 + frameid * 4); - VDE_WR(value1, vde->frameid + 0x080 + frameid * 4); - VDE_WR(value2, vde->frameid + 0x280 + frameid * 4); + tegra_vde_writel(vde, y_addr >> 8, vde->frameid, 0x000 + frameid * 4); + tegra_vde_writel(vde, cb_addr >> 8, vde->frameid, 0x100 + frameid * 4); + tegra_vde_writel(vde, cr_addr >> 8, vde->frameid, 0x180 + frameid * 4); + tegra_vde_writel(vde, value1, vde->frameid, 0x080 + frameid * 4); + tegra_vde_writel(vde, value2, vde->frameid, 0x280 + frameid * 4); } static void tegra_setup_frameidx(struct tegra_vde *vde, @@ -228,8 +278,7 @@ static void tegra_vde_setup_iram_entry(struct tegra_vde *vde, { u32 *iram_tables = vde->iram; - dev_dbg(vde->miscdev.parent, "IRAM table %u: row %u: 0x%08X 0x%08X\n", - table, row, value1, value2); + trace_vde_setup_iram_entry(table, row, value1, value2); iram_tables[0x20 * table + row * 2] = value1; iram_tables[0x20 * table + row * 2 + 1] = value2; @@ -245,10 +294,7 @@ static void tegra_vde_setup_iram_tables(struct tegra_vde *vde, int with_later_poc_nb; unsigned int i, k; - dev_dbg(vde->miscdev.parent, "DPB: Frame 0: frame_num = %d\n", - dpb_frames[0].frame_num); - - dev_dbg(vde->miscdev.parent, "REF L0:\n"); + trace_vde_ref_l0(dpb_frames[0].frame_num); for (i = 0; i < 16; i++) { if (i < ref_frames_nb) { @@ -260,11 +306,6 @@ static void tegra_vde_setup_iram_tables(struct tegra_vde *vde, value |= !(frame->flags & FLAG_B_FRAME) << 25; value |= 1 << 24; value |= frame->frame_num; - - dev_dbg(vde->miscdev.parent, - "\tFrame %d: frame_num = %d B_frame = %d\n", - i + 1, frame->frame_num, - (frame->flags & FLAG_B_FRAME)); } else { aux_addr = 0x6ADEAD00; value = 0; @@ -284,9 +325,7 @@ static void tegra_vde_setup_iram_tables(struct tegra_vde *vde, with_later_poc_nb = ref_frames_nb - with_earlier_poc_nb; - dev_dbg(vde->miscdev.parent, - "REF L1: with_later_poc_nb %d with_earlier_poc_nb %d\n", - with_later_poc_nb, with_earlier_poc_nb); + trace_vde_ref_l1(with_later_poc_nb, with_earlier_poc_nb); for (i = 0, k = with_earlier_poc_nb; i < with_later_poc_nb; i++, k++) { frame = &dpb_frames[k + 1]; @@ -298,10 +337,6 @@ static void tegra_vde_setup_iram_tables(struct tegra_vde *vde, value |= 1 << 24; value |= frame->frame_num; - dev_dbg(vde->miscdev.parent, - "\tFrame %d: frame_num = %d\n", - k + 1, frame->frame_num); - tegra_vde_setup_iram_entry(vde, 2, i, value, aux_addr); } @@ -315,10 +350,6 @@ static void tegra_vde_setup_iram_tables(struct tegra_vde *vde, value |= 1 << 24; value |= frame->frame_num; - dev_dbg(vde->miscdev.parent, - "\tFrame %d: frame_num = %d\n", - k + 1, frame->frame_num); - tegra_vde_setup_iram_entry(vde, 2, i, value, aux_addr); } } @@ -334,32 +365,32 @@ static int tegra_vde_setup_hw_context(struct tegra_vde *vde, u32 value; int err; - tegra_vde_set_bits(vde, 0x000A, vde->sxe + 0xF0); - tegra_vde_set_bits(vde, 0x000B, vde->bsev + CMDQUE_CONTROL); - tegra_vde_set_bits(vde, 0x8002, vde->mbe + 0x50); - tegra_vde_set_bits(vde, 0x000A, vde->mbe + 0xA0); - tegra_vde_set_bits(vde, 0x000A, vde->ppe + 0x14); - tegra_vde_set_bits(vde, 0x000A, vde->ppe + 0x28); - tegra_vde_set_bits(vde, 0x0A00, vde->mce + 0x08); - tegra_vde_set_bits(vde, 0x000A, vde->tfe + 0x00); - tegra_vde_set_bits(vde, 0x0005, vde->vdma + 0x04); - - VDE_WR(0x00000000, vde->vdma + 0x1C); - VDE_WR(0x00000000, vde->vdma + 0x00); - VDE_WR(0x00000007, vde->vdma + 0x04); - VDE_WR(0x00000007, vde->frameid + 0x200); - VDE_WR(0x00000005, vde->tfe + 0x04); - VDE_WR(0x00000000, vde->mbe + 0x84); - VDE_WR(0x00000010, vde->sxe + 0x08); - VDE_WR(0x00000150, vde->sxe + 0x54); - VDE_WR(0x0000054C, vde->sxe + 0x58); - VDE_WR(0x00000E34, vde->sxe + 0x5C); - VDE_WR(0x063C063C, vde->mce + 0x10); - VDE_WR(0x0003FC00, vde->bsev + INTR_STATUS); - VDE_WR(0x0000150D, vde->bsev + BSE_CONFIG); - VDE_WR(0x00000100, vde->bsev + BSE_INT_ENB); - VDE_WR(0x00000000, vde->bsev + 0x98); - VDE_WR(0x00000060, vde->bsev + 0x9C); + tegra_vde_set_bits(vde, 0x000A, vde->sxe, 0xF0); + tegra_vde_set_bits(vde, 0x000B, vde->bsev, CMDQUE_CONTROL); + tegra_vde_set_bits(vde, 0x8002, vde->mbe, 0x50); + tegra_vde_set_bits(vde, 0x000A, vde->mbe, 0xA0); + tegra_vde_set_bits(vde, 0x000A, vde->ppe, 0x14); + tegra_vde_set_bits(vde, 0x000A, vde->ppe, 0x28); + tegra_vde_set_bits(vde, 0x0A00, vde->mce, 0x08); + tegra_vde_set_bits(vde, 0x000A, vde->tfe, 0x00); + tegra_vde_set_bits(vde, 0x0005, vde->vdma, 0x04); + + tegra_vde_writel(vde, 0x00000000, vde->vdma, 0x1C); + tegra_vde_writel(vde, 0x00000000, vde->vdma, 0x00); + tegra_vde_writel(vde, 0x00000007, vde->vdma, 0x04); + tegra_vde_writel(vde, 0x00000007, vde->frameid, 0x200); + tegra_vde_writel(vde, 0x00000005, vde->tfe, 0x04); + tegra_vde_writel(vde, 0x00000000, vde->mbe, 0x84); + tegra_vde_writel(vde, 0x00000010, vde->sxe, 0x08); + tegra_vde_writel(vde, 0x00000150, vde->sxe, 0x54); + tegra_vde_writel(vde, 0x0000054C, vde->sxe, 0x58); + tegra_vde_writel(vde, 0x00000E34, vde->sxe, 0x5C); + tegra_vde_writel(vde, 0x063C063C, vde->mce, 0x10); + tegra_vde_writel(vde, 0x0003FC00, vde->bsev, INTR_STATUS); + tegra_vde_writel(vde, 0x0000150D, vde->bsev, BSE_CONFIG); + tegra_vde_writel(vde, 0x00000100, vde->bsev, BSE_INT_ENB); + tegra_vde_writel(vde, 0x00000000, vde->bsev, 0x98); + tegra_vde_writel(vde, 0x00000060, vde->bsev, 0x9C); memset(vde->iram + 128, 0, macroblocks_nb / 2); @@ -376,13 +407,13 @@ static int tegra_vde_setup_hw_context(struct tegra_vde *vde, */ wmb(); - VDE_WR(0x00000000, vde->bsev + 0x8C); - VDE_WR(bitstream_data_addr + bitstream_data_size, - vde->bsev + 0x54); + tegra_vde_writel(vde, 0x00000000, vde->bsev, 0x8C); + tegra_vde_writel(vde, bitstream_data_addr + bitstream_data_size, + vde->bsev, 0x54); value = ctx->pic_width_in_mbs << 11 | ctx->pic_height_in_mbs << 3; - VDE_WR(value, vde->bsev + 0x88); + tegra_vde_writel(vde, value, vde->bsev, 0x88); err = tegra_vde_wait_bsev(vde, false); if (err) @@ -417,7 +448,7 @@ static int tegra_vde_setup_hw_context(struct tegra_vde *vde, value |= ctx->pic_width_in_mbs << 11; value |= ctx->pic_height_in_mbs << 3; - VDE_WR(value, vde->sxe + 0x10); + tegra_vde_writel(vde, value, vde->sxe, 0x10); value = !ctx->baseline_profile << 17; value |= ctx->level_idc << 13; @@ -425,54 +456,54 @@ static int tegra_vde_setup_hw_context(struct tegra_vde *vde, value |= ctx->pic_order_cnt_type << 5; value |= ctx->log2_max_frame_num; - VDE_WR(value, vde->sxe + 0x40); + tegra_vde_writel(vde, value, vde->sxe, 0x40); value = ctx->pic_init_qp << 25; value |= !!(ctx->deblocking_filter_control_present_flag) << 2; value |= !!ctx->pic_order_present_flag; - VDE_WR(value, vde->sxe + 0x44); + tegra_vde_writel(vde, value, vde->sxe, 0x44); value = ctx->chroma_qp_index_offset; value |= ctx->num_ref_idx_l0_active_minus1 << 5; value |= ctx->num_ref_idx_l1_active_minus1 << 10; value |= !!ctx->constrained_intra_pred_flag << 15; - VDE_WR(value, vde->sxe + 0x48); + tegra_vde_writel(vde, value, vde->sxe, 0x48); value = 0x0C000000; value |= !!(dpb_frames[0].flags & FLAG_B_FRAME) << 24; - VDE_WR(value, vde->sxe + 0x4C); + tegra_vde_writel(vde, value, vde->sxe, 0x4C); value = 0x03800000; value |= bitstream_data_size & GENMASK(19, 15); - VDE_WR(value, vde->sxe + 0x68); + tegra_vde_writel(vde, value, vde->sxe, 0x68); - VDE_WR(bitstream_data_addr, vde->sxe + 0x6C); + tegra_vde_writel(vde, bitstream_data_addr, vde->sxe, 0x6C); value = 0x10000005; value |= ctx->pic_width_in_mbs << 11; value |= ctx->pic_height_in_mbs << 3; - VDE_WR(value, vde->mbe + 0x80); + tegra_vde_writel(vde, value, vde->mbe, 0x80); value = 0x26800000; value |= ctx->level_idc << 4; value |= !ctx->baseline_profile << 1; value |= !!ctx->direct_8x8_inference_flag; - VDE_WR(value, vde->mbe + 0x80); + tegra_vde_writel(vde, value, vde->mbe, 0x80); - VDE_WR(0xF4000001, vde->mbe + 0x80); - VDE_WR(0x20000000, vde->mbe + 0x80); - VDE_WR(0xF4000101, vde->mbe + 0x80); + tegra_vde_writel(vde, 0xF4000001, vde->mbe, 0x80); + tegra_vde_writel(vde, 0x20000000, vde->mbe, 0x80); + tegra_vde_writel(vde, 0xF4000101, vde->mbe, 0x80); value = 0x20000000; value |= ctx->chroma_qp_index_offset << 8; - VDE_WR(value, vde->mbe + 0x80); + tegra_vde_writel(vde, value, vde->mbe, 0x80); err = tegra_vde_setup_mbe_frame_idx(vde, ctx->dpb_frames_nb - 1, @@ -494,7 +525,7 @@ static int tegra_vde_setup_hw_context(struct tegra_vde *vde, if (!ctx->baseline_profile) value |= !!(dpb_frames[0].flags & FLAG_REFERENCE) << 1; - VDE_WR(value, vde->mbe + 0x80); + tegra_vde_writel(vde, value, vde->mbe, 0x80); err = tegra_vde_wait_mbe(vde); if (err) { @@ -510,8 +541,9 @@ static void tegra_vde_decode_frame(struct tegra_vde *vde, { reinit_completion(&vde->decode_completion); - VDE_WR(0x00000001, vde->bsev + 0x8C); - VDE_WR(0x20000000 | (macroblocks_nb - 1), vde->sxe + 0x00); + tegra_vde_writel(vde, 0x00000001, vde->bsev, 0x8C); + tegra_vde_writel(vde, 0x20000000 | (macroblocks_nb - 1), + vde->sxe, 0x00); } static void tegra_vde_detach_and_put_dmabuf(struct dma_buf_attachment *a, @@ -883,8 +915,8 @@ static int tegra_vde_ioctl_decode_h264(struct tegra_vde *vde, timeout = wait_for_completion_interruptible_timeout( &vde->decode_completion, msecs_to_jiffies(1000)); if (timeout == 0) { - bsev_ptr = readl_relaxed(vde->bsev + 0x10); - macroblocks_nb = readl_relaxed(vde->sxe + 0xC8) & 0x1FFF; + bsev_ptr = tegra_vde_readl(vde, vde->bsev, 0x10); + macroblocks_nb = tegra_vde_readl(vde, vde->sxe, 0xC8) & 0x1FFF; read_bytes = bsev_ptr ? bsev_ptr - bitstream_data_addr : 0; dev_err(dev, "Decoding failed: read 0x%X bytes, %u macroblocks parsed\n", @@ -962,7 +994,7 @@ static irqreturn_t tegra_vde_isr(int irq, void *data) if (completion_done(&vde->decode_completion)) return IRQ_NONE; - tegra_vde_set_bits(vde, 0, vde->frameid + 0x208); + tegra_vde_set_bits(vde, 0, vde->frameid, 0x208); complete(&vde->decode_completion); return IRQ_HANDLED; diff --git a/drivers/staging/media/tegra-vde/trace.h b/drivers/staging/media/tegra-vde/trace.h new file mode 100644 index 000000000000..85e2f7e2d4d0 --- /dev/null +++ b/drivers/staging/media/tegra-vde/trace.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#undef TRACE_SYSTEM +#define TRACE_SYSTEM tegra_vde + +#if !defined(TEGRA_VDE_TRACE_H) || defined(TRACE_HEADER_MULTI_READ) +#define TEGRA_VDE_TRACE_H + +#include <linux/tracepoint.h> + +DECLARE_EVENT_CLASS(register_access, + TP_PROTO(struct tegra_vde *vde, void __iomem *base, + u32 offset, u32 value), + TP_ARGS(vde, base, offset, value), + TP_STRUCT__entry( + __string(hw_name, tegra_vde_reg_base_name(vde, base)) + __field(u32, offset) + __field(u32, value) + ), + TP_fast_assign( + __assign_str(hw_name, tegra_vde_reg_base_name(vde, base)); + __entry->offset = offset; + __entry->value = value; + ), + TP_printk("%s:0x%03x 0x%08x", __get_str(hw_name), __entry->offset, + __entry->value) +); + +DEFINE_EVENT(register_access, vde_writel, + TP_PROTO(struct tegra_vde *vde, void __iomem *base, + u32 offset, u32 value), + TP_ARGS(vde, base, offset, value)); +DEFINE_EVENT(register_access, vde_readl, + TP_PROTO(struct tegra_vde *vde, void __iomem *base, + u32 offset, u32 value), + TP_ARGS(vde, base, offset, value)); + +TRACE_EVENT(vde_setup_iram_entry, + TP_PROTO(unsigned int table, unsigned int row, u32 value, u32 aux_addr), + TP_ARGS(table, row, value, aux_addr), + TP_STRUCT__entry( + __field(unsigned int, table) + __field(unsigned int, row) + __field(u32, value) + __field(u32, aux_addr) + ), + TP_fast_assign( + __entry->table = table; + __entry->row = row; + __entry->value = value; + __entry->aux_addr = aux_addr; + ), + TP_printk("[%u][%u] = { 0x%08x (flags = \"%s\", frame_num = %u); 0x%08x }", + __entry->table, __entry->row, __entry->value, + __print_flags(__entry->value, " ", { (1 << 25), "B" }), + __entry->value & 0x7FFFFF, __entry->aux_addr) +); + +TRACE_EVENT(vde_ref_l0, + TP_PROTO(unsigned int frame_num), + TP_ARGS(frame_num), + TP_STRUCT__entry( + __field(unsigned int, frame_num) + ), + TP_fast_assign( + __entry->frame_num = frame_num; + ), + TP_printk("REF L0: DPB: Frame 0: frame_num = %u", __entry->frame_num) +); + +TRACE_EVENT(vde_ref_l1, + TP_PROTO(unsigned int with_later_poc_nb, + unsigned int with_earlier_poc_nb), + TP_ARGS(with_later_poc_nb, with_earlier_poc_nb), + TP_STRUCT__entry( + __field(unsigned int, with_later_poc_nb) + __field(unsigned int, with_earlier_poc_nb) + ), + TP_fast_assign( + __entry->with_later_poc_nb = with_later_poc_nb; + __entry->with_earlier_poc_nb = with_earlier_poc_nb; + ), + TP_printk("REF L1: with_later_poc_nb %u, with_earlier_poc_nb %u", + __entry->with_later_poc_nb, __entry->with_earlier_poc_nb) +); + +#endif /* TEGRA_VDE_TRACE_H */ + +/* This part must be outside protection */ +#undef TRACE_INCLUDE_PATH +#define TRACE_INCLUDE_PATH ../../drivers/staging/media/tegra-vde +#define TRACE_INCLUDE_FILE trace +#include <trace/define_trace.h> |