diff options
| author |   Jerry Chuang <wlanfae@realtek.com> | 2009-05-21 22:16:02 -0700 |
|---|---|---|
| committer |   Greg Kroah-Hartman <gregkh@suse.de> | 2009-06-19 11:00:53 -0700 |
| commit | 5f53d8ca3d5d6afa55011e1e858a4bf255a3abf4 (patch) | |
| tree | 5dfc036b97b9e68336298a61384e86f619d361e8 /drivers | |
| parent | Staging: cpc-usb: fix build warnings (diff) | |
| download | linux-dev-5f53d8ca3d5d6afa55011e1e858a4bf255a3abf4.tar.xz linux-dev-5f53d8ca3d5d6afa55011e1e858a4bf255a3abf4.zip | |
Staging: add rtl8192SU wireless usb driver
Driver from Realtek for the Realtek RTL8192 USB wifi device
Based on the r8187 driver from Andrea Merello <andreamrl@tiscali.it> and
others.
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers')
86 files changed, 78441 insertions, 0 deletions
diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig index f9371ab9d080..07998730d8e7 100644 --- a/drivers/staging/Kconfig +++ b/drivers/staging/Kconfig @@ -85,6 +85,8 @@ source "drivers/staging/altpciechdma/Kconfig" source "drivers/staging/rtl8187se/Kconfig" +source "drivers/staging/rtl8192su/Kconfig" + source "drivers/staging/rspiusb/Kconfig" source "drivers/staging/mimio/Kconfig" diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile index d6bafe2ff9cf..8fb84310bb38 100644 --- a/drivers/staging/Makefile +++ b/drivers/staging/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_ASUS_OLED) += asus_oled/ obj-$(CONFIG_PANEL) += panel/ obj-$(CONFIG_ALTERA_PCIE_CHDMA) += altpciechdma/ obj-$(CONFIG_RTL8187SE) += rtl8187se/ +obj-$(CONFIG_RTL8192SU) += rtl8192su/ obj-$(CONFIG_USB_RSPI) += rspiusb/ obj-$(CONFIG_INPUT_MIMIO) += mimio/ obj-$(CONFIG_TRANZPORT) += frontier/ diff --git a/drivers/staging/rtl8192su/Kconfig b/drivers/staging/rtl8192su/Kconfig new file mode 100644 index 000000000000..4b5552c5926e --- /dev/null +++ b/drivers/staging/rtl8192su/Kconfig @@ -0,0 +1,6 @@ +config RTL8192SU + tristate "RealTek RTL8192SU Wireless LAN NIC driver" + depends on PCI + depends on WIRELESS_EXT && COMPAT_NET_DEV_OPS + default N + ---help--- diff --git a/drivers/staging/rtl8192su/Makefile b/drivers/staging/rtl8192su/Makefile new file mode 100644 index 000000000000..f010ab502a97 --- /dev/null +++ b/drivers/staging/rtl8192su/Makefile @@ -0,0 +1,66 @@ +NIC_SELECT = RTL8192SU + +EXTRA_CFLAGS += -std=gnu89 +EXTRA_CFLAGS += -O2 +EXTRA_CFLAGS += -mhard-float -DCONFIG_FORCE_HARD_FLOAT=y + +EXTRA_CFLAGS += -DJACKSON_NEW_RX +EXTRA_CFLAGS += -DTHOMAS_BEACON -DTHOMAS_TURBO +#EXTRA_CFLAGS += -DUSE_ONE_PIPE +EXTRA_CFLAGS += -DENABLE_DOT11D + +EXTRA_CFLAGS += -DRTL8192SU +EXTRA_CFLAGS += -DRTL8190_Download_Firmware_From_Header=1 +EXTRA_CFLAGS += -DRTL8192S_PREPARE_FOR_NORMAL_RELEASE +EXTRA_CFLAGS += -DRTL8192SU_DISABLE_IQK=1 + +#EXTRA_CFLAGS += -DEEPROM_OLD_FORMAT_SUPPORT + +#EXTRA_CFLAGS += -DUSB_RX_AGGREGATION_SUPPORT=0 +#EXTRA_CFLAGS += -DUSB_TX_DRIVER_AGGREGATION_ENABLE=0 +#EXTRA_CFLAGS += -DRTL8192SU_DISABLE_CCK_RATE=0 +EXTRA_CFLAGS += -DRTL8192S_DISABLE_FW_DM=0 +EXTRA_CFLAGS += -DDISABLE_BB_RF=0 +EXTRA_CFLAGS += -DRTL8192SU_USE_PARAM_TXPWR=0 +EXTRA_CFLAGS += -DRTL8192SU_FPGA_UNSPECIFIED_NETWORK=0 +#EXTRA_CFLAGS += -DRTL8192SU_FPGA_2MAC_VERIFICATION #=0 +EXTRA_CFLAGS += -DRTL8192SU_ASIC_VERIFICATION +EXTRA_CFLAGS += -DRTL8192SU_USB_PHY_TEST=0 + +#EXTRA_CFLAGS += -DMUTIPLE_BULK_OUT +EXTRA_CFLAGS += -DCONFIG_RTL8192_PM + +r8192s_usb-objs := \ + r8180_93cx6.o \ + r8192U_wx.o \ + r8192S_phy.o \ + r8192S_rtl6052.o \ + r8192S_rtl8225.o \ + r819xU_cmdpkt.o \ + r8192U_dm.o \ + r8192SU_HWImg.o \ + r8192S_firmware.o \ + r8192S_Efuse.o \ + r8192U_core.o \ + r8192U_pm.o + +ieee80211-rsl-objs := \ + ieee80211/ieee80211_rx.o \ + ieee80211/ieee80211_softmac.o \ + ieee80211/ieee80211_tx.o \ + ieee80211/ieee80211_wx.o \ + ieee80211/ieee80211_module.o \ + ieee80211/ieee80211_softmac_wx.o\ + ieee80211/rtl819x_HTProc.o \ + ieee80211/rtl819x_TSProc.o \ + ieee80211/rtl819x_BAProc.o \ + ieee80211/dot11d.o + +obj-$(CONFIG_RTL8192SU) += r8192s_usb.o +obj-$(CONFIG_RTL8192SU) += ieee80211-rsl.o +obj-$(CONFIG_RTL8192SU) += ieee80211/ieee80211_crypt.o +obj-$(CONFIG_RTL8192SU) += ieee80211/ieee80211_crypt_tkip.o +obj-$(CONFIG_RTL8192SU) += ieee80211/ieee80211_crypt_ccmp.o +obj-$(CONFIG_RTL8192SU) += ieee80211/ieee80211_crypt_wep.o + + diff --git a/drivers/staging/rtl8192su/authors b/drivers/staging/rtl8192su/authors new file mode 100644 index 000000000000..b08bbae39e72 --- /dev/null +++ b/drivers/staging/rtl8192su/authors @@ -0,0 +1 @@ +Andrea Merello <andreamrl@tiscali.it> diff --git a/drivers/staging/rtl8192su/dot11d.h b/drivers/staging/rtl8192su/dot11d.h new file mode 100644 index 000000000000..15b7a4ba37b6 --- /dev/null +++ b/drivers/staging/rtl8192su/dot11d.h @@ -0,0 +1,102 @@ +#ifndef __INC_DOT11D_H +#define __INC_DOT11D_H + +#ifdef ENABLE_DOT11D +#include "ieee80211.h" + +//#define ENABLE_DOT11D + +//#define DOT11D_MAX_CHNL_NUM 83 + +typedef struct _CHNL_TXPOWER_TRIPLE { + u8 FirstChnl; + u8 NumChnls; + u8 MaxTxPowerInDbm; +}CHNL_TXPOWER_TRIPLE, *PCHNL_TXPOWER_TRIPLE; + +typedef enum _DOT11D_STATE { + DOT11D_STATE_NONE = 0, + DOT11D_STATE_LEARNED, + DOT11D_STATE_DONE, +}DOT11D_STATE; + +typedef struct _RT_DOT11D_INFO { + //DECLARE_RT_OBJECT(RT_DOT11D_INFO); + + bool bEnabled; // dot11MultiDomainCapabilityEnabled + + u16 CountryIeLen; // > 0 if CountryIeBuf[] contains valid country information element. + u8 CountryIeBuf[MAX_IE_LEN]; + u8 CountryIeSrcAddr[6]; // Source AP of the country IE. + u8 CountryIeWatchdog; + + u8 channel_map[MAX_CHANNEL_NUMBER+1]; //!!!Value 0: Invalid, 1: Valid (active scan), 2: Valid (passive scan) + //u8 ChnlListLen; // #Bytes valid in ChnlList[]. + //u8 ChnlList[DOT11D_MAX_CHNL_NUM]; + u8 MaxTxPwrDbmList[MAX_CHANNEL_NUMBER+1]; + + DOT11D_STATE State; +}RT_DOT11D_INFO, *PRT_DOT11D_INFO; +#define eqMacAddr(a,b) ( ((a)[0]==(b)[0] && (a)[1]==(b)[1] && (a)[2]==(b)[2] && (a)[3]==(b)[3] && (a)[4]==(b)[4] && (a)[5]==(b)[5]) ? 1:0 ) +#define cpMacAddr(des,src) ((des)[0]=(src)[0],(des)[1]=(src)[1],(des)[2]=(src)[2],(des)[3]=(src)[3],(des)[4]=(src)[4],(des)[5]=(src)[5]) +#define GET_DOT11D_INFO(__pIeeeDev) ((PRT_DOT11D_INFO)((__pIeeeDev)->pDot11dInfo)) + +#define IS_DOT11D_ENABLE(__pIeeeDev) GET_DOT11D_INFO(__pIeeeDev)->bEnabled +#define IS_COUNTRY_IE_VALID(__pIeeeDev) (GET_DOT11D_INFO(__pIeeeDev)->CountryIeLen > 0) + +#define IS_EQUAL_CIE_SRC(__pIeeeDev, __pTa) eqMacAddr(GET_DOT11D_INFO(__pIeeeDev)->CountryIeSrcAddr, __pTa) +#define UPDATE_CIE_SRC(__pIeeeDev, __pTa) cpMacAddr(GET_DOT11D_INFO(__pIeeeDev)->CountryIeSrcAddr, __pTa) + +#define IS_COUNTRY_IE_CHANGED(__pIeeeDev, __Ie) \ + (((__Ie).Length == 0 || (__Ie).Length != GET_DOT11D_INFO(__pIeeeDev)->CountryIeLen) ? \ + FALSE : \ + (!memcmp(GET_DOT11D_INFO(__pIeeeDev)->CountryIeBuf, (__Ie).Octet, (__Ie).Length))) + +#define CIE_WATCHDOG_TH 1 +#define GET_CIE_WATCHDOG(__pIeeeDev) GET_DOT11D_INFO(__pIeeeDev)->CountryIeWatchdog +#define RESET_CIE_WATCHDOG(__pIeeeDev) GET_CIE_WATCHDOG(__pIeeeDev) = 0 +#define UPDATE_CIE_WATCHDOG(__pIeeeDev) ++GET_CIE_WATCHDOG(__pIeeeDev) + +#define IS_DOT11D_STATE_DONE(__pIeeeDev) (GET_DOT11D_INFO(__pIeeeDev)->State == DOT11D_STATE_DONE) + + +void +Dot11d_Init( + struct ieee80211_device *dev + ); + +void +Dot11d_Reset( + struct ieee80211_device *dev + ); + +void +Dot11d_UpdateCountryIe( + struct ieee80211_device *dev, + u8 * pTaddr, + u16 CoutryIeLen, + u8 * pCoutryIe + ); + +u8 +DOT11D_GetMaxTxPwrInDbm( + struct ieee80211_device *dev, + u8 Channel + ); + +void +DOT11D_ScanComplete( + struct ieee80211_device * dev + ); + +int IsLegalChannel( + struct ieee80211_device * dev, + u8 channel +); + +int ToLegalChannel( + struct ieee80211_device * dev, + u8 channel +); +#endif //ENABLE_DOT11D +#endif // #ifndef __INC_DOT11D_H diff --git a/drivers/staging/rtl8192su/ieee80211.h b/drivers/staging/rtl8192su/ieee80211.h new file mode 100644 index 000000000000..0edb09a536f9 --- /dev/null +++ b/drivers/staging/rtl8192su/ieee80211.h @@ -0,0 +1,2901 @@ +/* + * Merged with mainline ieee80211.h in Aug 2004. Original ieee802_11 + * remains copyright by the original authors + * + * Portions of the merged code are based on Host AP (software wireless + * LAN access point) driver for Intersil Prism2/2.5/3. + * + * Copyright (c) 2001-2002, SSH Communications Security Corp and Jouni Malinen + * <jkmaline@cc.hut.fi> + * Copyright (c) 2002-2003, Jouni Malinen <jkmaline@cc.hut.fi> + * + * Adaption to a generic IEEE 802.11 stack by James Ketrenos + * <jketreno@linux.intel.com> + * Copyright (c) 2004, Intel Corporation + * + * Modified for Realtek's wi-fi cards by Andrea Merello + * <andreamrl@tiscali.it> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. See README and COPYING for + * more details. + */ +#ifndef IEEE80211_H +#define IEEE80211_H +#include <linux/if_ether.h> /* ETH_ALEN */ +#include <linux/kernel.h> /* ARRAY_SIZE */ +#include <linux/version.h> +#include <linux/module.h> +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) +#include <linux/jiffies.h> +#else +#include <linux/jffs.h> +#include <linux/tqueue.h> +#endif +#include <linux/timer.h> +#include <linux/sched.h> + +#include <linux/delay.h> +#include <linux/wireless.h> + +#include "ieee80211/rtl819x_HT.h" +#include "ieee80211/rtl819x_BA.h" +#include "ieee80211/rtl819x_TS.h" + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)) +#ifndef bool +typedef enum{false = 0, true} bool; +#endif +#endif + +#ifndef IW_MODE_MONITOR +#define IW_MODE_MONITOR 6 +#endif + +#ifndef IWEVCUSTOM +#define IWEVCUSTOM 0x8c02 +#endif + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)) +#ifndef __bitwise +#define __bitwise __attribute__((bitwise)) +#endif +typedef __u16 __le16; +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,27)) +struct iw_spy_data{ + /* --- Standard spy support --- */ + int spy_number; + u_char spy_address[IW_MAX_SPY][ETH_ALEN]; + struct iw_quality spy_stat[IW_MAX_SPY]; + /* --- Enhanced spy support (event) */ + struct iw_quality spy_thr_low; /* Low threshold */ + struct iw_quality spy_thr_high; /* High threshold */ + u_char spy_thr_under[IW_MAX_SPY]; +}; +#endif +#endif + +#ifndef container_of +/** + * container_of - cast a member of a structure out to the containing structure + * + * @ptr: the pointer to the member. + * @type: the type of the container struct this is embedded in. + * @member: the name of the member within the struct. + * + */ +#define container_of(ptr, type, member) ({ \ + const typeof( ((type *)0)->member ) *__mptr = (ptr); \ + (type *)( (char *)__mptr - offsetof(type,member) );}) +#endif + +#define KEY_TYPE_NA 0x0 +#define KEY_TYPE_WEP40 0x1 +#define KEY_TYPE_TKIP 0x2 +#define KEY_TYPE_CCMP 0x4 +#define KEY_TYPE_WEP104 0x5 + +/* added for rtl819x tx procedure */ +#define MAX_QUEUE_SIZE 0x10 + +// +// 8190 queue mapping +// +#define BK_QUEUE 0 +#define BE_QUEUE 1 +#define VI_QUEUE 2 +#define VO_QUEUE 3 +#define HCCA_QUEUE 4 +#define TXCMD_QUEUE 5 +#define MGNT_QUEUE 6 +#define HIGH_QUEUE 7 +#define BEACON_QUEUE 8 + +#define LOW_QUEUE BE_QUEUE +#define NORMAL_QUEUE MGNT_QUEUE + +//added by amy for ps +#define SWRF_TIMEOUT 50 + +//added by amy for LEAP related +#define IE_CISCO_FLAG_POSITION 0x08 // Flag byte: byte 8, numbered from 0. +#define SUPPORT_CKIP_MIC 0x08 // bit3 +#define SUPPORT_CKIP_PK 0x10 // bit4 +//added by amy for ps +// RF Off Level for IPS or HW/SW radio off +#define RT_RF_OFF_LEVL_ASPM BIT0 // PCI ASPM +#define RT_RF_OFF_LEVL_CLK_REQ BIT1 // PCI clock request +#define RT_RF_OFF_LEVL_PCI_D3 BIT2 // PCI D3 mode +#define RT_RF_OFF_LEVL_HALT_NIC BIT3 // NIC halt, re-initialize hw parameters +#define RT_RF_OFF_LEVL_FREE_FW BIT4 // FW free, re-download the FW +#define RT_RF_OFF_LEVL_FW_32K BIT5 // FW in 32k +#define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT6 // Always enable ASPM and Clock Req in initialization. +#define RT_RF_LPS_DISALBE_2R BIT30 // When LPS is on, disable 2R if no packet is received or transmittd. +#define RT_RF_LPS_LEVEL_ASPM BIT31 // LPS with ASPM +#define RT_IN_PS_LEVEL(pPSC, _PS_FLAG) ((pPSC->CurPsLevel & _PS_FLAG) ? true : false) +#define RT_CLEAR_PS_LEVEL(pPSC, _PS_FLAG) (pPSC->CurPsLevel &= (~(_PS_FLAG))) +#define RT_SET_PS_LEVEL(pPSC, _PS_FLAG) (pPSC->CurPsLevel->CurPsLevel |= _PS_FLAG) +/* defined for skb cb field */ +/* At most 28 byte */ +typedef struct cb_desc { + /* Tx Desc Related flags (8-9) */ + u8 bLastIniPkt:1; + u8 bCmdOrInit:1; + u8 bFirstSeg:1; + u8 bLastSeg:1; + u8 bEncrypt:1; + u8 bTxDisableRateFallBack:1; + u8 bTxUseDriverAssingedRate:1; + u8 bHwSec:1; //indicate whether use Hw security. WB + + u8 reserved1; + + /* Tx Firmware Relaged flags (10-11)*/ + u8 bCTSEnable:1; + u8 bRTSEnable:1; + u8 bUseShortGI:1; + u8 bUseShortPreamble:1; + u8 bTxEnableFwCalcDur:1; + u8 bAMPDUEnable:1; + u8 bRTSSTBC:1; + u8 RTSSC:1; + + u8 bRTSBW:1; + u8 bPacketBW:1; + u8 bRTSUseShortPreamble:1; + u8 bRTSUseShortGI:1; + u8 bMulticast:1; + u8 bBroadcast:1; + //u8 reserved2:2; + u8 drv_agg_enable:1; + u8 reserved2:1; + + /* Tx Desc related element(12-19) */ + u8 rata_index; + u8 queue_index; + //u8 reserved3; + //u8 reserved4; + u16 txbuf_size; + //u8 reserved5; + u8 RATRIndex; + u8 reserved6; + u8 reserved7; + u8 reserved8; + + /* Tx firmware related element(20-27) */ + u8 data_rate; + u8 rts_rate; + u8 ampdu_factor; + u8 ampdu_density; + //u8 reserved9; + //u8 reserved10; + //u8 reserved11; + u8 DrvAggrNum; + u16 pkt_size; + u8 reserved12; +}cb_desc, *pcb_desc; + +/*--------------------------Define -------------------------------------------*/ +#define MGN_1M 0x02 +#define MGN_2M 0x04 +#define MGN_5_5M 0x0b +#define MGN_11M 0x16 + +#define MGN_6M 0x0c +#define MGN_9M 0x12 +#define MGN_12M 0x18 +#define MGN_18M 0x24 +#define MGN_24M 0x30 +#define MGN_36M 0x48 +#define MGN_48M 0x60 +#define MGN_54M 0x6c + +#define MGN_MCS0 0x80 +#define MGN_MCS1 0x81 +#define MGN_MCS2 0x82 +#define MGN_MCS3 0x83 +#define MGN_MCS4 0x84 +#define MGN_MCS5 0x85 +#define MGN_MCS6 0x86 +#define MGN_MCS7 0x87 +#define MGN_MCS8 0x88 +#define MGN_MCS9 0x89 +#define MGN_MCS10 0x8a +#define MGN_MCS11 0x8b +#define MGN_MCS12 0x8c +#define MGN_MCS13 0x8d +#define MGN_MCS14 0x8e +#define MGN_MCS15 0x8f +#define MGN_MCS0_SG 0x90 +#define MGN_MCS1_SG 0x91 +#define MGN_MCS2_SG 0x92 +#define MGN_MCS3_SG 0x93 +#define MGN_MCS4_SG 0x94 +#define MGN_MCS5_SG 0x95 +#define MGN_MCS6_SG 0x96 +#define MGN_MCS7_SG 0x97 +#define MGN_MCS8_SG 0x98 +#define MGN_MCS9_SG 0x99 +#define MGN_MCS10_SG 0x9a +#define MGN_MCS11_SG 0x9b +#define MGN_MCS12_SG 0x9c +#define MGN_MCS13_SG 0x9d +#define MGN_MCS14_SG 0x9e +#define MGN_MCS15_SG 0x9f + + +//---------------------------------------------------------------------------- +// 802.11 Management frame Reason Code field +//---------------------------------------------------------------------------- +enum _ReasonCode{ + unspec_reason = 0x1, + auth_not_valid = 0x2, + deauth_lv_ss = 0x3, + inactivity = 0x4, + ap_overload = 0x5, + class2_err = 0x6, + class3_err = 0x7, + disas_lv_ss = 0x8, + asoc_not_auth = 0x9, + + //----MIC_CHECK + mic_failure = 0xe, + //----END MIC_CHECK + + // Reason code defined in 802.11i D10.0 p.28. + invalid_IE = 0x0d, + four_way_tmout = 0x0f, + two_way_tmout = 0x10, + IE_dismatch = 0x11, + invalid_Gcipher = 0x12, + invalid_Pcipher = 0x13, + invalid_AKMP = 0x14, + unsup_RSNIEver = 0x15, + invalid_RSNIE = 0x16, + auth_802_1x_fail= 0x17, + ciper_reject = 0x18, + + // Reason code defined in 7.3.1.7, 802.1e D13.0, p.42. Added by Annie, 2005-11-15. + QoS_unspec = 0x20, // 32 + QAP_bandwidth = 0x21, // 33 + poor_condition = 0x22, // 34 + no_facility = 0x23, // 35 + // Where is 36??? + req_declined = 0x25, // 37 + invalid_param = 0x26, // 38 + req_not_honored= 0x27, // 39 + TS_not_created = 0x2F, // 47 + DL_not_allowed = 0x30, // 48 + dest_not_exist = 0x31, // 49 + dest_not_QSTA = 0x32, // 50 +}; + + + +#define aSifsTime (((priv->ieee80211->current_network.mode == IEEE_A)||(priv->ieee80211->current_network.mode == IEEE_N_24G)||(priv->ieee80211->current_network.mode == IEEE_N_5G))? 16 : 10) + +#define MGMT_QUEUE_NUM 5 + +#define IEEE_CMD_SET_WPA_PARAM 1 +#define IEEE_CMD_SET_WPA_IE 2 +#define IEEE_CMD_SET_ENCRYPTION 3 +#define IEEE_CMD_MLME 4 + +#define IEEE_PARAM_WPA_ENABLED 1 +#define IEEE_PARAM_TKIP_COUNTERMEASURES 2 +#define IEEE_PARAM_DROP_UNENCRYPTED 3 +#define IEEE_PARAM_PRIVACY_INVOKED 4 +#define IEEE_PARAM_AUTH_ALGS 5 +#define IEEE_PARAM_IEEE_802_1X 6 +//It should consistent with the driver_XXX.c +// David, 2006.9.26 +#define IEEE_PARAM_WPAX_SELECT 7 +//Added for notify the encryption type selection +// David, 2006.9.26 +#define IEEE_PROTO_WPA 1 +#define IEEE_PROTO_RSN 2 +//Added for notify the encryption type selection +// David, 2006.9.26 +#define IEEE_WPAX_USEGROUP 0 +#define IEEE_WPAX_WEP40 1 +#define IEEE_WPAX_TKIP 2 +#define IEEE_WPAX_WRAP 3 +#define IEEE_WPAX_CCMP 4 +#define IEEE_WPAX_WEP104 5 + +#define IEEE_KEY_MGMT_IEEE8021X 1 +#define IEEE_KEY_MGMT_PSK 2 + +#define IEEE_MLME_STA_DEAUTH 1 +#define IEEE_MLME_STA_DISASSOC 2 + + +#define IEEE_CRYPT_ERR_UNKNOWN_ALG 2 +#define IEEE_CRYPT_ERR_UNKNOWN_ADDR 3 +#define IEEE_CRYPT_ERR_CRYPT_INIT_FAILED 4 +#define IEEE_CRYPT_ERR_KEY_SET_FAILED 5 +#define IEEE_CRYPT_ERR_TX_KEY_SET_FAILED 6 +#define IEEE_CRYPT_ERR_CARD_CONF_FAILED 7 + + +#define IEEE_CRYPT_ALG_NAME_LEN 16 + +#define MAX_IE_LEN 0xff + +// added for kernel conflict +#define ieee80211_crypt_deinit_entries ieee80211_crypt_deinit_entries_rsl +#define ieee80211_crypt_deinit_handler ieee80211_crypt_deinit_handler_rsl +#define ieee80211_crypt_delayed_deinit ieee80211_crypt_delayed_deinit_rsl +#define ieee80211_register_crypto_ops ieee80211_register_crypto_ops_rsl +#define ieee80211_unregister_crypto_ops ieee80211_unregister_crypto_ops_rsl +#define ieee80211_get_crypto_ops ieee80211_get_crypto_ops_rsl + +#define ieee80211_ccmp_null ieee80211_ccmp_null_rsl + +#define ieee80211_tkip_null ieee80211_tkip_null_rsl + +#define ieee80211_wep_null ieee80211_wep_null_rsl + +#define free_ieee80211 free_ieee80211_rsl +#define alloc_ieee80211 alloc_ieee80211_rsl + +#define ieee80211_rx ieee80211_rx_rsl +#define ieee80211_rx_mgt ieee80211_rx_mgt_rsl + +#define ieee80211_get_beacon ieee80211_get_beacon_rsl +#define ieee80211_wake_queue ieee80211_wake_queue_rsl +#define ieee80211_stop_queue ieee80211_stop_queue_rsl +#define ieee80211_reset_queue ieee80211_reset_queue_rsl +#define ieee80211_softmac_stop_protocol ieee80211_softmac_stop_protocol_rsl +#define ieee80211_softmac_start_protocol ieee80211_softmac_start_protocol_rsl +#define ieee80211_is_shortslot ieee80211_is_shortslot_rsl +#define ieee80211_is_54g ieee80211_is_54g_rsl +#define ieee80211_wpa_supplicant_ioctl ieee80211_wpa_supplicant_ioctl_rsl +#define ieee80211_ps_tx_ack ieee80211_ps_tx_ack_rsl +#define ieee80211_softmac_xmit ieee80211_softmac_xmit_rsl +#define ieee80211_stop_send_beacons ieee80211_stop_send_beacons_rsl +#define notify_wx_assoc_event notify_wx_assoc_event_rsl +#define SendDisassociation SendDisassociation_rsl +#define ieee80211_disassociate ieee80211_disassociate_rsl +#define ieee80211_start_send_beacons ieee80211_start_send_beacons_rsl +#define ieee80211_stop_scan ieee80211_stop_scan_rsl +#define ieee80211_send_probe_requests ieee80211_send_probe_requests_rsl +#define ieee80211_softmac_scan_syncro ieee80211_softmac_scan_syncro_rsl +#define ieee80211_start_scan_syncro ieee80211_start_scan_syncro_rsl + +#define ieee80211_wx_get_essid ieee80211_wx_get_essid_rsl +#define ieee80211_wx_set_essid ieee80211_wx_set_essid_rsl +#define ieee80211_wx_set_rate ieee80211_wx_set_rate_rsl +#define ieee80211_wx_get_rate ieee80211_wx_get_rate_rsl +#define ieee80211_wx_set_wap ieee80211_wx_set_wap_rsl +#define ieee80211_wx_get_wap ieee80211_wx_get_wap_rsl +#define ieee80211_wx_set_mode ieee80211_wx_set_mode_rsl +#define ieee80211_wx_get_mode ieee80211_wx_get_mode_rsl +#define ieee80211_wx_set_scan ieee80211_wx_set_scan_rsl +#define ieee80211_wx_get_freq ieee80211_wx_get_freq_rsl +#define ieee80211_wx_set_freq ieee80211_wx_set_freq_rsl +#define ieee80211_wx_set_rawtx ieee80211_wx_set_rawtx_rsl +#define ieee80211_wx_get_name ieee80211_wx_get_name_rsl +#define ieee80211_wx_set_power ieee80211_wx_set_power_rsl +#define ieee80211_wx_get_power ieee80211_wx_get_power_rsl +#define ieee80211_wlan_frequencies ieee80211_wlan_frequencies_rsl +#define ieee80211_wx_set_rts ieee80211_wx_set_rts_rsl +#define ieee80211_wx_get_rts ieee80211_wx_get_rts_rsl + +#define ieee80211_txb_free ieee80211_txb_free_rsl + +#define ieee80211_wx_set_gen_ie ieee80211_wx_set_gen_ie_rsl +#define ieee80211_wx_get_scan ieee80211_wx_get_scan_rsl +#define ieee80211_wx_set_encode ieee80211_wx_set_encode_rsl +#define ieee80211_wx_get_encode ieee80211_wx_get_encode_rsl +#if WIRELESS_EXT >= 18 +#define ieee80211_wx_set_mlme ieee80211_wx_set_mlme_rsl +#define ieee80211_wx_set_auth ieee80211_wx_set_auth_rsl +#define ieee80211_wx_set_encode_ext ieee80211_wx_set_encode_ext_rsl +#define ieee80211_wx_get_encode_ext ieee80211_wx_get_encode_ext_rsl +#endif + + +typedef struct ieee_param { + u32 cmd; + u8 sta_addr[ETH_ALEN]; + union { + struct { + u8 name; + u32 value; + } wpa_param; + struct { + u32 len; + u8 reserved[32]; + u8 data[0]; + } wpa_ie; + struct{ + int command; + int reason_code; + } mlme; + struct { + u8 alg[IEEE_CRYPT_ALG_NAME_LEN]; + u8 set_tx; + u32 err; + u8 idx; + u8 seq[8]; /* sequence counter (set: RX, get: TX) */ + u16 key_len; + u8 key[0]; + } crypt; + } u; +}ieee_param; + + +#if WIRELESS_EXT < 17 +#define IW_QUAL_QUAL_INVALID 0x10 +#define IW_QUAL_LEVEL_INVALID 0x20 +#define IW_QUAL_NOISE_INVALID 0x40 +#define IW_QUAL_QUAL_UPDATED 0x1 +#define IW_QUAL_LEVEL_UPDATED 0x2 +#define IW_QUAL_NOISE_UPDATED 0x4 +#endif + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)) +static inline void tq_init(struct tq_struct * task, void(*func)(void *), void *data) +{ + task->routine = func; + task->data = data; + //task->next = NULL; + INIT_LIST_HEAD(&task->list); + task->sync = 0; +} +#endif + +// linux under 2.6.9 release may not support it, so modify it for common use +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,9)) +//#define MSECS(t) (1000 * ((t) / HZ) + 1000 * ((t) % HZ) / HZ) +#define MSECS(t) (HZ * ((t) / 1000) + (HZ * ((t) % 1000)) / 1000) +static inline unsigned long msleep_interruptible_rsl(unsigned int msecs) +{ + unsigned long timeout = MSECS(msecs) + 1; + + while (timeout) { + set_current_state(TASK_INTERRUPTIBLE); + timeout = schedule_timeout(timeout); + } + return timeout; +} +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,31)) +static inline void msleep(unsigned int msecs) +{ + unsigned long timeout = MSECS(msecs) + 1; + + while (timeout) { + set_current_state(TASK_UNINTERRUPTIBLE); + timeout = schedule_timeout(timeout); + } +} +#endif +#else +#define MSECS(t) msecs_to_jiffies(t) +#define msleep_interruptible_rsl msleep_interruptible +#endif + +#define IEEE80211_DATA_LEN 2304 +/* Maximum size for the MA-UNITDATA primitive, 802.11 standard section + 6.2.1.1.2. + + The figure in section 7.1.2 suggests a body size of up to 2312 + bytes is allowed, which is a bit confusing, I suspect this + represents the 2304 bytes of real data, plus a possible 8 bytes of + WEP IV and ICV. (this interpretation suggested by Ramiro Barreiro) */ +#define IEEE80211_1ADDR_LEN 10 +#define IEEE80211_2ADDR_LEN 16 +#define IEEE80211_3ADDR_LEN 24 +#define IEEE80211_4ADDR_LEN 30 +#define IEEE80211_FCS_LEN 4 +#define IEEE80211_HLEN (IEEE80211_4ADDR_LEN) +#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN) +#define IEEE80211_MGMT_HDR_LEN 24 +#define IEEE80211_DATA_HDR3_LEN 24 +#define IEEE80211_DATA_HDR4_LEN 30 + +#define MIN_FRAG_THRESHOLD 256U +#define MAX_FRAG_THRESHOLD 2346U + + +/* Frame control field constants */ +#define IEEE80211_FCTL_VERS 0x0003 +#define IEEE80211_FCTL_FTYPE 0x000c +#define IEEE80211_FCTL_STYPE 0x00f0 +#define IEEE80211_FCTL_FRAMETYPE 0x00fc +#define IEEE80211_FCTL_TODS 0x0100 +#define IEEE80211_FCTL_FROMDS 0x0200 +#define IEEE80211_FCTL_DSTODS 0x0300 //added by david +#define IEEE80211_FCTL_MOREFRAGS 0x0400 +#define IEEE80211_FCTL_RETRY 0x0800 +#define IEEE80211_FCTL_PM 0x1000 +#define IEEE80211_FCTL_MOREDATA 0x2000 +#define IEEE80211_FCTL_WEP 0x4000 +#define IEEE80211_FCTL_ORDER 0x8000 + +#define IEEE80211_FTYPE_MGMT 0x0000 +#define IEEE80211_FTYPE_CTL 0x0004 +#define IEEE80211_FTYPE_DATA 0x0008 + +/* management */ +#define IEEE80211_STYPE_ASSOC_REQ 0x0000 +#define IEEE80211_STYPE_ASSOC_RESP 0x0010 +#define IEEE80211_STYPE_REASSOC_REQ 0x0020 +#define IEEE80211_STYPE_REASSOC_RESP 0x0030 +#define IEEE80211_STYPE_PROBE_REQ 0x0040 +#define IEEE80211_STYPE_PROBE_RESP 0x0050 +#define IEEE80211_STYPE_BEACON 0x0080 +#define IEEE80211_STYPE_ATIM 0x0090 +#define IEEE80211_STYPE_DISASSOC 0x00A0 +#define IEEE80211_STYPE_AUTH 0x00B0 +#define IEEE80211_STYPE_DEAUTH 0x00C0 +#define IEEE80211_STYPE_MANAGE_ACT 0x00D0 + +/* control */ +#define IEEE80211_STYPE_PSPOLL 0x00A0 +#define IEEE80211_STYPE_RTS 0x00B0 +#define IEEE80211_STYPE_CTS 0x00C0 +#define IEEE80211_STYPE_ACK 0x00D0 +#define IEEE80211_STYPE_CFEND 0x00E0 +#define IEEE80211_STYPE_CFENDACK 0x00F0 +#define IEEE80211_STYPE_BLOCKACK 0x0094 + +/* data */ +#define IEEE80211_STYPE_DATA 0x0000 +#define IEEE80211_STYPE_DATA_CFACK 0x0010 +#define IEEE80211_STYPE_DATA_CFPOLL 0x0020 +#define IEEE80211_STYPE_DATA_CFACKPOLL 0x0030 +#define IEEE80211_STYPE_NULLFUNC 0x0040 +#define IEEE80211_STYPE_CFACK 0x0050 +#define IEEE80211_STYPE_CFPOLL 0x0060 +#define IEEE80211_STYPE_CFACKPOLL 0x0070 +#define IEEE80211_STYPE_QOS_DATA 0x0080 //added for WMM 2006/8/2 +#define IEEE80211_STYPE_QOS_NULL 0x00C0 + +#define IEEE80211_SCTL_FRAG 0x000F +#define IEEE80211_SCTL_SEQ 0xFFF0 + +/* QOS control */ +#define IEEE80211_QCTL_TID 0x000F + +#define FC_QOS_BIT BIT7 +#define IsDataFrame(pdu) ( ((pdu[0] & 0x0C)==0x08) ? true : false ) +#define IsLegacyDataFrame(pdu) (IsDataFrame(pdu) && (!(pdu[0]&FC_QOS_BIT)) ) +//added by wb. Is this right? +#define IsQoSDataFrame(pframe) ((*(u16*)pframe&(IEEE80211_STYPE_QOS_DATA|IEEE80211_FTYPE_DATA)) == (IEEE80211_STYPE_QOS_DATA|IEEE80211_FTYPE_DATA)) +#define Frame_Order(pframe) (*(u16*)pframe&IEEE80211_FCTL_ORDER) +#define SN_LESS(a, b) (((a-b)&0x800)!=0) +#define SN_EQUAL(a, b) (a == b) +#define MAX_DEV_ADDR_SIZE 8 +typedef enum _ACT_CATEGORY{ + ACT_CAT_QOS = 1, + ACT_CAT_DLS = 2, + ACT_CAT_BA = 3, + ACT_CAT_HT = 7, + ACT_CAT_WMM = 17, +} ACT_CATEGORY, *PACT_CATEGORY; + +typedef enum _TS_ACTION{ + ACT_ADDTSREQ = 0, + ACT_ADDTSRSP = 1, + ACT_DELTS = 2, + ACT_SCHEDULE = 3, +} TS_ACTION, *PTS_ACTION; + +typedef enum _BA_ACTION{ + ACT_ADDBAREQ = 0, + ACT_ADDBARSP = 1, + ACT_DELBA = 2, +} BA_ACTION, *PBA_ACTION; + +typedef enum _InitialGainOpType{ + IG_Backup=0, + IG_Restore, + IG_Max +}InitialGainOpType; +//added by amy for LED 090319 +//================================================================================ +// LED customization. +//================================================================================ +typedef enum _LED_CTL_MODE{ + LED_CTL_POWER_ON = 1, + LED_CTL_LINK = 2, + LED_CTL_NO_LINK = 3, + LED_CTL_TX = 4, + LED_CTL_RX = 5, + LED_CTL_SITE_SURVEY = 6, + LED_CTL_POWER_OFF = 7, + LED_CTL_START_TO_LINK = 8, + LED_CTL_START_WPS = 9, + LED_CTL_STOP_WPS = 10, + LED_CTL_START_WPS_BOTTON = 11, //added for runtop +}LED_CTL_MODE; + +/* debug macros */ +#define CONFIG_IEEE80211_DEBUG +#ifdef CONFIG_IEEE80211_DEBUG +extern u32 ieee80211_debug_level; +#define IEEE80211_DEBUG(level, fmt, args...) \ +do { if (ieee80211_debug_level & (level)) \ + printk(KERN_DEBUG "ieee80211: " fmt, ## args); } while (0) +//wb added to debug out data buf +//if you want print DATA buffer related BA, please set ieee80211_debug_level to DATA|BA +#define IEEE80211_DEBUG_DATA(level, data, datalen) \ + do{ if ((ieee80211_debug_level & (level)) == (level)) \ + { \ + int i; \ + u8* pdata = (u8*) data; \ + printk(KERN_DEBUG "ieee80211: %s()\n", __FUNCTION__); \ + for(i=0; i<(int)(datalen); i++) \ + { \ + printk("%2x ", pdata[i]); \ + if ((i+1)%16 == 0) printk("\n"); \ + } \ + printk("\n"); \ + } \ + } while (0) +#else +#define IEEE80211_DEBUG(level, fmt, args...) do {} while (0) +#define IEEE80211_DEBUG_DATA(level, data, datalen) do {} while(0) +#endif /* CONFIG_IEEE80211_DEBUG */ + +/* debug macros not dependent on CONFIG_IEEE80211_DEBUG */ + +#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x" +#define MAC_ARG(x) ((u8*)(x))[0],((u8*)(x))[1],((u8*)(x))[2],((u8*)(x))[3],((u8*)(x))[4],((u8*)(x))[5] + +/* + * To use the debug system; + * + * If you are defining a new debug classification, simply add it to the #define + * list here in the form of: + * + * #define IEEE80211_DL_xxxx VALUE + * + * shifting value to the left one bit from the previous entry. xxxx should be + * the name of the classification (for example, WEP) + * + * You then need to either add a IEEE80211_xxxx_DEBUG() macro definition for your + * classification, or use IEEE80211_DEBUG(IEEE80211_DL_xxxx, ...) whenever you want + * to send output to that classification. + * + * To add your debug level to the list of levels seen when you perform + * + * % cat /proc/net/ipw/debug_level + * + * you simply need to add your entry to the ipw_debug_levels array. + * + * If you do not see debug_level in /proc/net/ipw then you do not have + * CONFIG_IEEE80211_DEBUG defined in your kernel configuration + * + */ + +#define IEEE80211_DL_INFO (1<<0) +#define IEEE80211_DL_WX (1<<1) +#define IEEE80211_DL_SCAN (1<<2) +#define IEEE80211_DL_STATE (1<<3) +#define IEEE80211_DL_MGMT (1<<4) +#define IEEE80211_DL_FRAG (1<<5) +#define IEEE80211_DL_EAP (1<<6) +#define IEEE80211_DL_DROP (1<<7) + +#define IEEE80211_DL_TX (1<<8) +#define IEEE80211_DL_RX (1<<9) + +#define IEEE80211_DL_HT (1<<10) //HT +#define IEEE80211_DL_BA (1<<11) //ba +#define IEEE80211_DL_TS (1<<12) //TS +#define IEEE80211_DL_QOS (1<<13) +#define IEEE80211_DL_REORDER (1<<14) +#define IEEE80211_DL_IOT (1<<15) +#define IEEE80211_DL_IPS (1<<16) +#define IEEE80211_DL_TRACE (1<<29) //trace function, need to user net_ratelimit() together in order not to print too much to the screen +#define IEEE80211_DL_DATA (1<<30) //use this flag to control whether print data buf out. +#define IEEE80211_DL_ERR (1<<31) //always open +#define IEEE80211_ERROR(f, a...) printk(KERN_ERR "ieee80211: " f, ## a) +#define IEEE80211_WARNING(f, a...) printk(KERN_WARNING "ieee80211: " f, ## a) +#define IEEE80211_DEBUG_INFO(f, a...) IEEE80211_DEBUG(IEEE80211_DL_INFO, f, ## a) + +#define IEEE80211_DEBUG_WX(f, a...) IEEE80211_DEBUG(IEEE80211_DL_WX, f, ## a) +#define IEEE80211_DEBUG_SCAN(f, a...) IEEE80211_DEBUG(IEEE80211_DL_SCAN, f, ## a) +#define IEEE80211_DEBUG_STATE(f, a...) IEEE80211_DEBUG(IEEE80211_DL_STATE, f, ## a) +#define IEEE80211_DEBUG_MGMT(f, a...) IEEE80211_DEBUG(IEEE80211_DL_MGMT, f, ## a) +#define IEEE80211_DEBUG_FRAG(f, a...) IEEE80211_DEBUG(IEEE80211_DL_FRAG, f, ## a) +#define IEEE80211_DEBUG_EAP(f, a...) IEEE80211_DEBUG(IEEE80211_DL_EAP, f, ## a) +#define IEEE80211_DEBUG_DROP(f, a...) IEEE80211_DEBUG(IEEE80211_DL_DROP, f, ## a) +#define IEEE80211_DEBUG_TX(f, a...) IEEE80211_DEBUG(IEEE80211_DL_TX, f, ## a) +#define IEEE80211_DEBUG_RX(f, a...) IEEE80211_DEBUG(IEEE80211_DL_RX, f, ## a) +#define IEEE80211_DEBUG_QOS(f, a...) IEEE80211_DEBUG(IEEE80211_DL_QOS, f, ## a) + +#ifdef CONFIG_IEEE80211_DEBUG +/* Added by Annie, 2005-11-22. */ +#define MAX_STR_LEN 64 +/* I want to see ASCII 33 to 126 only. Otherwise, I print '?'. Annie, 2005-11-22.*/ +#define PRINTABLE(_ch) (_ch>'!' && _ch<'~') +#define IEEE80211_PRINT_STR(_Comp, _TitleString, _Ptr, _Len) \ + if((_Comp) & level) \ + { \ + int __i; \ + u8 buffer[MAX_STR_LEN]; \ + int length = (_Len<MAX_STR_LEN)? _Len : (MAX_STR_LEN-1) ; \ + memset(buffer, 0, MAX_STR_LEN); \ + memcpy(buffer, (u8 *)_Ptr, length ); \ + for( __i=0; __i<MAX_STR_LEN; __i++ ) \ + { \ + if( !PRINTABLE(buffer[__i]) ) buffer[__i] = '?'; \ + } \ + buffer[length] = '\0'; \ + printk("Rtl819x: "); \ + printk(_TitleString); \ + printk(": %d, <%s>\n", _Len, buffer); \ + } +#else +#define IEEE80211_PRINT_STR(_Comp, _TitleString, _Ptr, _Len) do {} while (0) +#endif + +#include <linux/netdevice.h> +#include <linux/if_arp.h> /* ARPHRD_ETHER */ + +#ifndef WIRELESS_SPY +#define WIRELESS_SPY // enable iwspy support +#endif +#include <net/iw_handler.h> // new driver API + +#ifndef ETH_P_PAE +#define ETH_P_PAE 0x888E /* Port Access Entity (IEEE 802.1X) */ +#endif /* ETH_P_PAE */ + +#define ETH_P_PREAUTH 0x88C7 /* IEEE 802.11i pre-authentication */ + +#ifndef ETH_P_80211_RAW +#define ETH_P_80211_RAW (ETH_P_ECONET + 1) +#endif + +/* IEEE 802.11 defines */ + +#define P80211_OUI_LEN 3 + +struct ieee80211_snap_hdr { + + u8 dsap; /* always 0xAA */ + u8 ssap; /* always 0xAA */ + u8 ctrl; /* always 0x03 */ + u8 oui[P80211_OUI_LEN]; /* organizational universal id */ + +} __attribute__ ((packed)); + +#define SNAP_SIZE sizeof(struct ieee80211_snap_hdr) + +#define WLAN_FC_GET_VERS(fc) ((fc) & IEEE80211_FCTL_VERS) +#define WLAN_FC_GET_TYPE(fc) ((fc) & IEEE80211_FCTL_FTYPE) +#define WLAN_FC_GET_STYPE(fc) ((fc) & IEEE80211_FCTL_STYPE) + +#define WLAN_FC_GET_FRAMETYPE(fc) ((fc) & IEEE80211_FCTL_FRAMETYPE) +#define WLAN_GET_SEQ_FRAG(seq) ((seq) & IEEE80211_SCTL_FRAG) +#define WLAN_GET_SEQ_SEQ(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4) + +/* Authentication algorithms */ +#define WLAN_AUTH_OPEN 0 +#define WLAN_AUTH_SHARED_KEY 1 +#define WLAN_AUTH_LEAP 2 + +#define WLAN_AUTH_CHALLENGE_LEN 128 + +#define WLAN_CAPABILITY_BSS (1<<0) +#define WLAN_CAPABILITY_IBSS (1<<1) +#define WLAN_CAPABILITY_CF_POLLABLE (1<<2) +#define WLAN_CAPABILITY_CF_POLL_REQUEST (1<<3) +#define WLAN_CAPABILITY_PRIVACY (1<<4) +#define WLAN_CAPABILITY_SHORT_PREAMBLE (1<<5) +#define WLAN_CAPABILITY_PBCC (1<<6) +#define WLAN_CAPABILITY_CHANNEL_AGILITY (1<<7) +#define WLAN_CAPABILITY_SPECTRUM_MGMT (1<<8) +#define WLAN_CAPABILITY_QOS (1<<9) +#define WLAN_CAPABILITY_SHORT_SLOT (1<<10) +#define WLAN_CAPABILITY_DSSS_OFDM (1<<13) + +/* 802.11g ERP information element */ +#define WLAN_ERP_NON_ERP_PRESENT (1<<0) +#define WLAN_ERP_USE_PROTECTION (1<<1) +#define WLAN_ERP_BARKER_PREAMBLE (1<<2) + +/* Status codes */ +enum ieee80211_statuscode { + WLAN_STATUS_SUCCESS = 0, + WLAN_STATUS_UNSPECIFIED_FAILURE = 1, + WLAN_STATUS_CAPS_UNSUPPORTED = 10, + WLAN_STATUS_REASSOC_NO_ASSOC = 11, + WLAN_STATUS_ASSOC_DENIED_UNSPEC = 12, + WLAN_STATUS_NOT_SUPPORTED_AUTH_ALG = 13, + WLAN_STATUS_UNKNOWN_AUTH_TRANSACTION = 14, + WLAN_STATUS_CHALLENGE_FAIL = 15, + WLAN_STATUS_AUTH_TIMEOUT = 16, + WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA = 17, + WLAN_STATUS_ASSOC_DENIED_RATES = 18, + /* 802.11b */ + WLAN_STATUS_ASSOC_DENIED_NOSHORTPREAMBLE = 19, + WLAN_STATUS_ASSOC_DENIED_NOPBCC = 20, + WLAN_STATUS_ASSOC_DENIED_NOAGILITY = 21, + /* 802.11h */ + WLAN_STATUS_ASSOC_DENIED_NOSPECTRUM = 22, + WLAN_STATUS_ASSOC_REJECTED_BAD_POWER = 23, + WLAN_STATUS_ASSOC_REJECTED_BAD_SUPP_CHAN = 24, + /* 802.11g */ + WLAN_STATUS_ASSOC_DENIED_NOSHORTTIME = 25, + WLAN_STATUS_ASSOC_DENIED_NODSSSOFDM = 26, + /* 802.11i */ + WLAN_STATUS_INVALID_IE = 40, + WLAN_STATUS_INVALID_GROUP_CIPHER = 41, + WLAN_STATUS_INVALID_PAIRWISE_CIPHER = 42, + WLAN_STATUS_INVALID_AKMP = 43, + WLAN_STATUS_UNSUPP_RSN_VERSION = 44, + WLAN_STATUS_INVALID_RSN_IE_CAP = 45, + WLAN_STATUS_CIPHER_SUITE_REJECTED = 46, +}; + +/* Reason codes */ +enum ieee80211_reasoncode { + WLAN_REASON_UNSPECIFIED = 1, + WLAN_REASON_PREV_AUTH_NOT_VALID = 2, + WLAN_REASON_DEAUTH_LEAVING = 3, + WLAN_REASON_DISASSOC_DUE_TO_INACTIVITY = 4, + WLAN_REASON_DISASSOC_AP_BUSY = 5, + WLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA = 6, + WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA = 7, + WLAN_REASON_DISASSOC_STA_HAS_LEFT = 8, + WLAN_REASON_STA_REQ_ASSOC_WITHOUT_AUTH = 9, + /* 802.11h */ + WLAN_REASON_DISASSOC_BAD_POWER = 10, + WLAN_REASON_DISASSOC_BAD_SUPP_CHAN = 11, + /* 802.11i */ + WLAN_REASON_INVALID_IE = 13, + WLAN_REASON_MIC_FAILURE = 14, + WLAN_REASON_4WAY_HANDSHAKE_TIMEOUT = 15, + WLAN_REASON_GROUP_KEY_HANDSHAKE_TIMEOUT = 16, + WLAN_REASON_IE_DIFFERENT = 17, + WLAN_REASON_INVALID_GROUP_CIPHER = 18, + WLAN_REASON_INVALID_PAIRWISE_CIPHER = 19, + WLAN_REASON_INVALID_AKMP = 20, + WLAN_REASON_UNSUPP_RSN_VERSION = 21, + WLAN_REASON_INVALID_RSN_IE_CAP = 22, + WLAN_REASON_IEEE8021X_FAILED = 23, + WLAN_REASON_CIPHER_SUITE_REJECTED = 24, +}; + +#define IEEE80211_STATMASK_SIGNAL (1<<0) +#define IEEE80211_STATMASK_RSSI (1<<1) +#define IEEE80211_STATMASK_NOISE (1<<2) +#define IEEE80211_STATMASK_RATE (1<<3) +#define IEEE80211_STATMASK_WEMASK 0x7 + +#define IEEE80211_CCK_MODULATION (1<<0) +#define IEEE80211_OFDM_MODULATION (1<<1) + +#define IEEE80211_24GHZ_BAND (1<<0) +#define IEEE80211_52GHZ_BAND (1<<1) + +#define IEEE80211_CCK_RATE_LEN 4 +#define IEEE80211_CCK_RATE_1MB 0x02 +#define IEEE80211_CCK_RATE_2MB 0x04 +#define IEEE80211_CCK_RATE_5MB 0x0B +#define IEEE80211_CCK_RATE_11MB 0x16 +#define IEEE80211_OFDM_RATE_LEN 8 +#define IEEE80211_OFDM_RATE_6MB 0x0C +#define IEEE80211_OFDM_RATE_9MB 0x12 +#define IEEE80211_OFDM_RATE_12MB 0x18 +#define IEEE80211_OFDM_RATE_18MB 0x24 +#define IEEE80211_OFDM_RATE_24MB 0x30 +#define IEEE80211_OFDM_RATE_36MB 0x48 +#define IEEE80211_OFDM_RATE_48MB 0x60 +#define IEEE80211_OFDM_RATE_54MB 0x6C +#define IEEE80211_BASIC_RATE_MASK 0x80 + +#define IEEE80211_CCK_RATE_1MB_MASK (1<<0) +#define IEEE80211_CCK_RATE_2MB_MASK (1<<1) +#define IEEE80211_CCK_RATE_5MB_MASK (1<<2) +#define IEEE80211_CCK_RATE_11MB_MASK (1<<3) +#define IEEE80211_OFDM_RATE_6MB_MASK (1<<4) +#define IEEE80211_OFDM_RATE_9MB_MASK (1<<5) +#define IEEE80211_OFDM_RATE_12MB_MASK (1<<6) +#define IEEE80211_OFDM_RATE_18MB_MASK (1<<7) +#define IEEE80211_OFDM_RATE_24MB_MASK (1<<8) +#define IEEE80211_OFDM_RATE_36MB_MASK (1<<9) +#define IEEE80211_OFDM_RATE_48MB_MASK (1<<10) +#define IEEE80211_OFDM_RATE_54MB_MASK (1<<11) + +#define IEEE80211_CCK_RATES_MASK 0x0000000F +#define IEEE80211_CCK_BASIC_RATES_MASK (IEEE80211_CCK_RATE_1MB_MASK | \ + IEEE80211_CCK_RATE_2MB_MASK) +#define IEEE80211_CCK_DEFAULT_RATES_MASK (IEEE80211_CCK_BASIC_RATES_MASK | \ + IEEE80211_CCK_RATE_5MB_MASK | \ + IEEE80211_CCK_RATE_11MB_MASK) + +#define IEEE80211_OFDM_RATES_MASK 0x00000FF0 +#define IEEE80211_OFDM_BASIC_RATES_MASK (IEEE80211_OFDM_RATE_6MB_MASK | \ + IEEE80211_OFDM_RATE_12MB_MASK | \ + IEEE80211_OFDM_RATE_24MB_MASK) +#define IEEE80211_OFDM_DEFAULT_RATES_MASK (IEEE80211_OFDM_BASIC_RATES_MASK | \ + IEEE80211_OFDM_RATE_9MB_MASK | \ + IEEE80211_OFDM_RATE_18MB_MASK | \ + IEEE80211_OFDM_RATE_36MB_MASK | \ + IEEE80211_OFDM_RATE_48MB_MASK | \ + IEEE80211_OFDM_RATE_54MB_MASK) +#define IEEE80211_DEFAULT_RATES_MASK (IEEE80211_OFDM_DEFAULT_RATES_MASK | \ + IEEE80211_CCK_DEFAULT_RATES_MASK) + +#define IEEE80211_NUM_OFDM_RATES 8 +#define IEEE80211_NUM_CCK_RATES 4 +#define IEEE80211_OFDM_SHIFT_MASK_A 4 + + +/* this is stolen and modified from the madwifi driver*/ +#define IEEE80211_FC0_TYPE_MASK 0x0c +#define IEEE80211_FC0_TYPE_DATA 0x08 +#define IEEE80211_FC0_SUBTYPE_MASK 0xB0 +#define IEEE80211_FC0_SUBTYPE_QOS 0x80 + +#define IEEE80211_QOS_HAS_SEQ(fc) \ + (((fc) & (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == \ + (IEEE80211_FC0_TYPE_DATA | IEEE80211_FC0_SUBTYPE_QOS)) + +/* this is stolen from ipw2200 driver */ +#define IEEE_IBSS_MAC_HASH_SIZE 31 +struct ieee_ibss_seq { + u8 mac[ETH_ALEN]; + u16 seq_num[17]; + u16 frag_num[17]; + unsigned long packet_time[17]; + struct list_head list; +}; + +/* NOTE: This data is for statistical purposes; not all hardware provides this + * information for frames received. Not setting these will not cause + * any adverse affects. */ +struct ieee80211_rx_stats { +#if 1 + u32 mac_time[2]; + s8 rssi; + u8 signal; + u8 noise; + u16 rate; /* in 100 kbps */ + u8 received_channel; + u8 control; + u8 mask; + u8 freq; + u16 len; + u64 tsf; + u32 beacon_time; + u8 nic_type; + u16 Length; + // u8 DataRate; // In 0.5 Mbps + u8 SignalQuality; // in 0-100 index. + s32 RecvSignalPower; // Real power in dBm for this packet, no beautification and aggregation. + s8 RxPower; // in dBm Translate from PWdB + u8 SignalStrength; // in 0-100 index. + u16 bHwError:1; + u16 bCRC:1; + u16 bICV:1; + u16 bShortPreamble:1; + u16 Antenna:1; //for rtl8185 + u16 Decrypted:1; //for rtl8185, rtl8187 + u16 Wakeup:1; //for rtl8185 + u16 Reserved0:1; //for rtl8185 + u8 AGC; + u32 TimeStampLow; + u32 TimeStampHigh; + bool bShift; + bool bIsQosData; // Added by Annie, 2005-12-22. + u8 UserPriority; + + //1!!!!!!!!!!!!!!!!!!!!!!!!!!! + //1Attention Please!!!<11n or 8190 specific code should be put below this line> + //1!!!!!!!!!!!!!!!!!!!!!!!!!!! + + u8 RxDrvInfoSize; + u8 RxBufShift; + bool bIsAMPDU; + bool bFirstMPDU; + bool bContainHTC; + bool RxIs40MHzPacket; + u32 RxPWDBAll; + u8 RxMIMOSignalStrength[4]; // in 0~100 index + s8 RxMIMOSignalQuality[2]; + bool bPacketMatchBSSID; + bool bIsCCK; + bool bPacketToSelf; + //added by amy + u8* virtual_address; + u16 packetlength; // Total packet length: Must equal to sum of all FragLength + u16 fraglength; // FragLength should equal to PacketLength in non-fragment case + u16 fragoffset; // Data offset for this fragment + u16 ntotalfrag; + bool bisrxaggrsubframe; + bool bPacketBeacon; //cosa add for rssi + bool bToSelfBA; //cosa add for rssi + char cck_adc_pwdb[4]; //cosa add for rx path selection + u16 Seq_Num; + u8 nTotalAggPkt; // Number of aggregated packets. +#endif + +}; + +/* IEEE 802.11 requires that STA supports concurrent reception of at least + * three fragmented frames. This define can be increased to support more + * concurrent frames, but it should be noted that each entry can consume about + * 2 kB of RAM and increasing cache size will slow down frame reassembly. */ +#define IEEE80211_FRAG_CACHE_LEN 4 + +struct ieee80211_frag_entry { + unsigned long first_frag_time; + unsigned int seq; + unsigned int last_frag; + struct sk_buff *skb; + u8 src_addr[ETH_ALEN]; + u8 dst_addr[ETH_ALEN]; +}; + +struct ieee80211_stats { + unsigned int tx_unicast_frames; + unsigned int tx_multicast_frames; + unsigned int tx_fragments; + unsigned int tx_unicast_octets; + unsigned int tx_multicast_octets; + unsigned int tx_deferred_transmissions; + unsigned int tx_single_retry_frames; + unsigned int tx_multiple_retry_frames; + unsigned int tx_retry_limit_exceeded; + unsigned int tx_discards; + unsigned int rx_unicast_frames; + unsigned int rx_multicast_frames; + unsigned int rx_fragments; + unsigned int rx_unicast_octets; + unsigned int rx_multicast_octets; + unsigned int rx_fcs_errors; + unsigned int rx_discards_no_buffer; + unsigned int tx_discards_wrong_sa; + unsigned int rx_discards_undecryptable; + unsigned int rx_message_in_msg_fragments; + unsigned int rx_message_in_bad_msg_fragments; +}; + +struct ieee80211_device; + +#include "ieee80211_crypt.h" + +#define SEC_KEY_1 (1<<0) +#define SEC_KEY_2 (1<<1) +#define SEC_KEY_3 (1<<2) +#define SEC_KEY_4 (1<<3) +#define SEC_ACTIVE_KEY (1<<4) +#define SEC_AUTH_MODE (1<<5) +#define SEC_UNICAST_GROUP (1<<6) +#define SEC_LEVEL (1<<7) +#define SEC_ENABLED (1<<8) +#define SEC_ENCRYPT (1<<9) + +#define SEC_LEVEL_0 0 /* None */ +#define SEC_LEVEL_1 1 /* WEP 40 and 104 bit */ +#define SEC_LEVEL_2 2 /* Level 1 + TKIP */ +#define SEC_LEVEL_2_CKIP 3 /* Level 1 + CKIP */ +#define SEC_LEVEL_3 4 /* Level 2 + CCMP */ + +#define SEC_ALG_NONE 0 +#define SEC_ALG_WEP 1 +#define SEC_ALG_TKIP 2 +#define SEC_ALG_CCMP 3 + +#define WEP_KEYS 4 +#define WEP_KEY_LEN 13 +#define SCM_KEY_LEN 32 +#define SCM_TEMPORAL_KEY_LENGTH 16 + +struct ieee80211_security { + u16 active_key:2, + enabled:1, + auth_mode:2, + auth_algo:4, + unicast_uses_group:1, + encrypt:1; + u8 key_sizes[WEP_KEYS]; + u8 keys[WEP_KEYS][SCM_KEY_LEN]; + u8 level; + u16 flags; +} __attribute__ ((packed)); + + +/* + 802.11 data frame from AP + ,-------------------------------------------------------------------. +Bytes | 2 | 2 | 6 | 6 | 6 | 2 | 0..2312 | 4 | + |------|------|---------|---------|---------|------|---------|------| +Desc. | ctrl | dura | DA/RA | TA | SA | Sequ | frame | fcs | + | | tion | (BSSID) | | | ence | data | | + `-------------------------------------------------------------------' +Total: 28-2340 bytes +*/ + +/* Management Frame Information Element Types */ +enum ieee80211_mfie { + MFIE_TYPE_SSID = 0, + MFIE_TYPE_RATES = 1, + MFIE_TYPE_FH_SET = 2, + MFIE_TYPE_DS_SET = 3, + MFIE_TYPE_CF_SET = 4, + MFIE_TYPE_TIM = 5, + MFIE_TYPE_IBSS_SET = 6, + MFIE_TYPE_COUNTRY = 7, + MFIE_TYPE_HOP_PARAMS = 8, + MFIE_TYPE_HOP_TABLE = 9, + MFIE_TYPE_REQUEST = 10, + MFIE_TYPE_CHALLENGE = 16, + MFIE_TYPE_POWER_CONSTRAINT = 32, + MFIE_TYPE_POWER_CAPABILITY = 33, + MFIE_TYPE_TPC_REQUEST = 34, + MFIE_TYPE_TPC_REPORT = 35, + MFIE_TYPE_SUPP_CHANNELS = 36, + MFIE_TYPE_CSA = 37, + MFIE_TYPE_MEASURE_REQUEST = 38, + MFIE_TYPE_MEASURE_REPORT = 39, + MFIE_TYPE_QUIET = 40, + MFIE_TYPE_IBSS_DFS = 41, + MFIE_TYPE_ERP = 42, + MFIE_TYPE_RSN = 48, + MFIE_TYPE_RATES_EX = 50, + MFIE_TYPE_HT_CAP= 45, + MFIE_TYPE_HT_INFO= 61, + MFIE_TYPE_AIRONET=133, + MFIE_TYPE_GENERIC = 221, + MFIE_TYPE_QOS_PARAMETER = 222, +}; + +/* Minimal header; can be used for passing 802.11 frames with sufficient + * information to determine what type of underlying data type is actually + * stored in the data. */ +struct ieee80211_hdr { + __le16 frame_ctl; + __le16 duration_id; + u8 payload[0]; +} __attribute__ ((packed)); + +struct ieee80211_hdr_1addr { + __le16 frame_ctl; + __le16 duration_id; + u8 addr1[ETH_ALEN]; + u8 payload[0]; +} __attribute__ ((packed)); + +struct ieee80211_hdr_2addr { + __le16 frame_ctl; + __le16 duration_id; + u8 addr1[ETH_ALEN]; + u8 addr2[ETH_ALEN]; + u8 payload[0]; +} __attribute__ ((packed)); + +struct ieee80211_hdr_3addr { + __le16 frame_ctl; + __le16 duration_id; + u8 addr1[ETH_ALEN]; + u8 addr2[ETH_ALEN]; + u8 addr3[ETH_ALEN]; + __le16 seq_ctl; + u8 payload[0]; +} __attribute__ ((packed)); + +struct ieee80211_hdr_4addr { + __le16 frame_ctl; + __le16 duration_id; + u8 addr1[ETH_ALEN]; + u8 addr2[ETH_ALEN]; + u8 addr3[ETH_ALEN]; + __le16 seq_ctl; + u8 addr4[ETH_ALEN]; + u8 payload[0]; +} __attribute__ ((packed)); + +struct ieee80211_hdr_3addrqos { + __le16 frame_ctl; + __le16 duration_id; + u8 addr1[ETH_ALEN]; + u8 addr2[ETH_ALEN]; + u8 addr3[ETH_ALEN]; + __le16 seq_ctl; + u8 payload[0]; + __le16 qos_ctl; +} __attribute__ ((packed)); + +struct ieee80211_hdr_4addrqos { + __le16 frame_ctl; + __le16 duration_id; + u8 addr1[ETH_ALEN]; + u8 addr2[ETH_ALEN]; + u8 addr3[ETH_ALEN]; + __le16 seq_ctl; + u8 addr4[ETH_ALEN]; + u8 payload[0]; + __le16 qos_ctl; +} __attribute__ ((packed)); + +struct ieee80211_info_element { + u8 id; + u8 len; + u8 data[0]; +} __attribute__ ((packed)); + +struct ieee80211_authentication { + struct ieee80211_hdr_3addr header; + __le16 algorithm; + __le16 transaction; + __le16 status; + /*challenge*/ + struct ieee80211_info_element info_element[0]; +} __attribute__ ((packed)); + +struct ieee80211_disassoc { + struct ieee80211_hdr_3addr header; + __le16 reason; +} __attribute__ ((packed)); + +struct ieee80211_probe_request { + struct ieee80211_hdr_3addr header; + /* SSID, supported rates */ + struct ieee80211_info_element info_element[0]; +} __attribute__ ((packed)); + +struct ieee80211_probe_response { + struct ieee80211_hdr_3addr header; + u32 time_stamp[2]; + __le16 beacon_interval; + __le16 capability; + /* SSID, supported rates, FH params, DS params, + * CF params, IBSS params, TIM (if beacon), RSN */ + struct ieee80211_info_element info_element[0]; +} __attribute__ ((packed)); + +/* Alias beacon for probe_response */ +#define ieee80211_beacon ieee80211_probe_response + +struct ieee80211_assoc_request_frame { + struct ieee80211_hdr_3addr header; + __le16 capability; + __le16 listen_interval; + /* SSID, supported rates, RSN */ + struct ieee80211_info_element info_element[0]; +} __attribute__ ((packed)); + +struct ieee80211_reassoc_request_frame { + struct ieee80211_hdr_3addr header; + __le16 capability; + __le16 listen_interval; + u8 current_ap[ETH_ALEN]; + /* SSID, supported rates, RSN */ + struct ieee80211_info_element info_element[0]; +} __attribute__ ((packed)); + +struct ieee80211_assoc_response_frame { + struct ieee80211_hdr_3addr header; + __le16 capability; + __le16 status; + __le16 aid; + struct ieee80211_info_element info_element[0]; /* supported rates */ +} __attribute__ ((packed)); + +struct ieee80211_txb { + u8 nr_frags; + u8 encrypted; + u8 queue_index; + u8 rts_included; + u16 reserved; + __le16 frag_size; + __le16 payload_size; + struct sk_buff *fragments[0]; +}; + +#define MAX_TX_AGG_COUNT 16 +struct ieee80211_drv_agg_txb { + u8 nr_drv_agg_frames; + struct sk_buff *tx_agg_frames[MAX_TX_AGG_COUNT]; +}__attribute__((packed)); + +#define MAX_SUBFRAME_COUNT 64 +struct ieee80211_rxb { + u8 nr_subframes; + struct sk_buff *subframes[MAX_SUBFRAME_COUNT]; + u8 dst[ETH_ALEN]; + u8 src[ETH_ALEN]; +}__attribute__((packed)); + +typedef union _frameqos { + u16 shortdata; + u8 chardata[2]; + struct { + u16 tid:4; + u16 eosp:1; + u16 ack_policy:2; + u16 reserved:1; + u16 txop:8; + }field; +}frameqos,*pframeqos; + +/* SWEEP TABLE ENTRIES NUMBER*/ +#define MAX_SWEEP_TAB_ENTRIES 42 +#define MAX_SWEEP_TAB_ENTRIES_PER_PACKET 7 +/* MAX_RATES_LENGTH needs to be 12. The spec says 8, and many APs + * only use 8, and then use extended rates for the remaining supported + * rates. Other APs, however, stick all of their supported rates on the + * main rates information element... */ +#define MAX_RATES_LENGTH ((u8)12) +#define MAX_RATES_EX_LENGTH ((u8)16) +#define MAX_NETWORK_COUNT 128 + +#define MAX_CHANNEL_NUMBER 161 +#define IEEE80211_SOFTMAC_SCAN_TIME 100 +//(HZ / 2) +#define IEEE80211_SOFTMAC_ASSOC_RETRY_TIME (HZ * 2) + +#define CRC_LENGTH 4U + +#define MAX_WPA_IE_LEN 64 + +#define NETWORK_EMPTY_ESSID (1<<0) +#define NETWORK_HAS_OFDM (1<<1) +#define NETWORK_HAS_CCK (1<<2) + +/* QoS structure */ +#define NETWORK_HAS_QOS_PARAMETERS (1<<3) +#define NETWORK_HAS_QOS_INFORMATION (1<<4) +#define NETWORK_HAS_QOS_MASK (NETWORK_HAS_QOS_PARAMETERS | \ + NETWORK_HAS_QOS_INFORMATION) +/* 802.11h */ +#define NETWORK_HAS_POWER_CONSTRAINT (1<<5) +#define NETWORK_HAS_CSA (1<<6) +#define NETWORK_HAS_QUIET (1<<7) +#define NETWORK_HAS_IBSS_DFS (1<<8) +#define NETWORK_HAS_TPC_REPORT (1<<9) + +#define NETWORK_HAS_ERP_VALUE (1<<10) + +#define QOS_QUEUE_NUM 4 +#define QOS_OUI_LEN 3 +#define QOS_OUI_TYPE 2 +#define QOS_ELEMENT_ID 221 +#define QOS_OUI_INFO_SUB_TYPE 0 +#define QOS_OUI_PARAM_SUB_TYPE 1 +#define QOS_VERSION_1 1 +#define QOS_AIFSN_MIN_VALUE 2 +#if 1 +struct ieee80211_qos_information_element { + u8 elementID; + u8 length; + u8 qui[QOS_OUI_LEN]; + u8 qui_type; + u8 qui_subtype; + u8 version; + u8 ac_info; +} __attribute__ ((packed)); + +struct ieee80211_qos_ac_parameter { + u8 aci_aifsn; + u8 ecw_min_max; + __le16 tx_op_limit; +} __attribute__ ((packed)); + +struct ieee80211_qos_parameter_info { + struct ieee80211_qos_information_element info_element; + u8 reserved; + struct ieee80211_qos_ac_parameter ac_params_record[QOS_QUEUE_NUM]; +} __attribute__ ((packed)); + +struct ieee80211_qos_parameters { + __le16 cw_min[QOS_QUEUE_NUM]; + __le16 cw_max[QOS_QUEUE_NUM]; + u8 aifs[QOS_QUEUE_NUM]; + u8 flag[QOS_QUEUE_NUM]; + __le16 tx_op_limit[QOS_QUEUE_NUM]; +} __attribute__ ((packed)); + +struct ieee80211_qos_data { + struct ieee80211_qos_parameters parameters; + int active; + int supported; + u8 param_count; + u8 old_param_count; +}; + +struct ieee80211_tim_parameters { + u8 tim_count; + u8 tim_period; +} __attribute__ ((packed)); + +//#else +struct ieee80211_wmm_ac_param { + u8 ac_aci_acm_aifsn; + u8 ac_ecwmin_ecwmax; + u16 ac_txop_limit; +}; + +struct ieee80211_wmm_ts_info { + u8 ac_dir_tid; + u8 ac_up_psb; + u8 reserved; +} __attribute__ ((packed)); + +struct ieee80211_wmm_tspec_elem { + struct ieee80211_wmm_ts_info ts_info; + u16 norm_msdu_size; + u16 max_msdu_size; + u32 min_serv_inter; + u32 max_serv_inter; + u32 inact_inter; + u32 suspen_inter; + u32 serv_start_time; + u32 min_data_rate; + u32 mean_data_rate; + u32 peak_data_rate; + u32 max_burst_size; + u32 delay_bound; + u32 min_phy_rate; + u16 surp_band_allow; + u16 medium_time; +}__attribute__((packed)); +#endif +enum eap_type { + EAP_PACKET = 0, + EAPOL_START, + EAPOL_LOGOFF, + EAPOL_KEY, + EAPOL_ENCAP_ASF_ALERT +}; + +static const char *eap_types[] = { + [EAP_PACKET] = "EAP-Packet", + [EAPOL_START] = "EAPOL-Start", + [EAPOL_LOGOFF] = "EAPOL-Logoff", + [EAPOL_KEY] = "EAPOL-Key", + [EAPOL_ENCAP_ASF_ALERT] = "EAPOL-Encap-ASF-Alert" +}; + +static inline const char *eap_get_type(int type) +{ + return ((u32)type >= ARRAY_SIZE(eap_types)) ? "Unknown" : eap_types[type]; +} +//added by amy for reorder +static inline u8 Frame_QoSTID(u8* buf) +{ + struct ieee80211_hdr_3addr *hdr; + u16 fc; + hdr = (struct ieee80211_hdr_3addr *)buf; + fc = le16_to_cpu(hdr->frame_ctl); + return (u8)((frameqos*)(buf + (((fc & IEEE80211_FCTL_TODS)&&(fc & IEEE80211_FCTL_FROMDS))? 30 : 24)))->field.tid; +} + +//added by amy for reorder + +struct eapol { + u8 snap[6]; + u16 ethertype; + u8 version; + u8 type; + u16 length; +} __attribute__ ((packed)); + +struct ieee80211_softmac_stats{ + unsigned int rx_ass_ok; + unsigned int rx_ass_err; + unsigned int rx_probe_rq; + unsigned int tx_probe_rs; + unsigned int tx_beacons; + unsigned int rx_auth_rq; + unsigned int rx_auth_rs_ok; + unsigned int rx_auth_rs_err; + unsigned int tx_auth_rq; + unsigned int no_auth_rs; + unsigned int no_ass_rs; + unsigned int tx_ass_rq; + unsigned int rx_ass_rq; + unsigned int tx_probe_rq; + unsigned int reassoc; + unsigned int swtxstop; + unsigned int swtxawake; + unsigned char CurrentShowTxate; + unsigned char last_packet_rate; + unsigned int txretrycount; +}; + +#define BEACON_PROBE_SSID_ID_POSITION 12 + +struct ieee80211_info_element_hdr { + u8 id; + u8 len; +} __attribute__ ((packed)); + +/* + * These are the data types that can make up management packets + * + u16 auth_algorithm; + u16 auth_sequence; + u16 beacon_interval; + u16 capability; + u8 current_ap[ETH_ALEN]; + u16 listen_interval; + struct { + u16 association_id:14, reserved:2; + } __attribute__ ((packed)); + u32 time_stamp[2]; + u16 reason; + u16 status; +*/ + +#define IEEE80211_DEFAULT_TX_ESSID "Penguin" +#define IEEE80211_DEFAULT_BASIC_RATE 2 //1Mbps + +enum {WMM_all_frame, WMM_two_frame, WMM_four_frame, WMM_six_frame}; +#define MAX_SP_Len (WMM_all_frame << 4) +#define IEEE80211_QOS_TID 0x0f +#define QOS_CTL_NOTCONTAIN_ACK (0x01 << 5) + +#define IEEE80211_DTIM_MBCAST 4 +#define IEEE80211_DTIM_UCAST 2 +#define IEEE80211_DTIM_VALID 1 +#define IEEE80211_DTIM_INVALID 0 + +#define IEEE80211_PS_DISABLED 0 +#define IEEE80211_PS_UNICAST IEEE80211_DTIM_UCAST +#define IEEE80211_PS_MBCAST IEEE80211_DTIM_MBCAST + +//added by David for QoS 2006/6/30 +//#define WMM_Hang_8187 +#ifdef WMM_Hang_8187 +#undef WMM_Hang_8187 +#endif + +#define WME_AC_BK 0x00 +#define WME_AC_BE 0x01 +#define WME_AC_VI 0x02 +#define WME_AC_VO 0x03 +#define WME_ACI_MASK 0x03 +#define WME_AIFSN_MASK 0x03 +#define WME_AC_PRAM_LEN 16 + +#define MAX_RECEIVE_BUFFER_SIZE 9100 + +//UP Mapping to AC, using in MgntQuery_SequenceNumber() and maybe for DSCP +//#define UP2AC(up) ((up<3) ? ((up==0)?1:0) : (up>>1)) +#if 1 +#define UP2AC(up) ( \ + ((up) < 1) ? WME_AC_BE : \ + ((up) < 3) ? WME_AC_BK : \ + ((up) < 4) ? WME_AC_BE : \ + ((up) < 6) ? WME_AC_VI : \ + WME_AC_VO) +#endif +//AC Mapping to UP, using in Tx part for selecting the corresponding TX queue +#define AC2UP(_ac) ( \ + ((_ac) == WME_AC_VO) ? 6 : \ + ((_ac) == WME_AC_VI) ? 5 : \ + ((_ac) == WME_AC_BK) ? 1 : \ + 0) + +#define ETHER_ADDR_LEN 6 /* length of an Ethernet address */ +#define ETHERNET_HEADER_SIZE 14 /* length of two Ethernet address plus ether type*/ + +struct ether_header { + u8 ether_dhost[ETHER_ADDR_LEN]; + u8 ether_shost[ETHER_ADDR_LEN]; + u16 ether_type; +} __attribute__((packed)); + +#ifndef ETHERTYPE_PAE +#define ETHERTYPE_PAE 0x888e /* EAPOL PAE/802.1x */ +#endif +#ifndef ETHERTYPE_IP +#define ETHERTYPE_IP 0x0800 /* IP protocol */ +#endif + +typedef struct _bss_ht{ + + bool support_ht; + + // HT related elements + u8 ht_cap_buf[32]; + u16 ht_cap_len; + u8 ht_info_buf[32]; + u16 ht_info_len; + + HT_SPEC_VER ht_spec_ver; + //HT_CAPABILITY_ELE bdHTCapEle; + //HT_INFORMATION_ELE bdHTInfoEle; + + bool aggregation; + bool long_slot_time; +}bss_ht, *pbss_ht; + +typedef enum _erp_t{ + ERP_NonERPpresent = 0x01, + ERP_UseProtection = 0x02, + ERP_BarkerPreambleMode = 0x04, +} erp_t; + + +struct ieee80211_network { + /* These entries are used to identify a unique network */ + u8 bssid[ETH_ALEN]; + u8 channel; + /* Ensure null-terminated for any debug msgs */ + u8 ssid[IW_ESSID_MAX_SIZE + 1]; + u8 ssid_len; +#if 1 + struct ieee80211_qos_data qos_data; +#else + // Qos related. Added by Annie, 2005-11-01. + BSS_QOS BssQos; +#endif + + //added by amy for LEAP + bool bWithAironetIE; + bool bCkipSupported; + bool bCcxRmEnable; + u16 CcxRmState[2]; + // CCXv4 S59, MBSSID. + bool bMBssidValid; + u8 MBssidMask; + u8 MBssid[6]; + // CCX 2 S38, WLAN Device Version Number element. Annie, 2006-08-20. + bool bWithCcxVerNum; + u8 BssCcxVerNumber; + /* These are network statistics */ + struct ieee80211_rx_stats stats; + u16 capability; + u8 rates[MAX_RATES_LENGTH]; + u8 rates_len; + u8 rates_ex[MAX_RATES_EX_LENGTH]; + u8 rates_ex_len; + unsigned long last_scanned; + u8 mode; + u32 flags; + u32 last_associate; + u32 time_stamp[2]; + u16 beacon_interval; + u16 listen_interval; + u16 atim_window; + u8 erp_value; + u8 wpa_ie[MAX_WPA_IE_LEN]; + size_t wpa_ie_len; + u8 rsn_ie[MAX_WPA_IE_LEN]; + size_t rsn_ie_len; + + struct ieee80211_tim_parameters tim; + u8 dtim_period; + u8 dtim_data; + u32 last_dtim_sta_time[2]; + + //appeded for QoS + u8 wmm_info; + struct ieee80211_wmm_ac_param wmm_param[4]; + u8 QoS_Enable; +#ifdef THOMAS_TURBO + u8 Turbo_Enable;//enable turbo mode, added by thomas +#endif +#ifdef ENABLE_DOT11D + u16 CountryIeLen; + u8 CountryIeBuf[MAX_IE_LEN]; +#endif + // HT Related, by amy, 2008.04.29 + BSS_HT bssht; + // Add to handle broadcom AP management frame CCK rate. + bool broadcom_cap_exist; + bool realtek_cap_exit; + bool marvell_cap_exist; + bool ralink_cap_exist; + bool atheros_cap_exist; + bool cisco_cap_exist; + bool unknown_cap_exist; +// u8 berp_info; + bool berp_info_valid; + bool buseprotection; + //put at the end of the structure. + struct list_head list; +}; + +#if 1 +enum ieee80211_state { + + /* the card is not linked at all */ + IEEE80211_NOLINK = 0, + + /* IEEE80211_ASSOCIATING* are for BSS client mode + * the driver shall not perform RX filtering unless + * the state is LINKED. + * The driver shall just check for the state LINKED and + * defaults to NOLINK for ALL the other states (including + * LINKED_SCANNING) + */ + + /* the association procedure will start (wq scheduling)*/ + IEEE80211_ASSOCIATING, + IEEE80211_ASSOCIATING_RETRY, + + /* the association procedure is sending AUTH request*/ + IEEE80211_ASSOCIATING_AUTHENTICATING, + + /* the association procedure has successfully authentcated + * and is sending association request + */ + IEEE80211_ASSOCIATING_AUTHENTICATED, + + /* the link is ok. the card associated to a BSS or linked + * to a ibss cell or acting as an AP and creating the bss + */ + IEEE80211_LINKED, + + /* same as LINKED, but the driver shall apply RX filter + * rules as we are in NO_LINK mode. As the card is still + * logically linked, but it is doing a syncro site survey + * then it will be back to LINKED state. + */ + IEEE80211_LINKED_SCANNING, + +}; +#else +enum ieee80211_state { + IEEE80211_UNINITIALIZED = 0, + IEEE80211_INITIALIZED, + IEEE80211_ASSOCIATING, + IEEE80211_ASSOCIATED, + IEEE80211_AUTHENTICATING, + IEEE80211_AUTHENTICATED, + IEEE80211_SHUTDOWN +}; +#endif + +#define DEFAULT_MAX_SCAN_AGE (15 * HZ) +#define DEFAULT_FTS 2346 + +#define CFG_IEEE80211_RESERVE_FCS (1<<0) +#define CFG_IEEE80211_COMPUTE_FCS (1<<1) +#define CFG_IEEE80211_RTS (1<<2) + +#define IEEE80211_24GHZ_MIN_CHANNEL 1 +#define IEEE80211_24GHZ_MAX_CHANNEL 14 +#define IEEE80211_24GHZ_CHANNELS (IEEE80211_24GHZ_MAX_CHANNEL - \ + IEEE80211_24GHZ_MIN_CHANNEL + 1) + +#define IEEE80211_52GHZ_MIN_CHANNEL 34 +#define IEEE80211_52GHZ_MAX_CHANNEL 165 +#define IEEE80211_52GHZ_CHANNELS (IEEE80211_52GHZ_MAX_CHANNEL - \ + IEEE80211_52GHZ_MIN_CHANNEL + 1) + +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,11)) +extern inline int is_multicast_ether_addr(const u8 *addr) +{ + return ((addr[0] != 0xff) && (0x01 & addr[0])); +} +#endif + +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,13)) +extern inline int is_broadcast_ether_addr(const u8 *addr) +{ + return ((addr[0] == 0xff) && (addr[1] == 0xff) && (addr[2] == 0xff) && \ + (addr[3] == 0xff) && (addr[4] == 0xff) && (addr[5] == 0xff)); +} +#endif + +typedef struct tx_pending_t{ + int frag; + struct ieee80211_txb *txb; +}tx_pending_t; + +typedef struct _bandwidth_autoswitch +{ + long threshold_20Mhzto40Mhz; + long threshold_40Mhzto20Mhz; + bool bforced_tx20Mhz; + bool bautoswitch_enable; +}bandwidth_autoswitch,*pbandwidth_autoswitch; + + +//added by amy for order + +#define REORDER_WIN_SIZE 128 +#define REORDER_ENTRY_NUM 128 +typedef struct _RX_REORDER_ENTRY +{ + struct list_head List; + u16 SeqNum; + struct ieee80211_rxb* prxb; +} RX_REORDER_ENTRY, *PRX_REORDER_ENTRY; +//added by amy for order +typedef enum _Fsync_State{ + Default_Fsync, + HW_Fsync, + SW_Fsync +}Fsync_State; + +// Power save mode configured. +typedef enum _RT_PS_MODE +{ + eActive, // Active/Continuous access. + eMaxPs, // Max power save mode. + eFastPs // Fast power save mode. +}RT_PS_MODE; + +typedef enum _IPS_CALLBACK_FUNCION +{ + IPS_CALLBACK_NONE = 0, + IPS_CALLBACK_MGNT_LINK_REQUEST = 1, + IPS_CALLBACK_JOIN_REQUEST = 2, +}IPS_CALLBACK_FUNCION; + +typedef enum _RT_JOIN_ACTION{ + RT_JOIN_INFRA = 1, + RT_JOIN_IBSS = 2, + RT_START_IBSS = 3, + RT_NO_ACTION = 4, +}RT_JOIN_ACTION; + +typedef struct _IbssParms{ + u16 atimWin; +}IbssParms, *PIbssParms; +#define MAX_NUM_RATES 264 // Max num of support rates element: 8, Max num of ext. support rate: 255. 061122, by rcnjko. + +// RF state. +typedef enum _RT_RF_POWER_STATE +{ + eRfOn, + eRfSleep, + eRfOff +}RT_RF_POWER_STATE; + +typedef struct _RT_POWER_SAVE_CONTROL +{ + + // + // Inactive Power Save(IPS) : Disable RF when disconnected + // + bool bInactivePs; + bool bIPSModeBackup; + bool bHaltAdapterClkRQ; + bool bSwRfProcessing; + RT_RF_POWER_STATE eInactivePowerState; +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + struct work_struct InactivePsWorkItem; +#else + struct tq_struct InactivePsWorkItem; +#endif + struct timer_list InactivePsTimer; + + // Return point for join action + IPS_CALLBACK_FUNCION ReturnPoint; + + // Recored Parameters for rescheduled JoinRequest + bool bTmpBssDesc; + RT_JOIN_ACTION tmpJoinAction; + struct ieee80211_network tmpBssDesc; + + // Recored Parameters for rescheduled MgntLinkRequest + bool bTmpScanOnly; + bool bTmpActiveScan; + bool bTmpFilterHiddenAP; + bool bTmpUpdateParms; + u8 tmpSsidBuf[33]; + OCTET_STRING tmpSsid2Scan; + bool bTmpSsid2Scan; + u8 tmpNetworkType; + u8 tmpChannelNumber; + u16 tmpBcnPeriod; + u8 tmpDtimPeriod; + u16 tmpmCap; + OCTET_STRING tmpSuppRateSet; + u8 tmpSuppRateBuf[MAX_NUM_RATES]; + bool bTmpSuppRate; + IbssParms tmpIbpm; + bool bTmpIbpm; + + // + // Leisre Poswer Save : Disable RF if connected but traffic is not busy + // + bool bLeisurePs; + u32 PowerProfile; + u8 LpsIdleCount; + u8 RegMaxLPSAwakeIntvl; + u8 LPSAwakeIntvl; + + //RF OFF Level + u32 CurPsLevel; + u32 RegRfPsLevel; + + //Fw Control LPS + bool bFwCtrlLPS; + u8 FWCtrlPSMode; + + //2009.01.01 added by tynli + // Record if there is a link request in IPS RF off progress. + bool LinkReqInIPSRFOffPgs; + // To make sure that connect info should be executed, so we set the bit to filter the link info which comes after the connect info. + bool BufConnectinfoBefore; + +}RT_POWER_SAVE_CONTROL,*PRT_POWER_SAVE_CONTROL; + +typedef u32 RT_RF_CHANGE_SOURCE; +#define RF_CHANGE_BY_SW BIT31 +#define RF_CHANGE_BY_HW BIT30 +#define RF_CHANGE_BY_PS BIT29 +#define RF_CHANGE_BY_IPS BIT28 +#define RF_CHANGE_BY_INIT 0 // Do not change the RFOff reason. Defined by Bruce, 2008-01-17. + +#ifdef ENABLE_DOT11D +typedef enum +{ + COUNTRY_CODE_FCC = 0, + COUNTRY_CODE_IC = 1, + COUNTRY_CODE_ETSI = 2, + COUNTRY_CODE_SPAIN = 3, + COUNTRY_CODE_FRANCE = 4, + COUNTRY_CODE_MKK = 5, + COUNTRY_CODE_MKK1 = 6, + COUNTRY_CODE_ISRAEL = 7, + COUNTRY_CODE_TELEC, + COUNTRY_CODE_MIC, + COUNTRY_CODE_GLOBAL_DOMAIN +}country_code_type_t; +#endif + // Firmware realted CMD IO. +typedef enum _FW_CMD_IO_TYPE{ + FW_CMD_DIG_ENABLE = 0, // For DIG DM + FW_CMD_DIG_DISABLE = 1, + FW_CMD_DIG_HALT = 2, + FW_CMD_DIG_RESUME = 3, + FW_CMD_HIGH_PWR_ENABLE = 4, // For High Power DM + FW_CMD_HIGH_PWR_DISABLE = 5, + FW_CMD_RA_RESET = 6, // For Rate adaptive DM + FW_CMD_RA_ACTIVE= 7, + FW_CMD_RA_REFRESH_N= 8, + FW_CMD_RA_REFRESH_BG= 9, + FW_CMD_IQK_ENABLE = 10, // For FW supported IQK + FW_CMD_TXPWR_TRACK_ENABLE = 11, // Tx power tracking switch + FW_CMD_TXPWR_TRACK_DISABLE = 12, // Tx power tracking switch + FW_CMD_PAUSE_DM_BY_SCAN = 13, + FW_CMD_RESUME_DM_BY_SCAN = 14, + FW_CMD_MID_HIGH_PWR_ENABLE = 15, + FW_CMD_LPS_ENTER = 16, // Indifate firmware that driver enters LPS, For PS-Poll hardware bug + FW_CMD_LPS_LEAVE = 17, // Indicate firmware that driver leave LPS, 2009/1/4, by Emily +}FW_CMD_IO_TYPE,*PFW_CMD_IO_TYPE; +#define RT_MAX_LD_SLOT_NUM 10 +typedef struct _RT_LINK_DETECT_T{ + + u32 NumRecvBcnInPeriod; + u32 NumRecvDataInPeriod; + + u32 RxBcnNum[RT_MAX_LD_SLOT_NUM]; // number of Rx beacon / CheckForHang_period to determine link status + u32 RxDataNum[RT_MAX_LD_SLOT_NUM]; // number of Rx data / CheckForHang_period to determine link status + u16 SlotNum; // number of CheckForHang period to determine link status + u16 SlotIndex; + + u32 NumTxOkInPeriod; + u32 NumRxOkInPeriod; + bool bBusyTraffic; +}RT_LINK_DETECT_T, *PRT_LINK_DETECT_T; + + +struct ieee80211_device { + struct net_device *dev; + struct ieee80211_security sec; + + //hw security related +// u8 hwsec_support; //support? + u8 hwsec_active; //hw security active. + bool is_silent_reset; + bool is_roaming; + bool ieee_up; + //added by amy + bool bSupportRemoteWakeUp; + RT_PS_MODE dot11PowerSaveMode; // Power save mode configured. + bool actscanning; + //added by amy 090313 + bool be_scan_inprogress; + bool beinretry; + RT_RF_POWER_STATE eRFPowerState; + RT_RF_CHANGE_SOURCE RfOffReason; + bool is_set_key; + //11n spec related I wonder if These info structure need to be moved out of ieee80211_device + + //11n HT below + PRT_HIGH_THROUGHPUT pHTInfo; + //struct timer_list SwBwTimer; +// spinlock_t chnlop_spinlock; + spinlock_t bw_spinlock; + + spinlock_t reorder_spinlock; + // for HT operation rate set. we use this one for HT data rate to seperate different descriptors + //the way fill this is the same as in the IE + u8 Regdot11HTOperationalRateSet[16]; //use RATR format + u8 dot11HTOperationalRateSet[16]; //use RATR format + u8 RegHTSuppRateSet[16]; + u8 HTCurrentOperaRate; + u8 HTHighestOperaRate; + //wb added for rate operation mode to firmware + u8 bTxDisableRateFallBack; + u8 bTxUseDriverAssingedRate; + atomic_t atm_chnlop; + atomic_t atm_swbw; +// u8 HTHighestOperaRate; +// u8 HTCurrentOperaRate; + + // 802.11e and WMM Traffic Stream Info (TX) + struct list_head Tx_TS_Admit_List; + struct list_head Tx_TS_Pending_List; + struct list_head Tx_TS_Unused_List; + TX_TS_RECORD TxTsRecord[TOTAL_TS_NUM]; + // 802.11e and WMM Traffic Stream Info (RX) + struct list_head Rx_TS_Admit_List; + struct list_head Rx_TS_Pending_List; + struct list_head Rx_TS_Unused_List; + RX_TS_RECORD RxTsRecord[TOTAL_TS_NUM]; +//#ifdef TO_DO_LIST + RX_REORDER_ENTRY RxReorderEntry[128]; + struct list_head RxReorder_Unused_List; +//#endif + // Qos related. Added by Annie, 2005-11-01. +// PSTA_QOS pStaQos; + u8 ForcedPriority; // Force per-packet priority 1~7. (default: 0, not to force it.) + + + /* Bookkeeping structures */ + struct net_device_stats stats; + struct ieee80211_stats ieee_stats; + struct ieee80211_softmac_stats softmac_stats; + + /* Probe / Beacon management */ + struct list_head network_free_list; + struct list_head network_list; + struct ieee80211_network *networks; + int scans; + int scan_age; + + int iw_mode; /* operating mode (IW_MODE_*) */ + struct iw_spy_data spy_data; + + spinlock_t lock; + spinlock_t wpax_suitlist_lock; + + int tx_headroom; /* Set to size of any additional room needed at front + * of allocated Tx SKBs */ + u32 config; + + /* WEP and other encryption related settings at the device level */ + int open_wep; /* Set to 1 to allow unencrypted frames */ + int auth_mode; + int reset_on_keychange; /* Set to 1 if the HW needs to be reset on + * WEP key changes */ + + /* If the host performs {en,de}cryption, then set to 1 */ + int host_encrypt; + int host_encrypt_msdu; + int host_decrypt; + /* host performs multicast decryption */ + int host_mc_decrypt; + + /* host should strip IV and ICV from protected frames */ + /* meaningful only when hardware decryption is being used */ + int host_strip_iv_icv; + + int host_open_frag; + int host_build_iv; + int ieee802_1x; /* is IEEE 802.1X used */ + + /* WPA data */ + bool bHalfWirelessN24GMode; + int wpa_enabled; + int drop_unencrypted; + int tkip_countermeasures; + int privacy_invoked; + size_t wpa_ie_len; + u8 *wpa_ie; + u8 ap_mac_addr[6]; + u16 pairwise_key_type; + u16 group_key_type; + struct list_head crypt_deinit_list; + struct ieee80211_crypt_data *crypt[WEP_KEYS]; + int tx_keyidx; /* default TX key index (crypt[tx_keyidx]) */ + struct timer_list crypt_deinit_timer; + int crypt_quiesced; + + int bcrx_sta_key; /* use individual keys to override default keys even + * with RX of broad/multicast frames */ + + /* Fragmentation structures */ + // each streaming contain a entry + struct ieee80211_frag_entry frag_cache[17][IEEE80211_FRAG_CACHE_LEN]; + unsigned int frag_next_idx[17]; + u16 fts; /* Fragmentation Threshold */ +#define DEFAULT_RTS_THRESHOLD 2346U +#define MIN_RTS_THRESHOLD 1 +#define MAX_RTS_THRESHOLD 2346U + u16 rts; /* RTS threshold */ + + /* Association info */ + u8 bssid[ETH_ALEN]; + + /* This stores infos for the current network. + * Either the network we are associated in INFRASTRUCTURE + * or the network that we are creating in MASTER mode. + * ad-hoc is a mixture ;-). + * Note that in infrastructure mode, even when not associated, + * fields bssid and essid may be valid (if wpa_set and essid_set + * are true) as thy carry the value set by the user via iwconfig + */ + struct ieee80211_network current_network; + + enum ieee80211_state state; + + int short_slot; + int reg_mode; + int mode; /* A, B, G */ + int modulation; /* CCK, OFDM */ + int freq_band; /* 2.4Ghz, 5.2Ghz, Mixed */ + int abg_true; /* ABG flag */ + + /* used for forcing the ibss workqueue to terminate + * without wait for the syncro scan to terminate + */ + short sync_scan_hurryup; + u16 scan_watch_dog; + int perfect_rssi; + int worst_rssi; + + u16 prev_seq_ctl; /* used to drop duplicate frames */ + + /* map of allowed channels. 0 is dummy */ + // FIXME: remeber to default to a basic channel plan depending of the PHY type +#ifdef ENABLE_DOT11D + void* pDot11dInfo; + bool bGlobalDomain; +#else + int channel_map[MAX_CHANNEL_NUMBER+1]; +#endif + int rate; /* current rate */ + int basic_rate; + //FIXME: pleace callback, see if redundant with softmac_features + short active_scan; + + /* this contains flags for selectively enable softmac support */ + u16 softmac_features; + + /* if the sequence control field is not filled by HW */ + u16 seq_ctrl[5]; + + /* association procedure transaction sequence number */ + u16 associate_seq; + + /* AID for RTXed association responses */ + u16 assoc_id; + + /* power save mode related*/ + u8 ack_tx_to_ieee; + short ps; + short sta_sleep; + int ps_timeout; + int ps_period; + struct tasklet_struct ps_task; + u32 ps_th; + u32 ps_tl; + + short raw_tx; + /* used if IEEE_SOFTMAC_TX_QUEUE is set */ + short queue_stop; + short scanning; + short proto_started; + + struct semaphore wx_sem; + struct semaphore scan_sem; + + spinlock_t mgmt_tx_lock; + spinlock_t beacon_lock; + + short beacon_txing; + + short wap_set; + short ssid_set; + + u8 wpax_type_set; //{added by David, 2006.9.28} + u32 wpax_type_notify; //{added by David, 2006.9.26} + + /* QoS related flag */ + char init_wmmparam_flag; + /* set on initialization */ + u8 qos_support; + + /* for discarding duplicated packets in IBSS */ + struct list_head ibss_mac_hash[IEEE_IBSS_MAC_HASH_SIZE]; + + /* for discarding duplicated packets in BSS */ + u16 last_rxseq_num[17]; /* rx seq previous per-tid */ + u16 last_rxfrag_num[17];/* tx frag previous per-tid */ + unsigned long last_packet_time[17]; + + /* for PS mode */ + unsigned long last_rx_ps_time; + + /* used if IEEE_SOFTMAC_SINGLE_QUEUE is set */ + struct sk_buff *mgmt_queue_ring[MGMT_QUEUE_NUM]; + int mgmt_queue_head; + int mgmt_queue_tail; +//{ added for rtl819x +#define IEEE80211_QUEUE_LIMIT 128 + u8 AsocRetryCount; + unsigned int hw_header; + struct sk_buff_head skb_waitQ[MAX_QUEUE_SIZE]; + struct sk_buff_head skb_aggQ[MAX_QUEUE_SIZE]; + struct sk_buff_head skb_drv_aggQ[MAX_QUEUE_SIZE]; + u32 sta_edca_param[4]; + bool aggregation; + // Enable/Disable Rx immediate BA capability. + bool enable_rx_imm_BA; + bool bibsscoordinator; + + //+by amy for DM ,080515 + //Dynamic Tx power for near/far range enable/Disable , by amy , 2008-05-15 + bool bdynamic_txpower_enable; + + bool bCTSToSelfEnable; + u8 CTSToSelfTH; + + u32 fsync_time_interval; + u32 fsync_rate_bitmap; + u8 fsync_rssi_threshold; + bool bfsync_enable; + + u8 fsync_multiple_timeinterval; // FsyncMultipleTimeInterval * FsyncTimeInterval + u32 fsync_firstdiff_ratethreshold; // low threshold + u32 fsync_seconddiff_ratethreshold; // decrease threshold + Fsync_State fsync_state; + bool bis_any_nonbepkts; + //20Mhz 40Mhz AutoSwitch Threshold + bandwidth_autoswitch bandwidth_auto_switch; + //for txpower tracking + bool FwRWRF; + + //added by amy for AP roaming + RT_LINK_DETECT_T LinkDetectInfo; + //added by amy for ps + RT_POWER_SAVE_CONTROL PowerSaveControl; +//} + /* used if IEEE_SOFTMAC_TX_QUEUE is set */ + struct tx_pending_t tx_pending; + + /* used if IEEE_SOFTMAC_ASSOCIATE is set */ + struct timer_list associate_timer; + + /* used if IEEE_SOFTMAC_BEACONS is set */ + struct timer_list beacon_timer; +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + struct work_struct associate_complete_wq; + struct work_struct associate_procedure_wq; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + struct delayed_work softmac_scan_wq; + struct delayed_work associate_retry_wq; + struct delayed_work start_ibss_wq; + struct delayed_work hw_wakeup_wq; + struct delayed_work hw_sleep_wq; + struct delayed_work link_change_wq; +#else + struct work_struct softmac_scan_wq; + struct work_struct associate_retry_wq; + struct work_struct start_ibss_wq; + struct work_struct hw_wakeup_wq; + struct work_struct hw_sleep_wq; + struct work_struct link_change_wq; +#endif + struct work_struct wx_sync_scan_wq; + struct workqueue_struct *wq; +#else + /* used for periodly scan */ + struct timer_list scan_timer; + + struct tq_struct associate_complete_wq; + struct tq_struct associate_retry_wq; + struct tq_struct start_ibss_wq; + struct tq_struct associate_procedure_wq; + struct tq_struct softmac_scan_wq; + struct tq_struct wx_sync_scan_wq; + struct tq_struct hw_wakeup_wq; + struct tq_struct hw_sleep_wq; + struct tq_struct link_change_wq; + +#endif + // Qos related. Added by Annie, 2005-11-01. + //STA_QOS StaQos; + + //u32 STA_EDCA_PARAM[4]; + //CHANNEL_ACCESS_SETTING ChannelAccessSetting; + + + /* Callback functions */ + void (*set_security)(struct net_device *dev, + struct ieee80211_security *sec); + + /* Used to TX data frame by using txb structs. + * this is not used if in the softmac_features + * is set the flag IEEE_SOFTMAC_TX_QUEUE + */ + int (*hard_start_xmit)(struct ieee80211_txb *txb, + struct net_device *dev); + + int (*reset_port)(struct net_device *dev); + int (*is_queue_full) (struct net_device * dev, int pri); + + int (*handle_management) (struct net_device * dev, + struct ieee80211_network * network, u16 type); + int (*is_qos_active) (struct net_device *dev, struct sk_buff *skb); + + /* Softmac-generated frames (mamagement) are TXed via this + * callback if the flag IEEE_SOFTMAC_SINGLE_QUEUE is + * not set. As some cards may have different HW queues that + * one might want to use for data and management frames + * the option to have two callbacks might be useful. + * This fucntion can't sleep. + */ + int (*softmac_hard_start_xmit)(struct sk_buff *skb, + struct net_device *dev); + + /* used instead of hard_start_xmit (not softmac_hard_start_xmit) + * if the IEEE_SOFTMAC_TX_QUEUE feature is used to TX data + * frames. I the option IEEE_SOFTMAC_SINGLE_QUEUE is also set + * then also management frames are sent via this callback. + * This function can't sleep. + */ + void (*softmac_data_hard_start_xmit)(struct sk_buff *skb, + struct net_device *dev,int rate); + + /* stops the HW queue for DATA frames. Useful to avoid + * waste time to TX data frame when we are reassociating + * This function can sleep. + */ + void (*data_hard_stop)(struct net_device *dev); + + /* OK this is complementar to data_poll_hard_stop */ + void (*data_hard_resume)(struct net_device *dev); + + /* ask to the driver to retune the radio . + * This function can sleep. the driver should ensure + * the radio has been swithced before return. + */ + void (*set_chan)(struct net_device *dev,short ch); + + /* These are not used if the ieee stack takes care of + * scanning (IEEE_SOFTMAC_SCAN feature set). + * In this case only the set_chan is used. + * + * The syncro version is similar to the start_scan but + * does not return until all channels has been scanned. + * this is called in user context and should sleep, + * it is called in a work_queue when swithcing to ad-hoc mode + * or in behalf of iwlist scan when the card is associated + * and root user ask for a scan. + * the fucntion stop_scan should stop both the syncro and + * background scanning and can sleep. + * The fucntion start_scan should initiate the background + * scanning and can't sleep. + */ + void (*scan_syncro)(struct net_device *dev); + void (*start_scan)(struct net_device *dev); + void (*stop_scan)(struct net_device *dev); + + /* indicate the driver that the link state is changed + * for example it may indicate the card is associated now. + * Driver might be interested in this to apply RX filter + * rules or simply light the LINK led + */ + void (*link_change)(struct net_device *dev); + + /* these two function indicates to the HW when to start + * and stop to send beacons. This is used when the + * IEEE_SOFTMAC_BEACONS is not set. For now the + * stop_send_bacons is NOT guaranteed to be called only + * after start_send_beacons. + */ + void (*start_send_beacons) (struct net_device *dev); + void (*stop_send_beacons) (struct net_device *dev); + + /* power save mode related */ + void (*sta_wake_up) (struct net_device *dev); +// void (*ps_request_tx_ack) (struct net_device *dev); + void (*enter_sleep_state) (struct net_device *dev, u32 th, u32 tl); + short (*ps_is_queue_empty) (struct net_device *dev); +#if 0 + /* Typical STA methods */ + int (*handle_auth) (struct net_device * dev, + struct ieee80211_auth * auth); + int (*handle_deauth) (struct net_device * dev, + struct ieee80211_deauth * auth); + int (*handle_action) (struct net_device * dev, + struct ieee80211_action * action, + struct ieee80211_rx_stats * stats); + int (*handle_disassoc) (struct net_device * dev, + struct ieee80211_disassoc * assoc); +#endif + int (*handle_beacon) (struct net_device * dev, struct ieee80211_beacon * beacon, struct ieee80211_network * network); +#if 0 + int (*handle_probe_response) (struct net_device * dev, + struct ieee80211_probe_response * resp, + struct ieee80211_network * network); + int (*handle_probe_request) (struct net_device * dev, + struct ieee80211_probe_request * req, + struct ieee80211_rx_stats * stats); +#endif + int (*handle_assoc_response) (struct net_device * dev, struct ieee80211_assoc_response_frame * resp, struct ieee80211_network * network); + +#if 0 + /* Typical AP methods */ + int (*handle_assoc_request) (struct net_device * dev); + int (*handle_reassoc_request) (struct net_device * dev, + struct ieee80211_reassoc_request * req); +#endif + + /* check whether Tx hw resouce available */ + short (*check_nic_enough_desc)(struct net_device *dev, int queue_index); + //added by wb for HT related +// void (*SwChnlByTimerHandler)(struct net_device *dev, int channel); + void (*SetBWModeHandler)(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset); +// void (*UpdateHalRATRTableHandler)(struct net_device* dev, u8* pMcsRate); + bool (*GetNmodeSupportBySecCfg)(struct net_device* dev); + void (*SetWirelessMode)(struct net_device* dev, u8 wireless_mode); + bool (*GetHalfNmodeSupportByAPsHandler)(struct net_device* dev); + bool (*is_ap_in_wep_tkip)(struct net_device* dev); + void (*InitialGainHandler)(struct net_device *dev, u8 Operation); + bool (*SetFwCmdHandler)(struct net_device *dev, FW_CMD_IO_TYPE FwCmdIO); + void (*LedControlHandler)(struct net_device * dev, LED_CTL_MODE LedAction); + /* This must be the last item so that it points to the data + * allocated beyond this structure by alloc_ieee80211 */ + u8 priv[0]; +}; + +#define IEEE_A (1<<0) +#define IEEE_B (1<<1) +#define IEEE_G (1<<2) +#define IEEE_N_24G (1<<4) +#define IEEE_N_5G (1<<5) +#define IEEE_MODE_MASK (IEEE_A|IEEE_B|IEEE_G) + +/* Generate a 802.11 header */ + +/* Uses the channel change callback directly + * instead of [start/stop] scan callbacks + */ +#define IEEE_SOFTMAC_SCAN (1<<2) + +/* Perform authentication and association handshake */ +#define IEEE_SOFTMAC_ASSOCIATE (1<<3) + +/* Generate probe requests */ +#define IEEE_SOFTMAC_PROBERQ (1<<4) + +/* Generate respones to probe requests */ +#define IEEE_SOFTMAC_PROBERS (1<<5) + +/* The ieee802.11 stack will manages the netif queue + * wake/stop for the driver, taking care of 802.11 + * fragmentation. See softmac.c for details. */ +#define IEEE_SOFTMAC_TX_QUEUE (1<<7) + +/* Uses only the softmac_data_hard_start_xmit + * even for TX management frames. + */ +#define IEEE_SOFTMAC_SINGLE_QUEUE (1<<8) + +/* Generate beacons. The stack will enqueue beacons + * to the card + */ +#define IEEE_SOFTMAC_BEACONS (1<<6) + +static inline void *ieee80211_priv(struct net_device *dev) +{ +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + return ((struct ieee80211_device *)netdev_priv(dev))->priv; +#else + return ((struct ieee80211_device *)dev->priv)->priv; +#endif +} + +extern inline int ieee80211_is_empty_essid(const char *essid, int essid_len) +{ + /* Single white space is for Linksys APs */ + if (essid_len == 1 && essid[0] == ' ') + return 1; + + /* Otherwise, if the entire essid is 0, we assume it is hidden */ + while (essid_len) { + essid_len--; + if (essid[essid_len] != '\0') + return 0; + } + + return 1; +} + +extern inline int ieee80211_is_valid_mode(struct ieee80211_device *ieee, int mode) +{ + /* + * It is possible for both access points and our device to support + * combinations of modes, so as long as there is one valid combination + * of ap/device supported modes, then return success + * + */ + if ((mode & IEEE_A) && + (ieee->modulation & IEEE80211_OFDM_MODULATION) && + (ieee->freq_band & IEEE80211_52GHZ_BAND)) + return 1; + + if ((mode & IEEE_G) && + (ieee->modulation & IEEE80211_OFDM_MODULATION) && + (ieee->freq_band & IEEE80211_24GHZ_BAND)) + return 1; + + if ((mode & IEEE_B) && + (ieee->modulation & IEEE80211_CCK_MODULATION) && + (ieee->freq_band & IEEE80211_24GHZ_BAND)) + return 1; + + return 0; +} + +extern inline int ieee80211_get_hdrlen(u16 fc) +{ + int hdrlen = IEEE80211_3ADDR_LEN; + + switch (WLAN_FC_GET_TYPE(fc)) { + case IEEE80211_FTYPE_DATA: + if ((fc & IEEE80211_FCTL_FROMDS) && (fc & IEEE80211_FCTL_TODS)) + hdrlen = IEEE80211_4ADDR_LEN; /* Addr4 */ + if(IEEE80211_QOS_HAS_SEQ(fc)) + hdrlen += 2; /* QOS ctrl*/ + break; + case IEEE80211_FTYPE_CTL: + switch (WLAN_FC_GET_STYPE(fc)) { + case IEEE80211_STYPE_CTS: + case IEEE80211_STYPE_ACK: + hdrlen = IEEE80211_1ADDR_LEN; + break; + default: + hdrlen = IEEE80211_2ADDR_LEN; + break; + } + break; + } + + return hdrlen; +} + +static inline u8 *ieee80211_get_payload(struct ieee80211_hdr *hdr) +{ + switch (ieee80211_get_hdrlen(le16_to_cpu(hdr->frame_ctl))) { + case IEEE80211_1ADDR_LEN: + return ((struct ieee80211_hdr_1addr *)hdr)->payload; + case IEEE80211_2ADDR_LEN: + return ((struct ieee80211_hdr_2addr *)hdr)->payload; + case IEEE80211_3ADDR_LEN: + return ((struct ieee80211_hdr_3addr *)hdr)->payload; + case IEEE80211_4ADDR_LEN: + return ((struct ieee80211_hdr_4addr *)hdr)->payload; + } + return NULL; +} + +static inline int ieee80211_is_ofdm_rate(u8 rate) +{ + switch (rate & ~IEEE80211_BASIC_RATE_MASK) { + case IEEE80211_OFDM_RATE_6MB: + case IEEE80211_OFDM_RATE_9MB: + case IEEE80211_OFDM_RATE_12MB: + case IEEE80211_OFDM_RATE_18MB: + case IEEE80211_OFDM_RATE_24MB: + case IEEE80211_OFDM_RATE_36MB: + case IEEE80211_OFDM_RATE_48MB: + case IEEE80211_OFDM_RATE_54MB: + return 1; + } + return 0; +} + +static inline int ieee80211_is_cck_rate(u8 rate) +{ + switch (rate & ~IEEE80211_BASIC_RATE_MASK) { + case IEEE80211_CCK_RATE_1MB: + case IEEE80211_CCK_RATE_2MB: + case IEEE80211_CCK_RATE_5MB: + case IEEE80211_CCK_RATE_11MB: + return 1; + } + return 0; +} + + +/* ieee80211.c */ +extern void free_ieee80211(struct net_device *dev); +extern struct net_device *alloc_ieee80211(int sizeof_priv); + +extern int ieee80211_set_encryption(struct ieee80211_device *ieee); + +/* ieee80211_tx.c */ + +extern int ieee80211_encrypt_fragment( + struct ieee80211_device *ieee, + struct sk_buff *frag, + int hdr_len); + +extern int ieee80211_xmit(struct sk_buff *skb, + struct net_device *dev); +extern void ieee80211_txb_free(struct ieee80211_txb *); + + +/* ieee80211_rx.c */ +extern int ieee80211_rx(struct ieee80211_device *ieee, struct sk_buff *skb, + struct ieee80211_rx_stats *rx_stats); +extern void ieee80211_rx_mgt(struct ieee80211_device *ieee, + struct ieee80211_hdr_4addr *header, + struct ieee80211_rx_stats *stats); + +/* ieee80211_wx.c */ +extern int ieee80211_wx_get_scan(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data *wrqu, char *key); +extern int ieee80211_wx_set_encode(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data *wrqu, char *key); +extern int ieee80211_wx_get_encode(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data *wrqu, char *key); +#if WIRELESS_EXT >= 18 +extern int ieee80211_wx_get_encode_ext(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data* wrqu, char *extra); +extern int ieee80211_wx_set_encode_ext(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data* wrqu, char *extra); +extern int ieee80211_wx_set_auth(struct ieee80211_device *ieee, + struct iw_request_info *info, + struct iw_param *data, char *extra); +extern int ieee80211_wx_set_mlme(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); +#endif +extern int ieee80211_wx_set_gen_ie(struct ieee80211_device *ieee, u8 *ie, size_t len); + +/* ieee80211_softmac.c */ +extern short ieee80211_is_54g(struct ieee80211_network net); +extern short ieee80211_is_shortslot(struct ieee80211_network net); +extern int ieee80211_rx_frame_softmac(struct ieee80211_device *ieee, struct sk_buff *skb, + struct ieee80211_rx_stats *rx_stats, u16 type, + u16 stype); +extern void ieee80211_softmac_new_net(struct ieee80211_device *ieee, struct ieee80211_network *net); + +void SendDisassociation(struct ieee80211_device *ieee, u8* asSta, u8 asRsn); +extern void ieee80211_softmac_xmit(struct ieee80211_txb *txb, struct ieee80211_device *ieee); + +extern void ieee80211_stop_send_beacons(struct ieee80211_device *ieee); +extern void notify_wx_assoc_event(struct ieee80211_device *ieee); +extern void ieee80211_softmac_check_all_nets(struct ieee80211_device *ieee); +extern void ieee80211_start_bss(struct ieee80211_device *ieee); +extern void ieee80211_start_master_bss(struct ieee80211_device *ieee); +extern void ieee80211_start_ibss(struct ieee80211_device *ieee); +extern void ieee80211_softmac_init(struct ieee80211_device *ieee); +extern void ieee80211_softmac_free(struct ieee80211_device *ieee); +extern void ieee80211_associate_abort(struct ieee80211_device *ieee); +extern void ieee80211_disassociate(struct ieee80211_device *ieee); +extern void ieee80211_stop_scan(struct ieee80211_device *ieee); +extern void ieee80211_start_scan_syncro(struct ieee80211_device *ieee); +extern void ieee80211_check_all_nets(struct ieee80211_device *ieee); +extern void ieee80211_start_protocol(struct ieee80211_device *ieee); +extern void ieee80211_stop_protocol(struct ieee80211_device *ieee); +extern void ieee80211_softmac_start_protocol(struct ieee80211_device *ieee); +extern void ieee80211_softmac_stop_protocol(struct ieee80211_device *ieee); +extern void ieee80211_reset_queue(struct ieee80211_device *ieee); +extern void ieee80211_wake_queue(struct ieee80211_device *ieee); +extern void ieee80211_stop_queue(struct ieee80211_device *ieee); +extern struct sk_buff *ieee80211_get_beacon(struct ieee80211_device *ieee); +extern void ieee80211_start_send_beacons(struct ieee80211_device *ieee); +extern void ieee80211_stop_send_beacons(struct ieee80211_device *ieee); +extern int ieee80211_wpa_supplicant_ioctl(struct ieee80211_device *ieee, struct iw_point *p); +extern void notify_wx_assoc_event(struct ieee80211_device *ieee); +extern void ieee80211_ps_tx_ack(struct ieee80211_device *ieee, short success); + +extern void softmac_mgmt_xmit(struct sk_buff *skb, struct ieee80211_device *ieee); + +/* ieee80211_crypt_ccmp&tkip&wep.c */ +extern void ieee80211_tkip_null(void); +extern void ieee80211_wep_null(void); +extern void ieee80211_ccmp_null(void); + +/* ieee80211_softmac_wx.c */ + +extern int ieee80211_wx_get_wap(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data *wrqu, char *ext); + +extern int ieee80211_wx_set_wap(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data *awrq, + char *extra); + +extern int ieee80211_wx_get_essid(struct ieee80211_device *ieee, struct iw_request_info *a,union iwreq_data *wrqu,char *b); + +extern int ieee80211_wx_set_rate(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); + +extern int ieee80211_wx_get_rate(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); + +extern int ieee80211_wx_set_mode(struct ieee80211_device *ieee, struct iw_request_info *a, + union iwreq_data *wrqu, char *b); + +extern int ieee80211_wx_set_scan(struct ieee80211_device *ieee, struct iw_request_info *a, + union iwreq_data *wrqu, char *b); + +extern int ieee80211_wx_set_essid(struct ieee80211_device *ieee, + struct iw_request_info *a, + union iwreq_data *wrqu, char *extra); + +extern int ieee80211_wx_get_mode(struct ieee80211_device *ieee, struct iw_request_info *a, + union iwreq_data *wrqu, char *b); + +extern int ieee80211_wx_set_freq(struct ieee80211_device *ieee, struct iw_request_info *a, + union iwreq_data *wrqu, char *b); + +extern int ieee80211_wx_get_freq(struct ieee80211_device *ieee, struct iw_request_info *a, + union iwreq_data *wrqu, char *b); + +//extern void ieee80211_wx_sync_scan_wq(struct ieee80211_device *ieee); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) +extern void ieee80211_wx_sync_scan_wq(struct work_struct *work); +#else + extern void ieee80211_wx_sync_scan_wq(struct ieee80211_device *ieee); +#endif + + +extern int ieee80211_wx_set_rawtx(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); + +extern int ieee80211_wx_get_name(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); + +extern int ieee80211_wx_set_power(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); + +extern int ieee80211_wx_get_power(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); + +extern int ieee80211_wx_set_rts(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); + +extern int ieee80211_wx_get_rts(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); +//HT +#define MAX_RECEIVE_BUFFER_SIZE 9100 // +extern void HTDebugHTCapability(u8* CapIE, u8* TitleString ); +extern void HTDebugHTInfo(u8* InfoIE, u8* TitleString); + +void HTSetConnectBwMode(struct ieee80211_device* ieee, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset); +extern void HTUpdateDefaultSetting(struct ieee80211_device* ieee); +extern void HTConstructCapabilityElement(struct ieee80211_device* ieee, u8* posHTCap, u8* len, u8 isEncrypt); +extern void HTConstructInfoElement(struct ieee80211_device* ieee, u8* posHTInfo, u8* len, u8 isEncrypt); +extern void HTConstructRT2RTAggElement(struct ieee80211_device* ieee, u8* posRT2RTAgg, u8* len); +extern void HTOnAssocRsp(struct ieee80211_device *ieee); +extern void HTInitializeHTInfo(struct ieee80211_device* ieee); +extern void HTInitializeBssDesc(PBSS_HT pBssHT); +extern void HTResetSelfAndSavePeerSetting(struct ieee80211_device* ieee, struct ieee80211_network * pNetwork); +extern void HTUpdateSelfAndPeerSetting(struct ieee80211_device* ieee, struct ieee80211_network * pNetwork); +extern u8 HTGetHighestMCSRate(struct ieee80211_device* ieee, u8* pMCSRateSet, u8* pMCSFilter); +extern u8 MCS_FILTER_ALL[]; +extern u16 MCS_DATA_RATE[2][2][77] ; +extern u8 HTCCheck(struct ieee80211_device* ieee, u8* pFrame); +//extern void HTSetConnectBwModeCallback(unsigned long data); +extern void HTResetIOTSetting(PRT_HIGH_THROUGHPUT pHTInfo); +extern bool IsHTHalfNmodeAPs(struct ieee80211_device* ieee); +extern u16 HTHalfMcsToDataRate(struct ieee80211_device* ieee, u8 nMcsRate); +extern u16 HTMcsToDataRate( struct ieee80211_device* ieee, u8 nMcsRate); +extern u16 TxCountToDataRate( struct ieee80211_device* ieee, u8 nDataRate); +//function in BAPROC.c +extern int ieee80211_rx_ADDBAReq( struct ieee80211_device* ieee, struct sk_buff *skb); +extern int ieee80211_rx_ADDBARsp( struct ieee80211_device* ieee, struct sk_buff *skb); +extern int ieee80211_rx_DELBA(struct ieee80211_device* ieee,struct sk_buff *skb); +extern void TsInitAddBA( struct ieee80211_device* ieee, PTX_TS_RECORD pTS, u8 Policy, u8 bOverwritePending); +extern void TsInitDelBA( struct ieee80211_device* ieee, PTS_COMMON_INFO pTsCommonInfo, TR_SELECT TxRxSelect); +extern void BaSetupTimeOut(unsigned long data); +extern void TxBaInactTimeout(unsigned long data); +extern void RxBaInactTimeout(unsigned long data); +extern void ResetBaEntry( PBA_RECORD pBA); +//function in TS.c +extern bool GetTs( + struct ieee80211_device* ieee, + PTS_COMMON_INFO *ppTS, + u8* Addr, + u8 TID, + TR_SELECT TxRxSelect, //Rx:1, Tx:0 + bool bAddNewTs + ); +extern void TSInitialize(struct ieee80211_device *ieee); +extern void TsStartAddBaProcess(struct ieee80211_device* ieee, PTX_TS_RECORD pTxTS); +extern void RemovePeerTS(struct ieee80211_device* ieee, u8* Addr); +extern void RemoveAllTS(struct ieee80211_device* ieee); +void ieee80211_softmac_scan_syncro(struct ieee80211_device *ieee); + +extern const long ieee80211_wlan_frequencies[]; + +extern inline void ieee80211_increment_scans(struct ieee80211_device *ieee) +{ + ieee->scans++; +} + +extern inline int ieee80211_get_scans(struct ieee80211_device *ieee) +{ + return ieee->scans; +} + +static inline const char *escape_essid(const char *essid, u8 essid_len) { + static char escaped[IW_ESSID_MAX_SIZE * 2 + 1]; + const char *s = essid; + char *d = escaped; + + if (ieee80211_is_empty_essid(essid, essid_len)) { + memcpy(escaped, "<hidden>", sizeof("<hidden>")); + return escaped; + } + + essid_len = min(essid_len, (u8)IW_ESSID_MAX_SIZE); + while (essid_len--) { + if (*s == '\0') { + *d++ = '\\'; + *d++ = '0'; + s++; + } else { + *d++ = *s++; + } + } + *d = '\0'; + return escaped; +} + +/* For the function is more related to hardware setting, it's better to use the + * ieee handler to refer to it. + */ +extern short check_nic_enough_desc(struct net_device *dev, int queue_index); +extern int ieee80211_data_xmit(struct sk_buff *skb, struct net_device *dev); +extern int ieee80211_parse_info_param(struct ieee80211_device *ieee, + struct ieee80211_info_element *info_element, + u16 length, + struct ieee80211_network *network, + struct ieee80211_rx_stats *stats); + +void ieee80211_indicate_packets(struct ieee80211_device *ieee, struct ieee80211_rxb** prxbIndicateArray,u8 index); +#define RT_ASOC_RETRY_LIMIT 5 +#endif /* IEEE80211_H */ diff --git a/drivers/staging/rtl8192su/ieee80211/EndianFree.h b/drivers/staging/rtl8192su/ieee80211/EndianFree.h new file mode 100644 index 000000000000..0c417a6234a9 --- /dev/null +++ b/drivers/staging/rtl8192su/ieee80211/EndianFree.h @@ -0,0 +1,199 @@ +#ifndef __INC_ENDIANFREE_H +#define __INC_ENDIANFREE_H + +/* + * Call endian free function when + * 1. Read/write packet content. + * 2. Before write integer to IO. + * 3. After read integer from IO. + */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)) +#ifndef bool +typedef enum{false = 0, true} bool; +#endif +#endif + +#define __MACHINE_LITTLE_ENDIAN 1234 /* LSB first: i386, vax */ +#define __MACHINE_BIG_ENDIAN 4321 /* MSB first: 68000, ibm, net, ppc */ + +#define BYTE_ORDER __MACHINE_LITTLE_ENDIAN + +#if BYTE_ORDER == __MACHINE_LITTLE_ENDIAN +// Convert data +#define EF1Byte(_val) ((u8)(_val)) +#define EF2Byte(_val) ((u16)(_val)) +#define EF4Byte(_val) ((u32)(_val)) + +#else +// Convert data +#define EF1Byte(_val) ((u8)(_val)) +#define EF2Byte(_val) (((((u16)(_val))&0x00ff)<<8)|((((u16)(_val))&0xff00)>>8)) +#define EF4Byte(_val) (((((u32)(_val))&0x000000ff)<<24)|\ + ((((u32)(_val))&0x0000ff00)<<8)|\ + ((((u32)(_val))&0x00ff0000)>>8)|\ + ((((u32)(_val))&0xff000000)>>24)) +#endif + +// Read data from memory +#define ReadEF1Byte(_ptr) EF1Byte(*((u8 *)(_ptr))) +#define ReadEF2Byte(_ptr) EF2Byte(*((u16 *)(_ptr))) +#define ReadEF4Byte(_ptr) EF4Byte(*((u32 *)(_ptr))) + +// Write data to memory +#define WriteEF1Byte(_ptr, _val) (*((u8 *)(_ptr)))=EF1Byte(_val) +#define WriteEF2Byte(_ptr, _val) (*((u16 *)(_ptr)))=EF2Byte(_val) +#define WriteEF4Byte(_ptr, _val) (*((u32 *)(_ptr)))=EF4Byte(_val) +// Convert Host system specific byte ording (litten or big endia) to Network byte ording (big endian). +// 2006.05.07, by rcnjko. +#if BYTE_ORDER == __MACHINE_LITTLE_ENDIAN +#define H2N1BYTE(_val) ((u8)(_val)) +#define H2N2BYTE(_val) (((((u16)(_val))&0x00ff)<<8)|\ + ((((u16)(_val))&0xff00)>>8)) +#define H2N4BYTE(_val) (((((u32)(_val))&0x000000ff)<<24)|\ + ((((u32)(_val))&0x0000ff00)<<8) |\ + ((((u32)(_val))&0x00ff0000)>>8) |\ + ((((u32)(_val))&0xff000000)>>24)) +#else +#define H2N1BYTE(_val) ((u8)(_val)) +#define H2N2BYTE(_val) ((u16)(_val)) +#define H2N4BYTE(_val) ((u32)(_val)) +#endif + +// Convert from Network byte ording (big endian) to Host system specific byte ording (litten or big endia). +// 2006.05.07, by rcnjko. +#if BYTE_ORDER == __MACHINE_LITTLE_ENDIAN +#define N2H1BYTE(_val) ((u8)(_val)) +#define N2H2BYTE(_val) (((((u16)(_val))&0x00ff)<<8)|\ + ((((u16)(_val))&0xff00)>>8)) +#define N2H4BYTE(_val) (((((u32)(_val))&0x000000ff)<<24)|\ + ((((u32)(_val))&0x0000ff00)<<8) |\ + ((((u32)(_val))&0x00ff0000)>>8) |\ + ((((u32)(_val))&0xff000000)>>24)) +#else +#define N2H1BYTE(_val) ((u8)(_val)) +#define N2H2BYTE(_val) ((u16)(_val)) +#define N2H4BYTE(_val) ((u32)(_val)) +#endif + +// +// Example: +// BIT_LEN_MASK_32(0) => 0x00000000 +// BIT_LEN_MASK_32(1) => 0x00000001 +// BIT_LEN_MASK_32(2) => 0x00000003 +// BIT_LEN_MASK_32(32) => 0xFFFFFFFF +// +#define BIT_LEN_MASK_32(__BitLen) (0xFFFFFFFF >> (32 - (__BitLen))) +// +// Example: +// BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003 +// BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000 +// +#define BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) (BIT_LEN_MASK_32(__BitLen) << (__BitOffset)) + +// +// Description: +// Return 4-byte value in host byte ordering from +// 4-byte pointer in litten-endian system. +// +#define LE_P4BYTE_TO_HOST_4BYTE(__pStart) (EF4Byte(*((u32 *)(__pStart)))) + +// +// Description: +// Translate subfield (continuous bits in little-endian) of 4-byte value in litten byte to +// 4-byte value in host byte ordering. +// +#define LE_BITS_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ + ( \ + ( LE_P4BYTE_TO_HOST_4BYTE(__pStart) >> (__BitOffset) ) \ + & \ + BIT_LEN_MASK_32(__BitLen) \ + ) + +// +// Description: +// Mask subfield (continuous bits in little-endian) of 4-byte value in litten byte oredering +// and return the result in 4-byte value in host byte ordering. +// +#define LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ + ( \ + LE_P4BYTE_TO_HOST_4BYTE(__pStart) \ + & \ + ( ~BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) ) \ + ) + +// +// Description: +// Set subfield of little-endian 4-byte value to specified value. +// +#define SET_BITS_TO_LE_4BYTE(__pStart, __BitOffset, __BitLen, __Value) \ + *((u32 *)(__pStart)) = \ + EF4Byte( \ + LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ + | \ + ( (((u32)__Value) & BIT_LEN_MASK_32(__BitLen)) << (__BitOffset) ) \ + ); + + +#define BIT_LEN_MASK_16(__BitLen) \ + (0xFFFF >> (16 - (__BitLen))) + +#define BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen) \ + (BIT_LEN_MASK_16(__BitLen) << (__BitOffset)) + +#define LE_P2BYTE_TO_HOST_2BYTE(__pStart) \ + (EF2Byte(*((u16 *)(__pStart)))) + +#define LE_BITS_TO_2BYTE(__pStart, __BitOffset, __BitLen) \ + ( \ + ( LE_P2BYTE_TO_HOST_2BYTE(__pStart) >> (__BitOffset) ) \ + & \ + BIT_LEN_MASK_16(__BitLen) \ + ) + +#define LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \ + ( \ + LE_P2BYTE_TO_HOST_2BYTE(__pStart) \ + & \ + ( ~BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen) ) \ + ) + +#define SET_BITS_TO_LE_2BYTE(__pStart, __BitOffset, __BitLen, __Value) \ + *((u16 *)(__pStart)) = \ + EF2Byte( \ + LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \ + | \ + ( (((u16)__Value) & BIT_LEN_MASK_16(__BitLen)) << (__BitOffset) ) \ + ); + +#define BIT_LEN_MASK_8(__BitLen) \ + (0xFF >> (8 - (__BitLen))) + +#define BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen) \ + (BIT_LEN_MASK_8(__BitLen) << (__BitOffset)) + +#define LE_P1BYTE_TO_HOST_1BYTE(__pStart) \ + (EF1Byte(*((u8 *)(__pStart)))) + +#define LE_BITS_TO_1BYTE(__pStart, __BitOffset, __BitLen) \ + ( \ + ( LE_P1BYTE_TO_HOST_1BYTE(__pStart) >> (__BitOffset) ) \ + & \ + BIT_LEN_MASK_8(__BitLen) \ + ) + +#define LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \ + ( \ + LE_P1BYTE_TO_HOST_1BYTE(__pStart) \ + & \ + ( ~BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen) ) \ + ) + +#define SET_BITS_TO_LE_1BYTE(__pStart, __BitOffset, __BitLen, __Value) \ + *((u8 *)(__pStart)) = \ + EF1Byte( \ + LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \ + | \ + ( (((u8)__Value) & BIT_LEN_MASK_8(__BitLen)) << (__BitOffset) ) \ + ); + +#endif // #ifndef __INC_ENDIANFREE_H diff --git a/drivers/staging/rtl8192su/ieee80211/Makefile b/drivers/staging/rtl8192su/ieee80211/Makefile new file mode 100644 index 000000000000..295a18f3c9ca --- /dev/null +++ b/drivers/staging/rtl8192su/ieee80211/Makefile @@ -0,0 +1,31 @@ +NIC_SELECT = RTL8192SU + +EXTRA_CFLAGS += -O2 +EXTRA_CFLAGS += -DRTL8192S_DISABLE_FW_DM=0 +EXTRA_CFLAGS += -DRTL8192SU +#EXTRA_CFLAGS += -DJOHN_NOCPY +EXTRA_CFLAGS += -DTHOMAS_TURBO +#flags to enable or disble 80211D feature +EXTRA_CFLAGS += -DENABLE_DOT11D +ieee80211-rsl-objs := ieee80211_rx.o \ + ieee80211_softmac.o \ + ieee80211_tx.o \ + ieee80211_wx.o \ + ieee80211_module.o \ + ieee80211_softmac_wx.o\ + rtl819x_HTProc.o\ + rtl819x_TSProc.o\ + rtl819x_BAProc.o\ + dot11d.o + +ieee80211_crypt-rsl-objs := ieee80211_crypt.o +ieee80211_crypt_tkip-rsl-objs := ieee80211_crypt_tkip.o +ieee80211_crypt_ccmp-rsl-objs := ieee80211_crypt_ccmp.o +ieee80211_crypt_wep-rsl-objs := ieee80211_crypt_wep.o + +obj-m +=ieee80211-rsl.o +obj-m +=ieee80211_crypt-rsl.o +obj-m +=ieee80211_crypt_wep-rsl.o +obj-m +=ieee80211_crypt_tkip-rsl.o +obj-m +=ieee80211_crypt_ccmp-rsl.o + diff --git a/drivers/staging/rtl8192su/ieee80211/aes.c b/drivers/staging/rtl8192su/ieee80211/aes.c new file mode 100644 index 000000000000..0c176e29a797 --- /dev/null +++ b/drivers/staging/rtl8192su/ieee80211/aes.c @@ -0,0 +1,469 @@ +/* + * Cryptographic API. + * + * AES Cipher Algorithm. + * + * Based on Brian Gladman's code. + * + * Linux developers: + * Alexander Kjeldaas <astor@fast.no> + * Herbert Valerio Riedel <hvr@hvrlab.org> + * Kyle McMartin <kyle@debian.org> + * Adam J. Richter <adam@yggdrasil.com> (conversion to 2.5 API). + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * --------------------------------------------------------------------------- + * Copyright (c) 2002, Dr Brian Gladman <brg@gladman.me.uk>, Worcester, UK. + * All rights reserved. + * + * LICENSE TERMS + * + * The free distribution and use of this software in both source and binary + * form is allowed (with or without changes) provided that: + * + * 1. distributions of this source code include the above copyright + * notice, this list of conditions and the following disclaimer; + * + * 2. distributions in binary form include the above copyright + * notice, this list of conditions and the following disclaimer + * in the documentation and/or other associated materials; + * + * 3. the copyright holder's name is not used to endorse products + * built using this software without specific written permission. + * + * ALTERNATIVELY, provided that this notice is retained in full, this product + * may be distributed under the terms of the GNU General Public License (GPL), + * in which case the provisions of the GPL apply INSTEAD OF those given above. + * + * DISCLAIMER + * + * This software is provided 'as is' with no explicit or implied warranties + * in respect of its properties, including, but not limited to, correctness + * and/or fitness for purpose. + * --------------------------------------------------------------------------- + */ + +/* Some changes from the Gladman version: + s/RIJNDAEL(e_key)/E_KEY/g + s/RIJNDAEL(d_key)/D_KEY/g +*/ + +#include <linux/module.h> +#include <linux/init.h> +#include <linux/types.h> +#include <linux/errno.h> +//#include <linux/crypto.h> +#include "rtl_crypto.h" +#include <asm/byteorder.h> + +#define AES_MIN_KEY_SIZE 16 +#define AES_MAX_KEY_SIZE 32 + +#define AES_BLOCK_SIZE 16 + +static inline +u32 generic_rotr32 (const u32 x, const unsigned bits) +{ + const unsigned n = bits % 32; + return (x >> n) | (x << (32 - n)); +} + +static inline +u32 generic_rotl32 (const u32 x, const unsigned bits) +{ + const unsigned n = bits % 32; + return (x << n) | (x >> (32 - n)); +} + +#define rotl generic_rotl32 +#define rotr generic_rotr32 + +/* + * #define byte(x, nr) ((unsigned char)((x) >> (nr*8))) + */ +inline static u8 +byte(const u32 x, const unsigned n) +{ + return x >> (n << 3); +} + +#define u32_in(x) le32_to_cpu(*(const u32 *)(x)) +#define u32_out(to, from) (*(u32 *)(to) = cpu_to_le32(from)) + +struct aes_ctx { + int key_length; + u32 E[60]; + u32 D[60]; +}; + +#define E_KEY ctx->E +#define D_KEY ctx->D + +static u8 pow_tab[256] __initdata; +static u8 log_tab[256] __initdata; +static u8 sbx_tab[256] __initdata; +static u8 isb_tab[256] __initdata; +static u32 rco_tab[10]; +static u32 ft_tab[4][256]; +static u32 it_tab[4][256]; + +static u32 fl_tab[4][256]; +static u32 il_tab[4][256]; + +static inline u8 __init +f_mult (u8 a, u8 b) +{ + u8 aa = log_tab[a], cc = aa + log_tab[b]; + + return pow_tab[cc + (cc < aa ? 1 : 0)]; +} + +#define ff_mult(a,b) (a && b ? f_mult(a, b) : 0) + +#define f_rn(bo, bi, n, k) \ + bo[n] = ft_tab[0][byte(bi[n],0)] ^ \ + ft_tab[1][byte(bi[(n + 1) & 3],1)] ^ \ + ft_tab[2][byte(bi[(n + 2) & 3],2)] ^ \ + ft_tab[3][byte(bi[(n + 3) & 3],3)] ^ *(k + n) + +#define i_rn(bo, bi, n, k) \ + bo[n] = it_tab[0][byte(bi[n],0)] ^ \ + it_tab[1][byte(bi[(n + 3) & 3],1)] ^ \ + it_tab[2][byte(bi[(n + 2) & 3],2)] ^ \ + it_tab[3][byte(bi[(n + 1) & 3],3)] ^ *(k + n) + +#define ls_box(x) \ + ( fl_tab[0][byte(x, 0)] ^ \ + fl_tab[1][byte(x, 1)] ^ \ + fl_tab[2][byte(x, 2)] ^ \ + fl_tab[3][byte(x, 3)] ) + +#define f_rl(bo, bi, n, k) \ + bo[n] = fl_tab[0][byte(bi[n],0)] ^ \ + fl_tab[1][byte(bi[(n + 1) & 3],1)] ^ \ + fl_tab[2][byte(bi[(n + 2) & 3],2)] ^ \ + fl_tab[3][byte(bi[(n + 3) & 3],3)] ^ *(k + n) + +#define i_rl(bo, bi, n, k) \ + bo[n] = il_tab[0][byte(bi[n],0)] ^ \ + il_tab[1][byte(bi[(n + 3) & 3],1)] ^ \ + il_tab[2][byte(bi[(n + 2) & 3],2)] ^ \ + il_tab[3][byte(bi[(n + 1) & 3],3)] ^ *(k + n) + +static void __init +gen_tabs (void) +{ + u32 i, t; + u8 p, q; + + /* log and power tables for GF(2**8) finite field with + 0x011b as modular polynomial - the simplest primitive + root is 0x03, used here to generate the tables */ + + for (i = 0, p = 1; i < 256; ++i) { + pow_tab[i] = (u8) p; + log_tab[p] = (u8) i; + + p ^= (p << 1) ^ (p & 0x80 ? 0x01b : 0); + } + + log_tab[1] = 0; + + for (i = 0, p = 1; i < 10; ++i) { + rco_tab[i] = p; + + p = (p << 1) ^ (p & 0x80 ? 0x01b : 0); + } + + for (i = 0; i < 256; ++i) { + p = (i ? pow_tab[255 - log_tab[i]] : 0); + q = ((p >> 7) | (p << 1)) ^ ((p >> 6) | (p << 2)); + p ^= 0x63 ^ q ^ ((q >> 6) | (q << 2)); + sbx_tab[i] = p; + isb_tab[p] = (u8) i; + } + + for (i = 0; i < 256; ++i) { + p = sbx_tab[i]; + + t = p; + fl_tab[0][i] = t; + fl_tab[1][i] = rotl (t, 8); + fl_tab[2][i] = rotl (t, 16); + fl_tab[3][i] = rotl (t, 24); + + t = ((u32) ff_mult (2, p)) | + ((u32) p << 8) | + ((u32) p << 16) | ((u32) ff_mult (3, p) << 24); + + ft_tab[0][i] = t; + ft_tab[1][i] = rotl (t, 8); + ft_tab[2][i] = rotl (t, 16); + ft_tab[3][i] = rotl (t, 24); + + p = isb_tab[i]; + + t = p; + il_tab[0][i] = t; + il_tab[1][i] = rotl (t, 8); + il_tab[2][i] = rotl (t, 16); + il_tab[3][i] = rotl (t, 24); + + t = ((u32) ff_mult (14, p)) | + ((u32) ff_mult (9, p) << 8) | + ((u32) ff_mult (13, p) << 16) | + ((u32) ff_mult (11, p) << 24); + + it_tab[0][i] = t; + it_tab[1][i] = rotl (t, 8); + it_tab[2][i] = rotl (t, 16); + it_tab[3][i] = rotl (t, 24); + } +} + +#define star_x(x) (((x) & 0x7f7f7f7f) << 1) ^ ((((x) & 0x80808080) >> 7) * 0x1b) + +#define imix_col(y,x) \ + u = star_x(x); \ + v = star_x(u); \ + w = star_x(v); \ + t = w ^ (x); \ + (y) = u ^ v ^ w; \ + (y) ^= rotr(u ^ t, 8) ^ \ + rotr(v ^ t, 16) ^ \ + rotr(t,24) + +/* initialise the key schedule from the user supplied key */ + +#define loop4(i) \ +{ t = rotr(t, 8); t = ls_box(t) ^ rco_tab[i]; \ + t ^= E_KEY[4 * i]; E_KEY[4 * i + 4] = t; \ + t ^= E_KEY[4 * i + 1]; E_KEY[4 * i + 5] = t; \ + t ^= E_KEY[4 * i + 2]; E_KEY[4 * i + 6] = t; \ + t ^= E_KEY[4 * i + 3]; E_KEY[4 * i + 7] = t; \ +} + +#define loop6(i) \ +{ t = rotr(t, 8); t = ls_box(t) ^ rco_tab[i]; \ + t ^= E_KEY[6 * i]; E_KEY[6 * i + 6] = t; \ + t ^= E_KEY[6 * i + 1]; E_KEY[6 * i + 7] = t; \ + t ^= E_KEY[6 * i + 2]; E_KEY[6 * i + 8] = t; \ + t ^= E_KEY[6 * i + 3]; E_KEY[6 * i + 9] = t; \ + t ^= E_KEY[6 * i + 4]; E_KEY[6 * i + 10] = t; \ + t ^= E_KEY[6 * i + 5]; E_KEY[6 * i + 11] = t; \ +} + +#define loop8(i) \ +{ t = rotr(t, 8); ; t = ls_box(t) ^ rco_tab[i]; \ + t ^= E_KEY[8 * i]; E_KEY[8 * i + 8] = t; \ + t ^= E_KEY[8 * i + 1]; E_KEY[8 * i + 9] = t; \ + t ^= E_KEY[8 * i + 2]; E_KEY[8 * i + 10] = t; \ + t ^= E_KEY[8 * i + 3]; E_KEY[8 * i + 11] = t; \ + t = E_KEY[8 * i + 4] ^ ls_box(t); \ + E_KEY[8 * i + 12] = t; \ + t ^= E_KEY[8 * i + 5]; E_KEY[8 * i + 13] = t; \ + t ^= E_KEY[8 * i + 6]; E_KEY[8 * i + 14] = t; \ + t ^= E_KEY[8 * i + 7]; E_KEY[8 * i + 15] = t; \ +} + +static int +aes_set_key(void *ctx_arg, const u8 *in_key, unsigned int key_len, u32 *flags) +{ + struct aes_ctx *ctx = ctx_arg; + u32 i, t, u, v, w; + + if (key_len != 16 && key_len != 24 && key_len != 32) { + *flags |= CRYPTO_TFM_RES_BAD_KEY_LEN; + return -EINVAL; + } + + ctx->key_length = key_len; + + E_KEY[0] = u32_in (in_key); + E_KEY[1] = u32_in (in_key + 4); + E_KEY[2] = u32_in (in_key + 8); + E_KEY[3] = u32_in (in_key + 12); + + switch (key_len) { + case 16: + t = E_KEY[3]; + for (i = 0; i < 10; ++i) + loop4 (i); + break; + + case 24: + E_KEY[4] = u32_in (in_key + 16); + t = E_KEY[5] = u32_in (in_key + 20); + for (i = 0; i < 8; ++i) + loop6 (i); + break; + + case 32: + E_KEY[4] = u32_in (in_key + 16); + E_KEY[5] = u32_in (in_key + 20); + E_KEY[6] = u32_in (in_key + 24); + t = E_KEY[7] = u32_in (in_key + 28); + for (i = 0; i < 7; ++i) + loop8 (i); + break; + } + + D_KEY[0] = E_KEY[0]; + D_KEY[1] = E_KEY[1]; + D_KEY[2] = E_KEY[2]; + D_KEY[3] = E_KEY[3]; + + for (i = 4; i < key_len + 24; ++i) { + imix_col (D_KEY[i], E_KEY[i]); + } + + return 0; +} + +/* encrypt a block of text */ + +#define f_nround(bo, bi, k) \ + f_rn(bo, bi, 0, k); \ + f_rn(bo, bi, 1, k); \ + f_rn(bo, bi, 2, k); \ + f_rn(bo, bi, 3, k); \ + k += 4 + +#define f_lround(bo, bi, k) \ + f_rl(bo, bi, 0, k); \ + f_rl(bo, bi, 1, k); \ + f_rl(bo, bi, 2, k); \ + f_rl(bo, bi, 3, k) + +static void aes_encrypt(void *ctx_arg, u8 *out, const u8 *in) +{ + const struct aes_ctx *ctx = ctx_arg; + u32 b0[4], b1[4]; + const u32 *kp = E_KEY + 4; + + b0[0] = u32_in (in) ^ E_KEY[0]; + b0[1] = u32_in (in + 4) ^ E_KEY[1]; + b0[2] = u32_in (in + 8) ^ E_KEY[2]; + b0[3] = u32_in (in + 12) ^ E_KEY[3]; + + if (ctx->key_length > 24) { + f_nround (b1, b0, kp); + f_nround (b0, b1, kp); + } + + if (ctx->key_length > 16) { + f_nround (b1, b0, kp); + f_nround (b0, b1, kp); + } + + f_nround (b1, b0, kp); + f_nround (b0, b1, kp); + f_nround (b1, b0, kp); + f_nround (b0, b1, kp); + f_nround (b1, b0, kp); + f_nround (b0, b1, kp); + f_nround (b1, b0, kp); + f_nround (b0, b1, kp); + f_nround (b1, b0, kp); + f_lround (b0, b1, kp); + + u32_out (out, b0[0]); + u32_out (out + 4, b0[1]); + u32_out (out + 8, b0[2]); + u32_out (out + 12, b0[3]); +} + +/* decrypt a block of text */ + +#define i_nround(bo, bi, k) \ + i_rn(bo, bi, 0, k); \ + i_rn(bo, bi, 1, k); \ + i_rn(bo, bi, 2, k); \ + i_rn(bo, bi, 3, k); \ + k -= 4 + +#define i_lround(bo, bi, k) \ + i_rl(bo, bi, 0, k); \ + i_rl(bo, bi, 1, k); \ + i_rl(bo, bi, 2, k); \ + i_rl(bo, bi, 3, k) + +static void aes_decrypt(void *ctx_arg, u8 *out, const u8 *in) +{ + const struct aes_ctx *ctx = ctx_arg; + u32 b0[4], b1[4]; + const int key_len = ctx->key_length; + const u32 *kp = D_KEY + key_len + 20; + + b0[0] = u32_in (in) ^ E_KEY[key_len + 24]; + b0[1] = u32_in (in + 4) ^ E_KEY[key_len + 25]; + b0[2] = u32_in (in + 8) ^ E_KEY[key_len + 26]; + b0[3] = u32_in (in + 12) ^ E_KEY[key_len + 27]; + + if (key_len > 24) { + i_nround (b1, b0, kp); + i_nround (b0, b1, kp); + } + + if (key_len > 16) { + i_nround (b1, b0, kp); + i_nround (b0, b1, kp); + } + + i_nround (b1, b0, kp); + i_nround (b0, b1, kp); + i_nround (b1, b0, kp); + i_nround (b0, b1, kp); + i_nround (b1, b0, kp); + i_nround (b0, b1, kp); + i_nround (b1, b0, kp); + i_nround (b0, b1, kp); + i_nround (b1, b0, kp); + i_lround (b0, b1, kp); + + u32_out (out, b0[0]); + u32_out (out + 4, b0[1]); + u32_out (out + 8, b0[2]); + u32_out (out + 12, b0[3]); +} + + +static struct crypto_alg aes_alg = { + .cra_name = "aes", + .cra_flags = CRYPTO_ALG_TYPE_CIPHER, + .cra_blocksize = AES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct aes_ctx), + .cra_module = THIS_MODULE, + .cra_list = LIST_HEAD_INIT(aes_alg.cra_list), + .cra_u = { + .cipher = { + .cia_min_keysize = AES_MIN_KEY_SIZE, + .cia_max_keysize = AES_MAX_KEY_SIZE, + .cia_setkey = aes_set_key, + .cia_encrypt = aes_encrypt, + .cia_decrypt = aes_decrypt + } + } +}; + +static int __init aes_init(void) +{ + gen_tabs(); + return crypto_register_alg(&aes_alg); +} + +static void __exit aes_fini(void) +{ + crypto_unregister_alg(&aes_alg); +} + +module_init(aes_init); +module_exit(aes_fini); + +MODULE_DESCRIPTION("Rijndael (AES) Cipher Algorithm"); +MODULE_LICENSE("Dual BSD/GPL"); + diff --git a/drivers/staging/rtl8192su/ieee80211/api.c b/drivers/staging/rtl8192su/ieee80211/api.c new file mode 100644 index 000000000000..c627d029528b --- /dev/null +++ b/drivers/staging/rtl8192su/ieee80211/api.c @@ -0,0 +1,246 @@ +/* + * Scatterlist Cryptographic API. + * + * Copyright (c) 2002 James Morris <jmorris@intercode.com.au> + * Copyright (c) 2002 David S. Miller (davem@redhat.com) + * + * Portions derived from Cryptoapi, by Alexander Kjeldaas <astor@fast.no> + * and Nettle, by Niels Mé°ˆler. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + */ +#include "kmap_types.h" + +#include <linux/init.h> +#include <linux/module.h> +//#include <linux/crypto.h> +#include "rtl_crypto.h" +#include <linux/errno.h> +#include <linux/rwsem.h> +#include <linux/slab.h> +#include "internal.h" + +LIST_HEAD(crypto_alg_list); +DECLARE_RWSEM(crypto_alg_sem); + +static inline int crypto_alg_get(struct crypto_alg *alg) +{ + return try_inc_mod_count(alg->cra_module); +} + +static inline void crypto_alg_put(struct crypto_alg *alg) +{ + if (alg->cra_module) + __MOD_DEC_USE_COUNT(alg->cra_module); +} + +struct crypto_alg *crypto_alg_lookup(const char *name) +{ + struct crypto_alg *q, *alg = NULL; + + if (!name) + return NULL; + + down_read(&crypto_alg_sem); + + list_for_each_entry(q, &crypto_alg_list, cra_list) { + if (!(strcmp(q->cra_name, name))) { + if (crypto_alg_get(q)) + alg = q; + break; + } + } + + up_read(&crypto_alg_sem); + return alg; +} + +static int crypto_init_flags(struct crypto_tfm *tfm, u32 flags) +{ + tfm->crt_flags = 0; + + switch (crypto_tfm_alg_type(tfm)) { + case CRYPTO_ALG_TYPE_CIPHER: + return crypto_init_cipher_flags(tfm, flags); + + case CRYPTO_ALG_TYPE_DIGEST: + return crypto_init_digest_flags(tfm, flags); + + case CRYPTO_ALG_TYPE_COMPRESS: + return crypto_init_compress_flags(tfm, flags); + + default: + break; + } + + BUG(); + return -EINVAL; +} + +static int crypto_init_ops(struct crypto_tfm *tfm) +{ + switch (crypto_tfm_alg_type(tfm)) { + case CRYPTO_ALG_TYPE_CIPHER: + return crypto_init_cipher_ops(tfm); + + case CRYPTO_ALG_TYPE_DIGEST: + return crypto_init_digest_ops(tfm); + + case CRYPTO_ALG_TYPE_COMPRESS: + return crypto_init_compress_ops(tfm); + + default: + break; + } + + BUG(); + return -EINVAL; +} + +static void crypto_exit_ops(struct crypto_tfm *tfm) +{ + switch (crypto_tfm_alg_type(tfm)) { + case CRYPTO_ALG_TYPE_CIPHER: + crypto_exit_cipher_ops(tfm); + break; + + case CRYPTO_ALG_TYPE_DIGEST: + crypto_exit_digest_ops(tfm); + break; + + case CRYPTO_ALG_TYPE_COMPRESS: + crypto_exit_compress_ops(tfm); + break; + + default: + BUG(); + + } +} + +struct crypto_tfm *crypto_alloc_tfm(const char *name, u32 flags) +{ + struct crypto_tfm *tfm = NULL; + struct crypto_alg *alg; + + alg = crypto_alg_mod_lookup(name); + if (alg == NULL) + goto out; + + tfm = kmalloc(sizeof(*tfm) + alg->cra_ctxsize, GFP_KERNEL); + if (tfm == NULL) + goto out_put; + + memset(tfm, 0, sizeof(*tfm) + alg->cra_ctxsize); + + tfm->__crt_alg = alg; + + if (crypto_init_flags(tfm, flags)) + goto out_free_tfm; + + if (crypto_init_ops(tfm)) { + crypto_exit_ops(tfm); + goto out_free_tfm; + } + + goto out; + +out_free_tfm: + kfree(tfm); + tfm = NULL; +out_put: + crypto_alg_put(alg); +out: + return tfm; +} + +void crypto_free_tfm(struct crypto_tfm *tfm) +{ + struct crypto_alg *alg = tfm->__crt_alg; + int size = sizeof(*tfm) + alg->cra_ctxsize; + + crypto_exit_ops(tfm); + crypto_alg_put(alg); + memset(tfm, 0, size); + kfree(tfm); +} + +int crypto_register_alg(struct crypto_alg *alg) +{ + int ret = 0; + struct crypto_alg *q; + + down_write(&crypto_alg_sem); + + list_for_each_entry(q, &crypto_alg_list, cra_list) { + if (!(strcmp(q->cra_name, alg->cra_name))) { + ret = -EEXIST; + goto out; + } + } + + list_add_tail(&alg->cra_list, &crypto_alg_list); +out: + up_write(&crypto_alg_sem); + return ret; +} + +int crypto_unregister_alg(struct crypto_alg *alg) +{ + int ret = -ENOENT; + struct crypto_alg *q; + + BUG_ON(!alg->cra_module); + + down_write(&crypto_alg_sem); + list_for_each_entry(q, &crypto_alg_list, cra_list) { + if (alg == q) { + list_del(&alg->cra_list); + ret = 0; + goto out; + } + } +out: + up_write(&crypto_alg_sem); + return ret; +} + +int crypto_alg_available(const char *name, u32 flags) +{ + int ret = 0; + struct crypto_alg *alg = crypto_alg_mod_lookup(name); + + if (alg) { + crypto_alg_put(alg); + ret = 1; + } + + return ret; +} + +static int __init init_crypto(void) +{ + printk(KERN_INFO "Initializing Cryptographic API\n"); + crypto_init_proc(); + return 0; +} + +__initcall(init_crypto); + +/* +EXPORT_SYMBOL_GPL(crypto_register_alg); +EXPORT_SYMBOL_GPL(crypto_unregister_alg); +EXPORT_SYMBOL_GPL(crypto_alloc_tfm); +EXPORT_SYMBOL_GPL(crypto_free_tfm); +EXPORT_SYMBOL_GPL(crypto_alg_available); +*/ + +EXPORT_SYMBOL_NOVERS(crypto_register_alg); +EXPORT_SYMBOL_NOVERS(crypto_unregister_alg); +EXPORT_SYMBOL_NOVERS(crypto_alloc_tfm); +EXPORT_SYMBOL_NOVERS(crypto_free_tfm); +EXPORT_SYMBOL_NOVERS(crypto_alg_available); diff --git a/drivers/staging/rtl8192su/ieee80211/arc4.c b/drivers/staging/rtl8192su/ieee80211/arc4.c new file mode 100644 index 000000000000..e408472af305 --- /dev/null +++ b/drivers/staging/rtl8192su/ieee80211/arc4.c @@ -0,0 +1,103 @@ +/* + * Cryptographic API + * + * ARC4 Cipher Algorithm + * + * Jon Oberheide <jon@oberheide.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ +#include <linux/module.h> +#include <linux/init.h> +#include "rtl_crypto.h" + +#define ARC4_MIN_KEY_SIZE 1 +#define ARC4_MAX_KEY_SIZE 256 +#define ARC4_BLOCK_SIZE 1 + +struct arc4_ctx { + u8 S[256]; + u8 x, y; +}; + +static int arc4_set_key(void *ctx_arg, const u8 *in_key, unsigned int key_len, u32 *flags) +{ + struct arc4_ctx *ctx = ctx_arg; + int i, j = 0, k = 0; + + ctx->x = 1; + ctx->y = 0; + + for(i = 0; i < 256; i++) + ctx->S[i] = i; + + for(i = 0; i < 256; i++) + { + u8 a = ctx->S[i]; + j = (j + in_key[k] + a) & 0xff; + ctx->S[i] = ctx->S[j]; + ctx->S[j] = a; + if((unsigned int)++k >= key_len) + k = 0; + } + + return 0; +} + +static void arc4_crypt(void *ctx_arg, u8 *out, const u8 *in) +{ + struct arc4_ctx *ctx = ctx_arg; + + u8 *const S = ctx->S; + u8 x = ctx->x; + u8 y = ctx->y; + u8 a, b; + + a = S[x]; + y = (y + a) & 0xff; + b = S[y]; + S[x] = b; + S[y] = a; + x = (x + 1) & 0xff; + *out++ = *in ^ S[(a + b) & 0xff]; + + ctx->x = x; + ctx->y = y; +} + +static struct crypto_alg arc4_alg = { + .cra_name = "arc4", + .cra_flags = CRYPTO_ALG_TYPE_CIPHER, + .cra_blocksize = ARC4_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct arc4_ctx), + .cra_module = THIS_MODULE, + .cra_list = LIST_HEAD_INIT(arc4_alg.cra_list), + .cra_u = { .cipher = { + .cia_min_keysize = ARC4_MIN_KEY_SIZE, + .cia_max_keysize = ARC4_MAX_KEY_SIZE, + .cia_setkey = arc4_set_key, + .cia_encrypt = arc4_crypt, + .cia_decrypt = arc4_crypt } } +}; + +static int __init arc4_init(void) +{ + return crypto_register_alg(&arc4_alg); +} + + +static void __exit arc4_exit(void) +{ + crypto_unregister_alg(&arc4_alg); +} + +module_init(arc4_init); +module_exit(arc4_exit); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("ARC4 Cipher Algorithm"); +MODULE_AUTHOR("Jon Oberheide <jon@oberheide.org>"); diff --git a/drivers/staging/rtl8192su/ieee80211/autoload.c b/drivers/staging/rtl8192su/ieee80211/autoload.c new file mode 100644 index 000000000000..c97756f3b2ea --- /dev/null +++ b/drivers/staging/rtl8192su/ieee80211/autoload.c @@ -0,0 +1,40 @@ +/* + * Cryptographic API. + * + * Algorithm autoloader. + * + * Copyright (c) 2002 James Morris <jmorris@intercode.com.au> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + */ +#include "kmap_types.h" + +#include <linux/kernel.h> +//#include <linux/crypto.h> +#include "rtl_crypto.h" +#include <linux/string.h> +#include <linux/kmod.h> +#include "internal.h" + +/* + * A far more intelligent version of this is planned. For now, just + * try an exact match on the name of the algorithm. + */ +void crypto_alg_autoload(const char *name) +{ + request_module(name); +} + +struct crypto_alg *crypto_alg_mod_lookup(const char *name) +{ + struct crypto_alg *alg = crypto_alg_lookup(name); + if (alg == NULL) { + crypto_alg_autoload(name); + alg = crypto_alg_lookup(name); + } + return alg; +} diff --git a/drivers/staging/rtl8192su/ieee80211/cipher.c b/drivers/staging/rtl8192su/ieee80211/cipher.c new file mode 100644 index 000000000000..1968acfe32b1 --- /dev/null +++ b/drivers/staging/rtl8192su/ieee80211/cipher.c @@ -0,0 +1,299 @@ +/* + * Cryptographic API. + * + * Cipher operations. + * + * Copyright (c) 2002 James Morris <jmorris@intercode.com.au> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + */ +#include <linux/kernel.h> +//#include <linux/crypto.h> +#include "rtl_crypto.h" +#include <linux/errno.h> +#include <linux/mm.h> +#include <linux/slab.h> +#include <asm/scatterlist.h> +#include "internal.h" +#include "scatterwalk.h" + +typedef void (cryptfn_t)(void *, u8 *, const u8 *); +typedef void (procfn_t)(struct crypto_tfm *, u8 *, + u8*, cryptfn_t, int enc, void *, int); + +static inline void xor_64(u8 *a, const u8 *b) +{ + ((u32 *)a)[0] ^= ((u32 *)b)[0]; + ((u32 *)a)[1] ^= ((u32 *)b)[1]; +} + +static inline void xor_128(u8 *a, const u8 *b) +{ + ((u32 *)a)[0] ^= ((u32 *)b)[0]; + ((u32 *)a)[1] ^= ((u32 *)b)[1]; + ((u32 *)a)[2] ^= ((u32 *)b)[2]; + ((u32 *)a)[3] ^= ((u32 *)b)[3]; +} + + +/* + * Generic encrypt/decrypt wrapper for ciphers, handles operations across + * multiple page boundaries by using temporary blocks. In user context, + * the kernel is given a chance to schedule us once per block. + */ +static int crypt(struct crypto_tfm *tfm, + struct scatterlist *dst, + struct scatterlist *src, + unsigned int nbytes, cryptfn_t crfn, + procfn_t prfn, int enc, void *info) +{ + struct scatter_walk walk_in, walk_out; + const unsigned int bsize = crypto_tfm_alg_blocksize(tfm); + u8 tmp_src[bsize]; + u8 tmp_dst[bsize]; + + if (!nbytes) + return 0; + + if (nbytes % bsize) { + tfm->crt_flags |= CRYPTO_TFM_RES_BAD_BLOCK_LEN; + return -EINVAL; + } + + scatterwalk_start(&walk_in, src); + scatterwalk_start(&walk_out, dst); + + for(;;) { + u8 *src_p, *dst_p; + int in_place; + + scatterwalk_map(&walk_in, 0); + scatterwalk_map(&walk_out, 1); + src_p = scatterwalk_whichbuf(&walk_in, bsize, tmp_src); + dst_p = scatterwalk_whichbuf(&walk_out, bsize, tmp_dst); + in_place = scatterwalk_samebuf(&walk_in, &walk_out, + src_p, dst_p); + + nbytes -= bsize; + + scatterwalk_copychunks(src_p, &walk_in, bsize, 0); + + prfn(tfm, dst_p, src_p, crfn, enc, info, in_place); + + scatterwalk_done(&walk_in, 0, nbytes); + + scatterwalk_copychunks(dst_p, &walk_out, bsize, 1); + scatterwalk_done(&walk_out, 1, nbytes); + + if (!nbytes) + return 0; + + crypto_yield(tfm); + } +} + +static void cbc_process(struct crypto_tfm *tfm, u8 *dst, u8 *src, + cryptfn_t fn, int enc, void *info, int in_place) +{ + u8 *iv = info; + + /* Null encryption */ + if (!iv) + return; + + if (enc) { + tfm->crt_u.cipher.cit_xor_block(iv, src); + fn(crypto_tfm_ctx(tfm), dst, iv); + memcpy(iv, dst, crypto_tfm_alg_blocksize(tfm)); + } else { + u8 stack[in_place ? crypto_tfm_alg_blocksize(tfm) : 0]; + u8 *buf = in_place ? stack : dst; + + fn(crypto_tfm_ctx(tfm), buf, src); + tfm->crt_u.cipher.cit_xor_block(buf, iv); + memcpy(iv, src, crypto_tfm_alg_blocksize(tfm)); + if (buf != dst) + memcpy(dst, buf, crypto_tfm_alg_blocksize(tfm)); + } +} + +static void ecb_process(struct crypto_tfm *tfm, u8 *dst, u8 *src, + cryptfn_t fn, int enc, void *info, int in_place) +{ + fn(crypto_tfm_ctx(tfm), dst, src); +} + +static int setkey(struct crypto_tfm *tfm, const u8 *key, unsigned int keylen) +{ + struct cipher_alg *cia = &tfm->__crt_alg->cra_cipher; + + if (keylen < cia->cia_min_keysize || keylen > cia->cia_max_keysize) { + tfm->crt_flags |= CRYPTO_TFM_RES_BAD_KEY_LEN; + return -EINVAL; + } else + return cia->cia_setkey(crypto_tfm_ctx(tfm), key, keylen, + &tfm->crt_flags); +} + +static int ecb_encrypt(struct crypto_tfm *tfm, + struct scatterlist *dst, + struct scatterlist *src, unsigned int nbytes) +{ + return crypt(tfm, dst, src, nbytes, + tfm->__crt_alg->cra_cipher.cia_encrypt, + ecb_process, 1, NULL); +} + +static int ecb_decrypt(struct crypto_tfm *tfm, + struct scatterlist *dst, + struct scatterlist *src, + unsigned int nbytes) +{ + return crypt(tfm, dst, src, nbytes, + tfm->__crt_alg->cra_cipher.cia_decrypt, + ecb_process, 1, NULL); +} + +static int cbc_encrypt(struct crypto_tfm *tfm, + struct scatterlist *dst, + struct scatterlist *src, + unsigned int nbytes) +{ + return crypt(tfm, dst, src, nbytes, + tfm->__crt_alg->cra_cipher.cia_encrypt, + cbc_process, 1, tfm->crt_cipher.cit_iv); +} + +static int cbc_encrypt_iv(struct crypto_tfm *tfm, + struct scatterlist *dst, + struct scatterlist *src, + unsigned int nbytes, u8 *iv) +{ + return crypt(tfm, dst, src, nbytes, + tfm->__crt_alg->cra_cipher.cia_encrypt, + cbc_process, 1, iv); +} + +static int cbc_decrypt(struct crypto_tfm *tfm, + struct scatterlist *dst, + struct scatterlist *src, + unsigned int nbytes) +{ + return crypt(tfm, dst, src, nbytes, + tfm->__crt_alg->cra_cipher.cia_decrypt, + cbc_process, 0, tfm->crt_cipher.cit_iv); +} + +static int cbc_decrypt_iv(struct crypto_tfm *tfm, + struct scatterlist *dst, + struct scatterlist *src, + unsigned int nbytes, u8 *iv) +{ + return crypt(tfm, dst, src, nbytes, + tfm->__crt_alg->cra_cipher.cia_decrypt, + cbc_process, 0, iv); +} + +static int nocrypt(struct crypto_tfm *tfm, + struct scatterlist *dst, + struct scatterlist *src, + unsigned int nbytes) +{ + return -ENOSYS; +} + +static int nocrypt_iv(struct crypto_tfm *tfm, + struct scatterlist *dst, + struct scatterlist *src, + unsigned int nbytes, u8 *iv) +{ + return -ENOSYS; +} + +int crypto_init_cipher_flags(struct crypto_tfm *tfm, u32 flags) +{ + u32 mode = flags & CRYPTO_TFM_MODE_MASK; + + tfm->crt_cipher.cit_mode = mode ? mode : CRYPTO_TFM_MODE_ECB; + if (flags & CRYPTO_TFM_REQ_WEAK_KEY) + tfm->crt_flags = CRYPTO_TFM_REQ_WEAK_KEY; + + return 0; +} + +int crypto_init_cipher_ops(struct crypto_tfm *tfm) +{ + int ret = 0; + struct cipher_tfm *ops = &tfm->crt_cipher; + + ops->cit_setkey = setkey; + + switch (tfm->crt_cipher.cit_mode) { + case CRYPTO_TFM_MODE_ECB: + ops->cit_encrypt = ecb_encrypt; + ops->cit_decrypt = ecb_decrypt; + break; + + case CRYPTO_TFM_MODE_CBC: + ops->cit_encrypt = cbc_encrypt; + ops->cit_decrypt = cbc_decrypt; + ops->cit_encrypt_iv = cbc_encrypt_iv; + ops->cit_decrypt_iv = cbc_decrypt_iv; + break; + + case CRYPTO_TFM_MODE_CFB: + ops->cit_encrypt = nocrypt; + ops->cit_decrypt = nocrypt; + ops->cit_encrypt_iv = nocrypt_iv; + ops->cit_decrypt_iv = nocrypt_iv; + break; + + case CRYPTO_TFM_MODE_CTR: + ops->cit_encrypt = nocrypt; + ops->cit_decrypt = nocrypt; + ops->cit_encrypt_iv = nocrypt_iv; + ops->cit_decrypt_iv = nocrypt_iv; + break; + + default: + BUG(); + } + + if (ops->cit_mode == CRYPTO_TFM_MODE_CBC) { + + switch (crypto_tfm_alg_blocksize(tfm)) { + case 8: + ops->cit_xor_block = xor_64; + break; + + case 16: + ops->cit_xor_block = xor_128; + break; + + default: + printk(KERN_WARNING "%s: block size %u not supported\n", + crypto_tfm_alg_name(tfm), + crypto_tfm_alg_blocksize(tfm)); + ret = -EINVAL; + goto out; + } + + ops->cit_ivsize = crypto_tfm_alg_blocksize(tfm); + ops->cit_iv = kmalloc(ops->cit_ivsize, GFP_KERNEL); + if (ops->cit_iv == NULL) + ret = -ENOMEM; + } + +out: + return ret; +} + +void crypto_exit_cipher_ops(struct crypto_tfm *tfm) +{ + if (tfm->crt_cipher.cit_iv) + kfree(tfm->crt_cipher.cit_iv); +} diff --git a/drivers/staging/rtl8192su/ieee80211/compress.c b/drivers/staging/rtl8192su/ieee80211/compress.c new file mode 100644 index 000000000000..c2df80e2ed9d --- /dev/null +++ b/drivers/staging/rtl8192su/ieee80211/compress.c @@ -0,0 +1,64 @@ +/* + * Cryptographic API. + * + * Compression operations. + * + * Copyright (c) 2002 James Morris <jmorris@intercode.com.au> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + */ +#include <linux/types.h> +//#include <linux/crypto.h> +#include "rtl_crypto.h" +#include <linux/errno.h> +#include <asm/scatterlist.h> +#include <linux/string.h> +#include "internal.h" + +static int crypto_compress(struct crypto_tfm *tfm, + const u8 *src, unsigned int slen, + u8 *dst, unsigned int *dlen) +{ + return tfm->__crt_alg->cra_compress.coa_compress(crypto_tfm_ctx(tfm), + src, slen, dst, + dlen); +} + +static int crypto_decompress(struct crypto_tfm *tfm, + const u8 *src, unsigned int slen, + u8 *dst, unsigned int *dlen) +{ + return tfm->__crt_alg->cra_compress.coa_decompress(crypto_tfm_ctx(tfm), + src, slen, dst, + dlen); +} + +int crypto_init_compress_flags(struct crypto_tfm *tfm, u32 flags) +{ + return flags ? -EINVAL : 0; +} + +int crypto_init_compress_ops(struct crypto_tfm *tfm) +{ + int ret = 0; + struct compress_tfm *ops = &tfm->crt_compress; + + ret = tfm->__crt_alg->cra_compress.coa_init(crypto_tfm_ctx(tfm)); + if (ret) + goto out; + + ops->cot_compress = crypto_compress; + ops->cot_decompress = crypto_decompress; + +out: + return ret; +} + +void crypto_exit_compress_ops(struct crypto_tfm *tfm) +{ + tfm->__crt_alg->cra_compress.coa_exit(crypto_tfm_ctx(tfm)); +} diff --git a/drivers/staging/rtl8192su/ieee80211/crypto_compat.h b/drivers/staging/rtl8192su/ieee80211/crypto_compat.h new file mode 100644 index 000000000000..587e8bb2db6a --- /dev/null +++ b/drivers/staging/rtl8192su/ieee80211/crypto_compat.h @@ -0,0 +1,90 @@ +/* + * Header file to maintain compatibility among different kernel versions. + * + * Copyright (c) 2004-2006 <lawrence_wang@realsil.com.cn> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. See README and COPYING for + * more details. + */ + +#include <linux/crypto.h> + +static inline int crypto_cipher_encrypt(struct crypto_tfm *tfm, + struct scatterlist *dst, + struct scatterlist *src, + unsigned int nbytes) +{ + BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_CIPHER); + return tfm->crt_cipher.cit_encrypt(tfm, dst, src, nbytes); +} + + +static inline int crypto_cipher_decrypt(struct crypto_tfm *tfm, + struct scatterlist *dst, + struct scatterlist *src, + unsigned int nbytes) +{ + BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_CIPHER); + return tfm->crt_cipher.cit_decrypt(tfm, dst, src, nbytes); +} + +#if 0 +/* + * crypto_free_tfm - Free crypto transform + * @tfm: Transform to free + * + * crypto_free_tfm() frees up the transform and any associated resources, + * then drops the refcount on the associated algorithm. + */ +void crypto_free_tfm(struct crypto_tfm *tfm) +{ + struct crypto_alg *alg; + int size; + + if (unlikely(!tfm)) + return; + + alg = tfm->__crt_alg; + size = sizeof(*tfm) + alg->cra_ctxsize; + + if (alg->cra_exit) + alg->cra_exit(tfm); + crypto_exit_ops(tfm); + crypto_mod_put(alg); + memset(tfm, 0, size); + kfree(tfm); +} + +#endif +#if 1 + struct crypto_tfm *crypto_alloc_tfm(const char *name, u32 flags) +{ + struct crypto_tfm *tfm = NULL; + int err; + printk("call crypto_alloc_tfm!!!\n"); + do { + struct crypto_alg *alg; + + alg = crypto_alg_mod_lookup(name, 0, CRYPTO_ALG_ASYNC); + err = PTR_ERR(alg); + if (IS_ERR(alg)) + continue; + + tfm = __crypto_alloc_tfm(alg, flags); + err = 0; + if (IS_ERR(tfm)) { + crypto_mod_put(alg); + err = PTR_ERR(tfm); + tfm = NULL; + } + } while (err == -EAGAIN && !signal_pending(current)); + + return tfm; +} +#endif +//EXPORT_SYMBOL_GPL(crypto_alloc_tfm); +//EXPORT_SYMBOL_GPL(crypto_free_tfm); + + diff --git a/drivers/staging/rtl8192su/ieee80211/digest.c b/drivers/staging/rtl8192su/ieee80211/digest.c new file mode 100644 index 000000000000..1a95f2d37837 --- /dev/null +++ b/drivers/staging/rtl8192su/ieee80211/digest.c @@ -0,0 +1,108 @@ +/* + * Cryptographic API. + * + * Digest operations. + * + * Copyright (c) 2002 James Morris <jmorris@intercode.com.au> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + */ +//#include <linux/crypto.h> +#include "rtl_crypto.h" +#include <linux/mm.h> +#include <linux/errno.h> +#include <linux/highmem.h> +#include <asm/scatterlist.h> +#include "internal.h" + +static void init(struct crypto_tfm *tfm) +{ + tfm->__crt_alg->cra_digest.dia_init(crypto_tfm_ctx(tfm)); +} + +static void update(struct crypto_tfm *tfm, + struct scatterlist *sg, unsigned int nsg) +{ + unsigned int i; + + for (i = 0; i < nsg; i++) { + + struct page *pg = sg[i].page; + unsigned int offset = sg[i].offset; + unsigned int l = sg[i].length; + + do { + unsigned int bytes_from_page = min(l, ((unsigned int) + (PAGE_SIZE)) - + offset); + char *p = crypto_kmap(pg, 0) + offset; + + tfm->__crt_alg->cra_digest.dia_update + (crypto_tfm_ctx(tfm), p, + bytes_from_page); + crypto_kunmap(p, 0); + crypto_yield(tfm); + offset = 0; + pg++; + l -= bytes_from_page; + } while (l > 0); + } +} + +static void final(struct crypto_tfm *tfm, u8 *out) +{ + tfm->__crt_alg->cra_digest.dia_final(crypto_tfm_ctx(tfm), out); +} + +static int setkey(struct crypto_tfm *tfm, const u8 *key, unsigned int keylen) +{ + u32 flags; + if (tfm->__crt_alg->cra_digest.dia_setkey == NULL) + return -ENOSYS; + return tfm->__crt_alg->cra_digest.dia_setkey(crypto_tfm_ctx(tfm), + key, keylen, &flags); +} + +static void digest(struct crypto_tfm *tfm, + struct scatterlist *sg, unsigned int nsg, u8 *out) +{ + unsigned int i; + + tfm->crt_digest.dit_init(tfm); + + for (i = 0; i < nsg; i++) { + char *p = crypto_kmap(sg[i].page, 0) + sg[i].offset; + tfm->__crt_alg->cra_digest.dia_update(crypto_tfm_ctx(tfm), + p, sg[i].length); + crypto_kunmap(p, 0); + crypto_yield(tfm); + } + crypto_digest_final(tfm, out); +} + +int crypto_init_digest_flags(struct crypto_tfm *tfm, u32 flags) +{ + return flags ? -EINVAL : 0; +} + +int crypto_init_digest_ops(struct crypto_tfm *tfm) +{ + struct digest_tfm *ops = &tfm->crt_digest; + + ops->dit_init = init; + ops->dit_update = update; + ops->dit_final = final; + ops->dit_digest = digest; + ops->dit_setkey = setkey; + + return crypto_alloc_hmac_block(tfm); +} + +void crypto_exit_digest_ops(struct crypto_tfm *tfm) +{ + crypto_free_hmac_block(tfm); +} diff --git a/drivers/staging/rtl8192su/ieee80211/dot11d.c b/drivers/staging/rtl8192su/ieee80211/dot11d.c new file mode 100644 index 000000000000..e5f2dedc4372 --- /dev/null +++ b/drivers/staging/rtl8192su/ieee80211/dot11d.c @@ -0,0 +1,239 @@ +#ifdef ENABLE_DOT11D +//----------------------------------------------------------------------------- +// File: +// Dot11d.c +// +// Description: +// Implement 802.11d. +// +//----------------------------------------------------------------------------- + +#include "dot11d.h" + +void +Dot11d_Init(struct ieee80211_device *ieee) +{ + PRT_DOT11D_INFO pDot11dInfo = GET_DOT11D_INFO(ieee); + + pDot11dInfo->bEnabled = 0; + + pDot11dInfo->State = DOT11D_STATE_NONE; + pDot11dInfo->CountryIeLen = 0; + memset(pDot11dInfo->channel_map, 0, MAX_CHANNEL_NUMBER+1); + memset(pDot11dInfo->MaxTxPwrDbmList, 0xFF, MAX_CHANNEL_NUMBER+1); + RESET_CIE_WATCHDOG(ieee); + + printk("Dot11d_Init()\n"); +} + +// +// Description: +// Reset to the state as we are just entering a regulatory domain. +// +void +Dot11d_Reset(struct ieee80211_device *ieee) +{ + u32 i; + PRT_DOT11D_INFO pDot11dInfo = GET_DOT11D_INFO(ieee); +#if 0 + if(!pDot11dInfo->bEnabled) + return; +#endif + // Clear old channel map + memset(pDot11dInfo->channel_map, 0, MAX_CHANNEL_NUMBER+1); + memset(pDot11dInfo->MaxTxPwrDbmList, 0xFF, MAX_CHANNEL_NUMBER+1); + // Set new channel map + for (i=1; i<=11; i++) { + (pDot11dInfo->channel_map)[i] = 1; + } + for (i=12; i<=14; i++) { + (pDot11dInfo->channel_map)[i] = 2; + } + + pDot11dInfo->State = DOT11D_STATE_NONE; + pDot11dInfo->CountryIeLen = 0; + RESET_CIE_WATCHDOG(ieee); + + //printk("Dot11d_Reset()\n"); +} + +// +// Description: +// Update country IE from Beacon or Probe Resopnse +// and configure PHY for operation in the regulatory domain. +// +// TODO: +// Configure Tx power. +// +// Assumption: +// 1. IS_DOT11D_ENABLE() is TRUE. +// 2. Input IE is an valid one. +// +void +Dot11d_UpdateCountryIe( + struct ieee80211_device *dev, + u8 * pTaddr, + u16 CoutryIeLen, + u8 * pCoutryIe + ) +{ + PRT_DOT11D_INFO pDot11dInfo = GET_DOT11D_INFO(dev); + u8 i, j, NumTriples, MaxChnlNum; + PCHNL_TXPOWER_TRIPLE pTriple; + + memset(pDot11dInfo->channel_map, 0, MAX_CHANNEL_NUMBER+1); + memset(pDot11dInfo->MaxTxPwrDbmList, 0xFF, MAX_CHANNEL_NUMBER+1); + MaxChnlNum = 0; + NumTriples = (CoutryIeLen - 3) / 3; // skip 3-byte country string. + pTriple = (PCHNL_TXPOWER_TRIPLE)(pCoutryIe + 3); + for(i = 0; i < NumTriples; i++) + { + if(MaxChnlNum >= pTriple->FirstChnl) + { // It is not in a monotonically increasing order, so stop processing. + printk("Dot11d_UpdateCountryIe(): Invalid country IE, skip it........1\n"); + return; + } + if(MAX_CHANNEL_NUMBER < (pTriple->FirstChnl + pTriple->NumChnls)) + { // It is not a valid set of channel id, so stop processing. + printk("Dot11d_UpdateCountryIe(): Invalid country IE, skip it........2\n"); + return; + } + + for(j = 0 ; j < pTriple->NumChnls; j++) + { + pDot11dInfo->channel_map[pTriple->FirstChnl + j] = 1; + pDot11dInfo->MaxTxPwrDbmList[pTriple->FirstChnl + j] = pTriple->MaxTxPowerInDbm; + MaxChnlNum = pTriple->FirstChnl + j; + } + + pTriple = (PCHNL_TXPOWER_TRIPLE)((u8*)pTriple + 3); + } +#if 1 + //printk("Dot11d_UpdateCountryIe(): Channel List:\n"); + printk("Channel List:"); + for(i=1; i<= MAX_CHANNEL_NUMBER; i++) + if(pDot11dInfo->channel_map[i] > 0) + printk(" %d", i); + printk("\n"); +#endif + + UPDATE_CIE_SRC(dev, pTaddr); + + pDot11dInfo->CountryIeLen = CoutryIeLen; + memcpy(pDot11dInfo->CountryIeBuf, pCoutryIe,CoutryIeLen); + pDot11dInfo->State = DOT11D_STATE_LEARNED; +} + + +u8 +DOT11D_GetMaxTxPwrInDbm( + struct ieee80211_device *dev, + u8 Channel + ) +{ + PRT_DOT11D_INFO pDot11dInfo = GET_DOT11D_INFO(dev); + u8 MaxTxPwrInDbm = 255; + + if(MAX_CHANNEL_NUMBER < Channel) + { + printk("DOT11D_GetMaxTxPwrInDbm(): Invalid Channel\n"); + return MaxTxPwrInDbm; + } + if(pDot11dInfo->channel_map[Channel]) + { + MaxTxPwrInDbm = pDot11dInfo->MaxTxPwrDbmList[Channel]; + } + + return MaxTxPwrInDbm; +} + + +void +DOT11D_ScanComplete( + struct ieee80211_device * dev + ) +{ + PRT_DOT11D_INFO pDot11dInfo = GET_DOT11D_INFO(dev); + + switch(pDot11dInfo->State) + { + case DOT11D_STATE_LEARNED: + pDot11dInfo->State = DOT11D_STATE_DONE; + break; + + case DOT11D_STATE_DONE: + if( GET_CIE_WATCHDOG(dev) == 0 ) + { // Reset country IE if previous one is gone. + Dot11d_Reset(dev); + } + break; + case DOT11D_STATE_NONE: + break; + } +} + +int IsLegalChannel( + struct ieee80211_device * dev, + u8 channel +) +{ + PRT_DOT11D_INFO pDot11dInfo = GET_DOT11D_INFO(dev); + + if(MAX_CHANNEL_NUMBER < channel) + { + printk("IsLegalChannel(): Invalid Channel\n"); + return 0; + } + if(pDot11dInfo->channel_map[channel] > 0) + return 1; + return 0; +} + +int ToLegalChannel( + struct ieee80211_device * dev, + u8 channel +) +{ + PRT_DOT11D_INFO pDot11dInfo = GET_DOT11D_INFO(dev); + u8 default_chn = 0; + u32 i = 0; + + for (i=1; i<= MAX_CHANNEL_NUMBER; i++) + { + if(pDot11dInfo->channel_map[i] > 0) + { + default_chn = i; + break; + } + } + + if(MAX_CHANNEL_NUMBER < channel) + { + printk("IsLegalChannel(): Invalid Channel\n"); + return default_chn; + } + + if(pDot11dInfo->channel_map[channel] > 0) + return channel; + + return default_chn; +} +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) +EXPORT_SYMBOL(Dot11d_Init); +EXPORT_SYMBOL(Dot11d_Reset); +EXPORT_SYMBOL(Dot11d_UpdateCountryIe); +EXPORT_SYMBOL(DOT11D_GetMaxTxPwrInDbm); +EXPORT_SYMBOL(DOT11D_ScanComplete); +EXPORT_SYMBOL(IsLegalChannel); +EXPORT_SYMBOL(ToLegalChannel); +#else +EXPORT_SYMBOL_NOVERS(Dot11d_Init); +EXPORT_SYMBOL_NOVERS(Dot11d_Reset); +EXPORT_SYMBOL_NOVERS(Dot11d_UpdateCountryIe); +EXPORT_SYMBOL_NOVERS(DOT11D_GetMaxTxPwrInDbm); +EXPORT_SYMBOL_NOVERS(DOT11D_ScanComplete); +EXPORT_SYMBOL_NOVERS(IsLegalChannel); +EXPORT_SYMBOL_NOVERS(ToLegalChannel); +#endif + +#endif diff --git a/drivers/staging/rtl8192su/ieee80211/dot11d.h b/drivers/staging/rtl8192su/ieee80211/dot11d.h new file mode 100644 index 000000000000..15b7a4ba37b6 --- /dev/null +++ b/drivers/staging/rtl8192su/ieee80211/dot11d.h @@ -0,0 +1,102 @@ +#ifndef __INC_DOT11D_H +#define __INC_DOT11D_H + +#ifdef ENABLE_DOT11D +#include "ieee80211.h" + +//#define ENABLE_DOT11D + +//#define DOT11D_MAX_CHNL_NUM 83 + +typedef struct _CHNL_TXPOWER_TRIPLE { + u8 FirstChnl; + u8 NumChnls; + u8 MaxTxPowerInDbm; +}CHNL_TXPOWER_TRIPLE, *PCHNL_TXPOWER_TRIPLE; + +typedef enum _DOT11D_STATE { + DOT11D_STATE_NONE = 0, + DOT11D_STATE_LEARNED, + DOT11D_STATE_DONE, +}DOT11D_STATE; + +typedef struct _RT_DOT11D_INFO { + //DECLARE_RT_OBJECT(RT_DOT11D_INFO); + + bool bEnabled; // dot11MultiDomainCapabilityEnabled + + u16 CountryIeLen; // > 0 if CountryIeBuf[] contains valid country information element. + u8 CountryIeBuf[MAX_IE_LEN]; + u8 CountryIeSrcAddr[6]; // Source AP of the country IE. + u8 CountryIeWatchdog; + + u8 channel_map[MAX_CHANNEL_NUMBER+1]; //!!!Value 0: Invalid, 1: Valid (active scan), 2: Valid (passive scan) + //u8 ChnlListLen; // #Bytes valid in ChnlList[]. + //u8 ChnlList[DOT11D_MAX_CHNL_NUM]; + u8 MaxTxPwrDbmList[MAX_CHANNEL_NUMBER+1]; + + DOT11D_STATE State; +}RT_DOT11D_INFO, *PRT_DOT11D_INFO; +#define eqMacAddr(a,b) ( ((a)[0]==(b)[0] && (a)[1]==(b)[1] && (a)[2]==(b)[2] && (a)[3]==(b)[3] && (a)[4]==(b)[4] && (a)[5]==(b)[5]) ? 1:0 ) +#define cpMacAddr(des,src) ((des)[0]=(src)[0],(des)[1]=(src)[1],(des)[2]=(src)[2],(des)[3]=(src)[3],(des)[4]=(src)[4],(des)[5]=(src)[5]) +#define GET_DOT11D_INFO(__pIeeeDev) ((PRT_DOT11D_INFO)((__pIeeeDev)->pDot11dInfo)) + +#define IS_DOT11D_ENABLE(__pIeeeDev) GET_DOT11D_INFO(__pIeeeDev)->bEnabled +#define IS_COUNTRY_IE_VALID(__pIeeeDev) (GET_DOT11D_INFO(__pIeeeDev)->CountryIeLen > 0) + +#define IS_EQUAL_CIE_SRC(__pIeeeDev, __pTa) eqMacAddr(GET_DOT11D_INFO(__pIeeeDev)->CountryIeSrcAddr, __pTa) +#define UPDATE_CIE_SRC(__pIeeeDev, __pTa) cpMacAddr(GET_DOT11D_INFO(__pIeeeDev)->CountryIeSrcAddr, __pTa) + +#define IS_COUNTRY_IE_CHANGED(__pIeeeDev, __Ie) \ + (((__Ie).Length == 0 || (__Ie).Length != GET_DOT11D_INFO(__pIeeeDev)->CountryIeLen) ? \ + FALSE : \ + (!memcmp(GET_DOT11D_INFO(__pIeeeDev)->CountryIeBuf, (__Ie).Octet, (__Ie).Length))) + +#define CIE_WATCHDOG_TH 1 +#define GET_CIE_WATCHDOG(__pIeeeDev) GET_DOT11D_INFO(__pIeeeDev)->CountryIeWatchdog +#define RESET_CIE_WATCHDOG(__pIeeeDev) GET_CIE_WATCHDOG(__pIeeeDev) = 0 +#define UPDATE_CIE_WATCHDOG(__pIeeeDev) ++GET_CIE_WATCHDOG(__pIeeeDev) + +#define IS_DOT11D_STATE_DONE(__pIeeeDev) (GET_DOT11D_INFO(__pIeeeDev)->State == DOT11D_STATE_DONE) + + +void +Dot11d_Init( + struct ieee80211_device *dev + ); + +void +Dot11d_Reset( + struct ieee80211_device *dev + ); + +void +Dot11d_UpdateCountryIe( + struct ieee80211_device *dev, + u8 * pTaddr, + u16 CoutryIeLen, + u8 * pCoutryIe + ); + +u8 +DOT11D_GetMaxTxPwrInDbm( + struct ieee80211_device *dev, + u8 Channel + ); + +void +DOT11D_ScanComplete( + struct ieee80211_device * dev + ); + +int IsLegalChannel( + struct ieee80211_device * dev, + u8 channel +); + +int ToLegalChannel( + struct ieee80211_device * dev, + u8 channel +); +#endif //ENABLE_DOT11D +#endif // #ifndef __INC_DOT11D_H diff --git a/drivers/staging/rtl8192su/ieee80211/ieee80211.h b/drivers/staging/rtl8192su/ieee80211/ieee80211.h new file mode 100644 index 000000000000..720bfcbfadc1 --- /dev/null +++ b/drivers/staging/rtl8192su/ieee80211/ieee80211.h @@ -0,0 +1,2901 @@ +/* + * Merged with mainline ieee80211.h in Aug 2004. Original ieee802_11 + * remains copyright by the original authors + * + * Portions of the merged code are based on Host AP (software wireless + * LAN access point) driver for Intersil Prism2/2.5/3. + * + * Copyright (c) 2001-2002, SSH Communications Security Corp and Jouni Malinen + * <jkmaline@cc.hut.fi> + * Copyright (c) 2002-2003, Jouni Malinen <jkmaline@cc.hut.fi> + * + * Adaption to a generic IEEE 802.11 stack by James Ketrenos + * <jketreno@linux.intel.com> + * Copyright (c) 2004, Intel Corporation + * + * Modified for Realtek's wi-fi cards by Andrea Merello + * <andreamrl@tiscali.it> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. See README and COPYING for + * more details. + */ +#ifndef IEEE80211_H +#define IEEE80211_H +#include <linux/if_ether.h> /* ETH_ALEN */ +#include <linux/kernel.h> /* ARRAY_SIZE */ +#include <linux/version.h> +#include <linux/module.h> +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) +#include <linux/jiffies.h> +#else +#include <linux/jffs.h> +#include <linux/tqueue.h> +#endif +#include <linux/timer.h> +#include <linux/sched.h> + +#include <linux/delay.h> +#include <linux/wireless.h> + +#include "rtl819x_HT.h" +#include "rtl819x_BA.h" +#include "rtl819x_TS.h" + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)) +#ifndef bool +typedef enum{false = 0, true} bool; +#endif +#endif + +#ifndef IW_MODE_MONITOR +#define IW_MODE_MONITOR 6 +#endif + +#ifndef IWEVCUSTOM +#define IWEVCUSTOM 0x8c02 +#endif + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)) +#ifndef __bitwise +#define __bitwise __attribute__((bitwise)) +#endif +typedef __u16 __le16; +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,27)) +struct iw_spy_data{ + /* --- Standard spy support --- */ + int spy_number; + u_char spy_address[IW_MAX_SPY][ETH_ALEN]; + struct iw_quality spy_stat[IW_MAX_SPY]; + /* --- Enhanced spy support (event) */ + struct iw_quality spy_thr_low; /* Low threshold */ + struct iw_quality spy_thr_high; /* High threshold */ + u_char spy_thr_under[IW_MAX_SPY]; +}; +#endif +#endif + +#ifndef container_of +/** + * container_of - cast a member of a structure out to the containing structure + * + * @ptr: the pointer to the member. + * @type: the type of the container struct this is embedded in. + * @member: the name of the member within the struct. + * + */ +#define container_of(ptr, type, member) ({ \ + const typeof( ((type *)0)->member ) *__mptr = (ptr); \ + (type *)( (char *)__mptr - offsetof(type,member) );}) +#endif + +#define KEY_TYPE_NA 0x0 +#define KEY_TYPE_WEP40 0x1 +#define KEY_TYPE_TKIP 0x2 +#define KEY_TYPE_CCMP 0x4 +#define KEY_TYPE_WEP104 0x5 + +/* added for rtl819x tx procedure */ +#define MAX_QUEUE_SIZE 0x10 + +// +// 8190 queue mapping +// +#define BK_QUEUE 0 +#define BE_QUEUE 1 +#define VI_QUEUE 2 +#define VO_QUEUE 3 +#define HCCA_QUEUE 4 +#define TXCMD_QUEUE 5 +#define MGNT_QUEUE 6 +#define HIGH_QUEUE 7 +#define BEACON_QUEUE 8 + +#define LOW_QUEUE BE_QUEUE +#define NORMAL_QUEUE MGNT_QUEUE + +//added by amy for ps +#define SWRF_TIMEOUT 50 + +//added by amy for LEAP related +#define IE_CISCO_FLAG_POSITION 0x08 // Flag byte: byte 8, numbered from 0. +#define SUPPORT_CKIP_MIC 0x08 // bit3 +#define SUPPORT_CKIP_PK 0x10 // bit4 +//added by amy for ps +// RF Off Level for IPS or HW/SW radio off +#define RT_RF_OFF_LEVL_ASPM BIT0 // PCI ASPM +#define RT_RF_OFF_LEVL_CLK_REQ BIT1 // PCI clock request +#define RT_RF_OFF_LEVL_PCI_D3 BIT2 // PCI D3 mode +#define RT_RF_OFF_LEVL_HALT_NIC BIT3 // NIC halt, re-initialize hw parameters +#define RT_RF_OFF_LEVL_FREE_FW BIT4 // FW free, re-download the FW +#define RT_RF_OFF_LEVL_FW_32K BIT5 // FW in 32k +#define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT6 // Always enable ASPM and Clock Req in initialization. +#define RT_RF_LPS_DISALBE_2R BIT30 // When LPS is on, disable 2R if no packet is received or transmittd. +#define RT_RF_LPS_LEVEL_ASPM BIT31 // LPS with ASPM +#define RT_IN_PS_LEVEL(pPSC, _PS_FLAG) ((pPSC->CurPsLevel & _PS_FLAG) ? true : false) +#define RT_CLEAR_PS_LEVEL(pPSC, _PS_FLAG) (pPSC->CurPsLevel &= (~(_PS_FLAG))) +#define RT_SET_PS_LEVEL(pPSC, _PS_FLAG) (pPSC->CurPsLevel->CurPsLevel |= _PS_FLAG) +/* defined for skb cb field */ +/* At most 28 byte */ +typedef struct cb_desc { + /* Tx Desc Related flags (8-9) */ + u8 bLastIniPkt:1; + u8 bCmdOrInit:1; + u8 bFirstSeg:1; + u8 bLastSeg:1; + u8 bEncrypt:1; + u8 bTxDisableRateFallBack:1; + u8 bTxUseDriverAssingedRate:1; + u8 bHwSec:1; //indicate whether use Hw security. WB + + u8 reserved1; + + /* Tx Firmware Relaged flags (10-11)*/ + u8 bCTSEnable:1; + u8 bRTSEnable:1; + u8 bUseShortGI:1; + u8 bUseShortPreamble:1; + u8 bTxEnableFwCalcDur:1; + u8 bAMPDUEnable:1; + u8 bRTSSTBC:1; + u8 RTSSC:1; + + u8 bRTSBW:1; + u8 bPacketBW:1; + u8 bRTSUseShortPreamble:1; + u8 bRTSUseShortGI:1; + u8 bMulticast:1; + u8 bBroadcast:1; + //u8 reserved2:2; + u8 drv_agg_enable:1; + u8 reserved2:1; + + /* Tx Desc related element(12-19) */ + u8 rata_index; + u8 queue_index; + //u8 reserved3; + //u8 reserved4; + u16 txbuf_size; + //u8 reserved5; + u8 RATRIndex; + u8 reserved6; + u8 reserved7; + u8 reserved8; + + /* Tx firmware related element(20-27) */ + u8 data_rate; + u8 rts_rate; + u8 ampdu_factor; + u8 ampdu_density; + //u8 reserved9; + //u8 reserved10; + //u8 reserved11; + u8 DrvAggrNum; + u16 pkt_size; + u8 reserved12; +}cb_desc, *pcb_desc; + +/*--------------------------Define -------------------------------------------*/ +#define MGN_1M 0x02 +#define MGN_2M 0x04 +#define MGN_5_5M 0x0b +#define MGN_11M 0x16 + +#define MGN_6M 0x0c +#define MGN_9M 0x12 +#define MGN_12M 0x18 +#define MGN_18M 0x24 +#define MGN_24M 0x30 +#define MGN_36M 0x48 +#define MGN_48M 0x60 +#define MGN_54M 0x6c + +#define MGN_MCS0 0x80 +#define MGN_MCS1 0x81 +#define MGN_MCS2 0x82 +#define MGN_MCS3 0x83 +#define MGN_MCS4 0x84 +#define MGN_MCS5 0x85 +#define MGN_MCS6 0x86 +#define MGN_MCS7 0x87 +#define MGN_MCS8 0x88 +#define MGN_MCS9 0x89 +#define MGN_MCS10 0x8a +#define MGN_MCS11 0x8b +#define MGN_MCS12 0x8c +#define MGN_MCS13 0x8d +#define MGN_MCS14 0x8e +#define MGN_MCS15 0x8f +#define MGN_MCS0_SG 0x90 +#define MGN_MCS1_SG 0x91 +#define MGN_MCS2_SG 0x92 +#define MGN_MCS3_SG 0x93 +#define MGN_MCS4_SG 0x94 +#define MGN_MCS5_SG 0x95 +#define MGN_MCS6_SG 0x96 +#define MGN_MCS7_SG 0x97 +#define MGN_MCS8_SG 0x98 +#define MGN_MCS9_SG 0x99 +#define MGN_MCS10_SG 0x9a +#define MGN_MCS11_SG 0x9b +#define MGN_MCS12_SG 0x9c +#define MGN_MCS13_SG 0x9d +#define MGN_MCS14_SG 0x9e +#define MGN_MCS15_SG 0x9f + + +//---------------------------------------------------------------------------- +// 802.11 Management frame Reason Code field +//---------------------------------------------------------------------------- +enum _ReasonCode{ + unspec_reason = 0x1, + auth_not_valid = 0x2, + deauth_lv_ss = 0x3, + inactivity = 0x4, + ap_overload = 0x5, + class2_err = 0x6, + class3_err = 0x7, + disas_lv_ss = 0x8, + asoc_not_auth = 0x9, + + //----MIC_CHECK + mic_failure = 0xe, + //----END MIC_CHECK + + // Reason code defined in 802.11i D10.0 p.28. + invalid_IE = 0x0d, + four_way_tmout = 0x0f, + two_way_tmout = 0x10, + IE_dismatch = 0x11, + invalid_Gcipher = 0x12, + invalid_Pcipher = 0x13, + invalid_AKMP = 0x14, + unsup_RSNIEver = 0x15, + invalid_RSNIE = 0x16, + auth_802_1x_fail= 0x17, + ciper_reject = 0x18, + + // Reason code defined in 7.3.1.7, 802.1e D13.0, p.42. Added by Annie, 2005-11-15. + QoS_unspec = 0x20, // 32 + QAP_bandwidth = 0x21, // 33 + poor_condition = 0x22, // 34 + no_facility = 0x23, // 35 + // Where is 36??? + req_declined = 0x25, // 37 + invalid_param = 0x26, // 38 + req_not_honored= 0x27, // 39 + TS_not_created = 0x2F, // 47 + DL_not_allowed = 0x30, // 48 + dest_not_exist = 0x31, // 49 + dest_not_QSTA = 0x32, // 50 +}; + + + +#define aSifsTime (((priv->ieee80211->current_network.mode == IEEE_A)||(priv->ieee80211->current_network.mode == IEEE_N_24G)||(priv->ieee80211->current_network.mode == IEEE_N_5G))? 16 : 10) + +#define MGMT_QUEUE_NUM 5 + +#define IEEE_CMD_SET_WPA_PARAM 1 +#define IEEE_CMD_SET_WPA_IE 2 +#define IEEE_CMD_SET_ENCRYPTION 3 +#define IEEE_CMD_MLME 4 + +#define IEEE_PARAM_WPA_ENABLED 1 +#define IEEE_PARAM_TKIP_COUNTERMEASURES 2 +#define IEEE_PARAM_DROP_UNENCRYPTED 3 +#define IEEE_PARAM_PRIVACY_INVOKED 4 +#define IEEE_PARAM_AUTH_ALGS 5 +#define IEEE_PARAM_IEEE_802_1X 6 +//It should consistent with the driver_XXX.c +// David, 2006.9.26 +#define IEEE_PARAM_WPAX_SELECT 7 +//Added for notify the encryption type selection +// David, 2006.9.26 +#define IEEE_PROTO_WPA 1 +#define IEEE_PROTO_RSN 2 +//Added for notify the encryption type selection +// David, 2006.9.26 +#define IEEE_WPAX_USEGROUP 0 +#define IEEE_WPAX_WEP40 1 +#define IEEE_WPAX_TKIP 2 +#define IEEE_WPAX_WRAP 3 +#define IEEE_WPAX_CCMP 4 +#define IEEE_WPAX_WEP104 5 + +#define IEEE_KEY_MGMT_IEEE8021X 1 +#define IEEE_KEY_MGMT_PSK 2 + +#define IEEE_MLME_STA_DEAUTH 1 +#define IEEE_MLME_STA_DISASSOC 2 + + +#define IEEE_CRYPT_ERR_UNKNOWN_ALG 2 +#define IEEE_CRYPT_ERR_UNKNOWN_ADDR 3 +#define IEEE_CRYPT_ERR_CRYPT_INIT_FAILED 4 +#define IEEE_CRYPT_ERR_KEY_SET_FAILED 5 +#define IEEE_CRYPT_ERR_TX_KEY_SET_FAILED 6 +#define IEEE_CRYPT_ERR_CARD_CONF_FAILED 7 + + +#define IEEE_CRYPT_ALG_NAME_LEN 16 + +#define MAX_IE_LEN 0xff + +// added for kernel conflict +#define ieee80211_crypt_deinit_entries ieee80211_crypt_deinit_entries_rsl +#define ieee80211_crypt_deinit_handler ieee80211_crypt_deinit_handler_rsl +#define ieee80211_crypt_delayed_deinit ieee80211_crypt_delayed_deinit_rsl +#define ieee80211_register_crypto_ops ieee80211_register_crypto_ops_rsl +#define ieee80211_unregister_crypto_ops ieee80211_unregister_crypto_ops_rsl +#define ieee80211_get_crypto_ops ieee80211_get_crypto_ops_rsl + +#define ieee80211_ccmp_null ieee80211_ccmp_null_rsl + +#define ieee80211_tkip_null ieee80211_tkip_null_rsl + +#define ieee80211_wep_null ieee80211_wep_null_rsl + +#define free_ieee80211 free_ieee80211_rsl +#define alloc_ieee80211 alloc_ieee80211_rsl + +#define ieee80211_rx ieee80211_rx_rsl +#define ieee80211_rx_mgt ieee80211_rx_mgt_rsl + +#define ieee80211_get_beacon ieee80211_get_beacon_rsl +#define ieee80211_wake_queue ieee80211_wake_queue_rsl +#define ieee80211_stop_queue ieee80211_stop_queue_rsl +#define ieee80211_reset_queue ieee80211_reset_queue_rsl +#define ieee80211_softmac_stop_protocol ieee80211_softmac_stop_protocol_rsl +#define ieee80211_softmac_start_protocol ieee80211_softmac_start_protocol_rsl +#define ieee80211_is_shortslot ieee80211_is_shortslot_rsl +#define ieee80211_is_54g ieee80211_is_54g_rsl +#define ieee80211_wpa_supplicant_ioctl ieee80211_wpa_supplicant_ioctl_rsl +#define ieee80211_ps_tx_ack ieee80211_ps_tx_ack_rsl +#define ieee80211_softmac_xmit ieee80211_softmac_xmit_rsl +#define ieee80211_stop_send_beacons ieee80211_stop_send_beacons_rsl +#define notify_wx_assoc_event notify_wx_assoc_event_rsl +#define SendDisassociation SendDisassociation_rsl +#define ieee80211_disassociate ieee80211_disassociate_rsl +#define ieee80211_start_send_beacons ieee80211_start_send_beacons_rsl +#define ieee80211_stop_scan ieee80211_stop_scan_rsl +#define ieee80211_send_probe_requests ieee80211_send_probe_requests_rsl +#define ieee80211_softmac_scan_syncro ieee80211_softmac_scan_syncro_rsl +#define ieee80211_start_scan_syncro ieee80211_start_scan_syncro_rsl + +#define ieee80211_wx_get_essid ieee80211_wx_get_essid_rsl +#define ieee80211_wx_set_essid ieee80211_wx_set_essid_rsl +#define ieee80211_wx_set_rate ieee80211_wx_set_rate_rsl +#define ieee80211_wx_get_rate ieee80211_wx_get_rate_rsl +#define ieee80211_wx_set_wap ieee80211_wx_set_wap_rsl +#define ieee80211_wx_get_wap ieee80211_wx_get_wap_rsl +#define ieee80211_wx_set_mode ieee80211_wx_set_mode_rsl +#define ieee80211_wx_get_mode ieee80211_wx_get_mode_rsl +#define ieee80211_wx_set_scan ieee80211_wx_set_scan_rsl +#define ieee80211_wx_get_freq ieee80211_wx_get_freq_rsl +#define ieee80211_wx_set_freq ieee80211_wx_set_freq_rsl +#define ieee80211_wx_set_rawtx ieee80211_wx_set_rawtx_rsl +#define ieee80211_wx_get_name ieee80211_wx_get_name_rsl +#define ieee80211_wx_set_power ieee80211_wx_set_power_rsl +#define ieee80211_wx_get_power ieee80211_wx_get_power_rsl +#define ieee80211_wlan_frequencies ieee80211_wlan_frequencies_rsl +#define ieee80211_wx_set_rts ieee80211_wx_set_rts_rsl +#define ieee80211_wx_get_rts ieee80211_wx_get_rts_rsl + +#define ieee80211_txb_free ieee80211_txb_free_rsl + +#define ieee80211_wx_set_gen_ie ieee80211_wx_set_gen_ie_rsl +#define ieee80211_wx_get_scan ieee80211_wx_get_scan_rsl +#define ieee80211_wx_set_encode ieee80211_wx_set_encode_rsl +#define ieee80211_wx_get_encode ieee80211_wx_get_encode_rsl +#if WIRELESS_EXT >= 18 +#define ieee80211_wx_set_mlme ieee80211_wx_set_mlme_rsl +#define ieee80211_wx_set_auth ieee80211_wx_set_auth_rsl +#define ieee80211_wx_set_encode_ext ieee80211_wx_set_encode_ext_rsl +#define ieee80211_wx_get_encode_ext ieee80211_wx_get_encode_ext_rsl +#endif + + +typedef struct ieee_param { + u32 cmd; + u8 sta_addr[ETH_ALEN]; + union { + struct { + u8 name; + u32 value; + } wpa_param; + struct { + u32 len; + u8 reserved[32]; + u8 data[0]; + } wpa_ie; + struct{ + int command; + int reason_code; + } mlme; + struct { + u8 alg[IEEE_CRYPT_ALG_NAME_LEN]; + u8 set_tx; + u32 err; + u8 idx; + u8 seq[8]; /* sequence counter (set: RX, get: TX) */ + u16 key_len; + u8 key[0]; + } crypt; + } u; +}ieee_param; + + +#if WIRELESS_EXT < 17 +#define IW_QUAL_QUAL_INVALID 0x10 +#define IW_QUAL_LEVEL_INVALID 0x20 +#define IW_QUAL_NOISE_INVALID 0x40 +#define IW_QUAL_QUAL_UPDATED 0x1 +#define IW_QUAL_LEVEL_UPDATED 0x2 +#define IW_QUAL_NOISE_UPDATED 0x4 +#endif + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)) +static inline void tq_init(struct tq_struct * task, void(*func)(void *), void *data) +{ + task->routine = func; + task->data = data; + //task->next = NULL; + INIT_LIST_HEAD(&task->list); + task->sync = 0; +} +#endif + +// linux under 2.6.9 release may not support it, so modify it for common use +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,9)) +//#define MSECS(t) (1000 * ((t) / HZ) + 1000 * ((t) % HZ) / HZ) +#define MSECS(t) (HZ * ((t) / 1000) + (HZ * ((t) % 1000)) / 1000) +static inline unsigned long msleep_interruptible_rsl(unsigned int msecs) +{ + unsigned long timeout = MSECS(msecs) + 1; + + while (timeout) { + set_current_state(TASK_INTERRUPTIBLE); + timeout = schedule_timeout(timeout); + } + return timeout; +} +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,31)) +static inline void msleep(unsigned int msecs) +{ + unsigned long timeout = MSECS(msecs) + 1; + + while (timeout) { + set_current_state(TASK_UNINTERRUPTIBLE); + timeout = schedule_timeout(timeout); + } +} +#endif +#else +#define MSECS(t) msecs_to_jiffies(t) +#define msleep_interruptible_rsl msleep_interruptible +#endif + +#define IEEE80211_DATA_LEN 2304 +/* Maximum size for the MA-UNITDATA primitive, 802.11 standard section + 6.2.1.1.2. + + The figure in section 7.1.2 suggests a body size of up to 2312 + bytes is allowed, which is a bit confusing, I suspect this + represents the 2304 bytes of real data, plus a possible 8 bytes of + WEP IV and ICV. (this interpretation suggested by Ramiro Barreiro) */ +#define IEEE80211_1ADDR_LEN 10 +#define IEEE80211_2ADDR_LEN 16 +#define IEEE80211_3ADDR_LEN 24 +#define IEEE80211_4ADDR_LEN 30 +#define IEEE80211_FCS_LEN 4 +#define IEEE80211_HLEN (IEEE80211_4ADDR_LEN) +#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN) +#define IEEE80211_MGMT_HDR_LEN 24 +#define IEEE80211_DATA_HDR3_LEN 24 +#define IEEE80211_DATA_HDR4_LEN 30 + +#define MIN_FRAG_THRESHOLD 256U +#define MAX_FRAG_THRESHOLD 2346U + + +/* Frame control field constants */ +#define IEEE80211_FCTL_VERS 0x0003 +#define IEEE80211_FCTL_FTYPE 0x000c +#define IEEE80211_FCTL_STYPE 0x00f0 +#define IEEE80211_FCTL_FRAMETYPE 0x00fc +#define IEEE80211_FCTL_TODS 0x0100 +#define IEEE80211_FCTL_FROMDS 0x0200 +#define IEEE80211_FCTL_DSTODS 0x0300 //added by david +#define IEEE80211_FCTL_MOREFRAGS 0x0400 +#define IEEE80211_FCTL_RETRY 0x0800 +#define IEEE80211_FCTL_PM 0x1000 +#define IEEE80211_FCTL_MOREDATA 0x2000 +#define IEEE80211_FCTL_WEP 0x4000 +#define IEEE80211_FCTL_ORDER 0x8000 + +#define IEEE80211_FTYPE_MGMT 0x0000 +#define IEEE80211_FTYPE_CTL 0x0004 +#define IEEE80211_FTYPE_DATA 0x0008 + +/* management */ +#define IEEE80211_STYPE_ASSOC_REQ 0x0000 +#define IEEE80211_STYPE_ASSOC_RESP 0x0010 +#define IEEE80211_STYPE_REASSOC_REQ 0x0020 +#define IEEE80211_STYPE_REASSOC_RESP 0x0030 +#define IEEE80211_STYPE_PROBE_REQ 0x0040 +#define IEEE80211_STYPE_PROBE_RESP 0x0050 +#define IEEE80211_STYPE_BEACON 0x0080 +#define IEEE80211_STYPE_ATIM 0x0090 +#define IEEE80211_STYPE_DISASSOC 0x00A0 +#define IEEE80211_STYPE_AUTH 0x00B0 +#define IEEE80211_STYPE_DEAUTH 0x00C0 +#define IEEE80211_STYPE_MANAGE_ACT 0x00D0 + +/* control */ +#define IEEE80211_STYPE_PSPOLL 0x00A0 +#define IEEE80211_STYPE_RTS 0x00B0 +#define IEEE80211_STYPE_CTS 0x00C0 +#define IEEE80211_STYPE_ACK 0x00D0 +#define IEEE80211_STYPE_CFEND 0x00E0 +#define IEEE80211_STYPE_CFENDACK 0x00F0 +#define IEEE80211_STYPE_BLOCKACK 0x0094 + +/* data */ +#define IEEE80211_STYPE_DATA 0x0000 +#define IEEE80211_STYPE_DATA_CFACK 0x0010 +#define IEEE80211_STYPE_DATA_CFPOLL 0x0020 +#define IEEE80211_STYPE_DATA_CFACKPOLL 0x0030 +#define IEEE80211_STYPE_NULLFUNC 0x0040 +#define IEEE80211_STYPE_CFACK 0x0050 +#define IEEE80211_STYPE_CFPOLL 0x0060 +#define IEEE80211_STYPE_CFACKPOLL 0x0070 +#define IEEE80211_STYPE_QOS_DATA 0x0080 //added for WMM 2006/8/2 +#define IEEE80211_STYPE_QOS_NULL 0x00C0 + +#define IEEE80211_SCTL_FRAG 0x000F +#define IEEE80211_SCTL_SEQ 0xFFF0 + +/* QOS control */ +#define IEEE80211_QCTL_TID 0x000F + +#define FC_QOS_BIT BIT7 +#define IsDataFrame(pdu) ( ((pdu[0] & 0x0C)==0x08) ? true : false ) +#define IsLegacyDataFrame(pdu) (IsDataFrame(pdu) && (!(pdu[0]&FC_QOS_BIT)) ) +//added by wb. Is this right? +#define IsQoSDataFrame(pframe) ((*(u16*)pframe&(IEEE80211_STYPE_QOS_DATA|IEEE80211_FTYPE_DATA)) == (IEEE80211_STYPE_QOS_DATA|IEEE80211_FTYPE_DATA)) +#define Frame_Order(pframe) (*(u16*)pframe&IEEE80211_FCTL_ORDER) +#define SN_LESS(a, b) (((a-b)&0x800)!=0) +#define SN_EQUAL(a, b) (a == b) +#define MAX_DEV_ADDR_SIZE 8 +typedef enum _ACT_CATEGORY{ + ACT_CAT_QOS = 1, + ACT_CAT_DLS = 2, + ACT_CAT_BA = 3, + ACT_CAT_HT = 7, + ACT_CAT_WMM = 17, +} ACT_CATEGORY, *PACT_CATEGORY; + +typedef enum _TS_ACTION{ + ACT_ADDTSREQ = 0, + ACT_ADDTSRSP = 1, + ACT_DELTS = 2, + ACT_SCHEDULE = 3, +} TS_ACTION, *PTS_ACTION; + +typedef enum _BA_ACTION{ + ACT_ADDBAREQ = 0, + ACT_ADDBARSP = 1, + ACT_DELBA = 2, +} BA_ACTION, *PBA_ACTION; + +typedef enum _InitialGainOpType{ + IG_Backup=0, + IG_Restore, + IG_Max +}InitialGainOpType; +//added by amy for LED 090319 +//================================================================================ +// LED customization. +//================================================================================ +typedef enum _LED_CTL_MODE{ + LED_CTL_POWER_ON = 1, + LED_CTL_LINK = 2, + LED_CTL_NO_LINK = 3, + LED_CTL_TX = 4, + LED_CTL_RX = 5, + LED_CTL_SITE_SURVEY = 6, + LED_CTL_POWER_OFF = 7, + LED_CTL_START_TO_LINK = 8, + LED_CTL_START_WPS = 9, + LED_CTL_STOP_WPS = 10, + LED_CTL_START_WPS_BOTTON = 11, //added for runtop +}LED_CTL_MODE; + +/* debug macros */ +#define CONFIG_IEEE80211_DEBUG +#ifdef CONFIG_IEEE80211_DEBUG +extern u32 ieee80211_debug_level; +#define IEEE80211_DEBUG(level, fmt, args...) \ +do { if (ieee80211_debug_level & (level)) \ + printk(KERN_DEBUG "ieee80211: " fmt, ## args); } while (0) +//wb added to debug out data buf +//if you want print DATA buffer related BA, please set ieee80211_debug_level to DATA|BA +#define IEEE80211_DEBUG_DATA(level, data, datalen) \ + do{ if ((ieee80211_debug_level & (level)) == (level)) \ + { \ + int i; \ + u8* pdata = (u8*) data; \ + printk(KERN_DEBUG "ieee80211: %s()\n", __FUNCTION__); \ + for(i=0; i<(int)(datalen); i++) \ + { \ + printk("%2x ", pdata[i]); \ + if ((i+1)%16 == 0) printk("\n"); \ + } \ + printk("\n"); \ + } \ + } while (0) +#else +#define IEEE80211_DEBUG(level, fmt, args...) do {} while (0) +#define IEEE80211_DEBUG_DATA(level, data, datalen) do {} while(0) +#endif /* CONFIG_IEEE80211_DEBUG */ + +/* debug macros not dependent on CONFIG_IEEE80211_DEBUG */ + +#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x" +#define MAC_ARG(x) ((u8*)(x))[0],((u8*)(x))[1],((u8*)(x))[2],((u8*)(x))[3],((u8*)(x))[4],((u8*)(x))[5] + +/* + * To use the debug system; + * + * If you are defining a new debug classification, simply add it to the #define + * list here in the form of: + * + * #define IEEE80211_DL_xxxx VALUE + * + * shifting value to the left one bit from the previous entry. xxxx should be + * the name of the classification (for example, WEP) + * + * You then need to either add a IEEE80211_xxxx_DEBUG() macro definition for your + * classification, or use IEEE80211_DEBUG(IEEE80211_DL_xxxx, ...) whenever you want + * to send output to that classification. + * + * To add your debug level to the list of levels seen when you perform + * + * % cat /proc/net/ipw/debug_level + * + * you simply need to add your entry to the ipw_debug_levels array. + * + * If you do not see debug_level in /proc/net/ipw then you do not have + * CONFIG_IEEE80211_DEBUG defined in your kernel configuration + * + */ + +#define IEEE80211_DL_INFO (1<<0) +#define IEEE80211_DL_WX (1<<1) +#define IEEE80211_DL_SCAN (1<<2) +#define IEEE80211_DL_STATE (1<<3) +#define IEEE80211_DL_MGMT (1<<4) +#define IEEE80211_DL_FRAG (1<<5) +#define IEEE80211_DL_EAP (1<<6) +#define IEEE80211_DL_DROP (1<<7) + +#define IEEE80211_DL_TX (1<<8) +#define IEEE80211_DL_RX (1<<9) + +#define IEEE80211_DL_HT (1<<10) //HT +#define IEEE80211_DL_BA (1<<11) //ba +#define IEEE80211_DL_TS (1<<12) //TS +#define IEEE80211_DL_QOS (1<<13) +#define IEEE80211_DL_REORDER (1<<14) +#define IEEE80211_DL_IOT (1<<15) +#define IEEE80211_DL_IPS (1<<16) +#define IEEE80211_DL_TRACE (1<<29) //trace function, need to user net_ratelimit() together in order not to print too much to the screen +#define IEEE80211_DL_DATA (1<<30) //use this flag to control whether print data buf out. +#define IEEE80211_DL_ERR (1<<31) //always open +#define IEEE80211_ERROR(f, a...) printk(KERN_ERR "ieee80211: " f, ## a) +#define IEEE80211_WARNING(f, a...) printk(KERN_WARNING "ieee80211: " f, ## a) +#define IEEE80211_DEBUG_INFO(f, a...) IEEE80211_DEBUG(IEEE80211_DL_INFO, f, ## a) + +#define IEEE80211_DEBUG_WX(f, a...) IEEE80211_DEBUG(IEEE80211_DL_WX, f, ## a) +#define IEEE80211_DEBUG_SCAN(f, a...) IEEE80211_DEBUG(IEEE80211_DL_SCAN, f, ## a) +#define IEEE80211_DEBUG_STATE(f, a...) IEEE80211_DEBUG(IEEE80211_DL_STATE, f, ## a) +#define IEEE80211_DEBUG_MGMT(f, a...) IEEE80211_DEBUG(IEEE80211_DL_MGMT, f, ## a) +#define IEEE80211_DEBUG_FRAG(f, a...) IEEE80211_DEBUG(IEEE80211_DL_FRAG, f, ## a) +#define IEEE80211_DEBUG_EAP(f, a...) IEEE80211_DEBUG(IEEE80211_DL_EAP, f, ## a) +#define IEEE80211_DEBUG_DROP(f, a...) IEEE80211_DEBUG(IEEE80211_DL_DROP, f, ## a) +#define IEEE80211_DEBUG_TX(f, a...) IEEE80211_DEBUG(IEEE80211_DL_TX, f, ## a) +#define IEEE80211_DEBUG_RX(f, a...) IEEE80211_DEBUG(IEEE80211_DL_RX, f, ## a) +#define IEEE80211_DEBUG_QOS(f, a...) IEEE80211_DEBUG(IEEE80211_DL_QOS, f, ## a) + +#ifdef CONFIG_IEEE80211_DEBUG +/* Added by Annie, 2005-11-22. */ +#define MAX_STR_LEN 64 +/* I want to see ASCII 33 to 126 only. Otherwise, I print '?'. Annie, 2005-11-22.*/ +#define PRINTABLE(_ch) (_ch>'!' && _ch<'~') +#define IEEE80211_PRINT_STR(_Comp, _TitleString, _Ptr, _Len) \ + if((_Comp) & level) \ + { \ + int __i; \ + u8 buffer[MAX_STR_LEN]; \ + int length = (_Len<MAX_STR_LEN)? _Len : (MAX_STR_LEN-1) ; \ + memset(buffer, 0, MAX_STR_LEN); \ + memcpy(buffer, (u8 *)_Ptr, length ); \ + for( __i=0; __i<MAX_STR_LEN; __i++ ) \ + { \ + if( !PRINTABLE(buffer[__i]) ) buffer[__i] = '?'; \ + } \ + buffer[length] = '\0'; \ + printk("Rtl819x: "); \ + printk(_TitleString); \ + printk(": %d, <%s>\n", _Len, buffer); \ + } +#else +#define IEEE80211_PRINT_STR(_Comp, _TitleString, _Ptr, _Len) do {} while (0) +#endif + +#include <linux/netdevice.h> +#include <linux/if_arp.h> /* ARPHRD_ETHER */ + +#ifndef WIRELESS_SPY +#define WIRELESS_SPY // enable iwspy support +#endif +#include <net/iw_handler.h> // new driver API + +#ifndef ETH_P_PAE +#define ETH_P_PAE 0x888E /* Port Access Entity (IEEE 802.1X) */ +#endif /* ETH_P_PAE */ + +#define ETH_P_PREAUTH 0x88C7 /* IEEE 802.11i pre-authentication */ + +#ifndef ETH_P_80211_RAW +#define ETH_P_80211_RAW (ETH_P_ECONET + 1) +#endif + +/* IEEE 802.11 defines */ + +#define P80211_OUI_LEN 3 + +struct ieee80211_snap_hdr { + + u8 dsap; /* always 0xAA */ + u8 ssap; /* always 0xAA */ + u8 ctrl; /* always 0x03 */ + u8 oui[P80211_OUI_LEN]; /* organizational universal id */ + +} __attribute__ ((packed)); + +#define SNAP_SIZE sizeof(struct ieee80211_snap_hdr) + +#define WLAN_FC_GET_VERS(fc) ((fc) & IEEE80211_FCTL_VERS) +#define WLAN_FC_GET_TYPE(fc) ((fc) & IEEE80211_FCTL_FTYPE) +#define WLAN_FC_GET_STYPE(fc) ((fc) & IEEE80211_FCTL_STYPE) + +#define WLAN_FC_GET_FRAMETYPE(fc) ((fc) & IEEE80211_FCTL_FRAMETYPE) +#define WLAN_GET_SEQ_FRAG(seq) ((seq) & IEEE80211_SCTL_FRAG) +#define WLAN_GET_SEQ_SEQ(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4) + +/* Authentication algorithms */ +#define WLAN_AUTH_OPEN 0 +#define WLAN_AUTH_SHARED_KEY 1 +#define WLAN_AUTH_LEAP 2 + +#define WLAN_AUTH_CHALLENGE_LEN 128 + +#define WLAN_CAPABILITY_BSS (1<<0) +#define WLAN_CAPABILITY_IBSS (1<<1) +#define WLAN_CAPABILITY_CF_POLLABLE (1<<2) +#define WLAN_CAPABILITY_CF_POLL_REQUEST (1<<3) +#define WLAN_CAPABILITY_PRIVACY (1<<4) +#define WLAN_CAPABILITY_SHORT_PREAMBLE (1<<5) +#define WLAN_CAPABILITY_PBCC (1<<6) +#define WLAN_CAPABILITY_CHANNEL_AGILITY (1<<7) +#define WLAN_CAPABILITY_SPECTRUM_MGMT (1<<8) +#define WLAN_CAPABILITY_QOS (1<<9) +#define WLAN_CAPABILITY_SHORT_SLOT (1<<10) +#define WLAN_CAPABILITY_DSSS_OFDM (1<<13) + +/* 802.11g ERP information element */ +#define WLAN_ERP_NON_ERP_PRESENT (1<<0) +#define WLAN_ERP_USE_PROTECTION (1<<1) +#define WLAN_ERP_BARKER_PREAMBLE (1<<2) + +/* Status codes */ +enum ieee80211_statuscode { + WLAN_STATUS_SUCCESS = 0, + WLAN_STATUS_UNSPECIFIED_FAILURE = 1, + WLAN_STATUS_CAPS_UNSUPPORTED = 10, + WLAN_STATUS_REASSOC_NO_ASSOC = 11, + WLAN_STATUS_ASSOC_DENIED_UNSPEC = 12, + WLAN_STATUS_NOT_SUPPORTED_AUTH_ALG = 13, + WLAN_STATUS_UNKNOWN_AUTH_TRANSACTION = 14, + WLAN_STATUS_CHALLENGE_FAIL = 15, + WLAN_STATUS_AUTH_TIMEOUT = 16, + WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA = 17, + WLAN_STATUS_ASSOC_DENIED_RATES = 18, + /* 802.11b */ + WLAN_STATUS_ASSOC_DENIED_NOSHORTPREAMBLE = 19, + WLAN_STATUS_ASSOC_DENIED_NOPBCC = 20, + WLAN_STATUS_ASSOC_DENIED_NOAGILITY = 21, + /* 802.11h */ + WLAN_STATUS_ASSOC_DENIED_NOSPECTRUM = 22, + WLAN_STATUS_ASSOC_REJECTED_BAD_POWER = 23, + WLAN_STATUS_ASSOC_REJECTED_BAD_SUPP_CHAN = 24, + /* 802.11g */ + WLAN_STATUS_ASSOC_DENIED_NOSHORTTIME = 25, + WLAN_STATUS_ASSOC_DENIED_NODSSSOFDM = 26, + /* 802.11i */ + WLAN_STATUS_INVALID_IE = 40, + WLAN_STATUS_INVALID_GROUP_CIPHER = 41, + WLAN_STATUS_INVALID_PAIRWISE_CIPHER = 42, + WLAN_STATUS_INVALID_AKMP = 43, + WLAN_STATUS_UNSUPP_RSN_VERSION = 44, + WLAN_STATUS_INVALID_RSN_IE_CAP = 45, + WLAN_STATUS_CIPHER_SUITE_REJECTED = 46, +}; + +/* Reason codes */ +enum ieee80211_reasoncode { + WLAN_REASON_UNSPECIFIED = 1, + WLAN_REASON_PREV_AUTH_NOT_VALID = 2, + WLAN_REASON_DEAUTH_LEAVING = 3, + WLAN_REASON_DISASSOC_DUE_TO_INACTIVITY = 4, + WLAN_REASON_DISASSOC_AP_BUSY = 5, + WLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA = 6, + WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA = 7, + WLAN_REASON_DISASSOC_STA_HAS_LEFT = 8, + WLAN_REASON_STA_REQ_ASSOC_WITHOUT_AUTH = 9, + /* 802.11h */ + WLAN_REASON_DISASSOC_BAD_POWER = 10, + WLAN_REASON_DISASSOC_BAD_SUPP_CHAN = 11, + /* 802.11i */ + WLAN_REASON_INVALID_IE = 13, + WLAN_REASON_MIC_FAILURE = 14, + WLAN_REASON_4WAY_HANDSHAKE_TIMEOUT = 15, + WLAN_REASON_GROUP_KEY_HANDSHAKE_TIMEOUT = 16, + WLAN_REASON_IE_DIFFERENT = 17, + WLAN_REASON_INVALID_GROUP_CIPHER = 18, + WLAN_REASON_INVALID_PAIRWISE_CIPHER = 19, + WLAN_REASON_INVALID_AKMP = 20, + WLAN_REASON_UNSUPP_RSN_VERSION = 21, + WLAN_REASON_INVALID_RSN_IE_CAP = 22, + WLAN_REASON_IEEE8021X_FAILED = 23, + WLAN_REASON_CIPHER_SUITE_REJECTED = 24, +}; + +#define IEEE80211_STATMASK_SIGNAL (1<<0) +#define IEEE80211_STATMASK_RSSI (1<<1) +#define IEEE80211_STATMASK_NOISE (1<<2) +#define IEEE80211_STATMASK_RATE (1<<3) +#define IEEE80211_STATMASK_WEMASK 0x7 + +#define IEEE80211_CCK_MODULATION (1<<0) +#define IEEE80211_OFDM_MODULATION (1<<1) + +#define IEEE80211_24GHZ_BAND (1<<0) +#define IEEE80211_52GHZ_BAND (1<<1) + +#define IEEE80211_CCK_RATE_LEN 4 +#define IEEE80211_CCK_RATE_1MB 0x02 +#define IEEE80211_CCK_RATE_2MB 0x04 +#define IEEE80211_CCK_RATE_5MB 0x0B +#define IEEE80211_CCK_RATE_11MB 0x16 +#define IEEE80211_OFDM_RATE_LEN 8 +#define IEEE80211_OFDM_RATE_6MB 0x0C +#define IEEE80211_OFDM_RATE_9MB 0x12 +#define IEEE80211_OFDM_RATE_12MB 0x18 +#define IEEE80211_OFDM_RATE_18MB 0x24 +#define IEEE80211_OFDM_RATE_24MB 0x30 +#define IEEE80211_OFDM_RATE_36MB 0x48 +#define IEEE80211_OFDM_RATE_48MB 0x60 +#define IEEE80211_OFDM_RATE_54MB 0x6C +#define IEEE80211_BASIC_RATE_MASK 0x80 + +#define IEEE80211_CCK_RATE_1MB_MASK (1<<0) +#define IEEE80211_CCK_RATE_2MB_MASK (1<<1) +#define IEEE80211_CCK_RATE_5MB_MASK (1<<2) +#define IEEE80211_CCK_RATE_11MB_MASK (1<<3) +#define IEEE80211_OFDM_RATE_6MB_MASK (1<<4) +#define IEEE80211_OFDM_RATE_9MB_MASK (1<<5) +#define IEEE80211_OFDM_RATE_12MB_MASK (1<<6) +#define IEEE80211_OFDM_RATE_18MB_MASK (1<<7) +#define IEEE80211_OFDM_RATE_24MB_MASK (1<<8) +#define IEEE80211_OFDM_RATE_36MB_MASK (1<<9) +#define IEEE80211_OFDM_RATE_48MB_MASK (1<<10) +#define IEEE80211_OFDM_RATE_54MB_MASK (1<<11) + +#define IEEE80211_CCK_RATES_MASK 0x0000000F +#define IEEE80211_CCK_BASIC_RATES_MASK (IEEE80211_CCK_RATE_1MB_MASK | \ + IEEE80211_CCK_RATE_2MB_MASK) +#define IEEE80211_CCK_DEFAULT_RATES_MASK (IEEE80211_CCK_BASIC_RATES_MASK | \ + IEEE80211_CCK_RATE_5MB_MASK | \ + IEEE80211_CCK_RATE_11MB_MASK) + +#define IEEE80211_OFDM_RATES_MASK 0x00000FF0 +#define IEEE80211_OFDM_BASIC_RATES_MASK (IEEE80211_OFDM_RATE_6MB_MASK | \ + IEEE80211_OFDM_RATE_12MB_MASK | \ + IEEE80211_OFDM_RATE_24MB_MASK) +#define IEEE80211_OFDM_DEFAULT_RATES_MASK (IEEE80211_OFDM_BASIC_RATES_MASK | \ + IEEE80211_OFDM_RATE_9MB_MASK | \ + IEEE80211_OFDM_RATE_18MB_MASK | \ + IEEE80211_OFDM_RATE_36MB_MASK | \ + IEEE80211_OFDM_RATE_48MB_MASK | \ + IEEE80211_OFDM_RATE_54MB_MASK) +#define IEEE80211_DEFAULT_RATES_MASK (IEEE80211_OFDM_DEFAULT_RATES_MASK | \ + IEEE80211_CCK_DEFAULT_RATES_MASK) + +#define IEEE80211_NUM_OFDM_RATES 8 +#define IEEE80211_NUM_CCK_RATES 4 +#define IEEE80211_OFDM_SHIFT_MASK_A 4 + + +/* this is stolen and modified from the madwifi driver*/ +#define IEEE80211_FC0_TYPE_MASK 0x0c +#define IEEE80211_FC0_TYPE_DATA 0x08 +#define IEEE80211_FC0_SUBTYPE_MASK 0xB0 +#define IEEE80211_FC0_SUBTYPE_QOS 0x80 + +#define IEEE80211_QOS_HAS_SEQ(fc) \ + (((fc) & (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == \ + (IEEE80211_FC0_TYPE_DATA | IEEE80211_FC0_SUBTYPE_QOS)) + +/* this is stolen from ipw2200 driver */ +#define IEEE_IBSS_MAC_HASH_SIZE 31 +struct ieee_ibss_seq { + u8 mac[ETH_ALEN]; + u16 seq_num[17]; + u16 frag_num[17]; + unsigned long packet_time[17]; + struct list_head list; +}; + +/* NOTE: This data is for statistical purposes; not all hardware provides this + * information for frames received. Not setting these will not cause + * any adverse affects. */ +struct ieee80211_rx_stats { +#if 1 + u32 mac_time[2]; + s8 rssi; + u8 signal; + u8 noise; + u16 rate; /* in 100 kbps */ + u8 received_channel; + u8 control; + u8 mask; + u8 freq; + u16 len; + u64 tsf; + u32 beacon_time; + u8 nic_type; + u16 Length; + // u8 DataRate; // In 0.5 Mbps + u8 SignalQuality; // in 0-100 index. + s32 RecvSignalPower; // Real power in dBm for this packet, no beautification and aggregation. + s8 RxPower; // in dBm Translate from PWdB + u8 SignalStrength; // in 0-100 index. + u16 bHwError:1; + u16 bCRC:1; + u16 bICV:1; + u16 bShortPreamble:1; + u16 Antenna:1; //for rtl8185 + u16 Decrypted:1; //for rtl8185, rtl8187 + u16 Wakeup:1; //for rtl8185 + u16 Reserved0:1; //for rtl8185 + u8 AGC; + u32 TimeStampLow; + u32 TimeStampHigh; + bool bShift; + bool bIsQosData; // Added by Annie, 2005-12-22. + u8 UserPriority; + + //1!!!!!!!!!!!!!!!!!!!!!!!!!!! + //1Attention Please!!!<11n or 8190 specific code should be put below this line> + //1!!!!!!!!!!!!!!!!!!!!!!!!!!! + + u8 RxDrvInfoSize; + u8 RxBufShift; + bool bIsAMPDU; + bool bFirstMPDU; + bool bContainHTC; + bool RxIs40MHzPacket; + u32 RxPWDBAll; + u8 RxMIMOSignalStrength[4]; // in 0~100 index + s8 RxMIMOSignalQuality[2]; + bool bPacketMatchBSSID; + bool bIsCCK; + bool bPacketToSelf; + //added by amy + u8* virtual_address; + u16 packetlength; // Total packet length: Must equal to sum of all FragLength + u16 fraglength; // FragLength should equal to PacketLength in non-fragment case + u16 fragoffset; // Data offset for this fragment + u16 ntotalfrag; + bool bisrxaggrsubframe; + bool bPacketBeacon; //cosa add for rssi + bool bToSelfBA; //cosa add for rssi + char cck_adc_pwdb[4]; //cosa add for rx path selection + u16 Seq_Num; + u8 nTotalAggPkt; // Number of aggregated packets. +#endif + +}; + +/* IEEE 802.11 requires that STA supports concurrent reception of at least + * three fragmented frames. This define can be increased to support more + * concurrent frames, but it should be noted that each entry can consume about + * 2 kB of RAM and increasing cache size will slow down frame reassembly. */ +#define IEEE80211_FRAG_CACHE_LEN 4 + +struct ieee80211_frag_entry { + unsigned long first_frag_time; + unsigned int seq; + unsigned int last_frag; + struct sk_buff *skb; + u8 src_addr[ETH_ALEN]; + u8 dst_addr[ETH_ALEN]; +}; + +struct ieee80211_stats { + unsigned int tx_unicast_frames; + unsigned int tx_multicast_frames; + unsigned int tx_fragments; + unsigned int tx_unicast_octets; + unsigned int tx_multicast_octets; + unsigned int tx_deferred_transmissions; + unsigned int tx_single_retry_frames; + unsigned int tx_multiple_retry_frames; + unsigned int tx_retry_limit_exceeded; + unsigned int tx_discards; + unsigned int rx_unicast_frames; + unsigned int rx_multicast_frames; + unsigned int rx_fragments; + unsigned int rx_unicast_octets; + unsigned int rx_multicast_octets; + unsigned int rx_fcs_errors; + unsigned int rx_discards_no_buffer; + unsigned int tx_discards_wrong_sa; + unsigned int rx_discards_undecryptable; + unsigned int rx_message_in_msg_fragments; + unsigned int rx_message_in_bad_msg_fragments; +}; + +struct ieee80211_device; + +#include "ieee80211_crypt.h" + +#define SEC_KEY_1 (1<<0) +#define SEC_KEY_2 (1<<1) +#define SEC_KEY_3 (1<<2) +#define SEC_KEY_4 (1<<3) +#define SEC_ACTIVE_KEY (1<<4) +#define SEC_AUTH_MODE (1<<5) +#define SEC_UNICAST_GROUP (1<<6) +#define SEC_LEVEL (1<<7) +#define SEC_ENABLED (1<<8) +#define SEC_ENCRYPT (1<<9) + +#define SEC_LEVEL_0 0 /* None */ +#define SEC_LEVEL_1 1 /* WEP 40 and 104 bit */ +#define SEC_LEVEL_2 2 /* Level 1 + TKIP */ +#define SEC_LEVEL_2_CKIP 3 /* Level 1 + CKIP */ +#define SEC_LEVEL_3 4 /* Level 2 + CCMP */ + +#define SEC_ALG_NONE 0 +#define SEC_ALG_WEP 1 +#define SEC_ALG_TKIP 2 +#define SEC_ALG_CCMP 3 + +#define WEP_KEYS 4 +#define WEP_KEY_LEN 13 +#define SCM_KEY_LEN 32 +#define SCM_TEMPORAL_KEY_LENGTH 16 + +struct ieee80211_security { + u16 active_key:2, + enabled:1, + auth_mode:2, + auth_algo:4, + unicast_uses_group:1, + encrypt:1; + u8 key_sizes[WEP_KEYS]; + u8 keys[WEP_KEYS][SCM_KEY_LEN]; + u8 level; + u16 flags; +} __attribute__ ((packed)); + + +/* + 802.11 data frame from AP + ,-------------------------------------------------------------------. +Bytes | 2 | 2 | 6 | 6 | 6 | 2 | 0..2312 | 4 | + |------|------|---------|---------|---------|------|---------|------| +Desc. | ctrl | dura | DA/RA | TA | SA | Sequ | frame | fcs | + | | tion | (BSSID) | | | ence | data | | + `-------------------------------------------------------------------' +Total: 28-2340 bytes +*/ + +/* Management Frame Information Element Types */ +enum ieee80211_mfie { + MFIE_TYPE_SSID = 0, + MFIE_TYPE_RATES = 1, + MFIE_TYPE_FH_SET = 2, + MFIE_TYPE_DS_SET = 3, + MFIE_TYPE_CF_SET = 4, + MFIE_TYPE_TIM = 5, + MFIE_TYPE_IBSS_SET = 6, + MFIE_TYPE_COUNTRY = 7, + MFIE_TYPE_HOP_PARAMS = 8, + MFIE_TYPE_HOP_TABLE = 9, + MFIE_TYPE_REQUEST = 10, + MFIE_TYPE_CHALLENGE = 16, + MFIE_TYPE_POWER_CONSTRAINT = 32, + MFIE_TYPE_POWER_CAPABILITY = 33, + MFIE_TYPE_TPC_REQUEST = 34, + MFIE_TYPE_TPC_REPORT = 35, + MFIE_TYPE_SUPP_CHANNELS = 36, + MFIE_TYPE_CSA = 37, + MFIE_TYPE_MEASURE_REQUEST = 38, + MFIE_TYPE_MEASURE_REPORT = 39, + MFIE_TYPE_QUIET = 40, + MFIE_TYPE_IBSS_DFS = 41, + MFIE_TYPE_ERP = 42, + MFIE_TYPE_RSN = 48, + MFIE_TYPE_RATES_EX = 50, + MFIE_TYPE_HT_CAP= 45, + MFIE_TYPE_HT_INFO= 61, + MFIE_TYPE_AIRONET=133, + MFIE_TYPE_GENERIC = 221, + MFIE_TYPE_QOS_PARAMETER = 222, +}; + +/* Minimal header; can be used for passing 802.11 frames with sufficient + * information to determine what type of underlying data type is actually + * stored in the data. */ +struct ieee80211_hdr { + __le16 frame_ctl; + __le16 duration_id; + u8 payload[0]; +} __attribute__ ((packed)); + +struct ieee80211_hdr_1addr { + __le16 frame_ctl; + __le16 duration_id; + u8 addr1[ETH_ALEN]; + u8 payload[0]; +} __attribute__ ((packed)); + +struct ieee80211_hdr_2addr { + __le16 frame_ctl; + __le16 duration_id; + u8 addr1[ETH_ALEN]; + u8 addr2[ETH_ALEN]; + u8 payload[0]; +} __attribute__ ((packed)); + +struct ieee80211_hdr_3addr { + __le16 frame_ctl; + __le16 duration_id; + u8 addr1[ETH_ALEN]; + u8 addr2[ETH_ALEN]; + u8 addr3[ETH_ALEN]; + __le16 seq_ctl; + u8 payload[0]; +} __attribute__ ((packed)); + +struct ieee80211_hdr_4addr { + __le16 frame_ctl; + __le16 duration_id; + u8 addr1[ETH_ALEN]; + u8 addr2[ETH_ALEN]; + u8 addr3[ETH_ALEN]; + __le16 seq_ctl; + u8 addr4[ETH_ALEN]; + u8 payload[0]; +} __attribute__ ((packed)); + +struct ieee80211_hdr_3addrqos { + __le16 frame_ctl; + __le16 duration_id; + u8 addr1[ETH_ALEN]; + u8 addr2[ETH_ALEN]; + u8 addr3[ETH_ALEN]; + __le16 seq_ctl; + u8 payload[0]; + __le16 qos_ctl; +} __attribute__ ((packed)); + +struct ieee80211_hdr_4addrqos { + __le16 frame_ctl; + __le16 duration_id; + u8 addr1[ETH_ALEN]; + u8 addr2[ETH_ALEN]; + u8 addr3[ETH_ALEN]; + __le16 seq_ctl; + u8 addr4[ETH_ALEN]; + u8 payload[0]; + __le16 qos_ctl; +} __attribute__ ((packed)); + +struct ieee80211_info_element { + u8 id; + u8 len; + u8 data[0]; +} __attribute__ ((packed)); + +struct ieee80211_authentication { + struct ieee80211_hdr_3addr header; + __le16 algorithm; + __le16 transaction; + __le16 status; + /*challenge*/ + struct ieee80211_info_element info_element[0]; +} __attribute__ ((packed)); + +struct ieee80211_disassoc { + struct ieee80211_hdr_3addr header; + __le16 reason; +} __attribute__ ((packed)); + +struct ieee80211_probe_request { + struct ieee80211_hdr_3addr header; + /* SSID, supported rates */ + struct ieee80211_info_element info_element[0]; +} __attribute__ ((packed)); + +struct ieee80211_probe_response { + struct ieee80211_hdr_3addr header; + u32 time_stamp[2]; + __le16 beacon_interval; + __le16 capability; + /* SSID, supported rates, FH params, DS params, + * CF params, IBSS params, TIM (if beacon), RSN */ + struct ieee80211_info_element info_element[0]; +} __attribute__ ((packed)); + +/* Alias beacon for probe_response */ +#define ieee80211_beacon ieee80211_probe_response + +struct ieee80211_assoc_request_frame { + struct ieee80211_hdr_3addr header; + __le16 capability; + __le16 listen_interval; + /* SSID, supported rates, RSN */ + struct ieee80211_info_element info_element[0]; +} __attribute__ ((packed)); + +struct ieee80211_reassoc_request_frame { + struct ieee80211_hdr_3addr header; + __le16 capability; + __le16 listen_interval; + u8 current_ap[ETH_ALEN]; + /* SSID, supported rates, RSN */ + struct ieee80211_info_element info_element[0]; +} __attribute__ ((packed)); + +struct ieee80211_assoc_response_frame { + struct ieee80211_hdr_3addr header; + __le16 capability; + __le16 status; + __le16 aid; + struct ieee80211_info_element info_element[0]; /* supported rates */ +} __attribute__ ((packed)); + +struct ieee80211_txb { + u8 nr_frags; + u8 encrypted; + u8 queue_index; + u8 rts_included; + u16 reserved; + __le16 frag_size; + __le16 payload_size; + struct sk_buff *fragments[0]; +}; + +#define MAX_TX_AGG_COUNT 16 +struct ieee80211_drv_agg_txb { + u8 nr_drv_agg_frames; + struct sk_buff *tx_agg_frames[MAX_TX_AGG_COUNT]; +}__attribute__((packed)); + +#define MAX_SUBFRAME_COUNT 64 +struct ieee80211_rxb { + u8 nr_subframes; + struct sk_buff *subframes[MAX_SUBFRAME_COUNT]; + u8 dst[ETH_ALEN]; + u8 src[ETH_ALEN]; +}__attribute__((packed)); + +typedef union _frameqos { + u16 shortdata; + u8 chardata[2]; + struct { + u16 tid:4; + u16 eosp:1; + u16 ack_policy:2; + u16 reserved:1; + u16 txop:8; + }field; +}frameqos,*pframeqos; + +/* SWEEP TABLE ENTRIES NUMBER*/ +#define MAX_SWEEP_TAB_ENTRIES 42 +#define MAX_SWEEP_TAB_ENTRIES_PER_PACKET 7 +/* MAX_RATES_LENGTH needs to be 12. The spec says 8, and many APs + * only use 8, and then use extended rates for the remaining supported + * rates. Other APs, however, stick all of their supported rates on the + * main rates information element... */ +#define MAX_RATES_LENGTH ((u8)12) +#define MAX_RATES_EX_LENGTH ((u8)16) +#define MAX_NETWORK_COUNT 128 + +#define MAX_CHANNEL_NUMBER 161 +#define IEEE80211_SOFTMAC_SCAN_TIME 100 +//(HZ / 2) +#define IEEE80211_SOFTMAC_ASSOC_RETRY_TIME (HZ * 2) + +#define CRC_LENGTH 4U + +#define MAX_WPA_IE_LEN 64 + +#define NETWORK_EMPTY_ESSID (1<<0) +#define NETWORK_HAS_OFDM (1<<1) +#define NETWORK_HAS_CCK (1<<2) + +/* QoS structure */ +#define NETWORK_HAS_QOS_PARAMETERS (1<<3) +#define NETWORK_HAS_QOS_INFORMATION (1<<4) +#define NETWORK_HAS_QOS_MASK (NETWORK_HAS_QOS_PARAMETERS | \ + NETWORK_HAS_QOS_INFORMATION) +/* 802.11h */ +#define NETWORK_HAS_POWER_CONSTRAINT (1<<5) +#define NETWORK_HAS_CSA (1<<6) +#define NETWORK_HAS_QUIET (1<<7) +#define NETWORK_HAS_IBSS_DFS (1<<8) +#define NETWORK_HAS_TPC_REPORT (1<<9) + +#define NETWORK_HAS_ERP_VALUE (1<<10) + +#define QOS_QUEUE_NUM 4 +#define QOS_OUI_LEN 3 +#define QOS_OUI_TYPE 2 +#define QOS_ELEMENT_ID 221 +#define QOS_OUI_INFO_SUB_TYPE 0 +#define QOS_OUI_PARAM_SUB_TYPE 1 +#define QOS_VERSION_1 1 +#define QOS_AIFSN_MIN_VALUE 2 +#if 1 +struct ieee80211_qos_information_element { + u8 elementID; + u8 length; + u8 qui[QOS_OUI_LEN]; + u8 qui_type; + u8 qui_subtype; + u8 version; + u8 ac_info; +} __attribute__ ((packed)); + +struct ieee80211_qos_ac_parameter { + u8 aci_aifsn; + u8 ecw_min_max; + __le16 tx_op_limit; +} __attribute__ ((packed)); + +struct ieee80211_qos_parameter_info { + struct ieee80211_qos_information_element info_element; + u8 reserved; + struct ieee80211_qos_ac_parameter ac_params_record[QOS_QUEUE_NUM]; +} __attribute__ ((packed)); + +struct ieee80211_qos_parameters { + __le16 cw_min[QOS_QUEUE_NUM]; + __le16 cw_max[QOS_QUEUE_NUM]; + u8 aifs[QOS_QUEUE_NUM]; + u8 flag[QOS_QUEUE_NUM]; + __le16 tx_op_limit[QOS_QUEUE_NUM]; +} __attribute__ ((packed)); + +struct ieee80211_qos_data { + struct ieee80211_qos_parameters parameters; + int active; + int supported; + u8 param_count; + u8 old_param_count; +}; + +struct ieee80211_tim_parameters { + u8 tim_count; + u8 tim_period; +} __attribute__ ((packed)); + +//#else +struct ieee80211_wmm_ac_param { + u8 ac_aci_acm_aifsn; + u8 ac_ecwmin_ecwmax; + u16 ac_txop_limit; +}; + +struct ieee80211_wmm_ts_info { + u8 ac_dir_tid; + u8 ac_up_psb; + u8 reserved; +} __attribute__ ((packed)); + +struct ieee80211_wmm_tspec_elem { + struct ieee80211_wmm_ts_info ts_info; + u16 norm_msdu_size; + u16 max_msdu_size; + u32 min_serv_inter; + u32 max_serv_inter; + u32 inact_inter; + u32 suspen_inter; + u32 serv_start_time; + u32 min_data_rate; + u32 mean_data_rate; + u32 peak_data_rate; + u32 max_burst_size; + u32 delay_bound; + u32 min_phy_rate; + u16 surp_band_allow; + u16 medium_time; +}__attribute__((packed)); +#endif +enum eap_type { + EAP_PACKET = 0, + EAPOL_START, + EAPOL_LOGOFF, + EAPOL_KEY, + EAPOL_ENCAP_ASF_ALERT +}; + +static const char *eap_types[] = { + [EAP_PACKET] = "EAP-Packet", + [EAPOL_START] = "EAPOL-Start", + [EAPOL_LOGOFF] = "EAPOL-Logoff", + [EAPOL_KEY] = "EAPOL-Key", + [EAPOL_ENCAP_ASF_ALERT] = "EAPOL-Encap-ASF-Alert" +}; + +static inline const char *eap_get_type(int type) +{ + return ((u32)type >= ARRAY_SIZE(eap_types)) ? "Unknown" : eap_types[type]; +} +//added by amy for reorder +static inline u8 Frame_QoSTID(u8* buf) +{ + struct ieee80211_hdr_3addr *hdr; + u16 fc; + hdr = (struct ieee80211_hdr_3addr *)buf; + fc = le16_to_cpu(hdr->frame_ctl); + return (u8)((frameqos*)(buf + (((fc & IEEE80211_FCTL_TODS)&&(fc & IEEE80211_FCTL_FROMDS))? 30 : 24)))->field.tid; +} + +//added by amy for reorder + +struct eapol { + u8 snap[6]; + u16 ethertype; + u8 version; + u8 type; + u16 length; +} __attribute__ ((packed)); + +struct ieee80211_softmac_stats{ + unsigned int rx_ass_ok; + unsigned int rx_ass_err; + unsigned int rx_probe_rq; + unsigned int tx_probe_rs; + unsigned int tx_beacons; + unsigned int rx_auth_rq; + unsigned int rx_auth_rs_ok; + unsigned int rx_auth_rs_err; + unsigned int tx_auth_rq; + unsigned int no_auth_rs; + unsigned int no_ass_rs; + unsigned int tx_ass_rq; + unsigned int rx_ass_rq; + unsigned int tx_probe_rq; + unsigned int reassoc; + unsigned int swtxstop; + unsigned int swtxawake; + unsigned char CurrentShowTxate; + unsigned char last_packet_rate; + unsigned int txretrycount; +}; + +#define BEACON_PROBE_SSID_ID_POSITION 12 + +struct ieee80211_info_element_hdr { + u8 id; + u8 len; +} __attribute__ ((packed)); + +/* + * These are the data types that can make up management packets + * + u16 auth_algorithm; + u16 auth_sequence; + u16 beacon_interval; + u16 capability; + u8 current_ap[ETH_ALEN]; + u16 listen_interval; + struct { + u16 association_id:14, reserved:2; + } __attribute__ ((packed)); + u32 time_stamp[2]; + u16 reason; + u16 status; +*/ + +#define IEEE80211_DEFAULT_TX_ESSID "Penguin" +#define IEEE80211_DEFAULT_BASIC_RATE 2 //1Mbps + +enum {WMM_all_frame, WMM_two_frame, WMM_four_frame, WMM_six_frame}; +#define MAX_SP_Len (WMM_all_frame << 4) +#define IEEE80211_QOS_TID 0x0f +#define QOS_CTL_NOTCONTAIN_ACK (0x01 << 5) + +#define IEEE80211_DTIM_MBCAST 4 +#define IEEE80211_DTIM_UCAST 2 +#define IEEE80211_DTIM_VALID 1 +#define IEEE80211_DTIM_INVALID 0 + +#define IEEE80211_PS_DISABLED 0 +#define IEEE80211_PS_UNICAST IEEE80211_DTIM_UCAST +#define IEEE80211_PS_MBCAST IEEE80211_DTIM_MBCAST + +//added by David for QoS 2006/6/30 +//#define WMM_Hang_8187 +#ifdef WMM_Hang_8187 +#undef WMM_Hang_8187 +#endif + +#define WME_AC_BK 0x00 +#define WME_AC_BE 0x01 +#define WME_AC_VI 0x02 +#define WME_AC_VO 0x03 +#define WME_ACI_MASK 0x03 +#define WME_AIFSN_MASK 0x03 +#define WME_AC_PRAM_LEN 16 + +#define MAX_RECEIVE_BUFFER_SIZE 9100 + +//UP Mapping to AC, using in MgntQuery_SequenceNumber() and maybe for DSCP +//#define UP2AC(up) ((up<3) ? ((up==0)?1:0) : (up>>1)) +#if 1 +#define UP2AC(up) ( \ + ((up) < 1) ? WME_AC_BE : \ + ((up) < 3) ? WME_AC_BK : \ + ((up) < 4) ? WME_AC_BE : \ + ((up) < 6) ? WME_AC_VI : \ + WME_AC_VO) +#endif +//AC Mapping to UP, using in Tx part for selecting the corresponding TX queue +#define AC2UP(_ac) ( \ + ((_ac) == WME_AC_VO) ? 6 : \ + ((_ac) == WME_AC_VI) ? 5 : \ + ((_ac) == WME_AC_BK) ? 1 : \ + 0) + +#define ETHER_ADDR_LEN 6 /* length of an Ethernet address */ +#define ETHERNET_HEADER_SIZE 14 /* length of two Ethernet address plus ether type*/ + +struct ether_header { + u8 ether_dhost[ETHER_ADDR_LEN]; + u8 ether_shost[ETHER_ADDR_LEN]; + u16 ether_type; +} __attribute__((packed)); + +#ifndef ETHERTYPE_PAE +#define ETHERTYPE_PAE 0x888e /* EAPOL PAE/802.1x */ +#endif +#ifndef ETHERTYPE_IP +#define ETHERTYPE_IP 0x0800 /* IP protocol */ +#endif + +typedef struct _bss_ht{ + + bool support_ht; + + // HT related elements + u8 ht_cap_buf[32]; + u16 ht_cap_len; + u8 ht_info_buf[32]; + u16 ht_info_len; + + HT_SPEC_VER ht_spec_ver; + //HT_CAPABILITY_ELE bdHTCapEle; + //HT_INFORMATION_ELE bdHTInfoEle; + + bool aggregation; + bool long_slot_time; +}bss_ht, *pbss_ht; + +typedef enum _erp_t{ + ERP_NonERPpresent = 0x01, + ERP_UseProtection = 0x02, + ERP_BarkerPreambleMode = 0x04, +} erp_t; + + +struct ieee80211_network { + /* These entries are used to identify a unique network */ + u8 bssid[ETH_ALEN]; + u8 channel; + /* Ensure null-terminated for any debug msgs */ + u8 ssid[IW_ESSID_MAX_SIZE + 1]; + u8 ssid_len; +#if 1 + struct ieee80211_qos_data qos_data; +#else + // Qos related. Added by Annie, 2005-11-01. + BSS_QOS BssQos; +#endif + + //added by amy for LEAP + bool bWithAironetIE; + bool bCkipSupported; + bool bCcxRmEnable; + u16 CcxRmState[2]; + // CCXv4 S59, MBSSID. + bool bMBssidValid; + u8 MBssidMask; + u8 MBssid[6]; + // CCX 2 S38, WLAN Device Version Number element. Annie, 2006-08-20. + bool bWithCcxVerNum; + u8 BssCcxVerNumber; + /* These are network statistics */ + struct ieee80211_rx_stats stats; + u16 capability; + u8 rates[MAX_RATES_LENGTH]; + u8 rates_len; + u8 rates_ex[MAX_RATES_EX_LENGTH]; + u8 rates_ex_len; + unsigned long last_scanned; + u8 mode; + u32 flags; + u32 last_associate; + u32 time_stamp[2]; + u16 beacon_interval; + u16 listen_interval; + u16 atim_window; + u8 erp_value; + u8 wpa_ie[MAX_WPA_IE_LEN]; + size_t wpa_ie_len; + u8 rsn_ie[MAX_WPA_IE_LEN]; + size_t rsn_ie_len; + + struct ieee80211_tim_parameters tim; + u8 dtim_period; + u8 dtim_data; + u32 last_dtim_sta_time[2]; + + //appeded for QoS + u8 wmm_info; + struct ieee80211_wmm_ac_param wmm_param[4]; + u8 QoS_Enable; +#ifdef THOMAS_TURBO + u8 Turbo_Enable;//enable turbo mode, added by thomas +#endif +#ifdef ENABLE_DOT11D + u16 CountryIeLen; + u8 CountryIeBuf[MAX_IE_LEN]; +#endif + // HT Related, by amy, 2008.04.29 + BSS_HT bssht; + // Add to handle broadcom AP management frame CCK rate. + bool broadcom_cap_exist; + bool realtek_cap_exit; + bool marvell_cap_exist; + bool ralink_cap_exist; + bool atheros_cap_exist; + bool cisco_cap_exist; + bool unknown_cap_exist; +// u8 berp_info; + bool berp_info_valid; + bool buseprotection; + //put at the end of the structure. + struct list_head list; +}; + +#if 1 +enum ieee80211_state { + + /* the card is not linked at all */ + IEEE80211_NOLINK = 0, + + /* IEEE80211_ASSOCIATING* are for BSS client mode + * the driver shall not perform RX filtering unless + * the state is LINKED. + * The driver shall just check for the state LINKED and + * defaults to NOLINK for ALL the other states (including + * LINKED_SCANNING) + */ + + /* the association procedure will start (wq scheduling)*/ + IEEE80211_ASSOCIATING, + IEEE80211_ASSOCIATING_RETRY, + + /* the association procedure is sending AUTH request*/ + IEEE80211_ASSOCIATING_AUTHENTICATING, + + /* the association procedure has successfully authentcated + * and is sending association request + */ + IEEE80211_ASSOCIATING_AUTHENTICATED, + + /* the link is ok. the card associated to a BSS or linked + * to a ibss cell or acting as an AP and creating the bss + */ + IEEE80211_LINKED, + + /* same as LINKED, but the driver shall apply RX filter + * rules as we are in NO_LINK mode. As the card is still + * logically linked, but it is doing a syncro site survey + * then it will be back to LINKED state. + */ + IEEE80211_LINKED_SCANNING, + +}; +#else +enum ieee80211_state { + IEEE80211_UNINITIALIZED = 0, + IEEE80211_INITIALIZED, + IEEE80211_ASSOCIATING, + IEEE80211_ASSOCIATED, + IEEE80211_AUTHENTICATING, + IEEE80211_AUTHENTICATED, + IEEE80211_SHUTDOWN +}; +#endif + +#define DEFAULT_MAX_SCAN_AGE (15 * HZ) +#define DEFAULT_FTS 2346 + +#define CFG_IEEE80211_RESERVE_FCS (1<<0) +#define CFG_IEEE80211_COMPUTE_FCS (1<<1) +#define CFG_IEEE80211_RTS (1<<2) + +#define IEEE80211_24GHZ_MIN_CHANNEL 1 +#define IEEE80211_24GHZ_MAX_CHANNEL 14 +#define IEEE80211_24GHZ_CHANNELS (IEEE80211_24GHZ_MAX_CHANNEL - \ + IEEE80211_24GHZ_MIN_CHANNEL + 1) + +#define IEEE80211_52GHZ_MIN_CHANNEL 34 +#define IEEE80211_52GHZ_MAX_CHANNEL 165 +#define IEEE80211_52GHZ_CHANNELS (IEEE80211_52GHZ_MAX_CHANNEL - \ + IEEE80211_52GHZ_MIN_CHANNEL + 1) + +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,11)) +extern inline int is_multicast_ether_addr(const u8 *addr) +{ + return ((addr[0] != 0xff) && (0x01 & addr[0])); +} +#endif + +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,13)) +extern inline int is_broadcast_ether_addr(const u8 *addr) +{ + return ((addr[0] == 0xff) && (addr[1] == 0xff) && (addr[2] == 0xff) && \ + (addr[3] == 0xff) && (addr[4] == 0xff) && (addr[5] == 0xff)); +} +#endif + +typedef struct tx_pending_t{ + int frag; + struct ieee80211_txb *txb; +}tx_pending_t; + +typedef struct _bandwidth_autoswitch +{ + long threshold_20Mhzto40Mhz; + long threshold_40Mhzto20Mhz; + bool bforced_tx20Mhz; + bool bautoswitch_enable; +}bandwidth_autoswitch,*pbandwidth_autoswitch; + + +//added by amy for order + +#define REORDER_WIN_SIZE 128 +#define REORDER_ENTRY_NUM 128 +typedef struct _RX_REORDER_ENTRY +{ + struct list_head List; + u16 SeqNum; + struct ieee80211_rxb* prxb; +} RX_REORDER_ENTRY, *PRX_REORDER_ENTRY; +//added by amy for order +typedef enum _Fsync_State{ + Default_Fsync, + HW_Fsync, + SW_Fsync +}Fsync_State; + +// Power save mode configured. +typedef enum _RT_PS_MODE +{ + eActive, // Active/Continuous access. + eMaxPs, // Max power save mode. + eFastPs // Fast power save mode. +}RT_PS_MODE; + +typedef enum _IPS_CALLBACK_FUNCION +{ + IPS_CALLBACK_NONE = 0, + IPS_CALLBACK_MGNT_LINK_REQUEST = 1, + IPS_CALLBACK_JOIN_REQUEST = 2, +}IPS_CALLBACK_FUNCION; + +typedef enum _RT_JOIN_ACTION{ + RT_JOIN_INFRA = 1, + RT_JOIN_IBSS = 2, + RT_START_IBSS = 3, + RT_NO_ACTION = 4, +}RT_JOIN_ACTION; + +typedef struct _IbssParms{ + u16 atimWin; +}IbssParms, *PIbssParms; +#define MAX_NUM_RATES 264 // Max num of support rates element: 8, Max num of ext. support rate: 255. 061122, by rcnjko. + +// RF state. +typedef enum _RT_RF_POWER_STATE +{ + eRfOn, + eRfSleep, + eRfOff +}RT_RF_POWER_STATE; + +typedef struct _RT_POWER_SAVE_CONTROL +{ + + // + // Inactive Power Save(IPS) : Disable RF when disconnected + // + bool bInactivePs; + bool bIPSModeBackup; + bool bHaltAdapterClkRQ; + bool bSwRfProcessing; + RT_RF_POWER_STATE eInactivePowerState; +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + struct work_struct InactivePsWorkItem; +#else + struct tq_struct InactivePsWorkItem; +#endif + struct timer_list InactivePsTimer; + + // Return point for join action + IPS_CALLBACK_FUNCION ReturnPoint; + + // Recored Parameters for rescheduled JoinRequest + bool bTmpBssDesc; + RT_JOIN_ACTION tmpJoinAction; + struct ieee80211_network tmpBssDesc; + + // Recored Parameters for rescheduled MgntLinkRequest + bool bTmpScanOnly; + bool bTmpActiveScan; + bool bTmpFilterHiddenAP; + bool bTmpUpdateParms; + u8 tmpSsidBuf[33]; + OCTET_STRING tmpSsid2Scan; + bool bTmpSsid2Scan; + u8 tmpNetworkType; + u8 tmpChannelNumber; + u16 tmpBcnPeriod; + u8 tmpDtimPeriod; + u16 tmpmCap; + OCTET_STRING tmpSuppRateSet; + u8 tmpSuppRateBuf[MAX_NUM_RATES]; + bool bTmpSuppRate; + IbssParms tmpIbpm; + bool bTmpIbpm; + + // + // Leisre Poswer Save : Disable RF if connected but traffic is not busy + // + bool bLeisurePs; + u32 PowerProfile; + u8 LpsIdleCount; + u8 RegMaxLPSAwakeIntvl; + u8 LPSAwakeIntvl; + + //RF OFF Level + u32 CurPsLevel; + u32 RegRfPsLevel; + + //Fw Control LPS + bool bFwCtrlLPS; + u8 FWCtrlPSMode; + + //2009.01.01 added by tynli + // Record if there is a link request in IPS RF off progress. + bool LinkReqInIPSRFOffPgs; + // To make sure that connect info should be executed, so we set the bit to filter the link info which comes after the connect info. + bool BufConnectinfoBefore; + +}RT_POWER_SAVE_CONTROL,*PRT_POWER_SAVE_CONTROL; + +typedef u32 RT_RF_CHANGE_SOURCE; +#define RF_CHANGE_BY_SW BIT31 +#define RF_CHANGE_BY_HW BIT30 +#define RF_CHANGE_BY_PS BIT29 +#define RF_CHANGE_BY_IPS BIT28 +#define RF_CHANGE_BY_INIT 0 // Do not change the RFOff reason. Defined by Bruce, 2008-01-17. + +#ifdef ENABLE_DOT11D +typedef enum +{ + COUNTRY_CODE_FCC = 0, + COUNTRY_CODE_IC = 1, + COUNTRY_CODE_ETSI = 2, + COUNTRY_CODE_SPAIN = 3, + COUNTRY_CODE_FRANCE = 4, + COUNTRY_CODE_MKK = 5, + COUNTRY_CODE_MKK1 = 6, + COUNTRY_CODE_ISRAEL = 7, + COUNTRY_CODE_TELEC, + COUNTRY_CODE_MIC, + COUNTRY_CODE_GLOBAL_DOMAIN +}country_code_type_t; +#endif + // Firmware realted CMD IO. +typedef enum _FW_CMD_IO_TYPE{ + FW_CMD_DIG_ENABLE = 0, // For DIG DM + FW_CMD_DIG_DISABLE = 1, + FW_CMD_DIG_HALT = 2, + FW_CMD_DIG_RESUME = 3, + FW_CMD_HIGH_PWR_ENABLE = 4, // For High Power DM + FW_CMD_HIGH_PWR_DISABLE = 5, + FW_CMD_RA_RESET = 6, // For Rate adaptive DM + FW_CMD_RA_ACTIVE= 7, + FW_CMD_RA_REFRESH_N= 8, + FW_CMD_RA_REFRESH_BG= 9, + FW_CMD_IQK_ENABLE = 10, // For FW supported IQK + FW_CMD_TXPWR_TRACK_ENABLE = 11, // Tx power tracking switch + FW_CMD_TXPWR_TRACK_DISABLE = 12, // Tx power tracking switch + FW_CMD_PAUSE_DM_BY_SCAN = 13, + FW_CMD_RESUME_DM_BY_SCAN = 14, + FW_CMD_MID_HIGH_PWR_ENABLE = 15, + FW_CMD_LPS_ENTER = 16, // Indifate firmware that driver enters LPS, For PS-Poll hardware bug + FW_CMD_LPS_LEAVE = 17, // Indicate firmware that driver leave LPS, 2009/1/4, by Emily +}FW_CMD_IO_TYPE,*PFW_CMD_IO_TYPE; +#define RT_MAX_LD_SLOT_NUM 10 +typedef struct _RT_LINK_DETECT_T{ + + u32 NumRecvBcnInPeriod; + u32 NumRecvDataInPeriod; + + u32 RxBcnNum[RT_MAX_LD_SLOT_NUM]; // number of Rx beacon / CheckForHang_period to determine link status + u32 RxDataNum[RT_MAX_LD_SLOT_NUM]; // number of Rx data / CheckForHang_period to determine link status + u16 SlotNum; // number of CheckForHang period to determine link status + u16 SlotIndex; + + u32 NumTxOkInPeriod; + u32 NumRxOkInPeriod; + bool bBusyTraffic; +}RT_LINK_DETECT_T, *PRT_LINK_DETECT_T; + + +struct ieee80211_device { + struct net_device *dev; + struct ieee80211_security sec; + + //hw security related +// u8 hwsec_support; //support? + u8 hwsec_active; //hw security active. + bool is_silent_reset; + bool is_roaming; + bool ieee_up; + //added by amy + bool bSupportRemoteWakeUp; + RT_PS_MODE dot11PowerSaveMode; // Power save mode configured. + bool actscanning; + //added by amy 090313 + bool be_scan_inprogress; + bool beinretry; + RT_RF_POWER_STATE eRFPowerState; + RT_RF_CHANGE_SOURCE RfOffReason; + bool is_set_key; + //11n spec related I wonder if These info structure need to be moved out of ieee80211_device + + //11n HT below + PRT_HIGH_THROUGHPUT pHTInfo; + //struct timer_list SwBwTimer; +// spinlock_t chnlop_spinlock; + spinlock_t bw_spinlock; + + spinlock_t reorder_spinlock; + // for HT operation rate set. we use this one for HT data rate to seperate different descriptors + //the way fill this is the same as in the IE + u8 Regdot11HTOperationalRateSet[16]; //use RATR format + u8 dot11HTOperationalRateSet[16]; //use RATR format + u8 RegHTSuppRateSet[16]; + u8 HTCurrentOperaRate; + u8 HTHighestOperaRate; + //wb added for rate operation mode to firmware + u8 bTxDisableRateFallBack; + u8 bTxUseDriverAssingedRate; + atomic_t atm_chnlop; + atomic_t atm_swbw; +// u8 HTHighestOperaRate; +// u8 HTCurrentOperaRate; + + // 802.11e and WMM Traffic Stream Info (TX) + struct list_head Tx_TS_Admit_List; + struct list_head Tx_TS_Pending_List; + struct list_head Tx_TS_Unused_List; + TX_TS_RECORD TxTsRecord[TOTAL_TS_NUM]; + // 802.11e and WMM Traffic Stream Info (RX) + struct list_head Rx_TS_Admit_List; + struct list_head Rx_TS_Pending_List; + struct list_head Rx_TS_Unused_List; + RX_TS_RECORD RxTsRecord[TOTAL_TS_NUM]; +//#ifdef TO_DO_LIST + RX_REORDER_ENTRY RxReorderEntry[128]; + struct list_head RxReorder_Unused_List; +//#endif + // Qos related. Added by Annie, 2005-11-01. +// PSTA_QOS pStaQos; + u8 ForcedPriority; // Force per-packet priority 1~7. (default: 0, not to force it.) + + + /* Bookkeeping structures */ + struct net_device_stats stats; + struct ieee80211_stats ieee_stats; + struct ieee80211_softmac_stats softmac_stats; + + /* Probe / Beacon management */ + struct list_head network_free_list; + struct list_head network_list; + struct ieee80211_network *networks; + int scans; + int scan_age; + + int iw_mode; /* operating mode (IW_MODE_*) */ + struct iw_spy_data spy_data; + + spinlock_t lock; + spinlock_t wpax_suitlist_lock; + + int tx_headroom; /* Set to size of any additional room needed at front + * of allocated Tx SKBs */ + u32 config; + + /* WEP and other encryption related settings at the device level */ + int open_wep; /* Set to 1 to allow unencrypted frames */ + int auth_mode; + int reset_on_keychange; /* Set to 1 if the HW needs to be reset on + * WEP key changes */ + + /* If the host performs {en,de}cryption, then set to 1 */ + int host_encrypt; + int host_encrypt_msdu; + int host_decrypt; + /* host performs multicast decryption */ + int host_mc_decrypt; + + /* host should strip IV and ICV from protected frames */ + /* meaningful only when hardware decryption is being used */ + int host_strip_iv_icv; + + int host_open_frag; + int host_build_iv; + int ieee802_1x; /* is IEEE 802.1X used */ + + /* WPA data */ + bool bHalfWirelessN24GMode; + int wpa_enabled; + int drop_unencrypted; + int tkip_countermeasures; + int privacy_invoked; + size_t wpa_ie_len; + u8 *wpa_ie; + u8 ap_mac_addr[6]; + u16 pairwise_key_type; + u16 group_key_type; + struct list_head crypt_deinit_list; + struct ieee80211_crypt_data *crypt[WEP_KEYS]; + int tx_keyidx; /* default TX key index (crypt[tx_keyidx]) */ + struct timer_list crypt_deinit_timer; + int crypt_quiesced; + + int bcrx_sta_key; /* use individual keys to override default keys even + * with RX of broad/multicast frames */ + + /* Fragmentation structures */ + // each streaming contain a entry + struct ieee80211_frag_entry frag_cache[17][IEEE80211_FRAG_CACHE_LEN]; + unsigned int frag_next_idx[17]; + u16 fts; /* Fragmentation Threshold */ +#define DEFAULT_RTS_THRESHOLD 2346U +#define MIN_RTS_THRESHOLD 1 +#define MAX_RTS_THRESHOLD 2346U + u16 rts; /* RTS threshold */ + + /* Association info */ + u8 bssid[ETH_ALEN]; + + /* This stores infos for the current network. + * Either the network we are associated in INFRASTRUCTURE + * or the network that we are creating in MASTER mode. + * ad-hoc is a mixture ;-). + * Note that in infrastructure mode, even when not associated, + * fields bssid and essid may be valid (if wpa_set and essid_set + * are true) as thy carry the value set by the user via iwconfig + */ + struct ieee80211_network current_network; + + enum ieee80211_state state; + + int short_slot; + int reg_mode; + int mode; /* A, B, G */ + int modulation; /* CCK, OFDM */ + int freq_band; /* 2.4Ghz, 5.2Ghz, Mixed */ + int abg_true; /* ABG flag */ + + /* used for forcing the ibss workqueue to terminate + * without wait for the syncro scan to terminate + */ + short sync_scan_hurryup; + u16 scan_watch_dog; + int perfect_rssi; + int worst_rssi; + + u16 prev_seq_ctl; /* used to drop duplicate frames */ + + /* map of allowed channels. 0 is dummy */ + // FIXME: remeber to default to a basic channel plan depending of the PHY type +#ifdef ENABLE_DOT11D + void* pDot11dInfo; + bool bGlobalDomain; +#else + int channel_map[MAX_CHANNEL_NUMBER+1]; +#endif + int rate; /* current rate */ + int basic_rate; + //FIXME: pleace callback, see if redundant with softmac_features + short active_scan; + + /* this contains flags for selectively enable softmac support */ + u16 softmac_features; + + /* if the sequence control field is not filled by HW */ + u16 seq_ctrl[5]; + + /* association procedure transaction sequence number */ + u16 associate_seq; + + /* AID for RTXed association responses */ + u16 assoc_id; + + /* power save mode related*/ + u8 ack_tx_to_ieee; + short ps; + short sta_sleep; + int ps_timeout; + int ps_period; + struct tasklet_struct ps_task; + u32 ps_th; + u32 ps_tl; + + short raw_tx; + /* used if IEEE_SOFTMAC_TX_QUEUE is set */ + short queue_stop; + short scanning; + short proto_started; + + struct semaphore wx_sem; + struct semaphore scan_sem; + + spinlock_t mgmt_tx_lock; + spinlock_t beacon_lock; + + short beacon_txing; + + short wap_set; + short ssid_set; + + u8 wpax_type_set; //{added by David, 2006.9.28} + u32 wpax_type_notify; //{added by David, 2006.9.26} + + /* QoS related flag */ + char init_wmmparam_flag; + /* set on initialization */ + u8 qos_support; + + /* for discarding duplicated packets in IBSS */ + struct list_head ibss_mac_hash[IEEE_IBSS_MAC_HASH_SIZE]; + + /* for discarding duplicated packets in BSS */ + u16 last_rxseq_num[17]; /* rx seq previous per-tid */ + u16 last_rxfrag_num[17];/* tx frag previous per-tid */ + unsigned long last_packet_time[17]; + + /* for PS mode */ + unsigned long last_rx_ps_time; + + /* used if IEEE_SOFTMAC_SINGLE_QUEUE is set */ + struct sk_buff *mgmt_queue_ring[MGMT_QUEUE_NUM]; + int mgmt_queue_head; + int mgmt_queue_tail; +//{ added for rtl819x +#define IEEE80211_QUEUE_LIMIT 128 + u8 AsocRetryCount; + unsigned int hw_header; + struct sk_buff_head skb_waitQ[MAX_QUEUE_SIZE]; + struct sk_buff_head skb_aggQ[MAX_QUEUE_SIZE]; + struct sk_buff_head skb_drv_aggQ[MAX_QUEUE_SIZE]; + u32 sta_edca_param[4]; + bool aggregation; + // Enable/Disable Rx immediate BA capability. + bool enable_rx_imm_BA; + bool bibsscoordinator; + + //+by amy for DM ,080515 + //Dynamic Tx power for near/far range enable/Disable , by amy , 2008-05-15 + bool bdynamic_txpower_enable; + + bool bCTSToSelfEnable; + u8 CTSToSelfTH; + + u32 fsync_time_interval; + u32 fsync_rate_bitmap; + u8 fsync_rssi_threshold; + bool bfsync_enable; + + u8 fsync_multiple_timeinterval; // FsyncMultipleTimeInterval * FsyncTimeInterval + u32 fsync_firstdiff_ratethreshold; // low threshold + u32 fsync_seconddiff_ratethreshold; // decrease threshold + Fsync_State fsync_state; + bool bis_any_nonbepkts; + //20Mhz 40Mhz AutoSwitch Threshold + bandwidth_autoswitch bandwidth_auto_switch; + //for txpower tracking + bool FwRWRF; + + //added by amy for AP roaming + RT_LINK_DETECT_T LinkDetectInfo; + //added by amy for ps + RT_POWER_SAVE_CONTROL PowerSaveControl; +//} + /* used if IEEE_SOFTMAC_TX_QUEUE is set */ + struct tx_pending_t tx_pending; + + /* used if IEEE_SOFTMAC_ASSOCIATE is set */ + struct timer_list associate_timer; + + /* used if IEEE_SOFTMAC_BEACONS is set */ + struct timer_list beacon_timer; +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + struct work_struct associate_complete_wq; + struct work_struct associate_procedure_wq; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + struct delayed_work softmac_scan_wq; + struct delayed_work associate_retry_wq; + struct delayed_work start_ibss_wq; + struct delayed_work hw_wakeup_wq; + struct delayed_work hw_sleep_wq; + struct delayed_work link_change_wq; +#else + struct work_struct softmac_scan_wq; + struct work_struct associate_retry_wq; + struct work_struct start_ibss_wq; + struct work_struct hw_wakeup_wq; + struct work_struct hw_sleep_wq; + struct work_struct link_change_wq; +#endif + struct work_struct wx_sync_scan_wq; + struct workqueue_struct *wq; +#else + /* used for periodly scan */ + struct timer_list scan_timer; + + struct tq_struct associate_complete_wq; + struct tq_struct associate_retry_wq; + struct tq_struct start_ibss_wq; + struct tq_struct associate_procedure_wq; + struct tq_struct softmac_scan_wq; + struct tq_struct wx_sync_scan_wq; + struct tq_struct hw_wakeup_wq; + struct tq_struct hw_sleep_wq; + struct tq_struct link_change_wq; + +#endif + // Qos related. Added by Annie, 2005-11-01. + //STA_QOS StaQos; + + //u32 STA_EDCA_PARAM[4]; + //CHANNEL_ACCESS_SETTING ChannelAccessSetting; + + + /* Callback functions */ + void (*set_security)(struct net_device *dev, + struct ieee80211_security *sec); + + /* Used to TX data frame by using txb structs. + * this is not used if in the softmac_features + * is set the flag IEEE_SOFTMAC_TX_QUEUE + */ + int (*hard_start_xmit)(struct ieee80211_txb *txb, + struct net_device *dev); + + int (*reset_port)(struct net_device *dev); + int (*is_queue_full) (struct net_device * dev, int pri); + + int (*handle_management) (struct net_device * dev, + struct ieee80211_network * network, u16 type); + int (*is_qos_active) (struct net_device *dev, struct sk_buff *skb); + + /* Softmac-generated frames (mamagement) are TXed via this + * callback if the flag IEEE_SOFTMAC_SINGLE_QUEUE is + * not set. As some cards may have different HW queues that + * one might want to use for data and management frames + * the option to have two callbacks might be useful. + * This fucntion can't sleep. + */ + int (*softmac_hard_start_xmit)(struct sk_buff *skb, + struct net_device *dev); + + /* used instead of hard_start_xmit (not softmac_hard_start_xmit) + * if the IEEE_SOFTMAC_TX_QUEUE feature is used to TX data + * frames. I the option IEEE_SOFTMAC_SINGLE_QUEUE is also set + * then also management frames are sent via this callback. + * This function can't sleep. + */ + void (*softmac_data_hard_start_xmit)(struct sk_buff *skb, + struct net_device *dev,int rate); + + /* stops the HW queue for DATA frames. Useful to avoid + * waste time to TX data frame when we are reassociating + * This function can sleep. + */ + void (*data_hard_stop)(struct net_device *dev); + + /* OK this is complementar to data_poll_hard_stop */ + void (*data_hard_resume)(struct net_device *dev); + + /* ask to the driver to retune the radio . + * This function can sleep. the driver should ensure + * the radio has been swithced before return. + */ + void (*set_chan)(struct net_device *dev,short ch); + + /* These are not used if the ieee stack takes care of + * scanning (IEEE_SOFTMAC_SCAN feature set). + * In this case only the set_chan is used. + * + * The syncro version is similar to the start_scan but + * does not return until all channels has been scanned. + * this is called in user context and should sleep, + * it is called in a work_queue when swithcing to ad-hoc mode + * or in behalf of iwlist scan when the card is associated + * and root user ask for a scan. + * the fucntion stop_scan should stop both the syncro and + * background scanning and can sleep. + * The fucntion start_scan should initiate the background + * scanning and can't sleep. + */ + void (*scan_syncro)(struct net_device *dev); + void (*start_scan)(struct net_device *dev); + void (*stop_scan)(struct net_device *dev); + + /* indicate the driver that the link state is changed + * for example it may indicate the card is associated now. + * Driver might be interested in this to apply RX filter + * rules or simply light the LINK led + */ + void (*link_change)(struct net_device *dev); + + /* these two function indicates to the HW when to start + * and stop to send beacons. This is used when the + * IEEE_SOFTMAC_BEACONS is not set. For now the + * stop_send_bacons is NOT guaranteed to be called only + * after start_send_beacons. + */ + void (*start_send_beacons) (struct net_device *dev); + void (*stop_send_beacons) (struct net_device *dev); + + /* power save mode related */ + void (*sta_wake_up) (struct net_device *dev); +// void (*ps_request_tx_ack) (struct net_device *dev); + void (*enter_sleep_state) (struct net_device *dev, u32 th, u32 tl); + short (*ps_is_queue_empty) (struct net_device *dev); +#if 0 + /* Typical STA methods */ + int (*handle_auth) (struct net_device * dev, + struct ieee80211_auth * auth); + int (*handle_deauth) (struct net_device * dev, + struct ieee80211_deauth * auth); + int (*handle_action) (struct net_device * dev, + struct ieee80211_action * action, + struct ieee80211_rx_stats * stats); + int (*handle_disassoc) (struct net_device * dev, + struct ieee80211_disassoc * assoc); +#endif + int (*handle_beacon) (struct net_device * dev, struct ieee80211_beacon * beacon, struct ieee80211_network * network); +#if 0 + int (*handle_probe_response) (struct net_device * dev, + struct ieee80211_probe_response * resp, + struct ieee80211_network * network); + int (*handle_probe_request) (struct net_device * dev, + struct ieee80211_probe_request * req, + struct ieee80211_rx_stats * stats); +#endif + int (*handle_assoc_response) (struct net_device * dev, struct ieee80211_assoc_response_frame * resp, struct ieee80211_network * network); + +#if 0 + /* Typical AP methods */ + int (*handle_assoc_request) (struct net_device * dev); + int (*handle_reassoc_request) (struct net_device * dev, + struct ieee80211_reassoc_request * req); +#endif + + /* check whether Tx hw resouce available */ + short (*check_nic_enough_desc)(struct net_device *dev, int queue_index); + //added by wb for HT related +// void (*SwChnlByTimerHandler)(struct net_device *dev, int channel); + void (*SetBWModeHandler)(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset); +// void (*UpdateHalRATRTableHandler)(struct net_device* dev, u8* pMcsRate); + bool (*GetNmodeSupportBySecCfg)(struct net_device* dev); + void (*SetWirelessMode)(struct net_device* dev, u8 wireless_mode); + bool (*GetHalfNmodeSupportByAPsHandler)(struct net_device* dev); + bool (*is_ap_in_wep_tkip)(struct net_device* dev); + void (*InitialGainHandler)(struct net_device *dev, u8 Operation); + bool (*SetFwCmdHandler)(struct net_device *dev, FW_CMD_IO_TYPE FwCmdIO); + void (*LedControlHandler)(struct net_device * dev, LED_CTL_MODE LedAction); + /* This must be the last item so that it points to the data + * allocated beyond this structure by alloc_ieee80211 */ + u8 priv[0]; +}; + +#define IEEE_A (1<<0) +#define IEEE_B (1<<1) +#define IEEE_G (1<<2) +#define IEEE_N_24G (1<<4) +#define IEEE_N_5G (1<<5) +#define IEEE_MODE_MASK (IEEE_A|IEEE_B|IEEE_G) + +/* Generate a 802.11 header */ + +/* Uses the channel change callback directly + * instead of [start/stop] scan callbacks + */ +#define IEEE_SOFTMAC_SCAN (1<<2) + +/* Perform authentication and association handshake */ +#define IEEE_SOFTMAC_ASSOCIATE (1<<3) + +/* Generate probe requests */ +#define IEEE_SOFTMAC_PROBERQ (1<<4) + +/* Generate respones to probe requests */ +#define IEEE_SOFTMAC_PROBERS (1<<5) + +/* The ieee802.11 stack will manages the netif queue + * wake/stop for the driver, taking care of 802.11 + * fragmentation. See softmac.c for details. */ +#define IEEE_SOFTMAC_TX_QUEUE (1<<7) + +/* Uses only the softmac_data_hard_start_xmit + * even for TX management frames. + */ +#define IEEE_SOFTMAC_SINGLE_QUEUE (1<<8) + +/* Generate beacons. The stack will enqueue beacons + * to the card + */ +#define IEEE_SOFTMAC_BEACONS (1<<6) + +static inline void *ieee80211_priv(struct net_device *dev) +{ +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + return ((struct ieee80211_device *)netdev_priv(dev))->priv; +#else + return ((struct ieee80211_device *)dev->priv)->priv; +#endif +} + +extern inline int ieee80211_is_empty_essid(const char *essid, int essid_len) +{ + /* Single white space is for Linksys APs */ + if (essid_len == 1 && essid[0] == ' ') + return 1; + + /* Otherwise, if the entire essid is 0, we assume it is hidden */ + while (essid_len) { + essid_len--; + if (essid[essid_len] != '\0') + return 0; + } + + return 1; +} + +extern inline int ieee80211_is_valid_mode(struct ieee80211_device *ieee, int mode) +{ + /* + * It is possible for both access points and our device to support + * combinations of modes, so as long as there is one valid combination + * of ap/device supported modes, then return success + * + */ + if ((mode & IEEE_A) && + (ieee->modulation & IEEE80211_OFDM_MODULATION) && + (ieee->freq_band & IEEE80211_52GHZ_BAND)) + return 1; + + if ((mode & IEEE_G) && + (ieee->modulation & IEEE80211_OFDM_MODULATION) && + (ieee->freq_band & IEEE80211_24GHZ_BAND)) + return 1; + + if ((mode & IEEE_B) && + (ieee->modulation & IEEE80211_CCK_MODULATION) && + (ieee->freq_band & IEEE80211_24GHZ_BAND)) + return 1; + + return 0; +} + +extern inline int ieee80211_get_hdrlen(u16 fc) +{ + int hdrlen = IEEE80211_3ADDR_LEN; + + switch (WLAN_FC_GET_TYPE(fc)) { + case IEEE80211_FTYPE_DATA: + if ((fc & IEEE80211_FCTL_FROMDS) && (fc & IEEE80211_FCTL_TODS)) + hdrlen = IEEE80211_4ADDR_LEN; /* Addr4 */ + if(IEEE80211_QOS_HAS_SEQ(fc)) + hdrlen += 2; /* QOS ctrl*/ + break; + case IEEE80211_FTYPE_CTL: + switch (WLAN_FC_GET_STYPE(fc)) { + case IEEE80211_STYPE_CTS: + case IEEE80211_STYPE_ACK: + hdrlen = IEEE80211_1ADDR_LEN; + break; + default: + hdrlen = IEEE80211_2ADDR_LEN; + break; + } + break; + } + + return hdrlen; +} + +static inline u8 *ieee80211_get_payload(struct ieee80211_hdr *hdr) +{ + switch (ieee80211_get_hdrlen(le16_to_cpu(hdr->frame_ctl))) { + case IEEE80211_1ADDR_LEN: + return ((struct ieee80211_hdr_1addr *)hdr)->payload; + case IEEE80211_2ADDR_LEN: + return ((struct ieee80211_hdr_2addr *)hdr)->payload; + case IEEE80211_3ADDR_LEN: + return ((struct ieee80211_hdr_3addr *)hdr)->payload; + case IEEE80211_4ADDR_LEN: + return ((struct ieee80211_hdr_4addr *)hdr)->payload; + } + return NULL; +} + +static inline int ieee80211_is_ofdm_rate(u8 rate) +{ + switch (rate & ~IEEE80211_BASIC_RATE_MASK) { + case IEEE80211_OFDM_RATE_6MB: + case IEEE80211_OFDM_RATE_9MB: + case IEEE80211_OFDM_RATE_12MB: + case IEEE80211_OFDM_RATE_18MB: + case IEEE80211_OFDM_RATE_24MB: + case IEEE80211_OFDM_RATE_36MB: + case IEEE80211_OFDM_RATE_48MB: + case IEEE80211_OFDM_RATE_54MB: + return 1; + } + return 0; +} + +static inline int ieee80211_is_cck_rate(u8 rate) +{ + switch (rate & ~IEEE80211_BASIC_RATE_MASK) { + case IEEE80211_CCK_RATE_1MB: + case IEEE80211_CCK_RATE_2MB: + case IEEE80211_CCK_RATE_5MB: + case IEEE80211_CCK_RATE_11MB: + return 1; + } + return 0; +} + + +/* ieee80211.c */ +extern void free_ieee80211(struct net_device *dev); +extern struct net_device *alloc_ieee80211(int sizeof_priv); + +extern int ieee80211_set_encryption(struct ieee80211_device *ieee); + +/* ieee80211_tx.c */ + +extern int ieee80211_encrypt_fragment( + struct ieee80211_device *ieee, + struct sk_buff *frag, + int hdr_len); + +extern int ieee80211_xmit(struct sk_buff *skb, + struct net_device *dev); +extern void ieee80211_txb_free(struct ieee80211_txb *); + + +/* ieee80211_rx.c */ +extern int ieee80211_rx(struct ieee80211_device *ieee, struct sk_buff *skb, + struct ieee80211_rx_stats *rx_stats); +extern void ieee80211_rx_mgt(struct ieee80211_device *ieee, + struct ieee80211_hdr_4addr *header, + struct ieee80211_rx_stats *stats); + +/* ieee80211_wx.c */ +extern int ieee80211_wx_get_scan(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data *wrqu, char *key); +extern int ieee80211_wx_set_encode(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data *wrqu, char *key); +extern int ieee80211_wx_get_encode(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data *wrqu, char *key); +#if WIRELESS_EXT >= 18 +extern int ieee80211_wx_get_encode_ext(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data* wrqu, char *extra); +extern int ieee80211_wx_set_encode_ext(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data* wrqu, char *extra); +extern int ieee80211_wx_set_auth(struct ieee80211_device *ieee, + struct iw_request_info *info, + struct iw_param *data, char *extra); +extern int ieee80211_wx_set_mlme(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); +#endif +extern int ieee80211_wx_set_gen_ie(struct ieee80211_device *ieee, u8 *ie, size_t len); + +/* ieee80211_softmac.c */ +extern short ieee80211_is_54g(struct ieee80211_network net); +extern short ieee80211_is_shortslot(struct ieee80211_network net); +extern int ieee80211_rx_frame_softmac(struct ieee80211_device *ieee, struct sk_buff *skb, + struct ieee80211_rx_stats *rx_stats, u16 type, + u16 stype); +extern void ieee80211_softmac_new_net(struct ieee80211_device *ieee, struct ieee80211_network *net); + +void SendDisassociation(struct ieee80211_device *ieee, u8* asSta, u8 asRsn); +extern void ieee80211_softmac_xmit(struct ieee80211_txb *txb, struct ieee80211_device *ieee); + +extern void ieee80211_stop_send_beacons(struct ieee80211_device *ieee); +extern void notify_wx_assoc_event(struct ieee80211_device *ieee); +extern void ieee80211_softmac_check_all_nets(struct ieee80211_device *ieee); +extern void ieee80211_start_bss(struct ieee80211_device *ieee); +extern void ieee80211_start_master_bss(struct ieee80211_device *ieee); +extern void ieee80211_start_ibss(struct ieee80211_device *ieee); +extern void ieee80211_softmac_init(struct ieee80211_device *ieee); +extern void ieee80211_softmac_free(struct ieee80211_device *ieee); +extern void ieee80211_associate_abort(struct ieee80211_device *ieee); +extern void ieee80211_disassociate(struct ieee80211_device *ieee); +extern void ieee80211_stop_scan(struct ieee80211_device *ieee); +extern void ieee80211_start_scan_syncro(struct ieee80211_device *ieee); +extern void ieee80211_check_all_nets(struct ieee80211_device *ieee); +extern void ieee80211_start_protocol(struct ieee80211_device *ieee); +extern void ieee80211_stop_protocol(struct ieee80211_device *ieee); +extern void ieee80211_softmac_start_protocol(struct ieee80211_device *ieee); +extern void ieee80211_softmac_stop_protocol(struct ieee80211_device *ieee); +extern void ieee80211_reset_queue(struct ieee80211_device *ieee); +extern void ieee80211_wake_queue(struct ieee80211_device *ieee); +extern void ieee80211_stop_queue(struct ieee80211_device *ieee); +extern struct sk_buff *ieee80211_get_beacon(struct ieee80211_device *ieee); +extern void ieee80211_start_send_beacons(struct ieee80211_device *ieee); +extern void ieee80211_stop_send_beacons(struct ieee80211_device *ieee); +extern int ieee80211_wpa_supplicant_ioctl(struct ieee80211_device *ieee, struct iw_point *p); +extern void notify_wx_assoc_event(struct ieee80211_device *ieee); +extern void ieee80211_ps_tx_ack(struct ieee80211_device *ieee, short success); + +extern void softmac_mgmt_xmit(struct sk_buff *skb, struct ieee80211_device *ieee); + +/* ieee80211_crypt_ccmp&tkip&wep.c */ +extern void ieee80211_tkip_null(void); +extern void ieee80211_wep_null(void); +extern void ieee80211_ccmp_null(void); + +/* ieee80211_softmac_wx.c */ + +extern int ieee80211_wx_get_wap(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data *wrqu, char *ext); + +extern int ieee80211_wx_set_wap(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data *awrq, + char *extra); + +extern int ieee80211_wx_get_essid(struct ieee80211_device *ieee, struct iw_request_info *a,union iwreq_data *wrqu,char *b); + +extern int ieee80211_wx_set_rate(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); + +extern int ieee80211_wx_get_rate(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); + +extern int ieee80211_wx_set_mode(struct ieee80211_device *ieee, struct iw_request_info *a, + union iwreq_data *wrqu, char *b); + +extern int ieee80211_wx_set_scan(struct ieee80211_device *ieee, struct iw_request_info *a, + union iwreq_data *wrqu, char *b); + +extern int ieee80211_wx_set_essid(struct ieee80211_device *ieee, + struct iw_request_info *a, + union iwreq_data *wrqu, char *extra); + +extern int ieee80211_wx_get_mode(struct ieee80211_device *ieee, struct iw_request_info *a, + union iwreq_data *wrqu, char *b); + +extern int ieee80211_wx_set_freq(struct ieee80211_device *ieee, struct iw_request_info *a, + union iwreq_data *wrqu, char *b); + +extern int ieee80211_wx_get_freq(struct ieee80211_device *ieee, struct iw_request_info *a, + union iwreq_data *wrqu, char *b); + +//extern void ieee80211_wx_sync_scan_wq(struct ieee80211_device *ieee); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) +extern void ieee80211_wx_sync_scan_wq(struct work_struct *work); +#else + extern void ieee80211_wx_sync_scan_wq(struct ieee80211_device *ieee); +#endif + + +extern int ieee80211_wx_set_rawtx(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); + +extern int ieee80211_wx_get_name(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); + +extern int ieee80211_wx_set_power(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); + +extern int ieee80211_wx_get_power(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); + +extern int ieee80211_wx_set_rts(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); + +extern int ieee80211_wx_get_rts(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); +//HT +#define MAX_RECEIVE_BUFFER_SIZE 9100 // +extern void HTDebugHTCapability(u8* CapIE, u8* TitleString ); +extern void HTDebugHTInfo(u8* InfoIE, u8* TitleString); + +void HTSetConnectBwMode(struct ieee80211_device* ieee, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset); +extern void HTUpdateDefaultSetting(struct ieee80211_device* ieee); +extern void HTConstructCapabilityElement(struct ieee80211_device* ieee, u8* posHTCap, u8* len, u8 isEncrypt); +extern void HTConstructInfoElement(struct ieee80211_device* ieee, u8* posHTInfo, u8* len, u8 isEncrypt); +extern void HTConstructRT2RTAggElement(struct ieee80211_device* ieee, u8* posRT2RTAgg, u8* len); +extern void HTOnAssocRsp(struct ieee80211_device *ieee); +extern void HTInitializeHTInfo(struct ieee80211_device* ieee); +extern void HTInitializeBssDesc(PBSS_HT pBssHT); +extern void HTResetSelfAndSavePeerSetting(struct ieee80211_device* ieee, struct ieee80211_network * pNetwork); +extern void HTUpdateSelfAndPeerSetting(struct ieee80211_device* ieee, struct ieee80211_network * pNetwork); +extern u8 HTGetHighestMCSRate(struct ieee80211_device* ieee, u8* pMCSRateSet, u8* pMCSFilter); +extern u8 MCS_FILTER_ALL[]; +extern u16 MCS_DATA_RATE[2][2][77] ; +extern u8 HTCCheck(struct ieee80211_device* ieee, u8* pFrame); +//extern void HTSetConnectBwModeCallback(unsigned long data); +extern void HTResetIOTSetting(PRT_HIGH_THROUGHPUT pHTInfo); +extern bool IsHTHalfNmodeAPs(struct ieee80211_device* ieee); +extern u16 HTHalfMcsToDataRate(struct ieee80211_device* ieee, u8 nMcsRate); +extern u16 HTMcsToDataRate( struct ieee80211_device* ieee, u8 nMcsRate); +extern u16 TxCountToDataRate( struct ieee80211_device* ieee, u8 nDataRate); +//function in BAPROC.c +extern int ieee80211_rx_ADDBAReq( struct ieee80211_device* ieee, struct sk_buff *skb); +extern int ieee80211_rx_ADDBARsp( struct ieee80211_device* ieee, struct sk_buff *skb); +extern int ieee80211_rx_DELBA(struct ieee80211_device* ieee,struct sk_buff *skb); +extern void TsInitAddBA( struct ieee80211_device* ieee, PTX_TS_RECORD pTS, u8 Policy, u8 bOverwritePending); +extern void TsInitDelBA( struct ieee80211_device* ieee, PTS_COMMON_INFO pTsCommonInfo, TR_SELECT TxRxSelect); +extern void BaSetupTimeOut(unsigned long data); +extern void TxBaInactTimeout(unsigned long data); +extern void RxBaInactTimeout(unsigned long data); +extern void ResetBaEntry( PBA_RECORD pBA); +//function in TS.c +extern bool GetTs( + struct ieee80211_device* ieee, + PTS_COMMON_INFO *ppTS, + u8* Addr, + u8 TID, + TR_SELECT TxRxSelect, //Rx:1, Tx:0 + bool bAddNewTs + ); +extern void TSInitialize(struct ieee80211_device *ieee); +extern void TsStartAddBaProcess(struct ieee80211_device* ieee, PTX_TS_RECORD pTxTS); +extern void RemovePeerTS(struct ieee80211_device* ieee, u8* Addr); +extern void RemoveAllTS(struct ieee80211_device* ieee); +void ieee80211_softmac_scan_syncro(struct ieee80211_device *ieee); + +extern const long ieee80211_wlan_frequencies[]; + +extern inline void ieee80211_increment_scans(struct ieee80211_device *ieee) +{ + ieee->scans++; +} + +extern inline int ieee80211_get_scans(struct ieee80211_device *ieee) +{ + return ieee->scans; +} + +static inline const char *escape_essid(const char *essid, u8 essid_len) { + static char escaped[IW_ESSID_MAX_SIZE * 2 + 1]; + const char *s = essid; + char *d = escaped; + + if (ieee80211_is_empty_essid(essid, essid_len)) { + memcpy(escaped, "<hidden>", sizeof("<hidden>")); + return escaped; + } + + essid_len = min(essid_len, (u8)IW_ESSID_MAX_SIZE); + while (essid_len--) { + if (*s == '\0') { + *d++ = '\\'; + *d++ = '0'; + s++; + } else { + *d++ = *s++; + } + } + *d = '\0'; + return escaped; +} + +/* For the function is more related to hardware setting, it's better to use the + * ieee handler to refer to it. + */ +extern short check_nic_enough_desc(struct net_device *dev, int queue_index); +extern int ieee80211_data_xmit(struct sk_buff *skb, struct net_device *dev); +extern int ieee80211_parse_info_param(struct ieee80211_device *ieee, + struct ieee80211_info_element *info_element, + u16 length, + struct ieee80211_network *network, + struct ieee80211_rx_stats *stats); + +void ieee80211_indicate_packets(struct ieee80211_device *ieee, struct ieee80211_rxb** prxbIndicateArray,u8 index); +#define RT_ASOC_RETRY_LIMIT 5 +#endif /* IEEE80211_H */ diff --git a/drivers/staging/rtl8192su/ieee80211/ieee80211_crypt.c b/drivers/staging/rtl8192su/ieee80211/ieee80211_crypt.c new file mode 100644 index 000000000000..199ee1695ad3 --- /dev/null +++ b/drivers/staging/rtl8192su/ieee80211/ieee80211_crypt.c @@ -0,0 +1,273 @@ +/* + * Host AP crypto routines + * + * Copyright (c) 2002-2003, Jouni Malinen <jkmaline@cc.hut.fi> + * Portions Copyright (C) 2004, Intel Corporation <jketreno@linux.intel.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. See README and COPYING for + * more details. + * + */ + +//#include <linux/config.h> +#include <linux/version.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/slab.h> +#include <asm/string.h> +#include <asm/errno.h> + +#include "ieee80211.h" + +MODULE_AUTHOR("Jouni Malinen"); +MODULE_DESCRIPTION("HostAP crypto"); +MODULE_LICENSE("GPL"); + +struct ieee80211_crypto_alg { + struct list_head list; + struct ieee80211_crypto_ops *ops; +}; + + +struct ieee80211_crypto { + struct list_head algs; + spinlock_t lock; +}; + +static struct ieee80211_crypto *hcrypt; + +void ieee80211_crypt_deinit_entries(struct ieee80211_device *ieee, + int force) +{ + struct list_head *ptr, *n; + struct ieee80211_crypt_data *entry; + + for (ptr = ieee->crypt_deinit_list.next, n = ptr->next; + ptr != &ieee->crypt_deinit_list; ptr = n, n = ptr->next) { + entry = list_entry(ptr, struct ieee80211_crypt_data, list); + + if (atomic_read(&entry->refcnt) != 0 && !force) + continue; + + list_del(ptr); + + if (entry->ops) { + entry->ops->deinit(entry->priv); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) + module_put(entry->ops->owner); +#else + __MOD_DEC_USE_COUNT(entry->ops->owner); +#endif + } + kfree(entry); + } +} + +void ieee80211_crypt_deinit_handler(unsigned long data) +{ + struct ieee80211_device *ieee = (struct ieee80211_device *)data; + unsigned long flags; + + spin_lock_irqsave(&ieee->lock, flags); + ieee80211_crypt_deinit_entries(ieee, 0); + if (!list_empty(&ieee->crypt_deinit_list)) { + printk(KERN_DEBUG "%s: entries remaining in delayed crypt " + "deletion list\n", ieee->dev->name); + ieee->crypt_deinit_timer.expires = jiffies + HZ; + add_timer(&ieee->crypt_deinit_timer); + } + spin_unlock_irqrestore(&ieee->lock, flags); + +} + +void ieee80211_crypt_delayed_deinit(struct ieee80211_device *ieee, + struct ieee80211_crypt_data **crypt) +{ + struct ieee80211_crypt_data *tmp; + unsigned long flags; + + if (*crypt == NULL) + return; + + tmp = *crypt; + *crypt = NULL; + + /* must not run ops->deinit() while there may be pending encrypt or + * decrypt operations. Use a list of delayed deinits to avoid needing + * locking. */ + + spin_lock_irqsave(&ieee->lock, flags); + list_add(&tmp->list, &ieee->crypt_deinit_list); + if (!timer_pending(&ieee->crypt_deinit_timer)) { + ieee->crypt_deinit_timer.expires = jiffies + HZ; + add_timer(&ieee->crypt_deinit_timer); + } + spin_unlock_irqrestore(&ieee->lock, flags); +} + +int ieee80211_register_crypto_ops(struct ieee80211_crypto_ops *ops) +{ + unsigned long flags; + struct ieee80211_crypto_alg *alg; + + if (hcrypt == NULL) + return -1; + + alg = kmalloc(sizeof(*alg), GFP_KERNEL); + if (alg == NULL) + return -ENOMEM; + + memset(alg, 0, sizeof(*alg)); + alg->ops = ops; + + spin_lock_irqsave(&hcrypt->lock, flags); + list_add(&alg->list, &hcrypt->algs); + spin_unlock_irqrestore(&hcrypt->lock, flags); + + printk(KERN_DEBUG "ieee80211_crypt: registered algorithm '%s'\n", + ops->name); + + return 0; +} + +int ieee80211_unregister_crypto_ops(struct ieee80211_crypto_ops *ops) +{ + unsigned long flags; + struct list_head *ptr; + struct ieee80211_crypto_alg *del_alg = NULL; + + if (hcrypt == NULL) + return -1; + + spin_lock_irqsave(&hcrypt->lock, flags); + for (ptr = hcrypt->algs.next; ptr != &hcrypt->algs; ptr = ptr->next) { + struct ieee80211_crypto_alg *alg = + (struct ieee80211_crypto_alg *) ptr; + if (alg->ops == ops) { + list_del(&alg->list); + del_alg = alg; + break; + } + } + spin_unlock_irqrestore(&hcrypt->lock, flags); + + if (del_alg) { + printk(KERN_DEBUG "ieee80211_crypt: unregistered algorithm " + "'%s'\n", ops->name); + kfree(del_alg); + } + + return del_alg ? 0 : -1; +} + + +struct ieee80211_crypto_ops * ieee80211_get_crypto_ops(const char *name) +{ + unsigned long flags; + struct list_head *ptr; + struct ieee80211_crypto_alg *found_alg = NULL; + + if (hcrypt == NULL) + return NULL; + + spin_lock_irqsave(&hcrypt->lock, flags); + for (ptr = hcrypt->algs.next; ptr != &hcrypt->algs; ptr = ptr->next) { + struct ieee80211_crypto_alg *alg = + (struct ieee80211_crypto_alg *) ptr; + if (strcmp(alg->ops->name, name) == 0) { + found_alg = alg; + break; + } + } + spin_unlock_irqrestore(&hcrypt->lock, flags); + + if (found_alg) + return found_alg->ops; + else + return NULL; +} + + +static void * ieee80211_crypt_null_init(int keyidx) { return (void *) 1; } +static void ieee80211_crypt_null_deinit(void *priv) {} + +static struct ieee80211_crypto_ops ieee80211_crypt_null = { + .name = "NULL", + .init = ieee80211_crypt_null_init, + .deinit = ieee80211_crypt_null_deinit, + .encrypt_mpdu = NULL, + .decrypt_mpdu = NULL, + .encrypt_msdu = NULL, + .decrypt_msdu = NULL, + .set_key = NULL, + .get_key = NULL, + .extra_prefix_len = 0, + .extra_postfix_len = 0, + .owner = THIS_MODULE, +}; + + +static int __init ieee80211_crypto_init(void) +{ + int ret = -ENOMEM; + + hcrypt = kmalloc(sizeof(*hcrypt), GFP_KERNEL); + if (!hcrypt) + goto out; + + memset(hcrypt, 0, sizeof(*hcrypt)); + INIT_LIST_HEAD(&hcrypt->algs); + spin_lock_init(&hcrypt->lock); + + ret = ieee80211_register_crypto_ops(&ieee80211_crypt_null); + if (ret < 0) { + kfree(hcrypt); + hcrypt = NULL; + } +out: + return ret; +} + + +static void __exit ieee80211_crypto_deinit(void) +{ + struct list_head *ptr, *n; + + if (hcrypt == NULL) + return; + + for (ptr = hcrypt->algs.next, n = ptr->next; ptr != &hcrypt->algs; + ptr = n, n = ptr->next) { + struct ieee80211_crypto_alg *alg = + (struct ieee80211_crypto_alg *) ptr; + list_del(ptr); + printk(KERN_DEBUG "ieee80211_crypt: unregistered algorithm " + "'%s' (deinit)\n", alg->ops->name); + kfree(alg); + } + + kfree(hcrypt); +} + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) +EXPORT_SYMBOL(ieee80211_crypt_deinit_entries); +EXPORT_SYMBOL(ieee80211_crypt_deinit_handler); +EXPORT_SYMBOL(ieee80211_crypt_delayed_deinit); + +EXPORT_SYMBOL(ieee80211_register_crypto_ops); +EXPORT_SYMBOL(ieee80211_unregister_crypto_ops); +EXPORT_SYMBOL(ieee80211_get_crypto_ops); +#else +EXPORT_SYMBOL_NOVERS(ieee80211_crypt_deinit_entries); +EXPORT_SYMBOL_NOVERS(ieee80211_crypt_deinit_handler); +EXPORT_SYMBOL_NOVERS(ieee80211_crypt_delayed_deinit); + +EXPORT_SYMBOL_NOVERS(ieee80211_register_crypto_ops); +EXPORT_SYMBOL_NOVERS(ieee80211_unregister_crypto_ops); +EXPORT_SYMBOL_NOVERS(ieee80211_get_crypto_ops); +#endif + +module_init(ieee80211_crypto_init); +module_exit(ieee80211_crypto_deinit); diff --git a/drivers/staging/rtl8192su/ieee80211/ieee80211_crypt.h b/drivers/staging/rtl8192su/ieee80211/ieee80211_crypt.h new file mode 100644 index 000000000000..a84df4b76489 --- /dev/null +++ b/drivers/staging/rtl8192su/ieee80211/ieee80211_crypt.h @@ -0,0 +1,93 @@ +/* + * Original code based on Host AP (software wireless LAN access point) driver + * for Intersil Prism2/2.5/3. + * + * Copyright (c) 2001-2002, SSH Communications Security Corp and Jouni Malinen + * <jkmaline@cc.hut.fi> + * Copyright (c) 2002-2003, Jouni Malinen <jkmaline@cc.hut.fi> + * + * Adaption to a generic IEEE 802.11 stack by James Ketrenos + * <jketreno@linux.intel.com> + * + * Copyright (c) 2004, Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. See README and COPYING for + * more details. + */ + +/* + * This file defines the interface to the ieee80211 crypto module. + */ +#ifndef IEEE80211_CRYPT_H +#define IEEE80211_CRYPT_H + +#include <linux/skbuff.h> + +struct ieee80211_crypto_ops { + const char *name; + + /* init new crypto context (e.g., allocate private data space, + * select IV, etc.); returns NULL on failure or pointer to allocated + * private data on success */ + void * (*init)(int keyidx); + + /* deinitialize crypto context and free allocated private data */ + void (*deinit)(void *priv); + + /* encrypt/decrypt return < 0 on error or >= 0 on success. The return + * value from decrypt_mpdu is passed as the keyidx value for + * decrypt_msdu. skb must have enough head and tail room for the + * encryption; if not, error will be returned; these functions are + * called for all MPDUs (i.e., fragments). + */ + int (*encrypt_mpdu)(struct sk_buff *skb, int hdr_len, void *priv); + int (*decrypt_mpdu)(struct sk_buff *skb, int hdr_len, void *priv); + + /* These functions are called for full MSDUs, i.e. full frames. + * These can be NULL if full MSDU operations are not needed. */ + int (*encrypt_msdu)(struct sk_buff *skb, int hdr_len, void *priv); + int (*decrypt_msdu)(struct sk_buff *skb, int keyidx, int hdr_len, + void *priv); + + int (*set_key)(void *key, int len, u8 *seq, void *priv); + int (*get_key)(void *key, int len, u8 *seq, void *priv); + + /* procfs handler for printing out key information and possible + * statistics */ + char * (*print_stats)(char *p, void *priv); + + /* maximum number of bytes added by encryption; encrypt buf is + * allocated with extra_prefix_len bytes, copy of in_buf, and + * extra_postfix_len; encrypt need not use all this space, but + * the result must start at the beginning of the buffer and correct + * length must be returned */ + int extra_prefix_len, extra_postfix_len; + + struct module *owner; +}; + +struct ieee80211_crypt_data { + struct list_head list; /* delayed deletion list */ + struct ieee80211_crypto_ops *ops; + void *priv; + atomic_t refcnt; +}; + +int ieee80211_register_crypto_ops(struct ieee80211_crypto_ops *ops); +int ieee80211_unregister_crypto_ops(struct ieee80211_crypto_ops *ops); +struct ieee80211_crypto_ops * ieee80211_get_crypto_ops(const char *name); +void ieee80211_crypt_deinit_entries(struct ieee80211_device *, int); +void ieee80211_crypt_deinit_handler(unsigned long); +void ieee80211_crypt_delayed_deinit(struct ieee80211_device *ieee, + struct ieee80211_crypt_data **crypt); +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)) +#define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK) +#endif +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,31)) +#define crypto_alloc_tfm crypto_alloc_tfm_rsl +#define crypto_free_tfm crypto_free_tfm_rsl +#endif + +#endif diff --git a/drivers/staging/rtl8192su/ieee80211/ieee80211_crypt_ccmp.c b/drivers/staging/rtl8192su/ieee80211/ieee80211_crypt_ccmp.c new file mode 100644 index 000000000000..a86c26eceb34 --- /dev/null +++ b/drivers/staging/rtl8192su/ieee80211/ieee80211_crypt_ccmp.c @@ -0,0 +1,534 @@ +/* + * Host AP crypt: host-based CCMP encryption implementation for Host AP driver + * + * Copyright (c) 2003-2004, Jouni Malinen <jkmaline@cc.hut.fi> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. See README and COPYING for + * more details. + */ + +//#include <linux/config.h> +#include <linux/version.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/slab.h> +#include <linux/random.h> +#include <linux/skbuff.h> +#include <linux/netdevice.h> +#include <linux/if_ether.h> +#include <linux/if_arp.h> +#include <asm/string.h> +#include <linux/wireless.h> + +#include "ieee80211.h" + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)) +#include "rtl_crypto.h" +#else +#include <linux/crypto.h> +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) + #include <asm/scatterlist.h> +#else + #include <linux/scatterlist.h> +#endif +//#include <asm/scatterlist.h> + +MODULE_AUTHOR("Jouni Malinen"); +MODULE_DESCRIPTION("Host AP crypt: CCMP"); +MODULE_LICENSE("GPL"); + +#ifndef OPENSUSE_SLED +#define OPENSUSE_SLED 0 +#endif + +#define AES_BLOCK_LEN 16 +#define CCMP_HDR_LEN 8 +#define CCMP_MIC_LEN 8 +#define CCMP_TK_LEN 16 +#define CCMP_PN_LEN 6 + +struct ieee80211_ccmp_data { + u8 key[CCMP_TK_LEN]; + int key_set; + + u8 tx_pn[CCMP_PN_LEN]; + u8 rx_pn[CCMP_PN_LEN]; + + u32 dot11RSNAStatsCCMPFormatErrors; + u32 dot11RSNAStatsCCMPReplays; + u32 dot11RSNAStatsCCMPDecryptErrors; + + int key_idx; + + struct crypto_tfm *tfm; + + /* scratch buffers for virt_to_page() (crypto API) */ + u8 tx_b0[AES_BLOCK_LEN], tx_b[AES_BLOCK_LEN], + tx_e[AES_BLOCK_LEN], tx_s0[AES_BLOCK_LEN]; + u8 rx_b0[AES_BLOCK_LEN], rx_b[AES_BLOCK_LEN], rx_a[AES_BLOCK_LEN]; +}; + +void ieee80211_ccmp_aes_encrypt(struct crypto_tfm *tfm, + const u8 pt[16], u8 ct[16]) +{ +#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED)) + struct scatterlist src, dst; + + src.page = virt_to_page(pt); + src.offset = offset_in_page(pt); + src.length = AES_BLOCK_LEN; + + dst.page = virt_to_page(ct); + dst.offset = offset_in_page(ct); + dst.length = AES_BLOCK_LEN; + + crypto_cipher_encrypt(tfm, &dst, &src, AES_BLOCK_LEN); +#else + crypto_cipher_encrypt_one((void*)tfm, ct, pt); +#endif +} + +static void * ieee80211_ccmp_init(int key_idx) +{ + struct ieee80211_ccmp_data *priv; + + priv = kmalloc(sizeof(*priv), GFP_ATOMIC); + if (priv == NULL) + goto fail; + memset(priv, 0, sizeof(*priv)); + priv->key_idx = key_idx; + +#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED)) + priv->tfm = crypto_alloc_tfm("aes", 0); + if (priv->tfm == NULL) { + printk(KERN_DEBUG "ieee80211_crypt_ccmp: could not allocate " + "crypto API aes\n"); + goto fail; + } + #else + priv->tfm = (void*)crypto_alloc_cipher("aes", 0, CRYPTO_ALG_ASYNC); + if (IS_ERR(priv->tfm)) { + printk(KERN_DEBUG "ieee80211_crypt_ccmp: could not allocate " + "crypto API aes\n"); + priv->tfm = NULL; + goto fail; + } + #endif + return priv; + +fail: + if (priv) { + if (priv->tfm) + #if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) + crypto_free_tfm(priv->tfm); + #else + crypto_free_cipher((void*)priv->tfm); + #endif + kfree(priv); + } + + return NULL; +} + + +static void ieee80211_ccmp_deinit(void *priv) +{ + struct ieee80211_ccmp_data *_priv = priv; + if (_priv && _priv->tfm) +#if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) + crypto_free_tfm(_priv->tfm); +#else + crypto_free_cipher((void*)_priv->tfm); +#endif + kfree(priv); +} + + +static inline void xor_block(u8 *b, u8 *a, size_t len) +{ + int i; + for (i = 0; i < len; i++) + b[i] ^= a[i]; +} + + + +static void ccmp_init_blocks(struct crypto_tfm *tfm, + struct ieee80211_hdr_4addr *hdr, + u8 *pn, size_t dlen, u8 *b0, u8 *auth, + u8 *s0) +{ + u8 *pos, qc = 0; + size_t aad_len; + u16 fc; + int a4_included, qc_included; + u8 aad[2 * AES_BLOCK_LEN]; + + fc = le16_to_cpu(hdr->frame_ctl); + a4_included = ((fc & (IEEE80211_FCTL_TODS | IEEE80211_FCTL_FROMDS)) == + (IEEE80211_FCTL_TODS | IEEE80211_FCTL_FROMDS)); + /* + qc_included = ((WLAN_FC_GET_TYPE(fc) == IEEE80211_FTYPE_DATA) && + (WLAN_FC_GET_STYPE(fc) & 0x08)); + */ + // fixed by David :2006.9.6 + qc_included = ((WLAN_FC_GET_TYPE(fc) == IEEE80211_FTYPE_DATA) && + (WLAN_FC_GET_STYPE(fc) & 0x80)); + aad_len = 22; + if (a4_included) + aad_len += 6; + if (qc_included) { + pos = (u8 *) &hdr->addr4; + if (a4_included) + pos += 6; + qc = *pos & 0x0f; + aad_len += 2; + } + /* CCM Initial Block: + * Flag (Include authentication header, M=3 (8-octet MIC), + * L=1 (2-octet Dlen)) + * Nonce: 0x00 | A2 | PN + * Dlen */ + b0[0] = 0x59; + b0[1] = qc; + memcpy(b0 + 2, hdr->addr2, ETH_ALEN); + memcpy(b0 + 8, pn, CCMP_PN_LEN); + b0[14] = (dlen >> 8) & 0xff; + b0[15] = dlen & 0xff; + + /* AAD: + * FC with bits 4..6 and 11..13 masked to zero; 14 is always one + * A1 | A2 | A3 + * SC with bits 4..15 (seq#) masked to zero + * A4 (if present) + * QC (if present) + */ + pos = (u8 *) hdr; + aad[0] = 0; /* aad_len >> 8 */ + aad[1] = aad_len & 0xff; + aad[2] = pos[0] & 0x8f; + aad[3] = pos[1] & 0xc7; + memcpy(aad + 4, hdr->addr1, 3 * ETH_ALEN); + pos = (u8 *) &hdr->seq_ctl; + aad[22] = pos[0] & 0x0f; + aad[23] = 0; /* all bits masked */ + memset(aad + 24, 0, 8); + if (a4_included) + memcpy(aad + 24, hdr->addr4, ETH_ALEN); + if (qc_included) { + aad[a4_included ? 30 : 24] = qc; + /* rest of QC masked */ + } + + /* Start with the first block and AAD */ + ieee80211_ccmp_aes_encrypt(tfm, b0, auth); + xor_block(auth, aad, AES_BLOCK_LEN); + ieee80211_ccmp_aes_encrypt(tfm, auth, auth); + xor_block(auth, &aad[AES_BLOCK_LEN], AES_BLOCK_LEN); + ieee80211_ccmp_aes_encrypt(tfm, auth, auth); + b0[0] &= 0x07; + b0[14] = b0[15] = 0; + ieee80211_ccmp_aes_encrypt(tfm, b0, s0); +} + + + +static int ieee80211_ccmp_encrypt(struct sk_buff *skb, int hdr_len, void *priv) +{ + struct ieee80211_ccmp_data *key = priv; + int data_len, i; + u8 *pos; + struct ieee80211_hdr_4addr *hdr; + cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE); + + if (skb_headroom(skb) < CCMP_HDR_LEN || + skb_tailroom(skb) < CCMP_MIC_LEN || + skb->len < hdr_len) + return -1; + + data_len = skb->len - hdr_len; + pos = skb_push(skb, CCMP_HDR_LEN); + memmove(pos, pos + CCMP_HDR_LEN, hdr_len); + pos += hdr_len; +// mic = skb_put(skb, CCMP_MIC_LEN); + + i = CCMP_PN_LEN - 1; + while (i >= 0) { + key->tx_pn[i]++; + if (key->tx_pn[i] != 0) + break; + i--; + } + + *pos++ = key->tx_pn[5]; + *pos++ = key->tx_pn[4]; + *pos++ = 0; + *pos++ = (key->key_idx << 6) | (1 << 5) /* Ext IV included */; + *pos++ = key->tx_pn[3]; + *pos++ = key->tx_pn[2]; + *pos++ = key->tx_pn[1]; + *pos++ = key->tx_pn[0]; + + + hdr = (struct ieee80211_hdr_4addr *) skb->data; + if (!tcb_desc->bHwSec) + { + int blocks, last, len; + u8 *mic; + u8 *b0 = key->tx_b0; + u8 *b = key->tx_b; + u8 *e = key->tx_e; + u8 *s0 = key->tx_s0; + + //mic is moved to here by john + mic = skb_put(skb, CCMP_MIC_LEN); + + ccmp_init_blocks(key->tfm, hdr, key->tx_pn, data_len, b0, b, s0); + + blocks = (data_len + AES_BLOCK_LEN - 1) / AES_BLOCK_LEN; + last = data_len % AES_BLOCK_LEN; + + for (i = 1; i <= blocks; i++) { + len = (i == blocks && last) ? last : AES_BLOCK_LEN; + /* Authentication */ + xor_block(b, pos, len); + ieee80211_ccmp_aes_encrypt(key->tfm, b, b); + /* Encryption, with counter */ + b0[14] = (i >> 8) & 0xff; + b0[15] = i & 0xff; + ieee80211_ccmp_aes_encrypt(key->tfm, b0, e); + xor_block(pos, e, len); + pos += len; + } + + for (i = 0; i < CCMP_MIC_LEN; i++) + mic[i] = b[i] ^ s0[i]; + } + return 0; +} + + +static int ieee80211_ccmp_decrypt(struct sk_buff *skb, int hdr_len, void *priv) +{ + struct ieee80211_ccmp_data *key = priv; + u8 keyidx, *pos; + struct ieee80211_hdr_4addr *hdr; + cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE); + u8 pn[6]; + + if (skb->len < hdr_len + CCMP_HDR_LEN + CCMP_MIC_LEN) { + key->dot11RSNAStatsCCMPFormatErrors++; + return -1; + } + + hdr = (struct ieee80211_hdr_4addr *) skb->data; + pos = skb->data + hdr_len; + keyidx = pos[3]; + if (!(keyidx & (1 << 5))) { + if (net_ratelimit()) { + printk(KERN_DEBUG "CCMP: received packet without ExtIV" + " flag from " MAC_FMT "\n", MAC_ARG(hdr->addr2)); + } + key->dot11RSNAStatsCCMPFormatErrors++; + return -2; + } + keyidx >>= 6; + if (key->key_idx != keyidx) { + printk(KERN_DEBUG "CCMP: RX tkey->key_idx=%d frame " + "keyidx=%d priv=%p\n", key->key_idx, keyidx, priv); + return -6; + } + if (!key->key_set) { + if (net_ratelimit()) { + printk(KERN_DEBUG "CCMP: received packet from " MAC_FMT + " with keyid=%d that does not have a configured" + " key\n", MAC_ARG(hdr->addr2), keyidx); + } + return -3; + } + + pn[0] = pos[7]; + pn[1] = pos[6]; + pn[2] = pos[5]; + pn[3] = pos[4]; + pn[4] = pos[1]; + pn[5] = pos[0]; + pos += 8; + + if (memcmp(pn, key->rx_pn, CCMP_PN_LEN) <= 0) { + if (net_ratelimit()) { + printk(KERN_DEBUG "CCMP: replay detected: STA=" MAC_FMT + " previous PN %02x%02x%02x%02x%02x%02x " + "received PN %02x%02x%02x%02x%02x%02x\n", + MAC_ARG(hdr->addr2), MAC_ARG(key->rx_pn), + MAC_ARG(pn)); + } + key->dot11RSNAStatsCCMPReplays++; + return -4; + } + if (!tcb_desc->bHwSec) + { + size_t data_len = skb->len - hdr_len - CCMP_HDR_LEN - CCMP_MIC_LEN; + u8 *mic = skb->data + skb->len - CCMP_MIC_LEN; + u8 *b0 = key->rx_b0; + u8 *b = key->rx_b; + u8 *a = key->rx_a; + int i, blocks, last, len; + + + ccmp_init_blocks(key->tfm, hdr, pn, data_len, b0, a, b); + xor_block(mic, b, CCMP_MIC_LEN); + + blocks = (data_len + AES_BLOCK_LEN - 1) / AES_BLOCK_LEN; + last = data_len % AES_BLOCK_LEN; + + for (i = 1; i <= blocks; i++) { + len = (i == blocks && last) ? last : AES_BLOCK_LEN; + /* Decrypt, with counter */ + b0[14] = (i >> 8) & 0xff; + b0[15] = i & 0xff; + ieee80211_ccmp_aes_encrypt(key->tfm, b0, b); + xor_block(pos, b, len); + /* Authentication */ + xor_block(a, pos, len); + ieee80211_ccmp_aes_encrypt(key->tfm, a, a); + pos += len; + } + + if (memcmp(mic, a, CCMP_MIC_LEN) != 0) { + if (net_ratelimit()) { + printk(KERN_DEBUG "CCMP: decrypt failed: STA=" + MAC_FMT "\n", MAC_ARG(hdr->addr2)); + } + key->dot11RSNAStatsCCMPDecryptErrors++; + return -5; + } + + memcpy(key->rx_pn, pn, CCMP_PN_LEN); + } + /* Remove hdr and MIC */ + memmove(skb->data + CCMP_HDR_LEN, skb->data, hdr_len); + skb_pull(skb, CCMP_HDR_LEN); + skb_trim(skb, skb->len - CCMP_MIC_LEN); + + return keyidx; +} + + +static int ieee80211_ccmp_set_key(void *key, int len, u8 *seq, void *priv) +{ + struct ieee80211_ccmp_data *data = priv; + int keyidx; + struct crypto_tfm *tfm = data->tfm; + + keyidx = data->key_idx; + memset(data, 0, sizeof(*data)); + data->key_idx = keyidx; + data->tfm = tfm; + if (len == CCMP_TK_LEN) { + memcpy(data->key, key, CCMP_TK_LEN); + data->key_set = 1; + if (seq) { + data->rx_pn[0] = seq[5]; + data->rx_pn[1] = seq[4]; + data->rx_pn[2] = seq[3]; + data->rx_pn[3] = seq[2]; + data->rx_pn[4] = seq[1]; + data->rx_pn[5] = seq[0]; + } + crypto_cipher_setkey((void*)data->tfm, data->key, CCMP_TK_LEN); + } else if (len == 0) + data->key_set = 0; + else + return -1; + + return 0; +} + + +static int ieee80211_ccmp_get_key(void *key, int len, u8 *seq, void *priv) +{ + struct ieee80211_ccmp_data *data = priv; + + if (len < CCMP_TK_LEN) + return -1; + + if (!data->key_set) + return 0; + memcpy(key, data->key, CCMP_TK_LEN); + + if (seq) { + seq[0] = data->tx_pn[5]; + seq[1] = data->tx_pn[4]; + seq[2] = data->tx_pn[3]; + seq[3] = data->tx_pn[2]; + seq[4] = data->tx_pn[1]; + seq[5] = data->tx_pn[0]; + } + + return CCMP_TK_LEN; +} + + +static char * ieee80211_ccmp_print_stats(char *p, void *priv) +{ + struct ieee80211_ccmp_data *ccmp = priv; + p += sprintf(p, "key[%d] alg=CCMP key_set=%d " + "tx_pn=%02x%02x%02x%02x%02x%02x " + "rx_pn=%02x%02x%02x%02x%02x%02x " + "format_errors=%d replays=%d decrypt_errors=%d\n", + ccmp->key_idx, ccmp->key_set, + MAC_ARG(ccmp->tx_pn), MAC_ARG(ccmp->rx_pn), + ccmp->dot11RSNAStatsCCMPFormatErrors, + ccmp->dot11RSNAStatsCCMPReplays, + ccmp->dot11RSNAStatsCCMPDecryptErrors); + + return p; +} + +void ieee80211_ccmp_null(void) +{ +// printk("============>%s()\n", __FUNCTION__); + return; +} + +static struct ieee80211_crypto_ops ieee80211_crypt_ccmp = { + .name = "CCMP", + .init = ieee80211_ccmp_init, + .deinit = ieee80211_ccmp_deinit, + .encrypt_mpdu = ieee80211_ccmp_encrypt, + .decrypt_mpdu = ieee80211_ccmp_decrypt, + .encrypt_msdu = NULL, + .decrypt_msdu = NULL, + .set_key = ieee80211_ccmp_set_key, + .get_key = ieee80211_ccmp_get_key, + .print_stats = ieee80211_ccmp_print_stats, + .extra_prefix_len = CCMP_HDR_LEN, + .extra_postfix_len = CCMP_MIC_LEN, + .owner = THIS_MODULE, +}; + + +static int __init ieee80211_crypto_ccmp_init(void) +{ + return ieee80211_register_crypto_ops(&ieee80211_crypt_ccmp); +} + + +static void __exit ieee80211_crypto_ccmp_exit(void) +{ + ieee80211_unregister_crypto_ops(&ieee80211_crypt_ccmp); +} + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) +EXPORT_SYMBOL(ieee80211_ccmp_null); +#else +EXPORT_SYMBOL_NOVERS(ieee80211_ccmp_null); +#endif + +module_init(ieee80211_crypto_ccmp_init); +module_exit(ieee80211_crypto_ccmp_exit); diff --git a/drivers/staging/rtl8192su/ieee80211/ieee80211_crypt_tkip.c b/drivers/staging/rtl8192su/ieee80211/ieee80211_crypt_tkip.c new file mode 100644 index 000000000000..b031b6495247 --- /dev/null +++ b/drivers/staging/rtl8192su/ieee80211/ieee80211_crypt_tkip.c @@ -0,0 +1,1034 @@ +/* + * Host AP crypt: host-based TKIP encryption implementation for Host AP driver + * + * Copyright (c) 2003-2004, Jouni Malinen <jkmaline@cc.hut.fi> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. See README and COPYING for + * more details. + */ + +//#include <linux/config.h> +#include <linux/version.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/slab.h> +#include <linux/random.h> +#include <linux/skbuff.h> +#include <linux/netdevice.h> +#include <linux/if_ether.h> +#include <linux/if_arp.h> +#include <asm/string.h> + +#include "ieee80211.h" +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,20)) +//#include "crypto_compat.h" +#endif + + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)) +#include "rtl_crypto.h" +#else +#include <linux/crypto.h> +#endif +//#include <asm/scatterlist.h> +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) + #include <asm/scatterlist.h> +#else + #include <linux/scatterlist.h> +#endif + +#include <linux/crc32.h> + +MODULE_AUTHOR("Jouni Malinen"); +MODULE_DESCRIPTION("Host AP crypt: TKIP"); +MODULE_LICENSE("GPL"); + +#ifndef OPENSUSE_SLED +#define OPENSUSE_SLED 0 +#endif + +struct ieee80211_tkip_data { +#define TKIP_KEY_LEN 32 + u8 key[TKIP_KEY_LEN]; + int key_set; + + u32 tx_iv32; + u16 tx_iv16; + u16 tx_ttak[5]; + int tx_phase1_done; + + u32 rx_iv32; + u16 rx_iv16; + u16 rx_ttak[5]; + int rx_phase1_done; + u32 rx_iv32_new; + u16 rx_iv16_new; + + u32 dot11RSNAStatsTKIPReplays; + u32 dot11RSNAStatsTKIPICVErrors; + u32 dot11RSNAStatsTKIPLocalMICFailures; + + int key_idx; +#if((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)) || (OPENSUSE_SLED)) + struct crypto_blkcipher *rx_tfm_arc4; + struct crypto_hash *rx_tfm_michael; + struct crypto_blkcipher *tx_tfm_arc4; + struct crypto_hash *tx_tfm_michael; +#else + struct crypto_tfm *tx_tfm_arc4; + struct crypto_tfm *tx_tfm_michael; + struct crypto_tfm *rx_tfm_arc4; + struct crypto_tfm *rx_tfm_michael; +#endif + /* scratch buffers for virt_to_page() (crypto API) */ + u8 rx_hdr[16], tx_hdr[16]; +}; + +static void * ieee80211_tkip_init(int key_idx) +{ + struct ieee80211_tkip_data *priv; + + priv = kmalloc(sizeof(*priv), GFP_ATOMIC); + if (priv == NULL) + goto fail; + memset(priv, 0, sizeof(*priv)); + priv->key_idx = key_idx; +#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED)) + priv->tx_tfm_arc4 = crypto_alloc_tfm("arc4", 0); + if (priv->tx_tfm_arc4 == NULL) { + printk(KERN_DEBUG "ieee80211_crypt_tkip: could not allocate " + "crypto API arc4\n"); + goto fail; + } + + priv->tx_tfm_michael = crypto_alloc_tfm("michael_mic", 0); + if (priv->tx_tfm_michael == NULL) { + printk(KERN_DEBUG "ieee80211_crypt_tkip: could not allocate " + "crypto API michael_mic\n"); + goto fail; + } + + priv->rx_tfm_arc4 = crypto_alloc_tfm("arc4", 0); + if (priv->rx_tfm_arc4 == NULL) { + printk(KERN_DEBUG "ieee80211_crypt_tkip: could not allocate " + "crypto API arc4\n"); + goto fail; + } + + priv->rx_tfm_michael = crypto_alloc_tfm("michael_mic", 0); + if (priv->rx_tfm_michael == NULL) { + printk(KERN_DEBUG "ieee80211_crypt_tkip: could not allocate " + "crypto API michael_mic\n"); + goto fail; + } +#else + priv->tx_tfm_arc4 = crypto_alloc_blkcipher("ecb(arc4)", 0, + CRYPTO_ALG_ASYNC); + if (IS_ERR(priv->tx_tfm_arc4)) { + printk(KERN_DEBUG "ieee80211_crypt_tkip: could not allocate " + "crypto API arc4\n"); + priv->tx_tfm_arc4 = NULL; + goto fail; + } + + priv->tx_tfm_michael = crypto_alloc_hash("michael_mic", 0, + CRYPTO_ALG_ASYNC); + if (IS_ERR(priv->tx_tfm_michael)) { + printk(KERN_DEBUG "ieee80211_crypt_tkip: could not allocate " + "crypto API michael_mic\n"); + priv->tx_tfm_michael = NULL; + goto fail; + } + + priv->rx_tfm_arc4 = crypto_alloc_blkcipher("ecb(arc4)", 0, + CRYPTO_ALG_ASYNC); + if (IS_ERR(priv->rx_tfm_arc4)) { + printk(KERN_DEBUG "ieee80211_crypt_tkip: could not allocate " + "crypto API arc4\n"); + priv->rx_tfm_arc4 = NULL; + goto fail; + } + + priv->rx_tfm_michael = crypto_alloc_hash("michael_mic", 0, + CRYPTO_ALG_ASYNC); + if (IS_ERR(priv->rx_tfm_michael)) { + printk(KERN_DEBUG "ieee80211_crypt_tkip: could not allocate " + "crypto API michael_mic\n"); + priv->rx_tfm_michael = NULL; + goto fail; + } +#endif + return priv; + +fail: + if (priv) { +#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED)) + if (priv->tx_tfm_michael) + crypto_free_tfm(priv->tx_tfm_michael); + if (priv->tx_tfm_arc4) + crypto_free_tfm(priv->tx_tfm_arc4); + if (priv->rx_tfm_michael) + crypto_free_tfm(priv->rx_tfm_michael); + if (priv->rx_tfm_arc4) + crypto_free_tfm(priv->rx_tfm_arc4); + +#else + if (priv->tx_tfm_michael) + crypto_free_hash(priv->tx_tfm_michael); + if (priv->tx_tfm_arc4) + crypto_free_blkcipher(priv->tx_tfm_arc4); + if (priv->rx_tfm_michael) + crypto_free_hash(priv->rx_tfm_michael); + if (priv->rx_tfm_arc4) + crypto_free_blkcipher(priv->rx_tfm_arc4); +#endif + kfree(priv); + } + + return NULL; +} + + +static void ieee80211_tkip_deinit(void *priv) +{ + struct ieee80211_tkip_data *_priv = priv; +#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED)) + if (_priv->tx_tfm_michael) + crypto_free_tfm(_priv->tx_tfm_michael); + if (_priv->tx_tfm_arc4) + crypto_free_tfm(_priv->tx_tfm_arc4); + if (_priv->rx_tfm_michael) + crypto_free_tfm(_priv->rx_tfm_michael); + if (_priv->rx_tfm_arc4) + crypto_free_tfm(_priv->rx_tfm_arc4); +#else + if (_priv) { + if (_priv->tx_tfm_michael) + crypto_free_hash(_priv->tx_tfm_michael); + if (_priv->tx_tfm_arc4) + crypto_free_blkcipher(_priv->tx_tfm_arc4); + if (_priv->rx_tfm_michael) + crypto_free_hash(_priv->rx_tfm_michael); + if (_priv->rx_tfm_arc4) + crypto_free_blkcipher(_priv->rx_tfm_arc4); + } +#endif + kfree(priv); +} + + +static inline u16 RotR1(u16 val) +{ + return (val >> 1) | (val << 15); +} + + +static inline u8 Lo8(u16 val) +{ + return val & 0xff; +} + + +static inline u8 Hi8(u16 val) +{ + return val >> 8; +} + + +static inline u16 Lo16(u32 val) +{ + return val & 0xffff; +} + + +static inline u16 Hi16(u32 val) +{ + return val >> 16; +} + + +static inline u16 Mk16(u8 hi, u8 lo) +{ + return lo | (((u16) hi) << 8); +} + + +static inline u16 Mk16_le(u16 *v) +{ + return le16_to_cpu(*v); +} + + +static const u16 Sbox[256] = +{ + 0xC6A5, 0xF884, 0xEE99, 0xF68D, 0xFF0D, 0xD6BD, 0xDEB1, 0x9154, + 0x6050, 0x0203, 0xCEA9, 0x567D, 0xE719, 0xB562, 0x4DE6, 0xEC9A, + 0x8F45, 0x1F9D, 0x8940, 0xFA87, 0xEF15, 0xB2EB, 0x8EC9, 0xFB0B, + 0x41EC, 0xB367, 0x5FFD, 0x45EA, 0x23BF, 0x53F7, 0xE496, 0x9B5B, + 0x75C2, 0xE11C, 0x3DAE, 0x4C6A, 0x6C5A, 0x7E41, 0xF502, 0x834F, + 0x685C, 0x51F4, 0xD134, 0xF908, 0xE293, 0xAB73, 0x6253, 0x2A3F, + 0x080C, 0x9552, 0x4665, 0x9D5E, 0x3028, 0x37A1, 0x0A0F, 0x2FB5, + 0x0E09, 0x2436, 0x1B9B, 0xDF3D, 0xCD26, 0x4E69, 0x7FCD, 0xEA9F, + 0x121B, 0x1D9E, 0x5874, 0x342E, 0x362D, 0xDCB2, 0xB4EE, 0x5BFB, + 0xA4F6, 0x764D, 0xB761, 0x7DCE, 0x527B, 0xDD3E, 0x5E71, 0x1397, + 0xA6F5, 0xB968, 0x0000, 0xC12C, 0x4060, 0xE31F, 0x79C8, 0xB6ED, + 0xD4BE, 0x8D46, 0x67D9, 0x724B, 0x94DE, 0x98D4, 0xB0E8, 0x854A, + 0xBB6B, 0xC52A, 0x4FE5, 0xED16, 0x86C5, 0x9AD7, 0x6655, 0x1194, + 0x8ACF, 0xE910, 0x0406, 0xFE81, 0xA0F0, 0x7844, 0x25BA, 0x4BE3, + 0xA2F3, 0x5DFE, 0x80C0, 0x058A, 0x3FAD, 0x21BC, 0x7048, 0xF104, + 0x63DF, 0x77C1, 0xAF75, 0x4263, 0x2030, 0xE51A, 0xFD0E, 0xBF6D, + 0x814C, 0x1814, 0x2635, 0xC32F, 0xBEE1, 0x35A2, 0x88CC, 0x2E39, + 0x9357, 0x55F2, 0xFC82, 0x7A47, 0xC8AC, 0xBAE7, 0x322B, 0xE695, + 0xC0A0, 0x1998, 0x9ED1, 0xA37F, 0x4466, 0x547E, 0x3BAB, 0x0B83, + 0x8CCA, 0xC729, 0x6BD3, 0x283C, 0xA779, 0xBCE2, 0x161D, 0xAD76, + 0xDB3B, 0x6456, 0x744E, 0x141E, 0x92DB, 0x0C0A, 0x486C, 0xB8E4, + 0x9F5D, 0xBD6E, 0x43EF, 0xC4A6, 0x39A8, 0x31A4, 0xD337, 0xF28B, + 0xD532, 0x8B43, 0x6E59, 0xDAB7, 0x018C, 0xB164, 0x9CD2, 0x49E0, + 0xD8B4, 0xACFA, 0xF307, 0xCF25, 0xCAAF, 0xF48E, 0x47E9, 0x1018, + 0x6FD5, 0xF088, 0x4A6F, 0x5C72, 0x3824, 0x57F1, 0x73C7, 0x9751, + 0xCB23, 0xA17C, 0xE89C, 0x3E21, 0x96DD, 0x61DC, 0x0D86, 0x0F85, + 0xE090, 0x7C42, 0x71C4, 0xCCAA, 0x90D8, 0x0605, 0xF701, 0x1C12, + 0xC2A3, 0x6A5F, 0xAEF9, 0x69D0, 0x1791, 0x9958, 0x3A27, 0x27B9, + 0xD938, 0xEB13, 0x2BB3, 0x2233, 0xD2BB, 0xA970, 0x0789, 0x33A7, + 0x2DB6, 0x3C22, 0x1592, 0xC920, 0x8749, 0xAAFF, 0x5078, 0xA57A, + 0x038F, 0x59F8, 0x0980, 0x1A17, 0x65DA, 0xD731, 0x84C6, 0xD0B8, + 0x82C3, 0x29B0, 0x5A77, 0x1E11, 0x7BCB, 0xA8FC, 0x6DD6, 0x2C3A, +}; + + +static inline u16 _S_(u16 v) +{ + u16 t = Sbox[Hi8(v)]; + return Sbox[Lo8(v)] ^ ((t << 8) | (t >> 8)); +} + + +#define PHASE1_LOOP_COUNT 8 + + +static void tkip_mixing_phase1(u16 *TTAK, const u8 *TK, const u8 *TA, u32 IV32) +{ + int i, j; + + /* Initialize the 80-bit TTAK from TSC (IV32) and TA[0..5] */ + TTAK[0] = Lo16(IV32); + TTAK[1] = Hi16(IV32); + TTAK[2] = Mk16(TA[1], TA[0]); + TTAK[3] = Mk16(TA[3], TA[2]); + TTAK[4] = Mk16(TA[5], TA[4]); + + for (i = 0; i < PHASE1_LOOP_COUNT; i++) { + j = 2 * (i & 1); + TTAK[0] += _S_(TTAK[4] ^ Mk16(TK[1 + j], TK[0 + j])); + TTAK[1] += _S_(TTAK[0] ^ Mk16(TK[5 + j], TK[4 + j])); + TTAK[2] += _S_(TTAK[1] ^ Mk16(TK[9 + j], TK[8 + j])); + TTAK[3] += _S_(TTAK[2] ^ Mk16(TK[13 + j], TK[12 + j])); + TTAK[4] += _S_(TTAK[3] ^ Mk16(TK[1 + j], TK[0 + j])) + i; + } +} + + +static void tkip_mixing_phase2(u8 *WEPSeed, const u8 *TK, const u16 *TTAK, + u16 IV16) +{ + /* Make temporary area overlap WEP seed so that the final copy can be + * avoided on little endian hosts. */ + u16 *PPK = (u16 *) &WEPSeed[4]; + + /* Step 1 - make copy of TTAK and bring in TSC */ + PPK[0] = TTAK[0]; + PPK[1] = TTAK[1]; + PPK[2] = TTAK[2]; + PPK[3] = TTAK[3]; + PPK[4] = TTAK[4]; + PPK[5] = TTAK[4] + IV16; + + /* Step 2 - 96-bit bijective mixing using S-box */ + PPK[0] += _S_(PPK[5] ^ Mk16_le((u16 *) &TK[0])); + PPK[1] += _S_(PPK[0] ^ Mk16_le((u16 *) &TK[2])); + PPK[2] += _S_(PPK[1] ^ Mk16_le((u16 *) &TK[4])); + PPK[3] += _S_(PPK[2] ^ Mk16_le((u16 *) &TK[6])); + PPK[4] += _S_(PPK[3] ^ Mk16_le((u16 *) &TK[8])); + PPK[5] += _S_(PPK[4] ^ Mk16_le((u16 *) &TK[10])); + + PPK[0] += RotR1(PPK[5] ^ Mk16_le((u16 *) &TK[12])); + PPK[1] += RotR1(PPK[0] ^ Mk16_le((u16 *) &TK[14])); + PPK[2] += RotR1(PPK[1]); + PPK[3] += RotR1(PPK[2]); + PPK[4] += RotR1(PPK[3]); + PPK[5] += RotR1(PPK[4]); + + /* Step 3 - bring in last of TK bits, assign 24-bit WEP IV value + * WEPSeed[0..2] is transmitted as WEP IV */ + WEPSeed[0] = Hi8(IV16); + WEPSeed[1] = (Hi8(IV16) | 0x20) & 0x7F; + WEPSeed[2] = Lo8(IV16); + WEPSeed[3] = Lo8((PPK[5] ^ Mk16_le((u16 *) &TK[0])) >> 1); + +#ifdef __BIG_ENDIAN + { + int i; + for (i = 0; i < 6; i++) + PPK[i] = (PPK[i] << 8) | (PPK[i] >> 8); + } +#endif +} + + +static int ieee80211_tkip_encrypt(struct sk_buff *skb, int hdr_len, void *priv) +{ + struct ieee80211_tkip_data *tkey = priv; + int len; + u8 *pos; + struct ieee80211_hdr_4addr *hdr; + cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE); + + #if((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)) || (OPENSUSE_SLED)) + struct blkcipher_desc desc = {.tfm = tkey->tx_tfm_arc4}; + int ret = 0; + #endif + u8 rc4key[16], *icv; + u32 crc; + struct scatterlist sg; + + if (skb_headroom(skb) < 8 || skb_tailroom(skb) < 4 || + skb->len < hdr_len) + return -1; + + hdr = (struct ieee80211_hdr_4addr *) skb->data; + +#if 0 +printk("@@ tkey\n"); +printk("%x|", ((u32*)tkey->key)[0]); +printk("%x|", ((u32*)tkey->key)[1]); +printk("%x|", ((u32*)tkey->key)[2]); +printk("%x|", ((u32*)tkey->key)[3]); +printk("%x|", ((u32*)tkey->key)[4]); +printk("%x|", ((u32*)tkey->key)[5]); +printk("%x|", ((u32*)tkey->key)[6]); +printk("%x\n", ((u32*)tkey->key)[7]); +#endif + + if (!tcb_desc->bHwSec) + { + if (!tkey->tx_phase1_done) { + tkip_mixing_phase1(tkey->tx_ttak, tkey->key, hdr->addr2, + tkey->tx_iv32); + tkey->tx_phase1_done = 1; + } + tkip_mixing_phase2(rc4key, tkey->key, tkey->tx_ttak, tkey->tx_iv16); + } + else + tkey->tx_phase1_done = 1; + + + len = skb->len - hdr_len; + pos = skb_push(skb, 8); + memmove(pos, pos + 8, hdr_len); + pos += hdr_len; + + if (tcb_desc->bHwSec) + { + *pos++ = Hi8(tkey->tx_iv16); + *pos++ = (Hi8(tkey->tx_iv16) | 0x20) & 0x7F; + *pos++ = Lo8(tkey->tx_iv16); + } + else + { + *pos++ = rc4key[0]; + *pos++ = rc4key[1]; + *pos++ = rc4key[2]; + } + + *pos++ = (tkey->key_idx << 6) | (1 << 5) /* Ext IV included */; + *pos++ = tkey->tx_iv32 & 0xff; + *pos++ = (tkey->tx_iv32 >> 8) & 0xff; + *pos++ = (tkey->tx_iv32 >> 16) & 0xff; + *pos++ = (tkey->tx_iv32 >> 24) & 0xff; + + if (!tcb_desc->bHwSec) + { + icv = skb_put(skb, 4); +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) + crc = ~crc32_le(~0, pos, len); +#else + crc = ~ether_crc_le(len, pos); +#endif + icv[0] = crc; + icv[1] = crc >> 8; + icv[2] = crc >> 16; + icv[3] = crc >> 24; +#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED)) + crypto_cipher_setkey(tkey->tx_tfm_arc4, rc4key, 16); + sg.page = virt_to_page(pos); + sg.offset = offset_in_page(pos); + sg.length = len + 4; + crypto_cipher_encrypt(tkey->tx_tfm_arc4, &sg, &sg, len + 4); +#else + crypto_blkcipher_setkey(tkey->tx_tfm_arc4, rc4key, 16); +#if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) + sg.page = virt_to_page(pos); + sg.offset = offset_in_page(pos); + sg.length = len + 4; +#else + sg_init_one(&sg, pos, len+4); +#endif + ret= crypto_blkcipher_encrypt(&desc, &sg, &sg, len + 4); +#endif + + } + + tkey->tx_iv16++; + if (tkey->tx_iv16 == 0) { + tkey->tx_phase1_done = 0; + tkey->tx_iv32++; + } + + if (!tcb_desc->bHwSec) +#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED)) + return 0; + #else + return ret; + #endif + else + return 0; + + +} + +static int ieee80211_tkip_decrypt(struct sk_buff *skb, int hdr_len, void *priv) +{ + struct ieee80211_tkip_data *tkey = priv; + u8 keyidx, *pos; + u32 iv32; + u16 iv16; + struct ieee80211_hdr_4addr *hdr; + cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE); + #if((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)) || (OPENSUSE_SLED)) + struct blkcipher_desc desc = {.tfm = tkey->rx_tfm_arc4}; + #endif + u8 rc4key[16]; + u8 icv[4]; + u32 crc; + struct scatterlist sg; + int plen; + if (skb->len < hdr_len + 8 + 4) + return -1; + + hdr = (struct ieee80211_hdr_4addr *) skb->data; + pos = skb->data + hdr_len; + keyidx = pos[3]; + if (!(keyidx & (1 << 5))) { + if (net_ratelimit()) { + printk(KERN_DEBUG "TKIP: received packet without ExtIV" + " flag from " MAC_FMT "\n", MAC_ARG(hdr->addr2)); + } + return -2; + } + keyidx >>= 6; + if (tkey->key_idx != keyidx) { + printk(KERN_DEBUG "TKIP: RX tkey->key_idx=%d frame " + "keyidx=%d priv=%p\n", tkey->key_idx, keyidx, priv); + return -6; + } + if (!tkey->key_set) { + if (net_ratelimit()) { + printk(KERN_DEBUG "TKIP: received packet from " MAC_FMT + " with keyid=%d that does not have a configured" + " key\n", MAC_ARG(hdr->addr2), keyidx); + } + return -3; + } + iv16 = (pos[0] << 8) | pos[2]; + iv32 = pos[4] | (pos[5] << 8) | (pos[6] << 16) | (pos[7] << 24); + pos += 8; + + if (!tcb_desc->bHwSec) + { + if (iv32 < tkey->rx_iv32 || + (iv32 == tkey->rx_iv32 && iv16 <= tkey->rx_iv16)) { + if (net_ratelimit()) { + printk(KERN_DEBUG "TKIP: replay detected: STA=" MAC_FMT + " previous TSC %08x%04x received TSC " + "%08x%04x\n", MAC_ARG(hdr->addr2), + tkey->rx_iv32, tkey->rx_iv16, iv32, iv16); + } + tkey->dot11RSNAStatsTKIPReplays++; + return -4; + } + + if (iv32 != tkey->rx_iv32 || !tkey->rx_phase1_done) { + tkip_mixing_phase1(tkey->rx_ttak, tkey->key, hdr->addr2, iv32); + tkey->rx_phase1_done = 1; + } + tkip_mixing_phase2(rc4key, tkey->key, tkey->rx_ttak, iv16); + + plen = skb->len - hdr_len - 12; + +#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED)) + crypto_cipher_setkey(tkey->rx_tfm_arc4, rc4key, 16); + sg.page = virt_to_page(pos); + sg.offset = offset_in_page(pos); + sg.length = plen + 4; + crypto_cipher_decrypt(tkey->rx_tfm_arc4, &sg, &sg, plen + 4); +#else + crypto_blkcipher_setkey(tkey->rx_tfm_arc4, rc4key, 16); +#if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) + sg.page = virt_to_page(pos); + sg.offset = offset_in_page(pos); + sg.length = plen + 4; +#else + sg_init_one(&sg, pos, plen+4); +#endif + if (crypto_blkcipher_decrypt(&desc, &sg, &sg, plen + 4)) { + if (net_ratelimit()) { + printk(KERN_DEBUG ": TKIP: failed to decrypt " + "received packet from " MAC_FMT "\n", + MAC_ARG(hdr->addr2)); + } + return -7; + } +#endif + + #if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) + crc = ~crc32_le(~0, pos, plen); + #else + crc = ~ether_crc_le(plen, pos); + #endif + icv[0] = crc; + icv[1] = crc >> 8; + icv[2] = crc >> 16; + icv[3] = crc >> 24; + + if (memcmp(icv, pos + plen, 4) != 0) { + if (iv32 != tkey->rx_iv32) { + /* Previously cached Phase1 result was already lost, so + * it needs to be recalculated for the next packet. */ + tkey->rx_phase1_done = 0; + } + if (net_ratelimit()) { + printk(KERN_DEBUG "TKIP: ICV error detected: STA=" + MAC_FMT "\n", MAC_ARG(hdr->addr2)); + } + tkey->dot11RSNAStatsTKIPICVErrors++; + return -5; + } + + } + + /* Update real counters only after Michael MIC verification has + * completed */ + tkey->rx_iv32_new = iv32; + tkey->rx_iv16_new = iv16; + + /* Remove IV and ICV */ + memmove(skb->data + 8, skb->data, hdr_len); + skb_pull(skb, 8); + skb_trim(skb, skb->len - 4); + +//john's test +#ifdef JOHN_DUMP +if( ((u16*)skb->data)[0] & 0x4000){ + printk("@@ rx decrypted skb->data"); + int i; + for(i=0;i<skb->len;i++){ + if( (i%24)==0 ) printk("\n"); + printk("%2x ", ((u8*)skb->data)[i]); + } + printk("\n"); +} +#endif /*JOHN_DUMP*/ + return keyidx; +} + + +#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED)) +static int michael_mic(struct crypto_tfm * tfm_michael, u8 *key, u8 *hdr, + u8 *data, size_t data_len, u8 *mic) +{ + struct scatterlist sg[2]; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + struct hash_desc desc; + int ret = 0; +#endif + + if (tfm_michael == NULL){ + printk(KERN_WARNING "michael_mic: tfm_michael == NULL\n"); + return -1; + } + sg[0].page = virt_to_page(hdr); + sg[0].offset = offset_in_page(hdr); + sg[0].length = 16; + + sg[1].page = virt_to_page(data); + sg[1].offset = offset_in_page(data); + sg[1].length = data_len; + + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) + crypto_digest_init(tfm_michael); + crypto_digest_setkey(tfm_michael, key, 8); + crypto_digest_update(tfm_michael, sg, 2); + crypto_digest_final(tfm_michael, mic); + return 0; +#else +if (crypto_hash_setkey(tkey->tfm_michael, key, 8)) + return -1; + +// return 0; + desc.tfm = tkey->tfm_michael; + desc.flags = 0; + ret = crypto_hash_digest(&desc, sg, data_len + 16, mic); + return ret; +#endif +} +#else +static int michael_mic(struct crypto_hash *tfm_michael, u8 * key, u8 * hdr, + u8 * data, size_t data_len, u8 * mic) +{ + struct hash_desc desc; + struct scatterlist sg[2]; + + if (tfm_michael == NULL) { + printk(KERN_WARNING "michael_mic: tfm_michael == NULL\n"); + return -1; + } +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) + sg[0].page = virt_to_page(hdr); + sg[0].offset = offset_in_page(hdr); + sg[0].length = 16; + + sg[1].page = virt_to_page(data); + sg[1].offset = offset_in_page(data); + sg[1].length = data_len; +#else + sg_init_table(sg, 2); + sg_set_buf(&sg[0], hdr, 16); + sg_set_buf(&sg[1], data, data_len); +#endif + + if (crypto_hash_setkey(tfm_michael, key, 8)) + return -1; + + desc.tfm = tfm_michael; + desc.flags = 0; + return crypto_hash_digest(&desc, sg, data_len + 16, mic); +} +#endif + + + +static void michael_mic_hdr(struct sk_buff *skb, u8 *hdr) +{ + struct ieee80211_hdr_4addr *hdr11; + + hdr11 = (struct ieee80211_hdr_4addr *) skb->data; + switch (le16_to_cpu(hdr11->frame_ctl) & + (IEEE80211_FCTL_FROMDS | IEEE80211_FCTL_TODS)) { + case IEEE80211_FCTL_TODS: + memcpy(hdr, hdr11->addr3, ETH_ALEN); /* DA */ + memcpy(hdr + ETH_ALEN, hdr11->addr2, ETH_ALEN); /* SA */ + break; + case IEEE80211_FCTL_FROMDS: + memcpy(hdr, hdr11->addr1, ETH_ALEN); /* DA */ + memcpy(hdr + ETH_ALEN, hdr11->addr3, ETH_ALEN); /* SA */ + break; + case IEEE80211_FCTL_FROMDS | IEEE80211_FCTL_TODS: + memcpy(hdr, hdr11->addr3, ETH_ALEN); /* DA */ + memcpy(hdr + ETH_ALEN, hdr11->addr4, ETH_ALEN); /* SA */ + break; + case 0: + memcpy(hdr, hdr11->addr1, ETH_ALEN); /* DA */ + memcpy(hdr + ETH_ALEN, hdr11->addr2, ETH_ALEN); /* SA */ + break; + } + + hdr[12] = 0; /* priority */ + + hdr[13] = hdr[14] = hdr[15] = 0; /* reserved */ +} + + +static int ieee80211_michael_mic_add(struct sk_buff *skb, int hdr_len, void *priv) +{ + struct ieee80211_tkip_data *tkey = priv; + u8 *pos; + struct ieee80211_hdr_4addr *hdr; + + hdr = (struct ieee80211_hdr_4addr *) skb->data; + + if (skb_tailroom(skb) < 8 || skb->len < hdr_len) { + printk(KERN_DEBUG "Invalid packet for Michael MIC add " + "(tailroom=%d hdr_len=%d skb->len=%d)\n", + skb_tailroom(skb), hdr_len, skb->len); + return -1; + } + + michael_mic_hdr(skb, tkey->tx_hdr); + + // { david, 2006.9.1 + // fix the wpa process with wmm enabled. + if(IEEE80211_QOS_HAS_SEQ(le16_to_cpu(hdr->frame_ctl))) { + tkey->tx_hdr[12] = *(skb->data + hdr_len - 2) & 0x07; + } + // } + pos = skb_put(skb, 8); +#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED)) + if (michael_mic(tkey->tx_tfm_michael, &tkey->key[16], tkey->tx_hdr, + skb->data + hdr_len, skb->len - 8 - hdr_len, pos)) +#else + if (michael_mic(tkey->tx_tfm_michael, &tkey->key[16], tkey->tx_hdr, + skb->data + hdr_len, skb->len - 8 - hdr_len, pos)) +#endif + return -1; + + return 0; +} + + +#if WIRELESS_EXT >= 18 +static void ieee80211_michael_mic_failure(struct net_device *dev, + struct ieee80211_hdr_4addr *hdr, + int keyidx) +{ + union iwreq_data wrqu; + struct iw_michaelmicfailure ev; + + /* TODO: needed parameters: count, keyid, key type, TSC */ + memset(&ev, 0, sizeof(ev)); + ev.flags = keyidx & IW_MICFAILURE_KEY_ID; + if (hdr->addr1[0] & 0x01) + ev.flags |= IW_MICFAILURE_GROUP; + else + ev.flags |= IW_MICFAILURE_PAIRWISE; + ev.src_addr.sa_family = ARPHRD_ETHER; + memcpy(ev.src_addr.sa_data, hdr->addr2, ETH_ALEN); + memset(&wrqu, 0, sizeof(wrqu)); + wrqu.data.length = sizeof(ev); + wireless_send_event(dev, IWEVMICHAELMICFAILURE, &wrqu, (char *) &ev); +} +#elif WIRELESS_EXT >= 15 +static void ieee80211_michael_mic_failure(struct net_device *dev, + struct ieee80211_hdr_4addr *hdr, + int keyidx) +{ + union iwreq_data wrqu; + char buf[128]; + + /* TODO: needed parameters: count, keyid, key type, TSC */ + sprintf(buf, "MLME-MICHAELMICFAILURE.indication(keyid=%d %scast addr=" + MAC_FMT ")", keyidx, hdr->addr1[0] & 0x01 ? "broad" : "uni", + MAC_ARG(hdr->addr2)); + memset(&wrqu, 0, sizeof(wrqu)); + wrqu.data.length = strlen(buf); + wireless_send_event(dev, IWEVCUSTOM, &wrqu, buf); +} +#else /* WIRELESS_EXT >= 15 */ +static inline void ieee80211_michael_mic_failure(struct net_device *dev, + struct ieee80211_hdr_4addr *hdr, + int keyidx) +{ +} +#endif /* WIRELESS_EXT >= 15 */ + +static int ieee80211_michael_mic_verify(struct sk_buff *skb, int keyidx, + int hdr_len, void *priv) +{ + struct ieee80211_tkip_data *tkey = priv; + u8 mic[8]; + struct ieee80211_hdr_4addr *hdr; + + hdr = (struct ieee80211_hdr_4addr *) skb->data; + + if (!tkey->key_set) + return -1; + + michael_mic_hdr(skb, tkey->rx_hdr); + // { david, 2006.9.1 + // fix the wpa process with wmm enabled. + if(IEEE80211_QOS_HAS_SEQ(le16_to_cpu(hdr->frame_ctl))) { + tkey->rx_hdr[12] = *(skb->data + hdr_len - 2) & 0x07; + } + // } + +#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED)) + if (michael_mic(tkey->rx_tfm_michael, &tkey->key[24], tkey->rx_hdr, + skb->data + hdr_len, skb->len - 8 - hdr_len, mic)) +#else + if (michael_mic(tkey->rx_tfm_michael, &tkey->key[24], tkey->rx_hdr, + skb->data + hdr_len, skb->len - 8 - hdr_len, mic)) +#endif + return -1; + if (memcmp(mic, skb->data + skb->len - 8, 8) != 0) { + struct ieee80211_hdr_4addr *hdr; + hdr = (struct ieee80211_hdr_4addr *) skb->data; + printk(KERN_DEBUG "%s: Michael MIC verification failed for " + "MSDU from " MAC_FMT " keyidx=%d\n", + skb->dev ? skb->dev->name : "N/A", MAC_ARG(hdr->addr2), + keyidx); + if (skb->dev) + ieee80211_michael_mic_failure(skb->dev, hdr, keyidx); + tkey->dot11RSNAStatsTKIPLocalMICFailures++; + return -1; + } + + /* Update TSC counters for RX now that the packet verification has + * completed. */ + tkey->rx_iv32 = tkey->rx_iv32_new; + tkey->rx_iv16 = tkey->rx_iv16_new; + + skb_trim(skb, skb->len - 8); + + return 0; +} + + +static int ieee80211_tkip_set_key(void *key, int len, u8 *seq, void *priv) +{ + struct ieee80211_tkip_data *tkey = priv; + int keyidx; +#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED)) + struct crypto_tfm *tfm = tkey->tx_tfm_michael; + struct crypto_tfm *tfm2 = tkey->tx_tfm_arc4; + struct crypto_tfm *tfm3 = tkey->rx_tfm_michael; + struct crypto_tfm *tfm4 = tkey->rx_tfm_arc4; +#else + struct crypto_hash *tfm = tkey->tx_tfm_michael; + struct crypto_blkcipher *tfm2 = tkey->tx_tfm_arc4; + struct crypto_hash *tfm3 = tkey->rx_tfm_michael; + struct crypto_blkcipher *tfm4 = tkey->rx_tfm_arc4; +#endif + + keyidx = tkey->key_idx; + memset(tkey, 0, sizeof(*tkey)); + tkey->key_idx = keyidx; +#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED)) + tkey->tx_tfm_michael = tfm; + tkey->tx_tfm_arc4 = tfm2; + tkey->rx_tfm_michael = tfm3; + tkey->rx_tfm_arc4 = tfm4; +#else + tkey->tx_tfm_michael = tfm; + tkey->tx_tfm_arc4 = tfm2; + tkey->rx_tfm_michael = tfm3; + tkey->rx_tfm_arc4 = tfm4; +#endif + + if (len == TKIP_KEY_LEN) { + memcpy(tkey->key, key, TKIP_KEY_LEN); + tkey->key_set = 1; + tkey->tx_iv16 = 1; /* TSC is initialized to 1 */ + if (seq) { + tkey->rx_iv32 = (seq[5] << 24) | (seq[4] << 16) | + (seq[3] << 8) | seq[2]; + tkey->rx_iv16 = (seq[1] << 8) | seq[0]; + } + } else if (len == 0) + tkey->key_set = 0; + else + return -1; + + return 0; +} + + +static int ieee80211_tkip_get_key(void *key, int len, u8 *seq, void *priv) +{ + struct ieee80211_tkip_data *tkey = priv; + + if (len < TKIP_KEY_LEN) + return -1; + + if (!tkey->key_set) + return 0; + memcpy(key, tkey->key, TKIP_KEY_LEN); + + if (seq) { + /* Return the sequence number of the last transmitted frame. */ + u16 iv16 = tkey->tx_iv16; + u32 iv32 = tkey->tx_iv32; + if (iv16 == 0) + iv32--; + iv16--; + seq[0] = tkey->tx_iv16; + seq[1] = tkey->tx_iv16 >> 8; + seq[2] = tkey->tx_iv32; + seq[3] = tkey->tx_iv32 >> 8; + seq[4] = tkey->tx_iv32 >> 16; + seq[5] = tkey->tx_iv32 >> 24; + } + + return TKIP_KEY_LEN; +} + + +static char * ieee80211_tkip_print_stats(char *p, void *priv) +{ + struct ieee80211_tkip_data *tkip = priv; + p += sprintf(p, "key[%d] alg=TKIP key_set=%d " + "tx_pn=%02x%02x%02x%02x%02x%02x " + "rx_pn=%02x%02x%02x%02x%02x%02x " + "replays=%d icv_errors=%d local_mic_failures=%d\n", + tkip->key_idx, tkip->key_set, + (tkip->tx_iv32 >> 24) & 0xff, + (tkip->tx_iv32 >> 16) & 0xff, + (tkip->tx_iv32 >> 8) & 0xff, + tkip->tx_iv32 & 0xff, + (tkip->tx_iv16 >> 8) & 0xff, + tkip->tx_iv16 & 0xff, + (tkip->rx_iv32 >> 24) & 0xff, + (tkip->rx_iv32 >> 16) & 0xff, + (tkip->rx_iv32 >> 8) & 0xff, + tkip->rx_iv32 & 0xff, + (tkip->rx_iv16 >> 8) & 0xff, + tkip->rx_iv16 & 0xff, + tkip->dot11RSNAStatsTKIPReplays, + tkip->dot11RSNAStatsTKIPICVErrors, + tkip->dot11RSNAStatsTKIPLocalMICFailures); + return p; +} + + +static struct ieee80211_crypto_ops ieee80211_crypt_tkip = { + .name = "TKIP", + .init = ieee80211_tkip_init, + .deinit = ieee80211_tkip_deinit, + .encrypt_mpdu = ieee80211_tkip_encrypt, + .decrypt_mpdu = ieee80211_tkip_decrypt, + .encrypt_msdu = ieee80211_michael_mic_add, + .decrypt_msdu = ieee80211_michael_mic_verify, + .set_key = ieee80211_tkip_set_key, + .get_key = ieee80211_tkip_get_key, + .print_stats = ieee80211_tkip_print_stats, + .extra_prefix_len = 4 + 4, /* IV + ExtIV */ + .extra_postfix_len = 8 + 4, /* MIC + ICV */ + .owner = THIS_MODULE, +}; + + +static int __init ieee80211_crypto_tkip_init(void) +{ + return ieee80211_register_crypto_ops(&ieee80211_crypt_tkip); +} + + +static void __exit ieee80211_crypto_tkip_exit(void) +{ + ieee80211_unregister_crypto_ops(&ieee80211_crypt_tkip); +} + +void ieee80211_tkip_null(void) +{ +// printk("============>%s()\n", __FUNCTION__); + return; +} +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) +EXPORT_SYMBOL(ieee80211_tkip_null); +#else +EXPORT_SYMBOL_NOVERS(ieee80211_tkip_null); +#endif + +module_init(ieee80211_crypto_tkip_init); +module_exit(ieee80211_crypto_tkip_exit); diff --git a/drivers/staging/rtl8192su/ieee80211/ieee80211_crypt_wep.c b/drivers/staging/rtl8192su/ieee80211/ieee80211_crypt_wep.c new file mode 100644 index 000000000000..7e394328ec90 --- /dev/null +++ b/drivers/staging/rtl8192su/ieee80211/ieee80211_crypt_wep.c @@ -0,0 +1,397 @@ +/* + * Host AP crypt: host-based WEP encryption implementation for Host AP driver + * + * Copyright (c) 2002-2004, Jouni Malinen <jkmaline@cc.hut.fi> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. See README and COPYING for + * more details. + */ + +//#include <linux/config.h> +#include <linux/version.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/slab.h> +#include <linux/random.h> +#include <linux/skbuff.h> +#include <asm/string.h> + +#include "ieee80211.h" + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,20)) +//#include "crypto_compat.h" +#endif + + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)) +#include "rtl_crypto.h" +#else +#include <linux/crypto.h> +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) + #include <asm/scatterlist.h> +#else + #include <linux/scatterlist.h> +#endif +//#include <asm/scatterlist.h> +#include <linux/crc32.h> +// +/* +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)) +#include "rtl_crypto.h" +#else +#include <linux/crypto.h> +#endif + +#include <asm/scatterlist.h> +#include <linux/crc32.h> +*/ +MODULE_AUTHOR("Jouni Malinen"); +MODULE_DESCRIPTION("Host AP crypt: WEP"); +MODULE_LICENSE("GPL"); +#ifndef OPENSUSE_SLED +#define OPENSUSE_SLED 0 +#endif + +struct prism2_wep_data { + u32 iv; +#define WEP_KEY_LEN 13 + u8 key[WEP_KEY_LEN + 1]; + u8 key_len; + u8 key_idx; +#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED)) + struct crypto_tfm *tfm; + #else + struct crypto_blkcipher *tx_tfm; + struct crypto_blkcipher *rx_tfm; + #endif +}; + + +static void * prism2_wep_init(int keyidx) +{ + struct prism2_wep_data *priv; + + priv = kmalloc(sizeof(*priv), GFP_ATOMIC); + if (priv == NULL) + goto fail; + memset(priv, 0, sizeof(*priv)); + priv->key_idx = keyidx; + +#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED)) + priv->tfm = crypto_alloc_tfm("arc4", 0); + if (priv->tfm == NULL) { + printk(KERN_DEBUG "ieee80211_crypt_wep: could not allocate " + "crypto API arc4\n"); + goto fail; + } + #else + priv->tx_tfm = crypto_alloc_blkcipher("ecb(arc4)", 0, CRYPTO_ALG_ASYNC); + if (IS_ERR(priv->tx_tfm)) { + printk(KERN_DEBUG "ieee80211_crypt_wep: could not allocate " + "crypto API arc4\n"); + priv->tx_tfm = NULL; + goto fail; + } + priv->rx_tfm = crypto_alloc_blkcipher("ecb(arc4)", 0, CRYPTO_ALG_ASYNC); + if (IS_ERR(priv->rx_tfm)) { + printk(KERN_DEBUG "ieee80211_crypt_wep: could not allocate " + "crypto API arc4\n"); + priv->rx_tfm = NULL; + goto fail; + } + #endif + + /* start WEP IV from a random value */ + get_random_bytes(&priv->iv, 4); + + return priv; + +fail: +#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED)) + if (priv) { + if (priv->tfm) + crypto_free_tfm(priv->tfm); + kfree(priv); + } + #else + if (priv) { + if (priv->tx_tfm) + crypto_free_blkcipher(priv->tx_tfm); + if (priv->rx_tfm) + crypto_free_blkcipher(priv->rx_tfm); + kfree(priv); + } + #endif + return NULL; +} + + +static void prism2_wep_deinit(void *priv) +{ + struct prism2_wep_data *_priv = priv; +#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED)) + if (_priv && _priv->tfm) + crypto_free_tfm(_priv->tfm); + #else + if (_priv) { + if (_priv->tx_tfm) + crypto_free_blkcipher(_priv->tx_tfm); + if (_priv->rx_tfm) + crypto_free_blkcipher(_priv->rx_tfm); + } + #endif + kfree(priv); +} + +/* Perform WEP encryption on given skb that has at least 4 bytes of headroom + * for IV and 4 bytes of tailroom for ICV. Both IV and ICV will be transmitted, + * so the payload length increases with 8 bytes. + * + * WEP frame payload: IV + TX key idx, RC4(data), ICV = RC4(CRC32(data)) + */ +static int prism2_wep_encrypt(struct sk_buff *skb, int hdr_len, void *priv) +{ + struct prism2_wep_data *wep = priv; + u32 klen, len; + u8 key[WEP_KEY_LEN + 3]; + u8 *pos; + cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE); + #if((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)) || (OPENSUSE_SLED)) + struct blkcipher_desc desc = {.tfm = wep->tx_tfm}; + #endif + u32 crc; + u8 *icv; + struct scatterlist sg; + if (skb_headroom(skb) < 4 || skb_tailroom(skb) < 4 || + skb->len < hdr_len) + return -1; + + len = skb->len - hdr_len; + pos = skb_push(skb, 4); + memmove(pos, pos + 4, hdr_len); + pos += hdr_len; + + klen = 3 + wep->key_len; + + wep->iv++; + + /* Fluhrer, Mantin, and Shamir have reported weaknesses in the key + * scheduling algorithm of RC4. At least IVs (KeyByte + 3, 0xff, N) + * can be used to speedup attacks, so avoid using them. */ + if ((wep->iv & 0xff00) == 0xff00) { + u8 B = (wep->iv >> 16) & 0xff; + if (B >= 3 && B < klen) + wep->iv += 0x0100; + } + + /* Prepend 24-bit IV to RC4 key and TX frame */ + *pos++ = key[0] = (wep->iv >> 16) & 0xff; + *pos++ = key[1] = (wep->iv >> 8) & 0xff; + *pos++ = key[2] = wep->iv & 0xff; + *pos++ = wep->key_idx << 6; + + /* Copy rest of the WEP key (the secret part) */ + memcpy(key + 3, wep->key, wep->key_len); + + if (!tcb_desc->bHwSec) + { + + /* Append little-endian CRC32 and encrypt it to produce ICV */ + #if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) + crc = ~crc32_le(~0, pos, len); + #else + crc = ~ether_crc_le(len, pos); + #endif + icv = skb_put(skb, 4); + icv[0] = crc; + icv[1] = crc >> 8; + icv[2] = crc >> 16; + icv[3] = crc >> 24; + +#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED)) + crypto_cipher_setkey(wep->tfm, key, klen); + sg.page = virt_to_page(pos); + sg.offset = offset_in_page(pos); + sg.length = len + 4; + crypto_cipher_encrypt(wep->tfm, &sg, &sg, len + 4); + return 0; + #else + crypto_blkcipher_setkey(wep->tx_tfm, key, klen); + #if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) + sg.page = virt_to_page(pos); + sg.offset = offset_in_page(pos); + sg.length = len + 4; + #else + sg_init_one(&sg, pos, len+4); + #endif + return crypto_blkcipher_encrypt(&desc, &sg, &sg, len + 4); + #endif + } + + return 0; +} + + +/* Perform WEP decryption on given buffer. Buffer includes whole WEP part of + * the frame: IV (4 bytes), encrypted payload (including SNAP header), + * ICV (4 bytes). len includes both IV and ICV. + * + * Returns 0 if frame was decrypted successfully and ICV was correct and -1 on + * failure. If frame is OK, IV and ICV will be removed. + */ +static int prism2_wep_decrypt(struct sk_buff *skb, int hdr_len, void *priv) +{ + struct prism2_wep_data *wep = priv; + u32 klen, plen; + u8 key[WEP_KEY_LEN + 3]; + u8 keyidx, *pos; + cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE); + #if((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)) || (OPENSUSE_SLED)) + struct blkcipher_desc desc = {.tfm = wep->rx_tfm}; + #endif + u32 crc; + u8 icv[4]; + struct scatterlist sg; + if (skb->len < hdr_len + 8) + return -1; + + pos = skb->data + hdr_len; + key[0] = *pos++; + key[1] = *pos++; + key[2] = *pos++; + keyidx = *pos++ >> 6; + if (keyidx != wep->key_idx) + return -1; + + klen = 3 + wep->key_len; + + /* Copy rest of the WEP key (the secret part) */ + memcpy(key + 3, wep->key, wep->key_len); + + /* Apply RC4 to data and compute CRC32 over decrypted data */ + plen = skb->len - hdr_len - 8; + + if (!tcb_desc->bHwSec) + { +#if((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) && (!OPENSUSE_SLED)) + crypto_cipher_setkey(wep->tfm, key, klen); + sg.page = virt_to_page(pos); + sg.offset = offset_in_page(pos); + sg.length = plen + 4; + crypto_cipher_decrypt(wep->tfm, &sg, &sg, plen + 4); + #else + crypto_blkcipher_setkey(wep->rx_tfm, key, klen); + #if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) + sg.page = virt_to_page(pos); + sg.offset = offset_in_page(pos); + sg.length = plen + 4; + #else + sg_init_one(&sg, pos, plen+4); + #endif + if (crypto_blkcipher_decrypt(&desc, &sg, &sg, plen + 4)) + return -7; + #endif + #if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) + crc = ~crc32_le(~0, pos, plen); + #else + crc = ~ether_crc_le(plen, pos); + #endif + icv[0] = crc; + icv[1] = crc >> 8; + icv[2] = crc >> 16; + icv[3] = crc >> 24; + if (memcmp(icv, pos + plen, 4) != 0) { + /* ICV mismatch - drop frame */ + return -2; + } + } + /* Remove IV and ICV */ + memmove(skb->data + 4, skb->data, hdr_len); + skb_pull(skb, 4); + skb_trim(skb, skb->len - 4); + + return 0; +} + + +static int prism2_wep_set_key(void *key, int len, u8 *seq, void *priv) +{ + struct prism2_wep_data *wep = priv; + + if (len < 0 || len > WEP_KEY_LEN) + return -1; + + memcpy(wep->key, key, len); + wep->key_len = len; + + return 0; +} + + +static int prism2_wep_get_key(void *key, int len, u8 *seq, void *priv) +{ + struct prism2_wep_data *wep = priv; + + if (len < wep->key_len) + return -1; + + memcpy(key, wep->key, wep->key_len); + + return wep->key_len; +} + + +static char * prism2_wep_print_stats(char *p, void *priv) +{ + struct prism2_wep_data *wep = priv; + p += sprintf(p, "key[%d] alg=WEP len=%d\n", + wep->key_idx, wep->key_len); + return p; +} + + +static struct ieee80211_crypto_ops ieee80211_crypt_wep = { + .name = "WEP", + .init = prism2_wep_init, + .deinit = prism2_wep_deinit, + .encrypt_mpdu = prism2_wep_encrypt, + .decrypt_mpdu = prism2_wep_decrypt, + .encrypt_msdu = NULL, + .decrypt_msdu = NULL, + .set_key = prism2_wep_set_key, + .get_key = prism2_wep_get_key, + .print_stats = prism2_wep_print_stats, + .extra_prefix_len = 4, /* IV */ + .extra_postfix_len = 4, /* ICV */ + .owner = THIS_MODULE, +}; + + +static int __init ieee80211_crypto_wep_init(void) +{ + return ieee80211_register_crypto_ops(&ieee80211_crypt_wep); +} + + +static void __exit ieee80211_crypto_wep_exit(void) +{ + ieee80211_unregister_crypto_ops(&ieee80211_crypt_wep); +} + +void ieee80211_wep_null(void) +{ +// printk("============>%s()\n", __FUNCTION__); + return; +} +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) +EXPORT_SYMBOL(ieee80211_wep_null); +#else +EXPORT_SYMBOL_NOVERS(ieee80211_wep_null); +#endif + +module_init(ieee80211_crypto_wep_init); +module_exit(ieee80211_crypto_wep_exit); diff --git a/drivers/staging/rtl8192su/ieee80211/ieee80211_module.c b/drivers/staging/rtl8192su/ieee80211/ieee80211_module.c new file mode 100644 index 000000000000..f408b4583b82 --- /dev/null +++ b/drivers/staging/rtl8192su/ieee80211/ieee80211_module.c @@ -0,0 +1,394 @@ +/******************************************************************************* + + Copyright(c) 2004 Intel Corporation. All rights reserved. + + Portions of this file are based on the WEP enablement code provided by the + Host AP project hostap-drivers v0.1.3 + Copyright (c) 2001-2002, SSH Communications Security Corp and Jouni Malinen + <jkmaline@cc.hut.fi> + Copyright (c) 2002-2003, Jouni Malinen <jkmaline@cc.hut.fi> + + This program is free software; you can redistribute it and/or modify it + under the terms of version 2 of the GNU General Public License as + published by the Free Software Foundation. + + This program is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + You should have received a copy of the GNU General Public License along with + this program; if not, write to the Free Software Foundation, Inc., 59 + Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + The full GNU General Public License is included in this distribution in the + file called LICENSE. + + Contact Information: + James P. Ketrenos <ipw2100-admin@linux.intel.com> + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 + +*******************************************************************************/ + +#include <linux/compiler.h> +//#include <linux/config.h> +#include <linux/errno.h> +#include <linux/if_arp.h> +#include <linux/in6.h> +#include <linux/in.h> +#include <linux/ip.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/netdevice.h> +#include <linux/pci.h> +#include <linux/proc_fs.h> +#include <linux/skbuff.h> +#include <linux/slab.h> +#include <linux/tcp.h> +#include <linux/types.h> +#include <linux/version.h> +#include <linux/wireless.h> +#include <linux/etherdevice.h> +#include <asm/uaccess.h> +#include <net/arp.h> + +#include "ieee80211.h" + +MODULE_DESCRIPTION("802.11 data/management/control stack"); +MODULE_AUTHOR("Copyright (C) 2004 Intel Corporation <jketreno@linux.intel.com>"); +MODULE_LICENSE("GPL"); + +#define DRV_NAME "ieee80211" + +static inline int ieee80211_networks_allocate(struct ieee80211_device *ieee) +{ + if (ieee->networks) + return 0; + + ieee->networks = kmalloc( + MAX_NETWORK_COUNT * sizeof(struct ieee80211_network), + GFP_KERNEL); + if (!ieee->networks) { + printk(KERN_WARNING "%s: Out of memory allocating beacons\n", + ieee->dev->name); + return -ENOMEM; + } + + memset(ieee->networks, 0, + MAX_NETWORK_COUNT * sizeof(struct ieee80211_network)); + + return 0; +} + +static inline void ieee80211_networks_free(struct ieee80211_device *ieee) +{ + if (!ieee->networks) + return; + kfree(ieee->networks); + ieee->networks = NULL; +} + +static inline void ieee80211_networks_initialize(struct ieee80211_device *ieee) +{ + int i; + + INIT_LIST_HEAD(&ieee->network_free_list); + INIT_LIST_HEAD(&ieee->network_list); + for (i = 0; i < MAX_NETWORK_COUNT; i++) + list_add_tail(&ieee->networks[i].list, &ieee->network_free_list); +} + + +struct net_device *alloc_ieee80211(int sizeof_priv) +{ + struct ieee80211_device *ieee; + struct net_device *dev; + int i,err; + + IEEE80211_DEBUG_INFO("Initializing...\n"); + + dev = alloc_etherdev(sizeof(struct ieee80211_device) + sizeof_priv); + if (!dev) { + IEEE80211_ERROR("Unable to network device.\n"); + goto failed; + } + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)) + ieee = netdev_priv(dev); +#else + ieee = (struct ieee80211_device *)dev->priv; +#endif + dev->hard_start_xmit = ieee80211_xmit; + + memset(ieee, 0, sizeof(struct ieee80211_device)+sizeof_priv); + ieee->dev = dev; + + err = ieee80211_networks_allocate(ieee); + if (err) { + IEEE80211_ERROR("Unable to allocate beacon storage: %d\n", + err); + goto failed; + } + ieee80211_networks_initialize(ieee); + + + /* Default fragmentation threshold is maximum payload size */ + ieee->fts = DEFAULT_FTS; + ieee->scan_age = DEFAULT_MAX_SCAN_AGE; + ieee->open_wep = 1; + + /* Default to enabling full open WEP with host based encrypt/decrypt */ + ieee->host_encrypt = 1; + ieee->host_decrypt = 1; + ieee->ieee802_1x = 1; /* Default to supporting 802.1x */ + + INIT_LIST_HEAD(&ieee->crypt_deinit_list); + init_timer(&ieee->crypt_deinit_timer); + ieee->crypt_deinit_timer.data = (unsigned long)ieee; + ieee->crypt_deinit_timer.function = ieee80211_crypt_deinit_handler; + + spin_lock_init(&ieee->lock); + spin_lock_init(&ieee->wpax_suitlist_lock); + spin_lock_init(&ieee->bw_spinlock); + spin_lock_init(&ieee->reorder_spinlock); + //added by WB + atomic_set(&(ieee->atm_chnlop), 0); + atomic_set(&(ieee->atm_swbw), 0); + + ieee->wpax_type_set = 0; + ieee->wpa_enabled = 0; + ieee->tkip_countermeasures = 0; + ieee->drop_unencrypted = 0; + ieee->privacy_invoked = 0; + ieee->ieee802_1x = 1; + ieee->raw_tx = 0; + //ieee->hwsec_support = 1; //defalt support hw security. //use module_param instead. + ieee->hwsec_active = 0; //disable hwsec, switch it on when necessary. + + ieee80211_softmac_init(ieee); + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,13)) + ieee->pHTInfo = (RT_HIGH_THROUGHPUT*)kzalloc(sizeof(RT_HIGH_THROUGHPUT), GFP_KERNEL); +#else + ieee->pHTInfo = (RT_HIGH_THROUGHPUT*)kmalloc(sizeof(RT_HIGH_THROUGHPUT), GFP_KERNEL); + memset(ieee->pHTInfo,0,sizeof(RT_HIGH_THROUGHPUT)); +#endif + if (ieee->pHTInfo == NULL) + { + IEEE80211_DEBUG(IEEE80211_DL_ERR, "can't alloc memory for HTInfo\n"); + return NULL; + } + HTUpdateDefaultSetting(ieee); + HTInitializeHTInfo(ieee); //may move to other place. + TSInitialize(ieee); +#if 0 +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) + INIT_WORK(&ieee->ht_onAssRsp, (void(*)(void*)) HTOnAssocRsp_wq); +#else + INIT_WORK(&ieee->ht_onAssRsp, (void(*)(void*)) HTOnAssocRsp_wq, ieee); +#endif +#endif + for (i = 0; i < IEEE_IBSS_MAC_HASH_SIZE; i++) + INIT_LIST_HEAD(&ieee->ibss_mac_hash[i]); + + for (i = 0; i < 17; i++) { + ieee->last_rxseq_num[i] = -1; + ieee->last_rxfrag_num[i] = -1; + ieee->last_packet_time[i] = 0; + } + +//These function were added to load crypte module autoly + ieee80211_tkip_null(); + ieee80211_wep_null(); + ieee80211_ccmp_null(); + + return dev; + + failed: + if (dev) +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)) + free_netdev(dev); +#else + kfree(dev); +#endif + return NULL; +} + + +void free_ieee80211(struct net_device *dev) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)) + struct ieee80211_device *ieee = netdev_priv(dev); +#else + struct ieee80211_device *ieee = (struct ieee80211_device *)dev->priv; +#endif + int i; + //struct list_head *p, *q; +// del_timer_sync(&ieee->SwBwTimer); +#if 1 + if (ieee->pHTInfo != NULL) + { + kfree(ieee->pHTInfo); + ieee->pHTInfo = NULL; + } +#endif + RemoveAllTS(ieee); + ieee80211_softmac_free(ieee); + del_timer_sync(&ieee->crypt_deinit_timer); + ieee80211_crypt_deinit_entries(ieee, 1); + + for (i = 0; i < WEP_KEYS; i++) { + struct ieee80211_crypt_data *crypt = ieee->crypt[i]; + if (crypt) { + if (crypt->ops) { + crypt->ops->deinit(crypt->priv); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) + module_put(crypt->ops->owner); +#else + __MOD_DEC_USE_COUNT(crypt->ops->owner); +#endif + } + kfree(crypt); + ieee->crypt[i] = NULL; + } + } + + ieee80211_networks_free(ieee); +#if 0 + for (i = 0; i < IEEE_IBSS_MAC_HASH_SIZE; i++) { + list_for_each_safe(p, q, &ieee->ibss_mac_hash[i]) { + kfree(list_entry(p, struct ieee_ibss_seq, list)); + list_del(p); + } + } + +#endif +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)) + free_netdev(dev); +#else + kfree(dev); +#endif +} + +#ifdef CONFIG_IEEE80211_DEBUG + +u32 ieee80211_debug_level = 0; +static int debug = \ + // IEEE80211_DL_INFO | + // IEEE80211_DL_WX | + // IEEE80211_DL_SCAN | + // IEEE80211_DL_STATE | + // IEEE80211_DL_MGMT | + // IEEE80211_DL_FRAG | + // IEEE80211_DL_EAP | + // IEEE80211_DL_DROP | + // IEEE80211_DL_TX | + // IEEE80211_DL_RX | + //IEEE80211_DL_QOS | + // IEEE80211_DL_HT | + // IEEE80211_DL_TS | +// IEEE80211_DL_BA | + // IEEE80211_DL_REORDER| +// IEEE80211_DL_TRACE | + //IEEE80211_DL_DATA | + IEEE80211_DL_ERR //awayls open this flags to show error out + ; +struct proc_dir_entry *ieee80211_proc = NULL; + +static int show_debug_level(char *page, char **start, off_t offset, + int count, int *eof, void *data) +{ + return snprintf(page, count, "0x%08X\n", ieee80211_debug_level); +} + +static int store_debug_level(struct file *file, const char *buffer, + unsigned long count, void *data) +{ + char buf[] = "0x00000000"; + unsigned long len = min(sizeof(buf) - 1, (u32)count); + char *p = (char *)buf; + unsigned long val; + + if (copy_from_user(buf, buffer, len)) + return count; + buf[len] = 0; + if (p[1] == 'x' || p[1] == 'X' || p[0] == 'x' || p[0] == 'X') { + p++; + if (p[0] == 'x' || p[0] == 'X') + p++; + val = simple_strtoul(p, &p, 16); + } else + val = simple_strtoul(p, &p, 10); + if (p == buf) + printk(KERN_INFO DRV_NAME + ": %s is not in hex or decimal form.\n", buf); + else + ieee80211_debug_level = val; + + return strnlen(buf, count); +} + +static int __init ieee80211_init(void) +{ + struct proc_dir_entry *e; + + ieee80211_debug_level = debug; +#if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) + ieee80211_proc = create_proc_entry(DRV_NAME, S_IFDIR, proc_net); +#else + ieee80211_proc = create_proc_entry(DRV_NAME, S_IFDIR, init_net.proc_net); +#endif + if (ieee80211_proc == NULL) { + IEEE80211_ERROR("Unable to create " DRV_NAME + " proc directory\n"); + return -EIO; + } + e = create_proc_entry("debug_level", S_IFREG | S_IRUGO | S_IWUSR, + ieee80211_proc); + if (!e) { +#if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) + remove_proc_entry(DRV_NAME, proc_net); +#else + remove_proc_entry(DRV_NAME, init_net.proc_net); +#endif + ieee80211_proc = NULL; + return -EIO; + } + e->read_proc = show_debug_level; + e->write_proc = store_debug_level; + e->data = NULL; + + return 0; +} + +static void __exit ieee80211_exit(void) +{ + if (ieee80211_proc) { + remove_proc_entry("debug_level", ieee80211_proc); +#if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) + remove_proc_entry(DRV_NAME, proc_net); +#else + remove_proc_entry(DRV_NAME, init_net.proc_net); +#endif + ieee80211_proc = NULL; + } +} + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) +#include <linux/moduleparam.h> +module_param(debug, int, 0444); +MODULE_PARM_DESC(debug, "debug output mask"); + + +module_exit(ieee80211_exit); +module_init(ieee80211_init); +#endif +#endif + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) +EXPORT_SYMBOL(alloc_ieee80211); +EXPORT_SYMBOL(free_ieee80211); +#else +EXPORT_SYMBOL_NOVERS(alloc_ieee80211); +EXPORT_SYMBOL_NOVERS(free_ieee80211); +#endif diff --git a/drivers/staging/rtl8192su/ieee80211/ieee80211_rx.c b/drivers/staging/rtl8192su/ieee80211/ieee80211_rx.c new file mode 100644 index 000000000000..2b2ffd34bc92 --- /dev/null +++ b/drivers/staging/rtl8192su/ieee80211/ieee80211_rx.c @@ -0,0 +1,2832 @@ +/* + * Original code based Host AP (software wireless LAN access point) driver + * for Intersil Prism2/2.5/3 - hostap.o module, common routines + * + * Copyright (c) 2001-2002, SSH Communications Security Corp and Jouni Malinen + * <jkmaline@cc.hut.fi> + * Copyright (c) 2002-2003, Jouni Malinen <jkmaline@cc.hut.fi> + * Copyright (c) 2004, Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. See README and COPYING for + * more details. + ****************************************************************************** + + Few modifications for Realtek's Wi-Fi drivers by + Andrea Merello <andreamrl@tiscali.it> + + A special thanks goes to Realtek for their support ! + +******************************************************************************/ + + +#include <linux/compiler.h> +//#include <linux/config.h> +#include <linux/errno.h> +#include <linux/if_arp.h> +#include <linux/in6.h> +#include <linux/in.h> +#include <linux/ip.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/netdevice.h> +#include <linux/pci.h> +#include <linux/proc_fs.h> +#include <linux/skbuff.h> +#include <linux/slab.h> +#include <linux/tcp.h> +#include <linux/types.h> +#include <linux/version.h> +#include <linux/wireless.h> +#include <linux/etherdevice.h> +#include <asm/uaccess.h> +#include <linux/ctype.h> + +#include "ieee80211.h" +#ifdef ENABLE_DOT11D +#include "dot11d.h" +#endif +static inline void ieee80211_monitor_rx(struct ieee80211_device *ieee, + struct sk_buff *skb, + struct ieee80211_rx_stats *rx_stats) +{ + struct ieee80211_hdr_4addr *hdr = (struct ieee80211_hdr_4addr *)skb->data; + u16 fc = le16_to_cpu(hdr->frame_ctl); + + skb->dev = ieee->dev; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22) + skb_reset_mac_header(skb); +#else + skb->mac.raw = skb->data; +#endif + + skb_pull(skb, ieee80211_get_hdrlen(fc)); + skb->pkt_type = PACKET_OTHERHOST; + skb->protocol = __constant_htons(ETH_P_80211_RAW); + memset(skb->cb, 0, sizeof(skb->cb)); + netif_rx(skb); +} + + +/* Called only as a tasklet (software IRQ) */ +static struct ieee80211_frag_entry * +ieee80211_frag_cache_find(struct ieee80211_device *ieee, unsigned int seq, + unsigned int frag, u8 tid,u8 *src, u8 *dst) +{ + struct ieee80211_frag_entry *entry; + int i; + + for (i = 0; i < IEEE80211_FRAG_CACHE_LEN; i++) { + entry = &ieee->frag_cache[tid][i]; + if (entry->skb != NULL && + time_after(jiffies, entry->first_frag_time + 2 * HZ)) { + IEEE80211_DEBUG_FRAG( + "expiring fragment cache entry " + "seq=%u last_frag=%u\n", + entry->seq, entry->last_frag); + dev_kfree_skb_any(entry->skb); + entry->skb = NULL; + } + + if (entry->skb != NULL && entry->seq == seq && + (entry->last_frag + 1 == frag || frag == -1) && + memcmp(entry->src_addr, src, ETH_ALEN) == 0 && + memcmp(entry->dst_addr, dst, ETH_ALEN) == 0) + return entry; + } + + return NULL; +} + +/* Called only as a tasklet (software IRQ) */ +static struct sk_buff * +ieee80211_frag_cache_get(struct ieee80211_device *ieee, + struct ieee80211_hdr_4addr *hdr) +{ + struct sk_buff *skb = NULL; + u16 fc = le16_to_cpu(hdr->frame_ctl); + u16 sc = le16_to_cpu(hdr->seq_ctl); + unsigned int frag = WLAN_GET_SEQ_FRAG(sc); + unsigned int seq = WLAN_GET_SEQ_SEQ(sc); + struct ieee80211_frag_entry *entry; + struct ieee80211_hdr_3addrqos *hdr_3addrqos; + struct ieee80211_hdr_4addrqos *hdr_4addrqos; + u8 tid; + + if (((fc & IEEE80211_FCTL_DSTODS) == IEEE80211_FCTL_DSTODS)&&IEEE80211_QOS_HAS_SEQ(fc)) { + hdr_4addrqos = (struct ieee80211_hdr_4addrqos *)hdr; + tid = le16_to_cpu(hdr_4addrqos->qos_ctl) & IEEE80211_QCTL_TID; + tid = UP2AC(tid); + tid ++; + } else if (IEEE80211_QOS_HAS_SEQ(fc)) { + hdr_3addrqos = (struct ieee80211_hdr_3addrqos *)hdr; + tid = le16_to_cpu(hdr_3addrqos->qos_ctl) & IEEE80211_QCTL_TID; + tid = UP2AC(tid); + tid ++; + } else { + tid = 0; + } + + if (frag == 0) { + /* Reserve enough space to fit maximum frame length */ + skb = dev_alloc_skb(ieee->dev->mtu + + sizeof(struct ieee80211_hdr_4addr) + + 8 /* LLC */ + + 2 /* alignment */ + + 8 /* WEP */ + + ETH_ALEN /* WDS */ + + (IEEE80211_QOS_HAS_SEQ(fc)?2:0) /* QOS Control */); + if (skb == NULL) + return NULL; + + entry = &ieee->frag_cache[tid][ieee->frag_next_idx[tid]]; + ieee->frag_next_idx[tid]++; + if (ieee->frag_next_idx[tid] >= IEEE80211_FRAG_CACHE_LEN) + ieee->frag_next_idx[tid] = 0; + + if (entry->skb != NULL) + dev_kfree_skb_any(entry->skb); + + entry->first_frag_time = jiffies; + entry->seq = seq; + entry->last_frag = frag; + entry->skb = skb; + memcpy(entry->src_addr, hdr->addr2, ETH_ALEN); + memcpy(entry->dst_addr, hdr->addr1, ETH_ALEN); + } else { + /* received a fragment of a frame for which the head fragment + * should have already been received */ + entry = ieee80211_frag_cache_find(ieee, seq, frag, tid,hdr->addr2, + hdr->addr1); + if (entry != NULL) { + entry->last_frag = frag; + skb = entry->skb; + } + } + + return skb; +} + + +/* Called only as a tasklet (software IRQ) */ +static int ieee80211_frag_cache_invalidate(struct ieee80211_device *ieee, + struct ieee80211_hdr_4addr *hdr) +{ + u16 fc = le16_to_cpu(hdr->frame_ctl); + u16 sc = le16_to_cpu(hdr->seq_ctl); + unsigned int seq = WLAN_GET_SEQ_SEQ(sc); + struct ieee80211_frag_entry *entry; + struct ieee80211_hdr_3addrqos *hdr_3addrqos; + struct ieee80211_hdr_4addrqos *hdr_4addrqos; + u8 tid; + + if(((fc & IEEE80211_FCTL_DSTODS) == IEEE80211_FCTL_DSTODS)&&IEEE80211_QOS_HAS_SEQ(fc)) { + hdr_4addrqos = (struct ieee80211_hdr_4addrqos *)hdr; + tid = le16_to_cpu(hdr_4addrqos->qos_ctl) & IEEE80211_QCTL_TID; + tid = UP2AC(tid); + tid ++; + } else if (IEEE80211_QOS_HAS_SEQ(fc)) { + hdr_3addrqos = (struct ieee80211_hdr_3addrqos *)hdr; + tid = le16_to_cpu(hdr_3addrqos->qos_ctl) & IEEE80211_QCTL_TID; + tid = UP2AC(tid); + tid ++; + } else { + tid = 0; + } + + entry = ieee80211_frag_cache_find(ieee, seq, -1, tid,hdr->addr2, + hdr->addr1); + + if (entry == NULL) { + IEEE80211_DEBUG_FRAG( + "could not invalidate fragment cache " + "entry (seq=%u)\n", seq); + return -1; + } + + entry->skb = NULL; + return 0; +} + + + +/* ieee80211_rx_frame_mgtmt + * + * Responsible for handling management control frames + * + * Called by ieee80211_rx */ +static inline int +ieee80211_rx_frame_mgmt(struct ieee80211_device *ieee, struct sk_buff *skb, + struct ieee80211_rx_stats *rx_stats, u16 type, + u16 stype) +{ + /* On the struct stats definition there is written that + * this is not mandatory.... but seems that the probe + * response parser uses it + */ + struct ieee80211_hdr_3addr * hdr = (struct ieee80211_hdr_3addr *)skb->data; + + rx_stats->len = skb->len; + ieee80211_rx_mgt(ieee,(struct ieee80211_hdr_4addr *)skb->data,rx_stats); + //if ((ieee->state == IEEE80211_LINKED) && (memcmp(hdr->addr3, ieee->current_network.bssid, ETH_ALEN))) + if ((memcmp(hdr->addr1, ieee->dev->dev_addr, ETH_ALEN)))//use ADDR1 to perform address matching for Management frames + { + dev_kfree_skb_any(skb); + return 0; + } + + ieee80211_rx_frame_softmac(ieee, skb, rx_stats, type, stype); + + dev_kfree_skb_any(skb); + + return 0; + + #ifdef NOT_YET + if (ieee->iw_mode == IW_MODE_MASTER) { + printk(KERN_DEBUG "%s: Master mode not yet suppported.\n", + ieee->dev->name); + return 0; +/* + hostap_update_sta_ps(ieee, (struct hostap_ieee80211_hdr_4addr *) + skb->data);*/ + } + + if (ieee->hostapd && type == IEEE80211_TYPE_MGMT) { + if (stype == WLAN_FC_STYPE_BEACON && + ieee->iw_mode == IW_MODE_MASTER) { + struct sk_buff *skb2; + /* Process beacon frames also in kernel driver to + * update STA(AP) table statistics */ + skb2 = skb_clone(skb, GFP_ATOMIC); + if (skb2) + hostap_rx(skb2->dev, skb2, rx_stats); + } + + /* send management frames to the user space daemon for + * processing */ + ieee->apdevstats.rx_packets++; + ieee->apdevstats.rx_bytes += skb->len; + prism2_rx_80211(ieee->apdev, skb, rx_stats, PRISM2_RX_MGMT); + return 0; + } + + if (ieee->iw_mode == IW_MODE_MASTER) { + if (type != WLAN_FC_TYPE_MGMT && type != WLAN_FC_TYPE_CTRL) { + printk(KERN_DEBUG "%s: unknown management frame " + "(type=0x%02x, stype=0x%02x) dropped\n", + skb->dev->name, type, stype); + return -1; + } + + hostap_rx(skb->dev, skb, rx_stats); + return 0; + } + + printk(KERN_DEBUG "%s: hostap_rx_frame_mgmt: management frame " + "received in non-Host AP mode\n", skb->dev->name); + return -1; + #endif +} + + + +/* See IEEE 802.1H for LLC/SNAP encapsulation/decapsulation */ +/* Ethernet-II snap header (RFC1042 for most EtherTypes) */ +static unsigned char rfc1042_header[] = +{ 0xaa, 0xaa, 0x03, 0x00, 0x00, 0x00 }; +/* Bridge-Tunnel header (for EtherTypes ETH_P_AARP and ETH_P_IPX) */ +static unsigned char bridge_tunnel_header[] = +{ 0xaa, 0xaa, 0x03, 0x00, 0x00, 0xf8 }; +/* No encapsulation header if EtherType < 0x600 (=length) */ + +/* Called by ieee80211_rx_frame_decrypt */ +static int ieee80211_is_eapol_frame(struct ieee80211_device *ieee, + struct sk_buff *skb, size_t hdrlen) +{ + struct net_device *dev = ieee->dev; + u16 fc, ethertype; + struct ieee80211_hdr_4addr *hdr; + u8 *pos; + + if (skb->len < 24) + return 0; + + hdr = (struct ieee80211_hdr_4addr *) skb->data; + fc = le16_to_cpu(hdr->frame_ctl); + + /* check that the frame is unicast frame to us */ + if ((fc & (IEEE80211_FCTL_TODS | IEEE80211_FCTL_FROMDS)) == + IEEE80211_FCTL_TODS && + memcmp(hdr->addr1, dev->dev_addr, ETH_ALEN) == 0 && + memcmp(hdr->addr3, dev->dev_addr, ETH_ALEN) == 0) { + /* ToDS frame with own addr BSSID and DA */ + } else if ((fc & (IEEE80211_FCTL_TODS | IEEE80211_FCTL_FROMDS)) == + IEEE80211_FCTL_FROMDS && + memcmp(hdr->addr1, dev->dev_addr, ETH_ALEN) == 0) { + /* FromDS frame with own addr as DA */ + } else + return 0; + + if (skb->len < 24 + 8) + return 0; + + /* check for port access entity Ethernet type */ +// pos = skb->data + 24; + pos = skb->data + hdrlen; + ethertype = (pos[6] << 8) | pos[7]; + if (ethertype == ETH_P_PAE) + return 1; + + return 0; +} + +/* Called only as a tasklet (software IRQ), by ieee80211_rx */ +static inline int +ieee80211_rx_frame_decrypt(struct ieee80211_device* ieee, struct sk_buff *skb, + struct ieee80211_crypt_data *crypt) +{ + struct ieee80211_hdr_4addr *hdr; + int res, hdrlen; + + if (crypt == NULL || crypt->ops->decrypt_mpdu == NULL) + return 0; +#if 1 + if (ieee->hwsec_active) + { + cb_desc *tcb_desc = (cb_desc *)(skb->cb+ MAX_DEV_ADDR_SIZE); + tcb_desc->bHwSec = 1; + } +#endif + hdr = (struct ieee80211_hdr_4addr *) skb->data; + hdrlen = ieee80211_get_hdrlen(le16_to_cpu(hdr->frame_ctl)); + +#ifdef CONFIG_IEEE80211_CRYPT_TKIP + if (ieee->tkip_countermeasures && + strcmp(crypt->ops->name, "TKIP") == 0) { + if (net_ratelimit()) { + printk(KERN_DEBUG "%s: TKIP countermeasures: dropped " + "received packet from " MAC_FMT "\n", + ieee->dev->name, MAC_ARG(hdr->addr2)); + } + return -1; + } +#endif + + atomic_inc(&crypt->refcnt); + res = crypt->ops->decrypt_mpdu(skb, hdrlen, crypt->priv); + atomic_dec(&crypt->refcnt); + if (res < 0) { + IEEE80211_DEBUG_DROP( + "decryption failed (SA=" MAC_FMT + ") res=%d\n", MAC_ARG(hdr->addr2), res); + if (res == -2) + IEEE80211_DEBUG_DROP("Decryption failed ICV " + "mismatch (key %d)\n", + skb->data[hdrlen + 3] >> 6); + ieee->ieee_stats.rx_discards_undecryptable++; + return -1; + } + + return res; +} + + +/* Called only as a tasklet (software IRQ), by ieee80211_rx */ +static inline int +ieee80211_rx_frame_decrypt_msdu(struct ieee80211_device* ieee, struct sk_buff *skb, + int keyidx, struct ieee80211_crypt_data *crypt) +{ + struct ieee80211_hdr_4addr *hdr; + int res, hdrlen; + + if (crypt == NULL || crypt->ops->decrypt_msdu == NULL) + return 0; + if (ieee->hwsec_active) + { + cb_desc *tcb_desc = (cb_desc *)(skb->cb+ MAX_DEV_ADDR_SIZE); + tcb_desc->bHwSec = 1; + } + + hdr = (struct ieee80211_hdr_4addr *) skb->data; + hdrlen = ieee80211_get_hdrlen(le16_to_cpu(hdr->frame_ctl)); + + atomic_inc(&crypt->refcnt); + res = crypt->ops->decrypt_msdu(skb, keyidx, hdrlen, crypt->priv); + atomic_dec(&crypt->refcnt); + if (res < 0) { + printk(KERN_DEBUG "%s: MSDU decryption/MIC verification failed" + " (SA=" MAC_FMT " keyidx=%d)\n", + ieee->dev->name, MAC_ARG(hdr->addr2), keyidx); + return -1; + } + + return 0; +} + + +/* this function is stolen from ipw2200 driver*/ +#define IEEE_PACKET_RETRY_TIME (5*HZ) +static int is_duplicate_packet(struct ieee80211_device *ieee, + struct ieee80211_hdr_4addr *header) +{ + u16 fc = le16_to_cpu(header->frame_ctl); + u16 sc = le16_to_cpu(header->seq_ctl); + u16 seq = WLAN_GET_SEQ_SEQ(sc); + u16 frag = WLAN_GET_SEQ_FRAG(sc); + u16 *last_seq, *last_frag; + unsigned long *last_time; + struct ieee80211_hdr_3addrqos *hdr_3addrqos; + struct ieee80211_hdr_4addrqos *hdr_4addrqos; + u8 tid; + + + //TO2DS and QoS + if(((fc & IEEE80211_FCTL_DSTODS) == IEEE80211_FCTL_DSTODS)&&IEEE80211_QOS_HAS_SEQ(fc)) { + hdr_4addrqos = (struct ieee80211_hdr_4addrqos *)header; + tid = le16_to_cpu(hdr_4addrqos->qos_ctl) & IEEE80211_QCTL_TID; + tid = UP2AC(tid); + tid ++; + } else if(IEEE80211_QOS_HAS_SEQ(fc)) { //QoS + hdr_3addrqos = (struct ieee80211_hdr_3addrqos*)header; + tid = le16_to_cpu(hdr_3addrqos->qos_ctl) & IEEE80211_QCTL_TID; + tid = UP2AC(tid); + tid ++; + } else { // no QoS + tid = 0; + } + + switch (ieee->iw_mode) { + case IW_MODE_ADHOC: + { + struct list_head *p; + struct ieee_ibss_seq *entry = NULL; + u8 *mac = header->addr2; + int index = mac[5] % IEEE_IBSS_MAC_HASH_SIZE; + //for (pos = (head)->next; pos != (head); pos = pos->next) + //__list_for_each(p, &ieee->ibss_mac_hash[index]) { + list_for_each(p, &ieee->ibss_mac_hash[index]) { + entry = list_entry(p, struct ieee_ibss_seq, list); + if (!memcmp(entry->mac, mac, ETH_ALEN)) + break; + } + // if (memcmp(entry->mac, mac, ETH_ALEN)){ + if (p == &ieee->ibss_mac_hash[index]) { + entry = kmalloc(sizeof(struct ieee_ibss_seq), GFP_ATOMIC); + if (!entry) { + printk(KERN_WARNING "Cannot malloc new mac entry\n"); + return 0; + } + memcpy(entry->mac, mac, ETH_ALEN); + entry->seq_num[tid] = seq; + entry->frag_num[tid] = frag; + entry->packet_time[tid] = jiffies; + list_add(&entry->list, &ieee->ibss_mac_hash[index]); + return 0; + } + last_seq = &entry->seq_num[tid]; + last_frag = &entry->frag_num[tid]; + last_time = &entry->packet_time[tid]; + break; + } + + case IW_MODE_INFRA: + last_seq = &ieee->last_rxseq_num[tid]; + last_frag = &ieee->last_rxfrag_num[tid]; + last_time = &ieee->last_packet_time[tid]; + + break; + default: + return 0; + } + +// if(tid != 0) { +// printk(KERN_WARNING ":)))))))))))%x %x %x, fc(%x)\n", tid, *last_seq, seq, header->frame_ctl); +// } + if ((*last_seq == seq) && + time_after(*last_time + IEEE_PACKET_RETRY_TIME, jiffies)) { + if (*last_frag == frag){ + //printk(KERN_WARNING "[1] go drop!\n"); + goto drop; + + } + if (*last_frag + 1 != frag) + /* out-of-order fragment */ + //printk(KERN_WARNING "[2] go drop!\n"); + goto drop; + } else + *last_seq = seq; + + *last_frag = frag; + *last_time = jiffies; + return 0; + +drop: +// BUG_ON(!(fc & IEEE80211_FCTL_RETRY)); +// printk("DUP\n"); + + return 1; +} +bool +AddReorderEntry( + PRX_TS_RECORD pTS, + PRX_REORDER_ENTRY pReorderEntry + ) +{ + struct list_head *pList = &pTS->RxPendingPktList; +#if 1 + while(pList->next != &pTS->RxPendingPktList) + { + if( SN_LESS(pReorderEntry->SeqNum, ((PRX_REORDER_ENTRY)list_entry(pList->next,RX_REORDER_ENTRY,List))->SeqNum) ) + { + pList = pList->next; + } + else if( SN_EQUAL(pReorderEntry->SeqNum, ((PRX_REORDER_ENTRY)list_entry(pList->next,RX_REORDER_ENTRY,List))->SeqNum) ) + { + return false; + } + else + { + break; + } + } +#endif + pReorderEntry->List.next = pList->next; + pReorderEntry->List.next->prev = &pReorderEntry->List; + pReorderEntry->List.prev = pList; + pList->next = &pReorderEntry->List; + + return true; +} + +void ieee80211_indicate_packets(struct ieee80211_device *ieee, struct ieee80211_rxb** prxbIndicateArray,u8 index) +{ + u8 i = 0 , j=0; + u16 ethertype; +// if(index > 1) +// IEEE80211_DEBUG(IEEE80211_DL_REORDER,"%s(): hahahahhhh, We indicate packet from reorder list, index is %u\n",__FUNCTION__,index); + for(j = 0; j<index; j++) + { +//added by amy for reorder + struct ieee80211_rxb* prxb = prxbIndicateArray[j]; + for(i = 0; i<prxb->nr_subframes; i++) { + struct sk_buff *sub_skb = prxb->subframes[i]; + + /* convert hdr + possible LLC headers into Ethernet header */ + ethertype = (sub_skb->data[6] << 8) | sub_skb->data[7]; + if (sub_skb->len >= 8 && + ((memcmp(sub_skb->data, rfc1042_header, SNAP_SIZE) == 0 && + ethertype != ETH_P_AARP && ethertype != ETH_P_IPX) || + memcmp(sub_skb->data, bridge_tunnel_header, SNAP_SIZE) == 0)) { + /* remove RFC1042 or Bridge-Tunnel encapsulation and + * replace EtherType */ + skb_pull(sub_skb, SNAP_SIZE); + memcpy(skb_push(sub_skb, ETH_ALEN), prxb->src, ETH_ALEN); + memcpy(skb_push(sub_skb, ETH_ALEN), prxb->dst, ETH_ALEN); + } else { + u16 len; + /* Leave Ethernet header part of hdr and full payload */ + len = htons(sub_skb->len); + memcpy(skb_push(sub_skb, 2), &len, 2); + memcpy(skb_push(sub_skb, ETH_ALEN), prxb->src, ETH_ALEN); + memcpy(skb_push(sub_skb, ETH_ALEN), prxb->dst, ETH_ALEN); + } + //stats->rx_packets++; + //stats->rx_bytes += sub_skb->len; + + /* Indicat the packets to upper layer */ + if (sub_skb) { + //printk("0skb_len(%d)\n", skb->len); + sub_skb->protocol = eth_type_trans(sub_skb, ieee->dev); + memset(sub_skb->cb, 0, sizeof(sub_skb->cb)); + sub_skb->dev = ieee->dev; + sub_skb->ip_summed = CHECKSUM_NONE; /* 802.11 crc not sufficient */ + //skb->ip_summed = CHECKSUM_UNNECESSARY; /* 802.11 crc not sufficient */ + ieee->last_rx_ps_time = jiffies; + //printk("1skb_len(%d)\n", skb->len); + netif_rx(sub_skb); + } + } + kfree(prxb); + prxb = NULL; + } +} + + +void RxReorderIndicatePacket( struct ieee80211_device *ieee, + struct ieee80211_rxb* prxb, + PRX_TS_RECORD pTS, + u16 SeqNum) +{ + PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; + PRX_REORDER_ENTRY pReorderEntry = NULL; + struct ieee80211_rxb* prxbIndicateArray[REORDER_WIN_SIZE]; + u8 WinSize = pHTInfo->RxReorderWinSize; + u16 WinEnd = (pTS->RxIndicateSeq + WinSize -1)%4096; + u8 index = 0; + bool bMatchWinStart = false, bPktInBuf = false; + IEEE80211_DEBUG(IEEE80211_DL_REORDER,"%s(): Seq is %d,pTS->RxIndicateSeq is %d, WinSize is %d\n",__FUNCTION__,SeqNum,pTS->RxIndicateSeq,WinSize); +#if 0 + if(!list_empty(&ieee->RxReorder_Unused_List)) + IEEE80211_DEBUG(IEEE80211_DL_REORDER,"%s(): ieee->RxReorder_Unused_List is nut NULL\n"); +#endif + /* Rx Reorder initialize condition.*/ + if(pTS->RxIndicateSeq == 0xffff) { + pTS->RxIndicateSeq = SeqNum; + } + + /* Drop out the packet which SeqNum is smaller than WinStart */ + if(SN_LESS(SeqNum, pTS->RxIndicateSeq)) { + IEEE80211_DEBUG(IEEE80211_DL_REORDER,"Packet Drop! IndicateSeq: %d, NewSeq: %d\n", + pTS->RxIndicateSeq, SeqNum); + pHTInfo->RxReorderDropCounter++; + { + int i; + for(i =0; i < prxb->nr_subframes; i++) { + dev_kfree_skb(prxb->subframes[i]); + } + kfree(prxb); + prxb = NULL; + } + return; + } + + /* + * Sliding window manipulation. Conditions includes: + * 1. Incoming SeqNum is equal to WinStart =>Window shift 1 + * 2. Incoming SeqNum is larger than the WinEnd => Window shift N + */ + if(SN_EQUAL(SeqNum, pTS->RxIndicateSeq)) { + pTS->RxIndicateSeq = (pTS->RxIndicateSeq + 1) % 4096; + bMatchWinStart = true; + } else if(SN_LESS(WinEnd, SeqNum)) { + if(SeqNum >= (WinSize - 1)) { + pTS->RxIndicateSeq = SeqNum + 1 -WinSize; + } else { + pTS->RxIndicateSeq = 4095 - (WinSize - (SeqNum +1)) + 1; + } + IEEE80211_DEBUG(IEEE80211_DL_REORDER, "Window Shift! IndicateSeq: %d, NewSeq: %d\n",pTS->RxIndicateSeq, SeqNum); + } + + /* + * Indication process. + * After Packet dropping and Sliding Window shifting as above, we can now just indicate the packets + * with the SeqNum smaller than latest WinStart and buffer other packets. + */ + /* For Rx Reorder condition: + * 1. All packets with SeqNum smaller than WinStart => Indicate + * 2. All packets with SeqNum larger than or equal to WinStart => Buffer it. + */ + if(bMatchWinStart) { + /* Current packet is going to be indicated.*/ + IEEE80211_DEBUG(IEEE80211_DL_REORDER, "Packets indication!! IndicateSeq: %d, NewSeq: %d\n",\ + pTS->RxIndicateSeq, SeqNum); + prxbIndicateArray[0] = prxb; +// printk("========================>%s(): SeqNum is %d\n",__FUNCTION__,SeqNum); + index = 1; + } else { + /* Current packet is going to be inserted into pending list.*/ + //IEEE80211_DEBUG(IEEE80211_DL_REORDER,"%s(): We RX no ordered packed, insert to orderd list\n",__FUNCTION__); + if(!list_empty(&ieee->RxReorder_Unused_List)) { + pReorderEntry = (PRX_REORDER_ENTRY)list_entry(ieee->RxReorder_Unused_List.next,RX_REORDER_ENTRY,List); + list_del_init(&pReorderEntry->List); + + /* Make a reorder entry and insert into a the packet list.*/ + pReorderEntry->SeqNum = SeqNum; + pReorderEntry->prxb = prxb; + // IEEE80211_DEBUG(IEEE80211_DL_REORDER,"%s(): pREorderEntry->SeqNum is %d\n",__FUNCTION__,pReorderEntry->SeqNum); + +#if 1 + if(!AddReorderEntry(pTS, pReorderEntry)) { + IEEE80211_DEBUG(IEEE80211_DL_REORDER, "%s(): Duplicate packet is dropped!! IndicateSeq: %d, NewSeq: %d\n", + __FUNCTION__, pTS->RxIndicateSeq, SeqNum); + list_add_tail(&pReorderEntry->List,&ieee->RxReorder_Unused_List); + { + int i; + for(i =0; i < prxb->nr_subframes; i++) { + dev_kfree_skb(prxb->subframes[i]); + } + kfree(prxb); + prxb = NULL; + } + } else { + IEEE80211_DEBUG(IEEE80211_DL_REORDER, + "Pkt insert into buffer!! IndicateSeq: %d, NewSeq: %d\n",pTS->RxIndicateSeq, SeqNum); + } +#endif + } + else { + /* + * Packets are dropped if there is not enough reorder entries. + * This part shall be modified!! We can just indicate all the + * packets in buffer and get reorder entries. + */ + IEEE80211_DEBUG(IEEE80211_DL_ERR, "RxReorderIndicatePacket(): There is no reorder entry!! Packet is dropped!!\n"); + { + int i; + for(i =0; i < prxb->nr_subframes; i++) { + dev_kfree_skb(prxb->subframes[i]); + } + kfree(prxb); + prxb = NULL; + } + } + } + + /* Check if there is any packet need indicate.*/ + while(!list_empty(&pTS->RxPendingPktList)) { + IEEE80211_DEBUG(IEEE80211_DL_REORDER,"%s(): start RREORDER indicate\n",__FUNCTION__); +#if 1 + pReorderEntry = (PRX_REORDER_ENTRY)list_entry(pTS->RxPendingPktList.prev,RX_REORDER_ENTRY,List); + if( SN_LESS(pReorderEntry->SeqNum, pTS->RxIndicateSeq) || + SN_EQUAL(pReorderEntry->SeqNum, pTS->RxIndicateSeq)) + { + /* This protect buffer from overflow. */ + if(index >= REORDER_WIN_SIZE) { + IEEE80211_DEBUG(IEEE80211_DL_ERR, "RxReorderIndicatePacket(): Buffer overflow!! \n"); + bPktInBuf = true; + break; + } + + list_del_init(&pReorderEntry->List); + + if(SN_EQUAL(pReorderEntry->SeqNum, pTS->RxIndicateSeq)) + pTS->RxIndicateSeq = (pTS->RxIndicateSeq + 1) % 4096; + + IEEE80211_DEBUG(IEEE80211_DL_REORDER,"Packets indication!! IndicateSeq: %d, NewSeq: %d\n",pTS->RxIndicateSeq, SeqNum); + prxbIndicateArray[index] = pReorderEntry->prxb; + // printk("========================>%s(): pReorderEntry->SeqNum is %d\n",__FUNCTION__,pReorderEntry->SeqNum); + index++; + + list_add_tail(&pReorderEntry->List,&ieee->RxReorder_Unused_List); + } else { + bPktInBuf = true; + break; + } +#endif + } + + /* Handling pending timer. Set this timer to prevent from long time Rx buffering.*/ + if(index>0) { + // Cancel previous pending timer. + if(timer_pending(&pTS->RxPktPendingTimer)) + { + del_timer_sync(&pTS->RxPktPendingTimer); + } + // del_timer_sync(&pTS->RxPktPendingTimer); + pTS->RxTimeoutIndicateSeq = 0xffff; + + // Indicate packets + if(index>REORDER_WIN_SIZE){ + IEEE80211_DEBUG(IEEE80211_DL_ERR, "RxReorderIndicatePacket(): Rx Reorer buffer full!! \n"); + return; + } + ieee80211_indicate_packets(ieee, prxbIndicateArray, index); + bPktInBuf = false; + } + +#if 1 + if(bPktInBuf && pTS->RxTimeoutIndicateSeq==0xffff) { + // Set new pending timer. + IEEE80211_DEBUG(IEEE80211_DL_REORDER,"%s(): SET rx timeout timer\n", __FUNCTION__); + pTS->RxTimeoutIndicateSeq = pTS->RxIndicateSeq; +#if 0 + if(timer_pending(&pTS->RxPktPendingTimer)) + del_timer_sync(&pTS->RxPktPendingTimer); + pTS->RxPktPendingTimer.expires = jiffies + MSECS(pHTInfo->RxReorderPendingTime); + add_timer(&pTS->RxPktPendingTimer); +#else + mod_timer(&pTS->RxPktPendingTimer, jiffies + MSECS(pHTInfo->RxReorderPendingTime)); +#endif + } +#endif +} + +u8 parse_subframe(struct sk_buff *skb, + struct ieee80211_rx_stats *rx_stats, + struct ieee80211_rxb *rxb,u8* src,u8* dst) +{ + struct ieee80211_hdr_3addr *hdr = (struct ieee80211_hdr_3addr* )skb->data; + u16 fc = le16_to_cpu(hdr->frame_ctl); + + u16 LLCOffset= sizeof(struct ieee80211_hdr_3addr); + u16 ChkLength; + bool bIsAggregateFrame = false; + u16 nSubframe_Length; + u8 nPadding_Length = 0; + u16 SeqNum=0; + + struct sk_buff *sub_skb; + u8 *data_ptr; + /* just for debug purpose */ + SeqNum = WLAN_GET_SEQ_SEQ(le16_to_cpu(hdr->seq_ctl)); + + if((IEEE80211_QOS_HAS_SEQ(fc))&&\ + (((frameqos *)(skb->data + IEEE80211_3ADDR_LEN))->field.reserved)) { + bIsAggregateFrame = true; + } + + if(IEEE80211_QOS_HAS_SEQ(fc)) { + LLCOffset += 2; + } + + if(rx_stats->bContainHTC) { + LLCOffset += sHTCLng; + } + //printk("ChkLength = %d\n", LLCOffset); + // Null packet, don't indicate it to upper layer + ChkLength = LLCOffset;/* + (Frame_WEP(frame)!=0 ?Adapter->MgntInfo.SecurityInfo.EncryptionHeadOverhead:0);*/ + + if( skb->len <= ChkLength ) { + return 0; + } + + skb_pull(skb, LLCOffset); + + if(!bIsAggregateFrame) { + rxb->nr_subframes = 1; +#ifdef JOHN_NOCPY + rxb->subframes[0] = skb; +#else + rxb->subframes[0] = skb_copy(skb, GFP_ATOMIC); +#endif + + memcpy(rxb->src,src,ETH_ALEN); + memcpy(rxb->dst,dst,ETH_ALEN); + //IEEE80211_DEBUG_DATA(IEEE80211_DL_RX,skb->data,skb->len); + return 1; + } else { + rxb->nr_subframes = 0; + memcpy(rxb->src,src,ETH_ALEN); + memcpy(rxb->dst,dst,ETH_ALEN); + while(skb->len > ETHERNET_HEADER_SIZE) { + /* Offset 12 denote 2 mac address */ + nSubframe_Length = *((u16*)(skb->data + 12)); + //==m==>change the length order + nSubframe_Length = (nSubframe_Length>>8) + (nSubframe_Length<<8); + + if(skb->len<(ETHERNET_HEADER_SIZE + nSubframe_Length)) { +#if 0//cosa + RT_ASSERT( + (nRemain_Length>=(ETHERNET_HEADER_SIZE + nSubframe_Length)), + ("ParseSubframe(): A-MSDU subframe parse error!! Subframe Length: %d\n", nSubframe_Length) ); +#endif + printk("%s: A-MSDU parse error!! pRfd->nTotalSubframe : %d\n",\ + __FUNCTION__,rxb->nr_subframes); + printk("%s: A-MSDU parse error!! Subframe Length: %d\n",__FUNCTION__, nSubframe_Length); + printk("nRemain_Length is %d and nSubframe_Length is : %d\n",skb->len,nSubframe_Length); + printk("The Packet SeqNum is %d\n",SeqNum); + return 0; + } + + /* move the data point to data content */ + skb_pull(skb, ETHERNET_HEADER_SIZE); + +#ifdef JOHN_NOCPY + sub_skb = skb_clone(skb, GFP_ATOMIC); + sub_skb->len = nSubframe_Length; + sub_skb->tail = sub_skb->data + nSubframe_Length; +#else + /* Allocate new skb for releasing to upper layer */ + sub_skb = dev_alloc_skb(nSubframe_Length + 12); + skb_reserve(sub_skb, 12); + data_ptr = (u8 *)skb_put(sub_skb, nSubframe_Length); + memcpy(data_ptr,skb->data,nSubframe_Length); +#endif + rxb->subframes[rxb->nr_subframes++] = sub_skb; + if(rxb->nr_subframes >= MAX_SUBFRAME_COUNT) { + IEEE80211_DEBUG_RX("ParseSubframe(): Too many Subframes! Packets dropped!\n"); + break; + } + skb_pull(skb,nSubframe_Length); + + if(skb->len != 0) { + nPadding_Length = 4 - ((nSubframe_Length + ETHERNET_HEADER_SIZE) % 4); + if(nPadding_Length == 4) { + nPadding_Length = 0; + } + + if(skb->len < nPadding_Length) { + return 0; + } + + skb_pull(skb,nPadding_Length); + } + } +#ifdef JOHN_NOCPY + dev_kfree_skb(skb); +#endif + //{just for debug added by david + //printk("AMSDU::rxb->nr_subframes = %d\n",rxb->nr_subframes); + //} + return rxb->nr_subframes; + } +} + +/* All received frames are sent to this function. @skb contains the frame in + * IEEE 802.11 format, i.e., in the format it was sent over air. + * This function is called only as a tasklet (software IRQ). */ +int ieee80211_rx(struct ieee80211_device *ieee, struct sk_buff *skb, + struct ieee80211_rx_stats *rx_stats) +{ + struct net_device *dev = ieee->dev; + struct ieee80211_hdr_4addr *hdr; + //struct ieee80211_hdr_3addrqos *hdr; + + size_t hdrlen; + u16 fc, type, stype, sc; + struct net_device_stats *stats; + unsigned int frag; + u8 *payload; + u16 ethertype; + //added by amy for reorder + u8 TID = 0; + u16 SeqNum = 0; + PRX_TS_RECORD pTS = NULL; + //bool bIsAggregateFrame = false; + //added by amy for reorder +#ifdef NOT_YET + struct net_device *wds = NULL; + struct sk_buff *skb2 = NULL; + struct net_device *wds = NULL; + int frame_authorized = 0; + int from_assoc_ap = 0; + void *sta = NULL; +#endif +// u16 qos_ctl = 0; + u8 dst[ETH_ALEN]; + u8 src[ETH_ALEN]; + u8 bssid[ETH_ALEN]; + struct ieee80211_crypt_data *crypt = NULL; + int keyidx = 0; + + int i; + struct ieee80211_rxb* rxb = NULL; + // cheat the the hdr type + hdr = (struct ieee80211_hdr_4addr *)skb->data; + stats = &ieee->stats; + + if (skb->len < 10) { + printk(KERN_INFO "%s: SKB length < 10\n", + dev->name); + goto rx_dropped; + } + + fc = le16_to_cpu(hdr->frame_ctl); + type = WLAN_FC_GET_TYPE(fc); + stype = WLAN_FC_GET_STYPE(fc); + sc = le16_to_cpu(hdr->seq_ctl); + + frag = WLAN_GET_SEQ_FRAG(sc); + hdrlen = ieee80211_get_hdrlen(fc); + + if(HTCCheck(ieee, skb->data)) + { + if(net_ratelimit()) + printk("find HTCControl\n"); + hdrlen += 4; + rx_stats->bContainHTC = 1; + } + + //IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA, skb->data, skb->len); +#ifdef NOT_YET +#if WIRELESS_EXT > 15 + /* Put this code here so that we avoid duplicating it in all + * Rx paths. - Jean II */ +#ifdef IW_WIRELESS_SPY /* defined in iw_handler.h */ + /* If spy monitoring on */ + if (iface->spy_data.spy_number > 0) { + struct iw_quality wstats; + wstats.level = rx_stats->rssi; + wstats.noise = rx_stats->noise; + wstats.updated = 6; /* No qual value */ + /* Update spy records */ + wireless_spy_update(dev, hdr->addr2, &wstats); + } +#endif /* IW_WIRELESS_SPY */ +#endif /* WIRELESS_EXT > 15 */ + hostap_update_rx_stats(local->ap, hdr, rx_stats); +#endif + +#if WIRELESS_EXT > 15 + if (ieee->iw_mode == IW_MODE_MONITOR) { + ieee80211_monitor_rx(ieee, skb, rx_stats); + stats->rx_packets++; + stats->rx_bytes += skb->len; + return 1; + } +#endif + if (ieee->host_decrypt) { + int idx = 0; + if (skb->len >= hdrlen + 3) + idx = skb->data[hdrlen + 3] >> 6; + crypt = ieee->crypt[idx]; +#ifdef NOT_YET + sta = NULL; + + /* Use station specific key to override default keys if the + * receiver address is a unicast address ("individual RA"). If + * bcrx_sta_key parameter is set, station specific key is used + * even with broad/multicast targets (this is against IEEE + * 802.11, but makes it easier to use different keys with + * stations that do not support WEP key mapping). */ + + if (!(hdr->addr1[0] & 0x01) || local->bcrx_sta_key) + (void) hostap_handle_sta_crypto(local, hdr, &crypt, + &sta); +#endif + + /* allow NULL decrypt to indicate an station specific override + * for default encryption */ + if (crypt && (crypt->ops == NULL || + crypt->ops->decrypt_mpdu == NULL)) + crypt = NULL; + + if (!crypt && (fc & IEEE80211_FCTL_WEP)) { + /* This seems to be triggered by some (multicast?) + * frames from other than current BSS, so just drop the + * frames silently instead of filling system log with + * these reports. */ + IEEE80211_DEBUG_DROP("Decryption failed (not set)" + " (SA=" MAC_FMT ")\n", + MAC_ARG(hdr->addr2)); + ieee->ieee_stats.rx_discards_undecryptable++; + goto rx_dropped; + } + } + + if (skb->len < IEEE80211_DATA_HDR3_LEN) + goto rx_dropped; + + // if QoS enabled, should check the sequence for each of the AC + if( (ieee->pHTInfo->bCurRxReorderEnable == false) || !ieee->current_network.qos_data.active|| !IsDataFrame(skb->data) || IsLegacyDataFrame(skb->data)){ + if (is_duplicate_packet(ieee, hdr)) + goto rx_dropped; + + } + else + { + PRX_TS_RECORD pRxTS = NULL; + #if 0 + struct ieee80211_hdr_3addr *hdr; + u16 fc; + hdr = (struct ieee80211_hdr_3addr *)skb->data; + fc = le16_to_cpu(hdr->frame_ctl); + u8 tmp = (fc & IEEE80211_FCTL_FROMDS) && (fc & IEEE80211_FCTL_TODS); + + u8 tid = (*((u8*)skb->data + (((fc& IEEE80211_FCTL_FROMDS) && (fc & IEEE80211_FCTL_TODS))?30:24)))&0xf; + printk("====================>fc:%x, tid:%d, tmp:%d\n", fc, tid, tmp); + //u8 tid = (u8)((frameqos*)(buf + ((fc & IEEE80211_FCTL_TODS)&&(fc & IEEE80211_FCTL_FROMDS))? 30 : 24))->field.tid; + #endif + //IEEE80211_DEBUG(IEEE80211_DL_REORDER,"%s(): QOS ENABLE AND RECEIVE QOS DATA , we will get Ts, tid:%d\n",__FUNCTION__, tid); +#if 1 + if(GetTs( + ieee, + (PTS_COMMON_INFO*) &pRxTS, + hdr->addr2, + (u8)Frame_QoSTID((u8*)(skb->data)), + RX_DIR, + true)) + { + + // IEEE80211_DEBUG(IEEE80211_DL_REORDER,"%s(): pRxTS->RxLastFragNum is %d,frag is %d,pRxTS->RxLastSeqNum is %d,seq is %d\n",__FUNCTION__,pRxTS->RxLastFragNum,frag,pRxTS->RxLastSeqNum,WLAN_GET_SEQ_SEQ(sc)); + if( (fc & (1<<11)) && + (frag == pRxTS->RxLastFragNum) && + (WLAN_GET_SEQ_SEQ(sc) == pRxTS->RxLastSeqNum) ) + { + goto rx_dropped; + } + else + { + pRxTS->RxLastFragNum = frag; + pRxTS->RxLastSeqNum = WLAN_GET_SEQ_SEQ(sc); + } + } + else + { + IEEE80211_DEBUG(IEEE80211_DL_ERR, "%s(): No TS!! Skip the check!!\n",__FUNCTION__); + goto rx_dropped; + } + } +#endif + if (type == IEEE80211_FTYPE_MGMT) { + + #if 0 + if ( stype == IEEE80211_STYPE_AUTH && + fc & IEEE80211_FCTL_WEP && ieee->host_decrypt && + (keyidx = hostap_rx_frame_decrypt(ieee, skb, crypt)) < 0) + { + printk(KERN_DEBUG "%s: failed to decrypt mgmt::auth " + "from " MAC_FMT "\n", dev->name, + MAC_ARG(hdr->addr2)); + /* TODO: could inform hostapd about this so that it + * could send auth failure report */ + goto rx_dropped; + } + #endif + + //IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA, skb->data, skb->len); + if (ieee80211_rx_frame_mgmt(ieee, skb, rx_stats, type, stype)) + goto rx_dropped; + else + goto rx_exit; + } + + /* Data frame - extract src/dst addresses */ + switch (fc & (IEEE80211_FCTL_FROMDS | IEEE80211_FCTL_TODS)) { + case IEEE80211_FCTL_FROMDS: + memcpy(dst, hdr->addr1, ETH_ALEN); + memcpy(src, hdr->addr3, ETH_ALEN); + memcpy(bssid, hdr->addr2, ETH_ALEN); + break; + case IEEE80211_FCTL_TODS: + memcpy(dst, hdr->addr3, ETH_ALEN); + memcpy(src, hdr->addr2, ETH_ALEN); + memcpy(bssid, hdr->addr1, ETH_ALEN); + break; + case IEEE80211_FCTL_FROMDS | IEEE80211_FCTL_TODS: + if (skb->len < IEEE80211_DATA_HDR4_LEN) + goto rx_dropped; + memcpy(dst, hdr->addr3, ETH_ALEN); + memcpy(src, hdr->addr4, ETH_ALEN); + memcpy(bssid, ieee->current_network.bssid, ETH_ALEN); + break; + case 0: + memcpy(dst, hdr->addr1, ETH_ALEN); + memcpy(src, hdr->addr2, ETH_ALEN); + memcpy(bssid, hdr->addr3, ETH_ALEN); + break; + } + +#ifdef NOT_YET + if (hostap_rx_frame_wds(ieee, hdr, fc, &wds)) + goto rx_dropped; + if (wds) { + skb->dev = dev = wds; + stats = hostap_get_stats(dev); + } + + if (ieee->iw_mode == IW_MODE_MASTER && !wds && + (fc & (IEEE80211_FCTL_TODS | IEEE80211_FCTL_FROMDS)) == IEEE80211_FCTL_FROMDS && + ieee->stadev && + memcmp(hdr->addr2, ieee->assoc_ap_addr, ETH_ALEN) == 0) { + /* Frame from BSSID of the AP for which we are a client */ + skb->dev = dev = ieee->stadev; + stats = hostap_get_stats(dev); + from_assoc_ap = 1; + } +#endif + + dev->last_rx = jiffies; + +#ifdef NOT_YET + if ((ieee->iw_mode == IW_MODE_MASTER || + ieee->iw_mode == IW_MODE_REPEAT) && + !from_assoc_ap) { + switch (hostap_handle_sta_rx(ieee, dev, skb, rx_stats, + wds != NULL)) { + case AP_RX_CONTINUE_NOT_AUTHORIZED: + frame_authorized = 0; + break; + case AP_RX_CONTINUE: + frame_authorized = 1; + break; + case AP_RX_DROP: + goto rx_dropped; + case AP_RX_EXIT: + goto rx_exit; + } + } +#endif + //IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA, skb->data, skb->len); + /* Nullfunc frames may have PS-bit set, so they must be passed to + * hostap_handle_sta_rx() before being dropped here. */ + if (stype != IEEE80211_STYPE_DATA && + stype != IEEE80211_STYPE_DATA_CFACK && + stype != IEEE80211_STYPE_DATA_CFPOLL && + stype != IEEE80211_STYPE_DATA_CFACKPOLL&& + stype != IEEE80211_STYPE_QOS_DATA//add by David,2006.8.4 + ) { + if (stype != IEEE80211_STYPE_NULLFUNC) + IEEE80211_DEBUG_DROP( + "RX: dropped data frame " + "with no data (type=0x%02x, " + "subtype=0x%02x, len=%d)\n", + type, stype, skb->len); + goto rx_dropped; + } + if (memcmp(bssid, ieee->current_network.bssid, ETH_ALEN)) + goto rx_dropped; + + /* skb: hdr + (possibly fragmented, possibly encrypted) payload */ + + if (ieee->host_decrypt && (fc & IEEE80211_FCTL_WEP) && + (keyidx = ieee80211_rx_frame_decrypt(ieee, skb, crypt)) < 0) + { + printk("decrypt frame error\n"); + goto rx_dropped; + } + + + hdr = (struct ieee80211_hdr_4addr *) skb->data; + + /* skb: hdr + (possibly fragmented) plaintext payload */ + // PR: FIXME: hostap has additional conditions in the "if" below: + // ieee->host_decrypt && (fc & IEEE80211_FCTL_WEP) && + if ((frag != 0 || (fc & IEEE80211_FCTL_MOREFRAGS))) { + int flen; + struct sk_buff *frag_skb = ieee80211_frag_cache_get(ieee, hdr); + IEEE80211_DEBUG_FRAG("Rx Fragment received (%u)\n", frag); + + if (!frag_skb) { + IEEE80211_DEBUG(IEEE80211_DL_RX | IEEE80211_DL_FRAG, + "Rx cannot get skb from fragment " + "cache (morefrag=%d seq=%u frag=%u)\n", + (fc & IEEE80211_FCTL_MOREFRAGS) != 0, + WLAN_GET_SEQ_SEQ(sc), frag); + goto rx_dropped; + } + flen = skb->len; + if (frag != 0) + flen -= hdrlen; + + if (frag_skb->tail + flen > frag_skb->end) { + printk(KERN_WARNING "%s: host decrypted and " + "reassembled frame did not fit skb\n", + dev->name); + ieee80211_frag_cache_invalidate(ieee, hdr); + goto rx_dropped; + } + + if (frag == 0) { + /* copy first fragment (including full headers) into + * beginning of the fragment cache skb */ + memcpy(skb_put(frag_skb, flen), skb->data, flen); + } else { + /* append frame payload to the end of the fragment + * cache skb */ + memcpy(skb_put(frag_skb, flen), skb->data + hdrlen, + flen); + } + dev_kfree_skb_any(skb); + skb = NULL; + + if (fc & IEEE80211_FCTL_MOREFRAGS) { + /* more fragments expected - leave the skb in fragment + * cache for now; it will be delivered to upper layers + * after all fragments have been received */ + goto rx_exit; + } + + /* this was the last fragment and the frame will be + * delivered, so remove skb from fragment cache */ + skb = frag_skb; + hdr = (struct ieee80211_hdr_4addr *) skb->data; + ieee80211_frag_cache_invalidate(ieee, hdr); + } + + /* skb: hdr + (possible reassembled) full MSDU payload; possibly still + * encrypted/authenticated */ + if (ieee->host_decrypt && (fc & IEEE80211_FCTL_WEP) && + ieee80211_rx_frame_decrypt_msdu(ieee, skb, keyidx, crypt)) + { + printk("==>decrypt msdu error\n"); + goto rx_dropped; + } + + //added by amy for AP roaming + ieee->LinkDetectInfo.NumRecvDataInPeriod++; + ieee->LinkDetectInfo.NumRxOkInPeriod++; + + hdr = (struct ieee80211_hdr_4addr *) skb->data; + if (crypt && !(fc & IEEE80211_FCTL_WEP) && !ieee->open_wep) { + if (/*ieee->ieee802_1x &&*/ + ieee80211_is_eapol_frame(ieee, skb, hdrlen)) { + +#ifdef CONFIG_IEEE80211_DEBUG + /* pass unencrypted EAPOL frames even if encryption is + * configured */ + struct eapol *eap = (struct eapol *)(skb->data + + 24); + IEEE80211_DEBUG_EAP("RX: IEEE 802.1X EAPOL frame: %s\n", + eap_get_type(eap->type)); +#endif + } else { + IEEE80211_DEBUG_DROP( + "encryption configured, but RX " + "frame not encrypted (SA=" MAC_FMT ")\n", + MAC_ARG(hdr->addr2)); + goto rx_dropped; + } + } + +#ifdef CONFIG_IEEE80211_DEBUG + if (crypt && !(fc & IEEE80211_FCTL_WEP) && + ieee80211_is_eapol_frame(ieee, skb, hdrlen)) { + struct eapol *eap = (struct eapol *)(skb->data + + 24); + IEEE80211_DEBUG_EAP("RX: IEEE 802.1X EAPOL frame: %s\n", + eap_get_type(eap->type)); + } +#endif + + if (crypt && !(fc & IEEE80211_FCTL_WEP) && !ieee->open_wep && + !ieee80211_is_eapol_frame(ieee, skb, hdrlen)) { + IEEE80211_DEBUG_DROP( + "dropped unencrypted RX data " + "frame from " MAC_FMT + " (drop_unencrypted=1)\n", + MAC_ARG(hdr->addr2)); + goto rx_dropped; + } +/* + if(ieee80211_is_eapol_frame(ieee, skb, hdrlen)) { + printk(KERN_WARNING "RX: IEEE802.1X EPAOL frame!\n"); + } +*/ +//added by amy for reorder +#if 1 + if(ieee->current_network.qos_data.active && IsQoSDataFrame(skb->data) + && !is_multicast_ether_addr(hdr->addr1) && !is_broadcast_ether_addr(hdr->addr1)) + { + TID = Frame_QoSTID(skb->data); + SeqNum = WLAN_GET_SEQ_SEQ(sc); + GetTs(ieee,(PTS_COMMON_INFO*) &pTS,hdr->addr2,TID,RX_DIR,true); + if(TID !=0 && TID !=3) + { + ieee->bis_any_nonbepkts = true; + } + } +#endif +//added by amy for reorder + /* skb: hdr + (possible reassembled) full plaintext payload */ + payload = skb->data + hdrlen; + //ethertype = (payload[6] << 8) | payload[7]; + rxb = (struct ieee80211_rxb*)kmalloc(sizeof(struct ieee80211_rxb),GFP_ATOMIC); + if(rxb == NULL) + { + IEEE80211_DEBUG(IEEE80211_DL_ERR,"%s(): kmalloc rxb error\n",__FUNCTION__); + goto rx_dropped; + } + /* to parse amsdu packets */ + /* qos data packets & reserved bit is 1 */ + if(parse_subframe(skb,rx_stats,rxb,src,dst) == 0) { + /* only to free rxb, and not submit the packets to upper layer */ + for(i =0; i < rxb->nr_subframes; i++) { + dev_kfree_skb(rxb->subframes[i]); + } + kfree(rxb); + rxb = NULL; + goto rx_dropped; + } + + ieee->last_rx_ps_time = jiffies; +//added by amy for reorder + if(ieee->pHTInfo->bCurRxReorderEnable == false ||pTS == NULL){ +//added by amy for reorder + for(i = 0; i<rxb->nr_subframes; i++) { + struct sk_buff *sub_skb = rxb->subframes[i]; + + if (sub_skb) { + /* convert hdr + possible LLC headers into Ethernet header */ + ethertype = (sub_skb->data[6] << 8) | sub_skb->data[7]; + if (sub_skb->len >= 8 && + ((memcmp(sub_skb->data, rfc1042_header, SNAP_SIZE) == 0 && + ethertype != ETH_P_AARP && ethertype != ETH_P_IPX) || + memcmp(sub_skb->data, bridge_tunnel_header, SNAP_SIZE) == 0)) { + /* remove RFC1042 or Bridge-Tunnel encapsulation and + * replace EtherType */ + skb_pull(sub_skb, SNAP_SIZE); + memcpy(skb_push(sub_skb, ETH_ALEN), src, ETH_ALEN); + memcpy(skb_push(sub_skb, ETH_ALEN), dst, ETH_ALEN); + } else { + u16 len; + /* Leave Ethernet header part of hdr and full payload */ + len = htons(sub_skb->len); + memcpy(skb_push(sub_skb, 2), &len, 2); + memcpy(skb_push(sub_skb, ETH_ALEN), src, ETH_ALEN); + memcpy(skb_push(sub_skb, ETH_ALEN), dst, ETH_ALEN); + } + + stats->rx_packets++; + stats->rx_bytes += sub_skb->len; + if(is_multicast_ether_addr(dst)) { + stats->multicast++; + } + + /* Indicat the packets to upper layer */ + //printk("0skb_len(%d)\n", skb->len); + sub_skb->protocol = eth_type_trans(sub_skb, dev); + memset(sub_skb->cb, 0, sizeof(sub_skb->cb)); + sub_skb->dev = dev; + sub_skb->ip_summed = CHECKSUM_NONE; /* 802.11 crc not sufficient */ + //skb->ip_summed = CHECKSUM_UNNECESSARY; /* 802.11 crc not sufficient */ + //printk("1skb_len(%d)\n", skb->len); + netif_rx(sub_skb); + } + } + kfree(rxb); + rxb = NULL; + + } + else + { + IEEE80211_DEBUG(IEEE80211_DL_REORDER,"%s(): REORDER ENABLE AND PTS not NULL, and we will enter RxReorderIndicatePacket()\n",__FUNCTION__); + RxReorderIndicatePacket(ieee, rxb, pTS, SeqNum); + } +#ifndef JOHN_NOCPY + dev_kfree_skb(skb); +#endif + + rx_exit: +#ifdef NOT_YET + if (sta) + hostap_handle_sta_release(sta); +#endif + return 1; + + rx_dropped: + if (rxb != NULL) + { + kfree(rxb); + rxb = NULL; + } + stats->rx_dropped++; + + /* Returning 0 indicates to caller that we have not handled the SKB-- + * so it is still allocated and can be used again by underlying + * hardware as a DMA target */ + return 0; +} + +#define MGMT_FRAME_FIXED_PART_LENGTH 0x24 + +static u8 qos_oui[QOS_OUI_LEN] = { 0x00, 0x50, 0xF2 }; + +/* +* Make ther structure we read from the beacon packet has +* the right values +*/ +static int ieee80211_verify_qos_info(struct ieee80211_qos_information_element + *info_element, int sub_type) +{ + + if (info_element->qui_subtype != sub_type) + return -1; + if (memcmp(info_element->qui, qos_oui, QOS_OUI_LEN)) + return -1; + if (info_element->qui_type != QOS_OUI_TYPE) + return -1; + if (info_element->version != QOS_VERSION_1) + return -1; + + return 0; +} + + +/* + * Parse a QoS parameter element + */ +static int ieee80211_read_qos_param_element(struct ieee80211_qos_parameter_info + *element_param, struct ieee80211_info_element + *info_element) +{ + int ret = 0; + u16 size = sizeof(struct ieee80211_qos_parameter_info) - 2; + + if ((info_element == NULL) || (element_param == NULL)) + return -1; + + if (info_element->id == QOS_ELEMENT_ID && info_element->len == size) { + memcpy(element_param->info_element.qui, info_element->data, + info_element->len); + element_param->info_element.elementID = info_element->id; + element_param->info_element.length = info_element->len; + } else + ret = -1; + if (ret == 0) + ret = ieee80211_verify_qos_info(&element_param->info_element, + QOS_OUI_PARAM_SUB_TYPE); + return ret; +} + +/* + * Parse a QoS information element + */ +static int ieee80211_read_qos_info_element(struct + ieee80211_qos_information_element + *element_info, struct ieee80211_info_element + *info_element) +{ + int ret = 0; + u16 size = sizeof(struct ieee80211_qos_information_element) - 2; + + if (element_info == NULL) + return -1; + if (info_element == NULL) + return -1; + + if ((info_element->id == QOS_ELEMENT_ID) && (info_element->len == size)) { + memcpy(element_info->qui, info_element->data, + info_element->len); + element_info->elementID = info_element->id; + element_info->length = info_element->len; + } else + ret = -1; + + if (ret == 0) + ret = ieee80211_verify_qos_info(element_info, + QOS_OUI_INFO_SUB_TYPE); + return ret; +} + + +/* + * Write QoS parameters from the ac parameters. + */ +static int ieee80211_qos_convert_ac_to_parameters(struct + ieee80211_qos_parameter_info + *param_elm, struct + ieee80211_qos_parameters + *qos_param) +{ + int rc = 0; + int i; + struct ieee80211_qos_ac_parameter *ac_params; + u8 aci; + //u8 cw_min; + //u8 cw_max; + + for (i = 0; i < QOS_QUEUE_NUM; i++) { + ac_params = &(param_elm->ac_params_record[i]); + + aci = (ac_params->aci_aifsn & 0x60) >> 5; + + if(aci >= QOS_QUEUE_NUM) + continue; + qos_param->aifs[aci] = (ac_params->aci_aifsn) & 0x0f; + + /* WMM spec P.11: The minimum value for AIFSN shall be 2 */ + qos_param->aifs[aci] = (qos_param->aifs[aci] < 2) ? 2:qos_param->aifs[aci]; + + qos_param->cw_min[aci] = ac_params->ecw_min_max & 0x0F; + + qos_param->cw_max[aci] = (ac_params->ecw_min_max & 0xF0) >> 4; + + qos_param->flag[aci] = + (ac_params->aci_aifsn & 0x10) ? 0x01 : 0x00; + qos_param->tx_op_limit[aci] = le16_to_cpu(ac_params->tx_op_limit); + } + return rc; +} + +/* + * we have a generic data element which it may contain QoS information or + * parameters element. check the information element length to decide + * which type to read + */ +static int ieee80211_parse_qos_info_param_IE(struct ieee80211_info_element + *info_element, + struct ieee80211_network *network) +{ + int rc = 0; + struct ieee80211_qos_parameters *qos_param = NULL; + struct ieee80211_qos_information_element qos_info_element; + + rc = ieee80211_read_qos_info_element(&qos_info_element, info_element); + + if (rc == 0) { + network->qos_data.param_count = qos_info_element.ac_info & 0x0F; + network->flags |= NETWORK_HAS_QOS_INFORMATION; + } else { + struct ieee80211_qos_parameter_info param_element; + + rc = ieee80211_read_qos_param_element(¶m_element, + info_element); + if (rc == 0) { + qos_param = &(network->qos_data.parameters); + ieee80211_qos_convert_ac_to_parameters(¶m_element, + qos_param); + network->flags |= NETWORK_HAS_QOS_PARAMETERS; + network->qos_data.param_count = + param_element.info_element.ac_info & 0x0F; + } + } + + if (rc == 0) { + IEEE80211_DEBUG_QOS("QoS is supported\n"); + network->qos_data.supported = 1; + } + return rc; +} + +#ifdef CONFIG_IEEE80211_DEBUG +#define MFIE_STRING(x) case MFIE_TYPE_ ##x: return #x + +static const char *get_info_element_string(u16 id) +{ + switch (id) { + MFIE_STRING(SSID); + MFIE_STRING(RATES); + MFIE_STRING(FH_SET); + MFIE_STRING(DS_SET); + MFIE_STRING(CF_SET); + MFIE_STRING(TIM); + MFIE_STRING(IBSS_SET); + MFIE_STRING(COUNTRY); + MFIE_STRING(HOP_PARAMS); + MFIE_STRING(HOP_TABLE); + MFIE_STRING(REQUEST); + MFIE_STRING(CHALLENGE); + MFIE_STRING(POWER_CONSTRAINT); + MFIE_STRING(POWER_CAPABILITY); + MFIE_STRING(TPC_REQUEST); + MFIE_STRING(TPC_REPORT); + MFIE_STRING(SUPP_CHANNELS); + MFIE_STRING(CSA); + MFIE_STRING(MEASURE_REQUEST); + MFIE_STRING(MEASURE_REPORT); + MFIE_STRING(QUIET); + MFIE_STRING(IBSS_DFS); + // MFIE_STRING(ERP_INFO); + MFIE_STRING(RSN); + MFIE_STRING(RATES_EX); + MFIE_STRING(GENERIC); + MFIE_STRING(QOS_PARAMETER); + default: + return "UNKNOWN"; + } +} +#endif + +#ifdef ENABLE_DOT11D +static inline void ieee80211_extract_country_ie( + struct ieee80211_device *ieee, + struct ieee80211_info_element *info_element, + struct ieee80211_network *network, + u8 * addr2 +) +{ + if(IS_DOT11D_ENABLE(ieee)) + { + if(info_element->len!= 0) + { + memcpy(network->CountryIeBuf, info_element->data, info_element->len); + network->CountryIeLen = info_element->len; + + if(!IS_COUNTRY_IE_VALID(ieee)) + { + Dot11d_UpdateCountryIe(ieee, addr2, info_element->len, info_element->data); + } + } + + // + // 070305, rcnjko: I update country IE watch dog here because + // some AP (e.g. Cisco 1242) don't include country IE in their + // probe response frame. + // + if(IS_EQUAL_CIE_SRC(ieee, addr2) ) + { + UPDATE_CIE_WATCHDOG(ieee); + } + } + +} +#endif + +int ieee80211_parse_info_param(struct ieee80211_device *ieee, + struct ieee80211_info_element *info_element, + u16 length, + struct ieee80211_network *network, + struct ieee80211_rx_stats *stats) +{ + u8 i; + short offset; + u16 tmp_htcap_len=0; + u16 tmp_htinfo_len=0; + u16 ht_realtek_agg_len=0; + u8 ht_realtek_agg_buf[MAX_IE_LEN]; +// u16 broadcom_len = 0; +#ifdef CONFIG_IEEE80211_DEBUG + char rates_str[64]; + char *p; +#endif + + while (length >= sizeof(*info_element)) { + if (sizeof(*info_element) + info_element->len > length) { + IEEE80211_DEBUG_MGMT("Info elem: parse failed: " + "info_element->len + 2 > left : " + "info_element->len+2=%zd left=%d, id=%d.\n", + info_element->len + + sizeof(*info_element), + length, info_element->id); + /* We stop processing but don't return an error here + * because some misbehaviour APs break this rule. ie. + * Orinoco AP1000. */ + break; + } + + switch (info_element->id) { + case MFIE_TYPE_SSID: + if (ieee80211_is_empty_essid(info_element->data, + info_element->len)) { + network->flags |= NETWORK_EMPTY_ESSID; + break; + } + + network->ssid_len = min(info_element->len, + (u8) IW_ESSID_MAX_SIZE); + memcpy(network->ssid, info_element->data, network->ssid_len); + if (network->ssid_len < IW_ESSID_MAX_SIZE) + memset(network->ssid + network->ssid_len, 0, + IW_ESSID_MAX_SIZE - network->ssid_len); + + IEEE80211_DEBUG_MGMT("MFIE_TYPE_SSID: '%s' len=%d.\n", + network->ssid, network->ssid_len); + break; + + case MFIE_TYPE_RATES: +#ifdef CONFIG_IEEE80211_DEBUG + p = rates_str; +#endif + network->rates_len = min(info_element->len, + MAX_RATES_LENGTH); + for (i = 0; i < network->rates_len; i++) { + network->rates[i] = info_element->data[i]; +#ifdef CONFIG_IEEE80211_DEBUG + p += snprintf(p, sizeof(rates_str) - + (p - rates_str), "%02X ", + network->rates[i]); +#endif + if (ieee80211_is_ofdm_rate + (info_element->data[i])) { + network->flags |= NETWORK_HAS_OFDM; + if (info_element->data[i] & + IEEE80211_BASIC_RATE_MASK) + network->flags &= + ~NETWORK_HAS_CCK; + } + } + + IEEE80211_DEBUG_MGMT("MFIE_TYPE_RATES: '%s' (%d)\n", + rates_str, network->rates_len); + break; + + case MFIE_TYPE_RATES_EX: +#ifdef CONFIG_IEEE80211_DEBUG + p = rates_str; +#endif + network->rates_ex_len = min(info_element->len, + MAX_RATES_EX_LENGTH); + for (i = 0; i < network->rates_ex_len; i++) { + network->rates_ex[i] = info_element->data[i]; +#ifdef CONFIG_IEEE80211_DEBUG + p += snprintf(p, sizeof(rates_str) - + (p - rates_str), "%02X ", + network->rates[i]); +#endif + if (ieee80211_is_ofdm_rate + (info_element->data[i])) { + network->flags |= NETWORK_HAS_OFDM; + if (info_element->data[i] & + IEEE80211_BASIC_RATE_MASK) + network->flags &= + ~NETWORK_HAS_CCK; + } + } + + IEEE80211_DEBUG_MGMT("MFIE_TYPE_RATES_EX: '%s' (%d)\n", + rates_str, network->rates_ex_len); + break; + + case MFIE_TYPE_DS_SET: + IEEE80211_DEBUG_MGMT("MFIE_TYPE_DS_SET: %d\n", + info_element->data[0]); + network->channel = info_element->data[0]; + break; + + case MFIE_TYPE_FH_SET: + IEEE80211_DEBUG_MGMT("MFIE_TYPE_FH_SET: ignored\n"); + break; + + case MFIE_TYPE_CF_SET: + IEEE80211_DEBUG_MGMT("MFIE_TYPE_CF_SET: ignored\n"); + break; + + case MFIE_TYPE_TIM: + if(info_element->len < 4) + break; + + network->tim.tim_count = info_element->data[0]; + network->tim.tim_period = info_element->data[1]; + + network->dtim_period = info_element->data[1]; + if(ieee->state != IEEE80211_LINKED) + break; +#if 0 + network->last_dtim_sta_time[0] = stats->mac_time[0]; +#else + //we use jiffies for legacy Power save + network->last_dtim_sta_time[0] = jiffies; +#endif + network->last_dtim_sta_time[1] = stats->mac_time[1]; + + network->dtim_data = IEEE80211_DTIM_VALID; + + if(info_element->data[0] != 0) + break; + + if(info_element->data[2] & 1) + network->dtim_data |= IEEE80211_DTIM_MBCAST; + + offset = (info_element->data[2] >> 1)*2; + + //printk("offset1:%x aid:%x\n",offset, ieee->assoc_id); + + if(ieee->assoc_id < 8*offset || + ieee->assoc_id > 8*(offset + info_element->len -3)) + + break; + + offset = (ieee->assoc_id / 8) - offset;// + ((aid % 8)? 0 : 1) ; + + if(info_element->data[3+offset] & (1<<(ieee->assoc_id%8))) + network->dtim_data |= IEEE80211_DTIM_UCAST; + + //IEEE80211_DEBUG_MGMT("MFIE_TYPE_TIM: partially ignored\n"); + break; + + case MFIE_TYPE_ERP: + network->erp_value = info_element->data[0]; + network->flags |= NETWORK_HAS_ERP_VALUE; + IEEE80211_DEBUG_MGMT("MFIE_TYPE_ERP_SET: %d\n", + network->erp_value); + break; + case MFIE_TYPE_IBSS_SET: + network->atim_window = info_element->data[0]; + IEEE80211_DEBUG_MGMT("MFIE_TYPE_IBSS_SET: %d\n", + network->atim_window); + break; + + case MFIE_TYPE_CHALLENGE: + IEEE80211_DEBUG_MGMT("MFIE_TYPE_CHALLENGE: ignored\n"); + break; + + case MFIE_TYPE_GENERIC: + IEEE80211_DEBUG_MGMT("MFIE_TYPE_GENERIC: %d bytes\n", + info_element->len); + if (!ieee80211_parse_qos_info_param_IE(info_element, + network)) + break; + + if (info_element->len >= 4 && + info_element->data[0] == 0x00 && + info_element->data[1] == 0x50 && + info_element->data[2] == 0xf2 && + info_element->data[3] == 0x01) { + network->wpa_ie_len = min(info_element->len + 2, + MAX_WPA_IE_LEN); + memcpy(network->wpa_ie, info_element, + network->wpa_ie_len); + break; + } + +#ifdef THOMAS_TURBO + if (info_element->len == 7 && + info_element->data[0] == 0x00 && + info_element->data[1] == 0xe0 && + info_element->data[2] == 0x4c && + info_element->data[3] == 0x01 && + info_element->data[4] == 0x02) { + network->Turbo_Enable = 1; + } +#endif + + //for HTcap and HTinfo parameters + if(tmp_htcap_len == 0){ + if(info_element->len >= 4 && + info_element->data[0] == 0x00 && + info_element->data[1] == 0x90 && + info_element->data[2] == 0x4c && + info_element->data[3] == 0x033){ + + tmp_htcap_len = min(info_element->len,(u8)MAX_IE_LEN); + if(tmp_htcap_len != 0){ + network->bssht.bdHTSpecVer = HT_SPEC_VER_EWC; + network->bssht.bdHTCapLen = tmp_htcap_len > sizeof(network->bssht.bdHTCapBuf)?\ + sizeof(network->bssht.bdHTCapBuf):tmp_htcap_len; + memcpy(network->bssht.bdHTCapBuf,info_element->data,network->bssht.bdHTCapLen); + } + } + if(tmp_htcap_len != 0){ + network->bssht.bdSupportHT = true; + network->bssht.bdHT1R = ((((PHT_CAPABILITY_ELE)(network->bssht.bdHTCapBuf))->MCS[1]) == 0); + }else{ + network->bssht.bdSupportHT = false; + network->bssht.bdHT1R = false; + } + } + + + if(tmp_htinfo_len == 0){ + if(info_element->len >= 4 && + info_element->data[0] == 0x00 && + info_element->data[1] == 0x90 && + info_element->data[2] == 0x4c && + info_element->data[3] == 0x034){ + + tmp_htinfo_len = min(info_element->len,(u8)MAX_IE_LEN); + if(tmp_htinfo_len != 0){ + network->bssht.bdHTSpecVer = HT_SPEC_VER_EWC; + if(tmp_htinfo_len){ + network->bssht.bdHTInfoLen = tmp_htinfo_len > sizeof(network->bssht.bdHTInfoBuf)?\ + sizeof(network->bssht.bdHTInfoBuf):tmp_htinfo_len; + memcpy(network->bssht.bdHTInfoBuf,info_element->data,network->bssht.bdHTInfoLen); + } + + } + + } + } + + if(ieee->aggregation){ + if(network->bssht.bdSupportHT){ + if(info_element->len >= 4 && + info_element->data[0] == 0x00 && + info_element->data[1] == 0xe0 && + info_element->data[2] == 0x4c && + info_element->data[3] == 0x02){ + + ht_realtek_agg_len = min(info_element->len,(u8)MAX_IE_LEN); + memcpy(ht_realtek_agg_buf,info_element->data,info_element->len); + + } + if(ht_realtek_agg_len >= 5){ + network->realtek_cap_exit = true; + network->bssht.bdRT2RTAggregation = true; + + if((ht_realtek_agg_buf[4] == 1) && (ht_realtek_agg_buf[5] & 0x02)) + network->bssht.bdRT2RTLongSlotTime = true; + + if((ht_realtek_agg_buf[4]==1) && (ht_realtek_agg_buf[5] & RT_HT_CAP_USE_92SE)) + { + network->bssht.RT2RT_HT_Mode |= RT_HT_CAP_USE_92SE; + //bssDesc->Vender = HT_IOT_PEER_REALTEK_92SE; + } + } + } + + } + + //if(tmp_htcap_len !=0 || tmp_htinfo_len != 0) + { + if((info_element->len >= 3 && + info_element->data[0] == 0x00 && + info_element->data[1] == 0x05 && + info_element->data[2] == 0xb5) || + (info_element->len >= 3 && + info_element->data[0] == 0x00 && + info_element->data[1] == 0x0a && + info_element->data[2] == 0xf7) || + (info_element->len >= 3 && + info_element->data[0] == 0x00 && + info_element->data[1] == 0x10 && + info_element->data[2] == 0x18)){ + + network->broadcom_cap_exist = true; + + } + } +#if 0 + if (tmp_htcap_len !=0) + { + u16 cap_ext = ((PHT_CAPABILITY_ELE)&info_element->data[0])->ExtHTCapInfo; + if ((cap_ext & 0x0c00) == 0x0c00) + { + network->ralink_cap_exist = true; + } + } +#endif + if(info_element->len >= 3 && + info_element->data[0] == 0x00 && + info_element->data[1] == 0x0c && + info_element->data[2] == 0x43) + { + network->ralink_cap_exist = true; + } + else + network->ralink_cap_exist = false; + //added by amy for atheros AP + if((info_element->len >= 3 && + info_element->data[0] == 0x00 && + info_element->data[1] == 0x03 && + info_element->data[2] == 0x7f) || + (info_element->len >= 3 && + info_element->data[0] == 0x00 && + info_element->data[1] == 0x13 && + info_element->data[2] == 0x74)) + { + // printk("========>%s(): athros AP is exist\n",__FUNCTION__); + network->atheros_cap_exist = true; + } + else + network->atheros_cap_exist = false; + + if ((info_element->len >= 3 && + info_element->data[0] == 0x00 && + info_element->data[1] == 0x50 && + info_element->data[2] == 0x43) ) + { + network->marvell_cap_exist = true; + } + else + network->marvell_cap_exist = false; + + if(info_element->len >= 3 && + info_element->data[0] == 0x00 && + info_element->data[1] == 0x40 && + info_element->data[2] == 0x96) + { + network->cisco_cap_exist = true; + } + else + network->cisco_cap_exist = false; + //added by amy for LEAP of cisco + if(info_element->len > 4 && + info_element->data[0] == 0x00 && + info_element->data[1] == 0x40 && + info_element->data[2] == 0x96 && + info_element->data[3] == 0x01) + { + if(info_element->len == 6) + { + memcpy(network->CcxRmState, &info_element[4], 2); + if(network->CcxRmState[0] != 0) + { + network->bCcxRmEnable = true; + } + else + network->bCcxRmEnable = false; + // + // CCXv4 Table 59-1 MBSSID Masks. + // + network->MBssidMask = network->CcxRmState[1] & 0x07; + if(network->MBssidMask != 0) + { + network->bMBssidValid = true; + network->MBssidMask = 0xff << (network->MBssidMask); + cpMacAddr(network->MBssid, network->bssid); + network->MBssid[5] &= network->MBssidMask; + } + else + { + network->bMBssidValid = false; + } + } + else + { + network->bCcxRmEnable = false; + } + } + if(info_element->len > 4 && + info_element->data[0] == 0x00 && + info_element->data[1] == 0x40 && + info_element->data[2] == 0x96 && + info_element->data[3] == 0x03) + { + if(info_element->len == 5) + { + network->bWithCcxVerNum = true; + network->BssCcxVerNumber = info_element->data[4]; + } + else + { + network->bWithCcxVerNum = false; + network->BssCcxVerNumber = 0; + } + } + break; + + case MFIE_TYPE_RSN: + IEEE80211_DEBUG_MGMT("MFIE_TYPE_RSN: %d bytes\n", + info_element->len); + network->rsn_ie_len = min(info_element->len + 2, + MAX_WPA_IE_LEN); + memcpy(network->rsn_ie, info_element, + network->rsn_ie_len); + break; + + //HT related element. + case MFIE_TYPE_HT_CAP: + IEEE80211_DEBUG_SCAN("MFIE_TYPE_HT_CAP: %d bytes\n", + info_element->len); + tmp_htcap_len = min(info_element->len,(u8)MAX_IE_LEN); + if(tmp_htcap_len != 0){ + network->bssht.bdHTSpecVer = HT_SPEC_VER_EWC; + network->bssht.bdHTCapLen = tmp_htcap_len > sizeof(network->bssht.bdHTCapBuf)?\ + sizeof(network->bssht.bdHTCapBuf):tmp_htcap_len; + memcpy(network->bssht.bdHTCapBuf,info_element->data,network->bssht.bdHTCapLen); + + //If peer is HT, but not WMM, call QosSetLegacyWMMParamWithHT() + // windows driver will update WMM parameters each beacon received once connected + // Linux driver is a bit different. + network->bssht.bdSupportHT = true; + network->bssht.bdHT1R = ((((PHT_CAPABILITY_ELE)(network->bssht.bdHTCapBuf))->MCS[1]) == 0); + } + else{ + network->bssht.bdSupportHT = false; + network->bssht.bdHT1R = false; + } + break; + + + case MFIE_TYPE_HT_INFO: + IEEE80211_DEBUG_SCAN("MFIE_TYPE_HT_INFO: %d bytes\n", + info_element->len); + tmp_htinfo_len = min(info_element->len,(u8)MAX_IE_LEN); + if(tmp_htinfo_len){ + network->bssht.bdHTSpecVer = HT_SPEC_VER_IEEE; + network->bssht.bdHTInfoLen = tmp_htinfo_len > sizeof(network->bssht.bdHTInfoBuf)?\ + sizeof(network->bssht.bdHTInfoBuf):tmp_htinfo_len; + memcpy(network->bssht.bdHTInfoBuf,info_element->data,network->bssht.bdHTInfoLen); + } + break; + + case MFIE_TYPE_AIRONET: + IEEE80211_DEBUG_SCAN("MFIE_TYPE_AIRONET: %d bytes\n", + info_element->len); + if(info_element->len >IE_CISCO_FLAG_POSITION) + { + network->bWithAironetIE = true; + + // CCX 1 spec v1.13, A01.1 CKIP Negotiation (page23): + // "A Cisco access point advertises support for CKIP in beacon and probe response packets, + // by adding an Aironet element and setting one or both of the CKIP negotiation bits." + if( (info_element->data[IE_CISCO_FLAG_POSITION]&SUPPORT_CKIP_MIC) || + (info_element->data[IE_CISCO_FLAG_POSITION]&SUPPORT_CKIP_PK) ) + { + network->bCkipSupported = true; + } + else + { + network->bCkipSupported = false; + } + } + else + { + network->bWithAironetIE = false; + network->bCkipSupported = false; + } + break; + case MFIE_TYPE_QOS_PARAMETER: + printk(KERN_ERR + "QoS Error need to parse QOS_PARAMETER IE\n"); + break; + +#ifdef ENABLE_DOT11D + case MFIE_TYPE_COUNTRY: + IEEE80211_DEBUG_SCAN("MFIE_TYPE_COUNTRY: %d bytes\n", + info_element->len); + //printk("=====>Receive <%s> Country IE\n",network->ssid); + ieee80211_extract_country_ie(ieee, info_element, network, network->bssid);//addr2 is same as addr3 when from an AP + break; +#endif +/* TODO */ +#if 0 + /* 802.11h */ + case MFIE_TYPE_POWER_CONSTRAINT: + network->power_constraint = info_element->data[0]; + network->flags |= NETWORK_HAS_POWER_CONSTRAINT; + break; + + case MFIE_TYPE_CSA: + network->power_constraint = info_element->data[0]; + network->flags |= NETWORK_HAS_CSA; + break; + + case MFIE_TYPE_QUIET: + network->quiet.count = info_element->data[0]; + network->quiet.period = info_element->data[1]; + network->quiet.duration = info_element->data[2]; + network->quiet.offset = info_element->data[3]; + network->flags |= NETWORK_HAS_QUIET; + break; + + case MFIE_TYPE_IBSS_DFS: + if (network->ibss_dfs) + break; + network->ibss_dfs = kmemdup(info_element->data, + info_element->len, + GFP_ATOMIC); + if (!network->ibss_dfs) + return 1; + network->flags |= NETWORK_HAS_IBSS_DFS; + break; + + case MFIE_TYPE_TPC_REPORT: + network->tpc_report.transmit_power = + info_element->data[0]; + network->tpc_report.link_margin = info_element->data[1]; + network->flags |= NETWORK_HAS_TPC_REPORT; + break; +#endif + default: + IEEE80211_DEBUG_MGMT + ("Unsupported info element: %s (%d)\n", + get_info_element_string(info_element->id), + info_element->id); + break; + } + + length -= sizeof(*info_element) + info_element->len; + info_element = + (struct ieee80211_info_element *)&info_element-> + data[info_element->len]; + } + + if(!network->atheros_cap_exist && !network->broadcom_cap_exist && + !network->cisco_cap_exist && !network->ralink_cap_exist && !network->bssht.bdRT2RTAggregation) + { + network->unknown_cap_exist = true; + } + else + { + network->unknown_cap_exist = false; + } + return 0; +} + +static inline u8 ieee80211_SignalStrengthTranslate( + u8 CurrSS + ) +{ + u8 RetSS; + + // Step 1. Scale mapping. + if(CurrSS >= 71 && CurrSS <= 100) + { + RetSS = 90 + ((CurrSS - 70) / 3); + } + else if(CurrSS >= 41 && CurrSS <= 70) + { + RetSS = 78 + ((CurrSS - 40) / 3); + } + else if(CurrSS >= 31 && CurrSS <= 40) + { + RetSS = 66 + (CurrSS - 30); + } + else if(CurrSS >= 21 && CurrSS <= 30) + { + RetSS = 54 + (CurrSS - 20); + } + else if(CurrSS >= 5 && CurrSS <= 20) + { + RetSS = 42 + (((CurrSS - 5) * 2) / 3); + } + else if(CurrSS == 4) + { + RetSS = 36; + } + else if(CurrSS == 3) + { + RetSS = 27; + } + else if(CurrSS == 2) + { + RetSS = 18; + } + else if(CurrSS == 1) + { + RetSS = 9; + } + else + { + RetSS = CurrSS; + } + //RT_TRACE(COMP_DBG, DBG_LOUD, ("##### After Mapping: LastSS: %d, CurrSS: %d, RetSS: %d\n", LastSS, CurrSS, RetSS)); + + // Step 2. Smoothing. + + //RT_TRACE(COMP_DBG, DBG_LOUD, ("$$$$$ After Smoothing: LastSS: %d, CurrSS: %d, RetSS: %d\n", LastSS, CurrSS, RetSS)); + + return RetSS; +} + +long ieee80211_translate_todbm(u8 signal_strength_index )// 0-100 index. +{ + long signal_power; // in dBm. + + // Translate to dBm (x=0.5y-95). + signal_power = (long)((signal_strength_index + 1) >> 1); + signal_power -= 95; + + return signal_power; +} + +static inline int ieee80211_network_init( + struct ieee80211_device *ieee, + struct ieee80211_probe_response *beacon, + struct ieee80211_network *network, + struct ieee80211_rx_stats *stats) +{ +#ifdef CONFIG_IEEE80211_DEBUG + //char rates_str[64]; + //char *p; +#endif + + network->qos_data.active = 0; + network->qos_data.supported = 0; + network->qos_data.param_count = 0; + network->qos_data.old_param_count = 0; + + /* Pull out fixed field data */ + memcpy(network->bssid, beacon->header.addr3, ETH_ALEN); + network->capability = le16_to_cpu(beacon->capability); + network->last_scanned = jiffies; + network->time_stamp[0] = le32_to_cpu(beacon->time_stamp[0]); + network->time_stamp[1] = le32_to_cpu(beacon->time_stamp[1]); + network->beacon_interval = le32_to_cpu(beacon->beacon_interval); + /* Where to pull this? beacon->listen_interval;*/ + network->listen_interval = 0x0A; + network->rates_len = network->rates_ex_len = 0; + network->last_associate = 0; + network->ssid_len = 0; + network->flags = 0; + network->atim_window = 0; + network->erp_value = (network->capability & WLAN_CAPABILITY_IBSS) ? + 0x3 : 0x0; + network->berp_info_valid = false; + network->broadcom_cap_exist = false; + network->ralink_cap_exist = false; + network->atheros_cap_exist = false; + network->cisco_cap_exist = false; + network->unknown_cap_exist = false; + network->realtek_cap_exit = false; + network->marvell_cap_exist = false; +#ifdef THOMAS_TURBO + network->Turbo_Enable = 0; +#endif +#ifdef ENABLE_DOT11D + network->CountryIeLen = 0; + memset(network->CountryIeBuf, 0, MAX_IE_LEN); +#endif +//Initialize HT parameters + //ieee80211_ht_initialize(&network->bssht); + HTInitializeBssDesc(&network->bssht); + if (stats->freq == IEEE80211_52GHZ_BAND) { + /* for A band (No DS info) */ + network->channel = stats->received_channel; + } else + network->flags |= NETWORK_HAS_CCK; + + network->wpa_ie_len = 0; + network->rsn_ie_len = 0; + + if (ieee80211_parse_info_param + (ieee,beacon->info_element, stats->len - sizeof(*beacon), network, stats)) + return 1; + + network->mode = 0; + if (stats->freq == IEEE80211_52GHZ_BAND) + network->mode = IEEE_A; + else { + if (network->flags & NETWORK_HAS_OFDM) + network->mode |= IEEE_G; + if (network->flags & NETWORK_HAS_CCK) + network->mode |= IEEE_B; + } + + if (network->mode == 0) { + IEEE80211_DEBUG_SCAN("Filtered out '%s (" MAC_FMT ")' " + "network.\n", + escape_essid(network->ssid, + network->ssid_len), + MAC_ARG(network->bssid)); + return 1; + } + + if(network->bssht.bdSupportHT){ + if(network->mode == IEEE_A) + network->mode = IEEE_N_5G; + else if(network->mode & (IEEE_G | IEEE_B)) + network->mode = IEEE_N_24G; + } + if (ieee80211_is_empty_essid(network->ssid, network->ssid_len)) + network->flags |= NETWORK_EMPTY_ESSID; + +#if 1 + stats->signal = 30 + (stats->SignalStrength * 70) / 100; + //stats->signal = ieee80211_SignalStrengthTranslate(stats->signal); + stats->noise = ieee80211_translate_todbm((u8)(100-stats->signal)) -25; +#endif + + memcpy(&network->stats, stats, sizeof(network->stats)); + + return 0; +} + +static inline int is_same_network(struct ieee80211_network *src, + struct ieee80211_network *dst, struct ieee80211_device* ieee) +{ + /* A network is only a duplicate if the channel, BSSID, ESSID + * and the capability field (in particular IBSS and BSS) all match. + * We treat all <hidden> with the same BSSID and channel + * as one network */ + return //((src->ssid_len == dst->ssid_len) && + (((src->ssid_len == dst->ssid_len) || (ieee->iw_mode == IW_MODE_INFRA)) && + (src->channel == dst->channel) && + !memcmp(src->bssid, dst->bssid, ETH_ALEN) && + //!memcmp(src->ssid, dst->ssid, src->ssid_len) && + (!memcmp(src->ssid, dst->ssid, src->ssid_len) || (ieee->iw_mode == IW_MODE_INFRA)) && + ((src->capability & WLAN_CAPABILITY_IBSS) == + (dst->capability & WLAN_CAPABILITY_IBSS)) && + ((src->capability & WLAN_CAPABILITY_BSS) == + (dst->capability & WLAN_CAPABILITY_BSS))); +} + +static inline void update_network(struct ieee80211_network *dst, + struct ieee80211_network *src) +{ + int qos_active; + u8 old_param; + + memcpy(&dst->stats, &src->stats, sizeof(struct ieee80211_rx_stats)); + dst->capability = src->capability; + memcpy(dst->rates, src->rates, src->rates_len); + dst->rates_len = src->rates_len; + memcpy(dst->rates_ex, src->rates_ex, src->rates_ex_len); + dst->rates_ex_len = src->rates_ex_len; + if(src->ssid_len > 0) + { + memset(dst->ssid, 0, dst->ssid_len); + dst->ssid_len = src->ssid_len; + memcpy(dst->ssid, src->ssid, src->ssid_len); + } + dst->mode = src->mode; + dst->flags = src->flags; + dst->time_stamp[0] = src->time_stamp[0]; + dst->time_stamp[1] = src->time_stamp[1]; + if (src->flags & NETWORK_HAS_ERP_VALUE) + { + dst->erp_value = src->erp_value; + dst->berp_info_valid = src->berp_info_valid = true; + } + dst->beacon_interval = src->beacon_interval; + dst->listen_interval = src->listen_interval; + dst->atim_window = src->atim_window; + dst->dtim_period = src->dtim_period; + dst->dtim_data = src->dtim_data; + dst->last_dtim_sta_time[0] = src->last_dtim_sta_time[0]; + dst->last_dtim_sta_time[1] = src->last_dtim_sta_time[1]; + memcpy(&dst->tim, &src->tim, sizeof(struct ieee80211_tim_parameters)); + + dst->bssht.bdSupportHT = src->bssht.bdSupportHT; + dst->bssht.bdRT2RTAggregation = src->bssht.bdRT2RTAggregation; + dst->bssht.bdHTCapLen= src->bssht.bdHTCapLen; + memcpy(dst->bssht.bdHTCapBuf,src->bssht.bdHTCapBuf,src->bssht.bdHTCapLen); + dst->bssht.bdHTInfoLen= src->bssht.bdHTInfoLen; + memcpy(dst->bssht.bdHTInfoBuf,src->bssht.bdHTInfoBuf,src->bssht.bdHTInfoLen); + dst->bssht.bdHTSpecVer = src->bssht.bdHTSpecVer; + dst->bssht.bdRT2RTLongSlotTime = src->bssht.bdRT2RTLongSlotTime; + dst->broadcom_cap_exist = src->broadcom_cap_exist; + dst->ralink_cap_exist = src->ralink_cap_exist; + dst->atheros_cap_exist = src->atheros_cap_exist; + dst->realtek_cap_exit = src->realtek_cap_exit; + dst->marvell_cap_exist = src->marvell_cap_exist; + dst->cisco_cap_exist = src->cisco_cap_exist; + dst->unknown_cap_exist = src->unknown_cap_exist; + memcpy(dst->wpa_ie, src->wpa_ie, src->wpa_ie_len); + dst->wpa_ie_len = src->wpa_ie_len; + memcpy(dst->rsn_ie, src->rsn_ie, src->rsn_ie_len); + dst->rsn_ie_len = src->rsn_ie_len; + + dst->last_scanned = jiffies; + /* qos related parameters */ + //qos_active = src->qos_data.active; + qos_active = dst->qos_data.active; + //old_param = dst->qos_data.old_param_count; + old_param = dst->qos_data.param_count; + if(dst->flags & NETWORK_HAS_QOS_MASK){ + //not update QOS paramter in beacon, as most AP will set all these parameter to 0.//WB + // printk("====>%s(), aifs:%x, %x\n", __FUNCTION__, dst->qos_data.parameters.aifs[0], src->qos_data.parameters.aifs[0]); + // memcpy(&dst->qos_data, &src->qos_data, + // sizeof(struct ieee80211_qos_data)); + } + else { + dst->qos_data.supported = src->qos_data.supported; + dst->qos_data.param_count = src->qos_data.param_count; + } + + if(dst->qos_data.supported == 1) { + dst->QoS_Enable = 1; + if(dst->ssid_len) + IEEE80211_DEBUG_QOS + ("QoS the network %s is QoS supported\n", + dst->ssid); + else + IEEE80211_DEBUG_QOS + ("QoS the network is QoS supported\n"); + } + dst->qos_data.active = qos_active; + dst->qos_data.old_param_count = old_param; + + /* dst->last_associate is not overwritten */ +#if 1 + dst->wmm_info = src->wmm_info; //sure to exist in beacon or probe response frame. + if(src->wmm_param[0].ac_aci_acm_aifsn|| \ + src->wmm_param[1].ac_aci_acm_aifsn|| \ + src->wmm_param[2].ac_aci_acm_aifsn|| \ + src->wmm_param[1].ac_aci_acm_aifsn) { + memcpy(dst->wmm_param, src->wmm_param, WME_AC_PRAM_LEN); + } + //dst->QoS_Enable = src->QoS_Enable; +#else + dst->QoS_Enable = 1;//for Rtl8187 simulation +#endif +#ifdef THOMAS_TURBO + dst->Turbo_Enable = src->Turbo_Enable; +#endif + +#ifdef ENABLE_DOT11D + dst->CountryIeLen = src->CountryIeLen; + memcpy(dst->CountryIeBuf, src->CountryIeBuf, src->CountryIeLen); +#endif + + //added by amy for LEAP + dst->bWithAironetIE = src->bWithAironetIE; + dst->bCkipSupported = src->bCkipSupported; + memcpy(dst->CcxRmState,src->CcxRmState,2); + dst->bCcxRmEnable = src->bCcxRmEnable; + dst->MBssidMask = src->MBssidMask; + dst->bMBssidValid = src->bMBssidValid; + memcpy(dst->MBssid,src->MBssid,6); + dst->bWithCcxVerNum = src->bWithCcxVerNum; + dst->BssCcxVerNumber = src->BssCcxVerNumber; + +} + +static inline int is_beacon(__le16 fc) +{ + return (WLAN_FC_GET_STYPE(le16_to_cpu(fc)) == IEEE80211_STYPE_BEACON); +} + +static inline void ieee80211_process_probe_response( + struct ieee80211_device *ieee, + struct ieee80211_probe_response *beacon, + struct ieee80211_rx_stats *stats) +{ + struct ieee80211_network network; + struct ieee80211_network *target; + struct ieee80211_network *oldest = NULL; +#ifdef CONFIG_IEEE80211_DEBUG + struct ieee80211_info_element *info_element = &beacon->info_element[0]; +#endif + unsigned long flags; + short renew; + //u8 wmm_info; + + memset(&network, 0, sizeof(struct ieee80211_network)); + IEEE80211_DEBUG_SCAN( + "'%s' (" MAC_FMT "): %c%c%c%c %c%c%c%c-%c%c%c%c %c%c%c%c\n", + escape_essid(info_element->data, info_element->len), + MAC_ARG(beacon->header.addr3), + (beacon->capability & (1<<0xf)) ? '1' : '0', + (beacon->capability & (1<<0xe)) ? '1' : '0', + (beacon->capability & (1<<0xd)) ? '1' : '0', + (beacon->capability & (1<<0xc)) ? '1' : '0', + (beacon->capability & (1<<0xb)) ? '1' : '0', + (beacon->capability & (1<<0xa)) ? '1' : '0', + (beacon->capability & (1<<0x9)) ? '1' : '0', + (beacon->capability & (1<<0x8)) ? '1' : '0', + (beacon->capability & (1<<0x7)) ? '1' : '0', + (beacon->capability & (1<<0x6)) ? '1' : '0', + (beacon->capability & (1<<0x5)) ? '1' : '0', + (beacon->capability & (1<<0x4)) ? '1' : '0', + (beacon->capability & (1<<0x3)) ? '1' : '0', + (beacon->capability & (1<<0x2)) ? '1' : '0', + (beacon->capability & (1<<0x1)) ? '1' : '0', + (beacon->capability & (1<<0x0)) ? '1' : '0'); + + if (ieee80211_network_init(ieee, beacon, &network, stats)) { + IEEE80211_DEBUG_SCAN("Dropped '%s' (" MAC_FMT ") via %s.\n", + escape_essid(info_element->data, + info_element->len), + MAC_ARG(beacon->header.addr3), + WLAN_FC_GET_STYPE(beacon->header.frame_ctl) == + IEEE80211_STYPE_PROBE_RESP ? + "PROBE RESPONSE" : "BEACON"); + return; + } + +#ifdef ENABLE_DOT11D + // For Asus EeePc request, + // (1) if wireless adapter receive get any 802.11d country code in AP beacon, + // wireless adapter should follow the country code. + // (2) If there is no any country code in beacon, + // then wireless adapter should do active scan from ch1~11 and + // passive scan from ch12~14 + + if( !IsLegalChannel(ieee, network.channel) ) + return; + if(ieee->bGlobalDomain) + { + if (WLAN_FC_GET_STYPE(beacon->header.frame_ctl) == IEEE80211_STYPE_PROBE_RESP) + { + // Case 1: Country code + if(IS_COUNTRY_IE_VALID(ieee) ) + { + if( !IsLegalChannel(ieee, network.channel) ) + { + printk("GetScanInfo(): For Country code, filter probe response at channel(%d).\n", network.channel); + return; + } + } + // Case 2: No any country code. + else + { + // Filter over channel ch12~14 + if(network.channel > 11) + { + printk("GetScanInfo(): For Global Domain, filter probe response at channel(%d).\n", network.channel); + return; + } + } + } + else + { + // Case 1: Country code + if(IS_COUNTRY_IE_VALID(ieee) ) + { + if( !IsLegalChannel(ieee, network.channel) ) + { + printk("GetScanInfo(): For Country code, filter beacon at channel(%d).\n",network.channel); + return; + } + } + // Case 2: No any country code. + else + { + // Filter over channel ch12~14 + if(network.channel > 14) + { + printk("GetScanInfo(): For Global Domain, filter beacon at channel(%d).\n",network.channel); + return; + } + } + } + } +#endif + + /* The network parsed correctly -- so now we scan our known networks + * to see if we can find it in our list. + * + * NOTE: This search is definitely not optimized. Once its doing + * the "right thing" we'll optimize it for efficiency if + * necessary */ + + /* Search for this entry in the list and update it if it is + * already there. */ + + spin_lock_irqsave(&ieee->lock, flags); + + if(is_same_network(&ieee->current_network, &network, ieee)) { + update_network(&ieee->current_network, &network); + if((ieee->current_network.mode == IEEE_N_24G || ieee->current_network.mode == IEEE_G) + && ieee->current_network.berp_info_valid){ + if(ieee->current_network.erp_value& ERP_UseProtection) + ieee->current_network.buseprotection = true; + else + ieee->current_network.buseprotection = false; + } + if(is_beacon(beacon->header.frame_ctl)) + { + if(ieee->state == IEEE80211_LINKED) + ieee->LinkDetectInfo.NumRecvBcnInPeriod++; + } + else //hidden AP + network.flags = (~NETWORK_EMPTY_ESSID & network.flags)|(NETWORK_EMPTY_ESSID & ieee->current_network.flags); + } + + list_for_each_entry(target, &ieee->network_list, list) { + if (is_same_network(target, &network, ieee)) + break; + if ((oldest == NULL) || + (target->last_scanned < oldest->last_scanned)) + oldest = target; + } + + /* If we didn't find a match, then get a new network slot to initialize + * with this beacon's information */ + if (&target->list == &ieee->network_list) { + if (list_empty(&ieee->network_free_list)) { + /* If there are no more slots, expire the oldest */ + list_del(&oldest->list); + target = oldest; + IEEE80211_DEBUG_SCAN("Expired '%s' (" MAC_FMT ") from " + "network list.\n", + escape_essid(target->ssid, + target->ssid_len), + MAC_ARG(target->bssid)); + } else { + /* Otherwise just pull from the free list */ + target = list_entry(ieee->network_free_list.next, + struct ieee80211_network, list); + list_del(ieee->network_free_list.next); + } + + +#ifdef CONFIG_IEEE80211_DEBUG + IEEE80211_DEBUG_SCAN("Adding '%s' (" MAC_FMT ") via %s.\n", + escape_essid(network.ssid, + network.ssid_len), + MAC_ARG(network.bssid), + WLAN_FC_GET_STYPE(beacon->header.frame_ctl) == + IEEE80211_STYPE_PROBE_RESP ? + "PROBE RESPONSE" : "BEACON"); +#endif + memcpy(target, &network, sizeof(*target)); + list_add_tail(&target->list, &ieee->network_list); + if(ieee->softmac_features & IEEE_SOFTMAC_ASSOCIATE) + ieee80211_softmac_new_net(ieee,&network); + } else { + IEEE80211_DEBUG_SCAN("Updating '%s' (" MAC_FMT ") via %s.\n", + escape_essid(target->ssid, + target->ssid_len), + MAC_ARG(target->bssid), + WLAN_FC_GET_STYPE(beacon->header.frame_ctl) == + IEEE80211_STYPE_PROBE_RESP ? + "PROBE RESPONSE" : "BEACON"); + + /* we have an entry and we are going to update it. But this entry may + * be already expired. In this case we do the same as we found a new + * net and call the new_net handler + */ + renew = !time_after(target->last_scanned + ieee->scan_age, jiffies); + //YJ,add,080819,for hidden ap + if(is_beacon(beacon->header.frame_ctl) == 0) + network.flags = (~NETWORK_EMPTY_ESSID & network.flags)|(NETWORK_EMPTY_ESSID & target->flags); + //if(strncmp(network.ssid, "linksys-c",9) == 0) + // printk("====>2 network.ssid=%s FLAG=%d target.ssid=%s FLAG=%d\n", network.ssid, network.flags, target->ssid, target->flags); + if(((network.flags & NETWORK_EMPTY_ESSID) == NETWORK_EMPTY_ESSID) \ + && (((network.ssid_len > 0) && (strncmp(target->ssid, network.ssid, network.ssid_len)))\ + ||((ieee->current_network.ssid_len == network.ssid_len)&&(strncmp(ieee->current_network.ssid, network.ssid, network.ssid_len) == 0)&&(ieee->state == IEEE80211_NOLINK)))) + renew = 1; + //YJ,add,080819,for hidden ap,end + + update_network(target, &network); + if(renew && (ieee->softmac_features & IEEE_SOFTMAC_ASSOCIATE)) + ieee80211_softmac_new_net(ieee,&network); + } + + spin_unlock_irqrestore(&ieee->lock, flags); + if (is_beacon(beacon->header.frame_ctl)&&is_same_network(&ieee->current_network, &network, ieee)&&\ + (ieee->state == IEEE80211_LINKED)) { + if(ieee->handle_beacon != NULL) { + ieee->handle_beacon(ieee->dev,beacon,&ieee->current_network); + } + } +} + +void ieee80211_rx_mgt(struct ieee80211_device *ieee, + struct ieee80211_hdr_4addr *header, + struct ieee80211_rx_stats *stats) +{ + if(ieee->sta_sleep || (ieee->ps != IEEE80211_PS_DISABLED && + ieee->iw_mode == IW_MODE_INFRA && + ieee->state == IEEE80211_LINKED)) + { + tasklet_schedule(&ieee->ps_task); + } + + if(WLAN_FC_GET_STYPE(header->frame_ctl) != IEEE80211_STYPE_PROBE_RESP && + WLAN_FC_GET_STYPE(header->frame_ctl) != IEEE80211_STYPE_BEACON) + ieee->last_rx_ps_time = jiffies; + + switch (WLAN_FC_GET_STYPE(header->frame_ctl)) { + + case IEEE80211_STYPE_BEACON: + IEEE80211_DEBUG_MGMT("received BEACON (%d)\n", + WLAN_FC_GET_STYPE(header->frame_ctl)); + IEEE80211_DEBUG_SCAN("Beacon\n"); + ieee80211_process_probe_response( + ieee, (struct ieee80211_probe_response *)header, stats); + break; + + case IEEE80211_STYPE_PROBE_RESP: + IEEE80211_DEBUG_MGMT("received PROBE RESPONSE (%d)\n", + WLAN_FC_GET_STYPE(header->frame_ctl)); + IEEE80211_DEBUG_SCAN("Probe response\n"); + ieee80211_process_probe_response( + ieee, (struct ieee80211_probe_response *)header, stats); + break; + + } +} + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) +EXPORT_SYMBOL(ieee80211_rx_mgt); +EXPORT_SYMBOL(ieee80211_rx); +#else +EXPORT_SYMBOL_NOVERS(ieee80211_rx_mgt); +EXPORT_SYMBOL_NOVERS(ieee80211_rx); +#endif diff --git a/drivers/staging/rtl8192su/ieee80211/ieee80211_softmac.c b/drivers/staging/rtl8192su/ieee80211/ieee80211_softmac.c new file mode 100644 index 000000000000..6773e84c778e --- /dev/null +++ b/drivers/staging/rtl8192su/ieee80211/ieee80211_softmac.c @@ -0,0 +1,3580 @@ +/* IEEE 802.11 SoftMAC layer + * Copyright (c) 2005 Andrea Merello <andreamrl@tiscali.it> + * + * Mostly extracted from the rtl8180-sa2400 driver for the + * in-kernel generic ieee802.11 stack. + * + * Few lines might be stolen from other part of the ieee80211 + * stack. Copyright who own it's copyright + * + * WPA code stolen from the ipw2200 driver. + * Copyright who own it's copyright. + * + * released under the GPL + */ + + +#include "ieee80211.h" + +#include <linux/random.h> +#include <linux/delay.h> +#include <linux/version.h> +#include <asm/uaccess.h> +#ifdef ENABLE_DOT11D +#include "dot11d.h" +#endif + +u8 rsn_authen_cipher_suite[16][4] = { + {0x00,0x0F,0xAC,0x00}, //Use group key, //Reserved + {0x00,0x0F,0xAC,0x01}, //WEP-40 //RSNA default + {0x00,0x0F,0xAC,0x02}, //TKIP //NONE //{used just as default} + {0x00,0x0F,0xAC,0x03}, //WRAP-historical + {0x00,0x0F,0xAC,0x04}, //CCMP + {0x00,0x0F,0xAC,0x05}, //WEP-104 +}; + +short ieee80211_is_54g(struct ieee80211_network net) +{ + return ((net.rates_ex_len > 0) || (net.rates_len > 4)); +} + +short ieee80211_is_shortslot(struct ieee80211_network net) +{ + return (net.capability & WLAN_CAPABILITY_SHORT_SLOT); +} + +/* returns the total length needed for pleacing the RATE MFIE + * tag and the EXTENDED RATE MFIE tag if needed. + * It encludes two bytes per tag for the tag itself and its len + */ +unsigned int ieee80211_MFIE_rate_len(struct ieee80211_device *ieee) +{ + unsigned int rate_len = 0; + + if (ieee->modulation & IEEE80211_CCK_MODULATION) + rate_len = IEEE80211_CCK_RATE_LEN + 2; + + if (ieee->modulation & IEEE80211_OFDM_MODULATION) + + rate_len += IEEE80211_OFDM_RATE_LEN + 2; + + return rate_len; +} + +/* pleace the MFIE rate, tag to the memory (double) poined. + * Then it updates the pointer so that + * it points after the new MFIE tag added. + */ +void ieee80211_MFIE_Brate(struct ieee80211_device *ieee, u8 **tag_p) +{ + u8 *tag = *tag_p; + + if (ieee->modulation & IEEE80211_CCK_MODULATION){ + *tag++ = MFIE_TYPE_RATES; + *tag++ = 4; + *tag++ = IEEE80211_BASIC_RATE_MASK | IEEE80211_CCK_RATE_1MB; + *tag++ = IEEE80211_BASIC_RATE_MASK | IEEE80211_CCK_RATE_2MB; + *tag++ = IEEE80211_BASIC_RATE_MASK | IEEE80211_CCK_RATE_5MB; + *tag++ = IEEE80211_BASIC_RATE_MASK | IEEE80211_CCK_RATE_11MB; + } + + /* We may add an option for custom rates that specific HW might support */ + *tag_p = tag; +} + +void ieee80211_MFIE_Grate(struct ieee80211_device *ieee, u8 **tag_p) +{ + u8 *tag = *tag_p; + + if (ieee->modulation & IEEE80211_OFDM_MODULATION){ + + *tag++ = MFIE_TYPE_RATES_EX; + *tag++ = 8; + *tag++ = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_6MB; + *tag++ = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_9MB; + *tag++ = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_12MB; + *tag++ = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_18MB; + *tag++ = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_24MB; + *tag++ = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_36MB; + *tag++ = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_48MB; + *tag++ = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_54MB; + + } + + /* We may add an option for custom rates that specific HW might support */ + *tag_p = tag; +} + + +void ieee80211_WMM_Info(struct ieee80211_device *ieee, u8 **tag_p) { + u8 *tag = *tag_p; + + *tag++ = MFIE_TYPE_GENERIC; //0 + *tag++ = 7; + *tag++ = 0x00; + *tag++ = 0x50; + *tag++ = 0xf2; + *tag++ = 0x02;//5 + *tag++ = 0x00; + *tag++ = 0x01; +#ifdef SUPPORT_USPD + if(ieee->current_network.wmm_info & 0x80) { + *tag++ = 0x0f|MAX_SP_Len; + } else { + *tag++ = MAX_SP_Len; + } +#else + *tag++ = MAX_SP_Len; +#endif + *tag_p = tag; +} + +#ifdef THOMAS_TURBO +void ieee80211_TURBO_Info(struct ieee80211_device *ieee, u8 **tag_p) { + u8 *tag = *tag_p; + + *tag++ = MFIE_TYPE_GENERIC; //0 + *tag++ = 7; + *tag++ = 0x00; + *tag++ = 0xe0; + *tag++ = 0x4c; + *tag++ = 0x01;//5 + *tag++ = 0x02; + *tag++ = 0x11; + *tag++ = 0x00; + + *tag_p = tag; + printk(KERN_ALERT "This is enable turbo mode IE process\n"); +} +#endif + +void enqueue_mgmt(struct ieee80211_device *ieee, struct sk_buff *skb) +{ + int nh; + nh = (ieee->mgmt_queue_head +1) % MGMT_QUEUE_NUM; + +/* + * if the queue is full but we have newer frames then + * just overwrites the oldest. + * + * if (nh == ieee->mgmt_queue_tail) + * return -1; + */ + ieee->mgmt_queue_head = nh; + ieee->mgmt_queue_ring[nh] = skb; + + //return 0; +} + +struct sk_buff *dequeue_mgmt(struct ieee80211_device *ieee) +{ + struct sk_buff *ret; + + if(ieee->mgmt_queue_tail == ieee->mgmt_queue_head) + return NULL; + + ret = ieee->mgmt_queue_ring[ieee->mgmt_queue_tail]; + + ieee->mgmt_queue_tail = + (ieee->mgmt_queue_tail+1) % MGMT_QUEUE_NUM; + + return ret; +} + +void init_mgmt_queue(struct ieee80211_device *ieee) +{ + ieee->mgmt_queue_tail = ieee->mgmt_queue_head = 0; +} + +u8 MgntQuery_MgntFrameTxRate(struct ieee80211_device *ieee) +{ + PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; + u8 rate; + + // 2008/01/25 MH For broadcom, MGNT frame set as OFDM 6M. + if(pHTInfo->IOTAction & HT_IOT_ACT_MGNT_USE_CCK_6M) + rate = 0x0c; + else + rate = ieee->basic_rate & 0x7f; + + if(rate == 0){ + // 2005.01.26, by rcnjko. + if(ieee->mode == IEEE_A|| + ieee->mode== IEEE_N_5G|| + (ieee->mode== IEEE_N_24G&&!pHTInfo->bCurSuppCCK)) + rate = 0x0c; + else + rate = 0x02; + } + + /* + // Data rate of ProbeReq is already decided. Annie, 2005-03-31 + if( pMgntInfo->bScanInProgress || (pMgntInfo->bDualModeScanStep!=0) ) + { + if(pMgntInfo->dot11CurrentWirelessMode==WIRELESS_MODE_A) + rate = 0x0c; + else + rate = 0x02; + } + */ + return rate; +} + + +void ieee80211_sta_wakeup(struct ieee80211_device *ieee, short nl); + +inline void softmac_mgmt_xmit(struct sk_buff *skb, struct ieee80211_device *ieee) +{ + unsigned long flags; + short single = ieee->softmac_features & IEEE_SOFTMAC_SINGLE_QUEUE; + struct ieee80211_hdr_3addr *header= + (struct ieee80211_hdr_3addr *) skb->data; + + cb_desc *tcb_desc = (cb_desc *)(skb->cb + 8); + spin_lock_irqsave(&ieee->lock, flags); + + /* called with 2nd param 0, no mgmt lock required */ + ieee80211_sta_wakeup(ieee,0); + + tcb_desc->queue_index = MGNT_QUEUE; + tcb_desc->data_rate = MgntQuery_MgntFrameTxRate(ieee); + tcb_desc->RATRIndex = 7; + tcb_desc->bTxDisableRateFallBack = 1; + tcb_desc->bTxUseDriverAssingedRate = 1; + + if(single){ + if(ieee->queue_stop){ + enqueue_mgmt(ieee,skb); + }else{ + header->seq_ctl = cpu_to_le16(ieee->seq_ctrl[0]<<4); + + if (ieee->seq_ctrl[0] == 0xFFF) + ieee->seq_ctrl[0] = 0; + else + ieee->seq_ctrl[0]++; + + /* avoid watchdog triggers */ + // ieee->dev->trans_start = jiffies; + ieee->softmac_data_hard_start_xmit(skb,ieee->dev,ieee->basic_rate); + //dev_kfree_skb_any(skb);//edit by thomas + } + + spin_unlock_irqrestore(&ieee->lock, flags); + }else{ + spin_unlock_irqrestore(&ieee->lock, flags); + spin_lock_irqsave(&ieee->mgmt_tx_lock, flags); + + header->seq_ctl = cpu_to_le16(ieee->seq_ctrl[0] << 4); + + if (ieee->seq_ctrl[0] == 0xFFF) + ieee->seq_ctrl[0] = 0; + else + ieee->seq_ctrl[0]++; + + /* check wether the managed packet queued greater than 5 */ + if(!ieee->check_nic_enough_desc(ieee->dev,tcb_desc->queue_index)||\ + (skb_queue_len(&ieee->skb_waitQ[tcb_desc->queue_index]) != 0)||\ + (ieee->queue_stop) ) { + /* insert the skb packet to the management queue */ + /* as for the completion function, it does not need + * to check it any more. + * */ + printk("%s():insert to waitqueue!\n",__FUNCTION__); + skb_queue_tail(&ieee->skb_waitQ[tcb_desc->queue_index], skb); + } else { + //printk("TX packet!\n"); + ieee->softmac_hard_start_xmit(skb,ieee->dev); + //dev_kfree_skb_any(skb);//edit by thomas + } + spin_unlock_irqrestore(&ieee->mgmt_tx_lock, flags); + } +} + +inline void softmac_ps_mgmt_xmit(struct sk_buff *skb, struct ieee80211_device *ieee) +{ + + short single = ieee->softmac_features & IEEE_SOFTMAC_SINGLE_QUEUE; + struct ieee80211_hdr_3addr *header = + (struct ieee80211_hdr_3addr *) skb->data; + cb_desc *tcb_desc = (cb_desc *)(skb->cb + 8); + + tcb_desc->queue_index = MGNT_QUEUE; + tcb_desc->data_rate = MgntQuery_MgntFrameTxRate(ieee); + tcb_desc->RATRIndex = 7; + tcb_desc->bTxDisableRateFallBack = 1; + tcb_desc->bTxUseDriverAssingedRate = 1; + //printk("=============>%s()\n", __FUNCTION__); + if(single){ + + header->seq_ctl = cpu_to_le16(ieee->seq_ctrl[0] << 4); + + if (ieee->seq_ctrl[0] == 0xFFF) + ieee->seq_ctrl[0] = 0; + else + ieee->seq_ctrl[0]++; + + /* avoid watchdog triggers */ + // ieee->dev->trans_start = jiffies; + ieee->softmac_data_hard_start_xmit(skb,ieee->dev,ieee->basic_rate); + + }else{ + + header->seq_ctl = cpu_to_le16(ieee->seq_ctrl[0] << 4); + + if (ieee->seq_ctrl[0] == 0xFFF) + ieee->seq_ctrl[0] = 0; + else + ieee->seq_ctrl[0]++; + + ieee->softmac_hard_start_xmit(skb,ieee->dev); + + } + //dev_kfree_skb_any(skb);//edit by thomas +} + +inline struct sk_buff *ieee80211_probe_req(struct ieee80211_device *ieee) +{ + unsigned int len,rate_len; + u8 *tag; + struct sk_buff *skb; + struct ieee80211_probe_request *req; + + len = ieee->current_network.ssid_len; + + rate_len = ieee80211_MFIE_rate_len(ieee); + + skb = dev_alloc_skb(sizeof(struct ieee80211_probe_request) + + 2 + len + rate_len + ieee->tx_headroom); + if (!skb) + return NULL; + + skb_reserve(skb, ieee->tx_headroom); + + req = (struct ieee80211_probe_request *) skb_put(skb,sizeof(struct ieee80211_probe_request)); + req->header.frame_ctl = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ); + req->header.duration_id = 0; //FIXME: is this OK ? + + memset(req->header.addr1, 0xff, ETH_ALEN); + memcpy(req->header.addr2, ieee->dev->dev_addr, ETH_ALEN); + memset(req->header.addr3, 0xff, ETH_ALEN); + + tag = (u8 *) skb_put(skb,len+2+rate_len); + + *tag++ = MFIE_TYPE_SSID; + *tag++ = len; + memcpy(tag, ieee->current_network.ssid, len); + tag += len; + + ieee80211_MFIE_Brate(ieee,&tag); + ieee80211_MFIE_Grate(ieee,&tag); + return skb; +} + +struct sk_buff *ieee80211_get_beacon_(struct ieee80211_device *ieee); +void ieee80211_send_beacon(struct ieee80211_device *ieee) +{ + struct sk_buff *skb; + if(!ieee->ieee_up) + return; + //unsigned long flags; + skb = ieee80211_get_beacon_(ieee); + + if (skb){ + softmac_mgmt_xmit(skb, ieee); + ieee->softmac_stats.tx_beacons++; + //dev_kfree_skb_any(skb);//edit by thomas + } +// ieee->beacon_timer.expires = jiffies + +// (MSECS( ieee->current_network.beacon_interval -5)); + + //spin_lock_irqsave(&ieee->beacon_lock,flags); + if(ieee->beacon_txing && ieee->ieee_up){ +// if(!timer_pending(&ieee->beacon_timer)) +// add_timer(&ieee->beacon_timer); + mod_timer(&ieee->beacon_timer,jiffies+(MSECS(ieee->current_network.beacon_interval-5))); + } + //spin_unlock_irqrestore(&ieee->beacon_lock,flags); +} + + +void ieee80211_send_beacon_cb(unsigned long _ieee) +{ + struct ieee80211_device *ieee = + (struct ieee80211_device *) _ieee; + unsigned long flags; + + spin_lock_irqsave(&ieee->beacon_lock, flags); + ieee80211_send_beacon(ieee); + spin_unlock_irqrestore(&ieee->beacon_lock, flags); +} + + +void ieee80211_send_probe(struct ieee80211_device *ieee) +{ + struct sk_buff *skb; + + skb = ieee80211_probe_req(ieee); + if (skb){ + softmac_mgmt_xmit(skb, ieee); + ieee->softmac_stats.tx_probe_rq++; + //dev_kfree_skb_any(skb);//edit by thomas + } +} + +void ieee80211_send_probe_requests(struct ieee80211_device *ieee) +{ + if (ieee->active_scan && (ieee->softmac_features & IEEE_SOFTMAC_PROBERQ)){ + ieee80211_send_probe(ieee); + ieee80211_send_probe(ieee); + } +} + +/* this performs syncro scan blocking the caller until all channels + * in the allowed channel map has been checked. + */ +void ieee80211_softmac_scan_syncro(struct ieee80211_device *ieee) +{ + short ch = 0; +#ifdef ENABLE_DOT11D + u8 channel_map[MAX_CHANNEL_NUMBER+1]; + memcpy(channel_map, GET_DOT11D_INFO(ieee)->channel_map, MAX_CHANNEL_NUMBER+1); +#endif + ieee->be_scan_inprogress = true; + down(&ieee->scan_sem); + + while(1) + { + + do{ + ch++; + if (ch > MAX_CHANNEL_NUMBER) + goto out; /* scan completed */ +#ifdef ENABLE_DOT11D + }while(!channel_map[ch]); +#else + }while(!ieee->channel_map[ch]); +#endif + + /* this fuction can be called in two situations + * 1- We have switched to ad-hoc mode and we are + * performing a complete syncro scan before conclude + * there are no interesting cell and to create a + * new one. In this case the link state is + * IEEE80211_NOLINK until we found an interesting cell. + * If so the ieee8021_new_net, called by the RX path + * will set the state to IEEE80211_LINKED, so we stop + * scanning + * 2- We are linked and the root uses run iwlist scan. + * So we switch to IEEE80211_LINKED_SCANNING to remember + * that we are still logically linked (not interested in + * new network events, despite for updating the net list, + * but we are temporarly 'unlinked' as the driver shall + * not filter RX frames and the channel is changing. + * So the only situation in witch are interested is to check + * if the state become LINKED because of the #1 situation + */ + + if (ieee->state == IEEE80211_LINKED) + goto out; + ieee->set_chan(ieee->dev, ch); +#ifdef ENABLE_DOT11D + if(channel_map[ch] == 1) +#endif + ieee80211_send_probe_requests(ieee); + + /* this prevent excessive time wait when we + * need to wait for a syncro scan to end.. + */ + if(ieee->state < IEEE80211_LINKED) + ; + else + if (ieee->sync_scan_hurryup) + goto out; + + + msleep_interruptible_rsl(IEEE80211_SOFTMAC_SCAN_TIME); + + } +out: + if(ieee->state < IEEE80211_LINKED){ + ieee->actscanning = false; + up(&ieee->scan_sem); + ieee->be_scan_inprogress = false; + } + else{ + ieee->sync_scan_hurryup = 0; +#ifdef ENABLE_DOT11D + if(IS_DOT11D_ENABLE(ieee)) + DOT11D_ScanComplete(ieee); +#endif + up(&ieee->scan_sem); + ieee->be_scan_inprogress = false; +} +} + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) +/* called both by wq with ieee->lock held */ +void ieee80211_softmac_scan(struct ieee80211_device *ieee) +{ +#if 0 + short watchdog = 0; + do{ + ieee->current_network.channel = + (ieee->current_network.channel + 1) % MAX_CHANNEL_NUMBER; + if (watchdog++ > MAX_CHANNEL_NUMBER) + return; /* no good chans */ + + }while(!ieee->channel_map[ieee->current_network.channel]); +#endif + + schedule_task(&ieee->softmac_scan_wq); +} +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) +void ieee80211_softmac_scan_wq(struct work_struct *work) +{ + struct delayed_work *dwork = container_of(work, struct delayed_work, work); + struct ieee80211_device *ieee = container_of(dwork, struct ieee80211_device, softmac_scan_wq); +#else +void ieee80211_softmac_scan_wq(struct ieee80211_device *ieee) +{ +#endif + u8 last_channel = ieee->current_network.channel; //recored init channel inorder not change current channel when comming out the scan unexpectedly. WB. +#ifdef ENABLE_DOT11D + u8 channel_map[MAX_CHANNEL_NUMBER+1]; + memcpy(channel_map, GET_DOT11D_INFO(ieee)->channel_map, MAX_CHANNEL_NUMBER+1); +#endif + if(!ieee->ieee_up) + return; + down(&ieee->scan_sem); + do{ + ieee->current_network.channel = + (ieee->current_network.channel + 1) % MAX_CHANNEL_NUMBER; + if (ieee->scan_watch_dog++ > MAX_CHANNEL_NUMBER) + { + //if current channel is not in channel map, set to default channel. + #ifdef ENABLE_DOT11D + if (!channel_map[ieee->current_network.channel]); + #else + if (!ieee->channel_map[ieee->current_network.channel]); + #endif + ieee->current_network.channel = 6; + goto out; /* no good chans */ + } +#ifdef ENABLE_DOT11D + }while(!channel_map[ieee->current_network.channel]); +#else + }while(!ieee->channel_map[ieee->current_network.channel]); +#endif + if (ieee->scanning == 0 ) + goto out; + ieee->set_chan(ieee->dev, ieee->current_network.channel); +#ifdef ENABLE_DOT11D + if(channel_map[ieee->current_network.channel] == 1) +#endif + ieee80211_send_probe_requests(ieee); + + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + queue_delayed_work(ieee->wq, &ieee->softmac_scan_wq, IEEE80211_SOFTMAC_SCAN_TIME); +#else + //ieee->scan_timer.expires = jiffies + MSECS(IEEE80211_SOFTMAC_SCAN_TIME); + if (ieee->scanning == 1) + mod_timer(&ieee->scan_timer,(jiffies + MSECS(IEEE80211_SOFTMAC_SCAN_TIME))); +#endif + + up(&ieee->scan_sem); + return; +out: +#ifdef ENABLE_DOT11D + if(IS_DOT11D_ENABLE(ieee)) + DOT11D_ScanComplete(ieee); +#endif + ieee->current_network.channel = last_channel; + ieee->actscanning = false; + ieee->scan_watch_dog = 0; + ieee->scanning = 0; + up(&ieee->scan_sem); +} + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) +void ieee80211_softmac_scan_cb(unsigned long _dev) +{ + unsigned long flags; + struct ieee80211_device *ieee = (struct ieee80211_device *)_dev; + + spin_lock_irqsave(&ieee->lock, flags); + ieee80211_softmac_scan(ieee); + spin_unlock_irqrestore(&ieee->lock, flags); +} +#endif + + +void ieee80211_beacons_start(struct ieee80211_device *ieee) +{ + unsigned long flags; + spin_lock_irqsave(&ieee->beacon_lock,flags); + + ieee->beacon_txing = 1; + ieee80211_send_beacon(ieee); + + spin_unlock_irqrestore(&ieee->beacon_lock,flags); +} + +void ieee80211_beacons_stop(struct ieee80211_device *ieee) +{ + unsigned long flags; + + spin_lock_irqsave(&ieee->beacon_lock,flags); + + ieee->beacon_txing = 0; + del_timer_sync(&ieee->beacon_timer); + + spin_unlock_irqrestore(&ieee->beacon_lock,flags); + +} + + +void ieee80211_stop_send_beacons(struct ieee80211_device *ieee) +{ + if(ieee->stop_send_beacons) + ieee->stop_send_beacons(ieee->dev); + if (ieee->softmac_features & IEEE_SOFTMAC_BEACONS) + ieee80211_beacons_stop(ieee); +} + + +void ieee80211_start_send_beacons(struct ieee80211_device *ieee) +{ + if(ieee->start_send_beacons) + ieee->start_send_beacons(ieee->dev); + if(ieee->softmac_features & IEEE_SOFTMAC_BEACONS) + ieee80211_beacons_start(ieee); +} + + +void ieee80211_softmac_stop_scan(struct ieee80211_device *ieee) +{ +// unsigned long flags; + + //ieee->sync_scan_hurryup = 1; + + down(&ieee->scan_sem); +// spin_lock_irqsave(&ieee->lock, flags); + ieee->scan_watch_dog = 0; + if (ieee->scanning == 1){ + ieee->scanning = 0; + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + cancel_delayed_work(&ieee->softmac_scan_wq); +#else + del_timer_sync(&ieee->scan_timer); +#endif + } + +// spin_unlock_irqrestore(&ieee->lock, flags); + up(&ieee->scan_sem); +} + +void ieee80211_stop_scan(struct ieee80211_device *ieee) +{ + if (ieee->softmac_features & IEEE_SOFTMAC_SCAN) + ieee80211_softmac_stop_scan(ieee); + else + ieee->stop_scan(ieee->dev); +} + +/* called with ieee->lock held */ +void ieee80211_start_scan(struct ieee80211_device *ieee) +{ +#ifdef ENABLE_DOT11D + if(IS_DOT11D_ENABLE(ieee) ) + { + if(IS_COUNTRY_IE_VALID(ieee)) + { + RESET_CIE_WATCHDOG(ieee); + } + } +#endif + if (ieee->softmac_features & IEEE_SOFTMAC_SCAN){ + if (ieee->scanning == 0){ + ieee->scanning = 1; +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + queue_delayed_work(ieee->wq, &ieee->softmac_scan_wq, 0); +#else + + queue_work(ieee->wq, &ieee->softmac_scan_wq); +#endif +#else + ieee80211_softmac_scan(ieee); +#endif + } + }else + ieee->start_scan(ieee->dev); + +} + +/* called with wx_sem held */ +void ieee80211_start_scan_syncro(struct ieee80211_device *ieee) +{ +#ifdef ENABLE_DOT11D + if(IS_DOT11D_ENABLE(ieee) ) + { + if(IS_COUNTRY_IE_VALID(ieee)) + { + RESET_CIE_WATCHDOG(ieee); + } + } +#endif + ieee->sync_scan_hurryup = 0; + if (ieee->softmac_features & IEEE_SOFTMAC_SCAN) + ieee80211_softmac_scan_syncro(ieee); + else + ieee->scan_syncro(ieee->dev); + +} + +inline struct sk_buff *ieee80211_authentication_req(struct ieee80211_network *beacon, + struct ieee80211_device *ieee, int challengelen) +{ + struct sk_buff *skb; + struct ieee80211_authentication *auth; + int len = sizeof(struct ieee80211_authentication) + challengelen + ieee->tx_headroom; + + + skb = dev_alloc_skb(len); + if (!skb) return NULL; + + skb_reserve(skb, ieee->tx_headroom); + auth = (struct ieee80211_authentication *) + skb_put(skb, sizeof(struct ieee80211_authentication)); + + auth->header.frame_ctl = IEEE80211_STYPE_AUTH; + if (challengelen) auth->header.frame_ctl |= IEEE80211_FCTL_WEP; + + auth->header.duration_id = 0x013a; //FIXME + + memcpy(auth->header.addr1, beacon->bssid, ETH_ALEN); + memcpy(auth->header.addr2, ieee->dev->dev_addr, ETH_ALEN); + memcpy(auth->header.addr3, beacon->bssid, ETH_ALEN); + + //auth->algorithm = ieee->open_wep ? WLAN_AUTH_OPEN : WLAN_AUTH_SHARED_KEY; + if(ieee->auth_mode == 0) + auth->algorithm = WLAN_AUTH_OPEN; + else if(ieee->auth_mode == 1) + auth->algorithm = WLAN_AUTH_SHARED_KEY; + else if(ieee->auth_mode == 2) + auth->algorithm = WLAN_AUTH_OPEN;//0x80; + printk("=================>%s():auth->algorithm is %d\n",__FUNCTION__,auth->algorithm); + auth->transaction = cpu_to_le16(ieee->associate_seq); + ieee->associate_seq++; + + auth->status = cpu_to_le16(WLAN_STATUS_SUCCESS); + + return skb; + +} + + +static struct sk_buff* ieee80211_probe_resp(struct ieee80211_device *ieee, u8 *dest) +{ + u8 *tag; + int beacon_size; + struct ieee80211_probe_response *beacon_buf; + struct sk_buff *skb = NULL; + int encrypt; + int atim_len,erp_len; + struct ieee80211_crypt_data* crypt; + + char *ssid = ieee->current_network.ssid; + int ssid_len = ieee->current_network.ssid_len; + int rate_len = ieee->current_network.rates_len+2; + int rate_ex_len = ieee->current_network.rates_ex_len; + int wpa_ie_len = ieee->wpa_ie_len; + u8 erpinfo_content = 0; + + u8* tmp_ht_cap_buf; + u8 tmp_ht_cap_len=0; + u8* tmp_ht_info_buf; + u8 tmp_ht_info_len=0; + PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; + u8* tmp_generic_ie_buf=NULL; + u8 tmp_generic_ie_len=0; + + if(rate_ex_len > 0) rate_ex_len+=2; + + if(ieee->current_network.capability & WLAN_CAPABILITY_IBSS) + atim_len = 4; + else + atim_len = 0; + +#if 1 + if(ieee80211_is_54g(ieee->current_network)) + erp_len = 3; + else + erp_len = 0; +#else + if((ieee->current_network.mode == IEEE_G) + ||( ieee->current_network.mode == IEEE_N_24G && ieee->pHTInfo->bCurSuppCCK)) { + erp_len = 3; + erpinfo_content = 0; + if(ieee->current_network.buseprotection) + erpinfo_content |= ERP_UseProtection; + } + else + erp_len = 0; +#endif + + + crypt = ieee->crypt[ieee->tx_keyidx]; + + + encrypt = ieee->host_encrypt && crypt && crypt->ops && + ((0 == strcmp(crypt->ops->name, "WEP") || wpa_ie_len)); + //HT ralated element +#if 1 + tmp_ht_cap_buf =(u8*) &(ieee->pHTInfo->SelfHTCap); + tmp_ht_cap_len = sizeof(ieee->pHTInfo->SelfHTCap); + tmp_ht_info_buf =(u8*) &(ieee->pHTInfo->SelfHTInfo); + tmp_ht_info_len = sizeof(ieee->pHTInfo->SelfHTInfo); + HTConstructCapabilityElement(ieee, tmp_ht_cap_buf, &tmp_ht_cap_len,encrypt); + HTConstructInfoElement(ieee,tmp_ht_info_buf,&tmp_ht_info_len, encrypt); + + + if(pHTInfo->bRegRT2RTAggregation) + { + tmp_generic_ie_buf = ieee->pHTInfo->szRT2RTAggBuffer; + tmp_generic_ie_len = sizeof(ieee->pHTInfo->szRT2RTAggBuffer); + HTConstructRT2RTAggElement(ieee, tmp_generic_ie_buf, &tmp_generic_ie_len); + } +// printk("===============>tmp_ht_cap_len is %d,tmp_ht_info_len is %d, tmp_generic_ie_len is %d\n",tmp_ht_cap_len,tmp_ht_info_len,tmp_generic_ie_len); +#endif + beacon_size = sizeof(struct ieee80211_probe_response)+2+ + ssid_len + +3 //channel + +rate_len + +rate_ex_len + +atim_len + +erp_len + +wpa_ie_len + // +tmp_ht_cap_len + // +tmp_ht_info_len + // +tmp_generic_ie_len +// +wmm_len+2 + +ieee->tx_headroom; + skb = dev_alloc_skb(beacon_size); + if (!skb) + return NULL; + skb_reserve(skb, ieee->tx_headroom); + beacon_buf = (struct ieee80211_probe_response*) skb_put(skb, (beacon_size - ieee->tx_headroom)); + memcpy (beacon_buf->header.addr1, dest,ETH_ALEN); + memcpy (beacon_buf->header.addr2, ieee->dev->dev_addr, ETH_ALEN); + memcpy (beacon_buf->header.addr3, ieee->current_network.bssid, ETH_ALEN); + + beacon_buf->header.duration_id = 0; //FIXME + beacon_buf->beacon_interval = + cpu_to_le16(ieee->current_network.beacon_interval); + beacon_buf->capability = + cpu_to_le16(ieee->current_network.capability & WLAN_CAPABILITY_IBSS); + beacon_buf->capability |= + cpu_to_le16(ieee->current_network.capability & WLAN_CAPABILITY_SHORT_PREAMBLE); //add short preamble here + + if(ieee->short_slot && (ieee->current_network.capability & WLAN_CAPABILITY_SHORT_SLOT)) + cpu_to_le16((beacon_buf->capability |= WLAN_CAPABILITY_SHORT_SLOT)); + + crypt = ieee->crypt[ieee->tx_keyidx]; +#if 0 + encrypt = ieee->host_encrypt && crypt && crypt->ops && + (0 == strcmp(crypt->ops->name, "WEP")); +#endif + if (encrypt) + beacon_buf->capability |= cpu_to_le16(WLAN_CAPABILITY_PRIVACY); + + + beacon_buf->header.frame_ctl = cpu_to_le16(IEEE80211_STYPE_PROBE_RESP); + beacon_buf->info_element[0].id = MFIE_TYPE_SSID; + beacon_buf->info_element[0].len = ssid_len; + + tag = (u8*) beacon_buf->info_element[0].data; + + memcpy(tag, ssid, ssid_len); + + tag += ssid_len; + + *(tag++) = MFIE_TYPE_RATES; + *(tag++) = rate_len-2; + memcpy(tag,ieee->current_network.rates,rate_len-2); + tag+=rate_len-2; + + *(tag++) = MFIE_TYPE_DS_SET; + *(tag++) = 1; + *(tag++) = ieee->current_network.channel; + + if(atim_len){ + u16 val16; + *(tag++) = MFIE_TYPE_IBSS_SET; + *(tag++) = 2; + //*((u16*)(tag)) = cpu_to_le16(ieee->current_network.atim_window); + val16 = cpu_to_le16(ieee->current_network.atim_window); + memcpy((u8 *)tag, (u8 *)&val16, 2); + tag+=2; + } + + if(erp_len){ + *(tag++) = MFIE_TYPE_ERP; + *(tag++) = 1; + *(tag++) = erpinfo_content; + } +#if 0 + //Include High Throuput capability + + *(tag++) = MFIE_TYPE_HT_CAP; + *(tag++) = tmp_ht_cap_len - 2; + memcpy(tag, tmp_ht_cap_buf, tmp_ht_cap_len - 2); + tag += tmp_ht_cap_len - 2; +#endif + if(rate_ex_len){ + *(tag++) = MFIE_TYPE_RATES_EX; + *(tag++) = rate_ex_len-2; + memcpy(tag,ieee->current_network.rates_ex,rate_ex_len-2); + tag+=rate_ex_len-2; + } + +#if 0 + //Include High Throuput info + + *(tag++) = MFIE_TYPE_HT_INFO; + *(tag++) = tmp_ht_info_len - 2; + memcpy(tag, tmp_ht_info_buf, tmp_ht_info_len -2); + tag += tmp_ht_info_len - 2; +#endif + if (wpa_ie_len) + { + if (ieee->iw_mode == IW_MODE_ADHOC) + {//as Windows will set pairwise key same as the group key which is not allowed in Linux, so set this for IOT issue. WB 2008.07.07 + memcpy(&ieee->wpa_ie[14], &ieee->wpa_ie[8], 4); + } + memcpy(tag, ieee->wpa_ie, ieee->wpa_ie_len); + tag += wpa_ie_len; + } + +#if 0 + // + // Construct Realtek Proprietary Aggregation mode (Set AMPDU Factor to 2, 32k) + // + if(pHTInfo->bRegRT2RTAggregation) + { + (*tag++) = 0xdd; + (*tag++) = tmp_generic_ie_len - 2; + memcpy(tag,tmp_generic_ie_buf,tmp_generic_ie_len -2); + tag += tmp_generic_ie_len -2; + + } +#endif +#if 0 + if(ieee->qos_support) + { + (*tag++) = 0xdd; + (*tag++) = wmm_len; + memcpy(tag,QosOui,wmm_len); + tag += wmm_len; + } +#endif + //skb->dev = ieee->dev; + return skb; +} + + +struct sk_buff* ieee80211_assoc_resp(struct ieee80211_device *ieee, u8 *dest) +{ + struct sk_buff *skb; + u8* tag; + + struct ieee80211_crypt_data* crypt; + struct ieee80211_assoc_response_frame *assoc; + short encrypt; + + unsigned int rate_len = ieee80211_MFIE_rate_len(ieee); + int len = sizeof(struct ieee80211_assoc_response_frame) + rate_len + ieee->tx_headroom; + + skb = dev_alloc_skb(len); + + if (!skb) + return NULL; + + skb_reserve(skb, ieee->tx_headroom); + + assoc = (struct ieee80211_assoc_response_frame *) + skb_put(skb,sizeof(struct ieee80211_assoc_response_frame)); + + assoc->header.frame_ctl = cpu_to_le16(IEEE80211_STYPE_ASSOC_RESP); + memcpy(assoc->header.addr1, dest,ETH_ALEN); + memcpy(assoc->header.addr3, ieee->dev->dev_addr, ETH_ALEN); + memcpy(assoc->header.addr2, ieee->dev->dev_addr, ETH_ALEN); + assoc->capability = cpu_to_le16(ieee->iw_mode == IW_MODE_MASTER ? + WLAN_CAPABILITY_BSS : WLAN_CAPABILITY_IBSS); + + + if(ieee->short_slot) + assoc->capability |= cpu_to_le16(WLAN_CAPABILITY_SHORT_SLOT); + + if (ieee->host_encrypt) + crypt = ieee->crypt[ieee->tx_keyidx]; + else crypt = NULL; + + encrypt = ( crypt && crypt->ops); + + if (encrypt) + assoc->capability |= cpu_to_le16(WLAN_CAPABILITY_PRIVACY); + + assoc->status = 0; + assoc->aid = cpu_to_le16(ieee->assoc_id); + if (ieee->assoc_id == 0x2007) ieee->assoc_id=0; + else ieee->assoc_id++; + + tag = (u8*) skb_put(skb, rate_len); + + ieee80211_MFIE_Brate(ieee, &tag); + ieee80211_MFIE_Grate(ieee, &tag); + + return skb; +} + +struct sk_buff* ieee80211_auth_resp(struct ieee80211_device *ieee,int status, u8 *dest) +{ + struct sk_buff *skb; + struct ieee80211_authentication *auth; + int len = ieee->tx_headroom + sizeof(struct ieee80211_authentication)+1; + + skb = dev_alloc_skb(len); + + if (!skb) + return NULL; + + skb->len = sizeof(struct ieee80211_authentication); + + auth = (struct ieee80211_authentication *)skb->data; + + auth->status = cpu_to_le16(status); + auth->transaction = cpu_to_le16(2); + auth->algorithm = cpu_to_le16(WLAN_AUTH_OPEN); + + memcpy(auth->header.addr3, ieee->dev->dev_addr, ETH_ALEN); + memcpy(auth->header.addr2, ieee->dev->dev_addr, ETH_ALEN); + memcpy(auth->header.addr1, dest, ETH_ALEN); + auth->header.frame_ctl = cpu_to_le16(IEEE80211_STYPE_AUTH); + return skb; + + +} + +struct sk_buff* ieee80211_null_func(struct ieee80211_device *ieee,short pwr) +{ + struct sk_buff *skb; + struct ieee80211_hdr_3addr* hdr; + + skb = dev_alloc_skb(sizeof(struct ieee80211_hdr_3addr)); + + if (!skb) + return NULL; + + hdr = (struct ieee80211_hdr_3addr*)skb_put(skb,sizeof(struct ieee80211_hdr_3addr)); + + memcpy(hdr->addr1, ieee->current_network.bssid, ETH_ALEN); + memcpy(hdr->addr2, ieee->dev->dev_addr, ETH_ALEN); + memcpy(hdr->addr3, ieee->current_network.bssid, ETH_ALEN); + + hdr->frame_ctl = cpu_to_le16(IEEE80211_FTYPE_DATA | + IEEE80211_STYPE_NULLFUNC | IEEE80211_FCTL_TODS | + (pwr ? IEEE80211_FCTL_PM:0)); + + return skb; + + +} + + +void ieee80211_resp_to_assoc_rq(struct ieee80211_device *ieee, u8* dest) +{ + struct sk_buff *buf = ieee80211_assoc_resp(ieee, dest); + + if (buf) + softmac_mgmt_xmit(buf, ieee); +} + + +void ieee80211_resp_to_auth(struct ieee80211_device *ieee, int s, u8* dest) +{ + struct sk_buff *buf = ieee80211_auth_resp(ieee, s, dest); + + if (buf) + softmac_mgmt_xmit(buf, ieee); +} + + +void ieee80211_resp_to_probe(struct ieee80211_device *ieee, u8 *dest) +{ + + + struct sk_buff *buf = ieee80211_probe_resp(ieee, dest); + if (buf) + softmac_mgmt_xmit(buf, ieee); +} + + +inline struct sk_buff *ieee80211_association_req(struct ieee80211_network *beacon,struct ieee80211_device *ieee) +{ + struct sk_buff *skb; + //unsigned long flags; + + struct ieee80211_assoc_request_frame *hdr; + u8 *tag;//,*rsn_ie; + //short info_addr = 0; + //int i; + //u16 suite_count = 0; + //u8 suit_select = 0; + //unsigned int wpa_len = beacon->wpa_ie_len; + //for HT + u8* ht_cap_buf = NULL; + u8 ht_cap_len=0; + u8* realtek_ie_buf=NULL; + u8 realtek_ie_len=0; + int wpa_ie_len= ieee->wpa_ie_len; + unsigned int ckip_ie_len=0; + unsigned int ccxrm_ie_len=0; + unsigned int cxvernum_ie_len=0; + struct ieee80211_crypt_data* crypt; + int encrypt; + + unsigned int rate_len = ieee80211_MFIE_rate_len(ieee); + unsigned int wmm_info_len = beacon->qos_data.supported?9:0; +#ifdef THOMAS_TURBO + unsigned int turbo_info_len = beacon->Turbo_Enable?9:0; +#endif + + int len = 0; + + crypt = ieee->crypt[ieee->tx_keyidx]; + encrypt = ieee->host_encrypt && crypt && crypt->ops && ((0 == strcmp(crypt->ops->name,"WEP") || wpa_ie_len)); + + //Include High Throuput capability && Realtek proprietary + if(ieee->pHTInfo->bCurrentHTSupport&&ieee->pHTInfo->bEnableHT) + { + ht_cap_buf = (u8*)&(ieee->pHTInfo->SelfHTCap); + ht_cap_len = sizeof(ieee->pHTInfo->SelfHTCap); + HTConstructCapabilityElement(ieee, ht_cap_buf, &ht_cap_len, encrypt); + if(ieee->pHTInfo->bCurrentRT2RTAggregation) + { + realtek_ie_buf = ieee->pHTInfo->szRT2RTAggBuffer; + realtek_ie_len = sizeof( ieee->pHTInfo->szRT2RTAggBuffer); + HTConstructRT2RTAggElement(ieee, realtek_ie_buf, &realtek_ie_len); + + } + } + if(ieee->qos_support){ + wmm_info_len = beacon->qos_data.supported?9:0; + } + + + if(beacon->bCkipSupported) + { + ckip_ie_len = 30+2; + } + if(beacon->bCcxRmEnable) + { + ccxrm_ie_len = 6+2; + } + if( beacon->BssCcxVerNumber >= 2 ) + { + cxvernum_ie_len = 5+2; + } +#ifdef THOMAS_TURBO + len = sizeof(struct ieee80211_assoc_request_frame)+ 2 + + beacon->ssid_len//essid tagged val + + rate_len//rates tagged val + + wpa_ie_len + + wmm_info_len + + turbo_info_len + + ht_cap_len + + realtek_ie_len + + ckip_ie_len + + ccxrm_ie_len + + cxvernum_ie_len + + ieee->tx_headroom; +#else + len = sizeof(struct ieee80211_assoc_request_frame)+ 2 + + beacon->ssid_len//essid tagged val + + rate_len//rates tagged val + + wpa_ie_len + + wmm_info_len + + ht_cap_len + + realtek_ie_len + + ckip_ie_len + + ccxrm_ie_len + + cxvernum_ie_len + + ieee->tx_headroom; +#endif + + skb = dev_alloc_skb(len); + + if (!skb) + return NULL; + + skb_reserve(skb, ieee->tx_headroom); + + hdr = (struct ieee80211_assoc_request_frame *) + skb_put(skb, sizeof(struct ieee80211_assoc_request_frame)+2); + + + hdr->header.frame_ctl = IEEE80211_STYPE_ASSOC_REQ; + hdr->header.duration_id= 37; //FIXME + memcpy(hdr->header.addr1, beacon->bssid, ETH_ALEN); + memcpy(hdr->header.addr2, ieee->dev->dev_addr, ETH_ALEN); + memcpy(hdr->header.addr3, beacon->bssid, ETH_ALEN); + + memcpy(ieee->ap_mac_addr, beacon->bssid, ETH_ALEN);//for HW security, John + + hdr->capability = cpu_to_le16(WLAN_CAPABILITY_BSS); + if (beacon->capability & WLAN_CAPABILITY_PRIVACY ) + hdr->capability |= cpu_to_le16(WLAN_CAPABILITY_PRIVACY); + + if (beacon->capability & WLAN_CAPABILITY_SHORT_PREAMBLE) + hdr->capability |= cpu_to_le16(WLAN_CAPABILITY_SHORT_PREAMBLE); //add short_preamble here + + if(ieee->short_slot) + hdr->capability |= cpu_to_le16(WLAN_CAPABILITY_SHORT_SLOT); + if (wmm_info_len) //QOS + hdr->capability |= cpu_to_le16(WLAN_CAPABILITY_QOS); + + hdr->listen_interval = 0xa; //FIXME + + hdr->info_element[0].id = MFIE_TYPE_SSID; + + hdr->info_element[0].len = beacon->ssid_len; + tag = skb_put(skb, beacon->ssid_len); + memcpy(tag, beacon->ssid, beacon->ssid_len); + + tag = skb_put(skb, rate_len); + + ieee80211_MFIE_Brate(ieee, &tag); + ieee80211_MFIE_Grate(ieee, &tag); + // For CCX 1 S13, CKIP. Added by Annie, 2006-08-14. + if( beacon->bCkipSupported ) + { + static u8 AironetIeOui[] = {0x00, 0x01, 0x66}; // "4500-client" + u8 CcxAironetBuf[30]; + OCTET_STRING osCcxAironetIE; + + memset(CcxAironetBuf, 0,30); + osCcxAironetIE.Octet = CcxAironetBuf; + osCcxAironetIE.Length = sizeof(CcxAironetBuf); + // + // Ref. CCX test plan v3.61, 3.2.3.1 step 13. + // We want to make the device type as "4500-client". 060926, by CCW. + // + memcpy(osCcxAironetIE.Octet, AironetIeOui, sizeof(AironetIeOui)); + + // CCX1 spec V1.13, A01.1 CKIP Negotiation (page23): + // "The CKIP negotiation is started with the associate request from the client to the access point, + // containing an Aironet element with both the MIC and KP bits set." + osCcxAironetIE.Octet[IE_CISCO_FLAG_POSITION] |= (SUPPORT_CKIP_PK|SUPPORT_CKIP_MIC) ; + tag = skb_put(skb, ckip_ie_len); + *tag++ = MFIE_TYPE_AIRONET; + *tag++ = osCcxAironetIE.Length; + memcpy(tag,osCcxAironetIE.Octet,osCcxAironetIE.Length); + tag += osCcxAironetIE.Length; + } + + if(beacon->bCcxRmEnable) + { + static u8 CcxRmCapBuf[] = {0x00, 0x40, 0x96, 0x01, 0x01, 0x00}; + OCTET_STRING osCcxRmCap; + + osCcxRmCap.Octet = CcxRmCapBuf; + osCcxRmCap.Length = sizeof(CcxRmCapBuf); + tag = skb_put(skb,ccxrm_ie_len); + *tag++ = MFIE_TYPE_GENERIC; + *tag++ = osCcxRmCap.Length; + memcpy(tag,osCcxRmCap.Octet,osCcxRmCap.Length); + tag += osCcxRmCap.Length; + } + + if( beacon->BssCcxVerNumber >= 2 ) + { + u8 CcxVerNumBuf[] = {0x00, 0x40, 0x96, 0x03, 0x00}; + OCTET_STRING osCcxVerNum; + CcxVerNumBuf[4] = beacon->BssCcxVerNumber; + osCcxVerNum.Octet = CcxVerNumBuf; + osCcxVerNum.Length = sizeof(CcxVerNumBuf); + tag = skb_put(skb,cxvernum_ie_len); + *tag++ = MFIE_TYPE_GENERIC; + *tag++ = osCcxVerNum.Length; + memcpy(tag,osCcxVerNum.Octet,osCcxVerNum.Length); + tag += osCcxVerNum.Length; + } + //HT cap element + if(ieee->pHTInfo->bCurrentHTSupport&&ieee->pHTInfo->bEnableHT){ + if(ieee->pHTInfo->ePeerHTSpecVer != HT_SPEC_VER_EWC) + { + tag = skb_put(skb, ht_cap_len); + *tag++ = MFIE_TYPE_HT_CAP; + *tag++ = ht_cap_len - 2; + memcpy(tag, ht_cap_buf,ht_cap_len -2); + tag += ht_cap_len -2; + } + } + + + //choose what wpa_supplicant gives to associate. + tag = skb_put(skb, wpa_ie_len); + if (wpa_ie_len){ + memcpy(tag, ieee->wpa_ie, ieee->wpa_ie_len); + } + + tag = skb_put(skb,wmm_info_len); + if(wmm_info_len) { + ieee80211_WMM_Info(ieee, &tag); + } +#ifdef THOMAS_TURBO + tag = skb_put(skb,turbo_info_len); + if(turbo_info_len) { + ieee80211_TURBO_Info(ieee, &tag); + } +#endif + + if(ieee->pHTInfo->bCurrentHTSupport&&ieee->pHTInfo->bEnableHT){ + if(ieee->pHTInfo->ePeerHTSpecVer == HT_SPEC_VER_EWC) + { + tag = skb_put(skb, ht_cap_len); + *tag++ = MFIE_TYPE_GENERIC; + *tag++ = ht_cap_len - 2; + memcpy(tag, ht_cap_buf,ht_cap_len - 2); + tag += ht_cap_len -2; + } + + if(ieee->pHTInfo->bCurrentRT2RTAggregation){ + tag = skb_put(skb, realtek_ie_len); + *tag++ = MFIE_TYPE_GENERIC; + *tag++ = realtek_ie_len - 2; + memcpy(tag, realtek_ie_buf,realtek_ie_len -2 ); + } + } +// printk("<=====%s(), %p, %p\n", __FUNCTION__, ieee->dev, ieee->dev->dev_addr); +// IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA, skb->data, skb->len); + return skb; +} + +void ieee80211_associate_abort(struct ieee80211_device *ieee) +{ + + unsigned long flags; + spin_lock_irqsave(&ieee->lock, flags); + + ieee->associate_seq++; + + /* don't scan, and avoid to have the RX path possibily + * try again to associate. Even do not react to AUTH or + * ASSOC response. Just wait for the retry wq to be scheduled. + * Here we will check if there are good nets to associate + * with, so we retry or just get back to NO_LINK and scanning + */ + if (ieee->state == IEEE80211_ASSOCIATING_AUTHENTICATING){ + IEEE80211_DEBUG_MGMT("Authentication failed\n"); + ieee->softmac_stats.no_auth_rs++; + }else{ + IEEE80211_DEBUG_MGMT("Association failed\n"); + ieee->softmac_stats.no_ass_rs++; + } + + ieee->state = IEEE80211_ASSOCIATING_RETRY; + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + queue_delayed_work(ieee->wq, &ieee->associate_retry_wq, \ + IEEE80211_SOFTMAC_ASSOC_RETRY_TIME); +#else + schedule_task(&ieee->associate_retry_wq); +#endif + + spin_unlock_irqrestore(&ieee->lock, flags); +} + +void ieee80211_associate_abort_cb(unsigned long dev) +{ + ieee80211_associate_abort((struct ieee80211_device *) dev); +} + + +void ieee80211_associate_step1(struct ieee80211_device *ieee) +{ + struct ieee80211_network *beacon = &ieee->current_network; + struct sk_buff *skb; + + IEEE80211_DEBUG_MGMT("Stopping scan\n"); + + ieee->softmac_stats.tx_auth_rq++; + skb=ieee80211_authentication_req(beacon, ieee, 0); + + if (!skb) + ieee80211_associate_abort(ieee); + else{ + ieee->state = IEEE80211_ASSOCIATING_AUTHENTICATING ; + IEEE80211_DEBUG_MGMT("Sending authentication request\n"); + //printk(KERN_WARNING "Sending authentication request\n"); + softmac_mgmt_xmit(skb, ieee); + //BUGON when you try to add_timer twice, using mod_timer may be better, john0709 + if(!timer_pending(&ieee->associate_timer)){ + ieee->associate_timer.expires = jiffies + (HZ / 2); + add_timer(&ieee->associate_timer); + } + //dev_kfree_skb_any(skb);//edit by thomas + } +} + +void ieee80211_auth_challenge(struct ieee80211_device *ieee, u8 *challenge, int chlen) +{ + u8 *c; + struct sk_buff *skb; + struct ieee80211_network *beacon = &ieee->current_network; +// int hlen = sizeof(struct ieee80211_authentication); + + ieee->associate_seq++; + ieee->softmac_stats.tx_auth_rq++; + + skb = ieee80211_authentication_req(beacon, ieee, chlen+2); + if (!skb) + ieee80211_associate_abort(ieee); + else{ + c = skb_put(skb, chlen+2); + *(c++) = MFIE_TYPE_CHALLENGE; + *(c++) = chlen; + memcpy(c, challenge, chlen); + + IEEE80211_DEBUG_MGMT("Sending authentication challenge response\n"); + + ieee80211_encrypt_fragment(ieee, skb, sizeof(struct ieee80211_hdr_3addr )); + + softmac_mgmt_xmit(skb, ieee); + mod_timer(&ieee->associate_timer, jiffies + (HZ/2)); +#if 0 + ieee->associate_timer.expires = jiffies + (HZ / 2); + add_timer(&ieee->associate_timer); +#endif + //dev_kfree_skb_any(skb);//edit by thomas + } + kfree(challenge); +} + +void ieee80211_associate_step2(struct ieee80211_device *ieee) +{ + struct sk_buff* skb; + struct ieee80211_network *beacon = &ieee->current_network; + + del_timer_sync(&ieee->associate_timer); + + IEEE80211_DEBUG_MGMT("Sending association request\n"); + + ieee->softmac_stats.tx_ass_rq++; + skb=ieee80211_association_req(beacon, ieee); + if (!skb) + ieee80211_associate_abort(ieee); + else{ + softmac_mgmt_xmit(skb, ieee); + mod_timer(&ieee->associate_timer, jiffies + (HZ/2)); +#if 0 + ieee->associate_timer.expires = jiffies + (HZ / 2); + add_timer(&ieee->associate_timer); +#endif + //dev_kfree_skb_any(skb);//edit by thomas + } +} +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) +void ieee80211_associate_complete_wq(struct work_struct *work) +{ + struct ieee80211_device *ieee = container_of(work, struct ieee80211_device, associate_complete_wq); +#else +void ieee80211_associate_complete_wq(struct ieee80211_device *ieee) +{ +#endif + printk(KERN_INFO "Associated successfully\n"); + ieee->is_roaming = false; + if(ieee80211_is_54g(ieee->current_network) && + (ieee->modulation & IEEE80211_OFDM_MODULATION)){ + + ieee->rate = 108; + printk(KERN_INFO"Using G rates:%d\n", ieee->rate); + }else{ + ieee->rate = 22; + printk(KERN_INFO"Using B rates:%d\n", ieee->rate); + } + if (ieee->pHTInfo->bCurrentHTSupport&&ieee->pHTInfo->bEnableHT) + { + printk("Successfully associated, ht enabled\n"); + HTOnAssocRsp(ieee); + } + else + { + printk("Successfully associated, ht not enabled(%d, %d)\n", ieee->pHTInfo->bCurrentHTSupport, ieee->pHTInfo->bEnableHT); + memset(ieee->dot11HTOperationalRateSet, 0, 16); + //HTSetConnectBwMode(ieee, HT_CHANNEL_WIDTH_20, HT_EXTCHNL_OFFSET_NO_EXT); + } + ieee->LinkDetectInfo.SlotNum = 2 * (1 + ieee->current_network.beacon_interval/500); + // To prevent the immediately calling watch_dog after association. + if(ieee->LinkDetectInfo.NumRecvBcnInPeriod==0||ieee->LinkDetectInfo.NumRecvDataInPeriod==0 ) + { + ieee->LinkDetectInfo.NumRecvBcnInPeriod = 1; + ieee->LinkDetectInfo.NumRecvDataInPeriod= 1; + } + ieee->link_change(ieee->dev); + if(ieee->is_silent_reset == 0){ + printk("============>normal associate\n"); + notify_wx_assoc_event(ieee); + } + else if(ieee->is_silent_reset == 1) + { + printk("==================>silent reset associate\n"); + ieee->is_silent_reset = 0; + } + + if (ieee->data_hard_resume) + ieee->data_hard_resume(ieee->dev); + netif_carrier_on(ieee->dev); +} + +void ieee80211_associate_complete(struct ieee80211_device *ieee) +{ +// int i; +// struct net_device* dev = ieee->dev; + del_timer_sync(&ieee->associate_timer); + +#if 0 + for(i = 0; i < 6; i++) { + ieee->seq_ctrl[i] = 0; + } +#endif + ieee->state = IEEE80211_LINKED; +#if 0 + if (ieee->pHTInfo->bCurrentHTSupport) + { + printk("Successfully associated, ht enabled\n"); + queue_work(ieee->wq, &ieee->ht_onAssRsp); + } + else + { + printk("Successfully associated, ht not enabled\n"); + memset(ieee->dot11HTOperationalRateSet, 0, 16); + HTSetConnectBwMode(ieee, HT_CHANNEL_WIDTH_20, HT_EXTCHNL_OFFSET_NO_EXT); + } +#endif + //ieee->UpdateHalRATRTableHandler(dev, ieee->dot11HTOperationalRateSet); +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + queue_work(ieee->wq, &ieee->associate_complete_wq); +#else + schedule_task(&ieee->associate_complete_wq); +#endif +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) +void ieee80211_associate_procedure_wq(struct work_struct *work) +{ + struct ieee80211_device *ieee = container_of(work, struct ieee80211_device, associate_procedure_wq); +#else +void ieee80211_associate_procedure_wq(struct ieee80211_device *ieee) +{ +#endif + ieee->sync_scan_hurryup = 1; + down(&ieee->wx_sem); + + if (ieee->data_hard_stop) + ieee->data_hard_stop(ieee->dev); + + ieee80211_stop_scan(ieee); + printk("===>%s(), chan:%d\n", __FUNCTION__, ieee->current_network.channel); + //ieee->set_chan(ieee->dev, ieee->current_network.channel); + HTSetConnectBwMode(ieee, HT_CHANNEL_WIDTH_20, HT_EXTCHNL_OFFSET_NO_EXT); + + ieee->associate_seq = 1; + ieee80211_associate_step1(ieee); + + up(&ieee->wx_sem); +} + +inline void ieee80211_softmac_new_net(struct ieee80211_device *ieee, struct ieee80211_network *net) +{ + u8 tmp_ssid[IW_ESSID_MAX_SIZE+1]; + int tmp_ssid_len = 0; + + short apset,ssidset,ssidbroad,apmatch,ssidmatch; + + /* we are interested in new new only if we are not associated + * and we are not associating / authenticating + */ + if (ieee->state != IEEE80211_NOLINK) + return; + + if ((ieee->iw_mode == IW_MODE_INFRA) && !(net->capability & WLAN_CAPABILITY_BSS)) + return; + + if ((ieee->iw_mode == IW_MODE_ADHOC) && !(net->capability & WLAN_CAPABILITY_IBSS)) + return; + + + if (ieee->iw_mode == IW_MODE_INFRA || ieee->iw_mode == IW_MODE_ADHOC){ + /* if the user specified the AP MAC, we need also the essid + * This could be obtained by beacons or, if the network does not + * broadcast it, it can be put manually. + */ + apset = ieee->wap_set;//(memcmp(ieee->current_network.bssid, zero,ETH_ALEN)!=0 ); + ssidset = ieee->ssid_set;//ieee->current_network.ssid[0] != '\0'; + ssidbroad = !(net->ssid_len == 0 || net->ssid[0]== '\0'); + apmatch = (memcmp(ieee->current_network.bssid, net->bssid, ETH_ALEN)==0); + ssidmatch = (ieee->current_network.ssid_len == net->ssid_len)&&\ + (!strncmp(ieee->current_network.ssid, net->ssid, net->ssid_len)); + + + if ( /* if the user set the AP check if match. + * if the network does not broadcast essid we check the user supplyed ANY essid + * if the network does broadcast and the user does not set essid it is OK + * if the network does broadcast and the user did set essid chech if essid match + */ + ( apset && apmatch && + ((ssidset && ssidbroad && ssidmatch) || (ssidbroad && !ssidset) || (!ssidbroad && ssidset)) ) || + /* if the ap is not set, check that the user set the bssid + * and the network does bradcast and that those two bssid matches + */ + (!apset && ssidset && ssidbroad && ssidmatch) + ){ + /* if the essid is hidden replace it with the + * essid provided by the user. + */ + if (!ssidbroad){ + strncpy(tmp_ssid, ieee->current_network.ssid, IW_ESSID_MAX_SIZE); + tmp_ssid_len = ieee->current_network.ssid_len; + } + memcpy(&ieee->current_network, net, sizeof(struct ieee80211_network)); + + if (!ssidbroad){ + strncpy(ieee->current_network.ssid, tmp_ssid, IW_ESSID_MAX_SIZE); + ieee->current_network.ssid_len = tmp_ssid_len; + } + printk(KERN_INFO"Linking with %s,channel:%d, qos:%d, myHT:%d, networkHT:%d, mode:%x\n",ieee->current_network.ssid,ieee->current_network.channel, ieee->current_network.qos_data.supported, ieee->pHTInfo->bEnableHT, ieee->current_network.bssht.bdSupportHT, ieee->current_network.mode); + + //ieee->pHTInfo->IOTAction = 0; + HTResetIOTSetting(ieee->pHTInfo); + if (ieee->iw_mode == IW_MODE_INFRA){ + /* Join the network for the first time */ + ieee->AsocRetryCount = 0; + //for HT by amy 080514 + if((ieee->current_network.qos_data.supported == 1) && + // (ieee->pHTInfo->bEnableHT && ieee->current_network.bssht.bdSupportHT)) + ieee->current_network.bssht.bdSupportHT) +/*WB, 2008.09.09:bCurrentHTSupport and bEnableHT two flags are going to put together to check whether we are in HT now, so needn't to check bEnableHT flags here. That's is to say we will set to HT support whenever joined AP has the ability to support HT. And whether we are in HT or not, please check bCurrentHTSupport&&bEnableHT now please.*/ + { + // ieee->pHTInfo->bCurrentHTSupport = true; + HTResetSelfAndSavePeerSetting(ieee, &(ieee->current_network)); + } + else + { + ieee->pHTInfo->bCurrentHTSupport = false; + } + + ieee->state = IEEE80211_ASSOCIATING; + if(ieee->LedControlHandler != NULL) + ieee->LedControlHandler(ieee->dev, LED_CTL_START_TO_LINK); +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + queue_work(ieee->wq, &ieee->associate_procedure_wq); +#else + schedule_task(&ieee->associate_procedure_wq); +#endif + }else{ + if(ieee80211_is_54g(ieee->current_network) && + (ieee->modulation & IEEE80211_OFDM_MODULATION)){ + ieee->rate = 108; + ieee->SetWirelessMode(ieee->dev, IEEE_G); + printk(KERN_INFO"Using G rates\n"); + }else{ + ieee->rate = 22; + ieee->SetWirelessMode(ieee->dev, IEEE_B); + printk(KERN_INFO"Using B rates\n"); + } + memset(ieee->dot11HTOperationalRateSet, 0, 16); + //HTSetConnectBwMode(ieee, HT_CHANNEL_WIDTH_20, HT_EXTCHNL_OFFSET_NO_EXT); + ieee->state = IEEE80211_LINKED; + } + + } + } + +} + +void ieee80211_softmac_check_all_nets(struct ieee80211_device *ieee) +{ + unsigned long flags; + struct ieee80211_network *target; + + spin_lock_irqsave(&ieee->lock, flags); + + list_for_each_entry(target, &ieee->network_list, list) { + + /* if the state become different that NOLINK means + * we had found what we are searching for + */ + + if (ieee->state != IEEE80211_NOLINK) + break; + + if (ieee->scan_age == 0 || time_after(target->last_scanned + ieee->scan_age, jiffies)) + ieee80211_softmac_new_net(ieee, target); + } + + spin_unlock_irqrestore(&ieee->lock, flags); + +} + + +static inline u16 auth_parse(struct sk_buff *skb, u8** challenge, int *chlen) +{ + struct ieee80211_authentication *a; + u8 *t; + if (skb->len < (sizeof(struct ieee80211_authentication)-sizeof(struct ieee80211_info_element))){ + IEEE80211_DEBUG_MGMT("invalid len in auth resp: %d\n",skb->len); + return 0xcafe; + } + *challenge = NULL; + a = (struct ieee80211_authentication*) skb->data; + if(skb->len > (sizeof(struct ieee80211_authentication) +3)){ + t = skb->data + sizeof(struct ieee80211_authentication); + + if(*(t++) == MFIE_TYPE_CHALLENGE){ + *chlen = *(t++); + *challenge = (u8*)kmalloc(*chlen, GFP_ATOMIC); + memcpy(*challenge, t, *chlen); + } + } + + return cpu_to_le16(a->status); + +} + + +int auth_rq_parse(struct sk_buff *skb,u8* dest) +{ + struct ieee80211_authentication *a; + + if (skb->len < (sizeof(struct ieee80211_authentication)-sizeof(struct ieee80211_info_element))){ + IEEE80211_DEBUG_MGMT("invalid len in auth request: %d\n",skb->len); + return -1; + } + a = (struct ieee80211_authentication*) skb->data; + + memcpy(dest,a->header.addr2, ETH_ALEN); + + if (le16_to_cpu(a->algorithm) != WLAN_AUTH_OPEN) + return WLAN_STATUS_NOT_SUPPORTED_AUTH_ALG; + + return WLAN_STATUS_SUCCESS; +} + +static short probe_rq_parse(struct ieee80211_device *ieee, struct sk_buff *skb, u8 *src) +{ + u8 *tag; + u8 *skbend; + u8 *ssid=NULL; + u8 ssidlen = 0; + + struct ieee80211_hdr_3addr *header = + (struct ieee80211_hdr_3addr *) skb->data; + + if (skb->len < sizeof (struct ieee80211_hdr_3addr )) + return -1; /* corrupted */ + + memcpy(src,header->addr2, ETH_ALEN); + + skbend = (u8*)skb->data + skb->len; + + tag = skb->data + sizeof (struct ieee80211_hdr_3addr ); + + while (tag+1 < skbend){ + if (*tag == 0){ + ssid = tag+2; + ssidlen = *(tag+1); + break; + } + tag++; /* point to the len field */ + tag = tag + *(tag); /* point to the last data byte of the tag */ + tag++; /* point to the next tag */ + } + + //IEEE80211DMESG("Card MAC address is "MACSTR, MAC2STR(src)); + if (ssidlen == 0) return 1; + + if (!ssid) return 1; /* ssid not found in tagged param */ + return (!strncmp(ssid, ieee->current_network.ssid, ssidlen)); + +} + +int assoc_rq_parse(struct sk_buff *skb,u8* dest) +{ + struct ieee80211_assoc_request_frame *a; + + if (skb->len < (sizeof(struct ieee80211_assoc_request_frame) - + sizeof(struct ieee80211_info_element))) { + + IEEE80211_DEBUG_MGMT("invalid len in auth request:%d \n", skb->len); + return -1; + } + + a = (struct ieee80211_assoc_request_frame*) skb->data; + + memcpy(dest,a->header.addr2,ETH_ALEN); + + return 0; +} + +static inline u16 assoc_parse(struct ieee80211_device *ieee, struct sk_buff *skb, int *aid) +{ + struct ieee80211_assoc_response_frame *response_head; + u16 status_code; + + if (skb->len < sizeof(struct ieee80211_assoc_response_frame)){ + IEEE80211_DEBUG_MGMT("invalid len in auth resp: %d\n", skb->len); + return 0xcafe; + } + + response_head = (struct ieee80211_assoc_response_frame*) skb->data; + *aid = le16_to_cpu(response_head->aid) & 0x3fff; + + status_code = le16_to_cpu(response_head->status); + if((status_code==WLAN_STATUS_ASSOC_DENIED_RATES || \ + status_code==WLAN_STATUS_CAPS_UNSUPPORTED)&& + ((ieee->mode == IEEE_G) && + (ieee->current_network.mode == IEEE_N_24G) && + (ieee->AsocRetryCount++ < (RT_ASOC_RETRY_LIMIT-1)))) { + ieee->pHTInfo->IOTAction |= HT_IOT_ACT_PURE_N_MODE; + }else { + ieee->AsocRetryCount = 0; + } + + return le16_to_cpu(response_head->status); +} + +static inline void +ieee80211_rx_probe_rq(struct ieee80211_device *ieee, struct sk_buff *skb) +{ + u8 dest[ETH_ALEN]; + + //IEEE80211DMESG("Rx probe"); + ieee->softmac_stats.rx_probe_rq++; + //DMESG("Dest is "MACSTR, MAC2STR(dest)); + if (probe_rq_parse(ieee, skb, dest)){ + //IEEE80211DMESG("Was for me!"); + ieee->softmac_stats.tx_probe_rs++; + ieee80211_resp_to_probe(ieee, dest); + } +} + +static inline void +ieee80211_rx_auth_rq(struct ieee80211_device *ieee, struct sk_buff *skb) +{ + u8 dest[ETH_ALEN]; + int status; + //IEEE80211DMESG("Rx probe"); + ieee->softmac_stats.rx_auth_rq++; + + if ((status = auth_rq_parse(skb, dest))!= -1){ + ieee80211_resp_to_auth(ieee, status, dest); + } + //DMESG("Dest is "MACSTR, MAC2STR(dest)); + +} + +static inline void +ieee80211_rx_assoc_rq(struct ieee80211_device *ieee, struct sk_buff *skb) +{ + + u8 dest[ETH_ALEN]; + //unsigned long flags; + + ieee->softmac_stats.rx_ass_rq++; + if (assoc_rq_parse(skb,dest) != -1){ + ieee80211_resp_to_assoc_rq(ieee, dest); + } + + printk(KERN_INFO"New client associated: "MAC_FMT"\n", MAC_ARG(dest)); + //FIXME + #if 0 + spin_lock_irqsave(&ieee->lock,flags); + add_associate(ieee,dest); + spin_unlock_irqrestore(&ieee->lock,flags); + #endif +} + + + +void ieee80211_sta_ps_send_null_frame(struct ieee80211_device *ieee, short pwr) +{ + + struct sk_buff *buf = ieee80211_null_func(ieee, pwr); + + if (buf) + softmac_ps_mgmt_xmit(buf, ieee); + +} + + +short ieee80211_sta_ps_sleep(struct ieee80211_device *ieee, u32 *time_h, u32 *time_l) +{ + int timeout = ieee->ps_timeout; + u8 dtim; + /*if(ieee->ps == IEEE80211_PS_DISABLED || + ieee->iw_mode != IW_MODE_INFRA || + ieee->state != IEEE80211_LINKED) + + return 0; + */ + dtim = ieee->current_network.dtim_data; + //printk("DTIM\n"); + if(!(dtim & IEEE80211_DTIM_VALID)) + return 0; + timeout = ieee->current_network.beacon_interval; //should we use ps_timeout value or beacon_interval + //printk("VALID\n"); + ieee->current_network.dtim_data = IEEE80211_DTIM_INVALID; + + if(dtim & ((IEEE80211_DTIM_UCAST | IEEE80211_DTIM_MBCAST)& ieee->ps)) + return 2; + + if(!time_after(jiffies, ieee->dev->trans_start + MSECS(timeout))) + return 0; + + if(!time_after(jiffies, ieee->last_rx_ps_time + MSECS(timeout))) + return 0; + + if((ieee->softmac_features & IEEE_SOFTMAC_SINGLE_QUEUE ) && + (ieee->mgmt_queue_tail != ieee->mgmt_queue_head)) + return 0; + + if(time_l){ + *time_l = ieee->current_network.last_dtim_sta_time[0] + + (ieee->current_network.beacon_interval); + // * ieee->current_network.dtim_period) * 1000; + } + + if(time_h){ + *time_h = ieee->current_network.last_dtim_sta_time[1]; + if(time_l && *time_l < ieee->current_network.last_dtim_sta_time[0]) + *time_h += 1; + } + + return 1; + + +} + +inline void ieee80211_sta_ps(struct ieee80211_device *ieee) +{ + + u32 th,tl; + short sleep; + + unsigned long flags,flags2; + + spin_lock_irqsave(&ieee->lock, flags); + + if((ieee->ps == IEEE80211_PS_DISABLED || + ieee->iw_mode != IW_MODE_INFRA || + ieee->state != IEEE80211_LINKED)){ + + // #warning CHECK_LOCK_HERE + spin_lock_irqsave(&ieee->mgmt_tx_lock, flags2); + + ieee80211_sta_wakeup(ieee, 1); + + spin_unlock_irqrestore(&ieee->mgmt_tx_lock, flags2); + } + + sleep = ieee80211_sta_ps_sleep(ieee,&th, &tl); + /* 2 wake, 1 sleep, 0 do nothing */ + if(sleep == 0) + goto out; + + if(sleep == 1){ + + if(ieee->sta_sleep == 1) + ieee->enter_sleep_state(ieee->dev,th,tl); + + else if(ieee->sta_sleep == 0){ + // printk("send null 1\n"); + spin_lock_irqsave(&ieee->mgmt_tx_lock, flags2); + + if(ieee->ps_is_queue_empty(ieee->dev)){ + + + ieee->sta_sleep = 2; + + ieee->ack_tx_to_ieee = 1; + + ieee80211_sta_ps_send_null_frame(ieee,1); + + ieee->ps_th = th; + ieee->ps_tl = tl; + } + spin_unlock_irqrestore(&ieee->mgmt_tx_lock, flags2); + + } + + + }else if(sleep == 2){ +//#warning CHECK_LOCK_HERE + spin_lock_irqsave(&ieee->mgmt_tx_lock, flags2); + + ieee80211_sta_wakeup(ieee,1); + + spin_unlock_irqrestore(&ieee->mgmt_tx_lock, flags2); + } + +out: + spin_unlock_irqrestore(&ieee->lock, flags); + +} + +void ieee80211_sta_wakeup(struct ieee80211_device *ieee, short nl) +{ + if(ieee->sta_sleep == 0){ + if(nl){ + printk("Warning: driver is probably failing to report TX ps error\n"); + ieee->ack_tx_to_ieee = 1; + ieee80211_sta_ps_send_null_frame(ieee, 0); + } + return; + + } + + if(ieee->sta_sleep == 1) + ieee->sta_wake_up(ieee->dev); + + ieee->sta_sleep = 0; + + if(nl){ + ieee->ack_tx_to_ieee = 1; + ieee80211_sta_ps_send_null_frame(ieee, 0); + } +} + +void ieee80211_ps_tx_ack(struct ieee80211_device *ieee, short success) +{ + unsigned long flags,flags2; + + spin_lock_irqsave(&ieee->lock, flags); + + if(ieee->sta_sleep == 2){ + /* Null frame with PS bit set */ + if(success){ + ieee->sta_sleep = 1; + ieee->enter_sleep_state(ieee->dev,ieee->ps_th,ieee->ps_tl); + } + /* if the card report not success we can't be sure the AP + * has not RXed so we can't assume the AP believe us awake + */ + } + /* 21112005 - tx again null without PS bit if lost */ + else { + + if((ieee->sta_sleep == 0) && !success){ + spin_lock_irqsave(&ieee->mgmt_tx_lock, flags2); + ieee80211_sta_ps_send_null_frame(ieee, 0); + spin_unlock_irqrestore(&ieee->mgmt_tx_lock, flags2); + } + } + spin_unlock_irqrestore(&ieee->lock, flags); +} +void ieee80211_process_action(struct ieee80211_device* ieee, struct sk_buff* skb) +{ + struct ieee80211_hdr* header = (struct ieee80211_hdr*)skb->data; + u8* act = ieee80211_get_payload(header); + u8 tmp = 0; +// IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA|IEEE80211_DL_BA, skb->data, skb->len); + if (act == NULL) + { + IEEE80211_DEBUG(IEEE80211_DL_ERR, "error to get payload of action frame\n"); + return; + } + tmp = *act; + act ++; + switch (tmp) + { + case ACT_CAT_BA: + if (*act == ACT_ADDBAREQ) + ieee80211_rx_ADDBAReq(ieee, skb); + else if (*act == ACT_ADDBARSP) + ieee80211_rx_ADDBARsp(ieee, skb); + else if (*act == ACT_DELBA) + ieee80211_rx_DELBA(ieee, skb); + break; + default: +// if (net_ratelimit()) +// IEEE80211_DEBUG(IEEE80211_DL_BA, "unknown action frame(%d)\n", tmp); + break; + } + return; + +} +inline int +ieee80211_rx_frame_softmac(struct ieee80211_device *ieee, struct sk_buff *skb, + struct ieee80211_rx_stats *rx_stats, u16 type, + u16 stype) +{ + struct ieee80211_hdr_3addr *header = (struct ieee80211_hdr_3addr *) skb->data; + u16 errcode; + u8* challenge; + int chlen=0; + int aid; + struct ieee80211_assoc_response_frame *assoc_resp; +// struct ieee80211_info_element *info_element; + bool bSupportNmode = true, bHalfSupportNmode = false; //default support N mode, disable halfNmode + + if(!ieee->proto_started) + return 0; +#if 0 + printk("%d, %d, %d, %d\n", ieee->sta_sleep, ieee->ps, ieee->iw_mode, ieee->state); + if(ieee->sta_sleep || (ieee->ps != IEEE80211_PS_DISABLED && + ieee->iw_mode == IW_MODE_INFRA && + ieee->state == IEEE80211_LINKED)) + + tasklet_schedule(&ieee->ps_task); + + if(WLAN_FC_GET_STYPE(header->frame_ctl) != IEEE80211_STYPE_PROBE_RESP && + WLAN_FC_GET_STYPE(header->frame_ctl) != IEEE80211_STYPE_BEACON) + ieee->last_rx_ps_time = jiffies; +#endif + + switch (WLAN_FC_GET_STYPE(header->frame_ctl)) { + + case IEEE80211_STYPE_ASSOC_RESP: + case IEEE80211_STYPE_REASSOC_RESP: + + IEEE80211_DEBUG_MGMT("received [RE]ASSOCIATION RESPONSE (%d)\n", + WLAN_FC_GET_STYPE(header->frame_ctl)); + if ((ieee->softmac_features & IEEE_SOFTMAC_ASSOCIATE) && + ieee->state == IEEE80211_ASSOCIATING_AUTHENTICATED && + ieee->iw_mode == IW_MODE_INFRA){ + struct ieee80211_network network_resp; + struct ieee80211_network *network = &network_resp; + + if (0 == (errcode=assoc_parse(ieee,skb, &aid))){ + ieee->state=IEEE80211_LINKED; + ieee->assoc_id = aid; + ieee->softmac_stats.rx_ass_ok++; + /* station support qos */ + /* Let the register setting defaultly with Legacy station */ + if(ieee->qos_support) { + assoc_resp = (struct ieee80211_assoc_response_frame*)skb->data; + memset(network, 0, sizeof(*network)); + if (ieee80211_parse_info_param(ieee,assoc_resp->info_element,\ + rx_stats->len - sizeof(*assoc_resp),\ + network,rx_stats)){ + return 1; + } + else + { //filling the PeerHTCap. //maybe not neccesary as we can get its info from current_network. + memcpy(ieee->pHTInfo->PeerHTCapBuf, network->bssht.bdHTCapBuf, network->bssht.bdHTCapLen); + memcpy(ieee->pHTInfo->PeerHTInfoBuf, network->bssht.bdHTInfoBuf, network->bssht.bdHTInfoLen); + } + if (ieee->handle_assoc_response != NULL) + ieee->handle_assoc_response(ieee->dev, (struct ieee80211_assoc_response_frame*)header, network); + } + ieee80211_associate_complete(ieee); + } else { + /* aid could not been allocated */ + ieee->softmac_stats.rx_ass_err++; + printk( + "Association response status code 0x%x\n", + errcode); + IEEE80211_DEBUG_MGMT( + "Association response status code 0x%x\n", + errcode); + if(ieee->AsocRetryCount < RT_ASOC_RETRY_LIMIT) { +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + queue_work(ieee->wq, &ieee->associate_procedure_wq); +#else + schedule_task(&ieee->associate_procedure_wq); +#endif + } else { + ieee80211_associate_abort(ieee); + } + } + } + break; + + case IEEE80211_STYPE_ASSOC_REQ: + case IEEE80211_STYPE_REASSOC_REQ: + + if ((ieee->softmac_features & IEEE_SOFTMAC_ASSOCIATE) && + ieee->iw_mode == IW_MODE_MASTER) + + ieee80211_rx_assoc_rq(ieee, skb); + break; + + case IEEE80211_STYPE_AUTH: + + if (ieee->softmac_features & IEEE_SOFTMAC_ASSOCIATE){ + if (ieee->state == IEEE80211_ASSOCIATING_AUTHENTICATING && + ieee->iw_mode == IW_MODE_INFRA){ + + IEEE80211_DEBUG_MGMT("Received authentication response"); + + if (0 == (errcode=auth_parse(skb, &challenge, &chlen))){ + if(ieee->open_wep || !challenge){ + ieee->state = IEEE80211_ASSOCIATING_AUTHENTICATED; + ieee->softmac_stats.rx_auth_rs_ok++; + if(!(ieee->pHTInfo->IOTAction&HT_IOT_ACT_PURE_N_MODE)) + { + if (!ieee->GetNmodeSupportBySecCfg(ieee->dev)) + { + // WEP or TKIP encryption + if(IsHTHalfNmodeAPs(ieee)) + { + bSupportNmode = true; + bHalfSupportNmode = true; + } + else + { + bSupportNmode = false; + bHalfSupportNmode = false; + } + printk("==========>to link with AP using SEC(%d, %d)", bSupportNmode, bHalfSupportNmode); + } + } + /* Dummy wirless mode setting to avoid encryption issue */ + if(bSupportNmode) { + //N mode setting + ieee->SetWirelessMode(ieee->dev, \ + ieee->current_network.mode); + }else{ + //b/g mode setting + /*TODO*/ + ieee->SetWirelessMode(ieee->dev, IEEE_G); + } + + if (ieee->current_network.mode == IEEE_N_24G && bHalfSupportNmode == true) + { + printk("===============>entern half N mode\n"); + ieee->bHalfWirelessN24GMode = true; + } + else + ieee->bHalfWirelessN24GMode = false; + + ieee80211_associate_step2(ieee); + }else{ + ieee80211_auth_challenge(ieee, challenge, chlen); + } + }else{ + ieee->softmac_stats.rx_auth_rs_err++; + IEEE80211_DEBUG_MGMT("Authentication respose status code 0x%x",errcode); + + printk("Authentication respose status code 0x%x",errcode); + ieee80211_associate_abort(ieee); + } + + }else if (ieee->iw_mode == IW_MODE_MASTER){ + ieee80211_rx_auth_rq(ieee, skb); + } + } + break; + + case IEEE80211_STYPE_PROBE_REQ: + + if ((ieee->softmac_features & IEEE_SOFTMAC_PROBERS) && + ((ieee->iw_mode == IW_MODE_ADHOC || + ieee->iw_mode == IW_MODE_MASTER) && + ieee->state == IEEE80211_LINKED)){ + ieee80211_rx_probe_rq(ieee, skb); + } + break; + + case IEEE80211_STYPE_DISASSOC: + case IEEE80211_STYPE_DEAUTH: + /* FIXME for now repeat all the association procedure + * both for disassociation and deauthentication + */ + if ((ieee->softmac_features & IEEE_SOFTMAC_ASSOCIATE) && + ieee->state == IEEE80211_LINKED && + ieee->iw_mode == IW_MODE_INFRA){ + printk("==========>received disassoc/deauth(%x) frame, reason code:%x\n",WLAN_FC_GET_STYPE(header->frame_ctl), ((struct ieee80211_disassoc*)skb->data)->reason); + ieee->state = IEEE80211_ASSOCIATING; + ieee->softmac_stats.reassoc++; + ieee->is_roaming = true; + ieee80211_disassociate(ieee); + // notify_wx_assoc_event(ieee); + //HTSetConnectBwMode(ieee, HT_CHANNEL_WIDTH_20, HT_EXTCHNL_OFFSET_NO_EXT); + RemovePeerTS(ieee, header->addr2); + if(ieee->LedControlHandler != NULL) + ieee->LedControlHandler(ieee->dev, LED_CTL_START_TO_LINK); //added by amy for LED 090318 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + queue_work(ieee->wq, &ieee->associate_procedure_wq); +#else + schedule_task(&ieee->associate_procedure_wq); +#endif + } + break; + case IEEE80211_STYPE_MANAGE_ACT: + ieee80211_process_action(ieee,skb); + break; + default: + return -1; + break; + } + + //dev_kfree_skb_any(skb); + return 0; +} + +/* following are for a simplier TX queue management. + * Instead of using netif_[stop/wake]_queue the driver + * will uses these two function (plus a reset one), that + * will internally uses the kernel netif_* and takes + * care of the ieee802.11 fragmentation. + * So the driver receives a fragment per time and might + * call the stop function when it want without take care + * to have enought room to TX an entire packet. + * This might be useful if each fragment need it's own + * descriptor, thus just keep a total free memory > than + * the max fragmentation treshold is not enought.. If the + * ieee802.11 stack passed a TXB struct then you needed + * to keep N free descriptors where + * N = MAX_PACKET_SIZE / MIN_FRAG_TRESHOLD + * In this way you need just one and the 802.11 stack + * will take care of buffering fragments and pass them to + * to the driver later, when it wakes the queue. + */ +void ieee80211_softmac_xmit(struct ieee80211_txb *txb, struct ieee80211_device *ieee) +{ + + unsigned int queue_index = txb->queue_index; + unsigned long flags; + int i; + cb_desc *tcb_desc = NULL; + + spin_lock_irqsave(&ieee->lock,flags); + + /* called with 2nd parm 0, no tx mgmt lock required */ + ieee80211_sta_wakeup(ieee,0); + + /* update the tx status */ +// ieee->stats.tx_bytes += txb->payload_size; +// ieee->stats.tx_packets++; + tcb_desc = (cb_desc *)(txb->fragments[0]->cb + MAX_DEV_ADDR_SIZE); + if(tcb_desc->bMulticast) { + ieee->stats.multicast++; + } +#if 1 + /* if xmit available, just xmit it immediately, else just insert it to the wait queue */ + for(i = 0; i < txb->nr_frags; i++) { +#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE + if ((skb_queue_len(&ieee->skb_drv_aggQ[queue_index]) != 0) || +#else + if ((skb_queue_len(&ieee->skb_waitQ[queue_index]) != 0) || +#endif + (!ieee->check_nic_enough_desc(ieee->dev,queue_index))||\ + (ieee->queue_stop)) { + /* insert the skb packet to the wait queue */ + /* as for the completion function, it does not need + * to check it any more. + * */ + //printk("error:no descriptor left@queue_index %d, %d, %d\n", queue_index, skb_queue_len(&ieee->skb_waitQ[queue_index]), ieee->check_nic_enough_desc(ieee->dev,queue_index)); + //ieee80211_stop_queue(ieee); +#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE + skb_queue_tail(&ieee->skb_drv_aggQ[queue_index], txb->fragments[i]); +#else + skb_queue_tail(&ieee->skb_waitQ[queue_index], txb->fragments[i]); +#endif + }else{ + ieee->softmac_data_hard_start_xmit( + txb->fragments[i], + ieee->dev,ieee->rate); + //ieee->stats.tx_packets++; + //ieee->stats.tx_bytes += txb->fragments[i]->len; + //ieee->dev->trans_start = jiffies; + } + } +#endif + ieee80211_txb_free(txb); + +//exit: + spin_unlock_irqrestore(&ieee->lock,flags); + +} + +/* called with ieee->lock acquired */ +void ieee80211_resume_tx(struct ieee80211_device *ieee) +{ + int i; + for(i = ieee->tx_pending.frag; i < ieee->tx_pending.txb->nr_frags; i++) { + + if (ieee->queue_stop){ + ieee->tx_pending.frag = i; + return; + }else{ + + ieee->softmac_data_hard_start_xmit( + ieee->tx_pending.txb->fragments[i], + ieee->dev,ieee->rate); + //(i+1)<ieee->tx_pending.txb->nr_frags); + ieee->stats.tx_packets++; + // ieee->dev->trans_start = jiffies; + } + } + + + ieee80211_txb_free(ieee->tx_pending.txb); + ieee->tx_pending.txb = NULL; +} + + +void ieee80211_reset_queue(struct ieee80211_device *ieee) +{ + unsigned long flags; + + spin_lock_irqsave(&ieee->lock,flags); + init_mgmt_queue(ieee); + if (ieee->tx_pending.txb){ + ieee80211_txb_free(ieee->tx_pending.txb); + ieee->tx_pending.txb = NULL; + } + ieee->queue_stop = 0; + spin_unlock_irqrestore(&ieee->lock,flags); + +} + +void ieee80211_wake_queue(struct ieee80211_device *ieee) +{ + + unsigned long flags; + struct sk_buff *skb; + struct ieee80211_hdr_3addr *header; + + spin_lock_irqsave(&ieee->lock,flags); + if (! ieee->queue_stop) goto exit; + + ieee->queue_stop = 0; + + if(ieee->softmac_features & IEEE_SOFTMAC_SINGLE_QUEUE){ + while (!ieee->queue_stop && (skb = dequeue_mgmt(ieee))){ + + header = (struct ieee80211_hdr_3addr *) skb->data; + + header->seq_ctl = cpu_to_le16(ieee->seq_ctrl[0] << 4); + + if (ieee->seq_ctrl[0] == 0xFFF) + ieee->seq_ctrl[0] = 0; + else + ieee->seq_ctrl[0]++; + + ieee->softmac_data_hard_start_xmit(skb,ieee->dev,ieee->basic_rate); + //dev_kfree_skb_any(skb);//edit by thomas + } + } + if (!ieee->queue_stop && ieee->tx_pending.txb) + ieee80211_resume_tx(ieee); + + if (!ieee->queue_stop && netif_queue_stopped(ieee->dev)){ + ieee->softmac_stats.swtxawake++; + netif_wake_queue(ieee->dev); + } + +exit : + spin_unlock_irqrestore(&ieee->lock,flags); +} + + +void ieee80211_stop_queue(struct ieee80211_device *ieee) +{ + //unsigned long flags; + //spin_lock_irqsave(&ieee->lock,flags); + + if (! netif_queue_stopped(ieee->dev)){ + netif_stop_queue(ieee->dev); + ieee->softmac_stats.swtxstop++; + } + ieee->queue_stop = 1; + //spin_unlock_irqrestore(&ieee->lock,flags); + +} + + +inline void ieee80211_randomize_cell(struct ieee80211_device *ieee) +{ + + get_random_bytes(ieee->current_network.bssid, ETH_ALEN); + + /* an IBSS cell address must have the two less significant + * bits of the first byte = 2 + */ + ieee->current_network.bssid[0] &= ~0x01; + ieee->current_network.bssid[0] |= 0x02; +} + +/* called in user context only */ +void ieee80211_start_master_bss(struct ieee80211_device *ieee) +{ + ieee->assoc_id = 1; + + if (ieee->current_network.ssid_len == 0){ + strncpy(ieee->current_network.ssid, + IEEE80211_DEFAULT_TX_ESSID, + IW_ESSID_MAX_SIZE); + + ieee->current_network.ssid_len = strlen(IEEE80211_DEFAULT_TX_ESSID); + ieee->ssid_set = 1; + } + + memcpy(ieee->current_network.bssid, ieee->dev->dev_addr, ETH_ALEN); + + ieee->set_chan(ieee->dev, ieee->current_network.channel); + ieee->state = IEEE80211_LINKED; + ieee->link_change(ieee->dev); + notify_wx_assoc_event(ieee); + + if (ieee->data_hard_resume) + ieee->data_hard_resume(ieee->dev); + + netif_carrier_on(ieee->dev); +} + +void ieee80211_start_monitor_mode(struct ieee80211_device *ieee) +{ + if(ieee->raw_tx){ + + if (ieee->data_hard_resume) + ieee->data_hard_resume(ieee->dev); + + netif_carrier_on(ieee->dev); + } +} +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) +void ieee80211_start_ibss_wq(struct work_struct *work) +{ + + struct delayed_work *dwork = container_of(work, struct delayed_work, work); + struct ieee80211_device *ieee = container_of(dwork, struct ieee80211_device, start_ibss_wq); +#else +void ieee80211_start_ibss_wq(struct ieee80211_device *ieee) +{ +#endif + /* iwconfig mode ad-hoc will schedule this and return + * on the other hand this will block further iwconfig SET + * operations because of the wx_sem hold. + * Anyway some most set operations set a flag to speed-up + * (abort) this wq (when syncro scanning) before sleeping + * on the semaphore + */ + if(!ieee->proto_started){ + printk("==========oh driver down return\n"); + return; + } + down(&ieee->wx_sem); + //FIXME:set back to 20M whenever HT for ibss is not ready. Otherwise,after being connected to 40M AP, it will still stay in 40M when set to ibss mode. WB 2009.02.04 + HTSetConnectBwMode(ieee, HT_CHANNEL_WIDTH_20, HT_EXTCHNL_OFFSET_NO_EXT); + + if (ieee->current_network.ssid_len == 0){ + strcpy(ieee->current_network.ssid,IEEE80211_DEFAULT_TX_ESSID); + ieee->current_network.ssid_len = strlen(IEEE80211_DEFAULT_TX_ESSID); + ieee->ssid_set = 1; + } + + /* check if we have this cell in our network list */ + ieee80211_softmac_check_all_nets(ieee); + + +#ifdef ENABLE_DOT11D //if creating an ad-hoc, set its channel to 10 temporarily--this is the requirement for ASUS, not 11D, so disable 11d. +// if((IS_DOT11D_ENABLE(ieee)) && (ieee->state == IEEE80211_NOLINK)) + if (ieee->state == IEEE80211_NOLINK) + ieee->current_network.channel = 6; +#endif + /* if not then the state is not linked. Maybe the user swithced to + * ad-hoc mode just after being in monitor mode, or just after + * being very few time in managed mode (so the card have had no + * time to scan all the chans..) or we have just run up the iface + * after setting ad-hoc mode. So we have to give another try.. + * Here, in ibss mode, should be safe to do this without extra care + * (in bss mode we had to make sure no-one tryed to associate when + * we had just checked the ieee->state and we was going to start the + * scan) beacause in ibss mode the ieee80211_new_net function, when + * finds a good net, just set the ieee->state to IEEE80211_LINKED, + * so, at worst, we waste a bit of time to initiate an unneeded syncro + * scan, that will stop at the first round because it sees the state + * associated. + */ + if (ieee->state == IEEE80211_NOLINK) + ieee80211_start_scan_syncro(ieee); + + /* the network definitively is not here.. create a new cell */ + if (ieee->state == IEEE80211_NOLINK){ + printk("creating new IBSS cell\n"); + if(!ieee->wap_set) + ieee80211_randomize_cell(ieee); + + if(ieee->modulation & IEEE80211_CCK_MODULATION){ + + ieee->current_network.rates_len = 4; + + ieee->current_network.rates[0] = IEEE80211_BASIC_RATE_MASK | IEEE80211_CCK_RATE_1MB; + ieee->current_network.rates[1] = IEEE80211_BASIC_RATE_MASK | IEEE80211_CCK_RATE_2MB; + ieee->current_network.rates[2] = IEEE80211_BASIC_RATE_MASK | IEEE80211_CCK_RATE_5MB; + ieee->current_network.rates[3] = IEEE80211_BASIC_RATE_MASK | IEEE80211_CCK_RATE_11MB; + + }else + ieee->current_network.rates_len = 0; + + if(ieee->modulation & IEEE80211_OFDM_MODULATION){ + ieee->current_network.rates_ex_len = 8; + + ieee->current_network.rates_ex[0] = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_6MB; + ieee->current_network.rates_ex[1] = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_9MB; + ieee->current_network.rates_ex[2] = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_12MB; + ieee->current_network.rates_ex[3] = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_18MB; + ieee->current_network.rates_ex[4] = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_24MB; + ieee->current_network.rates_ex[5] = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_36MB; + ieee->current_network.rates_ex[6] = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_48MB; + ieee->current_network.rates_ex[7] = IEEE80211_BASIC_RATE_MASK | IEEE80211_OFDM_RATE_54MB; + + ieee->rate = 108; + }else{ + ieee->current_network.rates_ex_len = 0; + ieee->rate = 22; + } + + // By default, WMM function will be disabled in IBSS mode + ieee->current_network.QoS_Enable = 0; + ieee->SetWirelessMode(ieee->dev, IEEE_G); + ieee->current_network.atim_window = 0; + ieee->current_network.capability = WLAN_CAPABILITY_IBSS; + if(ieee->short_slot) + ieee->current_network.capability |= WLAN_CAPABILITY_SHORT_SLOT; + + } + + ieee->state = IEEE80211_LINKED; + + ieee->set_chan(ieee->dev, ieee->current_network.channel); + ieee->link_change(ieee->dev); + if(ieee->LedControlHandler != NULL) + ieee->LedControlHandler(ieee->dev,LED_CTL_LINK); + notify_wx_assoc_event(ieee); + + ieee80211_start_send_beacons(ieee); + + if (ieee->data_hard_resume) + ieee->data_hard_resume(ieee->dev); + netif_carrier_on(ieee->dev); + + up(&ieee->wx_sem); +} + +inline void ieee80211_start_ibss(struct ieee80211_device *ieee) +{ +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + queue_delayed_work(ieee->wq, &ieee->start_ibss_wq, 150); +#else + schedule_task(&ieee->start_ibss_wq); +#endif +} + +/* this is called only in user context, with wx_sem held */ +void ieee80211_start_bss(struct ieee80211_device *ieee) +{ + unsigned long flags; +#ifdef ENABLE_DOT11D + // + // Ref: 802.11d 11.1.3.3 + // STA shall not start a BSS unless properly formed Beacon frame including a Country IE. + // + if(IS_DOT11D_ENABLE(ieee) && !IS_COUNTRY_IE_VALID(ieee)) + { + if(! ieee->bGlobalDomain) + { + return; + } + } +#endif + /* check if we have already found the net we + * are interested in (if any). + * if not (we are disassociated and we are not + * in associating / authenticating phase) start the background scanning. + */ + ieee80211_softmac_check_all_nets(ieee); + + /* ensure no-one start an associating process (thus setting + * the ieee->state to ieee80211_ASSOCIATING) while we + * have just cheked it and we are going to enable scan. + * The ieee80211_new_net function is always called with + * lock held (from both ieee80211_softmac_check_all_nets and + * the rx path), so we cannot be in the middle of such function + */ + spin_lock_irqsave(&ieee->lock, flags); + + if (ieee->state == IEEE80211_NOLINK){ + ieee->actscanning = true; + ieee80211_start_scan(ieee); + } + spin_unlock_irqrestore(&ieee->lock, flags); +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) +void ieee80211_link_change_wq(struct work_struct *work) +{ + struct delayed_work *dwork = container_of(work, struct delayed_work, work); + struct ieee80211_device *ieee = container_of(dwork, struct ieee80211_device, link_change_wq); +#else +void ieee80211_link_change_wq(struct ieee80211_device *ieee) +{ +#endif + ieee->link_change(ieee->dev); +} +/* called only in userspace context */ +void ieee80211_disassociate(struct ieee80211_device *ieee) +{ + + + netif_carrier_off(ieee->dev); + if (ieee->softmac_features & IEEE_SOFTMAC_TX_QUEUE) + ieee80211_reset_queue(ieee); + + if (ieee->data_hard_stop) + ieee->data_hard_stop(ieee->dev); +#ifdef ENABLE_DOT11D + if(IS_DOT11D_ENABLE(ieee)) + Dot11d_Reset(ieee); +#endif + ieee->state = IEEE80211_NOLINK; + ieee->is_set_key = false; + + //LZM for usb dev crash. + //ieee->link_change(ieee->dev); +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + queue_delayed_work(ieee->wq, &ieee->link_change_wq, 0); +#else + schedule_task(&ieee->link_change_wq); +#endif + + //HTSetConnectBwMode(ieee, HT_CHANNEL_WIDTH_20, HT_EXTCHNL_OFFSET_NO_EXT); + notify_wx_assoc_event(ieee); + +} +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) +void ieee80211_associate_retry_wq(struct work_struct *work) +{ + struct delayed_work *dwork = container_of(work, struct delayed_work, work); + struct ieee80211_device *ieee = container_of(dwork, struct ieee80211_device, associate_retry_wq); +#else +void ieee80211_associate_retry_wq(struct ieee80211_device *ieee) +{ +#endif + unsigned long flags; + + down(&ieee->wx_sem); + if(!ieee->proto_started) + goto exit; + + if(ieee->state != IEEE80211_ASSOCIATING_RETRY) + goto exit; + + /* until we do not set the state to IEEE80211_NOLINK + * there are no possibility to have someone else trying + * to start an association procdure (we get here with + * ieee->state = IEEE80211_ASSOCIATING). + * When we set the state to IEEE80211_NOLINK it is possible + * that the RX path run an attempt to associate, but + * both ieee80211_softmac_check_all_nets and the + * RX path works with ieee->lock held so there are no + * problems. If we are still disassociated then start a scan. + * the lock here is necessary to ensure no one try to start + * an association procedure when we have just checked the + * state and we are going to start the scan. + */ + ieee->beinretry = true; + ieee->state = IEEE80211_NOLINK; + + ieee80211_softmac_check_all_nets(ieee); + + spin_lock_irqsave(&ieee->lock, flags); + + if(ieee->state == IEEE80211_NOLINK) + { + ieee->actscanning = true; + ieee80211_start_scan(ieee); + } + spin_unlock_irqrestore(&ieee->lock, flags); + + ieee->beinretry = false; +exit: + up(&ieee->wx_sem); +} + +struct sk_buff *ieee80211_get_beacon_(struct ieee80211_device *ieee) +{ + u8 broadcast_addr[] = {0xff,0xff,0xff,0xff,0xff,0xff}; + + struct sk_buff *skb; + struct ieee80211_probe_response *b; + + skb = ieee80211_probe_resp(ieee, broadcast_addr); + + if (!skb) + return NULL; + + b = (struct ieee80211_probe_response *) skb->data; + b->header.frame_ctl = cpu_to_le16(IEEE80211_STYPE_BEACON); + + return skb; + +} + +struct sk_buff *ieee80211_get_beacon(struct ieee80211_device *ieee) +{ + struct sk_buff *skb; + struct ieee80211_probe_response *b; + + skb = ieee80211_get_beacon_(ieee); + if(!skb) + return NULL; + + b = (struct ieee80211_probe_response *) skb->data; + b->header.seq_ctl = cpu_to_le16(ieee->seq_ctrl[0] << 4); + + if (ieee->seq_ctrl[0] == 0xFFF) + ieee->seq_ctrl[0] = 0; + else + ieee->seq_ctrl[0]++; + + return skb; +} + +void ieee80211_softmac_stop_protocol(struct ieee80211_device *ieee) +{ + ieee->sync_scan_hurryup = 1; + down(&ieee->wx_sem); + ieee80211_stop_protocol(ieee); + up(&ieee->wx_sem); +} + + +void ieee80211_stop_protocol(struct ieee80211_device *ieee) +{ + if (!ieee->proto_started) + return; + + ieee->proto_started = 0; + + ieee80211_stop_send_beacons(ieee); + del_timer_sync(&ieee->associate_timer); +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + cancel_delayed_work(&ieee->associate_retry_wq); + cancel_delayed_work(&ieee->start_ibss_wq); + cancel_delayed_work(&ieee->link_change_wq); +#endif + ieee80211_stop_scan(ieee); + + ieee80211_disassociate(ieee); + RemoveAllTS(ieee); //added as we disconnect from the previous BSS, Remove all TS +} + +void ieee80211_softmac_start_protocol(struct ieee80211_device *ieee) +{ + ieee->sync_scan_hurryup = 0; + down(&ieee->wx_sem); + ieee80211_start_protocol(ieee); + up(&ieee->wx_sem); +} + +void ieee80211_start_protocol(struct ieee80211_device *ieee) +{ + short ch = 0; + int i = 0; + if (ieee->proto_started) + return; + + ieee->proto_started = 1; + + if (ieee->current_network.channel == 0){ + do{ + ch++; + if (ch > MAX_CHANNEL_NUMBER) + return; /* no channel found */ +#ifdef ENABLE_DOT11D + }while(!GET_DOT11D_INFO(ieee)->channel_map[ch]); +#else + }while(!ieee->channel_map[ch]); +#endif + ieee->current_network.channel = ch; + } + + if (ieee->current_network.beacon_interval == 0) + ieee->current_network.beacon_interval = 100; +// printk("===>%s(), chan:%d\n", __FUNCTION__, ieee->current_network.channel); +// ieee->set_chan(ieee->dev,ieee->current_network.channel); + + for(i = 0; i < 17; i++) { + ieee->last_rxseq_num[i] = -1; + ieee->last_rxfrag_num[i] = -1; + ieee->last_packet_time[i] = 0; + } + + ieee->init_wmmparam_flag = 0;//reinitialize AC_xx_PARAM registers. + + + /* if the user set the MAC of the ad-hoc cell and then + * switch to managed mode, shall we make sure that association + * attempts does not fail just because the user provide the essid + * and the nic is still checking for the AP MAC ?? + */ + if (ieee->iw_mode == IW_MODE_INFRA) + ieee80211_start_bss(ieee); + + else if (ieee->iw_mode == IW_MODE_ADHOC) + ieee80211_start_ibss(ieee); + + else if (ieee->iw_mode == IW_MODE_MASTER) + ieee80211_start_master_bss(ieee); + + else if(ieee->iw_mode == IW_MODE_MONITOR) + ieee80211_start_monitor_mode(ieee); +} + + +#define DRV_NAME "Ieee80211" +void ieee80211_softmac_init(struct ieee80211_device *ieee) +{ + int i; + memset(&ieee->current_network, 0, sizeof(struct ieee80211_network)); + + ieee->state = IEEE80211_NOLINK; + ieee->sync_scan_hurryup = 0; + for(i = 0; i < 5; i++) { + ieee->seq_ctrl[i] = 0; + } +#ifdef ENABLE_DOT11D + ieee->pDot11dInfo = kmalloc(sizeof(RT_DOT11D_INFO), GFP_ATOMIC); + if (!ieee->pDot11dInfo) + IEEE80211_DEBUG(IEEE80211_DL_ERR, "can't alloc memory for DOT11D\n"); + memset(ieee->pDot11dInfo, 0, sizeof(RT_DOT11D_INFO)); +#endif + //added for AP roaming + ieee->LinkDetectInfo.SlotNum = 2; + ieee->LinkDetectInfo.NumRecvBcnInPeriod=0; + ieee->LinkDetectInfo.NumRecvDataInPeriod=0; + + ieee->assoc_id = 0; + ieee->queue_stop = 0; + ieee->scanning = 0; + ieee->softmac_features = 0; //so IEEE2100-like driver are happy + ieee->wap_set = 0; + ieee->ssid_set = 0; + ieee->proto_started = 0; + ieee->basic_rate = IEEE80211_DEFAULT_BASIC_RATE; + ieee->rate = 22; + ieee->ps = IEEE80211_PS_DISABLED; + ieee->sta_sleep = 0; + ieee->Regdot11HTOperationalRateSet[0]= 0xff;//support MCS 0~7 + ieee->Regdot11HTOperationalRateSet[1]= 0xff;//support MCS 8~15 + ieee->Regdot11HTOperationalRateSet[4]= 0x01; + //added by amy + ieee->actscanning = false; + ieee->beinretry = false; + ieee->is_set_key = false; + init_mgmt_queue(ieee); + + ieee->sta_edca_param[0] = 0x0000A403; + ieee->sta_edca_param[1] = 0x0000A427; + ieee->sta_edca_param[2] = 0x005E4342; + ieee->sta_edca_param[3] = 0x002F3262; + ieee->aggregation = true; + ieee->enable_rx_imm_BA = 1; +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) + init_timer(&ieee->scan_timer); + ieee->scan_timer.data = (unsigned long)ieee; + ieee->scan_timer.function = ieee80211_softmac_scan_cb; +#endif + ieee->tx_pending.txb = NULL; + + init_timer(&ieee->associate_timer); + ieee->associate_timer.data = (unsigned long)ieee; + ieee->associate_timer.function = ieee80211_associate_abort_cb; + + init_timer(&ieee->beacon_timer); + ieee->beacon_timer.data = (unsigned long) ieee; + ieee->beacon_timer.function = ieee80211_send_beacon_cb; + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) +#ifdef PF_SYNCTHREAD + ieee->wq = create_workqueue(DRV_NAME,0); +#else + ieee->wq = create_workqueue(DRV_NAME); +#endif +#endif + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + INIT_DELAYED_WORK(&ieee->link_change_wq,ieee80211_link_change_wq); + INIT_DELAYED_WORK(&ieee->start_ibss_wq,ieee80211_start_ibss_wq); + INIT_WORK(&ieee->associate_complete_wq, ieee80211_associate_complete_wq); + INIT_WORK(&ieee->associate_procedure_wq, ieee80211_associate_procedure_wq); + INIT_DELAYED_WORK(&ieee->softmac_scan_wq,ieee80211_softmac_scan_wq); + INIT_DELAYED_WORK(&ieee->associate_retry_wq, ieee80211_associate_retry_wq); + INIT_WORK(&ieee->wx_sync_scan_wq,ieee80211_wx_sync_scan_wq); + +#else + INIT_WORK(&ieee->link_change_wq,(void(*)(void*)) ieee80211_link_change_wq,ieee); + INIT_WORK(&ieee->start_ibss_wq,(void(*)(void*)) ieee80211_start_ibss_wq,ieee); + INIT_WORK(&ieee->associate_retry_wq,(void(*)(void*)) ieee80211_associate_retry_wq,ieee); + INIT_WORK(&ieee->associate_complete_wq,(void(*)(void*)) ieee80211_associate_complete_wq,ieee); + INIT_WORK(&ieee->associate_procedure_wq,(void(*)(void*)) ieee80211_associate_procedure_wq,ieee); + INIT_WORK(&ieee->softmac_scan_wq,(void(*)(void*)) ieee80211_softmac_scan_wq,ieee); + INIT_WORK(&ieee->wx_sync_scan_wq,(void(*)(void*)) ieee80211_wx_sync_scan_wq,ieee); +#endif + +#else + tq_init(&ieee->link_change_wq,(void(*)(void*)) ieee80211_link_change_wq,ieee); + tq_init(&ieee->start_ibss_wq,(void(*)(void*)) ieee80211_start_ibss_wq,ieee); + tq_init(&ieee->associate_retry_wq,(void(*)(void*)) ieee80211_associate_retry_wq,ieee); + tq_init(&ieee->associate_complete_wq,(void(*)(void*)) ieee80211_associate_complete_wq,ieee); + tq_init(&ieee->associate_procedure_wq,(void(*)(void*)) ieee80211_associate_procedure_wq,ieee); + tq_init(&ieee->softmac_scan_wq,(void(*)(void*)) ieee80211_softmac_scan_wq,ieee); + tq_init(&ieee->wx_sync_scan_wq,(void(*)(void*)) ieee80211_wx_sync_scan_wq,ieee); +#endif + sema_init(&ieee->wx_sem, 1); + sema_init(&ieee->scan_sem, 1); + + spin_lock_init(&ieee->mgmt_tx_lock); + spin_lock_init(&ieee->beacon_lock); + + tasklet_init(&ieee->ps_task, + (void(*)(unsigned long)) ieee80211_sta_ps, + (unsigned long)ieee); + +} + +void ieee80211_softmac_free(struct ieee80211_device *ieee) +{ + down(&ieee->wx_sem); +#ifdef ENABLE_DOT11D + if(NULL != ieee->pDot11dInfo) + { + kfree(ieee->pDot11dInfo); + ieee->pDot11dInfo = NULL; + } +#endif + del_timer_sync(&ieee->associate_timer); + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + cancel_delayed_work(&ieee->associate_retry_wq); + destroy_workqueue(ieee->wq); +#endif + + up(&ieee->wx_sem); +} + +/******************************************************** + * Start of WPA code. * + * this is stolen from the ipw2200 driver * + ********************************************************/ + + +static int ieee80211_wpa_enable(struct ieee80211_device *ieee, int value) +{ + /* This is called when wpa_supplicant loads and closes the driver + * interface. */ + printk("%s WPA\n",value ? "enabling" : "disabling"); + ieee->wpa_enabled = value; + memset(ieee->ap_mac_addr, 0, 6); //reset ap_mac_addr everytime it starts wpa. + return 0; +} + + +void ieee80211_wpa_assoc_frame(struct ieee80211_device *ieee, char *wpa_ie, int wpa_ie_len) +{ + /* make sure WPA is enabled */ + ieee80211_wpa_enable(ieee, 1); + + ieee80211_disassociate(ieee); +} + + +static int ieee80211_wpa_mlme(struct ieee80211_device *ieee, int command, int reason) +{ + + int ret = 0; + + switch (command) { + case IEEE_MLME_STA_DEAUTH: + // silently ignore + break; + + case IEEE_MLME_STA_DISASSOC: + ieee80211_disassociate(ieee); + break; + + default: + printk("Unknown MLME request: %d\n", command); + ret = -EOPNOTSUPP; + } + + return ret; +} + + +static int ieee80211_wpa_set_wpa_ie(struct ieee80211_device *ieee, + struct ieee_param *param, int plen) +{ + u8 *buf; + + if (param->u.wpa_ie.len > MAX_WPA_IE_LEN || + (param->u.wpa_ie.len && param->u.wpa_ie.data == NULL)) + return -EINVAL; + + if (param->u.wpa_ie.len) { + buf = kmalloc(param->u.wpa_ie.len, GFP_KERNEL); + if (buf == NULL) + return -ENOMEM; + + memcpy(buf, param->u.wpa_ie.data, param->u.wpa_ie.len); + kfree(ieee->wpa_ie); + ieee->wpa_ie = buf; + ieee->wpa_ie_len = param->u.wpa_ie.len; + } else { + kfree(ieee->wpa_ie); + ieee->wpa_ie = NULL; + ieee->wpa_ie_len = 0; + } + + ieee80211_wpa_assoc_frame(ieee, ieee->wpa_ie, ieee->wpa_ie_len); + return 0; +} + +#define AUTH_ALG_OPEN_SYSTEM 0x1 +#define AUTH_ALG_SHARED_KEY 0x2 +#define AUTH_ALG_LEAP 0x4 +static int ieee80211_wpa_set_auth_algs(struct ieee80211_device *ieee, int value) +{ + + struct ieee80211_security sec = { + .flags = SEC_AUTH_MODE, + }; + int ret = 0; + + if (value & AUTH_ALG_SHARED_KEY) { + sec.auth_mode = WLAN_AUTH_SHARED_KEY; + ieee->open_wep = 0; + ieee->auth_mode = 1; + } else if (value & AUTH_ALG_OPEN_SYSTEM){ + sec.auth_mode = WLAN_AUTH_OPEN; + ieee->open_wep = 1; + ieee->auth_mode = 0; + } + else if (value & AUTH_ALG_LEAP){ + sec.auth_mode = WLAN_AUTH_LEAP; + ieee->open_wep = 1; + ieee->auth_mode = 2; + } + + + if (ieee->set_security) + ieee->set_security(ieee->dev, &sec); + //else + // ret = -EOPNOTSUPP; + + return ret; +} + +static int ieee80211_wpa_set_param(struct ieee80211_device *ieee, u8 name, u32 value) +{ + int ret=0; + unsigned long flags; + + switch (name) { + case IEEE_PARAM_WPA_ENABLED: + ret = ieee80211_wpa_enable(ieee, value); + break; + + case IEEE_PARAM_TKIP_COUNTERMEASURES: + ieee->tkip_countermeasures=value; + break; + + case IEEE_PARAM_DROP_UNENCRYPTED: { + /* HACK: + * + * wpa_supplicant calls set_wpa_enabled when the driver + * is loaded and unloaded, regardless of if WPA is being + * used. No other calls are made which can be used to + * determine if encryption will be used or not prior to + * association being expected. If encryption is not being + * used, drop_unencrypted is set to false, else true -- we + * can use this to determine if the CAP_PRIVACY_ON bit should + * be set. + */ + struct ieee80211_security sec = { + .flags = SEC_ENABLED, + .enabled = value, + }; + ieee->drop_unencrypted = value; + /* We only change SEC_LEVEL for open mode. Others + * are set by ipw_wpa_set_encryption. + */ + if (!value) { + sec.flags |= SEC_LEVEL; + sec.level = SEC_LEVEL_0; + } + else { + sec.flags |= SEC_LEVEL; + sec.level = SEC_LEVEL_1; + } + if (ieee->set_security) + ieee->set_security(ieee->dev, &sec); + break; + } + + case IEEE_PARAM_PRIVACY_INVOKED: + ieee->privacy_invoked=value; + break; + + case IEEE_PARAM_AUTH_ALGS: + ret = ieee80211_wpa_set_auth_algs(ieee, value); + break; + + case IEEE_PARAM_IEEE_802_1X: + ieee->ieee802_1x=value; + break; + case IEEE_PARAM_WPAX_SELECT: + // added for WPA2 mixed mode + spin_lock_irqsave(&ieee->wpax_suitlist_lock,flags); + ieee->wpax_type_set = 1; + ieee->wpax_type_notify = value; + spin_unlock_irqrestore(&ieee->wpax_suitlist_lock,flags); + break; + + default: + printk("Unknown WPA param: %d\n",name); + ret = -EOPNOTSUPP; + } + + return ret; +} + +/* implementation borrowed from hostap driver */ + +static int ieee80211_wpa_set_encryption(struct ieee80211_device *ieee, + struct ieee_param *param, int param_len) +{ + int ret = 0; + + struct ieee80211_crypto_ops *ops; + struct ieee80211_crypt_data **crypt; + + struct ieee80211_security sec = { + .flags = 0, + }; + + param->u.crypt.err = 0; + param->u.crypt.alg[IEEE_CRYPT_ALG_NAME_LEN - 1] = '\0'; + + if (param_len != + (int) ((char *) param->u.crypt.key - (char *) param) + + param->u.crypt.key_len) { + printk("Len mismatch %d, %d\n", param_len, + param->u.crypt.key_len); + return -EINVAL; + } + if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && + param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && + param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) { + if (param->u.crypt.idx >= WEP_KEYS) + return -EINVAL; + crypt = &ieee->crypt[param->u.crypt.idx]; + } else { + return -EINVAL; + } + + if (strcmp(param->u.crypt.alg, "none") == 0) { + if (crypt) { + sec.enabled = 0; + // FIXME FIXME + //sec.encrypt = 0; + sec.level = SEC_LEVEL_0; + sec.flags |= SEC_ENABLED | SEC_LEVEL; + ieee80211_crypt_delayed_deinit(ieee, crypt); + } + goto done; + } + sec.enabled = 1; +// FIXME FIXME +// sec.encrypt = 1; + sec.flags |= SEC_ENABLED; + + /* IPW HW cannot build TKIP MIC, host decryption still needed. */ + if (!(ieee->host_encrypt || ieee->host_decrypt) && + strcmp(param->u.crypt.alg, "TKIP")) + goto skip_host_crypt; + + ops = ieee80211_get_crypto_ops(param->u.crypt.alg); + if (ops == NULL && strcmp(param->u.crypt.alg, "WEP") == 0) { + request_module("ieee80211_crypt_wep"); + ops = ieee80211_get_crypto_ops(param->u.crypt.alg); + //set WEP40 first, it will be modified according to WEP104 or WEP40 at other place + } else if (ops == NULL && strcmp(param->u.crypt.alg, "TKIP") == 0) { + request_module("ieee80211_crypt_tkip"); + ops = ieee80211_get_crypto_ops(param->u.crypt.alg); + } else if (ops == NULL && strcmp(param->u.crypt.alg, "CCMP") == 0) { + request_module("ieee80211_crypt_ccmp"); + ops = ieee80211_get_crypto_ops(param->u.crypt.alg); + } + if (ops == NULL) { + printk("unknown crypto alg '%s'\n", param->u.crypt.alg); + param->u.crypt.err = IEEE_CRYPT_ERR_UNKNOWN_ALG; + ret = -EINVAL; + goto done; + } + + if (*crypt == NULL || (*crypt)->ops != ops) { + struct ieee80211_crypt_data *new_crypt; + + ieee80211_crypt_delayed_deinit(ieee, crypt); + + new_crypt = (struct ieee80211_crypt_data *) + kmalloc(sizeof(*new_crypt), GFP_KERNEL); + if (new_crypt == NULL) { + ret = -ENOMEM; + goto done; + } + memset(new_crypt, 0, sizeof(struct ieee80211_crypt_data)); + new_crypt->ops = ops; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) + if (new_crypt->ops && try_module_get(new_crypt->ops->owner)) +#else + if (new_crypt->ops && try_inc_mod_count(new_crypt->ops->owner)) +#endif + new_crypt->priv = + new_crypt->ops->init(param->u.crypt.idx); + + if (new_crypt->priv == NULL) { + kfree(new_crypt); + param->u.crypt.err = IEEE_CRYPT_ERR_CRYPT_INIT_FAILED; + ret = -EINVAL; + goto done; + } + + *crypt = new_crypt; + } + + if (param->u.crypt.key_len > 0 && (*crypt)->ops->set_key && + (*crypt)->ops->set_key(param->u.crypt.key, + param->u.crypt.key_len, param->u.crypt.seq, + (*crypt)->priv) < 0) { + printk("key setting failed\n"); + param->u.crypt.err = IEEE_CRYPT_ERR_KEY_SET_FAILED; + ret = -EINVAL; + goto done; + } + + skip_host_crypt: + if (param->u.crypt.set_tx) { + ieee->tx_keyidx = param->u.crypt.idx; + sec.active_key = param->u.crypt.idx; + sec.flags |= SEC_ACTIVE_KEY; + } else + sec.flags &= ~SEC_ACTIVE_KEY; + + if (param->u.crypt.alg != NULL) { + memcpy(sec.keys[param->u.crypt.idx], + param->u.crypt.key, + param->u.crypt.key_len); + sec.key_sizes[param->u.crypt.idx] = param->u.crypt.key_len; + sec.flags |= (1 << param->u.crypt.idx); + + if (strcmp(param->u.crypt.alg, "WEP") == 0) { + sec.flags |= SEC_LEVEL; + sec.level = SEC_LEVEL_1; + } else if (strcmp(param->u.crypt.alg, "TKIP") == 0) { + sec.flags |= SEC_LEVEL; + sec.level = SEC_LEVEL_2; + } else if (strcmp(param->u.crypt.alg, "CCMP") == 0) { + sec.flags |= SEC_LEVEL; + sec.level = SEC_LEVEL_3; + } + } + done: + if (ieee->set_security) + ieee->set_security(ieee->dev, &sec); + + /* Do not reset port if card is in Managed mode since resetting will + * generate new IEEE 802.11 authentication which may end up in looping + * with IEEE 802.1X. If your hardware requires a reset after WEP + * configuration (for example... Prism2), implement the reset_port in + * the callbacks structures used to initialize the 802.11 stack. */ + if (ieee->reset_on_keychange && + ieee->iw_mode != IW_MODE_INFRA && + ieee->reset_port && + ieee->reset_port(ieee->dev)) { + printk("reset_port failed\n"); + param->u.crypt.err = IEEE_CRYPT_ERR_CARD_CONF_FAILED; + return -EINVAL; + } + + return ret; +} + +inline struct sk_buff *ieee80211_disassociate_skb( + struct ieee80211_network *beacon, + struct ieee80211_device *ieee, + u8 asRsn) +{ + struct sk_buff *skb; + struct ieee80211_disassoc *disass; + + skb = dev_alloc_skb(sizeof(struct ieee80211_disassoc)); + if (!skb) + return NULL; + + disass = (struct ieee80211_disassoc *) skb_put(skb,sizeof(struct ieee80211_disassoc)); + disass->header.frame_ctl = cpu_to_le16(IEEE80211_STYPE_DISASSOC); + disass->header.duration_id = 0; + + memcpy(disass->header.addr1, beacon->bssid, ETH_ALEN); + memcpy(disass->header.addr2, ieee->dev->dev_addr, ETH_ALEN); + memcpy(disass->header.addr3, beacon->bssid, ETH_ALEN); + + disass->reason = asRsn; + return skb; +} + + +void +SendDisassociation( + struct ieee80211_device *ieee, + u8* asSta, + u8 asRsn +) +{ + struct ieee80211_network *beacon = &ieee->current_network; + struct sk_buff *skb; + skb = ieee80211_disassociate_skb(beacon,ieee,asRsn); + if (skb){ + softmac_mgmt_xmit(skb, ieee); + //dev_kfree_skb_any(skb);//edit by thomas + } +} + +int ieee80211_wpa_supplicant_ioctl(struct ieee80211_device *ieee, struct iw_point *p) +{ + struct ieee_param *param; + int ret=0; + + down(&ieee->wx_sem); + //IEEE_DEBUG_INFO("wpa_supplicant: len=%d\n", p->length); + + if (p->length < sizeof(struct ieee_param) || !p->pointer){ + ret = -EINVAL; + goto out; + } + + param = (struct ieee_param *)kmalloc(p->length, GFP_KERNEL); + if (param == NULL){ + ret = -ENOMEM; + goto out; + } + if (copy_from_user(param, p->pointer, p->length)) { + kfree(param); + ret = -EFAULT; + goto out; + } + + switch (param->cmd) { + + case IEEE_CMD_SET_WPA_PARAM: + ret = ieee80211_wpa_set_param(ieee, param->u.wpa_param.name, + param->u.wpa_param.value); + break; + + case IEEE_CMD_SET_WPA_IE: + ret = ieee80211_wpa_set_wpa_ie(ieee, param, p->length); + break; + + case IEEE_CMD_SET_ENCRYPTION: + ret = ieee80211_wpa_set_encryption(ieee, param, p->length); + break; + + case IEEE_CMD_MLME: + ret = ieee80211_wpa_mlme(ieee, param->u.mlme.command, + param->u.mlme.reason_code); + break; + + default: + printk("Unknown WPA supplicant request: %d\n",param->cmd); + ret = -EOPNOTSUPP; + break; + } + + if (ret == 0 && copy_to_user(p->pointer, param, p->length)) + ret = -EFAULT; + + kfree(param); +out: + up(&ieee->wx_sem); + + return ret; +} + +void notify_wx_assoc_event(struct ieee80211_device *ieee) +{ + union iwreq_data wrqu; + wrqu.ap_addr.sa_family = ARPHRD_ETHER; + if (ieee->state == IEEE80211_LINKED) + memcpy(wrqu.ap_addr.sa_data, ieee->current_network.bssid, ETH_ALEN); + else + memset(wrqu.ap_addr.sa_data, 0, ETH_ALEN); + wireless_send_event(ieee->dev, SIOCGIWAP, &wrqu, NULL); +} + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) +EXPORT_SYMBOL(ieee80211_get_beacon); +EXPORT_SYMBOL(ieee80211_wake_queue); +EXPORT_SYMBOL(ieee80211_stop_queue); +EXPORT_SYMBOL(ieee80211_reset_queue); +EXPORT_SYMBOL(ieee80211_softmac_stop_protocol); +EXPORT_SYMBOL(ieee80211_softmac_start_protocol); +EXPORT_SYMBOL(ieee80211_is_shortslot); +EXPORT_SYMBOL(ieee80211_is_54g); +EXPORT_SYMBOL(ieee80211_wpa_supplicant_ioctl); +EXPORT_SYMBOL(ieee80211_ps_tx_ack); +EXPORT_SYMBOL(ieee80211_softmac_xmit); +EXPORT_SYMBOL(ieee80211_stop_send_beacons); +EXPORT_SYMBOL(notify_wx_assoc_event); +EXPORT_SYMBOL(SendDisassociation); +EXPORT_SYMBOL(ieee80211_disassociate); +EXPORT_SYMBOL(ieee80211_start_send_beacons); +EXPORT_SYMBOL(ieee80211_stop_scan); +EXPORT_SYMBOL(ieee80211_send_probe_requests); +EXPORT_SYMBOL(ieee80211_softmac_scan_syncro); +EXPORT_SYMBOL(ieee80211_start_scan_syncro); +#else +EXPORT_SYMBOL_NOVERS(ieee80211_get_beacon); +EXPORT_SYMBOL_NOVERS(ieee80211_wake_queue); +EXPORT_SYMBOL_NOVERS(ieee80211_stop_queue); +EXPORT_SYMBOL_NOVERS(ieee80211_reset_queue); +EXPORT_SYMBOL_NOVERS(ieee80211_softmac_stop_protocol); +EXPORT_SYMBOL_NOVERS(ieee80211_softmac_start_protocol); +EXPORT_SYMBOL_NOVERS(ieee80211_is_shortslot); +EXPORT_SYMBOL_NOVERS(ieee80211_is_54g); +EXPORT_SYMBOL_NOVERS(ieee80211_wpa_supplicant_ioctl); +EXPORT_SYMBOL_NOVERS(ieee80211_ps_tx_ack); +EXPORT_SYMBOL_NOVERS(ieee80211_softmac_xmit); +EXPORT_SYMBOL_NOVERS(ieee80211_stop_send_beacons); +EXPORT_SYMBOL_NOVERS(notify_wx_assoc_event); +EXPORT_SYMBOL_NOVERS(SendDisassociation); +EXPORT_SYMBOL_NOVERS(ieee80211_disassociate); +EXPORT_SYMBOL_NOVERS(ieee80211_start_send_beacons); +EXPORT_SYMBOL_NOVERS(ieee80211_stop_scan); +EXPORT_SYMBOL_NOVERS(ieee80211_send_probe_requests); +EXPORT_SYMBOL_NOVERS(ieee80211_softmac_scan_syncro); +EXPORT_SYMBOL_NOVERS(ieee80211_start_scan_syncro); +#endif +//EXPORT_SYMBOL(ieee80211_sta_ps_send_null_frame); diff --git a/drivers/staging/rtl8192su/ieee80211/ieee80211_softmac_wx.c b/drivers/staging/rtl8192su/ieee80211/ieee80211_softmac_wx.c new file mode 100644 index 000000000000..1f50c46dcb90 --- /dev/null +++ b/drivers/staging/rtl8192su/ieee80211/ieee80211_softmac_wx.c @@ -0,0 +1,711 @@ +/* IEEE 802.11 SoftMAC layer + * Copyright (c) 2005 Andrea Merello <andreamrl@tiscali.it> + * + * Mostly extracted from the rtl8180-sa2400 driver for the + * in-kernel generic ieee802.11 stack. + * + * Some pieces of code might be stolen from ipw2100 driver + * copyright of who own it's copyright ;-) + * + * PS wx handler mostly stolen from hostap, copyright who + * own it's copyright ;-) + * + * released under the GPL + */ + + +#include "ieee80211.h" +#ifdef ENABLE_DOT11D +#include "dot11d.h" +#endif +/* FIXME: add A freqs */ + +const long ieee80211_wlan_frequencies[] = { + 2412, 2417, 2422, 2427, + 2432, 2437, 2442, 2447, + 2452, 2457, 2462, 2467, + 2472, 2484 +}; + + +int ieee80211_wx_set_freq(struct ieee80211_device *ieee, struct iw_request_info *a, + union iwreq_data *wrqu, char *b) +{ + int ret; + struct iw_freq *fwrq = & wrqu->freq; + + down(&ieee->wx_sem); + + if(ieee->iw_mode == IW_MODE_INFRA){ + ret = -EOPNOTSUPP; + goto out; + } + + /* if setting by freq convert to channel */ + if (fwrq->e == 1) { + if ((fwrq->m >= (int) 2.412e8 && + fwrq->m <= (int) 2.487e8)) { + int f = fwrq->m / 100000; + int c = 0; + + while ((c < 14) && (f != ieee80211_wlan_frequencies[c])) + c++; + + /* hack to fall through */ + fwrq->e = 0; + fwrq->m = c + 1; + } + } + + if (fwrq->e > 0 || fwrq->m > 14 || fwrq->m < 1 ){ + ret = -EOPNOTSUPP; + goto out; + + }else { /* Set the channel */ + +#ifdef ENABLE_DOT11D + if (!(GET_DOT11D_INFO(ieee)->channel_map)[fwrq->m]) { + ret = -EINVAL; + goto out; + } +#endif + ieee->current_network.channel = fwrq->m; + ieee->set_chan(ieee->dev, ieee->current_network.channel); + + if(ieee->iw_mode == IW_MODE_ADHOC || ieee->iw_mode == IW_MODE_MASTER) + if(ieee->state == IEEE80211_LINKED){ + + ieee80211_stop_send_beacons(ieee); + ieee80211_start_send_beacons(ieee); + } + } + + ret = 0; +out: + up(&ieee->wx_sem); + return ret; +} + + +int ieee80211_wx_get_freq(struct ieee80211_device *ieee, + struct iw_request_info *a, + union iwreq_data *wrqu, char *b) +{ + struct iw_freq *fwrq = & wrqu->freq; + + if (ieee->current_network.channel == 0) + return -1; + //NM 0.7.0 will not accept channel any more. + fwrq->m = ieee80211_wlan_frequencies[ieee->current_network.channel-1] * 100000; + fwrq->e = 1; +// fwrq->m = ieee->current_network.channel; +// fwrq->e = 0; + + return 0; +} + +int ieee80211_wx_get_wap(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + unsigned long flags; + + wrqu->ap_addr.sa_family = ARPHRD_ETHER; + + if (ieee->iw_mode == IW_MODE_MONITOR) + return -1; + + /* We want avoid to give to the user inconsistent infos*/ + spin_lock_irqsave(&ieee->lock, flags); + + if (ieee->state != IEEE80211_LINKED && + ieee->state != IEEE80211_LINKED_SCANNING && + ieee->wap_set == 0) + + memset(wrqu->ap_addr.sa_data, 0, ETH_ALEN); + else + memcpy(wrqu->ap_addr.sa_data, + ieee->current_network.bssid, ETH_ALEN); + + spin_unlock_irqrestore(&ieee->lock, flags); + + return 0; +} + + +int ieee80211_wx_set_wap(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data *awrq, + char *extra) +{ + + int ret = 0; + u8 zero[] = {0,0,0,0,0,0}; + unsigned long flags; + + short ifup = ieee->proto_started;//dev->flags & IFF_UP; + struct sockaddr *temp = (struct sockaddr *)awrq; + + ieee->sync_scan_hurryup = 1; + + down(&ieee->wx_sem); + /* use ifconfig hw ether */ + if (ieee->iw_mode == IW_MODE_MASTER){ + ret = -1; + goto out; + } + + if (temp->sa_family != ARPHRD_ETHER){ + ret = -EINVAL; + goto out; + } + + if (ifup) + ieee80211_stop_protocol(ieee); + + /* just to avoid to give inconsistent infos in the + * get wx method. not really needed otherwise + */ + spin_lock_irqsave(&ieee->lock, flags); + + memcpy(ieee->current_network.bssid, temp->sa_data, ETH_ALEN); + ieee->wap_set = memcmp(temp->sa_data, zero,ETH_ALEN)!=0; + + spin_unlock_irqrestore(&ieee->lock, flags); + + if (ifup) + ieee80211_start_protocol(ieee); +out: + up(&ieee->wx_sem); + return ret; +} + + int ieee80211_wx_get_essid(struct ieee80211_device *ieee, struct iw_request_info *a,union iwreq_data *wrqu,char *b) +{ + int len,ret = 0; + unsigned long flags; + + if (ieee->iw_mode == IW_MODE_MONITOR) + return -1; + + /* We want avoid to give to the user inconsistent infos*/ + spin_lock_irqsave(&ieee->lock, flags); + + if (ieee->current_network.ssid[0] == '\0' || + ieee->current_network.ssid_len == 0){ + ret = -1; + goto out; + } + + if (ieee->state != IEEE80211_LINKED && + ieee->state != IEEE80211_LINKED_SCANNING && + ieee->ssid_set == 0){ + ret = -1; + goto out; + } + len = ieee->current_network.ssid_len; + wrqu->essid.length = len; + strncpy(b,ieee->current_network.ssid,len); + wrqu->essid.flags = 1; + +out: + spin_unlock_irqrestore(&ieee->lock, flags); + + return ret; + +} + +int ieee80211_wx_set_rate(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + u32 target_rate = wrqu->bitrate.value; + + ieee->rate = target_rate/100000; + //FIXME: we might want to limit rate also in management protocols. + return 0; +} + + + +int ieee80211_wx_get_rate(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + u32 tmp_rate = 0; +#ifdef RTL8192SU + //printk("===>mode:%d, halfNmode:%d\n", ieee->mode, ieee->bHalfWirelessN24GMode); + if (ieee->mode & (IEEE_A | IEEE_B | IEEE_G)) + tmp_rate = ieee->rate; + else if (ieee->mode & IEEE_N_5G) + tmp_rate = 580; + else if (ieee->mode & IEEE_N_24G) + { + if (ieee->GetHalfNmodeSupportByAPsHandler(ieee->dev)) + tmp_rate = HTHalfMcsToDataRate(ieee, 15); + else + tmp_rate = HTMcsToDataRate(ieee, 15); + } +#else + tmp_rate = TxCountToDataRate(ieee, ieee->softmac_stats.CurrentShowTxate); + +#endif + wrqu->bitrate.value = tmp_rate * 500000; + + return 0; +} + + +int ieee80211_wx_set_rts(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + if (wrqu->rts.disabled || !wrqu->rts.fixed) + ieee->rts = DEFAULT_RTS_THRESHOLD; + else + { + if (wrqu->rts.value < MIN_RTS_THRESHOLD || + wrqu->rts.value > MAX_RTS_THRESHOLD) + return -EINVAL; + ieee->rts = wrqu->rts.value; + } + return 0; +} + +int ieee80211_wx_get_rts(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + wrqu->rts.value = ieee->rts; + wrqu->rts.fixed = 0; /* no auto select */ + wrqu->rts.disabled = (wrqu->rts.value == DEFAULT_RTS_THRESHOLD); + return 0; +} +int ieee80211_wx_set_mode(struct ieee80211_device *ieee, struct iw_request_info *a, + union iwreq_data *wrqu, char *b) +{ + + ieee->sync_scan_hurryup = 1; + + down(&ieee->wx_sem); + + if (wrqu->mode == ieee->iw_mode) + goto out; + + if (wrqu->mode == IW_MODE_MONITOR){ + + ieee->dev->type = ARPHRD_IEEE80211; + }else{ + ieee->dev->type = ARPHRD_ETHER; + } + + if (!ieee->proto_started){ + ieee->iw_mode = wrqu->mode; + }else{ + ieee80211_stop_protocol(ieee); + ieee->iw_mode = wrqu->mode; + ieee80211_start_protocol(ieee); + } + +out: + up(&ieee->wx_sem); + return 0; +} + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) +void ieee80211_wx_sync_scan_wq(struct work_struct *work) +{ + struct ieee80211_device *ieee = container_of(work, struct ieee80211_device, wx_sync_scan_wq); +#else +void ieee80211_wx_sync_scan_wq(struct ieee80211_device *ieee) +{ +#endif + short chan; + HT_EXTCHNL_OFFSET chan_offset=0; + HT_CHANNEL_WIDTH bandwidth=0; + int b40M = 0; + static int count = 0; + chan = ieee->current_network.channel; + netif_carrier_off(ieee->dev); + + if (ieee->data_hard_stop) + ieee->data_hard_stop(ieee->dev); + + ieee80211_stop_send_beacons(ieee); + + ieee->state = IEEE80211_LINKED_SCANNING; + ieee->link_change(ieee->dev); +#ifndef RTL8192SE + ieee->InitialGainHandler(ieee->dev,IG_Backup); +#endif +#if(RTL8192S_DISABLE_FW_DM == 0) + if (ieee->SetFwCmdHandler) + { + ieee->SetFwCmdHandler(ieee->dev, FW_CMD_DIG_HALT); + ieee->SetFwCmdHandler(ieee->dev, FW_CMD_HIGH_PWR_DISABLE); + } +#endif + if (ieee->pHTInfo->bCurrentHTSupport && ieee->pHTInfo->bEnableHT && ieee->pHTInfo->bCurBW40MHz) { + b40M = 1; + chan_offset = ieee->pHTInfo->CurSTAExtChnlOffset; + bandwidth = (HT_CHANNEL_WIDTH)ieee->pHTInfo->bCurBW40MHz; + printk("Scan in 40M, force to 20M first:%d, %d\n", chan_offset, bandwidth); + ieee->SetBWModeHandler(ieee->dev, HT_CHANNEL_WIDTH_20, HT_EXTCHNL_OFFSET_NO_EXT); + } + ieee80211_start_scan_syncro(ieee); + if (b40M) { + printk("Scan in 20M, back to 40M\n"); + if (chan_offset == HT_EXTCHNL_OFFSET_UPPER) + ieee->set_chan(ieee->dev, chan + 2); + else if (chan_offset == HT_EXTCHNL_OFFSET_LOWER) + ieee->set_chan(ieee->dev, chan - 2); + else + ieee->set_chan(ieee->dev, chan); + ieee->SetBWModeHandler(ieee->dev, bandwidth, chan_offset); + } else { + ieee->set_chan(ieee->dev, chan); + } + +#ifndef RTL8192SE + ieee->InitialGainHandler(ieee->dev,IG_Restore); +#endif +#if(RTL8192S_DISABLE_FW_DM == 0) + if (ieee->SetFwCmdHandler) + { + ieee->SetFwCmdHandler(ieee->dev, FW_CMD_DIG_RESUME); + ieee->SetFwCmdHandler(ieee->dev, FW_CMD_HIGH_PWR_ENABLE); + } +#endif + ieee->state = IEEE80211_LINKED; + ieee->link_change(ieee->dev); + // To prevent the immediately calling watch_dog after scan. + if(ieee->LinkDetectInfo.NumRecvBcnInPeriod==0||ieee->LinkDetectInfo.NumRecvDataInPeriod==0 ) + { + ieee->LinkDetectInfo.NumRecvBcnInPeriod = 1; + ieee->LinkDetectInfo.NumRecvDataInPeriod= 1; + } + if (ieee->data_hard_resume) + ieee->data_hard_resume(ieee->dev); + + if(ieee->iw_mode == IW_MODE_ADHOC || ieee->iw_mode == IW_MODE_MASTER) + ieee80211_start_send_beacons(ieee); + + netif_carrier_on(ieee->dev); + count = 0; + up(&ieee->wx_sem); + +} + +int ieee80211_wx_set_scan(struct ieee80211_device *ieee, struct iw_request_info *a, + union iwreq_data *wrqu, char *b) +{ + int ret = 0; + + down(&ieee->wx_sem); + + if (ieee->iw_mode == IW_MODE_MONITOR || !(ieee->proto_started)){ + ret = -1; + goto out; + } + + if ( ieee->state == IEEE80211_LINKED){ +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + queue_work(ieee->wq, &ieee->wx_sync_scan_wq); +#else + schedule_task(&ieee->wx_sync_scan_wq); +#endif + /* intentionally forget to up sem */ + return 0; + } + +out: + up(&ieee->wx_sem); + return ret; +} + +int ieee80211_wx_set_essid(struct ieee80211_device *ieee, + struct iw_request_info *a, + union iwreq_data *wrqu, char *extra) +{ + + int ret=0,len; + short proto_started; + unsigned long flags; + + ieee->sync_scan_hurryup = 1; + down(&ieee->wx_sem); + + proto_started = ieee->proto_started; + + if (wrqu->essid.length > IW_ESSID_MAX_SIZE){ + ret= -E2BIG; + goto out; + } + + if (ieee->iw_mode == IW_MODE_MONITOR){ + ret= -1; + goto out; + } + + if(proto_started) + ieee80211_stop_protocol(ieee); + + + /* this is just to be sure that the GET wx callback + * has consisten infos. not needed otherwise + */ + spin_lock_irqsave(&ieee->lock, flags); + + if (wrqu->essid.flags && wrqu->essid.length) { + //first flush current network.ssid + len = ((wrqu->essid.length-1) < IW_ESSID_MAX_SIZE) ? (wrqu->essid.length-1) : IW_ESSID_MAX_SIZE; +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) + strncpy(ieee->current_network.ssid, extra, len); + ieee->current_network.ssid_len = len; +#if 0 + { + int i; + for (i=0; i<len; i++) + printk("%c ", extra[i]); + printk("\n"); + } +#endif +#else + strncpy(ieee->current_network.ssid, extra, len+1); + ieee->current_network.ssid_len = len+1; +#if 0 + { + int i; + for (i=0; i<len + 1; i++) + printk("%c ", extra[i]); + printk("\n"); + } +#endif +#endif + ieee->ssid_set = 1; + } + else{ + ieee->ssid_set = 0; + ieee->current_network.ssid[0] = '\0'; + ieee->current_network.ssid_len = 0; + } + spin_unlock_irqrestore(&ieee->lock, flags); + + if (proto_started) + ieee80211_start_protocol(ieee); +out: + up(&ieee->wx_sem); + return ret; +} + + int ieee80211_wx_get_mode(struct ieee80211_device *ieee, struct iw_request_info *a, + union iwreq_data *wrqu, char *b) +{ + + wrqu->mode = ieee->iw_mode; + return 0; +} + + int ieee80211_wx_set_rawtx(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int *parms = (int *)extra; + int enable = (parms[0] > 0); + short prev = ieee->raw_tx; + + down(&ieee->wx_sem); + + if(enable) + ieee->raw_tx = 1; + else + ieee->raw_tx = 0; + + printk(KERN_INFO"raw TX is %s\n", + ieee->raw_tx ? "enabled" : "disabled"); + + if(ieee->iw_mode == IW_MODE_MONITOR) + { + if(prev == 0 && ieee->raw_tx){ + if (ieee->data_hard_resume) + ieee->data_hard_resume(ieee->dev); + + netif_carrier_on(ieee->dev); + } + + if(prev && ieee->raw_tx == 1) + netif_carrier_off(ieee->dev); + } + + up(&ieee->wx_sem); + + return 0; +} + +int ieee80211_wx_get_name(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + strcpy(wrqu->name, "802.11"); + if(ieee->modulation & IEEE80211_CCK_MODULATION){ + strcat(wrqu->name, "b"); + if(ieee->modulation & IEEE80211_OFDM_MODULATION) + strcat(wrqu->name, "/g"); + }else if(ieee->modulation & IEEE80211_OFDM_MODULATION) + strcat(wrqu->name, "g"); + if (ieee->mode & (IEEE_N_24G | IEEE_N_5G)) + strcat(wrqu->name, "/n"); + + if((ieee->state == IEEE80211_LINKED) || + (ieee->state == IEEE80211_LINKED_SCANNING)) + strcat(wrqu->name," linked"); + else if(ieee->state != IEEE80211_NOLINK) + strcat(wrqu->name," link.."); + + + return 0; +} + + +/* this is mostly stolen from hostap */ +int ieee80211_wx_set_power(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret = 0; +#if 1 + if( + (!ieee->sta_wake_up) || + // (!ieee->ps_request_tx_ack) || + (!ieee->enter_sleep_state) || + (!ieee->ps_is_queue_empty)){ + + // printk("ERROR. PS mode is tryied to be use but driver missed a callback\n\n"); + + return -1; + } +#endif + down(&ieee->wx_sem); + + if (wrqu->power.disabled){ + ieee->ps = IEEE80211_PS_DISABLED; + goto exit; + } + if (wrqu->power.flags & IW_POWER_TIMEOUT) { + //ieee->ps_period = wrqu->power.value / 1000; + ieee->ps_timeout = wrqu->power.value / 1000; + } + + if (wrqu->power.flags & IW_POWER_PERIOD) { + + //ieee->ps_timeout = wrqu->power.value / 1000; + ieee->ps_period = wrqu->power.value / 1000; + //wrq->value / 1024; + + } + switch (wrqu->power.flags & IW_POWER_MODE) { + case IW_POWER_UNICAST_R: + ieee->ps = IEEE80211_PS_UNICAST; + break; + case IW_POWER_MULTICAST_R: + ieee->ps = IEEE80211_PS_MBCAST; + break; + case IW_POWER_ALL_R: + ieee->ps = IEEE80211_PS_UNICAST | IEEE80211_PS_MBCAST; + break; + + case IW_POWER_ON: + // ieee->ps = IEEE80211_PS_DISABLED; + break; + + default: + ret = -EINVAL; + goto exit; + + } +exit: + up(&ieee->wx_sem); + return ret; + +} + +/* this is stolen from hostap */ +int ieee80211_wx_get_power(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret =0; + + down(&ieee->wx_sem); + + if(ieee->ps == IEEE80211_PS_DISABLED){ + wrqu->power.disabled = 1; + goto exit; + } + + wrqu->power.disabled = 0; + + if ((wrqu->power.flags & IW_POWER_TYPE) == IW_POWER_TIMEOUT) { + wrqu->power.flags = IW_POWER_TIMEOUT; + wrqu->power.value = ieee->ps_timeout * 1000; + } else { +// ret = -EOPNOTSUPP; +// goto exit; + wrqu->power.flags = IW_POWER_PERIOD; + wrqu->power.value = ieee->ps_period * 1000; +//ieee->current_network.dtim_period * ieee->current_network.beacon_interval * 1024; + } + + if ((ieee->ps & (IEEE80211_PS_MBCAST | IEEE80211_PS_UNICAST)) == (IEEE80211_PS_MBCAST | IEEE80211_PS_UNICAST)) + wrqu->power.flags |= IW_POWER_ALL_R; + else if (ieee->ps & IEEE80211_PS_MBCAST) + wrqu->power.flags |= IW_POWER_MULTICAST_R; + else + wrqu->power.flags |= IW_POWER_UNICAST_R; + +exit: + up(&ieee->wx_sem); + return ret; + +} +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) +EXPORT_SYMBOL(ieee80211_wx_get_essid); +EXPORT_SYMBOL(ieee80211_wx_set_essid); +EXPORT_SYMBOL(ieee80211_wx_set_rate); +EXPORT_SYMBOL(ieee80211_wx_get_rate); +EXPORT_SYMBOL(ieee80211_wx_set_wap); +EXPORT_SYMBOL(ieee80211_wx_get_wap); +EXPORT_SYMBOL(ieee80211_wx_set_mode); +EXPORT_SYMBOL(ieee80211_wx_get_mode); +EXPORT_SYMBOL(ieee80211_wx_set_scan); +EXPORT_SYMBOL(ieee80211_wx_get_freq); +EXPORT_SYMBOL(ieee80211_wx_set_freq); +EXPORT_SYMBOL(ieee80211_wx_set_rawtx); +EXPORT_SYMBOL(ieee80211_wx_get_name); +EXPORT_SYMBOL(ieee80211_wx_set_power); +EXPORT_SYMBOL(ieee80211_wx_get_power); +EXPORT_SYMBOL(ieee80211_wlan_frequencies); +EXPORT_SYMBOL(ieee80211_wx_set_rts); +EXPORT_SYMBOL(ieee80211_wx_get_rts); +#else +EXPORT_SYMBOL_NOVERS(ieee80211_wx_get_essid); +EXPORT_SYMBOL_NOVERS(ieee80211_wx_set_essid); +EXPORT_SYMBOL_NOVERS(ieee80211_wx_set_rate); +EXPORT_SYMBOL_NOVERS(ieee80211_wx_get_rate); +EXPORT_SYMBOL_NOVERS(ieee80211_wx_set_wap); +EXPORT_SYMBOL_NOVERS(ieee80211_wx_get_wap); +EXPORT_SYMBOL_NOVERS(ieee80211_wx_set_mode); +EXPORT_SYMBOL_NOVERS(ieee80211_wx_get_mode); +EXPORT_SYMBOL_NOVERS(ieee80211_wx_set_scan); +EXPORT_SYMBOL_NOVERS(ieee80211_wx_get_freq); +EXPORT_SYMBOL_NOVERS(ieee80211_wx_set_freq); +EXPORT_SYMBOL_NOVERS(ieee80211_wx_set_rawtx); +EXPORT_SYMBOL_NOVERS(ieee80211_wx_get_name); +EXPORT_SYMBOL_NOVERS(ieee80211_wx_set_power); +EXPORT_SYMBOL_NOVERS(ieee80211_wx_get_power); +EXPORT_SYMBOL_NOVERS(ieee80211_wlan_frequencies); +EXPORT_SYMBOL_NOVERS(ieee80211_wx_set_rts); +EXPORT_SYMBOL_NOVERS(ieee80211_wx_get_rts); +#endif diff --git a/drivers/staging/rtl8192su/ieee80211/ieee80211_tx.c b/drivers/staging/rtl8192su/ieee80211/ieee80211_tx.c new file mode 100644 index 000000000000..7294572b990f --- /dev/null +++ b/drivers/staging/rtl8192su/ieee80211/ieee80211_tx.c @@ -0,0 +1,947 @@ +/****************************************************************************** + + Copyright(c) 2003 - 2004 Intel Corporation. All rights reserved. + + This program is free software; you can redistribute it and/or modify it + under the terms of version 2 of the GNU General Public License as + published by the Free Software Foundation. + + This program is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + You should have received a copy of the GNU General Public License along with + this program; if not, write to the Free Software Foundation, Inc., 59 + Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + The full GNU General Public License is included in this distribution in the + file called LICENSE. + + Contact Information: + James P. Ketrenos <ipw2100-admin@linux.intel.com> + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 + +****************************************************************************** + + Few modifications for Realtek's Wi-Fi drivers by + Andrea Merello <andreamrl@tiscali.it> + + A special thanks goes to Realtek for their support ! + +******************************************************************************/ + +#include <linux/compiler.h> +//#include <linux/config.h> +#include <linux/errno.h> +#include <linux/if_arp.h> +#include <linux/in6.h> +#include <linux/in.h> +#include <linux/ip.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/netdevice.h> +#include <linux/pci.h> +#include <linux/proc_fs.h> +#include <linux/skbuff.h> +#include <linux/slab.h> +#include <linux/tcp.h> +#include <linux/types.h> +#include <linux/version.h> +#include <linux/wireless.h> +#include <linux/etherdevice.h> +#include <asm/uaccess.h> +#include <linux/if_vlan.h> + +#include "ieee80211.h" + + +/* + + +802.11 Data Frame + + +802.11 frame_contorl for data frames - 2 bytes + ,-----------------------------------------------------------------------------------------. +bits | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | a | b | c | d | e | + |----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|------| +val | 0 | 0 | 0 | 1 | x | 0 | 0 | 0 | 1 | 0 | x | x | x | x | x | + |----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|------| +desc | ^-ver-^ | ^type-^ | ^-----subtype-----^ | to |from |more |retry| pwr |more |wep | + | | | x=0 data,x=1 data+ack | DS | DS |frag | | mgm |data | | + '-----------------------------------------------------------------------------------------' + /\ + | +802.11 Data Frame | + ,--------- 'ctrl' expands to >-----------' + | + ,--'---,-------------------------------------------------------------. +Bytes | 2 | 2 | 6 | 6 | 6 | 2 | 0..2312 | 4 | + |------|------|---------|---------|---------|------|---------|------| +Desc. | ctrl | dura | DA/RA | TA | SA | Sequ | Frame | fcs | + | | tion | (BSSID) | | | ence | data | | + `--------------------------------------------------| |------' +Total: 28 non-data bytes `----.----' + | + .- 'Frame data' expands to <---------------------------' + | + V + ,---------------------------------------------------. +Bytes | 1 | 1 | 1 | 3 | 2 | 0-2304 | + |------|------|---------|----------|------|---------| +Desc. | SNAP | SNAP | Control |Eth Tunnel| Type | IP | + | DSAP | SSAP | | | | Packet | + | 0xAA | 0xAA |0x03 (UI)|0x00-00-F8| | | + `-----------------------------------------| | +Total: 8 non-data bytes `----.----' + | + .- 'IP Packet' expands, if WEP enabled, to <--' + | + V + ,-----------------------. +Bytes | 4 | 0-2296 | 4 | + |-----|-----------|-----| +Desc. | IV | Encrypted | ICV | + | | IP Packet | | + `-----------------------' +Total: 8 non-data bytes + + +802.3 Ethernet Data Frame + + ,-----------------------------------------. +Bytes | 6 | 6 | 2 | Variable | 4 | + |-------|-------|------|-----------|------| +Desc. | Dest. | Source| Type | IP Packet | fcs | + | MAC | MAC | | | | + `-----------------------------------------' +Total: 18 non-data bytes + +In the event that fragmentation is required, the incoming payload is split into +N parts of size ieee->fts. The first fragment contains the SNAP header and the +remaining packets are just data. + +If encryption is enabled, each fragment payload size is reduced by enough space +to add the prefix and postfix (IV and ICV totalling 8 bytes in the case of WEP) +So if you have 1500 bytes of payload with ieee->fts set to 500 without +encryption it will take 3 frames. With WEP it will take 4 frames as the +payload of each frame is reduced to 492 bytes. + +* SKB visualization +* +* ,- skb->data +* | +* | ETHERNET HEADER ,-<-- PAYLOAD +* | | 14 bytes from skb->data +* | 2 bytes for Type --> ,T. | (sizeof ethhdr) +* | | | | +* |,-Dest.--. ,--Src.---. | | | +* | 6 bytes| | 6 bytes | | | | +* v | | | | | | +* 0 | v 1 | v | v 2 +* 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 +* ^ | ^ | ^ | +* | | | | | | +* | | | | `T' <---- 2 bytes for Type +* | | | | +* | | '---SNAP--' <-------- 6 bytes for SNAP +* | | +* `-IV--' <-------------------- 4 bytes for IV (WEP) +* +* SNAP HEADER +* +*/ + +static u8 P802_1H_OUI[P80211_OUI_LEN] = { 0x00, 0x00, 0xf8 }; +static u8 RFC1042_OUI[P80211_OUI_LEN] = { 0x00, 0x00, 0x00 }; + +static inline int ieee80211_put_snap(u8 *data, u16 h_proto) +{ + struct ieee80211_snap_hdr *snap; + u8 *oui; + + snap = (struct ieee80211_snap_hdr *)data; + snap->dsap = 0xaa; + snap->ssap = 0xaa; + snap->ctrl = 0x03; + + if (h_proto == 0x8137 || h_proto == 0x80f3) + oui = P802_1H_OUI; + else + oui = RFC1042_OUI; + snap->oui[0] = oui[0]; + snap->oui[1] = oui[1]; + snap->oui[2] = oui[2]; + + *(u16 *)(data + SNAP_SIZE) = htons(h_proto); + + return SNAP_SIZE + sizeof(u16); +} + +int ieee80211_encrypt_fragment( + struct ieee80211_device *ieee, + struct sk_buff *frag, + int hdr_len) +{ + struct ieee80211_crypt_data* crypt = ieee->crypt[ieee->tx_keyidx]; + int res; + + if (!(crypt && crypt->ops)) + { + printk("=========>%s(), crypt is null\n", __FUNCTION__); + return -1; + } +#ifdef CONFIG_IEEE80211_CRYPT_TKIP + struct ieee80211_hdr *header; + + if (ieee->tkip_countermeasures && + crypt && crypt->ops && strcmp(crypt->ops->name, "TKIP") == 0) { + header = (struct ieee80211_hdr *) frag->data; + if (net_ratelimit()) { + printk(KERN_DEBUG "%s: TKIP countermeasures: dropped " + "TX packet to " MAC_FMT "\n", + ieee->dev->name, MAC_ARG(header->addr1)); + } + return -1; + } +#endif + /* To encrypt, frame format is: + * IV (4 bytes), clear payload (including SNAP), ICV (4 bytes) */ + + // PR: FIXME: Copied from hostap. Check fragmentation/MSDU/MPDU encryption. + /* Host-based IEEE 802.11 fragmentation for TX is not yet supported, so + * call both MSDU and MPDU encryption functions from here. */ + atomic_inc(&crypt->refcnt); + res = 0; + if (crypt->ops->encrypt_msdu) + res = crypt->ops->encrypt_msdu(frag, hdr_len, crypt->priv); + if (res == 0 && crypt->ops->encrypt_mpdu) + res = crypt->ops->encrypt_mpdu(frag, hdr_len, crypt->priv); + + atomic_dec(&crypt->refcnt); + if (res < 0) { + printk(KERN_INFO "%s: Encryption failed: len=%d.\n", + ieee->dev->name, frag->len); + ieee->ieee_stats.tx_discards++; + return -1; + } + + return 0; +} + + +void ieee80211_txb_free(struct ieee80211_txb *txb) { + //int i; + if (unlikely(!txb)) + return; +#if 0 + for (i = 0; i < txb->nr_frags; i++) + if (txb->fragments[i]) + dev_kfree_skb_any(txb->fragments[i]); +#endif + kfree(txb); +} + +struct ieee80211_txb *ieee80211_alloc_txb(int nr_frags, int txb_size, + int gfp_mask) +{ + struct ieee80211_txb *txb; + int i; + txb = kmalloc( + sizeof(struct ieee80211_txb) + (sizeof(u8*) * nr_frags), + gfp_mask); + if (!txb) + return NULL; + + memset(txb, 0, sizeof(struct ieee80211_txb)); + txb->nr_frags = nr_frags; + txb->frag_size = txb_size; + + for (i = 0; i < nr_frags; i++) { + txb->fragments[i] = dev_alloc_skb(txb_size); + if (unlikely(!txb->fragments[i])) { + i--; + break; + } + memset(txb->fragments[i]->cb, 0, sizeof(txb->fragments[i]->cb)); + } + if (unlikely(i != nr_frags)) { + while (i >= 0) + dev_kfree_skb_any(txb->fragments[i--]); + kfree(txb); + return NULL; + } + return txb; +} + +// Classify the to-be send data packet +// Need to acquire the sent queue index. +static int +ieee80211_classify(struct sk_buff *skb, struct ieee80211_network *network) +{ + struct ethhdr *eth; + struct iphdr *ip; + eth = (struct ethhdr *)skb->data; + if (eth->h_proto != htons(ETH_P_IP)) + return 0; + +// IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA, skb->data, skb->len); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22)) + ip = ip_hdr(skb); +#else + ip = (struct iphdr*)(skb->data + sizeof(struct ether_header)); +#endif + switch (ip->tos & 0xfc) { + case 0x20: + return 2; + case 0x40: + return 1; + case 0x60: + return 3; + case 0x80: + return 4; + case 0xa0: + return 5; + case 0xc0: + return 6; + case 0xe0: + return 7; + default: + return 0; + } +} + +#define SN_LESS(a, b) (((a-b)&0x800)!=0) +void ieee80211_tx_query_agg_cap(struct ieee80211_device* ieee, struct sk_buff* skb, cb_desc* tcb_desc) +{ + PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; + PTX_TS_RECORD pTxTs = NULL; + struct ieee80211_hdr_1addr* hdr = (struct ieee80211_hdr_1addr*)skb->data; + + if (!pHTInfo->bCurrentHTSupport||!pHTInfo->bEnableHT) + return; + if (!IsQoSDataFrame(skb->data)) + return; + + if (is_multicast_ether_addr(hdr->addr1) || is_broadcast_ether_addr(hdr->addr1)) + return; + //check packet and mode later +#ifdef TO_DO_LIST + if(pTcb->PacketLength >= 4096) + return; + // For RTL819X, if pairwisekey = wep/tkip, we don't aggrregation. + if(!Adapter->HalFunc.GetNmodeSupportBySecCfgHandler(Adapter)) + return; +#endif + + if(pHTInfo->IOTAction & HT_IOT_ACT_TX_NO_AGGREGATION) + return; + +#if 1 + if(!ieee->GetNmodeSupportBySecCfg(ieee->dev)) + { + return; + } +#endif + if(pHTInfo->bCurrentAMPDUEnable) + { + if (!GetTs(ieee, (PTS_COMMON_INFO*)(&pTxTs), hdr->addr1, skb->priority, TX_DIR, true)) + { + printk("===>can't get TS\n"); + return; + } + if (pTxTs->TxAdmittedBARecord.bValid == false) + { + //as some AP will refuse our action frame until key handshake has been finished. WB + if (ieee->wpa_ie_len && (ieee->pairwise_key_type == KEY_TYPE_NA)) + ; + else + TsStartAddBaProcess(ieee, pTxTs); + goto FORCED_AGG_SETTING; + } + else if (pTxTs->bUsingBa == false) + { + if (SN_LESS(pTxTs->TxAdmittedBARecord.BaStartSeqCtrl.field.SeqNum, (pTxTs->TxCurSeq+1)%4096)) + pTxTs->bUsingBa = true; + else + goto FORCED_AGG_SETTING; + } + + if (ieee->iw_mode == IW_MODE_INFRA) + { + tcb_desc->bAMPDUEnable = true; + tcb_desc->ampdu_factor = pHTInfo->CurrentAMPDUFactor; + tcb_desc->ampdu_density = pHTInfo->CurrentMPDUDensity; + } + } +FORCED_AGG_SETTING: + switch(pHTInfo->ForcedAMPDUMode ) + { + case HT_AGG_AUTO: + break; + + case HT_AGG_FORCE_ENABLE: + tcb_desc->bAMPDUEnable = true; + tcb_desc->ampdu_density = pHTInfo->ForcedMPDUDensity; + tcb_desc->ampdu_factor = pHTInfo->ForcedAMPDUFactor; + break; + + case HT_AGG_FORCE_DISABLE: + tcb_desc->bAMPDUEnable = false; + tcb_desc->ampdu_density = 0; + tcb_desc->ampdu_factor = 0; + break; + + } + return; +} + +extern void ieee80211_qurey_ShortPreambleMode(struct ieee80211_device* ieee, cb_desc* tcb_desc) +{ + tcb_desc->bUseShortPreamble = false; + if (tcb_desc->data_rate == 2) + {//// 1M can only use Long Preamble. 11B spec + return; + } + else if (ieee->current_network.capability & WLAN_CAPABILITY_SHORT_PREAMBLE) + { + tcb_desc->bUseShortPreamble = true; + } + return; +} +extern void +ieee80211_query_HTCapShortGI(struct ieee80211_device *ieee, cb_desc *tcb_desc) +{ + PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; + + tcb_desc->bUseShortGI = false; + + if(!pHTInfo->bCurrentHTSupport||!pHTInfo->bEnableHT) + return; + + if(pHTInfo->bForcedShortGI) + { + tcb_desc->bUseShortGI = true; + return; + } + + if((pHTInfo->bCurBW40MHz==true) && pHTInfo->bCurShortGI40MHz) + tcb_desc->bUseShortGI = true; + else if((pHTInfo->bCurBW40MHz==false) && pHTInfo->bCurShortGI20MHz) + tcb_desc->bUseShortGI = true; +} + +void ieee80211_query_BandwidthMode(struct ieee80211_device* ieee, cb_desc *tcb_desc) +{ + PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; + + tcb_desc->bPacketBW = false; + + if(!pHTInfo->bCurrentHTSupport||!pHTInfo->bEnableHT) + return; + + if(tcb_desc->bMulticast || tcb_desc->bBroadcast) + return; + + if((tcb_desc->data_rate & 0x80)==0) // If using legacy rate, it shall use 20MHz channel. + return; + //BandWidthAutoSwitch is for auto switch to 20 or 40 in long distance + if(pHTInfo->bCurBW40MHz && pHTInfo->bCurTxBW40MHz && !ieee->bandwidth_auto_switch.bforced_tx20Mhz) + tcb_desc->bPacketBW = true; + return; +} + +void ieee80211_query_protectionmode(struct ieee80211_device* ieee, cb_desc* tcb_desc, struct sk_buff* skb) +{ + // Common Settings + tcb_desc->bRTSSTBC = false; + tcb_desc->bRTSUseShortGI = false; // Since protection frames are always sent by legacy rate, ShortGI will never be used. + tcb_desc->bCTSEnable = false; // Most of protection using RTS/CTS + tcb_desc->RTSSC = 0; // 20MHz: Don't care; 40MHz: Duplicate. + tcb_desc->bRTSBW = false; // RTS frame bandwidth is always 20MHz + + if(tcb_desc->bBroadcast || tcb_desc->bMulticast)//only unicast frame will use rts/cts + return; + + if (is_broadcast_ether_addr(skb->data+16)) //check addr3 as infrastructure add3 is DA. + return; + + if (ieee->mode < IEEE_N_24G) //b, g mode + { + // (1) RTS_Threshold is compared to the MPDU, not MSDU. + // (2) If there are more than one frag in this MSDU, only the first frag uses protection frame. + // Other fragments are protected by previous fragment. + // So we only need to check the length of first fragment. + if (skb->len > ieee->rts) + { + tcb_desc->bRTSEnable = true; + tcb_desc->rts_rate = MGN_24M; + } + else if (ieee->current_network.buseprotection) + { + // Use CTS-to-SELF in protection mode. + tcb_desc->bRTSEnable = true; + tcb_desc->bCTSEnable = true; + tcb_desc->rts_rate = MGN_24M; + } + //otherwise return; + return; + } + else + {// 11n High throughput case. + PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; + while (true) + { + //check IOT action + if(pHTInfo->IOTAction & HT_IOT_ACT_FORCED_CTS2SELF) + { + tcb_desc->bCTSEnable = true; + tcb_desc->rts_rate = MGN_24M; +#if defined(RTL8192SE) || defined(RTL8192SU) + tcb_desc->bRTSEnable = false; +#else + tcb_desc->bRTSEnable = true; +#endif + break; + } + else if(pHTInfo->IOTAction & (HT_IOT_ACT_FORCED_RTS|HT_IOT_ACT_PURE_N_MODE)) + { + tcb_desc->bRTSEnable = true; + tcb_desc->rts_rate = MGN_24M; + break; + } + //check ERP protection + if (ieee->current_network.buseprotection) + {// CTS-to-SELF + tcb_desc->bRTSEnable = true; + tcb_desc->bCTSEnable = true; + tcb_desc->rts_rate = MGN_24M; + break; + } + //check HT op mode + if(pHTInfo->bCurrentHTSupport && pHTInfo->bEnableHT) + { + u8 HTOpMode = pHTInfo->CurrentOpMode; + if((pHTInfo->bCurBW40MHz && (HTOpMode == 2 || HTOpMode == 3)) || + (!pHTInfo->bCurBW40MHz && HTOpMode == 3) ) + { + tcb_desc->rts_rate = MGN_24M; // Rate is 24Mbps. + tcb_desc->bRTSEnable = true; + break; + } + } + //check rts + if (skb->len > ieee->rts) + { + tcb_desc->rts_rate = MGN_24M; // Rate is 24Mbps. + tcb_desc->bRTSEnable = true; + break; + } + //to do list: check MIMO power save condition. + //check AMPDU aggregation for TXOP + if(tcb_desc->bAMPDUEnable) + { + tcb_desc->rts_rate = MGN_24M; // Rate is 24Mbps. + // According to 8190 design, firmware sends CF-End only if RTS/CTS is enabled. However, it degrads + // throughput around 10M, so we disable of this mechanism. 2007.08.03 by Emily + tcb_desc->bRTSEnable = false; + break; + } + // Totally no protection case!! + goto NO_PROTECTION; + } + } + // For test , CTS replace with RTS + if( 0 ) + { + tcb_desc->bCTSEnable = true; + tcb_desc->rts_rate = MGN_24M; + tcb_desc->bRTSEnable = true; + } + if (ieee->current_network.capability & WLAN_CAPABILITY_SHORT_PREAMBLE) + tcb_desc->bUseShortPreamble = true; + if (ieee->mode == IW_MODE_MASTER) + goto NO_PROTECTION; + return; +NO_PROTECTION: + tcb_desc->bRTSEnable = false; + tcb_desc->bCTSEnable = false; + tcb_desc->rts_rate = 0; + tcb_desc->RTSSC = 0; + tcb_desc->bRTSBW = false; +} + + +void ieee80211_txrate_selectmode(struct ieee80211_device* ieee, cb_desc* tcb_desc) +{ +#ifdef TO_DO_LIST + if(!IsDataFrame(pFrame)) + { + pTcb->bTxDisableRateFallBack = TRUE; + pTcb->bTxUseDriverAssingedRate = TRUE; + pTcb->RATRIndex = 7; + return; + } + + if(pMgntInfo->ForcedDataRate!= 0) + { + pTcb->bTxDisableRateFallBack = TRUE; + pTcb->bTxUseDriverAssingedRate = TRUE; + return; + } +#endif + if(ieee->bTxDisableRateFallBack) + tcb_desc->bTxDisableRateFallBack = true; + + if(ieee->bTxUseDriverAssingedRate) + tcb_desc->bTxUseDriverAssingedRate = true; + if(!tcb_desc->bTxDisableRateFallBack || !tcb_desc->bTxUseDriverAssingedRate) + { + if (ieee->iw_mode == IW_MODE_INFRA || ieee->iw_mode == IW_MODE_ADHOC) + tcb_desc->RATRIndex = 0; + } +} + +void ieee80211_query_seqnum(struct ieee80211_device*ieee, struct sk_buff* skb, u8* dst) +{ + if (is_multicast_ether_addr(dst) || is_broadcast_ether_addr(dst)) + return; + if (IsQoSDataFrame(skb->data)) //we deal qos data only + { + PTX_TS_RECORD pTS = NULL; + if (!GetTs(ieee, (PTS_COMMON_INFO*)(&pTS), dst, skb->priority, TX_DIR, true)) + { + return; + } + pTS->TxCurSeq = (pTS->TxCurSeq+1)%4096; + } +} + +int ieee80211_xmit(struct sk_buff *skb, struct net_device *dev) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)) + struct ieee80211_device *ieee = netdev_priv(dev); +#else + struct ieee80211_device *ieee = (struct ieee80211_device *)dev->priv; +#endif + struct ieee80211_txb *txb = NULL; + struct ieee80211_hdr_3addrqos *frag_hdr; + int i, bytes_per_frag, nr_frags, bytes_last_frag, frag_size; + unsigned long flags; + struct net_device_stats *stats = &ieee->stats; + int ether_type = 0, encrypt; + int bytes, fc, qos_ctl = 0, hdr_len; + struct sk_buff *skb_frag; + struct ieee80211_hdr_3addrqos header = { /* Ensure zero initialized */ + .duration_id = 0, + .seq_ctl = 0, + .qos_ctl = 0 + }; + u8 dest[ETH_ALEN], src[ETH_ALEN]; + int qos_actived = ieee->current_network.qos_data.active; + + struct ieee80211_crypt_data* crypt; + + cb_desc *tcb_desc; + + spin_lock_irqsave(&ieee->lock, flags); + + /* If there is no driver handler to take the TXB, dont' bother + * creating it... */ + if ((!ieee->hard_start_xmit && !(ieee->softmac_features & IEEE_SOFTMAC_TX_QUEUE))|| + ((!ieee->softmac_data_hard_start_xmit && (ieee->softmac_features & IEEE_SOFTMAC_TX_QUEUE)))) { + printk(KERN_WARNING "%s: No xmit handler.\n", + ieee->dev->name); + goto success; + } + + + if(likely(ieee->raw_tx == 0)){ + if (unlikely(skb->len < SNAP_SIZE + sizeof(u16))) { + printk(KERN_WARNING "%s: skb too small (%d).\n", + ieee->dev->name, skb->len); + goto success; + } + + memset(skb->cb, 0, sizeof(skb->cb)); + ether_type = ntohs(((struct ethhdr *)skb->data)->h_proto); + + crypt = ieee->crypt[ieee->tx_keyidx]; + + encrypt = !(ether_type == ETH_P_PAE && ieee->ieee802_1x) && + ieee->host_encrypt && crypt && crypt->ops; + + if (!encrypt && ieee->ieee802_1x && + ieee->drop_unencrypted && ether_type != ETH_P_PAE) { + stats->tx_dropped++; + goto success; + } + #ifdef CONFIG_IEEE80211_DEBUG + if (crypt && !encrypt && ether_type == ETH_P_PAE) { + struct eapol *eap = (struct eapol *)(skb->data + + sizeof(struct ethhdr) - SNAP_SIZE - sizeof(u16)); + IEEE80211_DEBUG_EAP("TX: IEEE 802.11 EAPOL frame: %s\n", + eap_get_type(eap->type)); + } + #endif + + /* Save source and destination addresses */ + memcpy(&dest, skb->data, ETH_ALEN); + memcpy(&src, skb->data+ETH_ALEN, ETH_ALEN); + + /* Advance the SKB to the start of the payload */ + skb_pull(skb, sizeof(struct ethhdr)); + + /* Determine total amount of storage required for TXB packets */ + bytes = skb->len + SNAP_SIZE + sizeof(u16); + + if (encrypt) + fc = IEEE80211_FTYPE_DATA | IEEE80211_FCTL_WEP; + else + + fc = IEEE80211_FTYPE_DATA; + + //if(ieee->current_network.QoS_Enable) + if(qos_actived) + fc |= IEEE80211_STYPE_QOS_DATA; + else + fc |= IEEE80211_STYPE_DATA; + + if (ieee->iw_mode == IW_MODE_INFRA) { + fc |= IEEE80211_FCTL_TODS; + /* To DS: Addr1 = BSSID, Addr2 = SA, + Addr3 = DA */ + memcpy(&header.addr1, ieee->current_network.bssid, ETH_ALEN); + memcpy(&header.addr2, &src, ETH_ALEN); + memcpy(&header.addr3, &dest, ETH_ALEN); + } else if (ieee->iw_mode == IW_MODE_ADHOC) { + /* not From/To DS: Addr1 = DA, Addr2 = SA, + Addr3 = BSSID */ + memcpy(&header.addr1, dest, ETH_ALEN); + memcpy(&header.addr2, src, ETH_ALEN); + memcpy(&header.addr3, ieee->current_network.bssid, ETH_ALEN); + } + + header.frame_ctl = cpu_to_le16(fc); + + /* Determine fragmentation size based on destination (multicast + * and broadcast are not fragmented) */ + if (is_multicast_ether_addr(header.addr1) || + is_broadcast_ether_addr(header.addr1)) { + frag_size = MAX_FRAG_THRESHOLD; + qos_ctl |= QOS_CTL_NOTCONTAIN_ACK; + } + else { + frag_size = ieee->fts;//default:392 + qos_ctl = 0; + } + + //if (ieee->current_network.QoS_Enable) + if(qos_actived) + { + hdr_len = IEEE80211_3ADDR_LEN + 2; + + skb->priority = ieee80211_classify(skb, &ieee->current_network); + qos_ctl |= skb->priority; //set in the ieee80211_classify + header.qos_ctl = cpu_to_le16(qos_ctl & IEEE80211_QOS_TID); + } else { + hdr_len = IEEE80211_3ADDR_LEN; + } + /* Determine amount of payload per fragment. Regardless of if + * this stack is providing the full 802.11 header, one will + * eventually be affixed to this fragment -- so we must account for + * it when determining the amount of payload space. */ + bytes_per_frag = frag_size - hdr_len; + if (ieee->config & + (CFG_IEEE80211_COMPUTE_FCS | CFG_IEEE80211_RESERVE_FCS)) + bytes_per_frag -= IEEE80211_FCS_LEN; + + /* Each fragment may need to have room for encryptiong pre/postfix */ + if (encrypt) + bytes_per_frag -= crypt->ops->extra_prefix_len + + crypt->ops->extra_postfix_len; + + /* Number of fragments is the total bytes_per_frag / + * payload_per_fragment */ + nr_frags = bytes / bytes_per_frag; + bytes_last_frag = bytes % bytes_per_frag; + if (bytes_last_frag) + nr_frags++; + else + bytes_last_frag = bytes_per_frag; + + /* When we allocate the TXB we allocate enough space for the reserve + * and full fragment bytes (bytes_per_frag doesn't include prefix, + * postfix, header, FCS, etc.) */ + txb = ieee80211_alloc_txb(nr_frags, frag_size + ieee->tx_headroom, GFP_ATOMIC); + if (unlikely(!txb)) { + printk(KERN_WARNING "%s: Could not allocate TXB\n", + ieee->dev->name); + goto failed; + } + txb->encrypted = encrypt; + txb->payload_size = bytes; + + //if (ieee->current_network.QoS_Enable) + if(qos_actived) + { + txb->queue_index = UP2AC(skb->priority); + } else { + txb->queue_index = WME_AC_BK;; + } + + + + for (i = 0; i < nr_frags; i++) { + skb_frag = txb->fragments[i]; + tcb_desc = (cb_desc *)(skb_frag->cb + MAX_DEV_ADDR_SIZE); + if(qos_actived){ + skb_frag->priority = skb->priority;//UP2AC(skb->priority); + tcb_desc->queue_index = UP2AC(skb->priority); + } else { + skb_frag->priority = WME_AC_BK; + tcb_desc->queue_index = WME_AC_BK; + } + skb_reserve(skb_frag, ieee->tx_headroom); + + if (encrypt){ + if (ieee->hwsec_active) + tcb_desc->bHwSec = 1; + else + tcb_desc->bHwSec = 0; + skb_reserve(skb_frag, crypt->ops->extra_prefix_len); + } + else + { + tcb_desc->bHwSec = 0; + } + frag_hdr = (struct ieee80211_hdr_3addrqos *)skb_put(skb_frag, hdr_len); + memcpy(frag_hdr, &header, hdr_len); + + /* If this is not the last fragment, then add the MOREFRAGS + * bit to the frame control */ + if (i != nr_frags - 1) { + frag_hdr->frame_ctl = cpu_to_le16( + fc | IEEE80211_FCTL_MOREFRAGS); + bytes = bytes_per_frag; + + } else { + /* The last fragment takes the remaining length */ + bytes = bytes_last_frag; + } + //if(ieee->current_network.QoS_Enable) + if(qos_actived) + { + // add 1 only indicate to corresponding seq number control 2006/7/12 + frag_hdr->seq_ctl = cpu_to_le16(ieee->seq_ctrl[UP2AC(skb->priority)+1]<<4 | i); + } else { + frag_hdr->seq_ctl = cpu_to_le16(ieee->seq_ctrl[0]<<4 | i); + } + + /* Put a SNAP header on the first fragment */ + if (i == 0) { + ieee80211_put_snap( + skb_put(skb_frag, SNAP_SIZE + sizeof(u16)), + ether_type); + bytes -= SNAP_SIZE + sizeof(u16); + } + + memcpy(skb_put(skb_frag, bytes), skb->data, bytes); + + /* Advance the SKB... */ + skb_pull(skb, bytes); + + /* Encryption routine will move the header forward in order + * to insert the IV between the header and the payload */ + if (encrypt) + ieee80211_encrypt_fragment(ieee, skb_frag, hdr_len); + if (ieee->config & + (CFG_IEEE80211_COMPUTE_FCS | CFG_IEEE80211_RESERVE_FCS)) + skb_put(skb_frag, 4); + } + + if(qos_actived) + { + if (ieee->seq_ctrl[UP2AC(skb->priority) + 1] == 0xFFF) + ieee->seq_ctrl[UP2AC(skb->priority) + 1] = 0; + else + ieee->seq_ctrl[UP2AC(skb->priority) + 1]++; + } else { + if (ieee->seq_ctrl[0] == 0xFFF) + ieee->seq_ctrl[0] = 0; + else + ieee->seq_ctrl[0]++; + } + }else{ + if (unlikely(skb->len < sizeof(struct ieee80211_hdr_3addr))) { + printk(KERN_WARNING "%s: skb too small (%d).\n", + ieee->dev->name, skb->len); + goto success; + } + + txb = ieee80211_alloc_txb(1, skb->len, GFP_ATOMIC); + if(!txb){ + printk(KERN_WARNING "%s: Could not allocate TXB\n", + ieee->dev->name); + goto failed; + } + + txb->encrypted = 0; + txb->payload_size = skb->len; + memcpy(skb_put(txb->fragments[0],skb->len), skb->data, skb->len); + } + + success: +//WB add to fill data tcb_desc here. only first fragment is considered, need to change, and you may remove to other place. + if (txb) + { +#if 1 + cb_desc *tcb_desc = (cb_desc *)(txb->fragments[0]->cb + MAX_DEV_ADDR_SIZE); + tcb_desc->bTxEnableFwCalcDur = 1; + if (is_multicast_ether_addr(header.addr1)) + tcb_desc->bMulticast = 1; + if (is_broadcast_ether_addr(header.addr1)) + tcb_desc->bBroadcast = 1; + ieee80211_txrate_selectmode(ieee, tcb_desc); + if ( tcb_desc->bMulticast || tcb_desc->bBroadcast) + tcb_desc->data_rate = ieee->basic_rate; + else + //tcb_desc->data_rate = CURRENT_RATE(ieee->current_network.mode, ieee->rate, ieee->HTCurrentOperaRate); + tcb_desc->data_rate = CURRENT_RATE(ieee->mode, ieee->rate, ieee->HTCurrentOperaRate); + ieee80211_qurey_ShortPreambleMode(ieee, tcb_desc); + ieee80211_tx_query_agg_cap(ieee, txb->fragments[0], tcb_desc); + ieee80211_query_HTCapShortGI(ieee, tcb_desc); + ieee80211_query_BandwidthMode(ieee, tcb_desc); + ieee80211_query_protectionmode(ieee, tcb_desc, txb->fragments[0]); + ieee80211_query_seqnum(ieee, txb->fragments[0], header.addr1); +// IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA, txb->fragments[0]->data, txb->fragments[0]->len); + //IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA, tcb_desc, sizeof(cb_desc)); +#endif + } + spin_unlock_irqrestore(&ieee->lock, flags); + dev_kfree_skb_any(skb); + if (txb) { + if (ieee->softmac_features & IEEE_SOFTMAC_TX_QUEUE){ + ieee80211_softmac_xmit(txb, ieee); + }else{ + if ((*ieee->hard_start_xmit)(txb, dev) == 0) { + stats->tx_packets++; + stats->tx_bytes += txb->payload_size; + return 0; + } + ieee80211_txb_free(txb); + } + } + + return 0; + + failed: + spin_unlock_irqrestore(&ieee->lock, flags); + netif_stop_queue(dev); + stats->tx_errors++; + return 1; + +} + +EXPORT_SYMBOL(ieee80211_txb_free); diff --git a/drivers/staging/rtl8192su/ieee80211/ieee80211_wx.c b/drivers/staging/rtl8192su/ieee80211/ieee80211_wx.c new file mode 100644 index 000000000000..118dfe1c977f --- /dev/null +++ b/drivers/staging/rtl8192su/ieee80211/ieee80211_wx.c @@ -0,0 +1,1032 @@ +/****************************************************************************** + + Copyright(c) 2004 Intel Corporation. All rights reserved. + + Portions of this file are based on the WEP enablement code provided by the + Host AP project hostap-drivers v0.1.3 + Copyright (c) 2001-2002, SSH Communications Security Corp and Jouni Malinen + <jkmaline@cc.hut.fi> + Copyright (c) 2002-2003, Jouni Malinen <jkmaline@cc.hut.fi> + + This program is free software; you can redistribute it and/or modify it + under the terms of version 2 of the GNU General Public License as + published by the Free Software Foundation. + + This program is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + You should have received a copy of the GNU General Public License along with + this program; if not, write to the Free Software Foundation, Inc., 59 + Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + The full GNU General Public License is included in this distribution in the + file called LICENSE. + + Contact Information: + James P. Ketrenos <ipw2100-admin@linux.intel.com> + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 + +******************************************************************************/ +#include <linux/wireless.h> +#include <linux/version.h> +#include <linux/kmod.h> +#include <linux/module.h> + +#include "ieee80211.h" +#if 0 +static const char *ieee80211_modes[] = { + "?", "a", "b", "ab", "g", "ag", "bg", "abg" +}; +#endif +struct modes_unit { + char *mode_string; + int mode_size; +}; +struct modes_unit ieee80211_modes[] = { + {"a",1}, + {"b",1}, + {"g",1}, + {"?",1}, + {"N-24G",5}, + {"N-5G",4}, +}; + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,4,20)) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)) +static inline char * +iwe_stream_add_event_rsl(char * stream, /* Stream of events */ + char * ends, /* End of stream */ + struct iw_event *iwe, /* Payload */ + int event_len) /* Real size of payload */ +{ + /* Check if it's possible */ + if((stream + event_len) < ends) { + iwe->len = event_len; + ndelay(1); //new + memcpy(stream, (char *) iwe, event_len); + stream += event_len; + } + return stream; +} +#else +#define iwe_stream_add_event_rsl iwe_stream_add_event +#endif + +#define MAX_CUSTOM_LEN 64 +static inline char *rtl819x_translate_scan(struct ieee80211_device *ieee, + char *start, char *stop, + struct ieee80211_network *network, + struct iw_request_info *info) +{ + char custom[MAX_CUSTOM_LEN]; + char proto_name[IFNAMSIZ]; + char *pname = proto_name; + char *p; + struct iw_event iwe; + int i, j; + u16 max_rate, rate; + static u8 EWC11NHTCap[] = {0x00, 0x90, 0x4c, 0x33}; + + /* First entry *MUST* be the AP MAC address */ + iwe.cmd = SIOCGIWAP; + iwe.u.ap_addr.sa_family = ARPHRD_ETHER; + memcpy(iwe.u.ap_addr.sa_data, network->bssid, ETH_ALEN); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + start = iwe_stream_add_event_rsl(info, start, stop, &iwe, IW_EV_ADDR_LEN); +#else + start = iwe_stream_add_event_rsl(start, stop, &iwe, IW_EV_ADDR_LEN); +#endif + /* Remaining entries will be displayed in the order we provide them */ + + /* Add the ESSID */ + iwe.cmd = SIOCGIWESSID; + iwe.u.data.flags = 1; +// if (network->flags & NETWORK_EMPTY_ESSID) { + if (network->ssid_len == 0) { + iwe.u.data.length = sizeof("<hidden>"); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + start = iwe_stream_add_point(info, start, stop, &iwe, "<hidden>"); +#else + start = iwe_stream_add_point(start, stop, &iwe, "<hidden>"); +#endif + } else { + iwe.u.data.length = min(network->ssid_len, (u8)32); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + start = iwe_stream_add_point(info, start, stop, &iwe, network->ssid); +#else + start = iwe_stream_add_point(start, stop, &iwe, network->ssid); +#endif + } + /* Add the protocol name */ + iwe.cmd = SIOCGIWNAME; + for(i=0; i<(sizeof(ieee80211_modes)/sizeof(ieee80211_modes[0])); i++) { + if(network->mode&(1<<i)) { + sprintf(pname,ieee80211_modes[i].mode_string,ieee80211_modes[i].mode_size); + pname +=ieee80211_modes[i].mode_size; + } + } + *pname = '\0'; + snprintf(iwe.u.name, IFNAMSIZ, "IEEE802.11%s", proto_name); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + start = iwe_stream_add_event_rsl(info, start, stop, &iwe, IW_EV_CHAR_LEN); +#else + start = iwe_stream_add_event_rsl(start, stop, &iwe, IW_EV_CHAR_LEN); +#endif + /* Add mode */ + iwe.cmd = SIOCGIWMODE; + if (network->capability & + (WLAN_CAPABILITY_BSS | WLAN_CAPABILITY_IBSS)) { + if (network->capability & WLAN_CAPABILITY_BSS) + iwe.u.mode = IW_MODE_MASTER; + else + iwe.u.mode = IW_MODE_ADHOC; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + start = iwe_stream_add_event_rsl(info, start, stop, &iwe, IW_EV_UINT_LEN); +#else + start = iwe_stream_add_event_rsl(start, stop, &iwe, IW_EV_UINT_LEN); +#endif + } + + /* Add frequency/channel */ + iwe.cmd = SIOCGIWFREQ; +/* iwe.u.freq.m = ieee80211_frequency(network->channel, network->mode); + iwe.u.freq.e = 3; */ + iwe.u.freq.m = network->channel; + iwe.u.freq.e = 0; + iwe.u.freq.i = 0; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + start = iwe_stream_add_event_rsl(info, start, stop, &iwe, IW_EV_FREQ_LEN); +#else + start = iwe_stream_add_event_rsl(start, stop, &iwe, IW_EV_FREQ_LEN); +#endif + /* Add encryption capability */ + iwe.cmd = SIOCGIWENCODE; + if (network->capability & WLAN_CAPABILITY_PRIVACY) + iwe.u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY; + else + iwe.u.data.flags = IW_ENCODE_DISABLED; + iwe.u.data.length = 0; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + start = iwe_stream_add_point(info, start, stop, &iwe, network->ssid); +#else + start = iwe_stream_add_point(start, stop, &iwe, network->ssid); +#endif + /* Add basic and extended rates */ + max_rate = 0; + p = custom; + p += snprintf(p, MAX_CUSTOM_LEN - (p - custom), " Rates (Mb/s): "); + for (i = 0, j = 0; i < network->rates_len; ) { + if (j < network->rates_ex_len && + ((network->rates_ex[j] & 0x7F) < + (network->rates[i] & 0x7F))) + rate = network->rates_ex[j++] & 0x7F; + else + rate = network->rates[i++] & 0x7F; + if (rate > max_rate) + max_rate = rate; + p += snprintf(p, MAX_CUSTOM_LEN - (p - custom), + "%d%s ", rate >> 1, (rate & 1) ? ".5" : ""); + } + for (; j < network->rates_ex_len; j++) { + rate = network->rates_ex[j] & 0x7F; + p += snprintf(p, MAX_CUSTOM_LEN - (p - custom), + "%d%s ", rate >> 1, (rate & 1) ? ".5" : ""); + if (rate > max_rate) + max_rate = rate; + } + + if (network->mode >= IEEE_N_24G)//add N rate here; + { + PHT_CAPABILITY_ELE ht_cap = NULL; + bool is40M = false, isShortGI = false; + u8 max_mcs = 0; + if (!memcmp(network->bssht.bdHTCapBuf, EWC11NHTCap, 4)) + ht_cap = (PHT_CAPABILITY_ELE)&network->bssht.bdHTCapBuf[4]; + else + ht_cap = (PHT_CAPABILITY_ELE)&network->bssht.bdHTCapBuf[0]; + is40M = (ht_cap->ChlWidth)?1:0; + isShortGI = (ht_cap->ChlWidth)? + ((ht_cap->ShortGI40Mhz)?1:0): + ((ht_cap->ShortGI20Mhz)?1:0); + + max_mcs = HTGetHighestMCSRate(ieee, ht_cap->MCS, MCS_FILTER_ALL); + rate = MCS_DATA_RATE[is40M][isShortGI][max_mcs&0x7f]; + if (rate > max_rate) + max_rate = rate; + } +#if 0 + printk("max rate:%d ===basic rate:\n", max_rate); + for (i=0;i<network->rates_len;i++) + printk(" %x", network->rates[i]); + printk("\n=======extend rate\n"); + for (i=0; i<network->rates_ex_len; i++) + printk(" %x", network->rates_ex[i]); + printk("\n"); +#endif + iwe.cmd = SIOCGIWRATE; + iwe.u.bitrate.fixed = iwe.u.bitrate.disabled = 0; + iwe.u.bitrate.value = max_rate * 500000; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + start = iwe_stream_add_event_rsl(info, start, stop, &iwe, + IW_EV_PARAM_LEN); +#else + start = iwe_stream_add_event_rsl(start, stop, &iwe, + IW_EV_PARAM_LEN); +#endif + iwe.cmd = IWEVCUSTOM; + iwe.u.data.length = p - custom; + if (iwe.u.data.length) +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + start = iwe_stream_add_point(info, start, stop, &iwe, custom); +#else + start = iwe_stream_add_point(start, stop, &iwe, custom); +#endif + /* Add quality statistics */ + /* TODO: Fix these values... */ + iwe.cmd = IWEVQUAL; + iwe.u.qual.qual = network->stats.signal; + iwe.u.qual.level = network->stats.rssi; + iwe.u.qual.noise = network->stats.noise; + iwe.u.qual.updated = network->stats.mask & IEEE80211_STATMASK_WEMASK; + if (!(network->stats.mask & IEEE80211_STATMASK_RSSI)) + iwe.u.qual.updated |= IW_QUAL_LEVEL_INVALID; + if (!(network->stats.mask & IEEE80211_STATMASK_NOISE)) + iwe.u.qual.updated |= IW_QUAL_NOISE_INVALID; + if (!(network->stats.mask & IEEE80211_STATMASK_SIGNAL)) + iwe.u.qual.updated |= IW_QUAL_QUAL_INVALID; + iwe.u.qual.updated = 7; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + start = iwe_stream_add_event_rsl(info, start, stop, &iwe, IW_EV_QUAL_LEN); +#else + start = iwe_stream_add_event_rsl(start, stop, &iwe, IW_EV_QUAL_LEN); +#endif + iwe.cmd = IWEVCUSTOM; + p = custom; + + iwe.u.data.length = p - custom; + if (iwe.u.data.length) +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + start = iwe_stream_add_point(info, start, stop, &iwe, custom); +#else + start = iwe_stream_add_point(start, stop, &iwe, custom); +#endif +#if (WIRELESS_EXT < 18) + if (ieee->wpa_enabled && network->wpa_ie_len){ + char buf[MAX_WPA_IE_LEN * 2 + 30]; + // printk("WPA IE\n"); + u8 *p = buf; + p += sprintf(p, "wpa_ie="); + for (i = 0; i < network->wpa_ie_len; i++) { + p += sprintf(p, "%02x", network->wpa_ie[i]); + } + + memset(&iwe, 0, sizeof(iwe)); + iwe.cmd = IWEVCUSTOM; + iwe.u.data.length = strlen(buf); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + start = iwe_stream_add_point(info, start, stop, &iwe, buf); +#else + start = iwe_stream_add_point(start, stop, &iwe, buf); +#endif + } + + if (ieee->wpa_enabled && network->rsn_ie_len){ + char buf[MAX_WPA_IE_LEN * 2 + 30]; + + u8 *p = buf; + p += sprintf(p, "rsn_ie="); + for (i = 0; i < network->rsn_ie_len; i++) { + p += sprintf(p, "%02x", network->rsn_ie[i]); + } + + memset(&iwe, 0, sizeof(iwe)); + iwe.cmd = IWEVCUSTOM; + iwe.u.data.length = strlen(buf); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + start = iwe_stream_add_point(info, start, stop, &iwe, buf); +#else + start = iwe_stream_add_point(start, stop, &iwe, buf); +#endif + } +#else + memset(&iwe, 0, sizeof(iwe)); + if (network->wpa_ie_len) + { + char buf[MAX_WPA_IE_LEN]; + memcpy(buf, network->wpa_ie, network->wpa_ie_len); + iwe.cmd = IWEVGENIE; + iwe.u.data.length = network->wpa_ie_len; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + start = iwe_stream_add_point(info, start, stop, &iwe, buf); +#else + start = iwe_stream_add_point(start, stop, &iwe, buf); +#endif + } + memset(&iwe, 0, sizeof(iwe)); + if (network->rsn_ie_len) + { + char buf[MAX_WPA_IE_LEN]; + memcpy(buf, network->rsn_ie, network->rsn_ie_len); + iwe.cmd = IWEVGENIE; + iwe.u.data.length = network->rsn_ie_len; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + start = iwe_stream_add_point(info, start, stop, &iwe, buf); +#else + start = iwe_stream_add_point(start, stop, &iwe, buf); +#endif + } +#endif + + + /* Add EXTRA: Age to display seconds since last beacon/probe response + * for given network. */ + iwe.cmd = IWEVCUSTOM; + p = custom; + p += snprintf(p, MAX_CUSTOM_LEN - (p - custom), + " Last beacon: %lums ago", (jiffies - network->last_scanned) / (HZ / 100)); + iwe.u.data.length = p - custom; + if (iwe.u.data.length) +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + start = iwe_stream_add_point(info, start, stop, &iwe, custom); +#else + start = iwe_stream_add_point(start, stop, &iwe, custom); +#endif + + return start; +} + +int ieee80211_wx_get_scan(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct ieee80211_network *network; + unsigned long flags; + + char *ev = extra; +// char *stop = ev + IW_SCAN_MAX_DATA; + char *stop = ev + wrqu->data.length;//IW_SCAN_MAX_DATA; + //char *stop = ev + IW_SCAN_MAX_DATA; + int i = 0; + int err = 0; + IEEE80211_DEBUG_WX("Getting scan\n"); + down(&ieee->wx_sem); + spin_lock_irqsave(&ieee->lock, flags); + + list_for_each_entry(network, &ieee->network_list, list) { + i++; + if((stop-ev)<200) + { + err = -E2BIG; + break; + } + if (ieee->scan_age == 0 || + time_after(network->last_scanned + ieee->scan_age, jiffies)) + ev = rtl819x_translate_scan(ieee, ev, stop, network, info); + else + IEEE80211_DEBUG_SCAN( + "Not showing network '%s (" + MAC_FMT ")' due to age (%lums).\n", + escape_essid(network->ssid, + network->ssid_len), + MAC_ARG(network->bssid), + (jiffies - network->last_scanned) / (HZ / 100)); + } + + spin_unlock_irqrestore(&ieee->lock, flags); + up(&ieee->wx_sem); + wrqu->data.length = ev - extra; + wrqu->data.flags = 0; + + IEEE80211_DEBUG_WX("exit: %d networks returned.\n", i); + + return err; +} + +int ieee80211_wx_set_encode(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data *wrqu, char *keybuf) +{ + struct iw_point *erq = &(wrqu->encoding); + struct net_device *dev = ieee->dev; + struct ieee80211_security sec = { + .flags = 0 + }; + int i, key, key_provided, len; + struct ieee80211_crypt_data **crypt; + + IEEE80211_DEBUG_WX("SET_ENCODE\n"); + + key = erq->flags & IW_ENCODE_INDEX; + if (key) { + if (key > WEP_KEYS) + return -EINVAL; + key--; + key_provided = 1; + } else { + key_provided = 0; + key = ieee->tx_keyidx; + } + + IEEE80211_DEBUG_WX("Key: %d [%s]\n", key, key_provided ? + "provided" : "default"); + crypt = &ieee->crypt[key]; + + if (erq->flags & IW_ENCODE_DISABLED) { + if (key_provided && *crypt) { + IEEE80211_DEBUG_WX("Disabling encryption on key %d.\n", + key); + ieee80211_crypt_delayed_deinit(ieee, crypt); + } else + IEEE80211_DEBUG_WX("Disabling encryption.\n"); + + /* Check all the keys to see if any are still configured, + * and if no key index was provided, de-init them all */ + for (i = 0; i < WEP_KEYS; i++) { + if (ieee->crypt[i] != NULL) { + if (key_provided) + break; + ieee80211_crypt_delayed_deinit( + ieee, &ieee->crypt[i]); + } + } + + if (i == WEP_KEYS) { + sec.enabled = 0; + sec.level = SEC_LEVEL_0; + sec.flags |= SEC_ENABLED | SEC_LEVEL; + } + + goto done; + } + + + + sec.enabled = 1; + sec.flags |= SEC_ENABLED; + + if (*crypt != NULL && (*crypt)->ops != NULL && + strcmp((*crypt)->ops->name, "WEP") != 0) { + /* changing to use WEP; deinit previously used algorithm + * on this key */ + ieee80211_crypt_delayed_deinit(ieee, crypt); + } + + if (*crypt == NULL) { + struct ieee80211_crypt_data *new_crypt; + + /* take WEP into use */ + new_crypt = kmalloc(sizeof(struct ieee80211_crypt_data), + GFP_KERNEL); + if (new_crypt == NULL) + return -ENOMEM; + memset(new_crypt, 0, sizeof(struct ieee80211_crypt_data)); + new_crypt->ops = ieee80211_get_crypto_ops("WEP"); + if (!new_crypt->ops) { + request_module("ieee80211_crypt_wep"); + new_crypt->ops = ieee80211_get_crypto_ops("WEP"); + } +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) + if (new_crypt->ops && try_module_get(new_crypt->ops->owner)) +#else + if (new_crypt->ops && try_inc_mod_count(new_crypt->ops->owner)) +#endif + new_crypt->priv = new_crypt->ops->init(key); + + if (!new_crypt->ops || !new_crypt->priv) { + kfree(new_crypt); + new_crypt = NULL; + + printk(KERN_WARNING "%s: could not initialize WEP: " + "load module ieee80211_crypt_wep\n", + dev->name); + return -EOPNOTSUPP; + } + *crypt = new_crypt; + } + + /* If a new key was provided, set it up */ + if (erq->length > 0) { + len = erq->length <= 5 ? 5 : 13; + memcpy(sec.keys[key], keybuf, erq->length); + if (len > erq->length) + memset(sec.keys[key] + erq->length, 0, + len - erq->length); + IEEE80211_DEBUG_WX("Setting key %d to '%s' (%d:%d bytes)\n", + key, escape_essid(sec.keys[key], len), + erq->length, len); + sec.key_sizes[key] = len; + (*crypt)->ops->set_key(sec.keys[key], len, NULL, + (*crypt)->priv); + sec.flags |= (1 << key); + /* This ensures a key will be activated if no key is + * explicitely set */ + if (key == sec.active_key) + sec.flags |= SEC_ACTIVE_KEY; + ieee->tx_keyidx = key; + + } else { + len = (*crypt)->ops->get_key(sec.keys[key], WEP_KEY_LEN, + NULL, (*crypt)->priv); + if (len == 0) { + /* Set a default key of all 0 */ + printk("Setting key %d to all zero.\n", + key); + + IEEE80211_DEBUG_WX("Setting key %d to all zero.\n", + key); + memset(sec.keys[key], 0, 13); + (*crypt)->ops->set_key(sec.keys[key], 13, NULL, + (*crypt)->priv); + sec.key_sizes[key] = 13; + sec.flags |= (1 << key); + } + + /* No key data - just set the default TX key index */ + if (key_provided) { + IEEE80211_DEBUG_WX( + "Setting key %d to default Tx key.\n", key); + ieee->tx_keyidx = key; + sec.active_key = key; + sec.flags |= SEC_ACTIVE_KEY; + } + } + + done: + ieee->open_wep = !(erq->flags & IW_ENCODE_RESTRICTED); + ieee->auth_mode = ieee->open_wep ? WLAN_AUTH_OPEN : WLAN_AUTH_SHARED_KEY; + sec.auth_mode = ieee->open_wep ? WLAN_AUTH_OPEN : WLAN_AUTH_SHARED_KEY; + sec.flags |= SEC_AUTH_MODE; + IEEE80211_DEBUG_WX("Auth: %s\n", sec.auth_mode == WLAN_AUTH_OPEN ? + "OPEN" : "SHARED KEY"); + + /* For now we just support WEP, so only set that security level... + * TODO: When WPA is added this is one place that needs to change */ + sec.flags |= SEC_LEVEL; + sec.level = SEC_LEVEL_1; /* 40 and 104 bit WEP */ + + if (ieee->set_security) + ieee->set_security(dev, &sec); + + /* Do not reset port if card is in Managed mode since resetting will + * generate new IEEE 802.11 authentication which may end up in looping + * with IEEE 802.1X. If your hardware requires a reset after WEP + * configuration (for example... Prism2), implement the reset_port in + * the callbacks structures used to initialize the 802.11 stack. */ + if (ieee->reset_on_keychange && + ieee->iw_mode != IW_MODE_INFRA && + ieee->reset_port && ieee->reset_port(dev)) { + printk(KERN_DEBUG "%s: reset_port failed\n", dev->name); + return -EINVAL; + } + return 0; +} + +int ieee80211_wx_get_encode(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data *wrqu, char *keybuf) +{ + struct iw_point *erq = &(wrqu->encoding); + int len, key; + struct ieee80211_crypt_data *crypt; + + IEEE80211_DEBUG_WX("GET_ENCODE\n"); + + if(ieee->iw_mode == IW_MODE_MONITOR) + return -1; + + key = erq->flags & IW_ENCODE_INDEX; + if (key) { + if (key > WEP_KEYS) + return -EINVAL; + key--; + } else + key = ieee->tx_keyidx; + + crypt = ieee->crypt[key]; + erq->flags = key + 1; + + if (crypt == NULL || crypt->ops == NULL) { + erq->length = 0; + erq->flags |= IW_ENCODE_DISABLED; + return 0; + } +#if 0 + if (strcmp(crypt->ops->name, "WEP") != 0) { + /* only WEP is supported with wireless extensions, so just + * report that encryption is used */ + erq->length = 0; + erq->flags |= IW_ENCODE_ENABLED; + return 0; + } +#endif + len = crypt->ops->get_key(keybuf, SCM_KEY_LEN, NULL, crypt->priv); + erq->length = (len >= 0 ? len : 0); + + erq->flags |= IW_ENCODE_ENABLED; + + if (ieee->open_wep) + erq->flags |= IW_ENCODE_OPEN; + else + erq->flags |= IW_ENCODE_RESTRICTED; + + return 0; +} +#if (WIRELESS_EXT >= 18) +int ieee80211_wx_set_encode_ext(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret = 0; +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + struct net_device *dev = ieee->dev; + struct iw_point *encoding = &wrqu->encoding; + struct iw_encode_ext *ext = (struct iw_encode_ext *)extra; + int i, idx; + int group_key = 0; + const char *alg, *module; + struct ieee80211_crypto_ops *ops; + struct ieee80211_crypt_data **crypt; + + struct ieee80211_security sec = { + .flags = 0, + }; + //printk("======>encoding flag:%x,ext flag:%x, ext alg:%d\n", encoding->flags,ext->ext_flags, ext->alg); + idx = encoding->flags & IW_ENCODE_INDEX; + if (idx) { + if (idx < 1 || idx > WEP_KEYS) + return -EINVAL; + idx--; + } else + idx = ieee->tx_keyidx; + + if (ext->ext_flags & IW_ENCODE_EXT_GROUP_KEY) { + + crypt = &ieee->crypt[idx]; + + group_key = 1; + } else { + /* some Cisco APs use idx>0 for unicast in dynamic WEP */ + //printk("not group key, flags:%x, ext->alg:%d\n", ext->ext_flags, ext->alg); + if (idx != 0 && ext->alg != IW_ENCODE_ALG_WEP) + return -EINVAL; + if (ieee->iw_mode == IW_MODE_INFRA) + + crypt = &ieee->crypt[idx]; + + else + return -EINVAL; + } + + sec.flags |= SEC_ENABLED;// | SEC_ENCRYPT; + if ((encoding->flags & IW_ENCODE_DISABLED) || + ext->alg == IW_ENCODE_ALG_NONE) { + if (*crypt) + ieee80211_crypt_delayed_deinit(ieee, crypt); + + for (i = 0; i < WEP_KEYS; i++) + + if (ieee->crypt[i] != NULL) + + break; + + if (i == WEP_KEYS) { + sec.enabled = 0; + // sec.encrypt = 0; + sec.level = SEC_LEVEL_0; + sec.flags |= SEC_LEVEL; + } + //printk("disabled: flag:%x\n", encoding->flags); + goto done; + } + + sec.enabled = 1; + // sec.encrypt = 1; +#if 0 + if (group_key ? !ieee->host_mc_decrypt : + !(ieee->host_encrypt || ieee->host_decrypt || + ieee->host_encrypt_msdu)) + goto skip_host_crypt; +#endif + switch (ext->alg) { + case IW_ENCODE_ALG_WEP: + alg = "WEP"; + module = "ieee80211_crypt_wep"; + break; + case IW_ENCODE_ALG_TKIP: + alg = "TKIP"; + module = "ieee80211_crypt_tkip"; + break; + case IW_ENCODE_ALG_CCMP: + alg = "CCMP"; + module = "ieee80211_crypt_ccmp"; + break; + default: + IEEE80211_DEBUG_WX("%s: unknown crypto alg %d\n", + dev->name, ext->alg); + ret = -EINVAL; + goto done; + } + printk("alg name:%s\n",alg); + + ops = ieee80211_get_crypto_ops(alg); + if (ops == NULL) { + request_module(module); + ops = ieee80211_get_crypto_ops(alg); + } + if (ops == NULL) { + IEEE80211_DEBUG_WX("%s: unknown crypto alg %d\n", + dev->name, ext->alg); + printk("========>unknown crypto alg %d\n", ext->alg); + ret = -EINVAL; + goto done; + } + + if (*crypt == NULL || (*crypt)->ops != ops) { + struct ieee80211_crypt_data *new_crypt; + + ieee80211_crypt_delayed_deinit(ieee, crypt); + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,13)) + new_crypt = kzalloc(sizeof(*new_crypt), GFP_KERNEL); +#else + new_crypt = kmalloc(sizeof(*new_crypt), GFP_KERNEL); + memset(new_crypt,0,sizeof(*new_crypt)); +#endif + if (new_crypt == NULL) { + ret = -ENOMEM; + goto done; + } + new_crypt->ops = ops; + if (new_crypt->ops && try_module_get(new_crypt->ops->owner)) + new_crypt->priv = new_crypt->ops->init(idx); + if (new_crypt->priv == NULL) { + kfree(new_crypt); + ret = -EINVAL; + goto done; + } + *crypt = new_crypt; + + } + + if (ext->key_len > 0 && (*crypt)->ops->set_key && + (*crypt)->ops->set_key(ext->key, ext->key_len, ext->rx_seq, + (*crypt)->priv) < 0) { + IEEE80211_DEBUG_WX("%s: key setting failed\n", dev->name); + printk("key setting failed\n"); + ret = -EINVAL; + goto done; + } +#if 1 + //skip_host_crypt: + //printk("skip_host_crypt:ext_flags:%x\n", ext->ext_flags); + if (ext->ext_flags & IW_ENCODE_EXT_SET_TX_KEY) { + ieee->tx_keyidx = idx; + sec.active_key = idx; + sec.flags |= SEC_ACTIVE_KEY; + } + + if (ext->alg != IW_ENCODE_ALG_NONE) { + //memcpy(sec.keys[idx], ext->key, ext->key_len); + sec.key_sizes[idx] = ext->key_len; + sec.flags |= (1 << idx); + if (ext->alg == IW_ENCODE_ALG_WEP) { + // sec.encode_alg[idx] = SEC_ALG_WEP; + sec.flags |= SEC_LEVEL; + sec.level = SEC_LEVEL_1; + } else if (ext->alg == IW_ENCODE_ALG_TKIP) { + // sec.encode_alg[idx] = SEC_ALG_TKIP; + sec.flags |= SEC_LEVEL; + sec.level = SEC_LEVEL_2; + } else if (ext->alg == IW_ENCODE_ALG_CCMP) { + // sec.encode_alg[idx] = SEC_ALG_CCMP; + sec.flags |= SEC_LEVEL; + sec.level = SEC_LEVEL_3; + } + /* Don't set sec level for group keys. */ + if (group_key) + sec.flags &= ~SEC_LEVEL; + } +#endif +done: + if (ieee->set_security) + ieee->set_security(ieee->dev, &sec); + + if (ieee->reset_on_keychange && + ieee->iw_mode != IW_MODE_INFRA && + ieee->reset_port && ieee->reset_port(dev)) { + IEEE80211_DEBUG_WX("%s: reset_port failed\n", dev->name); + return -EINVAL; + } +#endif + return ret; +} + +int ieee80211_wx_get_encode_ext(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct iw_point *encoding = &wrqu->encoding; + struct iw_encode_ext *ext = (struct iw_encode_ext *)extra; + struct ieee80211_crypt_data *crypt; + int idx, max_key_len; + + max_key_len = encoding->length - sizeof(*ext); + if (max_key_len < 0) + return -EINVAL; + + idx = encoding->flags & IW_ENCODE_INDEX; + if (idx) { + if (idx < 1 || idx > WEP_KEYS) + return -EINVAL; + idx--; + } else + idx = ieee->tx_keyidx; + + if (!ext->ext_flags & IW_ENCODE_EXT_GROUP_KEY && + ext->alg != IW_ENCODE_ALG_WEP) + if (idx != 0 || ieee->iw_mode != IW_MODE_INFRA) + return -EINVAL; + + crypt = ieee->crypt[idx]; + encoding->flags = idx + 1; + memset(ext, 0, sizeof(*ext)); + + if (crypt == NULL || crypt->ops == NULL ) { + ext->alg = IW_ENCODE_ALG_NONE; + ext->key_len = 0; + encoding->flags |= IW_ENCODE_DISABLED; + } else { + if (strcmp(crypt->ops->name, "WEP") == 0 ) + ext->alg = IW_ENCODE_ALG_WEP; + else if (strcmp(crypt->ops->name, "TKIP")) + ext->alg = IW_ENCODE_ALG_TKIP; + else if (strcmp(crypt->ops->name, "CCMP")) + ext->alg = IW_ENCODE_ALG_CCMP; + else + return -EINVAL; + ext->key_len = crypt->ops->get_key(ext->key, SCM_KEY_LEN, NULL, crypt->priv); + encoding->flags |= IW_ENCODE_ENABLED; + if (ext->key_len && + (ext->alg == IW_ENCODE_ALG_TKIP || + ext->alg == IW_ENCODE_ALG_CCMP)) + ext->ext_flags |= IW_ENCODE_EXT_TX_SEQ_VALID; + + } + + return 0; +} + +int ieee80211_wx_set_mlme(struct ieee80211_device *ieee, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + struct iw_mlme *mlme = (struct iw_mlme *) extra; + switch (mlme->cmd) { + case IW_MLME_DEAUTH: + case IW_MLME_DISASSOC: + ieee80211_disassociate(ieee); + break; + default: + return -EOPNOTSUPP; + } +#endif + return 0; +} + +int ieee80211_wx_set_auth(struct ieee80211_device *ieee, + struct iw_request_info *info, + struct iw_param *data, char *extra) +{ +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + switch (data->flags & IW_AUTH_INDEX) { + case IW_AUTH_WPA_VERSION: + /*need to support wpa2 here*/ + //printk("wpa version:%x\n", data->value); + break; + case IW_AUTH_CIPHER_PAIRWISE: + case IW_AUTH_CIPHER_GROUP: + case IW_AUTH_KEY_MGMT: + /* + * * Host AP driver does not use these parameters and allows + * * wpa_supplicant to control them internally. + * */ + break; + case IW_AUTH_TKIP_COUNTERMEASURES: + ieee->tkip_countermeasures = data->value; + break; + case IW_AUTH_DROP_UNENCRYPTED: + ieee->drop_unencrypted = data->value; + break; + + case IW_AUTH_80211_AUTH_ALG: + //printk("======>%s():data->value is %d\n",__FUNCTION__,data->value); + // ieee->open_wep = (data->value&IW_AUTH_ALG_OPEN_SYSTEM)?1:0; + if(data->value & IW_AUTH_ALG_SHARED_KEY){ + ieee->open_wep = 0; + ieee->auth_mode = 1; + } + else if(data->value & IW_AUTH_ALG_OPEN_SYSTEM){ + ieee->open_wep = 1; + ieee->auth_mode = 0; + } + else if(data->value & IW_AUTH_ALG_LEAP){ + ieee->open_wep = 1; + ieee->auth_mode = 2; + //printk("hahahaa:LEAP\n"); + } + else + return -EINVAL; + //printk("open_wep:%d\n", ieee->open_wep); + break; + +#if 1 + case IW_AUTH_WPA_ENABLED: + ieee->wpa_enabled = (data->value)?1:0; + //printk("enalbe wpa:%d\n", ieee->wpa_enabled); + break; + +#endif + case IW_AUTH_RX_UNENCRYPTED_EAPOL: + ieee->ieee802_1x = data->value; + break; + case IW_AUTH_PRIVACY_INVOKED: + ieee->privacy_invoked = data->value; + break; + default: + return -EOPNOTSUPP; + } +#endif + return 0; +} +#endif +#if 1 +int ieee80211_wx_set_gen_ie(struct ieee80211_device *ieee, u8 *ie, size_t len) +{ +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) +#if 0 + printk("====>%s()\n", __FUNCTION__); + { + int i; + for (i=0; i<len; i++) + printk("%2x ", ie[i]&0xff); + printk("\n"); + } +#endif + u8 *buf; + + if (len>MAX_WPA_IE_LEN || (len && ie == NULL)) + { + // printk("return error out, len:%d\n", len); + return -EINVAL; + } + + + if (len) + { + if (len != ie[1]+2) + { + printk("len:%d, ie:%d\n", len, ie[1]); + return -EINVAL; + } + buf = kmalloc(len, GFP_KERNEL); + if (buf == NULL) + return -ENOMEM; + memcpy(buf, ie, len); + kfree(ieee->wpa_ie); + ieee->wpa_ie = buf; + ieee->wpa_ie_len = len; + } + else{ + if (ieee->wpa_ie) + kfree(ieee->wpa_ie); + ieee->wpa_ie = NULL; + ieee->wpa_ie_len = 0; + } +#endif + return 0; + +} +#endif + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) +EXPORT_SYMBOL(ieee80211_wx_set_gen_ie); +#if (WIRELESS_EXT >= 18) +EXPORT_SYMBOL(ieee80211_wx_set_mlme); +EXPORT_SYMBOL(ieee80211_wx_set_auth); +EXPORT_SYMBOL(ieee80211_wx_set_encode_ext); +EXPORT_SYMBOL(ieee80211_wx_get_encode_ext); +#endif +EXPORT_SYMBOL(ieee80211_wx_get_scan); +EXPORT_SYMBOL(ieee80211_wx_set_encode); +EXPORT_SYMBOL(ieee80211_wx_get_encode); +#else +EXPORT_SYMBOL_NOVERS(ieee80211_wx_set_gen_ie); +//EXPORT_SYMBOL_NOVERS(ieee80211_wx_set_mlme); +//EXPORT_SYMBOL_NOVERS(ieee80211_wx_set_auth); +//EXPORT_SYMBOL_NOVERS(ieee80211_wx_set_encode_ext); +EXPORT_SYMBOL_NOVERS(ieee80211_wx_get_scan); +EXPORT_SYMBOL_NOVERS(ieee80211_wx_set_encode); +EXPORT_SYMBOL_NOVERS(ieee80211_wx_get_encode); +#endif diff --git a/drivers/staging/rtl8192su/ieee80211/internal.h b/drivers/staging/rtl8192su/ieee80211/internal.h new file mode 100644 index 000000000000..ddc22350d006 --- /dev/null +++ b/drivers/staging/rtl8192su/ieee80211/internal.h @@ -0,0 +1,115 @@ +/* + * Cryptographic API. + * + * Copyright (c) 2002 James Morris <jmorris@intercode.com.au> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + */ +#ifndef _CRYPTO_INTERNAL_H +#define _CRYPTO_INTERNAL_H + + +//#include <linux/crypto.h> +#include "rtl_crypto.h" +#include <linux/mm.h> +#include <linux/highmem.h> +#include <linux/init.h> +#include <asm/hardirq.h> +#include <asm/softirq.h> +#include <asm/kmap_types.h> + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,20)) +#define list_for_each_entry(pos, head, member) \ + for (pos = list_entry((head)->next, typeof(*pos), member), \ + prefetch(pos->member.next); \ + &pos->member != (head); \ + pos = list_entry(pos->member.next, typeof(*pos), member), \ + prefetch(pos->member.next)) + +static inline void cond_resched(void) +{ + if (need_resched()) { + set_current_state(TASK_RUNNING); + schedule(); + } +} +#endif + +extern enum km_type crypto_km_types[]; + +static inline enum km_type crypto_kmap_type(int out) +{ + return crypto_km_types[(in_softirq() ? 2 : 0) + out]; +} + +static inline void *crypto_kmap(struct page *page, int out) +{ + return kmap_atomic(page, crypto_kmap_type(out)); +} + +static inline void crypto_kunmap(void *vaddr, int out) +{ + kunmap_atomic(vaddr, crypto_kmap_type(out)); +} + +static inline void crypto_yield(struct crypto_tfm *tfm) +{ + if (!in_softirq()) + cond_resched(); +} + +static inline void *crypto_tfm_ctx(struct crypto_tfm *tfm) +{ + return (void *)&tfm[1]; +} + +struct crypto_alg *crypto_alg_lookup(const char *name); + +#ifdef CONFIG_KMOD +void crypto_alg_autoload(const char *name); +struct crypto_alg *crypto_alg_mod_lookup(const char *name); +#else +static inline struct crypto_alg *crypto_alg_mod_lookup(const char *name) +{ + return crypto_alg_lookup(name); +} +#endif + +#ifdef CONFIG_CRYPTO_HMAC +int crypto_alloc_hmac_block(struct crypto_tfm *tfm); +void crypto_free_hmac_block(struct crypto_tfm *tfm); +#else +static inline int crypto_alloc_hmac_block(struct crypto_tfm *tfm) +{ + return 0; +} + +static inline void crypto_free_hmac_block(struct crypto_tfm *tfm) +{ } +#endif + +#ifdef CONFIG_PROC_FS +void __init crypto_init_proc(void); +#else +static inline void crypto_init_proc(void) +{ } +#endif + +int crypto_init_digest_flags(struct crypto_tfm *tfm, u32 flags); +int crypto_init_cipher_flags(struct crypto_tfm *tfm, u32 flags); +int crypto_init_compress_flags(struct crypto_tfm *tfm, u32 flags); + +int crypto_init_digest_ops(struct crypto_tfm *tfm); +int crypto_init_cipher_ops(struct crypto_tfm *tfm); +int crypto_init_compress_ops(struct crypto_tfm *tfm); + +void crypto_exit_digest_ops(struct crypto_tfm *tfm); +void crypto_exit_cipher_ops(struct crypto_tfm *tfm); +void crypto_exit_compress_ops(struct crypto_tfm *tfm); + +#endif /* _CRYPTO_INTERNAL_H */ + diff --git a/drivers/staging/rtl8192su/ieee80211/kmap_types.h b/drivers/staging/rtl8192su/ieee80211/kmap_types.h new file mode 100644 index 000000000000..de67bb01b5f5 --- /dev/null +++ b/drivers/staging/rtl8192su/ieee80211/kmap_types.h @@ -0,0 +1,20 @@ +#ifndef __KMAP_TYPES_H + +#define __KMAP_TYPES_H + + +enum km_type { + KM_BOUNCE_READ, + KM_SKB_SUNRPC_DATA, + KM_SKB_DATA_SOFTIRQ, + KM_USER0, + KM_USER1, + KM_BH_IRQ, + KM_SOFTIRQ0, + KM_SOFTIRQ1, + KM_TYPE_NR +}; + +#define _ASM_KMAP_TYPES_H + +#endif diff --git a/drivers/staging/rtl8192su/ieee80211/michael_mic.c b/drivers/staging/rtl8192su/ieee80211/michael_mic.c new file mode 100644 index 000000000000..df256e487c20 --- /dev/null +++ b/drivers/staging/rtl8192su/ieee80211/michael_mic.c @@ -0,0 +1,194 @@ +/* + * Cryptographic API + * + * Michael MIC (IEEE 802.11i/TKIP) keyed digest + * + * Copyright (c) 2004 Jouni Malinen <jkmaline@cc.hut.fi> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/string.h> +//#include <linux/crypto.h> +#include "rtl_crypto.h" + + +struct michael_mic_ctx { + u8 pending[4]; + size_t pending_len; + + u32 l, r; +}; + + +static inline u32 rotl(u32 val, int bits) +{ + return (val << bits) | (val >> (32 - bits)); +} + + +static inline u32 rotr(u32 val, int bits) +{ + return (val >> bits) | (val << (32 - bits)); +} + + +static inline u32 xswap(u32 val) +{ + return ((val & 0x00ff00ff) << 8) | ((val & 0xff00ff00) >> 8); +} + + +#define michael_block(l, r) \ +do { \ + r ^= rotl(l, 17); \ + l += r; \ + r ^= xswap(l); \ + l += r; \ + r ^= rotl(l, 3); \ + l += r; \ + r ^= rotr(l, 2); \ + l += r; \ +} while (0) + + +static inline u32 get_le32(const u8 *p) +{ + return p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24); +} + + +static inline void put_le32(u8 *p, u32 v) +{ + p[0] = v; + p[1] = v >> 8; + p[2] = v >> 16; + p[3] = v >> 24; +} + + +static void michael_init(void *ctx) +{ + struct michael_mic_ctx *mctx = ctx; + mctx->pending_len = 0; +} + + +static void michael_update(void *ctx, const u8 *data, unsigned int len) +{ + struct michael_mic_ctx *mctx = ctx; + + if (mctx->pending_len) { + int flen = 4 - mctx->pending_len; + if (flen > len) + flen = len; + memcpy(&mctx->pending[mctx->pending_len], data, flen); + mctx->pending_len += flen; + data += flen; + len -= flen; + + if (mctx->pending_len < 4) + return; + + mctx->l ^= get_le32(mctx->pending); + michael_block(mctx->l, mctx->r); + mctx->pending_len = 0; + } + + while (len >= 4) { + mctx->l ^= get_le32(data); + michael_block(mctx->l, mctx->r); + data += 4; + len -= 4; + } + + if (len > 0) { + mctx->pending_len = len; + memcpy(mctx->pending, data, len); + } +} + + +static void michael_final(void *ctx, u8 *out) +{ + struct michael_mic_ctx *mctx = ctx; + u8 *data = mctx->pending; + + /* Last block and padding (0x5a, 4..7 x 0) */ + switch (mctx->pending_len) { + case 0: + mctx->l ^= 0x5a; + break; + case 1: + mctx->l ^= data[0] | 0x5a00; + break; + case 2: + mctx->l ^= data[0] | (data[1] << 8) | 0x5a0000; + break; + case 3: + mctx->l ^= data[0] | (data[1] << 8) | (data[2] << 16) | + 0x5a000000; + break; + } + michael_block(mctx->l, mctx->r); + /* l ^= 0; */ + michael_block(mctx->l, mctx->r); + + put_le32(out, mctx->l); + put_le32(out + 4, mctx->r); +} + + +static int michael_setkey(void *ctx, const u8 *key, unsigned int keylen, + u32 *flags) +{ + struct michael_mic_ctx *mctx = ctx; + if (keylen != 8) { + if (flags) + *flags = CRYPTO_TFM_RES_BAD_KEY_LEN; + return -EINVAL; + } + mctx->l = get_le32(key); + mctx->r = get_le32(key + 4); + return 0; +} + + +static struct crypto_alg michael_mic_alg = { + .cra_name = "michael_mic", + .cra_flags = CRYPTO_ALG_TYPE_DIGEST, + .cra_blocksize = 8, + .cra_ctxsize = sizeof(struct michael_mic_ctx), + .cra_module = THIS_MODULE, + .cra_list = LIST_HEAD_INIT(michael_mic_alg.cra_list), + .cra_u = { .digest = { + .dia_digestsize = 8, + .dia_init = michael_init, + .dia_update = michael_update, + .dia_final = michael_final, + .dia_setkey = michael_setkey } } +}; + + +static int __init michael_mic_init(void) +{ + return crypto_register_alg(&michael_mic_alg); +} + + +static void __exit michael_mic_exit(void) +{ + crypto_unregister_alg(&michael_mic_alg); +} + + +module_init(michael_mic_init); +module_exit(michael_mic_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Michael MIC"); +MODULE_AUTHOR("Jouni Malinen <jkmaline@cc.hut.fi>"); diff --git a/drivers/staging/rtl8192su/ieee80211/proc.c b/drivers/staging/rtl8192su/ieee80211/proc.c new file mode 100644 index 000000000000..4f3f9ed7751a --- /dev/null +++ b/drivers/staging/rtl8192su/ieee80211/proc.c @@ -0,0 +1,116 @@ +/* + * Scatterlist Cryptographic API. + * + * Procfs information. + * + * Copyright (c) 2002 James Morris <jmorris@intercode.com.au> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + */ +#include <linux/init.h> +//#include <linux/crypto.h> +#include "rtl_crypto.h" +#include <linux/rwsem.h> +#include <linux/proc_fs.h> +#include <linux/seq_file.h> +#include "internal.h" + +extern struct list_head crypto_alg_list; +extern struct rw_semaphore crypto_alg_sem; + +static void *c_start(struct seq_file *m, loff_t *pos) +{ + struct list_head *v; + loff_t n = *pos; + + down_read(&crypto_alg_sem); + list_for_each(v, &crypto_alg_list) + if (!n--) + return list_entry(v, struct crypto_alg, cra_list); + return NULL; +} + +static void *c_next(struct seq_file *m, void *p, loff_t *pos) +{ + struct list_head *v = p; + + (*pos)++; + v = v->next; + return (v == &crypto_alg_list) ? + NULL : list_entry(v, struct crypto_alg, cra_list); +} + +static void c_stop(struct seq_file *m, void *p) +{ + up_read(&crypto_alg_sem); +} + +static int c_show(struct seq_file *m, void *p) +{ + struct crypto_alg *alg = (struct crypto_alg *)p; + + seq_printf(m, "name : %s\n", alg->cra_name); + seq_printf(m, "module : %s\n", + (alg->cra_module ? + alg->cra_module->name : + "kernel")); + + switch (alg->cra_flags & CRYPTO_ALG_TYPE_MASK) { + case CRYPTO_ALG_TYPE_CIPHER: + seq_printf(m, "type : cipher\n"); + seq_printf(m, "blocksize : %u\n", alg->cra_blocksize); + seq_printf(m, "min keysize : %u\n", + alg->cra_cipher.cia_min_keysize); + seq_printf(m, "max keysize : %u\n", + alg->cra_cipher.cia_max_keysize); + break; + + case CRYPTO_ALG_TYPE_DIGEST: + seq_printf(m, "type : digest\n"); + seq_printf(m, "blocksize : %u\n", alg->cra_blocksize); + seq_printf(m, "digestsize : %u\n", + alg->cra_digest.dia_digestsize); + break; + case CRYPTO_ALG_TYPE_COMPRESS: + seq_printf(m, "type : compression\n"); + break; + default: + seq_printf(m, "type : unknown\n"); + break; + } + + seq_putc(m, '\n'); + return 0; +} + +static struct seq_operations crypto_seq_ops = { + .start = c_start, + .next = c_next, + .stop = c_stop, + .show = c_show +}; + +static int crypto_info_open(struct inode *inode, struct file *file) +{ + return seq_open(file, &crypto_seq_ops); +} + +static struct file_operations proc_crypto_ops = { + .open = crypto_info_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release +}; + +void __init crypto_init_proc(void) +{ + struct proc_dir_entry *proc; + + proc = create_proc_entry("crypto", 0, NULL); + if (proc) + proc->proc_fops = &proc_crypto_ops; +} diff --git a/drivers/staging/rtl8192su/ieee80211/readme b/drivers/staging/rtl8192su/ieee80211/readme new file mode 100644 index 000000000000..5764f2859286 --- /dev/null +++ b/drivers/staging/rtl8192su/ieee80211/readme @@ -0,0 +1,162 @@ +What this layer should do + +- It mantain the old mechanism as alternative, so the + ipw2100 driver works with really few changes. +- Encapsulate / Decapsulate ieee80211 packet +- Handle fragmentation +- Optionally provide an alterantive mechanism for netif queue stop/wake, + so that the ieee80211 layer will pass one fragment per time instead of + one txb struct per time. so the driver can stop the queue in the middle + of a packet. +- Provide two different TX interfaces for cards that can handle management + frames on one HW queue, and data on another, and for cards that have only + one HW queue (the latter untested and very, very rough). +- Optionally provide the logic for handling IBSS/MASTER/MONITOR/BSS modes + and for the channel, essid and wap get/set wireless extension requests. + so that the driver has only to change channel when the ieee stack tell it. +- Optionally provide a scanning mechanism so that the driver has not to + worry about this, just implement the set channel calback and pass + frames to the upper layer +- Optionally provide the bss client protocol handshaking (just with open + authentication) +- Optionally provide the probe request send mechanism +- Optionally provide the bss master mode logic to handle association + protocol (only open authentication) and probe responses. +- SW wep encryption (with open authentication) +- It collects some stats +- It provides beacons to the card when it ask for them + +What this layer doesn't do (yet) +- Perform shared authentication +- Have full support for master mode (the AP should loop back in the air + frames from an associated client to another. This could be done easily + with few lines of code, and it is done in my previous version of the + stach, but a table of association must be keept and a disassociation + policy must be decided and implemented. +- Handle cleanly the full ieee 802.11 protocol. In AP mode it never + disassociate clients, and it is really prone to always allow access. + In bss client mode it is a bit rough with AP deauth and disassoc requests. +- It has not any entry point to view the collected stats. +- Altought it takes care of the card supported rates in the management frame + it sends, support for rate changing on TXed packet is not complete. +- Give up once associated in bss client mode (it never detect a + signal loss condition to disassociate and restart scanning) +- Provide a mechanism for enabling the TX in monitor mode, so + userspace programs can TX raw packets. +- Provide a mechanism for cards that need that the SW take care of beacon + TX completely, in sense that the SW has to enqueue by itself beacons + to the card so it TX them (if any...) +APIs + +Callback functions in the original stack has been mantained. +following has been added (from ieee80211.h) + + /* Softmac-generated frames (mamagement) are TXed via this + * callback if the flag IEEE_SOFTMAC_SINGLE_QUEUE is + * not set. As some cards may have different HW queues that + * one might want to use for data and management frames + * the option to have two callbacks might be useful. + * This fucntion can't sleep. + */ + int (*softmac_hard_start_xmit)(struct sk_buff *skb, + struct net_device *dev); + + /* used instead of hard_start_xmit (not softmac_hard_start_xmit) + * if the IEEE_SOFTMAC_TX_QUEUE feature is used to TX data + * frames. I the option IEEE_SOFTMAC_SINGLE_QUEUE is also set + * then also management frames are sent via this callback. + * This function can't sleep. + */ + void (*softmac_data_hard_start_xmit)(struct sk_buff *skb, + struct net_device *dev); + + /* stops the HW queue for DATA frames. Useful to avoid + * waste time to TX data frame when we are reassociating + * This function can sleep. + */ + void (*data_hard_stop)(struct net_device *dev); + + /* OK this is complementar to data_poll_hard_stop */ + void (*data_hard_resume)(struct net_device *dev); + + /* ask to the driver to retune the radio . + * This function can sleep. the driver should ensure + * the radio has been swithced before return. + */ + void (*set_chan)(struct net_device *dev,short ch); + + /* These are not used if the ieee stack takes care of + * scanning (IEEE_SOFTMAC_SCAN feature set). + * In this case only the set_chan is used. + * + * The syncro version is similar to the start_scan but + * does not return until all channels has been scanned. + * this is called in user context and should sleep, + * it is called in a work_queue when swithcing to ad-hoc mode + * or in behalf of iwlist scan when the card is associated + * and root user ask for a scan. + * the fucntion stop_scan should stop both the syncro and + * background scanning and can sleep. + * The fucntion start_scan should initiate the background + * scanning and can't sleep. + */ + void (*scan_syncro)(struct net_device *dev); + void (*start_scan)(struct net_device *dev); + void (*stop_scan)(struct net_device *dev); + + /* indicate the driver that the link state is changed + * for example it may indicate the card is associated now. + * Driver might be interested in this to apply RX filter + * rules or simply light the LINK led + */ + void (*link_change)(struct net_device *dev); + +Functions hard_data_[resume/stop] are optional and should not be used +if the driver decides to uses data+management frames enqueue in a +single HQ queue (thus using just the softmac_hard_data_start_xmit +callback). + +Function that the driver can use are: + +ieee80211_get_beacon - this is called by the driver when + the HW needs a beacon. +ieee80211_softmac_start_protocol - this should normally be called in the + driver open function +ieee80211_softmac_stop_protocol - the opposite of the above +ieee80211_wake_queue - this is similar to netif_wake_queue +ieee80211_reset_queue - this throw away fragments pending(if any) +ieee80211_stop_queue - this is similar to netif_stop_queue + + +known BUGS: +- When performing syncro scan (possiblily when swithcing to ad-hoc mode + and when running iwlist scan when associated) there is still an odd + behaviour.. I have not looked in this more accurately (yet). + +locking: +locking is done by means of three structures. +1- ieee->lock (by means of spin_[un]lock_irq[save/restore] +2- ieee->wx_sem +3- ieee->scan_sem + +the lock 1 is what protect most of the critical sections in the ieee stack. +the lock 2 is used to avoid that more than one of the SET wireless extension +handlers (as well as start/stop protocol function) are running at the same time. +the lock 1 is used when we need to modify or read the shared data in the wx handlers. +In other words the lock 2 will prevent one SET action will run across another SET +action (by make sleep the 2nd one) but allow GET actions, while the lock 1 +make atomic those little shared data access in both GET and SET operation. +So get operation will be never be delayed really: they will never sleep.. +Furthermore in the top of some SET operations a flag is set before acquiring +the lock. This is an help to make the previous running SET operation to +finish faster if needed (just in case the second one will totally undo the +first, so there is not need to complete the 1st really.. ). +The background scanning mechaninsm is protected by the lock 1 except for the +workqueue. this wq is here just to let the set_chan callback sleep (I thinked it +might be appreciated by USB network card driver developer). In this case the lock 3 +take its turn. +Thus the stop function needs both the locks. +Funny in the syncro scan the lock 2 play its role (as both the syncro_scan +function and the stop scan function are called with this semaphore held). + + diff --git a/drivers/staging/rtl8192su/ieee80211/rtl819x_BA.h b/drivers/staging/rtl8192su/ieee80211/rtl819x_BA.h new file mode 100644 index 000000000000..8ddc8bf9dc26 --- /dev/null +++ b/drivers/staging/rtl8192su/ieee80211/rtl819x_BA.h @@ -0,0 +1,69 @@ +#ifndef _BATYPE_H_ +#define _BATYPE_H_ + +#define TOTAL_TXBA_NUM 16 +#define TOTAL_RXBA_NUM 16 + +#define BA_SETUP_TIMEOUT 200 +#define BA_INACT_TIMEOUT 60000 + +#define BA_POLICY_DELAYED 0 +#define BA_POLICY_IMMEDIATE 1 + +#define ADDBA_STATUS_SUCCESS 0 +#define ADDBA_STATUS_REFUSED 37 +#define ADDBA_STATUS_INVALID_PARAM 38 + +#define DELBA_REASON_QSTA_LEAVING 36 +#define DELBA_REASON_END_BA 37 +#define DELBA_REASON_UNKNOWN_BA 38 +#define DELBA_REASON_TIMEOUT 39 +/* whether need define BA Action frames here? +struct ieee80211_ADDBA_Req{ + struct ieee80211_header_data header; + u8 category; + u8 +} __attribute__ ((packed)); +*/ +//Is this need?I put here just to make it easier to define structure BA_RECORD //WB +typedef union _SEQUENCE_CONTROL{ + u16 ShortData; + struct + { + u16 FragNum:4; + u16 SeqNum:12; + }field; +}SEQUENCE_CONTROL, *PSEQUENCE_CONTROL; + +typedef union _BA_PARAM_SET { + u8 charData[2]; + u16 shortData; + struct { + u16 AMSDU_Support:1; + u16 BAPolicy:1; + u16 TID:4; + u16 BufferSize:10; + } field; +} BA_PARAM_SET, *PBA_PARAM_SET; + +typedef union _DELBA_PARAM_SET { + u8 charData[2]; + u16 shortData; + struct { + u16 Reserved:11; + u16 Initiator:1; + u16 TID:4; + } field; +} DELBA_PARAM_SET, *PDELBA_PARAM_SET; + +typedef struct _BA_RECORD { + struct timer_list Timer; + u8 bValid; + u8 DialogToken; + BA_PARAM_SET BaParamSet; + u16 BaTimeoutValue; + SEQUENCE_CONTROL BaStartSeqCtrl; +} BA_RECORD, *PBA_RECORD; + +#endif //end _BATYPE_H_ + diff --git a/drivers/staging/rtl8192su/ieee80211/rtl819x_BAProc.c b/drivers/staging/rtl8192su/ieee80211/rtl819x_BAProc.c new file mode 100644 index 000000000000..cc5623a94b42 --- /dev/null +++ b/drivers/staging/rtl8192su/ieee80211/rtl819x_BAProc.c @@ -0,0 +1,781 @@ +/******************************************************************************************************************************** + * This file is created to process BA Action Frame. According to 802.11 spec, there are 3 BA action types at all. And as BA is + * related to TS, this part need some struture defined in QOS side code. Also TX RX is going to be resturctured, so how to send + * ADDBAREQ ADDBARSP and DELBA packet is still on consideration. Temporarily use MANAGE QUEUE instead of Normal Queue. + * WB 2008-05-27 + * *****************************************************************************************************************************/ +#include "ieee80211.h" +#include "rtl819x_BA.h" + +/******************************************************************************************************************** + *function: Activate BA entry. And if Time is nozero, start timer. + * input: PBA_RECORD pBA //BA entry to be enabled + * u16 Time //indicate time delay. + * output: none +********************************************************************************************************************/ +void ActivateBAEntry(struct ieee80211_device* ieee, PBA_RECORD pBA, u16 Time) +{ + pBA->bValid = true; + if(Time != 0) + mod_timer(&pBA->Timer, jiffies + MSECS(Time)); +} + +/******************************************************************************************************************** + *function: deactivate BA entry, including its timer. + * input: PBA_RECORD pBA //BA entry to be disabled + * output: none +********************************************************************************************************************/ +void DeActivateBAEntry( struct ieee80211_device* ieee, PBA_RECORD pBA) +{ + pBA->bValid = false; + del_timer_sync(&pBA->Timer); +} +/******************************************************************************************************************** + *function: deactivete BA entry in Tx Ts, and send DELBA. + * input: + * PTX_TS_RECORD pTxTs //Tx Ts which is to deactivate BA entry. + * output: none + * notice: As PTX_TS_RECORD structure will be defined in QOS, so wait to be merged. //FIXME +********************************************************************************************************************/ +u8 TxTsDeleteBA( struct ieee80211_device* ieee, PTX_TS_RECORD pTxTs) +{ + PBA_RECORD pAdmittedBa = &pTxTs->TxAdmittedBARecord; //These two BA entries must exist in TS structure + PBA_RECORD pPendingBa = &pTxTs->TxPendingBARecord; + u8 bSendDELBA = false; + + // Delete pending BA + if(pPendingBa->bValid) + { + DeActivateBAEntry(ieee, pPendingBa); + bSendDELBA = true; + } + + // Delete admitted BA + if(pAdmittedBa->bValid) + { + DeActivateBAEntry(ieee, pAdmittedBa); + bSendDELBA = true; + } + + return bSendDELBA; +} + +/******************************************************************************************************************** + *function: deactivete BA entry in Tx Ts, and send DELBA. + * input: + * PRX_TS_RECORD pRxTs //Rx Ts which is to deactivate BA entry. + * output: none + * notice: As PRX_TS_RECORD structure will be defined in QOS, so wait to be merged. //FIXME, same with above +********************************************************************************************************************/ +u8 RxTsDeleteBA( struct ieee80211_device* ieee, PRX_TS_RECORD pRxTs) +{ + PBA_RECORD pBa = &pRxTs->RxAdmittedBARecord; + u8 bSendDELBA = false; + + if(pBa->bValid) + { + DeActivateBAEntry(ieee, pBa); + bSendDELBA = true; + } + + return bSendDELBA; +} + +/******************************************************************************************************************** + *function: reset BA entry + * input: + * PBA_RECORD pBA //entry to be reset + * output: none +********************************************************************************************************************/ +void ResetBaEntry( PBA_RECORD pBA) +{ + pBA->bValid = false; + pBA->BaParamSet.shortData = 0; + pBA->BaTimeoutValue = 0; + pBA->DialogToken = 0; + pBA->BaStartSeqCtrl.ShortData = 0; +} +//These functions need porting here or not? +/******************************************************************************************************************************* + *function: construct ADDBAREQ and ADDBARSP frame here together. + * input: u8* Dst //ADDBA frame's destination + * PBA_RECORD pBA //BA_RECORD entry which stores the necessary information for BA. + * u16 StatusCode //status code in RSP and I will use it to indicate whether it's RSP or REQ(will I?) + * u8 type //indicate whether it's RSP(ACT_ADDBARSP) ow REQ(ACT_ADDBAREQ) + * output: none + * return: sk_buff* skb //return constructed skb to xmit +*******************************************************************************************************************************/ +static struct sk_buff* ieee80211_ADDBA(struct ieee80211_device* ieee, u8* Dst, PBA_RECORD pBA, u16 StatusCode, u8 type) +{ + struct sk_buff *skb = NULL; + struct ieee80211_hdr_3addr* BAReq = NULL; + u8* tag = NULL; + u16 tmp = 0; + u16 len = ieee->tx_headroom + 9; + //category(1) + action field(1) + Dialog Token(1) + BA Parameter Set(2) + BA Timeout Value(2) + BA Start SeqCtrl(2)(or StatusCode(2)) + IEEE80211_DEBUG(IEEE80211_DL_TRACE | IEEE80211_DL_BA, "========>%s(), frame(%d) sentd to:"MAC_FMT", ieee->dev:%p\n", __FUNCTION__, type, MAC_ARG(Dst), ieee->dev); + if (pBA == NULL||ieee == NULL) + { + IEEE80211_DEBUG(IEEE80211_DL_ERR, "pBA(%p) is NULL or ieee(%p) is NULL\n", pBA, ieee); + return NULL; + } + skb = dev_alloc_skb(len + sizeof( struct ieee80211_hdr_3addr)); //need to add something others? FIXME + if (skb == NULL) + { + IEEE80211_DEBUG(IEEE80211_DL_ERR, "can't alloc skb for ADDBA_REQ\n"); + return NULL; + } + + memset(skb->data, 0, sizeof( struct ieee80211_hdr_3addr)); //I wonder whether it's necessary. Apparently kernel will not do it when alloc a skb. + skb_reserve(skb, ieee->tx_headroom); + + BAReq = ( struct ieee80211_hdr_3addr *) skb_put(skb,sizeof( struct ieee80211_hdr_3addr)); + + memcpy(BAReq->addr1, Dst, ETH_ALEN); + memcpy(BAReq->addr2, ieee->dev->dev_addr, ETH_ALEN); + + memcpy(BAReq->addr3, ieee->current_network.bssid, ETH_ALEN); + + BAReq->frame_ctl = cpu_to_le16(IEEE80211_STYPE_MANAGE_ACT); //action frame + + //tag += sizeof( struct ieee80211_hdr_3addr); //move to action field + tag = (u8*)skb_put(skb, 9); + *tag ++= ACT_CAT_BA; + *tag ++= type; + // Dialog Token + *tag ++= pBA->DialogToken; + + if (ACT_ADDBARSP == type) + { + // Status Code + printk("=====>to send ADDBARSP\n"); + tmp = cpu_to_le16(StatusCode); + memcpy(tag, (u8*)&tmp, 2); + tag += 2; + } + // BA Parameter Set + tmp = cpu_to_le16(pBA->BaParamSet.shortData); + memcpy(tag, (u8*)&tmp, 2); + tag += 2; + // BA Timeout Value + tmp = cpu_to_le16(pBA->BaTimeoutValue); + memcpy(tag, (u8*)&tmp, 2); + tag += 2; + + if (ACT_ADDBAREQ == type) + { + // BA Start SeqCtrl + memcpy(tag,(u8*)&(pBA->BaStartSeqCtrl), 2); + tag += 2; + } + + IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA|IEEE80211_DL_BA, skb->data, skb->len); + return skb; + //return NULL; +} + +#if 0 //I try to merge ADDBA_REQ and ADDBA_RSP frames together.. +/******************************************************************************************************************** + *function: construct ADDBAREQ frame + * input: u8* dst //ADDBARsp frame's destination + * PBA_RECORD pBA //BA_RECORD entry which stores the necessary information for BA_RSP. + * u16 StatusCode //status code. + * output: none + * return: sk_buff* skb //return constructed skb to xmit +********************************************************************************************************************/ +static struct sk_buff* ieee80211_ADDBA_Rsp( IN struct ieee80211_device* ieee, u8* dst, PBA_RECORD pBA, u16 StatusCode) +{ + OCTET_STRING osADDBAFrame, tmp; + + FillOctetString(osADDBAFrame, Buffer, 0); + *pLength = 0; + + ConstructMaFrameHdr( + Adapter, + Addr, + ACT_CAT_BA, + ACT_ADDBARSP, + &osADDBAFrame ); + + // Dialog Token + FillOctetString(tmp, &pBA->DialogToken, 1); + PacketAppendData(&osADDBAFrame, tmp); + + // Status Code + FillOctetString(tmp, &StatusCode, 2); + PacketAppendData(&osADDBAFrame, tmp); + + // BA Parameter Set + FillOctetString(tmp, &pBA->BaParamSet, 2); + PacketAppendData(&osADDBAFrame, tmp); + + // BA Timeout Value + FillOctetString(tmp, &pBA->BaTimeoutValue, 2); + PacketAppendData(&osADDBAFrame, tmp); + + *pLength = osADDBAFrame.Length; +} +#endif + +/******************************************************************************************************************** + *function: construct DELBA frame + * input: u8* dst //DELBA frame's destination + * PBA_RECORD pBA //BA_RECORD entry which stores the necessary information for BA + * TR_SELECT TxRxSelect //TX RX direction + * u16 ReasonCode //status code. + * output: none + * return: sk_buff* skb //return constructed skb to xmit +********************************************************************************************************************/ +static struct sk_buff* ieee80211_DELBA( + struct ieee80211_device* ieee, + u8* dst, + PBA_RECORD pBA, + TR_SELECT TxRxSelect, + u16 ReasonCode + ) +{ + DELBA_PARAM_SET DelbaParamSet; + struct sk_buff *skb = NULL; + struct ieee80211_hdr_3addr* Delba = NULL; + u8* tag = NULL; + u16 tmp = 0; + //len = head len + DELBA Parameter Set(2) + Reason Code(2) + u16 len = 6 + ieee->tx_headroom; + + if (net_ratelimit()) + IEEE80211_DEBUG(IEEE80211_DL_TRACE | IEEE80211_DL_BA, "========>%s(), ReasonCode(%d) sentd to:"MAC_FMT"\n", __FUNCTION__, ReasonCode, MAC_ARG(dst)); + + memset(&DelbaParamSet, 0, 2); + + DelbaParamSet.field.Initiator = (TxRxSelect==TX_DIR)?1:0; + DelbaParamSet.field.TID = pBA->BaParamSet.field.TID; + + skb = dev_alloc_skb(len + sizeof( struct ieee80211_hdr_3addr)); //need to add something others? FIXME + if (skb == NULL) + { + IEEE80211_DEBUG(IEEE80211_DL_ERR, "can't alloc skb for ADDBA_REQ\n"); + return NULL; + } +// memset(skb->data, 0, len+sizeof( struct ieee80211_hdr_3addr)); + skb_reserve(skb, ieee->tx_headroom); + + Delba = ( struct ieee80211_hdr_3addr *) skb_put(skb,sizeof( struct ieee80211_hdr_3addr)); + + memcpy(Delba->addr1, dst, ETH_ALEN); + memcpy(Delba->addr2, ieee->dev->dev_addr, ETH_ALEN); + memcpy(Delba->addr3, ieee->current_network.bssid, ETH_ALEN); + Delba->frame_ctl = cpu_to_le16(IEEE80211_STYPE_MANAGE_ACT); //action frame + + tag = (u8*)skb_put(skb, 6); + + *tag ++= ACT_CAT_BA; + *tag ++= ACT_DELBA; + + // DELBA Parameter Set + tmp = cpu_to_le16(DelbaParamSet.shortData); + memcpy(tag, (u8*)&tmp, 2); + tag += 2; + // Reason Code + tmp = cpu_to_le16(ReasonCode); + memcpy(tag, (u8*)&tmp, 2); + tag += 2; + + IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA|IEEE80211_DL_BA, skb->data, skb->len); + if (net_ratelimit()) + IEEE80211_DEBUG(IEEE80211_DL_TRACE | IEEE80211_DL_BA, "<=====%s()\n", __FUNCTION__); + return skb; +} + +/******************************************************************************************************************** + *function: send ADDBAReq frame out + * input: u8* dst //ADDBAReq frame's destination + * PBA_RECORD pBA //BA_RECORD entry which stores the necessary information for BA + * output: none + * notice: If any possible, please hide pBA in ieee. And temporarily use Manage Queue as softmac_mgmt_xmit() usually does +********************************************************************************************************************/ +void ieee80211_send_ADDBAReq(struct ieee80211_device* ieee, u8* dst, PBA_RECORD pBA) +{ + struct sk_buff *skb = NULL; + skb = ieee80211_ADDBA(ieee, dst, pBA, 0, ACT_ADDBAREQ); //construct ACT_ADDBAREQ frames so set statuscode zero. + + if (skb) + { + softmac_mgmt_xmit(skb, ieee); + //add statistic needed here. + //and skb will be freed in softmac_mgmt_xmit(), so omit all dev_kfree_skb_any() outside softmac_mgmt_xmit() + //WB + } + else + { + IEEE80211_DEBUG(IEEE80211_DL_ERR, "alloc skb error in function %s()\n", __FUNCTION__); + } + return; +} + +/******************************************************************************************************************** + *function: send ADDBARSP frame out + * input: u8* dst //DELBA frame's destination + * PBA_RECORD pBA //BA_RECORD entry which stores the necessary information for BA + * u16 StatusCode //RSP StatusCode + * output: none + * notice: If any possible, please hide pBA in ieee. And temporarily use Manage Queue as softmac_mgmt_xmit() usually does +********************************************************************************************************************/ +void ieee80211_send_ADDBARsp(struct ieee80211_device* ieee, u8* dst, PBA_RECORD pBA, u16 StatusCode) +{ + struct sk_buff *skb = NULL; + skb = ieee80211_ADDBA(ieee, dst, pBA, StatusCode, ACT_ADDBARSP); //construct ACT_ADDBARSP frames + if (skb) + { + softmac_mgmt_xmit(skb, ieee); + //same above + } + else + { + IEEE80211_DEBUG(IEEE80211_DL_ERR, "alloc skb error in function %s()\n", __FUNCTION__); + } + + return; + +} +/******************************************************************************************************************** + *function: send ADDBARSP frame out + * input: u8* dst //DELBA frame's destination + * PBA_RECORD pBA //BA_RECORD entry which stores the necessary information for BA + * TR_SELECT TxRxSelect //TX or RX + * u16 ReasonCode //DEL ReasonCode + * output: none + * notice: If any possible, please hide pBA in ieee. And temporarily use Manage Queue as softmac_mgmt_xmit() usually does +********************************************************************************************************************/ + +void ieee80211_send_DELBA(struct ieee80211_device* ieee, u8* dst, PBA_RECORD pBA, TR_SELECT TxRxSelect, u16 ReasonCode) +{ + struct sk_buff *skb = NULL; + skb = ieee80211_DELBA(ieee, dst, pBA, TxRxSelect, ReasonCode); //construct ACT_ADDBARSP frames + if (skb) + { + softmac_mgmt_xmit(skb, ieee); + //same above + } + else + { + IEEE80211_DEBUG(IEEE80211_DL_ERR, "alloc skb error in function %s()\n", __FUNCTION__); + } + return ; +} + +/******************************************************************************************************************** + *function: RX ADDBAReq + * input: struct sk_buff * skb //incoming ADDBAReq skb. + * return: 0(pass), other(fail) + * notice: As this function need support of QOS, I comment some code out. And when qos is ready, this code need to be support. +********************************************************************************************************************/ +int ieee80211_rx_ADDBAReq( struct ieee80211_device* ieee, struct sk_buff *skb) +{ + struct ieee80211_hdr_3addr* req = NULL; + u16 rc = 0; + u8 * dst = NULL, *pDialogToken = NULL, *tag = NULL; + PBA_RECORD pBA = NULL; + PBA_PARAM_SET pBaParamSet = NULL; + u16* pBaTimeoutVal = NULL; + PSEQUENCE_CONTROL pBaStartSeqCtrl = NULL; + PRX_TS_RECORD pTS = NULL; + + if (skb->len < sizeof( struct ieee80211_hdr_3addr) + 9) + { + IEEE80211_DEBUG(IEEE80211_DL_ERR, " Invalid skb len in BAREQ(%d / %d)\n", skb->len, (sizeof( struct ieee80211_hdr_3addr) + 9)); + return -1; + } + + IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA|IEEE80211_DL_BA, skb->data, skb->len); + + req = ( struct ieee80211_hdr_3addr*) skb->data; + tag = (u8*)req; + dst = (u8*)(&req->addr2[0]); + tag += sizeof( struct ieee80211_hdr_3addr); + pDialogToken = tag + 2; //category+action + pBaParamSet = (PBA_PARAM_SET)(tag + 3); //+DialogToken + pBaTimeoutVal = (u16*)(tag + 5); + pBaStartSeqCtrl = (PSEQUENCE_CONTROL)(req + 7); + + printk("====================>rx ADDBAREQ from :"MAC_FMT"\n", MAC_ARG(dst)); +//some other capability is not ready now. + if( (ieee->current_network.qos_data.active == 0) || + (ieee->pHTInfo->bCurrentHTSupport == false) || + (ieee->pHTInfo->IOTAction & HT_IOT_ACT_REJECT_ADDBA_REQ)) //|| + // (ieee->pStaQos->bEnableRxImmBA == false) ) + { + rc = ADDBA_STATUS_REFUSED; + IEEE80211_DEBUG(IEEE80211_DL_ERR, "Failed to reply on ADDBA_REQ as some capability is not ready(%d, %d)\n", ieee->current_network.qos_data.active, ieee->pHTInfo->bCurrentHTSupport); + goto OnADDBAReq_Fail; + } + // Search for related traffic stream. + // If there is no matched TS, reject the ADDBA request. + if( !GetTs( + ieee, + (PTS_COMMON_INFO*)(&pTS), + dst, + (u8)(pBaParamSet->field.TID), + RX_DIR, + true) ) + { + rc = ADDBA_STATUS_REFUSED; + IEEE80211_DEBUG(IEEE80211_DL_ERR, "can't get TS in %s()\n", __FUNCTION__); + goto OnADDBAReq_Fail; + } + pBA = &pTS->RxAdmittedBARecord; + // To Determine the ADDBA Req content + // We can do much more check here, including BufferSize, AMSDU_Support, Policy, StartSeqCtrl... + // I want to check StartSeqCtrl to make sure when we start aggregation!!! + // + if(pBaParamSet->field.BAPolicy == BA_POLICY_DELAYED) + { + rc = ADDBA_STATUS_INVALID_PARAM; + IEEE80211_DEBUG(IEEE80211_DL_ERR, "BA Policy is not correct in %s()\n", __FUNCTION__); + goto OnADDBAReq_Fail; + } + // Admit the ADDBA Request + // + DeActivateBAEntry(ieee, pBA); + pBA->DialogToken = *pDialogToken; + pBA->BaParamSet = *pBaParamSet; + pBA->BaTimeoutValue = *pBaTimeoutVal; + pBA->BaStartSeqCtrl = *pBaStartSeqCtrl; + //for half N mode we only aggregate 1 frame + if (ieee->GetHalfNmodeSupportByAPsHandler(ieee->dev)|| + (ieee->pHTInfo->IOTAction & HT_IOT_ACT_ALLOW_PEER_AGG_ONE_PKT)) + pBA->BaParamSet.field.BufferSize = 1; + else + pBA->BaParamSet.field.BufferSize = 32; + ActivateBAEntry(ieee, pBA, 0);//pBA->BaTimeoutValue); + ieee80211_send_ADDBARsp(ieee, dst, pBA, ADDBA_STATUS_SUCCESS); + + // End of procedure. + return 0; + +OnADDBAReq_Fail: + { + BA_RECORD BA; + BA.BaParamSet = *pBaParamSet; + BA.BaTimeoutValue = *pBaTimeoutVal; + BA.DialogToken = *pDialogToken; + BA.BaParamSet.field.BAPolicy = BA_POLICY_IMMEDIATE; + ieee80211_send_ADDBARsp(ieee, dst, &BA, rc); + return 0; //we send RSP out. + } + +} + +/******************************************************************************************************************** + *function: RX ADDBARSP + * input: struct sk_buff * skb //incoming ADDBAReq skb. + * return: 0(pass), other(fail) + * notice: As this function need support of QOS, I comment some code out. And when qos is ready, this code need to be support. +********************************************************************************************************************/ +int ieee80211_rx_ADDBARsp( struct ieee80211_device* ieee, struct sk_buff *skb) +{ + struct ieee80211_hdr_3addr* rsp = NULL; + PBA_RECORD pPendingBA, pAdmittedBA; + PTX_TS_RECORD pTS = NULL; + u8* dst = NULL, *pDialogToken = NULL, *tag = NULL; + u16* pStatusCode = NULL, *pBaTimeoutVal = NULL; + PBA_PARAM_SET pBaParamSet = NULL; + u16 ReasonCode; + + if (skb->len < sizeof( struct ieee80211_hdr_3addr) + 9) + { + IEEE80211_DEBUG(IEEE80211_DL_ERR, " Invalid skb len in BARSP(%d / %d)\n", skb->len, (sizeof( struct ieee80211_hdr_3addr) + 9)); + return -1; + } + rsp = ( struct ieee80211_hdr_3addr*)skb->data; + tag = (u8*)rsp; + dst = (u8*)(&rsp->addr2[0]); + tag += sizeof( struct ieee80211_hdr_3addr); + pDialogToken = tag + 2; + pStatusCode = (u16*)(tag + 3); + pBaParamSet = (PBA_PARAM_SET)(tag + 5); + pBaTimeoutVal = (u16*)(tag + 7); + + // Check the capability + // Since we can always receive A-MPDU, we just check if it is under HT mode. + if( ieee->current_network.qos_data.active == 0 || + ieee->pHTInfo->bCurrentHTSupport == false || + ieee->pHTInfo->bCurrentAMPDUEnable == false ) + { + IEEE80211_DEBUG(IEEE80211_DL_ERR, "reject to ADDBA_RSP as some capability is not ready(%d, %d, %d)\n",ieee->current_network.qos_data.active, ieee->pHTInfo->bCurrentHTSupport, ieee->pHTInfo->bCurrentAMPDUEnable); + ReasonCode = DELBA_REASON_UNKNOWN_BA; + goto OnADDBARsp_Reject; + } + + + // + // Search for related TS. + // If there is no TS found, we wil reject ADDBA Rsp by sending DELBA frame. + // + if (!GetTs( + ieee, + (PTS_COMMON_INFO*)(&pTS), + dst, + (u8)(pBaParamSet->field.TID), + TX_DIR, + false) ) + { + IEEE80211_DEBUG(IEEE80211_DL_ERR, "can't get TS in %s()\n", __FUNCTION__); + ReasonCode = DELBA_REASON_UNKNOWN_BA; + goto OnADDBARsp_Reject; + } + + pTS->bAddBaReqInProgress = false; + pPendingBA = &pTS->TxPendingBARecord; + pAdmittedBA = &pTS->TxAdmittedBARecord; + + + // + // Check if related BA is waiting for setup. + // If not, reject by sending DELBA frame. + // + if((pAdmittedBA->bValid==true)) + { + // Since BA is already setup, we ignore all other ADDBA Response. + IEEE80211_DEBUG(IEEE80211_DL_BA, "OnADDBARsp(): Recv ADDBA Rsp. Drop because already admit it! \n"); + return -1; + } + else if((pPendingBA->bValid == false) ||(*pDialogToken != pPendingBA->DialogToken)) + { + IEEE80211_DEBUG(IEEE80211_DL_ERR, "OnADDBARsp(): Recv ADDBA Rsp. BA invalid, DELBA! \n"); + ReasonCode = DELBA_REASON_UNKNOWN_BA; + goto OnADDBARsp_Reject; + } + else + { + IEEE80211_DEBUG(IEEE80211_DL_BA, "OnADDBARsp(): Recv ADDBA Rsp. BA is admitted! Status code:%X\n", *pStatusCode); + DeActivateBAEntry(ieee, pPendingBA); + } + + + if(*pStatusCode == ADDBA_STATUS_SUCCESS) + { + // + // Determine ADDBA Rsp content here. + // We can compare the value of BA parameter set that Peer returned and Self sent. + // If it is OK, then admitted. Or we can send DELBA to cancel BA mechanism. + // + if(pBaParamSet->field.BAPolicy == BA_POLICY_DELAYED) + { + // Since this is a kind of ADDBA failed, we delay next ADDBA process. + pTS->bAddBaReqDelayed = true; + DeActivateBAEntry(ieee, pAdmittedBA); + ReasonCode = DELBA_REASON_END_BA; + goto OnADDBARsp_Reject; + } + + + // + // Admitted condition + // + pAdmittedBA->DialogToken = *pDialogToken; + pAdmittedBA->BaTimeoutValue = *pBaTimeoutVal; + pAdmittedBA->BaStartSeqCtrl = pPendingBA->BaStartSeqCtrl; + pAdmittedBA->BaParamSet = *pBaParamSet; + DeActivateBAEntry(ieee, pAdmittedBA); + ActivateBAEntry(ieee, pAdmittedBA, *pBaTimeoutVal); + } + else + { + // Delay next ADDBA process. + pTS->bAddBaReqDelayed = true; + } + + // End of procedure + return 0; + +OnADDBARsp_Reject: + { + BA_RECORD BA; + BA.BaParamSet = *pBaParamSet; + ieee80211_send_DELBA(ieee, dst, &BA, TX_DIR, ReasonCode); + return 0; + } + +} + +/******************************************************************************************************************** + *function: RX DELBA + * input: struct sk_buff * skb //incoming ADDBAReq skb. + * return: 0(pass), other(fail) + * notice: As this function need support of QOS, I comment some code out. And when qos is ready, this code need to be support. +********************************************************************************************************************/ +int ieee80211_rx_DELBA(struct ieee80211_device* ieee,struct sk_buff *skb) +{ + struct ieee80211_hdr_3addr* delba = NULL; + PDELBA_PARAM_SET pDelBaParamSet = NULL; + u16* pReasonCode = NULL; + u8* dst = NULL; + + if (skb->len < sizeof( struct ieee80211_hdr_3addr) + 6) + { + IEEE80211_DEBUG(IEEE80211_DL_ERR, " Invalid skb len in DELBA(%d / %d)\n", skb->len, (sizeof( struct ieee80211_hdr_3addr) + 6)); + return -1; + } + + if(ieee->current_network.qos_data.active == 0 || + ieee->pHTInfo->bCurrentHTSupport == false ) + { + IEEE80211_DEBUG(IEEE80211_DL_ERR, "received DELBA while QOS or HT is not supported(%d, %d)\n",ieee->current_network.qos_data.active, ieee->pHTInfo->bCurrentHTSupport); + return -1; + } + + IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA|IEEE80211_DL_BA, skb->data, skb->len); + delba = ( struct ieee80211_hdr_3addr*)skb->data; + dst = (u8*)(&delba->addr2[0]); + delba += sizeof( struct ieee80211_hdr_3addr); + pDelBaParamSet = (PDELBA_PARAM_SET)(delba+2); + pReasonCode = (u16*)(delba+4); + + if(pDelBaParamSet->field.Initiator == 1) + { + PRX_TS_RECORD pRxTs; + + if( !GetTs( + ieee, + (PTS_COMMON_INFO*)&pRxTs, + dst, + (u8)pDelBaParamSet->field.TID, + RX_DIR, + false) ) + { + IEEE80211_DEBUG(IEEE80211_DL_ERR, "can't get TS for RXTS in %s()\n", __FUNCTION__); + return -1; + } + + RxTsDeleteBA(ieee, pRxTs); + } + else + { + PTX_TS_RECORD pTxTs; + + if(!GetTs( + ieee, + (PTS_COMMON_INFO*)&pTxTs, + dst, + (u8)pDelBaParamSet->field.TID, + TX_DIR, + false) ) + { + IEEE80211_DEBUG(IEEE80211_DL_ERR, "can't get TS for TXTS in %s()\n", __FUNCTION__); + return -1; + } + + pTxTs->bUsingBa = false; + pTxTs->bAddBaReqInProgress = false; + pTxTs->bAddBaReqDelayed = false; + del_timer_sync(&pTxTs->TsAddBaTimer); + //PlatformCancelTimer(Adapter, &pTxTs->TsAddBaTimer); + TxTsDeleteBA(ieee, pTxTs); + } + return 0; +} + +// +// ADDBA initiate. This can only be called by TX side. +// +void +TsInitAddBA( + struct ieee80211_device* ieee, + PTX_TS_RECORD pTS, + u8 Policy, + u8 bOverwritePending + ) +{ + PBA_RECORD pBA = &pTS->TxPendingBARecord; + + if(pBA->bValid==true && bOverwritePending==false) + return; + + // Set parameters to "Pending" variable set + DeActivateBAEntry(ieee, pBA); + + pBA->DialogToken++; // DialogToken: Only keep the latest dialog token + pBA->BaParamSet.field.AMSDU_Support = 0; // Do not support A-MSDU with A-MPDU now!! + pBA->BaParamSet.field.BAPolicy = Policy; // Policy: Delayed or Immediate + pBA->BaParamSet.field.TID = pTS->TsCommonInfo.TSpec.f.TSInfo.field.ucTSID; // TID + // BufferSize: This need to be set according to A-MPDU vector + pBA->BaParamSet.field.BufferSize = 32; // BufferSize: This need to be set according to A-MPDU vector + pBA->BaTimeoutValue = 0; // Timeout value: Set 0 to disable Timer + pBA->BaStartSeqCtrl.field.SeqNum = (pTS->TxCurSeq + 3) % 4096; // Block Ack will start after 3 packets later. + + ActivateBAEntry(ieee, pBA, BA_SETUP_TIMEOUT); + + ieee80211_send_ADDBAReq(ieee, pTS->TsCommonInfo.Addr, pBA); +} + +void +TsInitDelBA( struct ieee80211_device* ieee, PTS_COMMON_INFO pTsCommonInfo, TR_SELECT TxRxSelect) +{ + + if(TxRxSelect == TX_DIR) + { + PTX_TS_RECORD pTxTs = (PTX_TS_RECORD)pTsCommonInfo; + + if(TxTsDeleteBA(ieee, pTxTs)) + ieee80211_send_DELBA( + ieee, + pTsCommonInfo->Addr, + (pTxTs->TxAdmittedBARecord.bValid)?(&pTxTs->TxAdmittedBARecord):(&pTxTs->TxPendingBARecord), + TxRxSelect, + DELBA_REASON_END_BA); + } + else if(TxRxSelect == RX_DIR) + { + PRX_TS_RECORD pRxTs = (PRX_TS_RECORD)pTsCommonInfo; + if(RxTsDeleteBA(ieee, pRxTs)) + ieee80211_send_DELBA( + ieee, + pTsCommonInfo->Addr, + &pRxTs->RxAdmittedBARecord, + TxRxSelect, + DELBA_REASON_END_BA ); + } +} +/******************************************************************************************************************** + *function: BA setup timer + * input: unsigned long data //acturally we send TX_TS_RECORD or RX_TS_RECORD to these timer + * return: NULL + * notice: +********************************************************************************************************************/ +void BaSetupTimeOut(unsigned long data) +{ + PTX_TS_RECORD pTxTs = (PTX_TS_RECORD)data; + + pTxTs->bAddBaReqInProgress = false; + pTxTs->bAddBaReqDelayed = true; + pTxTs->TxPendingBARecord.bValid = false; +} + +void TxBaInactTimeout(unsigned long data) +{ + PTX_TS_RECORD pTxTs = (PTX_TS_RECORD)data; + struct ieee80211_device *ieee = container_of(pTxTs, struct ieee80211_device, TxTsRecord[pTxTs->num]); + TxTsDeleteBA(ieee, pTxTs); + ieee80211_send_DELBA( + ieee, + pTxTs->TsCommonInfo.Addr, + &pTxTs->TxAdmittedBARecord, + TX_DIR, + DELBA_REASON_TIMEOUT); +} + +void RxBaInactTimeout(unsigned long data) +{ + PRX_TS_RECORD pRxTs = (PRX_TS_RECORD)data; + struct ieee80211_device *ieee = container_of(pRxTs, struct ieee80211_device, RxTsRecord[pRxTs->num]); + + RxTsDeleteBA(ieee, pRxTs); + ieee80211_send_DELBA( + ieee, + pRxTs->TsCommonInfo.Addr, + &pRxTs->RxAdmittedBARecord, + RX_DIR, + DELBA_REASON_TIMEOUT); + return ; +} + diff --git a/drivers/staging/rtl8192su/ieee80211/rtl819x_HT.h b/drivers/staging/rtl8192su/ieee80211/rtl819x_HT.h new file mode 100644 index 000000000000..16a7462d7dfb --- /dev/null +++ b/drivers/staging/rtl8192su/ieee80211/rtl819x_HT.h @@ -0,0 +1,517 @@ +#ifndef _RTL819XU_HTTYPE_H_ +#define _RTL819XU_HTTYPE_H_ + +//------------------------------------------------------------ +// The HT Capability element is present in beacons, association request, +// reassociation request and probe response frames +//------------------------------------------------------------ + +// +// Operation mode value +// +#define HT_OPMODE_NO_PROTECT 0 +#define HT_OPMODE_OPTIONAL 1 +#define HT_OPMODE_40MHZ_PROTECT 2 +#define HT_OPMODE_MIXED 3 + +// +// MIMO Power Save Setings +// +#define MIMO_PS_STATIC 0 +#define MIMO_PS_DYNAMIC 1 +#define MIMO_PS_NOLIMIT 3 + + +// +// There should be 128 bits to cover all of the MCS rates. However, since +// 8190 does not support too much rates, one integer is quite enough. +// + +#define sHTCLng 4 + + +#define HT_SUPPORTED_MCS_1SS_BITMAP 0x000000ff +#define HT_SUPPORTED_MCS_2SS_BITMAP 0x0000ff00 +#define HT_SUPPORTED_MCS_1SS_2SS_BITMAP HT_MCS_1SS_BITMAP|HT_MCS_1SS_2SS_BITMAP + + +typedef enum _HT_MCS_RATE{ + HT_MCS0 = 0x00000001, + HT_MCS1 = 0x00000002, + HT_MCS2 = 0x00000004, + HT_MCS3 = 0x00000008, + HT_MCS4 = 0x00000010, + HT_MCS5 = 0x00000020, + HT_MCS6 = 0x00000040, + HT_MCS7 = 0x00000080, + HT_MCS8 = 0x00000100, + HT_MCS9 = 0x00000200, + HT_MCS10 = 0x00000400, + HT_MCS11 = 0x00000800, + HT_MCS12 = 0x00001000, + HT_MCS13 = 0x00002000, + HT_MCS14 = 0x00004000, + HT_MCS15 = 0x00008000, + // Do not define MCS32 here although 8190 support MCS32 +}HT_MCS_RATE,*PHT_MCS_RATE; + +// +// Represent Channel Width in HT Capabilities +// +typedef enum _HT_CHANNEL_WIDTH{ + HT_CHANNEL_WIDTH_20 = 0, + HT_CHANNEL_WIDTH_20_40 = 1, +}HT_CHANNEL_WIDTH, *PHT_CHANNEL_WIDTH; + +// +// Represent Extention Channel Offset in HT Capabilities +// This is available only in 40Mhz mode. +// +typedef enum _HT_EXTCHNL_OFFSET{ + HT_EXTCHNL_OFFSET_NO_EXT = 0, + HT_EXTCHNL_OFFSET_UPPER = 1, + HT_EXTCHNL_OFFSET_NO_DEF = 2, + HT_EXTCHNL_OFFSET_LOWER = 3, +}HT_EXTCHNL_OFFSET, *PHT_EXTCHNL_OFFSET; + +typedef enum _CHNLOP{ + CHNLOP_NONE = 0, // No Action now + CHNLOP_SCAN = 1, // Scan in progress + CHNLOP_SWBW = 2, // Bandwidth switching in progress + CHNLOP_SWCHNL = 3, // Software Channel switching in progress +} CHNLOP, *PCHNLOP; + +// Determine if the Channel Operation is in progress +#define CHHLOP_IN_PROGRESS(_pHTInfo) \ + ((_pHTInfo)->ChnlOp > CHNLOP_NONE) ? TRUE : FALSE + +/* +typedef union _HT_CAPABILITY{ + u16 ShortData; + u8 CharData[2]; + struct + { + u16 AdvCoding:1; + u16 ChlWidth:1; + u16 MimoPwrSave:2; + u16 GreenField:1; + u16 ShortGI20Mhz:1; + u16 ShortGI40Mhz:1; + u16 STBC:1; + u16 BeamForm:1; + u16 DelayBA:1; + u16 MaxAMSDUSize:1; + u16 DssCCk:1; + u16 PSMP:1; + u16 Rsvd:3; + }Field; +}HT_CAPABILITY, *PHT_CAPABILITY; + +typedef union _HT_CAPABILITY_MACPARA{ + u8 ShortData; + u8 CharData[1]; + struct + { + u8 MaxRxAMPDU:2; + u8 MPDUDensity:2; + u8 Rsvd:4; + }Field; +}HT_CAPABILITY_MACPARA, *PHT_CAPABILITY_MACPARA; +*/ + +typedef enum _HT_ACTION{ + ACT_RECOMMAND_WIDTH = 0, + ACT_MIMO_PWR_SAVE = 1, + ACT_PSMP = 2, + ACT_SET_PCO_PHASE = 3, + ACT_MIMO_CHL_MEASURE = 4, + ACT_RECIPROCITY_CORRECT = 5, + ACT_MIMO_CSI_MATRICS = 6, + ACT_MIMO_NOCOMPR_STEER = 7, + ACT_MIMO_COMPR_STEER = 8, + ACT_ANTENNA_SELECT = 9, +} HT_ACTION, *PHT_ACTION; + + +/* 2007/06/07 MH Define sub-carrier mode for 40MHZ. */ +typedef enum _HT_Bandwidth_40MHZ_Sub_Carrier{ + SC_MODE_DUPLICATE = 0, + SC_MODE_LOWER = 1, + SC_MODE_UPPER = 2, + SC_MODE_FULL40MHZ = 3, +}HT_BW40_SC_E; + +typedef struct _HT_CAPABILITY_ELE{ + + //HT capability info + u8 AdvCoding:1; + u8 ChlWidth:1; + u8 MimoPwrSave:2; + u8 GreenField:1; + u8 ShortGI20Mhz:1; + u8 ShortGI40Mhz:1; + u8 TxSTBC:1; + u8 RxSTBC:2; + u8 DelayBA:1; + u8 MaxAMSDUSize:1; + u8 DssCCk:1; + u8 PSMP:1; + u8 Rsvd1:1; + u8 LSigTxopProtect:1; + + //MAC HT parameters info + u8 MaxRxAMPDUFactor:2; + u8 MPDUDensity:3; + u8 Rsvd2:3; + + //Supported MCS set + u8 MCS[16]; + + + //Extended HT Capability Info + u16 ExtHTCapInfo; + + //TXBF Capabilities + u8 TxBFCap[4]; + + //Antenna Selection Capabilities + u8 ASCap; + +} __attribute__ ((packed)) HT_CAPABILITY_ELE, *PHT_CAPABILITY_ELE; + +//------------------------------------------------------------ +// The HT Information element is present in beacons +// Only AP is required to include this element +//------------------------------------------------------------ + +typedef struct _HT_INFORMATION_ELE{ + u8 ControlChl; + + u8 ExtChlOffset:2; + u8 RecommemdedTxWidth:1; + u8 RIFS:1; + u8 PSMPAccessOnly:1; + u8 SrvIntGranularity:3; + + u8 OptMode:2; + u8 NonGFDevPresent:1; + u8 Revd1:5; + u8 Revd2:8; + + u8 Rsvd3:6; + u8 DualBeacon:1; + u8 DualCTSProtect:1; + + u8 SecondaryBeacon:1; + u8 LSigTxopProtectFull:1; + u8 PcoActive:1; + u8 PcoPhase:1; + u8 Rsvd4:4; + + u8 BasicMSC[16]; +} __attribute__ ((packed)) HT_INFORMATION_ELE, *PHT_INFORMATION_ELE; + +// +// MIMO Power Save control field. +// This is appear in MIMO Power Save Action Frame +// +typedef struct _MIMOPS_CTRL{ + u8 MimoPsEnable:1; + u8 MimoPsMode:1; + u8 Reserved:6; +} MIMOPS_CTRL, *PMIMOPS_CTRL; + +typedef enum _HT_SPEC_VER{ + HT_SPEC_VER_IEEE = 0, + HT_SPEC_VER_EWC = 1, +}HT_SPEC_VER, *PHT_SPEC_VER; + +typedef enum _HT_AGGRE_MODE_E{ + HT_AGG_AUTO = 0, + HT_AGG_FORCE_ENABLE = 1, + HT_AGG_FORCE_DISABLE = 2, +}HT_AGGRE_MODE_E, *PHT_AGGRE_MODE_E; + +//------------------------------------------------------------ +// The Data structure is used to keep HT related variables when card is +// configured as non-AP STA mode. **Note** Current_xxx should be set +// to default value in HTInitializeHTInfo() +//------------------------------------------------------------ + +typedef struct _RT_HIGH_THROUGHPUT{ + u8 bEnableHT; + u8 bCurrentHTSupport; + + u8 bRegBW40MHz; // Tx 40MHz channel capablity + u8 bCurBW40MHz; // Tx 40MHz channel capability + + u8 bRegShortGI40MHz; // Tx Short GI for 40Mhz + u8 bCurShortGI40MHz; // Tx Short GI for 40MHz + + u8 bRegShortGI20MHz; // Tx Short GI for 20MHz + u8 bCurShortGI20MHz; // Tx Short GI for 20MHz + + u8 bRegSuppCCK; // Tx CCK rate capability + u8 bCurSuppCCK; // Tx CCK rate capability + + // 802.11n spec version for "peer" + HT_SPEC_VER ePeerHTSpecVer; + + + // HT related information for "Self" + HT_CAPABILITY_ELE SelfHTCap; // This is HT cap element sent to peer STA, which also indicate HT Rx capabilities. + HT_INFORMATION_ELE SelfHTInfo; // This is HT info element sent to peer STA, which also indicate HT Rx capabilities. + + // HT related information for "Peer" + u8 PeerHTCapBuf[32]; + u8 PeerHTInfoBuf[32]; + + + // A-MSDU related + u8 bAMSDU_Support; // This indicates Tx A-MSDU capability + u16 nAMSDU_MaxSize; // This indicates Tx A-MSDU capability + u8 bCurrent_AMSDU_Support; // This indicates Tx A-MSDU capability + u16 nCurrent_AMSDU_MaxSize; // This indicates Tx A-MSDU capability + + + // AMPDU related <2006.08.10 Emily> + u8 bAMPDUEnable; // This indicate Tx A-MPDU capability + u8 bCurrentAMPDUEnable; // This indicate Tx A-MPDU capability + u8 AMPDU_Factor; // This indicate Tx A-MPDU capability + u8 CurrentAMPDUFactor; // This indicate Tx A-MPDU capability + u8 MPDU_Density; // This indicate Tx A-MPDU capability + u8 CurrentMPDUDensity; // This indicate Tx A-MPDU capability + + // Forced A-MPDU enable + HT_AGGRE_MODE_E ForcedAMPDUMode; + u8 ForcedAMPDUFactor; + u8 ForcedMPDUDensity; + + // Forced A-MSDU enable + HT_AGGRE_MODE_E ForcedAMSDUMode; + u16 ForcedAMSDUMaxSize; + + u8 bForcedShortGI; + + u8 CurrentOpMode; + + // MIMO PS related + u8 SelfMimoPs; + u8 PeerMimoPs; + + // 40MHz Channel Offset settings. + HT_EXTCHNL_OFFSET CurSTAExtChnlOffset; + u8 bCurTxBW40MHz; // If we use 40 MHz to Tx + u8 PeerBandwidth; + + // For Bandwidth Switching + u8 bSwBwInProgress; + CHNLOP ChnlOp; // software switching channel in progress. By Bruce, 2008-02-15. + u8 SwBwStep; + //struct timer_list SwBwTimer; //moved to ieee80211_device. as timer_list need include some header file here. + + // For Realtek proprietary A-MPDU factor for aggregation + u8 bRegRT2RTAggregation; + u8 RT2RT_HT_Mode; + u8 bCurrentRT2RTAggregation; + u8 bCurrentRT2RTLongSlotTime; + u8 szRT2RTAggBuffer[10]; + + // Rx Reorder control + u8 bRegRxReorderEnable; + u8 bCurRxReorderEnable; + u8 RxReorderWinSize; + u8 RxReorderPendingTime; + u16 RxReorderDropCounter; + +#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE + u8 UsbTxAggrNum; +#endif +#ifdef USB_RX_AGGREGATION_SUPPORT + u8 UsbRxFwAggrEn; + u8 UsbRxFwAggrPageNum; + u8 UsbRxFwAggrPacketNum; + u8 UsbRxFwAggrTimeout; +#endif + + // Add for Broadcom(Linksys) IOT. Joseph + u8 bIsPeerBcm; + + // For IOT issue. + u8 IOTPeer; + u32 IOTAction; + u8 IOTRaFunc; +} __attribute__ ((packed)) RT_HIGH_THROUGHPUT, *PRT_HIGH_THROUGHPUT; + + +//------------------------------------------------------------ +// The Data structure is used to keep HT related variable for "each Sta" +// when card is configured as "AP mode" +//------------------------------------------------------------ + +typedef struct _RT_HTINFO_STA_ENTRY{ + u8 bEnableHT; + + u8 bSupportCck; + + u16 AMSDU_MaxSize; + + u8 AMPDU_Factor; + u8 MPDU_Density; + + u8 HTHighestOperaRate; + + u8 bBw40MHz; + + u8 MimoPs; + + u8 McsRateSet[16]; + + +}RT_HTINFO_STA_ENTRY, *PRT_HTINFO_STA_ENTRY; + + + + + +//------------------------------------------------------------ +// The Data structure is used to keep HT related variable for "each AP" +// when card is configured as "STA mode" +//------------------------------------------------------------ + +typedef struct _BSS_HT{ + + u8 bdSupportHT; + + // HT related elements + u8 bdHTCapBuf[32]; + u16 bdHTCapLen; + u8 bdHTInfoBuf[32]; + u16 bdHTInfoLen; + + HT_SPEC_VER bdHTSpecVer; + //HT_CAPABILITY_ELE bdHTCapEle; + //HT_INFORMATION_ELE bdHTInfoEle; + + u8 bdRT2RTAggregation; + u8 bdRT2RTLongSlotTime; + u8 RT2RT_HT_Mode; + bool bdHT1R; +} __attribute__ ((packed)) BSS_HT, *PBSS_HT; + +typedef struct _MIMO_RSSI{ + u32 EnableAntenna; + u32 AntennaA; + u32 AntennaB; + u32 AntennaC; + u32 AntennaD; + u32 Average; +}MIMO_RSSI, *PMIMO_RSSI; + +typedef struct _MIMO_EVM{ + u32 EVM1; + u32 EVM2; +}MIMO_EVM, *PMIMO_EVM; + +typedef struct _FALSE_ALARM_STATISTICS{ + u32 Cnt_Parity_Fail; + u32 Cnt_Rate_Illegal; + u32 Cnt_Crc8_fail; + u32 Cnt_all; +}FALSE_ALARM_STATISTICS, *PFALSE_ALARM_STATISTICS; + + +extern u8 MCS_FILTER_ALL[16]; +extern u8 MCS_FILTER_1SS[16]; + +/* 2007/07/11 MH Modify the macro. Becaus STA may link with a N-AP. If we set + STA in A/B/G mode and AP is still in N mode. The macro will be wrong. We have + to add a macro to judge wireless mode. */ +#define PICK_RATE(_nLegacyRate, _nMcsRate) \ + (_nMcsRate==0)?(_nLegacyRate&0x7f):(_nMcsRate) +/* 2007/07/12 MH We only define legacy and HT wireless mode now. */ +#define LEGACY_WIRELESS_MODE IEEE_MODE_MASK + +#define CURRENT_RATE(WirelessMode, LegacyRate, HTRate) \ + ((WirelessMode & (LEGACY_WIRELESS_MODE))!=0)?\ + (LegacyRate):\ + (PICK_RATE(LegacyRate, HTRate)) + + + +// MCS Bw 40 {1~7, 12~15,32} +#define RATE_ADPT_1SS_MASK 0xFF +#define RATE_ADPT_2SS_MASK 0xF0 //Skip MCS8~11 because mcs7 > mcs6, 9, 10, 11. 2007.01.16 by Emily +#define RATE_ADPT_MCS32_MASK 0x01 + +#define IS_11N_MCS_RATE(rate) (rate&0x80) + +typedef enum _HT_AGGRE_SIZE{ + HT_AGG_SIZE_8K = 0, + HT_AGG_SIZE_16K = 1, + HT_AGG_SIZE_32K = 2, + HT_AGG_SIZE_64K = 3, +}HT_AGGRE_SIZE_E, *PHT_AGGRE_SIZE_E; + +/* Indicate different AP vendor for IOT issue */ +typedef enum _HT_IOT_PEER +{ + HT_IOT_PEER_UNKNOWN = 0, + HT_IOT_PEER_REALTEK = 1, + HT_IOT_PEER_REALTEK_92SE = 2, + HT_IOT_PEER_BROADCOM = 3, + HT_IOT_PEER_RALINK = 4, + HT_IOT_PEER_ATHEROS = 5, + HT_IOT_PEER_CISCO= 6, + HT_IOT_PEER_MARVELL=7, + HT_IOT_PEER_92U_SOFTAP = 8, + HT_IOT_PEER_SELF_SOFTAP = 9, + HT_IOT_PEER_MAX = 10, +}HT_IOT_PEER_E, *PHTIOT_PEER_E; + +// +// IOT Action for different AP +// +typedef enum _HT_IOT_ACTION{ + HT_IOT_ACT_TX_USE_AMSDU_4K = 0x00000001, + HT_IOT_ACT_TX_USE_AMSDU_8K = 0x00000002, + HT_IOT_ACT_DISABLE_MCS14 = 0x00000004, + HT_IOT_ACT_DISABLE_MCS15 = 0x00000008, + HT_IOT_ACT_DISABLE_ALL_2SS = 0x00000010, + HT_IOT_ACT_DISABLE_EDCA_TURBO = 0x00000020, + HT_IOT_ACT_MGNT_USE_CCK_6M = 0x00000040, + HT_IOT_ACT_CDD_FSYNC = 0x00000080, + HT_IOT_ACT_PURE_N_MODE = 0x00000100, + HT_IOT_ACT_FORCED_CTS2SELF = 0x00000200, + HT_IOT_ACT_FORCED_RTS = 0x00000400, + HT_IOT_ACT_AMSDU_ENABLE = 0x00000800, + HT_IOT_ACT_MID_HIGHPOWER = 0x00001000, + HT_IOT_ACT_REJECT_ADDBA_REQ = 0x00002000, + HT_IOT_ACT_ALLOW_PEER_AGG_ONE_PKT = 0x00004000, + HT_IOT_ACT_EDCA_BIAS_ON_RX = 0x00008000, + + HT_IOT_ACT_HYBRID_AGGREGATION = 0x00010000, + HT_IOT_ACT_DISABLE_SHORT_GI = 0x00020000, + HT_IOT_ACT_DISABLE_HIGH_POWER = 0x00040000, + HT_IOT_ACT_DISABLE_TX_40_MHZ = 0x00080000, + HT_IOT_ACT_TX_NO_AGGREGATION = 0x00100000, + HT_IOT_ACT_DISABLE_TX_2SS = 0x00200000, +}HT_IOT_ACTION_E, *PHT_IOT_ACTION_E; + +typedef enum _HT_IOT_RAFUNC{ + HT_IOT_RAFUNC_PEER_1R = 0x01, + HT_IOT_RAFUNC_TX_AMSDU = 0x02, + HT_IOT_RAFUNC_DISABLE_ALL = 0x80, +}HT_IOT_RAFUNC, *PHT_IOT_RAFUNC; + +typedef enum _RT_HT_CAP{ + RT_HT_CAP_USE_TURBO_AGGR = 0x01, + RT_HT_CAP_USE_LONG_PREAMBLE = 0x02, + RT_HT_CAP_USE_AMPDU = 0x04, + RT_HT_CAP_USE_WOW = 0x8, + RT_HT_CAP_USE_SOFTAP = 0x10, + RT_HT_CAP_USE_92SE = 0x20, +}RT_HT_CAPBILITY, *PRT_HT_CAPBILITY; + +#endif //_RTL819XU_HTTYPE_H_ + diff --git a/drivers/staging/rtl8192su/ieee80211/rtl819x_HTProc.c b/drivers/staging/rtl8192su/ieee80211/rtl819x_HTProc.c new file mode 100644 index 000000000000..f357085f6643 --- /dev/null +++ b/drivers/staging/rtl8192su/ieee80211/rtl819x_HTProc.c @@ -0,0 +1,2037 @@ + +//As this function is mainly ported from Windows driver, so leave the name little changed. If any confusion caused, tell me. Created by WB. 2008.05.08 +#include "ieee80211.h" +#include "rtl819x_HT.h" +u8 MCS_FILTER_ALL[16] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + +u8 MCS_FILTER_1SS[16] = {0xff, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + +u16 MCS_DATA_RATE[2][2][77] = + { { {13, 26, 39, 52, 78, 104, 117, 130, 26, 52, 78 ,104, 156, 208, 234, 260, + 39, 78, 117, 234, 312, 351, 390, 52, 104, 156, 208, 312, 416, 468, 520, + 0, 78, 104, 130, 117, 156, 195, 104, 130, 130, 156, 182, 182, 208, 156, 195, + 195, 234, 273, 273, 312, 130, 156, 181, 156, 181, 208, 234, 208, 234, 260, 260, + 286, 195, 234, 273, 234, 273, 312, 351, 312, 351, 390, 390, 429}, // Long GI, 20MHz + {14, 29, 43, 58, 87, 116, 130, 144, 29, 58, 87, 116, 173, 231, 260, 289, + 43, 87, 130, 173, 260, 347, 390, 433, 58, 116, 173, 231, 347, 462, 520, 578, + 0, 87, 116, 144, 130, 173, 217, 116, 144, 144, 173, 202, 202, 231, 173, 217, + 217, 260, 303, 303, 347, 144, 173, 202, 173, 202, 231, 260, 231, 260, 289, 289, + 318, 217, 260, 303, 260, 303, 347, 390, 347, 390, 433, 433, 477} }, // Short GI, 20MHz + { {27, 54, 81, 108, 162, 216, 243, 270, 54, 108, 162, 216, 324, 432, 486, 540, + 81, 162, 243, 324, 486, 648, 729, 810, 108, 216, 324, 432, 648, 864, 972, 1080, + 12, 162, 216, 270, 243, 324, 405, 216, 270, 270, 324, 378, 378, 432, 324, 405, + 405, 486, 567, 567, 648, 270, 324, 378, 324, 378, 432, 486, 432, 486, 540, 540, + 594, 405, 486, 567, 486, 567, 648, 729, 648, 729, 810, 810, 891}, // Long GI, 40MHz + {30, 60, 90, 120, 180, 240, 270, 300, 60, 120, 180, 240, 360, 480, 540, 600, + 90, 180, 270, 360, 540, 720, 810, 900, 120, 240, 360, 480, 720, 960, 1080, 1200, + 13, 180, 240, 300, 270, 360, 450, 240, 300, 300, 360, 420, 420, 480, 360, 450, + 450, 540, 630, 630, 720, 300, 360, 420, 360, 420, 480, 540, 480, 540, 600, 600, + 660, 450, 540, 630, 540, 630, 720, 810, 720, 810, 900, 900, 990} } // Short GI, 40MHz + }; + +static u8 UNKNOWN_BORADCOM[3] = {0x00, 0x14, 0xbf}; +static u8 LINKSYSWRT330_LINKSYSWRT300_BROADCOM[3] = {0x00, 0x1a, 0x70}; +static u8 LINKSYSWRT350_LINKSYSWRT150_BROADCOM[3] = {0x00, 0x1d, 0x7e}; +static u8 NETGEAR834Bv2_BROADCOM[3] = {0x00, 0x1b, 0x2f}; +static u8 BELKINF5D8233V1_RALINK[3] = {0x00, 0x17, 0x3f}; //cosa 03202008 +static u8 BELKINF5D82334V3_RALINK[3] = {0x00, 0x1c, 0xdf}; +static u8 PCI_RALINK[3] = {0x00, 0x90, 0xcc}; +static u8 EDIMAX_RALINK[3] = {0x00, 0x0e, 0x2e}; +static u8 AIRLINK_RALINK[3] = {0x00, 0x18, 0x02}; +static u8 DLINK_ATHEROS_1[3] = {0x00, 0x1c, 0xf0}; +static u8 DLINK_ATHEROS_2[3] = {0x00, 0x21, 0x91}; +static u8 CISCO_BROADCOM[3] = {0x00, 0x17, 0x94}; +static u8 LINKSYS_MARVELL_4400N[3] = {0x00, 0x14, 0xa4}; +// 2008/04/01 MH For Cisco G mode RX TP We need to change FW duration. Shoud we put the +// code in other place?? +//static u8 WIFI_CISCO_G_AP[3] = {0x00, 0x40, 0x96}; +/******************************************************************************************************************** + *function: This function update default settings in pHTInfo structure + * input: PRT_HIGH_THROUGHPUT pHTInfo + * output: none + * return: none + * notice: These value need be modified if any changes. + * *****************************************************************************************************************/ +void HTUpdateDefaultSetting(struct ieee80211_device* ieee) +{ + PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; + //const typeof( ((struct ieee80211_device *)0)->pHTInfo ) *__mptr = &pHTInfo; + + //printk("pHTinfo:%p, &pHTinfo:%p, mptr:%p, offsetof:%x\n", pHTInfo, &pHTInfo, __mptr, offsetof(struct ieee80211_device, pHTInfo)); + //printk("===>ieee:%p,\n", ieee); + // ShortGI support + pHTInfo->bRegShortGI20MHz= 1; + pHTInfo->bRegShortGI40MHz= 1; + + // 40MHz channel support + pHTInfo->bRegBW40MHz = 1; + + // CCK rate support in 40MHz channel + if(pHTInfo->bRegBW40MHz) + pHTInfo->bRegSuppCCK = 1; + else + pHTInfo->bRegSuppCCK = true; + + // AMSDU related + pHTInfo->nAMSDU_MaxSize = 7935UL; + pHTInfo->bAMSDU_Support = 0; + + // AMPDU related + pHTInfo->bAMPDUEnable = 1; //YJ,test,090311 + pHTInfo->AMPDU_Factor = 2; //// 0: 2n13(8K), 1:2n14(16K), 2:2n15(32K), 3:2n16(64k) + pHTInfo->MPDU_Density = 0;// 0: No restriction, 1: 1/8usec, 2: 1/4usec, 3: 1/2usec, 4: 1usec, 5: 2usec, 6: 4usec, 7:8usec + + // MIMO Power Save + pHTInfo->SelfMimoPs = 3;// 0: Static Mimo Ps, 1: Dynamic Mimo Ps, 3: No Limitation, 2: Reserved(Set to 3 automatically.) + if(pHTInfo->SelfMimoPs == 2) + pHTInfo->SelfMimoPs = 3; + // 8190 only. Assign rate operation mode to firmware + ieee->bTxDisableRateFallBack = 0; + ieee->bTxUseDriverAssingedRate = 0; + +#ifdef TO_DO_LIST + // 8190 only. Assign duration operation mode to firmware + pMgntInfo->bTxEnableFwCalcDur = (BOOLEAN)pNdisCommon->bRegTxEnableFwCalcDur; +#endif + // 8190 only, Realtek proprietary aggregation mode + // Set MPDUDensity=2, 1: Set MPDUDensity=2(32k) for Realtek AP and set MPDUDensity=0(8k) for others + pHTInfo->bRegRT2RTAggregation = 1;//0: Set MPDUDensity=2, 1: Set MPDUDensity=2(32k) for Realtek AP and set MPDUDensity=0(8k) for others + + // For Rx Reorder Control + pHTInfo->bRegRxReorderEnable = 1;//YJ,test,090311 + pHTInfo->RxReorderWinSize = 64; + pHTInfo->RxReorderPendingTime = 30; + +#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE + pHTInfo->UsbTxAggrNum = 4; +#endif +#ifdef USB_RX_AGGREGATION_SUPPORT +#ifdef RTL8192SU + pHTInfo->UsbRxFwAggrEn = 1; + pHTInfo->UsbRxFwAggrPageNum = 16; + pHTInfo->UsbRxFwAggrPacketNum = 8; + pHTInfo->UsbRxFwAggrTimeout = 4; ////usb rx FW aggregation timeout threshold.It's in units of 64us + // For page size of receive packet buffer. + pHTInfo->UsbRxPageSize= 128; +#else + pHTInfo->UsbRxFwAggrEn = 1; + pHTInfo->UsbRxFwAggrPageNum = 24; + pHTInfo->UsbRxFwAggrPacketNum = 8; + pHTInfo->UsbRxFwAggrTimeout = 16; ////usb rx FW aggregation timeout threshold.It's in units of 64us +#endif +#endif + + +} +/******************************************************************************************************************** + *function: This function print out each field on HT capability IE mainly from (Beacon/ProbeRsp/AssocReq) + * input: u8* CapIE //Capability IE to be printed out + * u8* TitleString //mainly print out caller function + * output: none + * return: none + * notice: Driver should not print out this message by default. + * *****************************************************************************************************************/ +void HTDebugHTCapability(u8* CapIE, u8* TitleString ) +{ + + static u8 EWC11NHTCap[] = {0x00, 0x90, 0x4c, 0x33}; // For 11n EWC definition, 2007.07.17, by Emily + PHT_CAPABILITY_ELE pCapELE; + + if(!memcmp(CapIE, EWC11NHTCap, sizeof(EWC11NHTCap))) + { + //EWC IE + IEEE80211_DEBUG(IEEE80211_DL_HT, "EWC IE in %s()\n", __FUNCTION__); + pCapELE = (PHT_CAPABILITY_ELE)(&CapIE[4]); + }else + pCapELE = (PHT_CAPABILITY_ELE)(&CapIE[0]); + + IEEE80211_DEBUG(IEEE80211_DL_HT, "<Log HT Capability>. Called by %s\n", TitleString ); + + IEEE80211_DEBUG(IEEE80211_DL_HT, "\tSupported Channel Width = %s\n", (pCapELE->ChlWidth)?"20MHz": "20/40MHz"); + IEEE80211_DEBUG(IEEE80211_DL_HT, "\tSupport Short GI for 20M = %s\n", (pCapELE->ShortGI20Mhz)?"YES": "NO"); + IEEE80211_DEBUG(IEEE80211_DL_HT, "\tSupport Short GI for 40M = %s\n", (pCapELE->ShortGI40Mhz)?"YES": "NO"); + IEEE80211_DEBUG(IEEE80211_DL_HT, "\tSupport TX STBC = %s\n", (pCapELE->TxSTBC)?"YES": "NO"); + IEEE80211_DEBUG(IEEE80211_DL_HT, "\tMax AMSDU Size = %s\n", (pCapELE->MaxAMSDUSize)?"3839": "7935"); + IEEE80211_DEBUG(IEEE80211_DL_HT, "\tSupport CCK in 20/40 mode = %s\n", (pCapELE->DssCCk)?"YES": "NO"); + IEEE80211_DEBUG(IEEE80211_DL_HT, "\tMax AMPDU Factor = %d\n", pCapELE->MaxRxAMPDUFactor); + IEEE80211_DEBUG(IEEE80211_DL_HT, "\tMPDU Density = %d\n", pCapELE->MPDUDensity); + IEEE80211_DEBUG(IEEE80211_DL_HT, "\tMCS Rate Set = [%x][%x][%x][%x][%x]\n", pCapELE->MCS[0],\ + pCapELE->MCS[1], pCapELE->MCS[2], pCapELE->MCS[3], pCapELE->MCS[4]); + return; + +} +/******************************************************************************************************************** + *function: This function print out each field on HT Information IE mainly from (Beacon/ProbeRsp) + * input: u8* InfoIE //Capability IE to be printed out + * u8* TitleString //mainly print out caller function + * output: none + * return: none + * notice: Driver should not print out this message by default. + * *****************************************************************************************************************/ +void HTDebugHTInfo(u8* InfoIE, u8* TitleString) +{ + + static u8 EWC11NHTInfo[] = {0x00, 0x90, 0x4c, 0x34}; // For 11n EWC definition, 2007.07.17, by Emily + PHT_INFORMATION_ELE pHTInfoEle; + + if(!memcmp(InfoIE, EWC11NHTInfo, sizeof(EWC11NHTInfo))) + { + // Not EWC IE + IEEE80211_DEBUG(IEEE80211_DL_HT, "EWC IE in %s()\n", __FUNCTION__); + pHTInfoEle = (PHT_INFORMATION_ELE)(&InfoIE[4]); + }else + pHTInfoEle = (PHT_INFORMATION_ELE)(&InfoIE[0]); + + + IEEE80211_DEBUG(IEEE80211_DL_HT, "<Log HT Information Element>. Called by %s\n", TitleString); + + IEEE80211_DEBUG(IEEE80211_DL_HT, "\tPrimary channel = %d\n", pHTInfoEle->ControlChl); + IEEE80211_DEBUG(IEEE80211_DL_HT, "\tSenondary channel ="); + switch(pHTInfoEle->ExtChlOffset) + { + case 0: + IEEE80211_DEBUG(IEEE80211_DL_HT, "Not Present\n"); + break; + case 1: + IEEE80211_DEBUG(IEEE80211_DL_HT, "Upper channel\n"); + break; + case 2: + IEEE80211_DEBUG(IEEE80211_DL_HT, "Reserved. Eooro!!!\n"); + break; + case 3: + IEEE80211_DEBUG(IEEE80211_DL_HT, "Lower Channel\n"); + break; + } + IEEE80211_DEBUG(IEEE80211_DL_HT, "\tRecommended channel width = %s\n", (pHTInfoEle->RecommemdedTxWidth)?"20Mhz": "40Mhz"); + + IEEE80211_DEBUG(IEEE80211_DL_HT, "\tOperation mode for protection = "); + switch(pHTInfoEle->OptMode) + { + case 0: + IEEE80211_DEBUG(IEEE80211_DL_HT, "No Protection\n"); + break; + case 1: + IEEE80211_DEBUG(IEEE80211_DL_HT, "HT non-member protection mode\n"); + break; + case 2: + IEEE80211_DEBUG(IEEE80211_DL_HT, "Suggest to open protection\n"); + break; + case 3: + IEEE80211_DEBUG(IEEE80211_DL_HT, "HT mixed mode\n"); + break; + } + + IEEE80211_DEBUG(IEEE80211_DL_HT, "\tBasic MCS Rate Set = [%x][%x][%x][%x][%x]\n", pHTInfoEle->BasicMSC[0],\ + pHTInfoEle->BasicMSC[1], pHTInfoEle->BasicMSC[2], pHTInfoEle->BasicMSC[3], pHTInfoEle->BasicMSC[4]); + return; +} + +/* +* Return: true if station in half n mode and AP supports 40 bw +*/ +bool IsHTHalfNmode40Bandwidth(struct ieee80211_device* ieee) +{ + bool retValue = false; + PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; + + if(pHTInfo->bCurrentHTSupport == false ) // wireless is n mode + retValue = false; + else if(pHTInfo->bRegBW40MHz == false) // station supports 40 bw + retValue = false; + else if(!ieee->GetHalfNmodeSupportByAPsHandler(ieee->dev)) // station in half n mode + retValue = false; + else if(((PHT_CAPABILITY_ELE)(pHTInfo->PeerHTCapBuf))->ChlWidth) // ap support 40 bw + retValue = true; + else + retValue = false; + + return retValue; +} + +bool IsHTHalfNmodeSGI(struct ieee80211_device* ieee, bool is40MHz) +{ + bool retValue = false; + PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; + + if(pHTInfo->bCurrentHTSupport == false ) // wireless is n mode + retValue = false; + else if(!ieee->GetHalfNmodeSupportByAPsHandler(ieee->dev)) // station in half n mode + retValue = false; + else if(is40MHz) // ap support 40 bw + { + if(((PHT_CAPABILITY_ELE)(pHTInfo->PeerHTCapBuf))->ShortGI40Mhz) // ap support 40 bw short GI + retValue = true; + else + retValue = false; + } + else + { + if(((PHT_CAPABILITY_ELE)(pHTInfo->PeerHTCapBuf))->ShortGI20Mhz) // ap support 40 bw short GI + retValue = true; + else + retValue = false; + } + + return retValue; +} + +u16 HTHalfMcsToDataRate(struct ieee80211_device* ieee, u8 nMcsRate) +{ + + u8 is40MHz; + u8 isShortGI; + + is40MHz = (IsHTHalfNmode40Bandwidth(ieee))?1:0; + isShortGI = (IsHTHalfNmodeSGI(ieee, is40MHz))? 1:0; + + return MCS_DATA_RATE[is40MHz][isShortGI][(nMcsRate&0x7f)]; +} + + +u16 HTMcsToDataRate( struct ieee80211_device* ieee, u8 nMcsRate) +{ + PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; + + u8 is40MHz = (pHTInfo->bCurBW40MHz)?1:0; + u8 isShortGI = (pHTInfo->bCurBW40MHz)? + ((pHTInfo->bCurShortGI40MHz)?1:0): + ((pHTInfo->bCurShortGI20MHz)?1:0); + return MCS_DATA_RATE[is40MHz][isShortGI][(nMcsRate&0x7f)]; +} + +/******************************************************************************************************************** + *function: This function returns current datarate. + * input: struct ieee80211_device* ieee + * u8 nDataRate + * output: none + * return: tx rate + * notice: quite unsure about how to use this function //wb + * *****************************************************************************************************************/ +u16 TxCountToDataRate( struct ieee80211_device* ieee, u8 nDataRate) +{ + //PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; + u16 CCKOFDMRate[12] = {0x02 , 0x04 , 0x0b , 0x16 , 0x0c , 0x12 , 0x18 , 0x24 , 0x30 , 0x48 , 0x60 , 0x6c}; + u8 is40MHz = 0; + u8 isShortGI = 0; + + if(nDataRate < 12) + { + return CCKOFDMRate[nDataRate]; + } + else + { + if (nDataRate >= 0x10 && nDataRate <= 0x1f)//if(nDataRate > 11 && nDataRate < 28 ) + { + is40MHz = 0; + isShortGI = 0; + + // nDataRate = nDataRate - 12; + } + else if(nDataRate >=0x20 && nDataRate <= 0x2f ) //(27, 44) + { + is40MHz = 1; + isShortGI = 0; + + //nDataRate = nDataRate - 28; + } + else if(nDataRate >= 0x30 && nDataRate <= 0x3f ) //(43, 60) + { + is40MHz = 0; + isShortGI = 1; + + //nDataRate = nDataRate - 44; + } + else if(nDataRate >= 0x40 && nDataRate <= 0x4f ) //(59, 76) + { + is40MHz = 1; + isShortGI = 1; + + //nDataRate = nDataRate - 60; + } + return MCS_DATA_RATE[is40MHz][isShortGI][nDataRate&0xf]; + } +} + + + +bool IsHTHalfNmodeAPs(struct ieee80211_device* ieee) +{ + bool retValue = false; + struct ieee80211_network* net = &ieee->current_network; +#if 0 + if(pMgntInfo->bHalfNMode == false) + retValue = false; + else +#endif + if((memcmp(net->bssid, BELKINF5D8233V1_RALINK, 3)==0) || + (memcmp(net->bssid, BELKINF5D82334V3_RALINK, 3)==0) || + (memcmp(net->bssid, PCI_RALINK, 3)==0) || + (memcmp(net->bssid, EDIMAX_RALINK, 3)==0) || + (memcmp(net->bssid, AIRLINK_RALINK, 3)==0) || + (net->ralink_cap_exist)) + retValue = true; + else if((memcmp(net->bssid, UNKNOWN_BORADCOM, 3)==0) || + (memcmp(net->bssid, LINKSYSWRT330_LINKSYSWRT300_BROADCOM, 3)==0)|| + (memcmp(net->bssid, LINKSYSWRT350_LINKSYSWRT150_BROADCOM, 3)==0)|| + (memcmp(net->bssid, NETGEAR834Bv2_BROADCOM, 3)==0) || + (net->broadcom_cap_exist)) + retValue = true; + else if(net->bssht.bdRT2RTAggregation) + retValue = true; + else + retValue = false; + + return retValue; +} + +/******************************************************************************************************************** + *function: This function returns peer IOT. + * input: struct ieee80211_device* ieee + * output: none + * return: + * notice: + * *****************************************************************************************************************/ +void HTIOTPeerDetermine(struct ieee80211_device* ieee) +{ + PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; + struct ieee80211_network* net = &ieee->current_network; + //FIXME: need to decide 92U_SOFTAP //LZM,090320 + if(net->bssht.bdRT2RTAggregation){ + pHTInfo->IOTPeer = HT_IOT_PEER_REALTEK; + if(net->bssht.RT2RT_HT_Mode & RT_HT_CAP_USE_92SE){ + pHTInfo->IOTPeer = HT_IOT_PEER_REALTEK_92SE; + } + } + else if(net->broadcom_cap_exist) + pHTInfo->IOTPeer = HT_IOT_PEER_BROADCOM; + else if((memcmp(net->bssid, UNKNOWN_BORADCOM, 3)==0) || + (memcmp(net->bssid, LINKSYSWRT330_LINKSYSWRT300_BROADCOM, 3)==0)|| + (memcmp(net->bssid, LINKSYSWRT350_LINKSYSWRT150_BROADCOM, 3)==0)|| + (memcmp(net->bssid, NETGEAR834Bv2_BROADCOM, 3)==0) ) + pHTInfo->IOTPeer = HT_IOT_PEER_BROADCOM; + else if((memcmp(net->bssid, BELKINF5D8233V1_RALINK, 3)==0) || + (memcmp(net->bssid, BELKINF5D82334V3_RALINK, 3)==0) || + (memcmp(net->bssid, PCI_RALINK, 3)==0) || + (memcmp(net->bssid, EDIMAX_RALINK, 3)==0) || + (memcmp(net->bssid, AIRLINK_RALINK, 3)==0) || + net->ralink_cap_exist) + pHTInfo->IOTPeer = HT_IOT_PEER_RALINK; + else if((net->atheros_cap_exist )|| + (memcmp(net->bssid, DLINK_ATHEROS_1, 3) == 0)|| + (memcmp(net->bssid, DLINK_ATHEROS_2, 3) == 0)) + pHTInfo->IOTPeer = HT_IOT_PEER_ATHEROS; + else if(memcmp(net->bssid, CISCO_BROADCOM, 3)==0) + pHTInfo->IOTPeer = HT_IOT_PEER_CISCO; + else if ((memcmp(net->bssid, LINKSYS_MARVELL_4400N, 3) == 0) || + net->marvell_cap_exist) + pHTInfo->IOTPeer = HT_IOT_PEER_MARVELL; + else + pHTInfo->IOTPeer = HT_IOT_PEER_UNKNOWN; + + IEEE80211_DEBUG(IEEE80211_DL_IOT, "Joseph debug!! IOTPEER: %x\n", pHTInfo->IOTPeer); +} +/******************************************************************************************************************** + *function: Check whether driver should declare received rate up to MCS13 only since some chipset is not good + * at receiving MCS14~15 frame from some AP. + * input: struct ieee80211_device* ieee + * u8 * PeerMacAddr + * output: none + * return: return 1 if driver should declare MCS13 only(otherwise return 0) + * *****************************************************************************************************************/ +u8 HTIOTActIsDisableMCS14(struct ieee80211_device* ieee, u8* PeerMacAddr) +{ + u8 ret = 0; +#if 0 + // Apply for 819u only +#if (HAL_CODE_BASE==RTL8192 && DEV_BUS_TYPE==USB_INTERFACE) + if((memcmp(PeerMacAddr, UNKNOWN_BORADCOM, 3)==0) || + (memcmp(PeerMacAddr, LINKSYSWRT330_LINKSYSWRT300_BROADCOM, 3)==0) + ) + { + ret = 1; + } + + + if(pHTInfo->bCurrentRT2RTAggregation) + { + // The parameter of pHTInfo->bCurrentRT2RTAggregation must be decided previously + ret = 1; + } +#endif +#endif + return ret; + } + + +/** +* Function: HTIOTActIsDisableMCS15 +* +* Overview: Check whether driver should declare capability of receving MCS15 +* +* Input: +* PADAPTER Adapter, +* +* Output: None +* Return: true if driver should disable MCS15 +* 2008.04.15 Emily +*/ +bool HTIOTActIsDisableMCS15(struct ieee80211_device* ieee) +{ + bool retValue = false; + +#ifdef TODO + // Apply for 819u only +#if (HAL_CODE_BASE==RTL8192) + +#if (DEV_BUS_TYPE == USB_INTERFACE) + // Alway disable MCS15 by Jerry Chang's request.by Emily, 2008.04.15 + retValue = true; +#elif (DEV_BUS_TYPE == PCI_INTERFACE) + // Enable MCS15 if the peer is Cisco AP. by Emily, 2008.05.12 +// if(pBssDesc->bCiscoCapExist) +// retValue = false; +// else + retValue = false; +#endif +#endif +#endif + // Jerry Chang suggest that 8190 1x2 does not need to disable MCS15 + + return retValue; +} + +/** +* Function: HTIOTActIsDisableMCSTwoSpatialStream +* +* Overview: Check whether driver should declare capability of receving All 2 ss packets +* +* Input: +* PADAPTER Adapter, +* +* Output: None +* Return: true if driver should disable all two spatial stream packet +* 2008.04.21 Emily +*/ +bool HTIOTActIsDisableMCSTwoSpatialStream(struct ieee80211_device* ieee) +{ + bool retValue = false; +#ifdef TODO + // Apply for 819u only +//#if (HAL_CODE_BASE==RTL8192) + + //This rule only apply to Belkin(Ralink) AP + if(IS_UNDER_11N_AES_MODE(Adapter)) + { + if((PlatformCompareMemory(PeerMacAddr, BELKINF5D8233V1_RALINK, 3)==0) || + (PlatformCompareMemory(PeerMacAddr, PCI_RALINK, 3)==0) || + (PlatformCompareMemory(PeerMacAddr, EDIMAX_RALINK, 3)==0)) + { + //Set True to disable this function. Disable by default, Emily, 2008.04.23 + retValue = false; + } + } + +//#endif +#endif +#if 1 +#if (defined(RTL8192SE) || (defined(RTL8192SU))) + PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; + if(ieee->is_ap_in_wep_tkip && ieee->is_ap_in_wep_tkip(ieee->dev)) + { + if( (pHTInfo->IOTPeer != HT_IOT_PEER_ATHEROS) && + (pHTInfo->IOTPeer != HT_IOT_PEER_UNKNOWN) && + (pHTInfo->IOTPeer != HT_IOT_PEER_MARVELL) ) + retValue = true; + } +#endif +#endif + return retValue; +} + +/******************************************************************************************************************** + *function: Check whether driver should disable EDCA turbo mode + * input: struct ieee80211_device* ieee + * u8* PeerMacAddr + * output: none + * return: return 1 if driver should disable EDCA turbo mode(otherwise return 0) + * *****************************************************************************************************************/ +u8 HTIOTActIsDisableEDCATurbo(struct ieee80211_device* ieee, u8* PeerMacAddr) +{ + u8 retValue = false; // default enable EDCA Turbo mode. + // Set specific EDCA parameter for different AP in DM handler. + + return retValue; +#if 0 + if((memcmp(PeerMacAddr, UNKNOWN_BORADCOM, 3)==0)|| + (memcmp(PeerMacAddr, LINKSYSWRT330_LINKSYSWRT300_BROADCOM, 3)==0)|| + (memcmp(PeerMacAddr, LINKSYSWRT350_LINKSYSWRT150_BROADCOM, 3)==0)|| + (memcmp(PeerMacAddr, NETGEAR834Bv2_BROADCOM, 3)==0)) + + { + retValue = 1; //Linksys disable EDCA turbo mode + } + + return retValue; +#endif +} + +/******************************************************************************************************************** + *function: Check whether we need to use OFDM to sned MGNT frame for broadcom AP + * input: struct ieee80211_network *network //current network we live + * output: none + * return: return 1 if true + * *****************************************************************************************************************/ +u8 HTIOTActIsMgntUseCCK6M(struct ieee80211_network *network) +{ + u8 retValue = 0; + + // 2008/01/25 MH Judeg if we need to use OFDM to sned MGNT frame for broadcom AP. + // 2008/01/28 MH We must prevent that we select null bssid to link. + + if(network->broadcom_cap_exist) + { + retValue = 1; + } + + return retValue; +} + +u8 HTIOTActIsForcedCTS2Self(struct ieee80211_network *network) +{ + u8 retValue = 0; + + if(network->marvell_cap_exist) + { + retValue = 1; + } + + return retValue; +} + +u8 HTIOTActIsForcedRTSCTS(struct ieee80211_device *ieee, struct ieee80211_network *network) +{ + u8 retValue = 0; + printk("============>%s(), %d\n", __FUNCTION__, network->realtek_cap_exit); + // Force protection +#if defined(RTL8192SE) || defined(RTL8192SU) + if(ieee->pHTInfo->bCurrentHTSupport) + { + //if(!network->realtek_cap_exit) + if((ieee->pHTInfo->IOTPeer != HT_IOT_PEER_REALTEK)&& + (ieee->pHTInfo->IOTPeer != HT_IOT_PEER_REALTEK_92SE)) + { + if((ieee->pHTInfo->IOTAction & HT_IOT_ACT_TX_NO_AGGREGATION) == 0) + retValue = 1; + } + } +#endif + return retValue; +} + +u8 +HTIOTActIsForcedAMSDU8K(struct ieee80211_device *ieee, struct ieee80211_network *network) +{ + u8 retValue = 0; + + return retValue; +} + +u8 HTIOTActIsCCDFsync(u8* PeerMacAddr) +{ + u8 retValue = 0; +#ifndef RTL8192SE + if( (memcmp(PeerMacAddr, UNKNOWN_BORADCOM, 3)==0) || + (memcmp(PeerMacAddr, LINKSYSWRT330_LINKSYSWRT300_BROADCOM, 3)==0) || + (memcmp(PeerMacAddr, LINKSYSWRT350_LINKSYSWRT150_BROADCOM, 3) ==0)) + { + retValue = 1; + } +#endif + return retValue; +} + +/* + * 819xS single chip b-cut series cannot handle BAR + */ +u8 +HTIOCActRejcectADDBARequest(struct ieee80211_network *network) +{ + u8 retValue = 0; + //if(IS_HARDWARE_TYPE_8192SE(Adapter) || + // IS_HARDWARE_TYPE_8192SU(Adapter) + //) +#if (defined RTL8192SE || defined RTL8192SU) + { + // Do not reject ADDBA REQ because some of the AP may + // keep on sending ADDBA REQ qhich cause DHCP fail or ping loss! + // by HPFan, 2008/12/30 + + //if(pBssDesc->Vender == HT_IOT_PEER_MARVELL) + // return FALSE; + + } +#endif + + return retValue; + +} + +/* + * EDCA parameters bias on downlink + */ + u8 + HTIOTActIsEDCABiasRx(struct ieee80211_device* ieee,struct ieee80211_network *network) +{ + u8 retValue = 0; + //if(IS_HARDWARE_TYPE_8192SU(Adapter)) +#ifdef RTL8192SU + PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; + { +//#if UNDER_VISTA +// if(pBssDesc->Vender==HT_IOT_PEER_ATHEROS || +// pBssDesc->Vender==HT_IOT_PEER_RALINK) +//#else + if(pHTInfo->IOTPeer==HT_IOT_PEER_ATHEROS || + pHTInfo->IOTPeer==HT_IOT_PEER_BROADCOM || + pHTInfo->IOTPeer==HT_IOT_PEER_RALINK) +//#endif + return 1; + + } +#endif + return retValue; +} + +u8 +HTIOTActDisableShortGI(struct ieee80211_device* ieee,struct ieee80211_network *network) +{ + u8 retValue = 0; + PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; + + if(pHTInfo->IOTPeer==HT_IOT_PEER_RALINK) + { + if(network->bssht.bdHT1R) + retValue = 1; + } + + return retValue; +} + +u8 +HTIOTActDisableHighPower(struct ieee80211_device* ieee,struct ieee80211_network *network) +{ + u8 retValue = 0; + PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; + + if(pHTInfo->IOTPeer==HT_IOT_PEER_RALINK) + { + if(network->bssht.bdHT1R) + retValue = 1; + } + + return retValue; +} + +void +HTIOTActDetermineRaFunc(struct ieee80211_device* ieee, bool bPeerRx2ss) +{ + PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; + pHTInfo->IOTRaFunc &= HT_IOT_RAFUNC_DISABLE_ALL; + + if(pHTInfo->IOTPeer == HT_IOT_PEER_RALINK && !bPeerRx2ss) + pHTInfo->IOTRaFunc |= HT_IOT_RAFUNC_PEER_1R; + + if(pHTInfo->IOTAction & HT_IOT_ACT_AMSDU_ENABLE) + pHTInfo->IOTRaFunc |= HT_IOT_RAFUNC_TX_AMSDU; + + printk("!!!!!!!!!!!!!!!!!!!!!!!!!!!IOTRaFunc = %8.8x\n", pHTInfo->IOTRaFunc); +} + + +u8 +HTIOTActIsDisableTx40MHz(struct ieee80211_device* ieee,struct ieee80211_network *network) +{ + u8 retValue = 0; + +#if (defined RTL8192SU || defined RTL8192SE) + PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; + if( (KEY_TYPE_WEP104 == ieee->pairwise_key_type) || + (KEY_TYPE_WEP40 == ieee->pairwise_key_type) || + (KEY_TYPE_WEP104 == ieee->group_key_type) || + (KEY_TYPE_WEP40 == ieee->group_key_type) || + (KEY_TYPE_TKIP == ieee->pairwise_key_type) ) + { + if((pHTInfo->IOTPeer==HT_IOT_PEER_REALTEK) && (network->bssht.bdSupportHT)) + retValue = 1; + } +#endif + + return retValue; +} + +u8 +HTIOTActIsTxNoAggregation(struct ieee80211_device* ieee,struct ieee80211_network *network) +{ + u8 retValue = 0; + +#if (defined RTL8192SU || defined RTL8192SE) + PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; + if( (KEY_TYPE_WEP104 == ieee->pairwise_key_type) || + (KEY_TYPE_WEP40 == ieee->pairwise_key_type) || + (KEY_TYPE_WEP104 == ieee->group_key_type) || + (KEY_TYPE_WEP40 == ieee->group_key_type) || + (KEY_TYPE_TKIP == ieee->pairwise_key_type) ) + { + if(pHTInfo->IOTPeer==HT_IOT_PEER_REALTEK || + pHTInfo->IOTPeer==HT_IOT_PEER_UNKNOWN) + retValue = 1; + } +#endif + + return retValue; +} + + +u8 +HTIOTActIsDisableTx2SS(struct ieee80211_device* ieee,struct ieee80211_network *network) +{ + u8 retValue = 0; + +#if (defined RTL8192SU || defined RTL8192SE) + PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; + if( (KEY_TYPE_WEP104 == ieee->pairwise_key_type) || + (KEY_TYPE_WEP40 == ieee->pairwise_key_type) || + (KEY_TYPE_WEP104 == ieee->group_key_type) || + (KEY_TYPE_WEP40 == ieee->group_key_type) || + (KEY_TYPE_TKIP == ieee->pairwise_key_type) ) + { + if((pHTInfo->IOTPeer==HT_IOT_PEER_REALTEK) && (network->bssht.bdSupportHT)) + retValue = 1; + } +#endif + + return retValue; +} + + +bool HTIOCActAllowPeerAggOnePacket(struct ieee80211_device* ieee,struct ieee80211_network *network) +{ + bool retValue = false; +#if defined(RTL8192SE) || defined(RTL8192SU) + PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; + { + if(pHTInfo->IOTPeer == HT_IOT_PEER_MARVELL) + return true; + + } +#endif + return retValue; +} + +void HTResetIOTSetting( + PRT_HIGH_THROUGHPUT pHTInfo +) +{ + pHTInfo->IOTAction = 0; + pHTInfo->IOTPeer = HT_IOT_PEER_UNKNOWN; + pHTInfo->IOTRaFunc = 0; +} + + +/******************************************************************************************************************** + *function: Construct Capablility Element in Beacon... if HTEnable is turned on + * input: struct ieee80211_device* ieee + * u8* posHTCap //pointer to store Capability Ele + * u8* len //store length of CE + * u8 IsEncrypt //whether encrypt, needed further + * output: none + * return: none + * notice: posHTCap can't be null and should be initialized before. + * *****************************************************************************************************************/ +void HTConstructCapabilityElement(struct ieee80211_device* ieee, u8* posHTCap, u8* len, u8 IsEncrypt) +{ + PRT_HIGH_THROUGHPUT pHT = ieee->pHTInfo; + PHT_CAPABILITY_ELE pCapELE = NULL; + //u8 bIsDeclareMCS13; + + if ((posHTCap == NULL) || (pHT == NULL)) + { + IEEE80211_DEBUG(IEEE80211_DL_ERR, "posHTCap or pHTInfo can't be null in HTConstructCapabilityElement()\n"); + return; + } + memset(posHTCap, 0, *len); + if(pHT->ePeerHTSpecVer == HT_SPEC_VER_EWC) + { + u8 EWC11NHTCap[] = {0x00, 0x90, 0x4c, 0x33}; // For 11n EWC definition, 2007.07.17, by Emily + memcpy(posHTCap, EWC11NHTCap, sizeof(EWC11NHTCap)); + pCapELE = (PHT_CAPABILITY_ELE)&(posHTCap[4]); + }else + { + pCapELE = (PHT_CAPABILITY_ELE)posHTCap; + } + + + //HT capability info + pCapELE->AdvCoding = 0; // This feature is not supported now!! + if(ieee->GetHalfNmodeSupportByAPsHandler(ieee->dev)) + { + pCapELE->ChlWidth = 0; + } + else + { + pCapELE->ChlWidth = (pHT->bRegBW40MHz?1:0); + } + +// pCapELE->ChlWidth = (pHT->bRegBW40MHz?1:0); + pCapELE->MimoPwrSave = pHT->SelfMimoPs; + pCapELE->GreenField = 0; // This feature is not supported now!! + pCapELE->ShortGI20Mhz = 1; // We can receive Short GI!! + pCapELE->ShortGI40Mhz = 1; // We can receive Short GI!! + //DbgPrint("TX HT cap/info ele BW=%d SG20=%d SG40=%d\n\r", + //pCapELE->ChlWidth, pCapELE->ShortGI20Mhz, pCapELE->ShortGI40Mhz); + pCapELE->TxSTBC = 1; + pCapELE->RxSTBC = 0; + pCapELE->DelayBA = 0; // Do not support now!! + pCapELE->MaxAMSDUSize = (MAX_RECEIVE_BUFFER_SIZE>=7935)?1:0; + pCapELE->DssCCk = ((pHT->bRegBW40MHz)?(pHT->bRegSuppCCK?1:0):0); + pCapELE->PSMP = 0; // Do not support now!! + pCapELE->LSigTxopProtect = 0; // Do not support now!! + + + //MAC HT parameters info + // TODO: Nedd to take care of this part + IEEE80211_DEBUG(IEEE80211_DL_HT, "TX HT cap/info ele BW=%d MaxAMSDUSize:%d DssCCk:%d\n", pCapELE->ChlWidth, pCapELE->MaxAMSDUSize, pCapELE->DssCCk); + + if( IsEncrypt) + { + pCapELE->MPDUDensity = 7; // 8us + pCapELE->MaxRxAMPDUFactor = 2; // 2 is for 32 K and 3 is 64K + } + else + { + pCapELE->MaxRxAMPDUFactor = 3; // 2 is for 32 K and 3 is 64K + pCapELE->MPDUDensity = 0; // no density + } + + //Supported MCS set + memcpy(pCapELE->MCS, ieee->Regdot11HTOperationalRateSet, 16); + if(pHT->IOTAction & HT_IOT_ACT_DISABLE_MCS15) + pCapELE->MCS[1] &= 0x7f; + + if(pHT->IOTAction & HT_IOT_ACT_DISABLE_MCS14) + pCapELE->MCS[1] &= 0xbf; + + if(pHT->IOTAction & HT_IOT_ACT_DISABLE_ALL_2SS) + pCapELE->MCS[1] &= 0x00; + + // 2008.06.12 + // For RTL819X, if pairwisekey = wep/tkip, ap is ralink, we support only MCS0~7. + if(ieee->GetHalfNmodeSupportByAPsHandler(ieee->dev)) + { + int i; + for(i = 1; i< 16; i++) + pCapELE->MCS[i] = 0; + } + + //Extended HT Capability Info + memset(&pCapELE->ExtHTCapInfo, 0, 2); + + + //TXBF Capabilities + memset(pCapELE->TxBFCap, 0, 4); + + //Antenna Selection Capabilities + pCapELE->ASCap = 0; +//add 2 to give space for element ID and len when construct frames + if(pHT->ePeerHTSpecVer == HT_SPEC_VER_EWC) + *len = 30 + 2; + else + *len = 26 + 2; + + + +// IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA | IEEE80211_DL_HT, posHTCap, *len -2); + + //Print each field in detail. Driver should not print out this message by default +// HTDebugHTCapability(posHTCap, (u8*)"HTConstructCapability()"); + return; + +} +/******************************************************************************************************************** + *function: Construct Information Element in Beacon... if HTEnable is turned on + * input: struct ieee80211_device* ieee + * u8* posHTCap //pointer to store Information Ele + * u8* len //store len of + * u8 IsEncrypt //whether encrypt, needed further + * output: none + * return: none + * notice: posHTCap can't be null and be initialized before. only AP and IBSS sta should do this + * *****************************************************************************************************************/ +void HTConstructInfoElement(struct ieee80211_device* ieee, u8* posHTInfo, u8* len, u8 IsEncrypt) +{ + PRT_HIGH_THROUGHPUT pHT = ieee->pHTInfo; + PHT_INFORMATION_ELE pHTInfoEle = (PHT_INFORMATION_ELE)posHTInfo; + if ((posHTInfo == NULL) || (pHTInfoEle == NULL)) + { + IEEE80211_DEBUG(IEEE80211_DL_ERR, "posHTInfo or pHTInfoEle can't be null in HTConstructInfoElement()\n"); + return; + } + + memset(posHTInfo, 0, *len); + if ( (ieee->iw_mode == IW_MODE_ADHOC) || (ieee->iw_mode == IW_MODE_MASTER)) //ap mode is not currently supported + { + pHTInfoEle->ControlChl = ieee->current_network.channel; + pHTInfoEle->ExtChlOffset = ((pHT->bRegBW40MHz == false)?HT_EXTCHNL_OFFSET_NO_EXT: + (ieee->current_network.channel<=6)? + HT_EXTCHNL_OFFSET_UPPER:HT_EXTCHNL_OFFSET_LOWER); + pHTInfoEle->RecommemdedTxWidth = pHT->bRegBW40MHz; + pHTInfoEle->RIFS = 0; + pHTInfoEle->PSMPAccessOnly = 0; + pHTInfoEle->SrvIntGranularity = 0; + pHTInfoEle->OptMode = pHT->CurrentOpMode; + pHTInfoEle->NonGFDevPresent = 0; + pHTInfoEle->DualBeacon = 0; + pHTInfoEle->SecondaryBeacon = 0; + pHTInfoEle->LSigTxopProtectFull = 0; + pHTInfoEle->PcoActive = 0; + pHTInfoEle->PcoPhase = 0; + + memset(pHTInfoEle->BasicMSC, 0, 16); + + + *len = 22 + 2; //same above + + } + else + { + //STA should not generate High Throughput Information Element + *len = 0; + } + //IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA | IEEE80211_DL_HT, posHTInfo, *len - 2); + //HTDebugHTInfo(posHTInfo, "HTConstructInforElement"); + return; +} + +/* + * According to experiment, Realtek AP to STA (based on rtl8190) may achieve best performance + * if both STA and AP set limitation of aggregation size to 32K, that is, set AMPDU density to 2 + * (Ref: IEEE 11n specification). However, if Realtek STA associates to other AP, STA should set + * limitation of aggregation size to 8K, otherwise, performance of traffic stream from STA to AP + * will be much less than the traffic stream from AP to STA if both of the stream runs concurrently + * at the same time. + * + * Frame Format + * Element ID Length OUI Type1 Reserved + * 1 byte 1 byte 3 bytes 1 byte 1 byte + * + * OUI = 0x00, 0xe0, 0x4c, + * Type = 0x02 + * Reserved = 0x00 + * + * 2007.8.21 by Emily +*/ +/******************************************************************************************************************** + *function: Construct Information Element in Beacon... in RT2RT condition + * input: struct ieee80211_device* ieee + * u8* posRT2RTAgg //pointer to store Information Ele + * u8* len //store len + * output: none + * return: none + * notice: + * *****************************************************************************************************************/ +void HTConstructRT2RTAggElement(struct ieee80211_device* ieee, u8* posRT2RTAgg, u8* len) +{ + if (posRT2RTAgg == NULL) { + IEEE80211_DEBUG(IEEE80211_DL_ERR, "posRT2RTAgg can't be null in HTConstructRT2RTAggElement()\n"); + return; + } + memset(posRT2RTAgg, 0, *len); + *posRT2RTAgg++ = 0x00; + *posRT2RTAgg++ = 0xe0; + *posRT2RTAgg++ = 0x4c; + *posRT2RTAgg++ = 0x02; + *posRT2RTAgg++ = 0x01; + *posRT2RTAgg = 0x10;//*posRT2RTAgg = 0x02; + + if(ieee->bSupportRemoteWakeUp) { + *posRT2RTAgg |= 0x08;//RT_HT_CAP_USE_WOW; + } + + *len = 6 + 2; + return; +#ifdef TODO +#if(HAL_CODE_BASE == RTL8192 && DEV_BUS_TYPE == USB_INTERFACE) + /* + //Emily. If it is required to Ask Realtek AP to send AMPDU during AES mode, enable this + section of code. + if(IS_UNDER_11N_AES_MODE(Adapter)) + { + posRT2RTAgg->Octet[5] |=RT_HT_CAP_USE_AMPDU; + }else + { + posRT2RTAgg->Octet[5] &= 0xfb; + } + */ + +#else + // Do Nothing +#endif + + posRT2RTAgg->Length = 6; +#endif + + + + +} + + +/******************************************************************************************************************** + *function: Pick the right Rate Adaptive table to use + * input: struct ieee80211_device* ieee + * u8* pOperateMCS //A pointer to MCS rate bitmap + * return: always we return true + * notice: + * *****************************************************************************************************************/ +u8 HT_PickMCSRate(struct ieee80211_device* ieee, u8* pOperateMCS) +{ + u8 i; + if (pOperateMCS == NULL) + { + IEEE80211_DEBUG(IEEE80211_DL_ERR, "pOperateMCS can't be null in HT_PickMCSRate()\n"); + return false; + } + + switch(ieee->mode) + { + case IEEE_A: + case IEEE_B: + case IEEE_G: + //legacy rate routine handled at selectedrate + + //no MCS rate + for(i=0;i<=15;i++){ + pOperateMCS[i] = 0; + } + break; + + case IEEE_N_24G: //assume CCK rate ok + case IEEE_N_5G: + // Legacy part we only use 6, 5.5,2,1 for N_24G and 6 for N_5G. + // Legacy part shall be handled at SelectRateSet(). + + //HT part + // TODO: may be different if we have different number of antenna + pOperateMCS[0] &=RATE_ADPT_1SS_MASK; //support MCS 0~7 + pOperateMCS[1] &=RATE_ADPT_2SS_MASK; + pOperateMCS[3] &=RATE_ADPT_MCS32_MASK; + break; + + //should never reach here + default: + + break; + + } + + return true; +} + +/* +* Description: +* This function will get the highest speed rate in input MCS set. +* +* /param Adapter Pionter to Adapter entity +* pMCSRateSet Pointer to MCS rate bitmap +* pMCSFilter Pointer to MCS rate filter +* +* /return Highest MCS rate included in pMCSRateSet and filtered by pMCSFilter. +* +*/ +/******************************************************************************************************************** + *function: This function will get the highest speed rate in input MCS set. + * input: struct ieee80211_device* ieee + * u8* pMCSRateSet //Pointer to MCS rate bitmap + * u8* pMCSFilter //Pointer to MCS rate filter + * return: Highest MCS rate included in pMCSRateSet and filtered by pMCSFilter + * notice: + * *****************************************************************************************************************/ +u8 HTGetHighestMCSRate(struct ieee80211_device* ieee, u8* pMCSRateSet, u8* pMCSFilter) +{ + u8 i, j; + u8 bitMap; + u8 mcsRate = 0; + u8 availableMcsRate[16]; + if (pMCSRateSet == NULL || pMCSFilter == NULL) + { + IEEE80211_DEBUG(IEEE80211_DL_ERR, "pMCSRateSet or pMCSFilter can't be null in HTGetHighestMCSRate()\n"); + return false; + } + for(i=0; i<16; i++) + availableMcsRate[i] = pMCSRateSet[i] & pMCSFilter[i]; + + for(i = 0; i < 16; i++) + { + if(availableMcsRate[i] != 0) + break; + } + if(i == 16) + return false; + + for(i = 0; i < 16; i++) + { + if(availableMcsRate[i] != 0) + { + bitMap = availableMcsRate[i]; + for(j = 0; j < 8; j++) + { + if((bitMap%2) != 0) + { + if(HTMcsToDataRate(ieee, (8*i+j)) > HTMcsToDataRate(ieee, mcsRate)) + mcsRate = (8*i+j); + } + bitMap = bitMap>>1; + } + } + } + return (mcsRate|0x80); +} + + + +/* +** +**1.Filter our operation rate set with AP's rate set +**2.shall reference channel bandwidth, STBC, Antenna number +**3.generate rate adative table for firmware +**David 20060906 +** +** \pHTSupportedCap: the connected STA's supported rate Capability element +*/ +u8 HTFilterMCSRate( struct ieee80211_device* ieee, u8* pSupportMCS, u8* pOperateMCS) +{ + + u8 i=0; + + // filter out operational rate set not supported by AP, the lenth of it is 16 + for(i=0;i<=15;i++){ + pOperateMCS[i] = ieee->Regdot11HTOperationalRateSet[i]&pSupportMCS[i]; + } + + + // TODO: adjust our operational rate set according to our channel bandwidth, STBC and Antenna number + + // TODO: fill suggested rate adaptive rate index and give firmware info using Tx command packet + // we also shall suggested the first start rate set according to our singal strength + HT_PickMCSRate(ieee, pOperateMCS); + + // For RTL819X, if pairwisekey = wep/tkip, we support only MCS0~7. + if(ieee->GetHalfNmodeSupportByAPsHandler(ieee->dev)) + pOperateMCS[1] = 0; + + // + // For RTL819X, we support only MCS0~15. + // And also, we do not know how to use MCS32 now. + // + for(i=2; i<=15; i++) + pOperateMCS[i] = 0; + + return true; +} +void HTSetConnectBwMode(struct ieee80211_device* ieee, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset); +#if 0 +//I need move this function to other places, such as rx? +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) +void HTOnAssocRsp_wq(struct work_struct *work) +{ + struct ieee80211_device *ieee = container_of(work, struct ieee80211_device, ht_onAssRsp); +#else +void HTOnAssocRsp_wq(struct ieee80211_device *ieee) +{ +#endif +#endif +void HTOnAssocRsp(struct ieee80211_device *ieee) +{ + PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; + PHT_CAPABILITY_ELE pPeerHTCap = NULL; + PHT_INFORMATION_ELE pPeerHTInfo = NULL; + u16 nMaxAMSDUSize = 0; + u8* pMcsFilter = NULL; + + static u8 EWC11NHTCap[] = {0x00, 0x90, 0x4c, 0x33}; // For 11n EWC definition, 2007.07.17, by Emily + static u8 EWC11NHTInfo[] = {0x00, 0x90, 0x4c, 0x34}; // For 11n EWC definition, 2007.07.17, by Emily + + if( pHTInfo->bCurrentHTSupport == false ) + { + IEEE80211_DEBUG(IEEE80211_DL_ERR, "<=== HTOnAssocRsp(): HT_DISABLE\n"); + return; + } + IEEE80211_DEBUG(IEEE80211_DL_HT, "===> HTOnAssocRsp_wq(): HT_ENABLE\n"); +// IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA, pHTInfo->PeerHTCapBuf, sizeof(HT_CAPABILITY_ELE)); +// IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA, pHTInfo->PeerHTInfoBuf, sizeof(HT_INFORMATION_ELE)); + +// HTDebugHTCapability(pHTInfo->PeerHTCapBuf,"HTOnAssocRsp_wq"); +// HTDebugHTInfo(pHTInfo->PeerHTInfoBuf,"HTOnAssocRsp_wq"); + // + if(!memcmp(pHTInfo->PeerHTCapBuf,EWC11NHTCap, sizeof(EWC11NHTCap))) + pPeerHTCap = (PHT_CAPABILITY_ELE)(&pHTInfo->PeerHTCapBuf[4]); + else + pPeerHTCap = (PHT_CAPABILITY_ELE)(pHTInfo->PeerHTCapBuf); + + if(!memcmp(pHTInfo->PeerHTInfoBuf, EWC11NHTInfo, sizeof(EWC11NHTInfo))) + pPeerHTInfo = (PHT_INFORMATION_ELE)(&pHTInfo->PeerHTInfoBuf[4]); + else + pPeerHTInfo = (PHT_INFORMATION_ELE)(pHTInfo->PeerHTInfoBuf); + + + //////////////////////////////////////////////////////// + // Configurations: + //////////////////////////////////////////////////////// + IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA|IEEE80211_DL_HT, pPeerHTCap, sizeof(HT_CAPABILITY_ELE)); +// IEEE80211_DEBUG_DATA(IEEE80211_DL_DATA|IEEE80211_DL_HT, pPeerHTInfo, sizeof(HT_INFORMATION_ELE)); + // Config Supported Channel Width setting + // + HTSetConnectBwMode(ieee, (HT_CHANNEL_WIDTH)(pPeerHTCap->ChlWidth), (HT_EXTCHNL_OFFSET)(pPeerHTInfo->ExtChlOffset)); + +// if(pHTInfo->bCurBW40MHz == true) + pHTInfo->bCurTxBW40MHz = ((pPeerHTInfo->RecommemdedTxWidth == 1)?true:false); + + // + // Update short GI/ long GI setting + // + // TODO: + pHTInfo->bCurShortGI20MHz= + ((pHTInfo->bRegShortGI20MHz)?((pPeerHTCap->ShortGI20Mhz==1)?true:false):false); + pHTInfo->bCurShortGI40MHz= + ((pHTInfo->bRegShortGI40MHz)?((pPeerHTCap->ShortGI40Mhz==1)?true:false):false); + + // + // Config TX STBC setting + // + // TODO: + + // + // Config DSSS/CCK mode in 40MHz mode + // + // TODO: + pHTInfo->bCurSuppCCK = + ((pHTInfo->bRegSuppCCK)?((pPeerHTCap->DssCCk==1)?true:false):false); + + + // + // Config and configure A-MSDU setting + // + pHTInfo->bCurrent_AMSDU_Support = pHTInfo->bAMSDU_Support; + + nMaxAMSDUSize = (pPeerHTCap->MaxAMSDUSize==0)?3839:7935; + + if(pHTInfo->nAMSDU_MaxSize > nMaxAMSDUSize ) + pHTInfo->nCurrent_AMSDU_MaxSize = nMaxAMSDUSize; + else + pHTInfo->nCurrent_AMSDU_MaxSize = pHTInfo->nAMSDU_MaxSize; + + // + // Config A-MPDU setting + // + pHTInfo->bCurrentAMPDUEnable = pHTInfo->bAMPDUEnable; + if(ieee->is_ap_in_wep_tkip && ieee->is_ap_in_wep_tkip(ieee->dev)) + { + if( (pHTInfo->IOTPeer== HT_IOT_PEER_ATHEROS) || + (pHTInfo->IOTPeer == HT_IOT_PEER_UNKNOWN) ) + pHTInfo->bCurrentAMPDUEnable = false; + } + + // <1> Decide AMPDU Factor + + // By Emily + if(!pHTInfo->bRegRT2RTAggregation) + { + // Decide AMPDU Factor according to protocol handshake + if(pHTInfo->AMPDU_Factor > pPeerHTCap->MaxRxAMPDUFactor) + pHTInfo->CurrentAMPDUFactor = pPeerHTCap->MaxRxAMPDUFactor; + else + pHTInfo->CurrentAMPDUFactor = pHTInfo->AMPDU_Factor; + + }else + { + // Set MPDU density to 2 to Realtek AP, and set it to 0 for others + // Replace MPDU factor declared in original association response frame format. 2007.08.20 by Emily +#if 0 + osTmp= PacketGetElement( asocpdu, EID_Vendor, OUI_SUB_REALTEK_AGG, OUI_SUBTYPE_DONT_CARE); + if(osTmp.Length >= 5) //00:e0:4c:02:00 +#endif + if (ieee->current_network.bssht.bdRT2RTAggregation) + { + if( ieee->pairwise_key_type != KEY_TYPE_NA) + // Realtek may set 32k in security mode and 64k for others + pHTInfo->CurrentAMPDUFactor = pPeerHTCap->MaxRxAMPDUFactor; + else + pHTInfo->CurrentAMPDUFactor = HT_AGG_SIZE_64K; + }else + { + if(pPeerHTCap->MaxRxAMPDUFactor < HT_AGG_SIZE_32K) + pHTInfo->CurrentAMPDUFactor = pPeerHTCap->MaxRxAMPDUFactor; + else + pHTInfo->CurrentAMPDUFactor = HT_AGG_SIZE_32K; + } + } + + // <2> Set AMPDU Minimum MPDU Start Spacing + // 802.11n 3.0 section 9.7d.3 +#if 1 + if(pHTInfo->MPDU_Density > pPeerHTCap->MPDUDensity) + pHTInfo->CurrentMPDUDensity = pHTInfo->MPDU_Density; + else + pHTInfo->CurrentMPDUDensity = pPeerHTCap->MPDUDensity; + if(ieee->pairwise_key_type != KEY_TYPE_NA ) + pHTInfo->CurrentMPDUDensity = 7; // 8us +#else + if(pHTInfo->MPDU_Density > pPeerHTCap->MPDUDensity) + pHTInfo->CurrentMPDUDensity = pHTInfo->MPDU_Density; + else + pHTInfo->CurrentMPDUDensity = pPeerHTCap->MPDUDensity; +#endif + // Force TX AMSDU + + // Lanhsin: mark for tmp to avoid deauth by ap from s3 + //if(memcmp(pMgntInfo->Bssid, NETGEAR834Bv2_BROADCOM, 3)==0) + if(pHTInfo->IOTAction & HT_IOT_ACT_TX_USE_AMSDU_8K) + { + + pHTInfo->bCurrentAMPDUEnable = false; + pHTInfo->ForcedAMSDUMode = HT_AGG_FORCE_ENABLE; + pHTInfo->ForcedAMSDUMaxSize = 7935; + } + + // Rx Reorder Setting + pHTInfo->bCurRxReorderEnable = pHTInfo->bRegRxReorderEnable; + + // + // Filter out unsupported HT rate for this AP + // Update RATR table + // This is only for 8190 ,8192 or later product which using firmware to handle rate adaptive mechanism. + // + + // Handle Ralink AP bad MCS rate set condition. Joseph. + // This fix the bug of Ralink AP. This may be removed in the future. + if(pPeerHTCap->MCS[0] == 0) + pPeerHTCap->MCS[0] = 0xff; + + // Joseph test //LZM ADD 090318 + HTIOTActDetermineRaFunc(ieee, ((pPeerHTCap->MCS[1])!=0)); + + HTFilterMCSRate(ieee, pPeerHTCap->MCS, ieee->dot11HTOperationalRateSet); + + // + // Config MIMO Power Save setting + // + pHTInfo->PeerMimoPs = pPeerHTCap->MimoPwrSave; + if(pHTInfo->PeerMimoPs == MIMO_PS_STATIC) + pMcsFilter = MCS_FILTER_1SS; + else + pMcsFilter = MCS_FILTER_ALL; + //WB add for MCS8 bug +// pMcsFilter = MCS_FILTER_1SS; + ieee->HTHighestOperaRate = HTGetHighestMCSRate(ieee, ieee->dot11HTOperationalRateSet, pMcsFilter); + ieee->HTCurrentOperaRate = ieee->HTHighestOperaRate; + + // + // Config current operation mode. + // + pHTInfo->CurrentOpMode = pPeerHTInfo->OptMode; + + + +} + +void HTSetConnectBwModeCallback(struct ieee80211_device* ieee); +/******************************************************************************************************************** + *function: initialize HT info(struct PRT_HIGH_THROUGHPUT) + * input: struct ieee80211_device* ieee + * output: none + * return: none + * notice: This function is called when * (1) MPInitialization Phase * (2) Receiving of Deauthentication from AP +********************************************************************************************************************/ +// TODO: Should this funciton be called when receiving of Disassociation? +void HTInitializeHTInfo(struct ieee80211_device* ieee) +{ + PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; + + // + // These parameters will be reset when receiving deauthentication packet + // + IEEE80211_DEBUG(IEEE80211_DL_HT, "===========>%s()\n", __FUNCTION__); + pHTInfo->bCurrentHTSupport = false; + + // 40MHz channel support + pHTInfo->bCurBW40MHz = false; + pHTInfo->bCurTxBW40MHz = false; + + // Short GI support + pHTInfo->bCurShortGI20MHz = false; + pHTInfo->bCurShortGI40MHz = false; + pHTInfo->bForcedShortGI = false; + + // CCK rate support + // This flag is set to true to support CCK rate by default. + // It will be affected by "pHTInfo->bRegSuppCCK" and AP capabilities only when associate to + // 11N BSS. + pHTInfo->bCurSuppCCK = true; + + // AMSDU related + pHTInfo->bCurrent_AMSDU_Support = false; + pHTInfo->nCurrent_AMSDU_MaxSize = pHTInfo->nAMSDU_MaxSize; + + // AMPUD related + pHTInfo->CurrentMPDUDensity = pHTInfo->MPDU_Density; + pHTInfo->CurrentAMPDUFactor = pHTInfo->AMPDU_Factor; + + + + // Initialize all of the parameters related to 11n + memset((void*)(&(pHTInfo->SelfHTCap)), 0, sizeof(pHTInfo->SelfHTCap)); + memset((void*)(&(pHTInfo->SelfHTInfo)), 0, sizeof(pHTInfo->SelfHTInfo)); + memset((void*)(&(pHTInfo->PeerHTCapBuf)), 0, sizeof(pHTInfo->PeerHTCapBuf)); + memset((void*)(&(pHTInfo->PeerHTInfoBuf)), 0, sizeof(pHTInfo->PeerHTInfoBuf)); + + pHTInfo->bSwBwInProgress = false; + pHTInfo->ChnlOp = CHNLOP_NONE; + + // Set default IEEE spec for Draft N + pHTInfo->ePeerHTSpecVer = HT_SPEC_VER_IEEE; + + // Realtek proprietary aggregation mode + pHTInfo->bCurrentRT2RTAggregation = false; + pHTInfo->bCurrentRT2RTLongSlotTime = false; + pHTInfo->RT2RT_HT_Mode = (RT_HT_CAPBILITY)0; + + pHTInfo->IOTPeer = 0; + pHTInfo->IOTAction = 0; + pHTInfo->IOTRaFunc = 0; + + //MCS rate initialized here + { + u8* RegHTSuppRateSets = &(ieee->RegHTSuppRateSet[0]); + RegHTSuppRateSets[0] = 0xFF; //support MCS 0~7 + RegHTSuppRateSets[1] = 0xFF; //support MCS 8~15 + RegHTSuppRateSets[4] = 0x01; //support MCS 32 + } +} +/******************************************************************************************************************** + *function: initialize Bss HT structure(struct PBSS_HT) + * input: PBSS_HT pBssHT //to be initialized + * output: none + * return: none + * notice: This function is called when initialize network structure +********************************************************************************************************************/ +void HTInitializeBssDesc(PBSS_HT pBssHT) +{ + + pBssHT->bdSupportHT = false; + memset(pBssHT->bdHTCapBuf, 0, sizeof(pBssHT->bdHTCapBuf)); + pBssHT->bdHTCapLen = 0; + memset(pBssHT->bdHTInfoBuf, 0, sizeof(pBssHT->bdHTInfoBuf)); + pBssHT->bdHTInfoLen = 0; + + pBssHT->bdHTSpecVer= HT_SPEC_VER_IEEE; + + pBssHT->bdRT2RTAggregation = false; + pBssHT->bdRT2RTLongSlotTime = false; + pBssHT->RT2RT_HT_Mode = (RT_HT_CAPBILITY)0; +} +#if 0 +//below function has merged into ieee80211_network_init() in ieee80211_rx.c +void +HTParsingHTCapElement( + IN PADAPTER Adapter, + IN OCTET_STRING HTCapIE, + OUT PRT_WLAN_BSS pBssDesc +) +{ + PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; + + if( HTCapIE.Length > sizeof(pBssDesc->BssHT.bdHTCapBuf) ) + { + RT_TRACE( COMP_HT, DBG_LOUD, ("HTParsingHTCapElement(): HT Capability Element length is too long!\n") ); + return; + } + + // TODO: Check the correctness of HT Cap + //Print each field in detail. Driver should not print out this message by default + if(!pMgntInfo->mActingAsAp && !pMgntInfo->mAssoc) + HTDebugHTCapability(DBG_TRACE, Adapter, &HTCapIE, (pu8)"HTParsingHTCapElement()"); + + HTCapIE.Length = HTCapIE.Length > sizeof(pBssDesc->BssHT.bdHTCapBuf)?\ + sizeof(pBssDesc->BssHT.bdHTCapBuf):HTCapIE.Length; //prevent from overflow + + CopyMem(pBssDesc->BssHT.bdHTCapBuf, HTCapIE.Octet, HTCapIE.Length); + pBssDesc->BssHT.bdHTCapLen = HTCapIE.Length; + +} + + +void +HTParsingHTInfoElement( + PADAPTER Adapter, + OCTET_STRING HTInfoIE, + PRT_WLAN_BSS pBssDesc +) +{ + PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; + + if( HTInfoIE.Length > sizeof(pBssDesc->BssHT.bdHTInfoBuf)) + { + RT_TRACE( COMP_HT, DBG_LOUD, ("HTParsingHTInfoElement(): HT Information Element length is too long!\n") ); + return; + } + + // TODO: Check the correctness of HT Info + //Print each field in detail. Driver should not print out this message by default + if(!pMgntInfo->mActingAsAp && !pMgntInfo->mAssoc) + HTDebugHTInfo(DBG_TRACE, Adapter, &HTInfoIE, (pu8)"HTParsingHTInfoElement()"); + + HTInfoIE.Length = HTInfoIE.Length > sizeof(pBssDesc->BssHT.bdHTInfoBuf)?\ + sizeof(pBssDesc->BssHT.bdHTInfoBuf):HTInfoIE.Length; //prevent from overflow + + CopyMem( pBssDesc->BssHT.bdHTInfoBuf, HTInfoIE.Octet, HTInfoIE.Length); + pBssDesc->BssHT.bdHTInfoLen = HTInfoIE.Length; +} + +/* + * Get HT related information from beacon and save it in BssDesc + * + * (1) Parse HTCap, and HTInfo, and record whether it is 11n AP + * (2) If peer is HT, but not WMM, call QosSetLegacyWMMParamWithHT() + * (3) Check whether peer is Realtek AP (for Realtek proprietary aggregation mode). + * Input: + * PADAPTER Adapter + * + * Output: + * PRT_TCB BssDesc + * +*/ +void HTGetValueFromBeaconOrProbeRsp( + PADAPTER Adapter, + POCTET_STRING pSRCmmpdu, + PRT_WLAN_BSS bssDesc +) +{ + PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; + PRT_HIGH_THROUGHPUT pHTInfo = GET_HT_INFO(pMgntInfo); + OCTET_STRING HTCapIE, HTInfoIE, HTRealtekAgg, mmpdu; + OCTET_STRING BroadcomElement, CiscoElement; + + mmpdu.Octet = pSRCmmpdu->Octet; + mmpdu.Length = pSRCmmpdu->Length; + + //2Note: + // Mark for IOT testing using Linksys WRT350N, This AP does not contain WMM IE when + // it is configured at pure-N mode. + // if(bssDesc->BssQos.bdQoSMode & QOS_WMM) + // + + HTInitializeBssDesc (&bssDesc->BssHT); + + //2<1> Parse HTCap, and HTInfo + // Get HT Capability IE: (1) Get IEEE Draft N IE or (2) Get EWC IE + HTCapIE = PacketGetElement(mmpdu, EID_HTCapability, OUI_SUB_DONT_CARE, OUI_SUBTYPE_DONT_CARE); + if(HTCapIE.Length == 0) + { + HTCapIE = PacketGetElement(mmpdu, EID_Vendor, OUI_SUB_11N_EWC_HT_CAP, OUI_SUBTYPE_DONT_CARE); + if(HTCapIE.Length != 0) + bssDesc->BssHT.bdHTSpecVer= HT_SPEC_VER_EWC; + } + if(HTCapIE.Length != 0) + HTParsingHTCapElement(Adapter, HTCapIE, bssDesc); + + // Get HT Information IE: (1) Get IEEE Draft N IE or (2) Get EWC IE + HTInfoIE = PacketGetElement(mmpdu, EID_HTInfo, OUI_SUB_DONT_CARE, OUI_SUBTYPE_DONT_CARE); + if(HTInfoIE.Length == 0) + { + HTInfoIE = PacketGetElement(mmpdu, EID_Vendor, OUI_SUB_11N_EWC_HT_INFO, OUI_SUBTYPE_DONT_CARE); + if(HTInfoIE.Length != 0) + bssDesc->BssHT.bdHTSpecVer = HT_SPEC_VER_EWC; + } + if(HTInfoIE.Length != 0) + HTParsingHTInfoElement(Adapter, HTInfoIE, bssDesc); + + //2<2>If peer is HT, but not WMM, call QosSetLegacyWMMParamWithHT() + if(HTCapIE.Length != 0) + { + bssDesc->BssHT.bdSupportHT = true; + if(bssDesc->BssQos.bdQoSMode == QOS_DISABLE) + QosSetLegacyWMMParamWithHT(Adapter, bssDesc); + } + else + { + bssDesc->BssHT.bdSupportHT = false; + } + + //2<3>Check whether the peer is Realtek AP/STA + if(pHTInfo->bRegRT2RTAggregation) + { + if(bssDesc->BssHT.bdSupportHT) + { + HTRealtekAgg = PacketGetElement(mmpdu, EID_Vendor, OUI_SUB_REALTEK_AGG, OUI_SUBTYPE_DONT_CARE); + if(HTRealtekAgg.Length >=5 ) + { + bssDesc->BssHT.bdRT2RTAggregation = true; + + if((HTRealtekAgg.Octet[4]==1) && (HTRealtekAgg.Octet[5] & 0x02)) + bssDesc->BssHT.bdRT2RTLongSlotTime = true; + } + } + } + + // + // 2008/01/25 MH Get Broadcom AP IE for manamgent frame CCK rate problem. + // AP can not receive CCK managemtn from from 92E. + // + + // Initialize every new bss broadcom cap exist as false.. + bssDesc->bBroadcomCapExist= false; + + if(HTCapIE.Length != 0 || HTInfoIE.Length != 0) + { + u4Byte Length = 0; + + FillOctetString(BroadcomElement, NULL, 0); + + BroadcomElement = PacketGetElement( mmpdu, EID_Vendor, OUI_SUB_BROADCOM_IE_1, OUI_SUBTYPE_DONT_CARE); + Length += BroadcomElement.Length; + BroadcomElement = PacketGetElement( mmpdu, EID_Vendor, OUI_SUB_BROADCOM_IE_2, OUI_SUBTYPE_DONT_CARE); + Length += BroadcomElement.Length; + BroadcomElement = PacketGetElement( mmpdu, EID_Vendor, OUI_SUB_BROADCOM_IE_3, OUI_SUBTYPE_DONT_CARE); + Length += BroadcomElement.Length; + + if(Length > 0) + bssDesc->bBroadcomCapExist = true; + } + + + // For Cisco IOT issue + CiscoElement = PacketGetElement( mmpdu, EID_Vendor, OUI_SUB_CISCO_IE, OUI_SUBTYPE_DONT_CARE); + if(CiscoElement.Length != 0){ // 3: 0x00, 0x40, 0x96 .... + bssDesc->bCiscoCapExist = true; + }else{ + bssDesc->bCiscoCapExist = false; + } +} + + +#endif +/******************************************************************************************************************** + *function: initialize Bss HT structure(struct PBSS_HT) + * input: struct ieee80211_device *ieee + * struct ieee80211_network *pNetwork //usually current network we are live in + * output: none + * return: none + * notice: This function should ONLY be called before association +********************************************************************************************************************/ +void HTResetSelfAndSavePeerSetting(struct ieee80211_device* ieee, struct ieee80211_network * pNetwork) +{ + PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; +// u16 nMaxAMSDUSize; +// PHT_CAPABILITY_ELE pPeerHTCap = (PHT_CAPABILITY_ELE)pNetwork->bssht.bdHTCapBuf; +// PHT_INFORMATION_ELE pPeerHTInfo = (PHT_INFORMATION_ELE)pNetwork->bssht.bdHTInfoBuf; +// u8* pMcsFilter; + u8 bIOTAction = 0; + + // + // Save Peer Setting before Association + // + IEEE80211_DEBUG(IEEE80211_DL_HT, "==============>%s()\n", __FUNCTION__); + /*unmark bEnableHT flag here is the same reason why unmarked in function ieee80211_softmac_new_net. WB 2008.09.10*/ +// if( pHTInfo->bEnableHT && pNetwork->bssht.bdSupportHT) + if (pNetwork->bssht.bdSupportHT) + { + pHTInfo->bCurrentHTSupport = true; + pHTInfo->ePeerHTSpecVer = pNetwork->bssht.bdHTSpecVer; + + // Save HTCap and HTInfo information Element + if(pNetwork->bssht.bdHTCapLen > 0 && pNetwork->bssht.bdHTCapLen <= sizeof(pHTInfo->PeerHTCapBuf)) + memcpy(pHTInfo->PeerHTCapBuf, pNetwork->bssht.bdHTCapBuf, pNetwork->bssht.bdHTCapLen); + + if(pNetwork->bssht.bdHTInfoLen > 0 && pNetwork->bssht.bdHTInfoLen <= sizeof(pHTInfo->PeerHTInfoBuf)) + memcpy(pHTInfo->PeerHTInfoBuf, pNetwork->bssht.bdHTInfoBuf, pNetwork->bssht.bdHTInfoLen); + + // Check whether RT to RT aggregation mode is enabled + if(pHTInfo->bRegRT2RTAggregation) + { + pHTInfo->bCurrentRT2RTAggregation = pNetwork->bssht.bdRT2RTAggregation; + pHTInfo->bCurrentRT2RTLongSlotTime = pNetwork->bssht.bdRT2RTLongSlotTime; + pHTInfo->RT2RT_HT_Mode = pNetwork->bssht.RT2RT_HT_Mode; + } + else + { + pHTInfo->bCurrentRT2RTAggregation = false; + pHTInfo->bCurrentRT2RTLongSlotTime = false; + pHTInfo->RT2RT_HT_Mode = (RT_HT_CAPBILITY)0; + } + + // Determine the IOT Peer Vendor. + HTIOTPeerDetermine(ieee); + + // Decide IOT Action + // Must be called after the parameter of pHTInfo->bCurrentRT2RTAggregation is decided + pHTInfo->IOTAction = 0; + bIOTAction = HTIOTActIsDisableMCS14(ieee, pNetwork->bssid); + if(bIOTAction) + pHTInfo->IOTAction |= HT_IOT_ACT_DISABLE_MCS14; + + bIOTAction = HTIOTActIsDisableMCS15(ieee); + if(bIOTAction) + pHTInfo->IOTAction |= HT_IOT_ACT_DISABLE_MCS15; + + bIOTAction = HTIOTActIsDisableMCSTwoSpatialStream(ieee); + if(bIOTAction) + pHTInfo->IOTAction |= HT_IOT_ACT_DISABLE_ALL_2SS; + + + bIOTAction = HTIOTActIsDisableEDCATurbo(ieee, pNetwork->bssid); + if(bIOTAction) + pHTInfo->IOTAction |= HT_IOT_ACT_DISABLE_EDCA_TURBO; + + bIOTAction = HTIOTActIsMgntUseCCK6M(pNetwork); + if(bIOTAction) + pHTInfo->IOTAction |= HT_IOT_ACT_MGNT_USE_CCK_6M; + + bIOTAction = HTIOTActIsCCDFsync(pNetwork->bssid); + if(bIOTAction) + pHTInfo->IOTAction |= HT_IOT_ACT_CDD_FSYNC; + + bIOTAction = HTIOTActIsForcedCTS2Self(pNetwork); + if(bIOTAction) + pHTInfo->IOTAction |= HT_IOT_ACT_FORCED_CTS2SELF; + + //bIOTAction = HTIOTActIsForcedRTSCTS(ieee, pNetwork); + //if(bIOTAction) + // pHTInfo->IOTAction |= HT_IOT_ACT_FORCED_RTS; + +#if defined(RTL8192SU) + bIOTAction = HTIOCActRejcectADDBARequest(pNetwork); + if(bIOTAction) + pHTInfo->IOTAction |= HT_IOT_ACT_REJECT_ADDBA_REQ; +#endif + + bIOTAction = HTIOCActAllowPeerAggOnePacket(ieee, pNetwork); + if(bIOTAction) + pHTInfo->IOTAction |= HT_IOT_ACT_ALLOW_PEER_AGG_ONE_PKT; + + bIOTAction = HTIOTActIsEDCABiasRx(ieee, pNetwork); + if(bIOTAction) + pHTInfo->IOTAction |= HT_IOT_ACT_EDCA_BIAS_ON_RX; + +#if defined(RTL8192SU) + bIOTAction = HTIOTActDisableShortGI(ieee, pNetwork); + if(bIOTAction) + pHTInfo->IOTAction |= HT_IOT_ACT_DISABLE_SHORT_GI; + + bIOTAction = HTIOTActDisableHighPower(ieee, pNetwork); + if(bIOTAction) + pHTInfo->IOTAction |= HT_IOT_ACT_DISABLE_HIGH_POWER; +#endif + + bIOTAction = HTIOTActIsForcedAMSDU8K(ieee, pNetwork); + if(bIOTAction) + pHTInfo->IOTAction |= HT_IOT_ACT_TX_USE_AMSDU_8K; + +#if defined(RTL8192SU) + bIOTAction = HTIOTActIsTxNoAggregation(ieee, pNetwork); + if(bIOTAction) + pHTInfo->IOTAction |= HT_IOT_ACT_TX_NO_AGGREGATION; + + bIOTAction = HTIOTActIsDisableTx40MHz(ieee, pNetwork); + if(bIOTAction) + pHTInfo->IOTAction |= HT_IOT_ACT_DISABLE_TX_40_MHZ; + + bIOTAction = HTIOTActIsDisableTx2SS(ieee, pNetwork); + if(bIOTAction) + pHTInfo->IOTAction |= HT_IOT_ACT_DISABLE_TX_2SS; +#endif + //must after HT_IOT_ACT_TX_NO_AGGREGATION + bIOTAction = HTIOTActIsForcedRTSCTS(ieee, pNetwork); + if(bIOTAction) + pHTInfo->IOTAction |= HT_IOT_ACT_FORCED_RTS; + + printk("!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!IOTAction = %8.8x\n", pHTInfo->IOTAction); + } + else + { + pHTInfo->bCurrentHTSupport = false; + pHTInfo->bCurrentRT2RTAggregation = false; + pHTInfo->bCurrentRT2RTLongSlotTime = false; + pHTInfo->RT2RT_HT_Mode = (RT_HT_CAPBILITY)0; + + pHTInfo->IOTAction = 0; + pHTInfo->IOTRaFunc = 0; + } + +} + +void HTUpdateSelfAndPeerSetting(struct ieee80211_device* ieee, struct ieee80211_network * pNetwork) +{ + PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; +// PHT_CAPABILITY_ELE pPeerHTCap = (PHT_CAPABILITY_ELE)pNetwork->bssht.bdHTCapBuf; + PHT_INFORMATION_ELE pPeerHTInfo = (PHT_INFORMATION_ELE)pNetwork->bssht.bdHTInfoBuf; + + if(pHTInfo->bCurrentHTSupport) + { + // + // Config current operation mode. + // + if(pNetwork->bssht.bdHTInfoLen != 0) + pHTInfo->CurrentOpMode = pPeerHTInfo->OptMode; + + // + // <TODO: Config according to OBSS non-HT STA present!!> + // + } +} + +void HTUseDefaultSetting(struct ieee80211_device* ieee) +{ + PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; +// u8 regBwOpMode; + + if(pHTInfo->bEnableHT) + { + pHTInfo->bCurrentHTSupport = true; + + pHTInfo->bCurSuppCCK = pHTInfo->bRegSuppCCK; + + pHTInfo->bCurBW40MHz = pHTInfo->bRegBW40MHz; + + pHTInfo->bCurShortGI20MHz= pHTInfo->bRegShortGI20MHz; + + pHTInfo->bCurShortGI40MHz= pHTInfo->bRegShortGI40MHz; + + pHTInfo->bCurrent_AMSDU_Support = pHTInfo->bAMSDU_Support; + + pHTInfo->nCurrent_AMSDU_MaxSize = pHTInfo->nAMSDU_MaxSize; + + pHTInfo->bCurrentAMPDUEnable = pHTInfo->bAMPDUEnable; + + pHTInfo->CurrentAMPDUFactor = pHTInfo->AMPDU_Factor; + + pHTInfo->CurrentMPDUDensity = pHTInfo->CurrentMPDUDensity; + + // Set BWOpMode register + + //update RATR index0 + HTFilterMCSRate(ieee, ieee->Regdot11HTOperationalRateSet, ieee->dot11HTOperationalRateSet); + //function below is not implemented at all. WB +#ifdef TODO + Adapter->HalFunc.InitHalRATRTableHandler( Adapter, &pMgntInfo->dot11OperationalRateSet, pMgntInfo->dot11HTOperationalRateSet); +#endif + ieee->HTHighestOperaRate = HTGetHighestMCSRate(ieee, ieee->dot11HTOperationalRateSet, MCS_FILTER_ALL); + ieee->HTCurrentOperaRate = ieee->HTHighestOperaRate; + + } + else + { + pHTInfo->bCurrentHTSupport = false; + } + return; +} +/******************************************************************************************************************** + *function: check whether HT control field exists + * input: struct ieee80211_device *ieee + * u8* pFrame //coming skb->data + * output: none + * return: return true if HT control field exists(false otherwise) + * notice: +********************************************************************************************************************/ +u8 HTCCheck(struct ieee80211_device* ieee, u8* pFrame) +{ + if(ieee->pHTInfo->bCurrentHTSupport) + { + if( (IsQoSDataFrame(pFrame) && Frame_Order(pFrame)) == 1) + { + IEEE80211_DEBUG(IEEE80211_DL_HT, "HT CONTROL FILED EXIST!!\n"); + return true; + } + } + return false; +} + +// +// This function set bandwidth mode in protocol layer. +// +void HTSetConnectBwMode(struct ieee80211_device* ieee, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset) +{ + PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; +// u32 flags = 0; + + if(pHTInfo->bRegBW40MHz == false) + return; + + + + // To reduce dummy operation +// if((pHTInfo->bCurBW40MHz==false && Bandwidth==HT_CHANNEL_WIDTH_20) || +// (pHTInfo->bCurBW40MHz==true && Bandwidth==HT_CHANNEL_WIDTH_20_40 && Offset==pHTInfo->CurSTAExtChnlOffset)) +// return; + +// spin_lock_irqsave(&(ieee->bw_spinlock), flags); + if(pHTInfo->bSwBwInProgress) { +// spin_unlock_irqrestore(&(ieee->bw_spinlock), flags); + return; + } + //if in half N mode, set to 20M bandwidth please 09.08.2008 WB. + if(Bandwidth==HT_CHANNEL_WIDTH_20_40 && (!ieee->GetHalfNmodeSupportByAPsHandler(ieee->dev))) + { + // Handle Illegal extention channel offset!! + if(ieee->current_network.channel<2 && Offset==HT_EXTCHNL_OFFSET_LOWER) + Offset = HT_EXTCHNL_OFFSET_NO_EXT; + if(Offset==HT_EXTCHNL_OFFSET_UPPER || Offset==HT_EXTCHNL_OFFSET_LOWER) { + pHTInfo->bCurBW40MHz = true; + pHTInfo->CurSTAExtChnlOffset = Offset; + } else { + pHTInfo->bCurBW40MHz = false; + pHTInfo->CurSTAExtChnlOffset = HT_EXTCHNL_OFFSET_NO_EXT; + } + } else { + pHTInfo->bCurBW40MHz = false; + pHTInfo->CurSTAExtChnlOffset = HT_EXTCHNL_OFFSET_NO_EXT; + } + + pHTInfo->bSwBwInProgress = true; + + // TODO: 2007.7.13 by Emily Wait 2000ms in order to garantee that switching + // bandwidth is executed after scan is finished. It is a temporal solution + // because software should ganrantee the last operation of switching bandwidth + // is executed properlly. + HTSetConnectBwModeCallback(ieee); + +// spin_unlock_irqrestore(&(ieee->bw_spinlock), flags); +} + +void HTSetConnectBwModeCallback(struct ieee80211_device* ieee) +{ + PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; + + IEEE80211_DEBUG(IEEE80211_DL_HT, "======>%s()\n", __FUNCTION__); + if(pHTInfo->bCurBW40MHz) + { + if(pHTInfo->CurSTAExtChnlOffset==HT_EXTCHNL_OFFSET_UPPER) + ieee->set_chan(ieee->dev, ieee->current_network.channel+2); + else if(pHTInfo->CurSTAExtChnlOffset==HT_EXTCHNL_OFFSET_LOWER) + ieee->set_chan(ieee->dev, ieee->current_network.channel-2); + else + ieee->set_chan(ieee->dev, ieee->current_network.channel); + + ieee->SetBWModeHandler(ieee->dev, HT_CHANNEL_WIDTH_20_40, pHTInfo->CurSTAExtChnlOffset); + } else { + ieee->set_chan(ieee->dev, ieee->current_network.channel); + ieee->SetBWModeHandler(ieee->dev, HT_CHANNEL_WIDTH_20, HT_EXTCHNL_OFFSET_NO_EXT); + } + + pHTInfo->bSwBwInProgress = false; +} + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) +EXPORT_SYMBOL_NOVERS(HTUpdateSelfAndPeerSetting); +#else +EXPORT_SYMBOL(HTUpdateSelfAndPeerSetting); +#endif diff --git a/drivers/staging/rtl8192su/ieee80211/rtl819x_Qos.h b/drivers/staging/rtl8192su/ieee80211/rtl819x_Qos.h new file mode 100644 index 000000000000..f7b882b99d14 --- /dev/null +++ b/drivers/staging/rtl8192su/ieee80211/rtl819x_Qos.h @@ -0,0 +1,749 @@ +#ifndef __INC_QOS_TYPE_H +#define __INC_QOS_TYPE_H + +//#include "EndianFree.h" +#define BIT0 0x00000001 +#define BIT1 0x00000002 +#define BIT2 0x00000004 +#define BIT3 0x00000008 +#define BIT4 0x00000010 +#define BIT5 0x00000020 +#define BIT6 0x00000040 +#define BIT7 0x00000080 +#define BIT8 0x00000100 +#define BIT9 0x00000200 +#define BIT10 0x00000400 +#define BIT11 0x00000800 +#define BIT12 0x00001000 +#define BIT13 0x00002000 +#define BIT14 0x00004000 +#define BIT15 0x00008000 +#define BIT16 0x00010000 +#define BIT17 0x00020000 +#define BIT18 0x00040000 +#define BIT19 0x00080000 +#define BIT20 0x00100000 +#define BIT21 0x00200000 +#define BIT22 0x00400000 +#define BIT23 0x00800000 +#define BIT24 0x01000000 +#define BIT25 0x02000000 +#define BIT26 0x04000000 +#define BIT27 0x08000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 + +#define MAX_WMMELE_LENGTH 64 + +// +// QoS mode. +// enum 0, 1, 2, 4: since we can use the OR(|) operation. +// +// QOS_MODE is redefined for enum can't be ++, | under C++ compiler, 2006.05.17, by rcnjko. +//typedef enum _QOS_MODE{ +// QOS_DISABLE = 0, +// QOS_WMM = 1, +// QOS_EDCA = 2, +// QOS_HCCA = 4, +//}QOS_MODE,*PQOS_MODE; +// +typedef u32 QOS_MODE, *PQOS_MODE; +#define QOS_DISABLE 0 +#define QOS_WMM 1 +#define QOS_WMMSA 2 +#define QOS_EDCA 4 +#define QOS_HCCA 8 +#define QOS_WMM_UAPSD 16 //WMM Power Save, 2006-06-14 Isaiah + +#define AC_PARAM_SIZE 4 +#define WMM_PARAM_ELE_BODY_LEN 18 + +// +// QoS ACK Policy Field Values +// Ref: WMM spec 2.1.6: QoS Control Field, p.10. +// +typedef enum _ACK_POLICY{ + eAckPlc0_ACK = 0x00, + eAckPlc1_NoACK = 0x01, +}ACK_POLICY,*PACK_POLICY; + +#define WMM_PARAM_ELEMENT_SIZE (8+(4*AC_PARAM_SIZE)) +#if 0 +#define GET_QOS_CTRL(_pStart) ReadEF2Byte((u8 *)(_pStart) + 24) +#define SET_QOS_CTRL(_pStart, _value) WriteEF2Byte((u8 *)(_pStart) + 24, _value) + +// WMM control field. +#define GET_QOS_CTRL_WMM_UP(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 0, 3)) +#define SET_QOS_CTRL_WMM_UP(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 0, 3, (u8)(_value)) + +#define GET_QOS_CTRL_WMM_EOSP(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 4, 1)) +#define SET_QOS_CTRL_WMM_EOSP(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 4, 1, (u8)(_value)) + +#define GET_QOS_CTRL_WMM_ACK_POLICY(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 5, 2)) +#define SET_QOS_CTRL_WMM_ACK_POLICY(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 5, 2, (u8)(_value)) + +// 802.11e control field (by STA, data) +#define GET_QOS_CTRL_STA_DATA_TID(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 0, 4)) +#define SET_QOS_CTRL_STA_DATA_TID(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 0, 4, (u8)(_value)) + +#define GET_QOS_CTRL_STA_DATA_QSIZE_FLAG(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 4, 1)) +#define SET_QOS_CTRL_STA_DATA_QSIZE_FLAG(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 4, 1, (u8)(_value)) + +#define GET_QOS_CTRL_STA_DATA_ACK_POLICY(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 5, 2)) +#define SET_QOS_CTRL_STA_DATA_ACK_POLICY(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 5, 2, (u8)(_value)) + +#define GET_QOS_CTRL_STA_DATA_TXOP(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 8, 8)) +#define SET_QOS_CTRL_STA_DATA_TXOP(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 8, 8, (u8)(_value)) + +#define GET_QOS_CTRL_STA_DATA_QSIZE(_pStart) GET_QOS_CTRL_STA_DATA_TXOP(_pStart) +#define SET_QOS_CTRL_STA_DATA_QSIZE(_pStart, _value) SET_QOS_CTRL_STA_DATA_TXOP(_pStart) + +// 802.11e control field (by HC, data) +#define GET_QOS_CTRL_HC_DATA_TID(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 0, 4)) +#define SET_QOS_CTRL_HC_DATA_TID(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 0, 4, (u8)(_value)) + +#define GET_QOS_CTRL_HC_DATA_EOSP(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 4, 1)) +#define SET_QOS_CTRL_HC_DATA_EOSP(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 4, 1, (u8)(_value)) + +#define GET_QOS_CTRL_HC_DATA_ACK_POLICY(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 5, 2)) +#define SET_QOS_CTRL_HC_DATA_ACK_POLICY(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 5, 2, (u8)(_value)) + +#define GET_QOS_CTRL_HC_DATA_PS_BUFSTATE(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 8, 8)) +#define SET_QOS_CTRL_HC_DATA_PS_BUFSTATE(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 8, 8, (u8)(_value)) + +// 802.11e control field (by HC, CFP) +#define GET_QOS_CTRL_HC_CFP_TID(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 0, 4)) +#define SET_QOS_CTRL_HC_CFP_TID(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 0, 4, (u8)(_value)) + +#define GET_QOS_CTRL_HC_CFP_EOSP(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 4, 1)) +#define SET_QOS_CTRL_HC_CFP_EOSP(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 4, 1, (u8)(_value)) + +#define GET_QOS_CTRL_HC_CFP_ACK_POLICY(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 5, 2)) +#define SET_QOS_CTRL_HC_CFP_ACK_POLICY(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 5, 2, (u8)(_value)) + +#define GET_QOS_CTRL_HC_CFP_TXOP_LIMIT(_pStart) ((u8)LE_BITS_TO_2BYTE((u8 *)(_pStart)+24, 8, 8)) +#define SET_QOS_CTRL_HC_CFP_TXOP_LIMIT(_pStart, _value) SET_BITS_TO_LE_2BYTE((u8 *)(_pStart)+24, 8, 8, (u8)(_value)) + +#define SET_WMM_QOS_INFO_FIELD(_pStart, _val) WriteEF1Byte(_pStart, _val) + +#define GET_WMM_QOS_INFO_FIELD_PARAMETERSET_COUNT(_pStart) LE_BITS_TO_1BYTE(_pStart, 0, 4) +#define SET_WMM_QOS_INFO_FIELD_PARAMETERSET_COUNT(_pStart, _val) SET_BITS_TO_LE_1BYTE(_pStart, 0, 4, _val) + +#define GET_WMM_QOS_INFO_FIELD_AP_UAPSD(_pStart) LE_BITS_TO_1BYTE(_pStart, 7, 1) +#define SET_WMM_QOS_INFO_FIELD_AP_UAPSD(_pStart, _val) SET_BITS_TO_LE_1BYTE(_pStart, 7, 1, _val) + +#define GET_WMM_QOS_INFO_FIELD_STA_AC_VO_UAPSD(_pStart) LE_BITS_TO_1BYTE(_pStart, 0, 1) +#define SET_WMM_QOS_INFO_FIELD_STA_AC_VO_UAPSD(_pStart, _val) SET_BITS_TO_LE_1BYTE(_pStart, 0, 1, _val) + +#define GET_WMM_QOS_INFO_FIELD_STA_AC_VI_UAPSD(_pStart) LE_BITS_TO_1BYTE(_pStart, 1, 1) +#define SET_WMM_QOS_INFO_FIELD_STA_AC_VI_UAPSD(_pStart, _val) SET_BITS_TO_LE_1BYTE(_pStart, 1, 1, _val) + +#define GET_WMM_QOS_INFO_FIELD_STA_AC_BE_UAPSD(_pStart) LE_BITS_TO_1BYTE(_pStart, 2, 1) +#define SET_WMM_QOS_INFO_FIELD_STA_AC_BE_UAPSD(_pStart, _val) SET_BITS_TO_LE_1BYTE(_pStart, 2, 1, _val) + +#define GET_WMM_QOS_INFO_FIELD_STA_AC_BK_UAPSD(_pStart) LE_BITS_TO_1BYTE(_pStart, 3, 1) +#define SET_WMM_QOS_INFO_FIELD_STA_AC_BK_UAPSD(_pStart, _val) SET_BITS_TO_LE_1BYTE(_pStart, 3, 1, _val) + +#define GET_WMM_QOS_INFO_FIELD_STA_MAX_SP_LEN(_pStart) LE_BITS_TO_1BYTE(_pStart, 5, 2) +#define SET_WMM_QOS_INFO_FIELD_STA_MAX_SP_LEN(_pStart, _val) SET_BITS_TO_LE_1BYTE(_pStart, 5, 2, _val) + + +#define WMM_INFO_ELEMENT_SIZE 7 + +#define GET_WMM_INFO_ELE_OUI(_pStart) ((u8 *)(_pStart)) +#define SET_WMM_INFO_ELE_OUI(_pStart, _pVal) PlatformMoveMemory(_pStart, _pVal, 3); + +#define GET_WMM_INFO_ELE_OUI_TYPE(_pStart) ( EF1Byte( *((u8 *)(_pStart)+3) ) ) +#define SET_WMM_INFO_ELE_OUI_TYPE(_pStart, _val) ( *((u8 *)(_pStart)+3) = EF1Byte(_val) ) + +#define GET_WMM_INFO_ELE_OUI_SUBTYPE(_pStart) ( EF1Byte( *((u8 *)(_pStart)+4) ) ) +#define SET_WMM_INFO_ELE_OUI_SUBTYPE(_pStart, _val) ( *((u8 *)(_pStart)+4) = EF1Byte(_val) ) + +#define GET_WMM_INFO_ELE_VERSION(_pStart) ( EF1Byte( *((u8 *)(_pStart)+5) ) ) +#define SET_WMM_INFO_ELE_VERSION(_pStart, _val) ( *((u8 *)(_pStart)+5) = EF1Byte(_val) ) + +#define GET_WMM_INFO_ELE_QOS_INFO_FIELD(_pStart) ( EF1Byte( *((u8 *)(_pStart)+6) ) ) +#define SET_WMM_INFO_ELE_QOS_INFO_FIELD(_pStart, _val) ( *((u8 *)(_pStart)+6) = EF1Byte(_val) ) + + + +#define GET_WMM_AC_PARAM_AIFSN(_pStart) ( (u8)LE_BITS_TO_4BYTE(_pStart, 0, 4) ) +#define SET_WMM_AC_PARAM_AIFSN(_pStart, _val) SET_BITS_TO_LE_4BYTE(_pStart, 0, 4, _val) + +#define GET_WMM_AC_PARAM_ACM(_pStart) ( (u8)LE_BITS_TO_4BYTE(_pStart, 4, 1) ) +#define SET_WMM_AC_PARAM_ACM(_pStart, _val) SET_BITS_TO_LE_4BYTE(_pStart, 4, 1, _val) + +#define GET_WMM_AC_PARAM_ACI(_pStart) ( (u8)LE_BITS_TO_4BYTE(_pStart, 5, 2) ) +#define SET_WMM_AC_PARAM_ACI(_pStart, _val) SET_BITS_TO_LE_4BYTE(_pStart, 5, 2, _val) + +#define GET_WMM_AC_PARAM_ACI_AIFSN(_pStart) ( (u8)LE_BITS_TO_4BYTE(_pStart, 0, 8) ) +#define SET_WMM_AC_PARAM_ACI_AIFSN(_pStart, _val) SET_BTIS_TO_LE_4BYTE(_pStart, 0, 8, _val) + +#define GET_WMM_AC_PARAM_ECWMIN(_pStart) ( (u8)LE_BITS_TO_4BYTE(_pStart, 8, 4) ) +#define SET_WMM_AC_PARAM_ECWMIN(_pStart, _val) SET_BITS_TO_LE_4BYTE(_pStart, 8, 4, _val) + +#define GET_WMM_AC_PARAM_ECWMAX(_pStart) ( (u8)LE_BITS_TO_4BYTE(_pStart, 12, 4) ) +#define SET_WMM_AC_PARAM_ECWMAX(_pStart, _val) SET_BITS_TO_LE_4BYTE(_pStart, 12, 4, _val) + +#define GET_WMM_AC_PARAM_TXOP_LIMIT(_pStart) ( (u16)LE_BITS_TO_4BYTE(_pStart, 16, 16) ) +#define SET_WMM_AC_PARAM_TXOP_LIMIT(_pStart, _val) SET_BITS_TO_LE_4BYTE(_pStart, 16, 16, _val) + + + + +#define GET_WMM_PARAM_ELE_OUI(_pStart) ((u8 *)(_pStart)) +#define SET_WMM_PARAM_ELE_OUI(_pStart, _pVal) PlatformMoveMemory(_pStart, _pVal, 3) + +#define GET_WMM_PARAM_ELE_OUI_TYPE(_pStart) ( EF1Byte( *((u8 *)(_pStart)+3) ) ) +#define SET_WMM_PARAM_ELE_OUI_TYPE(_pStart, _val) ( *((u8 *)(_pStart)+3) = EF1Byte(_val) ) + +#define GET_WMM_PARAM_ELE_OUI_SUBTYPE(_pStart) ( EF1Byte( *((u8 *)(_pStart)+4) ) ) +#define SET_WMM_PARAM_ELE_OUI_SUBTYPE(_pStart, _val) ( *((u8 *)(_pStart)+4) = EF1Byte(_val) ) + +#define GET_WMM_PARAM_ELE_VERSION(_pStart) ( EF1Byte( *((u8 *)(_pStart)+5) ) ) +#define SET_WMM_PARAM_ELE_VERSION(_pStart, _val) ( *((u8 *)(_pStart)+5) = EF1Byte(_val) ) + +#define GET_WMM_PARAM_ELE_QOS_INFO_FIELD(_pStart) ( EF1Byte( *((u8 *)(_pStart)+6) ) ) +#define SET_WMM_PARAM_ELE_QOS_INFO_FIELD(_pStart, _val) ( *((u8 *)(_pStart)+6) = EF1Byte(_val) ) + +#define GET_WMM_PARAM_ELE_AC_PARAM(_pStart) ( (u8 *)(_pStart)+8 ) +#define SET_WMM_PARAM_ELE_AC_PARAM(_pStart, _pVal) PlatformMoveMemory((_pStart)+8, _pVal, 16) +#endif + +// +// QoS Control Field +// Ref: +// 1. WMM spec 2.1.6: QoS Control Field, p.9. +// 2. 802.11e/D13.0 7.1.3.5, p.26. +// +typedef union _QOS_CTRL_FIELD{ + u8 charData[2]; + u16 shortData; + + // WMM spec + struct + { + u8 UP:3; + u8 usRsvd1:1; + u8 EOSP:1; + u8 AckPolicy:2; + u8 usRsvd2:1; + u8 ucRsvdByte; + }WMM; + + // 802.11e: QoS data type frame sent by non-AP QSTAs. + struct + { + u8 TID:4; + u8 bIsQsize:1;// 0: BIT[8:15] is TXOP Duration Requested, 1: BIT[8:15] is Queue Size. + u8 AckPolicy:2; + u8 usRsvd:1; + u8 TxopOrQsize; // (BIT4=0)TXOP Duration Requested or (BIT4=1)Queue Size. + }BySta; + + // 802.11e: QoS data, QoS Null, and QoS Data+CF-Ack frames sent by HC. + struct + { + u8 TID:4; + u8 EOSP:1; + u8 AckPolicy:2; + u8 usRsvd:1; + u8 PSBufState; // QAP PS Buffer State. + }ByHc_Data; + + // 802.11e: QoS (+) CF-Poll frames sent by HC. + struct + { + u8 TID:4; + u8 EOSP:1; + u8 AckPolicy:2; + u8 usRsvd:1; + u8 TxopLimit; // TXOP Limit. + }ByHc_CFP; + +}QOS_CTRL_FIELD, *PQOS_CTRL_FIELD; + + +// +// QoS Info Field +// Ref: +// 1. WMM spec 2.2.1: WME Information Element, p.11. +// 2. 8185 QoS code: QOS_INFO [def. in QoS_mp.h] +// +typedef union _QOS_INFO_FIELD{ + u8 charData; + + struct + { + u8 ucParameterSetCount:4; + u8 ucReserved:4; + }WMM; + + struct + { + //Ref WMM_Specification_1-1.pdf, 2006-06-13 Isaiah + u8 ucAC_VO_UAPSD:1; + u8 ucAC_VI_UAPSD:1; + u8 ucAC_BE_UAPSD:1; + u8 ucAC_BK_UAPSD:1; + u8 ucReserved1:1; + u8 ucMaxSPLen:2; + u8 ucReserved2:1; + + }ByWmmPsSta; + + struct + { + //Ref WMM_Specification_1-1.pdf, 2006-06-13 Isaiah + u8 ucParameterSetCount:4; + u8 ucReserved:3; + u8 ucApUapsd:1; + }ByWmmPsAp; + + struct + { + u8 ucAC3_UAPSD:1; + u8 ucAC2_UAPSD:1; + u8 ucAC1_UAPSD:1; + u8 ucAC0_UAPSD:1; + u8 ucQAck:1; + u8 ucMaxSPLen:2; + u8 ucMoreDataAck:1; + } By11eSta; + + struct + { + u8 ucParameterSetCount:4; + u8 ucQAck:1; + u8 ucQueueReq:1; + u8 ucTXOPReq:1; + u8 ucReserved:1; + } By11eAp; + + struct + { + u8 ucReserved1:4; + u8 ucQAck:1; + u8 ucReserved2:2; + u8 ucMoreDataAck:1; + } ByWmmsaSta; + + struct + { + u8 ucReserved1:4; + u8 ucQAck:1; + u8 ucQueueReq:1; + u8 ucTXOPReq:1; + u8 ucReserved2:1; + } ByWmmsaAp; + + struct + { + u8 ucAC3_UAPSD:1; + u8 ucAC2_UAPSD:1; + u8 ucAC1_UAPSD:1; + u8 ucAC0_UAPSD:1; + u8 ucQAck:1; + u8 ucMaxSPLen:2; + u8 ucMoreDataAck:1; + } ByAllSta; + + struct + { + u8 ucParameterSetCount:4; + u8 ucQAck:1; + u8 ucQueueReq:1; + u8 ucTXOPReq:1; + u8 ucApUapsd:1; + } ByAllAp; + +}QOS_INFO_FIELD, *PQOS_INFO_FIELD; + +#if 0 +// +// WMM Information Element +// Ref: WMM spec 2.2.1: WME Information Element, p.10. +// +typedef struct _WMM_INFO_ELEMENT{ +// u8 ElementID; +// u8 Length; + u8 OUI[3]; + u8 OUI_Type; + u8 OUI_SubType; + u8 Version; + QOS_INFO_FIELD QosInfo; +}WMM_INFO_ELEMENT, *PWMM_INFO_ELEMENT; +#endif + +// +// ACI to AC coding. +// Ref: WMM spec 2.2.2: WME Parameter Element, p.13. +// +// AC_CODING is redefined for enum can't be ++, | under C++ compiler, 2006.05.17, by rcnjko. +//typedef enum _AC_CODING{ +// AC0_BE = 0, // ACI: 0x00 // Best Effort +// AC1_BK = 1, // ACI: 0x01 // Background +// AC2_VI = 2, // ACI: 0x10 // Video +// AC3_VO = 3, // ACI: 0x11 // Voice +// AC_MAX = 4, // Max: define total number; Should not to be used as a real enum. +//}AC_CODING,*PAC_CODING; +// +typedef u32 AC_CODING; +#define AC0_BE 0 // ACI: 0x00 // Best Effort +#define AC1_BK 1 // ACI: 0x01 // Background +#define AC2_VI 2 // ACI: 0x10 // Video +#define AC3_VO 3 // ACI: 0x11 // Voice +#define AC_MAX 4 // Max: define total number; Should not to be used as a real enum. + +// +// ACI/AIFSN Field. +// Ref: WMM spec 2.2.2: WME Parameter Element, p.12. +// +typedef union _ACI_AIFSN{ + u8 charData; + + struct + { + u8 AIFSN:4; + u8 ACM:1; + u8 ACI:2; + u8 Reserved:1; + }f; // Field +}ACI_AIFSN, *PACI_AIFSN; + +// +// ECWmin/ECWmax field. +// Ref: WMM spec 2.2.2: WME Parameter Element, p.13. +// +typedef union _ECW{ + u8 charData; + struct + { + u8 ECWmin:4; + u8 ECWmax:4; + }f; // Field +}ECW, *PECW; + +// +// AC Parameters Record Format. +// Ref: WMM spec 2.2.2: WME Parameter Element, p.12. +// +typedef union _AC_PARAM{ + u32 longData; + u8 charData[4]; + + struct + { + ACI_AIFSN AciAifsn; + ECW Ecw; + u16 TXOPLimit; + }f; // Field +}AC_PARAM, *PAC_PARAM; + + + +// +// QoS element subtype +// +typedef enum _QOS_ELE_SUBTYPE{ + QOSELE_TYPE_INFO = 0x00, // 0x00: Information element + QOSELE_TYPE_PARAM = 0x01, // 0x01: parameter element +}QOS_ELE_SUBTYPE,*PQOS_ELE_SUBTYPE; + + +// +// Direction Field Values. +// Ref: WMM spec 2.2.11: WME TSPEC Element, p.18. +// +typedef enum _DIRECTION_VALUE{ + DIR_UP = 0, // 0x00 // UpLink + DIR_DOWN = 1, // 0x01 // DownLink + DIR_DIRECT = 2, // 0x10 // DirectLink + DIR_BI_DIR = 3, // 0x11 // Bi-Direction +}DIRECTION_VALUE,*PDIRECTION_VALUE; + + +// +// TS Info field in WMM TSPEC Element. +// Ref: +// 1. WMM spec 2.2.11: WME TSPEC Element, p.18. +// 2. 8185 QoS code: QOS_TSINFO [def. in QoS_mp.h] +// +typedef union _QOS_TSINFO{ + u8 charData[3]; + struct { + u8 ucTrafficType:1; //WMM is reserved + u8 ucTSID:4; + u8 ucDirection:2; + u8 ucAccessPolicy:2; //WMM: bit8=0, bit7=1 + u8 ucAggregation:1; //WMM is reserved + u8 ucPSB:1; //WMMSA is APSD + u8 ucUP:3; + u8 ucTSInfoAckPolicy:2; //WMM is reserved + u8 ucSchedule:1; //WMM is reserved + u8 ucReserved:7; + }field; +}QOS_TSINFO, *PQOS_TSINFO; + +// +// WMM TSPEC Body. +// Ref: WMM spec 2.2.11: WME TSPEC Element, p.16. +// +typedef union _TSPEC_BODY{ + u8 charData[55]; + + struct + { + QOS_TSINFO TSInfo; //u8 TSInfo[3]; + u16 NominalMSDUsize; + u16 MaxMSDUsize; + u32 MinServiceItv; + u32 MaxServiceItv; + u32 InactivityItv; + u32 SuspenItv; + u32 ServiceStartTime; + u32 MinDataRate; + u32 MeanDataRate; + u32 PeakDataRate; + u32 MaxBurstSize; + u32 DelayBound; + u32 MinPhyRate; + u16 SurplusBandwidthAllowance; + u16 MediumTime; + } f; // Field +}TSPEC_BODY, *PTSPEC_BODY; + + +// +// WMM TSPEC Element. +// Ref: WMM spec 2.2.11: WME TSPEC Element, p.16. +// +typedef struct _WMM_TSPEC{ + u8 ID; + u8 Length; + u8 OUI[3]; + u8 OUI_Type; + u8 OUI_SubType; + u8 Version; + TSPEC_BODY Body; +} WMM_TSPEC, *PWMM_TSPEC; + +// +// ACM implementation method. +// Annie, 2005-12-13. +// +typedef enum _ACM_METHOD{ + eAcmWay0_SwAndHw = 0, // By SW and HW. + eAcmWay1_HW = 1, // By HW. + eAcmWay2_SW = 2, // By SW. +}ACM_METHOD,*PACM_METHOD; + + +typedef struct _ACM{ +// u8 RegEnableACM; + u64 UsedTime; + u64 MediumTime; + u8 HwAcmCtl; // TRUE: UsedTime exceed => Do NOT USE this AC. It wll be written to ACM_CONTROL(0xBF BIT 0/1/2 in 8185B). +}ACM, *PACM; + +typedef u8 AC_UAPSD, *PAC_UAPSD; + +#define GET_VO_UAPSD(_apsd) ((_apsd) & BIT0) +#define SET_VO_UAPSD(_apsd) ((_apsd) |= BIT0) + +#define GET_VI_UAPSD(_apsd) ((_apsd) & BIT1) +#define SET_VI_UAPSD(_apsd) ((_apsd) |= BIT1) + +#define GET_BK_UAPSD(_apsd) ((_apsd) & BIT2) +#define SET_BK_UAPSD(_apsd) ((_apsd) |= BIT2) + +#define GET_BE_UAPSD(_apsd) ((_apsd) & BIT3) +#define SET_BE_UAPSD(_apsd) ((_apsd) |= BIT3) + + +//typedef struct _TCLASS{ +// TODO +//} TCLASS, *PTCLASS; +typedef union _QOS_TCLAS{ + + struct _TYPE_GENERAL{ + u8 Priority; + u8 ClassifierType; + u8 Mask; + } TYPE_GENERAL; + + struct _TYPE0_ETH{ + u8 Priority; + u8 ClassifierType; + u8 Mask; + u8 SrcAddr[6]; + u8 DstAddr[6]; + u16 Type; + } TYPE0_ETH; + + struct _TYPE1_IPV4{ + u8 Priority; + u8 ClassifierType; + u8 Mask; + u8 Version; + u8 SrcIP[4]; + u8 DstIP[4]; + u16 SrcPort; + u16 DstPort; + u8 DSCP; + u8 Protocol; + u8 Reserved; + } TYPE1_IPV4; + + struct _TYPE1_IPV6{ + u8 Priority; + u8 ClassifierType; + u8 Mask; + u8 Version; + u8 SrcIP[16]; + u8 DstIP[16]; + u16 SrcPort; + u16 DstPort; + u8 FlowLabel[3]; + } TYPE1_IPV6; + + struct _TYPE2_8021Q{ + u8 Priority; + u8 ClassifierType; + u8 Mask; + u16 TagType; + } TYPE2_8021Q; +} QOS_TCLAS, *PQOS_TCLAS; + +//typedef struct _WMM_TSTREAM{ +// +//- TSPEC +//- AC (which to mapping) +//} WMM_TSTREAM, *PWMM_TSTREAM; +typedef struct _QOS_TSTREAM{ + u8 AC; + WMM_TSPEC TSpec; + QOS_TCLAS TClass; +} QOS_TSTREAM, *PQOS_TSTREAM; + +//typedef struct _U_APSD{ +//- TriggerEnable [4] +//- MaxSPLength +//- HighestAcBuffered +//} U_APSD, *PU_APSD; + +//joseph TODO: +// UAPSD function should be implemented by 2 data structure +// "Qos control field" and "Qos info field" +//typedef struct _QOS_UAPSD{ +// u8 bTriggerEnable[4]; +// u8 MaxSPLength; +// u8 HighestBufAC; +//} QOS_UAPSD, *PQOS_APSD; + +//---------------------------------------------------------------------------- +// 802.11 Management frame Status Code field +//---------------------------------------------------------------------------- +typedef struct _OCTET_STRING{ + u8 *Octet; + u16 Length; +}OCTET_STRING, *POCTET_STRING; +#if 0 +#define FillOctetString(_os,_octet,_len) \ + (_os).Octet=(u8 *)(_octet); \ + (_os).Length=(_len); + +#define WMM_ELEM_HDR_LEN 6 +#define WMMElemSkipHdr(_osWMMElem) \ + (_osWMMElem).Octet += WMM_ELEM_HDR_LEN; \ + (_osWMMElem).Length -= WMM_ELEM_HDR_LEN; +#endif +// +// STA QoS data. +// Ref: DOT11_QOS in 8185 code. [def. in QoS_mp.h] +// +typedef struct _STA_QOS{ + //DECLARE_RT_OBJECT(STA_QOS); + u8 WMMIEBuf[MAX_WMMELE_LENGTH]; + u8* WMMIE; + + // Part 1. Self QoS Mode. + QOS_MODE QosCapability; //QoS Capability, 2006-06-14 Isaiah + QOS_MODE CurrentQosMode; + + // For WMM Power Save Mode : + // ACs are trigger/delivery enabled or legacy power save enabled. 2006-06-13 Isaiah + AC_UAPSD b4ac_Uapsd; //VoUapsd(bit0), ViUapsd(bit1), BkUapsd(bit2), BeUapsd(bit3), + AC_UAPSD Curr4acUapsd; + u8 bInServicePeriod; + u8 MaxSPLength; + int NumBcnBeforeTrigger; + + // Part 2. EDCA Parameter (perAC) + u8 * pWMMInfoEle; + u8 WMMParamEle[WMM_PARAM_ELEMENT_SIZE]; + u8 WMMPELength; + + // <Bruce_Note> + //2 ToDo: remove the Qos Info Field and replace it by the above WMM Info element. + // By Bruce, 2008-01-30. + // Part 2. EDCA Parameter (perAC) + QOS_INFO_FIELD QosInfoField_STA; // Maintained by STA + QOS_INFO_FIELD QosInfoField_AP; // Retrieved from AP + + AC_PARAM CurAcParameters[4]; + + // Part 3. ACM + ACM acm[4]; + ACM_METHOD AcmMethod; + + // Part 4. Per TID (Part 5: TCLASS will be described by TStream) + QOS_TSTREAM TStream[16]; + WMM_TSPEC TSpec; + + u32 QBssWirelessMode; + + // No Ack Setting + u8 bNoAck; + + // Enable/Disable Rx immediate BA capability. + u8 bEnableRxImmBA; + +}STA_QOS, *PSTA_QOS; + +// +// BSS QOS data. +// Ref: BssDscr in 8185 code. [def. in BssDscr.h] +// +typedef struct _BSS_QOS{ + QOS_MODE bdQoSMode; + + u8 bdWMMIEBuf[MAX_WMMELE_LENGTH]; + u8* bdWMMIE; + + QOS_ELE_SUBTYPE EleSubType; + + u8 * pWMMInfoEle; + u8 * pWMMParamEle; + + QOS_INFO_FIELD QosInfoField; + AC_PARAM AcParameter[4]; +}BSS_QOS, *PBSS_QOS; + + +// +// Ref: sQoSCtlLng and QoSCtl definition in 8185 QoS code. +//#define QoSCtl (( (Adapter->bRegQoS) && (Adapter->dot11QoS.QoSMode &(QOS_EDCA|QOS_HCCA)) ) ?sQoSCtlLng:0) +// +#define sQoSCtlLng 2 +#define QOS_CTRL_LEN(_QosMode) ((_QosMode > QOS_DISABLE)? sQoSCtlLng : 0) + + +//Added by joseph +//UP Mapping to AC, using in MgntQuery_SequenceNumber() and maybe for DSCP +//#define UP2AC(up) ((up<3)?((up==0)?1:0):(up>>1)) +#define IsACValid(ac) ((ac<=7 )?true:false ) + +#endif // #ifndef __INC_QOS_TYPE_H diff --git a/drivers/staging/rtl8192su/ieee80211/rtl819x_TS.h b/drivers/staging/rtl8192su/ieee80211/rtl819x_TS.h new file mode 100644 index 000000000000..baaac2149de1 --- /dev/null +++ b/drivers/staging/rtl8192su/ieee80211/rtl819x_TS.h @@ -0,0 +1,56 @@ +#ifndef _TSTYPE_H_ +#define _TSTYPE_H_ +#include "rtl819x_Qos.h" +#define TS_SETUP_TIMEOUT 60 // In millisecond +#define TS_INACT_TIMEOUT 60 +#define TS_ADDBA_DELAY 60 + +#define TOTAL_TS_NUM 16 +#define TCLAS_NUM 4 + +// This define the Tx/Rx directions +typedef enum _TR_SELECT { + TX_DIR = 0, + RX_DIR = 1, +} TR_SELECT, *PTR_SELECT; + +typedef struct _TS_COMMON_INFO{ + struct list_head List; + struct timer_list SetupTimer; + struct timer_list InactTimer; + u8 Addr[6]; + TSPEC_BODY TSpec; + QOS_TCLAS TClass[TCLAS_NUM]; + u8 TClasProc; + u8 TClasNum; +} TS_COMMON_INFO, *PTS_COMMON_INFO; + +typedef struct _TX_TS_RECORD{ + TS_COMMON_INFO TsCommonInfo; + u16 TxCurSeq; + BA_RECORD TxPendingBARecord; // For BA Originator + BA_RECORD TxAdmittedBARecord; // For BA Originator +// QOS_DL_RECORD DLRecord; + u8 bAddBaReqInProgress; + u8 bAddBaReqDelayed; + u8 bUsingBa; + struct timer_list TsAddBaTimer; + u8 num; +} TX_TS_RECORD, *PTX_TS_RECORD; + +typedef struct _RX_TS_RECORD { + TS_COMMON_INFO TsCommonInfo; + u16 RxIndicateSeq; + u16 RxTimeoutIndicateSeq; + struct list_head RxPendingPktList; + struct timer_list RxPktPendingTimer; + BA_RECORD RxAdmittedBARecord; // For BA Recepient + u16 RxLastSeqNum; + u8 RxLastFragNum; + u8 num; +// QOS_DL_RECORD DLRecord; +} RX_TS_RECORD, *PRX_TS_RECORD; + + +#endif + diff --git a/drivers/staging/rtl8192su/ieee80211/rtl819x_TSProc.c b/drivers/staging/rtl8192su/ieee80211/rtl819x_TSProc.c new file mode 100644 index 000000000000..6fb7033ed360 --- /dev/null +++ b/drivers/staging/rtl8192su/ieee80211/rtl819x_TSProc.c @@ -0,0 +1,667 @@ +#include "ieee80211.h" +#include <linux/etherdevice.h> +#include "rtl819x_TS.h" + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) +#define list_for_each_entry_safe(pos, n, head, member) \ + for (pos = list_entry((head)->next, typeof(*pos), member), \ + n = list_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = list_entry(n->member.next, typeof(*n), member)) +#endif +void TsSetupTimeOut(unsigned long data) +{ + // Not implement yet + // This is used for WMMSA and ACM , that would send ADDTSReq frame. +} + +void TsInactTimeout(unsigned long data) +{ + // Not implement yet + // This is used for WMMSA and ACM. + // This function would be call when TS is no Tx/Rx for some period of time. +} + +/******************************************************************************************************************** + *function: I still not understand this function, so wait for further implementation + * input: unsigned long data //acturally we send TX_TS_RECORD or RX_TS_RECORD to these timer + * return: NULL + * notice: +********************************************************************************************************************/ +#if 1 +void RxPktPendingTimeout(unsigned long data) +{ + PRX_TS_RECORD pRxTs = (PRX_TS_RECORD)data; + struct ieee80211_device *ieee = container_of(pRxTs, struct ieee80211_device, RxTsRecord[pRxTs->num]); + + PRX_REORDER_ENTRY pReorderEntry = NULL; + + //u32 flags = 0; + unsigned long flags = 0; + struct ieee80211_rxb *stats_IndicateArray[REORDER_WIN_SIZE]; + u8 index = 0; + bool bPktInBuf = false; + + + spin_lock_irqsave(&(ieee->reorder_spinlock), flags); + //PlatformAcquireSpinLock(Adapter, RT_RX_SPINLOCK); + IEEE80211_DEBUG(IEEE80211_DL_REORDER,"==================>%s()\n",__FUNCTION__); + if(pRxTs->RxTimeoutIndicateSeq != 0xffff) + { + // Indicate the pending packets sequentially according to SeqNum until meet the gap. + while(!list_empty(&pRxTs->RxPendingPktList)) + { + pReorderEntry = (PRX_REORDER_ENTRY)list_entry(pRxTs->RxPendingPktList.prev,RX_REORDER_ENTRY,List); + if(index == 0) + pRxTs->RxIndicateSeq = pReorderEntry->SeqNum; + + if( SN_LESS(pReorderEntry->SeqNum, pRxTs->RxIndicateSeq) || + SN_EQUAL(pReorderEntry->SeqNum, pRxTs->RxIndicateSeq) ) + { + list_del_init(&pReorderEntry->List); + + if(SN_EQUAL(pReorderEntry->SeqNum, pRxTs->RxIndicateSeq)) + pRxTs->RxIndicateSeq = (pRxTs->RxIndicateSeq + 1) % 4096; + + IEEE80211_DEBUG(IEEE80211_DL_REORDER,"RxPktPendingTimeout(): IndicateSeq: %d\n", pReorderEntry->SeqNum); + stats_IndicateArray[index] = pReorderEntry->prxb; + index++; + + list_add_tail(&pReorderEntry->List, &ieee->RxReorder_Unused_List); + } + else + { + bPktInBuf = true; + break; + } + } + } + + if(index>0) + { + // Set RxTimeoutIndicateSeq to 0xffff to indicate no pending packets in buffer now. + pRxTs->RxTimeoutIndicateSeq = 0xffff; + + // Indicate packets + if(index > REORDER_WIN_SIZE){ + IEEE80211_DEBUG(IEEE80211_DL_ERR, "RxReorderIndicatePacket(): Rx Reorer buffer full!! \n"); + spin_unlock_irqrestore(&(ieee->reorder_spinlock), flags); + return; + } + ieee80211_indicate_packets(ieee, stats_IndicateArray, index); + bPktInBuf = false; + + } + + if(bPktInBuf && (pRxTs->RxTimeoutIndicateSeq==0xffff)) + { + pRxTs->RxTimeoutIndicateSeq = pRxTs->RxIndicateSeq; +#if 0 + if(timer_pending(&pTS->RxPktPendingTimer)) + del_timer_sync(&pTS->RxPktPendingTimer); + pTS->RxPktPendingTimer.expires = jiffies + MSECS(pHTInfo->RxReorderPendingTime); + add_timer(&pTS->RxPktPendingTimer); +#else + mod_timer(&pRxTs->RxPktPendingTimer, jiffies + MSECS(ieee->pHTInfo->RxReorderPendingTime)); +#endif + +#if 0 + if(timer_pending(&pRxTs->RxPktPendingTimer)) + del_timer_sync(&pRxTs->RxPktPendingTimer); + pRxTs->RxPktPendingTimer.expires = jiffies + ieee->pHTInfo->RxReorderPendingTime; + add_timer(&pRxTs->RxPktPendingTimer); +#endif + } + spin_unlock_irqrestore(&(ieee->reorder_spinlock), flags); + //PlatformReleaseSpinLock(Adapter, RT_RX_SPINLOCK); +} +#endif + +/******************************************************************************************************************** + *function: Add BA timer function + * input: unsigned long data //acturally we send TX_TS_RECORD or RX_TS_RECORD to these timer + * return: NULL + * notice: +********************************************************************************************************************/ +void TsAddBaProcess(unsigned long data) +{ + PTX_TS_RECORD pTxTs = (PTX_TS_RECORD)data; + u8 num = pTxTs->num; + struct ieee80211_device *ieee = container_of(pTxTs, struct ieee80211_device, TxTsRecord[num]); + + TsInitAddBA(ieee, pTxTs, BA_POLICY_IMMEDIATE, false); + IEEE80211_DEBUG(IEEE80211_DL_BA, "TsAddBaProcess(): ADDBA Req is started!! \n"); +} + + +void ResetTsCommonInfo(PTS_COMMON_INFO pTsCommonInfo) +{ + memset(pTsCommonInfo->Addr, 0, 6); + memset(&pTsCommonInfo->TSpec, 0, sizeof(TSPEC_BODY)); + memset(&pTsCommonInfo->TClass, 0, sizeof(QOS_TCLAS)*TCLAS_NUM); + pTsCommonInfo->TClasProc = 0; + pTsCommonInfo->TClasNum = 0; +} + +void ResetTxTsEntry(PTX_TS_RECORD pTS) +{ + ResetTsCommonInfo(&pTS->TsCommonInfo); + pTS->TxCurSeq = 0; + pTS->bAddBaReqInProgress = false; + pTS->bAddBaReqDelayed = false; + pTS->bUsingBa = false; + ResetBaEntry(&pTS->TxAdmittedBARecord); //For BA Originator + ResetBaEntry(&pTS->TxPendingBARecord); +} + +void ResetRxTsEntry(PRX_TS_RECORD pTS) +{ + ResetTsCommonInfo(&pTS->TsCommonInfo); + pTS->RxIndicateSeq = 0xffff; // This indicate the RxIndicateSeq is not used now!! + pTS->RxTimeoutIndicateSeq = 0xffff; // This indicate the RxTimeoutIndicateSeq is not used now!! + ResetBaEntry(&pTS->RxAdmittedBARecord); // For BA Recepient +} + +void TSInitialize(struct ieee80211_device *ieee) +{ + PTX_TS_RECORD pTxTS = ieee->TxTsRecord; + PRX_TS_RECORD pRxTS = ieee->RxTsRecord; + PRX_REORDER_ENTRY pRxReorderEntry = ieee->RxReorderEntry; + u8 count = 0; + IEEE80211_DEBUG(IEEE80211_DL_TS, "==========>%s()\n", __FUNCTION__); + // Initialize Tx TS related info. + INIT_LIST_HEAD(&ieee->Tx_TS_Admit_List); + INIT_LIST_HEAD(&ieee->Tx_TS_Pending_List); + INIT_LIST_HEAD(&ieee->Tx_TS_Unused_List); + + for(count = 0; count < TOTAL_TS_NUM; count++) + { + // + pTxTS->num = count; + // The timers for the operation of Traffic Stream and Block Ack. + // DLS related timer will be add here in the future!! + init_timer(&pTxTS->TsCommonInfo.SetupTimer); + pTxTS->TsCommonInfo.SetupTimer.data = (unsigned long)pTxTS; + pTxTS->TsCommonInfo.SetupTimer.function = TsSetupTimeOut; + + init_timer(&pTxTS->TsCommonInfo.InactTimer); + pTxTS->TsCommonInfo.InactTimer.data = (unsigned long)pTxTS; + pTxTS->TsCommonInfo.InactTimer.function = TsInactTimeout; + + init_timer(&pTxTS->TsAddBaTimer); + pTxTS->TsAddBaTimer.data = (unsigned long)pTxTS; + pTxTS->TsAddBaTimer.function = TsAddBaProcess; + + init_timer(&pTxTS->TxPendingBARecord.Timer); + pTxTS->TxPendingBARecord.Timer.data = (unsigned long)pTxTS; + pTxTS->TxPendingBARecord.Timer.function = BaSetupTimeOut; + + init_timer(&pTxTS->TxAdmittedBARecord.Timer); + pTxTS->TxAdmittedBARecord.Timer.data = (unsigned long)pTxTS; + pTxTS->TxAdmittedBARecord.Timer.function = TxBaInactTimeout; + + ResetTxTsEntry(pTxTS); + list_add_tail(&pTxTS->TsCommonInfo.List, &ieee->Tx_TS_Unused_List); + pTxTS++; + } + + // Initialize Rx TS related info. + INIT_LIST_HEAD(&ieee->Rx_TS_Admit_List); + INIT_LIST_HEAD(&ieee->Rx_TS_Pending_List); + INIT_LIST_HEAD(&ieee->Rx_TS_Unused_List); + for(count = 0; count < TOTAL_TS_NUM; count++) + { + pRxTS->num = count; + INIT_LIST_HEAD(&pRxTS->RxPendingPktList); + + init_timer(&pRxTS->TsCommonInfo.SetupTimer); + pRxTS->TsCommonInfo.SetupTimer.data = (unsigned long)pRxTS; + pRxTS->TsCommonInfo.SetupTimer.function = TsSetupTimeOut; + + init_timer(&pRxTS->TsCommonInfo.InactTimer); + pRxTS->TsCommonInfo.InactTimer.data = (unsigned long)pRxTS; + pRxTS->TsCommonInfo.InactTimer.function = TsInactTimeout; + + init_timer(&pRxTS->RxAdmittedBARecord.Timer); + pRxTS->RxAdmittedBARecord.Timer.data = (unsigned long)pRxTS; + pRxTS->RxAdmittedBARecord.Timer.function = RxBaInactTimeout; + + init_timer(&pRxTS->RxPktPendingTimer); + pRxTS->RxPktPendingTimer.data = (unsigned long)pRxTS; + pRxTS->RxPktPendingTimer.function = RxPktPendingTimeout; + + ResetRxTsEntry(pRxTS); + list_add_tail(&pRxTS->TsCommonInfo.List, &ieee->Rx_TS_Unused_List); + pRxTS++; + } + // Initialize unused Rx Reorder List. + INIT_LIST_HEAD(&ieee->RxReorder_Unused_List); +//#ifdef TO_DO_LIST + for(count = 0; count < REORDER_ENTRY_NUM; count++) + { + list_add_tail( &pRxReorderEntry->List,&ieee->RxReorder_Unused_List); + if(count == (REORDER_ENTRY_NUM-1)) + break; + pRxReorderEntry = &ieee->RxReorderEntry[count+1]; + } +//#endif + +} + +void AdmitTS(struct ieee80211_device *ieee, PTS_COMMON_INFO pTsCommonInfo, u32 InactTime) +{ + del_timer_sync(&pTsCommonInfo->SetupTimer); + del_timer_sync(&pTsCommonInfo->InactTimer); + + if(InactTime!=0) + mod_timer(&pTsCommonInfo->InactTimer, jiffies + MSECS(InactTime)); +} + + +PTS_COMMON_INFO SearchAdmitTRStream(struct ieee80211_device *ieee, u8* Addr, u8 TID, TR_SELECT TxRxSelect) +{ + //DIRECTION_VALUE dir; + u8 dir; + bool search_dir[4] = {0, 0, 0, 0}; + struct list_head* psearch_list; //FIXME + PTS_COMMON_INFO pRet = NULL; + if(ieee->iw_mode == IW_MODE_MASTER) //ap mode + { + if(TxRxSelect == TX_DIR) + { + search_dir[DIR_DOWN] = true; + search_dir[DIR_BI_DIR]= true; + } + else + { + search_dir[DIR_UP] = true; + search_dir[DIR_BI_DIR]= true; + } + } + else if(ieee->iw_mode == IW_MODE_ADHOC) + { + if(TxRxSelect == TX_DIR) + search_dir[DIR_UP] = true; + else + search_dir[DIR_DOWN] = true; + } + else + { + if(TxRxSelect == TX_DIR) + { + search_dir[DIR_UP] = true; + search_dir[DIR_BI_DIR]= true; + search_dir[DIR_DIRECT]= true; + } + else + { + search_dir[DIR_DOWN] = true; + search_dir[DIR_BI_DIR]= true; + search_dir[DIR_DIRECT]= true; + } + } + + if(TxRxSelect == TX_DIR) + psearch_list = &ieee->Tx_TS_Admit_List; + else + psearch_list = &ieee->Rx_TS_Admit_List; + + //for(dir = DIR_UP; dir <= DIR_BI_DIR; dir++) + for(dir = 0; dir <= DIR_BI_DIR; dir++) + { + if(search_dir[dir] ==false ) + continue; + list_for_each_entry(pRet, psearch_list, List){ + // IEEE80211_DEBUG(IEEE80211_DL_TS, "ADD:"MAC_FMT", TID:%d, dir:%d\n", MAC_ARG(pRet->Addr), pRet->TSpec.f.TSInfo.field.ucTSID, pRet->TSpec.f.TSInfo.field.ucDirection); + if (memcmp(pRet->Addr, Addr, 6) == 0) + if (pRet->TSpec.f.TSInfo.field.ucTSID == TID) + if(pRet->TSpec.f.TSInfo.field.ucDirection == dir) + { + // printk("Bingo! got it\n"); + break; + } + + } + if(&pRet->List != psearch_list) + break; + } + + if(&pRet->List != psearch_list){ + return pRet ; + } + else + return NULL; +} + +void MakeTSEntry( + PTS_COMMON_INFO pTsCommonInfo, + u8* Addr, + PTSPEC_BODY pTSPEC, + PQOS_TCLAS pTCLAS, + u8 TCLAS_Num, + u8 TCLAS_Proc + ) +{ + u8 count; + + if(pTsCommonInfo == NULL) + return; + + memcpy(pTsCommonInfo->Addr, Addr, 6); + + if(pTSPEC != NULL) + memcpy((u8*)(&(pTsCommonInfo->TSpec)), (u8*)pTSPEC, sizeof(TSPEC_BODY)); + + for(count = 0; count < TCLAS_Num; count++) + memcpy((u8*)(&(pTsCommonInfo->TClass[count])), (u8*)pTCLAS, sizeof(QOS_TCLAS)); + + pTsCommonInfo->TClasProc = TCLAS_Proc; + pTsCommonInfo->TClasNum = TCLAS_Num; +} + + +bool GetTs( + struct ieee80211_device* ieee, + PTS_COMMON_INFO *ppTS, + u8* Addr, + u8 TID, + TR_SELECT TxRxSelect, //Rx:1, Tx:0 + bool bAddNewTs + ) +{ + u8 UP = 0; + // + // We do not build any TS for Broadcast or Multicast stream. + // So reject these kinds of search here. + // + if(is_broadcast_ether_addr(Addr) || is_multicast_ether_addr(Addr)) + { + IEEE80211_DEBUG(IEEE80211_DL_ERR, "get TS for Broadcast or Multicast\n"); + return false; + } +#if 0 + if(ieee->pStaQos->CurrentQosMode == QOS_DISABLE) + { UP = 0; } //only use one TS + else if(ieee->pStaQos->CurrentQosMode & QOS_WMM) + { +#else + if (ieee->current_network.qos_data.supported == 0) + UP = 0; + else + { +#endif + // In WMM case: we use 4 TID only + if (!IsACValid(TID)) + { + IEEE80211_DEBUG(IEEE80211_DL_ERR, " in %s(), TID(%d) is not valid\n", __FUNCTION__, TID); + return false; + } + + switch(TID) + { + case 0: + case 3: + UP = 0; + break; + + case 1: + case 2: + UP = 2; + break; + + case 4: + case 5: + UP = 5; + break; + + case 6: + case 7: + UP = 7; + break; + } + } + + *ppTS = SearchAdmitTRStream( + ieee, + Addr, + UP, + TxRxSelect); + if(*ppTS != NULL) + { + return true; + } + else + { + if(bAddNewTs == false) + { + IEEE80211_DEBUG(IEEE80211_DL_TS, "add new TS failed(tid:%d)\n", UP); + return false; + } + else + { + // + // Create a new Traffic stream for current Tx/Rx + // This is for EDCA and WMM to add a new TS. + // For HCCA or WMMSA, TS cannot be addmit without negotiation. + // + TSPEC_BODY TSpec; + PQOS_TSINFO pTSInfo = &TSpec.f.TSInfo; + struct list_head* pUnusedList = + (TxRxSelect == TX_DIR)? + (&ieee->Tx_TS_Unused_List): + (&ieee->Rx_TS_Unused_List); + + struct list_head* pAddmitList = + (TxRxSelect == TX_DIR)? + (&ieee->Tx_TS_Admit_List): + (&ieee->Rx_TS_Admit_List); + + DIRECTION_VALUE Dir = (ieee->iw_mode == IW_MODE_MASTER)? + ((TxRxSelect==TX_DIR)?DIR_DOWN:DIR_UP): + ((TxRxSelect==TX_DIR)?DIR_UP:DIR_DOWN); + IEEE80211_DEBUG(IEEE80211_DL_TS, "to add Ts\n"); + if(!list_empty(pUnusedList)) + { + (*ppTS) = list_entry(pUnusedList->next, TS_COMMON_INFO, List); + list_del_init(&(*ppTS)->List); + if(TxRxSelect==TX_DIR) + { + PTX_TS_RECORD tmp = container_of(*ppTS, TX_TS_RECORD, TsCommonInfo); + ResetTxTsEntry(tmp); + } + else{ + PRX_TS_RECORD tmp = container_of(*ppTS, RX_TS_RECORD, TsCommonInfo); + ResetRxTsEntry(tmp); + } + + IEEE80211_DEBUG(IEEE80211_DL_TS, "to init current TS, UP:%d, Dir:%d, addr:"MAC_FMT"\n", UP, Dir, MAC_ARG(Addr)); + // Prepare TS Info releated field + pTSInfo->field.ucTrafficType = 0; // Traffic type: WMM is reserved in this field + pTSInfo->field.ucTSID = UP; // TSID + pTSInfo->field.ucDirection = Dir; // Direction: if there is DirectLink, this need additional consideration. + pTSInfo->field.ucAccessPolicy = 1; // Access policy + pTSInfo->field.ucAggregation = 0; // Aggregation + pTSInfo->field.ucPSB = 0; // Aggregation + pTSInfo->field.ucUP = UP; // User priority + pTSInfo->field.ucTSInfoAckPolicy = 0; // Ack policy + pTSInfo->field.ucSchedule = 0; // Schedule + + MakeTSEntry(*ppTS, Addr, &TSpec, NULL, 0, 0); + AdmitTS(ieee, *ppTS, 0); + list_add_tail(&((*ppTS)->List), pAddmitList); + // if there is DirectLink, we need to do additional operation here!! + + return true; + } + else + { + IEEE80211_DEBUG(IEEE80211_DL_ERR, "in function %s() There is not enough TS record to be used!!", __FUNCTION__); + return false; + } + } + } +} + +void RemoveTsEntry( + struct ieee80211_device* ieee, + PTS_COMMON_INFO pTs, + TR_SELECT TxRxSelect + ) +{ + //u32 flags = 0; + unsigned long flags = 0; + del_timer_sync(&pTs->SetupTimer); + del_timer_sync(&pTs->InactTimer); + TsInitDelBA(ieee, pTs, TxRxSelect); + + if(TxRxSelect == RX_DIR) + { +//#ifdef TO_DO_LIST + PRX_REORDER_ENTRY pRxReorderEntry; + PRX_TS_RECORD pRxTS = (PRX_TS_RECORD)pTs; + if(timer_pending(&pRxTS->RxPktPendingTimer)) + del_timer_sync(&pRxTS->RxPktPendingTimer); + + while(!list_empty(&pRxTS->RxPendingPktList)) + { + // PlatformAcquireSpinLock(Adapter, RT_RX_SPINLOCK); + spin_lock_irqsave(&(ieee->reorder_spinlock), flags); + //pRxReorderEntry = list_entry(&pRxTS->RxPendingPktList.prev,RX_REORDER_ENTRY,List); + pRxReorderEntry = (PRX_REORDER_ENTRY)list_entry(pRxTS->RxPendingPktList.prev,RX_REORDER_ENTRY,List); + list_del_init(&pRxReorderEntry->List); + { + int i = 0; + struct ieee80211_rxb * prxb = pRxReorderEntry->prxb; + if (unlikely(!prxb)) + { + spin_unlock_irqrestore(&(ieee->reorder_spinlock), flags); + return; + } + for(i =0; i < prxb->nr_subframes; i++) { + dev_kfree_skb(prxb->subframes[i]); + } + kfree(prxb); + prxb = NULL; + } + list_add_tail(&pRxReorderEntry->List,&ieee->RxReorder_Unused_List); + //PlatformReleaseSpinLock(Adapter, RT_RX_SPINLOCK); + spin_unlock_irqrestore(&(ieee->reorder_spinlock), flags); + } + +//#endif + } + else + { + PTX_TS_RECORD pTxTS = (PTX_TS_RECORD)pTs; + del_timer_sync(&pTxTS->TsAddBaTimer); + } +} + +void RemovePeerTS(struct ieee80211_device* ieee, u8* Addr) +{ + PTS_COMMON_INFO pTS, pTmpTS; + printk("===========>RemovePeerTS,"MAC_FMT"\n", MAC_ARG(Addr)); +#if 1 + list_for_each_entry_safe(pTS, pTmpTS, &ieee->Tx_TS_Pending_List, List) + { + if (memcmp(pTS->Addr, Addr, 6) == 0) + { + RemoveTsEntry(ieee, pTS, TX_DIR); + list_del_init(&pTS->List); + list_add_tail(&pTS->List, &ieee->Tx_TS_Unused_List); + } + } + + list_for_each_entry_safe(pTS, pTmpTS, &ieee->Tx_TS_Admit_List, List) + { + if (memcmp(pTS->Addr, Addr, 6) == 0) + { + printk("====>remove Tx_TS_admin_list\n"); + RemoveTsEntry(ieee, pTS, TX_DIR); + list_del_init(&pTS->List); + list_add_tail(&pTS->List, &ieee->Tx_TS_Unused_List); + } + } + + list_for_each_entry_safe(pTS, pTmpTS, &ieee->Rx_TS_Pending_List, List) + { + if (memcmp(pTS->Addr, Addr, 6) == 0) + { + RemoveTsEntry(ieee, pTS, RX_DIR); + list_del_init(&pTS->List); + list_add_tail(&pTS->List, &ieee->Rx_TS_Unused_List); + } + } + + list_for_each_entry_safe(pTS, pTmpTS, &ieee->Rx_TS_Admit_List, List) + { + if (memcmp(pTS->Addr, Addr, 6) == 0) + { + RemoveTsEntry(ieee, pTS, RX_DIR); + list_del_init(&pTS->List); + list_add_tail(&pTS->List, &ieee->Rx_TS_Unused_List); + } + } +#endif +} + +void RemoveAllTS(struct ieee80211_device* ieee) +{ + PTS_COMMON_INFO pTS, pTmpTS; +#if 1 + list_for_each_entry_safe(pTS, pTmpTS, &ieee->Tx_TS_Pending_List, List) + { + RemoveTsEntry(ieee, pTS, TX_DIR); + list_del_init(&pTS->List); + list_add_tail(&pTS->List, &ieee->Tx_TS_Unused_List); + } + + list_for_each_entry_safe(pTS, pTmpTS, &ieee->Tx_TS_Admit_List, List) + { + RemoveTsEntry(ieee, pTS, TX_DIR); + list_del_init(&pTS->List); + list_add_tail(&pTS->List, &ieee->Tx_TS_Unused_List); + } + + list_for_each_entry_safe(pTS, pTmpTS, &ieee->Rx_TS_Pending_List, List) + { + RemoveTsEntry(ieee, pTS, RX_DIR); + list_del_init(&pTS->List); + list_add_tail(&pTS->List, &ieee->Rx_TS_Unused_List); + } + + list_for_each_entry_safe(pTS, pTmpTS, &ieee->Rx_TS_Admit_List, List) + { + RemoveTsEntry(ieee, pTS, RX_DIR); + list_del_init(&pTS->List); + list_add_tail(&pTS->List, &ieee->Rx_TS_Unused_List); + } +#endif +} + +void TsStartAddBaProcess(struct ieee80211_device* ieee, PTX_TS_RECORD pTxTS) +{ + if(pTxTS->bAddBaReqInProgress == false) + { + pTxTS->bAddBaReqInProgress = true; +#if 1 + if(pTxTS->bAddBaReqDelayed) + { + IEEE80211_DEBUG(IEEE80211_DL_BA, "TsStartAddBaProcess(): Delayed Start ADDBA after 60 sec!!\n"); + mod_timer(&pTxTS->TsAddBaTimer, jiffies + MSECS(TS_ADDBA_DELAY)); + } + else + { + IEEE80211_DEBUG(IEEE80211_DL_BA,"TsStartAddBaProcess(): Immediately Start ADDBA now!!\n"); + mod_timer(&pTxTS->TsAddBaTimer, jiffies+10); //set 10 ticks + } +#endif + } + else + IEEE80211_DEBUG(IEEE80211_DL_ERR, "%s()==>BA timer is already added\n", __FUNCTION__); +} +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) +EXPORT_SYMBOL_NOVERS(RemovePeerTS); +#else +EXPORT_SYMBOL(RemovePeerTS); +#endif diff --git a/drivers/staging/rtl8192su/ieee80211/rtl_crypto.h b/drivers/staging/rtl8192su/ieee80211/rtl_crypto.h new file mode 100644 index 000000000000..ccf6ae763572 --- /dev/null +++ b/drivers/staging/rtl8192su/ieee80211/rtl_crypto.h @@ -0,0 +1,399 @@ +/* + * Scatterlist Cryptographic API. + * + * Copyright (c) 2002 James Morris <jmorris@intercode.com.au> + * Copyright (c) 2002 David S. Miller (davem@redhat.com) + * + * Portions derived from Cryptoapi, by Alexander Kjeldaas <astor@fast.no> + * and Nettle, by Niels Mé°ˆler. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + */ +#ifndef _LINUX_CRYPTO_H +#define _LINUX_CRYPTO_H + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/list.h> +#include <linux/string.h> +#include <asm/page.h> +#include <asm/errno.h> + +#define crypto_register_alg crypto_register_alg_rsl +#define crypto_unregister_alg crypto_unregister_alg_rsl +#define crypto_alloc_tfm crypto_alloc_tfm_rsl +#define crypto_free_tfm crypto_free_tfm_rsl +#define crypto_alg_available crypto_alg_available_rsl + +/* + * Algorithm masks and types. + */ +#define CRYPTO_ALG_TYPE_MASK 0x000000ff +#define CRYPTO_ALG_TYPE_CIPHER 0x00000001 +#define CRYPTO_ALG_TYPE_DIGEST 0x00000002 +#define CRYPTO_ALG_TYPE_COMPRESS 0x00000004 + +/* + * Transform masks and values (for crt_flags). + */ +#define CRYPTO_TFM_MODE_MASK 0x000000ff +#define CRYPTO_TFM_REQ_MASK 0x000fff00 +#define CRYPTO_TFM_RES_MASK 0xfff00000 + +#define CRYPTO_TFM_MODE_ECB 0x00000001 +#define CRYPTO_TFM_MODE_CBC 0x00000002 +#define CRYPTO_TFM_MODE_CFB 0x00000004 +#define CRYPTO_TFM_MODE_CTR 0x00000008 + +#define CRYPTO_TFM_REQ_WEAK_KEY 0x00000100 +#define CRYPTO_TFM_RES_WEAK_KEY 0x00100000 +#define CRYPTO_TFM_RES_BAD_KEY_LEN 0x00200000 +#define CRYPTO_TFM_RES_BAD_KEY_SCHED 0x00400000 +#define CRYPTO_TFM_RES_BAD_BLOCK_LEN 0x00800000 +#define CRYPTO_TFM_RES_BAD_FLAGS 0x01000000 + +/* + * Miscellaneous stuff. + */ +#define CRYPTO_UNSPEC 0 +#define CRYPTO_MAX_ALG_NAME 64 + +struct scatterlist; + +/* + * Algorithms: modular crypto algorithm implementations, managed + * via crypto_register_alg() and crypto_unregister_alg(). + */ +struct cipher_alg { + unsigned int cia_min_keysize; + unsigned int cia_max_keysize; + int (*cia_setkey)(void *ctx, const u8 *key, + unsigned int keylen, u32 *flags); + void (*cia_encrypt)(void *ctx, u8 *dst, const u8 *src); + void (*cia_decrypt)(void *ctx, u8 *dst, const u8 *src); +}; + +struct digest_alg { + unsigned int dia_digestsize; + void (*dia_init)(void *ctx); + void (*dia_update)(void *ctx, const u8 *data, unsigned int len); + void (*dia_final)(void *ctx, u8 *out); + int (*dia_setkey)(void *ctx, const u8 *key, + unsigned int keylen, u32 *flags); +}; + +struct compress_alg { + int (*coa_init)(void *ctx); + void (*coa_exit)(void *ctx); + int (*coa_compress)(void *ctx, const u8 *src, unsigned int slen, + u8 *dst, unsigned int *dlen); + int (*coa_decompress)(void *ctx, const u8 *src, unsigned int slen, + u8 *dst, unsigned int *dlen); +}; + +#define cra_cipher cra_u.cipher +#define cra_digest cra_u.digest +#define cra_compress cra_u.compress + +struct crypto_alg { + struct list_head cra_list; + u32 cra_flags; + unsigned int cra_blocksize; + unsigned int cra_ctxsize; + const char cra_name[CRYPTO_MAX_ALG_NAME]; + + union { + struct cipher_alg cipher; + struct digest_alg digest; + struct compress_alg compress; + } cra_u; + + struct module *cra_module; +}; + +/* + * Algorithm registration interface. + */ +int crypto_register_alg(struct crypto_alg *alg); +int crypto_unregister_alg(struct crypto_alg *alg); + +/* + * Algorithm query interface. + */ +int crypto_alg_available(const char *name, u32 flags); + +/* + * Transforms: user-instantiated objects which encapsulate algorithms + * and core processing logic. Managed via crypto_alloc_tfm() and + * crypto_free_tfm(), as well as the various helpers below. + */ +struct crypto_tfm; + +struct cipher_tfm { + void *cit_iv; + unsigned int cit_ivsize; + u32 cit_mode; + int (*cit_setkey)(struct crypto_tfm *tfm, + const u8 *key, unsigned int keylen); + int (*cit_encrypt)(struct crypto_tfm *tfm, + struct scatterlist *dst, + struct scatterlist *src, + unsigned int nbytes); + int (*cit_encrypt_iv)(struct crypto_tfm *tfm, + struct scatterlist *dst, + struct scatterlist *src, + unsigned int nbytes, u8 *iv); + int (*cit_decrypt)(struct crypto_tfm *tfm, + struct scatterlist *dst, + struct scatterlist *src, + unsigned int nbytes); + int (*cit_decrypt_iv)(struct crypto_tfm *tfm, + struct scatterlist *dst, + struct scatterlist *src, + unsigned int nbytes, u8 *iv); + void (*cit_xor_block)(u8 *dst, const u8 *src); +}; + +struct digest_tfm { + void (*dit_init)(struct crypto_tfm *tfm); + void (*dit_update)(struct crypto_tfm *tfm, + struct scatterlist *sg, unsigned int nsg); + void (*dit_final)(struct crypto_tfm *tfm, u8 *out); + void (*dit_digest)(struct crypto_tfm *tfm, struct scatterlist *sg, + unsigned int nsg, u8 *out); + int (*dit_setkey)(struct crypto_tfm *tfm, + const u8 *key, unsigned int keylen); +#ifdef CONFIG_CRYPTO_HMAC + void *dit_hmac_block; +#endif +}; + +struct compress_tfm { + int (*cot_compress)(struct crypto_tfm *tfm, + const u8 *src, unsigned int slen, + u8 *dst, unsigned int *dlen); + int (*cot_decompress)(struct crypto_tfm *tfm, + const u8 *src, unsigned int slen, + u8 *dst, unsigned int *dlen); +}; + +#define crt_cipher crt_u.cipher +#define crt_digest crt_u.digest +#define crt_compress crt_u.compress + +struct crypto_tfm { + + u32 crt_flags; + + union { + struct cipher_tfm cipher; + struct digest_tfm digest; + struct compress_tfm compress; + } crt_u; + + struct crypto_alg *__crt_alg; +}; + +/* + * Transform user interface. + */ + +/* + * crypto_alloc_tfm() will first attempt to locate an already loaded algorithm. + * If that fails and the kernel supports dynamically loadable modules, it + * will then attempt to load a module of the same name or alias. A refcount + * is grabbed on the algorithm which is then associated with the new transform. + * + * crypto_free_tfm() frees up the transform and any associated resources, + * then drops the refcount on the associated algorithm. + */ +struct crypto_tfm *crypto_alloc_tfm(const char *alg_name, u32 tfm_flags); +void crypto_free_tfm(struct crypto_tfm *tfm); + +/* + * Transform helpers which query the underlying algorithm. + */ +static inline const char *crypto_tfm_alg_name(struct crypto_tfm *tfm) +{ + return tfm->__crt_alg->cra_name; +} + +static inline const char *crypto_tfm_alg_modname(struct crypto_tfm *tfm) +{ + struct crypto_alg *alg = tfm->__crt_alg; + + if (alg->cra_module) + return alg->cra_module->name; + else + return NULL; +} + +static inline u32 crypto_tfm_alg_type(struct crypto_tfm *tfm) +{ + return tfm->__crt_alg->cra_flags & CRYPTO_ALG_TYPE_MASK; +} + +static inline unsigned int crypto_tfm_alg_min_keysize(struct crypto_tfm *tfm) +{ + BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_CIPHER); + return tfm->__crt_alg->cra_cipher.cia_min_keysize; +} + +static inline unsigned int crypto_tfm_alg_max_keysize(struct crypto_tfm *tfm) +{ + BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_CIPHER); + return tfm->__crt_alg->cra_cipher.cia_max_keysize; +} + +static inline unsigned int crypto_tfm_alg_ivsize(struct crypto_tfm *tfm) +{ + BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_CIPHER); + return tfm->crt_cipher.cit_ivsize; +} + +static inline unsigned int crypto_tfm_alg_blocksize(struct crypto_tfm *tfm) +{ + return tfm->__crt_alg->cra_blocksize; +} + +static inline unsigned int crypto_tfm_alg_digestsize(struct crypto_tfm *tfm) +{ + BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_DIGEST); + return tfm->__crt_alg->cra_digest.dia_digestsize; +} + +/* + * API wrappers. + */ +static inline void crypto_digest_init(struct crypto_tfm *tfm) +{ + BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_DIGEST); + tfm->crt_digest.dit_init(tfm); +} + +static inline void crypto_digest_update(struct crypto_tfm *tfm, + struct scatterlist *sg, + unsigned int nsg) +{ + BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_DIGEST); + tfm->crt_digest.dit_update(tfm, sg, nsg); +} + +static inline void crypto_digest_final(struct crypto_tfm *tfm, u8 *out) +{ + BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_DIGEST); + tfm->crt_digest.dit_final(tfm, out); +} + +static inline void crypto_digest_digest(struct crypto_tfm *tfm, + struct scatterlist *sg, + unsigned int nsg, u8 *out) +{ + BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_DIGEST); + tfm->crt_digest.dit_digest(tfm, sg, nsg, out); +} + +static inline int crypto_digest_setkey(struct crypto_tfm *tfm, + const u8 *key, unsigned int keylen) +{ + BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_DIGEST); + if (tfm->crt_digest.dit_setkey == NULL) + return -ENOSYS; + return tfm->crt_digest.dit_setkey(tfm, key, keylen); +} + +static inline int crypto_cipher_setkey(struct crypto_tfm *tfm, + const u8 *key, unsigned int keylen) +{ + BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_CIPHER); + return tfm->crt_cipher.cit_setkey(tfm, key, keylen); +} + +static inline int crypto_cipher_encrypt(struct crypto_tfm *tfm, + struct scatterlist *dst, + struct scatterlist *src, + unsigned int nbytes) +{ + BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_CIPHER); + return tfm->crt_cipher.cit_encrypt(tfm, dst, src, nbytes); +} + +static inline int crypto_cipher_encrypt_iv(struct crypto_tfm *tfm, + struct scatterlist *dst, + struct scatterlist *src, + unsigned int nbytes, u8 *iv) +{ + BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_CIPHER); + BUG_ON(tfm->crt_cipher.cit_mode == CRYPTO_TFM_MODE_ECB); + return tfm->crt_cipher.cit_encrypt_iv(tfm, dst, src, nbytes, iv); +} + +static inline int crypto_cipher_decrypt(struct crypto_tfm *tfm, + struct scatterlist *dst, + struct scatterlist *src, + unsigned int nbytes) +{ + BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_CIPHER); + return tfm->crt_cipher.cit_decrypt(tfm, dst, src, nbytes); +} + +static inline int crypto_cipher_decrypt_iv(struct crypto_tfm *tfm, + struct scatterlist *dst, + struct scatterlist *src, + unsigned int nbytes, u8 *iv) +{ + BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_CIPHER); + BUG_ON(tfm->crt_cipher.cit_mode == CRYPTO_TFM_MODE_ECB); + return tfm->crt_cipher.cit_decrypt_iv(tfm, dst, src, nbytes, iv); +} + +static inline void crypto_cipher_set_iv(struct crypto_tfm *tfm, + const u8 *src, unsigned int len) +{ + BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_CIPHER); + memcpy(tfm->crt_cipher.cit_iv, src, len); +} + +static inline void crypto_cipher_get_iv(struct crypto_tfm *tfm, + u8 *dst, unsigned int len) +{ + BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_CIPHER); + memcpy(dst, tfm->crt_cipher.cit_iv, len); +} + +static inline int crypto_comp_compress(struct crypto_tfm *tfm, + const u8 *src, unsigned int slen, + u8 *dst, unsigned int *dlen) +{ + BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_COMPRESS); + return tfm->crt_compress.cot_compress(tfm, src, slen, dst, dlen); +} + +static inline int crypto_comp_decompress(struct crypto_tfm *tfm, + const u8 *src, unsigned int slen, + u8 *dst, unsigned int *dlen) +{ + BUG_ON(crypto_tfm_alg_type(tfm) != CRYPTO_ALG_TYPE_COMPRESS); + return tfm->crt_compress.cot_decompress(tfm, src, slen, dst, dlen); +} + +/* + * HMAC support. + */ +#ifdef CONFIG_CRYPTO_HMAC +void crypto_hmac_init(struct crypto_tfm *tfm, u8 *key, unsigned int *keylen); +void crypto_hmac_update(struct crypto_tfm *tfm, + struct scatterlist *sg, unsigned int nsg); +void crypto_hmac_final(struct crypto_tfm *tfm, u8 *key, + unsigned int *keylen, u8 *out); +void crypto_hmac(struct crypto_tfm *tfm, u8 *key, unsigned int *keylen, + struct scatterlist *sg, unsigned int nsg, u8 *out); +#endif /* CONFIG_CRYPTO_HMAC */ + +#endif /* _LINUX_CRYPTO_H */ + diff --git a/drivers/staging/rtl8192su/ieee80211/scatterwalk.c b/drivers/staging/rtl8192su/ieee80211/scatterwalk.c new file mode 100644 index 000000000000..49f401fbce88 --- /dev/null +++ b/drivers/staging/rtl8192su/ieee80211/scatterwalk.c @@ -0,0 +1,126 @@ +/* + * Cryptographic API. + * + * Cipher operations. + * + * Copyright (c) 2002 James Morris <jmorris@intercode.com.au> + * 2002 Adam J. Richter <adam@yggdrasil.com> + * 2004 Jean-Luc Cooke <jlcooke@certainkey.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + */ +#include "kmap_types.h" + +#include <linux/kernel.h> +#include <linux/mm.h> +#include <linux/pagemap.h> +#include <linux/highmem.h> +#include <asm/scatterlist.h> +#include "internal.h" +#include "scatterwalk.h" + +enum km_type crypto_km_types[] = { + KM_USER0, + KM_USER1, + KM_SOFTIRQ0, + KM_SOFTIRQ1, +}; + +void *scatterwalk_whichbuf(struct scatter_walk *walk, unsigned int nbytes, void *scratch) +{ + if (nbytes <= walk->len_this_page && + (((unsigned long)walk->data) & (PAGE_CACHE_SIZE - 1)) + nbytes <= + PAGE_CACHE_SIZE) + return walk->data; + else + return scratch; +} + +static void memcpy_dir(void *buf, void *sgdata, size_t nbytes, int out) +{ + if (out) + memcpy(sgdata, buf, nbytes); + else + memcpy(buf, sgdata, nbytes); +} + +void scatterwalk_start(struct scatter_walk *walk, struct scatterlist *sg) +{ + unsigned int rest_of_page; + + walk->sg = sg; + + walk->page = sg->page; + walk->len_this_segment = sg->length; + + rest_of_page = PAGE_CACHE_SIZE - (sg->offset & (PAGE_CACHE_SIZE - 1)); + walk->len_this_page = min(sg->length, rest_of_page); + walk->offset = sg->offset; +} + +void scatterwalk_map(struct scatter_walk *walk, int out) +{ + walk->data = crypto_kmap(walk->page, out) + walk->offset; +} + +static void scatterwalk_pagedone(struct scatter_walk *walk, int out, + unsigned int more) +{ + /* walk->data may be pointing the first byte of the next page; + however, we know we transfered at least one byte. So, + walk->data - 1 will be a virtual address in the mapped page. */ + + if (out) + flush_dcache_page(walk->page); + + if (more) { + walk->len_this_segment -= walk->len_this_page; + + if (walk->len_this_segment) { + walk->page++; + walk->len_this_page = min(walk->len_this_segment, + (unsigned)PAGE_CACHE_SIZE); + walk->offset = 0; + } + else + scatterwalk_start(walk, sg_next(walk->sg)); + } +} + +void scatterwalk_done(struct scatter_walk *walk, int out, int more) +{ + crypto_kunmap(walk->data, out); + if (walk->len_this_page == 0 || !more) + scatterwalk_pagedone(walk, out, more); +} + +/* + * Do not call this unless the total length of all of the fragments + * has been verified as multiple of the block size. + */ +int scatterwalk_copychunks(void *buf, struct scatter_walk *walk, + size_t nbytes, int out) +{ + if (buf != walk->data) { + while (nbytes > walk->len_this_page) { + memcpy_dir(buf, walk->data, walk->len_this_page, out); + buf += walk->len_this_page; + nbytes -= walk->len_this_page; + + crypto_kunmap(walk->data, out); + scatterwalk_pagedone(walk, out, 1); + scatterwalk_map(walk, out); + } + + memcpy_dir(buf, walk->data, nbytes, out); + } + + walk->offset += nbytes; + walk->len_this_page -= nbytes; + walk->len_this_segment -= nbytes; + return 0; +} diff --git a/drivers/staging/rtl8192su/ieee80211/scatterwalk.h b/drivers/staging/rtl8192su/ieee80211/scatterwalk.h new file mode 100644 index 000000000000..b16446519017 --- /dev/null +++ b/drivers/staging/rtl8192su/ieee80211/scatterwalk.h @@ -0,0 +1,51 @@ +/* + * Cryptographic API. + * + * Copyright (c) 2002 James Morris <jmorris@intercode.com.au> + * Copyright (c) 2002 Adam J. Richter <adam@yggdrasil.com> + * Copyright (c) 2004 Jean-Luc Cooke <jlcooke@certainkey.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + */ + +#ifndef _CRYPTO_SCATTERWALK_H +#define _CRYPTO_SCATTERWALK_H +#include <linux/mm.h> +#include <asm/scatterlist.h> + +struct scatter_walk { + struct scatterlist *sg; + struct page *page; + void *data; + unsigned int len_this_page; + unsigned int len_this_segment; + unsigned int offset; +}; + +/* Define sg_next is an inline routine now in case we want to change + scatterlist to a linked list later. */ +static inline struct scatterlist *sg_next(struct scatterlist *sg) +{ + return sg + 1; +} + +static inline int scatterwalk_samebuf(struct scatter_walk *walk_in, + struct scatter_walk *walk_out, + void *src_p, void *dst_p) +{ + return walk_in->page == walk_out->page && + walk_in->offset == walk_out->offset && + walk_in->data == src_p && walk_out->data == dst_p; +} + +void *scatterwalk_whichbuf(struct scatter_walk *walk, unsigned int nbytes, void *scratch); +void scatterwalk_start(struct scatter_walk *walk, struct scatterlist *sg); +int scatterwalk_copychunks(void *buf, struct scatter_walk *walk, size_t nbytes, int out); +void scatterwalk_map(struct scatter_walk *walk, int out); +void scatterwalk_done(struct scatter_walk *walk, int out, int more); + +#endif /* _CRYPTO_SCATTERWALK_H */ diff --git a/drivers/staging/rtl8192su/ieee80211_crypt.h b/drivers/staging/rtl8192su/ieee80211_crypt.h new file mode 100644 index 000000000000..b58a3bcc0dc0 --- /dev/null +++ b/drivers/staging/rtl8192su/ieee80211_crypt.h @@ -0,0 +1,86 @@ +/* + * Original code based on Host AP (software wireless LAN access point) driver + * for Intersil Prism2/2.5/3. + * + * Copyright (c) 2001-2002, SSH Communications Security Corp and Jouni Malinen + * <jkmaline@cc.hut.fi> + * Copyright (c) 2002-2003, Jouni Malinen <jkmaline@cc.hut.fi> + * + * Adaption to a generic IEEE 802.11 stack by James Ketrenos + * <jketreno@linux.intel.com> + * + * Copyright (c) 2004, Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. See README and COPYING for + * more details. + */ + +/* + * This file defines the interface to the ieee80211 crypto module. + */ +#ifndef IEEE80211_CRYPT_H +#define IEEE80211_CRYPT_H + +#include <linux/skbuff.h> + +struct ieee80211_crypto_ops { + const char *name; + + /* init new crypto context (e.g., allocate private data space, + * select IV, etc.); returns NULL on failure or pointer to allocated + * private data on success */ + void * (*init)(int keyidx); + + /* deinitialize crypto context and free allocated private data */ + void (*deinit)(void *priv); + + /* encrypt/decrypt return < 0 on error or >= 0 on success. The return + * value from decrypt_mpdu is passed as the keyidx value for + * decrypt_msdu. skb must have enough head and tail room for the + * encryption; if not, error will be returned; these functions are + * called for all MPDUs (i.e., fragments). + */ + int (*encrypt_mpdu)(struct sk_buff *skb, int hdr_len, void *priv); + int (*decrypt_mpdu)(struct sk_buff *skb, int hdr_len, void *priv); + + /* These functions are called for full MSDUs, i.e. full frames. + * These can be NULL if full MSDU operations are not needed. */ + int (*encrypt_msdu)(struct sk_buff *skb, int hdr_len, void *priv); + int (*decrypt_msdu)(struct sk_buff *skb, int keyidx, int hdr_len, + void *priv); + + int (*set_key)(void *key, int len, u8 *seq, void *priv); + int (*get_key)(void *key, int len, u8 *seq, void *priv); + + /* procfs handler for printing out key information and possible + * statistics */ + char * (*print_stats)(char *p, void *priv); + + /* maximum number of bytes added by encryption; encrypt buf is + * allocated with extra_prefix_len bytes, copy of in_buf, and + * extra_postfix_len; encrypt need not use all this space, but + * the result must start at the beginning of the buffer and correct + * length must be returned */ + int extra_prefix_len, extra_postfix_len; + + struct module *owner; +}; + +struct ieee80211_crypt_data { + struct list_head list; /* delayed deletion list */ + struct ieee80211_crypto_ops *ops; + void *priv; + atomic_t refcnt; +}; + +int ieee80211_register_crypto_ops(struct ieee80211_crypto_ops *ops); +int ieee80211_unregister_crypto_ops(struct ieee80211_crypto_ops *ops); +struct ieee80211_crypto_ops * ieee80211_get_crypto_ops(const char *name); +void ieee80211_crypt_deinit_entries(struct ieee80211_device *, int); +void ieee80211_crypt_deinit_handler(unsigned long); +void ieee80211_crypt_delayed_deinit(struct ieee80211_device *ieee, + struct ieee80211_crypt_data **crypt); + +#endif diff --git a/drivers/staging/rtl8192su/r8180_93cx6.c b/drivers/staging/rtl8192su/r8180_93cx6.c new file mode 100644 index 000000000000..8878cfeb0fbb --- /dev/null +++ b/drivers/staging/rtl8192su/r8180_93cx6.c @@ -0,0 +1,146 @@ +/* + This files contains card eeprom (93c46 or 93c56) programming routines, + memory is addressed by 16 bits words. + + This is part of rtl8180 OpenSource driver. + Copyright (C) Andrea Merello 2004 <andreamrl@tiscali.it> + Released under the terms of GPL (General Public Licence) + + Parts of this driver are based on the GPL part of the + official realtek driver. + + Parts of this driver are based on the rtl8180 driver skeleton + from Patric Schenke & Andres Salomon. + + Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver. + + We want to tanks the Authors of those projects and the Ndiswrapper + project Authors. +*/ + +#include "r8180_93cx6.h" + +void eprom_cs(struct net_device *dev, short bit) +{ + if(bit) + write_nic_byte_E(dev, EPROM_CMD, + (1<<EPROM_CS_SHIFT) | \ + read_nic_byte_E(dev, EPROM_CMD)); //enable EPROM + else + write_nic_byte_E(dev, EPROM_CMD, read_nic_byte_E(dev, EPROM_CMD)\ + &~(1<<EPROM_CS_SHIFT)); //disable EPROM + + force_pci_posting(dev); + udelay(EPROM_DELAY); +} + + +void eprom_ck_cycle(struct net_device *dev) +{ + write_nic_byte_E(dev, EPROM_CMD, + (1<<EPROM_CK_SHIFT) | read_nic_byte_E(dev,EPROM_CMD)); + force_pci_posting(dev); + udelay(EPROM_DELAY); + write_nic_byte_E(dev, EPROM_CMD, + read_nic_byte_E(dev, EPROM_CMD) &~ (1<<EPROM_CK_SHIFT)); + force_pci_posting(dev); + udelay(EPROM_DELAY); +} + + +void eprom_w(struct net_device *dev,short bit) +{ + if(bit) + write_nic_byte_E(dev, EPROM_CMD, (1<<EPROM_W_SHIFT) | \ + read_nic_byte_E(dev,EPROM_CMD)); + else + write_nic_byte_E(dev, EPROM_CMD, read_nic_byte_E(dev,EPROM_CMD)\ + &~(1<<EPROM_W_SHIFT)); + + force_pci_posting(dev); + udelay(EPROM_DELAY); +} + + +short eprom_r(struct net_device *dev) +{ + short bit; + + bit=(read_nic_byte_E(dev, EPROM_CMD) & (1<<EPROM_R_SHIFT) ); + udelay(EPROM_DELAY); + + if(bit) return 1; + return 0; +} + + +void eprom_send_bits_string(struct net_device *dev, short b[], int len) +{ + int i; + + for(i=0; i<len; i++){ + eprom_w(dev, b[i]); + eprom_ck_cycle(dev); + } +} + + +u32 eprom_read(struct net_device *dev, u32 addr) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + short read_cmd[]={1,1,0}; + short addr_str[8]; + int i; + int addr_len; + u32 ret; + + ret=0; + //enable EPROM programming + write_nic_byte_E(dev, EPROM_CMD, + (EPROM_CMD_PROGRAM<<EPROM_CMD_OPERATING_MODE_SHIFT)); + force_pci_posting(dev); + udelay(EPROM_DELAY); + + if (priv->epromtype==EPROM_93c56){ + addr_str[7]=addr & 1; + addr_str[6]=addr & (1<<1); + addr_str[5]=addr & (1<<2); + addr_str[4]=addr & (1<<3); + addr_str[3]=addr & (1<<4); + addr_str[2]=addr & (1<<5); + addr_str[1]=addr & (1<<6); + addr_str[0]=addr & (1<<7); + addr_len=8; + }else{ + addr_str[5]=addr & 1; + addr_str[4]=addr & (1<<1); + addr_str[3]=addr & (1<<2); + addr_str[2]=addr & (1<<3); + addr_str[1]=addr & (1<<4); + addr_str[0]=addr & (1<<5); + addr_len=6; + } + eprom_cs(dev, 1); + eprom_ck_cycle(dev); + eprom_send_bits_string(dev, read_cmd, 3); + eprom_send_bits_string(dev, addr_str, addr_len); + + //keep chip pin D to low state while reading. + //I'm unsure if it is necessary, but anyway shouldn't hurt + eprom_w(dev, 0); + + for(i=0;i<16;i++){ + //eeprom needs a clk cycle between writing opcode&adr + //and reading data. (eeprom outs a dummy 0) + eprom_ck_cycle(dev); + ret |= (eprom_r(dev)<<(15-i)); + } + + eprom_cs(dev, 0); + eprom_ck_cycle(dev); + + //disable EPROM programming + write_nic_byte_E(dev, EPROM_CMD, + (EPROM_CMD_NORMAL<<EPROM_CMD_OPERATING_MODE_SHIFT)); + return ret; +} diff --git a/drivers/staging/rtl8192su/r8180_93cx6.h b/drivers/staging/rtl8192su/r8180_93cx6.h new file mode 100644 index 000000000000..ca228d368174 --- /dev/null +++ b/drivers/staging/rtl8192su/r8180_93cx6.h @@ -0,0 +1,45 @@ +/* + This is part of rtl8187 OpenSource driver + Copyright (C) Andrea Merello 2004-2005 <andreamrl@tiscali.it> + Released under the terms of GPL (General Public Licence) + + Parts of this driver are based on the GPL part of the official realtek driver + Parts of this driver are based on the rtl8180 driver skeleton from Patric Schenke & Andres Salomon + Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver + + We want to tanks the Authors of such projects and the Ndiswrapper project Authors. +*/ + +/*This files contains card eeprom (93c46 or 93c56) programming routines*/ +/*memory is addressed by WORDS*/ + +#ifdef RTL8192SU +#include "r8192U.h" +#include "r8192S_hw.h" +#else +#include "r8192U.h" +#include "r8192U_hw.h" +#endif + +#define EPROM_DELAY 10 + +#define EPROM_ANAPARAM_ADDRLWORD 0xd +#define EPROM_ANAPARAM_ADDRHWORD 0xe + +#define EPROM_RFCHIPID 0x6 +#define EPROM_TXPW_BASE 0x05 +#define EPROM_RFCHIPID_RTL8225U 5 +#define EPROM_RF_PARAM 0x4 +#define EPROM_CONFIG2 0xc + +#define EPROM_VERSION 0x1E +#define MAC_ADR 0x7 + +#define CIS 0x18 + +#define EPROM_TXPW0 0x16 +#define EPROM_TXPW2 0x1b +#define EPROM_TXPW1 0x3d + + +u32 eprom_read(struct net_device *dev,u32 addr); //reads a 16 bits word diff --git a/drivers/staging/rtl8192su/r8190_rtl8256.c b/drivers/staging/rtl8192su/r8190_rtl8256.c new file mode 100644 index 000000000000..74ff337b0583 --- /dev/null +++ b/drivers/staging/rtl8192su/r8190_rtl8256.c @@ -0,0 +1,312 @@ +/* + This is part of the rtl8192 driver + released under the GPL (See file COPYING for details). + + This files contains programming code for the rtl8256 + radio frontend. + + *Many* thanks to Realtek Corp. for their great support! + +*/ + +#include "r8192U.h" +#include "r8192U_hw.h" +#include "r819xU_phyreg.h" +#include "r819xU_phy.h" +#include "r8190_rtl8256.h" + +/*-------------------------------------------------------------------------- + * Overview: set RF band width (20M or 40M) + * Input: struct net_device* dev + * WIRELESS_BANDWIDTH_E Bandwidth //20M or 40M + * Output: NONE + * Return: NONE + * Note: 8226 support both 20M and 40 MHz + *---------------------------------------------------------------------------*/ +void PHY_SetRF8256Bandwidth(struct net_device* dev , HT_CHANNEL_WIDTH Bandwidth) //20M or 40M +{ + u8 eRFPath; + struct r8192_priv *priv = ieee80211_priv(dev); + + //for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++) + for(eRFPath = 0; eRFPath <RF90_PATH_MAX; eRFPath++) + { + if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) + continue; + + switch(Bandwidth) + { + case HT_CHANNEL_WIDTH_20: + if(priv->card_8192_version == VERSION_819xU_A || priv->card_8192_version == VERSION_819xU_B)// 8256 D-cut, E-cut, xiong: consider it later! + { + rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0b, bMask12Bits, 0x100); //phy para:1ba + rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3d7); + rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0e, bMask12Bits, 0x021); + + //cosa add for sd3's request 01/23/2008 + rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x5ab); + } + else + { + RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown hardware version\n"); + } + + break; + case HT_CHANNEL_WIDTH_20_40: + if(priv->card_8192_version == VERSION_819xU_A ||priv->card_8192_version == VERSION_819xU_B)// 8256 D-cut, E-cut, xiong: consider it later! + { + rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0b, bMask12Bits, 0x300); //phy para:3ba + rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3df); + rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0e, bMask12Bits, 0x0a1); + + //cosa add for sd3's request 01/23/2008 + if(priv->chan == 3 || priv->chan == 9) //I need to set priv->chan whenever current channel changes + rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x59b); + else + rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x5ab); + } + else + { + RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown hardware version\n"); + } + + + break; + default: + RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth ); + break; + + } + } + return; +} +/*-------------------------------------------------------------------------- + * Overview: Interface to config 8256 + * Input: struct net_device* dev + * Output: NONE + * Return: NONE + *---------------------------------------------------------------------------*/ +void PHY_RF8256_Config(struct net_device* dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + // Initialize general global value + // + // TODO: Extend RF_PATH_C and RF_PATH_D in the future + priv->NumTotalRFPath = RTL819X_TOTAL_RF_PATH; + // Config BB and RF + phy_RF8256_Config_ParaFile(dev); + + return; +} +/*-------------------------------------------------------------------------- + * Overview: Interface to config 8256 + * Input: struct net_device* dev + * Output: NONE + * Return: NONE + *---------------------------------------------------------------------------*/ +void phy_RF8256_Config_ParaFile(struct net_device* dev) +{ + u32 u4RegValue = 0; + //static s1Byte szRadioAFile[] = RTL819X_PHY_RADIO_A; + //static s1Byte szRadioBFile[] = RTL819X_PHY_RADIO_B; + //static s1Byte szRadioCFile[] = RTL819X_PHY_RADIO_C; + //static s1Byte szRadioDFile[] = RTL819X_PHY_RADIO_D; + u8 eRFPath; + BB_REGISTER_DEFINITION_T *pPhyReg; + struct r8192_priv *priv = ieee80211_priv(dev); + u32 RegOffSetToBeCheck = 0x3; + u32 RegValueToBeCheck = 0x7f1; + u32 RF3_Final_Value = 0; + u8 ConstRetryTimes = 5, RetryTimes = 5; + u8 ret = 0; + //3//----------------------------------------------------------------- + //3// <2> Initialize RF + //3//----------------------------------------------------------------- + for(eRFPath = (RF90_RADIO_PATH_E)RF90_PATH_A; eRFPath <priv->NumTotalRFPath; eRFPath++) + { + if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) + continue; + + pPhyReg = &priv->PHYRegDef[eRFPath]; + + // Joseph test for shorten RF config + // pHalData->RfReg0Value[eRFPath] = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, rGlobalCtrl, bMaskDWord); + + /*----Store original RFENV control type----*/ + switch(eRFPath) + { + case RF90_PATH_A: + case RF90_PATH_C: + u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV); + break; + case RF90_PATH_B : + case RF90_PATH_D: + u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16); + break; + } + + /*----Set RF_ENV enable----*/ + rtl8192_setBBreg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1); + + /*----Set RF_ENV output high----*/ + rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1); + + /* Set bit number of Address and Data for RF register */ + rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); // Set 0 to 4 bits for Z-serial and set 1 to 6 bits for 8258 + rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); // Set 0 to 12 bits for Z-serial and 8258, and set 1 to 14 bits for ??? + + rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E) eRFPath, 0x0, bMask12Bits, 0xbf); + + /*----Check RF block (for FPGA platform only)----*/ + // TODO: this function should be removed on ASIC , Emily 2007.2.2 + if (rtl8192_phy_checkBBAndRF(dev, HW90_BLOCK_RF, (RF90_RADIO_PATH_E)eRFPath)) + { + RT_TRACE(COMP_ERR, "PHY_RF8256_Config():Check Radio[%d] Fail!!\n", eRFPath); + goto phy_RF8256_Config_ParaFile_Fail; + } + + RetryTimes = ConstRetryTimes; + RF3_Final_Value = 0; + /*----Initialize RF fom connfiguration file----*/ + switch(eRFPath) + { + case RF90_PATH_A: + while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0) + { + ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath); + RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits); + RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); + RetryTimes--; + } + break; + case RF90_PATH_B: + while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0) + { + ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath); + RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits); + RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); + RetryTimes--; + } + break; + case RF90_PATH_C: + while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0) + { + ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath); + RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits); + RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); + RetryTimes--; + } + break; + case RF90_PATH_D: + while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0) + { + ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath); + RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits); + RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); + RetryTimes--; + } + break; + } + + /*----Restore RFENV control type----*/; + switch(eRFPath) + { + case RF90_PATH_A: + case RF90_PATH_C: + rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue); + break; + case RF90_PATH_B : + case RF90_PATH_D: + rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue); + break; + } + + if(ret){ + RT_TRACE(COMP_ERR, "phy_RF8256_Config_ParaFile():Radio[%d] Fail!!", eRFPath); + goto phy_RF8256_Config_ParaFile_Fail; + } + + } + + RT_TRACE(COMP_PHY, "PHY Initialization Success\n") ; + return ; + +phy_RF8256_Config_ParaFile_Fail: + RT_TRACE(COMP_ERR, "PHY Initialization failed\n") ; + return ; +} + + +void PHY_SetRF8256CCKTxPower(struct net_device* dev, u8 powerlevel) +{ + u32 TxAGC=0; + struct r8192_priv *priv = ieee80211_priv(dev); + //modified by vivi, 20080109 + TxAGC = powerlevel; + + if(priv->bDynamicTxLowPower == TRUE ) //cosa 05/22/2008 for scan + { + if(priv->CustomerID == RT_CID_819x_Netcore) + TxAGC = 0x22; + else + TxAGC += priv->CckPwEnl; + } + + if(TxAGC > 0x24) + TxAGC = 0x24; + rtl8192_setBBreg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC); +} + + +void PHY_SetRF8256OFDMTxPower(struct net_device* dev, u8 powerlevel) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + //Joseph TxPower for 8192 testing + u32 writeVal, powerBase0, powerBase1, writeVal_tmp; + u8 index = 0; + u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c}; + u8 byte0, byte1, byte2, byte3; + + powerBase0 = powerlevel + priv->TxPowerDiff; //OFDM rates + powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0; + powerBase1 = powerlevel; //MCS rates + powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1; + + for(index=0; index<6; index++) + { + writeVal = priv->MCSTxPowerLevelOriginalOffset[index] + ((index<2)?powerBase0:powerBase1); + byte0 = (u8)(writeVal & 0x7f); + byte1 = (u8)((writeVal & 0x7f00)>>8); + byte2 = (u8)((writeVal & 0x7f0000)>>16); + byte3 = (u8)((writeVal & 0x7f000000)>>24); + if(byte0 > 0x24) // Max power index = 0x24 + byte0 = 0x24; + if(byte1 > 0x24) + byte1 = 0x24; + if(byte2 > 0x24) + byte2 = 0x24; + if(byte3 > 0x24) + byte3 = 0x24; + + //for tx power track + if(index == 3) + { + writeVal_tmp = (byte3<<24) | (byte2<<16) |(byte1<<8) |byte0; + priv->Pwr_Track = writeVal_tmp; + } + + if(priv->bDynamicTxHighPower == TRUE) //Add by Jacken 2008/03/06 + { + // Emily, 20080613. Set low tx power for both MCS and legacy OFDM + writeVal = 0x03030303; + } + else + { + writeVal = (byte3<<24) | (byte2<<16) |(byte1<<8) |byte0; + } + rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal); + } + return; + +} + diff --git a/drivers/staging/rtl8192su/r8190_rtl8256.h b/drivers/staging/rtl8192su/r8190_rtl8256.h new file mode 100644 index 000000000000..5c1f650fe824 --- /dev/null +++ b/drivers/staging/rtl8192su/r8190_rtl8256.h @@ -0,0 +1,27 @@ +/* + This is part of the rtl8180-sa2400 driver + released under the GPL (See file COPYING for details). + Copyright (c) 2005 Andrea Merello <andreamrl@tiscali.it> + + This files contains programming code for the rtl8256 + radio frontend. + + *Many* thanks to Realtek Corp. for their great support! + +*/ + +#ifndef RTL8225H +#define RTL8225H + +#ifdef RTL8190P +#define RTL819X_TOTAL_RF_PATH 4 //for 90P +#else +#define RTL819X_TOTAL_RF_PATH 2 //for 8192U +#endif +extern void PHY_SetRF8256Bandwidth(struct net_device* dev , HT_CHANNEL_WIDTH Bandwidth); +extern void PHY_RF8256_Config(struct net_device* dev); +extern void phy_RF8256_Config_ParaFile(struct net_device* dev); +extern void PHY_SetRF8256CCKTxPower(struct net_device* dev, u8 powerlevel); +extern void PHY_SetRF8256OFDMTxPower(struct net_device* dev, u8 powerlevel); + +#endif diff --git a/drivers/staging/rtl8192su/r8192SU_HWImg.c b/drivers/staging/rtl8192su/r8192SU_HWImg.c new file mode 100644 index 000000000000..cbb65795a302 --- /dev/null +++ b/drivers/staging/rtl8192su/r8192SU_HWImg.c @@ -0,0 +1,4902 @@ +/*Created on 2009/ 1/15, 3:10*/ + +#include "r8192SU_HWImg.h" + +u8 Rtl8192SUFwImgArray[ImgArrayLength] = { +0x92,0x81,0x2b,0x90,0x30,0x00,0x00,0x00,0x08,0x74,0x00,0x00,0x88,0x96,0x00,0x00, +0x30,0x00,0x00,0x00,0x00,0x95,0x00,0x00,0x00,0x00,0x2b,0x00,0x03,0x03,0x23,0x00, +0x92,0x81,0x02,0x01,0x00,0x00,0x12,0x04,0x00,0x00,0x00,0x00,0x00,0x07,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x01,0x01,0x01,0x00,0x00, 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+0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, +0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01, +0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x10, +0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02, +0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x10, +0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x00,0x19,0x77,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x26,0x72,0xb0,0x00,0x26,0x72,0xb0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x26,0x65,0x60,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x02, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0xf2,0x30,0xb8,0xff,0xff,0xff,0xff, +}; + +u8 Rtl8192SUFwMainArray[MainArrayLength] = { +0x0, }; + +u8 Rtl8192SUFwDataArray[DataArrayLength] = { +0x0, }; + +u32 Rtl8192SUPHY_REG_2T2RArray[PHY_REG_2T2RArrayLength] = { +0x01c,0x07000000, +0x800,0x00040000, +0x804,0x00008003, +0x808,0x0000fc00, +0x80c,0x0000000a, +0x810,0x10005088, +0x814,0x020c3d10, +0x818,0x00200185, +0x81c,0x00000000, +0x820,0x01000000, +0x824,0x00390004, +0x828,0x01000000, +0x82c,0x00390004, +0x830,0x00000004, +0x834,0x00690200, +0x838,0x00000004, +0x83c,0x00690200, +0x840,0x00010000, +0x844,0x00010000, +0x848,0x00000000, +0x84c,0x00000000, +0x850,0x00000000, +0x854,0x00000000, +0x858,0x48484848, +0x85c,0x65a965a9, +0x860,0x0f7f0130, +0x864,0x0f7f0130, +0x868,0x0f7f0130, +0x86c,0x0f7f0130, +0x870,0x03000700, +0x874,0x03000300, +0x878,0x00020002, +0x87c,0x004f0201, +0x880,0xa8300ac1, +0x884,0x00000058, +0x888,0x00000008, +0x88c,0x00000004, +0x890,0x00000000, +0x894,0xfffffffe, +0x898,0x40302010, +0x89c,0x00706050, +0x8b0,0x00000000, +0x8e0,0x00000000, +0x8e4,0x00000000, +0xe00,0x30333333, +0xe04,0x2a2d2e2f, +0xe08,0x00003232, +0xe10,0x30333333, +0xe14,0x2a2d2e2f, +0xe18,0x30333333, +0xe1c,0x2a2d2e2f, +0xe30,0x01007c00, +0xe34,0x01004800, +0xe38,0x1000dc1f, +0xe3c,0x10008c1f, +0xe40,0x021400a0, +0xe44,0x281600a0, +0xe48,0xf8000001, +0xe4c,0x00002910, +0xe50,0x01007c00, +0xe54,0x01004800, +0xe58,0x1000dc1f, +0xe5c,0x10008c1f, +0xe60,0x021400a0, +0xe64,0x281600a0, +0xe6c,0x00002910, +0xe70,0x31ed92fb, +0xe74,0x361536fb, +0xe78,0x361536fb, +0xe7c,0x361536fb, +0xe80,0x361536fb, +0xe84,0x000d92fb, +0xe88,0x000d92fb, +0xe8c,0x31ed92fb, +0xed0,0x31ed92fb, +0xed4,0x31ed92fb, +0xed8,0x000d92fb, +0xedc,0x000d92fb, +0xee0,0x000d92fb, +0xee4,0x015e5448, +0xee8,0x21555448, +0x900,0x00000000, +0x904,0x00000023, +0x908,0x00000000, +0x90c,0x03321333, +0xa00,0x00d047c8, +0xa04,0x80ff0008, +0xa08,0x8ccd8300, +0xa0c,0x2e62120f, +0xa10,0x9500bb78, +0xa14,0x11144028, +0xa18,0x00881117, +0xa1c,0x89140f00, +0xa20,0x1a1b0000, +0xa24,0x090e1317, +0xa28,0x00000204, +0xa2c,0x10d30000, +0xc00,0x40071d40, +0xc04,0x00a05633, +0xc08,0x000000e4, +0xc0c,0x6c6c6c6c, +0xc10,0x08800000, +0xc14,0x40000100, +0xc18,0x08000000, +0xc1c,0x40000100, +0xc20,0x08000000, +0xc24,0x40000100, +0xc28,0x08000000, +0xc2c,0x40000100, +0xc30,0x6de9ac44, +0xc34,0x469652cf, +0xc38,0x49795994, +0xc3c,0x0a979764, +0xc40,0x1f7c403f, +0xc44,0x000100b7, +0xc48,0xec020000, +0xc4c,0x007f037f, +0xc50,0x69543420, +0xc54,0x433c0094, +0xc58,0x69543420, +0xc5c,0x433c0094, +0xc60,0x69543420, +0xc64,0x433c0094, +0xc68,0x69543420, +0xc6c,0x433c0094, +0xc70,0x2c7f000d, +0xc74,0x0186155b, +0xc78,0x0000001f, +0xc7c,0x00b91612, +0xc80,0x40000100, +0xc84,0x20f60000, +0xc88,0x20000080, +0xc8c,0x20200000, +0xc90,0x40000100, +0xc94,0x00000000, +0xc98,0x40000100, +0xc9c,0x00000000, +0xca0,0x00492492, +0xca4,0x00000000, +0xca8,0x00000000, +0xcac,0x00000000, +0xcb0,0x00000000, +0xcb4,0x00000000, +0xcb8,0x00000000, +0xcbc,0x28000000, +0xcc0,0x00000000, +0xcc4,0x00000000, +0xcc8,0x00000000, +0xccc,0x00000000, +0xcd0,0x00000000, +0xcd4,0x00000000, +0xcd8,0x64b22427, +0xcdc,0x00766932, +0xce0,0x00222222, +0xce4,0x00000000, +0xce8,0x37644302, +0xcec,0x2f97d40c, +0xd00,0x00000750, +0xd04,0x00000403, +0xd08,0x0000907f, +0xd0c,0x00000001, +0xd10,0xa0633333, +0xd14,0x33333c63, +0xd18,0x6a8f5b6b, +0xd1c,0x00000000, +0xd20,0x00000000, +0xd24,0x00000000, +0xd28,0x00000000, +0xd2c,0xcc979975, +0xd30,0x00000000, +0xd34,0x00000000, +0xd38,0x00000000, +0xd3c,0x00027293, +0xd40,0x00000000, +0xd44,0x00000000, +0xd48,0x00000000, +0xd50,0x6437140a, +0xd54,0x024dbd02, +0xd58,0x00000000, +0xd5c,0x30032064, +0xd60,0x4653de68, +0xd64,0x00518a3c, +0xd68,0x00002101, +0xf14,0x00000003, +0xf4c,0x00000000, +0xf00,0x00000300, +}; + +u32 Rtl8192SUPHY_REG_1T2RArray[PHY_REG_1T2RArrayLength] = { +0x0, }; + +u32 Rtl8192SUPHY_ChangeTo_1T1RArray[PHY_ChangeTo_1T1RArrayLength] = { +0x844,0xffffffff,0x00010000, +0x804,0x0000000f,0x00000001, +0x824,0x00f0000f,0x00300004, +0x82c,0x00f0000f,0x00100002, +0x870,0x04000000,0x00000001, +0x864,0x00000400,0x00000000, +0x878,0x000f000f,0x00000002, +0xe74,0x0f000000,0x00000002, +0xe78,0x0f000000,0x00000002, +0xe7c,0x0f000000,0x00000002, +0xe80,0x0f000000,0x00000002, +0x90c,0x000000ff,0x00000011, +0xc04,0x000000ff,0x00000011, +0xd04,0x0000000f,0x00000001, +0x1f4,0xffff0000,0x00007777, +0x234,0xf8000000,0x0000000a, +}; + +u32 Rtl8192SUPHY_ChangeTo_1T2RArray[PHY_ChangeTo_1T2RArrayLength] = { +0x804,0x0000000f,0x00000003, +0x824,0x00f0000f,0x00300004, +0x82c,0x00f0000f,0x00300002, +0x870,0x04000000,0x00000001, +0x864,0x00000400,0x00000000, +0x878,0x000f000f,0x00000002, +0xe74,0x0f000000,0x00000002, +0xe78,0x0f000000,0x00000002, +0xe7c,0x0f000000,0x00000002, +0xe80,0x0f000000,0x00000002, +0x90c,0x000000ff,0x00000011, +0xc04,0x000000ff,0x00000033, +0xd04,0x0000000f,0x00000003, +0x1f4,0xffff0000,0x00007777, +0x234,0xf8000000,0x0000000a, +}; + +u32 Rtl8192SUPHY_ChangeTo_2T2RArray[PHY_ChangeTo_2T2RArrayLength] = { +0x804,0x0000000f,0x00000003, +0x824,0x00f0000f,0x00300004, +0x82c,0x00f0000f,0x00300004, +0x870,0x04000000,0x00000001, +0x864,0x00000400,0x00000001, +0x878,0x000f000f,0x00020002, +0xe74,0x0f000000,0x00000006, +0xe78,0x0f000000,0x00000006, +0xe7c,0x0f000000,0x00000006, +0xe80,0x0f000000,0x00000006, +0x90c,0x000000ff,0x00000033, +0xc04,0x000000ff,0x00000033, +0xd04,0x0000000f,0x00000003, +0x1f4,0xffff0000,0x0000ffff, +0x234,0xf8000000,0x00000013, +}; + +u32 Rtl8192SUPHY_REG_Array_PG[PHY_REG_Array_PGLength] = { +0xe00,0xffffffff,0x06090909, +0xe04,0xffffffff,0x00030406, +0xe08,0x0000ff00,0x00000000, +0xe10,0xffffffff,0x0a0c0d0e, +0xe14,0xffffffff,0x04070809, +0xe18,0xffffffff,0x0a0c0d0e, +0xe1c,0xffffffff,0x04070809, +}; + +u32 Rtl8192SURadioA_1T_Array[RadioA_1T_ArrayLength] = { +0x000,0x00030159, +0x001,0x00030250, +0x002,0x00010000, +0x010,0x0008000f, +0x011,0x000231fc, +0x010,0x000c000f, +0x011,0x0003f9f8, +0x010,0x0002000f, +0x011,0x00020101, +0x014,0x0001093e, +0x014,0x0009093e, +0x015,0x000198f4, +0x017,0x000f6500, +0x01a,0x00013056, +0x01b,0x00060000, +0x01c,0x00000300, +0x01e,0x00031059, +0x021,0x00054000, +0x022,0x0000083c, +0x023,0x00001558, +0x024,0x00000060, +0x025,0x00022583, +0x026,0x0000f200, +0x027,0x000eacf1, +0x028,0x0009bd54, +0x029,0x00004582, +0x02a,0x00000001, +0x02b,0x00021334, +0x02a,0x00000000, +0x02b,0x0000000a, +0x02a,0x00000001, +0x02b,0x00000808, +0x02b,0x00053333, +0x02c,0x0000000c, +0x02a,0x00000002, +0x02b,0x00000808, +0x02b,0x0005b333, +0x02c,0x0000000d, +0x02a,0x00000003, +0x02b,0x00000808, +0x02b,0x00063333, +0x02c,0x0000000d, +0x02a,0x00000004, +0x02b,0x00000808, +0x02b,0x0006b333, +0x02c,0x0000000d, +0x02a,0x00000005, +0x02b,0x00000709, +0x02b,0x00053333, +0x02c,0x0000000d, +0x02a,0x00000006, +0x02b,0x00000709, +0x02b,0x0005b333, +0x02c,0x0000000d, +0x02a,0x00000007, +0x02b,0x00000709, +0x02b,0x00063333, +0x02c,0x0000000d, +0x02a,0x00000008, +0x02b,0x00000709, +0x02b,0x0006b333, +0x02c,0x0000000d, +0x02a,0x00000009, +0x02b,0x0000060a, +0x02b,0x00053333, +0x02c,0x0000000d, +0x02a,0x0000000a, +0x02b,0x0000060a, +0x02b,0x0005b333, +0x02c,0x0000000d, +0x02a,0x0000000b, +0x02b,0x0000060a, +0x02b,0x00063333, +0x02c,0x0000000d, +0x02a,0x0000000c, +0x02b,0x0000060a, +0x02b,0x0006b333, +0x02c,0x0000000d, +0x02a,0x0000000d, +0x02b,0x0000050b, +0x02b,0x00053333, +0x02c,0x0000000d, +0x02a,0x0000000e, +0x02b,0x0000050b, +0x02b,0x00066623, +0x02c,0x0000001a, +0x02a,0x000e4000, +0x030,0x00020000, +0x031,0x000b9631, +0x032,0x0000130d, +0x033,0x00000187, +0x013,0x00019e6c, +0x013,0x00015e94, +0x000,0x00010159, +0x018,0x0000f401, +0x0fe,0x00000000, +0x01e,0x0003105b, +0x0fe,0x00000000, +0x000,0x00030159, +0x010,0x0004000f, +0x011,0x000203f9, +}; + +u32 Rtl8192SURadioB_Array[RadioB_ArrayLength] = { +0x000,0x00030159, +0x001,0x00001041, +0x002,0x00011000, +0x005,0x00080fc0, +0x007,0x000fc803, +0x013,0x00017cb0, +0x013,0x00011cc0, +0x013,0x0000dc60, +0x013,0x00008c60, +0x013,0x00004450, +0x013,0x00000020, +}; + +u32 Rtl8192SURadioA_to1T_Array[RadioA_to1T_ArrayLength] = { +0x000,0x00000000, +}; + +u32 Rtl8192SURadioA_to2T_Array[RadioA_to2T_ArrayLength] = { +0x000,0x00000000, +}; + +u32 Rtl8192SURadioB_GM_Array[RadioB_GM_ArrayLength] = { +0x000,0x00030159, +0x001,0x00001041, +0x002,0x00011000, +0x005,0x00080fc0, +0x007,0x000fc803, +0x013,0x0000bef0, +0x013,0x00007e90, +0x013,0x00003e30, +}; + +u32 Rtl8192SUMAC_2T_Array[MAC_2T_ArrayLength] = { +0x020,0x00000035, +0x048,0x0000000e, +0x049,0x000000f0, +0x04a,0x00000077, +0x04b,0x00000083, +0x0b5,0x00000021, +0x0dc,0x000000ff, +0x0dd,0x000000ff, +0x0de,0x000000ff, +0x0df,0x000000ff, +0x116,0x00000000, +0x117,0x00000000, +0x118,0x00000000, +0x119,0x00000000, +0x11a,0x00000000, +0x11b,0x00000000, +0x11c,0x00000000, +0x11d,0x00000000, +0x160,0x0000000b, +0x161,0x0000000b, +0x162,0x0000000b, +0x163,0x0000000b, +0x164,0x0000000b, +0x165,0x0000000b, +0x166,0x0000000b, +0x167,0x0000000b, +0x168,0x0000000b, +0x169,0x0000000b, +0x16a,0x0000000b, +0x16b,0x0000000b, +0x16c,0x0000000b, +0x16d,0x0000000b, +0x16e,0x0000000b, +0x16f,0x0000000b, +0x170,0x0000000b, +0x171,0x0000000b, +0x172,0x0000000b, +0x173,0x0000000b, +0x174,0x0000000b, +0x175,0x0000000b, +0x176,0x0000000b, +0x177,0x0000000b, +0x178,0x0000000b, +0x179,0x0000000b, +0x17a,0x0000000b, +0x17b,0x0000000b, +0x17c,0x0000000b, +0x17d,0x0000000b, +0x17e,0x0000000b, +0x17f,0x0000000b, +0x236,0x0000000c, +0x503,0x00000022, +0x560,0x00000009, +}; + +u32 Rtl8192SUMACPHY_Array_PG[MACPHY_Array_PGLength] = { +0x0, }; + +u32 Rtl8192SUAGCTAB_Array[AGCTAB_ArrayLength] = { +0xc78,0x7f000001, +0xc78,0x7f010001, +0xc78,0x7e020001, +0xc78,0x7d030001, +0xc78,0x7c040001, +0xc78,0x7b050001, +0xc78,0x7a060001, +0xc78,0x79070001, +0xc78,0x78080001, +0xc78,0x77090001, +0xc78,0x760a0001, +0xc78,0x750b0001, +0xc78,0x740c0001, +0xc78,0x730d0001, +0xc78,0x720e0001, +0xc78,0x710f0001, +0xc78,0x70100001, +0xc78,0x6f110001, +0xc78,0x6f120001, +0xc78,0x6e130001, +0xc78,0x6d140001, +0xc78,0x6d150001, +0xc78,0x6c160001, +0xc78,0x6b170001, +0xc78,0x6a180001, +0xc78,0x6a190001, +0xc78,0x691a0001, +0xc78,0x681b0001, +0xc78,0x671c0001, +0xc78,0x661d0001, +0xc78,0x651e0001, +0xc78,0x641f0001, +0xc78,0x63200001, +0xc78,0x4c210001, +0xc78,0x4b220001, +0xc78,0x4a230001, +0xc78,0x49240001, +0xc78,0x48250001, +0xc78,0x47260001, +0xc78,0x46270001, +0xc78,0x45280001, +0xc78,0x44290001, +0xc78,0x2c2a0001, +0xc78,0x2b2b0001, +0xc78,0x2a2c0001, +0xc78,0x292d0001, +0xc78,0x282e0001, +0xc78,0x272f0001, +0xc78,0x26300001, +0xc78,0x25310001, +0xc78,0x24320001, +0xc78,0x23330001, +0xc78,0x22340001, +0xc78,0x09350001, +0xc78,0x08360001, +0xc78,0x07370001, +0xc78,0x06380001, +0xc78,0x05390001, +0xc78,0x043a0001, +0xc78,0x033b0001, +0xc78,0x023c0001, +0xc78,0x013d0001, +0xc78,0x003e0001, +0xc78,0x003f0001, +0xc78,0x7f400001, +0xc78,0x7f410001, +0xc78,0x7e420001, +0xc78,0x7d430001, +0xc78,0x7c440001, +0xc78,0x7b450001, +0xc78,0x7a460001, +0xc78,0x79470001, +0xc78,0x78480001, +0xc78,0x77490001, +0xc78,0x764a0001, +0xc78,0x754b0001, +0xc78,0x744c0001, +0xc78,0x734d0001, +0xc78,0x724e0001, +0xc78,0x714f0001, +0xc78,0x70500001, +0xc78,0x6f510001, +0xc78,0x6f520001, +0xc78,0x6e530001, +0xc78,0x6d540001, +0xc78,0x6d550001, +0xc78,0x6c560001, +0xc78,0x6b570001, +0xc78,0x6a580001, +0xc78,0x6a590001, +0xc78,0x695a0001, +0xc78,0x685b0001, +0xc78,0x675c0001, +0xc78,0x665d0001, +0xc78,0x655e0001, +0xc78,0x645f0001, +0xc78,0x63600001, +0xc78,0x4c610001, +0xc78,0x4b620001, +0xc78,0x4a630001, +0xc78,0x49640001, +0xc78,0x48650001, +0xc78,0x47660001, +0xc78,0x46670001, +0xc78,0x45680001, +0xc78,0x44690001, +0xc78,0x2c6a0001, +0xc78,0x2b6b0001, +0xc78,0x2a6c0001, +0xc78,0x296d0001, +0xc78,0x286e0001, +0xc78,0x276f0001, +0xc78,0x26700001, +0xc78,0x25710001, +0xc78,0x24720001, +0xc78,0x23730001, +0xc78,0x22740001, +0xc78,0x09750001, +0xc78,0x08760001, +0xc78,0x07770001, +0xc78,0x06780001, +0xc78,0x05790001, +0xc78,0x047a0001, +0xc78,0x037b0001, +0xc78,0x027c0001, +0xc78,0x017d0001, +0xc78,0x007e0001, +0xc78,0x007f0001, +0xc78,0x3000001e, +0xc78,0x3001001e, +0xc78,0x3002001e, +0xc78,0x3003001e, +0xc78,0x3004001e, +0xc78,0x3405001e, +0xc78,0x3806001e, +0xc78,0x3e07001e, +0xc78,0x3e08001e, +0xc78,0x4409001e, +0xc78,0x460a001e, +0xc78,0x480b001e, +0xc78,0x480c001e, +0xc78,0x4e0d001e, +0xc78,0x560e001e, +0xc78,0x5a0f001e, +0xc78,0x5e10001e, +0xc78,0x6211001e, +0xc78,0x6c12001e, +0xc78,0x7213001e, +0xc78,0x7214001e, +0xc78,0x7215001e, +0xc78,0x7216001e, +0xc78,0x7217001e, +0xc78,0x7218001e, +0xc78,0x7219001e, +0xc78,0x721a001e, +0xc78,0x721b001e, +0xc78,0x721c001e, +0xc78,0x721d001e, +0xc78,0x721e001e, +0xc78,0x721f001e, +}; + diff --git a/drivers/staging/rtl8192su/r8192SU_HWImg.h b/drivers/staging/rtl8192su/r8192SU_HWImg.h new file mode 100644 index 000000000000..96b15252ea86 --- /dev/null +++ b/drivers/staging/rtl8192su/r8192SU_HWImg.h @@ -0,0 +1,44 @@ +#ifndef __INC_HAL8192SU_FW_IMG_H +#define __INC_HAL8192SU_FW_IMG_H + +#include <linux/types.h> + +/*Created on 2009/ 3/ 6, 5:29*/ + +#define ImgArrayLength 68368 +extern u8 Rtl8192SUFwImgArray[ImgArrayLength]; +#define MainArrayLength 1 +extern u8 Rtl8192SUFwMainArray[MainArrayLength]; +#define DataArrayLength 1 +extern u8 Rtl8192SUFwDataArray[DataArrayLength]; +#define PHY_REG_2T2RArrayLength 372 +extern u32 Rtl8192SUPHY_REG_2T2RArray[PHY_REG_2T2RArrayLength]; +#define PHY_REG_1T2RArrayLength 1 +extern u32 Rtl8192SUPHY_REG_1T2RArray[PHY_REG_1T2RArrayLength]; +#define PHY_ChangeTo_1T1RArrayLength 48 +extern u32 Rtl8192SUPHY_ChangeTo_1T1RArray[PHY_ChangeTo_1T1RArrayLength]; +#define PHY_ChangeTo_1T2RArrayLength 45 +extern u32 Rtl8192SUPHY_ChangeTo_1T2RArray[PHY_ChangeTo_1T2RArrayLength]; +#define PHY_ChangeTo_2T2RArrayLength 45 +extern u32 Rtl8192SUPHY_ChangeTo_2T2RArray[PHY_ChangeTo_2T2RArrayLength]; +#define PHY_REG_Array_PGLength 21 +extern u32 Rtl8192SUPHY_REG_Array_PG[PHY_REG_Array_PGLength]; +#define RadioA_1T_ArrayLength 202 +extern u32 Rtl8192SURadioA_1T_Array[RadioA_1T_ArrayLength]; +#define RadioB_ArrayLength 22 +extern u32 Rtl8192SURadioB_Array[RadioB_ArrayLength]; +#define RadioA_to1T_ArrayLength 2 +extern u32 Rtl8192SURadioA_to1T_Array[RadioA_to1T_ArrayLength]; +#define RadioA_to2T_ArrayLength 2 +extern u32 Rtl8192SURadioA_to2T_Array[RadioA_to2T_ArrayLength]; +#define RadioB_GM_ArrayLength 16 +extern u32 Rtl8192SURadioB_GM_Array[RadioB_GM_ArrayLength]; +#define MAC_2T_ArrayLength 106 +extern u32 Rtl8192SUMAC_2T_Array[MAC_2T_ArrayLength]; +#define MACPHY_Array_PGLength 1 +extern u32 Rtl8192SUMACPHY_Array_PG[MACPHY_Array_PGLength]; +#define AGCTAB_ArrayLength 320 +extern u32 Rtl8192SUAGCTAB_Array[AGCTAB_ArrayLength]; + +#endif //__INC_HAL8192SU_FW_IMG_H + diff --git a/drivers/staging/rtl8192su/r8192S_Efuse.c b/drivers/staging/rtl8192su/r8192S_Efuse.c new file mode 100644 index 000000000000..394ab9674359 --- /dev/null +++ b/drivers/staging/rtl8192su/r8192S_Efuse.c @@ -0,0 +1,2442 @@ +/****************************************************************************** + * + * (c) Copyright 2008, RealTEK Technologies Inc. All Rights Reserved. + * + * Module: Efuse.c ( Source C File) + * + * Note: Copy from WMAC for the first version!!!! + * + * + * Function: + * + * Export: + * + * Abbrev: + * + * History: + * Data Who Remark + * + * 09/23/2008 MHC Porting Efuse R/W API from WMAC. + * 11/10/2008 MHC 1. Porting from 8712 EFUSE. + * 2. Add description and reorganize code arch. + * 11/16/2008 MHC 1. Reorganize code architecture. + * 2. Rename for some API and change extern or static type. + * +******************************************************************************/ +#include "r8192U.h" +#include "r8192S_hw.h" +#include "r8192S_phy.h" +#include "r8192S_phyreg.h" +#include "r8192S_Efuse.h" + +#include <linux/types.h> + +//typedef int INT32; +// +// In the future, we will always support EFUSE!! +// +#ifdef RTL8192SU +/*---------------------------Define Local Constant---------------------------*/ +#define _POWERON_DELAY_ +#define _PRE_EXECUTE_READ_CMD_ + +#define EFUSE_REPEAT_THRESHOLD_ 3 +#define EFUSE_ERROE_HANDLE 1 + + +// From 8712!!!!! +typedef struct _EFUSE_MAP_A{ + u8 offset; //0~15 + u8 word_start; //0~3 + u8 byte_start; //0 or 1 + u8 byte_cnts; + +}EFUSE_MAP, *PEFUSE_MAP; + +typedef struct PG_PKT_STRUCT_A{ + u8 offset; + u8 word_en; + u8 data[8]; +}PGPKT_STRUCT,*PPGPKT_STRUCT; + +typedef enum _EFUSE_DATA_ITEM{ + EFUSE_CHIP_ID=0, + EFUSE_LDO_SETTING, + EFUSE_CLK_SETTING, + EFUSE_SDIO_SETTING, + EFUSE_CCCR, + EFUSE_SDIO_MODE, + EFUSE_OCR, + EFUSE_F0CIS, + EFUSE_F1CIS, + EFUSE_MAC_ADDR, + EFUSE_EEPROM_VER, + EFUSE_CHAN_PLAN, + EFUSE_TXPW_TAB +} EFUSE_DATA_ITEM; + +struct efuse_priv +{ + u8 id[2]; + u8 ldo_setting[2]; + u8 clk_setting[2]; + u8 cccr; + u8 sdio_mode; + u8 ocr[3]; + u8 cis0[17]; + u8 cis1[48]; + u8 mac_addr[6]; + u8 eeprom_verno; + u8 channel_plan; + u8 tx_power_b[14]; + u8 tx_power_g[14]; +}; + +/*---------------------------Define Local Constant---------------------------*/ + + +/*------------------------Define global variable-----------------------------*/ +const u8 MAX_PGPKT_SIZE = 9; //header+ 2* 4 words (BYTES) +const u8 PGPKT_DATA_SIZE = 8; //BYTES sizeof(u8)*8 +const u32 EFUSE_MAX_SIZE = 512; + + +const EFUSE_MAP RTL8712_SDIO_EFUSE_TABLE[]={ + //offset word_s byte_start byte_cnts +/*ID*/ {0 ,0 ,0 ,2 }, // 00~01h +/*LDO Setting*/ {0 ,1 ,0 ,2 }, // 02~03h +/*CLK Setting*/ {0 ,2 ,0 ,2 }, // 04~05h +/*SDIO Setting*/ {1 ,0 ,0 ,1 }, // 08h +/*CCCR*/ {1 ,0 ,1 ,1 }, // 09h +/*SDIO MODE*/ {1 ,1 ,0 ,1 }, // 0Ah +/*OCR*/ {1 ,1 ,1 ,3 }, // 0B~0Dh +/*CCIS*/ {1 ,3 ,0 ,17 }, // 0E~1Eh 2...1 +/*F1CIS*/ {3 ,3 ,1 ,48 }, // 1F~4Eh 6...0 +/*MAC Addr*/ {10 ,0 ,0 ,6 }, // 50~55h +/*EEPROM ver*/ {10 ,3 ,0 ,1 }, // 56h +/*Channel plan*/ {10 ,3 ,1 ,1 }, // 57h +/*TxPwIndex */ {11 ,0 ,0 ,28 } // 58~73h 3...4 +}; + +/*------------------------Define global variable-----------------------------*/ + + +/*------------------------Define local variable------------------------------*/ + +/*------------------------Define local variable------------------------------*/ + + +/*--------------------Define function prototype-----------------------*/ +// +// From WMAC Efuse one byte R/W +// +extern void +EFUSE_Initialize(struct net_device* dev); +extern u8 +EFUSE_Read1Byte(struct net_device* dev, u16 Address); +extern void +EFUSE_Write1Byte(struct net_device* dev, u16 Address,u8 Value); + +// +// Efuse Shadow Area operation +// +static void +efuse_ShadowRead1Byte(struct net_device* dev,u16 Offset,u8 *Value); +static void +efuse_ShadowRead2Byte(struct net_device* dev, u16 Offset,u16 *Value ); +static void +efuse_ShadowRead4Byte(struct net_device* dev, u16 Offset,u32 *Value ); +static void +efuse_ShadowWrite1Byte(struct net_device* dev, u16 Offset, u8 Value); +static void +efuse_ShadowWrite2Byte(struct net_device* dev, u16 Offset,u16 Value); +static void +efuse_ShadowWrite4Byte(struct net_device* dev, u16 Offset,u32 Value); + +// +// Real Efuse operation +// +static u8 +efuse_OneByteRead(struct net_device* dev,u16 addr,u8 *data); +static u8 +efuse_OneByteWrite(struct net_device* dev,u16 addr, u8 data); + +// +// HW setting map file operation +// +static void +efuse_ReadAllMap(struct net_device* dev,u8 *Efuse); +#ifdef TO_DO_LIST +static void +efuse_WriteAllMap(struct net_device* dev,u8 *eeprom,u32 eeprom_size); +static bool +efuse_ParsingMap(char* szStr,u32* pu4bVal,u32* pu4bMove); +#endif +// +// Reald Efuse R/W or other operation API. +// +static u8 +efuse_PgPacketRead( struct net_device* dev,u8 offset,u8 *data); +static u8 +efuse_PgPacketWrite(struct net_device* dev,u8 offset,u8 word_en,u8 *data); +static void +efuse_WordEnableDataRead( u8 word_en,u8 *sourdata,u8 *targetdata); +static u8 +efuse_WordEnableDataWrite( struct net_device* dev, u16 efuse_addr, u8 word_en, u8 *data); +static void +efuse_PowerSwitch(struct net_device* dev,u8 PwrState); +static u16 +efuse_GetCurrentSize(struct net_device* dev); +static u8 +efuse_CalculateWordCnts(u8 word_en); +#if 0 +static void +efuse_ResetLoader(struct net_device* dev); +#endif +// +// API for power on power off!!! +// +#ifdef TO_DO_LIST +static void efuse_reg_ctrl(struct net_device* dev, u8 bPowerOn); +#endif +/*--------------------Define function prototype-----------------------*/ + + + +/*----------------------------------------------------------------------------- + * Function: EFUSE_Initialize + * + * Overview: Copy from WMAC fot EFUSE testing setting init. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 09/23/2008 MHC Copy from WMAC. + * + *---------------------------------------------------------------------------*/ +extern void +EFUSE_Initialize(struct net_device* dev) +{ + u8 Bytetemp = {0x00}; + u8 temp = {0x00}; + + //Enable Digital Core Vdd : 0x2[13]=1 + Bytetemp = read_nic_byte(dev, SYS_FUNC_EN+1); + temp = Bytetemp | 0x20; + write_nic_byte(dev, SYS_FUNC_EN+1, temp); + + //EE loader to retention path1: attach 0x0[8]=0 + Bytetemp = read_nic_byte(dev, SYS_ISO_CTRL+1); + temp = Bytetemp & 0xFE; + write_nic_byte(dev, SYS_ISO_CTRL+1, temp); + + + //Enable E-fuse use 2.5V LDO : 0x37[7]=1 + Bytetemp = read_nic_byte(dev, EFUSE_TEST+3); + temp = Bytetemp | 0x80; + write_nic_byte(dev, EFUSE_TEST+3, temp); + + //E-fuse clk switch from 500k to 40M : 0x2F8[1:0]=11b + write_nic_byte(dev, 0x2F8, 0x3); + + //Set E-fuse program time & read time : 0x30[30:24]=1110010b + write_nic_byte(dev, EFUSE_CTRL+3, 0x72); + +} /* EFUSE_Initialize */ + + +/*----------------------------------------------------------------------------- + * Function: EFUSE_Read1Byte + * + * Overview: Copy from WMAC fot EFUSE read 1 byte. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 09/23/2008 MHC Copy from WMAC. + * + *---------------------------------------------------------------------------*/ +extern u8 +EFUSE_Read1Byte(struct net_device* dev, u16 Address) +{ + u8 data; + u8 Bytetemp = {0x00}; + u8 temp = {0x00}; + u32 k=0; + + if (Address < EFUSE_MAC_LEN) //E-fuse 512Byte + { + //Write E-fuse Register address bit0~7 + temp = Address & 0xFF; + write_nic_byte(dev, EFUSE_CTRL+1, temp); + Bytetemp = read_nic_byte(dev, EFUSE_CTRL+2); + //Write E-fuse Register address bit8~9 + temp = ((Address >> 8) & 0x03) | (Bytetemp & 0xFC); + write_nic_byte(dev, EFUSE_CTRL+2, temp); + + //Write 0x30[31]=0 + Bytetemp = read_nic_byte(dev, EFUSE_CTRL+3); + temp = Bytetemp & 0x7F; + write_nic_byte(dev, EFUSE_CTRL+3, temp); + + //Wait Write-ready (0x30[31]=1) + Bytetemp = read_nic_byte(dev, EFUSE_CTRL+3); + while(!(Bytetemp & 0x80)) + { + Bytetemp = read_nic_byte(dev, EFUSE_CTRL+3); + k++; + if(k==1000) + { + k=0; + break; + } + } + data=read_nic_byte(dev, EFUSE_CTRL); + return data; + } + else + return 0xFF; + +} /* EFUSE_Read1Byte */ + + +/*----------------------------------------------------------------------------- + * Function: EFUSE_Write1Byte + * + * Overview: Copy from WMAC fot EFUSE write 1 byte. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 09/23/2008 MHC Copy from WMAC. + * + *---------------------------------------------------------------------------*/ +extern void +EFUSE_Write1Byte(struct net_device* dev, u16 Address,u8 Value) +{ + //u8 data; + u8 Bytetemp = {0x00}; + u8 temp = {0x00}; + u32 k=0; + + //RT_TRACE(COMP_EFUSE, "Addr=%x Data =%x\n", Address, Value); + + if( Address < EFUSE_MAC_LEN) //E-fuse 512Byte + { + write_nic_byte(dev, EFUSE_CTRL, Value); + + //Write E-fuse Register address bit0~7 + temp = Address & 0xFF; + write_nic_byte(dev, EFUSE_CTRL+1, temp); + Bytetemp = read_nic_byte(dev, EFUSE_CTRL+2); + + //Write E-fuse Register address bit8~9 + temp = ((Address >> 8) & 0x03) | (Bytetemp & 0xFC); + write_nic_byte(dev, EFUSE_CTRL+2, temp); + + //Write 0x30[31]=1 + Bytetemp = read_nic_byte(dev, EFUSE_CTRL+3); + temp = Bytetemp | 0x80; + write_nic_byte(dev, EFUSE_CTRL+3, temp); + + //Wait Write-ready (0x30[31]=0) + Bytetemp = read_nic_byte(dev, EFUSE_CTRL+3); + while(Bytetemp & 0x80) + { + Bytetemp = read_nic_byte(dev, EFUSE_CTRL+3); + k++; + if(k==100) + { + k=0; + break; + } + } + } + +} /* EFUSE_Write1Byte */ + + +#ifdef EFUSE_FOR_92SU +// +// Description: +// 1. Process CR93C46 Data polling cycle. +// 2. Refered from SD1 Richard. +// +// Assumption: +// 1. Boot from E-Fuse and successfully auto-load. +// 2. PASSIVE_LEVEL (USB interface) +// +// Created by Roger, 2008.10.21. +// +void do_93c46(struct net_device* dev, u8 addorvalue) +{ + //u8 clear[1] = {0x0}; // cs=0 , sk=0 , di=0 , do=0 + u8 cs[1] = {0x88}; // cs=1 , sk=0 , di=0 , do=0 + u8 cssk[1] = {0x8c}; // cs=1 , sk=1 , di=0 , do=0 + u8 csdi[1] = {0x8a}; // cs=1 , sk=0 , di=1 , do=0 + u8 csskdi[1] = {0x8e}; // cs=1 , sk=1 , di=1 , do=0 + //u8 di[1] = {0x82}; // cs=0 , sk=0 , di=1 , do=0 + u8 count; + + for(count=0 ; count<8 ; count++) + { + if((addorvalue&0x80)!=0) + { + write_nic_byte(dev, EPROM_CMD, csdi[0]); + write_nic_byte(dev, EPROM_CMD, csskdi[0]); + } + else + { + write_nic_byte(dev, EPROM_CMD, cs[0]); + write_nic_byte(dev, EPROM_CMD, cssk[0]); + } + addorvalue = addorvalue << 1; + } +} + + +// +// Description: +// Process CR93C46 Data read polling cycle. +// Refered from SD1 Richard. +// +// Assumption: +// 1. Boot from E-Fuse and successfully auto-load. +// 2. PASSIVE_LEVEL (USB interface) +// +// Created by Roger, 2008.10.21. +// +u16 Read93C46(struct net_device* dev, u16 Reg ) +{ + + u8 clear[1] = {0x0}; // cs=0 , sk=0 , di=0 , do=0 + u8 cs[1] = {0x88}; // cs=1 , sk=0 , di=0 , do=0 + u8 cssk[1] = {0x8c}; // cs=1 , sk=1 , di=0 , do=0 + u8 csdi[1] = {0x8a}; // cs=1 , sk=0 , di=1 , do=0 + u8 csskdi[1] = {0x8e}; // cs=1 , sk=1 , di=1 , do=0 + //u8 di[1] = {0x82}; // cs=0 , sk=0 , di=1 , do=0 + u8 EepromSEL[1]={0x00}; + u8 address; + + u16 storedataF[1] = {0x0}; //93c46 data packet for 16bits + u8 t,data[1],storedata[1]; + + + address = (u8)Reg; + + // Suggested by SD1 Alex, 2008.10.20. Revised by Roger. + *EepromSEL= read_nic_byte(dev, EPROM_CMD); + + if((*EepromSEL & 0x10) == 0x10) // select 93c46 + { + address = address | 0x80; + + write_nic_byte(dev, EPROM_CMD, csdi[0]); + write_nic_byte(dev, EPROM_CMD, csskdi[0]); + do_93c46(dev, address); + } + + + for(t=0 ; t<16 ; t++) //if read 93c46 , t=16 + { + write_nic_byte(dev, EPROM_CMD, cs[0]); + write_nic_byte(dev, EPROM_CMD, cssk[0]); + *data= read_nic_byte(dev, EPROM_CMD); + + if(*data & 0x8d) //original code + { + *data = *data & 0x01; + *storedata = *data; + } + else + { + *data = *data & 0x01 ; + *storedata = *data; + } + *storedataF = (*storedataF << 1 ) + *storedata; + } + write_nic_byte(dev, EPROM_CMD, cs[0]); + write_nic_byte(dev, EPROM_CMD, clear[0]); + + return *storedataF; +} + + +// +// Description: +// Execute E-Fuse read byte operation. +// Refered from SD1 Richard. +// +// Assumption: +// 1. Boot from E-Fuse and successfully auto-load. +// 2. PASSIVE_LEVEL (USB interface) +// +// Created by Roger, 2008.10.21. +// +void +ReadEFuseByte(struct net_device* dev,u16 _offset, u8 *pbuf) +{ + + //u16 indexk=0; + u32 value32; + u8 readbyte; + u16 retry; + + + //Write Address + write_nic_byte(dev, EFUSE_CTRL+1, (_offset & 0xff)); + readbyte = read_nic_byte(dev, EFUSE_CTRL+2); + write_nic_byte(dev, EFUSE_CTRL+2, ((_offset >> 8) & 0x03) | (readbyte & 0xfc)); + + //Write bit 32 0 + readbyte = read_nic_byte(dev, EFUSE_CTRL+3); + write_nic_byte(dev, EFUSE_CTRL+3, (readbyte & 0x7f)); + + //Check bit 32 read-ready + retry = 0; + value32 = read_nic_dword(dev, EFUSE_CTRL); + //while(!(((value32 >> 24) & 0xff) & 0x80) && (retry<10)) + while(!(((value32 >> 24) & 0xff) & 0x80) && (retry<10000)) + { + value32 = read_nic_dword(dev, EFUSE_CTRL); + retry++; + } + *pbuf = (u8)(value32 & 0xff); +} + + +#define EFUSE_READ_SWITCH 1 +// +// Description: +// 1. Execute E-Fuse read byte operation according as map offset and +// save to E-Fuse table. +// 2. Refered from SD1 Richard. +// +// Assumption: +// 1. Boot from E-Fuse and successfully auto-load. +// 2. PASSIVE_LEVEL (USB interface) +// +// Created by Roger, 2008.10.21. +// +void +ReadEFuse(struct net_device* dev, u16 _offset, u16 _size_byte, u8 *pbuf) +{ + + u8 efuseTbl[128]; + u8 rtemp8[1]; + u16 eFuse_Addr = 0; + u8 offset, wren; + u16 i, j; + u16 eFuseWord[16][4];// = {0xFF};//FIXLZM + + for(i=0; i<16; i++) + for(j=0; j<4; j++) + eFuseWord[i][j]=0xFF; + + // Do NOT excess total size of EFuse table. Added by Roger, 2008.11.10. + if((_offset + _size_byte)>128) + {// total E-Fuse table is 128bytes + //RT_TRACE(COMP_EFUSE, "ReadEFuse(): Invalid offset(%#x) with read bytes(%#x)!!\n",_offset, _size_byte); + printk("ReadEFuse(): Invalid offset with read bytes!!\n"); + return; + } + + // Refresh efuse init map as all oxFF. + for (i = 0; i < 128; i++) + efuseTbl[i] = 0xFF; + +#if (EFUSE_READ_SWITCH == 1) + ReadEFuseByte(dev, eFuse_Addr, rtemp8); +#else + rtemp8[0] = EFUSE_Read1Byte(dev, eFuse_Addr); +#endif + if(*rtemp8 != 0xFF) eFuse_Addr++; + while((*rtemp8 != 0xFF) && (eFuse_Addr < 512)){ + offset = ((*rtemp8 >> 4) & 0x0f); + if(offset <= 0x0F){ + wren = (*rtemp8 & 0x0f); + for(i=0; i<4; i++){ + if(!(wren & 0x01)){ +#if (EFUSE_READ_SWITCH == 1) + ReadEFuseByte(dev, eFuse_Addr, rtemp8); eFuse_Addr++; +#else + rtemp8[0] = EFUSE_Read1Byte(dev, eFuse_Addr); eFuse_Addr++; +#endif + eFuseWord[offset][i] = (*rtemp8 & 0xff); + if(eFuse_Addr >= 512) break; +#if (EFUSE_READ_SWITCH == 1) + ReadEFuseByte(dev, eFuse_Addr, rtemp8); eFuse_Addr++; +#else + rtemp8[0] = EFUSE_Read1Byte(dev, eFuse_Addr); eFuse_Addr++; +#endif + eFuseWord[offset][i] |= (((u16)*rtemp8 << 8) & 0xff00); + if(eFuse_Addr >= 512) break; + } + wren >>= 1; + } + } +#if (EFUSE_READ_SWITCH == 1) + ReadEFuseByte(dev, eFuse_Addr, rtemp8); +#else + rtemp8[0] = EFUSE_Read1Byte(dev, eFuse_Addr); eFuse_Addr++; +#endif + if(*rtemp8 != 0xFF && (eFuse_Addr < 512)) eFuse_Addr++; + } + + for(i=0; i<16; i++){ + for(j=0; j<4; j++){ + efuseTbl[(i*8)+(j*2)]=(eFuseWord[i][j] & 0xff); + efuseTbl[(i*8)+((j*2)+1)]=((eFuseWord[i][j] >> 8) & 0xff); + } + } + for(i=0; i<_size_byte; i++) + pbuf[i] = efuseTbl[_offset+i]; +} +#endif // #if (EFUSE_FOR_92SU == 1) + + +/*----------------------------------------------------------------------------- + * Function: EFUSE_ShadowRead + * + * Overview: Read from efuse init map !!!!! + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 11/12/2008 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +extern void +EFUSE_ShadowRead( struct net_device* dev, u8 Type, u16 Offset, u32 *Value) +{ + //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + if (Type == 1) + efuse_ShadowRead1Byte(dev, Offset, (u8 *)Value); + else if (Type == 2) + efuse_ShadowRead2Byte(dev, Offset, (u16 *)Value); + else if (Type == 4) + efuse_ShadowRead4Byte(dev, Offset, (u32 *)Value); + +} // EFUSE_ShadowRead + + +/*----------------------------------------------------------------------------- + * Function: EFUSE_ShadowWrite + * + * Overview: Write efuse modify map for later update operation to use!!!!! + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 11/12/2008 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +extern void +EFUSE_ShadowWrite( struct net_device* dev, u8 Type, u16 Offset,u32 Value) +{ + //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + if (Offset >= 0x18 && Offset <= 0x1F) + return; + + if (Type == 1) + efuse_ShadowWrite1Byte(dev, Offset, (u8)Value); + else if (Type == 2) + efuse_ShadowWrite2Byte(dev, Offset, (u16)Value); + else if (Type == 4) + efuse_ShadowWrite4Byte(dev, Offset, (u32)Value); + +} // EFUSE_ShadowWrite + + +/*----------------------------------------------------------------------------- + * Function: EFUSE_ShadowUpdate + * + * Overview: Compare init and modify map to update Efuse!!!!! + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 11/12/2008 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +extern void +EFUSE_ShadowUpdate(struct net_device* dev) +{ + //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + struct r8192_priv *priv = ieee80211_priv(dev); + u16 i, offset, base = 0; + u8 word_en = 0x0F; + bool first_pg = false; + // For Efuse write action, we must enable LDO2.5V and 40MHZ clk. + efuse_PowerSwitch(dev, TRUE); + + // + // Efuse support 16 write are with PG header packet!!!! + // + for (offset = 0; offset < 16; offset++) + { + // Offset 0x18-1F are reserved now!!! +#ifdef RTL8192SE + if(priv->card_8192 == NIC_8192SE){ + if (offset == 3) + continue; + } +#endif + word_en = 0x0F; + base = offset * 8; + + // + // Decide Word Enable Bit for the Efuse section + // One section contain 4 words = 8 bytes!!!!! + // + for (i = 0; i < 8; i++) + { + if (offset == 0 && priv->EfuseMap[EFUSE_INIT_MAP][base+i] == 0xFF) + { + first_pg = TRUE; + } + + // 2008/12/11 MH HW autoload fail workaround for A/BCUT. +#ifdef RTL8192SE + if (first_pg == TRUE && offset == 1 && (priv->card_8192 == NIC_8192SE)) + { + continue; + } +#endif + + if (first_pg == TRUE) + { + word_en &= ~(1<<(i/2)); + priv->EfuseMap[EFUSE_INIT_MAP][base+i] = + priv->EfuseMap[EFUSE_MODIFY_MAP][base+i]; + }else + { + if ( priv->EfuseMap[EFUSE_INIT_MAP][base+i] != + priv->EfuseMap[EFUSE_MODIFY_MAP][base+i]) + { + word_en &= ~(EFUSE_BIT(i/2)); + //RT_TRACE(COMP_EFUSE, "Offset=%d Addr%x %x ==> %x Word_En=%02x\n", + //offset, base+i, priv->EfuseMap[0][base+i], priv->EfuseMap[1][base+i],word_en); + + // Update init table!!! + priv->EfuseMap[EFUSE_INIT_MAP][base+i] = + priv->EfuseMap[EFUSE_MODIFY_MAP][base+i]; + } + } + } + + // + // Call Efuse real write section !!!! + // + if (word_en != 0x0F) + { + u8 tmpdata[8]; + + //FIXLZM + memcpy(tmpdata, &(priv->EfuseMap[EFUSE_MODIFY_MAP][base]), 8); + //RT_PRINT_DATA(COMP_INIT, DBG_LOUD, ("U-EFUSE\n"), tmpdata, 8); + efuse_PgPacketWrite(dev,(u8)offset,word_en,tmpdata); + } + + } + // 2008/12/01 MH For Efuse HW load bug workarounf method!!!! + // We will force write 0x10EC into address 10&11 after all Efuse content. + // +#ifdef RTL8192SE + if (first_pg == TRUE && (priv->card_8192 == NIC_8192SE)) + { + // 2008/12/11 MH Use new method to prevent HW autoload fail. + u8 tmpdata[8]; + + memcpy(tmpdata, (&priv->EfuseMap[EFUSE_MODIFY_MAP][8]), 8); + efuse_PgPacketWrite(dev, 1, 0x0, tmpdata); +#if 0 + u1Byte tmpdata[8] = {0xFF, 0xFF, 0xEC, 0x10, 0xFF, 0xFF, 0xFF, 0xFF}; + + efuse_PgPacketWrite(pAdapter, 1, 0xD, tmpdata); +#endif + } +#endif + + + // For warm reboot, we must resume Efuse clock to 500K. + efuse_PowerSwitch(dev, FALSE); + // 2008/12/01 MH We update shadow content again!!!! + EFUSE_ShadowMapUpdate(dev); + +} // EFUSE_ShadowUpdate + + +/*----------------------------------------------------------------------------- + * Function: EFUSE_ShadowMapUpdate + * + * Overview: Transfer current EFUSE content to shadow init and modify map. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 11/13/2008 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +extern void EFUSE_ShadowMapUpdate(struct net_device* dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + + if (priv->AutoloadFailFlag == true){ + memset(&(priv->EfuseMap[EFUSE_INIT_MAP][0]), 0xff, 128); + }else{ + efuse_ReadAllMap(dev, &priv->EfuseMap[EFUSE_INIT_MAP][0]); + } + //PlatformMoveMemory(&priv->EfuseMap[EFUSE_MODIFY_MAP][0], + //&priv->EfuseMap[EFUSE_INIT_MAP][0], HWSET_MAX_SIZE_92S);//FIXLZM + memcpy(&priv->EfuseMap[EFUSE_MODIFY_MAP][0], + &priv->EfuseMap[EFUSE_INIT_MAP][0], HWSET_MAX_SIZE_92S); + +} // EFUSE_ShadowMapUpdate + +extern void +EFUSE_ForceWriteVendorId( struct net_device* dev) +{ + u8 tmpdata[8] = {0xFF, 0xFF, 0xEC, 0x10, 0xFF, 0xFF, 0xFF, 0xFF}; + + efuse_PowerSwitch(dev, TRUE); + + efuse_PgPacketWrite(dev, 1, 0xD, tmpdata); + + efuse_PowerSwitch(dev, FALSE); + +} // EFUSE_ForceWriteVendorId + +/*----------------------------------------------------------------------------- + * Function: efuse_ShadowRead1Byte + * efuse_ShadowRead2Byte + * efuse_ShadowRead4Byte + * + * Overview: Read from efuse init map by one/two/four bytes !!!!! + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 11/12/2008 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +static void +efuse_ShadowRead1Byte(struct net_device* dev, u16 Offset, u8 *Value) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + + *Value = priv->EfuseMap[EFUSE_MODIFY_MAP][Offset]; + +} // EFUSE_ShadowRead1Byte + +//---------------Read Two Bytes +static void +efuse_ShadowRead2Byte(struct net_device* dev, u16 Offset, u16 *Value) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + + *Value = priv->EfuseMap[EFUSE_MODIFY_MAP][Offset]; + *Value |= priv->EfuseMap[EFUSE_MODIFY_MAP][Offset+1]<<8; + +} // EFUSE_ShadowRead2Byte + +//---------------Read Four Bytes +static void +efuse_ShadowRead4Byte(struct net_device* dev, u16 Offset, u32 *Value) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + + *Value = priv->EfuseMap[EFUSE_MODIFY_MAP][Offset]; + *Value |= priv->EfuseMap[EFUSE_MODIFY_MAP][Offset+1]<<8; + *Value |= priv->EfuseMap[EFUSE_MODIFY_MAP][Offset+2]<<16; + *Value |= priv->EfuseMap[EFUSE_MODIFY_MAP][Offset+3]<<24; + +} // efuse_ShadowRead4Byte + + + +/*----------------------------------------------------------------------------- + * Function: efuse_ShadowWrite1Byte + * efuse_ShadowWrite2Byte + * efuse_ShadowWrite4Byte + * + * Overview: Write efuse modify map by one/two/four byte. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 11/12/2008 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +static void +efuse_ShadowWrite1Byte(struct net_device* dev, u16 Offset, u8 Value) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + + priv->EfuseMap[EFUSE_MODIFY_MAP][Offset] = Value; + +} // efuse_ShadowWrite1Byte + +//---------------Write Two Bytes +static void +efuse_ShadowWrite2Byte(struct net_device* dev, u16 Offset, u16 Value) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + + priv->EfuseMap[EFUSE_MODIFY_MAP][Offset] = Value&0x00FF; + priv->EfuseMap[EFUSE_MODIFY_MAP][Offset+1] = Value>>8; + +} // efuse_ShadowWrite1Byte + +//---------------Write Four Bytes +static void +efuse_ShadowWrite4Byte(struct net_device* dev, u16 Offset, u32 Value) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + + priv->EfuseMap[EFUSE_MODIFY_MAP][Offset] = (u8)(Value&0x000000FF); + priv->EfuseMap[EFUSE_MODIFY_MAP][Offset+1] = (u8)((Value>>8)&0x0000FF); + priv->EfuseMap[EFUSE_MODIFY_MAP][Offset+2] = (u8)((Value>>16)&0x00FF); + priv->EfuseMap[EFUSE_MODIFY_MAP][Offset+3] = (u8)((Value>>24)&0xFF); + +} // efuse_ShadowWrite1Byte + + +/* 11/16/2008 MH Read one byte from real Efuse. */ +static u8 +efuse_OneByteRead(struct net_device* dev, u16 addr,u8 *data) +{ + u8 tmpidx = 0; + u8 bResult; + + // -----------------e-fuse reg ctrl --------------------------------- + //address + write_nic_byte(dev, EFUSE_CTRL+1, (u8)(addr&0xff)); + write_nic_byte(dev, EFUSE_CTRL+2, ((u8)((addr>>8) &0x03) ) | + (read_nic_byte(dev, EFUSE_CTRL+2)&0xFC )); + + write_nic_byte(dev, EFUSE_CTRL+3, 0x72);//read cmd + + while(!(0x80 &read_nic_byte(dev, EFUSE_CTRL+3))&&(tmpidx<100)) + { + tmpidx++; + } + if(tmpidx<100) + { + *data=read_nic_byte(dev, EFUSE_CTRL); + bResult = TRUE; + } + else + { + *data = 0xff; + bResult = FALSE; + } + return bResult; +} // efuse_OneByteRead + +/* 11/16/2008 MH Write one byte to reald Efuse. */ +static u8 +efuse_OneByteWrite(struct net_device* dev, u16 addr, u8 data) +{ + u8 tmpidx = 0; + u8 bResult; + + //RT_TRACE(COMP_EFUSE, "Addr = %x Data=%x\n", addr, data); + + //return 0; + + // -----------------e-fuse reg ctrl --------------------------------- + //address + write_nic_byte(dev, EFUSE_CTRL+1, (u8)(addr&0xff)); + write_nic_byte(dev, EFUSE_CTRL+2, + read_nic_byte(dev, EFUSE_CTRL+2)|(u8)((addr>>8)&0x03) ); + + write_nic_byte(dev, EFUSE_CTRL, data);//data + write_nic_byte(dev, EFUSE_CTRL+3, 0xF2);//write cmd + + while((0x80 & read_nic_byte(dev, EFUSE_CTRL+3)) && (tmpidx<100) ){ + tmpidx++; + } + + if(tmpidx<100) + { + bResult = TRUE; + } + else + { + bResult = FALSE; + } + + return bResult; +} // efuse_OneByteWrite + + +/*----------------------------------------------------------------------------- + * Function: efuse_ReadAllMap + * + * Overview: Read All Efuse content + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 11/11/2008 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +static void +efuse_ReadAllMap(struct net_device* dev, u8 *Efuse) +{ + //u8 pg_data[8]; + //u8 offset = 0; + //u8 tmpidx; + //static u8 index = 0; + + // + // We must enable clock and LDO 2.5V otherwise, read all map will be fail!!!! + // + efuse_PowerSwitch(dev, TRUE); + ReadEFuse(dev, 0, 128, Efuse); + efuse_PowerSwitch(dev, FALSE); +#if 0 + // ==> Prevent efuse read error!!! + RT_TRACE(COMP_INIT, "efuse_ResetLoader\n"); + efuse_ResetLoader(dev); + + // Change Efuse Clock for write action to 40MHZ + write_nic_byte(dev, EFUSE_CLK, 0x03); + + ReadEFuse(dev, 0, 128, Efuse); + + // Change Efuse Clock for write action to 500K + write_nic_byte(dev, EFUSE_CLK, 0x02); +#if 0 // Error !!!!!! + for(offset = 0;offset<16;offset++) // For 8192SE + { + PlatformFillMemory((PVOID)pg_data, 8, 0xff); + efuse_PgPacketRead(pAdapter,offset,pg_data); + + PlatformMoveMemory((PVOID)&Efuse[offset*8], (PVOID)pg_data, 8); + } +#endif + + // + // Error Check and Reset Again!!!! + // + if (Efuse[0] != 0x29 || Efuse[1] != 0x81) + { + // SW autoload fail, we have to read again!!! + if (index ++ < 5) + { + RT_TRACE(COMP_INIT, "EFUSE R FAIL %d\n", index); + efuse_ReadAllMap(dev, Efuse); + // Wait a few time ???? Or need to do some setting ??? + // When we reload driver, efuse will be OK!! + } + } + else + { + index = 0; + } + + //efuse_PowerSwitch(pAdapter, FALSE); +#endif +} // efuse_ReadAllMap + + +/*----------------------------------------------------------------------------- + * Function: efuse_WriteAllMap + * + * Overview: Write All Efuse content + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 11/11/2008 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +#ifdef TO_DO_LIST +static void +efuse_WriteAllMap(struct net_device* dev,u8 *eeprom, u32 eeprom_size) +{ + unsigned char word_en = 0x00; + + unsigned char tmpdata[8]; + unsigned char offset; + + // For Efuse write action, we must enable LDO2.5V and 40MHZ clk. + efuse_PowerSwitch(dev, TRUE); + + //sdio contents + for(offset=0 ; offset< eeprom_size/PGPKT_DATA_SIZE ; offset++) + { + // 92S will only reserv 0x18-1F 8 bytes now. The 3rd efuse write area! + if (IS_HARDWARE_TYPE_8192SE(dev)) + { + // Refer to + // 0x18-1f Reserve >0x50 Reserve for tx power + if (offset == 3/* || offset > 9*/) + continue;//word_en = 0x0F; + //else if (offset == 9) // 0x4c-4f Reserve + //word_en = 0x0C; + else + word_en = 0x00; + } + //RT_TRACE(COMP_EFUSE, ("Addr=%d size=%d Word_En=%02x\n", offset, eeprom_size, word_en)); + + //memcpy(tmpdata,eeprom+(offset*PGPKT_DATA_SIZE),8); + memcpy(tmpdata, (eeprom+(offset*PGPKT_DATA_SIZE)), 8); + + //RT_PRINT_DATA(COMP_INIT, DBG_LOUD, ("EFUSE\t"), tmpdata, 8); + + efuse_PgPacketWrite(dev,offset,word_en,tmpdata); + + + } + + // For warm reboot, we must resume Efuse clock to 500K. + efuse_PowerSwitch(dev, FALSE); + +} // efuse_WriteAllMap +#endif + +/*----------------------------------------------------------------------------- + * Function: efuse_PgPacketRead + * + * Overview: Receive dedicated Efuse are content. For92s, we support 16 + * area now. It will return 8 bytes content for every area. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 11/16/2008 MHC Reorganize code Arch and assign as local API. + * + *---------------------------------------------------------------------------*/ +static u8 +efuse_PgPacketRead( struct net_device* dev, u8 offset, u8 *data) +{ + u8 ReadState = PG_STATE_HEADER; + + bool bContinual = TRUE; + bool bDataEmpty = TRUE ; + + u8 efuse_data,word_cnts=0; + u16 efuse_addr = 0; + u8 hoffset=0,hworden=0; + u8 tmpidx=0; + u8 tmpdata[8]; + + if(data==NULL) return FALSE; + if(offset>15) return FALSE; + + //FIXLZM + //PlatformFillMemory((PVOID)data, sizeof(u8)*PGPKT_DATA_SIZE, 0xff); + //PlatformFillMemory((PVOID)tmpdata, sizeof(u8)*PGPKT_DATA_SIZE, 0xff); + memset(data, 0xff, sizeof(u8)*PGPKT_DATA_SIZE); + memset(tmpdata, 0xff, sizeof(u8)*PGPKT_DATA_SIZE); + + //RT_PRINT_DATA(COMP_EFUSE, DBG_LOUD, ("efuse_PgPacketRead-1\n"), data, 8); + + //efuse_reg_ctrl(pAdapter,TRUE);//power on + while(bContinual && (efuse_addr < EFUSE_MAX_SIZE) ) + { + //------- Header Read ------------- + if(ReadState & PG_STATE_HEADER) + { + if(efuse_OneByteRead(dev, efuse_addr ,&efuse_data)&&(efuse_data!=0xFF)){ + hoffset = (efuse_data>>4) & 0x0F; + hworden = efuse_data & 0x0F; + word_cnts = efuse_CalculateWordCnts(hworden); + bDataEmpty = TRUE ; + + if(hoffset==offset){ + for(tmpidx = 0;tmpidx< word_cnts*2 ;tmpidx++){ + if(efuse_OneByteRead(dev, efuse_addr+1+tmpidx ,&efuse_data) ){ + tmpdata[tmpidx] = efuse_data; + if(efuse_data!=0xff){ + bDataEmpty = FALSE; + } + } + } + if(bDataEmpty==FALSE){ + ReadState = PG_STATE_DATA; + }else{//read next header + efuse_addr = efuse_addr + (word_cnts*2)+1; + ReadState = PG_STATE_HEADER; + } + } + else{//read next header + efuse_addr = efuse_addr + (word_cnts*2)+1; + ReadState = PG_STATE_HEADER; + } + + } + else{ + bContinual = FALSE ; + } + } + //------- Data section Read ------------- + else if(ReadState & PG_STATE_DATA) + { + efuse_WordEnableDataRead(hworden,tmpdata,data); + efuse_addr = efuse_addr + (word_cnts*2)+1; + ReadState = PG_STATE_HEADER; + } + + } + //efuse_reg_ctrl(pAdapter,FALSE);//power off + + //RT_PRINT_DATA(COMP_EFUSE, DBG_LOUD, ("efuse_PgPacketRead-2\n"), data, 8); + + if( (data[0]==0xff) &&(data[1]==0xff) && (data[2]==0xff) && (data[3]==0xff) && + (data[4]==0xff) &&(data[5]==0xff) && (data[6]==0xff) && (data[7]==0xff)) + return FALSE; + else + return TRUE; + +} // efuse_PgPacketRead + + +/*----------------------------------------------------------------------------- + * Function: efuse_PgPacketWrite + * + * Overview: Send A G package for different section in real efuse area. + * For 92S, One PG package contain 8 bytes content and 4 word + * unit. PG header = 0x[bit7-4=offset][bit3-0word enable] + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 11/16/2008 MHC Reorganize code Arch and assign as local API. + * + *---------------------------------------------------------------------------*/ +static u8 efuse_PgPacketWrite(struct net_device* dev, u8 offset, u8 word_en,u8 *data) +{ + u8 WriteState = PG_STATE_HEADER; + + bool bContinual = TRUE,bDataEmpty=TRUE, bResult = TRUE; + u16 efuse_addr = 0; + u8 efuse_data; + + u8 pg_header = 0; + + //u16 tmp_addr=0; + u8 tmp_word_cnts=0,target_word_cnts=0; + u8 tmp_header,match_word_en,tmp_word_en; + + //u8 efuse_clk_ori,efuse_clk_new; + + PGPKT_STRUCT target_pkt; + PGPKT_STRUCT tmp_pkt; + + u8 originaldata[sizeof(u8)*8]; + u8 tmpindex = 0,badworden = 0x0F; + + static u32 repeat_times = 0; + + if( efuse_GetCurrentSize(dev) >= EFUSE_MAX_SIZE) + { + printk("efuse_PgPacketWrite error \n"); + return FALSE; + } + + // Init the 8 bytes content as 0xff + target_pkt.offset = offset; + target_pkt.word_en= word_en; + + //PlatformFillMemory((PVOID)target_pkt.data, sizeof(u8)*8, 0xFF); + memset(target_pkt.data,0xFF,sizeof(u8)*8); + + efuse_WordEnableDataRead(word_en,data,target_pkt.data); + target_word_cnts = efuse_CalculateWordCnts(target_pkt.word_en); + + //efuse_reg_ctrl(pAdapter,TRUE);//power on + printk("EFUSE Power ON\n"); + + while( bContinual && (efuse_addr < EFUSE_MAX_SIZE) ) + { + + if(WriteState==PG_STATE_HEADER) + { + bDataEmpty=TRUE; + badworden = 0x0F; + //************ so ******************* + printk("EFUSE PG_STATE_HEADER\n"); + if ( efuse_OneByteRead(dev, efuse_addr ,&efuse_data) && + (efuse_data!=0xFF)) + { + tmp_header = efuse_data; + + tmp_pkt.offset = (tmp_header>>4) & 0x0F; + tmp_pkt.word_en = tmp_header & 0x0F; + tmp_word_cnts = efuse_CalculateWordCnts(tmp_pkt.word_en); + + //************ so-1 ******************* + if(tmp_pkt.offset != target_pkt.offset) + { + efuse_addr = efuse_addr + (tmp_word_cnts*2) +1; //Next pg_packet + #if (EFUSE_ERROE_HANDLE == 1) + WriteState = PG_STATE_HEADER; + #endif + } + else + { + //************ so-2 ******************* + for(tmpindex=0 ; tmpindex<(tmp_word_cnts*2) ; tmpindex++) + { + if(efuse_OneByteRead(dev, (efuse_addr+1+tmpindex) ,&efuse_data)&&(efuse_data != 0xFF)){ + bDataEmpty = FALSE; + } + } + //************ so-2-1 ******************* + if(bDataEmpty == FALSE) + { + efuse_addr = efuse_addr + (tmp_word_cnts*2) +1; //Next pg_packet + #if (EFUSE_ERROE_HANDLE == 1) + WriteState=PG_STATE_HEADER; + #endif + } + else + {//************ so-2-2 ******************* + match_word_en = 0x0F; + if( !( (target_pkt.word_en&BIT0)|(tmp_pkt.word_en&BIT0) )) + { + match_word_en &= (~BIT0); + } + if( !( (target_pkt.word_en&BIT1)|(tmp_pkt.word_en&BIT1) )) + { + match_word_en &= (~BIT1); + } + if( !( (target_pkt.word_en&BIT2)|(tmp_pkt.word_en&BIT2) )) + { + match_word_en &= (~BIT2); + } + if( !( (target_pkt.word_en&BIT3)|(tmp_pkt.word_en&BIT3) )) + { + match_word_en &= (~BIT3); + } + + //************ so-2-2-A ******************* + if((match_word_en&0x0F)!=0x0F) + { + badworden = efuse_WordEnableDataWrite(dev,efuse_addr+1, tmp_pkt.word_en ,target_pkt.data); + + //************ so-2-2-A-1 ******************* + //############################ + if(0x0F != (badworden&0x0F)) + { + u8 reorg_offset = offset; + u8 reorg_worden=badworden; + efuse_PgPacketWrite(dev,reorg_offset,reorg_worden,originaldata); + } + //############################ + + tmp_word_en = 0x0F; + if( (target_pkt.word_en&BIT0)^(match_word_en&BIT0) ) + { + tmp_word_en &= (~BIT0); + } + if( (target_pkt.word_en&BIT1)^(match_word_en&BIT1) ) + { + tmp_word_en &= (~BIT1); + } + if( (target_pkt.word_en&BIT2)^(match_word_en&BIT2) ) + { + tmp_word_en &= (~BIT2); + } + if( (target_pkt.word_en&BIT3)^(match_word_en&BIT3) ) + { + tmp_word_en &=(~BIT3); + } + + //************ so-2-2-A-2 ******************* + if((tmp_word_en&0x0F)!=0x0F){ + //reorganize other pg packet + //efuse_addr = efuse_addr + (2*tmp_word_cnts) +1;//next pg packet addr + efuse_addr = efuse_GetCurrentSize(dev); + //=========================== + target_pkt.offset = offset; + target_pkt.word_en= tmp_word_en; + //=========================== + }else{ + bContinual = FALSE; + } + #if (EFUSE_ERROE_HANDLE == 1) + WriteState=PG_STATE_HEADER; + repeat_times++; + if(repeat_times>EFUSE_REPEAT_THRESHOLD_){ + bContinual = FALSE; + bResult = FALSE; + } + #endif + } + else{//************ so-2-2-B ******************* + //reorganize other pg packet + efuse_addr = efuse_addr + (2*tmp_word_cnts) +1;//next pg packet addr + //=========================== + target_pkt.offset = offset; + target_pkt.word_en= target_pkt.word_en; + //=========================== + #if (EFUSE_ERROE_HANDLE == 1) + WriteState=PG_STATE_HEADER; + #endif + } + } + } + printk("EFUSE PG_STATE_HEADER-1\n"); + } + else //************ s1: header == oxff ******************* + { + pg_header = ((target_pkt.offset << 4)&0xf0) |target_pkt.word_en; + + efuse_OneByteWrite(dev,efuse_addr, pg_header); + efuse_OneByteRead(dev,efuse_addr, &tmp_header); + + if(tmp_header == pg_header) + { //************ s1-1******************* + WriteState = PG_STATE_DATA; + } + #if (EFUSE_ERROE_HANDLE == 1) + else if(tmp_header == 0xFF){//************ s1-3: if Write or read func doesn't work ******************* + //efuse_addr doesn't change + WriteState = PG_STATE_HEADER; + repeat_times++; + if(repeat_times>EFUSE_REPEAT_THRESHOLD_){ + bContinual = FALSE; + bResult = FALSE; + } + } + #endif + else + {//************ s1-2 : fixed the header procedure ******************* + tmp_pkt.offset = (tmp_header>>4) & 0x0F; + tmp_pkt.word_en= tmp_header & 0x0F; + tmp_word_cnts = efuse_CalculateWordCnts(tmp_pkt.word_en); + + //************ s1-2-A :cover the exist data ******************* + memset(originaldata,0xff,sizeof(u8)*8); + //PlatformFillMemory((PVOID)originaldata, sizeof(u8)*8, 0xff); + + if(efuse_PgPacketRead( dev, tmp_pkt.offset,originaldata)) + { //check if data exist + //efuse_reg_ctrl(pAdapter,TRUE);//power on + badworden = efuse_WordEnableDataWrite(dev,efuse_addr+1,tmp_pkt.word_en,originaldata); + //############################ + if(0x0F != (badworden&0x0F)) + { + u8 reorg_offset = tmp_pkt.offset; + u8 reorg_worden=badworden; + efuse_PgPacketWrite(dev,reorg_offset,reorg_worden,originaldata); + efuse_addr = efuse_GetCurrentSize(dev); + } + //############################ + else{ + efuse_addr = efuse_addr + (tmp_word_cnts*2) +1; //Next pg_packet + } + } + //************ s1-2-B: wrong address******************* + else + { + efuse_addr = efuse_addr + (tmp_word_cnts*2) +1; //Next pg_packet + } + + #if (EFUSE_ERROE_HANDLE == 1) + WriteState=PG_STATE_HEADER; + repeat_times++; + if(repeat_times>EFUSE_REPEAT_THRESHOLD_){ + bContinual = FALSE; + bResult = FALSE; + } + #endif + + printk("EFUSE PG_STATE_HEADER-2\n"); + } + + } + + } + //write data state + else if(WriteState==PG_STATE_DATA) + { //************ s1-1 ******************* + printk("EFUSE PG_STATE_DATA\n"); + badworden = 0x0f; + badworden = efuse_WordEnableDataWrite(dev,efuse_addr+1,target_pkt.word_en,target_pkt.data); + if((badworden&0x0F)==0x0F) + { //************ s1-1-A ******************* + bContinual = FALSE; + } + else + {//reorganize other pg packet //************ s1-1-B ******************* + efuse_addr = efuse_addr + (2*target_word_cnts) +1;//next pg packet addr + + //=========================== + target_pkt.offset = offset; + target_pkt.word_en= badworden; + target_word_cnts = efuse_CalculateWordCnts(target_pkt.word_en); + //=========================== + #if (EFUSE_ERROE_HANDLE == 1) + WriteState=PG_STATE_HEADER; + repeat_times++; + if(repeat_times>EFUSE_REPEAT_THRESHOLD_){ + bContinual = FALSE; + bResult = FALSE; + } + #endif + printk("EFUSE PG_STATE_HEADER-3\n"); + } + } + } + + //efuse_reg_ctrl(pAdapter,FALSE);//power off + + return TRUE; +} // efuse_PgPacketWrite + + +/*----------------------------------------------------------------------------- + * Function: efuse_WordEnableDataRead + * + * Overview: Read allowed word in current efuse section data. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 11/16/2008 MHC Create Version 0. + * 11/21/2008 MHC Fix Write bug when we only enable late word. + * + *---------------------------------------------------------------------------*/ +static void +efuse_WordEnableDataRead( u8 word_en,u8 *sourdata,u8 *targetdata) +{ + //u8 tmpindex = 0; + + //DbgPrint("efuse_WordEnableDataRead word_en = %x\n", word_en); + + //RT_PRINT_DATA(COMP_EFUSE, DBG_LOUD, ("sourdata\n"), sourdata, 8); + //RT_PRINT_DATA(COMP_EFUSE, DBG_LOUD, ("targetdata\n"), targetdata, 8); + + if (!(word_en&BIT0)) + { + targetdata[0] = sourdata[0];//sourdata[tmpindex++]; + targetdata[1] = sourdata[1];//sourdata[tmpindex++]; + } + if (!(word_en&BIT1)) + { + targetdata[2] = sourdata[2];//sourdata[tmpindex++]; + targetdata[3] = sourdata[3];//sourdata[tmpindex++]; + } + if (!(word_en&BIT2)) + { + targetdata[4] = sourdata[4];//sourdata[tmpindex++]; + targetdata[5] = sourdata[5];//sourdata[tmpindex++]; + } + if (!(word_en&BIT3)) + { + targetdata[6] = sourdata[6];//sourdata[tmpindex++]; + targetdata[7] = sourdata[7];//sourdata[tmpindex++]; + } +} // efuse_WordEnableDataRead + + +/*----------------------------------------------------------------------------- + * Function: efuse_WordEnableDataWrite + * + * Overview: Write necessary word unit into current efuse section! + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 11/16/2008 MHC Reorganize Efuse operate flow!!. + * + *---------------------------------------------------------------------------*/ +static u8 +efuse_WordEnableDataWrite( struct net_device* dev, u16 efuse_addr, u8 word_en, u8 *data) +{ + u16 tmpaddr = 0; + u16 start_addr = efuse_addr; + u8 badworden = 0x0F; + //u8 NextState; + u8 tmpdata[8]; + + memset(tmpdata,0xff,PGPKT_DATA_SIZE); + //PlatformFillMemory((PVOID)tmpdata, PGPKT_DATA_SIZE, 0xff); + + //RT_TRACE(COMP_EFUSE, "word_en = %x efuse_addr=%x\n", word_en, efuse_addr); + + //RT_PRINT_DATA(COMP_EFUSE, DBG_LOUD, ("U-EFUSE\n"), data, 8); + + if(!(word_en&BIT0)) + { + tmpaddr = start_addr; + efuse_OneByteWrite(dev,start_addr++, data[0]); + efuse_OneByteWrite(dev,start_addr++, data[1]); + + efuse_OneByteRead(dev,tmpaddr, &tmpdata[0]); + efuse_OneByteRead(dev,tmpaddr+1, &tmpdata[1]); + if((data[0]!=tmpdata[0])||(data[1]!=tmpdata[1])){ + badworden &= (~BIT0); + } + } + if(!(word_en&BIT1)) + { + tmpaddr = start_addr; + efuse_OneByteWrite(dev,start_addr++, data[2]); + efuse_OneByteWrite(dev,start_addr++, data[3]); + + efuse_OneByteRead(dev,tmpaddr , &tmpdata[2]); + efuse_OneByteRead(dev,tmpaddr+1, &tmpdata[3]); + if((data[2]!=tmpdata[2])||(data[3]!=tmpdata[3])){ + badworden &=( ~BIT1); + } + } + if(!(word_en&BIT2)) + { + tmpaddr = start_addr; + efuse_OneByteWrite(dev,start_addr++, data[4]); + efuse_OneByteWrite(dev,start_addr++, data[5]); + + efuse_OneByteRead(dev,tmpaddr, &tmpdata[4]); + efuse_OneByteRead(dev,tmpaddr+1, &tmpdata[5]); + if((data[4]!=tmpdata[4])||(data[5]!=tmpdata[5])){ + badworden &=( ~BIT2); + } + } + if(!(word_en&BIT3)) + { + tmpaddr = start_addr; + efuse_OneByteWrite(dev,start_addr++, data[6]); + efuse_OneByteWrite(dev,start_addr++, data[7]); + + efuse_OneByteRead(dev,tmpaddr, &tmpdata[6]); + efuse_OneByteRead(dev,tmpaddr+1, &tmpdata[7]); + if((data[6]!=tmpdata[6])||(data[7]!=tmpdata[7])){ + badworden &=( ~BIT3); + } + } + return badworden; +} // efuse_WordEnableDataWrite + + +/*----------------------------------------------------------------------------- + * Function: efuse_PowerSwitch + * + * Overview: When we want to enable write operation, we should change to + * pwr on state. When we stop write, we should switch to 500k mode + * and disable LDO 2.5V. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 11/17/2008 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +static void +efuse_PowerSwitch(struct net_device* dev, u8 PwrState) +{ + u8 tempval; + if (PwrState == TRUE) + { + // Enable LDO 2.5V for write action + tempval = read_nic_byte(dev, EFUSE_TEST+3); + write_nic_byte(dev, EFUSE_TEST+3, (tempval | 0x80)); + + // Change Efuse Clock for write action to 40MHZ + write_nic_byte(dev, EFUSE_CLK, 0x03); + } + else + { + // Enable LDO 2.5V for write action + tempval = read_nic_byte(dev, EFUSE_TEST+3); + write_nic_byte(dev, EFUSE_TEST+3, (tempval & 0x7F)); + + // Change Efuse Clock for write action to 500K + write_nic_byte(dev, EFUSE_CLK, 0x02); + } + +} /* efuse_PowerSwitch */ + + +/*----------------------------------------------------------------------------- + * Function: efuse_GetCurrentSize + * + * Overview: Get current efuse size!!! + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 11/16/2008 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +static u16 +efuse_GetCurrentSize(struct net_device* dev) +{ + bool bContinual = TRUE; + + u16 efuse_addr = 0; + u8 hoffset=0,hworden=0; + u8 efuse_data,word_cnts=0; + + //efuse_reg_ctrl(pAdapter,TRUE);//power on + + while ( bContinual && + efuse_OneByteRead(dev, efuse_addr ,&efuse_data) && + (efuse_addr < EFUSE_MAX_SIZE) ) + { + if(efuse_data!=0xFF) + { + hoffset = (efuse_data>>4) & 0x0F; + hworden = efuse_data & 0x0F; + word_cnts = efuse_CalculateWordCnts(hworden); + //read next header + efuse_addr = efuse_addr + (word_cnts*2)+1; + } + else + { + bContinual = FALSE ; + } + } + + //efuse_reg_ctrl(pAdapter,FALSE);//power off + + return efuse_addr; + +} // efuse_GetCurrentSize} + + +/* 11/16/2008 MH Add description. Get current efuse area enabled word!!. */ +static u8 +efuse_CalculateWordCnts(u8 word_en) +{ + u8 word_cnts = 0; + if(!(word_en & BIT0)) word_cnts++; // 0 : write enable + if(!(word_en & BIT1)) word_cnts++; + if(!(word_en & BIT2)) word_cnts++; + if(!(word_en & BIT3)) word_cnts++; + return word_cnts; +} // efuse_CalculateWordCnts + + +/*----------------------------------------------------------------------------- + * Function: efuse_ResetLoader + * + * Overview: When read Efuse Fail we must reset loader!!!! + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 11/22/2008 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +#if 0 +static void efuse_ResetLoader(struct net_device* dev) +{ + u16 tmpU2b; + + // + // 2008/11/22 MH Sometimes, we may read efuse fail, for preventing the condition + // We have to reset loader. + // + tmpU2b = read_nic_word(dev, SYS_FUNC_EN); + write_nic_word(dev, SYS_FUNC_EN, (tmpU2b&~(BIT12))); + //PlatformStallExecution(10000); // How long should we delay!!! + mdelay(10); + write_nic_word(dev, SYS_FUNC_EN, (tmpU2b|BIT12)); + //PlatformStallExecution(10000); // How long should we delay!!! + mdelay(10); + +} // efuse_ResetLoader +#endif + +/*----------------------------------------------------------------------------- + * Function: EFUSE_ProgramMap + * + * Overview: Read EFUSE map file and execute PG. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 11/10/2008 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ + #ifdef TO_DO_LIST +extern bool // 0=Shadow 1=Real Efuse +EFUSE_ProgramMap(struct net_device* dev, char* pFileName,u8 TableType) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + s4Byte nLinesRead, ithLine; + RT_STATUS rtStatus = RT_STATUS_SUCCESS; + char* szLine; + u32 u4bRegValue, u4RegMask; + u32 u4bMove; + u16 index = 0; + u16 i; + u8 eeprom[HWSET_MAX_SIZE_92S]; + + rtStatus = PlatformReadFile( + dev, + pFileName, + (u8*)(priv->BufOfLines), + MAX_LINES_HWCONFIG_TXT, + MAX_BYTES_LINE_HWCONFIG_TXT, + &nLinesRead + ); + + if(rtStatus == RT_STATUS_SUCCESS) + { + memcp(pHalData->BufOfLines3, pHalData->BufOfLines, + nLinesRead*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesRead3 = nLinesRead; + } + + if(rtStatus == RT_STATUS_SUCCESS) + { + printk("szEepromFile(): read %s ok\n", pFileName); + for(ithLine = 0; ithLine < nLinesRead; ithLine++) + { + szLine = pHalData->BufOfLines[ithLine]; + printk("Line-%d String =%s\n", ithLine, szLine); + + if(!IsCommentString(szLine)) + { + // EEPROM map one line has 8 words content. + for (i = 0; i < 8; i++) + { + u32 j; + + //GetHexValueFromString(szLine, &u4bRegValue, &u4bMove); + efuse_ParsingMap(szLine, &u4bRegValue, &u4bMove); + + // Get next hex value as EEPROM value. + szLine += u4bMove; + //WriteEEprom(dev, (u16)(ithLine*8+i), (u16)u4bRegValue); + eeprom[index++] = (u8)(u4bRegValue&0xff); + eeprom[index++] = (u8)((u4bRegValue>>8)&0xff); + + printk("Addr-%d = %x\n", (ithLine*8+i), u4bRegValue); + } + } + + } + + } + else + { + printk("szEepromFile(): Fail read%s\n", pFileName); + return RT_STATUS_FAILURE; + } + + + //RT_PRINT_DATA(COMP_EFUSE, DBG_LOUD, ("EFUSE "), eeprom, HWSET_MAX_SIZE_92S); + + // Use map file to update real Efuse or shadow modify table. + if (TableType == 1) + { + efuse_WriteAllMap(dev, eeprom, HWSET_MAX_SIZE_92S); + } + else + { + // Modify shadow table. + for (i = 0; i < HWSET_MAX_SIZE_92S; i++) + EFUSE_ShadowWrite(dev, 1, i, (u32)eeprom[i]); + } + + return rtStatus; +} /* EFUSE_ProgramMap */ + +#endif + +// +// Description: +// Return TRUE if chTmp is represent for hex digit and +// FALSE otherwise. +// +// +bool IsHexDigit( char chTmp) +{ + if( (chTmp >= '0' && chTmp <= '9') || + (chTmp >= 'a' && chTmp <= 'f') || + (chTmp >= 'A' && chTmp <= 'F') ) + { + return TRUE; + } + else + { + return FALSE; + } +} + +// +// Description: +// Translate a character to hex digit. +// +u32 MapCharToHexDigit(char chTmp) +{ + if(chTmp >= '0' && chTmp <= '9') + return (chTmp - '0'); + else if(chTmp >= 'a' && chTmp <= 'f') + return (10 + (chTmp - 'a')); + else if(chTmp >= 'A' && chTmp <= 'F') + return (10 + (chTmp - 'A')); + else + return 0; +} + +/*----------------------------------------------------------------------------- + * Function: efuse_ParsingMap + * + * Overview: + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 11/08/2008 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +#ifdef TO_DO_LIST +static bool +efuse_ParsingMap(char* szStr,u32* pu4bVal,u32* pu4bMove) +{ + char* szScan = szStr; + + // Check input parameter. + if(szStr == NULL || pu4bVal == NULL || pu4bMove == NULL) + { + //RT_TRACE(COMP_EFUSE, + //"eeprom_ParsingMap(): Invalid IN args! szStr: %p, pu4bVal: %p, pu4bMove: %p\n", + //szStr, pu4bVal, pu4bMove); + return FALSE; + } + + // Initialize output. + *pu4bMove = 0; + *pu4bVal = 0; + + // Skip leading space. + while( *szScan != '\0' && + (*szScan == ' ' || *szScan == '\t') ) + { + szScan++; + (*pu4bMove)++; + } + + // Check if szScan is now pointer to a character for hex digit, + // if not, it means this is not a valid hex number. + if(!IsHexDigit(*szScan)) + { + return FALSE; + } + + // Parse each digit. + do + { + (*pu4bVal) <<= 4; + *pu4bVal += MapCharToHexDigit(*szScan); + + szScan++; + (*pu4bMove)++; + } while(IsHexDigit(*szScan)); + + return TRUE; + +} /* efuse_ParsingMap */ +#endif + +// +// Useless Section Code Now!!!!!! +// +// Porting from 8712 SDIO +int efuse_one_byte_rw(struct net_device* dev, u8 bRead, u16 addr, u8 *data) +{ + u32 bResult; + //u8 efuse_ctlreg,tmpidx = 0; + u8 tmpidx = 0; + u8 tmpv8=0; + + // -----------------e-fuse reg ctrl --------------------------------- + + write_nic_byte(dev, EFUSE_CTRL+1, (u8)(addr&0xff)); //address + tmpv8 = ((u8)((addr>>8) &0x03) ) | (read_nic_byte(dev, EFUSE_CTRL+2)&0xFC ); + write_nic_byte(dev, EFUSE_CTRL+2, tmpv8); + + if(TRUE==bRead){ + + write_nic_byte(dev, EFUSE_CTRL+3, 0x72);//read cmd + + while(!(0x80 & read_nic_byte(dev, EFUSE_CTRL+3)) && (tmpidx<100) ){ + tmpidx++; + } + if(tmpidx<100){ + *data=read_nic_byte(dev, EFUSE_CTRL); + bResult = TRUE; + } + else + { + *data = 0; + bResult = FALSE; + } + + } + else{ + //return 0; + write_nic_byte(dev, EFUSE_CTRL, *data);//data + + write_nic_byte(dev, EFUSE_CTRL+3, 0xF2);//write cmd + + while((0x80 & read_nic_byte(dev, EFUSE_CTRL+3)) && (tmpidx<100) ){ + tmpidx++; + } + if(tmpidx<100) + { + *data=read_nic_byte(dev, EFUSE_CTRL); + bResult = TRUE; + } + else + { + *data = 0; + bResult = FALSE; + } + + } + return bResult; +} +//------------------------------------------------------------------------------ +void efuse_access(struct net_device* dev, u8 bRead,u16 start_addr, u8 cnts, u8 *data) +{ + u8 efuse_clk_ori,efuse_clk_new;//,tmp8; + u32 i = 0; + + if(start_addr>0x200) return; + //RT_TRACE(_module_rtl871x_mp_ioctl_c_,_drv_err_, + // ("\n ===> efuse_access [start_addr=0x%x cnts:%d dataarray:0x%08x Query Efuse].\n",start_addr,cnts,data)); + // -----------------SYS_FUNC_EN Digital Core Vdd enable --------------------------------- + efuse_clk_ori = read_nic_byte(dev,SYS_FUNC_EN+1); + efuse_clk_new = efuse_clk_ori|0x20; + + if(efuse_clk_new!= efuse_clk_ori){ + //RT_TRACE(_module_rtl871x_mp_ioctl_c_,_drv_err_,("====write 0x10250003=====\n")); + write_nic_byte(dev, SYS_FUNC_EN+1, efuse_clk_new); + } +#ifdef _POWERON_DELAY_ + mdelay(10); +#endif + // -----------------e-fuse pwr & clk reg ctrl --------------------------------- + write_nic_byte(dev, EFUSE_TEST+3, (read_nic_byte(dev, EFUSE_TEST+3)|0x80)); + write_nic_byte(dev, EFUSE_CLK_CTRL, (read_nic_byte(dev, EFUSE_CLK_CTRL)|0x03)); + +#ifdef _PRE_EXECUTE_READ_CMD_ + { + unsigned char tmpdata; + efuse_OneByteRead(dev, 0,&tmpdata); + } +#endif + + //-----------------e-fuse one byte read / write ------------------------------ + for(i=0;i<cnts;i++){ + efuse_one_byte_rw(dev,bRead, start_addr+i , data+i); + ////RT_TRACE(_module_rtl871x_mp_ioctl_c_,_drv_err_,("==>efuse_access addr:0x%02x value:0x%02x\n",data+i,*(data+i))); + } + // -----------------e-fuse pwr & clk reg ctrl --------------------------------- + write_nic_byte(dev, EFUSE_TEST+3, read_nic_byte(dev, EFUSE_TEST+3)&0x7f); + write_nic_byte(dev, EFUSE_CLK_CTRL, read_nic_byte(dev, EFUSE_CLK_CTRL)&0xfd); + + // -----------------SYS_FUNC_EN Digital Core Vdd disable --------------------------------- + if(efuse_clk_new != efuse_clk_ori) write_nic_byte(dev, 0x10250003, efuse_clk_ori); + +} +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ + +#ifdef TO_DO_LIST +static void efuse_reg_ctrl(struct net_device* dev, u8 bPowerOn) +{ + if(TRUE==bPowerOn){ + // -----------------SYS_FUNC_EN Digital Core Vdd enable --------------------------------- + write_nic_byte(dev, SYS_FUNC_EN+1, read_nic_byte(dev,SYS_FUNC_EN+1)|0x20); +#ifdef _POWERON_DELAY_ + mdelay(10); +#endif + // -----------------e-fuse pwr & clk reg ctrl --------------------------------- + write_nic_byte(dev, EFUSE_TEST+4, (read_nic_byte(dev, EFUSE_TEST+4)|0x80)); + write_nic_byte(dev, EFUSE_CLK_CTRL, (read_nic_byte(dev, EFUSE_CLK_CTRL)|0x03)); +#ifdef _PRE_EXECUTE_READ_CMD_ + { + unsigned char tmpdata; + efuse_OneByteRead(dev, 0,&tmpdata); + } + +#endif + } + else{ + // -----------------e-fuse pwr & clk reg ctrl --------------------------------- + write_nic_byte(dev, EFUSE_TEST+4, read_nic_byte(dev, EFUSE_TEST+4)&0x7f); + write_nic_byte(dev, EFUSE_CLK_CTRL, read_nic_byte(dev, EFUSE_CLK_CTRL)&0xfd); + // -----------------SYS_FUNC_EN Digital Core Vdd disable --------------------------------- + + //write_nic_byte(pAdapter, SYS_FUNC_EN+1, read_nic_byte(pAdapter,SYS_FUNC_EN+1)&0xDF); + } + + +} +#endif +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +void efuse_read_data(struct net_device* dev,u8 efuse_read_item,u8 *data,u32 data_size) +{ + u8 offset, word_start,byte_start,byte_cnts; + u8 efusedata[EFUSE_MAC_LEN]; + u8 *tmpdata = NULL; + + u8 pg_pkt_cnts ; + + u8 tmpidx; + u8 pg_data[8]; + //u8 temp_value[8] = {0xff}; + + if(efuse_read_item> (sizeof(RTL8712_SDIO_EFUSE_TABLE)/sizeof(EFUSE_MAP))){ + //error msg + return ; + } + + offset = RTL8712_SDIO_EFUSE_TABLE[efuse_read_item].offset ; + word_start = RTL8712_SDIO_EFUSE_TABLE[efuse_read_item].word_start; + byte_start = RTL8712_SDIO_EFUSE_TABLE[efuse_read_item].byte_start; + byte_cnts = RTL8712_SDIO_EFUSE_TABLE[efuse_read_item].byte_cnts; + + if(data_size!=byte_cnts){ + //error msg + return; + } + + pg_pkt_cnts = (byte_cnts /PGPKT_DATA_SIZE) +1; + + if(pg_pkt_cnts > 1){ + //tmpdata = _malloc(pg_pkt_cnts*PGPKT_DATA_SIZE); + tmpdata = efusedata; + + if(tmpdata!=NULL) + { + memset(tmpdata,0xff,pg_pkt_cnts*PGPKT_DATA_SIZE); + //PlatformFillMemory((PVOID)pg_data, pg_pkt_cnts*PGPKT_DATA_SIZE, 0xff); + + for(tmpidx=0;tmpidx<pg_pkt_cnts;tmpidx++) + { + memset(pg_data,0xff,PGPKT_DATA_SIZE); + //PlatformFillMemory((PVOID)pg_data, PGPKT_DATA_SIZE, 0xff); + if(TRUE== efuse_PgPacketRead(dev,offset+tmpidx,pg_data)) + { + memcpy(tmpdata+(PGPKT_DATA_SIZE*tmpidx),pg_data,PGPKT_DATA_SIZE); + //PlatformMoveMemory((PVOID)(tmpdata+(PGPKT_DATA_SIZE*tmpidx)), (PVOID)pg_data, PGPKT_DATA_SIZE); + } + } + memcpy(data,(tmpdata+ (2*word_start)+byte_start ),data_size); + //PlatformMoveMemory((PVOID)data, (PVOID)(tmpdata+ (2*word_start)+byte_start ), data_size); + //_mfree(tmpdata, pg_pkt_cnts*PGPKT_DATA_SIZE); + } + } + else + { + memset(pg_data,0xff,PGPKT_DATA_SIZE); + //PlatformFillMemory((PVOID)pg_data, PGPKT_DATA_SIZE, 0xff); + if(TRUE==efuse_PgPacketRead(dev,offset,pg_data)){ + memcpy(data,pg_data+ (2*word_start)+byte_start ,data_size); + //PlatformMoveMemory((PVOID)data, (PVOID)(pg_data+ (2*word_start)+byte_start), data_size); + } + } + +} +//------------------------------------------------------------------------------ +//per interface doesn't alike +void efuse_write_data(struct net_device* dev,u8 efuse_write_item,u8 *data,u32 data_size,u32 bWordUnit) +{ + u8 offset, word_start,byte_start,byte_cnts; + u8 word_en = 0x0f,word_cnts; + u8 pg_pkt_cnts ; + + u8 tmpidx,tmpbitmask; + u8 pg_data[8],tmpbytes=0; + + if(efuse_write_item> (sizeof(RTL8712_SDIO_EFUSE_TABLE)/sizeof(EFUSE_MAP))){ + //error msg + return ; + } + + offset = RTL8712_SDIO_EFUSE_TABLE[efuse_write_item].offset ; + word_start = RTL8712_SDIO_EFUSE_TABLE[efuse_write_item].word_start; + byte_start = RTL8712_SDIO_EFUSE_TABLE[efuse_write_item].byte_start; + byte_cnts = RTL8712_SDIO_EFUSE_TABLE[efuse_write_item].byte_cnts; + + if(data_size > byte_cnts){ + //error msg + return; + } + pg_pkt_cnts = (byte_cnts /PGPKT_DATA_SIZE) +1; + word_cnts = byte_cnts /2 ; + + if(byte_cnts %2){ + word_cnts+=1; + } + if((byte_start==1)||((byte_cnts%2)==1)){//situation A + + if((efuse_write_item==EFUSE_F0CIS)||(efuse_write_item==EFUSE_F1CIS)){ + memset(pg_data,0xff,PGPKT_DATA_SIZE); + //PlatformFillMemory((PVOID)pg_data, PGPKT_DATA_SIZE, 0xff); + efuse_PgPacketRead(dev,offset,pg_data); + + if(efuse_write_item==EFUSE_F0CIS){ + word_en = 0x07; + memcpy(pg_data+word_start*2+byte_start,data,sizeof(u8)*2); + //PlatformMoveMemory((PVOID)(pg_data+word_start*2+byte_start), (PVOID)data, sizeof(u8)*2); + efuse_PgPacketWrite(dev,offset,word_en,pg_data+(word_start*2)); + + word_en = 0x00; + efuse_PgPacketWrite(dev,(offset+1),word_en,data+2); + + word_en = 0x00; + efuse_PgPacketRead(dev,offset+2,pg_data); + memcpy(pg_data,data+2+8,sizeof(u8)*7); + //PlatformMoveMemory((PVOID)(pg_data), (PVOID)(data+2+8), sizeof(u8)*7); + + efuse_PgPacketWrite(dev,(offset+2),word_en,pg_data); + } + else if(efuse_write_item==EFUSE_F1CIS){ + word_en = 0x07; + efuse_PgPacketRead(dev,offset,pg_data); + pg_data[7] = data[0]; + efuse_PgPacketWrite(dev,offset,word_en,pg_data+(word_start*2)); + + word_en = 0x00; + for(tmpidx = 0 ;tmpidx<(word_cnts/4);tmpidx++){ + efuse_PgPacketWrite(dev,(offset+1+tmpidx),word_en,data+1+(tmpidx*PGPKT_DATA_SIZE)); + } + } + + } + else{ + memset(pg_data,0xff,PGPKT_DATA_SIZE); + //PlatformFillMemory((PVOID)pg_data, PGPKT_DATA_SIZE, 0xff); + if((efuse_write_item==EFUSE_SDIO_SETTING)||(efuse_write_item==EFUSE_CCCR)){ + word_en = 0x0e ; + tmpbytes = 2; + } + else if(efuse_write_item == EFUSE_SDIO_MODE){ + word_en = 0x0d ; + tmpbytes = 2; + } + else if(efuse_write_item == EFUSE_OCR){ + word_en = 0x09 ; + tmpbytes = 4; + } + else if((efuse_write_item == EFUSE_EEPROM_VER)||(efuse_write_item==EFUSE_CHAN_PLAN)){ + word_en = 0x07 ; + tmpbytes = 2; + } + if(bWordUnit==TRUE){ + memcpy(pg_data+word_start*2 ,data,sizeof(u8)*tmpbytes); + //PlatformMoveMemory((PVOID)(pg_data+word_start*2), (PVOID)(data), sizeof(u8)*tmpbytes); + } + else{ + efuse_PgPacketRead(dev,offset,pg_data); + memcpy(pg_data+(2*word_start)+byte_start,data,sizeof(u8)*byte_cnts); + //PlatformMoveMemory((PVOID)(pg_data+(2*word_start)+byte_start), (PVOID)(data), sizeof(u8)*byte_cnts); + } + + efuse_PgPacketWrite(dev,offset,word_en,pg_data+(word_start*2)); + + } + + } + //======================================================================== + else if(pg_pkt_cnts>1){//situation B + if(word_start==0){ + word_en = 0x00; + for(tmpidx = 0 ;tmpidx<(word_cnts/4);tmpidx++) + { + efuse_PgPacketWrite(dev,(offset+tmpidx),word_en,data+(tmpidx*PGPKT_DATA_SIZE)); + } + word_en = 0x0f; + for(tmpidx= 0; tmpidx<(word_cnts%4) ; tmpidx++) + { + tmpbitmask =tmpidx; + word_en &= (~(EFUSE_BIT(tmpbitmask))); + //BIT0 + } + efuse_PgPacketWrite(dev,offset+(word_cnts/4),word_en,data+((word_cnts/4)*PGPKT_DATA_SIZE)); + }else + { + + } + } + //======================================================================== + else{//situation C + word_en = 0x0f; + for(tmpidx= 0; tmpidx<word_cnts ; tmpidx++) + { + tmpbitmask = word_start + tmpidx ; + word_en &= (~(EFUSE_BIT(tmpbitmask))); + } + efuse_PgPacketWrite(dev,offset,word_en,data); + } + +} +//------------------------------------------------------------------------------ + +void efuset_test_func_read(struct net_device* dev) +{ + u8 chipid[2]; + u8 ocr[3]; + u8 macaddr[6]; + u8 txpowertable[28]; + + memset(chipid,0,sizeof(u8)*2); + efuse_read_data(dev,EFUSE_CHIP_ID,chipid,sizeof(chipid)); + + memset(ocr,0,sizeof(u8)*3); + efuse_read_data(dev,EFUSE_CCCR,ocr,sizeof(ocr)); + + memset(macaddr,0,sizeof(u8)*6); + efuse_read_data(dev,EFUSE_MAC_ADDR,macaddr,sizeof(macaddr)); + + memset(txpowertable,0,sizeof(u8)*28); + efuse_read_data(dev,EFUSE_TXPW_TAB,txpowertable,sizeof(txpowertable)); +} +//------------------------------------------------------------------------------ + +void efuset_test_func_write(struct net_device* dev) +{ + u32 bWordUnit = TRUE; + u8 CCCR=0x02,SDIO_SETTING = 0xFF; + u8 tmpdata[2]; + + u8 macaddr[6] = {0x00,0xe0,0x4c,0x87,0x12,0x66}; + efuse_write_data(dev,EFUSE_MAC_ADDR,macaddr,sizeof(macaddr),bWordUnit); + + bWordUnit = FALSE; + efuse_write_data(dev,EFUSE_CCCR,&CCCR,sizeof(u8),bWordUnit); + + bWordUnit = FALSE; + efuse_write_data(dev,EFUSE_SDIO_SETTING,&SDIO_SETTING,sizeof(u8),bWordUnit); + + bWordUnit = TRUE; + tmpdata[0] =SDIO_SETTING ; + tmpdata[1] =CCCR ; + efuse_write_data(dev,EFUSE_SDIO_SETTING,tmpdata,sizeof(tmpdata),bWordUnit); + +} +//------------------------------------------------------------------------------ + + + + +#endif // #if (HAL_CODE_BASE == RTL8192_S) + + + + + + +/* End of Efuse.c */ + + + + diff --git a/drivers/staging/rtl8192su/r8192S_Efuse.h b/drivers/staging/rtl8192su/r8192S_Efuse.h new file mode 100644 index 000000000000..1e50153ba02c --- /dev/null +++ b/drivers/staging/rtl8192su/r8192S_Efuse.h @@ -0,0 +1,101 @@ +/****************************************************************************** + * + * (c) Copyright 2008, RealTEK Technologies Inc. All Rights Reserved. + * + * Module: Efuse.h ( Header File) + * + * Note: + * + * Function: + * + * Export: + * + * Abbrev: + * + * History: + * Data Who Remark + * + * 09/23/2008 MHC Porting Efuse R/W API from WMAC. + * 11/10/2008 MHC Porting Efuse.h from 8712 SDIO. + * 1. We muse redefine the header file to fit our coding + * style. + * 2. THe API we export to other module, we must redefine + * for 8192S series. + * + * +******************************************************************************/ +/* Check to see if the file has been included already. */ + +#ifndef __INC_EFUSE_H +#define __INC_EFUSE_H + +// Roger porting for 8192SU +#define EFUSE_FOR_92SU 1 + +/*--------------------------Define Parameters-------------------------------*/ +#define EFUSE_MAC_LEN 0x200 + +#define EFUSE_INIT_MAP 0 +#define EFUSE_MODIFY_MAP 1 + +#define EFUSE_CLK_CTRL EFUSE_CTRL +#define EFUSE_BIT(x) (1 << (x)) + +// From 8712!!!!!!!! +#define PG_STATE_HEADER 0x01 +#define PG_STATE_WORD_0 0x02 +#define PG_STATE_WORD_1 0x04 +#define PG_STATE_WORD_2 0x08 +#define PG_STATE_WORD_3 0x10 +#define PG_STATE_DATA 0x20 + +#define PG_SWBYTE_H 0x01 +#define PG_SWBYTE_L 0x02 + +/*--------------------------Define Parameters-------------------------------*/ + + +/*------------------------------Define structure----------------------------*/ + +/*------------------------------Define structure----------------------------*/ + + +/*------------------------Export global variable----------------------------*/ +/*------------------------Export global variable----------------------------*/ + +/*------------------------Export Marco Definition---------------------------*/ + +/*------------------------Export Marco Definition---------------------------*/ + + +/*--------------------------Exported Function prototype---------------------*/ +extern void +EFUSE_Initialize(struct net_device* dev); +extern u8 +EFUSE_Read1Byte(struct net_device* dev,u16 Address); +extern void +EFUSE_Write1Byte(struct net_device* dev,u16 Address,u8 Value); + +#ifdef EFUSE_FOR_92SU +extern void +ReadEFuse(struct net_device* dev,u16 _offset,u16 _size_byte,u8* pbuf); +extern void +ReadEFuseByte(struct net_device* dev,u16 _offset,u8 *pbuf); +#endif // #if (EFUSE_FOR_92SU == 1) + +extern void +EFUSE_ShadowRead(struct net_device* dev,unsigned char Type,unsigned short Offset,u32 *Value); +extern void +EFUSE_ShadowWrite(struct net_device* dev,unsigned char Type,unsigned short Offset,u32 Value); +extern void +EFUSE_ShadowUpdate(struct net_device* dev); +extern void +EFUSE_ShadowMapUpdate(struct net_device* dev); + +extern bool +EFUSE_ProgramMap(struct net_device* dev,char* pFileName, u8 TableType); // 0=Shadow 1=Real Efuse +/*--------------------------Exported Function prototype---------------------*/ + +/* End of Efuse.h */ + +#endif //__INC_EFUSE_H diff --git a/drivers/staging/rtl8192su/r8192S_FwImgDTM.h b/drivers/staging/rtl8192su/r8192S_FwImgDTM.h new file mode 100644 index 000000000000..afced75271bb --- /dev/null +++ b/drivers/staging/rtl8192su/r8192S_FwImgDTM.h @@ -0,0 +1,3797 @@ +#ifndef HAL8192PciE_FW_IMG_DTM_H +#define HAL8192PciE_FW_IMG_DTM_H + +/*Created on 2008/ 3/11, 8:34*/ +#include <linux/types.h> + +#define MACPHY_ArrayLengthDTM 18 +#define MACPHY_Array_PGLengthDTM 30 +#define AGCTAB_ArrayLengthDTM 384 +#define AGCTAB_ArrayLength 384 + +#define BootArrayLengthDTM 344 +u8 Rtl8192PciEFwBootArrayDTM[BootArrayLengthDTM] = { +0x10,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x3c,0x08,0xbf,0xc0,0x25,0x08,0x00,0x08, +0x3c,0x09,0xb0,0x03,0xad,0x28,0x00,0x20,0x40,0x80,0x68,0x00,0x00,0x00,0x00,0x00, +0x3c,0x0a,0xd0,0x00,0x40,0x8a,0x60,0x00,0x00,0x00,0x00,0x00,0x3c,0x08,0x80,0x01, +0x25,0x08,0xbc,0xf0,0x24,0x09,0x00,0x01,0x3c,0x01,0x7f,0xff,0x34,0x21,0xff,0xff, +0x01,0x01,0x50,0x24,0x00,0x09,0x48,0x40,0x35,0x29,0x00,0x01,0x01,0x2a,0x10,0x2b, +0x14,0x40,0xff,0xfc,0x00,0x00,0x00,0x00,0x3c,0x0a,0x00,0x00,0x25,0x4a,0x00,0x00, +0x4c,0x8a,0x00,0x00,0x4c,0x89,0x08,0x00,0x00,0x00,0x00,0x00,0x3c,0x08,0x80,0x01, +0x25,0x08,0xbc,0xf0,0x3c,0x01,0x80,0x00,0x01,0x21,0x48,0x25,0x3c,0x0a,0xbf,0xc0, +0x25,0x4a,0x00,0x7c,0x3c,0x0b,0xb0,0x03,0xad,0x6a,0x00,0x20,0xad,0x00,0x00,0x00, +0x21,0x08,0x00,0x04,0x01,0x09,0x10,0x2b,0x14,0x40,0xff,0xf8,0x00,0x00,0x00,0x00, +0x3c,0x08,0x80,0x01,0x25,0x08,0x7f,0xff,0x24,0x09,0x00,0x01,0x3c,0x01,0x7f,0xff, +0x34,0x21,0xff,0xff,0x01,0x01,0x50,0x24,0x00,0x09,0x48,0x40,0x35,0x29,0x00,0x01, +0x01,0x2a,0x10,0x2b,0x14,0x40,0xff,0xfc,0x00,0x00,0x00,0x00,0x3c,0x0a,0x80,0x01, +0x25,0x4a,0x00,0x00,0x3c,0x01,0x7f,0xff,0x34,0x21,0xff,0xff,0x01,0x41,0x50,0x24, +0x3c,0x09,0x00,0x01,0x35,0x29,0x7f,0xff,0x4c,0x8a,0x20,0x00,0x4c,0x89,0x28,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x24,0x08,0x04,0x10, +0x00,0x00,0x00,0x00,0x40,0x88,0xa0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x3c,0x08,0xbf,0xc0,0x00,0x00,0x00,0x00,0x8d,0x09,0x00,0x00,0x00,0x00,0x00,0x00, +0x3c,0x0a,0xbf,0xc0,0x25,0x4a,0x01,0x20,0x3c,0x0b,0xb0,0x03,0xad,0x6a,0x00,0x20, +0x3c,0x08,0xb0,0x03,0x8d,0x09,0x00,0x00,0x00,0x00,0x00,0x00,0x35,0x29,0x00,0x10, +0xad,0x09,0x00,0x00,0x00,0x00,0x00,0x00,0x3c,0x08,0x80,0x00,0x25,0x08,0x5f,0x84, +0x01,0x00,0x00,0x08,0x00,0x00,0x00,0x00,}; + +#define MainArrayLengthDTM 48368 +u8 Rtl8192PciEFwMainArrayDTM[MainArrayLengthDTM] = { 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+0x3c,0x04,0xb0,0x03,0x3c,0x06,0xb0,0x07,0x3c,0x02,0x80,0x01,0x34,0xc6,0x00,0x18, +0x34,0x84,0x00,0x20,0x24,0x42,0xbc,0x40,0x24,0x03,0xff,0x83,0xac,0x82,0x00,0x00, +0xa0,0xc3,0x00,0x00,0x90,0xc4,0x00,0x00,0x27,0xbd,0xff,0xf8,0x3c,0x03,0xb0,0x07, +0x24,0x02,0xff,0x82,0xa3,0xa4,0x00,0x00,0xa0,0x62,0x00,0x00,0x90,0x64,0x00,0x00, +0x3c,0x02,0xb0,0x07,0x34,0x42,0x00,0x08,0xa3,0xa4,0x00,0x01,0xa0,0x40,0x00,0x00, +0x90,0x43,0x00,0x00,0x24,0x02,0x00,0x03,0x3c,0x05,0xb0,0x07,0xa3,0xa3,0x00,0x00, +0xa0,0xc2,0x00,0x00,0x90,0xc4,0x00,0x00,0x34,0xa5,0x00,0x10,0x24,0x02,0x00,0x06, +0x3c,0x03,0xb0,0x07,0xa3,0xa4,0x00,0x00,0x34,0x63,0x00,0x38,0xa0,0xa2,0x00,0x00, +0x90,0x64,0x00,0x00,0x3c,0x02,0xb0,0x07,0x34,0x42,0x00,0x20,0xa3,0xa4,0x00,0x00, +0xa0,0xa0,0x00,0x00,0x90,0xa3,0x00,0x00,0xaf,0x82,0xc2,0x5c,0xa3,0xa3,0x00,0x00, +0xa0,0x40,0x00,0x00,0x90,0x43,0x00,0x00,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x08, +}; + +#define DataArrayLengthDTM 2860 +u8 Rtl8192PciEFwDataArrayDTM[DataArrayLengthDTM] = { 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+0x80,0x00,0xa7,0x98,0x80,0x00,0xa7,0x90,0x80,0x00,0xa7,0x98,0x80,0x00,0xa7,0x78, +0x80,0x00,0xa7,0x98,0x80,0x00,0xa7,0x98,0x80,0x00,0xab,0xc0,0x80,0x00,0xa8,0xb0, +0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8, +0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8, +0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8, +0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8, +0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8, +0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8, +0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8, +0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8, +0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8, +0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8, +0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8, +0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8, +0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xa8,0xbc,0x80,0x00,0xaa,0xc8, +0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8, +0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8, +0x80,0x00,0xaa,0xc8,0x80,0x00,0xa8,0x44,0x80,0x00,0xa9,0x90,0x80,0x00,0xaa,0xc8, +0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xa9,0x90, +0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8, +0x80,0x00,0xa9,0x98,0x80,0x00,0xa9,0xb8,0x80,0x00,0xa9,0xc0,0x80,0x00,0xaa,0xc8, +0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0x18,0x80,0x00,0xaa,0xc8,0x80,0x00,0xa8,0xc4, +0x80,0x00,0xaa,0xc8,0x80,0x00,0xaa,0xc8,0x80,0x00,0xa8,0xc0,}; + +#define PHY_REGArrayLengthDTM 1 +u32 Rtl8192PciEPHY_REGArrayDTM[PHY_REGArrayLengthDTM] = { +0x0, }; + +#define PHY_REG_1T2RArrayLengthDTM 296 +u32 Rtl8192PciEPHY_REG_1T2RArrayDTM[PHY_REG_1T2RArrayLengthDTM] = { +0x800,0x00000000, +0x804,0x00000001, +0x808,0x0000fc00, +0x80c,0x0000001c, +0x810,0x801010aa, +0x814,0x008514d0, +0x818,0x00000040, +0x81c,0x00000000, +0x820,0x00000004, +0x824,0x00690000, +0x828,0x00000004, +0x82c,0x00e90000, +0x830,0x00000004, +0x834,0x00690000, +0x838,0x00000004, +0x83c,0x00e90000, +0x840,0x00000000, +0x844,0x00000000, +0x848,0x00000000, +0x84c,0x00000000, +0x850,0x00000000, +0x854,0x00000000, +0x858,0x65a965a9, +0x85c,0x65a965a9, +0x860,0x001f0010, +0x864,0x007f0010, +0x868,0x001f0010, +0x86c,0x007f0010, +0x870,0x0f100f70, +0x874,0x0f100f70, +0x878,0x00000000, +0x87c,0x00000000, +0x880,0x6870e36c, +0x884,0xe3573600, +0x888,0x4260c340, +0x88c,0x0000ff00, +0x890,0x00000000, +0x894,0xfffffffe, +0x898,0x40302010, +0x89c,0x00706050, +0x8b0,0x00000000, +0x8e0,0x00000000, +0x8e4,0x00000000, +0x900,0x00000000, +0x904,0x00000023, +0x908,0x00000000, +0x90c,0x31121311, +0xa00,0x00d0c7d8, +0xa04,0x811f0008, +0xa08,0x80cd8300, +0xa0c,0x2e62740f, +0xa10,0x95009b78, +0xa14,0x11145008, +0xa18,0x00881117, +0xa1c,0x89140fa0, +0xa20,0x1a1b0000, +0xa24,0x090e1317, +0xa28,0x00000204, +0xa2c,0x00000000, +0xc00,0x00000040, +0xc04,0x00005411, +0xc08,0x000000e4, +0xc0c,0x6c6c6c6c, +0xc10,0x08800000, +0xc14,0x40000100, +0xc18,0x08000000, +0xc1c,0x40000100, +0xc20,0x08000000, +0xc24,0x40000100, +0xc28,0x08000000, +0xc2c,0x40000100, +0xc30,0x6de98a44, +0xc34,0x469652cd, +0xc38,0x49475996, +0xc3c,0x0a9a9764, +0xc40,0x1f7c423f, +0xc44,0x000100b7, +0xc48,0xec020000, +0xc4c,0x00000300, +0xc50,0x69543430, +0xc54,0x433c0094, +0xc58,0x69543430, +0xc5c,0x433c0094, +0xc60,0x69543430, +0xc64,0x433c0094, +0xc68,0x69543430, +0xc6c,0x433c0094, +0xc70,0x2c7f000d, +0xc74,0x0186175b, +0xc78,0x0000001f, +0xc7c,0x00b91612, +0xc80,0x40000100, +0xc84,0x20000000, +0xc88,0x40000100, +0xc8c,0x08000000, +0xc90,0x40000100, +0xc94,0x00000000, +0xc98,0x40000100, +0xc9c,0x00000000, +0xca0,0x00492492, +0xca4,0x00000000, +0xca8,0x00000000, +0xcac,0x00000000, +0xcb0,0x00000000, +0xcb4,0x00000000, +0xcb8,0x00000000, +0xcbc,0x00492492, +0xcc0,0x00000000, +0xcc4,0x00000000, +0xcc8,0x00000000, +0xccc,0x00000000, +0xcd0,0x00000000, +0xcd4,0x00000000, +0xcd8,0x64b22427, +0xcdc,0x00766932, +0xce0,0x00222222, +0xd00,0x00000740, +0xd04,0x00000401, +0xd08,0x0000907f, +0xd0c,0x00000001, +0xd10,0xa0633333, +0xd14,0x33333c63, +0xd18,0x6a8f5b6b, +0xd1c,0x00000000, +0xd20,0x00000000, +0xd24,0x00000000, +0xd28,0x00000000, +0xd2c,0xcc979975, +0xd30,0x00000000, +0xd34,0x00000000, +0xd38,0x00000000, +0xd3c,0x00027293, +0xd40,0x00000000, +0xd44,0x00000000, +0xd48,0x00000000, +0xd4c,0x00000000, +0xd50,0x6437140a, +0xd54,0x024dbd02, +0xd58,0x00000000, +0xd5c,0x2d432064, +0xe00,0x161a1a1a, +0xe04,0x12121416, +0xe08,0x00001800, +0xe0c,0x00000000, +0xe10,0x161a1a1a, +0xe14,0x12121416, +0xe18,0x161a1a1a, +0xe1c,0x12121416, +}; + +#define RadioA_ArrayLengthDTM 246 +u32 Rtl8192PciERadioA_ArrayDTM[RadioA_ArrayLengthDTM] = { +0x019,0x00000003, +0x000,0x000000bf, +0x001,0x00000ee0, +0x002,0x0000004c, +0x003,0x000007f1, +0x004,0x00000975, +0x005,0x00000c58, +0x006,0x00000ae6, +0x007,0x000000ca, +0x008,0x00000e1c, +0x009,0x000007f0, +0x00a,0x000009d0, +0x00b,0x000001ba, +0x00c,0x00000240, +0x00e,0x00000020, +0x00f,0x00000ff0, +0x012,0x00000806, +0x014,0x000005ab, +0x015,0x00000f80, +0x016,0x00000020, +0x017,0x00000597, +0x018,0x0000050a, +0x01a,0x00000e00, +0x01b,0x00000f5e, +0x01c,0x00000008, +0x01d,0x00000607, +0x01e,0x000006cc, +0x01f,0x00000000, +0x020,0x00000096, +0x01f,0x00000001, +0x020,0x00000076, +0x01f,0x00000002, +0x020,0x00000056, +0x01f,0x00000003, +0x020,0x00000036, +0x01f,0x00000004, +0x020,0x00000016, +0x01f,0x00000005, +0x020,0x000001f6, +0x01f,0x00000006, +0x020,0x000001d6, +0x01f,0x00000007, +0x020,0x000001b6, +0x01f,0x00000008, +0x020,0x00000196, +0x01f,0x00000009, +0x020,0x00000176, +0x01f,0x0000000a, +0x020,0x000000f7, +0x01f,0x0000000b, +0x020,0x000000d7, +0x01f,0x0000000c, +0x020,0x000000b7, +0x01f,0x0000000d, +0x020,0x00000097, +0x01f,0x0000000e, +0x020,0x00000077, +0x01f,0x0000000f, +0x020,0x00000057, +0x01f,0x00000010, +0x020,0x00000037, +0x01f,0x00000011, +0x020,0x000000fb, +0x01f,0x00000012, +0x020,0x000000db, +0x01f,0x00000013, +0x020,0x000000bb, +0x01f,0x00000014, +0x020,0x000000ff, +0x01f,0x00000015, +0x020,0x000000e3, +0x01f,0x00000016, +0x020,0x000000c3, +0x01f,0x00000017, +0x020,0x000000a3, +0x01f,0x00000018, +0x020,0x00000083, +0x01f,0x00000019, +0x020,0x00000063, +0x01f,0x0000001a, +0x020,0x00000043, +0x01f,0x0000001b, +0x020,0x00000023, +0x01f,0x0000001c, +0x020,0x00000003, +0x01f,0x0000001d, +0x020,0x000001e3, +0x01f,0x0000001e, +0x020,0x000001c3, +0x01f,0x0000001f, +0x020,0x000001a3, +0x01f,0x00000020, +0x020,0x00000183, +0x01f,0x00000021, +0x020,0x00000163, +0x01f,0x00000022, +0x020,0x00000143, +0x01f,0x00000023, +0x020,0x00000123, +0x01f,0x00000024, +0x020,0x00000103, +0x023,0x00000203, +0x024,0x00000200, +0x00b,0x000001ba, +0x02c,0x000003d7, +0x02d,0x00000ff0, +0x000,0x00000037, +0x004,0x00000160, +0x007,0x00000080, +0x002,0x0000088d, +0x0fe,0x00000000, +0x0fe,0x00000000, +0x016,0x00000200, +0x016,0x00000380, +0x016,0x00000020, +0x016,0x000001a0, +0x000,0x000000bf, +0x00d,0x0000001f, +0x00d,0x00000c9f, +0x002,0x0000004d, +0x000,0x00000cbf, +0x004,0x00000975, +0x007,0x00000700, +}; + +#define RadioB_ArrayLengthDTM 78 +u32 Rtl8192PciERadioB_ArrayDTM[RadioB_ArrayLengthDTM] = { +0x019,0x00000003, +0x000,0x000000bf, +0x001,0x000006e0, +0x002,0x0000004c, +0x003,0x000007f1, +0x004,0x00000975, +0x005,0x00000c58, +0x006,0x00000ae6, +0x007,0x000000ca, +0x008,0x00000e1c, +0x000,0x000000b7, +0x00a,0x00000850, +0x000,0x000000bf, +0x00b,0x000001ba, +0x00c,0x00000240, +0x00e,0x00000020, +0x015,0x00000f80, +0x016,0x00000020, +0x017,0x00000597, +0x018,0x0000050a, +0x01a,0x00000e00, +0x01b,0x00000f5e, +0x01d,0x00000607, +0x01e,0x000006cc, +0x00b,0x000001ba, +0x023,0x00000203, +0x024,0x00000200, +0x000,0x00000037, +0x004,0x00000160, +0x016,0x00000200, +0x016,0x00000380, +0x016,0x00000020, +0x016,0x000001a0, +0x00d,0x00000ccc, +0x000,0x000000bf, +0x002,0x0000004d, +0x000,0x00000cbf, +0x004,0x00000975, +0x007,0x00000700, +}; + +#define RadioC_ArrayLengthDTM 1 +u32 Rtl8192PciERadioC_ArrayDTM[RadioC_ArrayLengthDTM] = { +0x0, }; + +#define RadioD_ArrayLengthDTM 1 +u32 Rtl8192PciERadioD_ArrayDTM[RadioD_ArrayLengthDTM] = { +0x0, }; + +u32 Rtl8192PciEMACPHY_ArrayDTM[] = { +0x03c,0xffff0000,0x00000f0f, +0x340,0xffffffff,0x161a1a1a, +0x344,0xffffffff,0x12121416, +0x348,0x0000ffff,0x00001818, +0x12c,0xffffffff,0x04000802, +0x318,0x00000fff,0x00000100, +}; + +u32 Rtl8192PciEMACPHY_Array_PGDTM[] = { +0x03c,0xffff0000,0x00000f0f, +0xe00,0xffffffff,0x06090909, +0xe04,0xffffffff,0x00030306, +0xe08,0x0000ff00,0x00000000, +0xe10,0xffffffff,0x050b0b0e, +0xe14,0xffffffff,0x00030305, +0xe18,0xffffffff,0x050b0b0e, +0xe1c,0xffffffff,0x00030305, +0x12c,0xffffffff,0x04000802, +0x318,0x00000fff,0x00000800, +}; + +u32 Rtl8192PciEAGCTAB_ArrayDTM[AGCTAB_ArrayLength] = { +0xc78,0x7d000001, +0xc78,0x7d010001, +0xc78,0x7d020001, +0xc78,0x7d030001, +0xc78,0x7d040001, +0xc78,0x7d050001, +0xc78,0x7c060001, +0xc78,0x7b070001, +0xc78,0x7a080001, +0xc78,0x79090001, +0xc78,0x780a0001, +0xc78,0x770b0001, +0xc78,0x760c0001, +0xc78,0x750d0001, +0xc78,0x740e0001, +0xc78,0x730f0001, +0xc78,0x72100001, +0xc78,0x71110001, +0xc78,0x70120001, +0xc78,0x6f130001, +0xc78,0x6e140001, +0xc78,0x6d150001, +0xc78,0x6c160001, +0xc78,0x6b170001, +0xc78,0x6a180001, +0xc78,0x69190001, +0xc78,0x681a0001, +0xc78,0x671b0001, +0xc78,0x661c0001, +0xc78,0x651d0001, +0xc78,0x641e0001, +0xc78,0x491f0001, +0xc78,0x48200001, +0xc78,0x47210001, +0xc78,0x46220001, +0xc78,0x45230001, +0xc78,0x44240001, +0xc78,0x43250001, +0xc78,0x28260001, +0xc78,0x27270001, +0xc78,0x26280001, +0xc78,0x25290001, +0xc78,0x242a0001, +0xc78,0x232b0001, +0xc78,0x222c0001, +0xc78,0x212d0001, +0xc78,0x202e0001, +0xc78,0x0a2f0001, +0xc78,0x08300001, +0xc78,0x06310001, +0xc78,0x05320001, +0xc78,0x04330001, +0xc78,0x03340001, +0xc78,0x02350001, +0xc78,0x01360001, +0xc78,0x00370001, +0xc78,0x00380001, +0xc78,0x00390001, +0xc78,0x003a0001, +0xc78,0x003b0001, +0xc78,0x003c0001, +0xc78,0x003d0001, +0xc78,0x003e0001, +0xc78,0x003f0001, +0xc78,0x7d400001, +0xc78,0x7d410001, +0xc78,0x7d420001, +0xc78,0x7d430001, +0xc78,0x7d440001, +0xc78,0x7d450001, +0xc78,0x7c460001, +0xc78,0x7b470001, +0xc78,0x7a480001, +0xc78,0x79490001, +0xc78,0x784a0001, +0xc78,0x774b0001, +0xc78,0x764c0001, +0xc78,0x754d0001, +0xc78,0x744e0001, +0xc78,0x734f0001, +0xc78,0x72500001, +0xc78,0x71510001, +0xc78,0x70520001, +0xc78,0x6f530001, +0xc78,0x6e540001, +0xc78,0x6d550001, +0xc78,0x6c560001, +0xc78,0x6b570001, +0xc78,0x6a580001, +0xc78,0x69590001, +0xc78,0x685a0001, +0xc78,0x675b0001, +0xc78,0x665c0001, +0xc78,0x655d0001, +0xc78,0x645e0001, +0xc78,0x495f0001, +0xc78,0x48600001, +0xc78,0x47610001, +0xc78,0x46620001, +0xc78,0x45630001, +0xc78,0x44640001, +0xc78,0x43650001, +0xc78,0x28660001, +0xc78,0x27670001, +0xc78,0x26680001, +0xc78,0x25690001, +0xc78,0x246a0001, +0xc78,0x236b0001, +0xc78,0x226c0001, +0xc78,0x216d0001, +0xc78,0x206e0001, +0xc78,0x0a6f0001, +0xc78,0x08700001, +0xc78,0x06710001, +0xc78,0x05720001, +0xc78,0x04730001, +0xc78,0x03740001, +0xc78,0x02750001, +0xc78,0x01760001, +0xc78,0x00770001, +0xc78,0x00780001, +0xc78,0x00790001, +0xc78,0x007a0001, +0xc78,0x007b0001, +0xc78,0x007c0001, +0xc78,0x007d0001, +0xc78,0x007e0001, +0xc78,0x007f0001, +0xc78,0x2e00001e, +0xc78,0x2e01001e, +0xc78,0x2e02001e, +0xc78,0x2e03001e, +0xc78,0x2e04001e, +0xc78,0x2e05001e, +0xc78,0x3006001e, +0xc78,0x3407001e, +0xc78,0x3908001e, +0xc78,0x3c09001e, +0xc78,0x3f0a001e, +0xc78,0x420b001e, +0xc78,0x440c001e, +0xc78,0x450d001e, +0xc78,0x460e001e, +0xc78,0x460f001e, +0xc78,0x4710001e, +0xc78,0x4811001e, +0xc78,0x4912001e, +0xc78,0x4a13001e, +0xc78,0x4b14001e, +0xc78,0x4b15001e, +0xc78,0x4c16001e, +0xc78,0x4d17001e, +0xc78,0x4e18001e, +0xc78,0x4f19001e, +0xc78,0x4f1a001e, +0xc78,0x501b001e, +0xc78,0x511c001e, +0xc78,0x521d001e, +0xc78,0x521e001e, +0xc78,0x531f001e, +0xc78,0x5320001e, +0xc78,0x5421001e, +0xc78,0x5522001e, +0xc78,0x5523001e, +0xc78,0x5624001e, +0xc78,0x5725001e, +0xc78,0x5726001e, +0xc78,0x5827001e, +0xc78,0x5828001e, +0xc78,0x5929001e, +0xc78,0x592a001e, +0xc78,0x5a2b001e, +0xc78,0x5b2c001e, +0xc78,0x5c2d001e, +0xc78,0x5c2e001e, +0xc78,0x5d2f001e, +0xc78,0x5e30001e, +0xc78,0x5f31001e, +0xc78,0x6032001e, +0xc78,0x6033001e, +0xc78,0x6134001e, +0xc78,0x6235001e, +0xc78,0x6336001e, +0xc78,0x6437001e, +0xc78,0x6438001e, +0xc78,0x6539001e, +0xc78,0x663a001e, +0xc78,0x673b001e, +0xc78,0x673c001e, +0xc78,0x683d001e, +0xc78,0x693e001e, +0xc78,0x6a3f001e, +}; + +#endif //__INC_HAL8192PciE_FW_IMG_DTM_H diff --git a/drivers/staging/rtl8192su/r8192S_firmware.c b/drivers/staging/rtl8192su/r8192S_firmware.c new file mode 100644 index 000000000000..b3d69b33acba --- /dev/null +++ b/drivers/staging/rtl8192su/r8192S_firmware.c @@ -0,0 +1,1023 @@ +/************************************************************************************************** + * Procedure: Init boot code/firmware code/data session + * + * Description: This routine will intialize firmware. If any error occurs during the initialization + * process, the routine shall terminate immediately and return fail. + * NIC driver should call NdisOpenFile only from MiniportInitialize. + * + * Arguments: The pointer of the adapter + + * Returns: + * NDIS_STATUS_FAILURE - the following initialization process should be terminated + * NDIS_STATUS_SUCCESS - if firmware initialization process success +**************************************************************************************************/ +//#include "ieee80211.h" +#if defined(RTL8192SE)||defined(RTL8192SU) +#include "r8192U.h" +#include "r8192S_firmware.h" +#include <linux/unistd.h> + +#ifdef RTL8192SU +#include "r8192S_hw.h" +#include "r8192SU_HWImg.h" +//#include "r8192S_FwImgDTM.h" +#else +//#include "r8192U_hw.h" +#include "r8192xU_firmware_img.h" +#endif + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) +#include <linux/firmware.h> +#endif + +#define byte(x,n) ( (x >> (8 * n)) & 0xff ) + +// +// Description: This routine will intialize firmware. If any error occurs during the initialization +// process, the routine shall terminate immediately and return fail. +// +// Arguments: The pointer of the adapter +// Code address (Virtual address, should fill descriptor with physical address) +// Code size +// Created by Roger, 2008.04.10. +// +bool FirmwareDownloadCode(struct net_device *dev, u8 * code_virtual_address,u32 buffer_len) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + bool rt_status = true; + u16 frag_threshold = MAX_FIRMWARE_CODE_SIZE; //Fragmentation might be required in 90/92 but not in 92S + u16 frag_length, frag_offset = 0; + struct sk_buff *skb; + unsigned char *seg_ptr; + cb_desc *tcb_desc; + u8 bLastIniPkt = 0; + u16 ExtraDescOffset = 0; + +#ifdef RTL8192SE + fw_SetRQPN(dev); // For 92SE only +#endif + + RT_TRACE(COMP_FIRMWARE, "--->FirmwareDownloadCode()\n" ); + + //MAX_TRANSMIT_BUFFER_SIZE + if(buffer_len >= MAX_FIRMWARE_CODE_SIZE-USB_HWDESC_HEADER_LEN) + { + RT_TRACE(COMP_ERR, "Size over MAX_FIRMWARE_CODE_SIZE! \n"); + goto cmdsend_downloadcode_fail; + } + + ExtraDescOffset = USB_HWDESC_HEADER_LEN; + + do { + if((buffer_len-frag_offset) > frag_threshold) + { + frag_length = frag_threshold + ExtraDescOffset; + } + else + { + frag_length = (u16)(buffer_len - frag_offset + ExtraDescOffset); + bLastIniPkt = 1; + } + + /* Allocate skb buffer to contain firmware info and tx descriptor info. */ + skb = dev_alloc_skb(frag_length); + memcpy((unsigned char *)(skb->cb),&dev,sizeof(dev)); + + tcb_desc = (cb_desc*)(skb->cb + MAX_DEV_ADDR_SIZE); + tcb_desc->queue_index = TXCMD_QUEUE; + tcb_desc->bCmdOrInit = DESC_PACKET_TYPE_INIT; + tcb_desc->bLastIniPkt = bLastIniPkt; + + skb_reserve(skb, ExtraDescOffset); + seg_ptr = (u8 *)skb_put(skb, (u32)(frag_length-ExtraDescOffset)); + memcpy(seg_ptr, code_virtual_address+frag_offset, (u32)(frag_length-ExtraDescOffset)); + + tcb_desc->txbuf_size= frag_length; + + if(!priv->ieee80211->check_nic_enough_desc(dev,tcb_desc->queue_index)|| + (!skb_queue_empty(&priv->ieee80211->skb_waitQ[tcb_desc->queue_index]))||\ + (priv->ieee80211->queue_stop) ) + { + RT_TRACE(COMP_FIRMWARE,"=====================================================> tx full!\n"); + skb_queue_tail(&priv->ieee80211->skb_waitQ[tcb_desc->queue_index], skb); + } + else + { + priv->ieee80211->softmac_hard_start_xmit(skb,dev); + } + + frag_offset += (frag_length - ExtraDescOffset); + + }while(frag_offset < buffer_len); + + return rt_status ; + + +cmdsend_downloadcode_fail: + rt_status = false; + RT_TRACE(COMP_ERR, "CmdSendDownloadCode fail !!\n"); + return rt_status; + +} + +#ifdef RTL8192SE +static void fw_SetRQPN(struct net_device *dev) +{ + // Only for 92SE HW bug, we have to set RAPN before every FW download + // We can remove the code later. + write_nic_dword(dev, RQPN, 0xffffffff); + write_nic_dword(dev, RQPN+4, 0xffffffff); + write_nic_byte(dev, RQPN+8, 0xff); + write_nic_byte(dev, RQPN+0xB, 0x80); + //#if ((HAL_CODE_BASE == RTL8192_S) && (PLATFORM != PLATFORM_WINDOWS_USB)) + +} /* fw_SetRQPN */ +#endif + +RT_STATUS +FirmwareEnableCPU(struct net_device *dev) +{ + + RT_STATUS rtStatus = RT_STATUS_SUCCESS; + u8 tmpU1b, CPUStatus = 0; + u16 tmpU2b; + u32 iCheckTime = 200; + + RT_TRACE(COMP_FIRMWARE, "-->FirmwareEnableCPU()\n" ); +#ifdef RTL8192SE + fw_SetRQPN(dev); // For 92SE only +#endif + // Enable CPU. + tmpU1b = read_nic_byte(dev, SYS_CLKR); + write_nic_byte(dev, SYS_CLKR, (tmpU1b|SYS_CPU_CLKSEL)); //AFE source + + tmpU2b = read_nic_word(dev, SYS_FUNC_EN); + write_nic_word(dev, SYS_FUNC_EN, (tmpU2b|FEN_CPUEN)); + + //Polling IMEM Ready after CPU has refilled. + do + { + CPUStatus = read_nic_byte(dev, TCR); + if(CPUStatus& IMEM_RDY) + { + RT_TRACE(COMP_FIRMWARE, "IMEM Ready after CPU has refilled.\n"); + break; + } + + //usleep(100); + udelay(100); + }while(iCheckTime--); + + if(!(CPUStatus & IMEM_RDY)) + return RT_STATUS_FAILURE; + + RT_TRACE(COMP_FIRMWARE, "<--FirmwareEnableCPU(): rtStatus(%#x)\n", rtStatus); + return rtStatus; +} + +FIRMWARE_8192S_STATUS +FirmwareGetNextStatus(FIRMWARE_8192S_STATUS FWCurrentStatus) +{ + FIRMWARE_8192S_STATUS NextFWStatus = 0; + + switch(FWCurrentStatus) + { + case FW_STATUS_INIT: + NextFWStatus = FW_STATUS_LOAD_IMEM; + break; + + case FW_STATUS_LOAD_IMEM: + NextFWStatus = FW_STATUS_LOAD_EMEM; + break; + + case FW_STATUS_LOAD_EMEM: + NextFWStatus = FW_STATUS_LOAD_DMEM; + break; + + case FW_STATUS_LOAD_DMEM: + NextFWStatus = FW_STATUS_READY; + break; + + default: + RT_TRACE(COMP_ERR,"Invalid FW Status(%#x)!!\n", FWCurrentStatus); + break; + } + return NextFWStatus; +} + +bool +FirmwareCheckReady(struct net_device *dev, u8 LoadFWStatus) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + RT_STATUS rtStatus = RT_STATUS_SUCCESS; + rt_firmware *pFirmware = priv->pFirmware; + int PollingCnt = 1000; + //u8 tmpU1b, CPUStatus = 0; + u8 CPUStatus = 0; + u32 tmpU4b; + //bool bOrgIMREnable; + + RT_TRACE(COMP_FIRMWARE, "--->FirmwareCheckReady(): LoadStaus(%d),", LoadFWStatus); + + pFirmware->FWStatus = (FIRMWARE_8192S_STATUS)LoadFWStatus; + if( LoadFWStatus == FW_STATUS_LOAD_IMEM) + { + do + {//Polling IMEM code done. + CPUStatus = read_nic_byte(dev, TCR); + if(CPUStatus& IMEM_CODE_DONE) + break; + + udelay(5); + }while(PollingCnt--); + if(!(CPUStatus & IMEM_CHK_RPT) || PollingCnt <= 0) + { + RT_TRACE(COMP_ERR, "FW_STATUS_LOAD_IMEM FAIL CPU, Status=%x\r\n", CPUStatus); + return false; + } + } + else if( LoadFWStatus == FW_STATUS_LOAD_EMEM) + {//Check Put Code OK and Turn On CPU + do + {//Polling EMEM code done. + CPUStatus = read_nic_byte(dev, TCR); + if(CPUStatus& EMEM_CODE_DONE) + break; + + udelay(5); + }while(PollingCnt--); + if(!(CPUStatus & EMEM_CHK_RPT)) + { + RT_TRACE(COMP_ERR, "FW_STATUS_LOAD_EMEM FAIL CPU, Status=%x\r\n", CPUStatus); + return false; + } + + // Turn On CPU + rtStatus = FirmwareEnableCPU(dev); + if(rtStatus != RT_STATUS_SUCCESS) + { + RT_TRACE(COMP_ERR, "Enable CPU fail ! \n" ); + return false; + } + } + else if( LoadFWStatus == FW_STATUS_LOAD_DMEM) + { + do + {//Polling DMEM code done + CPUStatus = read_nic_byte(dev, TCR); + if(CPUStatus& DMEM_CODE_DONE) + break; + + udelay(5); + }while(PollingCnt--); + + if(!(CPUStatus & DMEM_CODE_DONE)) + { + RT_TRACE(COMP_ERR, "Polling DMEM code done fail ! CPUStatus(%#x)\n", CPUStatus); + return false; + } + + RT_TRACE(COMP_FIRMWARE, "DMEM code download success, CPUStatus(%#x)\n", CPUStatus); + +// PollingCnt = 100; // Set polling cycle to 10ms. + PollingCnt = 10000; // Set polling cycle to 10ms. + + do + {//Polling Load Firmware ready + CPUStatus = read_nic_byte(dev, TCR); + if(CPUStatus & FWRDY) + break; + + udelay(100); + }while(PollingCnt--); + + RT_TRACE(COMP_FIRMWARE, "Polling Load Firmware ready, CPUStatus(%x)\n", CPUStatus); + + //if(!(CPUStatus & LOAD_FW_READY)) + //if((CPUStatus & LOAD_FW_READY) != 0xff) + if((CPUStatus & LOAD_FW_READY) != LOAD_FW_READY) + { + RT_TRACE(COMP_ERR, "Polling Load Firmware ready fail ! CPUStatus(%x)\n", CPUStatus); + return false; + } + + // + // <Roger_Notes> USB interface will update reserved followings parameters later!! + // 2008.08.28. + // +#ifdef RTL8192SE + //write_nic_dword(dev, RQPN, 0x10101010); + //write_nic_byte(dev, 0xAB, 0x80); +#endif + + // + // <Roger_Notes> If right here, we can set TCR/RCR to desired value + // and config MAC lookback mode to normal mode. 2008.08.28. + // + tmpU4b = read_nic_dword(dev,TCR); + write_nic_dword(dev, TCR, (tmpU4b&(~TCR_ICV))); + + tmpU4b = read_nic_dword(dev, RCR); + write_nic_dword(dev, RCR, + (tmpU4b|RCR_APPFCS|RCR_APP_ICV|RCR_APP_MIC)); + + RT_TRACE(COMP_FIRMWARE, "FirmwareCheckReady(): Current RCR settings(%#x)\n", tmpU4b); + +#if (defined (RTL8192SU_FPGA_2MAC_VERIFICATION) ||defined (RTL8192SU_ASIC_VERIFICATION)) +#ifdef NOT_YET //YJ,TMP + priv->TransmitConfig = read_nic_dword(dev, TCR); + RT_TRACE(COMP_FIRMWARE, "FirmwareCheckReady(): Current TCR settings(%x)\n", priv->TransmitConfig); + pHalData->FwRsvdTxPageCfg = read_nic_byte(dev, FW_RSVD_PG_CRTL); +#endif +#endif + + // Set to normal mode. + write_nic_byte(dev, LBKMD_SEL, LBK_NORMAL); + + } + + RT_TRACE(COMP_FIRMWARE, "<---FirmwareCheckReady(): LoadFWStatus(%d), rtStatus(%x)\n", LoadFWStatus, rtStatus); + return (rtStatus == RT_STATUS_SUCCESS) ? true:false; +} + +// +// Description: This routine is to update the RF types in FW header partially. +// +// Created by Roger, 2008.12.24. +// +u8 FirmwareHeaderMapRfType(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + switch(priv->rf_type) + { + case RF_1T1R: return 0x11; + case RF_1T2R: return 0x12; + case RF_2T2R: return 0x22; + case RF_2T2R_GREEN: return 0x92; + default: + RT_TRACE(COMP_INIT, "Unknown RF type(%x)\n",priv->rf_type); + break; + } + return 0x22; +} + + +// +// Description: This routine is to update the private parts in FW header partially. +// +// Created by Roger, 2008.12.18. +// +void FirmwareHeaderPriveUpdate(struct net_device *dev, PRT_8192S_FIRMWARE_PRIV pFwPriv) +{ + struct r8192_priv *priv = ieee80211_priv(dev); +#ifdef RTL8192SU + // Update USB endpoint number for RQPN settings. + pFwPriv->usb_ep_num = priv->EEPROMUsbEndPointNumber; // endpoint number: 4, 6 and 11. + RT_TRACE(COMP_INIT, "FirmwarePriveUpdate(): usb_ep_num(%#x)\n", pFwPriv->usb_ep_num); +#endif + + // Update RF types for RATR settings. + pFwPriv->rf_config = FirmwareHeaderMapRfType(dev); +} + + + +bool FirmwareDownload92S(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + bool rtStatus = true; + const char *pFwImageFileName[1] = {"RTL8192SU/rtl8192sfw.bin"}; + u8 *pucMappedFile = NULL; + u32 ulFileLength, ulInitStep = 0; + u8 FwHdrSize = RT_8192S_FIRMWARE_HDR_SIZE; + rt_firmware *pFirmware = priv->pFirmware; + u8 FwStatus = FW_STATUS_INIT; + PRT_8192S_FIRMWARE_HDR pFwHdr = NULL; + PRT_8192S_FIRMWARE_PRIV pFwPriv = NULL; + int rc; + const struct firmware *fw_entry; + u32 file_length = 0; + + pFirmware->FWStatus = FW_STATUS_INIT; + + RT_TRACE(COMP_FIRMWARE, " --->FirmwareDownload92S()\n"); + + //3// + //3 //<1> Open Image file, and map file to contineous memory if open file success. + //3 // or read image file from array. Default load from BIN file + //3// +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) + priv->firmware_source = FW_SOURCE_HEADER_FILE; +#else + priv->firmware_source = FW_SOURCE_IMG_FILE;// We should decided by Reg. +#endif + + switch( priv->firmware_source ) + { + case FW_SOURCE_IMG_FILE: +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + if(pFirmware->szFwTmpBufferLen == 0) + { + + rc = request_firmware(&fw_entry, pFwImageFileName[ulInitStep],&priv->udev->dev);//===>1 + if(rc < 0 ) { + RT_TRACE(COMP_ERR, "request firmware fail!\n"); + goto DownloadFirmware_Fail; + } + + if(fw_entry->size > sizeof(pFirmware->szFwTmpBuffer)) + { + RT_TRACE(COMP_ERR, "img file size exceed the container buffer fail!\n"); + release_firmware(fw_entry); + goto DownloadFirmware_Fail; + } + + memcpy(pFirmware->szFwTmpBuffer,fw_entry->data,fw_entry->size); + pFirmware->szFwTmpBufferLen = fw_entry->size; + release_firmware(fw_entry); + + pucMappedFile = pFirmware->szFwTmpBuffer; + file_length = pFirmware->szFwTmpBufferLen; + + //Retrieve FW header. + pFirmware->pFwHeader = (PRT_8192S_FIRMWARE_HDR) pucMappedFile; + pFwHdr = pFirmware->pFwHeader; + RT_TRACE(COMP_FIRMWARE,"signature:%x, version:%x, size:%x, imemsize:%x, sram size:%x\n", \ + pFwHdr->Signature, pFwHdr->Version, pFwHdr->DMEMSize, \ + pFwHdr->IMG_IMEM_SIZE, pFwHdr->IMG_SRAM_SIZE); + pFirmware->FirmwareVersion = byte(pFwHdr->Version ,0); + if ((pFwHdr->IMG_IMEM_SIZE==0) || (pFwHdr->IMG_IMEM_SIZE > sizeof(pFirmware->FwIMEM))) + { + RT_TRACE(COMP_ERR, "%s: memory for data image is less than IMEM required\n",\ + __FUNCTION__); + goto DownloadFirmware_Fail; + } else { + pucMappedFile+=FwHdrSize; + + //Retrieve IMEM image. + memcpy(pFirmware->FwIMEM, pucMappedFile, pFwHdr->IMG_IMEM_SIZE); + pFirmware->FwIMEMLen = pFwHdr->IMG_IMEM_SIZE; + } + + if (pFwHdr->IMG_SRAM_SIZE > sizeof(pFirmware->FwEMEM)) + { + RT_TRACE(COMP_ERR, "%s: memory for data image is less than EMEM required\n",\ + __FUNCTION__); + goto DownloadFirmware_Fail; + } else { + pucMappedFile += pFirmware->FwIMEMLen; + + /* Retriecve EMEM image */ + memcpy(pFirmware->FwEMEM, pucMappedFile, pFwHdr->IMG_SRAM_SIZE);//===>6 + pFirmware->FwEMEMLen = pFwHdr->IMG_SRAM_SIZE; + } + + + } +#endif + break; + + case FW_SOURCE_HEADER_FILE: +#if 1 +#define Rtl819XFwImageArray Rtl8192SUFwImgArray + //2008.11.10 Add by tynli. + pucMappedFile = Rtl819XFwImageArray; + ulFileLength = ImgArrayLength; + + RT_TRACE(COMP_INIT,"Fw download from header.\n"); + /* Retrieve FW header*/ + pFirmware->pFwHeader = (PRT_8192S_FIRMWARE_HDR) pucMappedFile; + pFwHdr = pFirmware->pFwHeader; + RT_TRACE(COMP_FIRMWARE,"signature:%x, version:%x, size:%x, imemsize:%x, sram size:%x\n", \ + pFwHdr->Signature, pFwHdr->Version, pFwHdr->DMEMSize, \ + pFwHdr->IMG_IMEM_SIZE, pFwHdr->IMG_SRAM_SIZE); + pFirmware->FirmwareVersion = byte(pFwHdr->Version ,0); + + if ((pFwHdr->IMG_IMEM_SIZE==0) || (pFwHdr->IMG_IMEM_SIZE > sizeof(pFirmware->FwIMEM))) + { + printk("FirmwareDownload92S(): memory for data image is less than IMEM required\n"); + goto DownloadFirmware_Fail; + } else { + pucMappedFile+=FwHdrSize; + //Retrieve IMEM image. + memcpy(pFirmware->FwIMEM, pucMappedFile, pFwHdr->IMG_IMEM_SIZE); + pFirmware->FwIMEMLen = pFwHdr->IMG_IMEM_SIZE; + } + + if (pFwHdr->IMG_SRAM_SIZE > sizeof(pFirmware->FwEMEM)) + { + printk(" FirmwareDownload92S(): memory for data image is less than EMEM required\n"); + goto DownloadFirmware_Fail; + } else { + pucMappedFile+= pFirmware->FwIMEMLen; + + //Retriecve EMEM image. + memcpy(pFirmware->FwEMEM, pucMappedFile, pFwHdr->IMG_SRAM_SIZE); + pFirmware->FwEMEMLen = pFwHdr->IMG_SRAM_SIZE; + } +#endif + break; + default: + break; + } + + FwStatus = FirmwareGetNextStatus(pFirmware->FWStatus); + while(FwStatus!= FW_STATUS_READY) + { + // Image buffer redirection. + switch(FwStatus) + { + case FW_STATUS_LOAD_IMEM: + pucMappedFile = pFirmware->FwIMEM; + ulFileLength = pFirmware->FwIMEMLen; + break; + + case FW_STATUS_LOAD_EMEM: + pucMappedFile = pFirmware->FwEMEM; + ulFileLength = pFirmware->FwEMEMLen; + break; + + case FW_STATUS_LOAD_DMEM: + /* <Roger_Notes> Partial update the content of header private. 2008.12.18 */ + pFwHdr = pFirmware->pFwHeader; + pFwPriv = (PRT_8192S_FIRMWARE_PRIV)&pFwHdr->FWPriv; + FirmwareHeaderPriveUpdate(dev, pFwPriv); + pucMappedFile = (u8*)(pFirmware->pFwHeader)+RT_8192S_FIRMWARE_HDR_EXCLUDE_PRI_SIZE; + ulFileLength = FwHdrSize-RT_8192S_FIRMWARE_HDR_EXCLUDE_PRI_SIZE; + break; + + default: + RT_TRACE(COMP_ERR, "Unexpected Download step!!\n"); + goto DownloadFirmware_Fail; + break; + } + + //3// + //3// <2> Download image file + //3 // + rtStatus = FirmwareDownloadCode(dev, pucMappedFile, ulFileLength); + + if(rtStatus != true) + { + RT_TRACE(COMP_ERR, "FirmwareDownloadCode() fail ! \n" ); + goto DownloadFirmware_Fail; + } + + //3// + //3// <3> Check whether load FW process is ready + //3 // + rtStatus = FirmwareCheckReady(dev, FwStatus); + + if(rtStatus != true) + { + RT_TRACE(COMP_ERR, "FirmwareDownloadCode() fail ! \n"); + goto DownloadFirmware_Fail; + } + + FwStatus = FirmwareGetNextStatus(pFirmware->FWStatus); + } + + RT_TRACE(COMP_FIRMWARE, "Firmware Download Success!!\n"); + return rtStatus; + + DownloadFirmware_Fail: + RT_TRACE(COMP_ERR, "Firmware Download Fail!!%x\n",read_nic_word(dev, TCR)); + rtStatus = false; + return rtStatus; +} +#else +void firmware_init_param(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + rt_firmware *pfirmware = priv->pFirmware; + + pfirmware->cmdpacket_frag_thresold = GET_COMMAND_PACKET_FRAG_THRESHOLD(MAX_TRANSMIT_BUFFER_SIZE); +} + +/* + * segment the img and use the ptr and length to remember info on each segment + * + */ +bool fw_download_code(struct net_device *dev, u8 *code_virtual_address, u32 buffer_len) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + bool rt_status = true; + //u16 frag_threshold; + u16 frag_length, frag_offset = 0; + //u16 total_size; + int i; + + //rt_firmware *pfirmware = priv->pFirmware; + struct sk_buff *skb; + unsigned char *seg_ptr; + cb_desc *tcb_desc; + u8 bLastIniPkt; +#ifdef RTL8192SE + fw_SetRQPN(dev); // For 92SE only +#endif + +#ifndef RTL8192SU + if(buffer_len >= 64000-USB_HWDESC_HEADER_LEN) + { + return rt_status; + } + firmware_init_param(dev); + //Fragmentation might be required + frag_threshold = pfirmware->cmdpacket_frag_thresold; +#endif + + do { +#ifndef RTL8192SU + if((buffer_len - frag_offset) > frag_threshold) { + frag_length = frag_threshold ; + bLastIniPkt = 0; + + } else +#endif + { + frag_length = buffer_len - frag_offset; + bLastIniPkt = 1; + + } + + /* Allocate skb buffer to contain firmware info and tx descriptor info + * add 4 to avoid packet appending overflow. + * */ + #ifdef RTL8192U + skb = dev_alloc_skb(USB_HWDESC_HEADER_LEN + frag_length + 4); + #else + skb = dev_alloc_skb(frag_length + 4); + #endif + memcpy((unsigned char *)(skb->cb),&dev,sizeof(dev)); + tcb_desc = (cb_desc*)(skb->cb + MAX_DEV_ADDR_SIZE); + tcb_desc->queue_index = TXCMD_QUEUE; + tcb_desc->bCmdOrInit = DESC_PACKET_TYPE_INIT; + tcb_desc->bLastIniPkt = bLastIniPkt; + + #ifdef RTL8192U + skb_reserve(skb, USB_HWDESC_HEADER_LEN); + #endif + seg_ptr = skb->data; + /* + * Transform from little endian to big endian + * and pending zero + */ + for(i=0 ; i < frag_length; i+=4) { + *seg_ptr++ = ((i+0)<frag_length)?code_virtual_address[i+3]:0; + *seg_ptr++ = ((i+1)<frag_length)?code_virtual_address[i+2]:0; + *seg_ptr++ = ((i+2)<frag_length)?code_virtual_address[i+1]:0; + *seg_ptr++ = ((i+3)<frag_length)?code_virtual_address[i+0]:0; + } + tcb_desc->txbuf_size= (u16)i; + skb_put(skb, i); + + if(!priv->ieee80211->check_nic_enough_desc(dev,tcb_desc->queue_index)|| + (!skb_queue_empty(&priv->ieee80211->skb_waitQ[tcb_desc->queue_index]))||\ + (priv->ieee80211->queue_stop) ) { + RT_TRACE(COMP_FIRMWARE,"=====================================================> tx full!\n"); + skb_queue_tail(&priv->ieee80211->skb_waitQ[tcb_desc->queue_index], skb); + } else { + priv->ieee80211->softmac_hard_start_xmit(skb,dev); + } + + code_virtual_address += frag_length; + frag_offset += frag_length; + + }while(frag_offset < buffer_len); + + return rt_status; + +#if 0 +cmdsend_downloadcode_fail: + rt_status = false; + RT_TRACE(COMP_ERR, "CmdSendDownloadCode fail !!\n"); + return rt_status; +#endif +} + +bool +fwSendNullPacket( + struct net_device *dev, + u32 Length +) +{ + bool rtStatus = true; + struct r8192_priv *priv = ieee80211_priv(dev); + struct sk_buff *skb; + cb_desc *tcb_desc; + unsigned char *ptr_buf; + bool bLastInitPacket = false; + + //PlatformAcquireSpinLock(dev, RT_TX_SPINLOCK); + + //Get TCB and local buffer from common pool. (It is shared by CmdQ, MgntQ, and USB coalesce DataQ) + skb = dev_alloc_skb(Length+ 4); + memcpy((unsigned char *)(skb->cb),&dev,sizeof(dev)); + tcb_desc = (cb_desc*)(skb->cb + MAX_DEV_ADDR_SIZE); + tcb_desc->queue_index = TXCMD_QUEUE; + tcb_desc->bCmdOrInit = DESC_PACKET_TYPE_INIT; + tcb_desc->bLastIniPkt = bLastInitPacket; + ptr_buf = skb_put(skb, Length); + memset(ptr_buf,0,Length); + tcb_desc->txbuf_size= (u16)Length; + + if(!priv->ieee80211->check_nic_enough_desc(dev,tcb_desc->queue_index)|| + (!skb_queue_empty(&priv->ieee80211->skb_waitQ[tcb_desc->queue_index]))||\ + (priv->ieee80211->queue_stop) ) { + RT_TRACE(COMP_FIRMWARE,"===================NULL packet==================================> tx full!\n"); + skb_queue_tail(&priv->ieee80211->skb_waitQ[tcb_desc->queue_index], skb); + } else { + priv->ieee80211->softmac_hard_start_xmit(skb,dev); + } + + //PlatformReleaseSpinLock(dev, RT_TX_SPINLOCK); + return rtStatus; +} + +//----------------------------------------------------------------------------- +// Procedure: Check whether main code is download OK. If OK, turn on CPU +// +// Description: CPU register locates in different page against general register. +// Switch to CPU register in the begin and switch back before return +// +// +// Arguments: The pointer of the dev +// +// Returns: +// NDIS_STATUS_FAILURE - the following initialization process should be terminated +// NDIS_STATUS_SUCCESS - if firmware initialization process success +//----------------------------------------------------------------------------- +bool CPUcheck_maincodeok_turnonCPU(struct net_device *dev) +{ + bool rt_status = true; + int check_putcodeOK_time = 200000, check_bootOk_time = 200000; + u32 CPU_status = 0; + + /* Check whether put code OK */ + do { + CPU_status = read_nic_dword(dev, CPU_GEN); + + if(CPU_status&CPU_GEN_PUT_CODE_OK) + break; + + }while(check_putcodeOK_time--); + + if(!(CPU_status&CPU_GEN_PUT_CODE_OK)) { + RT_TRACE(COMP_ERR, "Download Firmware: Put code fail!\n"); + goto CPUCheckMainCodeOKAndTurnOnCPU_Fail; + } else { + RT_TRACE(COMP_FIRMWARE, "Download Firmware: Put code ok!\n"); + } + + /* Turn On CPU */ + CPU_status = read_nic_dword(dev, CPU_GEN); + write_nic_byte(dev, CPU_GEN, (u8)((CPU_status|CPU_GEN_PWR_STB_CPU)&0xff)); + mdelay(1000); + + /* Check whether CPU boot OK */ + do { + CPU_status = read_nic_dword(dev, CPU_GEN); + + if(CPU_status&CPU_GEN_BOOT_RDY) + break; + }while(check_bootOk_time--); + + if(!(CPU_status&CPU_GEN_BOOT_RDY)) { + goto CPUCheckMainCodeOKAndTurnOnCPU_Fail; + } else { + RT_TRACE(COMP_FIRMWARE, "Download Firmware: Boot ready!\n"); + } + + return rt_status; + +CPUCheckMainCodeOKAndTurnOnCPU_Fail: + RT_TRACE(COMP_ERR, "ERR in %s()\n", __FUNCTION__); + rt_status = FALSE; + return rt_status; +} + +bool CPUcheck_firmware_ready(struct net_device *dev) +{ + + bool rt_status = true; + int check_time = 200000; + u32 CPU_status = 0; + + /* Check Firmware Ready */ + do { + CPU_status = read_nic_dword(dev, CPU_GEN); + + if(CPU_status&CPU_GEN_FIRM_RDY) + break; + + }while(check_time--); + + if(!(CPU_status&CPU_GEN_FIRM_RDY)) + goto CPUCheckFirmwareReady_Fail; + else + RT_TRACE(COMP_FIRMWARE, "Download Firmware: Firmware ready!\n"); + + return rt_status; + +CPUCheckFirmwareReady_Fail: + RT_TRACE(COMP_ERR, "ERR in %s()\n", __FUNCTION__); + rt_status = false; + return rt_status; + +} + +bool init_firmware(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + bool rt_status = TRUE; + + u8 *firmware_img_buf[3] = { &rtl8190_fwboot_array[0], + &rtl8190_fwmain_array[0], + &rtl8190_fwdata_array[0]}; + + u32 firmware_img_len[3] = { sizeof(rtl8190_fwboot_array), + sizeof(rtl8190_fwmain_array), + sizeof(rtl8190_fwdata_array)}; + u32 file_length = 0; + u8 *mapped_file = NULL; + u32 init_step = 0; + opt_rst_type_e rst_opt = OPT_SYSTEM_RESET; + firmware_init_step_e starting_state = FW_INIT_STEP0_BOOT; + + rt_firmware *pfirmware = priv->pFirmware; + const struct firmware *fw_entry; + const char *fw_name[3] = { "RTL8192U/boot.img", + "RTL8192U/main.img", + "RTL8192U/data.img"}; + int rc; + + RT_TRACE(COMP_FIRMWARE, " PlatformInitFirmware()==>\n"); + + if (pfirmware->firmware_status == FW_STATUS_0_INIT ) { + /* it is called by reset */ + rst_opt = OPT_SYSTEM_RESET; + starting_state = FW_INIT_STEP0_BOOT; + // TODO: system reset + + }else if(pfirmware->firmware_status == FW_STATUS_5_READY) { + /* it is called by Initialize */ + rst_opt = OPT_FIRMWARE_RESET; + starting_state = FW_INIT_STEP2_DATA; + }else { + RT_TRACE(COMP_FIRMWARE, "PlatformInitFirmware: undefined firmware state\n"); + } + + /* + * Download boot, main, and data image for System reset. + * Download data image for firmware reseta + */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) + priv->firmware_source = FW_SOURCE_HEADER_FILE; +#else + priv->firmware_source = FW_SOURCE_IMG_FILE; +#endif + for(init_step = starting_state; init_step <= FW_INIT_STEP2_DATA; init_step++) { + /* + * Open Image file, and map file to contineous memory if open file success. + * or read image file from array. Default load from IMG file + */ + if(rst_opt == OPT_SYSTEM_RESET) { + switch(priv->firmware_source) { + case FW_SOURCE_IMG_FILE: + #if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + rc = request_firmware(&fw_entry, fw_name[init_step],&priv->udev->dev); + if(rc < 0 ) { + RT_TRACE(COMP_ERR, "request firmware fail!\n"); + goto download_firmware_fail; + } + + if(fw_entry->size > sizeof(pfirmware->firmware_buf)) { + RT_TRACE(COMP_ERR, "img file size exceed the container buffer fail!\n"); + goto download_firmware_fail; + } + + if(init_step != FW_INIT_STEP1_MAIN) { + memcpy(pfirmware->firmware_buf,fw_entry->data,fw_entry->size); + mapped_file = pfirmware->firmware_buf; + file_length = fw_entry->size; + } else { + #ifdef RTL8190P + memcpy(pfirmware->firmware_buf,fw_entry->data,fw_entry->size); + mapped_file = pfirmware->firmware_buf; + file_length = fw_entry->size; + #else + memset(pfirmware->firmware_buf,0,128); + memcpy(&pfirmware->firmware_buf[128],fw_entry->data,fw_entry->size); + mapped_file = pfirmware->firmware_buf; + file_length = fw_entry->size + 128; + #endif + } + pfirmware->firmware_buf_size = file_length; + #endif + break; + + case FW_SOURCE_HEADER_FILE: + mapped_file = firmware_img_buf[init_step]; + file_length = firmware_img_len[init_step]; + if(init_step == FW_INIT_STEP2_DATA) { + memcpy(pfirmware->firmware_buf, mapped_file, file_length); + pfirmware->firmware_buf_size = file_length; + } + break; + + default: + break; + } + + + }else if(rst_opt == OPT_FIRMWARE_RESET ) { + /* we only need to download data.img here */ + mapped_file = pfirmware->firmware_buf; + file_length = pfirmware->firmware_buf_size; + } + + /* Download image file */ + /* The firmware download process is just as following, + * 1. that is each packet will be segmented and inserted to the wait queue. + * 2. each packet segment will be put in the skb_buff packet. + * 3. each skb_buff packet data content will already include the firmware info + * and Tx descriptor info + * */ + rt_status = fw_download_code(dev,mapped_file,file_length); + #if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + if(rst_opt == OPT_SYSTEM_RESET) { + release_firmware(fw_entry); + } + #endif + + if(rt_status != TRUE) { + goto download_firmware_fail; + } + + switch(init_step) { + case FW_INIT_STEP0_BOOT: + /* Download boot + * initialize command descriptor. + * will set polling bit when firmware code is also configured + */ + pfirmware->firmware_status = FW_STATUS_1_MOVE_BOOT_CODE; +#ifdef RTL8190P + // To initialize IMEM, CPU move code from 0x80000080, hence, we send 0x80 byte packet + rt_status = fwSendNullPacket(dev, RTL8190_CPU_START_OFFSET); + if(rt_status != true) + { + RT_TRACE(COMP_INIT, "fwSendNullPacket() fail ! \n"); + goto download_firmware_fail; + } +#endif + //mdelay(1000); + /* + * To initialize IMEM, CPU move code from 0x80000080, + * hence, we send 0x80 byte packet + */ + break; + + case FW_INIT_STEP1_MAIN: + /* Download firmware code. Wait until Boot Ready and Turn on CPU */ + pfirmware->firmware_status = FW_STATUS_2_MOVE_MAIN_CODE; + + /* Check Put Code OK and Turn On CPU */ + rt_status = CPUcheck_maincodeok_turnonCPU(dev); + if(rt_status != TRUE) { + RT_TRACE(COMP_ERR, "CPUcheck_maincodeok_turnonCPU fail!\n"); + goto download_firmware_fail; + } + + pfirmware->firmware_status = FW_STATUS_3_TURNON_CPU; + break; + + case FW_INIT_STEP2_DATA: + /* download initial data code */ + pfirmware->firmware_status = FW_STATUS_4_MOVE_DATA_CODE; + mdelay(1); + + rt_status = CPUcheck_firmware_ready(dev); + if(rt_status != TRUE) { + RT_TRACE(COMP_ERR, "CPUcheck_firmware_ready fail(%d)!\n",rt_status); + goto download_firmware_fail; + } + + /* wait until data code is initialized ready.*/ + pfirmware->firmware_status = FW_STATUS_5_READY; + break; + } + } + + RT_TRACE(COMP_FIRMWARE, "Firmware Download Success\n"); + //assert(pfirmware->firmware_status == FW_STATUS_5_READY, ("Firmware Download Fail\n")); + + return rt_status; + +download_firmware_fail: + RT_TRACE(COMP_ERR, "ERR in %s()\n", __FUNCTION__); + rt_status = FALSE; + return rt_status; + +} +#endif + diff --git a/drivers/staging/rtl8192su/r8192S_firmware.h b/drivers/staging/rtl8192su/r8192S_firmware.h new file mode 100644 index 000000000000..047f8ae44740 --- /dev/null +++ b/drivers/staging/rtl8192su/r8192S_firmware.h @@ -0,0 +1,212 @@ +#ifndef __INC_FIRMWARE_H +#define __INC_FIRMWARE_H + + +//#define RTL8190_CPU_START_OFFSET 0x80 +/* TODO: this definition is TBD */ +//#define USB_HWDESC_HEADER_LEN 0 + +/* It should be double word alignment */ +//#if DEV_BUS_TYPE==PCI_INTERFACE +//#define GET_COMMAND_PACKET_FRAG_THRESHOLD(v) 4*(v/4) - 8 +//#else +//#define GET_COMMAND_PACKET_FRAG_THRESHOLD(v) (4*(v/4) - 8 - USB_HWDESC_HEADER_LEN) +//#endif + +//typedef enum _firmware_init_step{ +// FW_INIT_STEP0_BOOT = 0, +// FW_INIT_STEP1_MAIN = 1, +// FW_INIT_STEP2_DATA = 2, +//}firmware_init_step_e; + +//typedef enum _DESC_PACKET_TYPE{ +// DESC_PACKET_TYPE_INIT = 0, +// DESC_PACKET_TYPE_NORMAL = 1, +//}DESC_PACKET_TYPE; +#define RTL8192S_FW_PKT_FRAG_SIZE 0xFF00 // 64K + + +#define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000 //64k +#define MAX_FIRMWARE_CODE_SIZE 0xFF00 // Firmware Local buffer size. +#define RTL8190_CPU_START_OFFSET 0x80 + +#ifdef RTL8192SE +//It should be double word alignment +#define GET_COMMAND_PACKET_FRAG_THRESHOLD(v) 4*(v/4) - 8 +#else +#define GET_COMMAND_PACKET_FRAG_THRESHOLD(v) (4*(v/4) - 8 - USB_HWDESC_HEADER_LEN) +#endif + +//typedef enum _DESC_PACKET_TYPE{ +// DESC_PACKET_TYPE_INIT = 0, +// DESC_PACKET_TYPE_NORMAL = 1, +//}DESC_PACKET_TYPE; + +// Forward declaration. +//typedef struct _ADAPTER ADAPTER, *PADAPTER; +#ifdef RTL8192S +typedef enum _firmware_init_step{ + FW_INIT_STEP0_IMEM = 0, + FW_INIT_STEP1_MAIN = 1, + FW_INIT_STEP2_DATA = 2, +}firmware_init_step_e; +#else +typedef enum _firmware_init_step{ + FW_INIT_STEP0_BOOT = 0, + FW_INIT_STEP1_MAIN = 1, + FW_INIT_STEP2_DATA = 2, +}firmware_init_step_e; +#endif + +/* due to rtl8192 firmware */ +typedef enum _desc_packet_type_e{ + DESC_PACKET_TYPE_INIT = 0, + DESC_PACKET_TYPE_NORMAL = 1, +}desc_packet_type_e; + +typedef enum _firmware_source{ + FW_SOURCE_IMG_FILE = 0, + FW_SOURCE_HEADER_FILE = 1, +}firmware_source_e, *pfirmware_source_e; + + +typedef enum _opt_rst_type{ + OPT_SYSTEM_RESET = 0, + OPT_FIRMWARE_RESET = 1, +}opt_rst_type_e; + +/*typedef enum _FIRMWARE_STATUS{ + FW_STATUS_0_INIT = 0, + FW_STATUS_1_MOVE_BOOT_CODE = 1, + FW_STATUS_2_MOVE_MAIN_CODE = 2, + FW_STATUS_3_TURNON_CPU = 3, + FW_STATUS_4_MOVE_DATA_CODE = 4, + FW_STATUS_5_READY = 5, +}FIRMWARE_STATUS; +*/ +//-------------------------------------------------------------------------------- +// RTL8192S Firmware related, Revised by Roger, 2008.12.18. +//-------------------------------------------------------------------------------- +typedef struct _RT_8192S_FIRMWARE_PRIV { //8-bytes alignment required + + //--- long word 0 ---- + u8 signature_0; //0x12: CE product, 0x92: IT product + u8 signature_1; //0x87: CE product, 0x81: IT product + u8 hci_sel; //0x81: PCI-AP, 01:PCIe, 02: 92S-U, 0x82: USB-AP, 0x12: 72S-U, 03:SDIO + u8 chip_version; //the same value as reigster value + u8 customer_ID_0; //customer ID low byte + u8 customer_ID_1; //customer ID high byte + u8 rf_config; //0x11: 1T1R, 0x12: 1T2R, 0x92: 1T2R turbo, 0x22: 2T2R + u8 usb_ep_num; // 4: 4EP, 6: 6EP, 11: 11EP + + //--- long word 1 ---- + u8 regulatory_class_0; //regulatory class bit map 0 + u8 regulatory_class_1; //regulatory class bit map 1 + u8 regulatory_class_2; //regulatory class bit map 2 + u8 regulatory_class_3; //regulatory class bit map 3 + u8 rfintfs; // 0:SWSI, 1:HWSI, 2:HWPI + u8 def_nettype; + u8 rsvd010; + u8 rsvd011; + + + //--- long word 2 ---- + u8 lbk_mode; //0x00: normal, 0x03: MACLBK, 0x01: PHYLBK + u8 mp_mode; // 1: for MP use, 0: for normal driver (to be discussed) + u8 rsvd020; + u8 rsvd021; + u8 rsvd022; + u8 rsvd023; + u8 rsvd024; + u8 rsvd025; + + //--- long word 3 ---- + u8 qos_en; // QoS enable + u8 bw_40MHz_en; // 40MHz BW enable + u8 AMSDU2AMPDU_en; // 4181 convert AMSDU to AMPDU, 0: disable + u8 AMPDU_en; // 11n AMPDU enable + u8 rate_control_offload;//FW offloads, 0: driver handles + u8 aggregation_offload; // FW offloads, 0: driver handles + u8 rsvd030; + u8 rsvd031; + + + //--- long word 4 ---- + unsigned char beacon_offload; // 1. FW offloads, 0: driver handles + unsigned char MLME_offload; // 2. FW offloads, 0: driver handles + unsigned char hwpc_offload; // 3. FW offloads, 0: driver handles + unsigned char tcp_checksum_offload; // 4. FW offloads, 0: driver handles + unsigned char tcp_offload; // 5. FW offloads, 0: driver handles + unsigned char ps_control_offload; // 6. FW offloads, 0: driver handles + unsigned char WWLAN_offload; // 7. FW offloads, 0: driver handles + unsigned char rsvd040; + + //--- long word 5 ---- + u8 tcp_tx_frame_len_L; //tcp tx packet length low byte + u8 tcp_tx_frame_len_H; //tcp tx packet length high byte + u8 tcp_rx_frame_len_L; //tcp rx packet length low byte + u8 tcp_rx_frame_len_H; //tcp rx packet length high byte + u8 rsvd050; + u8 rsvd051; + u8 rsvd052; + u8 rsvd053; +}RT_8192S_FIRMWARE_PRIV, *PRT_8192S_FIRMWARE_PRIV; + +typedef struct _RT_8192S_FIRMWARE_HDR {//8-byte alinment required + + //--- LONG WORD 0 ---- + u16 Signature; + u16 Version; //0x8000 ~ 0x8FFF for FPGA version, 0x0000 ~ 0x7FFF for ASIC version, + u32 DMEMSize; //define the size of boot loader + + + //--- LONG WORD 1 ---- + u32 IMG_IMEM_SIZE; //define the size of FW in IMEM + u32 IMG_SRAM_SIZE; //define the size of FW in SRAM + + //--- LONG WORD 2 ---- + u32 FW_PRIV_SIZE; //define the size of DMEM variable + u32 Rsvd0; + + //--- LONG WORD 3 ---- + u32 Rsvd1; + u32 Rsvd2; + + RT_8192S_FIRMWARE_PRIV FWPriv; + +}RT_8192S_FIRMWARE_HDR, *PRT_8192S_FIRMWARE_HDR; + +#define RT_8192S_FIRMWARE_HDR_SIZE 80 +#define RT_8192S_FIRMWARE_HDR_EXCLUDE_PRI_SIZE 32 + +typedef enum _FIRMWARE_8192S_STATUS{ + FW_STATUS_INIT = 0, + FW_STATUS_LOAD_IMEM = 1, + FW_STATUS_LOAD_EMEM = 2, + FW_STATUS_LOAD_DMEM = 3, + FW_STATUS_READY = 4, +}FIRMWARE_8192S_STATUS; + +#define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000 //64k + +typedef struct _rt_firmware{ + firmware_source_e eFWSource; + PRT_8192S_FIRMWARE_HDR pFwHeader; + FIRMWARE_8192S_STATUS FWStatus; + u16 FirmwareVersion; + u8 FwIMEM[RTL8190_MAX_FIRMWARE_CODE_SIZE]; + u8 FwEMEM[RTL8190_MAX_FIRMWARE_CODE_SIZE]; + u32 FwIMEMLen; + u32 FwEMEMLen; + u8 szFwTmpBuffer[164000]; + u32 szFwTmpBufferLen; + u16 CmdPacketFragThresold; +}rt_firmware, *prt_firmware; + +//typedef struct _RT_FIRMWARE_INFO_8192SU{ +// u8 szInfo[16]; +//}RT_FIRMWARE_INFO_8192SU, *PRT_FIRMWARE_INFO_8192SU; +bool FirmwareDownload92S(struct net_device *dev); + +#endif + diff --git a/drivers/staging/rtl8192su/r8192S_hw.h b/drivers/staging/rtl8192su/r8192S_hw.h new file mode 100644 index 000000000000..7a3d850de0bf --- /dev/null +++ b/drivers/staging/rtl8192su/r8192S_hw.h @@ -0,0 +1,1677 @@ +/***************************************************************************** + * Copyright(c) 2008, RealTEK Technology Inc. All Right Reserved. + * + * Module: __INC_HAL8192SEREG_H + * + * + * Note: 1. Define Mac register address and corresponding bit mask map + * 2. CCX register + * 3. Backward compatible register with useless address. + * 4. Define 92SU required register address and definition. + * + * + * Export: Constants, macro, functions(API), global variables(None). + * + * Abbrev: + * + * History: + * Data Who Remark + * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h. + * 2. Reorganize code architecture. + * + *****************************************************************************/ +#ifndef R8192S_HW +#define R8192S_HW + +typedef enum _VERSION_8192S{ + VERSION_8192S_ACUT, + VERSION_8192S_BCUT, + VERSION_8192S_CCUT +}VERSION_8192S,*PVERSION_8192S; + +//#ifdef RTL8192SU +typedef enum _VERSION_8192SUsb{ + VERSION_8192SU_A, //A-Cut + VERSION_8192SU_B, //B-Cut + VERSION_8192SU_C, //C-Cut +}VERSION_8192SUsb, *PVERSION_8192SUsb; +//#else +typedef enum _VERSION_819xU{ + VERSION_819xU_A, // A-cut + VERSION_819xU_B, // B-cut + VERSION_819xU_C,// C-cut +}VERSION_819xU,*PVERSION_819xU; +//#endif + +/* 2007/11/15 MH Define different RF type. */ +typedef enum _RT_RF_TYPE_DEFINITION +{ + RF_1T2R = 0, + RF_2T4R, + RF_2T2R, +#ifdef RTL8192SU + RF_1T1R, + RF_2T2R_GREEN, +#endif + //RF_3T3R, + //RF_3T4R, + //RF_4T4R, + RF_819X_MAX_TYPE +}RT_RF_TYPE_DEF_E; + +typedef enum _BaseBand_Config_Type{ + BaseBand_Config_PHY_REG = 0, //Radio Path A + BaseBand_Config_AGC_TAB = 1, //Radio Path B +}BaseBand_Config_Type, *PBaseBand_Config_Type; + +#if 0 +typedef enum _RT_RF_TYPE_819xU{ + RF_TYPE_MIN = 0, + RF_8225, + RF_8256, + RF_8258, + RF_PSEUDO_11N = 4, +}RT_RF_TYPE_819xU, *PRT_RF_TYPE_819xU; +#endif + +#define RTL8187_REQT_READ 0xc0 +#define RTL8187_REQT_WRITE 0x40 +#define RTL8187_REQ_GET_REGS 0x05 +#define RTL8187_REQ_SET_REGS 0x05 + +#define MAX_TX_URB 5 +#define MAX_RX_URB 16 + +#define R8180_MAX_RETRY 255 +//#define MAX_RX_NORMAL_URB 3 +//#define MAX_RX_COMMAND_URB 2 +#define RX_URB_SIZE 9100 + +#define BB_ANTATTEN_CHAN14 0x0c +#define BB_ANTENNA_B 0x40 + +#define BB_HOST_BANG (1<<30) +#define BB_HOST_BANG_EN (1<<2) +#define BB_HOST_BANG_CLK (1<<1) +#define BB_HOST_BANG_RW (1<<3) +#define BB_HOST_BANG_DATA 1 + + +//============================================================ +// 8192S Regsiter bit +//============================================================ +#define BB_GLOBAL_RESET_BIT 0x1 + +#define CR_RST 0x10 +#define CR_RE 0x08 +#define CR_TE 0x04 +#define CR_MulRW 0x01 + +#define MAC_FILTER_MASK ((1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<5) | \ + (1<<12) | (1<<18) | (1<<19) | (1<<20) | (1<<21) | (1<<22) | (1<<23)) + +#define RX_FIFO_THRESHOLD_MASK ((1<<13) | (1<<14) | (1<<15)) +#define RX_FIFO_THRESHOLD_SHIFT 13 +#define RX_FIFO_THRESHOLD_128 3 +#define RX_FIFO_THRESHOLD_256 4 +#define RX_FIFO_THRESHOLD_512 5 +#define RX_FIFO_THRESHOLD_1024 6 +#define RX_FIFO_THRESHOLD_NONE 7 + +#define MAX_RX_DMA_MASK ((1<<8) | (1<<9) | (1<<10)) + +//---------------------------------------------------------------------------- +// 8190 CPU General Register (offset 0x100, 4 byte) +//---------------------------------------------------------------------------- +#define CPU_CCK_LOOPBACK 0x00030000 +#define CPU_GEN_SYSTEM_RESET 0x00000001 +#define CPU_GEN_FIRMWARE_RESET 0x00000008 +#define CPU_GEN_BOOT_RDY 0x00000010 +#define CPU_GEN_FIRM_RDY 0x00000020 +#define CPU_GEN_PUT_CODE_OK 0x00000080 +#define CPU_GEN_BB_RST 0x00000100 +#define CPU_GEN_PWR_STB_CPU 0x00000004 +#define CPU_GEN_NO_LOOPBACK_MSK 0xFFF8FFFF // Set bit18,17,16 to 0. Set bit19 +#define CPU_GEN_NO_LOOPBACK_SET 0x00080000 // Set BIT19 to 1 +//---------------------------------------------------------------------------- +//// +//// 8190 AcmHwCtrl bits (offset 0x171, 1 byte) +////---------------------------------------------------------------------------- +#define MSR_LINK_MASK ((1<<0)|(1<<1)) +#define MSR_LINK_MANAGED 2 +#define MSR_LINK_NONE 0 +#define MSR_LINK_SHIFT 0 +#define MSR_LINK_ADHOC 1 +#define MSR_LINK_MASTER 3 +#define MSR_LINK_ENEDCA (1<<4) + + +//#define Cmd9346CR_9356SEL (1<<4) +#define EPROM_CMD_RESERVED_MASK (1<<5) +#define EPROM_CMD_OPERATING_MODE_SHIFT 6 +#define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6)) +#define EPROM_CMD_CONFIG 0x3 +#define EPROM_CMD_NORMAL 0 +#define EPROM_CMD_LOAD 1 +#define EPROM_CMD_PROGRAM 2 +#define EPROM_CS_SHIFT 3 +#define EPROM_CK_SHIFT 2 +#define EPROM_W_SHIFT 1 +#define EPROM_R_SHIFT 0 + +//#define MAC0 0x000, +//#define MAC1 0x001, +//#define MAC2 0x002, +//#define MAC3 0x003, +//#define MAC4 0x004, +//#define MAC5 0x005, + +//============================================================ +// 8192S Regsiter offset definition +//============================================================ + +// +// MAC register 0x0 - 0x5xx +// 1. System configuration registers. +// 2. Command Control Registers +// 3. MACID Setting Registers +// 4. Timing Control Registers +// 5. FIFO Control Registers +// 6. Adaptive Control Registers +// 7. EDCA Setting Registers +// 8. WMAC, BA and CCX related Register. +// 9. Security Control Registers +// 10. Power Save Control Registers +// 11. General Purpose Registers +// 12. Host Interrupt Status Registers +// 13. Test Mode and Debug Control Registers +// 14. PCIE config register +// + + +// +// 1. System Configuration Registers (Offset: 0x0000 - 0x003F) +// +#define SYS_ISO_CTRL 0x0000 // System Isolation Interface Control. +#define SYS_FUNC_EN 0x0002 // System Function Enable. +#define PMC_FSM 0x0004 // Power Sequence Control. +#define SYS_CLKR 0x0008 // System Clock. +#define EPROM_CMD 0x000A // 93C46/93C56 Command Register. (win CR93C46) +#define EE_VPD 0x000C // EEPROM VPD Data. +#define AFE_MISC 0x0010 // AFE Misc. +#define SPS0_CTRL 0x0011 // Switching Power Supply 0 Control. +#define SPS1_CTRL 0x0018 // Switching Power Supply 1 Control. +#define RF_CTRL 0x001F // RF Block Control. +#define LDOA15_CTRL 0x0020 // V15 Digital LDO Control. +#define LDOV12D_CTRL 0x0021 // V12 Digital LDO Control. +#define LDOHCI12_CTRL 0x0022 // V12 Digital LDO Control. +#define LDO_USB_SDIO 0x0023 // LDO USB Control. +#define LPLDO_CTRL 0x0024 // Low Power LDO Control. +#define AFE_XTAL_CTRL 0x0026 // AFE Crystal Control. +#define AFE_PLL_CTRL 0x0028 // System Function Enable. +#define EFUSE_CTRL 0x0030 // E-Fuse Control. +#define EFUSE_TEST 0x0034 // E-Fuse Test. +#define PWR_DATA 0x0038 // Power on date. +#define DBG_PORT 0x003A // MAC debug port select +#define DPS_TIMER 0x003C // Deep Power Save Timer Register. +#define RCLK_MON 0x003E // Retention Clock Monitor. + +// +// 2. Command Control Registers (Offset: 0x0040 - 0x004F) +// +#define CMDR 0x0040 // MAC Command Register. +#define TXPAUSE 0x0042 // Transmission Pause Register. +#define LBKMD_SEL 0x0043 // Loopback Mode Select Register. +#define TCR 0x0044 // Transmit Configuration Register +#define RCR 0x0048 // Receive Configuration Register +#define MSR 0x004C // Media Status register +#define SYSF_CFG 0x004D // System Function Configuration. +#define RX_PKY_LIMIT 0x004E // RX packet length limit +#define MBIDCTRL 0x004F // MBSSID Control. + +// +// 3. MACID Setting Registers (Offset: 0x0050 - 0x007F) +// +#define MACIDR 0x0050 // MAC ID Register, Offset 0x0050-0x0055 +#define MACIDR0 0x0050 // MAC ID Register, Offset 0x0050-0x0053 +#define MACIDR4 0x0054 // MAC ID Register, Offset 0x0054-0x0055 +#define BSSIDR 0x0058 // BSSID Register, Offset 0x0058-0x005D +#define HWVID 0x005E // HW Version ID. +#define MAR 0x0060 // Multicase Address. +#define MBIDCAMCONTENT 0x0068 // MBSSID CAM Content. +#define MBIDCAMCFG 0x0070 // MBSSID CAM Configuration. +#define BUILDTIME 0x0074 // Build Time Register. +#define BUILDUSER 0x0078 // Build User Register. + +// Redifine MACID register, to compatible prior ICs. +#define IDR0 MACIDR0 +#define IDR4 MACIDR4 + +// +// 4. Timing Control Registers (Offset: 0x0080 - 0x009F) +// +#define TSFR 0x0080 // Timing Sync Function Timer Register. +#define SLOT_TIME 0x0089 // Slot Time Register, in us. +#define USTIME 0x008A // EDCA/TSF clock unit time us unit. +#define SIFS_CCK 0x008C // SIFS for CCK, in us. +#define SIFS_OFDM 0x008E // SIFS for OFDM, in us. +#define PIFS_TIME 0x0090 // PIFS time register. +#define ACK_TIMEOUT 0x0091 // Ack Timeout Register +#define EIFSTR 0x0092 // EIFS time regiser. +#define BCN_INTERVAL 0x0094 // Beacon Interval, in TU. +#define ATIMWND 0x0096 // ATIM Window width, in TU. +#define BCN_DRV_EARLY_INT 0x0098 // Driver Early Interrupt. +#define BCN_DMATIME 0x009A // Beacon DMA and ATIM INT Time. +#define BCN_ERR_THRESH 0x009C // Beacon Error Threshold. +#define MLT 0x009D // MSDU Lifetime. +#define RSVD_MAC_TUNE_US 0x009E // MAC Internal USE. + +// +// 5. FIFO Control Registers (Offset: 0x00A0 - 0x015F) +// +#define RQPN 0x00A0 +#define RQPN1 0x00A0 // Reserved Queue Page Number for BK +#define RQPN2 0x00A1 // Reserved Queue Page Number for BE +#define RQPN3 0x00A2 // Reserved Queue Page Number for VI +#define RQPN4 0x00A3 // Reserved Queue Page Number for VO +#define RQPN5 0x00A4 // Reserved Queue Page Number for HCCA +#define RQPN6 0x00A5 // Reserved Queue Page Number for CMD +#define RQPN7 0x00A6 // Reserved Queue Page Number for MGNT +#define RQPN8 0x00A7 // Reserved Queue Page Number for HIGH +#define RQPN9 0x00A8 // Reserved Queue Page Number for Beacon +#define RQPN10 0x00A9 // Reserved Queue Page Number for Public +#define LD_RQPN 0x00AB // +#define RXFF_BNDY 0x00AC // +#define RXRPT_BNDY 0x00B0 // +#define TXPKTBUF_PGBNDY 0x00B4 // +#define PBP 0x00B5 // +#define RXDRVINFO_SZ 0x00B6 // +#define TXFF_STATUS 0x00B7 // +#define RXFF_STATUS 0x00B8 // +#define TXFF_EMPTY_TH 0x00B9 // +#define SDIO_RX_BLKSZ 0x00BC // +#define RXDMA 0x00BD // +#define RXPKT_NUM 0x00BE // +#define C2HCMD_UDT_SIZE 0x00C0 // +#define C2HCMD_UDT_ADDR 0x00C2 // +#define FIFOPAGE1 0x00C4 // Available public queue page number +#define FIFOPAGE2 0x00C8 // +#define FIFOPAGE3 0x00CC // +#define FIFOPAGE4 0x00D0 // +#define FIFOPAGE5 0x00D4 // +#define FW_RSVD_PG_CRTL 0x00D8 // +#define RXDMA_AGG_PG_TH 0x00D9 // +#define TXRPTFF_RDPTR 0x00E0 // +#define TXRPTFF_WTPTR 0x00E4 // +#define C2HFF_RDPTR 0x00E8 //FIFO Read pointer register. +#define C2HFF_WTPTR 0x00EC //FIFO Write pointer register. +#define RXFF0_RDPTR 0x00F0 // +#define RXFF0_WTPTR 0x00F4 // +#define RXFF1_RDPTR 0x00F8 // +#define RXFF1_WTPTR 0x00FC // +#define RXRPT0_RDPTR 0x0100 // +#define RXRPT0_WTPTR 0x0104 // +#define RXRPT1_RDPTR 0x0108 // +#define RXRPT1_WTPTR 0x010C // +#define RX0_UDT_SIZE 0x0110 // +#define RX1PKTNUM 0x0114 // +#define RXFILTERMAP 0x0116 // +#define RXFILTERMAP_GP1 0x0118 // +#define RXFILTERMAP_GP2 0x011A // +#define RXFILTERMAP_GP3 0x011C // +#define BCNQ_CTRL 0x0120 // +#define MGTQ_CTRL 0x0124 // +#define HIQ_CTRL 0x0128 // +#define VOTID7_CTRL 0x012c // +#define VOTID6_CTRL 0x0130 // +#define VITID5_CTRL 0x0134 // +#define VITID4_CTRL 0x0138 // +#define BETID3_CTRL 0x013c // +#define BETID0_CTRL 0x0140 // +#define BKTID2_CTRL 0x0144 // +#define BKTID1_CTRL 0x0148 // +#define CMDQ_CTRL 0x014c // +#define TXPKT_NUM_CTRL 0x0150 // +#define TXQ_PGADD 0x0152 // +#define TXFF_PG_NUM 0x0154 // +#define TRXDMA_STATUS 0x0156 // + +// +// 6. Adaptive Control Registers (Offset: 0x0160 - 0x01CF) +// +#define INIMCS_SEL 0x0160 // Init MCSrate for 32 MACID 0x160-17f +#define TX_RATE_REG INIMCS_SEL //Current Tx rate register +#define INIRTSMCS_SEL 0x0180 // Init RTSMCSrate +#define RRSR 0x0181 // Response rate setting. +#define ARFR0 0x0184 // Auto Rate Fallback 0 Register. +#define ARFR1 0x0188 // +#define ARFR2 0x018C // +#define ARFR3 0x0190 // +#define ARFR4 0x0194 // +#define ARFR5 0x0198 // +#define ARFR6 0x019C // +#define ARFR7 0x01A0 // +#define AGGLEN_LMT_H 0x01A7 // Aggregation Length Limit for High-MCS +#define AGGLEN_LMT_L 0x01A8 // Aggregation Length Limit for Low-MCS. +#define DARFRC 0x01B0 // Data Auto Rate Fallback Retry Count. +#define RARFRC 0x01B8 // Response Auto Rate Fallback Count. +#define MCS_TXAGC 0x01C0 +#define CCK_TXAGC 0x01C8 + +// +// 7. EDCA Setting Registers (Offset: 0x01D0 - 0x01FF) +// +#define EDCAPARA_VO 0x01D0 // EDCA Parameter Register for VO queue. +#define EDCAPARA_VI 0x01D4 // EDCA Parameter Register for VI queue. +#define EDCAPARA_BE 0x01D8 // EDCA Parameter Register for BE queue. +#define EDCAPARA_BK 0x01DC // EDCA Parameter Register for BK queue. +#define BCNTCFG 0x01E0 // Beacon Time Configuration Register. +#define CWRR 0x01E2 // Contention Window Report Register. +#define ACMAVG 0x01E4 // ACM Average Register. +#define AcmHwCtrl 0x01E7 +#define VO_ADMTM 0x01E8 // Admission Time Register. +#define VI_ADMTM 0x01EC +#define BE_ADMTM 0x01F0 +#define RETRY_LIMIT 0x01F4 // Retry Limit Registers[15:8]-short, [7:0]-long +#define SG_RATE 0x01F6 // Max MCS Rate Available Register, which we Set the hightst SG rate. + +// +// 8. WMAC, BA and CCX related Register. (Offset: 0x0200 - 0x023F) +// +#define NAV_CTRL 0x0200 +#define BW_OPMODE 0x0203 +#define BACAMCMD 0x0204 +#define BACAMCONTENT 0x0208 // Block ACK CAM R/W Register. + +// Roger had defined the 0x2xx register WMAC definition +#define LBDLY 0x0210 // Loopback Delay Register. +#define FWDLY 0x0211 // FW Delay Register. +#define HWPC_RX_CTRL 0x0218 // HW Packet Conversion RX Control Reg +#define MQIR 0x0220 // Mesh Qos Type Indication Register. +#define MAIR 0x0222 // Mesh ACK. +#define MSIR 0x0224 // Mesh HW Security Requirement Indication Reg +#define CLM_RESULT 0x0227 // CCA Busy Fraction(Channel Load) +#define NHM_RPI_CNT 0x0228 // Noise Histogram Measurement (NHM) RPI Report. +#define RXERR_RPT 0x0230 // Rx Error Report. +#define NAV_PROT_LEN 0x0234 // NAV Protection Length. +#define CFEND_TH 0x0236 // CF-End Threshold. +#define AMPDU_MIN_SPACE 0x0237 // AMPDU Min Space. +#define TXOP_STALL_CTRL 0x0238 + +// +// 9. Security Control Registers (Offset: 0x0240 - 0x025F) +// +#define RWCAM 0x0240 //IN 8190 Data Sheet is called CAMcmd +#define WCAMI 0x0244 // Software write CAM input content +#define RCAMO 0x0248 // Software read/write CAM config +#define CAMDBG 0x024C +#define SECR 0x0250 //Security Configuration Register + +// +// 10. Power Save Control Registers (Offset: 0x0260 - 0x02DF) +// +#define WOW_CTRL 0x0260 //Wake On WLAN Control. +#define PSSTATUS 0x0261 // Power Save Status. +#define PSSWITCH 0x0262 // Power Save Switch. +#define MIMOPS_WAIT_PERIOD 0x0263 +#define LPNAV_CTRL 0x0264 +#define WFM0 0x0270 // Wakeup Frame Mask. +#define WFM1 0x0280 // +#define WFM2 0x0290 // +#define WFM3 0x02A0 // +#define WFM4 0x02B0 // +#define WFM5 0x02C0 // FW Control register. +#define WFCRC 0x02D0 // Wakeup Frame CRC. +#define RPWM 0x02DC // Host Request Power Mode. +#define CPWM 0x02DD // Current Power Mode. +#define FW_RPT_REG 0x02c4 + +// +// 11. General Purpose Registers (Offset: 0x02E0 - 0x02FF) +// +#define PSTIME 0x02E0 // Power Save Timer Register +#define TIMER0 0x02E4 // +#define TIMER1 0x02E8 // +#define GPIO_CTRL 0x02EC // GPIO Control Register +#define GPIO_IN 0x02EC // GPIO pins input value +#define GPIO_OUT 0x02ED // GPIO pins output value +#define GPIO_IO_SEL 0x02EE // GPIO pins output enable when a bit is set to "1"; otherwise, input is configured. +#define GPIO_MOD 0x02EF // +#define GPIO_INTCTRL 0x02F0 // GPIO Interrupt Control Register[7:0] +#define MAC_PINMUX_CFG 0x02F1 // MAC PINMUX Configuration Reg[7:0] +#define LEDCFG 0x02F2 // System PINMUX Configuration Reg[7:0] +#define PHY_REG 0x02F3 // RPT: PHY REG Access Report Reg[7:0] +#define PHY_REG_DATA 0x02F4 // PHY REG Read DATA Register [31:0] +#define EFUSE_CLK 0x02F8 // CTRL: E-FUSE Clock Control Reg[7:0] +//#define GPIO_INTCTRL 0x02F9 // GPIO Interrupt Control Register[7:0] + +// +// 12. Host Interrupt Status Registers (Offset: 0x0300 - 0x030F) +// +#define IMR 0x0300 // Interrupt Mask Register +#define ISR 0x0308 // Interrupt Status Register + +// +// 13. Test Mode and Debug Control Registers (Offset: 0x0310 - 0x034F) +// +#define DBG_PORT_SWITCH 0x003A +#define BIST 0x0310 // Bist reg definition +#define DBS 0x0314 // Debug Select ??? +#define CPUINST 0x0318 // CPU Instruction Read Register +#define CPUCAUSE 0x031C // CPU Cause Register +#define LBUS_ERR_ADDR 0x0320 // Lexra Bus Error Address Register +#define LBUS_ERR_CMD 0x0324 // Lexra Bus Error Command Register +#define LBUS_ERR_DATA_L 0x0328 // Lexra Bus Error Data Low DW Register +#define LBUS_ERR_DATA_H 0x032C // +#define LX_EXCEPTION_ADDR 0x0330 // Lexra Bus Exception Address Register +#define WDG_CTRL 0x0334 // Watch Dog Control Register +#define INTMTU 0x0338 // Interrupt Mitigation Time Unit Reg +#define INTM 0x033A // Interrupt Mitigation Register +#define FDLOCKTURN0 0x033C // FW/DRV Lock Turn 0 Register +#define FDLOCKTURN1 0x033D // FW/DRV Lock Turn 1 Register +#define TRXPKTBUF_DBG_DATA 0x0340 // TRX Packet Buffer Debug Data Register +#define TRXPKTBUF_DBG_CTRL 0x0348 // TRX Packet Buffer Debug Control Reg +#define DPLL 0x034A // DPLL Monitor Register [15:0] +#define CBUS_ERR_ADDR 0x0350 // CPU Bus Error Address Register +#define CBUS_ERR_CMD 0x0354 // CPU Bus Error Command Register +#define CBUS_ERR_DATA_L 0x0358 // CPU Bus Error Data Low DW Register +#define CBUS_ERR_DATA_H 0x035C // +#define USB_SIE_INTF_ADDR 0x0360 // USB SIE Access Interface Address Reg +#define USB_SIE_INTF_WD 0x0361 // USB SIE Access Interface WData Reg +#define USB_SIE_INTF_RD 0x0362 // USB SIE Access Interface RData Reg +#define USB_SIE_INTF_CTRL 0x0363 // USB SIE Access Interface Control Reg + +// Boundary is 0x37F + +// +// 14. PCIE config register (Offset 0x500-) +// +#define TPPoll 0x0500 // Transmit Polling +#define PM_CTRL 0x0502 // PCIE power management control Register +#define PCIF 0x0503 // PCI Function Register 0x0009h~0x000bh + +#define THPDA 0x0514 // Transmit High Priority Desc Addr +#define TMDA 0x0518 // Transmit Management Desc Addr +#define TCDA 0x051C // Transmit Command Desc Addr +#define HDA 0x0520 // HCCA Desc Addr +#define TVODA 0x0524 // Transmit VO Desc Addr +#define TVIDA 0x0528 // Transmit VI Desc Addr +#define TBEDA 0x052C // Transmit BE Desc Addr +#define TBKDA 0x0530 // Transmit BK Desc Addr +#define TBDA 0x0534 // Transmit Beacon Desc Addr +#define RCDA 0x0538 // Receive Command Desc Addr +#define RDSA 0x053C // Receive Desc Starting Addr +#define DBI_WDATA 0x0540 // DBI write data Register +#define DBI_RDATA 0x0544 // DBI read data Register +#define DBI_CTRL 0x0548 // PCIE DBI control Register +#define MDIO_DATA 0x0550 // PCIE MDIO data Register +#define MDIO_CTRL 0x0554 // PCIE MDIO control Register +#define PCI_RPWM 0x0561 // PCIE RPWM register +#define PCI_CPWM 0x0563 // Current Power Mode. + +// +// Config register (Offset 0x800-) +// +#define PHY_CCA 0x803 // CCA related register + +//============================================================================ +// 8192S USB specific Regsiter Offset and Content definition, +// 2008.08.28, added by Roger. +//============================================================================ +// Rx Aggregation time-out reg. +#define USB_RX_AGG_TIMEOUT 0xFE5B + +// Firware reserved Tx page control. +#define FW_OFFLOAD_EN BIT7 + +// Min Spacing related settings. +#define MAX_MSS_DENSITY 0x13 +#define MAX_MSS_DENSITY_2T 0x13 +#define MAX_MSS_DENSITY_1T 0x0A + +// Rx DMA Control related settings +#define RXDMA_AGG_EN BIT7 + +// USB Rx Aggregation TimeOut settings +#define RXDMA_AGG_TIMEOUT_DISABLE 0x00 +#define RXDMA_AGG_TIMEOUT_17MS 0x01 +#define RXDMA_AGG_TIMEOUT_17_2_MS 0x02 +#define RXDMA_AGG_TIMEOUT_17_4_MS 0x04 +#define RXDMA_AGG_TIMEOUT_17_10_MS 0x0A +// USB RPWM register +#define USB_RPWM 0xFE58 + +//FIXLZM SVN_BRACH NOT MOD HERE, IF MOD RX IS LITTLE LOW +//#if ((HAL_CODE_BASE == RTL8192_S) && (DEV_BUS_TYPE==PCI_INTERFACE)) +//#define RPWM PCI_RPWM +//#elif ((HAL_CODE_BASE == RTL8192_S) && (DEV_BUS_TYPE==USB_INTERFACE)) +//#define RPWM USB_RPWM +//#endif + + +//============================================================================ +// 8190 Regsiter offset definition +//============================================================================ +#if 1 // Delete the register later +#define AFR 0x010 // AutoLoad Function Register +#define BCN_TCFG 0x062 // Beacon Time Configuration +#define RATR0 0x320 // Rate Adaptive Table register1 +#endif +// TODO: Remove unused register, We must declare backward compatiable +//Undefined register set in 8192S. 0x320/350 DW is useless +#define UnusedRegister 0x0320 +#define PSR UnusedRegister // Page Select Register +//Security Related +#define DCAM UnusedRegister // Debug CAM Interface +//PHY Configuration related +#define BBAddr UnusedRegister // Phy register address register +#define PhyDataR UnusedRegister // Phy register data read +#define UFWP UnusedRegister + + +//============================================================================ +// 8192S Regsiter Bit and Content definition +//============================================================================ + +// +// 1. System Configuration Registers (Offset: 0x0000 - 0x003F) +// +//---------------------------------------------------------------------------- +// 8192S SYS_ISO_CTRL bits (Offset 0x0, 16bit) +//---------------------------------------------------------------------------- +#define ISO_MD2PP BIT0 // MACTOP/BB/PCIe Digital to Power On. +#define ISO_PA2PCIE BIT3 // PCIe Analog 1.2V to PCIe 3.3V +#define ISO_PLL2MD BIT4 // AFE PLL to MACTOP/BB/PCIe Digital. +#define ISO_PWC_DV2RP BIT11 // Digital Vdd to Retention Path +#define ISO_PWC_RV2RP BIT12 // LPLDOR12 to Retenrion Path, 1: isolation, 0: attach. + +//---------------------------------------------------------------------------- +// 8192S SYS_FUNC_EN bits (Offset 0x2, 16bit) +//---------------------------------------------------------------------------- +#define FEN_MREGEN BIT15 // MAC I/O Registers Enable. +#define FEN_DCORE BIT11 // Enable Core Digital. +#define FEN_CPUEN BIT10 // Enable CPU Core Digital. +// 8192S PMC_FSM bits (Offset 0x4, 32bit) +//---------------------------------------------------------------------------- +#define PAD_HWPD_IDN BIT22 // HWPDN PAD status Indicator + +//---------------------------------------------------------------------------- + +//---------------------------------------------------------------------------- +// 8192S SYS_CLKR bits (Offset 0x8, 16bit) +//---------------------------------------------------------------------------- +#define SYS_CLKSEL_80M BIT0 // System Clock 80MHz +#define SYS_PS_CLKSEL BIT1 //System power save clock select. +#define SYS_CPU_CLKSEL BIT2 // System Clock select, 1: AFE source, 0: System clock(L-Bus) +#define SYS_MAC_CLK_EN BIT11 // MAC Clock Enable. +#define SYS_SWHW_SEL BIT14 // Load done, control path seitch. +#define SYS_FWHW_SEL BIT15 // Sleep exit, control path swith. + + +//---------------------------------------------------------------------------- +// 8192S Cmd9346CR bits (Offset 0xA, 16bit) +//---------------------------------------------------------------------------- +#define CmdEEPROM_En BIT5 // EEPROM enable when set 1 +#define CmdEERPOMSEL BIT4 // System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346 +#define Cmd9346CR_9356SEL BIT4 +#define AutoLoadEEPROM (CmdEEPROM_En|CmdEERPOMSEL) +#define AutoLoadEFUSE CmdEEPROM_En + + +//---------------------------------------------------------------------------- +// 8192S AFE_MISC bits AFE Misc (Offset 0x10, 8bits) +//---------------------------------------------------------------------------- +#define AFE_MBEN BIT1 // Enable AFE Macro Block's Mbias. +#define AFE_BGEN BIT0 // Enable AFE Macro Block's Bandgap. + +//---------------------------------------------------------------------------- +// 8192S SPS1_CTRL bits (Offset 0x18-1E, 56bits) +//---------------------------------------------------------------------------- +#define SPS1_SWEN BIT1 // Enable vsps18 SW Macro Block. +#define SPS1_LDEN BIT0 // Enable VSPS12 LDO Macro block. + +//---------------------------------------------------------------------------- +// 8192S RF_CTRL bits (Offset 0x1F, 8bits) +//---------------------------------------------------------------------------- +#define RF_EN BIT0 // Enable RF module. +#define RF_RSTB BIT1 // Reset RF module. +#define RF_SDMRSTB BIT2 // Reset RF SDM module. + +//---------------------------------------------------------------------------- +// 8192S LDOA15_CTRL bits (Offset 0x20, 8bits) +//---------------------------------------------------------------------------- +#define LDA15_EN BIT0 // Enable LDOA15 Macro Block + +//---------------------------------------------------------------------------- +// 8192S LDOV12D_CTRL bits (Offset 0x21, 8bits) +//---------------------------------------------------------------------------- +#define LDV12_EN BIT0 // Enable LDOVD12 Macro Block +#define LDV12_SDBY BIT1 // LDOVD12 standby mode + +//---------------------------------------------------------------------------- +// 8192S AFE_XTAL_CTRL bits AFE Crystal Control. (Offset 0x26,16bits) +//---------------------------------------------------------------------------- +#define XTAL_GATE_AFE BIT10 +// Gated Control. 1: AFE Clock source gated, 0: Clock enable. + +//---------------------------------------------------------------------------- +// 8192S AFE_PLL_CTRL bits System Function Enable (Offset 0x28,64bits) +//---------------------------------------------------------------------------- +#define APLL_EN BIT0 // Enable AFE PLL Macro Block. + +// Find which card bus type +#define AFR_CardBEn BIT0 +#define AFR_CLKRUN_SEL BIT1 +#define AFR_FuncRegEn BIT2 + +// +// 2. Command Control Registers (Offset: 0x0040 - 0x004F) +// +//---------------------------------------------------------------------------- +// 8192S (CMD) command register bits (Offset 0x40, 16 bits) +//---------------------------------------------------------------------------- +#define APSDOFF_STATUS BIT15 // +#define APSDOFF BIT14 // +#define BBRSTn BIT13 //Enable OFDM/CCK +#define BB_GLB_RSTn BIT12 //Enable BB +#define SCHEDULE_EN BIT10 //Enable MAC scheduler +#define MACRXEN BIT9 // +#define MACTXEN BIT8 // +#define DDMA_EN BIT7 //FW off load function enable +#define FW2HW_EN BIT6 //MAC every module reset as below +#define RXDMA_EN BIT5 // +#define TXDMA_EN BIT4 // +#define HCI_RXDMA_EN BIT3 // +#define HCI_TXDMA_EN BIT2 // + +//---------------------------------------------------------------------------- +// 8192S (TXPAUSE) transmission pause (Offset 0x42, 8 bits) +//---------------------------------------------------------------------------- +#define StopHCCA BIT6 +#define StopHigh BIT5 +#define StopMgt BIT4 +#define StopVO BIT3 +#define StopVI BIT2 +#define StopBE BIT1 +#define StopBK BIT0 + +//---------------------------------------------------------------------------- +// 8192S (LBKMD) LoopBack Mode Select (Offset 0x43, 8 bits) +//---------------------------------------------------------------------------- +// +// [3] no buffer, 1: no delay, 0: delay; [2] dmalbk, [1] no_txphy, [0] diglbk. +// 0000: Normal +// 1011: MAC loopback (involving CPU) +// 0011: MAC Delay Loopback +// 0001: PHY loopback (not yet implemented) +// 0111: DMA loopback (only uses TxPktBuffer and DMA engine) +// All other combinations are reserved. +// Default: 0000b. +// +#define LBK_NORMAL 0x00 +#define LBK_MAC_LB (BIT0|BIT1|BIT3) +#define LBK_MAC_DLB (BIT0|BIT1) +#define LBK_DMA_LB (BIT0|BIT1|BIT2) + +//---------------------------------------------------------------------------- +// 8192S (TCR) transmission Configuration Register (Offset 0x44, 32 bits) +//---------------------------------------------------------------------------- +#define TCP_OFDL_EN BIT25 //For CE packet conversion +#define HWPC_TX_EN BIT24 //"" +#define TXDMAPRE2FULL BIT23 //TXDMA enable pre2full sync +#define DISCW BIT20 //CW disable +#define TCRICV BIT19 //Append ICV or not +#define CfendForm BIT17 //AP mode +#define TCRCRC BIT16 //Append CRC32 +#define FAKE_IMEM_EN BIT15 // +#define TSFRST BIT9 // +#define TSFEN BIT8 // +// For TCR FW download ready --> write by FW Bit0-7 must all one +#define FWALLRDY (BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6|BIT7) +#define FWRDY BIT7 +#define BASECHG BIT6 +#define IMEM BIT5 +#define DMEM_CODE_DONE BIT4 +#define EXT_IMEM_CHK_RPT BIT3 +#define EXT_IMEM_CODE_DONE BIT2 +#define IMEM_CHK_RPT BIT1 +#define IMEM_CODE_DONE BIT0 +// Copy fomr 92SU definition +#define IMEM_CODE_DONE BIT0 +#define IMEM_CHK_RPT BIT1 +#define EMEM_CODE_DONE BIT2 +#define EMEM_CHK_RPT BIT3 +#define DMEM_CODE_DONE BIT4 +#define IMEM_RDY BIT5 +#define BASECHG BIT6 +#define FWRDY BIT7 +#define LOAD_FW_READY (IMEM_CODE_DONE|IMEM_CHK_RPT|EMEM_CODE_DONE|\ + EMEM_CHK_RPT|DMEM_CODE_DONE|IMEM_RDY|BASECHG|\ + FWRDY) +#define TCR_TSFEN BIT8 // TSF function on or off. +#define TCR_TSFRST BIT9 // Reset TSF function to zero. +#define TCR_FAKE_IMEM_EN BIT15 +#define TCR_CRC BIT16 +#define TCR_ICV BIT19 // Integrity Check Value. +#define TCR_DISCW BIT20 // Disable Contention Windows Backoff. +#define TCR_HWPC_TX_EN BIT24 +#define TCR_TCP_OFDL_EN BIT25 +#define TXDMA_INIT_VALUE (IMEM_CHK_RPT|EXT_IMEM_CHK_RPT) +//---------------------------------------------------------------------------- +// 8192S (RCR) Receive Configuration Register (Offset 0x48, 32 bits) +//---------------------------------------------------------------------------- +#define RCR_APPFCS BIT31 //WMAC append FCS after pauload +#define RCR_DIS_ENC_2BYTE BIT30 //HW encrypt 2 or 1 byte mode +#define RCR_DIS_AES_2BYTE BIT29 // +#define RCR_HTC_LOC_CTRL BIT28 //MFC<--HTC=1 MFC-->HTC=0 +#define RCR_ENMBID BIT27 //Enable Multiple BssId. +#define RCR_RX_TCPOFDL_EN BIT26 // +#define RCR_APP_PHYST_RXFF BIT25 // +#define RCR_APP_PHYST_STAFF BIT24 // +#define RCR_CBSSID BIT23 //Accept BSSID match packet +#define RCR_APWRMGT BIT22 //Accept power management packet +#define RCR_ADD3 BIT21 //Accept address 3 match packet +#define RCR_AMF BIT20 //Accept management type frame +#define RCR_ACF BIT19 //Accept control type frame +#define RCR_ADF BIT18 //Accept data type frame +#define RCR_APP_MIC BIT17 // +#define RCR_APP_ICV BIT16 // +#define RCR_RXFTH BIT13 //Rx FIFO Threshold Bot 13 - 15 +#define RCR_AICV BIT12 //Accept ICV error packet +#define RCR_RXDESC_LK_EN BIT11 //Accept to update rx desc length +#define RCR_APP_BA_SSN BIT6 //Accept BA SSN +#define RCR_ACRC32 BIT5 //Accept CRC32 error packet +#define RCR_RXSHFT_EN BIT4 //Accept broadcast packet +#define RCR_AB BIT3 //Accept broadcast packet +#define RCR_AM BIT2 //Accept multicast packet +#define RCR_APM BIT1 //Accept physical match packet +#define RCR_AAP BIT0 //Accept all unicast packet +#define RCR_MXDMA_OFFSET 8 +#define RCR_FIFO_OFFSET 13 + +//in 92U FIXLZM +//#ifdef RTL8192U +#define RCR_ONLYERLPKT BIT31 // Early Receiving based on Packet Size. +#define RCR_ENCS2 BIT30 // Enable Carrier Sense Detection Method 2 +#define RCR_ENCS1 BIT29 // Enable Carrier Sense Detection Method 1 +#define RCR_ACKTXBW (BIT24|BIT25) // TXBW Setting of ACK frames +//#endif +//---------------------------------------------------------------------------- +// 8192S (MSR) Media Status Register (Offset 0x4C, 8 bits) +//---------------------------------------------------------------------------- +/* +Network Type +00: No link +01: Link in ad hoc network +10: Link in infrastructure network +11: AP mode +Default: 00b. +*/ +#define MSR_NOLINK 0x00 +#define MSR_ADHOC 0x01 +#define MSR_INFRA 0x02 +#define MSR_AP 0x03 + +//---------------------------------------------------------------------------- +// 8192S (SYSF_CFG) system Fucntion Config Reg (Offset 0x4D, 8 bits) +//---------------------------------------------------------------------------- +#define ENUART BIT7 +#define ENJTAG BIT3 +#define BTMODE (BIT2|BIT1) +#define ENBT BIT0 + +//---------------------------------------------------------------------------- +// 8192S (MBIDCTRL) MBSSID Control Register (Offset 0x4F, 8 bits) +//---------------------------------------------------------------------------- +#define ENMBID BIT7 +#define BCNUM (BIT6|BIT5|BIT4) + +// +// 3. MACID Setting Registers (Offset: 0x0050 - 0x007F) +// + +// +// 4. Timing Control Registers (Offset: 0x0080 - 0x009F) +// +//---------------------------------------------------------------------------- +// 8192S (USTIME) US Time Tunning Register (Offset 0x8A, 16 bits) +//---------------------------------------------------------------------------- +#define USTIME_EDCA 0xFF00 +#define USTIME_TSF 0x00FF + +//---------------------------------------------------------------------------- +// 8192S (SIFS_CCK/OFDM) US Time Tunning Register (Offset 0x8C/8E,16 bits) +//---------------------------------------------------------------------------- +#define SIFS_TRX 0xFF00 +#define SIFS_CTX 0x00FF + +//---------------------------------------------------------------------------- +// 8192S (DRVERLYINT) Driver Early Interrupt Reg (Offset 0x98, 16bit) +//---------------------------------------------------------------------------- +#define ENSWBCN BIT15 +#define DRVERLY_TU 0x0FF0 +#define DRVERLY_US 0x000F +#define BCN_TCFG_CW_SHIFT 8 +#define BCN_TCFG_IFS 0 + +// +// 5. FIFO Control Registers (Offset: 0x00A0 - 0x015F) +// + +// +// 6. Adaptive Control Registers (Offset: 0x0160 - 0x01CF) +// +//---------------------------------------------------------------------------- +// 8192S Response Rate Set Register (offset 0x181, 24bits) +//---------------------------------------------------------------------------- +#define RRSR_RSC_OFFSET 21 +#define RRSR_SHORT_OFFSET 23 +#define RRSR_RSC_BW_40M 0x600000 +#define RRSR_RSC_UPSUBCHNL 0x400000 +#define RRSR_RSC_LOWSUBCHNL 0x200000 +#define RRSR_SHORT 0x800000 +#define RRSR_1M BIT0 +#define RRSR_2M BIT1 +#define RRSR_5_5M BIT2 +#define RRSR_11M BIT3 +#define RRSR_6M BIT4 +#define RRSR_9M BIT5 +#define RRSR_12M BIT6 +#define RRSR_18M BIT7 +#define RRSR_24M BIT8 +#define RRSR_36M BIT9 +#define RRSR_48M BIT10 +#define RRSR_54M BIT11 +#define RRSR_MCS0 BIT12 +#define RRSR_MCS1 BIT13 +#define RRSR_MCS2 BIT14 +#define RRSR_MCS3 BIT15 +#define RRSR_MCS4 BIT16 +#define RRSR_MCS5 BIT17 +#define RRSR_MCS6 BIT18 +#define RRSR_MCS7 BIT19 +#define BRSR_AckShortPmb BIT23 + +#define RRSR_RSC_UPSUBCHANL 0x200000 +// CCK ACK: use Short Preamble or not + +//---------------------------------------------------------------------------- +// 8192S Rate Definition +//---------------------------------------------------------------------------- +//CCK +#define RATR_1M 0x00000001 +#define RATR_2M 0x00000002 +#define RATR_55M 0x00000004 +#define RATR_11M 0x00000008 +//OFDM +#define RATR_6M 0x00000010 +#define RATR_9M 0x00000020 +#define RATR_12M 0x00000040 +#define RATR_18M 0x00000080 +#define RATR_24M 0x00000100 +#define RATR_36M 0x00000200 +#define RATR_48M 0x00000400 +#define RATR_54M 0x00000800 +//MCS 1 Spatial Stream +#define RATR_MCS0 0x00001000 +#define RATR_MCS1 0x00002000 +#define RATR_MCS2 0x00004000 +#define RATR_MCS3 0x00008000 +#define RATR_MCS4 0x00010000 +#define RATR_MCS5 0x00020000 +#define RATR_MCS6 0x00040000 +#define RATR_MCS7 0x00080000 +//MCS 2 Spatial Stream +#define RATR_MCS8 0x00100000 +#define RATR_MCS9 0x00200000 +#define RATR_MCS10 0x00400000 +#define RATR_MCS11 0x00800000 +#define RATR_MCS12 0x01000000 +#define RATR_MCS13 0x02000000 +#define RATR_MCS14 0x04000000 +#define RATR_MCS15 0x08000000 +// ALL CCK Rate +#define RATE_ALL_CCK RATR_1M|RATR_2M|RATR_55M|RATR_11M +#define RATE_ALL_OFDM_AG RATR_6M|RATR_9M|RATR_12M|RATR_18M|RATR_24M|\ + RATR_36M|RATR_48M|RATR_54M +#define RATE_ALL_OFDM_1SS RATR_MCS0|RATR_MCS1|RATR_MCS2|RATR_MCS3 |\ + RATR_MCS4|RATR_MCS5|RATR_MCS6 |RATR_MCS7 +#define RATE_ALL_OFDM_2SS RATR_MCS8|RATR_MCS9 |RATR_MCS10|RATR_MCS11|\ + RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15 + +// +// 7. EDCA Setting Registers (Offset: 0x01D0 - 0x01FF) +// +//---------------------------------------------------------------------------- +// 8192S EDCA Setting (offset 0x1D0-1DF, 4DW VO/VI/BE/BK) +//---------------------------------------------------------------------------- +#define AC_PARAM_TXOP_LIMIT_OFFSET 16 +#define AC_PARAM_ECW_MAX_OFFSET 12 +#define AC_PARAM_ECW_MIN_OFFSET 8 +#define AC_PARAM_AIFS_OFFSET 0 + +//---------------------------------------------------------------------------- +// 8192S AcmHwCtrl bits (offset 0x1E7, 1 byte) +//---------------------------------------------------------------------------- +#define AcmHw_HwEn BIT0 +#define AcmHw_BeqEn BIT1 +#define AcmHw_ViqEn BIT2 +#define AcmHw_VoqEn BIT3 +#define AcmHw_BeqStatus BIT4 +#define AcmHw_ViqStatus BIT5 +#define AcmHw_VoqStatus BIT6 + +//---------------------------------------------------------------------------- +// 8192S Retry Limit (Offset 0x1F4, 16bit) +//---------------------------------------------------------------------------- +#define RETRY_LIMIT_SHORT_SHIFT 8 +#define RETRY_LIMIT_LONG_SHIFT 0 + +// +// 8. WMAC, BA and CCX related Register. (Offset: 0x0200 - 0x023F) +// +//---------------------------------------------------------------------------- +// 8192S NAV_CTRL bits (Offset 0x200, 24bit) +//---------------------------------------------------------------------------- +#define NAV_UPPER_EN BIT16 +#define NAV_UPPER 0xFF00 +#define NAV_RTSRST 0xFF +//---------------------------------------------------------------------------- +// 8192S BW_OPMODE bits (Offset 0x203, 8bit) +//---------------------------------------------------------------------------- +#define BW_OPMODE_20MHZ BIT2 +#define BW_OPMODE_5G BIT1 +#define BW_OPMODE_11J BIT0 +//---------------------------------------------------------------------------- +// 8192S BW_OPMODE bits (Offset 0x230, 4 Byte) +//---------------------------------------------------------------------------- +#define RXERR_RPT_RST BIT27 // Write "one" to set the counter to zero. +// RXERR_RPT_SEL +#define RXERR_OFDM_PPDU 0 +#define RXERR_OFDM_FALSE_ALARM 1 +#define RXERR_OFDM_MPDU_OK 2 +#define RXERR_OFDM_MPDU_FAIL 3 +#define RXERR_CCK_PPDU 4 +#define RXERR_CCK_FALSE_ALARM 5 +#define RXERR_CCK_MPDU_OK 6 +#define RXERR_CCK_MPDU_FAIL 7 +#define RXERR_HT_PPDU 8 +#define RXERR_HT_FALSE_ALARM 9 +#define RXERR_HT_MPDU_TOTAL 10 +#define RXERR_HT_MPDU_OK 11 +#define RXERR_HT_MPDU_FAIL 12 +#define RXERR_RX_FULL_DROP 15 + +// +// 9. Security Control Registers (Offset: 0x0240 - 0x025F) +// +//---------------------------------------------------------------------------- +// 8192S RWCAM CAM Command Register (offset 0x240, 4 byte) +//---------------------------------------------------------------------------- +#define CAM_CM_SecCAMPolling BIT31 //Security CAM Polling +#define CAM_CM_SecCAMClr BIT30 //Clear all bits in CAM +#define CAM_CM_SecCAMWE BIT16 //Security CAM enable +#define CAM_ADDR 0xFF //CAM Address Offset + +//---------------------------------------------------------------------------- +// 8192S CAMDBG Debug CAM Register (offset 0x24C, 4 byte) +//---------------------------------------------------------------------------- +#define Dbg_CAM_TXSecCAMInfo BIT31 //Retrieve lastest Tx Info +#define Dbg_CAM_SecKeyFound BIT30 //Security KEY Found + + +//---------------------------------------------------------------------------- +// 8192S SECR Security Configuration Register (offset 0x250, 1 byte) +//---------------------------------------------------------------------------- +#define SCR_TxUseDK BIT0 //Force Tx Use Default Key +#define SCR_RxUseDK BIT1 //Force Rx Use Default Key +#define SCR_TxEncEnable BIT2 //Enable Tx Encryption +#define SCR_RxDecEnable BIT3 //Enable Rx Decryption +#define SCR_SKByA2 BIT4 //Search kEY BY A2 +#define SCR_NoSKMC BIT5 //No Key Search Multicast +//---------------------------------------------------------------------------- +// 8192S CAM Config Setting (offset 0x250, 1 byte) +//---------------------------------------------------------------------------- +#define CAM_VALID BIT15 +#define CAM_NOTVALID 0x0000 +#define CAM_USEDK BIT5 + +#define CAM_NONE 0x0 +#define CAM_WEP40 0x01 +#define CAM_TKIP 0x02 +#define CAM_AES 0x04 +#define CAM_WEP104 0x05 + +#define TOTAL_CAM_ENTRY 32 + +#define CAM_CONFIG_USEDK TRUE +#define CAM_CONFIG_NO_USEDK FALSE + +#define CAM_WRITE BIT16 +#define CAM_READ 0x00000000 +#define CAM_POLLINIG BIT31 + +#define SCR_UseDK 0x01 +#define SCR_TxSecEnable 0x02 +#define SCR_RxSecEnable 0x04 + +// +// 10. Power Save Control Registers (Offset: 0x0260 - 0x02DF) +// +#define WOW_PMEN BIT0 // Power management Enable. +#define WOW_WOMEN BIT1 // WoW function on or off. +#define WOW_MAGIC BIT2 // Magic packet +#define WOW_UWF BIT3 // Unicast Wakeup frame. + +// +// 11. General Purpose Registers (Offset: 0x02E0 - 0x02FF) +// 8192S GPIO Config Setting (offset 0x2F1, 1 byte) +//---------------------------------------------------------------------------- +#define GPIOMUX_EN BIT3 // When this bit is set to "1", GPIO PINs will switch to MAC GPIO Function +#define GPIOSEL_GPIO 0 // UART or JTAG or pure GPIO +#define GPIOSEL_PHYDBG 1 // PHYDBG +#define GPIOSEL_BT 2 // BT_coex +#define GPIOSEL_WLANDBG 3 // WLANDBG +#define GPIOSEL_GPIO_MASK ~(BIT0|BIT1) + +//---------------------------------------------------------------------------- + +//---------------------------------------------------------------------------- +// PHY REG Access Report Register definition +//---------------------------------------------------------------------------- +#define HST_RDBUSY BIT0 +#define CPU_WTBUSY BIT1 + +// +// 12. Host Interrupt Status Registers (Offset: 0x0300 - 0x030F) +// +//---------------------------------------------------------------------------- +// 8190 IMR/ISR bits (offset 0xfd, 8bits) +//---------------------------------------------------------------------------- +#define IMR8190_DISABLED 0x0 + +// IMR DW1 Bit 0-31 +#define IMR_CPUERR BIT5 // CPU error interrupt +#define IMR_ATIMEND BIT4 // ATIM Window End Interrupt +#define IMR_TBDOK BIT3 // Transmit Beacon OK Interrupt +#define IMR_TBDER BIT2 // Transmit Beacon Error Interrupt +#define IMR_BCNDMAINT8 BIT1 // Beacon DMA Interrupt 8 +#define IMR_BCNDMAINT7 BIT0 // Beacon DMA Interrupt 7 +// IMR DW0 Bit 0-31 + +#define IMR_BCNDMAINT6 BIT31 // Beacon DMA Interrupt 6 +#define IMR_BCNDMAINT5 BIT30 // Beacon DMA Interrupt 5 +#define IMR_BCNDMAINT4 BIT29 // Beacon DMA Interrupt 4 +#define IMR_BCNDMAINT3 BIT28 // Beacon DMA Interrupt 3 +#define IMR_BCNDMAINT2 BIT27 // Beacon DMA Interrupt 2 +#define IMR_BCNDMAINT1 BIT26 // Beacon DMA Interrupt 1 +#define IMR_BCNDOK8 BIT25 // Beacon Queue DMA OK Interrup 8 +#define IMR_BCNDOK7 BIT24 // Beacon Queue DMA OK Interrup 7 +#define IMR_BCNDOK6 BIT23 // Beacon Queue DMA OK Interrup 6 +#define IMR_BCNDOK5 BIT22 // Beacon Queue DMA OK Interrup 5 +#define IMR_BCNDOK4 BIT21 // Beacon Queue DMA OK Interrup 4 +#define IMR_BCNDOK3 BIT20 // Beacon Queue DMA OK Interrup 3 +#define IMR_BCNDOK2 BIT19 // Beacon Queue DMA OK Interrup 2 +#define IMR_BCNDOK1 BIT18 // Beacon Queue DMA OK Interrup 1 +#define IMR_TIMEOUT2 BIT17 // Timeout interrupt 2 +#define IMR_TIMEOUT1 BIT16 // Timeout interrupt 1 +#define IMR_TXFOVW BIT15 // Transmit FIFO Overflow +#define IMR_PSTIMEOUT BIT14 // Power save time out interrupt +#define IMR_BcnInt BIT13 // Beacon DMA Interrupt 0 +#define IMR_RXFOVW BIT12 // Receive FIFO Overflow +#define IMR_RDU BIT11 // Receive Descriptor Unavailable +#define IMR_RXCMDOK BIT10 // Receive Command Packet OK +#define IMR_BDOK BIT9 // Beacon Queue DMA OK Interrup +#define IMR_HIGHDOK BIT8 // High Queue DMA OK Interrupt +#define IMR_COMDOK BIT7 // Command Queue DMA OK Interrupt +#define IMR_MGNTDOK BIT6 // Management Queue DMA OK Interrupt +#define IMR_HCCADOK BIT5 // HCCA Queue DMA OK Interrupt +#define IMR_BKDOK BIT4 // AC_BK DMA OK Interrupt +#define IMR_BEDOK BIT3 // AC_BE DMA OK Interrupt +#define IMR_VIDOK BIT2 // AC_VI DMA OK Interrupt +#define IMR_VODOK BIT1 // AC_VO DMA Interrupt +#define IMR_ROK BIT0 // Receive DMA OK Interrupt + +// +// 13. Test Mode and Debug Control Registers (Offset: 0x0310 - 0x034F) +// + +// +// 14. PCIE config register (Offset 0x500-) +// +//---------------------------------------------------------------------------- +// 8190 TPPool bits (offset 0xd9, 2 byte) +//---------------------------------------------------------------------------- +#define TPPoll_BKQ BIT0 // BK queue polling +#define TPPoll_BEQ BIT1 // BE queue polling +#define TPPoll_VIQ BIT2 // VI queue polling +#define TPPoll_VOQ BIT3 // VO queue polling +#define TPPoll_BQ BIT4 // Beacon queue polling +#define TPPoll_CQ BIT5 // Command queue polling +#define TPPoll_MQ BIT6 // Management queue polling +#define TPPoll_HQ BIT7 // High queue polling +#define TPPoll_HCCAQ BIT8 // HCCA queue polling +#define TPPoll_StopBK BIT9 // Stop BK queue +#define TPPoll_StopBE BIT10 // Stop BE queue +#define TPPoll_StopVI BIT11 // Stop VI queue +#define TPPoll_StopVO BIT12 // Stop VO queue +#define TPPoll_StopMgt BIT13 // Stop Mgnt queue +#define TPPoll_StopHigh BIT14 // Stop High queue +#define TPPoll_StopHCCA BIT15 // Stop HCCA queue +#define TPPoll_SHIFT 8 // Queue ID mapping + +//---------------------------------------------------------------------------- +// 8192S PCIF (Offset 0x500, 32bit) +//---------------------------------------------------------------------------- +#define MXDMA2_16bytes 0x000 +#define MXDMA2_32bytes 0x001 +#define MXDMA2_64bytes 0x010 +#define MXDMA2_128bytes 0x011 +#define MXDMA2_256bytes 0x100 +#define MXDMA2_512bytes 0x101 +#define MXDMA2_1024bytes 0x110 +#define MXDMA2_NoLimit 0x7 + +#define MULRW_SHIFT 3 +#define MXDMA2_RX_SHIFT 4 +#define MXDMA2_TX_SHIFT 0 + +//---------------------------------------------------------------------------- +// 8190 CCX_COMMAND_REG Setting (offset 0x25A, 1 byte) +//---------------------------------------------------------------------------- +#define CCX_CMD_CLM_ENABLE BIT0 // Enable Channel Load +#define CCX_CMD_NHM_ENABLE BIT1 // Enable Noise Histogram +#define CCX_CMD_FUNCTION_ENABLE BIT8 +// CCX function (Channel Load/RPI/Noise Histogram). +#define CCX_CMD_IGNORE_CCA BIT9 +// Treat CCA period as IDLE time for NHM. +#define CCX_CMD_IGNORE_TXON BIT10 +// Treat TXON period as IDLE time for NHM. +#define CCX_CLM_RESULT_READY BIT16 +// 1: Indicate the result of Channel Load is ready. +#define CCX_NHM_RESULT_READY BIT16 +// 1: Indicate the result of Noise histogram is ready. +#define CCX_CMD_RESET 0x0 +// Clear all the result of CCX measurement and disable the CCX function. + + +//---------------------------------------------------------------------------- +// 8192S EFUSE +//---------------------------------------------------------------------------- +//#define HWSET_MAX_SIZE_92S 128 + + +//---------------------------------------------------------------------------- +// 8192S EEPROM/EFUSE share register definition. +//---------------------------------------------------------------------------- + +#ifdef RTL8192SE +// +// 2008/11/05 MH Redefine EEPROM address for 8192SE +// 92SE/SU EEPROM definition seems not the same!!!!!! +// EEPROM MAP REgister Definition!!!! Please refer to 8192SE EEPROM V0.5 2008/10/21 +// Update to 8192SE EEPROM V0.6 2008/11/11 +// +#define RTL8190_EEPROM_ID 0x8129 // 0-1 +#define EEPROM_HPON 0x02 // LDO settings.2-5 +#define EEPROM_CLK 0x06 // Clock settings.6-7 +#define EEPROM_TESTR 0x08 // SE Test mode.8 + +#define EEPROM_VID 0x0A // SE Vendor ID.A-B +#define EEPROM_DID 0x0C // SE Device ID. C-D +#define EEPROM_SVID 0x0E // SE Vendor ID.E-F +#define EEPROM_SMID 0x10 // SE PCI Subsystem ID. 10-11 + +#define EEPROM_MAC_ADDR 0x12 // SEMAC Address. 12-17 +#define EEPROM_NODE_ADDRESS_BYTE_0 0x12 // MAC address. + +#define EEPROM_PwDiff 0x54 // Difference of gain index between legacy and high throughput OFDM. + +// +// 0x20 - 4B EPHY parameter!!! +// +// +#define EEPROM_TxPowerBase 0x50 // Tx Power of serving station. +#define EEPROM_TxPwIndex_CCK_24G 0x5D // 0x50~0x5D Range = 0~0x24//FIXLZM +#define EEPROM_TxPwIndex_OFDM_24G 0x6B // 0x5E~0x6B Range = 0~0x24//FIXLZM +#define EEPROM_TX_PWR_INDEX_RANGE 28 // CCK and OFDM 14 channel + + +// 2009/01/21 MH Add for SD3 requirement +#define EEPROM_TX_PWR_HT20_DIFF 0x62// HT20 Tx Power Index Difference +#define DEFAULT_HT20_TXPWR_DIFF 2 // HT20<->40 default Tx Power Index Difference +#define EEPROM_TX_PWR_OFDM_DIFF 0x65// OFDM Tx Power Index Difference +#define EEPROM_TX_PWR_BAND_EDGE 0x67// TX Power offset at band-edge channel +#define TX_PWR_BAND_EDGE_CHK 0x6D// Check if band-edge scheme is enabled + +// Oly old EEPROM format support the definition============================= +// +#define EEPROM_TxPwIndex_CCK_24G 0x5D // 0x50~0x5D Range = 0~0x24 +#define EEPROM_TxPwIndex_OFDM_24G 0x6B // 0x5E~0x6B Range = 0~0x24 +#define EEPROM_HT2T_CH1_A 0x6c //HT 2T path A channel 1 Power Index. +#define EEPROM_HT2T_CH7_A 0x6d //HT 2T path A channel 7 Power Index. +#define EEPROM_HT2T_CH13_A 0x6e //HT 2T path A channel 13 Power Index. +#define EEPROM_HT2T_CH1_B 0x6f //HT 2T path B channel 1 Power Index. +#define EEPROM_HT2T_CH7_B 0x70 //HT 2T path B channel 7 Power Index. +#define EEPROM_HT2T_CH13_B 0x71 //HT 2T path B channel 13 Power Index. +// +#define EEPROM_TSSI_A 0x74 //TSSI value of path A. +#define EEPROM_TSSI_B 0x75 //TSSI value of path B. +// +#define EEPROM_RFInd_PowerDiff 0x76 +#define EEPROM_Default_LegacyHTTxPowerDiff 0x3 +// +#define EEPROM_ThermalMeter 0x77 // Thermal meter default value. +#define EEPROM_CrystalCap 0x79 // Crystal Cap. +#define EEPROM_ChannelPlan 0x7B // Map of supported channels. +#define EEPROM_Version 0x7C // The EEPROM content version +#define EEPROM_CustomID 0x7A +#define EEPROM_BoardType 0x7E +// 0: 2x2 Green RTL8192GE miniCard (QFN68) +// 1: 1x2 RTL8191SE miniCard (QFN64) +// 2: 2x2 RTL8192SE miniCard (QFN68) +// 3: 1x2 RTL8191SR minicCard(QFN64) + +// +// Default Value for EEPROM or EFUSE!!! +// +#define EEPROM_Default_TSSI 0x0 +#define EEPROM_Default_TxPowerDiff 0x0 +#define EEPROM_Default_CrystalCap 0x5 +#define EEPROM_Default_BoardType 0x02 // Default: 2X2, RTL8192SE(QFPN68) +#define EEPROM_Default_TxPower 0x1010 +#define EEPROM_Default_HT2T_TxPwr 0x10 + +#ifdef EEPROM_OLD_FORMAT_SUPPORT +#define EEPROM_Default_TxPowerBase 0x0 +#define EEPROM_Default_ThermalMeter 0x12 +#define EEPROM_Default_PwDiff 0x4 +#else +#define EEPROM_Default_LegacyHTTxPowerDiff 0x3 +#define EEPROM_Default_ThermalMeter 0x12 +#define EEPROM_Default_AntTxPowerDiff 0x0 +#define EEPROM_Default_TxPwDiff_CrystalCap 0x5 +#define EEPROM_Default_TxPowerLevel 0x22 +#endif + +#define EEPROM_CHANNEL_PLAN_FCC 0x0 +#define EEPROM_CHANNEL_PLAN_IC 0x1 +#define EEPROM_CHANNEL_PLAN_ETSI 0x2 +#define EEPROM_CHANNEL_PLAN_SPAIN 0x3 +#define EEPROM_CHANNEL_PLAN_FRANCE 0x4 +#define EEPROM_CHANNEL_PLAN_MKK 0x5 +#define EEPROM_CHANNEL_PLAN_MKK1 0x6 +#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7 +#define EEPROM_CHANNEL_PLAN_TELEC 0x8 +#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9 +#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA +#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 + + +#define EEPROM_CID_DEFAULT 0x0 +#define EEPROM_CID_TOSHIBA 0x4 +#else +//---------------------------------------------------------------------------- +// 8192S EEROM and Compatible E-Fuse definition. Added by Roger, 2008.10.21. +//---------------------------------------------------------------------------- +#define RTL8190_EEPROM_ID 0x8129 +#define EEPROM_HPON 0x02 // LDO settings. +#define EEPROM_VID 0x08 // USB Vendor ID. +#define EEPROM_PID 0x0A // USB Product ID. +#define EEPROM_USB_OPTIONAL 0x0C // For optional function. +#define EEPROM_USB_PHY_PARA1 0x0D // For fine tune USB PHY. +#define EEPROM_NODE_ADDRESS_BYTE_0 0x12 // MAC address. +#define EEPROM_TxPowerDiff 0x1F + +#define EEPROM_Version 0x50 +#define EEPROM_ChannelPlan 0x51 // Map of supported channels. +#define EEPROM_CustomID 0x52 +#define EEPROM_SubCustomID 0x53 // Reserved for customer use. + + + // <Roger_Notes> The followin are for different version of EEPROM contents purpose. 2008.11.22. +#ifdef EEPROM_OLD_FORMAT_SUPPORT +#define EEPROM_PwDiff 0x54 // Difference of gain index between legacy and high throughput OFDM. +#define EEPROM_ThermalMeter 0x55 // Thermal meter default value. +#define EEPROM_Reserved 0x56 // Reserved. +#define EEPROM_CrystalCap 0x57 // Crystal Cap. +#define EEPROM_TxPowerBase 0x58 // Tx Power of serving station. +#define EEPROM_TxPwIndex_CCK_24G 0x59 // 0x59~0x66 +#define EEPROM_TxPwIndex_OFDM_24G 0x67 // 0x67~0x74 +#define EEPROM_TSSI_A 0x75 //TSSI value of path A. +#define EEPROM_TSSI_B 0x76 //TSSI value of path B. +#define EEPROM_TxPwTkMode 0x77 //Tx Power tracking mode. +#define EEPROM_HT2T_CH1_A 0x78 //HT 2T path A channel 1 Power Index. +#define EEPROM_HT2T_CH7_A 0x79 //HT 2T path A channel 7 Power Index. +#define EEPROM_HT2T_CH13_A 0x7a //HT 2T path A channel 13 Power Index. +#define EEPROM_HT2T_CH1_B 0x7b //HT 2T path B channel 1 Power Index. +#define EEPROM_HT2T_CH7_B 0x7c //HT 2T path B channel 7 Power Index. +#define EEPROM_HT2T_CH13_B 0x7d //HT 2T path B channel 13 Power Index. +#define EEPROM_BoardType 0x7e //0x0: RTL8188SU, 0x1: RTL8191SU, 0x2: RTL8192SU, 0x3: RTL8191GU +#else +#define EEPROM_BoardType 0x54 //0x0: RTL8188SU, 0x1: RTL8191SU, 0x2: RTL8192SU, 0x3: RTL8191GU +#define EEPROM_TxPwIndex 0x55 //0x55-0x66, Tx Power index. +#define EEPROM_PwDiff 0x67 // Difference of gain index between legacy and high throughput OFDM. +#define EEPROM_ThermalMeter 0x68 // Thermal meter default value. +#define EEPROM_CrystalCap 0x69 // Crystal Cap. +#define EEPROM_TxPowerBase 0x6a // Tx Power of serving station. +#define EEPROM_TSSI_A 0x6b //TSSI value of path A. +#define EEPROM_TSSI_B 0x6c //TSSI value of path B. +#define EEPROM_TxPwTkMode 0x6d //Tx Power tracking mode. +//#define EEPROM_Reserved 0x6e //0x6e-0x7f, reserved. + +// 2009/02/09 Cosa Add for SD3 requirement +#define EEPROM_TX_PWR_HT20_DIFF 0x6e// HT20 Tx Power Index Difference +#define DEFAULT_HT20_TXPWR_DIFF 2 // HT20<->40 default Tx Power Index Difference +#define EEPROM_TX_PWR_OFDM_DIFF 0x71// OFDM Tx Power Index Difference +#define EEPROM_TX_PWR_BAND_EDGE 0x73// TX Power offset at band-edge channel +#define TX_PWR_BAND_EDGE_CHK 0x79// Check if band-edge scheme is enabled +#endif +#define EEPROM_Default_LegacyHTTxPowerDiff 0x3 +#define EEPROM_USB_Default_OPTIONAL_FUNC 0x8 +#define EEPROM_USB_Default_PHY_PARAM 0x0 +#define EEPROM_Default_TSSI 0x0 +#define EEPROM_Default_TxPwrTkMode 0x0 +#define EEPROM_Default_TxPowerDiff 0x0 +#define EEPROM_Default_TxPowerBase 0x0 +#define EEPROM_Default_ThermalMeter 0x7 +#define EEPROM_Default_PwDiff 0x4 +#define EEPROM_Default_CrystalCap 0x5 +#define EEPROM_Default_TxPower 0x1010 +#define EEPROM_Default_BoardType 0x02 // Default: 2X2, RTL8192SU(QFPN68) +#define EEPROM_Default_HT2T_TxPwr 0x10 +#define EEPROM_USB_SN BIT0 +#define EEPROM_USB_REMOTE_WAKEUP BIT1 +#define EEPROM_USB_DEVICE_PWR BIT2 +#define EEPROM_EP_NUMBER (BIT3|BIT4) + +#define EEPROM_CHANNEL_PLAN_FCC 0x0 +#define EEPROM_CHANNEL_PLAN_IC 0x1 +#define EEPROM_CHANNEL_PLAN_ETSI 0x2 +#define EEPROM_CHANNEL_PLAN_SPAIN 0x3 +#define EEPROM_CHANNEL_PLAN_FRANCE 0x4 +#define EEPROM_CHANNEL_PLAN_MKK 0x5 +#define EEPROM_CHANNEL_PLAN_MKK1 0x6 +#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7 +#define EEPROM_CHANNEL_PLAN_TELEC 0x8 +#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9 +#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA +#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 + +#define EEPROM_CID_DEFAULT 0x0 +#define EEPROM_CID_ALPHA 0x1 +#define EEPROM_CID_CAMEO 0X8 +#define EEPROM_CID_SITECOM 0x9 + +//#define EEPROM_CID_RUNTOP 0x2 +//#define EEPROM_CID_Senao 0x3 +//#define EEPROM_CID_TOSHIBA 0x4 +//#define EEPROM_CID_NetCore 0x5 +#define EEPROM_CID_WHQL 0xFE // added by chiyoko for dtm, 20090108 +#endif + +//----------------------------------------------------------------- +// 0x2c0 FW Command Control register definition, added by Roger, 2008.11.27. +//----------------------------------------------------------------- +#define FW_DIG_DISABLE 0xfd00cc00 +#define FW_DIG_ENABLE 0xfd000000 +#define FW_DIG_HALT 0xfd000001 +#define FW_DIG_RESUME 0xfd000002 +#define FW_HIGH_PWR_DISABLE 0xfd000008 +#define FW_HIGH_PWR_ENABLE 0xfd000009 +#define FW_TXPWR_TRACK_ENABLE 0xfd000017 +#define FW_TXPWR_TRACK_DISABLE 0xfd000018 +#define FW_RA_RESET 0xfd0000af +#define FW_RA_ACTIVE 0xfd0000a6 +#define FW_RA_REFRESH 0xfd0000a0 +#define FW_RA_ENABLE_BG 0xfd0000ac +#define FW_IQK_ENABLE 0xf0000020 +#define FW_IQK_SUCCESS 0x0000dddd +#define FW_IQK_FAIL 0x0000ffff +#define FW_OP_FAILURE 0xffffffff +#define FW_DM_DISABLE 0xfd00aa00 +#define FW_BB_RESET_ENABLE 0xff00000d +#define FW_BB_RESET_DISABLE 0xff00000e +#if 0 +//---------------------------------------------------------------------------- +// 8190 EEROM +//---------------------------------------------------------------------------- +#define RTL8190_EEPROM_ID 0x8129 +//#define EEPROM_NODE_ADDRESS_BYTE_0 0x0C + +#define EEPROM_RFInd_PowerDiff 0x28 +#define EEPROM_ThermalMeter 0x29 +#define EEPROM_TxPwDiff_CrystalCap 0x2A //0x2A~0x2B +#define EEPROM_TxPwIndex_CCK 0x2C //0x2C~0x39 +#define EEPROM_TxPwIndex_OFDM_24G 0x3A //0x3A~0x47 +#define EEPROM_TxPwIndex_OFDM_5G 0x34 //0x34~0x7B + +//The following definition is for eeprom 93c56......modified 20080220 +#define EEPROM_C56_CrystalCap 0x17 //0x17 +#define EEPROM_C56_RfA_CCK_Chnl1_TxPwIndex 0x80 //0x80 +#define EEPROM_C56_RfA_HT_OFDM_TxPwIndex 0x81 //0x81~0x83 +#define EEPROM_C56_RfC_CCK_Chnl1_TxPwIndex 0xbc //0xb8 +#define EEPROM_C56_RfC_HT_OFDM_TxPwIndex 0xb9 //0xb9~0xbb +#define EEPROM_Customer_ID 0x7B //0x7B:CustomerID +#define EEPROM_ICVersion_ChannelPlan 0x7C //0x7C:ChnlPlan, + //0x7D:IC_Ver +#define EEPROM_CRC 0x7E //0x7E~0x7F + +#define EEPROM_Default_LegacyHTTxPowerDiff 0x4 +#define EEPROM_Default_ThermalMeter 0x77 +#define EEPROM_Default_AntTxPowerDiff 0x0 +#define EEPROM_Default_TxPwDiff_CrystalCap 0x5 +#define EEPROM_Default_TxPower 0x1010 +#define EEPROM_Default_TxPowerLevel 0x10 + +// +// Define Different EEPROM type for customer +// +#define EEPROM_CID_DEFAULT 0x0 +#define EEPROM_CID_CAMEO 0x1 +#define EEPROM_CID_RUNTOP 0x2 +#define EEPROM_CID_Senao 0x3 +#define EEPROM_CID_TOSHIBA 0x4 +#define EEPROM_CID_NetCore 0x5 +#define EEPROM_CID_Nettronix 0x6 +#define EEPROM_CID_Pronet 0x7 + +#endif + +// +//--------------92SU require delete or move to other place later +// + + + +// +// +// 2008/08/06 MH For share the same 92S source/header files, we copy some +// definition to pass 92SU compiler. But we must delete thm later. +// +// + +//============================================================================ +// 819xUsb Regsiter offset definition +//============================================================================ + +//2 define it temp!!! +#define RFPC 0x5F // Rx FIFO Packet Count +#define RCR_9356SEL BIT6 +#define TCR_LRL_OFFSET 0 +#define TCR_SRL_OFFSET 8 +#define TCR_MXDMA_OFFSET 21 +#define TCR_MXDMA_2048 7 +#define TCR_SAT BIT24 // Enable Rate depedent ack timeout timer +#define RCR_MXDMA_OFFSET 8 +#define RCR_FIFO_OFFSET 13 +#define RCR_OnlyErlPkt BIT31 // Rx Early mode is performed for packet size greater than 1536 +#define CWR 0xDC // Contention window register +#define RetryCTR 0xDE // Retry Count register + + +// For backward compatible for 9xUSB +#define LED1Cfg UnusedRegister // LED1 Configuration Register +#define LED0Cfg UnusedRegister // LED0 Configuration Register +#define GPI UnusedRegister // LED0 Configuration Register +#define BRSR UnusedRegister // LED0 Configuration Register +#define CPU_GEN UnusedRegister // LED0 Configuration Register +#define SIFS UnusedRegister // LED0 Configuration Register + +//---------------------------------------------------------------------------- +// 8190 CPU General Register (offset 0x100, 4 byte) +//---------------------------------------------------------------------------- +//#define CPU_CCK_LOOPBACK 0x00030000 +#define CPU_GEN_SYSTEM_RESET 0x00000001 +//#define CPU_GEN_FIRMWARE_RESET 0x00000008 +//#define CPU_GEN_BOOT_RDY 0x00000010 +//#define CPU_GEN_FIRM_RDY 0x00000020 +//#define CPU_GEN_PUT_CODE_OK 0x00000080 +//#define CPU_GEN_BB_RST 0x00000100 +//#define CPU_GEN_PWR_STB_CPU 0x00000004 +//#define CPU_GEN_NO_LOOPBACK_MSK 0xFFF8FFFF // Set bit18,17,16 to 0. Set bit19 +//#define CPU_GEN_NO_LOOPBACK_SET 0x00080000 // Set BIT19 to 1 + +//---------------------------------------------------------------------------- +// 8192S EEROM +//---------------------------------------------------------------------------- + +//#define RTL8190_EEPROM_ID 0x8129 +//#define EEPROM_VID 0x08 +//#define EEPROM_PID 0x0A +//#define EEPROM_USB_OPTIONAL 0x0C +//#define EEPROM_NODE_ADDRESS_BYTE_0 0x12 +// +//#define EEPROM_TxPowerDiff 0x1F +//#define EEPROM_ThermalMeter 0x20 +//#define EEPROM_PwDiff 0x21 //0x21 +//#define EEPROM_CrystalCap 0x22 //0x22 +// +//#define EEPROM_TxPwIndex_CCK 0x23 //0x23 +//#define EEPROM_TxPwIndex_OFDM_24G 0x24 //0x24~0x26 +#define EEPROM_TxPwIndex_CCK_V1 0x29 //0x29~0x2B +#define EEPROM_TxPwIndex_OFDM_24G_V1 0x2C //0x2C~0x2E +#define EEPROM_TxPwIndex_Ver 0x27 //0x27 +// +//#define EEPROM_Default_TxPowerDiff 0x0 +//#define EEPROM_Default_ThermalMeter 0x7 +//#define EEPROM_Default_PwDiff 0x4 +//#define EEPROM_Default_CrystalCap 0x5 +//#define EEPROM_Default_TxPower 0x1010 +//#define EEPROM_Customer_ID 0x7B //0x7B:CustomerID +//#define EEPROM_Version 0x50 // 0x50 +//#define EEPROM_CustomID 0x52 +//#define EEPROM_ChannelPlan 0x7c //0x7C +//#define EEPROM_IC_VER 0x7d //0x7D +//#define EEPROM_CRC 0x7e //0x7E~0x7F +// +// +//#define EEPROM_CID_DEFAULT 0x0 +//#define EEPROM_CID_CAMEO 0x1 +//#define EEPROM_CID_RUNTOP 0x2 +//#define EEPROM_CID_Senao 0x3 +//#define EEPROM_CID_TOSHIBA 0x4 // Toshiba setting, Merge by Jacken, 2008/01/31 +//#define EEPROM_CID_NetCore 0x5 + + +// +//--------------92SU require delete or move to other place later +// + +//============================================================ +// CCX Related Register +//============================================================ +#define CCX_COMMAND_REG 0x890 +// CCX Measurement Command Register. 4 Bytes. +// Bit[0]: R_CLM_En, 1=enable, 0=disable. Enable or disable "Channel Load +// Measurement (CLM)". +// Bit[1]: R_NHM_En, 1=enable, 0=disable. Enable or disalbe "Noise Histogram +// Measurement (NHM)". +// Bit[2~7]: Reserved +// Bit[8]: R_CCX_En: 1=enable, 0=disable. Enable or disable CCX function. +// Note: After clearing this bit, all the result of all NHM_Result and CLM_ +// Result are cleared concurrently. +// Bit[9]: R_Ignore_CCA: 1=enable, 0=disable. Enable means that treat CCA +// period as idle time for NHM. +// Bit[10]: R_Ignore_TXON: 1=enable, 0=disable. Enable means that treat TXON +// period as idle time for NHM. +// Bit[11~31]: Reserved. +#define CLM_PERIOD_REG 0x894 +// CCX Measurement Period Register, in unit of 4us. 2 Bytes. +#define NHM_PERIOD_REG 0x896 +// Noise Histogram Measurement Period Register, in unit of 4us. 2Bytes. +#define NHM_THRESHOLD0 0x898 // Noise Histogram Meashorement0 +#define NHM_THRESHOLD1 0x899 // Noise Histogram Meashorement1 +#define NHM_THRESHOLD2 0x89A // Noise Histogram Meashorement2 +#define NHM_THRESHOLD3 0x89B // Noise Histogram Meashorement3 +#define NHM_THRESHOLD4 0x89C // Noise Histogram Meashorement4 +#define NHM_THRESHOLD5 0x89D // Noise Histogram Meashorement5 +#define NHM_THRESHOLD6 0x89E // Noise Histogram Meashorement6 +#define CLM_RESULT_REG 0x8D0 +// Channel Load result register. 4 Bytes. +// Bit[0~15]: Total measured duration of CLM. The CCA busy fraction is caculate +// by CLM_RESULT_REG/CLM_PERIOD_REG. +// Bit[16]: Indicate the CLM result is ready. +// Bit[17~31]: Reserved. +#define NHM_RESULT_REG 0x8D4 +// Noise Histogram result register. 4 Bytes. +// Bit[0~15]: Total measured duration of NHM. If R_Ignore_CCA=1 or +// R_Ignore_TXON=1, this value will be less than NHM_PERIOD_REG. +// Bit[16]: Indicate the NHM result is ready. +// Bit[17~31]: Reserved. +#define NHM_RPI_COUNTER0 0x8D8 +// NHM RPI counter0, the fraction of signal strength < NHM_THRESHOLD0. +#define NHM_RPI_COUNTER1 0x8D9 +// NHM RPI counter1, the fraction of signal stren in NHM_THRESH0, NHM_THRESH1 +#define NHM_RPI_COUNTER2 0x8DA +// NHM RPI counter2, the fraction of signal stren in NHM_THRESH2, NHM_THRESH3 +#define NHM_RPI_COUNTER3 0x8DB +// NHM RPI counter3, the fraction of signal stren in NHM_THRESH4, NHM_THRESH5 +#define NHM_RPI_COUNTER4 0x8DC +// NHM RPI counter4, the fraction of signal stren in NHM_THRESH6, NHM_THRESH7 +#define NHM_RPI_COUNTER5 0x8DD +// NHM RPI counter5, the fraction of signal stren in NHM_THRESH8, NHM_THRESH9 +#define NHM_RPI_COUNTER6 0x8DE +// NHM RPI counter6, the fraction of signal stren in NHM_THRESH10, NHM_THRESH11 +#define NHM_RPI_COUNTER7 0x8DF +// NHM RPI counter7, the fraction of signal stren in NHM_THRESH12, NHM_THRESH13 + +#define HAL_RETRY_LIMIT_INFRA 48 +#define HAL_RETRY_LIMIT_AP_ADHOC 7 + +// HW Readio OFF switch (GPIO BIT) +#define HAL_8192S_HW_GPIO_OFF_BIT BIT3 +#define HAL_8192S_HW_GPIO_OFF_MASK 0xF7 +#define HAL_8192S_HW_GPIO_WPS_BIT BIT4 + +#endif //R8192S_HW + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/drivers/staging/rtl8192su/r8192S_phy.c b/drivers/staging/rtl8192su/r8192S_phy.c new file mode 100644 index 000000000000..99a4051a8458 --- /dev/null +++ b/drivers/staging/rtl8192su/r8192S_phy.c @@ -0,0 +1,5028 @@ +/****************************************************************************** + + (c) Copyright 2008, RealTEK Technologies Inc. All Rights Reserved. + + Module: hal8192sphy.c + + Note: Merge 92SE/SU PHY config as below + 1. BB register R/W API + 2. RF register R/W API + 3. Initial BB/RF/MAC config by reading BB/MAC/RF txt. + 3. Power setting API + 4. Channel switch API + 5. Initial gain switch API. + 6. Other BB/MAC/RF API. + + Function: PHY: Extern function, phy: local function + + Export: PHY_FunctionName + + Abbrev: NONE + + History: + Data Who Remark + 08/08/2008 MHC 1. Port from 9x series phycfg.c + 2. Reorganize code arch and ad description. + 3. Collect similar function. + 4. Seperate extern/local API. + 08/12/2008 MHC We must merge or move USB PHY relative function later. + 10/07/2008 MHC Add IQ calibration for PHY.(Only 1T2R mode now!!!) + 11/06/2008 MHC Add TX Power index PG file to config in 0xExx register + area to map with EEPROM/EFUSE tx pwr index. + +******************************************************************************/ +#include "r8192U.h" +#include "r8192U_dm.h" +#include "r8192S_rtl6052.h" + +#ifdef RTL8192SU +#include "r8192S_hw.h" +#include "r8192S_phy.h" +#include "r8192S_phyreg.h" +#include "r8192SU_HWImg.h" +//#include "r8192S_FwImgDTM.h" +#else +#include "r8192U_hw.h" +#include "r819xU_phy.h" +#include "r819xU_phyreg.h" +#endif + +#ifdef ENABLE_DOT11D +#include "dot11d.h" +#endif + +/*---------------------------Define Local Constant---------------------------*/ +/* Channel switch:The size of command tables for switch channel*/ +#define MAX_PRECMD_CNT 16 +#define MAX_RFDEPENDCMD_CNT 16 +#define MAX_POSTCMD_CNT 16 +#define MAX_DOZE_WAITING_TIMES_9x 64 + +/*------------------------Define local variable------------------------------*/ +// 2004-05-11 +#ifndef RTL8192SU +static u32 RF_CHANNEL_TABLE_ZEBRA[]={ + 0, + 0x085c,//2412 1 + 0x08dc,//2417 2 + 0x095c,//2422 3 + 0x09dc,//2427 4 + 0x0a5c,//2432 5 + 0x0adc,//2437 6 + 0x0b5c,//2442 7 + 0x0bdc,//2447 8 + 0x0c5c,//2452 9 + 0x0cdc,//2457 10 + 0x0d5c,//2462 11 + 0x0ddc,//2467 12 + 0x0e5c,//2472 13 + //0x0f5c,//2484 + 0x0f72,//2484 //20040810 +}; +#endif + +static u32 +phy_CalculateBitShift(u32 BitMask); +static RT_STATUS +phy_ConfigMACWithHeaderFile(struct net_device* dev); +static void +phy_InitBBRFRegisterDefinition(struct net_device* dev); +static RT_STATUS +phy_BB8192S_Config_ParaFile(struct net_device* dev); +static RT_STATUS +phy_ConfigBBWithHeaderFile(struct net_device* dev,u8 ConfigType); +static bool +phy_SetRFPowerState8192SU(struct net_device* dev,RT_RF_POWER_STATE eRFPowerState); +void +SetBWModeCallback8192SUsbWorkItem(struct net_device *dev); +void +SetBWModeCallback8192SUsbWorkItem(struct net_device *dev); +void +SwChnlCallback8192SUsbWorkItem(struct net_device *dev ); +static void +phy_FinishSwChnlNow(struct net_device* dev,u8 channel); +static bool +phy_SwChnlStepByStep( + struct net_device* dev, + u8 channel, + u8 *stage, + u8 *step, + u32 *delay + ); +static RT_STATUS +phy_ConfigBBWithPgHeaderFile(struct net_device* dev,u8 ConfigType); +#ifdef RTL8192SE +static u32 phy_FwRFSerialRead( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset); +static u32 phy_RFSerialRead(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset); +static void phy_FwRFSerialWrite( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data); +static void phy_RFSerialWrite( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data); +#endif +static long phy_TxPwrIdxToDbm( struct net_device* dev, WIRELESS_MODE WirelessMode, u8 TxPwrIdx); +static u8 phy_DbmToTxPwrIdx( struct net_device* dev, WIRELESS_MODE WirelessMode, long PowerInDbm); +void phy_SetFwCmdIOCallback(struct net_device* dev); + +//#if ((HAL_CODE_BASE == RTL8192_S) && (DEV_BUS_TYPE==USB_INTERFACE)) +#ifdef RTL8192SU +// +// Description: +// Base Band read by 4181 to make sure that operation could be done in unlimited cycle. +// +// Assumption: +// - Only use on RTL8192S USB interface. +// - PASSIVE LEVEL +// +// Created by Roger, 2008.09.06. +// +//use in phy only +u32 phy_QueryUsbBBReg(struct net_device* dev, u32 RegAddr) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + u32 ReturnValue = 0xffffffff; + u8 PollingCnt = 50; + u8 BBWaitCounter = 0; + + + // + // <Roger_Notes> Due to PASSIVE_LEVEL, so we ONLY simply busy waiting for a while here. + // We have to make sure that previous BB I/O has been done. + // 2008.08.20. + // + while(priv->bChangeBBInProgress) + { + BBWaitCounter ++; + RT_TRACE(COMP_RF, "phy_QueryUsbBBReg(): Wait 1 ms (%d times)...\n", BBWaitCounter); + msleep(1); // 1 ms + + // Wait too long, return FALSE to avoid to be stuck here. + if((BBWaitCounter > 100) )//||RT_USB_CANNOT_IO(Adapter)) + { + RT_TRACE(COMP_RF, "phy_QueryUsbBBReg(): (%d) Wait too logn to query BB!!\n", BBWaitCounter); + return ReturnValue; + } + } + + priv->bChangeBBInProgress = true; + + read_nic_dword(dev, RegAddr); + + do + {// Make sure that access could be done. + if((read_nic_byte(dev, PHY_REG)&HST_RDBUSY) == 0) + break; + }while( --PollingCnt ); + + if(PollingCnt == 0) + { + RT_TRACE(COMP_RF, "Fail!!!phy_QueryUsbBBReg(): RegAddr(%#x) = %#x\n", RegAddr, ReturnValue); + } + else + { + // Data FW read back. + ReturnValue = read_nic_dword(dev, PHY_REG_DATA); + RT_TRACE(COMP_RF, "phy_QueryUsbBBReg(): RegAddr(%#x) = %#x, PollingCnt(%d)\n", RegAddr, ReturnValue, PollingCnt); + } + + priv->bChangeBBInProgress = false; + + return ReturnValue; +} + + + +// +// Description: +// Base Band wrote by 4181 to make sure that operation could be done in unlimited cycle. +// +// Assumption: +// - Only use on RTL8192S USB interface. +// - PASSIVE LEVEL +// +// Created by Roger, 2008.09.06. +// +//use in phy only +void +phy_SetUsbBBReg(struct net_device* dev,u32 RegAddr,u32 Data) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + u8 BBWaitCounter = 0; + + RT_TRACE(COMP_RF, "phy_SetUsbBBReg(): RegAddr(%#x) <= %#x\n", RegAddr, Data); + + // + // <Roger_Notes> Due to PASSIVE_LEVEL, so we ONLY simply busy waiting for a while here. + // We have to make sure that previous BB I/O has been done. + // 2008.08.20. + // + while(priv->bChangeBBInProgress) + { + BBWaitCounter ++; + RT_TRACE(COMP_RF, "phy_SetUsbBBReg(): Wait 1 ms (%d times)...\n", BBWaitCounter); + msleep(1); // 1 ms + + if((BBWaitCounter > 100))// || RT_USB_CANNOT_IO(Adapter)) + { + RT_TRACE(COMP_RF, "phy_SetUsbBBReg(): (%d) Wait too logn to query BB!!\n", BBWaitCounter); + return; + } + } + + priv->bChangeBBInProgress = true; + //printk("**************%s: RegAddr:%x Data:%x\n", __FUNCTION__,RegAddr, Data); + write_nic_dword(dev, RegAddr, Data); + + priv->bChangeBBInProgress = false; +} + + + +// +// Description: +// RF read by 4181 to make sure that operation could be done in unlimited cycle. +// +// Assumption: +// - Only use on RTL8192S USB interface. +// - PASSIVE LEVEL +// - RT_RF_OPERATE_SPINLOCK is acquired and keep on holding to the end.FIXLZM +// +// Created by Roger, 2008.09.06. +// +//use in phy only +u32 phy_QueryUsbRFReg( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset) +{ + + struct r8192_priv *priv = ieee80211_priv(dev); + //u32 value = 0, ReturnValue = 0; + u32 ReturnValue = 0; + //u32 tmplong,tmplong2; + u8 PollingCnt = 50; + u8 RFWaitCounter = 0; + + + // + // <Roger_Notes> Due to PASSIVE_LEVEL, so we ONLY simply busy waiting for a while here. + // We have to make sure that previous RF I/O has been done. + // 2008.08.20. + // + while(priv->bChangeRFInProgress) + { + //PlatformReleaseSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK); + //spin_lock_irqsave(&priv->rf_lock, flags); //LZM,090318 + down(&priv->rf_sem); + + RFWaitCounter ++; + RT_TRACE(COMP_RF, "phy_QueryUsbRFReg(): Wait 1 ms (%d times)...\n", RFWaitCounter); + msleep(1); // 1 ms + + if((RFWaitCounter > 100)) //|| RT_USB_CANNOT_IO(Adapter)) + { + RT_TRACE(COMP_RF, "phy_QueryUsbRFReg(): (%d) Wait too logn to query BB!!\n", RFWaitCounter); + return 0xffffffff; + } + else + { + //PlatformAcquireSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK); + } + } + + priv->bChangeRFInProgress = true; + //PlatformReleaseSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK); + + + Offset &= 0x3f; //RF_Offset= 0x00~0x3F + + write_nic_dword(dev, RF_BB_CMD_ADDR, 0xF0000002| + (Offset<<8)| //RF_Offset= 0x00~0x3F + (eRFPath<<16)); //RF_Path = 0(A) or 1(B) + + do + {// Make sure that access could be done. + if(read_nic_dword(dev, RF_BB_CMD_ADDR) == 0) + break; + }while( --PollingCnt ); + + // Data FW read back. + ReturnValue = read_nic_dword(dev, RF_BB_CMD_DATA); + + //PlatformAcquireSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK); + //spin_unlock_irqrestore(&priv->rf_lock, flags); //LZM,090318 + up(&priv->rf_sem); + priv->bChangeRFInProgress = false; + + RT_TRACE(COMP_RF, "phy_QueryUsbRFReg(): eRFPath(%d), Offset(%#x) = %#x\n", eRFPath, Offset, ReturnValue); + + return ReturnValue; + +} + + +// +// Description: +// RF wrote by 4181 to make sure that operation could be done in unlimited cycle. +// +// Assumption: +// - Only use on RTL8192S USB interface. +// - PASSIVE LEVEL +// - RT_RF_OPERATE_SPINLOCK is acquired and keep on holding to the end.FIXLZM +// +// Created by Roger, 2008.09.06. +// +//use in phy only +void phy_SetUsbRFReg(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 RegAddr,u32 Data) +{ + + struct r8192_priv *priv = ieee80211_priv(dev); + u8 PollingCnt = 50; + u8 RFWaitCounter = 0; + + + // + // <Roger_Notes> Due to PASSIVE_LEVEL, so we ONLY simply busy waiting for a while here. + // We have to make sure that previous BB I/O has been done. + // 2008.08.20. + // + while(priv->bChangeRFInProgress) + { + //PlatformReleaseSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK); + //spin_lock_irqsave(&priv->rf_lock, flags); //LZM,090318 + down(&priv->rf_sem); + + RFWaitCounter ++; + RT_TRACE(COMP_RF, "phy_SetUsbRFReg(): Wait 1 ms (%d times)...\n", RFWaitCounter); + msleep(1); // 1 ms + + if((RFWaitCounter > 100))// || RT_USB_CANNOT_IO(Adapter)) + { + RT_TRACE(COMP_RF, "phy_SetUsbRFReg(): (%d) Wait too logn to query BB!!\n", RFWaitCounter); + return; + } + else + { + //PlatformAcquireSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK); + } + } + + priv->bChangeRFInProgress = true; + //PlatformReleaseSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK); + + + RegAddr &= 0x3f; //RF_Offset= 0x00~0x3F + + write_nic_dword(dev, RF_BB_CMD_DATA, Data); + write_nic_dword(dev, RF_BB_CMD_ADDR, 0xF0000003| + (RegAddr<<8)| //RF_Offset= 0x00~0x3F + (eRFPath<<16)); //RF_Path = 0(A) or 1(B) + + do + {// Make sure that access could be done. + if(read_nic_dword(dev, RF_BB_CMD_ADDR) == 0) + break; + }while( --PollingCnt ); + + if(PollingCnt == 0) + { + RT_TRACE(COMP_RF, "phy_SetUsbRFReg(): Set RegAddr(%#x) = %#x Fail!!!\n", RegAddr, Data); + } + + //PlatformAcquireSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK); + //spin_unlock_irqrestore(&priv->rf_lock, flags); //LZM,090318 + up(&priv->rf_sem); + priv->bChangeRFInProgress = false; + +} + +#endif + +/*---------------------Define local function prototype-----------------------*/ + + +/*----------------------------Function Body----------------------------------*/ +// +// 1. BB register R/W API +// +/** +* Function: PHY_QueryBBReg +* +* OverView: Read "sepcific bits" from BB register +* +* Input: +* PADAPTER Adapter, +* u32 RegAddr, //The target address to be readback +* u32 BitMask //The target bit position in the target address +* //to be readback +* Output: None +* Return: u32 Data //The readback register value +* Note: This function is equal to "GetRegSetting" in PHY programming guide +*/ +//use phy dm core 8225 8256 6052 +//u32 PHY_QueryBBReg(struct net_device* dev,u32 RegAddr, u32 BitMask) +u32 rtl8192_QueryBBReg(struct net_device* dev, u32 RegAddr, u32 BitMask) +{ + + u32 ReturnValue = 0, OriginalValue, BitShift; + +#if (DISABLE_BB_RF == 1) + return 0; +#endif + + RT_TRACE(COMP_RF, "--->PHY_QueryBBReg(): RegAddr(%#x), BitMask(%#x)\n", RegAddr, BitMask); + + // + // <Roger_Notes> Due to 8051 operation cycle (limitation cycle: 6us) and 1-Byte access issue, we should use + // 4181 to access Base Band instead of 8051 on USB interface to make sure that access could be done in + // infinite cycle. + // 2008.09.06. + // +//#if ((HAL_CODE_BASE == RTL8192_S) && (DEV_BUS_TYPE==USB_INTERFACE)) +#ifdef RTL8192SU + if(IS_BB_REG_OFFSET_92S(RegAddr)) + { + //if(RT_USB_CANNOT_IO(Adapter)) return FALSE; + + if((RegAddr & 0x03) != 0) + { + printk("%s: Not DWORD alignment!!\n", __FUNCTION__); + return 0; + } + + OriginalValue = phy_QueryUsbBBReg(dev, RegAddr); + } + else +#endif + { + OriginalValue = read_nic_dword(dev, RegAddr); + } + + BitShift = phy_CalculateBitShift(BitMask); + ReturnValue = (OriginalValue & BitMask) >> BitShift; + + //RTPRINT(FPHY, PHY_BBR, ("BBR MASK=0x%x Addr[0x%x]=0x%x\n", BitMask, RegAddr, OriginalValue)); + RT_TRACE(COMP_RF, "<---PHY_QueryBBReg(): RegAddr(%#x), BitMask(%#x), OriginalValue(%#x)\n", RegAddr, BitMask, OriginalValue); + return (ReturnValue); +} + +/** +* Function: PHY_SetBBReg +* +* OverView: Write "Specific bits" to BB register (page 8~) +* +* Input: +* PADAPTER Adapter, +* u32 RegAddr, //The target address to be modified +* u32 BitMask //The target bit position in the target address +* //to be modified +* u32 Data //The new register value in the target bit position +* //of the target address +* +* Output: None +* Return: None +* Note: This function is equal to "PutRegSetting" in PHY programming guide +*/ +//use phy dm core 8225 8256 +//void PHY_SetBBReg(struct net_device* dev,u32 RegAddr, u32 BitMask, u32 Data ) +void rtl8192_setBBreg(struct net_device* dev, u32 RegAddr, u32 BitMask, u32 Data) +{ + u32 OriginalValue, BitShift, NewValue; + +#if (DISABLE_BB_RF == 1) + return; +#endif + + RT_TRACE(COMP_RF, "--->PHY_SetBBReg(): RegAddr(%#x), BitMask(%#x), Data(%#x)\n", RegAddr, BitMask, Data); + + // + // <Roger_Notes> Due to 8051 operation cycle (limitation cycle: 6us) and 1-Byte access issue, we should use + // 4181 to access Base Band instead of 8051 on USB interface to make sure that access could be done in + // infinite cycle. + // 2008.09.06. + // +//#if ((HAL_CODE_BASE == RTL8192_S) && (DEV_BUS_TYPE==USB_INTERFACE)) +#ifdef RTL8192SU + if(IS_BB_REG_OFFSET_92S(RegAddr)) + { + if((RegAddr & 0x03) != 0) + { + printk("%s: Not DWORD alignment!!\n", __FUNCTION__); + return; + } + + if(BitMask!= bMaskDWord) + {//if not "double word" write + OriginalValue = phy_QueryUsbBBReg(dev, RegAddr); + BitShift = phy_CalculateBitShift(BitMask); + NewValue = (((OriginalValue) & (~BitMask))|(Data << BitShift)); + phy_SetUsbBBReg(dev, RegAddr, NewValue); + }else + phy_SetUsbBBReg(dev, RegAddr, Data); + } + else +#endif + { + if(BitMask!= bMaskDWord) + {//if not "double word" write + OriginalValue = read_nic_dword(dev, RegAddr); + BitShift = phy_CalculateBitShift(BitMask); + NewValue = (((OriginalValue) & (~BitMask)) | (Data << BitShift)); + write_nic_dword(dev, RegAddr, NewValue); + }else + write_nic_dword(dev, RegAddr, Data); + } + + //RT_TRACE(COMP_RF, "<---PHY_SetBBReg(): RegAddr(%#x), BitMask(%#x), Data(%#x)\n", RegAddr, BitMask, Data); + + return; +} + + +// +// 2. RF register R/W API +// +/** +* Function: PHY_QueryRFReg +* +* OverView: Query "Specific bits" to RF register (page 8~) +* +* Input: +* PADAPTER Adapter, +* RF90_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D +* u32 RegAddr, //The target address to be read +* u32 BitMask //The target bit position in the target address +* //to be read +* +* Output: None +* Return: u32 Readback value +* Note: This function is equal to "GetRFRegSetting" in PHY programming guide +*/ +//in dm 8256 and phy +//u32 PHY_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask) +u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask) +{ + u32 Original_Value, Readback_Value, BitShift;//, flags; + struct r8192_priv *priv = ieee80211_priv(dev); + +#if (DISABLE_BB_RF == 1) + return 0; +#endif + + RT_TRACE(COMP_RF, "--->PHY_QueryRFReg(): RegAddr(%#x), eRFPath(%#x), BitMask(%#x)\n", RegAddr, eRFPath,BitMask); + + if (!((priv->rf_pathmap >> eRFPath) & 0x1)) + { + printk("EEEEEError: rfpath off! rf_pathmap=%x eRFPath=%x\n", priv->rf_pathmap, eRFPath); + return 0; + } + + if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) + { + printk("EEEEEError: not legal rfpath! eRFPath=%x\n", eRFPath); + return 0; + } + + /* 2008/01/17 MH We get and release spin lock when reading RF register. */ + //PlatformAcquireSpinLock(dev, RT_RF_OPERATE_SPINLOCK);FIXLZM + //spin_lock_irqsave(&priv->rf_lock, flags); //YJ,test,090113 + down(&priv->rf_sem); + // + // <Roger_Notes> Due to 8051 operation cycle (limitation cycle: 6us) and 1-Byte access issue, we should use + // 4181 to access Base Band instead of 8051 on USB interface to make sure that access could be done in + // infinite cycle. + // 2008.09.06. + // +//#if (HAL_CODE_BASE == RTL8192_S && DEV_BUS_TYPE==USB_INTERFACE) +#ifdef RTL8192SU + //if(RT_USB_CANNOT_IO(Adapter)) return FALSE; + Original_Value = phy_QueryUsbRFReg(dev, eRFPath, RegAddr); +#else + if (priv->Rf_Mode == RF_OP_By_FW) + { + Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr); + } + else + { + Original_Value = phy_RFSerialRead(dev, eRFPath, RegAddr); + } +#endif + + BitShift = phy_CalculateBitShift(BitMask); + Readback_Value = (Original_Value & BitMask) >> BitShift; + //spin_unlock_irqrestore(&priv->rf_lock, flags); //YJ,test,090113 + up(&priv->rf_sem); + //PlatformReleaseSpinLock(dev, RT_RF_OPERATE_SPINLOCK); + + //RTPRINT(FPHY, PHY_RFR, ("RFR-%d MASK=0x%x Addr[0x%x]=0x%x\n", eRFPath, BitMask, RegAddr, Original_Value)); + + return (Readback_Value); +} + +/** +* Function: PHY_SetRFReg +* +* OverView: Write "Specific bits" to RF register (page 8~) +* +* Input: +* PADAPTER Adapter, +* RF90_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D +* u32 RegAddr, //The target address to be modified +* u32 BitMask //The target bit position in the target address +* //to be modified +* u32 Data //The new register Data in the target bit position +* //of the target address +* +* Output: None +* Return: None +* Note: This function is equal to "PutRFRegSetting" in PHY programming guide +*/ +//use phy 8225 8256 +//void PHY_SetRFReg(struct net_device* dev,RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask,u32 Data ) +void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data) +{ + + struct r8192_priv *priv = ieee80211_priv(dev); + u32 Original_Value, BitShift, New_Value;//, flags; +#if (DISABLE_BB_RF == 1) + return; +#endif + + RT_TRACE(COMP_RF, "--->PHY_SetRFReg(): RegAddr(%#x), BitMask(%#x), Data(%#x), eRFPath(%#x)\n", + RegAddr, BitMask, Data, eRFPath); + + if (!((priv->rf_pathmap >> eRFPath) & 0x1)) + { + printk("EEEEEError: rfpath off! rf_pathmap=%x eRFPath=%x\n", priv->rf_pathmap, eRFPath); + return ; + } + if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) + { + printk("EEEEEError: not legal rfpath! eRFPath=%x\n", eRFPath); + return; + } + + /* 2008/01/17 MH We get and release spin lock when writing RF register. */ + //PlatformAcquireSpinLock(dev, RT_RF_OPERATE_SPINLOCK); + //spin_lock_irqsave(&priv->rf_lock, flags); //YJ,test,090113 + down(&priv->rf_sem); + // + // <Roger_Notes> Due to 8051 operation cycle (limitation cycle: 6us) and 1-Byte access issue, we should use + // 4181 to access Base Band instead of 8051 on USB interface to make sure that access could be done in + // infinite cycle. + // 2008.09.06. + // +//#if (HAL_CODE_BASE == RTL8192_S && DEV_BUS_TYPE==USB_INTERFACE) +#ifdef RTL8192SU + //if(RT_USB_CANNOT_IO(Adapter)) return; + + if (BitMask != bRFRegOffsetMask) // RF data is 12 bits only + { + Original_Value = phy_QueryUsbRFReg(dev, eRFPath, RegAddr); + BitShift = phy_CalculateBitShift(BitMask); + New_Value = (((Original_Value)&(~BitMask))|(Data<< BitShift)); + phy_SetUsbRFReg(dev, eRFPath, RegAddr, New_Value); + } + else + phy_SetUsbRFReg(dev, eRFPath, RegAddr, Data); +#else + if (priv->Rf_Mode == RF_OP_By_FW) + { + //DbgPrint("eRFPath-%d Addr[%02x] = %08x\n", eRFPath, RegAddr, Data); + if (BitMask != bRFRegOffsetMask) // RF data is 12 bits only + { + Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr); + BitShift = phy_CalculateBitShift(BitMask); + New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift)); + + phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value); + } + else + phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data); + } + else + { + //DbgPrint("eRFPath-%d Addr[%02x] = %08x\n", eRFPath, RegAddr, Data); + if (BitMask != bRFRegOffsetMask) // RF data is 12 bits only + { + Original_Value = phy_RFSerialRead(dev, eRFPath, RegAddr); + BitShift = phy_CalculateBitShift(BitMask); + New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift)); + + phy_RFSerialWrite(dev, eRFPath, RegAddr, New_Value); + } + else + phy_RFSerialWrite(dev, eRFPath, RegAddr, Data); + + } +#endif + //PlatformReleaseSpinLock(dev, RT_RF_OPERATE_SPINLOCK); + //spin_unlock_irqrestore(&priv->rf_lock, flags); //YJ,test,090113 + up(&priv->rf_sem); + //RTPRINT(FPHY, PHY_RFW, ("RFW-%d MASK=0x%x Addr[0x%x]=0x%x\n", eRFPath, BitMask, RegAddr, Data)); + RT_TRACE(COMP_RF, "<---PHY_SetRFReg(): RegAddr(%#x), BitMask(%#x), Data(%#x), eRFPath(%#x)\n", + RegAddr, BitMask, Data, eRFPath); + +} + +#ifdef RTL8192SE +/*----------------------------------------------------------------------------- + * Function: phy_FwRFSerialRead() + * + * Overview: We support firmware to execute RF-R/W. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 01/21/2008 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +//use in phy only +static u32 +phy_FwRFSerialRead( + struct net_device* dev, + RF90_RADIO_PATH_E eRFPath, + u32 Offset ) +{ + u32 retValue = 0; + //u32 Data = 0; + //u8 time = 0; +#if 0 + //DbgPrint("FW RF CTRL\n\r"); + /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can + not execute the scheme in the initial step. Otherwise, RF-R/W will waste + much time. This is only for site survey. */ + // 1. Read operation need not insert data. bit 0-11 + //Data &= bMask12Bits; + // 2. Write RF register address. Bit 12-19 + Data |= ((Offset&0xFF)<<12); + // 3. Write RF path. bit 20-21 + Data |= ((eRFPath&0x3)<<20); + // 4. Set RF read indicator. bit 22=0 + //Data |= 0x00000; + // 5. Trigger Fw to operate the command. bit 31 + Data |= 0x80000000; + // 6. We can not execute read operation if bit 31 is 1. + while (PlatformIORead4Byte(dev, QPNR)&0x80000000) + { + // If FW can not finish RF-R/W for more than ?? times. We must reset FW. + if (time++ < 100) + { + //DbgPrint("FW not finish RF-R Time=%d\n\r", time); + delay_us(10); + } + else + break; + } + // 7. Execute read operation. + PlatformIOWrite4Byte(dev, QPNR, Data); + // 8. Check if firmawre send back RF content. + while (PlatformIORead4Byte(dev, QPNR)&0x80000000) + { + // If FW can not finish RF-R/W for more than ?? times. We must reset FW. + if (time++ < 100) + { + //DbgPrint("FW not finish RF-W Time=%d\n\r", time); + delay_us(10); + } + else + return (0); + } + retValue = PlatformIORead4Byte(dev, RF_DATA); +#endif + return (retValue); + +} /* phy_FwRFSerialRead */ + +/*----------------------------------------------------------------------------- + * Function: phy_FwRFSerialWrite() + * + * Overview: We support firmware to execute RF-R/W. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 01/21/2008 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +//use in phy only +static void +phy_FwRFSerialWrite( + struct net_device* dev, + RF90_RADIO_PATH_E eRFPath, + u32 Offset, + u32 Data ) +{ +#if 0 + u8 time = 0; + DbgPrint("N FW RF CTRL RF-%d OF%02x DATA=%03x\n\r", eRFPath, Offset, Data); + /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can + not execute the scheme in the initial step. Otherwise, RF-R/W will waste + much time. This is only for site survey. */ + + // 1. Set driver write bit and 12 bit data. bit 0-11 + //Data &= bMask12Bits; // Done by uper layer. + // 2. Write RF register address. bit 12-19 + Data |= ((Offset&0xFF)<<12); + // 3. Write RF path. bit 20-21 + Data |= ((eRFPath&0x3)<<20); + // 4. Set RF write indicator. bit 22=1 + Data |= 0x400000; + // 5. Trigger Fw to operate the command. bit 31=1 + Data |= 0x80000000; + + // 6. Write operation. We can not write if bit 31 is 1. + while (PlatformIORead4Byte(dev, QPNR)&0x80000000) + { + // If FW can not finish RF-R/W for more than ?? times. We must reset FW. + if (time++ < 100) + { + //DbgPrint("FW not finish RF-W Time=%d\n\r", time); + delay_us(10); + } + else + break; + } + // 7. No matter check bit. We always force the write. Because FW will + // not accept the command. + PlatformIOWrite4Byte(dev, QPNR, Data); + /* 2007/11/02 MH Acoording to test, we must delay 20us to wait firmware + to finish RF write operation. */ + /* 2008/01/17 MH We support delay in firmware side now. */ + //delay_us(20); +#endif +} /* phy_FwRFSerialWrite */ + +/** +* Function: phy_RFSerialRead +* +* OverView: Read regster from RF chips +* +* Input: +* PADAPTER Adapter, +* RF90_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D +* u32 Offset, //The target address to be read +* +* Output: None +* Return: u32 reback value +* Note: Threre are three types of serial operations: +* 1. Software serial write +* 2. Hardware LSSI-Low Speed Serial Interface +* 3. Hardware HSSI-High speed +* serial write. Driver need to implement (1) and (2). +* This function is equal to the combination of RF_ReadReg() and RFLSSIRead() +*/ +//use in phy only +static u32 phy_RFSerialRead(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset) +{ + + u32 retValue = 0; + struct r8192_priv *priv = ieee80211_priv(dev); + BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath]; + u32 NewOffset; + u8 RfPiEnable=0; + + + // + // Make sure RF register offset is correct + // + Offset &= 0x3f; + + // + // Switch page for 8256 RF IC + // + if( priv->rf_chip == RF_8256 || + priv->rf_chip == RF_8225 || + priv->rf_chip == RF_6052) + { + //analog to digital off, for protection + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8] + + if(Offset>=31) + { + priv->RFReadPageCnt[2]++;//cosa add for debug + priv->RfReg0Value[eRFPath] |= 0x140; + + // Switch to Reg_Mode2 for Reg31~45 + rtl8192_setBBreg(dev, + pPhyReg->rf3wireOffset, + bMaskDWord, + (priv->RfReg0Value[eRFPath] << 16) ); + + // Modified Offset + NewOffset = Offset - 30; + + }else if(Offset>=16) + { + priv->RFReadPageCnt[1]++;//cosa add for debug + priv->RfReg0Value[eRFPath] |= 0x100; + priv->RfReg0Value[eRFPath] &= (~0x40); + + // Switch to Reg_Mode1 for Reg16~30 + rtl8192_setBBreg(dev, + pPhyReg->rf3wireOffset, + bMaskDWord, + (priv->RfReg0Value[eRFPath] << 16) ); + + // Modified Offset + NewOffset = Offset - 15; + } + else + { + priv->RFReadPageCnt[0]++;//cosa add for debug + NewOffset = Offset; + } + } + else + NewOffset = Offset; + + // + // Put desired read address to LSSI control register + // + rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, NewOffset); + + // + // Issue a posedge trigger + // + rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0); + rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1); + + // TODO: we should not delay such a long time. Ask help from SD3 + mdelay(1); + + retValue = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData); + + // Switch back to Reg_Mode0; + if( priv->rf_chip == RF_8256 || + priv->rf_chip == RF_8225 || + priv->rf_chip == RF_0222D) + { + if (Offset >= 0x10) + { + priv->RfReg0Value[eRFPath] &= 0xebf; + + rtl8192_setBBreg( + dev, + pPhyReg->rf3wireOffset, + bMaskDWord, + (priv->RfReg0Value[eRFPath] << 16) ); + } + + //analog to digital on + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf);// 0x88c[11:8] + } + + return retValue; +} + + + +/** +* Function: phy_RFSerialWrite +* +* OverView: Write data to RF register (page 8~) +* +* Input: +* PADAPTER Adapter, +* RF90_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D +* u32 Offset, //The target address to be read +* u32 Data //The new register Data in the target bit position +* //of the target to be read +* +* Output: None +* Return: None +* Note: Threre are three types of serial operations: +* 1. Software serial write +* 2. Hardware LSSI-Low Speed Serial Interface +* 3. Hardware HSSI-High speed +* serial write. Driver need to implement (1) and (2). +* This function is equal to the combination of RF_ReadReg() and RFLSSIRead() + * + * Note: For RF8256 only + * The total count of RTL8256(Zebra4) register is around 36 bit it only employs + * 4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10]) + * to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration + * programming guide" for more details. + * Thus, we define a sub-finction for RTL8526 register address conversion + * =========================================================== + * Register Mode RegCTL[1] RegCTL[0] Note + * (Reg00[12]) (Reg00[10]) + * =========================================================== + * Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf) + * ------------------------------------------------------------------ + * Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf) + * ------------------------------------------------------------------ + * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf) + * ------------------------------------------------------------------ +*/ +////use in phy only +static void +phy_RFSerialWrite( + struct net_device* dev, + RF90_RADIO_PATH_E eRFPath, + u32 Offset, + u32 Data + ) +{ + u32 DataAndAddr = 0; + struct r8192_priv *priv = ieee80211_priv(dev); + BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath]; + u32 NewOffset; + + Offset &= 0x3f; + + // Shadow Update + PHY_RFShadowWrite(dev, eRFPath, Offset, Data); + + + // Switch page for 8256 RF IC + if( priv->rf_chip == RF_8256 || + priv->rf_chip == RF_8225 || + priv->rf_chip == RF_0222D) + { + //analog to digital off, for protection + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8] + + if(Offset>=31) + { + priv->RFWritePageCnt[2]++;//cosa add for debug + priv->RfReg0Value[eRFPath] |= 0x140; + + rtl8192_setBBreg(dev, + pPhyReg->rf3wireOffset, + bMaskDWord, + (priv->RfReg0Value[eRFPath] << 16) ); + + NewOffset = Offset - 30; + + }else if(Offset>=16) + { + priv->RFWritePageCnt[1]++;//cosa add for debug + priv->RfReg0Value[eRFPath] |= 0x100; + priv->RfReg0Value[eRFPath] &= (~0x40); + + + rtl8192_setBBreg(dev, + pPhyReg->rf3wireOffset, + bMaskDWord, + (priv->RfReg0Value[eRFPath] << 16) ); + + NewOffset = Offset - 15; + } + else + { + priv->RFWritePageCnt[0]++;//cosa add for debug + NewOffset = Offset; + } + } + else + NewOffset = Offset; + + // + // Put write addr in [5:0] and write data in [31:16] + // + DataAndAddr = (Data<<16) | (NewOffset&0x3f); + + // + // Write Operation + // + rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); + + + if(Offset==0x0) + priv->RfReg0Value[eRFPath] = Data; + + // Switch back to Reg_Mode0; + if( priv->rf_chip == RF_8256 || + priv->rf_chip == RF_8225 || + priv->rf_chip == RF_0222D) + { + if (Offset >= 0x10) + { + if(Offset != 0) + { + priv->RfReg0Value[eRFPath] &= 0xebf; + rtl8192_setBBreg( + dev, + pPhyReg->rf3wireOffset, + bMaskDWord, + (priv->RfReg0Value[eRFPath] << 16) ); + } + } + //analog to digital on + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf);// 0x88c[11:8] + } + +} +#else +/** +* Function: phy_RFSerialRead +* +* OverView: Read regster from RF chips +* +* Input: +* PADAPTER Adapter, +* RF90_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D +* u4Byte Offset, //The target address to be read +* +* Output: None +* Return: u4Byte reback value +* Note: Threre are three types of serial operations: +* 1. Software serial write +* 2. Hardware LSSI-Low Speed Serial Interface +* 3. Hardware HSSI-High speed +* serial write. Driver need to implement (1) and (2). +* This function is equal to the combination of RF_ReadReg() and RFLSSIRead() +*/ +#if 0 +static u32 +phy_RFSerialRead(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset) +{ + + u32 retValue = 0; + struct r8192_priv *priv = ieee80211_priv(dev); + BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath]; + u32 NewOffset; + //u32 value = 0; + u32 tmplong,tmplong2; + u32 RfPiEnable=0; +#if 0 + if(pHalData->RFChipID == RF_8225 && Offset > 0x24) //36 valid regs + return retValue; + if(pHalData->RFChipID == RF_8256 && Offset > 0x2D) //45 valid regs + return retValue; +#endif + // + // Make sure RF register offset is correct + // + Offset &= 0x3f; + + // + // Switch page for 8256 RF IC + // + NewOffset = Offset; + + // For 92S LSSI Read RFLSSIRead + // For RF A/B write 0x824/82c(does not work in the future) + // We must use 0x824 for RF A and B to execute read trigger + tmplong = rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, bMaskDWord); + tmplong2 = rtl8192_QueryBBReg(dev, pPhyReg->rfHSSIPara2, bMaskDWord); + tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge; //T65 RF + + rtl8192_setBBreg(dev, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong&(~bLSSIReadEdge)); + mdelay(1); + + rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bMaskDWord, tmplong2); + mdelay(1); + + rtl8192_setBBreg(dev, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong|bLSSIReadEdge); + mdelay(1); + + if(eRFPath == RF90_PATH_A) + RfPiEnable = (u8)rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter1, BIT8); + else if(eRFPath == RF90_PATH_B) + RfPiEnable = (u8)rtl8192_QueryBBReg(dev, rFPGA0_XB_HSSIParameter1, BIT8); + + if(RfPiEnable) + { // Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF + retValue = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBackPi, bLSSIReadBackData); + //DbgPrint("Readback from RF-PI : 0x%x\n", retValue); + } + else + { //Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF + retValue = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData); + //DbgPrint("Readback from RF-SI : 0x%x\n", retValue); + } + //RTPRINT(FPHY, PHY_RFR, ("RFR-%d Addr[0x%x]=0x%x\n", eRFPath, pPhyReg->rfLSSIReadBack, retValue)); + + return retValue; + +} +4 + + +/** +* Function: phy_RFSerialWrite +* +* OverView: Write data to RF register (page 8~) +* +* Input: +* PADAPTER Adapter, +* RF90_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D +* u4Byte Offset, //The target address to be read +* u4Byte Data //The new register Data in the target bit position +* //of the target to be read +* +* Output: None +* Return: None +* Note: Threre are three types of serial operations: +* 1. Software serial write +* 2. Hardware LSSI-Low Speed Serial Interface +* 3. Hardware HSSI-High speed +* serial write. Driver need to implement (1) and (2). +* This function is equal to the combination of RF_ReadReg() and RFLSSIRead() + * + * Note: For RF8256 only + * The total count of RTL8256(Zebra4) register is around 36 bit it only employs + * 4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10]) + * to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration + * programming guide" for more details. + * Thus, we define a sub-finction for RTL8526 register address conversion + * =========================================================== + * Register Mode RegCTL[1] RegCTL[0] Note + * (Reg00[12]) (Reg00[10]) + * =========================================================== + * Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf) + * ------------------------------------------------------------------ + * Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf) + * ------------------------------------------------------------------ + * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf) + * ------------------------------------------------------------------ + * + * 2008/09/02 MH Add 92S RF definition + * + * + * +*/ +static void +phy_RFSerialWrite(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset,u32 Data) +{ + u32 DataAndAddr = 0; + struct r8192_priv *priv = ieee80211_priv(dev); + BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath]; + u32 NewOffset; + +#if 0 + //<Roger_TODO> We should check valid regs for RF_6052 case. + if(pHalData->RFChipID == RF_8225 && Offset > 0x24) //36 valid regs + return; + if(pHalData->RFChipID == RF_8256 && Offset > 0x2D) //45 valid regs + return; +#endif + + Offset &= 0x3f; + + // + // Shadow Update + // + PHY_RFShadowWrite(dev, eRFPath, Offset, Data); + + // + // Switch page for 8256 RF IC + // + NewOffset = Offset; + + // + // Put write addr in [5:0] and write data in [31:16] + // + //DataAndAddr = (Data<<16) | (NewOffset&0x3f); + DataAndAddr = ((NewOffset<<20) | (Data&0x000fffff)) & 0x0fffffff; // T65 RF + + // + // Write Operation + // + rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); + //RTPRINT(FPHY, PHY_RFW, ("RFW-%d Addr[0x%x]=0x%x\n", eRFPath, pPhyReg->rf3wireOffset, DataAndAddr)); + +} +#endif +#endif + +/** +* Function: phy_CalculateBitShift +* +* OverView: Get shifted position of the BitMask +* +* Input: +* u32 BitMask, +* +* Output: none +* Return: u32 Return the shift bit bit position of the mask +*/ +//use in phy only +static u32 phy_CalculateBitShift(u32 BitMask) +{ + u32 i; + + for(i=0; i<=31; i++) + { + if ( ((BitMask>>i) & 0x1 ) == 1) + break; + } + + return (i); +} + + +// +// 3. Initial MAC/BB/RF config by reading MAC/BB/RF txt. +// +/*----------------------------------------------------------------------------- + * Function: PHY_MACConfig8192S + * + * Overview: Condig MAC by header file or parameter file. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 08/12/2008 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +//adapter_start +extern bool PHY_MACConfig8192S(struct net_device* dev) +{ + RT_STATUS rtStatus = RT_STATUS_SUCCESS; + + // + // Config MAC + // +#if RTL8190_Download_Firmware_From_Header + rtStatus = phy_ConfigMACWithHeaderFile(dev); +#else + // Not make sure EEPROM, add later + RT_TRACE(COMP_INIT, "Read MACREG.txt\n"); + //rtStatus = phy_ConfigMACWithParaFile(dev, RTL819X_PHY_MACREG);// lzm del it temp +#endif + return (rtStatus == RT_STATUS_SUCCESS) ? true:false; + +} + +//adapter_start +extern bool +PHY_BBConfig8192S(struct net_device* dev) +{ + RT_STATUS rtStatus = RT_STATUS_SUCCESS; + + u8 PathMap = 0, index = 0, rf_num = 0; + struct r8192_priv *priv = ieee80211_priv(dev); + phy_InitBBRFRegisterDefinition(dev); + + // + // Config BB and AGC + // + //switch( Adapter->MgntInfo.bRegHwParaFile ) + //{ + // case 0: + // phy_BB8190_Config_HardCode(dev); + // break; + + // case 1: + rtStatus = phy_BB8192S_Config_ParaFile(dev); + // break; + + // case 2: + // Partial Modify. + // phy_BB8190_Config_HardCode(dev); + // phy_BB8192S_Config_ParaFile(dev); + // break; + + // default: + // phy_BB8190_Config_HardCode(dev); + // break; + //} + PathMap = (u8)(rtl8192_QueryBBReg(dev, rFPGA0_TxInfo, 0xf) | + rtl8192_QueryBBReg(dev, rOFDM0_TRxPathEnable, 0xf)); + priv->rf_pathmap = PathMap; + for(index = 0; index<4; index++) + { + if((PathMap>>index)&0x1) + rf_num++; + } + + if((priv->rf_type==RF_1T1R && rf_num!=1) || + (priv->rf_type==RF_1T2R && rf_num!=2) || + (priv->rf_type==RF_2T2R && rf_num!=2) || + (priv->rf_type==RF_2T2R_GREEN && rf_num!=2) || + (priv->rf_type==RF_2T4R && rf_num!=4)) + { + RT_TRACE( COMP_INIT, "PHY_BBConfig8192S: RF_Type(%x) does not match RF_Num(%x)!!\n", priv->rf_type, rf_num); + } + return (rtStatus == RT_STATUS_SUCCESS) ? 1:0; +} + +//adapter_start +extern bool +PHY_RFConfig8192S(struct net_device* dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + RT_STATUS rtStatus = RT_STATUS_SUCCESS; + + //Set priv->rf_chip = RF_8225 to do real PHY FPGA initilization + + //<Roger_EXP> We assign RF type here temporally. 2008.09.12. + priv->rf_chip = RF_6052; + + // + // RF config + // + switch(priv->rf_chip) + { + case RF_8225: + case RF_6052: + rtStatus = PHY_RF6052_Config(dev); + break; + + case RF_8256: + //rtStatus = PHY_RF8256_Config(dev); + break; + + case RF_8258: + break; + + case RF_PSEUDO_11N: + //rtStatus = PHY_RF8225_Config(dev); + break; + default: + break; + } + + return (rtStatus == RT_STATUS_SUCCESS) ? 1:0; +} + + +// Joseph test: new initialize order!! +// Test only!! This part need to be re-organized. +// Now it is just for 8256. +//use in phy only +#ifdef TO_DO_LIST +static RT_STATUS +phy_BB8190_Config_HardCode(struct net_device* dev) +{ + //RT_ASSERT(FALSE, ("This function is not implement yet!! \n")); + return RT_STATUS_SUCCESS; +} +#endif + +/*----------------------------------------------------------------------------- + * Function: phy_SetBBtoDiffRFWithHeaderFile() + * + * Overview: This function + * + * + * Input: PADAPTER Adapter + * u1Byte ConfigType 0 => PHY_CONFIG + * + * Output: NONE + * + * Return: RT_STATUS_SUCCESS: configuration file exist + * When Who Remark + * 2008/11/10 tynli + * use in phy only + *---------------------------------------------------------------------------*/ +static RT_STATUS +phy_SetBBtoDiffRFWithHeaderFile(struct net_device* dev, u8 ConfigType) +{ + int i; + struct r8192_priv *priv = ieee80211_priv(dev); + u32* Rtl819XPHY_REGArraytoXTXR_Table; + u16 PHY_REGArraytoXTXRLen; + +//#if (HAL_CODE_BASE != RTL8192_S) + + if(priv->rf_type == RF_1T1R) + { + Rtl819XPHY_REGArraytoXTXR_Table = Rtl819XPHY_REG_to1T1R_Array; + PHY_REGArraytoXTXRLen = PHY_ChangeTo_1T1RArrayLength; + } + else if(priv->rf_type == RF_1T2R) + { + Rtl819XPHY_REGArraytoXTXR_Table = Rtl819XPHY_REG_to1T2R_Array; + PHY_REGArraytoXTXRLen = PHY_ChangeTo_1T2RArrayLength; + } + //else if(priv->rf_type == RF_2T2R || priv->rf_type == RF_2T2R_GREEN) + //{ + // Rtl819XPHY_REGArraytoXTXR_Table = Rtl819XPHY_REG_to2T2R_Array; + // PHY_REGArraytoXTXRLen = PHY_ChangeTo_2T2RArrayLength; + //} + else + { + return RT_STATUS_FAILURE; + } + + if(ConfigType == BaseBand_Config_PHY_REG) + { + for(i=0;i<PHY_REGArraytoXTXRLen;i=i+3) + { + if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfe) + mdelay(50); + else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfd) + mdelay(5); + else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfc) + mdelay(1); + else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfb) + udelay(50); + else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfa) + udelay(5); + else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xf9) + udelay(1); + rtl8192_setBBreg(dev, Rtl819XPHY_REGArraytoXTXR_Table[i], Rtl819XPHY_REGArraytoXTXR_Table[i+1], Rtl819XPHY_REGArraytoXTXR_Table[i+2]); + //RT_TRACE(COMP_SEND, + //"The Rtl819XPHY_REGArraytoXTXR_Table[0] is %lx Rtl819XPHY_REGArraytoXTXR_Table[1] is %lx Rtl819XPHY_REGArraytoXTXR_Table[2] is %lx \n", + //Rtl819XPHY_REGArraytoXTXR_Table[i],Rtl819XPHY_REGArraytoXTXR_Table[i+1], Rtl819XPHY_REGArraytoXTXR_Table[i+2]); + } + } + else { + RT_TRACE(COMP_SEND, "phy_SetBBtoDiffRFWithHeaderFile(): ConfigType != BaseBand_Config_PHY_REG\n"); + } +//#endif // #if (HAL_CODE_BASE != RTL8192_S) + return RT_STATUS_SUCCESS; +} + + +//use in phy only +static RT_STATUS +phy_BB8192S_Config_ParaFile(struct net_device* dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + RT_STATUS rtStatus = RT_STATUS_SUCCESS; + //u8 u2RegValue; + //u16 u4RegValue; + //char szBBRegFile[] = RTL819X_PHY_REG; + //char szBBRegFile1T2R[] = RTL819X_PHY_REG_1T2R; + //char szBBRegPgFile[] = RTL819X_PHY_REG_PG; + //char szAGCTableFile[] = RTL819X_AGC_TAB; + //char szBBRegto1T1RFile[] = RTL819X_PHY_REG_to1T1R; + //char szBBRegto1T2RFile[] = RTL819X_PHY_REG_to1T2R; + + RT_TRACE(COMP_INIT, "==>phy_BB8192S_Config_ParaFile\n"); + + // + // 1. Read PHY_REG.TXT BB INIT!! + // We will seperate as 1T1R/1T2R/1T2R_GREEN/2T2R + // +#if RTL8190_Download_Firmware_From_Header + if (priv->rf_type == RF_1T2R || priv->rf_type == RF_2T2R || + priv->rf_type == RF_1T1R ||priv->rf_type == RF_2T2R_GREEN) + { + rtStatus = phy_ConfigBBWithHeaderFile(dev,BaseBand_Config_PHY_REG); + if(priv->rf_type != RF_2T2R && priv->rf_type != RF_2T2R_GREEN) + {//2008.11.10 Added by tynli. The default PHY_REG.txt we read is for 2T2R, + //so we should reconfig BB reg with the right PHY parameters. + rtStatus = phy_SetBBtoDiffRFWithHeaderFile(dev,BaseBand_Config_PHY_REG); + } + }else + rtStatus = RT_STATUS_FAILURE; +#else + RT_TRACE(COMP_INIT, "RF_Type == %d\n", priv->rf_type); + // No matter what kind of RF we always read PHY_REG.txt. We must copy different + // type of parameter files to phy_reg.txt at first. + if (priv->rf_type == RF_1T2R || priv->rf_type == RF_2T2R || + priv->rf_type == RF_1T1R ||priv->rf_type == RF_2T2R_GREEN) + { + rtStatus = phy_ConfigBBWithParaFile(dev, (char* )&szBBRegFile); + if(priv->rf_type != RF_2T2R && priv->rf_type != RF_2T2R_GREEN) + {//2008.11.10 Added by tynli. The default PHY_REG.txt we read is for 2T2R, + //so we should reconfig BB reg with the right PHY parameters. + if(priv->rf_type == RF_1T1R) + rtStatus = phy_SetBBtoDiffRFWithParaFile(dev, (char* )&szBBRegto1T1RFile); + else if(priv->rf_type == RF_1T2R) + rtStatus = phy_SetBBtoDiffRFWithParaFile(dev, (char* )&szBBRegto1T2RFile); + } + + }else + rtStatus = RT_STATUS_FAILURE; +#endif + + if(rtStatus != RT_STATUS_SUCCESS){ + RT_TRACE(COMP_INIT, "phy_BB8192S_Config_ParaFile():Write BB Reg Fail!!"); + goto phy_BB8190_Config_ParaFile_Fail; + } + + // + // 2. If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt + // + if (priv->AutoloadFailFlag == false) + { +#if RTL8190_Download_Firmware_From_Header + rtStatus = phy_ConfigBBWithPgHeaderFile(dev,BaseBand_Config_PHY_REG); +#else + rtStatus = phy_ConfigBBWithPgParaFile(dev, (char* )&szBBRegPgFile); +#endif + } + if(rtStatus != RT_STATUS_SUCCESS){ + RT_TRACE(COMP_INIT, "phy_BB8192S_Config_ParaFile():BB_PG Reg Fail!!"); + goto phy_BB8190_Config_ParaFile_Fail; + } + + // + // 3. BB AGC table Initialization + // +#if RTL8190_Download_Firmware_From_Header + rtStatus = phy_ConfigBBWithHeaderFile(dev,BaseBand_Config_AGC_TAB); +#else + RT_TRACE(COMP_INIT, "phy_BB8192S_Config_ParaFile AGC_TAB.txt\n"); + rtStatus = phy_ConfigBBWithParaFile(Adapter, (char* )&szAGCTableFile); +#endif + + if(rtStatus != RT_STATUS_SUCCESS){ + printk( "phy_BB8192S_Config_ParaFile():AGC Table Fail\n"); + goto phy_BB8190_Config_ParaFile_Fail; + } + + +#if 0 // 2008/08/18 MH Disable for 92SE + if(pHalData->VersionID > VERSION_8190_BD) + { + //if(pHalData->RF_Type == RF_2T4R) + //{ + // Antenna gain offset from B/C/D to A + u4RegValue = ( pHalData->AntennaTxPwDiff[2]<<8 | + pHalData->AntennaTxPwDiff[1]<<4 | + pHalData->AntennaTxPwDiff[0]); + //} + //else + //u4RegValue = 0; + + PHY_SetBBReg(dev, rFPGA0_TxGainStage, + (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue); + + // CrystalCap + // Simulate 8192??? + u4RegValue = pHalData->CrystalCap; + PHY_SetBBReg(dev, rFPGA0_AnalogParameter1, bXtalCap92x, u4RegValue); + // Simulate 8190?? + //u4RegValue = ((pHalData->CrystalCap & 0xc)>>2); // bit2~3 of crystal cap + //PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, bXtalCap23, u4RegValue); + + } +#endif + + // Check if the CCK HighPower is turned ON. + // This is used to calculate PWDB. + priv->bCckHighPower = (bool)(rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, 0x200)); + + +phy_BB8190_Config_ParaFile_Fail: + return rtStatus; +} + +/*----------------------------------------------------------------------------- + * Function: phy_ConfigMACWithHeaderFile() + * + * Overview: This function read BB parameters from Header file we gen, and do register + * Read/Write + * + * Input: PADAPTER Adapter + * char* pFileName + * + * Output: NONE + * + * Return: RT_STATUS_SUCCESS: configuration file exist + * + * Note: The format of MACPHY_REG.txt is different from PHY and RF. + * [Register][Mask][Value] + *---------------------------------------------------------------------------*/ +//use in phy only +static RT_STATUS +phy_ConfigMACWithHeaderFile(struct net_device* dev) +{ + u32 i = 0; + u32 ArrayLength = 0; + u32* ptrArray; + //struct r8192_priv *priv = ieee80211_priv(dev); + +//#if (HAL_CODE_BASE != RTL8192_S) + /*if(Adapter->bInHctTest) + { + RT_TRACE(COMP_INIT, DBG_LOUD, ("Rtl819XMACPHY_ArrayDTM\n")); + ArrayLength = MACPHY_ArrayLengthDTM; + ptrArray = Rtl819XMACPHY_ArrayDTM; + } + else if(pHalData->bTXPowerDataReadFromEEPORM) + { +// RT_TRACE(COMP_INIT, DBG_LOUD, ("Rtl819XMACPHY_Array_PG\n")); +// ArrayLength = MACPHY_Array_PGLength; +// ptrArray = Rtl819XMACPHY_Array_PG; + + }else*/ + { //2008.11.06 Modified by tynli. + RT_TRACE(COMP_INIT, "Read Rtl819XMACPHY_Array\n"); + ArrayLength = MAC_2T_ArrayLength; + ptrArray = Rtl819XMAC_Array; + } + + /*for(i = 0 ;i < ArrayLength;i=i+3){ + RT_TRACE(COMP_SEND, DBG_LOUD, ("The Rtl819XMACPHY_Array[0] is %lx Rtl819XMACPHY_Array[1] is %lx Rtl819XMACPHY_Array[2] is %lx\n",ptrArray[i], ptrArray[i+1], ptrArray[i+2])); + if(ptrArray[i] == 0x318) + { + ptrArray[i+2] = 0x00000800; + //DbgPrint("ptrArray[i], ptrArray[i+1], ptrArray[i+2] = %x, %x, %x\n", + // ptrArray[i], ptrArray[i+1], ptrArray[i+2]); + } + PHY_SetBBReg(Adapter, ptrArray[i], ptrArray[i+1], ptrArray[i+2]); + }*/ + for(i = 0 ;i < ArrayLength;i=i+2){ // Add by tynli for 2 column + write_nic_byte(dev, ptrArray[i], (u8)ptrArray[i+1]); + } +//#endif + return RT_STATUS_SUCCESS; +} + +/*----------------------------------------------------------------------------- + * Function: phy_ConfigBBWithHeaderFile() + * + * Overview: This function read BB parameters from general file format, and do register + * Read/Write + * + * Input: PADAPTER Adapter + * u8 ConfigType 0 => PHY_CONFIG + * 1 =>AGC_TAB + * + * Output: NONE + * + * Return: RT_STATUS_SUCCESS: configuration file exist + * + *---------------------------------------------------------------------------*/ +//use in phy only +static RT_STATUS +phy_ConfigBBWithHeaderFile(struct net_device* dev,u8 ConfigType) +{ + int i; + //u8 ArrayLength; + u32* Rtl819XPHY_REGArray_Table; + u32* Rtl819XAGCTAB_Array_Table; + u16 PHY_REGArrayLen, AGCTAB_ArrayLen; + //struct r8192_priv *priv = ieee80211_priv(dev); +//#if (HAL_CODE_BASE != RTL8192_S) + /*if(Adapter->bInHctTest) + { + + AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM; + Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM; + + if(pHalData->RF_Type == RF_2T4R) + { + PHY_REGArrayLen = PHY_REGArrayLengthDTM; + Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArrayDTM; + } + else if (pHalData->RF_Type == RF_1T2R) + { + PHY_REGArrayLen = PHY_REG_1T2RArrayLengthDTM; + Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArrayDTM; + } + + } + else + */ + //{ + // + // 2008.11.06 Modified by tynli. + // + AGCTAB_ArrayLen = AGCTAB_ArrayLength; + Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array; + PHY_REGArrayLen = PHY_REG_2T2RArrayLength; // Default RF_type: 2T2R + Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_Array; + //} + + if(ConfigType == BaseBand_Config_PHY_REG) + { + for(i=0;i<PHY_REGArrayLen;i=i+2) + { + if (Rtl819XPHY_REGArray_Table[i] == 0xfe) + mdelay(50); + else if (Rtl819XPHY_REGArray_Table[i] == 0xfd) + mdelay(5); + else if (Rtl819XPHY_REGArray_Table[i] == 0xfc) + mdelay(1); + else if (Rtl819XPHY_REGArray_Table[i] == 0xfb) + udelay(50); + else if (Rtl819XPHY_REGArray_Table[i] == 0xfa) + udelay(5); + else if (Rtl819XPHY_REGArray_Table[i] == 0xf9) + udelay(1); + rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table[i], bMaskDWord, Rtl819XPHY_REGArray_Table[i+1]); + //RT_TRACE(COMP_SEND, "The Rtl819XPHY_REGArray_Table[0] is %lx Rtl819XPHY_REGArray[1] is %lx \n",Rtl819XPHY_REGArray_Table[i], Rtl819XPHY_REGArray_Table[i+1]); + + } + } + else if(ConfigType == BaseBand_Config_AGC_TAB){ + for(i=0;i<AGCTAB_ArrayLen;i=i+2) + { + rtl8192_setBBreg(dev, Rtl819XAGCTAB_Array_Table[i], bMaskDWord, Rtl819XAGCTAB_Array_Table[i+1]); + } + } +//#endif // #if (HAL_CODE_BASE != RTL8192_S) + return RT_STATUS_SUCCESS; +} + +/*----------------------------------------------------------------------------- + * Function: phy_ConfigBBWithPgHeaderFile + * + * Overview: Config PHY_REG_PG array + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 11/06/2008 MHC Add later!!!!!!.. Please modify for new files!!!! + * 11/10/2008 tynli Modify to mew files. + //use in phy only + *---------------------------------------------------------------------------*/ +static RT_STATUS +phy_ConfigBBWithPgHeaderFile(struct net_device* dev,u8 ConfigType) +{ + int i; + //u8 ArrayLength; + u32* Rtl819XPHY_REGArray_Table_PG; + u16 PHY_REGArrayPGLen; + //struct r8192_priv *priv = ieee80211_priv(dev); +//#if (HAL_CODE_BASE != RTL8192_S) + // Default: pHalData->RF_Type = RF_2T2R. + + PHY_REGArrayPGLen = PHY_REG_Array_PGLength; + Rtl819XPHY_REGArray_Table_PG = Rtl819XPHY_REG_Array_PG; + + if(ConfigType == BaseBand_Config_PHY_REG) + { + for(i=0;i<PHY_REGArrayPGLen;i=i+3) + { + if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfe) + mdelay(50); + else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfd) + mdelay(5); + else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfc) + mdelay(1); + else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfb) + udelay(50); + else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfa) + udelay(5); + else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xf9) + udelay(1); + rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1], Rtl819XPHY_REGArray_Table_PG[i+2]); + //RT_TRACE(COMP_SEND, "The Rtl819XPHY_REGArray_Table_PG[0] is %lx Rtl819XPHY_REGArray_Table_PG[1] is %lx \n", + // Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1]); + } + }else{ + RT_TRACE(COMP_SEND, "phy_ConfigBBWithPgHeaderFile(): ConfigType != BaseBand_Config_PHY_REG\n"); + } + return RT_STATUS_SUCCESS; + +} /* phy_ConfigBBWithPgHeaderFile */ + +/*----------------------------------------------------------------------------- + * Function: PHY_ConfigRFWithHeaderFile() + * + * Overview: This function read RF parameters from general file format, and do RF 3-wire + * + * Input: PADAPTER Adapter + * char* pFileName + * RF90_RADIO_PATH_E eRFPath + * + * Output: NONE + * + * Return: RT_STATUS_SUCCESS: configuration file exist + * + * Note: Delay may be required for RF configuration + *---------------------------------------------------------------------------*/ +//in 8256 phy_RF8256_Config_ParaFile only +//RT_STATUS PHY_ConfigRFWithHeaderFile(struct net_device* dev,RF90_RADIO_PATH_E eRFPath) +u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E eRFPath) +{ + + struct r8192_priv *priv = ieee80211_priv(dev); + int i; + //u32* pRFArray; + RT_STATUS rtStatus = RT_STATUS_SUCCESS; + u32 *Rtl819XRadioA_Array_Table; + u32 *Rtl819XRadioB_Array_Table; + //u32* Rtl819XRadioC_Array_Table; + //u32* Rtl819XRadioD_Array_Table; + u16 RadioA_ArrayLen,RadioB_ArrayLen; + + { //2008.11.06 Modified by tynli + RadioA_ArrayLen = RadioA_1T_ArrayLength; + Rtl819XRadioA_Array_Table=Rtl819XRadioA_Array; + Rtl819XRadioB_Array_Table=Rtl819XRadioB_Array; + RadioB_ArrayLen = RadioB_ArrayLength; + } + + if( priv->rf_type == RF_2T2R_GREEN ) + { + Rtl819XRadioB_Array_Table = Rtl819XRadioB_GM_Array; + RadioB_ArrayLen = RadioB_GM_ArrayLength; + } + else + { + Rtl819XRadioB_Array_Table = Rtl819XRadioB_Array; + RadioB_ArrayLen = RadioB_ArrayLength; + } + + rtStatus = RT_STATUS_SUCCESS; + + // When initialization, we want the delay function(mdelay(), delay_us() + // ==> actually we call PlatformStallExecution()) to do NdisStallExecution() + // [busy wait] instead of NdisMSleep(). So we acquire RT_INITIAL_SPINLOCK + // to run at Dispatch level to achive it. + //cosa PlatformAcquireSpinLock(Adapter, RT_INITIAL_SPINLOCK); + + switch(eRFPath){ + case RF90_PATH_A: + for(i = 0;i<RadioA_ArrayLen; i=i+2){ + if(Rtl819XRadioA_Array_Table[i] == 0xfe) + { // Deay specific ms. Only RF configuration require delay. +//#if (DEV_BUS_TYPE == USB_INTERFACE) +#ifdef RTL8192SU + mdelay(1000); +#else + mdelay(50); +#endif + } + else if (Rtl819XRadioA_Array_Table[i] == 0xfd) + mdelay(5); + else if (Rtl819XRadioA_Array_Table[i] == 0xfc) + mdelay(1); + else if (Rtl819XRadioA_Array_Table[i] == 0xfb) + udelay(50); + //PlatformStallExecution(50); + else if (Rtl819XRadioA_Array_Table[i] == 0xfa) + udelay(5); + else if (Rtl819XRadioA_Array_Table[i] == 0xf9) + udelay(1); + else + { + rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioA_Array_Table[i], bRFRegOffsetMask, Rtl819XRadioA_Array_Table[i+1]); + } + } + break; + case RF90_PATH_B: + for(i = 0;i<RadioB_ArrayLen; i=i+2){ + if(Rtl819XRadioB_Array_Table[i] == 0xfe) + { // Deay specific ms. Only RF configuration require delay. +//#if (DEV_BUS_TYPE == USB_INTERFACE) +#ifdef RTL8192SU + mdelay(1000); +#else + mdelay(50); +#endif + } + else if (Rtl819XRadioB_Array_Table[i] == 0xfd) + mdelay(5); + else if (Rtl819XRadioB_Array_Table[i] == 0xfc) + mdelay(1); + else if (Rtl819XRadioB_Array_Table[i] == 0xfb) + udelay(50); + else if (Rtl819XRadioB_Array_Table[i] == 0xfa) + udelay(5); + else if (Rtl819XRadioB_Array_Table[i] == 0xf9) + udelay(1); + else + { + rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioB_Array_Table[i], bRFRegOffsetMask, Rtl819XRadioB_Array_Table[i+1]); + } + } + break; + case RF90_PATH_C: + break; + case RF90_PATH_D: + break; + default: + break; + } + + return rtStatus; + +} + +/*----------------------------------------------------------------------------- + * Function: PHY_CheckBBAndRFOK() + * + * Overview: This function is write register and then readback to make sure whether + * BB[PHY0, PHY1], RF[Patha, path b, path c, path d] is Ok + * + * Input: PADAPTER Adapter + * HW90_BLOCK_E CheckBlock + * RF90_RADIO_PATH_E eRFPath // it is used only when CheckBlock is HW90_BLOCK_RF + * + * Output: NONE + * + * Return: RT_STATUS_SUCCESS: PHY is OK + * + * Note: This function may be removed in the ASIC + *---------------------------------------------------------------------------*/ +//in 8256 phy_RF8256_Config_HardCode +//but we don't use it temp +RT_STATUS +PHY_CheckBBAndRFOK( + struct net_device* dev, + HW90_BLOCK_E CheckBlock, + RF90_RADIO_PATH_E eRFPath + ) +{ + //struct r8192_priv *priv = ieee80211_priv(dev); + RT_STATUS rtStatus = RT_STATUS_SUCCESS; + u32 i, CheckTimes = 4,ulRegRead = 0; + u32 WriteAddr[4]; + u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f}; + + // Initialize register address offset to be checked + WriteAddr[HW90_BLOCK_MAC] = 0x100; + WriteAddr[HW90_BLOCK_PHY0] = 0x900; + WriteAddr[HW90_BLOCK_PHY1] = 0x800; + WriteAddr[HW90_BLOCK_RF] = 0x3; + + for(i=0 ; i < CheckTimes ; i++) + { + + // + // Write Data to register and readback + // + switch(CheckBlock) + { + case HW90_BLOCK_MAC: + //RT_ASSERT(FALSE, ("PHY_CheckBBRFOK(): Never Write 0x100 here!")); + RT_TRACE(COMP_INIT, "PHY_CheckBBRFOK(): Never Write 0x100 here!\n"); + break; + + case HW90_BLOCK_PHY0: + case HW90_BLOCK_PHY1: + write_nic_dword(dev, WriteAddr[CheckBlock], WriteData[i]); + ulRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]); + break; + + case HW90_BLOCK_RF: + // When initialization, we want the delay function(mdelay(), delay_us() + // ==> actually we call PlatformStallExecution()) to do NdisStallExecution() + // [busy wait] instead of NdisMSleep(). So we acquire RT_INITIAL_SPINLOCK + // to run at Dispatch level to achive it. + //cosa PlatformAcquireSpinLock(dev, RT_INITIAL_SPINLOCK); + WriteData[i] &= 0xfff; + rtl8192_phy_SetRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bRFRegOffsetMask, WriteData[i]); + // TODO: we should not delay for such a long time. Ask SD3 + mdelay(10); + ulRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMaskDWord); + mdelay(10); + //cosa PlatformReleaseSpinLock(dev, RT_INITIAL_SPINLOCK); + break; + + default: + rtStatus = RT_STATUS_FAILURE; + break; + } + + + // + // Check whether readback data is correct + // + if(ulRegRead != WriteData[i]) + { + //RT_TRACE(COMP_FPGA, ("ulRegRead: %x, WriteData: %x \n", ulRegRead, WriteData[i])); + RT_TRACE(COMP_ERR, "read back error(read:%x, write:%x)\n", ulRegRead, WriteData[i]); + rtStatus = RT_STATUS_FAILURE; + break; + } + } + + return rtStatus; +} + +//no use temp in windows driver +#ifdef TO_DO_LIST +void +PHY_SetRFPowerState8192SUsb( + struct net_device* dev, + RF_POWER_STATE RFPowerState + ) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + bool WaitShutDown = FALSE; + u32 DWordContent; + //RF90_RADIO_PATH_E eRFPath; + u8 eRFPath; + BB_REGISTER_DEFINITION_T *pPhyReg; + + if(priv->SetRFPowerStateInProgress == TRUE) + return; + + priv->SetRFPowerStateInProgress = TRUE; + + // TODO: Emily, 2006.11.21, we should rewrite this function + + if(RFPowerState==RF_SHUT_DOWN) + { + RFPowerState=RF_OFF; + WaitShutDown=TRUE; + } + + + priv->RFPowerState = RFPowerState; + switch( priv->rf_chip ) + { + case RF_8225: + case RF_6052: + switch( RFPowerState ) + { + case RF_ON: + break; + + case RF_SLEEP: + break; + + case RF_OFF: + break; + } + break; + + case RF_8256: + switch( RFPowerState ) + { + case RF_ON: + break; + + case RF_SLEEP: + break; + + case RF_OFF: + for(eRFPath=(RF90_RADIO_PATH_E)RF90_PATH_A; eRFPath < RF90_PATH_MAX; eRFPath++) + { + if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) + continue; + + pPhyReg = &priv->PHYRegDef[eRFPath]; + rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, bRFSI_RFENV); + rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0); + } + break; + } + break; + + case RF_8258: + break; + }// switch( priv->rf_chip ) + + priv->SetRFPowerStateInProgress = FALSE; +} +#endif + +#ifdef RTL8192U +//no use temp in windows driver +void +PHY_UpdateInitialGain( + struct net_device* dev + ) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + //unsigned char *IGTable; + //u8 DIG_CurrentInitialGain = 4; + + switch(priv->rf_chip) + { + case RF_8225: + break; + case RF_8256: + break; + case RF_8258: + break; + case RF_PSEUDO_11N: + break; + case RF_6052: + break; + default: + RT_TRACE(COMP_DBG, "PHY_UpdateInitialGain(): unknown rf_chip: %#X\n", priv->rf_chip); + break; + } +} +#endif + +//YJ,modified,090107 +void PHY_GetHWRegOriginalValue(struct net_device* dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + + // read tx power offset + // Simulate 8192 + priv->MCSTxPowerLevelOriginalOffset[0] = + rtl8192_QueryBBReg(dev, rTxAGC_Rate18_06, bMaskDWord); + priv->MCSTxPowerLevelOriginalOffset[1] = + rtl8192_QueryBBReg(dev, rTxAGC_Rate54_24, bMaskDWord); + priv->MCSTxPowerLevelOriginalOffset[2] = + rtl8192_QueryBBReg(dev, rTxAGC_Mcs03_Mcs00, bMaskDWord); + priv->MCSTxPowerLevelOriginalOffset[3] = + rtl8192_QueryBBReg(dev, rTxAGC_Mcs07_Mcs04, bMaskDWord); + priv->MCSTxPowerLevelOriginalOffset[4] = + rtl8192_QueryBBReg(dev, rTxAGC_Mcs11_Mcs08, bMaskDWord); + priv->MCSTxPowerLevelOriginalOffset[5] = + rtl8192_QueryBBReg(dev, rTxAGC_Mcs15_Mcs12, bMaskDWord); + + // Read CCK offset + priv->MCSTxPowerLevelOriginalOffset[6] = + rtl8192_QueryBBReg(dev, rTxAGC_CCK_Mcs32, bMaskDWord); + RT_TRACE(COMP_INIT, "Legacy OFDM =%08x/%08x HT_OFDM=%08x/%08x/%08x/%08x\n", + priv->MCSTxPowerLevelOriginalOffset[0], priv->MCSTxPowerLevelOriginalOffset[1] , + priv->MCSTxPowerLevelOriginalOffset[2], priv->MCSTxPowerLevelOriginalOffset[3] , + priv->MCSTxPowerLevelOriginalOffset[4], priv->MCSTxPowerLevelOriginalOffset[5] ); + + // read rx initial gain + priv->DefaultInitialGain[0] = rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bMaskByte0); + priv->DefaultInitialGain[1] = rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bMaskByte0); + priv->DefaultInitialGain[2] = rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bMaskByte0); + priv->DefaultInitialGain[3] = rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bMaskByte0); + RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n", + priv->DefaultInitialGain[0], priv->DefaultInitialGain[1], + priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]); + + // read framesync + priv->framesync = rtl8192_QueryBBReg(dev, rOFDM0_RxDetector3, bMaskByte0); + priv->framesyncC34 = rtl8192_QueryBBReg(dev, rOFDM0_RxDetector2, bMaskDWord); + RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n", + rOFDM0_RxDetector3, priv->framesync); +} +//YJ,modified,090107,end + + + +/** +* Function: phy_InitBBRFRegisterDefinition +* +* OverView: Initialize Register definition offset for Radio Path A/B/C/D +* +* Input: +* PADAPTER Adapter, +* +* Output: None +* Return: None +* Note: The initialization value is constant and it should never be changes +*/ +//use in phy only +static void phy_InitBBRFRegisterDefinition( struct net_device* dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + + // RF Interface Sowrtware Control + priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870 + priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) + priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 LSBs if read 32-bit from 0x874 + priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) + + // RF Interface Readback Value + priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0 + priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) + priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 LSBs if read 32-bit from 0x8E4 + priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) + + // RF Interface Output (and Enable) + priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860 + priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x864 + priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x868 + priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x86C + + // RF Interface (Output and) Enable + priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) + priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) + priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A) + priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E) + + //Addr of LSSI. Wirte RF register by driver + priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter + priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; + priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter; + priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter; + + // RF parameter + priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; //BB Band Select + priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter; + priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter; + priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter; + + // Tx AGC Gain Stage (same for all path. Should we remove this?) + priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage + priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage + priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage + priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage + + // Tranceiver A~D HSSI Parameter-1 + priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; //wire control parameter1 + priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; //wire control parameter1 + priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1; //wire control parameter1 + priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1; //wire control parameter1 + + // Tranceiver A~D HSSI Parameter-2 + priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; //wire control parameter2 + priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; //wire control parameter2 + priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2; //wire control parameter2 + priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; //wire control parameter1 + + // RF switch Control + priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; //TR/Ant switch control + priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl; + priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl; + priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl; + + // AGC control 1 + priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1; + priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1; + priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1; + priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1; + + // AGC control 2 + priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2; + priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2; + priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2; + priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2; + + // RX AFE control 1 + priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance; + priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance; + priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance; + priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance; + + // RX AFE control 1 + priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE; + priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE; + priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE; + priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE; + + // Tx AFE control 1 + priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance; + priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance; + priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance; + priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance; + + // Tx AFE control 2 + priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE; + priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE; + priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE; + priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE; + + // Tranceiver LSSI Readback SI mode + priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack; + priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack; + priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack; + priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack; + + // Tranceiver LSSI Readback PI mode + priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback; + priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback; + //pHalData->PHYRegDef[RF90_PATH_C].rfLSSIReadBackPi = rFPGA0_XC_LSSIReadBack; + //pHalData->PHYRegDef[RF90_PATH_D].rfLSSIReadBackPi = rFPGA0_XD_LSSIReadBack; + +} + + +// +// Description: Change RF power state. +// +// Assumption: This function must be executed in re-schdulable context, +// ie. PASSIVE_LEVEL. +// +// 050823, by rcnjko. +//not understand it seem's use in init +//SetHwReg8192SUsb--->HalFunc.SetHwRegHandler +bool PHY_SetRFPowerState(struct net_device* dev, RT_RF_POWER_STATE eRFPowerState) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + bool bResult = FALSE; + + RT_TRACE(COMP_RF, "---------> PHY_SetRFPowerState(): eRFPowerState(%d)\n", eRFPowerState); + + if(eRFPowerState == priv->ieee80211->eRFPowerState) + { + RT_TRACE(COMP_RF, "<--------- PHY_SetRFPowerState(): discard the request for eRFPowerState(%d) is the same.\n", eRFPowerState); + return bResult; + } + + bResult = phy_SetRFPowerState8192SU(dev, eRFPowerState); + + RT_TRACE(COMP_RF, "<--------- PHY_SetRFPowerState(): bResult(%d)\n", bResult); + + return bResult; +} + +//use in phy only +static bool phy_SetRFPowerState8192SU(struct net_device* dev,RT_RF_POWER_STATE eRFPowerState) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + bool bResult = TRUE; + //u8 eRFPath; + //u8 i, QueueID; + u8 u1bTmp; + + if(priv->SetRFPowerStateInProgress == TRUE) + return FALSE; + + priv->SetRFPowerStateInProgress = TRUE; + + switch(priv->rf_chip ) + { + default: + switch( eRFPowerState ) + { + case eRfOn: + write_nic_dword(dev, WFM5, FW_BB_RESET_ENABLE); + write_nic_word(dev, CMDR, 0x37FC); + write_nic_byte(dev, PHY_CCA, 0x3); + write_nic_byte(dev, TXPAUSE, 0x00); + write_nic_byte(dev, SPS1_CTRL, 0x64); + break; + + // + // In current solution, RFSleep=RFOff in order to save power under 802.11 power save. + // By Bruce, 2008-01-16. + // + case eRfSleep: + case eRfOff: + if (priv->ieee80211->eRFPowerState == eRfSleep || priv->ieee80211->eRFPowerState == eRfOff) + break; +#ifdef NOT_YET + // Make sure BusyQueue is empty befor turn off RFE pwoer. + for(QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) + { + if(RTIsListEmpty(&Adapter->TcbBusyQueue[QueueID])) + { + QueueID++; + continue; + } + else + { + RT_TRACE(COMP_POWER, "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n", (i+1), QueueID); + udelay(10); + i++; + } + + if(i >= MAX_DOZE_WAITING_TIMES_9x) + { + RT_TRACE(COMP_POWER, "\n\n\n SetZebraRFPowerState8185B(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n\n\n", MAX_DOZE_WAITING_TIMES_9x, QueueID); + break; + } + } +#endif + // + //RF Off/Sleep sequence. Designed/tested from SD4 Scott, SD1 Grent and Jonbon. + // Added by Bruce, 2008-11-22. + // + //================================================================== + // (0) Disable FW BB reset checking + write_nic_dword(dev, WFM5, FW_BB_RESET_DISABLE); + + // (1) Switching Power Supply Register : Disable LD12 & SW12 (for IT) + u1bTmp = read_nic_byte(dev, LDOV12D_CTRL); + u1bTmp |= BIT0; + write_nic_byte(dev, LDOV12D_CTRL, u1bTmp); + + write_nic_byte(dev, SPS1_CTRL, 0x0); + write_nic_byte(dev, TXPAUSE, 0xFF); + + // (2) MAC Tx/Rx enable, BB enable, CCK/OFDM enable + write_nic_word(dev, CMDR, 0x77FC); + write_nic_byte(dev, PHY_CCA, 0x0); + udelay(100); + + write_nic_word(dev, CMDR, 0x37FC); + udelay(10); + + write_nic_word(dev, CMDR, 0x77FC); + udelay(10); + + // (3) Reset BB TRX blocks + write_nic_word(dev, CMDR, 0x57FC); + break; + + default: + bResult = FALSE; + //RT_ASSERT(FALSE, ("phy_SetRFPowerState8192SU(): unknow state to set: 0x%X!!!\n", eRFPowerState)); + break; + } + break; + + } + priv->ieee80211->eRFPowerState = eRFPowerState; +#ifdef TO_DO_LIST + if(bResult) + { + // Update current RF state variable. + priv->ieee80211->eRFPowerState = eRFPowerState; + + switch(priv->rf_chip ) + { + case RF_8256: + switch(priv->ieee80211->eRFPowerState) + { + case eRfOff: + // + //If Rf off reason is from IPS, Led should blink with no link, by Maddest 071015 + // + if(pMgntInfo->RfOffReason==RF_CHANGE_BY_IPS ) + { + dev->HalFunc.LedControlHandler(dev,LED_CTL_NO_LINK); + } + else + { + // Turn off LED if RF is not ON. + dev->HalFunc.LedControlHandler(dev, LED_CTL_POWER_OFF); + } + break; + + case eRfOn: + // Turn on RF we are still linked, which might happen when + // we quickly turn off and on HW RF. 2006.05.12, by rcnjko. + if( pMgntInfo->bMediaConnect == TRUE ) + { + dev->HalFunc.LedControlHandler(dev, LED_CTL_LINK); + } + else + { + // Turn off LED if RF is not ON. + dev->HalFunc.LedControlHandler(dev, LED_CTL_NO_LINK); + } + break; + + default: + // do nothing. + break; + }// Switch RF state + + break; + + default: + RT_TRACE(COMP_RF, "phy_SetRFPowerState8192SU(): Unknown RF type\n"); + break; + }// Switch rf_chip + } +#endif + priv->SetRFPowerStateInProgress = FALSE; + + return bResult; +} + +/*----------------------------------------------------------------------------- + * Function: GetTxPowerLevel8190() + * + * Overview: This function is export to "common" moudule + * + * Input: PADAPTER Adapter + * psByte Power Level + * + * Output: NONE + * + * Return: NONE + * + *---------------------------------------------------------------------------*/ + // no use temp + void +PHY_GetTxPowerLevel8192S( + struct net_device* dev, + long* powerlevel + ) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + u8 TxPwrLevel = 0; + long TxPwrDbm; + // + // Because the Tx power indexes are different, we report the maximum of them to + // meet the CCX TPC request. By Bruce, 2008-01-31. + // + + // CCK + TxPwrLevel = priv->CurrentCckTxPwrIdx; + TxPwrDbm = phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_B, TxPwrLevel); + + // Legacy OFDM + TxPwrLevel = priv->CurrentOfdm24GTxPwrIdx + priv->LegacyHTTxPowerDiff; + + // Compare with Legacy OFDM Tx power. + if(phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_G, TxPwrLevel) > TxPwrDbm) + TxPwrDbm = phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_G, TxPwrLevel); + + // HT OFDM + TxPwrLevel = priv->CurrentOfdm24GTxPwrIdx; + + // Compare with HT OFDM Tx power. + if(phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_N_24G, TxPwrLevel) > TxPwrDbm) + TxPwrDbm = phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_N_24G, TxPwrLevel); + + *powerlevel = TxPwrDbm; +} + +/*----------------------------------------------------------------------------- + * Function: SetTxPowerLevel8190() + * + * Overview: This function is export to "HalCommon" moudule + * + * Input: PADAPTER Adapter + * u1Byte channel + * + * Output: NONE + * + * Return: NONE + * 2008/11/04 MHC We remove EEPROM_93C56. + * We need to move CCX relative code to independet file. +* 2009/01/21 MHC Support new EEPROM format from SD3 requirement. + *---------------------------------------------------------------------------*/ + void PHY_SetTxPowerLevel8192S(struct net_device* dev, u8 channel) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(dev); + u8 powerlevel = (u8)EEPROM_Default_TxPower, powerlevelOFDM24G = 0x10; + s8 ant_pwr_diff = 0; + u32 u4RegValue; + u8 index = (channel -1); + // 2009/01/22 MH Add for new EEPROM format from SD3 + u8 pwrdiff[2] = {0}; + u8 ht20pwr[2] = {0}, ht40pwr[2] = {0}; + u8 rfpath = 0, rfpathnum = 2; + + if(priv->bTXPowerDataReadFromEEPORM == FALSE) + return; + + // + // Read predefined TX power index in EEPROM + // +// if(priv->epromtype == EPROM_93c46) + { +#ifdef EEPROM_OLD_FORMAT_SUPPORT + powerlevel = priv->TxPowerLevelCCK[index]; + powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[index]; +#else + // + // Mainly we use RF-A Tx Power to write the Tx Power registers, but the RF-B Tx + // Power must be calculated by the antenna diff. + // So we have to rewrite Antenna gain offset register here. + // Please refer to BB register 0x80c + // 1. For CCK. + // 2. For OFDM 1T or 2T + // + + // 1. CCK + powerlevel = priv->RfTxPwrLevelCck[0][index]; + + if (priv->rf_type == RF_1T2R || priv->rf_type == RF_1T1R) + { + // Read HT 40 OFDM TX power + powerlevelOFDM24G = priv->RfTxPwrLevelOfdm1T[0][index]; + // RF B HT OFDM pwr-RFA HT OFDM pwr + // Only one RF we need not to decide B <-> A pwr diff + + // Legacy<->HT pwr diff, we only care about path A. + + // We only assume 1T as RF path A + rfpathnum = 1; + ht20pwr[0] = ht40pwr[0] = priv->RfTxPwrLevelOfdm1T[0][index]; + } + else if (priv->rf_type == RF_2T2R) + { + // Read HT 40 OFDM TX power + powerlevelOFDM24G = priv->RfTxPwrLevelOfdm2T[0][index]; + // RF B HT OFDM pwr-RFA HT OFDM pwr + ant_pwr_diff = priv->RfTxPwrLevelOfdm2T[1][index] - + priv->RfTxPwrLevelOfdm2T[0][index]; + // RF B (HT OFDM pwr+legacy-ht-diff) -(RFA HT OFDM pwr+legacy-ht-diff) + // We can not handle Path B&A HT/Legacy pwr diff for 92S now. + + //RTPRINT(FPHY, PHY_TXPWR, ("CH-%d HT40 A/B Pwr index = %x/%x(%d/%d)\n", + //channel, priv->RfTxPwrLevelOfdm2T[0][index], + //priv->RfTxPwrLevelOfdm2T[1][index], + //priv->RfTxPwrLevelOfdm2T[0][index], + //priv->RfTxPwrLevelOfdm2T[1][index])); + + ht20pwr[0] = ht40pwr[0] = priv->RfTxPwrLevelOfdm2T[0][index]; + ht20pwr[1] = ht40pwr[1] = priv->RfTxPwrLevelOfdm2T[1][index]; + } + + // + // 2009/01/21 MH Support new EEPROM format from SD3 requirement + // 2009/02/10 Cosa, Here is only for reg B/C/D to A gain diff. + // + if (priv->EEPROMVersion == 2) // Defined by SD1 Jong + { + if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) + { + for (rfpath = 0; rfpath < rfpathnum; rfpath++) + { + // HT 20<->40 pwr diff + pwrdiff[rfpath] = priv->TxPwrHt20Diff[rfpath][index]; + + // Calculate Antenna pwr diff + if (pwrdiff[rfpath] < 8) // 0~+7 + { + #if 0//cosa, it doesn't need to add the offset here + if (rfpath == 0) + powerlevelOFDM24G += pwrdiff[rfpath]; + #endif + ht20pwr[rfpath] += pwrdiff[rfpath]; + } + else // index8-15=-8~-1 + { + #if 0//cosa, it doesn't need to add the offset here + if (rfpath == 0) + powerlevelOFDM24G -= (15-pwrdiff[rfpath]); + #endif + ht20pwr[rfpath] -= (15-pwrdiff[rfpath]); + } + } + + // RF B HT OFDM pwr-RFA HT OFDM pwr + if (priv->rf_type == RF_2T2R) + ant_pwr_diff = ht20pwr[1] - ht20pwr[0]; + + //RTPRINT(FPHY, PHY_TXPWR, + //("HT20 to HT40 pwrdiff[A/B]=%d/%d, ant_pwr_diff=%d(B-A=%d-%d)\n", + //pwrdiff[0], pwrdiff[1], ant_pwr_diff, ht20pwr[1], ht20pwr[0])); + } + + // Band Edge scheme is enabled for FCC mode + if (priv->TxPwrbandEdgeFlag == 1/* && pHalData->ChannelPlan == 0*/) + { + for (rfpath = 0; rfpath < rfpathnum; rfpath++) + { + pwrdiff[rfpath] = 0; + if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) + { + if (channel <= 3) + pwrdiff[rfpath] = priv->TxPwrbandEdgeHt40[rfpath][0]; + else if (channel >= 9) + pwrdiff[rfpath] = priv->TxPwrbandEdgeHt40[rfpath][1]; + else + pwrdiff[rfpath] = 0; + + ht40pwr[rfpath] -= pwrdiff[rfpath]; + } + else if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) + { + if (channel == 1) + pwrdiff[rfpath] = priv->TxPwrbandEdgeHt20[rfpath][0]; + else if (channel >= 11) + pwrdiff[rfpath] = priv->TxPwrbandEdgeHt20[rfpath][1]; + else + pwrdiff[rfpath] = 0; + + ht20pwr[rfpath] -= pwrdiff[rfpath]; + } + #if 0//cosa, it doesn't need to add the offset here + if (rfpath == 0) + powerlevelOFDM24G -= pwrdiff[rfpath]; + #endif + } + + if (priv->rf_type == RF_2T2R) + { + // HT 20/40 must decide if they need to minus BD pwr offset + if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) + ant_pwr_diff = ht40pwr[1] - ht40pwr[0]; + else + ant_pwr_diff = ht20pwr[1] - ht20pwr[0]; + } + if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) + { + if (channel <= 1 || channel >= 11) + { + //RTPRINT(FPHY, PHY_TXPWR, + //("HT20 Band-edge pwrdiff[A/B]=%d/%d, ant_pwr_diff=%d(B-A=%d-%d)\n", + //pwrdiff[0], pwrdiff[1], ant_pwr_diff, ht20pwr[1], ht20pwr[0])); + } + } + else + { + if (channel <= 3 || channel >= 9) + { + //RTPRINT(FPHY, PHY_TXPWR, + //("HT40 Band-edge pwrdiff[A/B]=%d/%d, ant_pwr_diff=%d(B-A=%d-%d)\n", + //pwrdiff[0], pwrdiff[1], ant_pwr_diff, ht40pwr[1], ht40pwr[0])); + } + } + } +#if 0//cosa, useless + // Read HT/Legacy OFDM diff + legacy_ant_pwr_diff= pHalData->TxPwrLegacyHtDiff[RF90_PATH_A][index]; +#endif + } + + //Cosa added for protection, the reg rFPGA0_TxGainStage + // range is from 7~-8, index = 0x0~0xf + if(ant_pwr_diff > 7) + ant_pwr_diff = 7; + if(ant_pwr_diff < -8) + ant_pwr_diff = -8; + + //RTPRINT(FPHY, PHY_TXPWR, + //("CCK/HT Power index = %x/%x(%d/%d), ant_pwr_diff=%d\n", + //powerlevel, powerlevelOFDM24G, powerlevel, powerlevelOFDM24G, ant_pwr_diff)); + + ant_pwr_diff &= 0xf; + + // Antenna TX power difference + priv->AntennaTxPwDiff[2] = 0;// RF-D, don't care + priv->AntennaTxPwDiff[1] = 0;// RF-C, don't care + priv->AntennaTxPwDiff[0] = (u8)(ant_pwr_diff); // RF-B + + // Antenna gain offset from B/C/D to A + u4RegValue = ( priv->AntennaTxPwDiff[2]<<8 | + priv->AntennaTxPwDiff[1]<<4 | + priv->AntennaTxPwDiff[0] ); + + // Notify Tx power difference for B/C/D to A!!! + rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue); +#endif + } + + // + // CCX 2 S31, AP control of client transmit power: + // 1. We shall not exceed Cell Power Limit as possible as we can. + // 2. Tolerance is +/- 5dB. + // 3. 802.11h Power Contraint takes higher precedence over CCX Cell Power Limit. + // + // TODO: + // 1. 802.11h power contraint + // + // 071011, by rcnjko. + // +#ifdef TODO //WB, 11h has not implemented now. + if( priv->ieee80211->iw_mode != IW_MODE_INFRA && priv->bWithCcxCellPwr && + channel == priv->ieee80211->current_network.channel)// & priv->ieee80211->mAssoc ) + { + u8 CckCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_B, priv->CcxCellPwr); + u8 LegacyOfdmCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_G, priv->CcxCellPwr); + u8 OfdmCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_N_24G, priv->CcxCellPwr); + + RT_TRACE(COMP_TXAGC, + ("CCX Cell Limit: %d dbm => CCK Tx power index : %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n", + priv->CcxCellPwr, CckCellPwrIdx, LegacyOfdmCellPwrIdx, OfdmCellPwrIdx)); + RT_TRACE(COMP_TXAGC, + ("EEPROM channel(%d) => CCK Tx power index: %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n", + channel, powerlevel, powerlevelOFDM24G + priv->LegacyHTTxPowerDiff, powerlevelOFDM24G)); + + // CCK + if(powerlevel > CckCellPwrIdx) + powerlevel = CckCellPwrIdx; + // Legacy OFDM, HT OFDM + if(powerlevelOFDM24G + priv->LegacyHTTxPowerDiff > LegacyOfdmCellPwrIdx) + { + if((OfdmCellPwrIdx - priv->LegacyHTTxPowerDiff) > 0) + { + powerlevelOFDM24G = OfdmCellPwrIdx - priv->LegacyHTTxPowerDiff; + } + else + { + powerlevelOFDM24G = 0; + } + } + + RT_TRACE(COMP_TXAGC, + ("Altered CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n", + powerlevel, powerlevelOFDM24G + priv->LegacyHTTxPowerDiff, powerlevelOFDM24G)); + } +#endif + + priv->CurrentCckTxPwrIdx = powerlevel; + priv->CurrentOfdm24GTxPwrIdx = powerlevelOFDM24G; + + switch(priv->rf_chip) + { + case RF_8225: + //PHY_SetRF8225CckTxPower(dev, powerlevel); + //PHY_SetRF8225OfdmTxPower(dev, powerlevelOFDM24G); + break; + + case RF_8256: +#if 0 + PHY_SetRF8256CCKTxPower(dev, powerlevel); + PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G); +#endif + break; + + case RF_6052: + PHY_RF6052SetCckTxPower(dev, powerlevel); + PHY_RF6052SetOFDMTxPower(dev, powerlevelOFDM24G); + break; + + case RF_8258: + break; + default: + break; + } + +} + +// +// Description: +// Update transmit power level of all channel supported. +// +// TODO: +// A mode. +// By Bruce, 2008-02-04. +// no use temp +bool PHY_UpdateTxPowerDbm8192S(struct net_device* dev, long powerInDbm) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + u8 idx; + u8 rf_path; + + // TODO: A mode Tx power. + u8 CckTxPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_B, powerInDbm); + u8 OfdmTxPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_N_24G, powerInDbm); + + if(OfdmTxPwrIdx - priv->LegacyHTTxPowerDiff > 0) + OfdmTxPwrIdx -= priv->LegacyHTTxPowerDiff; + else + OfdmTxPwrIdx = 0; + + for(idx = 0; idx < 14; idx++) + { + priv->TxPowerLevelCCK[idx] = CckTxPwrIdx; + priv->TxPowerLevelCCK_A[idx] = CckTxPwrIdx; + priv->TxPowerLevelCCK_C[idx] = CckTxPwrIdx; + priv->TxPowerLevelOFDM24G[idx] = OfdmTxPwrIdx; + priv->TxPowerLevelOFDM24G_A[idx] = OfdmTxPwrIdx; + priv->TxPowerLevelOFDM24G_C[idx] = OfdmTxPwrIdx; + + for (rf_path = 0; rf_path < 2; rf_path++) + { + priv->RfTxPwrLevelCck[rf_path][idx] = CckTxPwrIdx; + priv->RfTxPwrLevelOfdm1T[rf_path][idx] = \ + priv->RfTxPwrLevelOfdm2T[rf_path][idx] = OfdmTxPwrIdx; + } + } + + PHY_SetTxPowerLevel8192S(dev, priv->chan); + + return TRUE; +} + +/* + Description: + When beacon interval is changed, the values of the + hw registers should be modified. + By tynli, 2008.10.24. + +*/ + +extern void PHY_SetBeaconHwReg( struct net_device* dev, u16 BeaconInterval) +{ + u32 NewBeaconNum; + + NewBeaconNum = BeaconInterval *32 - 64; + //PlatformEFIOWrite4Byte(Adapter, WFM3+4, NewBeaconNum); + //PlatformEFIOWrite4Byte(Adapter, WFM3, 0xB026007C); + write_nic_dword(dev, WFM3+4, NewBeaconNum); + write_nic_dword(dev, WFM3, 0xB026007C); +} + +// +// Description: +// Map dBm into Tx power index according to +// current HW model, for example, RF and PA, and +// current wireless mode. +// By Bruce, 2008-01-29. +// use in phy only +static u8 phy_DbmToTxPwrIdx( + struct net_device* dev, + WIRELESS_MODE WirelessMode, + long PowerInDbm + ) +{ + //struct r8192_priv *priv = ieee80211_priv(dev); + u8 TxPwrIdx = 0; + long Offset = 0; + + + // + // Tested by MP, we found that CCK Index 0 equals to -7dbm, OFDM legacy equals to + // 3dbm, and OFDM HT equals to 0dbm repectively. + // Note: + // The mapping may be different by different NICs. Do not use this formula for what needs accurate result. + // By Bruce, 2008-01-29. + // + switch(WirelessMode) + { + case WIRELESS_MODE_B: + Offset = -7; + break; + + case WIRELESS_MODE_G: + case WIRELESS_MODE_N_24G: + Offset = -8; + break; + default: + break; + } + + if((PowerInDbm - Offset) > 0) + { + TxPwrIdx = (u8)((PowerInDbm - Offset) * 2); + } + else + { + TxPwrIdx = 0; + } + + // Tx Power Index is too large. + if(TxPwrIdx > MAX_TXPWR_IDX_NMODE_92S) + TxPwrIdx = MAX_TXPWR_IDX_NMODE_92S; + + return TxPwrIdx; +} +// +// Description: +// Map Tx power index into dBm according to +// current HW model, for example, RF and PA, and +// current wireless mode. +// By Bruce, 2008-01-29. +// use in phy only +static long phy_TxPwrIdxToDbm( + struct net_device* dev, + WIRELESS_MODE WirelessMode, + u8 TxPwrIdx + ) +{ + //struct r8192_priv *priv = ieee80211_priv(dev); + long Offset = 0; + long PwrOutDbm = 0; + + // + // Tested by MP, we found that CCK Index 0 equals to -7dbm, OFDM legacy equals to + // 3dbm, and OFDM HT equals to 0dbm repectively. + // Note: + // The mapping may be different by different NICs. Do not use this formula for what needs accurate result. + // By Bruce, 2008-01-29. + // + switch(WirelessMode) + { + case WIRELESS_MODE_B: + Offset = -7; + break; + + case WIRELESS_MODE_G: + case WIRELESS_MODE_N_24G: + Offset = -8; + break; + default: + break; + } + + PwrOutDbm = TxPwrIdx / 2 + Offset; // Discard the decimal part. + + return PwrOutDbm; +} + +#ifdef TO_DO_LIST +extern VOID +PHY_ScanOperationBackup8192S( + IN PADAPTER Adapter, + IN u1Byte Operation + ) +{ + + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + u4Byte BitMask; + u1Byte initial_gain; + + + + +#if(RTL8192S_DISABLE_FW_DM == 0) + + if(!Adapter->bDriverStopped) + { + switch(Operation) + { + case SCAN_OPT_BACKUP: + // + // <Roger_Notes> We halt FW DIG and disable high ppower both two DMs here + // and resume both two DMs while scan complete. + // 2008.11.27. + // + Adapter->HalFunc.SetFwCmdHandler(Adapter, FW_CMD_PAUSE_DM_BY_SCAN); + break; + + case SCAN_OPT_RESTORE: + // + // <Roger_Notes> We resume DIG and enable high power both two DMs here and + // recover earlier DIG settings. + // 2008.11.27. + // + Adapter->HalFunc.SetFwCmdHandler(Adapter, FW_CMD_RESUME_DM_BY_SCAN); + break; + + default: + RT_TRACE(COMP_SCAN, DBG_LOUD, ("Unknown Scan Backup Operation. \n")); + break; + } + } +#endif +} +#endif + +//nouse temp +void PHY_InitialGain8192S(struct net_device* dev,u8 Operation ) +{ + + //struct r8192_priv *priv = ieee80211_priv(dev); + //u32 BitMask; + //u8 initial_gain; + +#if 0 // For 8192s test disable + if(!dev->bDriverStopped) + { + switch(Operation) + { + case IG_Backup: + RT_TRACE(COMP_SCAN, DBG_LOUD, ("IG_Backup, backup the initial gain.\n")); + initial_gain = priv->DefaultInitialGain[0]; + BitMask = bMaskByte0; + if(DM_DigTable.Dig_Algorithm == DIG_ALGO_BY_FALSE_ALARM) + PHY_SetMacReg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF + pMgntInfo->InitGain_Backup.XAAGCCore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask); + pMgntInfo->InitGain_Backup.XBAGCCore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask); + pMgntInfo->InitGain_Backup.XCAGCCore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, BitMask); + pMgntInfo->InitGain_Backup.XDAGCCore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, BitMask); + BitMask = bMaskByte2; + pMgntInfo->InitGain_Backup.CCA = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, BitMask); + + RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan InitialGainBackup 0xc50 is %x\n",pMgntInfo->InitGain_Backup.XAAGCCore1)); + RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan InitialGainBackup 0xc58 is %x\n",pMgntInfo->InitGain_Backup.XBAGCCore1)); + RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan InitialGainBackup 0xc60 is %x\n",pMgntInfo->InitGain_Backup.XCAGCCore1)); + RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan InitialGainBackup 0xc68 is %x\n",pMgntInfo->InitGain_Backup.XDAGCCore1)); + RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan InitialGainBackup 0xa0a is %x\n",pMgntInfo->InitGain_Backup.CCA)); + + RT_TRACE(COMP_SCAN, DBG_LOUD, ("Write scan initial gain = 0x%x \n", initial_gain)); + write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain); + write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain); + write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain); + write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain); + break; + case IG_Restore: + RT_TRACE(COMP_SCAN, DBG_LOUD, ("IG_Restore, restore the initial gain.\n")); + BitMask = 0x7f; //Bit0~ Bit6 + if(DM_DigTable.Dig_Algorithm == DIG_ALGO_BY_FALSE_ALARM) + PHY_SetMacReg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF + + rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)pMgntInfo->InitGain_Backup.XAAGCCore1); + rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)pMgntInfo->InitGain_Backup.XBAGCCore1); + rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, (u32)pMgntInfo->InitGain_Backup.XCAGCCore1); + rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)pMgntInfo->InitGain_Backup.XDAGCCore1); + BitMask = (BIT22|BIT23); + rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, (u32)pMgntInfo->InitGain_Backup.CCA); + + RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan BBInitialGainRestore 0xc50 is %x\n",pMgntInfo->InitGain_Backup.XAAGCCore1)); + RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan BBInitialGainRestore 0xc58 is %x\n",pMgntInfo->InitGain_Backup.XBAGCCore1)); + RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan BBInitialGainRestore 0xc60 is %x\n",pMgntInfo->InitGain_Backup.XCAGCCore1)); + RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan BBInitialGainRestore 0xc68 is %x\n",pMgntInfo->InitGain_Backup.XDAGCCore1)); + RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan BBInitialGainRestore 0xa0a is %x\n",pMgntInfo->InitGain_Backup.CCA)); + + if(DM_DigTable.Dig_Algorithm == DIG_ALGO_BY_FALSE_ALARM) + PHY_SetMacReg(dev, UFWP, bMaskByte1, 0x1); // FW DIG ON + break; + default: + RT_TRACE(COMP_SCAN, DBG_LOUD, ("Unknown IG Operation. \n")); + break; + } + } +#endif +} + +/*----------------------------------------------------------------------------- + * Function: SetBWModeCallback8190Pci() + * + * Overview: Timer callback function for SetSetBWMode + * + * Input: PRT_TIMER pTimer + * + * Output: NONE + * + * Return: NONE + * + * Note: (1) We do not take j mode into consideration now + * (2) Will two workitem of "switch channel" and "switch channel bandwidth" run + * concurrently? + *---------------------------------------------------------------------------*/ +// use in phy only (in win it's timer) +void PHY_SetBWModeCallback8192S(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + u8 regBwOpMode; + + //return; + + // Added it for 20/40 mhz switch time evaluation by guangan 070531 + //u32 NowL, NowH; + //u8Byte BeginTime, EndTime; + u8 regRRSR_RSC; + + RT_TRACE(COMP_SWBW, "==>SetBWModeCallback8190Pci() Switch to %s bandwidth\n", \ + priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"); + + if(priv->rf_chip == RF_PSEUDO_11N) + { + priv->SetBWModeInProgress= FALSE; + return; + } + + if(!priv->up) + return; + + // Added it for 20/40 mhz switch time evaluation by guangan 070531 + //NowL = read_nic_dword(dev, TSFR); + //NowH = read_nic_dword(dev, TSFR+4); + //BeginTime = ((u8Byte)NowH << 32) + NowL; + + //3// + //3//<1>Set MAC register + //3// + regBwOpMode = read_nic_byte(dev, BW_OPMODE); + regRRSR_RSC = read_nic_byte(dev, RRSR+2); + + switch(priv->CurrentChannelBW) + { + case HT_CHANNEL_WIDTH_20: + //if(priv->card_8192_version >= VERSION_8192S_BCUT) + // write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x58); + + regBwOpMode |= BW_OPMODE_20MHZ; + // 2007/02/07 Mark by Emily becasue we have not verify whether this register works + write_nic_byte(dev, BW_OPMODE, regBwOpMode); + break; + + case HT_CHANNEL_WIDTH_20_40: + //if(priv->card_8192_version >= VERSION_8192S_BCUT) + // write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x18); + + regBwOpMode &= ~BW_OPMODE_20MHZ; + // 2007/02/07 Mark by Emily becasue we have not verify whether this register works + write_nic_byte(dev, BW_OPMODE, regBwOpMode); + regRRSR_RSC = (regRRSR_RSC&0x90) |(priv->nCur40MhzPrimeSC<<5); + write_nic_byte(dev, RRSR+2, regRRSR_RSC); + break; + + default: + RT_TRACE(COMP_DBG, "SetBWModeCallback8190Pci():\ + unknown Bandwidth: %#X\n",priv->CurrentChannelBW); + break; + } + + //3// + //3//<2>Set PHY related register + //3// + switch(priv->CurrentChannelBW) + { + /* 20 MHz channel*/ + case HT_CHANNEL_WIDTH_20: + rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); + rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0); + + // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207 + // It is set in Tx descriptor for 8192x series + //write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000); + //write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317); + //write_nic_dword(dev, rCCK0_DebugPort, 0x00000204); + #if 0 //LZM 090219 + rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskDWord, 0x1a1b0000); + rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, 0x090e1317); + rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskDWord, 0x00000204); + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00300000, 3); + #endif + + if (priv->card_8192_version >= VERSION_8192S_BCUT) + write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x58); + + + break; + + /* 40 MHz channel*/ + case HT_CHANNEL_WIDTH_20_40: + rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1); + rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1); + + // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207 + //write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000); + //write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e); + //write_nic_dword(dev, rCCK0_DebugPort, 0x00000409); + #if 0 //LZM 090219 + rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskDWord, 0x35360000); + rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, 0x121c252e); + rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskDWord, 0x00000409); + #endif + + // Set Control channel to upper or lower. These settings are required only for 40MHz + rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1)); + rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC); + + //rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00300000, 3); + if (priv->card_8192_version >= VERSION_8192S_BCUT) + write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x18); + + break; + + default: + RT_TRACE(COMP_DBG, "SetBWModeCallback8190Pci(): unknown Bandwidth: %#X\n"\ + ,priv->CurrentChannelBW); + break; + + } + //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315 + + // Added it for 20/40 mhz switch time evaluation by guangan 070531 + //NowL = read_nic_dword(dev, TSFR); + //NowH = read_nic_dword(dev, TSFR+4); + //EndTime = ((u8Byte)NowH << 32) + NowL; + //RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWModeCallback8190Pci: time of SetBWMode = %I64d us!\n", (EndTime - BeginTime))); + + //3<3>Set RF related register + switch( priv->rf_chip ) + { + case RF_8225: + //PHY_SetRF8225Bandwidth(dev, priv->CurrentChannelBW); + break; + + case RF_8256: + // Please implement this function in Hal8190PciPhy8256.c + //PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW); + break; + + case RF_8258: + // Please implement this function in Hal8190PciPhy8258.c + // PHY_SetRF8258Bandwidth(); + break; + + case RF_PSEUDO_11N: + // Do Nothing + break; + + case RF_6052: + PHY_RF6052SetBandwidth(dev, priv->CurrentChannelBW); + break; + default: + printk("Unknown rf_chip: %d\n", priv->rf_chip); + break; + } + + priv->SetBWModeInProgress= FALSE; + + RT_TRACE(COMP_SWBW, "<==SetBWModeCallback8190Pci() \n" ); +} + + + /*----------------------------------------------------------------------------- + * Function: SetBWMode8190Pci() + * + * Overview: This function is export to "HalCommon" moudule + * + * Input: PADAPTER Adapter + * HT_CHANNEL_WIDTH Bandwidth //20M or 40M + * + * Output: NONE + * + * Return: NONE + * + * Note: We do not take j mode into consideration now + *---------------------------------------------------------------------------*/ +//extern void PHY_SetBWMode8192S( struct net_device* dev, +// HT_CHANNEL_WIDTH Bandwidth, // 20M or 40M +// HT_EXTCHNL_OFFSET Offset // Upper, Lower, or Don't care +void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + HT_CHANNEL_WIDTH tmpBW = priv->CurrentChannelBW; + + + // Modified it for 20/40 mhz switch by guangan 070531 + + //return; + + //if(priv->SwChnlInProgress) +// if(pMgntInfo->bScanInProgress) +// { +// RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWMode8190Pci() %s Exit because bScanInProgress!\n", +// Bandwidth == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz")); +// return; +// } + +// if(priv->SetBWModeInProgress) +// { +// // Modified it for 20/40 mhz switch by guangan 070531 +// RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWMode8190Pci() %s cancel last timer because SetBWModeInProgress!\n", +// Bandwidth == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz")); +// PlatformCancelTimer(dev, &priv->SetBWModeTimer); +// //return; +// } + + if(priv->SetBWModeInProgress) + return; + + priv->SetBWModeInProgress= TRUE; + + priv->CurrentChannelBW = Bandwidth; + + if(Offset==HT_EXTCHNL_OFFSET_LOWER) + priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER; + else if(Offset==HT_EXTCHNL_OFFSET_UPPER) + priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER; + else + priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + +#if 0 + if(!priv->bDriverStopped) + { +#ifdef USE_WORKITEM + PlatformScheduleWorkItem(&(priv->SetBWModeWorkItem));//SetBWModeCallback8192SUsbWorkItem +#else + PlatformSetTimer(dev, &(priv->SetBWModeTimer), 0);//PHY_SetBWModeCallback8192S +#endif + } +#endif + if((priv->up) )// && !(RT_CANNOT_IO(Adapter) && Adapter->bInSetPower) ) + { +#ifdef RTL8192SE + PHY_SetBWModeCallback8192S(dev); +#elif defined(RTL8192SU) + SetBWModeCallback8192SUsbWorkItem(dev); +#endif + } + else + { + RT_TRACE(COMP_SCAN, "PHY_SetBWMode8192S() SetBWModeInProgress FALSE driver sleep or unload\n"); + priv->SetBWModeInProgress= FALSE; + priv->CurrentChannelBW = tmpBW; + } +} + +// use in phy only (in win it's timer) +void PHY_SwChnlCallback8192S(struct net_device *dev) +{ + + struct r8192_priv *priv = ieee80211_priv(dev); + u32 delay; + //bool ret; + + RT_TRACE(COMP_CH, "==>SwChnlCallback8190Pci(), switch to channel %d\n", priv->chan); + + if(!priv->up) + return; + + if(priv->rf_chip == RF_PSEUDO_11N) + { + priv->SwChnlInProgress=FALSE; + return; //return immediately if it is peudo-phy + } + + do{ + if(!priv->SwChnlInProgress) + break; + + //if(!phy_SwChnlStepByStep(dev, priv->CurrentChannel, &priv->SwChnlStage, &priv->SwChnlStep, &delay)) + if(!phy_SwChnlStepByStep(dev, priv->chan, &priv->SwChnlStage, &priv->SwChnlStep, &delay)) + { + if(delay>0) + { + mdelay(delay); + //PlatformSetTimer(dev, &priv->SwChnlTimer, delay); + //mod_timer(&priv->SwChnlTimer, jiffies + MSECS(delay)); + //==>PHY_SwChnlCallback8192S(dev); for 92se + //==>SwChnlCallback8192SUsb(dev) for 92su + } + else + continue; + } + else + { + priv->SwChnlInProgress=FALSE; + break; + } + }while(true); +} + +// Call after initialization +//extern void PHY_SwChnl8192S(struct net_device* dev, u8 channel) +u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + //u8 tmpchannel =channel; + //bool bResult = false; + + if(!priv->up) + return false; + + if(priv->SwChnlInProgress) + return false; + + if(priv->SetBWModeInProgress) + return false; + + //-------------------------------------------- + switch(priv->ieee80211->mode) + { + case WIRELESS_MODE_A: + case WIRELESS_MODE_N_5G: + if (channel<=14){ + RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14"); + return false; + } + break; + + case WIRELESS_MODE_B: + if (channel>14){ + RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14"); + return false; + } + break; + + case WIRELESS_MODE_G: + case WIRELESS_MODE_N_24G: + if (channel>14){ + RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14"); + return false; + } + break; + + default: + ;//RT_TRACE(COMP_ERR, "Invalid WirelessMode(%#x)!!\n", priv->ieee80211->mode); + break; + } + //-------------------------------------------- + + priv->SwChnlInProgress = TRUE; + if( channel == 0) + channel = 1; + + priv->chan=channel; + + priv->SwChnlStage=0; + priv->SwChnlStep=0; + + if((priv->up))// && !(RT_CANNOT_IO(Adapter) && Adapter->bInSetPower)) + { +#ifdef RTL8192SE + PHY_SwChnlCallback8192S(dev); +#elif defined(RTL8192SU) + SwChnlCallback8192SUsbWorkItem(dev); +#endif +#ifdef TO_DO_LIST + if(bResult) + { + RT_TRACE(COMP_SCAN, "PHY_SwChnl8192S SwChnlInProgress TRUE schdule workitem done\n"); + } + else + { + RT_TRACE(COMP_SCAN, "PHY_SwChnl8192S SwChnlInProgress FALSE schdule workitem error\n"); + priv->SwChnlInProgress = false; + priv->CurrentChannel = tmpchannel; + } +#endif + } + else + { + RT_TRACE(COMP_SCAN, "PHY_SwChnl8192S SwChnlInProgress FALSE driver sleep or unload\n"); + priv->SwChnlInProgress = false; + //priv->CurrentChannel = tmpchannel; + } + return true; +} + + +// +// Description: +// Switch channel synchronously. Called by SwChnlByDelayHandler. +// +// Implemented by Bruce, 2008-02-14. +// The following procedure is operted according to SwChanlCallback8190Pci(). +// However, this procedure is performed synchronously which should be running under +// passive level. +// +//not understant it +void PHY_SwChnlPhy8192S( // Only called during initialize + struct net_device* dev, + u8 channel + ) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + + RT_TRACE(COMP_SCAN, "==>PHY_SwChnlPhy8192S(), switch to channel %d.\n", priv->chan); + +#ifdef TO_DO_LIST + // Cannot IO. + if(RT_CANNOT_IO(dev)) + return; +#endif + + // Channel Switching is in progress. + if(priv->SwChnlInProgress) + return; + + //return immediately if it is peudo-phy + if(priv->rf_chip == RF_PSEUDO_11N) + { + priv->SwChnlInProgress=FALSE; + return; + } + + priv->SwChnlInProgress = TRUE; + if( channel == 0) + channel = 1; + + priv->chan=channel; + + priv->SwChnlStage = 0; + priv->SwChnlStep = 0; + + phy_FinishSwChnlNow(dev,channel); + + priv->SwChnlInProgress = FALSE; +} + +// use in phy only +static bool +phy_SetSwChnlCmdArray( + SwChnlCmd* CmdTable, + u32 CmdTableIdx, + u32 CmdTableSz, + SwChnlCmdID CmdID, + u32 Para1, + u32 Para2, + u32 msDelay + ) +{ + SwChnlCmd* pCmd; + + if(CmdTable == NULL) + { + //RT_ASSERT(FALSE, ("phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n")); + return FALSE; + } + if(CmdTableIdx >= CmdTableSz) + { + //RT_ASSERT(FALSE, + // ("phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n", + //CmdTableIdx, CmdTableSz)); + return FALSE; + } + + pCmd = CmdTable + CmdTableIdx; + pCmd->CmdID = CmdID; + pCmd->Para1 = Para1; + pCmd->Para2 = Para2; + pCmd->msDelay = msDelay; + + return TRUE; +} + +// use in phy only +static bool +phy_SwChnlStepByStep( + struct net_device* dev, + u8 channel, + u8 *stage, + u8 *step, + u32 *delay + ) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + //PCHANNEL_ACCESS_SETTING pChnlAccessSetting; + SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT]; + u32 PreCommonCmdCnt; + SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT]; + u32 PostCommonCmdCnt; + SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT]; + u32 RfDependCmdCnt; + SwChnlCmd *CurrentCmd = NULL; + u8 eRFPath; + + //RT_ASSERT((dev != NULL), ("Adapter should not be NULL\n")); + //RT_ASSERT(IsLegalChannel(dev, channel), ("illegal channel: %d\n", channel)); + RT_TRACE(COMP_CH, "===========>%s(), channel:%d, stage:%d, step:%d\n", __FUNCTION__, channel, *stage, *step); + //RT_ASSERT((pHalData != NULL), ("pHalData should not be NULL\n")); +#ifdef ENABLE_DOT11D + if (!IsLegalChannel(priv->ieee80211, channel)) + { + RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n", channel); + return true; //return true to tell upper caller function this channel setting is finished! Or it will in while loop. + } +#endif + + //pChnlAccessSetting = &Adapter->MgntInfo.Info8185.ChannelAccessSetting; + //RT_ASSERT((pChnlAccessSetting != NULL), ("pChnlAccessSetting should not be NULL\n")); + + //for(eRFPath = RF90_PATH_A; eRFPath <priv->NumTotalRFPath; eRFPath++) + //for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++) + //{ + // <1> Fill up pre common command. + PreCommonCmdCnt = 0; + phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT, + CmdID_SetTxPowerLevel, 0, 0, 0); + phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT, + CmdID_End, 0, 0, 0); + + // <2> Fill up post common command. + PostCommonCmdCnt = 0; + + phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT, + CmdID_End, 0, 0, 0); + + // <3> Fill up RF dependent command. + RfDependCmdCnt = 0; + switch( priv->rf_chip ) + { + case RF_8225: + if (channel < 1 || channel > 14) + RT_TRACE(COMP_ERR, "illegal channel for zebra:%d\n", channel); + //RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel)); + // 2008/09/04 MH Change channel. + phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, + CmdID_RF_WriteReg, rRfChannel, channel, 10); + phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, + CmdID_End, 0, 0, 0); + break; + + case RF_8256: + if (channel < 1 || channel > 14) + RT_TRACE(COMP_ERR, "illegal channel for zebra:%d\n", channel); + // TEST!! This is not the table for 8256!! + //RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel)); + phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, + CmdID_RF_WriteReg, rRfChannel, channel, 10); + phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, + CmdID_End, 0, 0, 0); + break; + + case RF_6052: + if (channel < 1 || channel > 14) + RT_TRACE(COMP_ERR, "illegal channel for zebra:%d\n", channel); + phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, + CmdID_RF_WriteReg, RF_CHNLBW, channel, 10); + phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, + CmdID_End, 0, 0, 0); + break; + + case RF_8258: + break; + + default: + //RT_ASSERT(FALSE, ("Unknown rf_chip: %d\n", priv->rf_chip)); + return FALSE; + break; + } + + + do{ + switch(*stage) + { + case 0: + CurrentCmd=&PreCommonCmd[*step]; + break; + case 1: + CurrentCmd=&RfDependCmd[*step]; + break; + case 2: + CurrentCmd=&PostCommonCmd[*step]; + break; + } + + if(CurrentCmd->CmdID==CmdID_End) + { + if((*stage)==2) + { + return TRUE; + } + else + { + (*stage)++; + (*step)=0; + continue; + } + } + + switch(CurrentCmd->CmdID) + { + case CmdID_SetTxPowerLevel: + //if(priv->card_8192_version > VERSION_8190_BD) + PHY_SetTxPowerLevel8192S(dev,channel); + break; + case CmdID_WritePortUlong: + write_nic_dword(dev, CurrentCmd->Para1, CurrentCmd->Para2); + break; + case CmdID_WritePortUshort: + write_nic_word(dev, CurrentCmd->Para1, (u16)CurrentCmd->Para2); + break; + case CmdID_WritePortUchar: + write_nic_byte(dev, CurrentCmd->Para1, (u8)CurrentCmd->Para2); + break; + case CmdID_RF_WriteReg: // Only modify channel for the register now !!!!! + for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++) + { +#if (defined RTL8192SE ||defined RTL8192SU ) + // For new T65 RF 0222d register 0x18 bit 0-9 = channel number. + rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, 0x1f, (CurrentCmd->Para2)); + //printk("====>%x, %x, read_back:%x\n", CurrentCmd->Para2,CurrentCmd->Para1, rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, 0x1f)); +#else + rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bRFRegOffsetMask, ((CurrentCmd->Para2)<<7)); +#endif + } + break; + default: + break; + } + + break; + }while(TRUE); + //cosa }/*for(Number of RF paths)*/ + + (*delay)=CurrentCmd->msDelay; + (*step)++; + RT_TRACE(COMP_CH, "<===========%s(), channel:%d, stage:%d, step:%d\n", __FUNCTION__, channel, *stage, *step); + return FALSE; +} + +//called PHY_SwChnlPhy8192S, SwChnlCallback8192SUsbWorkItem +// use in phy only +static void +phy_FinishSwChnlNow( // We should not call this function directly + struct net_device* dev, + u8 channel + ) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + u32 delay; + + while(!phy_SwChnlStepByStep(dev,channel,&priv->SwChnlStage,&priv->SwChnlStep,&delay)) + { + if(delay>0) + mdelay(delay); + if(!priv->up) + break; + } +} + + +/*----------------------------------------------------------------------------- + * Function: PHYCheckIsLegalRfPath8190Pci() + * + * Overview: Check different RF type to execute legal judgement. If RF Path is illegal + * We will return false. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 11/15/2007 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ + //called by rtl8192_phy_QueryRFReg, rtl8192_phy_SetRFReg, PHY_SetRFPowerState8192SUsb +//extern bool +//PHY_CheckIsLegalRfPath8192S( +// struct net_device* dev, +// u32 eRFPath) +u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath) +{ +// struct r8192_priv *priv = ieee80211_priv(dev); + bool rtValue = TRUE; + + // NOt check RF Path now.! +#if 0 + if (priv->rf_type == RF_1T2R && eRFPath != RF90_PATH_A) + { + rtValue = FALSE; + } + if (priv->rf_type == RF_1T2R && eRFPath != RF90_PATH_A) + { + + } +#endif + return rtValue; + +} /* PHY_CheckIsLegalRfPath8192S */ + + + +/*----------------------------------------------------------------------------- + * Function: PHY_IQCalibrate8192S() + * + * Overview: After all MAC/PHY/RF is configued. We must execute IQ calibration + * to improve RF EVM!!? + * + * Input: IN PADAPTER pAdapter + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 10/07/2008 MHC Create. Document from SD3 RFSI Jenyu. + * + *---------------------------------------------------------------------------*/ + //called by InitializeAdapter8192SE +void +PHY_IQCalibrate( struct net_device* dev) +{ + //struct r8192_priv *priv = ieee80211_priv(dev); + u32 i, reg; + u32 old_value; + long X, Y, TX0[4]; + u32 TXA[4]; + + // 1. Check QFN68 or 64 92S (Read from EEPROM) + + // + // 2. QFN 68 + // + // For 1T2R IQK only now !!! + for (i = 0; i < 10; i++) + { + // IQK + rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05430); + //PlatformStallExecution(5); + udelay(5); + rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000800e4); + udelay(5); + rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x80800000); + udelay(5); + rtl8192_setBBreg(dev, 0xe40, bMaskDWord, 0x02140148); + udelay(5); + rtl8192_setBBreg(dev, 0xe44, bMaskDWord, 0x681604a2); + udelay(5); + rtl8192_setBBreg(dev, 0xe4c, bMaskDWord, 0x000028d1); + udelay(5); + rtl8192_setBBreg(dev, 0xe60, bMaskDWord, 0x0214014d); + udelay(5); + rtl8192_setBBreg(dev, 0xe64, bMaskDWord, 0x281608ba); + udelay(5); + rtl8192_setBBreg(dev, 0xe6c, bMaskDWord, 0x000028d1); + udelay(5); + rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xfb000001); + udelay(5); + rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xf8000001); + udelay(2000); + rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05433); + udelay(5); + rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000000e4); + udelay(5); + rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x0); + + + reg = rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord); + + // Readback IQK value and rewrite + if (!(reg&(BIT27|BIT28|BIT30|BIT31))) + { + old_value = (rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord) & 0x3FF); + + // Calibrate init gain for A path for TX0 + X = (rtl8192_QueryBBReg(dev, 0xe94, bMaskDWord) & 0x03FF0000)>>16; + TXA[RF90_PATH_A] = (X * old_value)/0x100; + reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord); + reg = (reg & 0xFFFFFC00) | (u32)TXA[RF90_PATH_A]; + rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg); + udelay(5); + + // Calibrate init gain for C path for TX0 + Y = ( rtl8192_QueryBBReg(dev, 0xe9C, bMaskDWord) & 0x03FF0000)>>16; + TX0[RF90_PATH_C] = ((Y * old_value)/0x100); + reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord); + reg = (reg & 0xffc0ffff) |((u32) (TX0[RF90_PATH_C]&0x3F)<<16); + rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg); + reg = rtl8192_QueryBBReg(dev, 0xc94, bMaskDWord); + reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28); + rtl8192_setBBreg(dev, 0xc94, bMaskDWord, reg); + udelay(5); + + // Calibrate RX A and B for RX0 + reg = rtl8192_QueryBBReg(dev, 0xc14, bMaskDWord); + X = (rtl8192_QueryBBReg(dev, 0xea4, bMaskDWord) & 0x03FF0000)>>16; + reg = (reg & 0xFFFFFC00) |X; + rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg); + Y = (rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord) & 0x003F0000)>>16; + reg = (reg & 0xFFFF03FF) |Y<<10; + rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg); + udelay(5); + old_value = (rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord) & 0x3FF); + + // Calibrate init gain for A path for TX1 !!!!!! + X = (rtl8192_QueryBBReg(dev, 0xeb4, bMaskDWord) & 0x03FF0000)>>16; + reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord); + TXA[RF90_PATH_A] = (X * old_value) / 0x100; + reg = (reg & 0xFFFFFC00) | TXA[RF90_PATH_A]; + rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg); + udelay(5); + + // Calibrate init gain for C path for TX1 + Y = (rtl8192_QueryBBReg(dev, 0xebc, bMaskDWord)& 0x03FF0000)>>16; + TX0[RF90_PATH_C] = ((Y * old_value)/0x100); + reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord); + reg = (reg & 0xffc0ffff) |( (TX0[RF90_PATH_C]&0x3F)<<16); + rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg); + reg = rtl8192_QueryBBReg(dev, 0xc9c, bMaskDWord); + reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28); + rtl8192_setBBreg(dev, 0xc9c, bMaskDWord, reg); + udelay(5); + + // Calibrate RX A and B for RX1 + reg = rtl8192_QueryBBReg(dev, 0xc1c, bMaskDWord); + X = (rtl8192_QueryBBReg(dev, 0xec4, bMaskDWord) & 0x03FF0000)>>16; + reg = (reg & 0xFFFFFC00) |X; + rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg); + + Y = (rtl8192_QueryBBReg(dev, 0xecc, bMaskDWord) & 0x003F0000)>>16; + reg = (reg & 0xFFFF03FF) |Y<<10; + rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg); + udelay(5); + + RT_TRACE(COMP_INIT, "PHY_IQCalibrate OK\n"); + break; + } + + } + + + // + // 3. QFN64. Not enabled now !!! We must use different gain table for 1T2R. + // + + +} + +/*----------------------------------------------------------------------------- + * Function: PHY_IQCalibrateBcut() + * + * Overview: After all MAC/PHY/RF is configued. We must execute IQ calibration + * to improve RF EVM!!? + * + * Input: IN PADAPTER pAdapter + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 11/18/2008 MHC Create. Document from SD3 RFSI Jenyu. + * 92S B-cut QFN 68 pin IQ calibration procedure.doc + * + *---------------------------------------------------------------------------*/ +extern void PHY_IQCalibrateBcut(struct net_device* dev) +{ + //struct r8192_priv *priv = ieee80211_priv(dev); + //PMGNT_INFO pMgntInfo = &pAdapter->MgntInfo; + u32 i, reg; + u32 old_value; + long X, Y, TX0[4]; + u32 TXA[4]; + u32 calibrate_set[13] = {0}; + u32 load_value[13]; + u8 RfPiEnable=0; + + // 0. Check QFN68 or 64 92S (Read from EEPROM/EFUSE) + + // + // 1. Save e70~ee0 register setting, and load calibration setting + // + /* + 0xee0[31:0]=0x3fed92fb; + 0xedc[31:0] =0x3fed92fb; + 0xe70[31:0] =0x3fed92fb; + 0xe74[31:0] =0x3fed92fb; + 0xe78[31:0] =0x3fed92fb; + 0xe7c[31:0]= 0x3fed92fb; + 0xe80[31:0]= 0x3fed92fb; + 0xe84[31:0]= 0x3fed92fb; + 0xe88[31:0]= 0x3fed92fb; + 0xe8c[31:0]= 0x3fed92fb; + 0xed0[31:0]= 0x3fed92fb; + 0xed4[31:0]= 0x3fed92fb; + 0xed8[31:0]= 0x3fed92fb; + */ + calibrate_set [0] = 0xee0; + calibrate_set [1] = 0xedc; + calibrate_set [2] = 0xe70; + calibrate_set [3] = 0xe74; + calibrate_set [4] = 0xe78; + calibrate_set [5] = 0xe7c; + calibrate_set [6] = 0xe80; + calibrate_set [7] = 0xe84; + calibrate_set [8] = 0xe88; + calibrate_set [9] = 0xe8c; + calibrate_set [10] = 0xed0; + calibrate_set [11] = 0xed4; + calibrate_set [12] = 0xed8; + //RT_TRACE(COMP_INIT, DBG_LOUD, ("Save e70~ee0 register setting\n")); + for (i = 0; i < 13; i++) + { + load_value[i] = rtl8192_QueryBBReg(dev, calibrate_set[i], bMaskDWord); + rtl8192_setBBreg(dev, calibrate_set[i], bMaskDWord, 0x3fed92fb); + + } + + RfPiEnable = (u8)rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter1, BIT8); + + // + // 2. QFN 68 + // + // For 1T2R IQK only now !!! + for (i = 0; i < 10; i++) + { + RT_TRACE(COMP_INIT, "IQK -%d\n", i); + //BB switch to PI mode. If default is PI mode, ignoring 2 commands below. + if (!RfPiEnable) //if original is SI mode, then switch to PI mode. + { + //DbgPrint("IQK Switch to PI mode\n"); + rtl8192_setBBreg(dev, 0x820, bMaskDWord, 0x01000100); + rtl8192_setBBreg(dev, 0x828, bMaskDWord, 0x01000100); + } + + // IQK + // 2. IQ calibration & LO leakage calibration + rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05430); + udelay(5); + rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000800e4); + udelay(5); + rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x80800000); + udelay(5); + //path-A IQ K and LO K gain setting + rtl8192_setBBreg(dev, 0xe40, bMaskDWord, 0x02140102); + udelay(5); + rtl8192_setBBreg(dev, 0xe44, bMaskDWord, 0x681604c2); + udelay(5); + //set LO calibration + rtl8192_setBBreg(dev, 0xe4c, bMaskDWord, 0x000028d1); + udelay(5); + //path-B IQ K and LO K gain setting + rtl8192_setBBreg(dev, 0xe60, bMaskDWord, 0x02140102); + udelay(5); + rtl8192_setBBreg(dev, 0xe64, bMaskDWord, 0x28160d05); + udelay(5); + //K idac_I & IQ + rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xfb000000); + udelay(5); + rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xf8000000); + udelay(5); + + // delay 2ms + udelay(2000); + + //idac_Q setting + rtl8192_setBBreg(dev, 0xe6c, bMaskDWord, 0x020028d1); + udelay(5); + //K idac_Q & IQ + rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xfb000000); + udelay(5); + rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xf8000000); + + // delay 2ms + udelay(2000); + + rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05433); + udelay(5); + rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000000e4); + udelay(5); + rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x0); + + if (!RfPiEnable) //if original is SI mode, then switch to PI mode. + { + //DbgPrint("IQK Switch back to SI mode\n"); + rtl8192_setBBreg(dev, 0x820, bMaskDWord, 0x01000000); + rtl8192_setBBreg(dev, 0x828, bMaskDWord, 0x01000000); + } + + + reg = rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord); + + // 3. check fail bit, and fill BB IQ matrix + // Readback IQK value and rewrite + if (!(reg&(BIT27|BIT28|BIT30|BIT31))) + { + old_value = (rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord) & 0x3FF); + + // Calibrate init gain for A path for TX0 + X = (rtl8192_QueryBBReg(dev, 0xe94, bMaskDWord) & 0x03FF0000)>>16; + TXA[RF90_PATH_A] = (X * old_value)/0x100; + reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord); + reg = (reg & 0xFFFFFC00) | (u32)TXA[RF90_PATH_A]; + rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg); + udelay(5); + + // Calibrate init gain for C path for TX0 + Y = ( rtl8192_QueryBBReg(dev, 0xe9C, bMaskDWord) & 0x03FF0000)>>16; + TX0[RF90_PATH_C] = ((Y * old_value)/0x100); + reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord); + reg = (reg & 0xffc0ffff) |((u32) (TX0[RF90_PATH_C]&0x3F)<<16); + rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg); + reg = rtl8192_QueryBBReg(dev, 0xc94, bMaskDWord); + reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28); + rtl8192_setBBreg(dev, 0xc94, bMaskDWord, reg); + udelay(5); + + // Calibrate RX A and B for RX0 + reg = rtl8192_QueryBBReg(dev, 0xc14, bMaskDWord); + X = (rtl8192_QueryBBReg(dev, 0xea4, bMaskDWord) & 0x03FF0000)>>16; + reg = (reg & 0xFFFFFC00) |X; + rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg); + Y = (rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord) & 0x003F0000)>>16; + reg = (reg & 0xFFFF03FF) |Y<<10; + rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg); + udelay(5); + old_value = (rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord) & 0x3FF); + + // Calibrate init gain for A path for TX1 !!!!!! + X = (rtl8192_QueryBBReg(dev, 0xeb4, bMaskDWord) & 0x03FF0000)>>16; + reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord); + TXA[RF90_PATH_A] = (X * old_value) / 0x100; + reg = (reg & 0xFFFFFC00) | TXA[RF90_PATH_A]; + rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg); + udelay(5); + + // Calibrate init gain for C path for TX1 + Y = (rtl8192_QueryBBReg(dev, 0xebc, bMaskDWord)& 0x03FF0000)>>16; + TX0[RF90_PATH_C] = ((Y * old_value)/0x100); + reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord); + reg = (reg & 0xffc0ffff) |( (TX0[RF90_PATH_C]&0x3F)<<16); + rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg); + reg = rtl8192_QueryBBReg(dev, 0xc9c, bMaskDWord); + reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28); + rtl8192_setBBreg(dev, 0xc9c, bMaskDWord, reg); + udelay(5); + + // Calibrate RX A and B for RX1 + reg = rtl8192_QueryBBReg(dev, 0xc1c, bMaskDWord); + X = (rtl8192_QueryBBReg(dev, 0xec4, bMaskDWord) & 0x03FF0000)>>16; + reg = (reg & 0xFFFFFC00) |X; + rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg); + + Y = (rtl8192_QueryBBReg(dev, 0xecc, bMaskDWord) & 0x003F0000)>>16; + reg = (reg & 0xFFFF03FF) |Y<<10; + rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg); + udelay(5); + + RT_TRACE(COMP_INIT, "PHY_IQCalibrate OK\n"); + break; + } + + } + + // + // 4. Reload e70~ee0 register setting. + // + //RT_TRACE(COMP_INIT, DBG_LOUD, ("Reload e70~ee0 register setting.\n")); + for (i = 0; i < 13; i++) + rtl8192_setBBreg(dev, calibrate_set[i], bMaskDWord, load_value[i]); + + + // + // 3. QFN64. Not enabled now !!! We must use different gain table for 1T2R. + // + + + +} // PHY_IQCalibrateBcut + + +// +// Move from phycfg.c to gen.c to be code independent later +// +//-------------------------Move to other DIR later----------------------------*/ +//#if (DEV_BUS_TYPE == USB_INTERFACE) +#ifdef RTL8192SU + +// use in phy only (in win it's timer) +void SwChnlCallback8192SUsb(struct net_device *dev) +{ + + struct r8192_priv *priv = ieee80211_priv(dev); + u32 delay; +// bool ret; + + RT_TRACE(COMP_SCAN, "==>SwChnlCallback8190Pci(), switch to channel\ + %d\n", priv->chan); + + + if(!priv->up) + return; + + if(priv->rf_chip == RF_PSEUDO_11N) + { + priv->SwChnlInProgress=FALSE; + return; //return immediately if it is peudo-phy + } + + do{ + if(!priv->SwChnlInProgress) + break; + + if(!phy_SwChnlStepByStep(dev, priv->chan, &priv->SwChnlStage, &priv->SwChnlStep, &delay)) + { + if(delay>0) + { + //PlatformSetTimer(dev, &priv->SwChnlTimer, delay); + + } + else + continue; + } + else + { + priv->SwChnlInProgress=FALSE; + } + break; + }while(TRUE); +} + + +// +// Callback routine of the work item for switch channel. +// +// use in phy only (in win it's work) +void SwChnlCallback8192SUsbWorkItem(struct net_device *dev ) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + + RT_TRACE(COMP_TRACE, "==> SwChnlCallback8192SUsbWorkItem()\n"); +#ifdef TO_DO_LIST + if(pAdapter->bInSetPower && RT_USB_CANNOT_IO(pAdapter)) + { + RT_TRACE(COMP_SCAN, DBG_LOUD, ("<== SwChnlCallback8192SUsbWorkItem() SwChnlInProgress FALSE driver sleep or unload\n")); + + pHalData->SwChnlInProgress = FALSE; + return; + } +#endif + phy_FinishSwChnlNow(dev, priv->chan); + priv->SwChnlInProgress = FALSE; + + RT_TRACE(COMP_TRACE, "<== SwChnlCallback8192SUsbWorkItem()\n"); +} + + +/*----------------------------------------------------------------------------- + * Function: SetBWModeCallback8192SUsb() + * + * Overview: Timer callback function for SetSetBWMode + * + * Input: PRT_TIMER pTimer + * + * Output: NONE + * + * Return: NONE + * + * Note: (1) We do not take j mode into consideration now + * (2) Will two workitem of "switch channel" and "switch channel bandwidth" run + * concurrently? + *---------------------------------------------------------------------------*/ +//====>//rtl8192_SetBWMode +// use in phy only (in win it's timer) +void SetBWModeCallback8192SUsb(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + u8 regBwOpMode; + + // Added it for 20/40 mhz switch time evaluation by guangan 070531 + //u32 NowL, NowH; + //u8Byte BeginTime, EndTime; + u8 regRRSR_RSC; + + RT_TRACE(COMP_SCAN, "==>SetBWModeCallback8190Pci() Switch to %s bandwidth\n", \ + priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"); + + if(priv->rf_chip == RF_PSEUDO_11N) + { + priv->SetBWModeInProgress= FALSE; + return; + } + + if(!priv->up) + return; + + // Added it for 20/40 mhz switch time evaluation by guangan 070531 + //NowL = read_nic_dword(dev, TSFR); + //NowH = read_nic_dword(dev, TSFR+4); + //BeginTime = ((u8Byte)NowH << 32) + NowL; + + //3<1>Set MAC register + regBwOpMode = read_nic_byte(dev, BW_OPMODE); + regRRSR_RSC = read_nic_byte(dev, RRSR+2); + + switch(priv->CurrentChannelBW) + { + case HT_CHANNEL_WIDTH_20: + regBwOpMode |= BW_OPMODE_20MHZ; + // 2007/02/07 Mark by Emily becasue we have not verify whether this register works + write_nic_byte(dev, BW_OPMODE, regBwOpMode); + break; + + case HT_CHANNEL_WIDTH_20_40: + regBwOpMode &= ~BW_OPMODE_20MHZ; + // 2007/02/07 Mark by Emily becasue we have not verify whether this register works + write_nic_byte(dev, BW_OPMODE, regBwOpMode); + + regRRSR_RSC = (regRRSR_RSC&0x90) |(priv->nCur40MhzPrimeSC<<5); + write_nic_byte(dev, RRSR+2, regRRSR_RSC); + break; + + default: + RT_TRACE(COMP_DBG, "SetChannelBandwidth8190Pci():\ + unknown Bandwidth: %#X\n",priv->CurrentChannelBW); + break; + } + + //3 <2>Set PHY related register + switch(priv->CurrentChannelBW) + { + case HT_CHANNEL_WIDTH_20: + rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); + rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0); + #if 0 //LZM090219 + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00300000, 3); + + // Correct the tx power for CCK rate in 20M. Suggest by YN, 20071207 + //write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000); + //write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317); + //write_nic_dword(dev, rCCK0_DebugPort, 0x00000204); + rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskDWord, 0x1a1b0000); + rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, 0x090e1317); + rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskDWord, 0x00000204); + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00300000, 3); + #endif + + if (priv->card_8192_version >= VERSION_8192S_BCUT) + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x58); + + break; + case HT_CHANNEL_WIDTH_20_40: + rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1); + rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1); + rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1)); + rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC); + + // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207 + //PHY_SetBBReg(Adapter, rCCK0_TxFilter1, bMaskDWord, 0x35360000); + //PHY_SetBBReg(Adapter, rCCK0_TxFilter2, bMaskDWord, 0x121c252e); + //PHY_SetBBReg(Adapter, rCCK0_DebugPort, bMaskDWord, 0x00000409); + //PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter1, bADClkPhase, 0); + + if (priv->card_8192_version >= VERSION_8192S_BCUT) + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x18); + + break; + default: + RT_TRACE(COMP_DBG, "SetChannelBandwidth8190Pci(): unknown Bandwidth: %#X\n"\ + ,priv->CurrentChannelBW); + break; + + } + //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315 + + // Added it for 20/40 mhz switch time evaluation by guangan 070531 + //NowL = read_nic_dword(dev, TSFR); + //NowH = read_nic_dword(dev, TSFR+4); + //EndTime = ((u8Byte)NowH << 32) + NowL; + //RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWModeCallback8190Pci: time of SetBWMode = %I64d us!\n", (EndTime - BeginTime))); + +#if 1 + //3<3>Set RF related register + switch( priv->rf_chip ) + { + case RF_8225: + PHY_SetRF8225Bandwidth(dev, priv->CurrentChannelBW); + break; + + case RF_8256: + // Please implement this function in Hal8190PciPhy8256.c + //PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW); + break; + + case RF_6052: + PHY_RF6052SetBandwidth(dev, priv->CurrentChannelBW); + break; + + case RF_8258: + // Please implement this function in Hal8190PciPhy8258.c + // PHY_SetRF8258Bandwidth(); + break; + + case RF_PSEUDO_11N: + // Do Nothing + break; + + default: + //RT_ASSERT(FALSE, ("Unknown rf_chip: %d\n", priv->rf_chip)); + break; + } +#endif + priv->SetBWModeInProgress= FALSE; + + RT_TRACE(COMP_SCAN, "<==SetBWMode8190Pci()" ); +} + +// +// Callback routine of the work item for set bandwidth mode. +// +// use in phy only (in win it's work) +void SetBWModeCallback8192SUsbWorkItem(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + u8 regBwOpMode; + + // Added it for 20/40 mhz switch time evaluation by guangan 070531 + //u32 NowL, NowH; + //u8Byte BeginTime, EndTime; + u8 regRRSR_RSC; + + RT_TRACE(COMP_SCAN, "==>SetBWModeCallback8192SUsbWorkItem() Switch to %s bandwidth\n", \ + priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"); + + if(priv->rf_chip == RF_PSEUDO_11N) + { + priv->SetBWModeInProgress= FALSE; + return; + } + + if(!priv->up) + return; + + // Added it for 20/40 mhz switch time evaluation by guangan 070531 + //NowL = read_nic_dword(dev, TSFR); + //NowH = read_nic_dword(dev, TSFR+4); + //BeginTime = ((u8Byte)NowH << 32) + NowL; + + //3<1>Set MAC register + regBwOpMode = read_nic_byte(dev, BW_OPMODE); + regRRSR_RSC = read_nic_byte(dev, RRSR+2); + + switch(priv->CurrentChannelBW) + { + case HT_CHANNEL_WIDTH_20: + regBwOpMode |= BW_OPMODE_20MHZ; + // 2007/02/07 Mark by Emily becasue we have not verify whether this register works + write_nic_byte(dev, BW_OPMODE, regBwOpMode); + break; + + case HT_CHANNEL_WIDTH_20_40: + regBwOpMode &= ~BW_OPMODE_20MHZ; + // 2007/02/07 Mark by Emily becasue we have not verify whether this register works + write_nic_byte(dev, BW_OPMODE, regBwOpMode); + regRRSR_RSC = (regRRSR_RSC&0x90) |(priv->nCur40MhzPrimeSC<<5); + write_nic_byte(dev, RRSR+2, regRRSR_RSC); + + break; + + default: + RT_TRACE(COMP_DBG, "SetBWModeCallback8192SUsbWorkItem():\ + unknown Bandwidth: %#X\n",priv->CurrentChannelBW); + break; + } + + //3 <2>Set PHY related register + switch(priv->CurrentChannelBW) + { + case HT_CHANNEL_WIDTH_20: + rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); + rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0); + + #if 0 //LZM 090219 + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bADClkPhase, 1); + + // Correct the tx power for CCK rate in 20M. Suggest by YN, 20071207 + rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskDWord, 0x1a1b0000); + rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, 0x090e1317); + rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskDWord, 0x00000204); + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1); + #endif + + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x58); + + break; + case HT_CHANNEL_WIDTH_20_40: + rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1); + rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1); + #if 0 //LZM 090219 + rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1)); + + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bADClkPhase, 0); + + rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC); + // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207 + rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskDWord, 0x35360000); + rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, 0x121c252e); + rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskDWord, 0x00000409); + #endif + + // Set Control channel to upper or lower. These settings are required only for 40MHz + rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1)); + rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC); + + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x18); + + break; + + + default: + RT_TRACE(COMP_DBG, "SetBWModeCallback8192SUsbWorkItem(): unknown Bandwidth: %#X\n"\ + ,priv->CurrentChannelBW); + break; + + } + //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315 + + //3<3>Set RF related register + switch( priv->rf_chip ) + { + case RF_8225: + PHY_SetRF8225Bandwidth(dev, priv->CurrentChannelBW); + break; + + case RF_8256: + // Please implement this function in Hal8190PciPhy8256.c + //PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW); + break; + + case RF_6052: + PHY_RF6052SetBandwidth(dev, priv->CurrentChannelBW); + break; + + case RF_8258: + // Please implement this function in Hal8190PciPhy8258.c + // PHY_SetRF8258Bandwidth(); + break; + + case RF_PSEUDO_11N: + // Do Nothing + break; + + default: + //RT_ASSERT(FALSE, ("Unknown rf_chip: %d\n", priv->rf_chip)); + break; + } + + priv->SetBWModeInProgress= FALSE; + + RT_TRACE(COMP_SCAN, "<==SetBWModeCallback8192SUsbWorkItem()" ); +} + +//--------------------------Move to oter DIR later-------------------------------*/ +#ifdef RTL8192SU +void InitialGain8192S(struct net_device *dev, u8 Operation) +{ +#ifdef TO_DO_LIST + struct r8192_priv *priv = ieee80211_priv(dev); +#endif + +} +#endif + +void InitialGain819xUsb(struct net_device *dev, u8 Operation) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + + priv->InitialGainOperateType = Operation; + + if(priv->up) + { + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + queue_delayed_work(priv->priv_wq,&priv->initialgain_operate_wq,0); + #else + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) + schedule_task(&priv->initialgain_operate_wq); + #else + queue_work(priv->priv_wq,&priv->initialgain_operate_wq); + #endif + #endif + } +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) +extern void InitialGainOperateWorkItemCallBack(struct work_struct *work) +{ + struct delayed_work *dwork = container_of(work,struct delayed_work,work); + struct r8192_priv *priv = container_of(dwork,struct r8192_priv,initialgain_operate_wq); + struct net_device *dev = priv->ieee80211->dev; +#else +extern void InitialGainOperateWorkItemCallBack(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); +#endif +#define SCAN_RX_INITIAL_GAIN 0x17 +#define POWER_DETECTION_TH 0x08 + u32 BitMask; + u8 initial_gain; + u8 Operation; + + Operation = priv->InitialGainOperateType; + + switch(Operation) + { + case IG_Backup: + RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n"); + initial_gain = SCAN_RX_INITIAL_GAIN;//priv->DefaultInitialGain[0];// + BitMask = bMaskByte0; + if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) + rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF + priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask); + priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask); + priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, BitMask); + priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, BitMask); + BitMask = bMaskByte2; + priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, BitMask); + + RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1); + RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1); + RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1); + RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1); + RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca); + + RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n", initial_gain); + write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain); + write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain); + write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain); + write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain); + RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n", POWER_DETECTION_TH); + write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH); + break; + case IG_Restore: + RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n"); + BitMask = 0x7f; //Bit0~ Bit6 + if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) + rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF + + rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1); + rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1); + rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, (u32)priv->initgain_backup.xcagccore1); + rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)priv->initgain_backup.xdagccore1); + BitMask = bMaskByte2; + rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, (u32)priv->initgain_backup.cca); + + RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1); + RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1); + RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1); + RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1); + RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca); + + PHY_SetTxPowerLevel8192S(dev,priv->ieee80211->current_network.channel); + + if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) + rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // FW DIG ON + break; + default: + RT_TRACE(COMP_SCAN, "Unknown IG Operation. \n"); + break; + } +} + +#endif // #if (DEV_BUS_TYPE == USB_INTERFACE) + +//----------------------------------------------------------------------------- +// Description: +// Schedule workitem to send specific CMD IO to FW. +// Added by Roger, 2008.12.03. +// +//----------------------------------------------------------------------------- +bool HalSetFwCmd8192S(struct net_device* dev, FW_CMD_IO_TYPE FwCmdIO) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + u16 FwCmdWaitCounter = 0; + + u16 FwCmdWaitLimit = 1000; + + //if(IS_HARDWARE_TYPE_8192SU(Adapter) && Adapter->bInHctTest) + if(priv->bInHctTest) + return true; + + RT_TRACE(COMP_CMD, "-->HalSetFwCmd8192S(): Set FW Cmd(%x), SetFwCmdInProgress(%d)\n", (u32)FwCmdIO, priv->SetFwCmdInProgress); + + // Will be done by high power respectively. + if(FwCmdIO==FW_CMD_DIG_HALT || FwCmdIO==FW_CMD_DIG_RESUME) + { + RT_TRACE(COMP_CMD, "<--HalSetFwCmd8192S(): Set FW Cmd(%x)\n", (u32)FwCmdIO); + return false; + } + +#if 1 + while(priv->SetFwCmdInProgress && FwCmdWaitCounter<FwCmdWaitLimit) + { + //if(RT_USB_CANNOT_IO(Adapter)) + //{ + // RT_TRACE(COMP_CMD, DBG_WARNING, ("HalSetFwCmd8192S(): USB can NOT IO!!\n")); + // return FALSE; + //} + + RT_TRACE(COMP_CMD, "HalSetFwCmd8192S(): previous workitem not finish!!\n"); + return false; + FwCmdWaitCounter ++; + RT_TRACE(COMP_CMD, "HalSetFwCmd8192S(): Wait 10 ms (%d times)...\n", FwCmdWaitCounter); + udelay(100); + } + + if(FwCmdWaitCounter == FwCmdWaitLimit) + { + //RT_ASSERT(FALSE, ("SetFwCmdIOWorkItemCallback(): Wait too logn to set FW CMD\n")); + RT_TRACE(COMP_CMD, "HalSetFwCmd8192S(): Wait too logn to set FW CMD\n"); + //return false; + } +#endif + if (priv->SetFwCmdInProgress) + { + RT_TRACE(COMP_ERR, "<--HalSetFwCmd8192S(): Set FW Cmd(%#x)\n", FwCmdIO); + return false; + } + priv->SetFwCmdInProgress = TRUE; + priv->CurrentFwCmdIO = FwCmdIO; // Update current FW Cmd for callback use. + + phy_SetFwCmdIOCallback(dev); + return true; +} +void ChkFwCmdIoDone(struct net_device* dev) +{ + u16 PollingCnt = 1000; + u32 tmpValue; + + do + {// Make sure that CMD IO has be accepted by FW. +#ifdef TO_DO_LIST + if(RT_USB_CANNOT_IO(Adapter)) + { + RT_TRACE(COMP_CMD, "ChkFwCmdIoDone(): USB can NOT IO!!\n"); + return; + } +#endif + udelay(10); // sleep 20us + tmpValue = read_nic_dword(dev, WFM5); + if(tmpValue == 0) + { + RT_TRACE(COMP_CMD, "[FW CMD] Set FW Cmd success!!\n"); + break; + } + else + { + RT_TRACE(COMP_CMD, "[FW CMD] Polling FW Cmd PollingCnt(%d)!!\n", PollingCnt); + } + }while( --PollingCnt ); + + if(PollingCnt == 0) + { + RT_TRACE(COMP_ERR, "[FW CMD] Set FW Cmd fail!!\n"); + } +} +// Callback routine of the timer callback for FW Cmd IO. +// +// Description: +// This routine will send specific CMD IO to FW and check whether it is done. +// +void phy_SetFwCmdIOCallback(struct net_device* dev) +{ + //struct net_device* dev = (struct net_device*) data; + u32 input; + static u32 ScanRegister; + struct r8192_priv *priv = ieee80211_priv(dev); + if(!priv->up) + { + RT_TRACE(COMP_CMD, "SetFwCmdIOTimerCallback(): driver is going to unload\n"); + return; + } + + RT_TRACE(COMP_CMD, "--->SetFwCmdIOTimerCallback(): Cmd(%#x), SetFwCmdInProgress(%d)\n", priv->CurrentFwCmdIO, priv->SetFwCmdInProgress); + + switch(priv->CurrentFwCmdIO) + { + case FW_CMD_HIGH_PWR_ENABLE: + if((priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER)==0) + write_nic_dword(dev, WFM5, FW_HIGH_PWR_ENABLE); + break; + + case FW_CMD_HIGH_PWR_DISABLE: + write_nic_dword(dev, WFM5, FW_HIGH_PWR_DISABLE); + break; + + case FW_CMD_DIG_RESUME: + write_nic_dword(dev, WFM5, FW_DIG_RESUME); + break; + + case FW_CMD_DIG_HALT: + write_nic_dword(dev, WFM5, FW_DIG_HALT); + break; + + // + // <Roger_Notes> The following FW CMD IO was combined into single operation + // (i.e., to prevent number of system workitem out of resource!!). + // 2008.12.04. + // + case FW_CMD_RESUME_DM_BY_SCAN: + RT_TRACE(COMP_CMD, "[FW CMD] Set HIGHPWR enable and DIG resume!!\n"); + if((priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER)==0) + { + write_nic_dword(dev, WFM5, FW_HIGH_PWR_ENABLE); //break; + ChkFwCmdIoDone(dev); + } + write_nic_dword(dev, WFM5, FW_DIG_RESUME); + break; + + case FW_CMD_PAUSE_DM_BY_SCAN: + RT_TRACE(COMP_CMD, "[FW CMD] Set HIGHPWR disable and DIG halt!!\n"); + write_nic_dword(dev, WFM5, FW_HIGH_PWR_DISABLE); //break; + ChkFwCmdIoDone(dev); + write_nic_dword(dev, WFM5, FW_DIG_HALT); + break; + + // + // <Roger_Notes> The following FW CMD IO should be checked + // (i.e., workitem schedule timing issue!!). + // 2008.12.04. + // + case FW_CMD_DIG_DISABLE: + RT_TRACE(COMP_CMD, "[FW CMD] Set DIG disable!!\n"); + write_nic_dword(dev, WFM5, FW_DIG_DISABLE); + break; + + case FW_CMD_DIG_ENABLE: + RT_TRACE(COMP_CMD, "[FW CMD] Set DIG enable!!\n"); + write_nic_dword(dev, WFM5, FW_DIG_ENABLE); + break; + + case FW_CMD_RA_RESET: + write_nic_dword(dev, WFM5, FW_RA_RESET); + break; + + case FW_CMD_RA_ACTIVE: + write_nic_dword(dev, WFM5, FW_RA_ACTIVE); + break; + + case FW_CMD_RA_REFRESH_N: + RT_TRACE(COMP_CMD, "[FW CMD] Set RA refresh!! N\n"); + if(priv->ieee80211->pHTInfo->IOTRaFunc & HT_IOT_RAFUNC_DISABLE_ALL) + input = FW_RA_REFRESH; + else + input = FW_RA_REFRESH | (priv->ieee80211->pHTInfo->IOTRaFunc << 8); + write_nic_dword(dev, WFM5, input); + break; + case FW_CMD_RA_REFRESH_BG: + RT_TRACE(COMP_CMD, "[FW CMD] Set RA refresh!! B/G\n"); + write_nic_dword(dev, WFM5, FW_RA_REFRESH); + ChkFwCmdIoDone(dev); + write_nic_dword(dev, WFM5, FW_RA_ENABLE_BG); + break; + + case FW_CMD_IQK_ENABLE: + write_nic_dword(dev, WFM5, FW_IQK_ENABLE); + break; + + case FW_CMD_TXPWR_TRACK_ENABLE: + write_nic_dword(dev, WFM5, FW_TXPWR_TRACK_ENABLE); + break; + + case FW_CMD_TXPWR_TRACK_DISABLE: + write_nic_dword(dev, WFM5, FW_TXPWR_TRACK_DISABLE); + break; + + default: + RT_TRACE(COMP_CMD,"Unknown FW Cmd IO(%#x)\n", priv->CurrentFwCmdIO); + break; + } + + ChkFwCmdIoDone(dev); + + switch(priv->CurrentFwCmdIO) + { + case FW_CMD_HIGH_PWR_DISABLE: + //if(pMgntInfo->bTurboScan) + { + //Lower initial gain + rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bMaskByte0, 0x17); + rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bMaskByte0, 0x17); + // CCA threshold + rtl8192_setBBreg(dev, rCCK0_CCA, bMaskByte2, 0x40); + // Disable OFDM Part + rtl8192_setBBreg(dev, rOFDM0_TRMuxPar, bMaskByte2, 0x1); + ScanRegister = rtl8192_QueryBBReg(dev, rOFDM0_RxDetector1,bMaskDWord); + rtl8192_setBBreg(dev, rOFDM0_RxDetector1, 0xf, 0xf); + rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0); + } + break; + + case FW_CMD_HIGH_PWR_ENABLE: + //if(pMgntInfo->bTurboScan) + { + rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bMaskByte0, 0x36); + rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bMaskByte0, 0x36); + + // CCA threshold + rtl8192_setBBreg(dev, rCCK0_CCA, bMaskByte2, 0x83); + // Enable OFDM Part + rtl8192_setBBreg(dev, rOFDM0_TRMuxPar, bMaskByte2, 0x0); + + //LZM ADD because sometimes there is no FW_CMD_HIGH_PWR_DISABLE, this value will be 0. + if(ScanRegister != 0){ + rtl8192_setBBreg(dev, rOFDM0_RxDetector1, bMaskDWord, ScanRegister); + } + + if(priv->rf_type == RF_1T2R || priv->rf_type == RF_2T2R) + rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x3); + else + rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x1); + } + break; + } + + priv->SetFwCmdInProgress = false;// Clear FW CMD operation flag. + RT_TRACE(COMP_CMD, "<---SetFwCmdIOWorkItemCallback()\n"); + +} + diff --git a/drivers/staging/rtl8192su/r8192S_phy.h b/drivers/staging/rtl8192su/r8192S_phy.h new file mode 100644 index 000000000000..580a7c6a7609 --- /dev/null +++ b/drivers/staging/rtl8192su/r8192S_phy.h @@ -0,0 +1,138 @@ +/***************************************************************************** + * Copyright(c) 2008, RealTEK Technology Inc. All Right Reserved. + * + * Module: __INC_HAL8192SPHYCFG_H + * + * + * Note: + * + * + * Export: Constants, macro, functions(API), global variables(None). + * + * Abbrev: + * + * History: + * Data Who Remark + * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h. + * 2. Reorganize code architecture. + * + *****************************************************************************/ + /* Check to see if the file has been included already. */ +#ifndef _R8192S_PHY_H +#define _R8192S_PHY_H + + +/*--------------------------Define Parameters-------------------------------*/ +#define LOOP_LIMIT 5 +#define MAX_STALL_TIME 50 //us +#define AntennaDiversityValue 0x80 //(dev->bSoftwareAntennaDiversity ? 0x00:0x80) +#define MAX_TXPWR_IDX_NMODE_92S 63 + +//#define delay_ms(_t) PlatformStallExecution(1000*(_t)) +//#define delay_us(_t) PlatformStallExecution(_t) + +/* Channel switch:The size of command tables for switch channel*/ +#define MAX_PRECMD_CNT 16 +#define MAX_RFDEPENDCMD_CNT 16 +#define MAX_POSTCMD_CNT 16 + + +/*------------------------------Define structure----------------------------*/ +typedef enum _SwChnlCmdID{ + CmdID_End, + CmdID_SetTxPowerLevel, + CmdID_BBRegWrite10, + CmdID_WritePortUlong, + CmdID_WritePortUshort, + CmdID_WritePortUchar, + CmdID_RF_WriteReg, +}SwChnlCmdID; + + +/* 1. Switch channel related */ +typedef struct _SwChnlCmd{ + SwChnlCmdID CmdID; + u32 Para1; + u32 Para2; + u32 msDelay; +}__attribute__ ((packed)) SwChnlCmd; + +extern u32 rtl819XMACPHY_Array_PG[]; +extern u32 rtl819XPHY_REG_1T2RArray[]; +extern u32 rtl819XAGCTAB_Array[]; +extern u32 rtl819XRadioA_Array[]; +extern u32 rtl819XRadioB_Array[]; +extern u32 rtl819XRadioC_Array[]; +extern u32 rtl819XRadioD_Array[]; + +typedef enum _HW90_BLOCK{ + HW90_BLOCK_MAC = 0, + HW90_BLOCK_PHY0 = 1, + HW90_BLOCK_PHY1 = 2, + HW90_BLOCK_RF = 3, + HW90_BLOCK_MAXIMUM = 4, // Never use this +}HW90_BLOCK_E, *PHW90_BLOCK_E; + +typedef enum _RF90_RADIO_PATH{ + RF90_PATH_A = 0, //Radio Path A + RF90_PATH_B = 1, //Radio Path B + RF90_PATH_C = 2, //Radio Path C + RF90_PATH_D = 3, //Radio Path D + RF90_PATH_MAX = 4, //Max RF number 90 support +}RF90_RADIO_PATH_E, *PRF90_RADIO_PATH_E; + +#define bMaskByte0 0xff +#define bMaskByte1 0xff00 +#define bMaskByte2 0xff0000 +#define bMaskByte3 0xff000000 +#define bMaskHWord 0xffff0000 +#define bMaskLWord 0x0000ffff +#define bMaskDWord 0xffffffff + +typedef enum _VERSION_8190{ + // RTL8190 + VERSION_8190_BD=0x3, + VERSION_8190_BE +}VERSION_8190,*PVERSION_8190; + +// +// BB and RF register read/write +// + +extern u32 rtl8192_QueryBBReg(struct net_device* dev,u32 RegAddr, u32 BitMask); +extern void rtl8192_setBBreg(struct net_device* dev,u32 RegAddr, u32 BitMask,u32 Data); +extern u32 rtl8192_phy_QueryRFReg(struct net_device* dev,RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask); +extern void rtl8192_phy_SetRFReg(struct net_device* dev,RF90_RADIO_PATH_E eRFPath, u32 RegAddr,u32 BitMask,u32 Data); + +bool rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath); + + +/* MAC/BB/RF HAL config */ +extern bool PHY_MACConfig8192S(struct net_device* dev); +extern bool PHY_BBConfig8192S(struct net_device* dev); +extern bool PHY_RFConfig8192S(struct net_device* dev); + +extern u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev,RF90_RADIO_PATH_E eRFPath); +extern void rtl8192_SetBWMode(struct net_device* dev,HT_CHANNEL_WIDTH ChnlWidth,HT_EXTCHNL_OFFSET Offset ); +extern u8 rtl8192_phy_SwChnl(struct net_device* dev,u8 channel); +extern u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev,u32 eRFPath ); +extern void rtl8192_BBConfig(struct net_device* dev); +extern void PHY_IQCalibrateBcut(struct net_device* dev); +extern void PHY_IQCalibrate(struct net_device* dev); +extern void PHY_GetHWRegOriginalValue(struct net_device* dev); + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) +extern void InitialGainOperateWorkItemCallBack(struct work_struct *work); +#else +extern void InitialGainOperateWorkItemCallBack(struct net_device *dev); +#endif +void PHY_SetTxPowerLevel8192S(struct net_device* dev, u8 channel); +void PHY_InitialGain8192S(struct net_device* dev,u8 Operation ); + +/*--------------------------Exported Function prototype---------------------*/ +bool HalSetFwCmd8192S(struct net_device* dev, FW_CMD_IO_TYPE FwCmdIO); +extern void PHY_SetBeaconHwReg( struct net_device* dev, u16 BeaconInterval); +void ChkFwCmdIoDone(struct net_device* dev); + +#endif // __INC_HAL8192SPHYCFG_H + diff --git a/drivers/staging/rtl8192su/r8192S_phyreg.h b/drivers/staging/rtl8192su/r8192S_phyreg.h new file mode 100644 index 000000000000..96c7cfa92542 --- /dev/null +++ b/drivers/staging/rtl8192su/r8192S_phyreg.h @@ -0,0 +1,1033 @@ +/***************************************************************************** + * Copyright(c) 2008, RealTEK Technology Inc. All Right Reserved. + * + * Module: __INC_HAL8192SPHYREG_H + * + * + * Note: 1. Define PMAC/BB register map + * 2. Define RF register map + * 3. PMAC/BB register bit mask. + * 4. RF reg bit mask. + * 5. Other BB/RF relative definition. + * + * + * Export: Constants, macro, functions(API), global variables(None). + * + * Abbrev: + * + * History: + * Data Who Remark + * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h. + * 2. Reorganize code architecture. + * 09/25/2008 MH 1. Add RL6052 register definition + * + *****************************************************************************/ +#ifndef __INC_HAL8192SPHYREG_H +#define __INC_HAL8192SPHYREG_H + + +/*--------------------------Define Parameters-------------------------------*/ + +//============================================================ +// 8192S Regsiter offset definition +//============================================================ + +// +// BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF +// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF +// 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 +// 3. RF register 0x00-2E +// 4. Bit Mask for BB/RF register +// 5. Other defintion for BB/RF R/W +// + + +// +// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF +// 1. Page1(0x100) +// +#define rPMAC_Reset 0x100 +#define rPMAC_TxStart 0x104 +#define rPMAC_TxLegacySIG 0x108 +#define rPMAC_TxHTSIG1 0x10c +#define rPMAC_TxHTSIG2 0x110 +#define rPMAC_PHYDebug 0x114 +#define rPMAC_TxPacketNum 0x118 +#define rPMAC_TxIdle 0x11c +#define rPMAC_TxMACHeader0 0x120 +#define rPMAC_TxMACHeader1 0x124 +#define rPMAC_TxMACHeader2 0x128 +#define rPMAC_TxMACHeader3 0x12c +#define rPMAC_TxMACHeader4 0x130 +#define rPMAC_TxMACHeader5 0x134 +#define rPMAC_TxDataType 0x138 +#define rPMAC_TxRandomSeed 0x13c +#define rPMAC_CCKPLCPPreamble 0x140 +#define rPMAC_CCKPLCPHeader 0x144 +#define rPMAC_CCKCRC16 0x148 +#define rPMAC_OFDMRxCRC32OK 0x170 +#define rPMAC_OFDMRxCRC32Er 0x174 +#define rPMAC_OFDMRxParityEr 0x178 +#define rPMAC_OFDMRxCRC8Er 0x17c +#define rPMAC_CCKCRxRC16Er 0x180 +#define rPMAC_CCKCRxRC32Er 0x184 +#define rPMAC_CCKCRxRC32OK 0x188 +#define rPMAC_TxStatus 0x18c + +// +// 2. Page2(0x200) +// +// The following two definition are only used for USB interface. +#define RF_BB_CMD_ADDR 0x02c0 // RF/BB read/write command address. +#define RF_BB_CMD_DATA 0x02c4 // RF/BB read/write command data. + +// +// 3. Page8(0x800) +// +#define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC // RF BW Setting?? + +#define rFPGA0_TxInfo 0x804 // Status report?? +#define rFPGA0_PSDFunction 0x808 + +#define rFPGA0_TxGainStage 0x80c // Set TX PWR init gain? + +#define rFPGA0_RFTiming1 0x810 // Useless now +#define rFPGA0_RFTiming2 0x814 +//#define rFPGA0_XC_RFTiming 0x818 +//#define rFPGA0_XD_RFTiming 0x81c + +#define rFPGA0_XA_HSSIParameter1 0x820 // RF 3 wire register +#define rFPGA0_XA_HSSIParameter2 0x824 +#define rFPGA0_XB_HSSIParameter1 0x828 +#define rFPGA0_XB_HSSIParameter2 0x82c +#define rFPGA0_XC_HSSIParameter1 0x830 +#define rFPGA0_XC_HSSIParameter2 0x834 +#define rFPGA0_XD_HSSIParameter1 0x838 +#define rFPGA0_XD_HSSIParameter2 0x83c +#define rFPGA0_XA_LSSIParameter 0x840 +#define rFPGA0_XB_LSSIParameter 0x844 +#define rFPGA0_XC_LSSIParameter 0x848 +#define rFPGA0_XD_LSSIParameter 0x84c + +#define rFPGA0_RFWakeUpParameter 0x850 // Useless now +#define rFPGA0_RFSleepUpParameter 0x854 + +#define rFPGA0_XAB_SwitchControl 0x858 // RF Channel switch +#define rFPGA0_XCD_SwitchControl 0x85c + +#define rFPGA0_XA_RFInterfaceOE 0x860 // RF Channel switch +#define rFPGA0_XB_RFInterfaceOE 0x864 +#define rFPGA0_XC_RFInterfaceOE 0x868 +#define rFPGA0_XD_RFInterfaceOE 0x86c + +#define rFPGA0_XAB_RFInterfaceSW 0x870 // RF Interface Software Control +#define rFPGA0_XCD_RFInterfaceSW 0x874 + +#define rFPGA0_XAB_RFParameter 0x878 // RF Parameter +#define rFPGA0_XCD_RFParameter 0x87c + +#define rFPGA0_AnalogParameter1 0x880 // Crystal cap setting RF-R/W protection for parameter4?? +#define rFPGA0_AnalogParameter2 0x884 +#define rFPGA0_AnalogParameter3 0x888 // Useless now +#define rFPGA0_AnalogParameter4 0x88c + +#define rFPGA0_XA_LSSIReadBack 0x8a0 // Tranceiver LSSI Readback +#define rFPGA0_XB_LSSIReadBack 0x8a4 +#define rFPGA0_XC_LSSIReadBack 0x8a8 +#define rFPGA0_XD_LSSIReadBack 0x8ac + +#define rFPGA0_PSDReport 0x8b4 // Useless now +#define TransceiverA_HSPI_Readback 0x8b8 // Transceiver A HSPI Readback +#define TransceiverB_HSPI_Readback 0x8bc // Transceiver B HSPI Readback +#define rFPGA0_XAB_RFInterfaceRB 0x8e0 // Useless now // RF Interface Readback Value +#define rFPGA0_XCD_RFInterfaceRB 0x8e4 // Useless now + +// +// 4. Page9(0x900) +// +#define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC // RF BW Setting?? + +#define rFPGA1_TxBlock 0x904 // Useless now +#define rFPGA1_DebugSelect 0x908 // Useless now +#define rFPGA1_TxInfo 0x90c // Useless now // Status report?? + +// +// 5. PageA(0xA00) +// +// Set Control channel to upper or lower. These settings are required only for 40MHz +#define rCCK0_System 0xa00 + +#define rCCK0_AFESetting 0xa04 // Disable init gain now // Select RX path by RSSI +#define rCCK0_CCA 0xa08 // Disable init gain now // Init gain + +#define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series +#define rCCK0_RxAGC2 0xa10 //AGC & DAGC + +#define rCCK0_RxHP 0xa14 + +#define rCCK0_DSPParameter1 0xa18 //Timing recovery & Channel estimation threshold +#define rCCK0_DSPParameter2 0xa1c //SQ threshold + +#define rCCK0_TxFilter1 0xa20 +#define rCCK0_TxFilter2 0xa24 +#define rCCK0_DebugPort 0xa28 //debug port and Tx filter3 +#define rCCK0_FalseAlarmReport 0xa2c //0xa2d useless now 0xa30-a4f channel report +#define rCCK0_TRSSIReport 0xa50 +#define rCCK0_RxReport 0xa54 //0xa57 +#define rCCK0_FACounterLower 0xa5c //0xa5b +#define rCCK0_FACounterUpper 0xa58 //0xa5c + +// +// 6. PageC(0xC00) +// +#define rOFDM0_LSTF 0xc00 + +#define rOFDM0_TRxPathEnable 0xc04 +#define rOFDM0_TRMuxPar 0xc08 +#define rOFDM0_TRSWIsolation 0xc0c + +#define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter +#define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix +#define rOFDM0_XBRxAFE 0xc18 +#define rOFDM0_XBRxIQImbalance 0xc1c +#define rOFDM0_XCRxAFE 0xc20 +#define rOFDM0_XCRxIQImbalance 0xc24 +#define rOFDM0_XDRxAFE 0xc28 +#define rOFDM0_XDRxIQImbalance 0xc2c + +#define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD // DM tune init gain +#define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync. +#define rOFDM0_RxDetector3 0xc38 //Frame Sync. +#define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI + +#define rOFDM0_RxDSP 0xc40 //Rx Sync Path +#define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC +#define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold +#define rOFDM0_ECCAThreshold 0xc4c // energy CCA + +#define rOFDM0_XAAGCCore1 0xc50 // DIG +#define rOFDM0_XAAGCCore2 0xc54 +#define rOFDM0_XBAGCCore1 0xc58 +#define rOFDM0_XBAGCCore2 0xc5c +#define rOFDM0_XCAGCCore1 0xc60 +#define rOFDM0_XCAGCCore2 0xc64 +#define rOFDM0_XDAGCCore1 0xc68 +#define rOFDM0_XDAGCCore2 0xc6c + +#define rOFDM0_AGCParameter1 0xc70 +#define rOFDM0_AGCParameter2 0xc74 +#define rOFDM0_AGCRSSITable 0xc78 +#define rOFDM0_HTSTFAGC 0xc7c + +#define rOFDM0_XATxIQImbalance 0xc80 // TX PWR TRACK and DIG +#define rOFDM0_XATxAFE 0xc84 +#define rOFDM0_XBTxIQImbalance 0xc88 +#define rOFDM0_XBTxAFE 0xc8c +#define rOFDM0_XCTxIQImbalance 0xc90 +#define rOFDM0_XCTxAFE 0xc94 +#define rOFDM0_XDTxIQImbalance 0xc98 +#define rOFDM0_XDTxAFE 0xc9c + +#define rOFDM0_RxHPParameter 0xce0 +#define rOFDM0_TxPseudoNoiseWgt 0xce4 +#define rOFDM0_FrameSync 0xcf0 +#define rOFDM0_DFSReport 0xcf4 +#define rOFDM0_TxCoeff1 0xca4 +#define rOFDM0_TxCoeff2 0xca8 +#define rOFDM0_TxCoeff3 0xcac +#define rOFDM0_TxCoeff4 0xcb0 +#define rOFDM0_TxCoeff5 0xcb4 +#define rOFDM0_TxCoeff6 0xcb8 + + +// +// 7. PageD(0xD00) +// +#define rOFDM1_LSTF 0xd00 +#define rOFDM1_TRxPathEnable 0xd04 +#define rOFDM1_CFO 0xd08 // No setting now +#define rOFDM1_CSI1 0xd10 +#define rOFDM1_SBD 0xd14 +#define rOFDM1_CSI2 0xd18 +#define rOFDM1_CFOTracking 0xd2c +#define rOFDM1_TRxMesaure1 0xd34 +#define rOFDM1_IntfDet 0xd3c +#define rOFDM1_PseudoNoiseStateAB 0xd50 +#define rOFDM1_PseudoNoiseStateCD 0xd54 +#define rOFDM1_RxPseudoNoiseWgt 0xd58 + +#define rOFDM_PHYCounter1 0xda0 //cca, parity fail +#define rOFDM_PHYCounter2 0xda4 //rate illegal, crc8 fail +#define rOFDM_PHYCounter3 0xda8 //MCS not support +#define rOFDM_ShortCFOAB 0xdac // No setting now +#define rOFDM_ShortCFOCD 0xdb0 +#define rOFDM_LongCFOAB 0xdb4 +#define rOFDM_LongCFOCD 0xdb8 +#define rOFDM_TailCFOAB 0xdbc +#define rOFDM_TailCFOCD 0xdc0 +#define rOFDM_PWMeasure1 0xdc4 +#define rOFDM_PWMeasure2 0xdc8 +#define rOFDM_BWReport 0xdcc +#define rOFDM_AGCReport 0xdd0 +#define rOFDM_RxSNR 0xdd4 +#define rOFDM_RxEVMCSI 0xdd8 +#define rOFDM_SIGReport 0xddc + + +// +// 8. PageE(0xE00) +// +#define rTxAGC_Rate18_06 0xe00 +#define rTxAGC_Rate54_24 0xe04 +#define rTxAGC_CCK_Mcs32 0xe08 +#define rTxAGC_Mcs03_Mcs00 0xe10 +#define rTxAGC_Mcs07_Mcs04 0xe14 +#define rTxAGC_Mcs11_Mcs08 0xe18 +#define rTxAGC_Mcs15_Mcs12 0xe1c + +// +// 7. RF Register 0x00-0x2E (RF 8256) +// RF-0222D 0x00-3F +// +//Zebra1 +#define rZebra1_HSSIEnable 0x0 // Useless now +#define rZebra1_TRxEnable1 0x1 +#define rZebra1_TRxEnable2 0x2 +#define rZebra1_AGC 0x4 +#define rZebra1_ChargePump 0x5 +//#if (RTL92SE_FPGA_VERIFY == 1) +#define rZebra1_Channel 0x7 // RF channel switch +//#else + +//#endif +#define rZebra1_TxGain 0x8 // Useless now +#define rZebra1_TxLPF 0x9 +#define rZebra1_RxLPF 0xb +#define rZebra1_RxHPFCorner 0xc + +//Zebra4 +#define rGlobalCtrl 0 // Useless now +#define rRTL8256_TxLPF 19 +#define rRTL8256_RxLPF 11 + +//RTL8258 +#define rRTL8258_TxLPF 0x11 // Useless now +#define rRTL8258_RxLPF 0x13 +#define rRTL8258_RSSILPF 0xa + +// +// RL6052 Register definition +// +#define RF_AC 0x00 // + +#define RF_IQADJ_G1 0x01 // +#define RF_IQADJ_G2 0x02 // +#define RF_POW_TRSW 0x05 // + +#define RF_GAIN_RX 0x06 // +#define RF_GAIN_TX 0x07 // + +#define RF_TXM_IDAC 0x08 // +#define RF_BS_IQGEN 0x0F // + +#define RF_MODE1 0x10 // +#define RF_MODE2 0x11 // + +#define RF_RX_AGC_HP 0x12 // +#define RF_TX_AGC 0x13 // +#define RF_BIAS 0x14 // +#define RF_IPA 0x15 // +#define RF_POW_ABILITY 0x17 // +#define RF_MODE_AG 0x18 // +#define rRfChannel 0x18 // RF channel and BW switch +#define RF_CHNLBW 0x18 // RF channel and BW switch +#define RF_TOP 0x19 // + +#define RF_RX_G1 0x1A // +#define RF_RX_G2 0x1B // + +#define RF_RX_BB2 0x1C // +#define RF_RX_BB1 0x1D // + +#define RF_RCK1 0x1E // +#define RF_RCK2 0x1F // + +#define RF_TX_G1 0x20 // +#define RF_TX_G2 0x21 // +#define RF_TX_G3 0x22 // + +#define RF_TX_BB1 0x23 // + +#define RF_T_METER 0x24 // + +#define RF_SYN_G1 0x25 // RF TX Power control +#define RF_SYN_G2 0x26 // RF TX Power control +#define RF_SYN_G3 0x27 // RF TX Power control +#define RF_SYN_G4 0x28 // RF TX Power control +#define RF_SYN_G5 0x29 // RF TX Power control +#define RF_SYN_G6 0x2A // RF TX Power control +#define RF_SYN_G7 0x2B // RF TX Power control +#define RF_SYN_G8 0x2C // RF TX Power control + +#define RF_RCK_OS 0x30 // RF TX PA control + +#define RF_TXPA_G1 0x31 // RF TX PA control +#define RF_TXPA_G2 0x32 // RF TX PA control +#define RF_TXPA_G3 0x33 // RF TX PA control + +// +//Bit Mask +// +// 1. Page1(0x100) +#define bBBResetB 0x100 // Useless now? +#define bGlobalResetB 0x200 +#define bOFDMTxStart 0x4 +#define bCCKTxStart 0x8 +#define bCRC32Debug 0x100 +#define bPMACLoopback 0x10 +#define bTxLSIG 0xffffff +#define bOFDMTxRate 0xf +#define bOFDMTxReserved 0x10 +#define bOFDMTxLength 0x1ffe0 +#define bOFDMTxParity 0x20000 +#define bTxHTSIG1 0xffffff +#define bTxHTMCSRate 0x7f +#define bTxHTBW 0x80 +#define bTxHTLength 0xffff00 +#define bTxHTSIG2 0xffffff +#define bTxHTSmoothing 0x1 +#define bTxHTSounding 0x2 +#define bTxHTReserved 0x4 +#define bTxHTAggreation 0x8 +#define bTxHTSTBC 0x30 +#define bTxHTAdvanceCoding 0x40 +#define bTxHTShortGI 0x80 +#define bTxHTNumberHT_LTF 0x300 +#define bTxHTCRC8 0x3fc00 +#define bCounterReset 0x10000 +#define bNumOfOFDMTx 0xffff +#define bNumOfCCKTx 0xffff0000 +#define bTxIdleInterval 0xffff +#define bOFDMService 0xffff0000 +#define bTxMACHeader 0xffffffff +#define bTxDataInit 0xff +#define bTxHTMode 0x100 +#define bTxDataType 0x30000 +#define bTxRandomSeed 0xffffffff +#define bCCKTxPreamble 0x1 +#define bCCKTxSFD 0xffff0000 +#define bCCKTxSIG 0xff +#define bCCKTxService 0xff00 +#define bCCKLengthExt 0x8000 +#define bCCKTxLength 0xffff0000 +#define bCCKTxCRC16 0xffff +#define bCCKTxStatus 0x1 +#define bOFDMTxStatus 0x2 + +#define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff)) + +// 2. Page8(0x800) +#define bRFMOD 0x1 // Reg 0x800 rFPGA0_RFMOD +#define bJapanMode 0x2 +#define bCCKTxSC 0x30 +#define bCCKEn 0x1000000 +#define bOFDMEn 0x2000000 + +#define bOFDMRxADCPhase 0x10000 // Useless now +#define bOFDMTxDACPhase 0x40000 +#define bXATxAGC 0x3f + +#define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage +#define bXCTxAGC 0xf000 +#define bXDTxAGC 0xf0000 + +#define bPAStart 0xf0000000 // Useless now +#define bTRStart 0x00f00000 +#define bRFStart 0x0000f000 +#define bBBStart 0x000000f0 +#define bBBCCKStart 0x0000000f +#define bPAEnd 0xf //Reg0x814 +#define bTREnd 0x0f000000 +#define bRFEnd 0x000f0000 +#define bCCAMask 0x000000f0 //T2R +#define bR2RCCAMask 0x00000f00 +#define bHSSI_R2TDelay 0xf8000000 +#define bHSSI_T2RDelay 0xf80000 +#define bContTxHSSI 0x400 //chane gain at continue Tx +#define bIGFromCCK 0x200 +#define bAGCAddress 0x3f +#define bRxHPTx 0x7000 +#define bRxHPT2R 0x38000 +#define bRxHPCCKIni 0xc0000 +#define bAGCTxCode 0xc00000 +#define bAGCRxCode 0x300000 + +#define b3WireDataLength 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1 +#define b3WireAddressLength 0x400 + +#define b3WireRFPowerDown 0x1 // Useless now +//#define bHWSISelect 0x8 +#define b5GPAPEPolarity 0x40000000 +#define b2GPAPEPolarity 0x80000000 +#define bRFSW_TxDefaultAnt 0x3 +#define bRFSW_TxOptionAnt 0x30 +#define bRFSW_RxDefaultAnt 0x300 +#define bRFSW_RxOptionAnt 0x3000 +#define bRFSI_3WireData 0x1 +#define bRFSI_3WireClock 0x2 +#define bRFSI_3WireLoad 0x4 +#define bRFSI_3WireRW 0x8 +#define bRFSI_3Wire 0xf + +#define bRFSI_RFENV 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW + +#define bRFSI_TRSW 0x20 // Useless now +#define bRFSI_TRSWB 0x40 +#define bRFSI_ANTSW 0x100 +#define bRFSI_ANTSWB 0x200 +#define bRFSI_PAPE 0x400 +#define bRFSI_PAPE5G 0x800 +#define bBandSelect 0x1 +#define bHTSIG2_GI 0x80 +#define bHTSIG2_Smoothing 0x01 +#define bHTSIG2_Sounding 0x02 +#define bHTSIG2_Aggreaton 0x08 +#define bHTSIG2_STBC 0x30 +#define bHTSIG2_AdvCoding 0x40 +#define bHTSIG2_NumOfHTLTF 0x300 +#define bHTSIG2_CRC8 0x3fc +#define bHTSIG1_MCS 0x7f +#define bHTSIG1_BandWidth 0x80 +#define bHTSIG1_HTLength 0xffff +#define bLSIG_Rate 0xf +#define bLSIG_Reserved 0x10 +#define bLSIG_Length 0x1fffe +#define bLSIG_Parity 0x20 +#define bCCKRxPhase 0x4 +#define bLSSIReadAddress 0x7f800000 // T65 RF +#define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal +#define bLSSIReadBackData 0xfffff // T65 RF +#define bLSSIReadOKFlag 0x1000 // Useless now +#define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz +#define bRegulator0Standby 0x1 +#define bRegulatorPLLStandby 0x2 +#define bRegulator1Standby 0x4 +#define bPLLPowerUp 0x8 +#define bDPLLPowerUp 0x10 +#define bDA10PowerUp 0x20 +#define bAD7PowerUp 0x200 +#define bDA6PowerUp 0x2000 +#define bXtalPowerUp 0x4000 +#define b40MDClkPowerUP 0x8000 +#define bDA6DebugMode 0x20000 +#define bDA6Swing 0x380000 + +#define bADClkPhase 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ + +#define b80MClkDelay 0x18000000 // Useless +#define bAFEWatchDogEnable 0x20000000 + +#define bXtalCap01 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap +#define bXtalCap23 0x3 +#define bXtalCap92x 0x0f000000 +#define bXtalCap 0x0f000000 + +#define bIntDifClkEnable 0x400 // Useless +#define bExtSigClkEnable 0x800 +#define bBandgapMbiasPowerUp 0x10000 +#define bAD11SHGain 0xc0000 +#define bAD11InputRange 0x700000 +#define bAD11OPCurrent 0x3800000 +#define bIPathLoopback 0x4000000 +#define bQPathLoopback 0x8000000 +#define bAFELoopback 0x10000000 +#define bDA10Swing 0x7e0 +#define bDA10Reverse 0x800 +#define bDAClkSource 0x1000 +#define bAD7InputRange 0x6000 +#define bAD7Gain 0x38000 +#define bAD7OutputCMMode 0x40000 +#define bAD7InputCMMode 0x380000 +#define bAD7Current 0xc00000 +#define bRegulatorAdjust 0x7000000 +#define bAD11PowerUpAtTx 0x1 +#define bDA10PSAtTx 0x10 +#define bAD11PowerUpAtRx 0x100 +#define bDA10PSAtRx 0x1000 +#define bCCKRxAGCFormat 0x200 +#define bPSDFFTSamplepPoint 0xc000 +#define bPSDAverageNum 0x3000 +#define bIQPathControl 0xc00 +#define bPSDFreq 0x3ff +#define bPSDAntennaPath 0x30 +#define bPSDIQSwitch 0x40 +#define bPSDRxTrigger 0x400000 +#define bPSDTxTrigger 0x80000000 +#define bPSDSineToneScale 0x7f000000 +#define bPSDReport 0xffff + +// 3. Page9(0x900) +#define bOFDMTxSC 0x30000000 // Useless +#define bCCKTxOn 0x1 +#define bOFDMTxOn 0x2 +#define bDebugPage 0xfff //reset debug page and also HWord, LWord +#define bDebugItem 0xff //reset debug page and LWord +#define bAntL 0x10 +#define bAntNonHT 0x100 +#define bAntHT1 0x1000 +#define bAntHT2 0x10000 +#define bAntHT1S1 0x100000 +#define bAntNonHTS1 0x1000000 + +// 4. PageA(0xA00) +#define bCCKBBMode 0x3 // Useless +#define bCCKTxPowerSaving 0x80 +#define bCCKRxPowerSaving 0x40 + +#define bCCKSideBand 0x10 // Reg 0xa00 rCCK0_System 20/40 switch + +#define bCCKScramble 0x8 // Useless +#define bCCKAntDiversity 0x8000 +#define bCCKCarrierRecovery 0x4000 +#define bCCKTxRate 0x3000 +#define bCCKDCCancel 0x0800 +#define bCCKISICancel 0x0400 +#define bCCKMatchFilter 0x0200 +#define bCCKEqualizer 0x0100 +#define bCCKPreambleDetect 0x800000 +#define bCCKFastFalseCCA 0x400000 +#define bCCKChEstStart 0x300000 +#define bCCKCCACount 0x080000 +#define bCCKcs_lim 0x070000 +#define bCCKBistMode 0x80000000 +#define bCCKCCAMask 0x40000000 +#define bCCKTxDACPhase 0x4 +#define bCCKRxADCPhase 0x20000000 //r_rx_clk +#define bCCKr_cp_mode0 0x0100 +#define bCCKTxDCOffset 0xf0 +#define bCCKRxDCOffset 0xf +#define bCCKCCAMode 0xc000 +#define bCCKFalseCS_lim 0x3f00 +#define bCCKCS_ratio 0xc00000 +#define bCCKCorgBit_sel 0x300000 +#define bCCKPD_lim 0x0f0000 +#define bCCKNewCCA 0x80000000 +#define bCCKRxHPofIG 0x8000 +#define bCCKRxIG 0x7f00 +#define bCCKLNAPolarity 0x800000 +#define bCCKRx1stGain 0x7f0000 +#define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity +#define bCCKRxAGCSatLevel 0x1f000000 +#define bCCKRxAGCSatCount 0xe0 +#define bCCKRxRFSettle 0x1f //AGCsamp_dly +#define bCCKFixedRxAGC 0x8000 +//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824 +#define bCCKAntennaPolarity 0x2000 +#define bCCKTxFilterType 0x0c00 +#define bCCKRxAGCReportType 0x0300 +#define bCCKRxDAGCEn 0x80000000 +#define bCCKRxDAGCPeriod 0x20000000 +#define bCCKRxDAGCSatLevel 0x1f000000 +#define bCCKTimingRecovery 0x800000 +#define bCCKTxC0 0x3f0000 +#define bCCKTxC1 0x3f000000 +#define bCCKTxC2 0x3f +#define bCCKTxC3 0x3f00 +#define bCCKTxC4 0x3f0000 +#define bCCKTxC5 0x3f000000 +#define bCCKTxC6 0x3f +#define bCCKTxC7 0x3f00 +#define bCCKDebugPort 0xff0000 +#define bCCKDACDebug 0x0f000000 +#define bCCKFalseAlarmEnable 0x8000 +#define bCCKFalseAlarmRead 0x4000 +#define bCCKTRSSI 0x7f +#define bCCKRxAGCReport 0xfe +#define bCCKRxReport_AntSel 0x80000000 +#define bCCKRxReport_MFOff 0x40000000 +#define bCCKRxRxReport_SQLoss 0x20000000 +#define bCCKRxReport_Pktloss 0x10000000 +#define bCCKRxReport_Lockedbit 0x08000000 +#define bCCKRxReport_RateError 0x04000000 +#define bCCKRxReport_RxRate 0x03000000 +#define bCCKRxFACounterLower 0xff +#define bCCKRxFACounterUpper 0xff000000 +#define bCCKRxHPAGCStart 0xe000 +#define bCCKRxHPAGCFinal 0x1c00 +#define bCCKRxFalseAlarmEnable 0x8000 +#define bCCKFACounterFreeze 0x4000 +#define bCCKTxPathSel 0x10000000 +#define bCCKDefaultRxPath 0xc000000 +#define bCCKOptionRxPath 0x3000000 + +// 5. PageC(0xC00) +#define bNumOfSTF 0x3 // Useless +#define bShift_L 0xc0 +#define bGI_TH 0xc +#define bRxPathA 0x1 +#define bRxPathB 0x2 +#define bRxPathC 0x4 +#define bRxPathD 0x8 +#define bTxPathA 0x1 +#define bTxPathB 0x2 +#define bTxPathC 0x4 +#define bTxPathD 0x8 +#define bTRSSIFreq 0x200 +#define bADCBackoff 0x3000 +#define bDFIRBackoff 0xc000 +#define bTRSSILatchPhase 0x10000 +#define bRxIDCOffset 0xff +#define bRxQDCOffset 0xff00 +#define bRxDFIRMode 0x1800000 +#define bRxDCNFType 0xe000000 +#define bRXIQImb_A 0x3ff +#define bRXIQImb_B 0xfc00 +#define bRXIQImb_C 0x3f0000 +#define bRXIQImb_D 0xffc00000 +#define bDC_dc_Notch 0x60000 +#define bRxNBINotch 0x1f000000 +#define bPD_TH 0xf +#define bPD_TH_Opt2 0xc000 +#define bPWED_TH 0x700 +#define bIfMF_Win_L 0x800 +#define bPD_Option 0x1000 +#define bMF_Win_L 0xe000 +#define bBW_Search_L 0x30000 +#define bwin_enh_L 0xc0000 +#define bBW_TH 0x700000 +#define bED_TH2 0x3800000 +#define bBW_option 0x4000000 +#define bRatio_TH 0x18000000 +#define bWindow_L 0xe0000000 +#define bSBD_Option 0x1 +#define bFrame_TH 0x1c +#define bFS_Option 0x60 +#define bDC_Slope_check 0x80 +#define bFGuard_Counter_DC_L 0xe00 +#define bFrame_Weight_Short 0x7000 +#define bSub_Tune 0xe00000 +#define bFrame_DC_Length 0xe000000 +#define bSBD_start_offset 0x30000000 +#define bFrame_TH_2 0x7 +#define bFrame_GI2_TH 0x38 +#define bGI2_Sync_en 0x40 +#define bSarch_Short_Early 0x300 +#define bSarch_Short_Late 0xc00 +#define bSarch_GI2_Late 0x70000 +#define bCFOAntSum 0x1 +#define bCFOAcc 0x2 +#define bCFOStartOffset 0xc +#define bCFOLookBack 0x70 +#define bCFOSumWeight 0x80 +#define bDAGCEnable 0x10000 +#define bTXIQImb_A 0x3ff +#define bTXIQImb_B 0xfc00 +#define bTXIQImb_C 0x3f0000 +#define bTXIQImb_D 0xffc00000 +#define bTxIDCOffset 0xff +#define bTxQDCOffset 0xff00 +#define bTxDFIRMode 0x10000 +#define bTxPesudoNoiseOn 0x4000000 +#define bTxPesudoNoise_A 0xff +#define bTxPesudoNoise_B 0xff00 +#define bTxPesudoNoise_C 0xff0000 +#define bTxPesudoNoise_D 0xff000000 +#define bCCADropOption 0x20000 +#define bCCADropThres 0xfff00000 +#define bEDCCA_H 0xf +#define bEDCCA_L 0xf0 +#define bLambda_ED 0x300 +#define bRxInitialGain 0x7f +#define bRxAntDivEn 0x80 +#define bRxAGCAddressForLNA 0x7f00 +#define bRxHighPowerFlow 0x8000 +#define bRxAGCFreezeThres 0xc0000 +#define bRxFreezeStep_AGC1 0x300000 +#define bRxFreezeStep_AGC2 0xc00000 +#define bRxFreezeStep_AGC3 0x3000000 +#define bRxFreezeStep_AGC0 0xc000000 +#define bRxRssi_Cmp_En 0x10000000 +#define bRxQuickAGCEn 0x20000000 +#define bRxAGCFreezeThresMode 0x40000000 +#define bRxOverFlowCheckType 0x80000000 +#define bRxAGCShift 0x7f +#define bTRSW_Tri_Only 0x80 +#define bPowerThres 0x300 +#define bRxAGCEn 0x1 +#define bRxAGCTogetherEn 0x2 +#define bRxAGCMin 0x4 +#define bRxHP_Ini 0x7 +#define bRxHP_TRLNA 0x70 +#define bRxHP_RSSI 0x700 +#define bRxHP_BBP1 0x7000 +#define bRxHP_BBP2 0x70000 +#define bRxHP_BBP3 0x700000 +#define bRSSI_H 0x7f0000 //the threshold for high power +#define bRSSI_Gen 0x7f000000 //the threshold for ant diversity +#define bRxSettle_TRSW 0x7 +#define bRxSettle_LNA 0x38 +#define bRxSettle_RSSI 0x1c0 +#define bRxSettle_BBP 0xe00 +#define bRxSettle_RxHP 0x7000 +#define bRxSettle_AntSW_RSSI 0x38000 +#define bRxSettle_AntSW 0xc0000 +#define bRxProcessTime_DAGC 0x300000 +#define bRxSettle_HSSI 0x400000 +#define bRxProcessTime_BBPPW 0x800000 +#define bRxAntennaPowerShift 0x3000000 +#define bRSSITableSelect 0xc000000 +#define bRxHP_Final 0x7000000 +#define bRxHTSettle_BBP 0x7 +#define bRxHTSettle_HSSI 0x8 +#define bRxHTSettle_RxHP 0x70 +#define bRxHTSettle_BBPPW 0x80 +#define bRxHTSettle_Idle 0x300 +#define bRxHTSettle_Reserved 0x1c00 +#define bRxHTRxHPEn 0x8000 +#define bRxHTAGCFreezeThres 0x30000 +#define bRxHTAGCTogetherEn 0x40000 +#define bRxHTAGCMin 0x80000 +#define bRxHTAGCEn 0x100000 +#define bRxHTDAGCEn 0x200000 +#define bRxHTRxHP_BBP 0x1c00000 +#define bRxHTRxHP_Final 0xe0000000 +#define bRxPWRatioTH 0x3 +#define bRxPWRatioEn 0x4 +#define bRxMFHold 0x3800 +#define bRxPD_Delay_TH1 0x38 +#define bRxPD_Delay_TH2 0x1c0 +#define bRxPD_DC_COUNT_MAX 0x600 +//#define bRxMF_Hold 0x3800 +#define bRxPD_Delay_TH 0x8000 +#define bRxProcess_Delay 0xf0000 +#define bRxSearchrange_GI2_Early 0x700000 +#define bRxFrame_Guard_Counter_L 0x3800000 +#define bRxSGI_Guard_L 0xc000000 +#define bRxSGI_Search_L 0x30000000 +#define bRxSGI_TH 0xc0000000 +#define bDFSCnt0 0xff +#define bDFSCnt1 0xff00 +#define bDFSFlag 0xf0000 +#define bMFWeightSum 0x300000 +#define bMinIdxTH 0x7f000000 +#define bDAFormat 0x40000 +#define bTxChEmuEnable 0x01000000 +#define bTRSWIsolation_A 0x7f +#define bTRSWIsolation_B 0x7f00 +#define bTRSWIsolation_C 0x7f0000 +#define bTRSWIsolation_D 0x7f000000 +#define bExtLNAGain 0x7c00 + +// 6. PageE(0xE00) +#define bSTBCEn 0x4 // Useless +#define bAntennaMapping 0x10 +#define bNss 0x20 +#define bCFOAntSumD 0x200 +#define bPHYCounterReset 0x8000000 +#define bCFOReportGet 0x4000000 +#define bOFDMContinueTx 0x10000000 +#define bOFDMSingleCarrier 0x20000000 +#define bOFDMSingleTone 0x40000000 +//#define bRxPath1 0x01 +//#define bRxPath2 0x02 +//#define bRxPath3 0x04 +//#define bRxPath4 0x08 +//#define bTxPath1 0x10 +//#define bTxPath2 0x20 +#define bHTDetect 0x100 +#define bCFOEn 0x10000 +#define bCFOValue 0xfff00000 +#define bSigTone_Re 0x3f +#define bSigTone_Im 0x7f00 +#define bCounter_CCA 0xffff +#define bCounter_ParityFail 0xffff0000 +#define bCounter_RateIllegal 0xffff +#define bCounter_CRC8Fail 0xffff0000 +#define bCounter_MCSNoSupport 0xffff +#define bCounter_FastSync 0xffff +#define bShortCFO 0xfff +#define bShortCFOTLength 12 //total +#define bShortCFOFLength 11 //fraction +#define bLongCFO 0x7ff +#define bLongCFOTLength 11 +#define bLongCFOFLength 11 +#define bTailCFO 0x1fff +#define bTailCFOTLength 13 +#define bTailCFOFLength 12 +#define bmax_en_pwdB 0xffff +#define bCC_power_dB 0xffff0000 +#define bnoise_pwdB 0xffff +#define bPowerMeasTLength 10 +#define bPowerMeasFLength 3 +#define bRx_HT_BW 0x1 +#define bRxSC 0x6 +#define bRx_HT 0x8 +#define bNB_intf_det_on 0x1 +#define bIntf_win_len_cfg 0x30 +#define bNB_Intf_TH_cfg 0x1c0 +#define bRFGain 0x3f +#define bTableSel 0x40 +#define bTRSW 0x80 +#define bRxSNR_A 0xff +#define bRxSNR_B 0xff00 +#define bRxSNR_C 0xff0000 +#define bRxSNR_D 0xff000000 +#define bSNREVMTLength 8 +#define bSNREVMFLength 1 +#define bCSI1st 0xff +#define bCSI2nd 0xff00 +#define bRxEVM1st 0xff0000 +#define bRxEVM2nd 0xff000000 +#define bSIGEVM 0xff +#define bPWDB 0xff00 +#define bSGIEN 0x10000 + +#define bSFactorQAM1 0xf // Useless +#define bSFactorQAM2 0xf0 +#define bSFactorQAM3 0xf00 +#define bSFactorQAM4 0xf000 +#define bSFactorQAM5 0xf0000 +#define bSFactorQAM6 0xf0000 +#define bSFactorQAM7 0xf00000 +#define bSFactorQAM8 0xf000000 +#define bSFactorQAM9 0xf0000000 +#define bCSIScheme 0x100000 + +#define bNoiseLvlTopSet 0x3 // Useless +#define bChSmooth 0x4 +#define bChSmoothCfg1 0x38 +#define bChSmoothCfg2 0x1c0 +#define bChSmoothCfg3 0xe00 +#define bChSmoothCfg4 0x7000 +#define bMRCMode 0x800000 +#define bTHEVMCfg 0x7000000 + +#define bLoopFitType 0x1 // Useless +#define bUpdCFO 0x40 +#define bUpdCFOOffData 0x80 +#define bAdvUpdCFO 0x100 +#define bAdvTimeCtrl 0x800 +#define bUpdClko 0x1000 +#define bFC 0x6000 +#define bTrackingMode 0x8000 +#define bPhCmpEnable 0x10000 +#define bUpdClkoLTF 0x20000 +#define bComChCFO 0x40000 +#define bCSIEstiMode 0x80000 +#define bAdvUpdEqz 0x100000 +#define bUChCfg 0x7000000 +#define bUpdEqz 0x8000000 + +#define bTxAGCRate18_06 0x7f7f7f7f // Useless +#define bTxAGCRate54_24 0x7f7f7f7f +#define bTxAGCRateMCS32 0x7f +#define bTxAGCRateCCK 0x7f00 +#define bTxAGCRateMCS3_MCS0 0x7f7f7f7f +#define bTxAGCRateMCS7_MCS4 0x7f7f7f7f +#define bTxAGCRateMCS11_MCS8 0x7f7f7f7f +#define bTxAGCRateMCS15_MCS12 0x7f7f7f7f + +//Rx Pseduo noise +#define bRxPesudoNoiseOn 0x20000000 // Useless +#define bRxPesudoNoise_A 0xff +#define bRxPesudoNoise_B 0xff00 +#define bRxPesudoNoise_C 0xff0000 +#define bRxPesudoNoise_D 0xff000000 +#define bPesudoNoiseState_A 0xffff +#define bPesudoNoiseState_B 0xffff0000 +#define bPesudoNoiseState_C 0xffff +#define bPesudoNoiseState_D 0xffff0000 + +//7. RF Register +//Zebra1 +#define bZebra1_HSSIEnable 0x8 // Useless +#define bZebra1_TRxControl 0xc00 +#define bZebra1_TRxGainSetting 0x07f +#define bZebra1_RxCorner 0xc00 +#define bZebra1_TxChargePump 0x38 +#define bZebra1_RxChargePump 0x7 +#define bZebra1_ChannelNum 0xf80 +#define bZebra1_TxLPFBW 0x400 +#define bZebra1_RxLPFBW 0x600 + +//Zebra4 +#define bRTL8256RegModeCtrl1 0x100 // Useless +#define bRTL8256RegModeCtrl0 0x40 +#define bRTL8256_TxLPFBW 0x18 +#define bRTL8256_RxLPFBW 0x600 + +//RTL8258 +#define bRTL8258_TxLPFBW 0xc // Useless +#define bRTL8258_RxLPFBW 0xc00 +#define bRTL8258_RSSILPFBW 0xc0 + + +// +// Other Definition +// + +//byte endable for sb_write +#define bByte0 0x1 // Useless +#define bByte1 0x2 +#define bByte2 0x4 +#define bByte3 0x8 +#define bWord0 0x3 +#define bWord1 0xc +#define bDWord 0xf + +//for PutRegsetting & GetRegSetting BitMask +#define bMaskByte0 0xff // Reg 0xc50 rOFDM0_XAAGCCore~0xC6f +#define bMaskByte1 0xff00 +#define bMaskByte2 0xff0000 +#define bMaskByte3 0xff000000 +#define bMaskHWord 0xffff0000 +#define bMaskLWord 0x0000ffff +#define bMaskDWord 0xffffffff + +//for PutRFRegsetting & GetRFRegSetting BitMask +#define bMask12Bits 0xfffff // RF Reg mask bits +#define bMask20Bits 0xfffff // RF Reg mask bits T65 RF +#define bRFRegOffsetMask 0xfffff + +#define bEnable 0x1 // Useless +#define bDisable 0x0 + +#define LeftAntenna 0x0 // Useless +#define RightAntenna 0x1 + +#define tCheckTxStatus 500 //500ms // Useless +#define tUpdateRxCounter 100 //100ms + +#define rateCCK 0 // Useless +#define rateOFDM 1 +#define rateHT 2 + +//define Register-End +#define bPMAC_End 0x1ff // Useless +#define bFPGAPHY0_End 0x8ff +#define bFPGAPHY1_End 0x9ff +#define bCCKPHY0_End 0xaff +#define bOFDMPHY0_End 0xcff +#define bOFDMPHY1_End 0xdff + +//define max debug item in each debug page +//#define bMaxItem_FPGA_PHY0 0x9 +//#define bMaxItem_FPGA_PHY1 0x3 +//#define bMaxItem_PHY_11B 0x16 +//#define bMaxItem_OFDM_PHY0 0x29 +//#define bMaxItem_OFDM_PHY1 0x0 + +#define bPMACControl 0x0 // Useless +#define bWMACControl 0x1 +#define bWNICControl 0x2 + +#define PathA 0x0 // Useless +#define PathB 0x1 +#define PathC 0x2 +#define PathD 0x3 + +/*--------------------------Define Parameters-------------------------------*/ + + +#endif //__INC_HAL8192SPHYREG_H + diff --git a/drivers/staging/rtl8192su/r8192S_rtl6052.c b/drivers/staging/rtl8192su/r8192S_rtl6052.c new file mode 100644 index 000000000000..71caf81a6e10 --- /dev/null +++ b/drivers/staging/rtl8192su/r8192S_rtl6052.c @@ -0,0 +1,946 @@ +/****************************************************************************** + * + * (c) Copyright 2008, RealTEK Technologies Inc. All Rights Reserved. + * + * Module: HalRf6052.c ( Source C File) + * + * Note: Provide RF 6052 series relative API. + * + * Function: + * + * Export: + * + * Abbrev: + * + * History: + * Data Who Remark + * + * 09/25/2008 MHC Create initial version. + * 11/05/2008 MHC Add API for tw power setting. + * + * +******************************************************************************/ +#include "r8192U.h" +#include "r8192S_rtl6052.h" + +#ifdef RTL8192SU +#include "r8192S_hw.h" +#include "r8192S_phyreg.h" +#include "r8192S_phy.h" +#else +#include "r8192U_hw.h" +#include "r819xU_phyreg.h" +#include "r819xU_phy.h" +#endif + + +/*---------------------------Define Local Constant---------------------------*/ +// Define local structure for debug!!!!! +typedef struct RF_Shadow_Compare_Map { + // Shadow register value + u32 Value; + // Compare or not flag + u8 Compare; + // Record If it had ever modified unpredicted + u8 ErrorOrNot; + // Recorver Flag + u8 Recorver; + // + u8 Driver_Write; +}RF_SHADOW_T; +/*---------------------------Define Local Constant---------------------------*/ + + +/*------------------------Define global variable-----------------------------*/ +/*------------------------Define global variable-----------------------------*/ + + + + +/*---------------------Define local function prototype-----------------------*/ +void phy_RF6052_Config_HardCode(struct net_device* dev); + +RT_STATUS phy_RF6052_Config_ParaFile(struct net_device* dev); +/*---------------------Define local function prototype-----------------------*/ + +/*------------------------Define function prototype--------------------------*/ +extern void RF_ChangeTxPath(struct net_device* dev, u16 DataRate); + +/*------------------------Define function prototype--------------------------*/ + +/*------------------------Define local variable------------------------------*/ +// 2008/11/20 MH For Debug only, RF +static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG];// = {{0}};//FIXLZM +/*------------------------Define local variable------------------------------*/ + +/*------------------------Define function prototype--------------------------*/ +/*----------------------------------------------------------------------------- + * Function: RF_ChangeTxPath + * + * Overview: For RL6052, we must change some RF settign for 1T or 2T. + * + * Input: u16 DataRate // 0x80-8f, 0x90-9f + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 09/25/2008 MHC Create Version 0. + * Firmwaer support the utility later. + * + *---------------------------------------------------------------------------*/ +extern void RF_ChangeTxPath(struct net_device* dev, u16 DataRate) +{ +// We do not support gain table change inACUT now !!!! Delete later !!! +#if 0//(RTL92SE_FPGA_VERIFY == 0) + static u1Byte RF_Path_Type = 2; // 1 = 1T 2= 2T + static u4Byte tx_gain_tbl1[6] + = {0x17f50, 0x11f40, 0x0cf30, 0x08720, 0x04310, 0x00100}; + static u4Byte tx_gain_tbl2[6] + = {0x15ea0, 0x10e90, 0x0c680, 0x08250, 0x04040, 0x00030}; + u1Byte i; + + if (RF_Path_Type == 2 && (DataRate&0xF) <= 0x7) + { + // Set TX SYNC power G2G3 loop filter + PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, + RF_TXPA_G2, bMask20Bits, 0x0f000); + PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, + RF_TXPA_G3, bMask20Bits, 0xeacf1); + + // Change TX AGC gain table + for (i = 0; i < 6; i++) + PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, + RF_TX_AGC, bMask20Bits, tx_gain_tbl1[i]); + + // Set PA to high value + PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, + RF_TXPA_G2, bMask20Bits, 0x01e39); + } + else if (RF_Path_Type == 1 && (DataRate&0xF) >= 0x8) + { + // Set TX SYNC power G2G3 loop filter + PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, + RF_TXPA_G2, bMask20Bits, 0x04440); + PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, + RF_TXPA_G3, bMask20Bits, 0xea4f1); + + // Change TX AGC gain table + for (i = 0; i < 6; i++) + PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, + RF_TX_AGC, bMask20Bits, tx_gain_tbl2[i]); + + // Set PA low gain + PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, + RF_TXPA_G2, bMask20Bits, 0x01e19); + } +#endif + +} /* RF_ChangeTxPath */ + + +/*----------------------------------------------------------------------------- + * Function: PHY_RF6052SetBandwidth() + * + * Overview: This function is called by SetBWModeCallback8190Pci() only + * + * Input: PADAPTER Adapter + * WIRELESS_BANDWIDTH_E Bandwidth //20M or 40M + * + * Output: NONE + * + * Return: NONE + * + * Note: For RF type 0222D + *---------------------------------------------------------------------------*/ +void PHY_RF6052SetBandwidth(struct net_device* dev, HT_CHANNEL_WIDTH Bandwidth) //20M or 40M +{ + //u8 eRFPath; + //struct r8192_priv *priv = ieee80211_priv(dev); + + + //if (priv->card_8192 == NIC_8192SE) +#ifdef RTL8192SU //YJ,test,090113 + { + switch(Bandwidth) + { + case HT_CHANNEL_WIDTH_20: + //if (priv->card_8192_version >= VERSION_8192S_BCUT) + // rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x58); + + rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, BIT10|BIT11, 0x01); + break; + case HT_CHANNEL_WIDTH_20_40: + //if (priv->card_8192_version >= VERSION_8192S_BCUT) + // rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x18); + + rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, BIT10|BIT11, 0x00); + break; + default: + RT_TRACE(COMP_DBG, "PHY_SetRF6052Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth); + break; + } + } +// else +#else + { + for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++) + { + switch(Bandwidth) + { + case HT_CHANNEL_WIDTH_20: + //PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, (BIT10|BIT11), 0x01); + break; + case HT_CHANNEL_WIDTH_20_40: + //PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, (BIT10|BIT11), 0x00); + break; + default: + RT_TRACE(COMP_DBG, "PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth ); + break; + + } + } + } +#endif +} + + +/*----------------------------------------------------------------------------- + * Function: PHY_RF6052SetCckTxPower + * + * Overview: + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 11/05/2008 MHC Simulate 8192series.. + * + *---------------------------------------------------------------------------*/ +extern void PHY_RF6052SetCckTxPower(struct net_device* dev, u8 powerlevel) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + u32 TxAGC=0; + + if(priv->ieee80211->scanning == 1) + TxAGC = 0x3f; + else if(priv->bDynamicTxLowPower == true)//cosa 04282008 for cck long range + TxAGC = 0x22; + else + TxAGC = powerlevel; + + //cosa add for lenovo, to pass the safety spec, don't increase power index for different rates. + if(priv->bIgnoreDiffRateTxPowerOffset) + TxAGC = powerlevel; + + if(TxAGC > RF6052_MAX_TX_PWR) + TxAGC = RF6052_MAX_TX_PWR; + + //printk("CCK PWR= %x\n", TxAGC); + rtl8192_setBBreg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC); + +} /* PHY_RF6052SetCckTxPower */ + + + +/*----------------------------------------------------------------------------- + * Function: PHY_RF6052SetOFDMTxPower + * + * Overview: For legacy and HY OFDM, we must read EEPROM TX power index for + * different channel and read original value in TX power register area from + * 0xe00. We increase offset and original value to be correct tx pwr. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 11/05/2008 MHC Simulate 8192 series method. +* 01/06/2009 MHC 1. Prevent Path B tx power overflow or underflow dure to + * A/B pwr difference or legacy/HT pwr diff. + * 2. We concern with path B legacy/HT OFDM difference. + * 01/22/2009 MHC Support new EPRO format from SD3. + *---------------------------------------------------------------------------*/ + #if 1 +extern void PHY_RF6052SetOFDMTxPower(struct net_device* dev, u8 powerlevel) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + u32 writeVal, powerBase0, powerBase1; + u8 index = 0; + u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c}; + //u8 byte0, byte1, byte2, byte3; + u8 Channel = priv->ieee80211->current_network.channel; + u8 rfa_pwr[4]; + u8 rfa_lower_bound = 0, rfa_upper_bound = 0 /*, rfa_htpwr, rfa_legacypwr*/; + u8 i; + u8 rf_pwr_diff = 0; + u8 Legacy_pwrdiff=0, HT20_pwrdiff=0, BandEdge_Pwrdiff=0; + u8 ofdm_bandedge_chnl_low=0, ofdm_bandedge_chnl_high=0; + + + // We only care about the path A for legacy. + if (priv->EEPROMVersion != 2) + powerBase0 = powerlevel + (priv->LegacyHTTxPowerDiff & 0xf); + else if (priv->EEPROMVersion == 2) // Defined by SD1 Jong + { + // + // 2009/01/21 MH Support new EEPROM format from SD3 requirement + // + Legacy_pwrdiff = priv->TxPwrLegacyHtDiff[RF90_PATH_A][Channel-1]; + // For legacy OFDM, tx pwr always > HT OFDM pwr. We do not care Path B + // legacy OFDM pwr diff. NO BB register to notify HW. + powerBase0 = powerlevel + Legacy_pwrdiff; + //RTPRINT(FPHY, PHY_TXPWR, (" [LagacyToHT40 pwr diff = %d]\n", Legacy_pwrdiff)); + + // Band Edge scheme is enabled for FCC mode + if (priv->TxPwrbandEdgeFlag == 1/* && pHalData->ChannelPlan == 0*/) + { + ofdm_bandedge_chnl_low = 1; + ofdm_bandedge_chnl_high = 11; + #if 0//cosa, Todo: check ofdm 40MHz, when lower and duplicate, the bandedge chnl low=3, high=9 + if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) + { // Is it the same with the document? + if(pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) + else if(pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER; + else + pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + } + #endif + BandEdge_Pwrdiff = 0; + if (Channel <= ofdm_bandedge_chnl_low) + BandEdge_Pwrdiff = priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_A][0]; + else if (Channel >= ofdm_bandedge_chnl_high) + { + BandEdge_Pwrdiff = priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_A][1]; + } + powerBase0 -= BandEdge_Pwrdiff; + if (Channel <= ofdm_bandedge_chnl_low || Channel >= ofdm_bandedge_chnl_high) + { + //RTPRINT(FPHY, PHY_TXPWR, (" [OFDM band-edge channel = %d, pwr diff = %d]\n", + //Channel, BandEdge_Pwrdiff)); + } + } + //RTPRINT(FPHY, PHY_TXPWR, (" [OFDM power base index = 0x%x]\n", powerBase0)); + } + powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0; + + //MCS rates + if(priv->EEPROMVersion == 2) + { + //Cosa add for new EEPROM content. 02102009 + + //Check HT20 to HT40 diff + if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) + { + // HT 20<->40 pwr diff + HT20_pwrdiff = priv->TxPwrHt20Diff[RF90_PATH_A][Channel-1]; + + // Calculate Antenna pwr diff + if (HT20_pwrdiff < 8) // 0~+7 + powerlevel += HT20_pwrdiff; + else // index8-15=-8~-1 + powerlevel -= (16-HT20_pwrdiff); + + //RTPRINT(FPHY, PHY_TXPWR, (" [HT20 to HT40 pwrdiff = %d]\n", HT20_pwrdiff)); + //RTPRINT(FPHY, PHY_TXPWR, (" [MCS power base index = 0x%x]\n", powerlevel)); + } + + // Band Edge scheme is enabled for FCC mode + if (priv->TxPwrbandEdgeFlag == 1/* && pHalData->ChannelPlan == 0*/) + { + BandEdge_Pwrdiff = 0; + if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) + { + if (Channel <= 3) + BandEdge_Pwrdiff = priv->TxPwrbandEdgeHt40[RF90_PATH_A][0]; + else if (Channel >= 9) + BandEdge_Pwrdiff = priv->TxPwrbandEdgeHt40[RF90_PATH_A][1]; + if (Channel <= 3 || Channel >= 9) + { + //RTPRINT(FPHY, PHY_TXPWR, (" [HT40 band-edge channel = %d, pwr diff = %d]\n", + //Channel, BandEdge_Pwrdiff)); + } + } + else if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) + { + if (Channel <= 1) + BandEdge_Pwrdiff = priv->TxPwrbandEdgeHt20[RF90_PATH_A][0]; + else if (Channel >= 11) + BandEdge_Pwrdiff = priv->TxPwrbandEdgeHt20[RF90_PATH_A][1]; + if (Channel <= 1 || Channel >= 11) + { + //RTPRINT(FPHY, PHY_TXPWR, (" [HT20 band-edge channel = %d, pwr diff = %d]\n", + //Channel, BandEdge_Pwrdiff)); + } + } + powerlevel -= BandEdge_Pwrdiff; + //RTPRINT(FPHY, PHY_TXPWR, (" [MCS power base index = 0x%x]\n", powerlevel)); + } + } + powerBase1 = powerlevel; + powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1; + + //RTPRINT(FPHY, PHY_TXPWR, (" [Legacy/HT power index= %x/%x]\n", powerBase0, powerBase1)); + + for(index=0; index<6; index++) + { + // + // Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate + // + //cosa add for lenovo, to pass the safety spec, don't increase power index for different rates. + if(priv->bIgnoreDiffRateTxPowerOffset) + writeVal = ((index<2)?powerBase0:powerBase1); + else + writeVal = priv->MCSTxPowerLevelOriginalOffset[index] + ((index<2)?powerBase0:powerBase1); + + //RTPRINT(FPHY, PHY_TXPWR, ("Reg 0x%x, Original=%x writeVal=%x\n", + //RegOffset[index], priv->MCSTxPowerLevelOriginalOffset[index], writeVal)); + + // + // If path A and Path B coexist, we must limit Path A tx power. + // Protect Path B pwr over or under flow. We need to calculate upper and + // lower bound of path A tx power. + // + if (priv->rf_type == RF_2T2R) + { + #if 0//cosa, we have only one AntennaTxPwDiff + // HT OFDM + if (index > 1) + { + rf_pwr_diff = pHalData->AntennaTxPwDiff[0]; + } + // Legacy OFDM + else + { + rf_pwr_diff = pHalData->AntTxPwDiffLegacy[0]; + } + #endif + rf_pwr_diff = priv->AntennaTxPwDiff[0]; + //RTPRINT(FPHY, PHY_TXPWR, ("2T2R RF-B to RF-A PWR DIFF=%d\n", rf_pwr_diff)); + + if (rf_pwr_diff >= 8) // Diff=-8~-1 + { // Prevent underflow!! + rfa_lower_bound = 0x10-rf_pwr_diff; + //RTPRINT(FPHY, PHY_TXPWR, ("rfa_lower_bound= %d\n", rfa_lower_bound)); + } + else if (rf_pwr_diff >= 0) // Diff = 0-7 + { + rfa_upper_bound = RF6052_MAX_TX_PWR-rf_pwr_diff; + //RTPRINT(FPHY, PHY_TXPWR, ("rfa_upper_bound= %d\n", rfa_upper_bound)); + } + } + + for (i= 0; i <4; i++) + { + rfa_pwr[i] = (u8)((writeVal & (0x7f<<(i*8)))>>(i*8)); + if (rfa_pwr[i] > RF6052_MAX_TX_PWR) + rfa_pwr[i] = RF6052_MAX_TX_PWR; + + // + // If path A and Path B coexist, we must limit Path A tx power. + // Protect Path B pwr over or under flow. We need to calculate upper and + // lower bound of path A tx power. + // + if (priv->rf_type == RF_2T2R) + { + if (rf_pwr_diff >= 8) // Diff=-8~-1 + { // Prevent underflow!! + if (rfa_pwr[i] <rfa_lower_bound) + { + //RTPRINT(FPHY, PHY_TXPWR, ("Underflow")); + rfa_pwr[i] = rfa_lower_bound; + } + } + else if (rf_pwr_diff >= 1) // Diff = 0-7 + { // Prevent overflow + if (rfa_pwr[i] > rfa_upper_bound) + { + //RTPRINT(FPHY, PHY_TXPWR, ("Overflow")); + rfa_pwr[i] = rfa_upper_bound; + } + } + //RTPRINT(FPHY, PHY_TXPWR, ("rfa_pwr[%d]=%x\n", i, rfa_pwr[i])); + } + + } + + // + // Add description: PWDB > threshold!!!High power issue!! + // We must decrease tx power !! Why is the value ??? + // + if(priv->bDynamicTxHighPower == TRUE) + { + // For MCS rate + if(index > 1) + { + writeVal = 0x03030303; + } + // For Legacy rate + else + { + writeVal = (rfa_pwr[3]<<24) | (rfa_pwr[2]<<16) |(rfa_pwr[1]<<8) |rfa_pwr[0]; + } + //RTPRINT(FPHY, PHY_TXPWR, ("HighPower=%08x\n", writeVal)); + } + else + { + writeVal = (rfa_pwr[3]<<24) | (rfa_pwr[2]<<16) |(rfa_pwr[1]<<8) |rfa_pwr[0]; + //RTPRINT(FPHY, PHY_TXPWR, ("NormalPower=%08x\n", writeVal)); + } + + // + // Write different rate set tx power index. + // + //if (DCMD_Test_Flag == 0) + rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal); + } + +} /* PHY_RF6052SetOFDMTxPower */ +#else +extern void PHY_RF6052SetOFDMTxPower(struct net_device* dev, u8 powerlevel) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + u32 writeVal, powerBase0, powerBase1; + u8 index = 0; + u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c}; + u8 byte0, byte1, byte2, byte3; + u8 channel = priv->ieee80211->current_network.channel; + + //Legacy OFDM rates + powerBase0 = powerlevel + (priv->LegacyHTTxPowerDiff & 0xf); + powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0; + + //MCS rates HT OFDM + powerBase1 = powerlevel; + powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1; + + //printk("Legacy/HT PWR= %x/%x\n", powerBase0, powerBase1); + + for(index=0; index<6; index++) + { + // + // Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate + // + writeVal = priv->MCSTxPowerLevelOriginalOffset[index] + ((index<2)?powerBase0:powerBase1); + + //printk("Index = %d Original=%x writeVal=%x\n", index, priv->MCSTxPowerLevelOriginalOffset[index], writeVal); + + byte0 = (u8)(writeVal & 0x7f); + byte1 = (u8)((writeVal & 0x7f00)>>8); + byte2 = (u8)((writeVal & 0x7f0000)>>16); + byte3 = (u8)((writeVal & 0x7f000000)>>24); + + // Max power index = 0x3F Range = 0-0x3F + if(byte0 > RF6052_MAX_TX_PWR) + byte0 = RF6052_MAX_TX_PWR; + if(byte1 > RF6052_MAX_TX_PWR) + byte1 = RF6052_MAX_TX_PWR; + if(byte2 > RF6052_MAX_TX_PWR) + byte2 = RF6052_MAX_TX_PWR; + if(byte3 > RF6052_MAX_TX_PWR) + byte3 = RF6052_MAX_TX_PWR; + + // + // Add description: PWDB > threshold!!!High power issue!! + // We must decrease tx power !! Why is the value ??? + // + if(priv->bDynamicTxHighPower == true) + { + // For MCS rate + if(index > 1) + { + writeVal = 0x03030303; + } + // For Legacy rate + else + { + writeVal = (byte3<<24) | (byte2<<16) |(byte1<<8) |byte0; + } + } + else + { + writeVal = (byte3<<24) | (byte2<<16) |(byte1<<8) |byte0; + } + + // + // Write different rate set tx power index. + // + rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal); + } + +} /* PHY_RF6052SetOFDMTxPower */ +#endif + +RT_STATUS PHY_RF6052_Config(struct net_device* dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + RT_STATUS rtStatus = RT_STATUS_SUCCESS; + //RF90_RADIO_PATH_E eRFPath; + //BB_REGISTER_DEFINITION_T *pPhyReg; + //u32 OrgStoreRFIntSW[RF90_PATH_D+1]; + + // + // Initialize general global value + // + // TODO: Extend RF_PATH_C and RF_PATH_D in the future + if(priv->rf_type == RF_1T1R) + priv->NumTotalRFPath = 1; + else + priv->NumTotalRFPath = 2; + + // + // Config BB and RF + // +// switch( priv->bRegHwParaFile ) +// { +// case 0: +// phy_RF6052_Config_HardCode(dev); +// break; + +// case 1: + rtStatus = phy_RF6052_Config_ParaFile(dev); +// break; + +// case 2: + // Partial Modify. +// phy_RF6052_Config_HardCode(dev); +// phy_RF6052_Config_ParaFile(dev); +// break; + +// default: +// phy_RF6052_Config_HardCode(dev); +// break; +// } + return rtStatus; + +} + +void phy_RF6052_Config_HardCode(struct net_device* dev) +{ + + // Set Default Bandwidth to 20M + //Adapter->HalFunc .SetBWModeHandler(Adapter, HT_CHANNEL_WIDTH_20); + + // TODO: Set Default Channel to channel one for RTL8225 + +} + +RT_STATUS phy_RF6052_Config_ParaFile(struct net_device* dev) +{ + u32 u4RegValue = 0; + //static s1Byte szRadioAFile[] = RTL819X_PHY_RADIO_A; + //static s1Byte szRadioBFile[] = RTL819X_PHY_RADIO_B; + //static s1Byte szRadioBGMFile[] = RTL819X_PHY_RADIO_B_GM; + u8 eRFPath; + RT_STATUS rtStatus = RT_STATUS_SUCCESS; + struct r8192_priv *priv = ieee80211_priv(dev); + BB_REGISTER_DEFINITION_T *pPhyReg; + //u8 eCheckItem; + + + //3//----------------------------------------------------------------- + //3// <2> Initialize RF + //3//----------------------------------------------------------------- + //for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++) + for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++) + { + + pPhyReg = &priv->PHYRegDef[eRFPath]; + + /*----Store original RFENV control type----*/ + switch(eRFPath) + { + case RF90_PATH_A: + case RF90_PATH_C: + u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV); + break; + case RF90_PATH_B : + case RF90_PATH_D: + u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16); + break; + } + + /*----Set RF_ENV enable----*/ + rtl8192_setBBreg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1); + + /*----Set RF_ENV output high----*/ + rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1); + + /* Set bit number of Address and Data for RF register */ + rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); // Set 1 to 4 bits for 8255 + rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); // Set 0 to 12 bits for 8255 + + + /*----Initialize RF fom connfiguration file----*/ + switch(eRFPath) + { + case RF90_PATH_A: +#if RTL8190_Download_Firmware_From_Header + rtStatus= rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath); +#else + rtStatus = PHY_ConfigRFWithParaFile(Adapter, (char* )&szRadioAFile, (RF90_RADIO_PATH_E)eRFPath); +#endif + break; + case RF90_PATH_B: +#if RTL8190_Download_Firmware_From_Header + rtStatus= rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath); +#else + if(priv->rf_type == RF_2T2R_GREEN) + rtStatus = PHY_ConfigRFWithParaFile(Adapter, (ps1Byte)&szRadioBGMFile, (RF90_RADIO_PATH_E)eRFPath); + else + rtStatus = PHY_ConfigRFWithParaFile(Adapter, (char* )&szRadioBFile, (RF90_RADIO_PATH_E)eRFPath); +#endif + break; + case RF90_PATH_C: + break; + case RF90_PATH_D: + break; + } + + /*----Restore RFENV control type----*/; + switch(eRFPath) + { + case RF90_PATH_A: + case RF90_PATH_C: + rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue); + break; + case RF90_PATH_B : + case RF90_PATH_D: + rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue); + break; + } + + if(rtStatus != RT_STATUS_SUCCESS){ + printk("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath); + goto phy_RF6052_Config_ParaFile_Fail; + } + + } + + RT_TRACE(COMP_INIT, "<---phy_RF6052_Config_ParaFile()\n"); + return rtStatus; + +phy_RF6052_Config_ParaFile_Fail: + return rtStatus; +} + + +// +// ==> RF shadow Operation API Code Section!!! +// +/*----------------------------------------------------------------------------- + * Function: PHY_RFShadowRead + * PHY_RFShadowWrite + * PHY_RFShadowCompare + * PHY_RFShadowRecorver + * PHY_RFShadowCompareAll + * PHY_RFShadowRecorverAll + * PHY_RFShadowCompareFlagSet + * PHY_RFShadowRecorverFlagSet + * + * Overview: When we set RF register, we must write shadow at first. + * When we are running, we must compare shadow abd locate error addr. + * Decide to recorver or not. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 11/20/2008 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +extern u32 PHY_RFShadowRead( + struct net_device * dev, + RF90_RADIO_PATH_E eRFPath, + u32 Offset) +{ + return RF_Shadow[eRFPath][Offset].Value; + +} /* PHY_RFShadowRead */ + + +extern void PHY_RFShadowWrite( + struct net_device * dev, + u32 eRFPath, + u32 Offset, + u32 Data) +{ + //RF_Shadow[eRFPath][Offset].Value = (Data & bMask20Bits); + RF_Shadow[eRFPath][Offset].Value = (Data & bRFRegOffsetMask); + RF_Shadow[eRFPath][Offset].Driver_Write = true; + +} /* PHY_RFShadowWrite */ + + +extern void PHY_RFShadowCompare( + struct net_device * dev, + RF90_RADIO_PATH_E eRFPath, + u32 Offset) +{ + u32 reg; + + // Check if we need to check the register + if (RF_Shadow[eRFPath][Offset].Compare == true) + { + reg = rtl8192_phy_QueryRFReg(dev, eRFPath, Offset, bRFRegOffsetMask); + // Compare shadow and real rf register for 20bits!! + if (RF_Shadow[eRFPath][Offset].Value != reg) + { + // Locate error position. + RF_Shadow[eRFPath][Offset].ErrorOrNot = true; + RT_TRACE(COMP_INIT, "PHY_RFShadowCompare RF-%d Addr%02xErr = %05x", eRFPath, Offset, reg); + } + } + +} /* PHY_RFShadowCompare */ + +extern void PHY_RFShadowRecorver( + struct net_device * dev, + RF90_RADIO_PATH_E eRFPath, + u32 Offset) +{ + // Check if the address is error + if (RF_Shadow[eRFPath][Offset].ErrorOrNot == true) + { + // Check if we need to recorver the register. + if (RF_Shadow[eRFPath][Offset].Recorver == true) + { + rtl8192_phy_SetRFReg(dev, eRFPath, Offset, bRFRegOffsetMask, RF_Shadow[eRFPath][Offset].Value); + RT_TRACE(COMP_INIT, "PHY_RFShadowRecorver RF-%d Addr%02x=%05x", + eRFPath, Offset, RF_Shadow[eRFPath][Offset].Value); + } + } + +} /* PHY_RFShadowRecorver */ + + +extern void PHY_RFShadowCompareAll(struct net_device * dev) +{ + u32 eRFPath; + u32 Offset; + + for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) + { + for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++) + { + PHY_RFShadowCompare(dev, (RF90_RADIO_PATH_E)eRFPath, Offset); + } + } + +} /* PHY_RFShadowCompareAll */ + + +extern void PHY_RFShadowRecorverAll(struct net_device * dev) +{ + u32 eRFPath; + u32 Offset; + + for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) + { + for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++) + { + PHY_RFShadowRecorver(dev, (RF90_RADIO_PATH_E)eRFPath, Offset); + } + } + +} /* PHY_RFShadowRecorverAll */ + + +extern void PHY_RFShadowCompareFlagSet( + struct net_device * dev, + RF90_RADIO_PATH_E eRFPath, + u32 Offset, + u8 Type) +{ + // Set True or False!!! + RF_Shadow[eRFPath][Offset].Compare = Type; + +} /* PHY_RFShadowCompareFlagSet */ + + +extern void PHY_RFShadowRecorverFlagSet( + struct net_device * dev, + RF90_RADIO_PATH_E eRFPath, + u32 Offset, + u8 Type) +{ + // Set True or False!!! + RF_Shadow[eRFPath][Offset].Recorver= Type; + +} /* PHY_RFShadowRecorverFlagSet */ + + +extern void PHY_RFShadowCompareFlagSetAll(struct net_device * dev) +{ + u32 eRFPath; + u32 Offset; + + for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) + { + for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++) + { + // 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!! + if (Offset != 0x26 && Offset != 0x27) + PHY_RFShadowCompareFlagSet(dev, (RF90_RADIO_PATH_E)eRFPath, Offset, FALSE); + else + PHY_RFShadowCompareFlagSet(dev, (RF90_RADIO_PATH_E)eRFPath, Offset, TRUE); + } + } + +} /* PHY_RFShadowCompareFlagSetAll */ + + +extern void PHY_RFShadowRecorverFlagSetAll(struct net_device * dev) +{ + u32 eRFPath; + u32 Offset; + + for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) + { + for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++) + { + // 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!! + if (Offset != 0x26 && Offset != 0x27) + PHY_RFShadowRecorverFlagSet(dev, (RF90_RADIO_PATH_E)eRFPath, Offset, FALSE); + else + PHY_RFShadowRecorverFlagSet(dev, (RF90_RADIO_PATH_E)eRFPath, Offset, TRUE); + } + } + +} /* PHY_RFShadowCompareFlagSetAll */ + + + +extern void PHY_RFShadowRefresh(struct net_device * dev) +{ + u32 eRFPath; + u32 Offset; + + for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) + { + for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++) + { + RF_Shadow[eRFPath][Offset].Value = 0; + RF_Shadow[eRFPath][Offset].Compare = false; + RF_Shadow[eRFPath][Offset].Recorver = false; + RF_Shadow[eRFPath][Offset].ErrorOrNot = false; + RF_Shadow[eRFPath][Offset].Driver_Write = false; + } + } + +} /* PHY_RFShadowRead */ + +/* End of HalRf6052.c */ diff --git a/drivers/staging/rtl8192su/r8192S_rtl6052.h b/drivers/staging/rtl8192su/r8192S_rtl6052.h new file mode 100644 index 000000000000..916603ceaae0 --- /dev/null +++ b/drivers/staging/rtl8192su/r8192S_rtl6052.h @@ -0,0 +1,134 @@ +/****************************************************************************** + * + * (c) Copyright 2008, RealTEK Technologies Inc. All Rights Reserved. + * + * Module: HalRf.h ( Header File) + * + * Note: Collect every HAL RF type exter API or constant. + * + * Function: + * + * Export: + * + * Abbrev: + * + * History: + * Data Who Remark + * + * 09/25/2008 MHC Create initial version. + * + * +******************************************************************************/ +/* Check to see if the file has been included already. */ + + +/*--------------------------Define Parameters-------------------------------*/ + +// +// For RF 6052 Series +// +#define RF6052_MAX_TX_PWR 0x3F +#define RF6052_MAX_REG 0x3F +#define RF6052_MAX_PATH 4 +/*--------------------------Define Parameters-------------------------------*/ + + +/*------------------------------Define structure----------------------------*/ + +/*------------------------------Define structure----------------------------*/ + + +/*------------------------Export global variable----------------------------*/ +/*------------------------Export global variable----------------------------*/ + +/*------------------------Export Marco Definition---------------------------*/ + +/*------------------------Export Marco Definition---------------------------*/ + + +/*--------------------------Exported Function prototype---------------------*/ +//====================================================== +#if 1 +// Function prototypes for HalPhy8225.c +//1====================================================== +extern void PHY_SetRF0222DBandwidth(struct net_device* dev , HT_CHANNEL_WIDTH Bandwidth); //20M or 40M; +extern void PHY_SetRF8225Bandwidth( struct net_device* dev , HT_CHANNEL_WIDTH Bandwidth); +extern bool PHY_RF8225_Config(struct net_device* dev ); +extern void phy_RF8225_Config_HardCode(struct net_device* dev); +extern bool phy_RF8225_Config_ParaFile(struct net_device* dev); +extern void PHY_SetRF8225CckTxPower(struct net_device* dev ,u8 powerlevel); +extern void PHY_SetRF8225OfdmTxPower(struct net_device* dev ,u8 powerlevel); +extern void PHY_SetRF0222DOfdmTxPower(struct net_device* dev ,u8 powerlevel); +extern void PHY_SetRF0222DCckTxPower(struct net_device* dev ,u8 powerlevel); + +//1====================================================== +// Function prototypes for HalPhy8256.c +//1====================================================== +extern void PHY_SetRF8256Bandwidth(struct net_device* dev , HT_CHANNEL_WIDTH Bandwidth); +extern void PHY_RF8256_Config(struct net_device* dev); +extern void phy_RF8256_Config_ParaFile(struct net_device* dev); +extern void PHY_SetRF8256CCKTxPower(struct net_device* dev, u8 powerlevel); +extern void PHY_SetRF8256OFDMTxPower(struct net_device* dev, u8 powerlevel); +#endif + +// +// RF RL6052 Series API +// +extern void RF_ChangeTxPath(struct net_device * dev, u16 DataRate); +extern void PHY_RF6052SetBandwidth(struct net_device * dev,HT_CHANNEL_WIDTH Bandwidth); +extern void PHY_RF6052SetCckTxPower(struct net_device * dev, u8 powerlevel); +extern void PHY_RF6052SetOFDMTxPower(struct net_device * dev, u8 powerlevel); +extern RT_STATUS PHY_RF6052_Config(struct net_device * dev); +extern void PHY_RFShadowRefresh( struct net_device * dev); +extern void PHY_RFShadowWrite( struct net_device* dev, u32 eRFPath, u32 Offset, u32 Data); +#if 0 +// +// RF Shadow operation relative API +// +extern u32 +PHY_RFShadowRead( + struct net_device * dev, + RF90_RADIO_PATH_E eRFPath, + u32 Offset); +extern void +PHY_RFShadowCompare( + struct net_device * dev, + RF90_RADIO_PATH_E eRFPath, + u32 Offset); +extern void +PHY_RFShadowRecorver( + struct net_device * dev, + RF90_RADIO_PATH_E eRFPath, + u32 Offset); +extern void +PHY_RFShadowCompareAll( + struct net_device * dev); +extern void +PHY_RFShadowRecorverAll( + struct net_device * dev); +extern void +PHY_RFShadowCompareFlagSet( + struct net_device * dev, + RF90_RADIO_PATH_E eRFPath, + u32 Offset, + u8 Type); +extern void +PHY_RFShadowRecorverFlagSet( + struct net_device * dev, + RF90_RADIO_PATH_E eRFPath, + u32 Offset, + u8 Type); +extern void +PHY_RFShadowCompareFlagSetAll( + struct net_device * dev); +extern void +PHY_RFShadowRecorverFlagSetAll( + struct net_device * dev); +extern void +PHY_RFShadowRefresh( + struct net_device * dev); +#endif +/*--------------------------Exported Function prototype---------------------*/ + + +/* End of HalRf.h */ diff --git a/drivers/staging/rtl8192su/r8192S_rtl8225.c b/drivers/staging/rtl8192su/r8192S_rtl8225.c new file mode 100644 index 000000000000..09465df2def6 --- /dev/null +++ b/drivers/staging/rtl8192su/r8192S_rtl8225.c @@ -0,0 +1,292 @@ + +#include "r8192U.h" +#include "r8192S_hw.h" +#include "r8192S_phyreg.h" +#include "r8192S_phy.h" +#include "r8192S_rtl8225.h" + +/*---------------------Define local function prototype-----------------------*/ +void phy_RF8225_Config_HardCode(struct net_device* dev ); +bool phy_RF8225_Config_ParaFile(struct net_device* dev ); +/*---------------------Define local function prototype-----------------------*/ +void PHY_SetRF8225OfdmTxPower(struct net_device* dev ,u8 powerlevel) +{ + +} + + + +void PHY_SetRF8225CckTxPower( struct net_device* dev , u8 powerlevel) +{ + +} + + +// TODO: The following RF 022D related function should be removed to HalPhy0222D.c. +void PHY_SetRF0222DOfdmTxPower(struct net_device* dev ,u8 powerlevel) +{ + //TODO: We should set RF TxPower for RF 0222D here!! +} + + + +void PHY_SetRF0222DCckTxPower(struct net_device* dev ,u8 powerlevel) +{ + //TODO: We should set RF TxPower for RF 0222D here!! +} + + +/*----------------------------------------------------------------------------- + * Function: PHY_SetRF0222DBandwidth() + * + * Overview: This function is called by SetBWModeCallback8190Pci() only + * + * Input: PADAPTER Adapter + * WIRELESS_BANDWIDTH_E Bandwidth //20M or 40M + * + * Output: NONE + * + * Return: NONE + * + * Note: For RF type 0222D + *---------------------------------------------------------------------------*/ + //just in phy +void PHY_SetRF0222DBandwidth(struct net_device* dev , HT_CHANNEL_WIDTH Bandwidth) //20M or 40M +{ + u8 eRFPath; + struct r8192_priv *priv = ieee80211_priv(dev); + + + //if (IS_HARDWARE_TYPE_8192S(dev)) + if (1) + { +#ifndef RTL92SE_FPGA_VERIFY + switch(Bandwidth) + { + case HT_CHANNEL_WIDTH_20: +#ifdef FIB_MODIFICATION + write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x58); +#endif + rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, BIT10|BIT11, 0x01); + break; + case HT_CHANNEL_WIDTH_20_40: +#ifdef FIB_MODIFICATION + write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x18); +#endif + rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, BIT10|BIT11, 0x00); + break; + default: + ;//RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth )); + break; + } +#endif + } + else + { + for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++) + { + switch(Bandwidth) + { + case HT_CHANNEL_WIDTH_20: + //rtl8192_phy_SetRFReg(Adapter, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, (BIT10|BIT11), 0x01); + break; + case HT_CHANNEL_WIDTH_20_40: + //rtl8192_phy_SetRFReg(Adapter, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, (BIT10|BIT11), 0x00); + break; + default: + ;//RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth )); + break; + + } + } + } + +} + +// TODO: Aabove RF 022D related function should be removed to HalPhy0222D.c. + +/*----------------------------------------------------------------------------- + * Function: PHY_SetRF8225Bandwidth() + * + * Overview: This function is called by SetBWModeCallback8190Pci() only + * + * Input: PADAPTER Adapter + * WIRELESS_BANDWIDTH_E Bandwidth //20M or 40M + * + * Output: NONE + * + * Return: NONE + * + * Note: 8225(zebra1) support 20M only + *---------------------------------------------------------------------------*/ + //just in phy +void PHY_SetRF8225Bandwidth(struct net_device* dev ,HT_CHANNEL_WIDTH Bandwidth) //20M or 40M +{ + u8 eRFPath; + struct r8192_priv *priv = ieee80211_priv(dev); + + //for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++) + for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++) + { + switch(Bandwidth) + { + case HT_CHANNEL_WIDTH_20: + // TODO: Update the parameters here + break; + case HT_CHANNEL_WIDTH_20_40: + RT_TRACE(COMP_DBG, "SetChannelBandwidth8190Pci():8225 does not support 40M mode\n"); + break; + default: + RT_TRACE(COMP_DBG, "PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth ); + break; + + } + } + +} + +//just in phy +bool PHY_RF8225_Config(struct net_device* dev ) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + bool rtStatus = true; + //RF90_RADIO_PATH_E eRFPath; + //BB_REGISTER_DEFINITION_T *pPhyReg; + //u32 OrgStoreRFIntSW[RF90_PATH_D+1]; + + // + // Initialize general global value + // + // TODO: Extend RF_PATH_C and RF_PATH_D in the future + priv->NumTotalRFPath = 2; + + // + // Config BB and RF + // + //switch( Adapter->MgntInfo.bRegHwParaFile ) + //{ + // case 0: + // phy_RF8225_Config_HardCode(dev); + // break; + + // case 1: + // rtStatus = phy_RF8225_Config_ParaFile(dev); + // break; + + // case 2: + // Partial Modify. + phy_RF8225_Config_HardCode(dev); + phy_RF8225_Config_ParaFile(dev); + // break; + + // default: + // phy_RF8225_Config_HardCode(dev); + // break; + //} + return rtStatus; + +} + +//just in 8225 +void phy_RF8225_Config_HardCode(struct net_device* dev) +{ + + // Set Default Bandwidth to 20M + //Adapter->HalFunc .SetBWModeHandler(Adapter, HT_CHANNEL_WIDTH_20); + + // TODO: Set Default Channel to channel one for RTL8225 + +} + +//just in 8225 +bool phy_RF8225_Config_ParaFile(struct net_device* dev) +{ + u32 u4RegValue = 0; + //static char szRadioAFile[] = RTL819X_PHY_RADIO_A; + //static char szRadioBFile[] = RTL819X_PHY_RADIO_B; + u8 eRFPath; + bool rtStatus = true; + struct r8192_priv *priv = ieee80211_priv(dev); + BB_REGISTER_DEFINITION_T *pPhyReg; + //u8 eCheckItem; + +#if 1 + //3//----------------------------------------------------------------- + //3// <2> Initialize RF + //3//----------------------------------------------------------------- + //for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++) + for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++) + { + + pPhyReg = &priv->PHYRegDef[eRFPath]; + + /*----Store original RFENV control type----*/ + switch(eRFPath) + { + case RF90_PATH_A: + case RF90_PATH_C: + u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV); + break; + case RF90_PATH_B : + case RF90_PATH_D: + u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16); + break; + } + + /*----Set RF_ENV enable----*/ + rtl8192_setBBreg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1); + + /*----Set RF_ENV output high----*/ + rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1); + + /* Set bit number of Address and Data for RF register */ + rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); // Set 1 to 4 bits for 8255 + rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); // Set 0 to 12 bits for 8255 + + + /*----Initialize RF fom connfiguration file----*/ + switch(eRFPath) + { + case RF90_PATH_A: + //rtStatus = PHY_ConfigRFWithParaFile(dev, (char* )&szRadioAFile, (RF90_RADIO_PATH_E)eRFPath); + rtStatus = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath); + break; + case RF90_PATH_B: + //rtStatus = PHY_ConfigRFWithParaFile(dev, (char* )&szRadioBFile, (RF90_RADIO_PATH_E)eRFPath); + rtStatus = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath); + break; + case RF90_PATH_C: + break; + case RF90_PATH_D: + break; + } + + /*----Restore RFENV control type----*/; + switch(eRFPath) + { + case RF90_PATH_A: + case RF90_PATH_C: + rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue); + break; + case RF90_PATH_B : + case RF90_PATH_D: + rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue); + break; + } + + if(rtStatus == false){ + //RT_TRACE(COMP_FPGA, DBG_LOUD, ("phy_RF8225_Config_ParaFile():Radio[%d] Fail!!", eRFPath)); + goto phy_RF8225_Config_ParaFile_Fail; + } + + } + + //RT_TRACE(COMP_INIT, DBG_LOUD, ("<---phy_RF8225_Config_ParaFile()\n")); + return rtStatus; + +phy_RF8225_Config_ParaFile_Fail: +#endif + return rtStatus; +} + + diff --git a/drivers/staging/rtl8192su/r8192S_rtl8225.h b/drivers/staging/rtl8192su/r8192S_rtl8225.h new file mode 100644 index 000000000000..8a647284af35 --- /dev/null +++ b/drivers/staging/rtl8192su/r8192S_rtl8225.h @@ -0,0 +1,30 @@ +/* + This is part of the rtl8180-sa2400 driver + released under the GPL (See file COPYING for details). + Copyright (c) 2005 Andrea Merello <andreamrl@tiscali.it> + + This files contains programming code for the rtl8256 + radio frontend. + + *Many* thanks to Realtek Corp. for their great support! + +*/ + +#ifndef RTL8225H +#define RTL8225H + +#ifdef RTL8190P +#define RTL819X_TOTAL_RF_PATH 4 //for 90P +#else +#define RTL819X_TOTAL_RF_PATH 2 //for 8192U +#endif +extern void PHY_SetRF0222DBandwidth(struct net_device* dev , HT_CHANNEL_WIDTH Bandwidth); //20M or 40M; +extern void PHY_SetRF8225Bandwidth( struct net_device* dev , HT_CHANNEL_WIDTH Bandwidth); +extern bool PHY_RF8225_Config(struct net_device* dev ); +extern void phy_RF8225_Config_HardCode(struct net_device* dev); +extern bool phy_RF8225_Config_ParaFile(struct net_device* dev); +extern void PHY_SetRF8225CckTxPower(struct net_device* dev ,u8 powerlevel); +extern void PHY_SetRF8225OfdmTxPower(struct net_device* dev ,u8 powerlevel); +extern void PHY_SetRF0222DOfdmTxPower(struct net_device* dev ,u8 powerlevel); +extern void PHY_SetRF0222DCckTxPower(struct net_device* dev ,u8 powerlevel); +#endif diff --git a/drivers/staging/rtl8192su/r8192U.h b/drivers/staging/rtl8192su/r8192U.h new file mode 100644 index 000000000000..a2365587b1c7 --- /dev/null +++ b/drivers/staging/rtl8192su/r8192U.h @@ -0,0 +1,2112 @@ +/* + This is part of rtl8187 OpenSource driver. + Copyright (C) Andrea Merello 2004-2005 <andreamrl@tiscali.it> + Released under the terms of GPL (General Public Licence) + + Parts of this driver are based on the GPL part of the + official realtek driver + + Parts of this driver are based on the rtl8192 driver skeleton + from Patric Schenke & Andres Salomon + + Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver + + We want to tanks the Authors of those projects and the Ndiswrapper + project Authors. +*/ + +#ifndef R819xU_H +#define R819xU_H + +#include <linux/module.h> +#include <linux/kernel.h> +//#include <linux/config.h> +#include <linux/init.h> +#include <linux/ioport.h> +#include <linux/sched.h> +#include <linux/types.h> +#include <linux/slab.h> +#include <linux/netdevice.h> +//#include <linux/pci.h> +#include <linux/usb.h> +#include <linux/etherdevice.h> +#include <linux/delay.h> +#include <linux/rtnetlink.h> //for rtnl_lock() +#include <linux/wireless.h> +#include <linux/timer.h> +#include <linux/proc_fs.h> // Necessary because we use the proc fs +#include <linux/if_arp.h> +#include <linux/random.h> +#include <linux/version.h> +#include <asm/io.h> +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27)) +#include <asm/semaphore.h> +#endif +#include "ieee80211.h" + +#ifdef RTL8192SU +#include "r8192S_firmware.h" +#else +#include "r819xU_firmware.h" +#endif + +//#define RTL8192U +#define RTL819xU_MODULE_NAME "rtl819xU" +//added for HW security, john.0629 +#define FALSE 0 +#define TRUE 1 +#define MAX_KEY_LEN 61 +#define KEY_BUF_SIZE 5 + +#define BIT0 0x00000001 +#define BIT1 0x00000002 +#define BIT2 0x00000004 +#define BIT3 0x00000008 +#define BIT4 0x00000010 +#define BIT5 0x00000020 +#define BIT6 0x00000040 +#define BIT7 0x00000080 +#define BIT8 0x00000100 +#define BIT9 0x00000200 +#define BIT10 0x00000400 +#define BIT11 0x00000800 +#define BIT12 0x00001000 +#define BIT13 0x00002000 +#define BIT14 0x00004000 +#define BIT15 0x00008000 +#define BIT16 0x00010000 +#define BIT17 0x00020000 +#define BIT18 0x00040000 +#define BIT19 0x00080000 +#define BIT20 0x00100000 +#define BIT21 0x00200000 +#define BIT22 0x00400000 +#define BIT23 0x00800000 +#define BIT24 0x01000000 +#define BIT25 0x02000000 +#define BIT26 0x04000000 +#define BIT27 0x08000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 + +// Rx smooth factor +#define Rx_Smooth_Factor 20 +#if 0 //we need to use RT_TRACE instead DMESG as RT_TRACE will clearly show debug level wb. +#define DMESG(x,a...) printk(KERN_INFO RTL819xU_MODULE_NAME ": " x "\n", ## a) +#define DMESGW(x,a...) printk(KERN_WARNING RTL819xU_MODULE_NAME ": WW:" x "\n", ## a) +#define DMESGE(x,a...) printk(KERN_WARNING RTL819xU_MODULE_NAME ": EE:" x "\n", ## a) +#else +#define DMESG(x,a...) +#define DMESGW(x,a...) +#define DMESGE(x,a...) +extern u32 rt_global_debug_component; +#define RT_TRACE(component, x, args...) \ +do { if(rt_global_debug_component & component) \ + printk(KERN_DEBUG RTL819xU_MODULE_NAME ":" x "\n" , \ + ##args);\ +}while(0); +//---------------------------------------------------------------------- +//// Get 8192SU Rx descriptor. Added by Roger, 2008.04.15. +////---------------------------------------------------------------------- +#define RX_DESC_SIZE 24 +#define RX_DRV_INFO_SIZE_UNIT 8 + +#define IS_UNDER_11N_AES_MODE(_ieee) ((_ieee->pHTInfo->bCurrentHTSupport==TRUE) &&\ + (_ieee->pairwise_key_type==KEY_TYPE_CCMP)) + +#define COMP_TRACE BIT0 // For function call tracing. +#define COMP_DBG BIT1 // Only for temporary debug message. +#define COMP_INIT BIT2 // during driver initialization / halt / reset. + + +#define COMP_RECV BIT3 // Reveive part data path. +#define COMP_SEND BIT4 // Send part path. +#define COMP_IO BIT5 // I/O Related. Added by Annie, 2006-03-02. +#define COMP_POWER BIT6 // 802.11 Power Save mode or System/Device Power state related. +#define COMP_EPROM BIT7 // 802.11 link related: join/start BSS, leave BSS. +#define COMP_SWBW BIT8 // For bandwidth switch. +#define COMP_POWER_TRACKING BIT9 //FOR 8190 TX POWER TRACKING +#define COMP_TURBO BIT10 // For Turbo Mode related. By Annie, 2005-10-21. +#define COMP_QOS BIT11 // For QoS. +#define COMP_RATE BIT12 // For Rate Adaptive mechanism, 2006.07.02, by rcnjko. +#define COMP_LPS BIT13 // For Radio Measurement. +#define COMP_DIG BIT14 // For DIG, 2006.09.25, by rcnjko. +#define COMP_PHY BIT15 +#define COMP_CH BIT16 //channel setting debug +#define COMP_TXAGC BIT17 // For Tx power, 060928, by rcnjko. +#define COMP_HIPWR BIT18 // For High Power Mechanism, 060928, by rcnjko. +#define COMP_HALDM BIT19 // For HW Dynamic Mechanism, 061010, by rcnjko. +#define COMP_SEC BIT20 // Event handling +#define COMP_LED BIT21 // For LED. +#define COMP_RF BIT22 // For RF. +//1!!!!!!!!!!!!!!!!!!!!!!!!!!! +#define COMP_RXDESC BIT23 // Show Rx desc information for SD3 debug. Added by Annie, 2006-07-15. +//1//1Attention Please!!!<11n or 8190 specific code should be put below this line> +//1!!!!!!!!!!!!!!!!!!!!!!!!!!! + +#define COMP_FIRMWARE BIT24 //for firmware downloading +#define COMP_HT BIT25 // For 802.11n HT related information. by Emily 2006-8-11 +#define COMP_AMSDU BIT26 // For A-MSDU Debugging + +#define COMP_SCAN BIT27 +#define COMP_CMD BIT28 +#define COMP_DOWN BIT29 //for rm driver module +#define COMP_RESET BIT30 //for silent reset +#define COMP_ERR BIT31 //for error out, always on +#endif + +#define RTL819x_DEBUG +#ifdef RTL819x_DEBUG +#define assert(expr) \ + if (!(expr)) { \ + printk( "Assertion failed! %s,%s,%s,line=%d\n", \ + #expr,__FILE__,__FUNCTION__,__LINE__); \ + } +//wb added to debug out data buf +//if you want print DATA buffer related BA, please set ieee80211_debug_level to DATA|BA +#define RT_DEBUG_DATA(level, data, datalen) \ + do{ if ((rt_global_debug_component & (level)) == (level)) \ + { \ + int i; \ + u8* pdata = (u8*) data; \ + printk(KERN_DEBUG RTL819xU_MODULE_NAME ": %s()\n", __FUNCTION__); \ + for(i=0; i<(int)(datalen); i++) \ + { \ + printk("%2x ", pdata[i]); \ + if ((i+1)%16 == 0) printk("\n"); \ + } \ + printk("\n"); \ + } \ + } while (0) +#else +#define assert(expr) do {} while (0) +#define RT_DEBUG_DATA(level, data, datalen) do {} while(0) +#endif /* RTL8169_DEBUG */ + +//#ifdef RTL8192SU + //2TODO: We should define 8192S firmware related macro settings here!! + #define RTL819X_DEFAULT_RF_TYPE RF_1T2R + #define RTL819X_TOTAL_RF_PATH 2 + + //#define Rtl819XFwBootArray Rtl8192UsbFwBootArray + //#define Rtl819XFwMainArray Rtl8192UsbFwMainArray + //#define Rtl819XFwDataArray Rtl8192UsbFwDataArray + + #define Rtl819XMACPHY_Array_PG Rtl8192UsbMACPHY_Array_PG + #define Rtl819XMACPHY_Array Rtl8192UsbMACPHY_Array + #define Rtl819XPHY_REGArray Rtl8192UsbPHY_REGArray + #define Rtl819XPHY_REG_1T2RArray Rtl8192UsbPHY_REG_1T2RArray + //#define Rtl819XRadioA_Array Rtl8192UsbRadioA_Array + //#define Rtl819XRadioB_Array Rtl8192UsbRadioB_Array + #define Rtl819XRadioC_Array Rtl8192UsbRadioC_Array + #define Rtl819XRadioD_Array Rtl8192UsbRadioD_Array + + //2008.11.06 Add. + #define Rtl819XFwImageArray Rtl8192SUFwImgArray + #define Rtl819XMAC_Array Rtl8192SUMAC_2T_Array + #define Rtl819XAGCTAB_Array Rtl8192SUAGCTAB_Array + #define Rtl819XPHY_REG_Array Rtl8192SUPHY_REG_2T2RArray + #define Rtl819XPHY_REG_to1T1R_Array Rtl8192SUPHY_ChangeTo_1T1RArray + #define Rtl819XPHY_REG_to1T2R_Array Rtl8192SUPHY_ChangeTo_1T2RArray + #define Rtl819XPHY_REG_to2T2R_Array Rtl8192SUPHY_ChangeTo_2T2RArray + #define Rtl819XPHY_REG_Array_PG Rtl8192SUPHY_REG_Array_PG + #define Rtl819XRadioA_Array Rtl8192SURadioA_1T_Array + #define Rtl819XRadioB_Array Rtl8192SURadioB_Array + #define Rtl819XRadioB_GM_Array Rtl8192SURadioB_GM_Array + #define Rtl819XRadioA_to1T_Array Rtl8192SURadioA_to1T_Array + #define Rtl819XRadioA_to2T_Array Rtl8192SURadioA_to2T_Array +//#endif + +// +// Queue Select Value in TxDesc +// +#define QSLT_BK 0x1 +#define QSLT_BE 0x0 +#define QSLT_VI 0x4 +#define QSLT_VO 0x6 +#define QSLT_BEACON 0x10 +#define QSLT_HIGH 0x11 +#define QSLT_MGNT 0x12 +#define QSLT_CMD 0x13 + +#define DESC90_RATE1M 0x00 +#define DESC90_RATE2M 0x01 +#define DESC90_RATE5_5M 0x02 +#define DESC90_RATE11M 0x03 +#define DESC90_RATE6M 0x04 +#define DESC90_RATE9M 0x05 +#define DESC90_RATE12M 0x06 +#define DESC90_RATE18M 0x07 +#define DESC90_RATE24M 0x08 +#define DESC90_RATE36M 0x09 +#define DESC90_RATE48M 0x0a +#define DESC90_RATE54M 0x0b +#define DESC90_RATEMCS0 0x00 +#define DESC90_RATEMCS1 0x01 +#define DESC90_RATEMCS2 0x02 +#define DESC90_RATEMCS3 0x03 +#define DESC90_RATEMCS4 0x04 +#define DESC90_RATEMCS5 0x05 +#define DESC90_RATEMCS6 0x06 +#define DESC90_RATEMCS7 0x07 +#define DESC90_RATEMCS8 0x08 +#define DESC90_RATEMCS9 0x09 +#define DESC90_RATEMCS10 0x0a +#define DESC90_RATEMCS11 0x0b +#define DESC90_RATEMCS12 0x0c +#define DESC90_RATEMCS13 0x0d +#define DESC90_RATEMCS14 0x0e +#define DESC90_RATEMCS15 0x0f +#define DESC90_RATEMCS32 0x20 + +//#ifdef RTL8192SU +// CCK Rates, TxHT = 0 +#define DESC92S_RATE1M 0x00 +#define DESC92S_RATE2M 0x01 +#define DESC92S_RATE5_5M 0x02 +#define DESC92S_RATE11M 0x03 + +// OFDM Rates, TxHT = 0 +#define DESC92S_RATE6M 0x04 +#define DESC92S_RATE9M 0x05 +#define DESC92S_RATE12M 0x06 +#define DESC92S_RATE18M 0x07 +#define DESC92S_RATE24M 0x08 +#define DESC92S_RATE36M 0x09 +#define DESC92S_RATE48M 0x0a +#define DESC92S_RATE54M 0x0b + +// MCS Rates, TxHT = 1 +#define DESC92S_RATEMCS0 0x0c +#define DESC92S_RATEMCS1 0x0d +#define DESC92S_RATEMCS2 0x0e +#define DESC92S_RATEMCS3 0x0f +#define DESC92S_RATEMCS4 0x10 +#define DESC92S_RATEMCS5 0x11 +#define DESC92S_RATEMCS6 0x12 +#define DESC92S_RATEMCS7 0x13 +#define DESC92S_RATEMCS8 0x14 +#define DESC92S_RATEMCS9 0x15 +#define DESC92S_RATEMCS10 0x16 +#define DESC92S_RATEMCS11 0x17 +#define DESC92S_RATEMCS12 0x18 +#define DESC92S_RATEMCS13 0x19 +#define DESC92S_RATEMCS14 0x1a +#define DESC92S_RATEMCS15 0x1b +#define DESC92S_RATEMCS15_SG 0x1c +#define DESC92S_RATEMCS32 0x20 +//#endif + +#define RTL819X_DEFAULT_RF_TYPE RF_1T2R + +#define IEEE80211_WATCH_DOG_TIME 2000 +#define PHY_Beacon_RSSI_SLID_WIN_MAX 10 +//for txpowertracking by amy +#define OFDM_Table_Length 19 +#define CCK_Table_length 12 + +#ifdef RTL8192SU +// +//Tx Descriptor for RLT8192SU(Normal mode) +// +typedef struct _tx_desc_819x_usb { + // DWORD 0 + u16 PktSize;//:16; + u8 Offset;//:8; + u8 Type:2; // Reserved for MAC header Frame Type subfield. + u8 LastSeg:1; + u8 FirstSeg:1; + u8 LINIP:1; + u8 AMSDU:1; + u8 GF:1; + u8 OWN:1; + + // DWORD 1 + u8 MacID:5; + u8 MoreData:1; + u8 MOREFRAG:1; + u8 PIFS:1; + u8 QueueSelect:5; + u8 AckPolicy:2; + u8 NoACM:1; + u8 NonQos:1; + u8 KeyID:2; + u8 OUI:1; + u8 PktType:1; + u8 EnDescID:1; + u8 SecType:2; + u8 HTC:1; //padding0 + u8 WDS:1; //padding1 + u8 PktOffset:5; //padding_len (hw) + u8 HWPC:1; + + // DWORD 2 + u32 DataRetryLmt:6; + u32 RetryLmtEn:1; + u32 TSFL:5; + u32 RTSRC:6; // Reserved for HW RTS Retry Count. + u32 DATARC:6; // Reserved for HW DATA Retry Count. + u32 Rsvd1:5; + u32 AllowAggregation:1; + u32 BK:1; //Aggregation break. + u32 OwnMAC:1; + + // DWORD 3 + u8 NextHeadPage;//:8; + u8 TailPage;//:8; + u16 Seq:12; + u16 Frag:4; + + // DWORD 4 + u32 RTSRate:6; + u32 DisRTSFB:1; + u32 RTSRateFBLmt:4; + u32 CTS2Self:1; + u32 RTSEn:1; + u32 RaBRSRID:3; //Rate adaptive BRSR ID. + u32 TxHT:1; + u32 TxShort:1;//for data + u32 TxBandwidth:1; + u32 TxSubCarrier:2; + u32 STBC:2; + u32 RD:1; + u32 RTSHT:1; + u32 RTSShort:1; + u32 RTSBW:1; + u32 RTSSubcarrier:2; + u32 RTSSTBC:2; + u32 USERATE:1; + // DWORD 5 + u32 PktID:9; + u32 TxRate:6; + u32 DISFB:1; + u32 DataRateFBLmt:5; + u32 TxAGC:11; + + // DWORD 6 + u16 IPChkSum;//:16; + u16 TCPChkSum;//:16; + + // DWORD 7 + //u16 TxBuffSize;//:16;//pcie + u16 TxBufferSize; + u16 IPHdrOffset:8; + u16 Rsvd2:7; + u16 TCPEn:1; +}tx_desc_819x_usb, *ptx_desc_819x_usb; +typedef struct _tx_status_desc_8192s_usb{ + + //DWORD 0 + u8 TxRate:6; + u8 Rsvd1:1; + u8 BandWidth:1; + u8 RTSRate:6; + u8 AGGLS:1; + u8 AGG:1; + u8 RTSRC:6; + u8 DataRC:6; + u8 FailCause:2; + u8 TxOK:1; + u8 Own:1; + + //DWORD 1 + u16 Seq:12; + u8 QueueSel:5; + u8 MACID:5; + u8 PwrMgt:1; + u8 MoreData:1; + u8 Rsvd2; + + //DWORD 2 + u8 RxAGC1; + u8 RxAGC2; + u8 RxAGC3; + u8 RxAGC4; +}tx_status_desc_8192s_usb, *ptx_status_desc_8192s_usb; +#else +/* for rtl819x */ +typedef struct _tx_desc_819x_usb { + //DWORD 0 + u16 PktSize; + u8 Offset; + u8 Reserved0:3; + u8 CmdInit:1; + u8 LastSeg:1; + u8 FirstSeg:1; + u8 LINIP:1; + u8 OWN:1; + + //DWORD 1 + u8 TxFWInfoSize; + u8 RATid:3; + u8 DISFB:1; + u8 USERATE:1; + u8 MOREFRAG:1; + u8 NoEnc:1; + u8 PIFS:1; + u8 QueueSelect:5; + u8 NoACM:1; + u8 Reserved1:2; + u8 SecCAMID:5; + u8 SecDescAssign:1; + u8 SecType:2; + + //DWORD 2 + u16 TxBufferSize; + //u16 Reserved2; + u8 ResvForPaddingLen:7; + u8 Reserved3:1; + u8 Reserved4; + + //DWORD 3, 4, 5 + u32 Reserved5; + u32 Reserved6; + u32 Reserved7; +}tx_desc_819x_usb, *ptx_desc_819x_usb; +#endif + +#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE +typedef struct _tx_desc_819x_usb_aggr_subframe { + //DWORD 0 + u16 PktSize; + u8 Offset; + u8 TxFWInfoSize; + + //DWORD 1 + u8 RATid:3; + u8 DISFB:1; + u8 USERATE:1; + u8 MOREFRAG:1; + u8 NoEnc:1; + u8 PIFS:1; + u8 QueueSelect:5; + u8 NoACM:1; + u8 Reserved1:2; + u8 SecCAMID:5; + u8 SecDescAssign:1; + u8 SecType:2; + u8 PacketID:7; + u8 OWN:1; +}tx_desc_819x_usb_aggr_subframe, *ptx_desc_819x_usb_aggr_subframe; +#endif + + +#ifdef RTL8192SU +// +//Tx Descriptor for RLT8192SU(Load FW mode) +// +typedef struct _tx_desc_cmd_819x_usb{ + // DWORD 0 + u16 PktSize; + u8 Offset; + u8 Rsvd0:4; + u8 LINIP:1; + u8 Rsvd1:2; + u8 OWN:1; + + // DWORD 1, 2, 3, 4, 5, 6 are all reserved. + u32 Rsvd2; + u32 Rsvd3; + u32 Rsvd4; + u32 Rsvd5; + u32 Rsvd6; + u32 Rsvd7; + + // DWORD 7 + u16 TxBuffSize;//pcie + u16 Rsvd8; +}tx_desc_cmd_819x_usb, *ptx_desc_cmd_819x_usb; +// +//H2C Command for RLT8192SU(Host TxCmd) +// +typedef struct _tx_h2c_desc_cmd_8192s_usb{ + // DWORD 0 + u32 PktSize:16; + u32 Offset:8; + u32 Rsvd0:7; + u32 OWN:1; + + // DWORD 1 + u32 Rsvd1:8; + u32 QSEL:5; + u32 Rsvd2:19; + + // DWORD 2 + u32 Rsvd3; + + // DWORD 3 + u32 NextHeadPage:8; + u32 TailPage:8; + u32 Rsvd4:16; + + // DWORD 4, 5, 6, 7 + u32 Rsvd5; + u32 Rsvd6; + u32 Rsvd7; + u32 Rsvd8; +}tx_h2c_desc_cmd_8192s_usb, *ptx_h2c_desc_cmd_8192s_usb; + + +typedef struct _tx_h2c_cmd_hdr_8192s_usb{ + // DWORD 0 + u32 CmdLen:16; + u32 ElementID:8; + u32 CmdSeq:8; + + // DWORD 1 + u32 Rsvd0; +}tx_h2c_cmd_hdr_8192s_usb, *ptx_h2c_cmd_hdr_8192s_usb; +#else +typedef struct _tx_desc_cmd_819x_usb { + //DWORD 0 + u16 Reserved0; + u8 Reserved1; + u8 Reserved2:3; + u8 CmdInit:1; + u8 LastSeg:1; + u8 FirstSeg:1; + u8 LINIP:1; + u8 OWN:1; + + //DOWRD 1 + //u32 Reserved3; + u8 TxFWInfoSize; + u8 Reserved3; + u8 QueueSelect; + u8 Reserved4; + + //DOWRD 2 + u16 TxBufferSize; + u16 Reserved5; + + //DWORD 3,4,5 + //u32 TxBufferAddr; + //u32 NextDescAddress; + u32 Reserved6; + u32 Reserved7; + u32 Reserved8; +}tx_desc_cmd_819x_usb, *ptx_desc_cmd_819x_usb; +#endif + +#ifdef RTL8192SU +typedef struct _tx_fwinfo_819x_usb{ + //DWORD 0 + u8 TxRate:7; + u8 CtsEnable:1; + u8 RtsRate:7; + u8 RtsEnable:1; + u8 TxHT:1; + u8 Short:1; //Short PLCP for CCK, or short GI for 11n MCS + u8 TxBandwidth:1; // This is used for HT MCS rate only. + u8 TxSubCarrier:2; // This is used for legacy OFDM rate only. + u8 STBC:2; + u8 AllowAggregation:1; + u8 RtsHT:1; //Interpre RtsRate field as high throughput data rate + u8 RtsShort:1; //Short PLCP for CCK, or short GI for 11n MCS + u8 RtsBandwidth:1; // This is used for HT MCS rate only. + u8 RtsSubcarrier:2; // This is used for legacy OFDM rate only. + u8 RtsSTBC:2; + u8 EnableCPUDur:1; //Enable firmware to recalculate and assign packet duration + + //DWORD 1 + u32 RxMF:2; + u32 RxAMD:3; + u32 Reserved1:3; + u32 TxAGCOffSet:4;//TxAGCOffset:4; + u32 TxAGCSign:1; + u32 Tx_INFO_RSVD:6; + u32 PacketID:13; +}tx_fwinfo_819x_usb, *ptx_fwinfo_819x_usb; +#else +typedef struct _tx_fwinfo_819x_usb { + //DOWRD 0 + u8 TxRate:7; + u8 CtsEnable:1; + u8 RtsRate:7; + u8 RtsEnable:1; + u8 TxHT:1; + u8 Short:1; //Short PLCP for CCK, or short GI for 11n MCS + u8 TxBandwidth:1; // This is used for HT MCS rate only. + u8 TxSubCarrier:2; // This is used for legacy OFDM rate only. + u8 STBC:2; + u8 AllowAggregation:1; + u8 RtsHT:1; //Interpre RtsRate field as high throughput data rate + u8 RtsShort:1; //Short PLCP for CCK, or short GI for 11n MCS + u8 RtsBandwidth:1; // This is used for HT MCS rate only. + u8 RtsSubcarrier:2; // This is used for legacy OFDM rate only. + u8 RtsSTBC:2; + u8 EnableCPUDur:1; //Enable firmware to recalculate and assign packet duration + + //DWORD 1 + u32 RxMF:2; + u32 RxAMD:3; + u32 TxPerPktInfoFeedback:1;//1 indicate Tx info gathtered by firmware and returned by Rx Cmd + u32 Reserved1:2; + u32 TxAGCOffSet:4; + u32 TxAGCSign:1; + u32 Tx_INFO_RSVD:6; + u32 PacketID:13; + //u32 Reserved; +}tx_fwinfo_819x_usb, *ptx_fwinfo_819x_usb; +#endif + +typedef struct rtl8192_rx_info { + struct urb *urb; + struct net_device *dev; + u8 out_pipe; +}rtl8192_rx_info ; + +#ifdef RTL8192SU +//typedef struct _RX_DESC_STATUS_8192SU{ +typedef struct rx_desc_819x_usb{ + //DWORD 0 + u16 Length:14; + u16 CRC32:1; + u16 ICV:1; + u8 RxDrvInfoSize:4; + u8 Security:3; + u8 Qos:1; + u8 Shift:2; + u8 PHYStatus:1; + u8 SWDec:1; + u8 LastSeg:1; + u8 FirstSeg:1; + u8 EOR:1; + u8 Own:1; + + //DWORD 1 + u16 MACID:5; + u16 TID:4; + u16 HwRsvd:5; + u16 PAGGR:1; + u16 FAGGR:1; + u8 A1_FIT:4; + u8 A2_FIT:4; + u8 PAM:1; + u8 PWR:1; + u8 MoreData:1; + u8 MoreFrag:1; + u8 Type:2; + u8 MC:1; + u8 BC:1; + + //DWORD 2 + u16 Seq:12; + u16 Frag:4; +#ifdef USB_RX_AGGREGATION_SUPPORT + u8 UsbAggPktNum;//:8; +#else + u8 NextPktLen;//:8; +#endif + u8 Rsvd0:6; + u8 NextIND:1; + u8 Rsvd1:1; + + //DWORD 3 + u8 RxMCS:6; + u8 RxHT:1; + u8 AMSDU:1; + u8 SPLCP:1; + u8 BW:1; + u8 HTC:1; + u8 TCPChkRpt:1; + u8 IPChkRpt:1; + u8 TCPChkValID:1; + u8 HwPCErr:1; + u8 HwPCInd:1; + u16 IV0;//:16; + + //DWORD 4 + u32 IV1; + + //DWORD 5 + u32 TSFL; +//}RX_DESC_STATUS_8192SU, *PRX_DESC_STATUS_8192SU; +}rx_desc_819x_usb, *prx_desc_819x_usb; +#else +typedef struct rx_desc_819x_usb{ + //DOWRD 0 + u16 Length:14; + u16 CRC32:1; + u16 ICV:1; + u8 RxDrvInfoSize; + u8 Shift:2; + u8 PHYStatus:1; + u8 SWDec:1; + //u8 LastSeg:1; + //u8 FirstSeg:1; + //u8 EOR:1; + //u8 OWN:1; + u8 Reserved1:4; + + //DWORD 1 + u32 Reserved2; + + //DWORD 2 + //u32 Reserved3; + + //DWORD 3 + //u32 BufferAddress; + +}rx_desc_819x_usb, *prx_desc_819x_usb; +#endif + +#ifdef USB_RX_AGGREGATION_SUPPORT +typedef struct _rx_desc_819x_usb_aggr_subframe{ + //DOWRD 0 + u16 Length:14; + u16 CRC32:1; + u16 ICV:1; + u8 Offset; + u8 RxDrvInfoSize; + //DOWRD 1 + u8 Shift:2; + u8 PHYStatus:1; + u8 SWDec:1; + u8 Reserved1:4; + u8 Reserved2; + u16 Reserved3; + //DWORD 2 + //u4Byte Reserved3; + //DWORD 3 + //u4Byte BufferAddress; +}rx_desc_819x_usb_aggr_subframe, *prx_desc_819x_usb_aggr_subframe; +#endif + +#ifdef RTL8192SU +// +// Driver info are written to the begining of the RxBuffer +// +//typedef struct _RX_DRIVER_INFO_8192S{ +typedef struct rx_drvinfo_819x_usb{ + // + // Driver info contain PHY status and other variabel size info + // PHY Status content as below + // + + //DWORD 0 + /*u4Byte gain_0:7; + u4Byte trsw_0:1; + u4Byte gain_1:7; + u4Byte trsw_1:1; + u4Byte gain_2:7; + u4Byte trsw_2:1; + u4Byte gain_3:7; + u4Byte trsw_3:1; */ + u8 gain_trsw[4]; + + //DWORD 1 + /*u4Byte pwdb_all:8; + u4Byte cfosho_0:8; + u4Byte cfosho_1:8; + u4Byte cfosho_2:8;*/ + u8 pwdb_all; + u8 cfosho[4]; + + //DWORD 2 + /*u4Byte cfosho_3:8; + u4Byte cfotail_0:8; + u4Byte cfotail_1:8; + u4Byte cfotail_2:8;*/ + u8 cfotail[4]; + + //DWORD 3 + /*u4Byte cfotail_3:8; + u4Byte rxevm_0:8; + u4Byte rxevm_1:8; + u4Byte rxsnr_0:8;*/ + char rxevm[2]; + char rxsnr[4]; + + //DWORD 4 + /*u4Byte rxsnr_1:8; + u4Byte rxsnr_2:8; + u4Byte rxsnr_3:8; + u4Byte pdsnr_0:8;*/ + u8 pdsnr[2]; + + //DWORD 5 + /*u4Byte pdsnr_1:8; + u4Byte csi_current_0:8; + u4Byte csi_current_1:8; + u4Byte csi_target_0:8;*/ + u8 csi_current[2]; + u8 csi_target[2]; + + //DWORD 6 + /*u4Byte csi_target_1:8; + u4Byte sigevm:8; + u4Byte max_ex_pwr:8; + u4Byte ex_intf_flag:1; + u4Byte sgi_en:1; + u4Byte rxsc:2; + u4Byte reserve:4;*/ + u8 sigevm; + u8 max_ex_pwr; + u8 ex_intf_flag:1; + u8 sgi_en:1; + u8 rxsc:2; + u8 reserve:4; + +}rx_drvinfo_819x_usb, *prx_drvinfo_819x_usb; +#else +typedef struct rx_drvinfo_819x_usb{ + //DWORD 0 + u16 Reserved1:12; + u16 PartAggr:1; + u16 FirstAGGR:1; + u16 Reserved2:2; + + u8 RxRate:7; + u8 RxHT:1; + + u8 BW:1; + u8 SPLCP:1; + u8 Reserved3:2; + u8 PAM:1; + u8 Mcast:1; + u8 Bcast:1; + u8 Reserved4:1; + + //DWORD 1 + u32 TSFL; + +}rx_drvinfo_819x_usb, *prx_drvinfo_819x_usb; +#endif + + #define HWSET_MAX_SIZE_92S 128 +#ifdef RTL8192SU + #define MAX_802_11_HEADER_LENGTH 40 + #define MAX_PKT_AGG_NUM 256 + #define TX_PACKET_SHIFT_BYTES USB_HWDESC_HEADER_LEN +#else + #define MAX_802_11_HEADER_LENGTH (40 + MAX_FIRMWARE_INFORMATION_SIZE) + #define MAX_PKT_AGG_NUM 64 + #define TX_PACKET_SHIFT_BYTES (USB_HWDESC_HEADER_LEN + sizeof(tx_fwinfo_819x_usb)) +#endif + +#define MAX_DEV_ADDR_SIZE 8 /* support till 64 bit bus width OS */ +#define MAX_FIRMWARE_INFORMATION_SIZE 32 /*2006/04/30 by Emily forRTL8190*/ +//#define MAX_802_11_HEADER_LENGTH (40 + MAX_FIRMWARE_INFORMATION_SIZE) +#define ENCRYPTION_MAX_OVERHEAD 128 +#define USB_HWDESC_HEADER_LEN sizeof(tx_desc_819x_usb) +//#define TX_PACKET_SHIFT_BYTES (USB_HWDESC_HEADER_LEN + sizeof(tx_fwinfo_819x_usb)) +#define MAX_FRAGMENT_COUNT 8 +#ifdef RTL8192U +#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE +#define MAX_TRANSMIT_BUFFER_SIZE 32000 +#else +#define MAX_TRANSMIT_BUFFER_SIZE 8000 +#endif +#else +#define MAX_TRANSMIT_BUFFER_SIZE (1600+(MAX_802_11_HEADER_LENGTH+ENCRYPTION_MAX_OVERHEAD)*MAX_FRAGMENT_COUNT) +#endif +#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE +#define TX_PACKET_DRVAGGR_SUBFRAME_SHIFT_BYTES (sizeof(tx_desc_819x_usb_aggr_subframe) + sizeof(tx_fwinfo_819x_usb)) +#endif +#define scrclng 4 // octets for crc32 (FCS, ICV) + +typedef enum rf_optype +{ + RF_OP_By_SW_3wire = 0, + RF_OP_By_FW, + RF_OP_MAX +}rf_op_type; +/* 8190 Loopback Mode definition */ +typedef enum _rtl819xUsb_loopback{ + RTL819xU_NO_LOOPBACK = 0, + RTL819xU_MAC_LOOPBACK = 1, + RTL819xU_DMA_LOOPBACK = 2, + RTL819xU_CCK_LOOPBACK = 3, +}rtl819xUsb_loopback_e; + +/* for rtl819x */ +typedef enum _RT_STATUS{ + RT_STATUS_SUCCESS = 0, + RT_STATUS_FAILURE = 1, + RT_STATUS_PENDING = 2, + RT_STATUS_RESOURCE = 3 +}RT_STATUS,*PRT_STATUS; + +//#ifdef RTL8192SU +typedef enum _RTL8192SUSB_LOOPBACK{ + RTL8192SU_NO_LOOPBACK = 0, + RTL8192SU_MAC_LOOPBACK = 1, + RTL8192SU_DMA_LOOPBACK = 2, + RTL8192SU_CCK_LOOPBACK = 3, +}RTL8192SUSB_LOOPBACK_E; +//#endif + + +#if 0 +/* due to rtl8192 firmware */ +typedef enum _desc_packet_type_e{ + DESC_PACKET_TYPE_INIT = 0, + DESC_PACKET_TYPE_NORMAL = 1, +}desc_packet_type_e; + +typedef enum _firmware_source{ + FW_SOURCE_IMG_FILE = 0, + FW_SOURCE_HEADER_FILE = 1, //from header file +}firmware_source_e, *pfirmware_source_e; + +typedef enum _firmware_status{ + FW_STATUS_0_INIT = 0, + FW_STATUS_1_MOVE_BOOT_CODE = 1, + FW_STATUS_2_MOVE_MAIN_CODE = 2, + FW_STATUS_3_TURNON_CPU = 3, + FW_STATUS_4_MOVE_DATA_CODE = 4, + FW_STATUS_5_READY = 5, +}firmware_status_e; + +typedef struct _rt_firmare_seg_container { + u16 seg_size; + u8 *seg_ptr; +}fw_seg_container, *pfw_seg_container; + +#ifdef RTL8192SU +//-------------------------------------------------------------------------------- +// 8192S Firmware related +//-------------------------------------------------------------------------------- +typedef struct _RT_8192S_FIRMWARE_PRIV { //8-bytes alignment required + + //--- LONG WORD 0 ---- + u32 RegulatoryClass; + u32 Rfintfs; + + //--- LONG WORD 1 ---- + u32 ChipVer; + u32 HCISel; + + //--- LONG WORD 2 ---- + u32 IBKMode; + u32 Rsvd00; + + //--- LONG WORD 3 ---- + u32 Rsvd01; + u8 Qos_En; // QoS enable + u8 En40MHz; // 40MHz BW enable + u8 AMSDU2AMPDU_En; //14181 convert AMSDU to AMPDU, 0: disable + u8 AMPDU_En; //111n AMPDU/AMSDU enable + + //--- LONG WORD 4 ---- + u8 rate_control_offload;//FW offloads, 0: driver handles + u8 aggregation_offload; // FW offloads, 0: driver handles + u8 beacon_offload; //FW offloads, 0: driver handles + u8 MLME_offload; // FW offloads, 0: driver handles + u8 hwpc_offload; // FW offloads, 0: driver handles + u8 tcp_checksum_offload; //FW offloads, 0: driver handles + u8 tcp_offload; //FW offloads, 0: driver handles + u8 ps_control_offload; //FW offloads, 0: driver handles + + //--- LONG WORD 5 ---- + u8 WWLAN_Offload; // FW offloads, 0: driver handles + u8 MPMode; // normal mode, 0: MP mode; + u16 Version; //0x8000 ~ 0x8FFF for FPGA version, 0x0000 ~ 0x7FFF for ASIC version, + u16 Signature; //0x12: 8712, 0x92: 8192S + u16 Rsvd11; + +// u32 rsvd1; +// u32 wireless_band; //no A-band exists in 8712 +}RT_8192S_FIRMWARE_PRIV, *PRT_8192S_FIRMWARE_PRIV; + +typedef struct _RT_8192S_FIRMWARE_HDR {//8-byte alinment required + + //--- LONG WORD 0 ---- + u16 Signature; + u16 Version; //0x8000 ~ 0x8FFF for FPGA version, 0x0000 ~ 0x7FFF for ASIC version, + u32 DMEMSize; //define the size of boot loader + + + //--- LONG WORD 1 ---- + u32 IMG_IMEM_SIZE; //define the size of FW in IMEM + u32 IMG_SRAM_SIZE; //define the size of FW in SRAM + + //--- LONG WORD 2 ---- + u32 FW_PRIV_SIZE; //define the size of DMEM variable + u32 Rsvd0; + + //--- LONG WORD 3 ---- + u32 Rsvd1; + u32 Rsvd2; + + RT_8192S_FIRMWARE_PRIV FWPriv; + +}RT_8192S_FIRMWARE_HDR, *PRT_8192S_FIRMWARE_HDR; + +#define RT_8192S_FIRMWARE_HDR_SIZE 80 + +typedef enum _FIRMWARE_8192S_STATUS{ + FW_STATUS_INIT = 0, + FW_STATUS_LOAD_IMEM = 1, + FW_STATUS_LOAD_EMEM = 2, + FW_STATUS_LOAD_DMEM = 3, + FW_STATUS_READY = 4, +}FIRMWARE_8192S_STATUS; + +#define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000 //64k + +typedef struct _rt_firmware{ + firmware_source_e eFWSource; + PRT_8192S_FIRMWARE_HDR pFwHeader; + FIRMWARE_8192S_STATUS FWStatus; + u8 FwIMEM[64000]; + u8 FwEMEM[64000]; + u32 FwIMEMLen; + u32 FwEMEMLen; + u8 szFwTmpBuffer[164000]; + u16 CmdPacketFragThresold; + //firmware_status_e firmware_status;//in 92u temp FIXLZM + //u16 cmdpacket_frag_thresold;//in 92u temp FIXLZM + //u8 firmware_buf[RTL8190_MAX_FIRMWARE_CODE_SIZE];//in 92u temp FIXLZM + //u16 firmware_buf_size;//in 92u temp FIXLZM + +}rt_firmware, *prt_firmware; +#else +typedef struct _rt_firmware{ + firmware_status_e firmware_status; + u16 cmdpacket_frag_thresold; +#define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000 //64k +#define MAX_FW_INIT_STEP 3 + u8 firmware_buf[MAX_FW_INIT_STEP][RTL8190_MAX_FIRMWARE_CODE_SIZE]; + u16 firmware_buf_size[MAX_FW_INIT_STEP]; +}rt_firmware, *prt_firmware; +#endif +typedef struct _rt_firmware_info_819xUsb{ + u8 sz_info[16]; +}rt_firmware_info_819xUsb, *prt_firmware_info_819xUsb; +#endif + +//+by amy 080507 +#define MAX_RECEIVE_BUFFER_SIZE 9100 // Add this to 9100 bytes to receive A-MSDU from RT-AP + + +/* Firmware Queue Layout */ +#define NUM_OF_FIRMWARE_QUEUE 10 +#define NUM_OF_PAGES_IN_FW 0x100 + +#ifdef USE_ONE_PIPE +#define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x000 +#define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x000 +#define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x0ff +#define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x000 +#define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0 +#define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x0 +#define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x00 +#define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0 +#define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x0 +#define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0x00 +#else + +#define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x020 +#define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x020 +#define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x040 +#define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x040 +#define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0 +#define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x4 +#define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x20 +#define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0 +#define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x4 +#define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0x18 + +#endif + +#define APPLIED_RESERVED_QUEUE_IN_FW 0x80000000 +#define RSVD_FW_QUEUE_PAGE_BK_SHIFT 0x00 +#define RSVD_FW_QUEUE_PAGE_BE_SHIFT 0x08 +#define RSVD_FW_QUEUE_PAGE_VI_SHIFT 0x10 +#define RSVD_FW_QUEUE_PAGE_VO_SHIFT 0x18 +#define RSVD_FW_QUEUE_PAGE_MGNT_SHIFT 0x10 +#define RSVD_FW_QUEUE_PAGE_CMD_SHIFT 0x08 +#define RSVD_FW_QUEUE_PAGE_BCN_SHIFT 0x00 +#define RSVD_FW_QUEUE_PAGE_PUB_SHIFT 0x08 +//================================================================= +//================================================================= + +#define EPROM_93c46 0 +#define EPROM_93c56 1 + +#define DEFAULT_FRAG_THRESHOLD 2342U +#define MIN_FRAG_THRESHOLD 256U +#define DEFAULT_BEACONINTERVAL 0x64U +#define DEFAULT_BEACON_ESSID "Rtl819xU" + +#define DEFAULT_SSID "" +#define DEFAULT_RETRY_RTS 7 +#define DEFAULT_RETRY_DATA 7 +#define PRISM_HDR_SIZE 64 + +#define PHY_RSSI_SLID_WIN_MAX 100 + + +typedef enum _WIRELESS_MODE { + WIRELESS_MODE_UNKNOWN = 0x00, + WIRELESS_MODE_A = 0x01, + WIRELESS_MODE_B = 0x02, + WIRELESS_MODE_G = 0x04, + WIRELESS_MODE_AUTO = 0x08, + WIRELESS_MODE_N_24G = 0x10, + WIRELESS_MODE_N_5G = 0x20 +} WIRELESS_MODE; + + +#define RTL_IOCTL_WPA_SUPPLICANT SIOCIWFIRSTPRIV+30 + +typedef struct buffer +{ + struct buffer *next; + u32 *buf; + +} buffer; + +typedef struct rtl_reg_debug{ + unsigned int cmd; + struct { + unsigned char type; + unsigned char addr; + unsigned char page; + unsigned char length; + } head; + unsigned char buf[0xff]; +}rtl_reg_debug; + + + + + +#if 0 + +typedef struct tx_pendingbuf +{ + struct ieee80211_txb *txb; + short ispending; + short descfrag; +} tx_pendigbuf; + +#endif + +typedef struct _rt_9x_tx_rate_history { + u32 cck[4]; + u32 ofdm[8]; + // HT_MCS[0][]: BW=0 SG=0 + // HT_MCS[1][]: BW=1 SG=0 + // HT_MCS[2][]: BW=0 SG=1 + // HT_MCS[3][]: BW=1 SG=1 + u32 ht_mcs[4][16]; +}rt_tx_rahis_t, *prt_tx_rahis_t; +typedef struct _RT_SMOOTH_DATA_4RF { + char elements[4][100];//array to store values + u32 index; //index to current array to store + u32 TotalNum; //num of valid elements + u32 TotalVal[4]; //sum of valid elements +}RT_SMOOTH_DATA_4RF, *PRT_SMOOTH_DATA_4RF; + +#define MAX_8192U_RX_SIZE 8192 // This maybe changed for D-cut larger aggregation size +//stats seems messed up, clean it ASAP +typedef struct Stats +{ + unsigned long txrdu; +// unsigned long rxrdu; + //unsigned long rxnolast; + //unsigned long rxnodata; +// unsigned long rxreset; +// unsigned long rxnopointer; + unsigned long rxok; + unsigned long rxframgment; + unsigned long rxcmdpkt[4]; //08/05/08 amy rx cmd element txfeedback/bcn report/cfg set/query + unsigned long rxurberr; + unsigned long rxstaterr; + unsigned long received_rate_histogram[4][32]; //0: Total, 1:OK, 2:CRC, 3:ICV, 2007 07 03 cosa + unsigned long received_preamble_GI[2][32]; //0: Long preamble/GI, 1:Short preamble/GI + unsigned long rx_AMPDUsize_histogram[5]; // level: (<4K), (4K~8K), (8K~16K), (16K~32K), (32K~64K) + unsigned long rx_AMPDUnum_histogram[5]; // level: (<5), (5~10), (10~20), (20~40), (>40) + unsigned long numpacket_matchbssid; // debug use only. + unsigned long numpacket_toself; // debug use only. + unsigned long num_process_phyinfo; // debug use only. + unsigned long numqry_phystatus; + unsigned long numqry_phystatusCCK; + unsigned long numqry_phystatusHT; + unsigned long received_bwtype[5]; //0: 20M, 1: funn40M, 2: upper20M, 3: lower20M, 4: duplicate + unsigned long txnperr; + unsigned long txnpdrop; + unsigned long txresumed; +// unsigned long rxerr; +// unsigned long rxoverflow; +// unsigned long rxint; + unsigned long txnpokint; +// unsigned long txhpokint; +// unsigned long txhperr; +// unsigned long ints; +// unsigned long shints; + unsigned long txoverflow; +// unsigned long rxdmafail; +// unsigned long txbeacon; +// unsigned long txbeaconerr; + unsigned long txlpokint; + unsigned long txlpdrop; + unsigned long txlperr; + unsigned long txbeokint; + unsigned long txbedrop; + unsigned long txbeerr; + unsigned long txbkokint; + unsigned long txbkdrop; + unsigned long txbkerr; + unsigned long txviokint; + unsigned long txvidrop; + unsigned long txvierr; + unsigned long txvookint; + unsigned long txvodrop; + unsigned long txvoerr; + unsigned long txbeaconokint; + unsigned long txbeacondrop; + unsigned long txbeaconerr; + unsigned long txmanageokint; + unsigned long txmanagedrop; + unsigned long txmanageerr; + unsigned long txdatapkt; + unsigned long txfeedback; + unsigned long txfeedbackok; + + unsigned long txoktotal; + unsigned long txokbytestotal; + unsigned long txokinperiod; + unsigned long txmulticast; + unsigned long txbytesmulticast; + unsigned long txbroadcast; + unsigned long txbytesbroadcast; + unsigned long txunicast; + unsigned long txbytesunicast; + + unsigned long rxoktotal; + unsigned long rxbytesunicast; + unsigned long txfeedbackfail; + unsigned long txerrtotal; + unsigned long txerrbytestotal; + unsigned long txerrmulticast; + unsigned long txerrbroadcast; + unsigned long txerrunicast; + unsigned long txretrycount; + unsigned long txfeedbackretry; + u8 last_packet_rate; + unsigned long slide_signal_strength[100]; + unsigned long slide_evm[100]; + unsigned long slide_rssi_total; // For recording sliding window's RSSI value + unsigned long slide_evm_total; // For recording sliding window's EVM value + long signal_strength; // Transformed, in dbm. Beautified signal strength for UI, not correct. + long signal_quality; + long last_signal_strength_inpercent; + long recv_signal_power; // Correct smoothed ss in Dbm, only used in driver to report real power now. + u8 rx_rssi_percentage[4]; + u8 rx_evm_percentage[2]; + long rxSNRdB[4]; + rt_tx_rahis_t txrate; + u32 Slide_Beacon_pwdb[100]; //cosa add for beacon rssi + u32 Slide_Beacon_Total; //cosa add for beacon rssi + RT_SMOOTH_DATA_4RF cck_adc_pwdb; + + u32 CurrentShowTxate; +} Stats; + + +// Bandwidth Offset +#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0 +#define HAL_PRIME_CHNL_OFFSET_LOWER 1 +#define HAL_PRIME_CHNL_OFFSET_UPPER 2 + +//+by amy 080507 + +typedef struct ChnlAccessSetting { + u16 SIFS_Timer; + u16 DIFS_Timer; + u16 SlotTimeTimer; + u16 EIFS_Timer; + u16 CWminIndex; + u16 CWmaxIndex; +}*PCHANNEL_ACCESS_SETTING,CHANNEL_ACCESS_SETTING; + +typedef struct _BB_REGISTER_DEFINITION{ + u32 rfintfs; // set software control: // 0x870~0x877[8 bytes] + u32 rfintfi; // readback data: // 0x8e0~0x8e7[8 bytes] + u32 rfintfo; // output data: // 0x860~0x86f [16 bytes] + u32 rfintfe; // output enable: // 0x860~0x86f [16 bytes] + u32 rf3wireOffset; // LSSI data: // 0x840~0x84f [16 bytes] + u32 rfLSSI_Select; // BB Band Select: // 0x878~0x87f [8 bytes] + u32 rfTxGainStage; // Tx gain stage: // 0x80c~0x80f [4 bytes] + u32 rfHSSIPara1; // wire parameter control1 : // 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes] + u32 rfHSSIPara2; // wire parameter control2 : // 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes] + u32 rfSwitchControl; //Tx Rx antenna control : // 0x858~0x85f [16 bytes] + u32 rfAGCControl1; //AGC parameter control1 : // 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes] + u32 rfAGCControl2; //AGC parameter control2 : // 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes] + u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix : // 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes] + u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : // 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes] + u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix // 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes] + u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type // 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes] + u32 rfLSSIReadBack; //LSSI RF readback data // 0x8a0~0x8af [16 bytes] + u32 rfLSSIReadBackPi; //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B +}BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T; + +typedef enum _RT_RF_TYPE_819xU{ + RF_TYPE_MIN = 0, + RF_8225, + RF_8256, + RF_8258, + RF_6052=4, // 4 11b/g/n RF + RF_PSEUDO_11N = 5, +}RT_RF_TYPE_819xU, *PRT_RF_TYPE_819xU; + +//#ifdef RTL8192SU +typedef enum _RF_POWER_STATE{ + RF_ON, + RF_SLEEP, + RF_OFF, + RF_SHUT_DOWN, +}RF_POWER_STATE, *PRF_POWER_STATE; +//#endif + +typedef struct _rate_adaptive +{ + u8 rate_adaptive_disabled; + u8 ratr_state; + u16 reserve; + + u32 high_rssi_thresh_for_ra; + u32 high2low_rssi_thresh_for_ra; + u8 low2high_rssi_thresh_for_ra40M; + u32 low_rssi_thresh_for_ra40M; + u8 low2high_rssi_thresh_for_ra20M; + u32 low_rssi_thresh_for_ra20M; + u32 upper_rssi_threshold_ratr; + u32 middle_rssi_threshold_ratr; + u32 low_rssi_threshold_ratr; + u32 low_rssi_threshold_ratr_40M; + u32 low_rssi_threshold_ratr_20M; + u8 ping_rssi_enable; //cosa add for test + u32 ping_rssi_ratr; //cosa add for test + u32 ping_rssi_thresh_for_ra;//cosa add for test + u32 last_ratr; + +} rate_adaptive, *prate_adaptive; + +#define TxBBGainTableLength 37 +#define CCKTxBBGainTableLength 23 + +typedef struct _txbbgain_struct +{ + long txbb_iq_amplifygain; + u32 txbbgain_value; +} txbbgain_struct, *ptxbbgain_struct; + +typedef struct _ccktxbbgain_struct +{ + //The Value is from a22 to a29 one Byte one time is much Safer + u8 ccktxbb_valuearray[8]; +} ccktxbbgain_struct,*pccktxbbgain_struct; + + +typedef struct _init_gain +{ + u8 xaagccore1; + u8 xbagccore1; + u8 xcagccore1; + u8 xdagccore1; + u8 cca; + +} init_gain, *pinit_gain; +//by amy 0606 + +typedef struct _phy_ofdm_rx_status_report_819xusb +{ + u8 trsw_gain_X[4]; + u8 pwdb_all; + u8 cfosho_X[4]; + u8 cfotail_X[4]; + u8 rxevm_X[2]; + u8 rxsnr_X[4]; + u8 pdsnr_X[2]; + u8 csi_current_X[2]; + u8 csi_target_X[2]; + u8 sigevm; + u8 max_ex_pwr; + u8 sgi_en; + u8 rxsc_sgien_exflg; +}phy_sts_ofdm_819xusb_t; + +typedef struct _phy_cck_rx_status_report_819xusb +{ + /* For CCK rate descriptor. This is a unsigned 8:1 variable. LSB bit presend + 0.5. And MSB 7 bts presend a signed value. Range from -64~+63.5. */ + u8 adc_pwdb_X[4]; + u8 sq_rpt; + u8 cck_agc_rpt; +}phy_sts_cck_819xusb_t; + + +typedef struct _phy_ofdm_rx_status_rxsc_sgien_exintfflag{ + u8 reserved:4; + u8 rxsc:2; + u8 sgi_en:1; + u8 ex_intf_flag:1; +}phy_ofdm_rx_status_rxsc_sgien_exintfflag; + +typedef enum _RT_CUSTOMER_ID +{ + RT_CID_DEFAULT = 0, + RT_CID_8187_ALPHA0 = 1, + RT_CID_8187_SERCOMM_PS = 2, + RT_CID_8187_HW_LED = 3, + RT_CID_8187_NETGEAR = 4, + RT_CID_WHQL = 5, + RT_CID_819x_CAMEO = 6, + RT_CID_819x_RUNTOP = 7, + RT_CID_819x_Senao = 8, + RT_CID_TOSHIBA = 9, // Merge by Jacken, 2008/01/31. + RT_CID_819x_Netcore = 10, + RT_CID_Nettronix = 11, + RT_CID_DLINK = 12, + RT_CID_PRONET = 13, +}RT_CUSTOMER_ID, *PRT_CUSTOMER_ID; + +//================================================================================ +// LED customization. +//================================================================================ + +typedef enum _LED_STRATEGY_8190{ + SW_LED_MODE0, // SW control 1 LED via GPIO0. It is default option. + SW_LED_MODE1, // SW control for PCI Express + SW_LED_MODE2, // SW control for Cameo. + SW_LED_MODE3, // SW contorl for RunTop. + SW_LED_MODE4, // SW control for Netcore + HW_LED, // HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes) +}LED_STRATEGY_8190, *PLED_STRATEGY_8190; + +typedef enum _RESET_TYPE { + RESET_TYPE_NORESET = 0x00, + RESET_TYPE_NORMAL = 0x01, + RESET_TYPE_SILENT = 0x02 +} RESET_TYPE; + +/* The simple tx command OP code. */ +typedef enum _tag_TxCmd_Config_Index{ + TXCMD_TXRA_HISTORY_CTRL = 0xFF900000, + TXCMD_RESET_TX_PKT_BUFF = 0xFF900001, + TXCMD_RESET_RX_PKT_BUFF = 0xFF900002, + TXCMD_SET_TX_DURATION = 0xFF900003, + TXCMD_SET_RX_RSSI = 0xFF900004, + TXCMD_SET_TX_PWR_TRACKING = 0xFF900005, + TXCMD_XXXX_CTRL, +}DCMD_TXCMD_OP; + +typedef enum{ + NIC_8192U = 1, + NIC_8190P = 2, + NIC_8192E = 3, + NIC_8192SE = 4, + NIC_8192SU = 5, + } nic_t; + +//definded by WB. Ready to fill handlers for different NIC types. +//add handle here when necessary. +struct rtl819x_ops{ + nic_t nic_type; + void (* rtl819x_read_eeprom_info)(struct net_device *dev); + short (* rtl819x_tx)(struct net_device *dev, struct sk_buff* skb); + short (* rtl819x_tx_cmd)(struct net_device *dev, struct sk_buff *skb); + void (* rtl819x_rx_nomal)(struct sk_buff* skb); + void (* rtl819x_rx_cmd)(struct sk_buff *skb); + bool (* rtl819x_adapter_start)(struct net_device *dev); + void (* rtl819x_link_change)(struct net_device *dev); + void (* rtl819x_initial_gain)(struct net_device *dev,u8 Operation); + void (* rtl819x_query_rxdesc_status)(struct sk_buff *skb, struct ieee80211_rx_stats *stats, bool bIsRxAggrSubframe); +}; + +typedef struct r8192_priv +{ + struct rtl819x_ops* ops; + struct usb_device *udev; + //added for maintain info from eeprom + short epromtype; + u16 eeprom_vid; + u16 eeprom_pid; + u8 eeprom_CustomerID; + u8 eeprom_SubCustomerID; + u8 eeprom_ChannelPlan; + RT_CUSTOMER_ID CustomerID; + LED_STRATEGY_8190 LedStrategy; + u8 txqueue_to_outpipemap[9]; + u8 RtOutPipes[16]; + u8 RtInPipes[16]; + u8 ep_in_num; + u8 ep_out_num; + u8 ep_num; + int irq; + struct ieee80211_device *ieee80211; + + short card_8192; /* O: rtl8192, 1:rtl8185 V B/C, 2:rtl8185 V D */ + u8 card_8192_version; /* if TCR reports card V B/C this discriminates */ +// short phy_ver; /* meaningful for rtl8225 1:A 2:B 3:C */ + short enable_gpio0; + enum card_type {PCI,MINIPCI,CARDBUS,USB}card_type; + short hw_plcp_len; + short plcp_preamble_mode; + + spinlock_t irq_lock; +// spinlock_t irq_th_lock; + spinlock_t tx_lock; + spinlock_t ps_lock; +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,16)) + struct semaphore mutex; +#else + struct mutex mutex; +#endif + spinlock_t rf_lock; //used to lock rf write operation added by wb + + u16 irq_mask; +// short irq_enabled; +// struct net_device *dev; //comment this out. + short chan; + short sens; + short max_sens; + + + // u8 chtxpwr[15]; //channels from 1 to 14, 0 not used +// u8 chtxpwr_ofdm[15]; //channels from 1 to 14, 0 not used +// u8 cck_txpwr_base; +// u8 ofdm_txpwr_base; +// u8 challow[15]; //channels from 1 to 14, 0 not used + short up; + short crcmon; //if 1 allow bad crc frame reception in monitor mode +// short prism_hdr; + +// struct timer_list scan_timer; + /*short scanpending; + short stopscan;*/ +// spinlock_t scan_lock; +// u8 active_probe; + //u8 active_scan_num; + struct semaphore wx_sem; + struct semaphore rf_sem; //used to lock rf write operation added by wb, modified by david +// short hw_wep; + +// short digphy; +// short antb; +// short diversity; +// u8 cs_treshold; +// short rcr_csense; + u8 rf_type; //0 means 1T2R, 1 means 2T4R + RT_RF_TYPE_819xU rf_chip; + +// u32 key0[4]; + short (*rf_set_sens)(struct net_device *dev,short sens); + u8 (*rf_set_chan)(struct net_device *dev,u8 ch); + void (*rf_close)(struct net_device *dev); + void (*rf_init)(struct net_device *dev); + //short rate; + short promisc; + /*stats*/ + struct Stats stats; + struct iw_statistics wstats; + struct proc_dir_entry *dir_dev; + + /*RX stuff*/ +// u32 *rxring; +// u32 *rxringtail; +// dma_addr_t rxringdma; + struct urb **rx_urb; + struct urb **rx_cmd_urb; + +/* modified by davad for Rx process */ + struct sk_buff_head rx_queue; + struct sk_buff_head skb_queue; +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)) + struct tq_struct qos_activate; +#else + struct work_struct qos_activate; +#endif + short tx_urb_index; + atomic_t tx_pending[0x10];//UART_PRIORITY+1 + + + struct tasklet_struct irq_rx_tasklet; + struct urb *rxurb_task; + + //2 Tx Related variables + u16 ShortRetryLimit; + u16 LongRetryLimit; + u32 TransmitConfig; + u8 RegCWinMin; // For turbo mode CW adaptive. Added by Annie, 2005-10-27. + + u32 LastRxDescTSFHigh; + u32 LastRxDescTSFLow; + + + //2 Rx Related variables + u16 EarlyRxThreshold; + u32 ReceiveConfig; + u8 AcmControl; + + u8 RFProgType; + + u8 retry_data; + u8 retry_rts; + u16 rts; + + struct ChnlAccessSetting ChannelAccessSetting; +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + struct work_struct reset_wq; +#else + struct tq_struct reset_wq; +#endif + +/**********************************************************/ + //for rtl819xUsb + u16 basic_rate; + u8 short_preamble; + u8 slot_time; + bool bDcut; + bool bCurrentRxAggrEnable; + u8 Rf_Mode; //add for Firmware RF -R/W switch + prt_firmware pFirmware; + rtl819xUsb_loopback_e LoopbackMode; + firmware_source_e firmware_source; + bool usb_error; + + u16 EEPROMTxPowerDiff; + u8 EEPROMThermalMeter; + u8 EEPROMPwDiff; + u8 EEPROMCrystalCap; + u8 EEPROM_Def_Ver; + u8 EEPROMTxPowerLevelCCK;// CCK channel 1~14 + u8 EEPROMTxPowerLevelCCK_V1[3]; + u8 EEPROMTxPowerLevelOFDM24G[3]; // OFDM 2.4G channel 1~14 + u8 EEPROMTxPowerLevelOFDM5G[24]; // OFDM 5G + +//RTL8192SU + bool bDmDisableProtect; + bool bIgnoreDiffRateTxPowerOffset; + +#ifdef EEPROM_OLD_FORMAT_SUPPORT + u8 EEPROMTxPowerLevelCCK24G[14]; // CCK 2.4G channel 1~14 + //u8 EEPROMTxPowerLevelOFDM24G[14]; // OFDM 2.4G channel 1~14 + //u8 EEPROMTxPowerLevelOFDM5G[24]; // OFDM 5G +#else + // For EEPROM TX Power Index like 8190 series + u8 EEPROMRfACCKChnl1TxPwLevel[3]; //RF-A CCK Tx Power Level at channel 7 + u8 EEPROMRfAOfdmChnlTxPwLevel[3];//RF-A CCK Tx Power Level at [0],[1],[2] = channel 1,7,13 + u8 EEPROMRfCCCKChnl1TxPwLevel[3]; //RF-C CCK Tx Power Level at channel 7 + u8 EEPROMRfCOfdmChnlTxPwLevel[3];//RF-C CCK Tx Power Level at [0],[1],[2] = channel 1,7,13 + + // F92S new definition + //RF-A&B CCK/OFDM Tx Power Level at three channel are [1-3] [4-9] [10-14] + u8 RfCckChnlAreaTxPwr[2][3]; + u8 RfOfdmChnlAreaTxPwr1T[2][3]; + u8 RfOfdmChnlAreaTxPwr2T[2][3]; +#endif + + // Add For EEPROM Efuse switch and Efuse Shadow map Setting + bool EepromOrEfuse; + bool bBootFromEfuse; // system boot form EFUSE + u8 EfuseMap[2][HWSET_MAX_SIZE_92S]; + + u8 EEPROMUsbOption; + u8 EEPROMUsbPhyParam[5]; + u8 EEPROMTxPwrBase; + u8 EEPROMBoardType; + bool bBootFromEEPROM; // system boot from EEPROM + u8 EEPROMTSSI_A; + u8 EEPROMTSSI_B; + u8 EEPROMHT2T_TxPwr[6]; // For channel 1, 7 and 13 on path A/B. + u8 EEPROMTxPwrTkMode; + + u8 bTXPowerDataReadFromEEPORM; + + u8 EEPROMVersion; + u8 EEPROMUsbEndPointNumber; + + bool AutoloadFailFlag; + u8 RfTxPwrLevelCck[2][14]; + u8 RfTxPwrLevelOfdm1T[2][14]; + u8 RfTxPwrLevelOfdm2T[2][14]; + // 2009/01/20 MH Add for new EEPROM format. + u8 TxPwrHt20Diff[2][14]; // HT 20<->40 Pwr diff + u8 TxPwrLegacyHtDiff[2][14]; // For HT<->legacy pwr diff + u8 TxPwrbandEdgeHt40[2][2]; // Band edge for HY 40MHZlow/up channel + u8 TxPwrbandEdgeHt20[2][2]; // Band edge for HY 40MHZ low/up channel + u8 TxPwrbandEdgeLegacyOfdm[2][2]; // Band edge for legacy ofdm low/up channel + u8 TxPwrbandEdgeFlag; // Band edge enable flag + + // L1 and L2 high power threshold. + u8 MidHighPwrTHR_L1; + u8 MidHighPwrTHR_L2; + u8 TxPwrSafetyFlag; // for Tx power safety spec +//RTL8192SU + +/*PHY related*/ + BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D + // Read/write are allow for following hardware information variables +#ifdef RTL8192SU + u32 MCSTxPowerLevelOriginalOffset[7];//FIXLZM +#else + u32 MCSTxPowerLevelOriginalOffset[6]; +#endif + u32 CCKTxPowerLevelOriginalOffset; + u8 TxPowerLevelCCK[14]; // CCK channel 1~14 + u8 TxPowerLevelOFDM24G[14]; // OFDM 2.4G channel 1~14 + u8 TxPowerLevelOFDM5G[14]; // OFDM 5G + u32 Pwr_Track; + u8 TxPowerDiff; + u8 AntennaTxPwDiff[2]; // Antenna gain offset, index 0 for B, 1 for C, and 2 for D + u8 CrystalCap; // CrystalCap. + u8 ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 + + u8 CckPwEnl; + // Use to calculate PWBD. + u8 bCckHighPower; + long undecorated_smoothed_pwdb; + + //for set channel + u8 SwChnlInProgress; + u8 SwChnlStage; + u8 SwChnlStep; + u8 SetBWModeInProgress; + HT_CHANNEL_WIDTH CurrentChannelBW; + u8 ChannelPlan; + u8 pwrGroupCnt; + // 8190 40MHz mode + // + u8 nCur40MhzPrimeSC; // Control channel sub-carrier + // Joseph test for shorten RF configuration time. + // We save RF reg0 in this variable to reduce RF reading. + // + u32 RfReg0Value[4]; + u8 NumTotalRFPath; + bool brfpath_rxenable[4]; + //RF set related + bool SetRFPowerStateInProgress; +//+by amy 080507 + struct timer_list watch_dog_timer; + +//+by amy 080515 for dynamic mechenism + //Add by amy Tx Power Control for Near/Far Range 2008/05/15 + bool bdynamic_txpower; //bDynamicTxPower + bool bDynamicTxHighPower; // Tx high power state + bool bDynamicTxLowPower; // Tx low power state + bool bLastDTPFlag_High; + bool bLastDTPFlag_Low; + + bool bstore_last_dtpflag; + bool bstart_txctrl_bydtp; //Define to discriminate on High power State or on sitesuvey to change Tx gain index + //Add by amy for Rate Adaptive + rate_adaptive rate_adaptive; + //Add by amy for TX power tracking + //2008/05/15 Mars OPEN/CLOSE TX POWER TRACKING + txbbgain_struct txbbgain_table[TxBBGainTableLength]; + u8 EEPROMTxPowerTrackEnable; + u8 txpower_count;//For 6 sec do tracking again + bool btxpower_trackingInit; + u8 OFDM_index; + u8 CCK_index; + //2007/09/10 Mars Add CCK TX Power Tracking + ccktxbbgain_struct cck_txbbgain_table[CCKTxBBGainTableLength]; + ccktxbbgain_struct cck_txbbgain_ch14_table[CCKTxBBGainTableLength]; + u8 rfa_txpowertrackingindex; + u8 rfa_txpowertrackingindex_real; + u8 rfa_txpowertracking_default; + u8 rfc_txpowertrackingindex; + u8 rfc_txpowertrackingindex_real; + + s8 cck_present_attentuation; + u8 cck_present_attentuation_20Mdefault; + u8 cck_present_attentuation_40Mdefault; + char cck_present_attentuation_difference; + bool btxpower_tracking; + bool bcck_in_ch14; + bool btxpowerdata_readfromEEPORM; + u16 TSSI_13dBm; + //For Backup Initial Gain + init_gain initgain_backup; + u8 DefaultInitialGain[4]; + // For EDCA Turbo mode, Added by amy 080515. + bool bis_any_nonbepkts; + bool bcurrent_turbo_EDCA; + bool bis_cur_rdlstate; + struct timer_list fsync_timer; + bool bfsync_processing; // 500ms Fsync timer is active or not + u32 rate_record; + u32 rateCountDiffRecord; + u32 ContiuneDiffCount; + bool bswitch_fsync; + + u8 framesync; + u32 framesyncC34; + u8 framesyncMonitor; + //Added by amy 080516 for RX related + u16 nrxAMPDU_size; + u8 nrxAMPDU_aggr_num; + + //by amy for gpio + bool bHwRadioOff; + + //by amy for reset_count + u32 reset_count; + bool bpbc_pressed; + //by amy for debug + u32 txpower_checkcnt; + u32 txpower_tracking_callback_cnt; + u8 thermal_read_val[40]; + u8 thermal_readback_index; + u32 ccktxpower_adjustcnt_not_ch14; + u32 ccktxpower_adjustcnt_ch14; + u8 tx_fwinfo_force_subcarriermode; + u8 tx_fwinfo_force_subcarrierval; + //by amy for silent reset + RESET_TYPE ResetProgress; + bool bForcedSilentReset; + bool bDisableNormalResetCheck; + u16 TxCounter; + u16 RxCounter; + int IrpPendingCount; + bool bResetInProgress; + bool force_reset; + u8 InitialGainOperateType; + + u16 SifsTime; + + //define work item by amy 080526 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + struct delayed_work update_beacon_wq; + struct delayed_work watch_dog_wq; + struct delayed_work txpower_tracking_wq; + struct delayed_work rfpath_check_wq; + struct delayed_work gpio_change_rf_wq; + struct delayed_work initialgain_operate_wq; +#else + struct work_struct update_beacon_wq; + struct work_struct watch_dog_wq; + struct work_struct txpower_tracking_wq; + struct work_struct rfpath_check_wq; + struct work_struct gpio_change_rf_wq; + struct work_struct initialgain_operate_wq; +#endif + struct workqueue_struct *priv_wq; +#else + /* used for periodly scan */ + struct tq_struct update_beacon_wq; + struct tq_struct txpower_tracking_wq; + struct tq_struct rfpath_check_wq; + struct tq_struct watch_dog_wq; + struct tq_struct gpio_change_rf_wq; + struct tq_struct initialgain_operate_wq; +#endif +//#ifdef RTL8192SU + //lzm add for 8192S + u32 IntrMask; + // RF and BB access related synchronization flags. + bool bChangeBBInProgress; // BaseBand RW is still in progress. + bool bChangeRFInProgress; // RF RW is still in progress. + + u32 CCKTxPowerAdjustCntCh14; //debug only + u32 CCKTxPowerAdjustCntNotCh14; //debug only + u32 TXPowerTrackingCallbackCnt; //debug only + u32 TxPowerCheckCnt; //debug only + u32 RFWritePageCnt[3]; //debug only + u32 RFReadPageCnt[3]; //debug only + u8 ThermalReadBackIndex; //debug only + u8 ThermalReadVal[40]; //debug only + + // For HCT test, 2005.07.15, by rcnjko. + // not realize true, just define it, set it 0 default, because some func use it + bool bInHctTest; + + // The current Tx Power Level + u8 CurrentCckTxPwrIdx; + u8 CurrentOfdm24GTxPwrIdx; + + // For pass 92S common phycfg.c compiler + u8 TxPowerLevelCCK_A[14]; // RF-A, CCK channel 1~14 + u8 TxPowerLevelOFDM24G_A[14]; // RF-A, OFDM 2.4G channel 1~14 + u8 TxPowerLevelCCK_C[14]; // RF-C, CCK channel 1~14 + u8 TxPowerLevelOFDM24G_C[14]; // RF-C, OFDM 2.4G channel 1~14 + u8 LegacyHTTxPowerDiff; // Legacy to HT rate power diff + char RF_C_TxPwDiff; // Antenna gain offset, rf-c to rf-a + + bool bRFSiOrPi;//0=si, 1=pi. + //lzm add for 8192S + + bool SetFwCmdInProgress; //is set FW CMD in Progress? 92S only + u8 CurrentFwCmdIO; + + u8 MinSpaceCfg; + + u16 rf_pathmap; +//#endif + + +#ifdef USB_RX_AGGREGATION_SUPPORT + bool bCurrentRxAggrEnable; + bool bForcedUsbRxAggr; + u32 ForcedUsbRxAggrInfo; + u32 LastUsbRxAggrInfoSetting; + u32 RegUsbRxAggrInfo; +#endif + + + +}r8192_priv; + +// for rtl8187 +// now mirging to rtl8187B +/* +typedef enum{ + LOW_PRIORITY = 0x02, + NORM_PRIORITY + } priority_t; +*/ +//for rtl8187B +typedef enum{ + BULK_PRIORITY = 0x01, + //RSVD0, + //RSVD1, + LOW_PRIORITY, + NORM_PRIORITY, + VO_PRIORITY, + VI_PRIORITY, //0x05 + BE_PRIORITY, + BK_PRIORITY, + RSVD2, + RSVD3, + BEACON_PRIORITY, //0x0A + HIGH_PRIORITY, + MANAGE_PRIORITY, + RSVD4, + RSVD5, + UART_PRIORITY //0x0F +} priority_t; + +#if 0 +typedef enum{ + NIC_8192U = 1, + NIC_8190P = 2, + NIC_8192E = 3, + NIC_8192SE = 4, + NIC_8192SU = 5, + } nic_t; +#endif + +#if 0 //defined in Qos.h +//typedef u32 AC_CODING; +#define AC0_BE 0 // ACI: 0x00 // Best Effort +#define AC1_BK 1 // ACI: 0x01 // Background +#define AC2_VI 2 // ACI: 0x10 // Video +#define AC3_VO 3 // ACI: 0x11 // Voice +#define AC_MAX 4 // Max: define total number; Should not to be used as a real enum. + +// +// ECWmin/ECWmax field. +// Ref: WMM spec 2.2.2: WME Parameter Element, p.13. +// +typedef union _ECW{ + u8 charData; + struct + { + u8 ECWmin:4; + u8 ECWmax:4; + }f; // Field +}ECW, *PECW; + +// +// ACI/AIFSN Field. +// Ref: WMM spec 2.2.2: WME Parameter Element, p.12. +// +typedef union _ACI_AIFSN{ + u8 charData; + + struct + { + u8 AIFSN:4; + u8 ACM:1; + u8 ACI:2; + u8 Reserved:1; + }f; // Field +}ACI_AIFSN, *PACI_AIFSN; + +// +// AC Parameters Record Format. +// Ref: WMM spec 2.2.2: WME Parameter Element, p.12. +// +typedef union _AC_PARAM{ + u32 longData; + u8 charData[4]; + + struct + { + ACI_AIFSN AciAifsn; + ECW Ecw; + u16 TXOPLimit; + }f; // Field +}AC_PARAM, *PAC_PARAM; + +#endif +#ifdef JOHN_HWSEC +struct ssid_thread { + struct net_device *dev; + u8 name[IW_ESSID_MAX_SIZE + 1]; +}; +#endif + +#ifdef RTL8192SU +short rtl8192SU_tx_cmd(struct net_device *dev, struct sk_buff *skb); +short rtl8192SU_tx(struct net_device *dev, struct sk_buff* skb); +bool FirmwareDownload92S(struct net_device *dev); +#else +short rtl8192_tx(struct net_device *dev, struct sk_buff* skb); +bool init_firmware(struct net_device *dev); +#endif + +short rtl819xU_tx_cmd(struct net_device *dev, struct sk_buff *skb); +short rtl8192_tx(struct net_device *dev, struct sk_buff* skb); + +u32 read_cam(struct net_device *dev, u8 addr); +void write_cam(struct net_device *dev, u8 addr, u32 data); + +u8 read_nic_byte(struct net_device *dev, int x); +u8 read_nic_byte_E(struct net_device *dev, int x); +u32 read_nic_dword(struct net_device *dev, int x); +u16 read_nic_word(struct net_device *dev, int x) ; +void write_nic_byte(struct net_device *dev, int x,u8 y); +void write_nic_byte_E(struct net_device *dev, int x,u8 y); +void write_nic_word(struct net_device *dev, int x,u16 y); +void write_nic_dword(struct net_device *dev, int x,u32 y); +void force_pci_posting(struct net_device *dev); + +void rtl8192_rtx_disable(struct net_device *); +void rtl8192_rx_enable(struct net_device *); +void rtl8192_tx_enable(struct net_device *); + +void rtl8192_disassociate(struct net_device *dev); +//void fix_rx_fifo(struct net_device *dev); +void rtl8185_set_rf_pins_enable(struct net_device *dev,u32 a); + +void rtl8192_set_anaparam(struct net_device *dev,u32 a); +void rtl8185_set_anaparam2(struct net_device *dev,u32 a); +void rtl8192_update_msr(struct net_device *dev); +int rtl8192_down(struct net_device *dev); +int rtl8192_up(struct net_device *dev); +void rtl8192_commit(struct net_device *dev); +void rtl8192_set_chan(struct net_device *dev,short ch); +void write_phy(struct net_device *dev, u8 adr, u8 data); +void write_phy_cck(struct net_device *dev, u8 adr, u32 data); +void write_phy_ofdm(struct net_device *dev, u8 adr, u32 data); +void rtl8185_tx_antenna(struct net_device *dev, u8 ant); +void rtl8192_set_rxconf(struct net_device *dev); +//short check_nic_enough_desc(struct net_device *dev, priority_t priority); +extern void rtl819xusb_beacon_tx(struct net_device *dev,u16 tx_rate); +void CamResetAllEntry(struct net_device* dev); +void EnableHWSecurityConfig8192(struct net_device *dev); +void setKey(struct net_device *dev, u8 EntryNo, u8 KeyIndex, u16 KeyType, u8 *MacAddr, u8 DefaultKey, u32 *KeyContent ); +short rtl8192_is_tx_queue_empty(struct net_device *dev); + +#endif diff --git a/drivers/staging/rtl8192su/r8192U_core.c b/drivers/staging/rtl8192su/r8192U_core.c new file mode 100644 index 000000000000..f1423d714496 --- /dev/null +++ b/drivers/staging/rtl8192su/r8192U_core.c @@ -0,0 +1,12460 @@ +/****************************************************************************** + * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. + * Linux device driver for RTL8192U + * + * Based on the r8187 driver, which is: + * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al. + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * Jerry chuang <wlanfae@realtek.com> + */ + +#ifndef CONFIG_FORCE_HARD_FLOAT +double __floatsidf (int i) { return i; } +unsigned int __fixunsdfsi (double d) { return d; } +double __adddf3(double a, double b) { return a+b; } +double __addsf3(float a, float b) { return a+b; } +double __subdf3(double a, double b) { return a-b; } +double __extendsfdf2(float a) {return a;} +#endif + +#undef LOOP_TEST +#undef DUMP_RX +#undef DUMP_TX +#undef DEBUG_TX_DESC2 +#undef RX_DONT_PASS_UL +#undef DEBUG_EPROM +#undef DEBUG_RX_VERBOSE +#undef DUMMY_RX +#undef DEBUG_ZERO_RX +#undef DEBUG_RX_SKB +#undef DEBUG_TX_FRAG +#undef DEBUG_RX_FRAG +#undef DEBUG_TX_FILLDESC +#undef DEBUG_TX +#undef DEBUG_IRQ +#undef DEBUG_RX +#undef DEBUG_RXALLOC +#undef DEBUG_REGISTERS +#undef DEBUG_RING +#undef DEBUG_IRQ_TASKLET +#undef DEBUG_TX_ALLOC +#undef DEBUG_TX_DESC + +#define CONFIG_RTL8192_IO_MAP + +#ifdef RTL8192SU +#include <asm/uaccess.h> +#include "r8192U.h" +//#include "r8190_rtl8256.h" /* RTL8225 Radio frontend */ +#include "r8180_93cx6.h" /* Card EEPROM */ +#include "r8192U_wx.h" + +#include "r8192S_rtl8225.h" +#include "r8192S_hw.h" +#include "r8192S_phy.h" +#include "r8192S_phyreg.h" +#include "r8192S_Efuse.h" + +#include "r819xU_cmdpkt.h" +#include "r8192U_dm.h" +//#include "r8192xU_phyreg.h" +#include <linux/usb.h> +// FIXME: check if 2.6.7 is ok +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,7)) +#define usb_kill_urb usb_unlink_urb +#endif + +#ifdef CONFIG_RTL8192_PM +#include "r8192U_pm.h" +#endif + +#ifdef ENABLE_DOT11D +#include "dot11d.h" +#endif + +#else + +#include <asm/uaccess.h> +#include "r8192U_hw.h" +#include "r8192U.h" +#include "r8190_rtl8256.h" /* RTL8225 Radio frontend */ +#include "r8180_93cx6.h" /* Card EEPROM */ +#include "r8192U_wx.h" +#include "r819xU_phy.h" //added by WB 4.30.2008 +#include "r819xU_phyreg.h" +#include "r819xU_cmdpkt.h" +#include "r8192U_dm.h" +//#include "r8192xU_phyreg.h" +#include <linux/usb.h> +// FIXME: check if 2.6.7 is ok +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,7)) +#define usb_kill_urb usb_unlink_urb +#endif + +#ifdef CONFIG_RTL8192_PM +#include "r8192U_pm.h" +#endif + +#ifdef ENABLE_DOT11D +#include "dot11d.h" +#endif + +#endif + + +#ifdef RTL8192SU +u32 rt_global_debug_component = \ +// COMP_TRACE | +// COMP_DBG | +// COMP_INIT | +// COMP_RECV | +// COMP_SEND | +// COMP_IO | + COMP_POWER | +// COMP_EPROM | + COMP_SWBW | + COMP_POWER_TRACKING | + COMP_TURBO | + COMP_QOS | +// COMP_RATE | +// COMP_RM | + COMP_DIG | +// COMP_EFUSE | +// COMP_CH | +// COMP_TXAGC | + COMP_HIPWR | +// COMP_HALDM | + COMP_SEC | + COMP_LED | +// COMP_RF | +// COMP_RXDESC | + COMP_FIRMWARE | + COMP_HT | + COMP_AMSDU | + COMP_SCAN | +// COMP_CMD | + COMP_DOWN | + COMP_RESET | + COMP_ERR; //always open err flags on +#else +//set here to open your trace code. //WB +u32 rt_global_debug_component = \ + // COMP_INIT | +// COMP_DBG | + // COMP_EPROM | +// COMP_PHY | + // COMP_RF | +// COMP_FIRMWARE | +// COMP_CH | + // COMP_POWER_TRACKING | +// COMP_RATE | + // COMP_TXAGC | + // COMP_TRACE | + COMP_DOWN | + // COMP_RECV | + // COMP_SWBW | + COMP_SEC | + // COMP_RESET | + // COMP_SEND | + // COMP_EVENTS | + COMP_ERR ; //always open err flags on +#endif + +#define TOTAL_CAM_ENTRY 32 +#define CAM_CONTENT_COUNT 8 + +static struct usb_device_id rtl8192_usb_id_tbl[] = { + /* Realtek */ + {USB_DEVICE(0x0bda, 0x8192)}, + {USB_DEVICE(0x0bda, 0x8709)}, + /* Corega */ + {USB_DEVICE(0x07aa, 0x0043)}, + /* Belkin */ + {USB_DEVICE(0x050d, 0x805E)}, + /* Sitecom */ + {USB_DEVICE(0x0df6, 0x0031)}, + /* EnGenius */ + {USB_DEVICE(0x1740, 0x9201)}, + /* Dlink */ + {USB_DEVICE(0x2001, 0x3301)}, + /* Zinwell */ + {USB_DEVICE(0x5a57, 0x0290)}, + //92SU + {USB_DEVICE(0x0bda, 0x8172)}, + {} +}; + +MODULE_LICENSE("GPL"); +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) +MODULE_VERSION("V 1.1"); +#endif +MODULE_DEVICE_TABLE(usb, rtl8192_usb_id_tbl); +MODULE_DESCRIPTION("Linux driver for Realtek RTL8192 USB WiFi cards"); + +static char* ifname = "wlan%d"; +#if 0 +static int hwseqnum = 0; +static int hwwep = 0; +#endif +static int hwwep = 1; //default use hw. set 0 to use software security +static int channels = 0x3fff; + + + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 9) +module_param(ifname, charp, S_IRUGO|S_IWUSR ); +//module_param(hwseqnum,int, S_IRUGO|S_IWUSR); +module_param(hwwep,int, S_IRUGO|S_IWUSR); +module_param(channels,int, S_IRUGO|S_IWUSR); +#else +MODULE_PARM(ifname, "s"); +//MODULE_PARM(hwseqnum,"i"); +MODULE_PARM(hwwep,"i"); +MODULE_PARM(channels,"i"); +#endif + +MODULE_PARM_DESC(ifname," Net interface name, wlan%d=default"); +//MODULE_PARM_DESC(hwseqnum," Try to use hardware 802.11 header sequence numbers. Zero=default"); +MODULE_PARM_DESC(hwwep," Try to use hardware security support. "); +MODULE_PARM_DESC(channels," Channel bitmask for specific locales. NYI"); + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) +static int __devinit rtl8192_usb_probe(struct usb_interface *intf, + const struct usb_device_id *id); +static void __devexit rtl8192_usb_disconnect(struct usb_interface *intf); +#else +static void *__devinit rtl8192_usb_probe(struct usb_device *udev,unsigned int ifnum, + const struct usb_device_id *id); +static void __devexit rtl8192_usb_disconnect(struct usb_device *udev, void *ptr); +#endif + + +static struct usb_driver rtl8192_usb_driver = { +#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 15) + .owner = THIS_MODULE, +#endif + .name = RTL819xU_MODULE_NAME, /* Driver name */ + .id_table = rtl8192_usb_id_tbl, /* PCI_ID table */ + .probe = rtl8192_usb_probe, /* probe fn */ + .disconnect = rtl8192_usb_disconnect, /* remove fn */ +#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0) +#ifdef CONFIG_RTL8192_PM + .suspend = rtl8192U_suspend, /* PM suspend fn */ + .resume = rtl8192U_resume, /* PM resume fn */ +#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 22) + .reset_resume = rtl8192U_resume, /* PM reset resume fn */ +#endif +#else + .suspend = NULL, /* PM suspend fn */ + .resume = NULL, /* PM resume fn */ +#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 22) + .reset_resume = NULL, /* PM reset resume fn */ +#endif +#endif +#endif +}; + + +#ifdef RTL8192SU +static void rtl8192SU_read_eeprom_info(struct net_device *dev); +short rtl8192SU_tx(struct net_device *dev, struct sk_buff* skb); +void rtl8192SU_rx_nomal(struct sk_buff* skb); +void rtl8192SU_rx_cmd(struct sk_buff *skb); +bool rtl8192SU_adapter_start(struct net_device *dev); +short rtl8192SU_tx_cmd(struct net_device *dev, struct sk_buff *skb); +void rtl8192SU_link_change(struct net_device *dev); +void InitialGain8192S(struct net_device *dev,u8 Operation); +void rtl8192SU_query_rxdesc_status(struct sk_buff *skb, struct ieee80211_rx_stats *stats, bool bIsRxAggrSubframe); + +struct rtl819x_ops rtl8192su_ops = { + .nic_type = NIC_8192SU, + .rtl819x_read_eeprom_info = rtl8192SU_read_eeprom_info, + .rtl819x_tx = rtl8192SU_tx, + .rtl819x_tx_cmd = rtl8192SU_tx_cmd, + .rtl819x_rx_nomal = rtl8192SU_rx_nomal, + .rtl819x_rx_cmd = rtl8192SU_rx_cmd, + .rtl819x_adapter_start = rtl8192SU_adapter_start, + .rtl819x_link_change = rtl8192SU_link_change, + .rtl819x_initial_gain = InitialGain8192S, + .rtl819x_query_rxdesc_status = rtl8192SU_query_rxdesc_status, +}; +#else +static void rtl8192_read_eeprom_info(struct net_device *dev); +short rtl8192_tx(struct net_device *dev, struct sk_buff* skb); +void rtl8192_rx_nomal(struct sk_buff* skb); +void rtl8192_rx_cmd(struct sk_buff *skb); +bool rtl8192_adapter_start(struct net_device *dev); +short rtl819xU_tx_cmd(struct net_device *dev, struct sk_buff *skb); +void rtl8192_link_change(struct net_device *dev); +void InitialGain819xUsb(struct net_device *dev,u8 Operation); +void query_rxdesc_status(struct sk_buff *skb, struct ieee80211_rx_stats *stats, bool bIsRxAggrSubframe); + +struct rtl819x_ops rtl8192u_ops = { + .nic_type = NIC_8192U, + .rtl819x_read_eeprom_info = rtl8192_read_eeprom_info, + .rtl819x_tx = rtl8192_tx, + .rtl819x_tx_cmd = rtl819xU_tx_cmd, + .rtl819x_rx_nomal = rtl8192_rx_nomal, + .rtl819x_rx_cmd = rtl8192_rx_cmd, + .rtl819x_adapter_start = rtl8192_adapter_start, + .rtl819x_link_change = rtl8192_link_change, + .rtl819x_initial_gain = InitialGain819xUsb, + .rtl819x_query_rxdesc_status = query_rxdesc_status, +}; +#endif + +#ifdef ENABLE_DOT11D + +typedef struct _CHANNEL_LIST +{ + u8 Channel[32]; + u8 Len; +}CHANNEL_LIST, *PCHANNEL_LIST; + +static CHANNEL_LIST ChannelPlan[] = { + {{1,2,3,4,5,6,7,8,9,10,11,36,40,44,48,52,56,60,64,149,153,157,161,165},24}, //FCC + {{1,2,3,4,5,6,7,8,9,10,11},11}, //IC + {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, //ETSI + {{1,2,3,4,5,6,7,8,9,10,11,12,13},13}, //Spain. Change to ETSI. + {{1,2,3,4,5,6,7,8,9,10,11,12,13},13}, //France. Change to ETSI. + {{1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,40,44,48,52,56,60,64},22}, //MKK //MKK + {{1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,40,44,48,52,56,60,64},22},//MKK1 + {{1,2,3,4,5,6,7,8,9,10,11,12,13},13}, //Israel. + {{1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,40,44,48,52,56,60,64},22}, // For 11a , TELEC + {{1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,40,44,48,52,56,60,64}, 22}, //MIC + {{1,2,3,4,5,6,7,8,9,10,11,12,13,14},14} //For Global Domain. 1-11:active scan, 12-14 passive scan. //+YJ, 080626 +}; + +static void rtl819x_set_channel_map(u8 channel_plan, struct r8192_priv* priv) +{ + int i, max_chan=-1, min_chan=-1; + struct ieee80211_device* ieee = priv->ieee80211; + switch (channel_plan) + { + case COUNTRY_CODE_FCC: + case COUNTRY_CODE_IC: + case COUNTRY_CODE_ETSI: + case COUNTRY_CODE_SPAIN: + case COUNTRY_CODE_FRANCE: + case COUNTRY_CODE_MKK: + case COUNTRY_CODE_MKK1: + case COUNTRY_CODE_ISRAEL: + case COUNTRY_CODE_TELEC: + case COUNTRY_CODE_MIC: + { + Dot11d_Init(ieee); + ieee->bGlobalDomain = false; + //acturally 8225 & 8256 rf chip only support B,G,24N mode + if ((priv->rf_chip == RF_8225) || (priv->rf_chip == RF_8256) || (priv->rf_chip == RF_6052)) + { + min_chan = 1; + max_chan = 14; + } + else + { + RT_TRACE(COMP_ERR, "unknown rf chip, can't set channel map in function:%s()\n", __FUNCTION__); + } + if (ChannelPlan[channel_plan].Len != 0){ + // Clear old channel map + memset(GET_DOT11D_INFO(ieee)->channel_map, 0, sizeof(GET_DOT11D_INFO(ieee)->channel_map)); + // Set new channel map + for (i=0;i<ChannelPlan[channel_plan].Len;i++) + { + if (ChannelPlan[channel_plan].Channel[i] < min_chan || ChannelPlan[channel_plan].Channel[i] > max_chan) + break; + GET_DOT11D_INFO(ieee)->channel_map[ChannelPlan[channel_plan].Channel[i]] = 1; + } + } + break; + } + case COUNTRY_CODE_GLOBAL_DOMAIN: + { + GET_DOT11D_INFO(ieee)->bEnabled = 0;//this flag enabled to follow 11d country IE setting, otherwise, it shall follow global domain settings. + Dot11d_Reset(ieee); + ieee->bGlobalDomain = true; + break; + } + default: + break; + } + return; +} +#endif + +#define eqMacAddr(a,b) ( ((a)[0]==(b)[0] && (a)[1]==(b)[1] && (a)[2]==(b)[2] && (a)[3]==(b)[3] && (a)[4]==(b)[4] && (a)[5]==(b)[5]) ? 1:0 ) + +#ifdef RTL8192SU +#define rx_hal_is_cck_rate(_pDesc)\ + ((_pDesc->RxMCS == DESC92S_RATE1M ||\ + _pDesc->RxMCS == DESC92S_RATE2M ||\ + _pDesc->RxMCS == DESC92S_RATE5_5M ||\ + _pDesc->RxMCS == DESC92S_RATE11M) &&\ + !_pDesc->RxHT) + +#define tx_hal_is_cck_rate(_DataRate)\ + ( _DataRate == MGN_1M ||\ + _DataRate == MGN_2M ||\ + _DataRate == MGN_5_5M ||\ + _DataRate == MGN_11M ) + +#else +#define rx_hal_is_cck_rate(_pdrvinfo)\ + ((_pdrvinfo->RxRate == DESC90_RATE1M ||\ + _pdrvinfo->RxRate == DESC90_RATE2M ||\ + _pdrvinfo->RxRate == DESC90_RATE5_5M ||\ + _pdrvinfo->RxRate == DESC90_RATE11M) &&\ + !_pdrvinfo->RxHT) +#endif + + + +void CamResetAllEntry(struct net_device *dev) +{ +#if 1 + u32 ulcommand = 0; + //2004/02/11 In static WEP, OID_ADD_KEY or OID_ADD_WEP are set before STA associate to AP. + // However, ResetKey is called on OID_802_11_INFRASTRUCTURE_MODE and MlmeAssociateRequest + // In this condition, Cam can not be reset because upper layer will not set this static key again. + //if(Adapter->EncAlgorithm == WEP_Encryption) + // return; +//debug + //DbgPrint("========================================\n"); + //DbgPrint(" Call ResetAllEntry \n"); + //DbgPrint("========================================\n\n"); + ulcommand |= BIT31|BIT30; + write_nic_dword(dev, RWCAM, ulcommand); +#else + for(ucIndex=0;ucIndex<TOTAL_CAM_ENTRY;ucIndex++) + CAM_mark_invalid(dev, ucIndex); + for(ucIndex=0;ucIndex<TOTAL_CAM_ENTRY;ucIndex++) + CAM_empty_entry(dev, ucIndex); +#endif + +} + + +void write_cam(struct net_device *dev, u8 addr, u32 data) +{ + write_nic_dword(dev, WCAMI, data); + write_nic_dword(dev, RWCAM, BIT31|BIT16|(addr&0xff) ); +} + +u32 read_cam(struct net_device *dev, u8 addr) +{ + write_nic_dword(dev, RWCAM, 0x80000000|(addr&0xff) ); + return read_nic_dword(dev, 0xa8); +} + +void write_nic_byte_E(struct net_device *dev, int indx, u8 data) +{ + int status; + struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + struct usb_device *udev = priv->udev; + + status = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), + RTL8187_REQ_SET_REGS, RTL8187_REQT_WRITE, + indx|0xfe00, 0, &data, 1, HZ / 2); + + if (status < 0) + { + printk("write_nic_byte_E TimeOut! status:%d\n", status); + } +} + +u8 read_nic_byte_E(struct net_device *dev, int indx) +{ + int status; + u8 data; + struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + struct usb_device *udev = priv->udev; + + status = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), + RTL8187_REQ_GET_REGS, RTL8187_REQT_READ, + indx|0xfe00, 0, &data, 1, HZ / 2); + + if (status < 0) + { + printk("read_nic_byte_E TimeOut! status:%d\n", status); + } + + return data; +} +//as 92U has extend page from 4 to 16, so modify functions below. +void write_nic_byte(struct net_device *dev, int indx, u8 data) +{ + int status; + + struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + struct usb_device *udev = priv->udev; + + status = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), + RTL8187_REQ_SET_REGS, RTL8187_REQT_WRITE, +#ifdef RTL8192SU + indx, 0, &data, 1, HZ / 2); +#else + (indx&0xff)|0xff00, (indx>>8)&0x0f, &data, 1, HZ / 2); +#endif + + if (status < 0) + { + printk("write_nic_byte TimeOut! status:%d\n", status); + } + + +} + + +void write_nic_word(struct net_device *dev, int indx, u16 data) +{ + + int status; + + struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + struct usb_device *udev = priv->udev; + + status = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), + RTL8187_REQ_SET_REGS, RTL8187_REQT_WRITE, +#ifdef RTL8192SU + indx, 0, &data, 2, HZ / 2); +#else + (indx&0xff)|0xff00, (indx>>8)&0x0f, &data, 2, HZ / 2); +#endif + + if (status < 0) + { + printk("write_nic_word TimeOut! status:%d\n", status); + } + +} + + +void write_nic_dword(struct net_device *dev, int indx, u32 data) +{ + + int status; + + struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + struct usb_device *udev = priv->udev; + + status = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), + RTL8187_REQ_SET_REGS, RTL8187_REQT_WRITE, +#ifdef RTL8192SU + indx, 0, &data, 4, HZ / 2); +#else + (indx&0xff)|0xff00, (indx>>8)&0x0f, &data, 4, HZ / 2); +#endif + + + if (status < 0) + { + printk("write_nic_dword TimeOut! status:%d\n", status); + } + +} + + + +u8 read_nic_byte(struct net_device *dev, int indx) +{ + u8 data; + int status; + struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + struct usb_device *udev = priv->udev; + + status = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), + RTL8187_REQ_GET_REGS, RTL8187_REQT_READ, +#ifdef RTL8192SU + indx, 0, &data, 1, HZ / 2); +#else + (indx&0xff)|0xff00, (indx>>8)&0x0f, &data, 1, HZ / 2); +#endif + + if (status < 0) + { + printk("read_nic_byte TimeOut! status:%d\n", status); + } + + return data; +} + + + +u16 read_nic_word(struct net_device *dev, int indx) +{ + u16 data; + int status; + struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + struct usb_device *udev = priv->udev; + + status = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), + RTL8187_REQ_GET_REGS, RTL8187_REQT_READ, +#ifdef RTL8192SU + indx, 0, &data, 2, HZ / 2); +#else + (indx&0xff)|0xff00, (indx>>8)&0x0f, &data, 2, HZ / 2); +#endif + + if (status < 0) + { + printk("read_nic_word TimeOut! status:%d\n", status); + } + + + return data; +} + +u16 read_nic_word_E(struct net_device *dev, int indx) +{ + u16 data; + int status; + struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + struct usb_device *udev = priv->udev; + + status = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), + RTL8187_REQ_GET_REGS, RTL8187_REQT_READ, + indx|0xfe00, 0, &data, 2, HZ / 2); + + if (status < 0) + { + printk("read_nic_word TimeOut! status:%d\n", status); + } + + + return data; +} + +u32 read_nic_dword(struct net_device *dev, int indx) +{ + u32 data; + int status; +// int result; + + struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + struct usb_device *udev = priv->udev; + + status = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), + RTL8187_REQ_GET_REGS, RTL8187_REQT_READ, +#ifdef RTL8192SU + indx, 0, &data, 4, HZ / 2); +#else + (indx&0xff)|0xff00, (indx>>8)&0x0f, &data, 4, HZ / 2); +#endif +// if(0 != result) { +// printk(KERN_WARNING "read size of data = %d\, date = %d\n", result, data); +// } + + if (status < 0) + { + printk("read_nic_dword TimeOut! status:%d\n", status); + if(status == -ENODEV) { + priv->usb_error = true; + } + } + + + + return data; +} + + +//u8 read_phy_cck(struct net_device *dev, u8 adr); +//u8 read_phy_ofdm(struct net_device *dev, u8 adr); +/* this might still called in what was the PHY rtl8185/rtl8192 common code + * plans are to possibilty turn it again in one common code... + */ +inline void force_pci_posting(struct net_device *dev) +{ +} + + +static struct net_device_stats *rtl8192_stats(struct net_device *dev); +void rtl8192_commit(struct net_device *dev); +//void rtl8192_restart(struct net_device *dev); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) +void rtl8192_restart(struct work_struct *work); +//void rtl8192_rq_tx_ack(struct work_struct *work); +#else + void rtl8192_restart(struct net_device *dev); +// //void rtl8192_rq_tx_ack(struct net_device *dev); + #endif + +void watch_dog_timer_callback(unsigned long data); + +/**************************************************************************** + -----------------------------PROCFS STUFF------------------------- +*****************************************************************************/ + +static struct proc_dir_entry *rtl8192_proc = NULL; + + + +static int proc_get_stats_ap(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; + struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + struct ieee80211_device *ieee = priv->ieee80211; + struct ieee80211_network *target; + + int len = 0; + + list_for_each_entry(target, &ieee->network_list, list) { + + len += snprintf(page + len, count - len, + "%s ", target->ssid); + + if(target->wpa_ie_len>0 || target->rsn_ie_len>0){ + len += snprintf(page + len, count - len, + "WPA\n"); + } + else{ + len += snprintf(page + len, count - len, + "non_WPA\n"); + } + + } + + *eof = 1; + return len; +} + +#ifdef RTL8192SU +static int proc_get_registers(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; +// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + + int len = 0; + int i,n,page0,page1,page2; + + int max=0xff; + page0 = 0x000; + page1 = 0x100; + page2 = 0x800; + + /* This dump the current register page */ + if(!IS_BB_REG_OFFSET_92S(page0)){ + len += snprintf(page + len, count - len, + "\n####################page %x##################\n ", (page0>>8)); + for(n=0;n<=max;) + { + len += snprintf(page + len, count - len, + "\nD: %2x > ",n); + for(i=0;i<16 && n<=max;i++,n++) + len += snprintf(page + len, count - len, + "%2.2x ",read_nic_byte(dev,(page0|n))); + } + }else{ + len += snprintf(page + len, count - len, + "\n####################page %x##################\n ", (page0>>8)); + for(n=0;n<=max;) + { + len += snprintf(page + len, count - len, "\nD: %2x > ",n); + for(i=0;i<4 && n<=max;n+=4,i++) + len += snprintf(page + len, count - len, + "%8.8x ",rtl8192_QueryBBReg(dev,(page0|n), bMaskDWord)); + } + } + len += snprintf(page + len, count - len,"\n"); + *eof = 1; + return len; + +} +static int proc_get_registers_1(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; +// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + + int len = 0; + int i,n,page0; + + int max=0xff; + page0 = 0x100; + + /* This dump the current register page */ + len += snprintf(page + len, count - len, + "\n####################page %x##################\n ", (page0>>8)); + for(n=0;n<=max;) + { + len += snprintf(page + len, count - len, + "\nD: %2x > ",n); + for(i=0;i<16 && n<=max;i++,n++) + len += snprintf(page + len, count - len, + "%2.2x ",read_nic_byte(dev,(page0|n))); + } + len += snprintf(page + len, count - len,"\n"); + *eof = 1; + return len; + +} +static int proc_get_registers_2(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; +// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + + int len = 0; + int i,n,page0; + + int max=0xff; + page0 = 0x200; + + /* This dump the current register page */ + len += snprintf(page + len, count - len, + "\n####################page %x##################\n ", (page0>>8)); + for(n=0;n<=max;) + { + len += snprintf(page + len, count - len, + "\nD: %2x > ",n); + for(i=0;i<16 && n<=max;i++,n++) + len += snprintf(page + len, count - len, + "%2.2x ",read_nic_byte(dev,(page0|n))); + } + len += snprintf(page + len, count - len,"\n"); + *eof = 1; + return len; + +} +static int proc_get_registers_8(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; + + int len = 0; + int i,n,page0; + + int max=0xff; + page0 = 0x800; + + /* This dump the current register page */ + len += snprintf(page + len, count - len, + "\n####################page %x##################\n ", (page0>>8)); + for(n=0;n<=max;) + { + len += snprintf(page + len, count - len, "\nD: %2x > ",n); + for(i=0;i<4 && n<=max;n+=4,i++) + len += snprintf(page + len, count - len, + "%8.8x ",rtl8192_QueryBBReg(dev,(page0|n), bMaskDWord)); + } + len += snprintf(page + len, count - len,"\n"); + *eof = 1; + return len; + + } +static int proc_get_registers_9(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; +// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + + int len = 0; + int i,n,page0; + + int max=0xff; + page0 = 0x900; + + /* This dump the current register page */ + len += snprintf(page + len, count - len, + "\n####################page %x##################\n ", (page0>>8)); + for(n=0;n<=max;) + { + len += snprintf(page + len, count - len, "\nD: %2x > ",n); + for(i=0;i<4 && n<=max;n+=4,i++) + len += snprintf(page + len, count - len, + "%8.8x ",rtl8192_QueryBBReg(dev,(page0|n), bMaskDWord)); + } + len += snprintf(page + len, count - len,"\n"); + *eof = 1; + return len; +} +static int proc_get_registers_a(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; +// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + + int len = 0; + int i,n,page0; + + int max=0xff; + page0 = 0xa00; + + /* This dump the current register page */ + len += snprintf(page + len, count - len, + "\n####################page %x##################\n ", (page0>>8)); + for(n=0;n<=max;) + { + len += snprintf(page + len, count - len, "\nD: %2x > ",n); + for(i=0;i<4 && n<=max;n+=4,i++) + len += snprintf(page + len, count - len, + "%8.8x ",rtl8192_QueryBBReg(dev,(page0|n), bMaskDWord)); + } + len += snprintf(page + len, count - len,"\n"); + *eof = 1; + return len; +} +static int proc_get_registers_b(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; +// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + + int len = 0; + int i,n,page0; + + int max=0xff; + page0 = 0xb00; + + /* This dump the current register page */ + len += snprintf(page + len, count - len, + "\n####################page %x##################\n ", (page0>>8)); + for(n=0;n<=max;) + { + len += snprintf(page + len, count - len, "\nD: %2x > ",n); + for(i=0;i<4 && n<=max;n+=4,i++) + len += snprintf(page + len, count - len, + "%8.8x ",rtl8192_QueryBBReg(dev,(page0|n), bMaskDWord)); + } + len += snprintf(page + len, count - len,"\n"); + *eof = 1; + return len; + } +static int proc_get_registers_c(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; +// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + + int len = 0; + int i,n,page0; + + int max=0xff; + page0 = 0xc00; + + /* This dump the current register page */ + len += snprintf(page + len, count - len, + "\n####################page %x##################\n ", (page0>>8)); + for(n=0;n<=max;) + { + len += snprintf(page + len, count - len, "\nD: %2x > ",n); + for(i=0;i<4 && n<=max;n+=4,i++) + len += snprintf(page + len, count - len, + "%8.8x ",rtl8192_QueryBBReg(dev,(page0|n), bMaskDWord)); + } + len += snprintf(page + len, count - len,"\n"); + *eof = 1; + return len; +} +static int proc_get_registers_d(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; +// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + + int len = 0; + int i,n,page0; + + int max=0xff; + page0 = 0xd00; + + /* This dump the current register page */ + len += snprintf(page + len, count - len, + "\n####################page %x##################\n ", (page0>>8)); + for(n=0;n<=max;) + { + len += snprintf(page + len, count - len, "\nD: %2x > ",n); + for(i=0;i<4 && n<=max;n+=4,i++) + len += snprintf(page + len, count - len, + "%8.8x ",rtl8192_QueryBBReg(dev,(page0|n), bMaskDWord)); + } + len += snprintf(page + len, count - len,"\n"); + *eof = 1; + return len; +} +static int proc_get_registers_e(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; +// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + + int len = 0; + int i,n,page0; + + int max=0xff; + page0 = 0xe00; + + /* This dump the current register page */ + len += snprintf(page + len, count - len, + "\n####################page %x##################\n ", (page0>>8)); + for(n=0;n<=max;) + { + len += snprintf(page + len, count - len, "\nD: %2x > ",n); + for(i=0;i<4 && n<=max;n+=4,i++) + len += snprintf(page + len, count - len, + "%8.8x ",rtl8192_QueryBBReg(dev,(page0|n), bMaskDWord)); + } + len += snprintf(page + len, count - len,"\n"); + *eof = 1; + return len; +} +#else +static int proc_get_registers(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; +// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + + int len = 0; + int i,n; + + int max=0xff; + + /* This dump the current register page */ +len += snprintf(page + len, count - len, + "\n####################page 0##################\n "); + + for(n=0;n<=max;) + { + //printk( "\nD: %2x> ", n); + len += snprintf(page + len, count - len, + "\nD: %2x > ",n); + + for(i=0;i<16 && n<=max;i++,n++) + len += snprintf(page + len, count - len, + "%2x ",read_nic_byte(dev,0x000|n)); + + // printk("%2x ",read_nic_byte(dev,n)); + } +#if 1 +len += snprintf(page + len, count - len, + "\n####################page 1##################\n "); + for(n=0;n<=max;) + { + //printk( "\nD: %2x> ", n); + len += snprintf(page + len, count - len, + "\nD: %2x > ",n); + + for(i=0;i<16 && n<=max;i++,n++) + len += snprintf(page + len, count - len, + "%2x ",read_nic_byte(dev,0x100|n)); + + // printk("%2x ",read_nic_byte(dev,n)); + } +len += snprintf(page + len, count - len, + "\n####################page 3##################\n "); + for(n=0;n<=max;) + { + //printk( "\nD: %2x> ", n); + len += snprintf(page + len, count - len, + "\nD: %2x > ",n); + + for(i=0;i<16 && n<=max;i++,n++) + len += snprintf(page + len, count - len, + "%2x ",read_nic_byte(dev,0x300|n)); + + // printk("%2x ",read_nic_byte(dev,n)); + } + +#endif + + len += snprintf(page + len, count - len,"\n"); + *eof = 1; + return len; + +} +#endif + +#if 0 +static int proc_get_cck_reg(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; +// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + + int len = 0; + int i,n; + + int max = 0x5F; + + /* This dump the current register page */ + for(n=0;n<=max;) + { + //printk( "\nD: %2x> ", n); + len += snprintf(page + len, count - len, + "\nD: %2x > ",n); + + for(i=0;i<16 && n<=max;i++,n++) + len += snprintf(page + len, count - len, + "%2x ",read_phy_cck(dev,n)); + + // printk("%2x ",read_nic_byte(dev,n)); + } + len += snprintf(page + len, count - len,"\n"); + + + *eof = 1; + return len; +} + +#endif + +#if 0 +static int proc_get_ofdm_reg(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; +// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + + int len = 0; + int i,n; + + //int max=0xff; + int max = 0x40; + + /* This dump the current register page */ + for(n=0;n<=max;) + { + //printk( "\nD: %2x> ", n); + len += snprintf(page + len, count - len, + "\nD: %2x > ",n); + + for(i=0;i<16 && n<=max;i++,n++) + len += snprintf(page + len, count - len, + "%2x ",read_phy_ofdm(dev,n)); + + // printk("%2x ",read_nic_byte(dev,n)); + } + len += snprintf(page + len, count - len,"\n"); + + + + *eof = 1; + return len; +} + +#endif + +#if 0 +static int proc_get_stats_hw(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; + struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + + int len = 0; + + len += snprintf(page + len, count - len, + "NIC int: %lu\n" + "Total int: %lu\n", + priv->stats.ints, + priv->stats.shints); + + *eof = 1; + return len; +} +#endif + +static int proc_get_stats_tx(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; + struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + + int len = 0; + + len += snprintf(page + len, count - len, + "TX VI priority ok int: %lu\n" + "TX VI priority error int: %lu\n" + "TX VO priority ok int: %lu\n" + "TX VO priority error int: %lu\n" + "TX BE priority ok int: %lu\n" + "TX BE priority error int: %lu\n" + "TX BK priority ok int: %lu\n" + "TX BK priority error int: %lu\n" + "TX MANAGE priority ok int: %lu\n" + "TX MANAGE priority error int: %lu\n" + "TX BEACON priority ok int: %lu\n" + "TX BEACON priority error int: %lu\n" +// "TX high priority ok int: %lu\n" +// "TX high priority failed error int: %lu\n" + "TX queue resume: %lu\n" + "TX queue stopped?: %d\n" + "TX fifo overflow: %lu\n" +// "TX beacon: %lu\n" + "TX VI queue: %d\n" + "TX VO queue: %d\n" + "TX BE queue: %d\n" + "TX BK queue: %d\n" +// "TX HW queue: %d\n" + "TX VI dropped: %lu\n" + "TX VO dropped: %lu\n" + "TX BE dropped: %lu\n" + "TX BK dropped: %lu\n" + "TX total data packets %lu\n", +// "TX beacon aborted: %lu\n", + priv->stats.txviokint, + priv->stats.txvierr, + priv->stats.txvookint, + priv->stats.txvoerr, + priv->stats.txbeokint, + priv->stats.txbeerr, + priv->stats.txbkokint, + priv->stats.txbkerr, + priv->stats.txmanageokint, + priv->stats.txmanageerr, + priv->stats.txbeaconokint, + priv->stats.txbeaconerr, +// priv->stats.txhpokint, +// priv->stats.txhperr, + priv->stats.txresumed, + netif_queue_stopped(dev), + priv->stats.txoverflow, +// priv->stats.txbeacon, + atomic_read(&(priv->tx_pending[VI_PRIORITY])), + atomic_read(&(priv->tx_pending[VO_PRIORITY])), + atomic_read(&(priv->tx_pending[BE_PRIORITY])), + atomic_read(&(priv->tx_pending[BK_PRIORITY])), +// read_nic_byte(dev, TXFIFOCOUNT), + priv->stats.txvidrop, + priv->stats.txvodrop, + priv->stats.txbedrop, + priv->stats.txbkdrop, + priv->stats.txdatapkt +// priv->stats.txbeaconerr + ); + + *eof = 1; + return len; +} + + + +static int proc_get_stats_rx(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; + struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + + int len = 0; + + len += snprintf(page + len, count - len, + "RX packets: %lu\n" + "RX urb status error: %lu\n" + "RX invalid urb error: %lu\n", + priv->stats.rxoktotal, + priv->stats.rxstaterr, + priv->stats.rxurberr); + + *eof = 1; + return len; +} +#if 0 +#if WIRELESS_EXT >= 12 && WIRELESS_EXT < 17 + +static struct iw_statistics *r8192_get_wireless_stats(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + + return &priv->wstats; +} +#endif +#endif +void rtl8192_proc_module_init(void) +{ + RT_TRACE(COMP_INIT, "Initializing proc filesystem"); +#if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) + rtl8192_proc=create_proc_entry(RTL819xU_MODULE_NAME, S_IFDIR, proc_net); +#else + rtl8192_proc=create_proc_entry(RTL819xU_MODULE_NAME, S_IFDIR, init_net.proc_net); +#endif +} + + +void rtl8192_proc_module_remove(void) +{ +#if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) + remove_proc_entry(RTL819xU_MODULE_NAME, proc_net); +#else + remove_proc_entry(RTL819xU_MODULE_NAME, init_net.proc_net); +#endif +} + + +void rtl8192_proc_remove_one(struct net_device *dev) +{ + struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + + + if (priv->dir_dev) { + // remove_proc_entry("stats-hw", priv->dir_dev); + remove_proc_entry("stats-tx", priv->dir_dev); + remove_proc_entry("stats-rx", priv->dir_dev); + // remove_proc_entry("stats-ieee", priv->dir_dev); + remove_proc_entry("stats-ap", priv->dir_dev); + remove_proc_entry("registers", priv->dir_dev); + remove_proc_entry("registers-1", priv->dir_dev); + remove_proc_entry("registers-2", priv->dir_dev); + remove_proc_entry("registers-8", priv->dir_dev); + remove_proc_entry("registers-9", priv->dir_dev); + remove_proc_entry("registers-a", priv->dir_dev); + remove_proc_entry("registers-b", priv->dir_dev); + remove_proc_entry("registers-c", priv->dir_dev); + remove_proc_entry("registers-d", priv->dir_dev); + remove_proc_entry("registers-e", priv->dir_dev); + // remove_proc_entry("cck-registers",priv->dir_dev); + // remove_proc_entry("ofdm-registers",priv->dir_dev); + //remove_proc_entry(dev->name, rtl8192_proc); + remove_proc_entry("wlan0", rtl8192_proc); + priv->dir_dev = NULL; + } +} + + +void rtl8192_proc_init_one(struct net_device *dev) +{ + struct proc_dir_entry *e; + struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + priv->dir_dev = create_proc_entry(dev->name, + S_IFDIR | S_IRUGO | S_IXUGO, + rtl8192_proc); + if (!priv->dir_dev) { + RT_TRACE(COMP_ERR, "Unable to initialize /proc/net/rtl8192/%s\n", + dev->name); + return; + } + #if 0 + e = create_proc_read_entry("stats-hw", S_IFREG | S_IRUGO, + priv->dir_dev, proc_get_stats_hw, dev); + + if (!e) { + DMESGE("Unable to initialize " + "/proc/net/rtl8192/%s/stats-hw\n", + dev->name); + } + #endif + e = create_proc_read_entry("stats-rx", S_IFREG | S_IRUGO, + priv->dir_dev, proc_get_stats_rx, dev); + + if (!e) { + RT_TRACE(COMP_ERR,"Unable to initialize " + "/proc/net/rtl8192/%s/stats-rx\n", + dev->name); + } + + + e = create_proc_read_entry("stats-tx", S_IFREG | S_IRUGO, + priv->dir_dev, proc_get_stats_tx, dev); + + if (!e) { + RT_TRACE(COMP_ERR, "Unable to initialize " + "/proc/net/rtl8192/%s/stats-tx\n", + dev->name); + } + #if 0 + e = create_proc_read_entry("stats-ieee", S_IFREG | S_IRUGO, + priv->dir_dev, proc_get_stats_ieee, dev); + + if (!e) { + DMESGE("Unable to initialize " + "/proc/net/rtl8192/%s/stats-ieee\n", + dev->name); + } + + #endif + + e = create_proc_read_entry("stats-ap", S_IFREG | S_IRUGO, + priv->dir_dev, proc_get_stats_ap, dev); + + if (!e) { + RT_TRACE(COMP_ERR, "Unable to initialize " + "/proc/net/rtl8192/%s/stats-ap\n", + dev->name); + } + + e = create_proc_read_entry("registers", S_IFREG | S_IRUGO, + priv->dir_dev, proc_get_registers, dev); + if (!e) { + RT_TRACE(COMP_ERR, "Unable to initialize " + "/proc/net/rtl8192/%s/registers\n", + dev->name); + } +#ifdef RTL8192SU + e = create_proc_read_entry("registers-1", S_IFREG | S_IRUGO, + priv->dir_dev, proc_get_registers_1, dev); + if (!e) { + RT_TRACE(COMP_ERR, "Unable to initialize " + "/proc/net/rtl8192/%s/registers-1\n", + dev->name); + } + e = create_proc_read_entry("registers-2", S_IFREG | S_IRUGO, + priv->dir_dev, proc_get_registers_2, dev); + if (!e) { + RT_TRACE(COMP_ERR, "Unable to initialize " + "/proc/net/rtl8192/%s/registers-2\n", + dev->name); + } + e = create_proc_read_entry("registers-8", S_IFREG | S_IRUGO, + priv->dir_dev, proc_get_registers_8, dev); + if (!e) { + RT_TRACE(COMP_ERR, "Unable to initialize " + "/proc/net/rtl8192/%s/registers-8\n", + dev->name); + } + e = create_proc_read_entry("registers-9", S_IFREG | S_IRUGO, + priv->dir_dev, proc_get_registers_9, dev); + if (!e) { + RT_TRACE(COMP_ERR, "Unable to initialize " + "/proc/net/rtl8192/%s/registers-9\n", + dev->name); + } + e = create_proc_read_entry("registers-a", S_IFREG | S_IRUGO, + priv->dir_dev, proc_get_registers_a, dev); + if (!e) { + RT_TRACE(COMP_ERR, "Unable to initialize " + "/proc/net/rtl8192/%s/registers-a\n", + dev->name); + } + e = create_proc_read_entry("registers-b", S_IFREG | S_IRUGO, + priv->dir_dev, proc_get_registers_b, dev); + if (!e) { + RT_TRACE(COMP_ERR, "Unable to initialize " + "/proc/net/rtl8192/%s/registers-b\n", + dev->name); + } + e = create_proc_read_entry("registers-c", S_IFREG | S_IRUGO, + priv->dir_dev, proc_get_registers_c, dev); + if (!e) { + RT_TRACE(COMP_ERR, "Unable to initialize " + "/proc/net/rtl8192/%s/registers-c\n", + dev->name); + } + e = create_proc_read_entry("registers-d", S_IFREG | S_IRUGO, + priv->dir_dev, proc_get_registers_d, dev); + if (!e) { + RT_TRACE(COMP_ERR, "Unable to initialize " + "/proc/net/rtl8192/%s/registers-d\n", + dev->name); + } + e = create_proc_read_entry("registers-e", S_IFREG | S_IRUGO, + priv->dir_dev, proc_get_registers_e, dev); + if (!e) { + RT_TRACE(COMP_ERR, "Unable to initialize " + "/proc/net/rtl8192/%s/registers-e\n", + dev->name); + } +#endif +#if 0 + e = create_proc_read_entry("cck-registers", S_IFREG | S_IRUGO, + priv->dir_dev, proc_get_cck_reg, dev); + if (!e) { + RT_TRACE(COMP_ERR, "Unable to initialize " + "/proc/net/rtl8192/%s/cck-registers\n", + dev->name); + } + + e = create_proc_read_entry("ofdm-registers", S_IFREG | S_IRUGO, + priv->dir_dev, proc_get_ofdm_reg, dev); + if (!e) { + RT_TRACE(COMP_ERR, "Unable to initialize " + "/proc/net/rtl8192/%s/ofdm-registers\n", + dev->name); + } +#endif +} +/**************************************************************************** + -----------------------------MISC STUFF------------------------- +*****************************************************************************/ + +/* this is only for debugging */ +void print_buffer(u32 *buffer, int len) +{ + int i; + u8 *buf =(u8*)buffer; + + printk("ASCII BUFFER DUMP (len: %x):\n",len); + + for(i=0;i<len;i++) + printk("%c",buf[i]); + + printk("\nBINARY BUFFER DUMP (len: %x):\n",len); + + for(i=0;i<len;i++) + printk("%x",buf[i]); + + printk("\n"); +} + +//short check_nic_enough_desc(struct net_device *dev, priority_t priority) +short check_nic_enough_desc(struct net_device *dev,int queue_index) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + int used = atomic_read(&priv->tx_pending[queue_index]); + + return (used < MAX_TX_URB); +} + +void tx_timeout(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + //rtl8192_commit(dev); + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) + schedule_work(&priv->reset_wq); +#else + schedule_task(&priv->reset_wq); +#endif + //DMESG("TXTIMEOUT"); +} + + +/* this is only for debug */ +void dump_eprom(struct net_device *dev) +{ + int i; + for(i=0; i<63; i++) + RT_TRACE(COMP_EPROM, "EEPROM addr %x : %x", i, eprom_read(dev,i)); +} + +/* this is only for debug */ +void rtl8192_dump_reg(struct net_device *dev) +{ + int i; + int n; + int max=0x1ff; + + RT_TRACE(COMP_PHY, "Dumping NIC register map"); + + for(n=0;n<=max;) + { + printk( "\nD: %2x> ", n); + for(i=0;i<16 && n<=max;i++,n++) + printk("%2x ",read_nic_byte(dev,n)); + } + printk("\n"); +} + +/**************************************************************************** + ------------------------------HW STUFF--------------------------- +*****************************************************************************/ + +#if 0 +void rtl8192_irq_enable(struct net_device *dev) +{ + struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + //priv->irq_enabled = 1; +/* + write_nic_word(dev,INTA_MASK,INTA_RXOK | INTA_RXDESCERR | INTA_RXOVERFLOW |\ + INTA_TXOVERFLOW | INTA_HIPRIORITYDESCERR | INTA_HIPRIORITYDESCOK |\ + INTA_NORMPRIORITYDESCERR | INTA_NORMPRIORITYDESCOK |\ + INTA_LOWPRIORITYDESCERR | INTA_LOWPRIORITYDESCOK | INTA_TIMEOUT); +*/ + write_nic_word(dev,INTA_MASK, priv->irq_mask); +} + + +void rtl8192_irq_disable(struct net_device *dev) +{ +// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + + write_nic_word(dev,INTA_MASK,0); + force_pci_posting(dev); +// priv->irq_enabled = 0; +} +#endif + +void rtl8192_set_mode(struct net_device *dev,int mode) +{ + u8 ecmd; + ecmd=read_nic_byte(dev, EPROM_CMD); + ecmd=ecmd &~ EPROM_CMD_OPERATING_MODE_MASK; + ecmd=ecmd | (mode<<EPROM_CMD_OPERATING_MODE_SHIFT); + ecmd=ecmd &~ (1<<EPROM_CS_SHIFT); + ecmd=ecmd &~ (1<<EPROM_CK_SHIFT); + write_nic_byte(dev, EPROM_CMD, ecmd); +} + + +void rtl8192_update_msr(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + u8 msr; + + msr = read_nic_byte(dev, MSR); + msr &= ~ MSR_LINK_MASK; + + /* do not change in link_state != WLAN_LINK_ASSOCIATED. + * msr must be updated if the state is ASSOCIATING. + * this is intentional and make sense for ad-hoc and + * master (see the create BSS/IBSS func) + */ + if (priv->ieee80211->state == IEEE80211_LINKED){ + + if (priv->ieee80211->iw_mode == IW_MODE_INFRA) + msr |= (MSR_LINK_MANAGED<<MSR_LINK_SHIFT); + else if (priv->ieee80211->iw_mode == IW_MODE_ADHOC) + msr |= (MSR_LINK_ADHOC<<MSR_LINK_SHIFT); + else if (priv->ieee80211->iw_mode == IW_MODE_MASTER) + msr |= (MSR_LINK_MASTER<<MSR_LINK_SHIFT); + + }else + msr |= (MSR_LINK_NONE<<MSR_LINK_SHIFT); + + write_nic_byte(dev, MSR, msr); +} + +void rtl8192_set_chan(struct net_device *dev,short ch) +{ + struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); +// u32 tx; + RT_TRACE(COMP_CH, "=====>%s()====ch:%d\n", __FUNCTION__, ch); + //printk("=====>%s()====ch:%d\n", __FUNCTION__, ch); + priv->chan=ch; + #if 0 + if(priv->ieee80211->iw_mode == IW_MODE_ADHOC || + priv->ieee80211->iw_mode == IW_MODE_MASTER){ + + priv->ieee80211->link_state = WLAN_LINK_ASSOCIATED; + priv->ieee80211->master_chan = ch; + rtl8192_update_beacon_ch(dev); + } + #endif + + /* this hack should avoid frame TX during channel setting*/ + + +// tx = read_nic_dword(dev,TX_CONF); +// tx &= ~TX_LOOPBACK_MASK; + +#ifndef LOOP_TEST +// write_nic_dword(dev,TX_CONF, tx |( TX_LOOPBACK_MAC<<TX_LOOPBACK_SHIFT)); + + //need to implement rf set channel here WB + + if (priv->rf_set_chan) + priv->rf_set_chan(dev,priv->chan); + mdelay(10); +// write_nic_dword(dev,TX_CONF,tx | (TX_LOOPBACK_NONE<<TX_LOOPBACK_SHIFT)); +#endif +} + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) +static void rtl8192_rx_isr(struct urb *urb, struct pt_regs *regs); +#else +static void rtl8192_rx_isr(struct urb *urb); +#endif +//static void rtl8192_rx_isr(struct urb *rx_urb); + +u32 get_rxpacket_shiftbytes_819xusb(struct ieee80211_rx_stats *pstats) +{ + +#ifdef USB_RX_AGGREGATION_SUPPORT + if (pstats->bisrxaggrsubframe) + return (sizeof(rx_desc_819x_usb) + pstats->RxDrvInfoSize + + pstats->RxBufShift + 8); + else +#endif + return (sizeof(rx_desc_819x_usb) + pstats->RxDrvInfoSize + + pstats->RxBufShift); + +} +static int rtl8192_rx_initiate(struct net_device*dev) +{ + struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + struct urb *entry; + struct sk_buff *skb; + struct rtl8192_rx_info *info; + + /* nomal packet rx procedure */ + while (skb_queue_len(&priv->rx_queue) < MAX_RX_URB) { + skb = __dev_alloc_skb(RX_URB_SIZE, GFP_KERNEL); + if (!skb) + break; +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + entry = usb_alloc_urb(0, GFP_KERNEL); +#else + entry = usb_alloc_urb(0); +#endif + if (!entry) { + kfree_skb(skb); + break; + } +// printk("nomal packet IN request!\n"); + usb_fill_bulk_urb(entry, priv->udev, + usb_rcvbulkpipe(priv->udev, 3), skb->tail, + RX_URB_SIZE, rtl8192_rx_isr, skb); + info = (struct rtl8192_rx_info *) skb->cb; + info->urb = entry; + info->dev = dev; + info->out_pipe = 3; //denote rx normal packet queue + skb_queue_tail(&priv->rx_queue, skb); +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + usb_submit_urb(entry, GFP_KERNEL); +#else + usb_submit_urb(entry); +#endif + } + + /* command packet rx procedure */ + while (skb_queue_len(&priv->rx_queue) < MAX_RX_URB + 3) { +// printk("command packet IN request!\n"); + skb = __dev_alloc_skb(RX_URB_SIZE ,GFP_KERNEL); + if (!skb) + break; +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + entry = usb_alloc_urb(0, GFP_KERNEL); +#else + entry = usb_alloc_urb(0); +#endif + if (!entry) { + kfree_skb(skb); + break; + } + usb_fill_bulk_urb(entry, priv->udev, + usb_rcvbulkpipe(priv->udev, 9), skb->tail, + RX_URB_SIZE, rtl8192_rx_isr, skb); + info = (struct rtl8192_rx_info *) skb->cb; + info->urb = entry; + info->dev = dev; + info->out_pipe = 9; //denote rx cmd packet queue + skb_queue_tail(&priv->rx_queue, skb); +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + usb_submit_urb(entry, GFP_KERNEL); +#else + usb_submit_urb(entry); +#endif + } + + return 0; +} + +void rtl8192_set_rxconf(struct net_device *dev) +{ + struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + u32 rxconf; + + rxconf=read_nic_dword(dev,RCR); + rxconf = rxconf &~ MAC_FILTER_MASK; + rxconf = rxconf | RCR_AMF; + rxconf = rxconf | RCR_ADF; + rxconf = rxconf | RCR_AB; + rxconf = rxconf | RCR_AM; + //rxconf = rxconf | RCR_ACF; + + if (dev->flags & IFF_PROMISC) {DMESG ("NIC in promisc mode");} + + if(priv->ieee80211->iw_mode == IW_MODE_MONITOR || \ + dev->flags & IFF_PROMISC){ + rxconf = rxconf | RCR_AAP; + } /*else if(priv->ieee80211->iw_mode == IW_MODE_MASTER){ + rxconf = rxconf | (1<<ACCEPT_ALLMAC_FRAME_SHIFT); + rxconf = rxconf | (1<<RX_CHECK_BSSID_SHIFT); + }*/else{ + rxconf = rxconf | RCR_APM; + rxconf = rxconf | RCR_CBSSID; + } + + + if(priv->ieee80211->iw_mode == IW_MODE_MONITOR){ + rxconf = rxconf | RCR_AICV; + rxconf = rxconf | RCR_APWRMGT; + } + + if( priv->crcmon == 1 && priv->ieee80211->iw_mode == IW_MODE_MONITOR) + rxconf = rxconf | RCR_ACRC32; + + + rxconf = rxconf &~ RX_FIFO_THRESHOLD_MASK; + rxconf = rxconf | (RX_FIFO_THRESHOLD_NONE<<RX_FIFO_THRESHOLD_SHIFT); + rxconf = rxconf &~ MAX_RX_DMA_MASK; + rxconf = rxconf | ((u32)7<<RCR_MXDMA_OFFSET); + +// rxconf = rxconf | (1<<RX_AUTORESETPHY_SHIFT); + rxconf = rxconf | RCR_ONLYERLPKT; + +// rxconf = rxconf &~ RCR_CS_MASK; +// rxconf = rxconf | (1<<RCR_CS_SHIFT); + + write_nic_dword(dev, RCR, rxconf); + + #ifdef DEBUG_RX + DMESG("rxconf: %x %x",rxconf ,read_nic_dword(dev,RCR)); + #endif +} +//wait to be removed +void rtl8192_rx_enable(struct net_device *dev) +{ + //u8 cmd; + + //struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + + rtl8192_rx_initiate(dev); + +// rtl8192_set_rxconf(dev); +#if 0 + if(NIC_8187 == priv->card_8187) { + cmd=read_nic_byte(dev,CMD); + write_nic_byte(dev,CMD,cmd | (1<<CMD_RX_ENABLE_SHIFT)); + } + else { + //write_nic_dword(dev, RX_CONF, priv->ReceiveConfig); + } +#endif +} + + +void rtl8192_tx_enable(struct net_device *dev) +{ +#if 0 + u8 cmd; + u8 byte; + u32 txconf; + struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + //test loopback + // priv->TransmitConfig |= (TX_LOOPBACK_BASEBAND<<TX_LOOPBACK_SHIFT); + if(NIC_8187B == priv->card_8187){ + write_nic_dword(dev, TX_CONF, priv->TransmitConfig); + byte = read_nic_byte(dev, MSR); + byte |= MSR_LINK_ENEDCA; + write_nic_byte(dev, MSR, byte); + } else { + byte = read_nic_byte(dev,CW_CONF); + byte &= ~(1<<CW_CONF_PERPACKET_CW_SHIFT); + byte &= ~(1<<CW_CONF_PERPACKET_RETRY_SHIFT); + write_nic_byte(dev, CW_CONF, byte); + + byte = read_nic_byte(dev, TX_AGC_CTL); + byte &= ~(1<<TX_AGC_CTL_PERPACKET_GAIN_SHIFT); + byte &= ~(1<<TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT); + byte &= ~(1<<TX_AGC_CTL_FEEDBACK_ANT); + write_nic_byte(dev, TX_AGC_CTL, byte); + + txconf= read_nic_dword(dev,TX_CONF); + + + txconf = txconf &~ TX_LOOPBACK_MASK; + +#ifndef LOOP_TEST + txconf = txconf | (TX_LOOPBACK_NONE<<TX_LOOPBACK_SHIFT); +#else + txconf = txconf | (TX_LOOPBACK_BASEBAND<<TX_LOOPBACK_SHIFT); +#endif + txconf = txconf &~ TCR_SRL_MASK; + txconf = txconf &~ TCR_LRL_MASK; + + txconf = txconf | (priv->retry_data<<TX_LRLRETRY_SHIFT); // long + txconf = txconf | (priv->retry_rts<<TX_SRLRETRY_SHIFT); // short + + txconf = txconf &~ (1<<TX_NOCRC_SHIFT); + + txconf = txconf &~ TCR_MXDMA_MASK; + txconf = txconf | (TCR_MXDMA_2048<<TCR_MXDMA_SHIFT); + + txconf = txconf | TCR_DISReqQsize; + txconf = txconf | TCR_DISCW; + txconf = txconf &~ TCR_SWPLCPLEN; + + txconf=txconf | (1<<TX_NOICV_SHIFT); + + write_nic_dword(dev,TX_CONF,txconf); + +#ifdef DEBUG_TX + DMESG("txconf: %x %x",txconf,read_nic_dword(dev,TX_CONF)); +#endif + + cmd=read_nic_byte(dev,CMD); + write_nic_byte(dev,CMD,cmd | (1<<CMD_TX_ENABLE_SHIFT)); + } +#endif +} + +#if 0 +void rtl8192_beacon_tx_enable(struct net_device *dev) +{ + struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + priv->dma_poll_mask &=~(1<<TX_DMA_STOP_BEACON_SHIFT); + rtl8192_set_mode(dev,EPROM_CMD_CONFIG); + write_nic_byte(dev,TX_DMA_POLLING,priv->dma_poll_mask); + rtl8192_set_mode(dev,EPROM_CMD_NORMAL); +} + + +void rtl8192_ +_disable(struct net_device *dev) +{ + struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + priv->dma_poll_mask |= (1<<TX_DMA_STOP_BEACON_SHIFT); + rtl8192_set_mode(dev,EPROM_CMD_CONFIG); + write_nic_byte(dev,TX_DMA_POLLING,priv->dma_poll_mask); + rtl8192_set_mode(dev,EPROM_CMD_NORMAL); +} + +#endif + + +void rtl8192_rtx_disable(struct net_device *dev) +{ + u8 cmd; + struct r8192_priv *priv = ieee80211_priv(dev); + struct sk_buff *skb; + struct rtl8192_rx_info *info; + + cmd=read_nic_byte(dev,CMDR); + write_nic_byte(dev, CMDR, cmd &~ \ + (CR_TE|CR_RE)); + force_pci_posting(dev); + mdelay(10); + + while ((skb = __skb_dequeue(&priv->rx_queue))) { + info = (struct rtl8192_rx_info *) skb->cb; + if (!info->urb) + continue; + + usb_kill_urb(info->urb); + kfree_skb(skb); + } + + if (skb_queue_len(&priv->skb_queue)) { + printk(KERN_WARNING "skb_queue not empty\n"); + } + + skb_queue_purge(&priv->skb_queue); + return; +} + + +int alloc_tx_beacon_desc_ring(struct net_device *dev, int count) +{ + #if 0 + int i; + u32 *tmp; + struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + + priv->txbeaconring = (u32*)pci_alloc_consistent(priv->pdev, + sizeof(u32)*8*count, + &priv->txbeaconringdma); + if (!priv->txbeaconring) return -1; + for (tmp=priv->txbeaconring,i=0;i<count;i++){ + *tmp = *tmp &~ (1<<31); // descriptor empty, owned by the drv + /* + *(tmp+2) = (u32)dma_tmp; + *(tmp+3) = bufsize; + */ + if(i+1<count) + *(tmp+4) = (u32)priv->txbeaconringdma+((i+1)*8*4); + else + *(tmp+4) = (u32)priv->txbeaconringdma; + + tmp=tmp+8; + } + #endif + return 0; +} + +#if 0 +void rtl8192_reset(struct net_device *dev) +{ + + //struct r8192_priv *priv = ieee80211_priv(dev); + //u8 cr; + + + /* make sure the analog power is on before + * reset, otherwise reset may fail + */ +#if 0 + if(NIC_8187 == priv->card_8187) { + rtl8192_set_anaparam(dev, RTL8225_ANAPARAM_ON); + rtl8185_set_anaparam2(dev, RTL8225_ANAPARAM2_ON); + rtl8192_irq_disable(dev); + mdelay(200); + write_nic_byte_E(dev,0x18,0x10); + write_nic_byte_E(dev,0x18,0x11); + write_nic_byte_E(dev,0x18,0x00); + mdelay(200); + } +#endif + printk("=====>reset?\n"); +#if 0 + cr=read_nic_byte(dev,CMD); + cr = cr & 2; + cr = cr | (1<<CMD_RST_SHIFT); + write_nic_byte(dev,CMD,cr); + + force_pci_posting(dev); + + mdelay(200); + + if(read_nic_byte(dev,CMD) & (1<<CMD_RST_SHIFT)) + RT_TRACE(COMP_ERR, "Card reset timeout!\n"); + else + RT_TRACE(COMP_DOWN, "Card successfully reset\n"); +#endif +#if 0 + if(NIC_8187 == priv->card_8187) { + + printk("This is RTL8187 Reset procedure\n"); + rtl8192_set_mode(dev,EPROM_CMD_LOAD); + force_pci_posting(dev); + mdelay(200); + + /* after the eeprom load cycle, make sure we have + * correct anaparams + */ + rtl8192_set_anaparam(dev, RTL8225_ANAPARAM_ON); + rtl8185_set_anaparam2(dev, RTL8225_ANAPARAM2_ON); + } + else +#endif + printk("This is RTL8187B Reset procedure\n"); + +} +#endif +inline u16 ieeerate2rtlrate(int rate) +{ + switch(rate){ + case 10: + return 0; + case 20: + return 1; + case 55: + return 2; + case 110: + return 3; + case 60: + return 4; + case 90: + return 5; + case 120: + return 6; + case 180: + return 7; + case 240: + return 8; + case 360: + return 9; + case 480: + return 10; + case 540: + return 11; + default: + return 3; + + } +} +static u16 rtl_rate[] = {10,20,55,110,60,90,120,180,240,360,480,540}; +inline u16 rtl8192_rate2rate(short rate) +{ + if (rate >11) return 0; + return rtl_rate[rate]; +} + + +/* The protype of rx_isr has changed since one verion of Linux Kernel */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) +static void rtl8192_rx_isr(struct urb *urb, struct pt_regs *regs) +#else +static void rtl8192_rx_isr(struct urb *urb) +#endif +{ + struct sk_buff *skb = (struct sk_buff *) urb->context; + struct rtl8192_rx_info *info = (struct rtl8192_rx_info *)skb->cb; + struct net_device *dev = info->dev; + struct r8192_priv *priv = ieee80211_priv(dev); + int out_pipe = info->out_pipe; + int err; + if(!priv->up) + return; + if (unlikely(urb->status)) { + info->urb = NULL; + priv->stats.rxstaterr++; + priv->ieee80211->stats.rx_errors++; + usb_free_urb(urb); + // printk("%s():rx status err\n",__FUNCTION__); + return; + } +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,14) + skb_unlink(skb, &priv->rx_queue); +#else + /* + * __skb_unlink before linux2.6.14 does not use spinlock to protect list head. + * add spinlock function manually. john,2008/12/03 + */ + { + unsigned long flags; + spin_lock_irqsave(&(priv->rx_queue.lock), flags); + __skb_unlink(skb,&priv->rx_queue); + spin_unlock_irqrestore(&(priv->rx_queue.lock), flags); + } +#endif + skb_put(skb, urb->actual_length); + + skb_queue_tail(&priv->skb_queue, skb); + tasklet_schedule(&priv->irq_rx_tasklet); + + skb = dev_alloc_skb(RX_URB_SIZE); + if (unlikely(!skb)) { + usb_free_urb(urb); + printk("%s():can,t alloc skb\n",__FUNCTION__); + /* TODO check rx queue length and refill *somewhere* */ + return; + } + + usb_fill_bulk_urb(urb, priv->udev, + usb_rcvbulkpipe(priv->udev, out_pipe), skb->tail, + RX_URB_SIZE, rtl8192_rx_isr, skb); + + info = (struct rtl8192_rx_info *) skb->cb; + info->urb = urb; + info->dev = dev; + info->out_pipe = out_pipe; + + urb->transfer_buffer = skb->tail; + urb->context = skb; + skb_queue_tail(&priv->rx_queue, skb); +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + err = usb_submit_urb(urb, GFP_ATOMIC); +#else + err = usb_submit_urb(urb); +#endif + if(err && err != EPERM) + printk("can not submit rxurb, err is %x,URB status is %x\n",err,urb->status); +} + +u32 +rtl819xusb_rx_command_packet( + struct net_device *dev, + struct ieee80211_rx_stats *pstats + ) +{ + u32 status; + + //RT_TRACE(COMP_RECV, DBG_TRACE, ("---> RxCommandPacketHandle819xUsb()\n")); + + status = cmpk_message_handle_rx(dev, pstats); + if (status) + { + DMESG("rxcommandpackethandle819xusb: It is a command packet\n"); + } + else + { + //RT_TRACE(COMP_RECV, DBG_TRACE, ("RxCommandPacketHandle819xUsb: It is not a command packet\n")); + } + + //RT_TRACE(COMP_RECV, DBG_TRACE, ("<--- RxCommandPacketHandle819xUsb()\n")); + return status; +} + +#if 0 +void rtl8192_tx_queues_stop(struct net_device *dev) +{ + //struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + u8 dma_poll_mask = (1<<TX_DMA_STOP_LOWPRIORITY_SHIFT); + dma_poll_mask |= (1<<TX_DMA_STOP_HIPRIORITY_SHIFT); + dma_poll_mask |= (1<<TX_DMA_STOP_NORMPRIORITY_SHIFT); + dma_poll_mask |= (1<<TX_DMA_STOP_BEACON_SHIFT); + + rtl8192_set_mode(dev,EPROM_CMD_CONFIG); + write_nic_byte(dev,TX_DMA_POLLING,dma_poll_mask); + rtl8192_set_mode(dev,EPROM_CMD_NORMAL); +} +#endif + +void rtl8192_data_hard_stop(struct net_device *dev) +{ + //FIXME !! + #if 0 + struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + priv->dma_poll_mask |= (1<<TX_DMA_STOP_LOWPRIORITY_SHIFT); + rtl8192_set_mode(dev,EPROM_CMD_CONFIG); + write_nic_byte(dev,TX_DMA_POLLING,priv->dma_poll_mask); + rtl8192_set_mode(dev,EPROM_CMD_NORMAL); + #endif +} + + +void rtl8192_data_hard_resume(struct net_device *dev) +{ + // FIXME !! + #if 0 + struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + priv->dma_poll_mask &= ~(1<<TX_DMA_STOP_LOWPRIORITY_SHIFT); + rtl8192_set_mode(dev,EPROM_CMD_CONFIG); + write_nic_byte(dev,TX_DMA_POLLING,priv->dma_poll_mask); + rtl8192_set_mode(dev,EPROM_CMD_NORMAL); + #endif +} + +/* this function TX data frames when the ieee80211 stack requires this. + * It checks also if we need to stop the ieee tx queue, eventually do it + */ +void rtl8192_hard_data_xmit(struct sk_buff *skb, struct net_device *dev, int rate) +{ + struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + int ret; + unsigned long flags; + cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE); + u8 queue_index = tcb_desc->queue_index; + + /* shall not be referred by command packet */ + assert(queue_index != TXCMD_QUEUE); + + spin_lock_irqsave(&priv->tx_lock,flags); + + memcpy((unsigned char *)(skb->cb),&dev,sizeof(dev)); +// tcb_desc->RATRIndex = 7; +// tcb_desc->bTxDisableRateFallBack = 1; +// tcb_desc->bTxUseDriverAssingedRate = 1; + tcb_desc->bTxEnableFwCalcDur = 1; + skb_push(skb, priv->ieee80211->tx_headroom); + ret = priv->ops->rtl819x_tx(dev, skb); + + //priv->ieee80211->stats.tx_bytes+=(skb->len - priv->ieee80211->tx_headroom); + //priv->ieee80211->stats.tx_packets++; + + spin_unlock_irqrestore(&priv->tx_lock,flags); + +// return ret; + return; +} + +/* This is a rough attempt to TX a frame + * This is called by the ieee 80211 stack to TX management frames. + * If the ring is full packet are dropped (for data frame the queue + * is stopped before this can happen). + */ +int rtl8192_hard_start_xmit(struct sk_buff *skb,struct net_device *dev) +{ + struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + int ret; + unsigned long flags; + cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE); + u8 queue_index = tcb_desc->queue_index; + + + spin_lock_irqsave(&priv->tx_lock,flags); + + memcpy((unsigned char *)(skb->cb),&dev,sizeof(dev)); + if(queue_index == TXCMD_QUEUE) { + skb_push(skb, USB_HWDESC_HEADER_LEN); + priv->ops->rtl819x_tx_cmd(dev, skb); + ret = 1; + spin_unlock_irqrestore(&priv->tx_lock,flags); + return ret; + } else { + skb_push(skb, priv->ieee80211->tx_headroom); + ret = priv->ops->rtl819x_tx(dev, skb); + } + + spin_unlock_irqrestore(&priv->tx_lock,flags); + + return ret; +} + + +void rtl8192_try_wake_queue(struct net_device *dev, int pri); + +#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE +u16 DrvAggr_PaddingAdd(struct net_device *dev, struct sk_buff *skb) +{ + u16 PaddingNum = 256 - ((skb->len + TX_PACKET_DRVAGGR_SUBFRAME_SHIFT_BYTES) % 256); + return (PaddingNum&0xff); +} + +u8 MRateToHwRate8190Pci(u8 rate); +u8 QueryIsShort(u8 TxHT, u8 TxRate, cb_desc *tcb_desc); +u8 MapHwQueueToFirmwareQueue(u8 QueueID); +struct sk_buff *DrvAggr_Aggregation(struct net_device *dev, struct ieee80211_drv_agg_txb *pSendList) +{ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) + struct ieee80211_device *ieee = netdev_priv(dev); +#else + struct ieee80211_device *ieee = (struct ieee80211_device *)dev->priv; +#endif + struct r8192_priv *priv = ieee80211_priv(dev); + cb_desc *tcb_desc = NULL; + u8 i; + u32 TotalLength; + struct sk_buff *skb; + struct sk_buff *agg_skb; + tx_desc_819x_usb_aggr_subframe *tx_agg_desc = NULL; + tx_fwinfo_819x_usb *tx_fwinfo = NULL; + + // + // Local variable initialization. + // + /* first skb initialization */ + skb = pSendList->tx_agg_frames[0]; + TotalLength = skb->len; + + /* Get the total aggregation length including the padding space and + * sub frame header. + */ + for(i = 1; i < pSendList->nr_drv_agg_frames; i++) { + TotalLength += DrvAggr_PaddingAdd(dev, skb); + skb = pSendList->tx_agg_frames[i]; + TotalLength += (skb->len + TX_PACKET_DRVAGGR_SUBFRAME_SHIFT_BYTES); + } + + /* allocate skb to contain the aggregated packets */ + agg_skb = dev_alloc_skb(TotalLength + ieee->tx_headroom); + memset(agg_skb->data, 0, agg_skb->len); + skb_reserve(agg_skb, ieee->tx_headroom); + +// RT_DEBUG_DATA(COMP_SEND, skb->cb, sizeof(skb->cb)); + /* reserve info for first subframe Tx descriptor to be set in the tx function */ + skb = pSendList->tx_agg_frames[0]; + tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE); + tcb_desc->drv_agg_enable = 1; + tcb_desc->pkt_size = skb->len; + tcb_desc->DrvAggrNum = pSendList->nr_drv_agg_frames; + printk("DrvAggNum = %d\n", tcb_desc->DrvAggrNum); +// RT_DEBUG_DATA(COMP_SEND, skb->cb, sizeof(skb->cb)); +// printk("========>skb->data ======> \n"); +// RT_DEBUG_DATA(COMP_SEND, skb->data, skb->len); + memcpy(agg_skb->cb, skb->cb, sizeof(skb->cb)); + memcpy(skb_put(agg_skb,skb->len),skb->data,skb->len); + + for(i = 1; i < pSendList->nr_drv_agg_frames; i++) { + /* push the next sub frame to be 256 byte aline */ + skb_put(agg_skb,DrvAggr_PaddingAdd(dev,skb)); + + /* Subframe drv Tx descriptor and firmware info setting */ + skb = pSendList->tx_agg_frames[i]; + tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE); + tx_agg_desc = (tx_desc_819x_usb_aggr_subframe *)agg_skb->tail; + tx_fwinfo = (tx_fwinfo_819x_usb *)(agg_skb->tail + sizeof(tx_desc_819x_usb_aggr_subframe)); + + memset(tx_fwinfo,0,sizeof(tx_fwinfo_819x_usb)); + /* DWORD 0 */ + tx_fwinfo->TxHT = (tcb_desc->data_rate&0x80)?1:0; + tx_fwinfo->TxRate = MRateToHwRate8190Pci(tcb_desc->data_rate); + tx_fwinfo->EnableCPUDur = tcb_desc->bTxEnableFwCalcDur; + tx_fwinfo->Short = QueryIsShort(tx_fwinfo->TxHT, tx_fwinfo->TxRate, tcb_desc); + if(tcb_desc->bAMPDUEnable) {//AMPDU enabled + tx_fwinfo->AllowAggregation = 1; + /* DWORD 1 */ + tx_fwinfo->RxMF = tcb_desc->ampdu_factor; + tx_fwinfo->RxAMD = tcb_desc->ampdu_density&0x07;//ampdudensity + } else { + tx_fwinfo->AllowAggregation = 0; + /* DWORD 1 */ + tx_fwinfo->RxMF = 0; + tx_fwinfo->RxAMD = 0; + } + + /* Protection mode related */ + tx_fwinfo->RtsEnable = (tcb_desc->bRTSEnable)?1:0; + tx_fwinfo->CtsEnable = (tcb_desc->bCTSEnable)?1:0; + tx_fwinfo->RtsSTBC = (tcb_desc->bRTSSTBC)?1:0; + tx_fwinfo->RtsHT = (tcb_desc->rts_rate&0x80)?1:0; + tx_fwinfo->RtsRate = MRateToHwRate8190Pci((u8)tcb_desc->rts_rate); + tx_fwinfo->RtsSubcarrier = (tx_fwinfo->RtsHT==0)?(tcb_desc->RTSSC):0; + tx_fwinfo->RtsBandwidth = (tx_fwinfo->RtsHT==1)?((tcb_desc->bRTSBW)?1:0):0; + tx_fwinfo->RtsShort = (tx_fwinfo->RtsHT==0)?(tcb_desc->bRTSUseShortPreamble?1:0):\ + (tcb_desc->bRTSUseShortGI?1:0); + + /* Set Bandwidth and sub-channel settings. */ + if(priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) + { + if(tcb_desc->bPacketBW) { + tx_fwinfo->TxBandwidth = 1; + tx_fwinfo->TxSubCarrier = 0; //By SD3's Jerry suggestion, use duplicated mode + } else { + tx_fwinfo->TxBandwidth = 0; + tx_fwinfo->TxSubCarrier = priv->nCur40MhzPrimeSC; + } + } else { + tx_fwinfo->TxBandwidth = 0; + tx_fwinfo->TxSubCarrier = 0; + } + + /* Fill Tx descriptor */ + memset(tx_agg_desc, 0, sizeof(tx_desc_819x_usb_aggr_subframe)); + /* DWORD 0 */ + //tx_agg_desc->LINIP = 0; + //tx_agg_desc->CmdInit = 1; + tx_agg_desc->Offset = sizeof(tx_fwinfo_819x_usb) + 8; + /* already raw data, need not to substract header length */ + tx_agg_desc->PktSize = skb->len & 0xffff; + + /*DWORD 1*/ + tx_agg_desc->SecCAMID= 0; + tx_agg_desc->RATid = tcb_desc->RATRIndex; +#if 0 + /* Fill security related */ + if( pTcb->bEncrypt && !Adapter->MgntInfo.SecurityInfo.SWTxEncryptFlag) + { + EncAlg = SecGetEncryptionOverhead( + Adapter, + &EncryptionMPDUHeadOverhead, + &EncryptionMPDUTailOverhead, + NULL, + NULL, + FALSE, + FALSE); + //2004/07/22, kcwu, EncryptionMPDUHeadOverhead has been added in previous code + //MPDUOverhead = EncryptionMPDUHeadOverhead + EncryptionMPDUTailOverhead; + MPDUOverhead = EncryptionMPDUTailOverhead; + tx_agg_desc->NoEnc = 0; + RT_TRACE(COMP_SEC, DBG_LOUD, ("******We in the loop SecCAMID is %d SecDescAssign is %d The Sec is %d********\n",tx_agg_desc->SecCAMID,tx_agg_desc->SecDescAssign,EncAlg)); + //CamDumpAll(Adapter); + } + else +#endif + { + //MPDUOverhead = 0; + tx_agg_desc->NoEnc = 1; + } +#if 0 + switch(EncAlg){ + case NO_Encryption: + tx_agg_desc->SecType = 0x0; + break; + case WEP40_Encryption: + case WEP104_Encryption: + tx_agg_desc->SecType = 0x1; + break; + case TKIP_Encryption: + tx_agg_desc->SecType = 0x2; + break; + case AESCCMP_Encryption: + tx_agg_desc->SecType = 0x3; + break; + default: + tx_agg_desc->SecType = 0x0; + break; + } +#else + tx_agg_desc->SecType = 0x0; +#endif + + if (tcb_desc->bHwSec) { + switch (priv->ieee80211->pairwise_key_type) + { + case KEY_TYPE_WEP40: + case KEY_TYPE_WEP104: + tx_agg_desc->SecType = 0x1; + tx_agg_desc->NoEnc = 0; + break; + case KEY_TYPE_TKIP: + tx_agg_desc->SecType = 0x2; + tx_agg_desc->NoEnc = 0; + break; + case KEY_TYPE_CCMP: + tx_agg_desc->SecType = 0x3; + tx_agg_desc->NoEnc = 0; + break; + case KEY_TYPE_NA: + tx_agg_desc->SecType = 0x0; + tx_agg_desc->NoEnc = 1; + break; + } + } + + tx_agg_desc->QueueSelect = MapHwQueueToFirmwareQueue(tcb_desc->queue_index); + tx_agg_desc->TxFWInfoSize = sizeof(tx_fwinfo_819x_usb); + + tx_agg_desc->DISFB = tcb_desc->bTxDisableRateFallBack; + tx_agg_desc->USERATE = tcb_desc->bTxUseDriverAssingedRate; + + tx_agg_desc->OWN = 1; + + //DWORD 2 + /* According windows driver, it seems that there no need to fill this field */ + //tx_agg_desc->TxBufferSize= (u32)(skb->len - USB_HWDESC_HEADER_LEN); + + /* to fill next packet */ + skb_put(agg_skb,TX_PACKET_DRVAGGR_SUBFRAME_SHIFT_BYTES); + memcpy(skb_put(agg_skb,skb->len),skb->data,skb->len); + } + + for(i = 0; i < pSendList->nr_drv_agg_frames; i++) { + dev_kfree_skb_any(pSendList->tx_agg_frames[i]); + } + + return agg_skb; +} + +/* NOTE: + This function return a list of PTCB which is proper to be aggregate with the input TCB. + If no proper TCB is found to do aggregation, SendList will only contain the input TCB. +*/ +u8 DrvAggr_GetAggregatibleList(struct net_device *dev, struct sk_buff *skb, + struct ieee80211_drv_agg_txb *pSendList) +{ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) + struct ieee80211_device *ieee = netdev_priv(dev); +#else + struct ieee80211_device *ieee = (struct ieee80211_device *)dev->priv; +#endif + PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo; + u16 nMaxAggrNum = pHTInfo->UsbTxAggrNum; + cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE); + u8 QueueID = tcb_desc->queue_index; + + do { + pSendList->tx_agg_frames[pSendList->nr_drv_agg_frames++] = skb; + if(pSendList->nr_drv_agg_frames >= nMaxAggrNum) { + break; + } + + } while((skb = skb_dequeue(&ieee->skb_drv_aggQ[QueueID]))); + + RT_TRACE(COMP_AMSDU, "DrvAggr_GetAggregatibleList, nAggrTcbNum = %d \n", pSendList->nr_drv_agg_frames); + return pSendList->nr_drv_agg_frames; +} +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) +static void rtl8192_tx_isr(struct urb *tx_urb, struct pt_regs *reg) +#else +static void rtl8192_tx_isr(struct urb *tx_urb) +#endif +{ + struct sk_buff *skb = (struct sk_buff*)tx_urb->context; + struct net_device *dev = NULL; + struct r8192_priv *priv = NULL; + cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE); + u8 queue_index = tcb_desc->queue_index; +// bool bToSend0Byte; +// u16 BufLen = skb->len; + + memcpy(&dev,(struct net_device*)(skb->cb),sizeof(struct net_device*)); + priv = ieee80211_priv(dev); + + if(tcb_desc->queue_index != TXCMD_QUEUE) { + if(tx_urb->status == 0) { + // dev->trans_start = jiffies; + // As act as station mode, destion shall be unicast address. + //priv->ieee80211->stats.tx_bytes+=(skb->len - priv->ieee80211->tx_headroom); + //priv->ieee80211->stats.tx_packets++; + priv->stats.txoktotal++; + priv->ieee80211->LinkDetectInfo.NumTxOkInPeriod++; + priv->stats.txbytesunicast += (skb->len - priv->ieee80211->tx_headroom); + } else { + priv->ieee80211->stats.tx_errors++; + //priv->stats.txmanageerr++; + /* TODO */ + } + } + + /* free skb and tx_urb */ + if(skb != NULL) { + dev_kfree_skb_any(skb); + usb_free_urb(tx_urb); + atomic_dec(&priv->tx_pending[queue_index]); + } + +#if 0 //we need to send zero byte packet just after 512 byte(64 byte)packet is transmitted, or we will halt. It will greatly reduced available page in FW, and ruin our throughput. WB 2008.08.27 + if(BufLen > 0 && ((BufLen % 512 == 0)||(BufLen % 64 == 0))) { + bToSend0Byte = true; + } + + bToSend0Byte = false; + // + // Note that, we at most handle 1 MPDU to send here, either + // fragment or MPDU in wait queue. + // + if(!bToSend0Byte) +#endif + { + // + // Handle HW Beacon: + // We had transfer our beacon frame to host controler at this moment. + // +#if 0 + if(tcb_desc->tx_queue == BEACON_QUEUE) + { + priv->bSendingBeacon = FALSE; + } +#endif + // + // Caution: + // Handling the wait queue of command packets. + // For Tx command packets, we must not do TCB fragment because it is not handled right now. + // We must cut the packets to match the size of TX_CMD_PKT before we send it. + // + if (queue_index == MGNT_QUEUE){ + if (priv->ieee80211->ack_tx_to_ieee){ + if (rtl8192_is_tx_queue_empty(dev)){ + priv->ieee80211->ack_tx_to_ieee = 0; + ieee80211_ps_tx_ack(priv->ieee80211, 1); + } + } + } + /* Handle MPDU in wait queue. */ + if(queue_index != BEACON_QUEUE) { + /* Don't send data frame during scanning.*/ + if((skb_queue_len(&priv->ieee80211->skb_waitQ[queue_index]) != 0)&&\ + (!(priv->ieee80211->queue_stop))) { + if(NULL != (skb = skb_dequeue(&(priv->ieee80211->skb_waitQ[queue_index])))) + priv->ieee80211->softmac_hard_start_xmit(skb, dev); + + return; //modified by david to avoid further processing AMSDU + } +#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE + else if ((skb_queue_len(&priv->ieee80211->skb_drv_aggQ[queue_index])!= 0)&&\ + (!(priv->ieee80211->queue_stop))) { + // Tx Driver Aggregation process + /* The driver will aggregation the packets according to the following stets + * 1. check whether there's tx irq available, for it's a completion return + * function, it should contain enough tx irq; + * 2. check pakcet type; + * 3. intialize sendlist, check whether the to-be send packet no greater than 1 + * 4. aggregation the packets, and fill firmware info and tx desc to it, etc. + * 5. check whehter the packet could be sent, otherwise just insert to wait head + * */ + skb = skb_dequeue(&priv->ieee80211->skb_drv_aggQ[queue_index]); + if(!check_nic_enough_desc(dev, queue_index)) { + skb_queue_head(&(priv->ieee80211->skb_drv_aggQ[queue_index]), skb); + return; + } + + { + /*TODO*/ + /* + u8* pHeader = skb->data; + + if(IsMgntQosData(pHeader) || + IsMgntQData_Ack(pHeader) || + IsMgntQData_Poll(pHeader) || + IsMgntQData_Poll_Ack(pHeader) + ) + */ + { + struct ieee80211_drv_agg_txb SendList; + + memset(&SendList, 0, sizeof(struct ieee80211_drv_agg_txb)); + if(DrvAggr_GetAggregatibleList(dev, skb, &SendList) > 1) { + skb = DrvAggr_Aggregation(dev, &SendList); + +#if 0 + printk("=============>to send aggregated packet!\n"); + RT_DEBUG_DATA(COMP_SEND, skb->cb, sizeof(skb->cb)); + printk("\n=================skb->len = %d\n", skb->len); + RT_DEBUG_DATA(COMP_SEND, skb->data, skb->len); +#endif + } + } + priv->ieee80211->softmac_hard_start_xmit(skb, dev); + } + } +#endif + } + } + +#if 0 + else + { + RT_TRACE( COMP_SEND,"HalUsbOutComplete(%d): bToSend0Byte.\n", PipeIndex); + + // + // In this case, we don't return skb now. + // It will be returned when the 0-byte request completed. + // + + // + // Bulk out an 0-byte padding transfer. + // + HalUsbOut0Byte(pAdapter, PipeIndex, skb); + } + +#endif +} + +void rtl8192_beacon_stop(struct net_device *dev) +{ + u8 msr, msrm, msr2; + struct r8192_priv *priv = ieee80211_priv(dev); + + msr = read_nic_byte(dev, MSR); + msrm = msr & MSR_LINK_MASK; + msr2 = msr & ~MSR_LINK_MASK; + + if(NIC_8192U == priv->card_8192) { + usb_kill_urb(priv->rx_urb[MAX_RX_URB]); + } + if ((msrm == (MSR_LINK_ADHOC<<MSR_LINK_SHIFT) || + (msrm == (MSR_LINK_MASTER<<MSR_LINK_SHIFT)))){ + write_nic_byte(dev, MSR, msr2 | MSR_LINK_NONE); + write_nic_byte(dev, MSR, msr); + } +} + +void rtl8192_config_rate(struct net_device* dev, u16* rate_config) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + struct ieee80211_network *net; + u8 i=0, basic_rate = 0; + net = & priv->ieee80211->current_network; + + for (i=0; i<net->rates_len; i++) + { + basic_rate = net->rates[i]&0x7f; + switch(basic_rate) + { + case MGN_1M: *rate_config |= RRSR_1M; break; + case MGN_2M: *rate_config |= RRSR_2M; break; + case MGN_5_5M: *rate_config |= RRSR_5_5M; break; + case MGN_11M: *rate_config |= RRSR_11M; break; + case MGN_6M: *rate_config |= RRSR_6M; break; + case MGN_9M: *rate_config |= RRSR_9M; break; + case MGN_12M: *rate_config |= RRSR_12M; break; + case MGN_18M: *rate_config |= RRSR_18M; break; + case MGN_24M: *rate_config |= RRSR_24M; break; + case MGN_36M: *rate_config |= RRSR_36M; break; + case MGN_48M: *rate_config |= RRSR_48M; break; + case MGN_54M: *rate_config |= RRSR_54M; break; + } + } + for (i=0; i<net->rates_ex_len; i++) + { + basic_rate = net->rates_ex[i]&0x7f; + switch(basic_rate) + { + case MGN_1M: *rate_config |= RRSR_1M; break; + case MGN_2M: *rate_config |= RRSR_2M; break; + case MGN_5_5M: *rate_config |= RRSR_5_5M; break; + case MGN_11M: *rate_config |= RRSR_11M; break; + case MGN_6M: *rate_config |= RRSR_6M; break; + case MGN_9M: *rate_config |= RRSR_9M; break; + case MGN_12M: *rate_config |= RRSR_12M; break; + case MGN_18M: *rate_config |= RRSR_18M; break; + case MGN_24M: *rate_config |= RRSR_24M; break; + case MGN_36M: *rate_config |= RRSR_36M; break; + case MGN_48M: *rate_config |= RRSR_48M; break; + case MGN_54M: *rate_config |= RRSR_54M; break; + } + } +} + + +#define SHORT_SLOT_TIME 9 +#define NON_SHORT_SLOT_TIME 20 + +void rtl8192_update_cap(struct net_device* dev, u16 cap) +{ + //u32 tmp = 0; + struct r8192_priv *priv = ieee80211_priv(dev); + struct ieee80211_network *net = &priv->ieee80211->current_network; + priv->short_preamble = cap & WLAN_CAPABILITY_SHORT_PREAMBLE; + + //LZM MOD 090303 HW_VAR_ACK_PREAMBLE +#ifdef RTL8192SU + if(0) + { + u8 tmp = 0; + tmp = ((priv->nCur40MhzPrimeSC) << 5); + if (priv->short_preamble) + tmp |= 0x80; + write_nic_byte(dev, RRSR+2, tmp); + } +#else + { + u32 tmp = 0; + tmp = priv->basic_rate; + if (priv->short_preamble) + tmp |= BRSR_AckShortPmb; + write_nic_dword(dev, RRSR, tmp); + } +#endif + + if (net->mode & (IEEE_G|IEEE_N_24G)) + { + u8 slot_time = 0; + if ((cap & WLAN_CAPABILITY_SHORT_SLOT)&&(!priv->ieee80211->pHTInfo->bCurrentRT2RTLongSlotTime)) + {//short slot time + slot_time = SHORT_SLOT_TIME; + } + else //long slot time + slot_time = NON_SHORT_SLOT_TIME; + priv->slot_time = slot_time; + write_nic_byte(dev, SLOT_TIME, slot_time); + } + +} +void rtl8192_net_update(struct net_device *dev) +{ + + struct r8192_priv *priv = ieee80211_priv(dev); + struct ieee80211_network *net; + u16 BcnTimeCfg = 0, BcnCW = 6, BcnIFS = 0xf; + u16 rate_config = 0; + net = & priv->ieee80211->current_network; + + rtl8192_config_rate(dev, &rate_config); + priv->basic_rate = rate_config &= 0x15f; + + write_nic_dword(dev,BSSIDR,((u32*)net->bssid)[0]); + write_nic_word(dev,BSSIDR+4,((u16*)net->bssid)[2]); + //for(i=0;i<ETH_ALEN;i++) + // write_nic_byte(dev,BSSID+i,net->bssid[i]); + + rtl8192_update_msr(dev); +// rtl8192_update_cap(dev, net->capability); + if (priv->ieee80211->iw_mode == IW_MODE_ADHOC) + { + write_nic_word(dev, ATIMWND, 2); + write_nic_word(dev, BCN_DMATIME, 1023); + write_nic_word(dev, BCN_INTERVAL, net->beacon_interval); +// write_nic_word(dev, BcnIntTime, 100); + write_nic_word(dev, BCN_DRV_EARLY_INT, 1); + write_nic_byte(dev, BCN_ERR_THRESH, 100); + BcnTimeCfg |= (BcnCW<<BCN_TCFG_CW_SHIFT); + // TODO: BcnIFS may required to be changed on ASIC + BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS; + + write_nic_word(dev, BCN_TCFG, BcnTimeCfg); + } + + + +} + +//temporary hw beacon is not used any more. +//open it when necessary +#if 1 +void rtl819xusb_beacon_tx(struct net_device *dev,u16 tx_rate) +{ + +#if 0 + struct r8192_priv *priv = ieee80211_priv(dev); + struct sk_buff *skb; + int i = 0; + //u8 cr; + + rtl8192_net_update(dev); + + skb = ieee80211_get_beacon(priv->ieee80211); + if(!skb){ + DMESG("not enought memory for allocating beacon"); + return; + } + + + write_nic_byte(dev, BQREQ, read_nic_byte(dev, BQREQ) | (1<<7)); + + i=0; + //while(!read_nic_byte(dev,BQREQ & (1<<7))) + while( (read_nic_byte(dev, BQREQ) & (1<<7)) == 0 ) + { + msleep_interruptible_rtl(HZ/2); + if(i++ > 10){ + DMESGW("get stuck to wait HW beacon to be ready"); + return ; + } + } + skb->cb[0] = NORM_PRIORITY; + skb->cb[1] = 0; //morefragment = 0 + skb->cb[2] = ieeerate2rtlrate(tx_rate); + + rtl8192_tx(dev,skb); + +#endif +} +#endif +inline u8 rtl8192_IsWirelessBMode(u16 rate) +{ + if( ((rate <= 110) && (rate != 60) && (rate != 90)) || (rate == 220) ) + return 1; + else return 0; +} + +u16 N_DBPSOfRate(u16 DataRate); + +u16 ComputeTxTime( + u16 FrameLength, + u16 DataRate, + u8 bManagementFrame, + u8 bShortPreamble +) +{ + u16 FrameTime; + u16 N_DBPS; + u16 Ceiling; + + if( rtl8192_IsWirelessBMode(DataRate) ) + { + if( bManagementFrame || !bShortPreamble || DataRate == 10 ) + { // long preamble + FrameTime = (u16)(144+48+(FrameLength*8/(DataRate/10))); + } + else + { // Short preamble + FrameTime = (u16)(72+24+(FrameLength*8/(DataRate/10))); + } + if( ( FrameLength*8 % (DataRate/10) ) != 0 ) //Get the Ceilling + FrameTime ++; + } else { //802.11g DSSS-OFDM PLCP length field calculation. + N_DBPS = N_DBPSOfRate(DataRate); + Ceiling = (16 + 8*FrameLength + 6) / N_DBPS + + (((16 + 8*FrameLength + 6) % N_DBPS) ? 1 : 0); + FrameTime = (u16)(16 + 4 + 4*Ceiling + 6); + } + return FrameTime; +} + +u16 N_DBPSOfRate(u16 DataRate) +{ + u16 N_DBPS = 24; + + switch(DataRate) + { + case 60: + N_DBPS = 24; + break; + + case 90: + N_DBPS = 36; + break; + + case 120: + N_DBPS = 48; + break; + + case 180: + N_DBPS = 72; + break; + + case 240: + N_DBPS = 96; + break; + + case 360: + N_DBPS = 144; + break; + + case 480: + N_DBPS = 192; + break; + + case 540: + N_DBPS = 216; + break; + + default: + break; + } + + return N_DBPS; +} + +void rtl819xU_cmd_isr(struct urb *tx_cmd_urb, struct pt_regs *regs) +{ +#if 0 + struct net_device *dev = (struct net_device*)tx_cmd_urb->context; + struct r8192_priv *priv = ieee80211_priv(dev); + int last_init_packet = 0; + u8 *ptr_cmd_buf; + u16 cmd_buf_len; + + if(tx_cmd_urb->status != 0) { + priv->pFirmware.firmware_seg_index = 0; //only begin transter, should it can be set to 1 + } + + /* Free the urb and the corresponding buf for common Tx cmd packet, or + * last segment of each firmware img. + */ + if((priv->pFirmware.firmware_seg_index == 0) ||(priv->pFirmware.firmware_seg_index == priv->pFirmware.firmware_seg_maxnum)) { + priv->pFirmware.firmware_seg_index = 0;//only begin transter, should it can be set to 1 + } else { + /* prepare for last transfer */ + /* update some infomation for */ + /* last segment of the firmware img need indicate to device */ + priv->pFirmware.firmware_seg_index++; + if(priv->pFirmware.firmware_seg_index == priv->pFirmware.firmware_seg_maxnum) { + last_init_packet = 1; + } + + cmd_buf_len = priv->pFirmware.firmware_seg_container[priv->pFirmware.firmware_seg_index-1].seg_size; + ptr_cmd_buf = priv->pFfirmware.firmware_seg_container[priv->pFfirmware.firmware_seg_index-1].seg_ptr; + rtl819xU_tx_cmd(dev, ptr_cmd_buf, cmd_buf_len, last_init_packet, DESC_PACKET_TYPE_INIT); + } + + kfree(tx_cmd_urb->transfer_buffer); +#endif + usb_free_urb(tx_cmd_urb); +} + +unsigned int txqueue2outpipe(struct r8192_priv* priv,unsigned int tx_queue) { + + if(tx_queue >= 9) + { + RT_TRACE(COMP_ERR,"%s():Unknown queue ID!!!\n",__FUNCTION__); + return 0x04; + } + return priv->txqueue_to_outpipemap[tx_queue]; +} + +#ifdef RTL8192SU +short rtl8192SU_tx_cmd(struct net_device *dev, struct sk_buff *skb) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + int status; + struct urb *tx_urb; + unsigned int idx_pipe; + tx_desc_cmd_819x_usb *pdesc = (tx_desc_cmd_819x_usb *)skb->data; + cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE); + u8 queue_index = tcb_desc->queue_index; + u32 PktSize = 0; + + //printk("\n %s::::::::::::::::::::::queue_index = %d\n",__FUNCTION__, queue_index); + atomic_inc(&priv->tx_pending[queue_index]); + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + tx_urb = usb_alloc_urb(0,GFP_ATOMIC); +#else + tx_urb = usb_alloc_urb(0); +#endif + if(!tx_urb){ + dev_kfree_skb(skb); + return -ENOMEM; + } + + memset(pdesc, 0, USB_HWDESC_HEADER_LEN); + + /* Tx descriptor ought to be set according to the skb->cb */ + pdesc->LINIP = tcb_desc->bLastIniPkt; + PktSize = (u16)(skb->len - USB_HWDESC_HEADER_LEN); + pdesc->PktSize = PktSize; + //printk("PKTSize = %d %x\n",pdesc->PktSize,pdesc->PktSize); + //---------------------------------------------------------------------------- + // Fill up USB_OUT_CONTEXT. + //---------------------------------------------------------------------------- + // Get index to out pipe from specified QueueID. + idx_pipe = txqueue2outpipe(priv,queue_index); + //printk("=============>%s queue_index:%d, outpipe:%d\n", __func__,queue_index,priv->RtOutPipes[idx_pipe]); + +#ifdef JOHN_DUMP_TXDESC + int i; + printk("Len = %d\n", skb->len); + for (i = 0; i < 8; i++) + printk("%2.2x ", *((u8*)skb->data+i)); + printk("\n"); +#endif + + usb_fill_bulk_urb(tx_urb, + priv->udev, + usb_sndbulkpipe(priv->udev,priv->RtOutPipes[idx_pipe]), + skb->data, + skb->len, + rtl8192_tx_isr, + skb); + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + status = usb_submit_urb(tx_urb, GFP_ATOMIC); +#else + status = usb_submit_urb(tx_urb); +#endif + + if (!status){ + return 0; + }else{ + printk("Error TX CMD URB, error %d", + status); + return -1; + } +} +#else +short rtl819xU_tx_cmd(struct net_device *dev, struct sk_buff *skb) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + //u8 *tx; + int status; + struct urb *tx_urb; + //int urb_buf_len; + unsigned int idx_pipe; + tx_desc_cmd_819x_usb *pdesc = (tx_desc_cmd_819x_usb *)skb->data; + cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE); + u8 queue_index = tcb_desc->queue_index; + + //printk("\n %s::queue_index = %d\n",__FUNCTION__, queue_index); + atomic_inc(&priv->tx_pending[queue_index]); +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + tx_urb = usb_alloc_urb(0,GFP_ATOMIC); +#else + tx_urb = usb_alloc_urb(0); +#endif + if(!tx_urb){ + dev_kfree_skb(skb); + return -ENOMEM; + } + + memset(pdesc, 0, USB_HWDESC_HEADER_LEN); + /* Tx descriptor ought to be set according to the skb->cb */ + pdesc->FirstSeg = 1;//bFirstSeg; + pdesc->LastSeg = 1;//bLastSeg; + pdesc->CmdInit = tcb_desc->bCmdOrInit; + pdesc->TxBufferSize = tcb_desc->txbuf_size; + pdesc->OWN = 1; + pdesc->LINIP = tcb_desc->bLastIniPkt; + + //---------------------------------------------------------------------------- + // Fill up USB_OUT_CONTEXT. + //---------------------------------------------------------------------------- + // Get index to out pipe from specified QueueID. +#ifndef USE_ONE_PIPE + idx_pipe = txqueue2outpipe(priv,queue_index); +#else + idx_pipe = 0x04; +#endif +#ifdef JOHN_DUMP_TXDESC + int i; + printk("<Tx descriptor>--rate %x---",rate); + for (i = 0; i < 8; i++) + printk("%8x ", tx[i]); + printk("\n"); +#endif + usb_fill_bulk_urb(tx_urb,priv->udev, usb_sndbulkpipe(priv->udev,idx_pipe), \ + skb->data, skb->len, rtl8192_tx_isr, skb); + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + status = usb_submit_urb(tx_urb, GFP_ATOMIC); +#else + status = usb_submit_urb(tx_urb); +#endif + + if (!status){ + return 0; + }else{ + DMESGE("Error TX CMD URB, error %d", + status); + return -1; + } +} +#endif + +/* + * Mapping Software/Hardware descriptor queue id to "Queue Select Field" + * in TxFwInfo data structure + * 2006.10.30 by Emily + * + * \param QUEUEID Software Queue +*/ +u8 MapHwQueueToFirmwareQueue(u8 QueueID) +{ + u8 QueueSelect = 0x0; //defualt set to + + switch(QueueID) { + case BE_QUEUE: + QueueSelect = QSLT_BE; //or QSelect = pTcb->priority; + break; + + case BK_QUEUE: + QueueSelect = QSLT_BK; //or QSelect = pTcb->priority; + break; + + case VO_QUEUE: + QueueSelect = QSLT_VO; //or QSelect = pTcb->priority; + break; + + case VI_QUEUE: + QueueSelect = QSLT_VI; //or QSelect = pTcb->priority; + break; + case MGNT_QUEUE: + QueueSelect = QSLT_MGNT; + break; + + case BEACON_QUEUE: + QueueSelect = QSLT_BEACON; + break; + + // TODO: 2006.10.30 mark other queue selection until we verify it is OK + // TODO: Remove Assertions +//#if (RTL819X_FPGA_VER & RTL819X_FPGA_GUANGAN_070502) + case TXCMD_QUEUE: + QueueSelect = QSLT_CMD; + break; +//#endif + case HIGH_QUEUE: + QueueSelect = QSLT_HIGH; + break; + + default: + RT_TRACE(COMP_ERR, "TransmitTCB(): Impossible Queue Selection: %d \n", QueueID); + break; + } + return QueueSelect; +} + +#ifdef RTL8192SU +u8 MRateToHwRate8190Pci(u8 rate) +{ + u8 ret = DESC92S_RATE1M; + + switch(rate) + { + // CCK and OFDM non-HT rates + case MGN_1M: ret = DESC92S_RATE1M; break; + case MGN_2M: ret = DESC92S_RATE2M; break; + case MGN_5_5M: ret = DESC92S_RATE5_5M; break; + case MGN_11M: ret = DESC92S_RATE11M; break; + case MGN_6M: ret = DESC92S_RATE6M; break; + case MGN_9M: ret = DESC92S_RATE9M; break; + case MGN_12M: ret = DESC92S_RATE12M; break; + case MGN_18M: ret = DESC92S_RATE18M; break; + case MGN_24M: ret = DESC92S_RATE24M; break; + case MGN_36M: ret = DESC92S_RATE36M; break; + case MGN_48M: ret = DESC92S_RATE48M; break; + case MGN_54M: ret = DESC92S_RATE54M; break; + + // HT rates since here + case MGN_MCS0: ret = DESC92S_RATEMCS0; break; + case MGN_MCS1: ret = DESC92S_RATEMCS1; break; + case MGN_MCS2: ret = DESC92S_RATEMCS2; break; + case MGN_MCS3: ret = DESC92S_RATEMCS3; break; + case MGN_MCS4: ret = DESC92S_RATEMCS4; break; + case MGN_MCS5: ret = DESC92S_RATEMCS5; break; + case MGN_MCS6: ret = DESC92S_RATEMCS6; break; + case MGN_MCS7: ret = DESC92S_RATEMCS7; break; + case MGN_MCS8: ret = DESC92S_RATEMCS8; break; + case MGN_MCS9: ret = DESC92S_RATEMCS9; break; + case MGN_MCS10: ret = DESC92S_RATEMCS10; break; + case MGN_MCS11: ret = DESC92S_RATEMCS11; break; + case MGN_MCS12: ret = DESC92S_RATEMCS12; break; + case MGN_MCS13: ret = DESC92S_RATEMCS13; break; + case MGN_MCS14: ret = DESC92S_RATEMCS14; break; + case MGN_MCS15: ret = DESC92S_RATEMCS15; break; + + // Set the highest SG rate + case MGN_MCS0_SG: + case MGN_MCS1_SG: + case MGN_MCS2_SG: + case MGN_MCS3_SG: + case MGN_MCS4_SG: + case MGN_MCS5_SG: + case MGN_MCS6_SG: + case MGN_MCS7_SG: + case MGN_MCS8_SG: + case MGN_MCS9_SG: + case MGN_MCS10_SG: + case MGN_MCS11_SG: + case MGN_MCS12_SG: + case MGN_MCS13_SG: + case MGN_MCS14_SG: + case MGN_MCS15_SG: + { + ret = DESC92S_RATEMCS15_SG; + break; + } + + default: break; + } + return ret; +} +#else +u8 MRateToHwRate8190Pci(u8 rate) +{ + u8 ret = DESC90_RATE1M; + + switch(rate) { + case MGN_1M: ret = DESC90_RATE1M; break; + case MGN_2M: ret = DESC90_RATE2M; break; + case MGN_5_5M: ret = DESC90_RATE5_5M; break; + case MGN_11M: ret = DESC90_RATE11M; break; + case MGN_6M: ret = DESC90_RATE6M; break; + case MGN_9M: ret = DESC90_RATE9M; break; + case MGN_12M: ret = DESC90_RATE12M; break; + case MGN_18M: ret = DESC90_RATE18M; break; + case MGN_24M: ret = DESC90_RATE24M; break; + case MGN_36M: ret = DESC90_RATE36M; break; + case MGN_48M: ret = DESC90_RATE48M; break; + case MGN_54M: ret = DESC90_RATE54M; break; + + // HT rate since here + case MGN_MCS0: ret = DESC90_RATEMCS0; break; + case MGN_MCS1: ret = DESC90_RATEMCS1; break; + case MGN_MCS2: ret = DESC90_RATEMCS2; break; + case MGN_MCS3: ret = DESC90_RATEMCS3; break; + case MGN_MCS4: ret = DESC90_RATEMCS4; break; + case MGN_MCS5: ret = DESC90_RATEMCS5; break; + case MGN_MCS6: ret = DESC90_RATEMCS6; break; + case MGN_MCS7: ret = DESC90_RATEMCS7; break; + case MGN_MCS8: ret = DESC90_RATEMCS8; break; + case MGN_MCS9: ret = DESC90_RATEMCS9; break; + case MGN_MCS10: ret = DESC90_RATEMCS10; break; + case MGN_MCS11: ret = DESC90_RATEMCS11; break; + case MGN_MCS12: ret = DESC90_RATEMCS12; break; + case MGN_MCS13: ret = DESC90_RATEMCS13; break; + case MGN_MCS14: ret = DESC90_RATEMCS14; break; + case MGN_MCS15: ret = DESC90_RATEMCS15; break; + case (0x80|0x20): ret = DESC90_RATEMCS32; break; + + default: break; + } + return ret; +} +#endif + +u8 QueryIsShort(u8 TxHT, u8 TxRate, cb_desc *tcb_desc) +{ + u8 tmp_Short; + + tmp_Short = (TxHT==1)?((tcb_desc->bUseShortGI)?1:0):((tcb_desc->bUseShortPreamble)?1:0); + + if(TxHT==1 && TxRate != DESC90_RATEMCS15) + tmp_Short = 0; + + return tmp_Short; +} + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) +static void tx_zero_isr(struct urb *tx_urb, struct pt_regs *reg) +#else +static void tx_zero_isr(struct urb *tx_urb) +#endif +{ + return; +} + + +#ifdef RTL8192SU +/* + * The tx procedure is just as following, skb->cb will contain all the following + *information: * priority, morefrag, rate, &dev. + * */ + // <Note> Buffer format for 8192S Usb bulk out: +// +// -------------------------------------------------- +// | 8192S Usb Tx Desc | 802_11_MAC_header | data | +// -------------------------------------------------- +// | 32 bytes | 24 bytes |0-2318 bytes| +// -------------------------------------------------- +// |<------------ BufferLen ------------------------->| + +short rtl8192SU_tx(struct net_device *dev, struct sk_buff* skb) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE); + tx_desc_819x_usb *tx_desc = (tx_desc_819x_usb *)skb->data; + //tx_fwinfo_819x_usb *tx_fwinfo = (tx_fwinfo_819x_usb *)(skb->data + USB_HWDESC_HEADER_LEN);//92su del + struct usb_device *udev = priv->udev; + int pend; + int status; + struct urb *tx_urb = NULL, *tx_urb_zero = NULL; + //int urb_len; + unsigned int idx_pipe; + u16 MPDUOverhead = 0; + //RT_DEBUG_DATA(COMP_SEND, tcb_desc, sizeof(cb_desc)); + +#if 0 + /* Added by Annie for filling Len_Adjust field. 2005-12-14. */ + RT_ENC_ALG EncAlg = NO_Encryption; +#endif + + + pend = atomic_read(&priv->tx_pending[tcb_desc->queue_index]); + /* we are locked here so the two atomic_read and inc are executed + * without interleaves * !!! For debug purpose */ + if( pend > MAX_TX_URB){ + switch (tcb_desc->queue_index) { + case VO_PRIORITY: + priv->stats.txvodrop++; + break; + case VI_PRIORITY: + priv->stats.txvidrop++; + break; + case BE_PRIORITY: + priv->stats.txbedrop++; + break; + default://BK_PRIORITY + priv->stats.txbkdrop++; + break; + } + printk("To discard skb packet!\n"); + dev_kfree_skb_any(skb); + return -1; + } + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + tx_urb = usb_alloc_urb(0,GFP_ATOMIC); +#else + tx_urb = usb_alloc_urb(0); +#endif + if(!tx_urb){ + dev_kfree_skb_any(skb); + return -ENOMEM; + } + + memset(tx_desc, 0, sizeof(tx_desc_819x_usb)); + + +#if RTL8192SU_FPGA_UNSPECIFIED_NETWORK + if(IsQoSDataFrame(skb->data)) + { + tcb_desc->bAMPDUEnable = TRUE; + tx_desc->NonQos = 0; + } + else + tcb_desc->bAMPDUEnable = FALSE; + + tcb_desc->bPacketBW = TRUE; + priv->CurrentChannelBW = HT_CHANNEL_WIDTH_20_40; +#endif + +#if (defined (RTL8192SU_FPGA_2MAC_VERIFICATION)||defined (RTL8192SU_ASIC_VERIFICATION)) + tx_desc->NonQos = (IsQoSDataFrame(skb->data)==TRUE)? 0:1; +#endif + + /* Fill Tx descriptor */ + //memset(tx_fwinfo,0,sizeof(tx_fwinfo_819x_usb)); + + // This part can just fill to the first descriptor of the frame. + /* DWORD 0 */ + tx_desc->TxHT = (tcb_desc->data_rate&0x80)?1:0; + +#ifdef RTL8192SU_DISABLE_CCK_RATE + if(tx_hal_is_cck_rate(tcb_desc->data_rate)) + tcb_desc->data_rate = MGN_6M; +#endif + + tx_desc->TxRate = MRateToHwRate8190Pci(tcb_desc->data_rate); + //tx_desc->EnableCPUDur = tcb_desc->bTxEnableFwCalcDur; + tx_desc->TxShort = QueryIsShort(tx_desc->TxHT, tx_desc->TxRate, tcb_desc); + + + // Aggregation related + if(tcb_desc->bAMPDUEnable) {//AMPDU enabled + tx_desc->AllowAggregation = 1; + /* DWORD 1 */ + //tx_fwinfo->RxMF = tcb_desc->ampdu_factor; + //tx_fwinfo->RxAMD = tcb_desc->ampdu_density&0x07;//ampdudensity + } else { + tx_desc->AllowAggregation = 0; + /* DWORD 1 */ + //tx_fwinfo->RxMF = 0; + //tx_fwinfo->RxAMD = 0; + } + + // + // <Roger_Notes> For AMPDU case, we must insert SSN into TX_DESC, + // FW according as this SSN to do necessary packet retry. + // 2008.06.06. + // + { + u8 *pSeq; + u16 Temp; + //pSeq = (u8 *)(VirtualAddress+USB_HWDESC_HEADER_LEN + FRAME_OFFSET_SEQUENCE); + pSeq = (u8 *)(skb->data+USB_HWDESC_HEADER_LEN + 22); + Temp = pSeq[0]; + Temp <<= 12; + Temp |= (*(u16 *)pSeq)>>4; + tx_desc->Seq = Temp; + } + + /* Protection mode related */ + tx_desc->RTSEn = (tcb_desc->bRTSEnable)?1:0; + tx_desc->CTS2Self = (tcb_desc->bCTSEnable)?1:0; + tx_desc->RTSSTBC = (tcb_desc->bRTSSTBC)?1:0; + tx_desc->RTSHT = (tcb_desc->rts_rate&0x80)?1:0; + tx_desc->RTSRate = MRateToHwRate8190Pci((u8)tcb_desc->rts_rate); + tx_desc->RTSSubcarrier = (tx_desc->RTSHT==0)?(tcb_desc->RTSSC):0; + tx_desc->RTSBW = (tx_desc->RTSHT==1)?((tcb_desc->bRTSBW)?1:0):0; + tx_desc->RTSShort = (tx_desc->RTSHT==0)?(tcb_desc->bRTSUseShortPreamble?1:0):\ + (tcb_desc->bRTSUseShortGI?1:0); + //LZM 090219 + tx_desc->DisRTSFB = 0; + tx_desc->RTSRateFBLmt = 0xf; + + // <Roger_EXP> 2008.09.22. We disable RTS rate fallback temporarily. + //tx_desc->DisRTSFB = 0x01; + + /* Set Bandwidth and sub-channel settings. */ + if(priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) + { + if(tcb_desc->bPacketBW) { + tx_desc->TxBandwidth = 1; + tx_desc->TxSubCarrier = 0; //By SD3's Jerry suggestion, use duplicated mode + } else { + tx_desc->TxBandwidth = 0; + tx_desc->TxSubCarrier = priv->nCur40MhzPrimeSC; + } + } else { + tx_desc->TxBandwidth = 0; + tx_desc->TxSubCarrier = 0; + } + +#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE + if (tcb_desc->drv_agg_enable) + { + //tx_desc->Tx_INFO_RSVD = (tcb_desc->DrvAggrNum & 0x1f) << 1; //92su del + } +#endif + + //memset(tx_desc, 0, sizeof(tx_desc_819x_usb)); + /* DWORD 0 */ + tx_desc->LINIP = 0; + //tx_desc->CmdInit = 1; //92su del + tx_desc->Offset = USB_HWDESC_HEADER_LEN; + +#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE + if (tcb_desc->drv_agg_enable) { + tx_desc->PktSize = tcb_desc->pkt_size;//FIXLZM + } else +#endif + { + tx_desc->PktSize = (skb->len - USB_HWDESC_HEADER_LEN) & 0xffff; + } + + /*DWORD 1*/ + //tx_desc->SecCAMID= 0;//92su del + tx_desc->RaBRSRID= tcb_desc->RATRIndex; +//#ifdef RTL8192S_PREPARE_FOR_NORMAL_RELEASE +#if 0//LZM 090219 + tx_desc->RaBRSRID= 1; +#endif + +#if 0 + /* Fill security related */ + if( pTcb->bEncrypt && !Adapter->MgntInfo.SecurityInfo.SWTxEncryptFlag) + { + EncAlg = SecGetEncryptionOverhead( + Adapter, + &EncryptionMPDUHeadOverhead, + &EncryptionMPDUTailOverhead, + NULL, + NULL, + FALSE, + FALSE); + //2004/07/22, kcwu, EncryptionMPDUHeadOverhead has been added in previous code + //MPDUOverhead = EncryptionMPDUHeadOverhead + EncryptionMPDUTailOverhead; + MPDUOverhead = EncryptionMPDUTailOverhead; + tx_desc->NoEnc = 0; + RT_TRACE(COMP_SEC, DBG_LOUD, ("******We in the loop SecCAMID is %d SecDescAssign is %d The Sec is %d********\n",tx_desc->SecCAMID,tx_desc->SecDescAssign,EncAlg)); + //CamDumpAll(Adapter); + } + else +#endif + { + MPDUOverhead = 0; + //tx_desc->NoEnc = 1;//92su del + } +#if 0 + switch(EncAlg){ + case NO_Encryption: + tx_desc->SecType = 0x0; + break; + case WEP40_Encryption: + case WEP104_Encryption: + tx_desc->SecType = 0x1; + break; + case TKIP_Encryption: + tx_desc->SecType = 0x2; + break; + case AESCCMP_Encryption: + tx_desc->SecType = 0x3; + break; + default: + tx_desc->SecType = 0x0; + break; + } +#else + tx_desc->SecType = 0x0; +#endif + if (tcb_desc->bHwSec) + { + switch (priv->ieee80211->pairwise_key_type) + { + case KEY_TYPE_WEP40: + case KEY_TYPE_WEP104: + tx_desc->SecType = 0x1; + //tx_desc->NoEnc = 0;//92su del + break; + case KEY_TYPE_TKIP: + tx_desc->SecType = 0x2; + //tx_desc->NoEnc = 0;//92su del + break; + case KEY_TYPE_CCMP: + tx_desc->SecType = 0x3; + //tx_desc->NoEnc = 0;//92su del + break; + case KEY_TYPE_NA: + tx_desc->SecType = 0x0; + //tx_desc->NoEnc = 1;//92su del + break; + default: + tx_desc->SecType = 0x0; + //tx_desc->NoEnc = 1;//92su del + break; + } + } + + //tx_desc->TxFWInfoSize = sizeof(tx_fwinfo_819x_usb);//92su del + + + tx_desc->USERATE = tcb_desc->bTxUseDriverAssingedRate; + tx_desc->DISFB = tcb_desc->bTxDisableRateFallBack; + tx_desc->DataRateFBLmt = 0x1F;// Alwasy enable all rate fallback range + + tx_desc->QueueSelect = MapHwQueueToFirmwareQueue(tcb_desc->queue_index); + + + /* Fill fields that are required to be initialized in all of the descriptors */ + //DWORD 0 +#if 0 + tx_desc->FirstSeg = (tcb_desc->bFirstSeg)? 1:0; + tx_desc->LastSeg = (tcb_desc->bLastSeg)?1:0; +#else + tx_desc->FirstSeg = 1; + tx_desc->LastSeg = 1; +#endif + tx_desc->OWN = 1; + +#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE + if (tcb_desc->drv_agg_enable) { + tx_desc->TxBufferSize = tcb_desc->pkt_size + sizeof(tx_fwinfo_819x_usb); + } else +#endif + { + //DWORD 2 + //tx_desc->TxBufferSize = (u32)(skb->len - USB_HWDESC_HEADER_LEN); + tx_desc->TxBufferSize = (u32)(skb->len);//92su mod FIXLZM + } + +#if 0 + RT_TRACE(COMP_FPGA, DBG_LOUD, ("(1)TxFillDescriptor8192SUsb(): DataRate(%#x)\n", pTcb->DataRate)); + RT_TRACE(COMP_FPGA, DBG_LOUD, ("(2)TxFillDescriptor8192SUsb(): bTxUseDriverAssingedRate(%#x)\n", pTcb->bTxUseDriverAssingedRate)); + RT_TRACE(COMP_FPGA, DBG_LOUD, ("(3)TxFillDescriptor8192SUsb(): bAMPDUEnable(%d)\n", pTcb->bAMPDUEnable)); + RT_TRACE(COMP_FPGA, DBG_LOUD, ("(4)TxFillDescriptor8192SUsb(): bRTSEnable(%d)\n", pTcb->bRTSEnable)); + RT_TRACE(COMP_FPGA, DBG_LOUD, ("(5)TxFillDescriptor8192SUsb(): RTSRate(%#x)\n", pTcb->RTSRate)); + RT_TRACE(COMP_FPGA, DBG_LOUD, ("(6)TxFillDescriptor8192SUsb(): bCTSEnable(%d)\n", pTcb->bCTSEnable)); + RT_TRACE(COMP_FPGA, DBG_LOUD, ("(7)TxFillDescriptor8192SUsb(): bUseShortGI(%d)\n", pTcb->bUseShortGI)); + RT_TRACE(COMP_FPGA, DBG_LOUD, ("(8)TxFillDescriptor8192SUsb(): bPacketBW(%d)\n", pTcb->bPacketBW)); + RT_TRACE(COMP_FPGA, DBG_LOUD, ("(9)TxFillDescriptor8192SUsb(): CurrentChannelBW(%d)\n", pHalData->CurrentChannelBW)); + RT_TRACE(COMP_FPGA, DBG_LOUD, ("(10)TxFillDescriptor8192SUsb(): bTxDisableRateFallBack(%d)\n", pTcb->bTxDisableRateFallBack)); + RT_TRACE(COMP_FPGA, DBG_LOUD, ("(11)TxFillDescriptor8192SUsb(): RATRIndex(%d)\n", pTcb->RATRIndex)); +#endif + + /* Get index to out pipe from specified QueueID */ + idx_pipe = txqueue2outpipe(priv,tcb_desc->queue_index); + //printk("=============>%s queue_index:%d, outpipe:%d\n", __func__,tcb_desc->queue_index,priv->RtOutPipes[idx_pipe]); + + //RT_DEBUG_DATA(COMP_SEND,tx_fwinfo,sizeof(tx_fwinfo_819x_usb)); + //RT_DEBUG_DATA(COMP_SEND,tx_desc,sizeof(tx_desc_819x_usb)); + + /* To submit bulk urb */ + usb_fill_bulk_urb(tx_urb, + udev, + usb_sndbulkpipe(udev,priv->RtOutPipes[idx_pipe]), + skb->data, + skb->len, rtl8192_tx_isr, skb); + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + status = usb_submit_urb(tx_urb, GFP_ATOMIC); +#else + status = usb_submit_urb(tx_urb); +#endif + if (!status){ +//we need to send 0 byte packet whenever 512N bytes/64N(HIGN SPEED/NORMAL SPEED) bytes packet has been transmitted. Otherwise, it will be halt to wait for another packet. WB. 2008.08.27 + bool bSend0Byte = false; + u8 zero = 0; + if(udev->speed == USB_SPEED_HIGH) + { + if (skb->len > 0 && skb->len % 512 == 0) + bSend0Byte = true; + } + else + { + if (skb->len > 0 && skb->len % 64 == 0) + bSend0Byte = true; + } + if (bSend0Byte) + { +#if 1 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + tx_urb_zero = usb_alloc_urb(0,GFP_ATOMIC); +#else + tx_urb_zero = usb_alloc_urb(0); +#endif + if(!tx_urb_zero){ + RT_TRACE(COMP_ERR, "can't alloc urb for zero byte\n"); + return -ENOMEM; + } + usb_fill_bulk_urb(tx_urb_zero,udev, + usb_sndbulkpipe(udev,idx_pipe), &zero, + 0, tx_zero_isr, dev); +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + status = usb_submit_urb(tx_urb_zero, GFP_ATOMIC); +#else + status = usb_submit_urb(tx_urb_zero); +#endif + if (status){ + RT_TRACE(COMP_ERR, "Error TX URB for zero byte %d, error %d", atomic_read(&priv->tx_pending[tcb_desc->queue_index]), status); + return -1; + } +#endif + } + dev->trans_start = jiffies; + atomic_inc(&priv->tx_pending[tcb_desc->queue_index]); + return 0; + }else{ + RT_TRACE(COMP_ERR, "Error TX URB %d, error %d", atomic_read(&priv->tx_pending[tcb_desc->queue_index]), + status); + return -1; + } +} +#else + +/* + * The tx procedure is just as following, + * skb->cb will contain all the following information, + * priority, morefrag, rate, &dev. + * */ +short rtl8192_tx(struct net_device *dev, struct sk_buff* skb) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + cb_desc *tcb_desc = (cb_desc *)(skb->cb + MAX_DEV_ADDR_SIZE); + tx_desc_819x_usb *tx_desc = (tx_desc_819x_usb *)skb->data; + tx_fwinfo_819x_usb *tx_fwinfo = (tx_fwinfo_819x_usb *)(skb->data + USB_HWDESC_HEADER_LEN); + struct usb_device *udev = priv->udev; + int pend; + int status; + struct urb *tx_urb = NULL, *tx_urb_zero = NULL; + //int urb_len; + unsigned int idx_pipe; +// RT_DEBUG_DATA(COMP_SEND, tcb_desc, sizeof(cb_desc)); +#if 0 + /* Added by Annie for filling Len_Adjust field. 2005-12-14. */ + RT_ENC_ALG EncAlg = NO_Encryption; +#endif +// printk("=============> %s\n", __FUNCTION__); + pend = atomic_read(&priv->tx_pending[tcb_desc->queue_index]); + /* we are locked here so the two atomic_read and inc are executed + * without interleaves + * !!! For debug purpose + */ + if( pend > MAX_TX_URB){ +#if 0 + switch (tcb_desc->queue_index) { + case VO_PRIORITY: + priv->stats.txvodrop++; + break; + case VI_PRIORITY: + priv->stats.txvidrop++; + break; + case BE_PRIORITY: + priv->stats.txbedrop++; + break; + default://BK_PRIORITY + priv->stats.txbkdrop++; + break; + } +#endif + printk("To discard skb packet!\n"); + dev_kfree_skb_any(skb); + return -1; + } + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + tx_urb = usb_alloc_urb(0,GFP_ATOMIC); +#else + tx_urb = usb_alloc_urb(0); +#endif + if(!tx_urb){ + dev_kfree_skb_any(skb); + return -ENOMEM; + } + + /* Fill Tx firmware info */ + memset(tx_fwinfo,0,sizeof(tx_fwinfo_819x_usb)); + /* DWORD 0 */ + tx_fwinfo->TxHT = (tcb_desc->data_rate&0x80)?1:0; + tx_fwinfo->TxRate = MRateToHwRate8190Pci(tcb_desc->data_rate); + tx_fwinfo->EnableCPUDur = tcb_desc->bTxEnableFwCalcDur; + tx_fwinfo->Short = QueryIsShort(tx_fwinfo->TxHT, tx_fwinfo->TxRate, tcb_desc); + if(tcb_desc->bAMPDUEnable) {//AMPDU enabled + tx_fwinfo->AllowAggregation = 1; + /* DWORD 1 */ + tx_fwinfo->RxMF = tcb_desc->ampdu_factor; + tx_fwinfo->RxAMD = tcb_desc->ampdu_density&0x07;//ampdudensity + } else { + tx_fwinfo->AllowAggregation = 0; + /* DWORD 1 */ + tx_fwinfo->RxMF = 0; + tx_fwinfo->RxAMD = 0; + } + + /* Protection mode related */ + tx_fwinfo->RtsEnable = (tcb_desc->bRTSEnable)?1:0; + tx_fwinfo->CtsEnable = (tcb_desc->bCTSEnable)?1:0; + tx_fwinfo->RtsSTBC = (tcb_desc->bRTSSTBC)?1:0; + tx_fwinfo->RtsHT = (tcb_desc->rts_rate&0x80)?1:0; + tx_fwinfo->RtsRate = MRateToHwRate8190Pci((u8)tcb_desc->rts_rate); + tx_fwinfo->RtsSubcarrier = (tx_fwinfo->RtsHT==0)?(tcb_desc->RTSSC):0; + tx_fwinfo->RtsBandwidth = (tx_fwinfo->RtsHT==1)?((tcb_desc->bRTSBW)?1:0):0; + tx_fwinfo->RtsShort = (tx_fwinfo->RtsHT==0)?(tcb_desc->bRTSUseShortPreamble?1:0):\ + (tcb_desc->bRTSUseShortGI?1:0); + + /* Set Bandwidth and sub-channel settings. */ + if(priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) + { + if(tcb_desc->bPacketBW) { + tx_fwinfo->TxBandwidth = 1; + tx_fwinfo->TxSubCarrier = 0; //By SD3's Jerry suggestion, use duplicated mode + } else { + tx_fwinfo->TxBandwidth = 0; + tx_fwinfo->TxSubCarrier = priv->nCur40MhzPrimeSC; + } + } else { + tx_fwinfo->TxBandwidth = 0; + tx_fwinfo->TxSubCarrier = 0; + } + +#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE + if (tcb_desc->drv_agg_enable) + { + tx_fwinfo->Tx_INFO_RSVD = (tcb_desc->DrvAggrNum & 0x1f) << 1; + } +#endif + /* Fill Tx descriptor */ + memset(tx_desc, 0, sizeof(tx_desc_819x_usb)); + /* DWORD 0 */ + tx_desc->LINIP = 0; + tx_desc->CmdInit = 1; + tx_desc->Offset = sizeof(tx_fwinfo_819x_usb) + 8; + +#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE + if (tcb_desc->drv_agg_enable) { + tx_desc->PktSize = tcb_desc->pkt_size; + } else +#endif + { + tx_desc->PktSize = (skb->len - TX_PACKET_SHIFT_BYTES) & 0xffff; + } + + /*DWORD 1*/ + tx_desc->SecCAMID= 0; + tx_desc->RATid = tcb_desc->RATRIndex; +#if 0 + /* Fill security related */ + if( pTcb->bEncrypt && !Adapter->MgntInfo.SecurityInfo.SWTxEncryptFlag) + { + EncAlg = SecGetEncryptionOverhead( + Adapter, + &EncryptionMPDUHeadOverhead, + &EncryptionMPDUTailOverhead, + NULL, + NULL, + FALSE, + FALSE); + //2004/07/22, kcwu, EncryptionMPDUHeadOverhead has been added in previous code + //MPDUOverhead = EncryptionMPDUHeadOverhead + EncryptionMPDUTailOverhead; + MPDUOverhead = EncryptionMPDUTailOverhead; + tx_desc->NoEnc = 0; + RT_TRACE(COMP_SEC, DBG_LOUD, ("******We in the loop SecCAMID is %d SecDescAssign is %d The Sec is %d********\n",tx_desc->SecCAMID,tx_desc->SecDescAssign,EncAlg)); + //CamDumpAll(Adapter); + } + else +#endif + { + //MPDUOverhead = 0; + tx_desc->NoEnc = 1; + } +#if 0 + switch(EncAlg){ + case NO_Encryption: + tx_desc->SecType = 0x0; + break; + case WEP40_Encryption: + case WEP104_Encryption: + tx_desc->SecType = 0x1; + break; + case TKIP_Encryption: + tx_desc->SecType = 0x2; + break; + case AESCCMP_Encryption: + tx_desc->SecType = 0x3; + break; + default: + tx_desc->SecType = 0x0; + break; + } +#else + tx_desc->SecType = 0x0; +#endif + if (tcb_desc->bHwSec) + { + switch (priv->ieee80211->pairwise_key_type) + { + case KEY_TYPE_WEP40: + case KEY_TYPE_WEP104: + tx_desc->SecType = 0x1; + tx_desc->NoEnc = 0; + break; + case KEY_TYPE_TKIP: + tx_desc->SecType = 0x2; + tx_desc->NoEnc = 0; + break; + case KEY_TYPE_CCMP: + tx_desc->SecType = 0x3; + tx_desc->NoEnc = 0; + break; + case KEY_TYPE_NA: + tx_desc->SecType = 0x0; + tx_desc->NoEnc = 1; + break; + } + } + + tx_desc->QueueSelect = MapHwQueueToFirmwareQueue(tcb_desc->queue_index); + tx_desc->TxFWInfoSize = sizeof(tx_fwinfo_819x_usb); + + tx_desc->DISFB = tcb_desc->bTxDisableRateFallBack; + tx_desc->USERATE = tcb_desc->bTxUseDriverAssingedRate; + + /* Fill fields that are required to be initialized in all of the descriptors */ + //DWORD 0 +#if 0 + tx_desc->FirstSeg = (tcb_desc->bFirstSeg)? 1:0; + tx_desc->LastSeg = (tcb_desc->bLastSeg)?1:0; +#else + tx_desc->FirstSeg = 1; + tx_desc->LastSeg = 1; +#endif + tx_desc->OWN = 1; + +#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE + if (tcb_desc->drv_agg_enable) { + tx_desc->TxBufferSize = tcb_desc->pkt_size + sizeof(tx_fwinfo_819x_usb); + } else +#endif + { + //DWORD 2 + tx_desc->TxBufferSize = (u32)(skb->len - USB_HWDESC_HEADER_LEN); + } + /* Get index to out pipe from specified QueueID */ +#ifndef USE_ONE_PIPE + idx_pipe = txqueue2outpipe(priv,tcb_desc->queue_index); +#else + idx_pipe = 0x5; +#endif + + //RT_DEBUG_DATA(COMP_SEND,tx_fwinfo,sizeof(tx_fwinfo_819x_usb)); + //RT_DEBUG_DATA(COMP_SEND,tx_desc,sizeof(tx_desc_819x_usb)); + + /* To submit bulk urb */ + usb_fill_bulk_urb(tx_urb,udev, + usb_sndbulkpipe(udev,idx_pipe), skb->data, + skb->len, rtl8192_tx_isr, skb); + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + status = usb_submit_urb(tx_urb, GFP_ATOMIC); +#else + status = usb_submit_urb(tx_urb); +#endif + if (!status){ +//we need to send 0 byte packet whenever 512N bytes/64N(HIGN SPEED/NORMAL SPEED) bytes packet has been transmitted. Otherwise, it will be halt to wait for another packet. WB. 2008.08.27 + bool bSend0Byte = false; + u8 zero = 0; + if(udev->speed == USB_SPEED_HIGH) + { + if (skb->len > 0 && skb->len % 512 == 0) + bSend0Byte = true; + } + else + { + if (skb->len > 0 && skb->len % 64 == 0) + bSend0Byte = true; + } + if (bSend0Byte) + { +#if 1 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + tx_urb_zero = usb_alloc_urb(0,GFP_ATOMIC); +#else + tx_urb_zero = usb_alloc_urb(0); +#endif + if(!tx_urb_zero){ + RT_TRACE(COMP_ERR, "can't alloc urb for zero byte\n"); + return -ENOMEM; + } + usb_fill_bulk_urb(tx_urb_zero,udev, + usb_sndbulkpipe(udev,idx_pipe), &zero, + 0, tx_zero_isr, dev); +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + status = usb_submit_urb(tx_urb_zero, GFP_ATOMIC); +#else + status = usb_submit_urb(tx_urb_zero); +#endif + if (status){ + RT_TRACE(COMP_ERR, "Error TX URB for zero byte %d, error %d", atomic_read(&priv->tx_pending[tcb_desc->queue_index]), status); + return -1; + } +#endif + } + dev->trans_start = jiffies; + atomic_inc(&priv->tx_pending[tcb_desc->queue_index]); + return 0; + }else{ + RT_TRACE(COMP_ERR, "Error TX URB %d, error %d", atomic_read(&priv->tx_pending[tcb_desc->queue_index]), + status); + return -1; + } +} +#endif + +#if 0 +void rtl8192_set_rate(struct net_device *dev) +{ + int i; + u16 word; + int basic_rate,min_rr_rate,max_rr_rate; + +// struct r8192_priv *priv = ieee80211_priv(dev); + + //if (ieee80211_is_54g(priv->ieee80211->current_network) && +// priv->ieee80211->state == IEEE80211_LINKED){ + basic_rate = ieeerate2rtlrate(240); + min_rr_rate = ieeerate2rtlrate(60); + max_rr_rate = ieeerate2rtlrate(240); + +// +// }else{ +// basic_rate = ieeerate2rtlrate(20); +// min_rr_rate = ieeerate2rtlrate(10); +// max_rr_rate = ieeerate2rtlrate(110); +// } + + write_nic_byte(dev, RESP_RATE, + max_rr_rate<<MAX_RESP_RATE_SHIFT| min_rr_rate<<MIN_RESP_RATE_SHIFT); + + //word = read_nic_word(dev, BRSR); + word = read_nic_word(dev, BRSR_8187); + word &= ~BRSR_MBR_8185; + + + for(i=0;i<=basic_rate;i++) + word |= (1<<i); + + //write_nic_word(dev, BRSR, word); + write_nic_word(dev, BRSR_8187, word); + //DMESG("RR:%x BRSR: %x", read_nic_byte(dev,RESP_RATE), read_nic_word(dev,BRSR)); +} +#endif + + +#ifdef RTL8192SU +void rtl8192SU_net_update(struct net_device *dev) +{ + + struct r8192_priv *priv = ieee80211_priv(dev); + struct ieee80211_device* ieee = priv->ieee80211; + struct ieee80211_network *net = &priv->ieee80211->current_network; + //u16 BcnTimeCfg = 0, BcnCW = 6, BcnIFS = 0xf; + u16 rate_config = 0; + u32 regTmp = 0; + u8 rateIndex = 0; + u8 retrylimit = 0x30; + u16 cap = net->capability; + + priv->short_preamble = cap & WLAN_CAPABILITY_SHORT_PREAMBLE; + +//HW_VAR_BASIC_RATE + //update Basic rate: RR, BRSR + rtl8192_config_rate(dev, &rate_config); //HalSetBrateCfg + +#ifdef RTL8192SU_DISABLE_CCK_RATE + priv->basic_rate = rate_config = rate_config & 0x150; // Disable CCK 11M, 5.5M, 2M, and 1M rates. +#else + priv->basic_rate = rate_config = rate_config & 0x15f; +#endif + + // Set RRSR rate table. + write_nic_byte(dev, RRSR, rate_config&0xff); + write_nic_byte(dev, RRSR+1, (rate_config>>8)&0xff); + + // Set RTS initial rate + while(rate_config > 0x1) + { + rate_config = (rate_config>> 1); + rateIndex++; + } + write_nic_byte(dev, INIRTSMCS_SEL, rateIndex); +//HW_VAR_BASIC_RATE + + //set ack preample + regTmp = (priv->nCur40MhzPrimeSC) << 5; + if (priv->short_preamble) + regTmp |= 0x80; + write_nic_byte(dev, RRSR+2, regTmp); + + write_nic_dword(dev,BSSIDR,((u32*)net->bssid)[0]); + write_nic_word(dev,BSSIDR+4,((u16*)net->bssid)[2]); + + write_nic_word(dev, BCN_INTERVAL, net->beacon_interval); + //2008.10.24 added by tynli for beacon changed. + PHY_SetBeaconHwReg( dev, net->beacon_interval); + + rtl8192_update_cap(dev, cap); + + if (ieee->iw_mode == IW_MODE_ADHOC){ + retrylimit = 7; + //we should enable ibss interrupt here, but disable it temporarily + if (0){ + priv->irq_mask |= (IMR_BcnInt | IMR_BcnInt | IMR_TBDOK | IMR_TBDER); + //rtl8192_irq_disable(dev); + //rtl8192_irq_enable(dev); + } + } + else{ + if (0){ + priv->irq_mask &= ~(IMR_BcnInt | IMR_BcnInt | IMR_TBDOK | IMR_TBDER); + //rtl8192_irq_disable(dev); + //rtl8192_irq_enable(dev); + } + } + + priv->ShortRetryLimit = priv->LongRetryLimit = retrylimit; + + write_nic_word(dev, RETRY_LIMIT, + retrylimit << RETRY_LIMIT_SHORT_SHIFT | \ + retrylimit << RETRY_LIMIT_LONG_SHIFT); +} + +void rtl8192SU_update_ratr_table(struct net_device* dev) +{ + struct r8192_priv* priv = ieee80211_priv(dev); + struct ieee80211_device* ieee = priv->ieee80211; + u8* pMcsRate = ieee->dot11HTOperationalRateSet; + //struct ieee80211_network *net = &ieee->current_network; + u32 ratr_value = 0; + + u8 rate_index = 0; + int WirelessMode = ieee->mode; + u8 MimoPs = ieee->pHTInfo->PeerMimoPs; + + u8 bNMode = 0; + + rtl8192_config_rate(dev, (u16*)(&ratr_value)); + ratr_value |= (*(u16*)(pMcsRate)) << 12; + + //switch (ieee->mode) + switch (WirelessMode) + { + case IEEE_A: + ratr_value &= 0x00000FF0; + break; + case IEEE_B: + ratr_value &= 0x0000000D; + break; + case IEEE_G: + ratr_value &= 0x00000FF5; + break; + case IEEE_N_24G: + case IEEE_N_5G: + { + bNMode = 1; + + if (MimoPs == 0) //MIMO_PS_STATIC + { + ratr_value &= 0x0007F005; + } + else + { // MCS rate only => for 11N mode. + u32 ratr_mask; + + // 1T2R or 1T1R, Spatial Stream 2 should be disabled + if ( priv->rf_type == RF_1T2R || + priv->rf_type == RF_1T1R || + (ieee->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_TX_2SS) ) + ratr_mask = 0x000ff005; + else + ratr_mask = 0x0f0ff005; + + if((ieee->pHTInfo->bCurTxBW40MHz) && + !(ieee->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_TX_40_MHZ)) + ratr_mask |= 0x00000010; // Set 6MBps + + // Select rates for rate adaptive mechanism. + ratr_value &= ratr_mask; + } + } + break; + default: + if(0) + { + if(priv->rf_type == RF_1T2R) // 1T2R, Spatial Stream 2 should be disabled + { + ratr_value &= 0x000ff0f5; + } + else + { + ratr_value &= 0x0f0ff0f5; + } + } + //printk("====>%s(), mode is not correct:%x\n", __FUNCTION__, ieee->mode); + break; + } + +#ifdef RTL8192SU_DISABLE_CCK_RATE + ratr_value &= 0x0FFFFFF0; +#else + ratr_value &= 0x0FFFFFFF; +#endif + + // Get MAX MCS available. + if ( (bNMode && ((ieee->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_SHORT_GI)==0)) && + ((ieee->pHTInfo->bCurBW40MHz && ieee->pHTInfo->bCurShortGI40MHz) || + (!ieee->pHTInfo->bCurBW40MHz && ieee->pHTInfo->bCurShortGI20MHz))) + { + u8 shortGI_rate = 0; + u32 tmp_ratr_value = 0; + ratr_value |= 0x10000000;//??? + tmp_ratr_value = (ratr_value>>12); + for(shortGI_rate=15; shortGI_rate>0; shortGI_rate--) + { + if((1<<shortGI_rate) & tmp_ratr_value) + break; + } + shortGI_rate = (shortGI_rate<<12)|(shortGI_rate<<8)|(shortGI_rate<<4)|(shortGI_rate); + write_nic_byte(dev, SG_RATE, shortGI_rate); + //printk("==>SG_RATE:%x\n", read_nic_byte(dev, SG_RATE)); + } + write_nic_dword(dev, ARFR0+rate_index*4, ratr_value); + printk("=============>ARFR0+rate_index*4:%#x\n", ratr_value); + + //2 UFWP + if (ratr_value & 0xfffff000){ + //printk("===>set to N mode\n"); + HalSetFwCmd8192S(dev, FW_CMD_RA_REFRESH_N); + } + else { + //printk("===>set to B/G mode\n"); + HalSetFwCmd8192S(dev, FW_CMD_RA_REFRESH_BG); + } +} + +void rtl8192SU_link_change(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + struct ieee80211_device* ieee = priv->ieee80211; + //unsigned long flags; + u32 reg = 0; + + printk("=====>%s 1\n", __func__); + reg = read_nic_dword(dev, RCR); + + if (ieee->state == IEEE80211_LINKED) + { + + rtl8192SU_net_update(dev); + rtl8192SU_update_ratr_table(dev); + ieee->SetFwCmdHandler(dev, FW_CMD_HIGH_PWR_ENABLE); + priv->ReceiveConfig = reg |= RCR_CBSSID; + + }else{ + priv->ReceiveConfig = reg &= ~RCR_CBSSID; + + } + + write_nic_dword(dev, RCR, reg); + rtl8192_update_msr(dev); + + printk("<=====%s 2\n", __func__); +} +#else +extern void rtl8192_update_ratr_table(struct net_device* dev); +void rtl8192_link_change(struct net_device *dev) +{ +// int i; + + struct r8192_priv *priv = ieee80211_priv(dev); + struct ieee80211_device* ieee = priv->ieee80211; + //write_nic_word(dev, BCN_INTR_ITV, net->beacon_interval); + if (ieee->state == IEEE80211_LINKED) + { + rtl8192_net_update(dev); + rtl8192_update_ratr_table(dev); +#if 1 + //add this as in pure N mode, wep encryption will use software way, but there is no chance to set this as wep will not set group key in wext. WB.2008.07.08 + if ((KEY_TYPE_WEP40 == ieee->pairwise_key_type) || (KEY_TYPE_WEP104 == ieee->pairwise_key_type)) + EnableHWSecurityConfig8192(dev); +#endif + } + /*update timing params*/ +// RT_TRACE(COMP_CH, "========>%s(), chan:%d\n", __FUNCTION__, priv->chan); +// rtl8192_set_chan(dev, priv->chan); + if (ieee->iw_mode == IW_MODE_INFRA || ieee->iw_mode == IW_MODE_ADHOC) + { + u32 reg = 0; + reg = read_nic_dword(dev, RCR); + if (priv->ieee80211->state == IEEE80211_LINKED) + priv->ReceiveConfig = reg |= RCR_CBSSID; + else + priv->ReceiveConfig = reg &= ~RCR_CBSSID; + write_nic_dword(dev, RCR, reg); + } + +// rtl8192_set_rxconf(dev); +} +#endif + +static struct ieee80211_qos_parameters def_qos_parameters = { + {3,3,3,3},/* cw_min */ + {7,7,7,7},/* cw_max */ + {2,2,2,2},/* aifs */ + {0,0,0,0},/* flags */ + {0,0,0,0} /* tx_op_limit */ +}; + + +#if LINUX_VERSION_CODE >=KERNEL_VERSION(2,6,20) +void rtl8192_update_beacon(struct work_struct * work) +{ + struct r8192_priv *priv = container_of(work, struct r8192_priv, update_beacon_wq.work); + struct net_device *dev = priv->ieee80211->dev; +#else +void rtl8192_update_beacon(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); +#endif + struct ieee80211_device* ieee = priv->ieee80211; + struct ieee80211_network* net = &ieee->current_network; + + if (ieee->pHTInfo->bCurrentHTSupport) + HTUpdateSelfAndPeerSetting(ieee, net); + ieee->pHTInfo->bCurrentRT2RTLongSlotTime = net->bssht.bdRT2RTLongSlotTime; + // Joseph test for turbo mode with AP + ieee->pHTInfo->RT2RT_HT_Mode = net->bssht.RT2RT_HT_Mode; + rtl8192_update_cap(dev, net->capability); +} +/* +* background support to run QoS activate functionality +*/ +int WDCAPARA_ADD[] = {EDCAPARA_BE,EDCAPARA_BK,EDCAPARA_VI,EDCAPARA_VO}; +#if LINUX_VERSION_CODE >=KERNEL_VERSION(2,6,20) +void rtl8192_qos_activate(struct work_struct * work) +{ + struct r8192_priv *priv = container_of(work, struct r8192_priv, qos_activate); + struct net_device *dev = priv->ieee80211->dev; +#else +void rtl8192_qos_activate(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); +#endif + struct ieee80211_qos_parameters *qos_parameters = &priv->ieee80211->current_network.qos_data.parameters; + u8 mode = priv->ieee80211->current_network.mode; + //u32 size = sizeof(struct ieee80211_qos_parameters); + u8 u1bAIFS; + u32 u4bAcParam; + int i; + + if (priv == NULL) + return; + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,16)) + down(&priv->mutex); +#else + mutex_lock(&priv->mutex); +#endif + if(priv->ieee80211->state != IEEE80211_LINKED) + goto success; + RT_TRACE(COMP_QOS,"qos active process with associate response received\n"); + /* It better set slot time at first */ + /* For we just support b/g mode at present, let the slot time at 9/20 selection */ + /* update the ac parameter to related registers */ + for(i = 0; i < QOS_QUEUE_NUM; i++) { + //Mode G/A: slotTimeTimer = 9; Mode B: 20 + u1bAIFS = qos_parameters->aifs[i] * ((mode&(IEEE_G|IEEE_N_24G)) ?9:20) + aSifsTime; + u4bAcParam = ((((u32)(qos_parameters->tx_op_limit[i]))<< AC_PARAM_TXOP_LIMIT_OFFSET)| + (((u32)(qos_parameters->cw_max[i]))<< AC_PARAM_ECW_MAX_OFFSET)| + (((u32)(qos_parameters->cw_min[i]))<< AC_PARAM_ECW_MIN_OFFSET)| + ((u32)u1bAIFS << AC_PARAM_AIFS_OFFSET)); + + write_nic_dword(dev, WDCAPARA_ADD[i], u4bAcParam); + //write_nic_dword(dev, WDCAPARA_ADD[i], 0x005e4322); + } + +success: +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,16)) + up(&priv->mutex); +#else + mutex_unlock(&priv->mutex); +#endif +} + +static int rtl8192_qos_handle_probe_response(struct r8192_priv *priv, + int active_network, + struct ieee80211_network *network) +{ + int ret = 0; + u32 size = sizeof(struct ieee80211_qos_parameters); + + if(priv->ieee80211->state !=IEEE80211_LINKED) + return ret; + + if ((priv->ieee80211->iw_mode != IW_MODE_INFRA)) + return ret; + + if (network->flags & NETWORK_HAS_QOS_MASK) { + if (active_network && + (network->flags & NETWORK_HAS_QOS_PARAMETERS)) + network->qos_data.active = network->qos_data.supported; + + if ((network->qos_data.active == 1) && (active_network == 1) && + (network->flags & NETWORK_HAS_QOS_PARAMETERS) && + (network->qos_data.old_param_count != + network->qos_data.param_count)) { + network->qos_data.old_param_count = + network->qos_data.param_count; +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + queue_work(priv->priv_wq, &priv->qos_activate); +#else + schedule_task(&priv->qos_activate); +#endif + RT_TRACE (COMP_QOS, "QoS parameters change call " + "qos_activate\n"); + } + } else { + memcpy(&priv->ieee80211->current_network.qos_data.parameters,\ + &def_qos_parameters, size); + + if ((network->qos_data.active == 1) && (active_network == 1)) { +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + queue_work(priv->priv_wq, &priv->qos_activate); +#else + schedule_task(&priv->qos_activate); +#endif + RT_TRACE(COMP_QOS, "QoS was disabled call qos_activate \n"); + } + network->qos_data.active = 0; + network->qos_data.supported = 0; + } + + return 0; +} + +/* handle manage frame frame beacon and probe response */ +static int rtl8192_handle_beacon(struct net_device * dev, + struct ieee80211_beacon * beacon, + struct ieee80211_network * network) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + + rtl8192_qos_handle_probe_response(priv,1,network); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + queue_delayed_work(priv->priv_wq, &priv->update_beacon_wq, 0); +#else +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) + schedule_task(&priv->update_beacon_wq); +#else + queue_work(priv->priv_wq, &priv->update_beacon_wq); +#endif + +#endif + return 0; + +} + +/* +* handling the beaconing responses. if we get different QoS setting +* off the network from the associated setting, adjust the QoS +* setting +*/ +static int rtl8192_qos_association_resp(struct r8192_priv *priv, + struct ieee80211_network *network) +{ + int ret = 0; + unsigned long flags; + u32 size = sizeof(struct ieee80211_qos_parameters); + int set_qos_param = 0; + + if ((priv == NULL) || (network == NULL)) + return ret; + + if(priv->ieee80211->state !=IEEE80211_LINKED) + return ret; + + if ((priv->ieee80211->iw_mode != IW_MODE_INFRA)) + return ret; + + spin_lock_irqsave(&priv->ieee80211->lock, flags); + if(network->flags & NETWORK_HAS_QOS_PARAMETERS) { + memcpy(&priv->ieee80211->current_network.qos_data.parameters,\ + &network->qos_data.parameters,\ + sizeof(struct ieee80211_qos_parameters)); + priv->ieee80211->current_network.qos_data.active = 1; +#if 0 + if((priv->ieee80211->current_network.qos_data.param_count != \ + network->qos_data.param_count)) +#endif + { + set_qos_param = 1; + /* update qos parameter for current network */ + priv->ieee80211->current_network.qos_data.old_param_count = \ + priv->ieee80211->current_network.qos_data.param_count; + priv->ieee80211->current_network.qos_data.param_count = \ + network->qos_data.param_count; + } + } else { + memcpy(&priv->ieee80211->current_network.qos_data.parameters,\ + &def_qos_parameters, size); + priv->ieee80211->current_network.qos_data.active = 0; + priv->ieee80211->current_network.qos_data.supported = 0; + set_qos_param = 1; + } + + spin_unlock_irqrestore(&priv->ieee80211->lock, flags); + + RT_TRACE(COMP_QOS, "%s: network->flags = %d,%d\n",__FUNCTION__,network->flags ,priv->ieee80211->current_network.qos_data.active); + if (set_qos_param == 1) +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + queue_work(priv->priv_wq, &priv->qos_activate); +#else + schedule_task(&priv->qos_activate); +#endif + + + return ret; +} + + +static int rtl8192_handle_assoc_response(struct net_device *dev, + struct ieee80211_assoc_response_frame *resp, + struct ieee80211_network *network) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + rtl8192_qos_association_resp(priv, network); + return 0; +} + + +void rtl8192_update_ratr_table(struct net_device* dev) + // POCTET_STRING posLegacyRate, + // u8* pMcsRate) + // PRT_WLAN_STA pEntry) +{ + struct r8192_priv* priv = ieee80211_priv(dev); + struct ieee80211_device* ieee = priv->ieee80211; + u8* pMcsRate = ieee->dot11HTOperationalRateSet; + //struct ieee80211_network *net = &ieee->current_network; + u32 ratr_value = 0; + u8 rate_index = 0; + rtl8192_config_rate(dev, (u16*)(&ratr_value)); + ratr_value |= (*(u16*)(pMcsRate)) << 12; +// switch (net->mode) + switch (ieee->mode) + { + case IEEE_A: + ratr_value &= 0x00000FF0; + break; + case IEEE_B: + ratr_value &= 0x0000000F; + break; + case IEEE_G: + ratr_value &= 0x00000FF7; + break; + case IEEE_N_24G: + case IEEE_N_5G: + if (ieee->pHTInfo->PeerMimoPs == 0) //MIMO_PS_STATIC + ratr_value &= 0x0007F007; + else{ + if (priv->rf_type == RF_1T2R) + ratr_value &= 0x000FF007; + else + ratr_value &= 0x0F81F007; + } + break; + default: + break; + } + ratr_value &= 0x0FFFFFFF; + if(ieee->pHTInfo->bCurTxBW40MHz && ieee->pHTInfo->bCurShortGI40MHz){ + ratr_value |= 0x80000000; + }else if(!ieee->pHTInfo->bCurTxBW40MHz && ieee->pHTInfo->bCurShortGI20MHz){ + ratr_value |= 0x80000000; + } + write_nic_dword(dev, RATR0+rate_index*4, ratr_value); + write_nic_byte(dev, UFWP, 1); +} + +static u8 ccmp_ie[4] = {0x00,0x50,0xf2,0x04}; +static u8 ccmp_rsn_ie[4] = {0x00, 0x0f, 0xac, 0x04}; +bool GetNmodeSupportBySecCfg8192(struct net_device*dev) +{ +#if 1 + struct r8192_priv* priv = ieee80211_priv(dev); + struct ieee80211_device* ieee = priv->ieee80211; + struct ieee80211_network * network = &ieee->current_network; + int wpa_ie_len= ieee->wpa_ie_len; + struct ieee80211_crypt_data* crypt; + int encrypt; +#if (defined (RTL8192SU_FPGA_2MAC_VERIFICATION)||defined (RTL8192SU_ASIC_VERIFICATION)) + return TRUE; +#endif + + crypt = ieee->crypt[ieee->tx_keyidx]; + //we use connecting AP's capability instead of only security config on our driver to distinguish whether it should use N mode or G mode + encrypt = (network->capability & WLAN_CAPABILITY_PRIVACY) || (ieee->host_encrypt && crypt && crypt->ops && (0 == strcmp(crypt->ops->name,"WEP"))); + + /* simply judge */ + if(encrypt && (wpa_ie_len == 0)) { + /* wep encryption, no N mode setting */ + return false; +// } else if((wpa_ie_len != 0)&&(memcmp(&(ieee->wpa_ie[14]),ccmp_ie,4))) { + } else if((wpa_ie_len != 0)) { + /* parse pairwise key type */ + //if((pairwisekey = WEP40)||(pairwisekey = WEP104)||(pairwisekey = TKIP)) + if (((ieee->wpa_ie[0] == 0xdd) && (!memcmp(&(ieee->wpa_ie[14]),ccmp_ie,4))) || ((ieee->wpa_ie[0] == 0x30) && (!memcmp(&ieee->wpa_ie[10],ccmp_rsn_ie, 4)))) + return true; + else + return false; + } else { + return true; + } + +#if 0 + //In here we discuss with SD4 David. He think we still can send TKIP in broadcast group key in MCS rate. + //We can't force in G mode if Pairwie key is AES and group key is TKIP + if((pSecInfo->GroupEncAlgorithm == WEP104_Encryption) || (pSecInfo->GroupEncAlgorithm == WEP40_Encryption) || + (pSecInfo->PairwiseEncAlgorithm == WEP104_Encryption) || + (pSecInfo->PairwiseEncAlgorithm == WEP40_Encryption) || (pSecInfo->PairwiseEncAlgorithm == TKIP_Encryption)) + { + return false; + } + else + return true; +#endif + return true; +#endif +} + +bool GetHalfNmodeSupportByAPs819xUsb(struct net_device* dev) +{ + bool Reval; + struct r8192_priv* priv = ieee80211_priv(dev); + struct ieee80211_device* ieee = priv->ieee80211; + +// Added by Roger, 2008.08.29. +#ifdef RTL8192SU + return false; +#endif + + if(ieee->bHalfWirelessN24GMode == true) + Reval = true; + else + Reval = false; + + return Reval; +} + +void rtl8192_refresh_supportrate(struct r8192_priv* priv) +{ + struct ieee80211_device* ieee = priv->ieee80211; + //we donot consider set support rate for ABG mode, only HT MCS rate is set here. + if (ieee->mode == WIRELESS_MODE_N_24G || ieee->mode == WIRELESS_MODE_N_5G) + { + memcpy(ieee->Regdot11HTOperationalRateSet, ieee->RegHTSuppRateSet, 16); + //RT_DEBUG_DATA(COMP_INIT, ieee->RegHTSuppRateSet, 16); + //RT_DEBUG_DATA(COMP_INIT, ieee->Regdot11HTOperationalRateSet, 16); + } + else + memset(ieee->Regdot11HTOperationalRateSet, 0, 16); + return; +} + +u8 rtl8192_getSupportedWireleeMode(struct net_device*dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + u8 ret = 0; + switch(priv->rf_chip) + { + case RF_8225: + case RF_8256: + case RF_PSEUDO_11N: + case RF_6052: + ret = (WIRELESS_MODE_N_24G|WIRELESS_MODE_G|WIRELESS_MODE_B); + break; + case RF_8258: + ret = (WIRELESS_MODE_A|WIRELESS_MODE_N_5G); + break; + default: + ret = WIRELESS_MODE_B; + break; + } + return ret; +} +void rtl8192_SetWirelessMode(struct net_device* dev, u8 wireless_mode) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + u8 bSupportMode = rtl8192_getSupportedWireleeMode(dev); + +#if 1 + if ((wireless_mode == WIRELESS_MODE_AUTO) || ((wireless_mode&bSupportMode)==0)) + { + if(bSupportMode & WIRELESS_MODE_N_24G) + { + wireless_mode = WIRELESS_MODE_N_24G; + } + else if(bSupportMode & WIRELESS_MODE_N_5G) + { + wireless_mode = WIRELESS_MODE_N_5G; + } + else if((bSupportMode & WIRELESS_MODE_A)) + { + wireless_mode = WIRELESS_MODE_A; + } + else if((bSupportMode & WIRELESS_MODE_G)) + { + wireless_mode = WIRELESS_MODE_G; + } + else if((bSupportMode & WIRELESS_MODE_B)) + { + wireless_mode = WIRELESS_MODE_B; + } + else{ + RT_TRACE(COMP_ERR, "%s(), No valid wireless mode supported, SupportedWirelessMode(%x)!!!\n", __FUNCTION__,bSupportMode); + wireless_mode = WIRELESS_MODE_B; + } + } +#ifdef TO_DO_LIST //// TODO: this function doesn't work well at this time, we shoud wait for FPGA + ActUpdateChannelAccessSetting( pAdapter, pHalData->CurrentWirelessMode, &pAdapter->MgntInfo.Info8185.ChannelAccessSetting ); +#endif +#ifdef RTL8192SU + //LZM 090306 usb crash here, mark it temp + //write_nic_word(dev, SIFS_OFDM, 0x0e0e); +#endif + priv->ieee80211->mode = wireless_mode; + + if ((wireless_mode == WIRELESS_MODE_N_24G) || (wireless_mode == WIRELESS_MODE_N_5G)) + priv->ieee80211->pHTInfo->bEnableHT = 1; + else + priv->ieee80211->pHTInfo->bEnableHT = 0; + RT_TRACE(COMP_INIT, "Current Wireless Mode is %x\n", wireless_mode); + rtl8192_refresh_supportrate(priv); +#endif + +} + + +short rtl8192_is_tx_queue_empty(struct net_device *dev) +{ + int i=0; + struct r8192_priv *priv = ieee80211_priv(dev); + //struct ieee80211_device* ieee = priv->ieee80211; + for (i=0; i<=MGNT_QUEUE; i++) + { + if ((i== TXCMD_QUEUE) || (i == HCCA_QUEUE) ) + continue; + if (atomic_read(&priv->tx_pending[i])) + { + printk("===>tx queue is not empty:%d, %d\n", i, atomic_read(&priv->tx_pending[i])); + return 0; + } + } + return 1; +} +#if 0 +void rtl8192_rq_tx_ack(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + priv->ieee80211->ack_tx_to_ieee = 1; +} +#endif +void rtl8192_hw_sleep_down(struct net_device *dev) +{ + RT_TRACE(COMP_POWER, "%s()============>come to sleep down\n", __FUNCTION__); +#ifdef TODO +// MgntActSet_RF_State(dev, eRfSleep, RF_CHANGE_BY_PS); +#endif +} +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) +void rtl8192_hw_sleep_wq (struct work_struct *work) +{ +// struct r8180_priv *priv = container_of(work, struct r8180_priv, watch_dog_wq); +// struct ieee80211_device * ieee = (struct ieee80211_device*) +// container_of(work, struct ieee80211_device, watch_dog_wq); + struct delayed_work *dwork = container_of(work,struct delayed_work,work); + struct ieee80211_device *ieee = container_of(dwork,struct ieee80211_device,hw_sleep_wq); + struct net_device *dev = ieee->dev; +#else +void rtl8192_hw_sleep_wq(struct net_device* dev) +{ +#endif + //printk("=========>%s()\n", __FUNCTION__); + rtl8192_hw_sleep_down(dev); +} +// printk("dev is %d\n",dev); +// printk("&*&(^*(&(&=========>%s()\n", __FUNCTION__); +void rtl8192_hw_wakeup(struct net_device* dev) +{ +// u32 flags = 0; + +// spin_lock_irqsave(&priv->ps_lock,flags); + RT_TRACE(COMP_POWER, "%s()============>come to wake up\n", __FUNCTION__); +#ifdef TODO +// MgntActSet_RF_State(dev, eRfSleep, RF_CHANGE_BY_PS); +#endif + //FIXME: will we send package stored while nic is sleep? +// spin_unlock_irqrestore(&priv->ps_lock,flags); +} +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) +void rtl8192_hw_wakeup_wq (struct work_struct *work) +{ +// struct r8180_priv *priv = container_of(work, struct r8180_priv, watch_dog_wq); +// struct ieee80211_device * ieee = (struct ieee80211_device*) +// container_of(work, struct ieee80211_device, watch_dog_wq); + struct delayed_work *dwork = container_of(work,struct delayed_work,work); + struct ieee80211_device *ieee = container_of(dwork,struct ieee80211_device,hw_wakeup_wq); + struct net_device *dev = ieee->dev; +#else +void rtl8192_hw_wakeup_wq(struct net_device* dev) +{ +#endif + rtl8192_hw_wakeup(dev); + +} + +#define MIN_SLEEP_TIME 50 +#define MAX_SLEEP_TIME 10000 +void rtl8192_hw_to_sleep(struct net_device *dev, u32 th, u32 tl) +{ + + struct r8192_priv *priv = ieee80211_priv(dev); + + u32 rb = jiffies; + unsigned long flags; + + spin_lock_irqsave(&priv->ps_lock,flags); + + /* Writing HW register with 0 equals to disable + * the timer, that is not really what we want + */ + tl -= MSECS(4+16+7); + + //if(tl == 0) tl = 1; + + /* FIXME HACK FIXME HACK */ +// force_pci_posting(dev); + //mdelay(1); + +// rb = read_nic_dword(dev, TSFTR); + + /* If the interval in witch we are requested to sleep is too + * short then give up and remain awake + */ + if(((tl>=rb)&& (tl-rb) <= MSECS(MIN_SLEEP_TIME)) + ||((rb>tl)&& (rb-tl) < MSECS(MIN_SLEEP_TIME))) { + spin_unlock_irqrestore(&priv->ps_lock,flags); + printk("too short to sleep\n"); + return; + } + +// write_nic_dword(dev, TimerInt, tl); +// rb = read_nic_dword(dev, TSFTR); + { + u32 tmp = (tl>rb)?(tl-rb):(rb-tl); + // if (tl<rb) + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) + schedule_task(&priv->ieee80211->hw_wakeup_wq); +#else + queue_delayed_work(priv->ieee80211->wq, &priv->ieee80211->hw_wakeup_wq, tmp); //as tl may be less than rb +#endif + } + /* if we suspect the TimerInt is gone beyond tl + * while setting it, then give up + */ +#if 1 + if(((tl > rb) && ((tl-rb) > MSECS(MAX_SLEEP_TIME)))|| + ((tl < rb) && ((rb-tl) > MSECS(MAX_SLEEP_TIME)))) { + printk("========>too long to sleep:%x, %x, %lx\n", tl, rb, MSECS(MAX_SLEEP_TIME)); + spin_unlock_irqrestore(&priv->ps_lock,flags); + return; + } +#endif +// if(priv->rf_sleep) +// priv->rf_sleep(dev); + + //printk("<=========%s()\n", __FUNCTION__); +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) + schedule_task(&priv->ieee80211->hw_sleep_wq); +#else + queue_delayed_work(priv->ieee80211->wq, (void *)&priv->ieee80211->hw_sleep_wq,0); +#endif + spin_unlock_irqrestore(&priv->ps_lock,flags); +} +//init priv variables here. only non_zero value should be initialized here. +static void rtl8192_init_priv_variable(struct net_device* dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + u8 i; + priv->card_8192 = NIC_8192U; + priv->chan = 1; //set to channel 1 + priv->ieee80211->mode = WIRELESS_MODE_AUTO; //SET AUTO + priv->ieee80211->iw_mode = IW_MODE_INFRA; + priv->ieee80211->ieee_up=0; + priv->retry_rts = DEFAULT_RETRY_RTS; + priv->retry_data = DEFAULT_RETRY_DATA; + priv->ieee80211->rts = DEFAULT_RTS_THRESHOLD; + priv->ieee80211->rate = 110; //11 mbps + priv->ieee80211->short_slot = 1; + priv->promisc = (dev->flags & IFF_PROMISC) ? 1:0; + priv->CckPwEnl = 6; + //for silent reset + priv->IrpPendingCount = 1; + priv->ResetProgress = RESET_TYPE_NORESET; + priv->bForcedSilentReset = 0; + priv->bDisableNormalResetCheck = false; + priv->force_reset = false; + + priv->ieee80211->FwRWRF = 0; //we don't use FW read/write RF until stable firmware is available. + priv->ieee80211->current_network.beacon_interval = DEFAULT_BEACONINTERVAL; + priv->ieee80211->iw_mode = IW_MODE_INFRA; + priv->ieee80211->softmac_features = IEEE_SOFTMAC_SCAN | + IEEE_SOFTMAC_ASSOCIATE | IEEE_SOFTMAC_PROBERQ | + IEEE_SOFTMAC_PROBERS | IEEE_SOFTMAC_TX_QUEUE | + IEEE_SOFTMAC_BEACONS;//added by amy 080604 //| //IEEE_SOFTMAC_SINGLE_QUEUE; + + priv->ieee80211->active_scan = 1; + priv->ieee80211->modulation = IEEE80211_CCK_MODULATION | IEEE80211_OFDM_MODULATION; + priv->ieee80211->host_encrypt = 1; + priv->ieee80211->host_decrypt = 1; + priv->ieee80211->start_send_beacons = NULL;//rtl819xusb_beacon_tx;//-by amy 080604 + priv->ieee80211->stop_send_beacons = NULL;//rtl8192_beacon_stop;//-by amy 080604 + priv->ieee80211->softmac_hard_start_xmit = rtl8192_hard_start_xmit; + priv->ieee80211->set_chan = rtl8192_set_chan; + priv->ieee80211->link_change = priv->ops->rtl819x_link_change; + priv->ieee80211->softmac_data_hard_start_xmit = rtl8192_hard_data_xmit; + priv->ieee80211->data_hard_stop = rtl8192_data_hard_stop; + priv->ieee80211->data_hard_resume = rtl8192_data_hard_resume; + priv->ieee80211->init_wmmparam_flag = 0; + priv->ieee80211->fts = DEFAULT_FRAG_THRESHOLD; + priv->ieee80211->check_nic_enough_desc = check_nic_enough_desc; + priv->ieee80211->tx_headroom = TX_PACKET_SHIFT_BYTES; + priv->ieee80211->qos_support = 1; + + //added by WB +// priv->ieee80211->SwChnlByTimerHandler = rtl8192_phy_SwChnl; + priv->ieee80211->SetBWModeHandler = rtl8192_SetBWMode; + priv->ieee80211->handle_assoc_response = rtl8192_handle_assoc_response; + priv->ieee80211->handle_beacon = rtl8192_handle_beacon; + //for LPS + priv->ieee80211->sta_wake_up = rtl8192_hw_wakeup; +// priv->ieee80211->ps_request_tx_ack = rtl8192_rq_tx_ack; + priv->ieee80211->enter_sleep_state = rtl8192_hw_to_sleep; + priv->ieee80211->ps_is_queue_empty = rtl8192_is_tx_queue_empty; + //added by david + priv->ieee80211->GetNmodeSupportBySecCfg = GetNmodeSupportBySecCfg8192; + priv->ieee80211->GetHalfNmodeSupportByAPsHandler = GetHalfNmodeSupportByAPs819xUsb; + priv->ieee80211->SetWirelessMode = rtl8192_SetWirelessMode; + //added by amy + priv->ieee80211->InitialGainHandler = priv->ops->rtl819x_initial_gain; + priv->card_type = USB; + +#ifdef RTL8192SU +//1 RTL8192SU/ + priv->ieee80211->current_network.beacon_interval = DEFAULT_BEACONINTERVAL; + priv->ieee80211->SetFwCmdHandler = HalSetFwCmd8192S; + priv->bRFSiOrPi = 0;//o=si,1=pi; + //lzm add + priv->bInHctTest = false; + + priv->MidHighPwrTHR_L1 = 0x3B; + priv->MidHighPwrTHR_L2 = 0x40; + + if(priv->bInHctTest) + { + priv->ShortRetryLimit = HAL_RETRY_LIMIT_AP_ADHOC; + priv->LongRetryLimit = HAL_RETRY_LIMIT_AP_ADHOC; + } + else + { + priv->ShortRetryLimit = HAL_RETRY_LIMIT_INFRA; + priv->LongRetryLimit = HAL_RETRY_LIMIT_INFRA; + } + + priv->SetFwCmdInProgress = false; //is set FW CMD in Progress? 92S only + priv->CurrentFwCmdIO = 0; + + priv->MinSpaceCfg = 0; + + priv->EarlyRxThreshold = 7; + priv->enable_gpio0 = 0; + priv->TransmitConfig = + ((u32)TCR_MXDMA_2048<<TCR_MXDMA_OFFSET) | // Max DMA Burst Size per Tx DMA Burst, 7: reservied. + (priv->ShortRetryLimit<<TCR_SRL_OFFSET) | // Short retry limit + (priv->LongRetryLimit<<TCR_LRL_OFFSET) | // Long retry limit + (false ? TCR_SAT : 0); // FALSE: HW provies PLCP length and LENGEXT, TURE: SW proiveds them + if(priv->bInHctTest) + priv->ReceiveConfig = //priv->CSMethod | + RCR_AMF | RCR_ADF | //RCR_AAP | //accept management/data + RCR_ACF |RCR_APPFCS| //accept control frame for SW AP needs PS-poll, 2005.07.07, by rcnjko. + RCR_AB | RCR_AM | RCR_APM | //accept BC/MC/UC + RCR_AICV | RCR_ACRC32 | //accept ICV/CRC error packet + RCR_APP_PHYST_STAFF | RCR_APP_PHYST_RXFF | // Accept PHY status + ((u32)7<<RCR_MXDMA_OFFSET) | // Max DMA Burst Size per Rx DMA Burst, 7: unlimited. + (priv->EarlyRxThreshold<<RCR_FIFO_OFFSET) | // Rx FIFO Threshold, 7: No Rx threshold. + (priv->EarlyRxThreshold == 7 ? RCR_OnlyErlPkt:0); + else + priv->ReceiveConfig = //priv->CSMethod | + RCR_AMF | RCR_ADF | RCR_AB | + RCR_AM | RCR_APM |RCR_AAP |RCR_ADD3|RCR_APP_ICV| + RCR_APP_PHYST_STAFF | RCR_APP_PHYST_RXFF | // Accept PHY status + RCR_APP_MIC | RCR_APPFCS; + + // <Roger_EXP> 2008.06.16. + priv->IntrMask = (u16)(IMR_ROK | IMR_VODOK | IMR_VIDOK | IMR_BEDOK | IMR_BKDOK | \ + IMR_HCCADOK | IMR_MGNTDOK | IMR_COMDOK | IMR_HIGHDOK | \ + IMR_BDOK | IMR_RXCMDOK | /*IMR_TIMEOUT0 |*/ IMR_RDU | IMR_RXFOVW | \ + IMR_TXFOVW | IMR_BcnInt | IMR_TBDOK | IMR_TBDER); + +//1 End + +#else + +#ifdef TO_DO_LIST + if(Adapter->bInHctTest) + { + pHalData->ShortRetryLimit = 7; + pHalData->LongRetryLimit = 7; + } +#endif + { + priv->ShortRetryLimit = 0x30; + priv->LongRetryLimit = 0x30; + } + priv->EarlyRxThreshold = 7; + priv->enable_gpio0 = 0; + priv->TransmitConfig = + // TCR_DurProcMode | //for RTL8185B, duration setting by HW + //? TCR_DISReqQsize | + (TCR_MXDMA_2048<<TCR_MXDMA_OFFSET)| // Max DMA Burst Size per Tx DMA Burst, 7: reservied. + (priv->ShortRetryLimit<<TCR_SRL_OFFSET)| // Short retry limit + (priv->LongRetryLimit<<TCR_LRL_OFFSET) | // Long retry limit + (false ? TCR_SAT: 0); // FALSE: HW provies PLCP length and LENGEXT, TURE: SW proiveds them +#ifdef TO_DO_LIST + if(Adapter->bInHctTest) + pHalData->ReceiveConfig = pHalData->CSMethod | + RCR_AMF | RCR_ADF | //RCR_AAP | //accept management/data + //guangan200710 + RCR_ACF | //accept control frame for SW AP needs PS-poll, 2005.07.07, by rcnjko. + RCR_AB | RCR_AM | RCR_APM | //accept BC/MC/UC + RCR_AICV | RCR_ACRC32 | //accept ICV/CRC error packet + ((u32)7<<RCR_MXDMA_OFFSET) | // Max DMA Burst Size per Rx DMA Burst, 7: unlimited. + (pHalData->EarlyRxThreshold<<RCR_FIFO_OFFSET) | // Rx FIFO Threshold, 7: No Rx threshold. + (pHalData->EarlyRxThreshold == 7 ? RCR_OnlyErlPkt:0); + else + +#endif + priv->ReceiveConfig = + RCR_AMF | RCR_ADF | //accept management/data + RCR_ACF | //accept control frame for SW AP needs PS-poll, 2005.07.07, by rcnjko. + RCR_AB | RCR_AM | RCR_APM | //accept BC/MC/UC + //RCR_AICV | RCR_ACRC32 | //accept ICV/CRC error packet + ((u32)7<<RCR_MXDMA_OFFSET)| // Max DMA Burst Size per Rx DMA Burst, 7: unlimited. + (priv->EarlyRxThreshold<<RX_FIFO_THRESHOLD_SHIFT) | // Rx FIFO Threshold, 7: No Rx threshold. + (priv->EarlyRxThreshold == 7 ? RCR_ONLYERLPKT:0); +#endif + + priv->AcmControl = 0; + priv->pFirmware = (rt_firmware*)vmalloc(sizeof(rt_firmware)); + if (priv->pFirmware) + memset(priv->pFirmware, 0, sizeof(rt_firmware)); + + /* rx related queue */ + skb_queue_head_init(&priv->rx_queue); + skb_queue_head_init(&priv->skb_queue); + + /* Tx related queue */ + for(i = 0; i < MAX_QUEUE_SIZE; i++) { + skb_queue_head_init(&priv->ieee80211->skb_waitQ [i]); + } + for(i = 0; i < MAX_QUEUE_SIZE; i++) { + skb_queue_head_init(&priv->ieee80211->skb_aggQ [i]); + } + for(i = 0; i < MAX_QUEUE_SIZE; i++) { + skb_queue_head_init(&priv->ieee80211->skb_drv_aggQ [i]); + } + priv->rf_set_chan = rtl8192_phy_SwChnl; +} + +//init lock here +static void rtl8192_init_priv_lock(struct r8192_priv* priv) +{ + spin_lock_init(&priv->tx_lock); + spin_lock_init(&priv->irq_lock);//added by thomas + //spin_lock_init(&priv->rf_lock);//use rf_sem, or will crash in some OS. + sema_init(&priv->wx_sem,1); + sema_init(&priv->rf_sem,1); + spin_lock_init(&priv->ps_lock); +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,16)) + sema_init(&priv->mutex, 1); +#else + mutex_init(&priv->mutex); +#endif +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) +extern void rtl819x_watchdog_wqcallback(struct work_struct *work); +#else +extern void rtl819x_watchdog_wqcallback(struct net_device *dev); +#endif + +void rtl8192_irq_rx_tasklet(struct r8192_priv *priv); +//init tasklet and wait_queue here. only 2.6 above kernel is considered +#define DRV_NAME "wlan0" +static void rtl8192_init_priv_task(struct net_device* dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) +#ifdef PF_SYNCTHREAD + priv->priv_wq = create_workqueue(DRV_NAME,0); +#else + priv->priv_wq = create_workqueue(DRV_NAME); +#endif +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) + INIT_WORK(&priv->reset_wq, rtl8192_restart); + + //INIT_DELAYED_WORK(&priv->watch_dog_wq, hal_dm_watchdog); + INIT_DELAYED_WORK(&priv->watch_dog_wq, rtl819x_watchdog_wqcallback); + INIT_DELAYED_WORK(&priv->txpower_tracking_wq, dm_txpower_trackingcallback); +// INIT_DELAYED_WORK(&priv->gpio_change_rf_wq, dm_gpio_change_rf_callback); + INIT_DELAYED_WORK(&priv->rfpath_check_wq, dm_rf_pathcheck_workitemcallback); + INIT_DELAYED_WORK(&priv->update_beacon_wq, rtl8192_update_beacon); + INIT_DELAYED_WORK(&priv->initialgain_operate_wq, InitialGainOperateWorkItemCallBack); + //INIT_WORK(&priv->SwChnlWorkItem, rtl8192_SwChnl_WorkItem); + //INIT_WORK(&priv->SetBWModeWorkItem, rtl8192_SetBWModeWorkItem); + INIT_WORK(&priv->qos_activate, rtl8192_qos_activate); + INIT_DELAYED_WORK(&priv->ieee80211->hw_wakeup_wq,(void*) rtl8192_hw_wakeup_wq); + INIT_DELAYED_WORK(&priv->ieee80211->hw_sleep_wq,(void*) rtl8192_hw_sleep_wq); + +#else +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)) + tq_init(&priv->reset_wq, (void*)rtl8192_restart, dev); + tq_init(&priv->watch_dog_wq, (void*)rtl819x_watchdog_wqcallback, dev); + tq_init(&priv->txpower_tracking_wq, (void*)dm_txpower_trackingcallback, dev); + tq_init(&priv->rfpath_check_wq, (void*)dm_rf_pathcheck_workitemcallback, dev); + tq_init(&priv->update_beacon_wq, (void*)rtl8192_update_beacon, dev); + //tq_init(&priv->SwChnlWorkItem, (void*) rtl8192_SwChnl_WorkItem, dev); + //tq_init(&priv->SetBWModeWorkItem, (void*)rtl8192_SetBWModeWorkItem, dev); + tq_init(&priv->qos_activate, (void *)rtl8192_qos_activate, dev); + tq_init(&priv->ieee80211->hw_wakeup_wq,(void*) rtl8192_hw_wakeup_wq, dev); + tq_init(&priv->ieee80211->hw_sleep_wq,(void*) rtl8192_hw_sleep_wq, dev); + +#else + INIT_WORK(&priv->reset_wq,(void(*)(void*)) rtl8192_restart,dev); + //INIT_WORK(&priv->watch_dog_wq, (void(*)(void*)) hal_dm_watchdog,dev); + INIT_WORK(&priv->watch_dog_wq, (void(*)(void*)) rtl819x_watchdog_wqcallback,dev); + INIT_WORK(&priv->txpower_tracking_wq, (void(*)(void*)) dm_txpower_trackingcallback,dev); +// INIT_WORK(&priv->gpio_change_rf_wq, (void(*)(void*)) dm_gpio_change_rf_callback,dev); + INIT_WORK(&priv->rfpath_check_wq, (void(*)(void*)) dm_rf_pathcheck_workitemcallback,dev); + INIT_WORK(&priv->update_beacon_wq, (void(*)(void*))rtl8192_update_beacon,dev); + INIT_WORK(&priv->initialgain_operate_wq, (void(*)(void*))InitialGainOperateWorkItemCallBack,dev); + //INIT_WORK(&priv->SwChnlWorkItem, (void(*)(void*)) rtl8192_SwChnl_WorkItem, dev); + //INIT_WORK(&priv->SetBWModeWorkItem, (void(*)(void*)) rtl8192_SetBWModeWorkItem, dev); + INIT_WORK(&priv->qos_activate, (void(*)(void *))rtl8192_qos_activate, dev); + INIT_WORK(&priv->ieee80211->hw_wakeup_wq,(void*) rtl8192_hw_wakeup_wq, dev); + INIT_WORK(&priv->ieee80211->hw_sleep_wq,(void*) rtl8192_hw_sleep_wq, dev); +#endif +#endif + + tasklet_init(&priv->irq_rx_tasklet, + (void(*)(unsigned long))rtl8192_irq_rx_tasklet, + (unsigned long)priv); +} + +static void rtl8192_get_eeprom_size(struct net_device* dev) +{ + u16 curCR = 0; + struct r8192_priv *priv = ieee80211_priv(dev); + RT_TRACE(COMP_EPROM, "===========>%s()\n", __FUNCTION__); + curCR = read_nic_word_E(dev,EPROM_CMD); + RT_TRACE(COMP_EPROM, "read from Reg EPROM_CMD(%x):%x\n", EPROM_CMD, curCR); + //whether need I consider BIT5? + priv->epromtype = (curCR & Cmd9346CR_9356SEL) ? EPROM_93c56 : EPROM_93c46; + RT_TRACE(COMP_EPROM, "<===========%s(), epromtype:%d\n", __FUNCTION__, priv->epromtype); +} + +//used to swap endian. as ntohl & htonl are not neccessary to swap endian, so use this instead. +static inline u16 endian_swap(u16* data) +{ + u16 tmp = *data; + *data = (tmp >> 8) | (tmp << 8); + return *data; +} + +#ifdef RTL8192SU +u8 rtl8192SU_UsbOptionToEndPointNumber(u8 UsbOption) +{ + u8 nEndPoint = 0; + switch(UsbOption) + { + case 0: + nEndPoint = 6; + break; + case 1: + nEndPoint = 11; + break; + case 2: + nEndPoint = 4; + break; + default: + RT_TRACE(COMP_INIT, "UsbOptionToEndPointNumber(): Invalid UsbOption(%#x)\n", UsbOption); + break; + } + return nEndPoint; +} + +u8 rtl8192SU_BoardTypeToRFtype(struct net_device* dev, u8 Boardtype) +{ + u8 RFtype = RF_1T2R; + + switch(Boardtype) + { + case 0: + RFtype = RF_1T1R; + break; + case 1: + RFtype = RF_1T2R; + break; + case 2: + RFtype = RF_2T2R; + break; + case 3: + RFtype = RF_2T2R_GREEN; + break; + default: + break; + } + + return RFtype; +} + +// +// Description: +// Config HW adapter information into initial value. +// +// Assumption: +// 1. After Auto load fail(i.e, check CR9346 fail) +// +// Created by Roger, 2008.10.21. +// +void +rtl8192SU_ConfigAdapterInfo8192SForAutoLoadFail(struct net_device* dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + //u16 i,usValue; + //u8 sMacAddr[6] = {0x00, 0xE0, 0x4C, 0x81, 0x92, 0x00}; + u8 rf_path, index; // For EEPROM/EFUSE After V0.6_1117 + int i; + + RT_TRACE(COMP_INIT, "====> ConfigAdapterInfo8192SForAutoLoadFail\n"); + + write_nic_byte(dev, SYS_ISO_CTRL+1, 0xE8); // Isolation signals from Loader + //PlatformStallExecution(10000); + mdelay(10); + write_nic_byte(dev, PMC_FSM, 0x02); // Enable Loader Data Keep + + //RT_ASSERT(priv->AutoloadFailFlag==TRUE, ("ReadAdapterInfo8192SEEPROM(): AutoloadFailFlag !=TRUE\n")); + + // Initialize IC Version && Channel Plan + priv->eeprom_vid = 0; + priv->eeprom_pid = 0; + priv->card_8192_version = 0; + priv->eeprom_ChannelPlan = 0; + priv->eeprom_CustomerID = 0; + priv->eeprom_SubCustomerID = 0; + priv->bIgnoreDiffRateTxPowerOffset = false; + + RT_TRACE(COMP_INIT, "EEPROM VID = 0x%4x\n", priv->eeprom_vid); + RT_TRACE(COMP_INIT, "EEPROM PID = 0x%4x\n", priv->eeprom_pid); + RT_TRACE(COMP_INIT, "EEPROM Customer ID: 0x%2x\n", priv->eeprom_CustomerID); + RT_TRACE(COMP_INIT, "EEPROM SubCustomer ID: 0x%2x\n", priv->eeprom_SubCustomerID); + RT_TRACE(COMP_INIT, "EEPROM ChannelPlan = 0x%4x\n", priv->eeprom_ChannelPlan); + RT_TRACE(COMP_INIT, "IgnoreDiffRateTxPowerOffset = %d\n", priv->bIgnoreDiffRateTxPowerOffset); + + + + priv->EEPROMUsbOption = EEPROM_USB_Default_OPTIONAL_FUNC; + RT_TRACE(COMP_INIT, "USB Option = %#x\n", priv->EEPROMUsbOption); + + for(i=0; i<5; i++) + priv->EEPROMUsbPhyParam[i] = EEPROM_USB_Default_PHY_PARAM; + + //RT_PRINT_DATA(COMP_INIT|COMP_EFUSE, DBG_LOUD, ("EFUSE USB PHY Param: \n"), priv->EEPROMUsbPhyParam, 5); + + { + //<Roger_Notes> In this case, we random assigh MAC address here. 2008.10.15. + static u8 sMacAddr[6] = {0x00, 0xE0, 0x4C, 0x81, 0x92, 0x00}; + u8 i; + + //sMacAddr[5] = (u8)GetRandomNumber(1, 254); + + for(i = 0; i < 6; i++) + dev->dev_addr[i] = sMacAddr[i]; + } + //NicIFSetMacAddress(Adapter, Adapter->PermanentAddress); + write_nic_dword(dev, IDR0, ((u32*)dev->dev_addr)[0]); + write_nic_word(dev, IDR4, ((u16*)(dev->dev_addr + 4))[0]); + + RT_TRACE(COMP_INIT, "ReadAdapterInfo8192SEFuse(), Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n", + dev->dev_addr[0], dev->dev_addr[1], + dev->dev_addr[2], dev->dev_addr[3], + dev->dev_addr[4], dev->dev_addr[5]); + + priv->EEPROMBoardType = EEPROM_Default_BoardType; + priv->rf_type = RF_1T2R; //RF_2T2R + priv->EEPROMTxPowerDiff = EEPROM_Default_PwDiff; + priv->EEPROMThermalMeter = EEPROM_Default_ThermalMeter; + priv->EEPROMCrystalCap = EEPROM_Default_CrystalCap; + priv->EEPROMTxPwrBase = EEPROM_Default_TxPowerBase; + priv->EEPROMTSSI_A = EEPROM_Default_TSSI; + priv->EEPROMTSSI_B = EEPROM_Default_TSSI; + priv->EEPROMTxPwrTkMode = EEPROM_Default_TxPwrTkMode; + + +#ifdef EEPROM_OLD_FORMAT_SUPPORT + for(i=0; i<6; i++) + { + priv->EEPROMHT2T_TxPwr[i] = EEPROM_Default_HT2T_TxPwr; + } + + for(i=0; i<14; i++) + { + priv->EEPROMTxPowerLevelCCK24G[i] = (u8)(EEPROM_Default_TxPower & 0xff); + priv->EEPROMTxPowerLevelOFDM24G[i] = (u8)(EEPROM_Default_TxPower & 0xff); + } + + // + // Update HAL variables. + // + memcpy( priv->TxPowerLevelOFDM24G, priv->EEPROMTxPowerLevelOFDM24G, 14); + memcpy( priv->TxPowerLevelCCK, priv->EEPROMTxPowerLevelCCK24G, 14); + //RT_PRINT_DATA(COMP_INIT|COMP_EFUSE, DBG_LOUD, ("HAL CCK 2.4G TxPwr: \n"), priv->TxPowerLevelCCK, 14); + //RT_PRINT_DATA(COMP_INIT|COMP_EFUSE, DBG_LOUD, ("HAL OFDM 2.4G TxPwr: \n"), priv->TxPowerLevelOFDM24G, 14); +#else + + for (rf_path = 0; rf_path < 2; rf_path++) + { + for (i = 0; i < 3; i++) + { + // Read CCK RF A & B Tx power + priv->RfCckChnlAreaTxPwr[rf_path][i] = + priv->RfOfdmChnlAreaTxPwr1T[rf_path][i] = + priv->RfOfdmChnlAreaTxPwr2T[rf_path][i] = + (u8)(EEPROM_Default_TxPower & 0xff); + } + } + + for (i = 0; i < 3; i++) + { + //RT_TRACE((COMP_EFUSE), "CCK RF-%d CHan_Area-%d = 0x%x\n", rf_path, i, + //priv->RfCckChnlAreaTxPwr[rf_path][i]); + //RT_TRACE((COMP_EFUSE), "OFDM-1T RF-%d CHan_Area-%d = 0x%x\n", rf_path, i, + //priv->RfOfdmChnlAreaTxPwr1T[rf_path][i]); + //RT_TRACE((COMP_EFUSE), "OFDM-2T RF-%d CHan_Area-%d = 0x%x\n", rf_path, i, + //priv->RfOfdmChnlAreaTxPwr2T[rf_path][i]); + } + + // Assign dedicated channel tx power + for(i=0; i<14; i++) // channel 1~3 use the same Tx Power Level. + { + if (i < 3) // Cjanel 1-3 + index = 0; + else if (i < 9) // Channel 4-9 + index = 1; + else // Channel 10-14 + index = 2; + + // Record A & B CCK /OFDM - 1T/2T Channel area tx power + priv->RfTxPwrLevelCck[rf_path][i] = + priv->RfCckChnlAreaTxPwr[rf_path][index]; + priv->RfTxPwrLevelOfdm1T[rf_path][i] = + priv->RfOfdmChnlAreaTxPwr1T[rf_path][index]; + priv->RfTxPwrLevelOfdm2T[rf_path][i] = + priv->RfOfdmChnlAreaTxPwr2T[rf_path][index]; + } + + for(i=0; i<14; i++) + { + //RT_TRACE((COMP_EFUSE), "Rf-%d TxPwr CH-%d CCK OFDM_1T OFDM_2T= 0x%x/0x%x/0x%x\n", + //rf_path, i, priv->RfTxPwrLevelCck[0][i], + //priv->RfTxPwrLevelOfdm1T[0][i] , + //priv->RfTxPwrLevelOfdm2T[0][i] ); + } +#endif + + // + // Update remained HAL variables. + // + priv->TSSI_13dBm = priv->EEPROMThermalMeter *100; + priv->LegacyHTTxPowerDiff = priv->EEPROMTxPowerDiff;//new + priv->TxPowerDiff = priv->EEPROMTxPowerDiff; + //priv->AntennaTxPwDiff[0] = (priv->EEPROMTxPowerDiff & 0xf);// Antenna B gain offset to antenna A, bit0~3 + //priv->AntennaTxPwDiff[1] = ((priv->EEPROMTxPowerDiff & 0xf0)>>4);// Antenna C gain offset to antenna A, bit4~7 + priv->CrystalCap = priv->EEPROMCrystalCap; // CrystalCap, bit12~15 + priv->ThermalMeter[0] = priv->EEPROMThermalMeter;// ThermalMeter, bit0~3 for RFIC1, bit4~7 for RFIC2 + priv->LedStrategy = SW_LED_MODE0; + + init_rate_adaptive(dev); + + RT_TRACE(COMP_INIT, "<==== ConfigAdapterInfo8192SForAutoLoadFail\n"); + +} + +#if 0 +static void rtl8192SU_ReadAdapterInfo8192SEEPROM(struct net_device* dev) +{ + u16 EEPROMId = 0; + u8 bLoad_From_EEPOM = false; + struct r8192_priv *priv = ieee80211_priv(dev); + u16 tmpValue = 0; + u8 tmpBuffer[30]; + int i; + + RT_TRACE(COMP_EPROM, "===========>%s()\n", __FUNCTION__); + + + write_nic_byte(dev, SYS_ISO_CTRL+1, 0xE8); // Isolation signals from Loader + udelay(10000); + write_nic_byte(dev, PMC_FSM, 0x02); // Enable Loader Data Keep + + + EEPROMId = eprom_read(dev, 0); //first read EEPROM ID out; + RT_TRACE(COMP_EPROM, "EEPROM ID is 0x%x\n", EEPROMId); + + if (EEPROMId != RTL8190_EEPROM_ID) + { + priv->AutoloadFailFlag = true; + RT_TRACE(COMP_ERR, "EEPROM ID is invalid(is 0x%x(should be 0x%x)\n", EEPROMId, RTL8190_EEPROM_ID); + } + else + { + priv->AutoloadFailFlag = false; + bLoad_From_EEPOM = true; + } + + if (bLoad_From_EEPOM) + { + tmpValue = eprom_read(dev, (EEPROM_VID>>1)); + priv->eeprom_vid = endian_swap(&tmpValue); + priv->eeprom_pid = eprom_read(dev, (EEPROM_PID>>1)); + + // Version ID, Channel plan + tmpValue = eprom_read(dev, (EEPROM_Version>>1)); + //pHalData->card_8192_version = (VERSION_8192S)((usValue&0x00ff)); + priv->eeprom_ChannelPlan =(tmpValue&0xff00)>>8; + priv->bTXPowerDataReadFromEEPORM = true; + + // Customer ID, 0x00 and 0xff are reserved for Realtek. + tmpValue = eprom_read(dev, (u16)(EEPROM_CustomID>>1)) ; + priv->eeprom_CustomerID = (u8)( tmpValue & 0xff); + priv->eeprom_SubCustomerID = (u8)((tmpValue & 0xff00)>>8); + } + else + { + priv->eeprom_vid = 0; + priv->eeprom_pid = 0; + //priv->card_8192_version = VERSION_8192SU_A; + priv->eeprom_ChannelPlan = 0; + priv->eeprom_CustomerID = 0; + priv->eeprom_SubCustomerID = 0; + } + RT_TRACE(COMP_EPROM, "vid:0x%4x, pid:0x%4x, CustomID:0x%2x, ChanPlan:0x%x\n", priv->eeprom_vid, priv->eeprom_pid, priv->eeprom_CustomerID, priv->eeprom_ChannelPlan); + //set channelplan from eeprom + priv->ChannelPlan = priv->eeprom_ChannelPlan;// FIXLZM + + RT_TRACE(COMP_INIT, "EEPROMId = 0x%4x\n", EEPROMId); + RT_TRACE(COMP_INIT, "EEPROM VID = 0x%4x\n", priv->eeprom_vid); + RT_TRACE(COMP_INIT, "EEPROM PID = 0x%4x\n", priv->eeprom_pid); + //RT_TRACE(COMP_INIT, DBG_LOUD, ("EEPROM Version ID: 0x%2x\n", pHalData->VersionID)); + RT_TRACE(COMP_INIT, "EEPROM Customer ID: 0x%2x\n", priv->eeprom_CustomerID); + RT_TRACE(COMP_INIT, "EEPROM SubCustomer ID: 0x%2x\n", priv->eeprom_SubCustomerID); + RT_TRACE(COMP_INIT, "EEPROM ChannelPlan = 0x%4x\n", priv->eeprom_ChannelPlan); + + // Read USB optional function. + if(bLoad_From_EEPOM) + { + tmpValue = eprom_read(dev, (EEPROM_USB_OPTIONAL>>1)); + priv->EEPROMUsbOption = (u8)(tmpValue&0xff); + } + else + { + priv->EEPROMUsbOption = EEPROM_USB_Default_OPTIONAL_FUNC; + } + + RT_TRACE(COMP_INIT, "USB Option = %#x\n", priv->EEPROMUsbOption); + + + if (bLoad_From_EEPOM) + { + int i; + for (i=0; i<6; i+=2) + { + u16 tmp = 0; + tmp = eprom_read(dev, (u16)((EEPROM_NODE_ADDRESS_BYTE_0 + i)>>1)); + *(u16*)(&dev->dev_addr[i]) = tmp; + } + } + else + { + //<Roger_Notes> In this case, we random assigh MAC address here. 2008.10.15. + static u8 sMacAddr[6] = {0x00, 0xE0, 0x4C, 0x81, 0x92, 0x00}; + u8 i; + + //sMacAddr[5] = (u8)GetRandomNumber(1, 254); + + for(i = 0; i < 6; i++) + dev->dev_addr[i] = sMacAddr[i]; + + //memcpy(dev->dev_addr, sMacAddr, 6); + //should I set IDR0 here? + } + write_nic_dword(dev, IDR0, ((u32*)dev->dev_addr)[0]); + write_nic_word(dev, IDR4, ((u16*)(dev->dev_addr + 4))[0]); + RT_TRACE(COMP_EPROM, "MAC addr:"MAC_FMT"\n", MAC_ARG(dev->dev_addr)); + + priv->rf_type = RTL819X_DEFAULT_RF_TYPE; //default 1T2R +#if (defined (RTL8192SU_FPGA_2MAC_VERIFICATION)||defined (RTL8192SU_ASIC_VERIFICATION)) + priv->rf_chip = RF_6052; + priv->rf_type = RTL819X_DEFAULT_RF_TYPE; + //priv->card_8192_version = VERSION_8192SU_A; //Over write for temporally experiment. 2008.10.16. By Roger. +#else + priv->rf_chip = RF_8256; +#endif + + { +#if 0 + if(bLoad_From_EEPOM) + { + tempval = (ReadEEprom(Adapter, (EEPROM_RFInd_PowerDiff>>1))) & 0xff; + if (tempval&0x80) //RF-indication, bit[7] + pHalData->RF_Type = RF_1T2R; + else + pHalData->RF_Type = RF_2T4R; + } +#endif + + priv->EEPROMTxPowerDiff = EEPROM_Default_TxPowerDiff; + RT_TRACE(COMP_INIT, "TxPowerDiff = %#x\n", priv->EEPROMTxPowerDiff); + + + // + // Read antenna tx power offset of B/C/D to A from EEPROM + // and read ThermalMeter from EEPROM + // + if(bLoad_From_EEPOM) + { + tmpValue = eprom_read(dev, (EEPROM_PwDiff>>1)); + priv->EEPROMPwDiff = tmpValue&0x00ff; + priv->EEPROMThermalMeter = (tmpValue&0xff00)>>8; + } + else + { + priv->EEPROMPwDiff = EEPROM_Default_PwDiff; + priv->EEPROMThermalMeter = EEPROM_Default_ThermalMeter; + } + RT_TRACE(COMP_INIT, "PwDiff = %#x\n", priv->EEPROMPwDiff); + RT_TRACE(COMP_INIT, "ThermalMeter = %#x\n", priv->EEPROMThermalMeter); + + priv->TSSI_13dBm = priv->EEPROMThermalMeter *100; + + + // Read CrystalCap from EEPROM + if(bLoad_From_EEPOM) + { + priv->EEPROMCrystalCap =(u8) (((eprom_read(dev, (EEPROM_CrystalCap>>1)))&0xf000)>>12); + } + else + { + priv->EEPROMCrystalCap = EEPROM_Default_CrystalCap; + } + RT_TRACE(COMP_INIT, "CrystalCap = %#x\n", priv->EEPROMCrystalCap); + + + //if(pHalData->EEPROM_Def_Ver == 0) // old eeprom definition + { + + // + // Get Tx Power Base.//===> + // + if(bLoad_From_EEPOM) + { + priv->EEPROMTxPwrBase =(u8) ((eprom_read(dev, (EEPROM_TxPowerBase>>1)))&0xff); + } + else + { + priv->EEPROMTxPwrBase = EEPROM_Default_TxPowerBase; + } + + RT_TRACE(COMP_INIT, "TxPwrBase = %#x\n", priv->EEPROMTxPwrBase); + + // + // Get CustomerID(Boad Type) + // i.e., 0x0: RTL8188SU, 0x1: RTL8191SU, 0x2: RTL8192SU, 0x3: RTL8191GU. + // Others: Reserved. Default is 0x2: RTL8192SU. + // + if(bLoad_From_EEPOM) + { + tmpValue = eprom_read(dev, (u16) (EEPROM_BoardType>>1)); + priv->EEPROMBoardType = (u8)(tmpValue&0xff); + } + else + { + priv->EEPROMBoardType = EEPROM_Default_BoardType; + } + + RT_TRACE(COMP_INIT, "BoardType = %#x\n", priv->EEPROMBoardType); + +#ifdef EEPROM_OLD_FORMAT_SUPPORT + + // + // Buffer TxPwIdx(i.e., from offset 0x58~0x75, total 30Bytes) + // + if(bLoad_From_EEPOM) + { + for(i = 0; i < 30; i += 2) + { + tmpValue = eprom_read(dev, (u16) ((EEPROM_TxPowerBase+i)>>1)); + *((u16 *)(&tmpBuffer[i])) = tmpValue; + } + } + + // + // Update CCK, OFDM Tx Power Index from above buffer. + // + if(bLoad_From_EEPOM) + { + for(i=0; i<14; i++) + { + priv->EEPROMTxPowerLevelCCK24G[i] = (u8)tmpBuffer[i+1]; + priv->EEPROMTxPowerLevelOFDM24G[i] = (u8)tmpBuffer[i+15]; + } + + } + else + { + for(i=0; i<14; i++) + { + priv->EEPROMTxPowerLevelCCK24G[i] = (u8)(EEPROM_Default_TxPower & 0xff); + priv->EEPROMTxPowerLevelOFDM24G[i] = (u8)(EEPROM_Default_TxPower & 0xff); + } + } + + for(i=0; i<14; i++) + { + RT_TRACE(COMP_INIT, "CCK 2.4G Tx Power Level, Index %d = 0x%02x\n", i, priv->EEPROMTxPowerLevelCCK24G[i]); + RT_TRACE(COMP_INIT, "OFDM 2.4G Tx Power Level, Index %d = 0x%02x\n", i, priv->EEPROMTxPowerLevelOFDM24G[i]); + } +#else + // Please add code in the section!!!! + // And merge tx power difference section. +#endif + + // + // Get TSSI value for each path. + // + if(bLoad_From_EEPOM) + { + tmpValue = eprom_read(dev, (u16) ((EEPROM_TSSI_A)>>1)); + priv->EEPROMTSSI_A = (u8)((tmpValue&0xff00)>>8); + } + else + { // Default setting for Empty EEPROM + priv->EEPROMTSSI_A = EEPROM_Default_TSSI; + } + + if(bLoad_From_EEPOM) + { + tmpValue = eprom_read(dev, (u16) ((EEPROM_TSSI_B)>>1)); + priv->EEPROMTSSI_B = (u8)(tmpValue&0xff); + priv->EEPROMTxPwrTkMode = (u8)((tmpValue&0xff00)>>8); + } + else + { // Default setting for Empty EEPROM + priv->EEPROMTSSI_B = EEPROM_Default_TSSI; + priv->EEPROMTxPwrTkMode = EEPROM_Default_TxPwrTkMode; + } + + RT_TRACE(COMP_INIT, "TSSI_A = %#x, TSSI_B = %#x\n", priv->EEPROMTSSI_A, priv->EEPROMTSSI_B); + RT_TRACE(COMP_INIT, "TxPwrTkMod = %#x\n", priv->EEPROMTxPwrTkMode); + +#ifdef EEPROM_OLD_FORMAT_SUPPORT + // + // Get HT 2T Path A and B Power Index. + // + if(bLoad_From_EEPOM) + { + for(i = 0; i < 6; i += 2) + { + tmpValue = eprom_read(dev, (u16) ((EEPROM_HT2T_CH1_A+i)>>1)); + *((u16*)(&priv->EEPROMHT2T_TxPwr[i])) = tmpValue; + } + } + else + { // Default setting for Empty EEPROM + for(i=0; i<6; i++) + { + priv->EEPROMHT2T_TxPwr[i] = EEPROM_Default_HT2T_TxPwr; + } + } + + for(i=0; i<6; i++) + { + RT_TRACE(COMP_INIT, "EEPROMHT2T_TxPwr, Index %d = 0x%02x\n", i, priv->EEPROMHT2T_TxPwr[i]); + } +#else + +#endif + } + +#ifdef EEPROM_OLD_FORMAT_SUPPORT + // + // Update HAL variables. + // + for(i=0; i<14; i++) + { + priv->TxPowerLevelOFDM24G[i] = priv->EEPROMTxPowerLevelOFDM24G[i]; + priv->TxPowerLevelCCK[i] = priv->EEPROMTxPowerLevelCCK24G[i]; + } +#else + +#endif + priv->TxPowerDiff = priv->EEPROMPwDiff; + // Antenna B gain offset to antenna A, bit0~3 + priv->AntennaTxPwDiff[0] = (priv->EEPROMTxPowerDiff & 0xf); + // Antenna C gain offset to antenna A, bit4~7 + priv->AntennaTxPwDiff[1] = ((priv->EEPROMTxPowerDiff & 0xf0)>>4); + // CrystalCap, bit12~15 + priv->CrystalCap = priv->EEPROMCrystalCap; + // ThermalMeter, bit0~3 for RFIC1, bit4~7 for RFIC2 + // 92U does not enable TX power tracking. + priv->ThermalMeter[0] = priv->EEPROMThermalMeter; + } + + priv->LedStrategy = SW_LED_MODE0; + + if(priv->rf_type == RF_1T2R) + { + RT_TRACE(COMP_EPROM, "\n1T2R config\n"); + } + else + { + RT_TRACE(COMP_EPROM, "\n2T4R config\n"); + } + + // 2008/01/16 MH We can only know RF type in the function. So we have to init + // DIG RATR table again. + init_rate_adaptive(dev); + //we need init DIG RATR table here again. + + RT_TRACE(COMP_EPROM, "<===========%s()\n", __FUNCTION__); + return; +} + +// +// Description: +// 1. Read HW adapter information by E-Fuse. +// 2. Refered from SD1 Richard. +// +// Assumption: +// 1. Boot from E-Fuse and CR9346 regiser has verified. +// 2. PASSIVE_LEVEL (USB interface) +// +// Created by Roger, 2008.10.21. +// +void +rtl8192SU_ReadAdapterInfo8192SEFuse(struct net_device* dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + u16 i,usValue; + u16 EEPROMId; + u8 readbyte; + u8 OFDMTxPwr[14]; + u8 CCKTxPwr[14]; + u8 HT2T_TxPwr[6]; + u8 UsbPhyParam[5]; + u8 hwinfo[HWSET_MAX_SIZE_92S]; + + + RT_TRACE(COMP_INIT, "====> ReadAdapterInfo8192SEFuse\n"); + + // + // <Roger_Notes> We set Isolation signals from Loader and reset EEPROM after system resuming + // from suspend mode. + // 2008.10.21. + // + write_nic_byte(dev, SYS_ISO_CTRL+1, 0xE8); // Isolation signals from Loader + //PlatformStallExecution(10000); + mdelay(10); + write_nic_byte(dev, SYS_FUNC_EN+1, 0x40); + write_nic_byte(dev, SYS_FUNC_EN+1, 0x50); + + readbyte = read_nic_byte(dev, EFUSE_TEST+3); + write_nic_byte(dev, EFUSE_TEST+3, (readbyte | 0x80)); + write_nic_byte(dev, EFUSE_TEST+3, 0x72); + write_nic_byte(dev, EFUSE_CLK, 0x03); + + // + // Dump EFUSe at init time for later use + // + // Read EFUSE real map to shadow!! + EFUSE_ShadowMapUpdate(dev); + + memcpy(hwinfo, (void*)&priv->EfuseMap[EFUSE_INIT_MAP][0], HWSET_MAX_SIZE_92S); + //RT_PRINT_DATA(COMP_INIT, DBG_LOUD, ("MAP \n"), hwinfo, HWSET_MAX_SIZE_92S); + + // + // <Roger_Notes> Event though CR9346 regiser can verify whether Autoload is success or not, but we still + // double check ID codes for 92S here(e.g., due to HW GPIO polling fail issue). + // 2008.10.21. + // + ReadEFuse(dev, 0, 2, (unsigned char*) &EEPROMId); + + if( EEPROMId != RTL8190_EEPROM_ID ) + { + RT_TRACE(COMP_INIT, "EEPROM ID(%#x) is invalid!!\n", EEPROMId); + priv->AutoloadFailFlag=true; + } + else + { + priv->AutoloadFailFlag=false; + } + + // Read IC Version && Channel Plan + if(!priv->AutoloadFailFlag) + { + + // VID, PID + ReadEFuse(dev, EEPROM_VID, 2, (unsigned char*) &priv->eeprom_vid); + ReadEFuse(dev, EEPROM_PID, 2, (unsigned char*) &priv->eeprom_pid); + + // Version ID, Channel plan + ReadEFuse(dev, EEPROM_Version, 2, (unsigned char*) &usValue); + //pHalData->VersionID = (VERSION_8192S)(usValue&0x00ff); + priv->eeprom_ChannelPlan = (usValue&0xff00>>8); + priv->bTXPowerDataReadFromEEPORM = true; + + // Customer ID, 0x00 and 0xff are reserved for Realtek. + ReadEFuse(dev, EEPROM_CustomID, 2, (unsigned char*) &usValue); + priv->eeprom_CustomerID = (u8)( usValue & 0xff); + priv->eeprom_SubCustomerID = (u8)((usValue & 0xff00)>>8); + } + else + { + priv->eeprom_vid = 0; + priv->eeprom_pid = 0; + priv->eeprom_ChannelPlan = 0; + priv->eeprom_CustomerID = 0; + priv->eeprom_SubCustomerID = 0; + } + + RT_TRACE(COMP_INIT, "EEPROM Id = 0x%4x\n", EEPROMId); + RT_TRACE(COMP_INIT, "EEPROM VID = 0x%4x\n", priv->eeprom_vid); + RT_TRACE(COMP_INIT, "EEPROM PID = 0x%4x\n", priv->eeprom_pid); + //RT_TRACE(COMP_INIT, DBG_LOUD, ("EEPROM Version ID: 0x%2x\n", pHalData->VersionID)); + RT_TRACE(COMP_INIT, "EEPROM Customer ID: 0x%2x\n", priv->eeprom_CustomerID); + RT_TRACE(COMP_INIT, "EEPROM SubCustomer ID: 0x%2x\n", priv->eeprom_SubCustomerID); + RT_TRACE(COMP_INIT, "EEPROM ChannelPlan = 0x%4x\n", priv->eeprom_ChannelPlan); + + + // Read USB optional function. + if(!priv->AutoloadFailFlag) + { + ReadEFuse(dev, EEPROM_USB_OPTIONAL, 1, (unsigned char*) &priv->EEPROMUsbOption); + } + else + { + priv->EEPROMUsbOption = EEPROM_USB_Default_OPTIONAL_FUNC; + } + + RT_TRACE(COMP_INIT, "USB Option = %#x\n", priv->EEPROMUsbOption); + + + // Read USB PHY parameters. + if(!priv->AutoloadFailFlag) + { + ReadEFuse(dev, EEPROM_USB_PHY_PARA1, 5, (unsigned char*)UsbPhyParam); + for(i=0; i<5; i++) + { + priv->EEPROMUsbPhyParam[i] = UsbPhyParam[i]; + RT_TRACE(COMP_INIT, "USB Param = index(%d) = %#x\n", i, priv->EEPROMUsbPhyParam[i]); + } + } + else + { + for(i=0; i<5; i++) + { + priv->EEPROMUsbPhyParam[i] = EEPROM_USB_Default_PHY_PARAM; + RT_TRACE(COMP_INIT, "USB Param = index(%d) = %#x\n", i, priv->EEPROMUsbPhyParam[i]); + } + } + + + //Read Permanent MAC address + if(!priv->AutoloadFailFlag) + { + u8 macaddr[6] = {0x00, 0xe1, 0x86, 0x4c, 0x92, 0x00}; + + ReadEFuse(dev, EEPROM_NODE_ADDRESS_BYTE_0, 6, (unsigned char*)macaddr); + for(i=0; i<6; i++) + dev->dev_addr[i] = macaddr[i]; + } + else + {//Auto load fail + + //<Roger_Notes> In this case, we random assigh MAC address here. 2008.10.15. + static u8 sMacAddr[6] = {0x00, 0xE0, 0x4C, 0x81, 0x92, 0x00}; + u8 i; + + //if(!Adapter->bInHctTest) + //sMacAddr[5] = (u8)GetRandomNumber(1, 254); + + for(i = 0; i < 6; i++) + dev->dev_addr[i] = sMacAddr[i]; + } + + //NicIFSetMacAddress(Adapter, Adapter->PermanentAddress); + write_nic_dword(dev, IDR0, ((u32*)dev->dev_addr)[0]); + write_nic_word(dev, IDR4, ((u16*)(dev->dev_addr + 4))[0]); + + RT_TRACE(COMP_INIT, "ReadAdapterInfo8192SEFuse(), Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n", + dev->dev_addr[0], dev->dev_addr[1], + dev->dev_addr[2], dev->dev_addr[3], + dev->dev_addr[4], dev->dev_addr[5]); + + // 2007/11/15 MH For RTL8192USB we assign as 1T2R now. + priv->rf_type = RTL819X_DEFAULT_RF_TYPE; // default : 1T2R + +#if (defined (RTL8192SU_FPGA_2MAC_VERIFICATION)||defined (RTL8192SU_ASIC_VERIFICATION)) + priv->rf_chip = RF_6052; + priv->rf_type = RTL819X_DEFAULT_RF_TYPE; +#else + priv->rf_chip = RF_8256; +#endif + + { + // + // Read antenna tx power offset of B/C/D to A from EEPROM + // and read ThermalMeter from EEPROM + // + if(!priv->AutoloadFailFlag) + { + ReadEFuse(dev, EEPROM_PwDiff, 2, (unsigned char*) &usValue); + priv->EEPROMPwDiff = usValue&0x00ff; + priv->EEPROMThermalMeter = (usValue&0xff00)>>8; + } + else + { + priv->EEPROMPwDiff = EEPROM_Default_PwDiff; + priv->EEPROMThermalMeter = EEPROM_Default_ThermalMeter; + } + + RT_TRACE(COMP_INIT, "PwDiff = %#x\n", priv->EEPROMPwDiff); + RT_TRACE(COMP_INIT, "ThermalMeter = %#x\n", priv->EEPROMThermalMeter); + + priv->TSSI_13dBm = priv->EEPROMThermalMeter *100; + + // + // Read Tx Power gain offset of legacy OFDM to HT rate. + // Read CrystalCap from EEPROM + // + if(!priv->AutoloadFailFlag) + { + ReadEFuse(dev, EEPROM_CrystalCap, 1, (unsigned char*) &usValue); + priv->EEPROMCrystalCap = (u8)((usValue&0xf0)>>4); + } + else + { + priv->EEPROMCrystalCap = EEPROM_Default_CrystalCap; + } + + RT_TRACE(COMP_INIT, "CrystalCap = %#x\n", priv->EEPROMCrystalCap); + + priv->EEPROMTxPowerDiff = EEPROM_Default_TxPowerDiff; + RT_TRACE(COMP_INIT, "TxPowerDiff = %d\n", priv->EEPROMTxPowerDiff); + + + // + // Get Tx Power Base. + // + if(!priv->AutoloadFailFlag) + { + ReadEFuse(dev, EEPROM_TxPowerBase, 1, (unsigned char*) &priv->EEPROMTxPwrBase ); + } + else + { + priv->EEPROMTxPwrBase = EEPROM_Default_TxPowerBase; + } + + RT_TRACE(COMP_INIT, "TxPwrBase = %#x\n", priv->EEPROMTxPwrBase); + + // + // Get CustomerID(Boad Type) + // i.e., 0x0: RTL8188SU, 0x1: RTL8191SU, 0x2: RTL8192SU, 0x3: RTL8191GU. + // Others: Reserved. Default is 0x2: RTL8192SU. + // + if(!priv->AutoloadFailFlag) + { + ReadEFuse(dev, EEPROM_BoardType, 1, (unsigned char*) &priv->EEPROMBoardType ); + } + else + { + priv->EEPROMBoardType = EEPROM_Default_BoardType; + } + + RT_TRACE(COMP_INIT, "BoardType = %#x\n", priv->EEPROMBoardType); + + //if(pHalData->EEPROM_Def_Ver == 0) + { +#ifdef EEPROM_OLD_FORMAT_SUPPORT + // + // Get CCK Tx Power Index. + // + if(!priv->AutoloadFailFlag) + { + ReadEFuse(dev, EEPROM_TxPwIndex_CCK_24G, 14, (unsigned char*)CCKTxPwr); + for(i=0; i<14; i++) + { + RT_TRACE(COMP_INIT, "CCK 2.4G Tx Power Level, Index %d = 0x%02x\n", i, CCKTxPwr[i]); + priv->EEPROMTxPowerLevelCCK24G[i] = CCKTxPwr[i]; + } + } + else + { // Default setting for Empty EEPROM + for(i=0; i<14; i++) + priv->EEPROMTxPowerLevelCCK24G[i] = (u8)(EEPROM_Default_TxPower & 0xff); + } + + // + // Get OFDM Tx Power Index. + // + if(!priv->AutoloadFailFlag) + { + ReadEFuse(dev, EEPROM_TxPwIndex_OFDM_24G, 14, (unsigned char*)OFDMTxPwr); + for(i=0; i<14; i++) + { + RT_TRACE(COMP_INIT, "OFDM 2.4G Tx Power Level, Index %d = 0x%02x\n", i, OFDMTxPwr[i]); + priv->EEPROMTxPowerLevelOFDM24G[i] = OFDMTxPwr[i]; + } + } + else + { // Default setting for Empty EEPROM + usValue = 0x10; + for(i=0; i<14; i++) + priv->EEPROMTxPowerLevelOFDM24G[i] = (u8)usValue; + } +#else + // Please add code in the section!!!! + // And merge tx power difference section. +#endif + + // + // Get TSSI value for each path. + // + if(!priv->AutoloadFailFlag) + { + ReadEFuse(dev, EEPROM_TSSI_A, 2, (unsigned char*)&usValue); + priv->EEPROMTSSI_A = (u8)(usValue&0xff); + priv->EEPROMTSSI_B = (u8)((usValue&0xff00)>>8); + } + else + { // Default setting for Empty EEPROM + priv->EEPROMTSSI_A = EEPROM_Default_TSSI; + priv->EEPROMTSSI_B = EEPROM_Default_TSSI; + } + + RT_TRACE(COMP_INIT, "TSSI_A = %#x, TSSI_B = %#x\n", + priv->EEPROMTSSI_A, priv->EEPROMTSSI_B); + + // + // Get Tx Power tracking mode. + // + if(!priv->AutoloadFailFlag) + { + ReadEFuse(dev, EEPROM_TxPwTkMode, 1, (unsigned char*)&priv->EEPROMTxPwrTkMode); + } + else + { // Default setting for Empty EEPROM + priv->EEPROMTxPwrTkMode = EEPROM_Default_TxPwrTkMode; + } + + RT_TRACE(COMP_INIT, "TxPwrTkMod = %#x\n", priv->EEPROMTxPwrTkMode); + + + // TODO: The following HT 2T Path A and B Power Index should be updated.!! Added by Roger, 2008.20.23. + + // + // Get HT 2T Path A and B Power Index. + // + if(!priv->AutoloadFailFlag) + { + ReadEFuse(dev, EEPROM_HT2T_CH1_A, 6, (unsigned char*)HT2T_TxPwr); + for(i=0; i<6; i++) + { + priv->EEPROMHT2T_TxPwr[i] = HT2T_TxPwr[i]; + } + } + else + { // Default setting for Empty EEPROM + for(i=0; i<6; i++) + { + priv->EEPROMHT2T_TxPwr[i] = EEPROM_Default_HT2T_TxPwr; + } + } + + for(i=0; i<6; i++) + { + RT_TRACE(COMP_INIT, "EEPROMHT2T_TxPwr, Index %d = 0x%02x\n", + i, priv->EEPROMHT2T_TxPwr[i]); + } + } + +#ifdef EEPROM_OLD_FORMAT_SUPPORT + // + // Update HAL variables. + // + for(i=0; i<14; i++) + { + priv->TxPowerLevelOFDM24G[i] = priv->EEPROMTxPowerLevelOFDM24G[i]; + priv->TxPowerLevelCCK[i] = priv->EEPROMTxPowerLevelCCK24G[i]; + } +#else + +#endif + priv->TxPowerDiff = priv->EEPROMPwDiff; + // Antenna B gain offset to antenna A, bit0~3 + priv->AntennaTxPwDiff[0] = (priv->EEPROMTxPowerDiff & 0xf); + // Antenna C gain offset to antenna A, bit4~7 + priv->AntennaTxPwDiff[1] = ((priv->EEPROMTxPowerDiff & 0xf0)>>4); + // CrystalCap, bit12~15 + priv->CrystalCap = priv->EEPROMCrystalCap; + // ThermalMeter, bit0~3 for RFIC1, bit4~7 for RFIC2 + // 92U does not enable TX power tracking. + priv->ThermalMeter[0] = priv->EEPROMThermalMeter; + } + + priv->LedStrategy = SW_LED_MODE0; + + init_rate_adaptive(dev); + + RT_TRACE(COMP_INIT, "<==== ReadAdapterInfo8192SEFuse\n"); + +} +#endif + +// +// Description: +// Read HW adapter information by E-Fuse or EEPROM according CR9346 reported. +// +// Assumption: +// 1. CR9346 regiser has verified. +// 2. PASSIVE_LEVEL (USB interface) +// +// Created by Roger, 2008.10.21. +// +void +rtl8192SU_ReadAdapterInfo8192SUsb(struct net_device* dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + u16 i,usValue; + u8 tmpU1b, tempval; + u16 EEPROMId; + u8 hwinfo[HWSET_MAX_SIZE_92S]; + u8 rf_path, index; // For EEPROM/EFUSE After V0.6_1117 + + + RT_TRACE(COMP_INIT, "====> ReadAdapterInfo8192SUsb\n"); + + // + // <Roger_Note> The following operation are prevent Efuse leakage by turn on 2.5V. + // 2008.11.25. + // + tmpU1b = read_nic_byte(dev, EFUSE_TEST+3); + write_nic_byte(dev, EFUSE_TEST+3, tmpU1b|0x80); + //PlatformStallExecution(1000); + mdelay(10); + write_nic_byte(dev, EFUSE_TEST+3, (tmpU1b&(~BIT7))); + + // Retrieve Chip version. + priv->card_8192_version = (VERSION_8192S)((read_nic_dword(dev, PMC_FSM)>>16)&0xF); + RT_TRACE(COMP_INIT, "Chip Version ID: 0x%2x\n", priv->card_8192_version); + + switch(priv->card_8192_version) + { + case 0: + RT_TRACE(COMP_INIT, "Chip Version ID: VERSION_8192S_ACUT.\n"); + break; + case 1: + RT_TRACE(COMP_INIT, "Chip Version ID: VERSION_8192S_BCUT.\n"); + break; + case 2: + RT_TRACE(COMP_INIT, "Chip Version ID: VERSION_8192S_CCUT.\n"); + break; + default: + RT_TRACE(COMP_INIT, "Unknown Chip Version!!\n"); + priv->card_8192_version = VERSION_8192S_BCUT; + break; + } + + //if (IS_BOOT_FROM_EEPROM(Adapter)) + if(priv->EepromOrEfuse) + { // Read frin EEPROM + write_nic_byte(dev, SYS_ISO_CTRL+1, 0xE8); // Isolation signals from Loader + //PlatformStallExecution(10000); + mdelay(10); + write_nic_byte(dev, PMC_FSM, 0x02); // Enable Loader Data Keep + // Read all Content from EEPROM or EFUSE. + for(i = 0; i < HWSET_MAX_SIZE_92S; i += 2) + { + usValue = eprom_read(dev, (u16) (i>>1)); + *((u16*)(&hwinfo[i])) = usValue; + } + } + else if (!(priv->EepromOrEfuse)) + { // Read from EFUSE + + // + // <Roger_Notes> We set Isolation signals from Loader and reset EEPROM after system resuming + // from suspend mode. + // 2008.10.21. + // + //PlatformEFIOWrite1Byte(Adapter, SYS_ISO_CTRL+1, 0xE8); // Isolation signals from Loader + //PlatformStallExecution(10000); + //PlatformEFIOWrite1Byte(Adapter, SYS_FUNC_EN+1, 0x40); + //PlatformEFIOWrite1Byte(Adapter, SYS_FUNC_EN+1, 0x50); + + //tmpU1b = PlatformEFIORead1Byte(Adapter, EFUSE_TEST+3); + //PlatformEFIOWrite1Byte(Adapter, EFUSE_TEST+3, (tmpU1b | 0x80)); + //PlatformEFIOWrite1Byte(Adapter, EFUSE_TEST+3, 0x72); + //PlatformEFIOWrite1Byte(Adapter, EFUSE_CLK, 0x03); + + // Read EFUSE real map to shadow. + EFUSE_ShadowMapUpdate(dev); + memcpy(hwinfo, &priv->EfuseMap[EFUSE_INIT_MAP][0], HWSET_MAX_SIZE_92S); + } + else + { + RT_TRACE(COMP_INIT, "ReadAdapterInfo8192SUsb(): Invalid boot type!!\n"); + } + + //YJ,test,090106 + //dump_buf(hwinfo,HWSET_MAX_SIZE_92S); + // + // <Roger_Notes> The following are EFUSE/EEPROM independent operations!! + // + //RT_PRINT_DATA(COMP_EFUSE, DBG_LOUD, ("MAP: \n"), hwinfo, HWSET_MAX_SIZE_92S); + + // + // <Roger_Notes> Event though CR9346 regiser can verify whether Autoload is success or not, but we still + // double check ID codes for 92S here(e.g., due to HW GPIO polling fail issue). + // 2008.10.21. + // + EEPROMId = *((u16 *)&hwinfo[0]); + + if( EEPROMId != RTL8190_EEPROM_ID ) + { + RT_TRACE(COMP_INIT, "ID(%#x) is invalid!!\n", EEPROMId); + priv->bTXPowerDataReadFromEEPORM = FALSE; + priv->AutoloadFailFlag=TRUE; + } + else + { + priv->AutoloadFailFlag=FALSE; +#if RTL8192SU_USE_PARAM_TXPWR + priv->bTXPowerDataReadFromEEPORM = FALSE; +#else + priv->bTXPowerDataReadFromEEPORM = TRUE; +#endif + + } + // Read IC Version && Channel Plan + if(!priv->AutoloadFailFlag) + { + // VID, PID + priv->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID]; + priv->eeprom_pid = *(u16 *)&hwinfo[EEPROM_PID]; + priv->bIgnoreDiffRateTxPowerOffset = false; //cosa for test + + + // EEPROM Version ID, Channel plan + priv->EEPROMVersion = *(u8 *)&hwinfo[EEPROM_Version]; + priv->eeprom_ChannelPlan = *(u8 *)&hwinfo[EEPROM_ChannelPlan]; + + // Customer ID, 0x00 and 0xff are reserved for Realtek. + priv->eeprom_CustomerID = *(u8 *)&hwinfo[EEPROM_CustomID]; + priv->eeprom_SubCustomerID = *(u8 *)&hwinfo[EEPROM_SubCustomID]; + } + else + { + //priv->eeprom_vid = 0; + //priv->eeprom_pid = 0; + //priv->EEPROMVersion = 0; + //priv->eeprom_ChannelPlan = 0; + //priv->eeprom_CustomerID = 0; + //priv->eeprom_SubCustomerID = 0; + + rtl8192SU_ConfigAdapterInfo8192SForAutoLoadFail(dev); + return; + } + + + RT_TRACE(COMP_INIT, "EEPROM Id = 0x%4x\n", EEPROMId); + RT_TRACE(COMP_INIT, "EEPROM VID = 0x%4x\n", priv->eeprom_vid); + RT_TRACE(COMP_INIT, "EEPROM PID = 0x%4x\n", priv->eeprom_pid); + RT_TRACE(COMP_INIT, "EEPROM Version ID: 0x%2x\n", priv->EEPROMVersion); + RT_TRACE(COMP_INIT, "EEPROM Customer ID: 0x%2x\n", priv->eeprom_CustomerID); + RT_TRACE(COMP_INIT, "EEPROM SubCustomer ID: 0x%2x\n", priv->eeprom_SubCustomerID); + RT_TRACE(COMP_INIT, "EEPROM ChannelPlan = 0x%4x\n", priv->eeprom_ChannelPlan); + RT_TRACE(COMP_INIT, "bIgnoreDiffRateTxPowerOffset = %d\n", priv->bIgnoreDiffRateTxPowerOffset); + + + // Read USB optional function. + if(!priv->AutoloadFailFlag) + { + priv->EEPROMUsbOption = *(u8 *)&hwinfo[EEPROM_USB_OPTIONAL]; + } + else + { + priv->EEPROMUsbOption = EEPROM_USB_Default_OPTIONAL_FUNC; + } + + + priv->EEPROMUsbEndPointNumber = rtl8192SU_UsbOptionToEndPointNumber((priv->EEPROMUsbOption&EEPROM_EP_NUMBER)>>3); + + RT_TRACE(COMP_INIT, "USB Option = %#x\n", priv->EEPROMUsbOption); + RT_TRACE(COMP_INIT, "EndPoint Number = %#x\n", priv->EEPROMUsbEndPointNumber); + +#ifdef TO_DO_LIST + // + // Decide CustomerID according to VID/DID or EEPROM + // + switch(pHalData->EEPROMCustomerID) + { + case EEPROM_CID_ALPHA: + pMgntInfo->CustomerID = RT_CID_819x_ALPHA; + break; + + case EEPROM_CID_CAMEO: + pMgntInfo->CustomerID = RT_CID_819x_CAMEO; + break; + + case EEPROM_CID_SITECOM: + pMgntInfo->CustomerID = RT_CID_819x_Sitecom; + RT_TRACE(COMP_INIT, DBG_LOUD, ("CustomerID = 0x%4x\n", pMgntInfo->CustomerID)); + + break; + + case EEPROM_CID_WHQL: + Adapter->bInHctTest = TRUE; + + pMgntInfo->bSupportTurboMode = FALSE; + pMgntInfo->bAutoTurboBy8186 = FALSE; + + pMgntInfo->PowerSaveControl.bInactivePs = FALSE; + pMgntInfo->PowerSaveControl.bIPSModeBackup = FALSE; + pMgntInfo->PowerSaveControl.bLeisurePs = FALSE; + pMgntInfo->keepAliveLevel = 0; + break; + + default: + pMgntInfo->CustomerID = RT_CID_DEFAULT; + break; + + } + + // + // Led mode + // + switch(pMgntInfo->CustomerID) + { + case RT_CID_DEFAULT: + case RT_CID_819x_ALPHA: + pHalData->LedStrategy = SW_LED_MODE1; + pHalData->bRegUseLed = TRUE; + pHalData->SwLed1.bLedOn = TRUE; + break; + case RT_CID_819x_CAMEO: + pHalData->LedStrategy = SW_LED_MODE1; + pHalData->bRegUseLed = TRUE; + break; + + case RT_CID_819x_Sitecom: + pHalData->LedStrategy = SW_LED_MODE2; + pHalData->bRegUseLed = TRUE; + break; + + default: + pHalData->LedStrategy = SW_LED_MODE0; + break; + } +#endif + + // Read USB PHY parameters. + for(i=0; i<5; i++) + priv->EEPROMUsbPhyParam[i] = *(u8 *)&hwinfo[EEPROM_USB_PHY_PARA1+i]; + + //RT_PRINT_DATA(COMP_EFUSE, DBG_LOUD, ("USB PHY Param: \n"), pHalData->EEPROMUsbPhyParam, 5); + + + //Read Permanent MAC address + for(i=0; i<6; i++) + dev->dev_addr[i] = *(u8 *)&hwinfo[EEPROM_NODE_ADDRESS_BYTE_0+i]; + + //NicIFSetMacAddress(Adapter, Adapter->PermanentAddress); + write_nic_dword(dev, IDR0, ((u32*)dev->dev_addr)[0]); + write_nic_word(dev, IDR4, ((u16*)(dev->dev_addr + 4))[0]); + + RT_TRACE(COMP_INIT, "ReadAdapterInfo8192SEFuse(), Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n", + dev->dev_addr[0], dev->dev_addr[1], + dev->dev_addr[2], dev->dev_addr[3], + dev->dev_addr[4], dev->dev_addr[5]); + + // + // Get CustomerID(Boad Type) + // i.e., 0x0: RTL8188SU, 0x1: RTL8191SU, 0x2: RTL8192SU, 0x3: RTL8191GU. + // Others: Reserved. Default is 0x2: RTL8192SU. + // + //if(!priv->AutoloadFailFlag) + //{ + priv->EEPROMBoardType = *(u8 *)&hwinfo[EEPROM_BoardType]; + priv->rf_type = rtl8192SU_BoardTypeToRFtype(dev, priv->EEPROMBoardType); + //} + //else + //{ + // priv->EEPROMBoardType = EEPROM_Default_BoardType; + // priv->rf_type = RF_1T2R; + //} + +#if (defined (RTL8192SU_FPGA_2MAC_VERIFICATION)||defined (RTL8192SU_ASIC_VERIFICATION)) + priv->rf_chip = RF_6052; +#else + priv->rf_chip = RF_8256; +#endif + + priv->rf_chip = RF_6052;//lzm test + RT_TRACE(COMP_INIT, "BoardType = 0x%2x\n", priv->EEPROMBoardType); + RT_TRACE(COMP_INIT, "RF_Type = 0x%2x\n", priv->rf_type); + + // + // Read antenna tx power offset of B/C/D to A from EEPROM + // and read ThermalMeter from EEPROM + // + //if(!priv->AutoloadFailFlag) + { + priv->EEPROMTxPowerDiff = *(u8 *)&hwinfo[EEPROM_PwDiff]; + priv->EEPROMThermalMeter = *(u8 *)&hwinfo[EEPROM_ThermalMeter]; + } + //else + //{ + // priv->EEPROMTxPowerDiff = EEPROM_Default_PwDiff; + // priv->EEPROMThermalMeter = EEPROM_Default_ThermalMeter; + //} + + RT_TRACE(COMP_INIT, "PwDiff = %#x\n", priv->EEPROMTxPowerDiff); + RT_TRACE(COMP_INIT, "ThermalMeter = %#x\n", priv->EEPROMThermalMeter); + + // + // Read Tx Power gain offset of legacy OFDM to HT rate. + // Read CrystalCap from EEPROM + // + //if(!priv->AutoloadFailFlag) + { + priv->EEPROMCrystalCap = *(u8 *)&hwinfo[EEPROM_CrystalCap]; + } + //else + //{ + // priv->EEPROMCrystalCap = EEPROM_Default_CrystalCap; + //} + + RT_TRACE(COMP_INIT, "CrystalCap = %#x\n", priv->EEPROMCrystalCap); + + // + // Get Tx Power Base. + // + //if(!priv->AutoloadFailFlag) + { + priv->EEPROMTxPwrBase = *(u8 *)&hwinfo[EEPROM_TxPowerBase]; + } + //else + //{ + // priv->EEPROMTxPwrBase = EEPROM_Default_TxPowerBase; + //} + + RT_TRACE(COMP_INIT, "TxPwrBase = %#x\n", priv->EEPROMTxPwrBase); + + + // + // Get TSSI value for each path. + // + //if(!priv->AutoloadFailFlag) + { + priv->EEPROMTSSI_A = *(u8 *)&hwinfo[EEPROM_TSSI_A]; + priv->EEPROMTSSI_B = *(u8 *)&hwinfo[EEPROM_TSSI_B]; + } + //else + //{ // Default setting for Empty EEPROM + // priv->EEPROMTSSI_A = EEPROM_Default_TSSI; + // priv->EEPROMTSSI_B = EEPROM_Default_TSSI; + //} + + RT_TRACE(COMP_INIT, "TSSI_A = %#x, TSSI_B = %#x\n", priv->EEPROMTSSI_A, priv->EEPROMTSSI_B); + + // + // Get Tx Power tracking mode. + // + //if(!priv->AutoloadFailFlag) + { + priv->EEPROMTxPwrTkMode = *(u8 *)&hwinfo[EEPROM_TxPwTkMode]; + } + + RT_TRACE(COMP_INIT, "TxPwrTkMod = %#x\n", priv->EEPROMTxPwrTkMode); + + +#ifdef EEPROM_OLD_FORMAT_SUPPORT + + // + // <Roger_Notes> The following settings are EFUSE version dependence. + // So we need to adjust reading offset. + // 2008.11.22. + // + { + // + // Get HT 2T Path A and B Power Index. + // + //if(!priv->AutoloadFailFlag) + { + for(i=0; i<6; i++) + { + priv->EEPROMHT2T_TxPwr[i] = *(u8 *)&hwinfo[EEPROM_HT2T_CH1_A+i]; + } + } + + //RT_PRINT_DATA(COMP_EFUSE, "HT2T TxPwr: \n"), pHalData->EEPROMHT2T_TxPwr, 6); + + // + // Get CCK and OFDM Tx Power Index. + // + //if(!priv->AutoloadFailFlag) + { + for(i=0; i<14; i++) + { + priv->EEPROMTxPowerLevelCCK24G[i] = *(u8 *)&hwinfo[EEPROM_TxPwIndex_CCK_24G+i]; + priv->EEPROMTxPowerLevelOFDM24G[i] = *(u8 *)&hwinfo[EEPROM_TxPwIndex_OFDM_24G+i]; + } + } + + //RT_PRINT_DATA(COMP_EFUSE, DBG_LOUD, ("CCK 2.4G TxPwr: \n"), pHalData->EEPROMTxPowerLevelCCK24G, 14); + //RT_PRINT_DATA(COMP_EFUSE, DBG_LOUD, ("OFDM 2.4G TxPwr: \n"), pHalData->EEPROMTxPowerLevelOFDM24G, 14); + + // + // Update HAL variables. + // + memcpy( priv->TxPowerLevelOFDM24G, priv->EEPROMTxPowerLevelOFDM24G, 14); + memcpy( priv->TxPowerLevelCCK, priv->EEPROMTxPowerLevelCCK24G, 14); + //RT_PRINT_DATA(COMP_EFUSE, DBG_LOUD, ("HAL CCK 2.4G TxPwr: \n"), pHalData->TxPowerLevelCCK, 14); + //RT_PRINT_DATA(COMP_EFUSE, DBG_LOUD, ("HAL OFDM 2.4G TxPwr: \n"), pHalData->TxPowerLevelOFDM24G, 14); + + } +#else // Support new version of EFUSE content, 2008.11.22. + { + // + // Buffer TxPwIdx(i.e., from offset 0x55~0x66, total 18Bytes) + // Update CCK, OFDM (1T/2T)Tx Power Index from above buffer. + // + + // + // Get Tx Power Level by Channel + // + //if(!priv->AutoloadFailFlag) + { + // Read Tx power of Channel 1 ~ 14 from EFUSE. + // 92S suupport RF A & B + for (rf_path = 0; rf_path < 2; rf_path++) + { + for (i = 0; i < 3; i++) + { + // Read CCK RF A & B Tx power + priv->RfCckChnlAreaTxPwr[rf_path][i] = + hwinfo[EEPROM_TxPwIndex+rf_path*3+i]; + + // Read OFDM RF A & B Tx power for 1T + priv->RfOfdmChnlAreaTxPwr1T[rf_path][i] = + hwinfo[EEPROM_TxPwIndex+6+rf_path*3+i]; + + // Read OFDM RF A & B Tx power for 2T + priv->RfOfdmChnlAreaTxPwr2T[rf_path][i] = + hwinfo[EEPROM_TxPwIndex+12+rf_path*3+i]; + } + } + + } +// + // Update Tx Power HAL variables. +// + for (rf_path = 0; rf_path < 2; rf_path++) + { + for (i = 0; i < 3; i++) + { + RT_TRACE((COMP_INIT), "CCK RF-%d CHan_Area-%d = 0x%x\n", rf_path, i, + priv->RfCckChnlAreaTxPwr[rf_path][i]); + RT_TRACE((COMP_INIT), "OFDM-1T RF-%d CHan_Area-%d = 0x%x\n", rf_path, i, + priv->RfOfdmChnlAreaTxPwr1T[rf_path][i]); + RT_TRACE((COMP_INIT), "OFDM-2T RF-%d CHan_Area-%d = 0x%x\n", rf_path, i, priv->RfOfdmChnlAreaTxPwr2T[rf_path][i]); + } + + // Assign dedicated channel tx power + for(i=0; i<14; i++) // channel 1~3 use the same Tx Power Level. + { + if (i < 3) // Cjanel 1-3 + index = 0; + else if (i < 9) // Channel 4-9 + index = 1; + else // Channel 10-14 + index = 2; + + // Record A & B CCK /OFDM - 1T/2T Channel area tx power + priv->RfTxPwrLevelCck[rf_path][i] = + priv->RfCckChnlAreaTxPwr[rf_path][index]; + priv->RfTxPwrLevelOfdm1T[rf_path][i] = + priv->RfOfdmChnlAreaTxPwr1T[rf_path][index]; + priv->RfTxPwrLevelOfdm2T[rf_path][i] = + priv->RfOfdmChnlAreaTxPwr2T[rf_path][index]; + if (rf_path == 0) + { + priv->TxPowerLevelOFDM24G[i] = priv->RfTxPwrLevelOfdm1T[rf_path][i] ; + priv->TxPowerLevelCCK[i] = priv->RfTxPwrLevelCck[rf_path][i]; + } + } + + for(i=0; i<14; i++) + { + RT_TRACE((COMP_INIT), + "Rf-%d TxPwr CH-%d CCK OFDM_1T OFDM_2T= 0x%x/0x%x/0x%x\n", + rf_path, i, priv->RfTxPwrLevelCck[rf_path][i], + priv->RfTxPwrLevelOfdm1T[rf_path][i] , + priv->RfTxPwrLevelOfdm2T[rf_path][i] ); + } + } + } + + // + // 2009/02/09 Cosa add for new EEPROM format + // + for(i=0; i<14; i++) // channel 1~3 use the same Tx Power Level. + { + // Read tx power difference between HT OFDM 20/40 MHZ + if (i < 3) // Cjanel 1-3 + index = 0; + else if (i < 9) // Channel 4-9 + index = 1; + else // Channel 10-14 + index = 2; + + tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_HT20_DIFF+index])&0xff; + priv->TxPwrHt20Diff[RF90_PATH_A][i] = (tempval&0xF); + priv->TxPwrHt20Diff[RF90_PATH_B][i] = ((tempval>>4)&0xF); + + // Read OFDM<->HT tx power diff + if (i < 3) // Cjanel 1-3 + tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_OFDM_DIFF])&0xff; + else if (i < 9) // Channel 4-9 + tempval = (*(u8 *)&hwinfo[EEPROM_PwDiff])&0xff; + else // Channel 10-14 + tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_OFDM_DIFF+1])&0xff; + + //cosa tempval = (*(u1Byte *)&hwinfo[EEPROM_TX_PWR_OFDM_DIFF+index])&0xff; + priv->TxPwrLegacyHtDiff[RF90_PATH_A][i] = (tempval&0xF); + priv->TxPwrLegacyHtDiff[RF90_PATH_B][i] = ((tempval>>4)&0xF); + + // + // Read Band Edge tx power offset and check if user enable the ability + // + // HT 40 band edge channel + tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_BAND_EDGE])&0xff; + priv->TxPwrbandEdgeHt40[RF90_PATH_A][0] = (tempval&0xF); // Band edge low channel + priv->TxPwrbandEdgeHt40[RF90_PATH_A][1] = ((tempval>>4)&0xF); // Band edge high channel + tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_BAND_EDGE+1])&0xff; + priv->TxPwrbandEdgeHt40[RF90_PATH_B][0] = (tempval&0xF); // Band edge low channel + priv->TxPwrbandEdgeHt40[RF90_PATH_B][1] = ((tempval>>4)&0xF); // Band edge high channel + // HT 20 band edge channel + tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_BAND_EDGE+2])&0xff; + priv->TxPwrbandEdgeHt20[RF90_PATH_A][0] = (tempval&0xF); // Band edge low channel + priv->TxPwrbandEdgeHt20[RF90_PATH_A][1] = ((tempval>>4)&0xF); // Band edge high channel + tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_BAND_EDGE+3])&0xff; + priv->TxPwrbandEdgeHt20[RF90_PATH_B][0] = (tempval&0xF); // Band edge low channel + priv->TxPwrbandEdgeHt20[RF90_PATH_B][1] = ((tempval>>4)&0xF); // Band edge high channel + // OFDM band edge channel + tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_BAND_EDGE+4])&0xff; + priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_A][0] = (tempval&0xF); // Band edge low channel + priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_A][1] = ((tempval>>4)&0xF); // Band edge high channel + tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_BAND_EDGE+5])&0xff; + priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_B][0] = (tempval&0xF); // Band edge low channel + priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_B][1] = ((tempval>>4)&0xF); // Band edge high channel + + priv->TxPwrbandEdgeFlag = (*(u8 *)&hwinfo[TX_PWR_BAND_EDGE_CHK]); + } + + for(i=0; i<14; i++) + RT_TRACE(COMP_INIT, "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i, priv->TxPwrHt20Diff[RF90_PATH_A][i]); + for(i=0; i<14; i++) + RT_TRACE(COMP_INIT, "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i, priv->TxPwrLegacyHtDiff[RF90_PATH_A][i]); + for(i=0; i<14; i++) + RT_TRACE(COMP_INIT, "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i, priv->TxPwrHt20Diff[RF90_PATH_B][i]); + for(i=0; i<14; i++) + RT_TRACE(COMP_INIT, "RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i, priv->TxPwrLegacyHtDiff[RF90_PATH_B][i]); + RT_TRACE(COMP_INIT, "RF-A HT40 band-edge low/high power diff = 0x%x/0x%x\n", + priv->TxPwrbandEdgeHt40[RF90_PATH_A][0], + priv->TxPwrbandEdgeHt40[RF90_PATH_A][1]); + RT_TRACE((COMP_INIT&COMP_DBG), "RF-B HT40 band-edge low/high power diff = 0x%x/0x%x\n", + priv->TxPwrbandEdgeHt40[RF90_PATH_B][0], + priv->TxPwrbandEdgeHt40[RF90_PATH_B][1]); + + RT_TRACE((COMP_INIT&COMP_DBG), "RF-A HT20 band-edge low/high power diff = 0x%x/0x%x\n", + priv->TxPwrbandEdgeHt20[RF90_PATH_A][0], + priv->TxPwrbandEdgeHt20[RF90_PATH_A][1]); + RT_TRACE((COMP_INIT&COMP_DBG), "RF-B HT20 band-edge low/high power diff = 0x%x/0x%x\n", + priv->TxPwrbandEdgeHt20[RF90_PATH_B][0], + priv->TxPwrbandEdgeHt20[RF90_PATH_B][1]); + + RT_TRACE((COMP_INIT&COMP_DBG), "RF-A OFDM band-edge low/high power diff = 0x%x/0x%x\n", + priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_A][0], + priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_A][1]); + RT_TRACE((COMP_INIT&COMP_DBG), "RF-B OFDM band-edge low/high power diff = 0x%x/0x%x\n", + priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_B][0], + priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_B][1]); + RT_TRACE((COMP_INIT&COMP_DBG), "Band-edge enable flag = %d\n", priv->TxPwrbandEdgeFlag); +#endif + + // + // Update remained HAL variables. + // + priv->TSSI_13dBm = priv->EEPROMThermalMeter *100; + priv->LegacyHTTxPowerDiff = priv->EEPROMTxPowerDiff; + priv->TxPowerDiff = priv->EEPROMTxPowerDiff; + //priv->AntennaTxPwDiff[0] = (priv->EEPROMTxPowerDiff & 0xf);// Antenna B gain offset to antenna A, bit[3:0] + //priv->AntennaTxPwDiff[1] = ((priv->EEPROMTxPowerDiff & 0xf0)>>4);// Antenna C gain offset to antenna A, bit[7:4] + priv->CrystalCap = priv->EEPROMCrystalCap; // CrystalCap, bit[15:12] + priv->ThermalMeter[0] = (priv->EEPROMThermalMeter&0x1f);// ThermalMeter, bit0~3 for RFIC1, bit4~7 for RFIC2 + priv->LedStrategy = SW_LED_MODE0; + + init_rate_adaptive(dev); + + RT_TRACE(COMP_INIT, "<==== ReadAdapterInfo8192SUsb\n"); + + //return RT_STATUS_SUCCESS; +} + + +// +// Description: +// Read HW adapter information by E-Fuse or EEPROM according CR9346 reported. +// +// Assumption: +// 1. CR9346 regiser has verified. +// 2. PASSIVE_LEVEL (USB interface) +// +// Created by Roger, 2008.10.21. +// +static void rtl8192SU_read_eeprom_info(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + u8 tmpU1b; + + RT_TRACE(COMP_INIT, "====> ReadAdapterInfo8192SUsb\n"); + + // Retrieve Chip version. + priv->card_8192_version = (VERSION_8192S)((read_nic_dword(dev, PMC_FSM)>>16)&0xF); + RT_TRACE(COMP_INIT, "Chip Version ID: 0x%2x\n", priv->card_8192_version); + + tmpU1b = read_nic_byte(dev, EPROM_CMD);//CR9346 + + // To check system boot selection. + if (tmpU1b & CmdEERPOMSEL) + { + RT_TRACE(COMP_INIT, "Boot from EEPROM\n"); + priv->EepromOrEfuse = TRUE; + } + else + { + RT_TRACE(COMP_INIT, "Boot from EFUSE\n"); + priv->EepromOrEfuse = FALSE; + } + + // To check autoload success or not. + if (tmpU1b & CmdEEPROM_En) + { + RT_TRACE(COMP_INIT, "Autoload OK!!\n"); + priv->AutoloadFailFlag=FALSE; + rtl8192SU_ReadAdapterInfo8192SUsb(dev);//eeprom or e-fuse + } + else + { // Auto load fail. + RT_TRACE(COMP_INIT, "AutoLoad Fail reported from CR9346!!\n"); + priv->AutoloadFailFlag=TRUE; + rtl8192SU_ConfigAdapterInfo8192SForAutoLoadFail(dev); + + //if (IS_BOOT_FROM_EFUSE(Adapter)) + if(!priv->EepromOrEfuse) + { + RT_TRACE(COMP_INIT, "Update shadow map for EFuse future use!!\n"); + EFUSE_ShadowMapUpdate(dev); + } + } +#ifdef TO_DO_LIST + if((priv->RegChannelPlan >= RT_CHANNEL_DOMAIN_MAX) || (pHalData->EEPROMChannelPlan & EEPROM_CHANNEL_PLAN_BY_HW_MASK)) + { + pMgntInfo->ChannelPlan = HalMapChannelPlan8192S(Adapter, (pHalData->EEPROMChannelPlan & (~(EEPROM_CHANNEL_PLAN_BY_HW_MASK)))); + pMgntInfo->bChnlPlanFromHW = (pHalData->EEPROMChannelPlan & EEPROM_CHANNEL_PLAN_BY_HW_MASK) ? TRUE : FALSE; // User cannot change channel plan. + } + else + { + pMgntInfo->ChannelPlan = (RT_CHANNEL_DOMAIN)pMgntInfo->RegChannelPlan; + } + + switch(pMgntInfo->ChannelPlan) + { + case RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN: + { + PRT_DOT11D_INFO pDot11dInfo = GET_DOT11D_INFO(pMgntInfo); + + pDot11dInfo->bEnabled = TRUE; + } + RT_TRACE(COMP_INIT, DBG_LOUD, ("ReadAdapterInfo8187(): Enable dot11d when RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN!\n")); + break; + } + + RT_TRACE(COMP_INIT, DBG_LOUD, ("RegChannelPlan(%d) EEPROMChannelPlan(%d)", pMgntInfo->RegChannelPlan, pHalData->EEPROMChannelPlan)); + RT_TRACE(COMP_INIT, DBG_LOUD, ("ChannelPlan = %d\n" , pMgntInfo->ChannelPlan)); + + RT_TRACE(COMP_INIT, DBG_LOUD, ("<==== ReadAdapterInfo8192S\n")); +#endif + + RT_TRACE(COMP_INIT, "<==== ReadAdapterInfo8192SUsb\n"); + + //return RT_STATUS_SUCCESS; +} +#else +static void rtl8192_read_eeprom_info(struct net_device* dev) +{ + u16 wEPROM_ID = 0; + u8 bMac_Tmp_Addr[6] = {0x00, 0xe0, 0x4c, 0x00, 0x00, 0x02}; + u8 bLoad_From_EEPOM = false; + struct r8192_priv *priv = ieee80211_priv(dev); + u16 tmpValue = 0; + RT_TRACE(COMP_EPROM, "===========>%s()\n", __FUNCTION__); + wEPROM_ID = eprom_read(dev, 0); //first read EEPROM ID out; + RT_TRACE(COMP_EPROM, "EEPROM ID is 0x%x\n", wEPROM_ID); + + if (wEPROM_ID != RTL8190_EEPROM_ID) + { + RT_TRACE(COMP_ERR, "EEPROM ID is invalid(is 0x%x(should be 0x%x)\n", wEPROM_ID, RTL8190_EEPROM_ID); + } + else + bLoad_From_EEPOM = true; + + if (bLoad_From_EEPOM) + { + tmpValue = eprom_read(dev, (EEPROM_VID>>1)); + priv->eeprom_vid = endian_swap(&tmpValue); + priv->eeprom_pid = eprom_read(dev, (EEPROM_PID>>1)); + tmpValue = eprom_read(dev, (EEPROM_ChannelPlan>>1)); + priv->eeprom_ChannelPlan =((tmpValue&0xff00)>>8); + priv->btxpowerdata_readfromEEPORM = true; + priv->eeprom_CustomerID = eprom_read(dev, (EEPROM_Customer_ID>>1)) >>8; + } + else + { + priv->eeprom_vid = 0; + priv->eeprom_pid = 0; + priv->card_8192_version = VERSION_819xU_B; + priv->eeprom_ChannelPlan = 0; + priv->eeprom_CustomerID = 0; + } + RT_TRACE(COMP_EPROM, "vid:0x%4x, pid:0x%4x, CustomID:0x%2x, ChanPlan:0x%x\n", priv->eeprom_vid, priv->eeprom_pid, priv->eeprom_CustomerID, priv->eeprom_ChannelPlan); + //set channelplan from eeprom + priv->ChannelPlan = priv->eeprom_ChannelPlan; + if (bLoad_From_EEPOM) + { + int i; + for (i=0; i<6; i+=2) + { + u16 tmp = 0; + tmp = eprom_read(dev, (u16)((EEPROM_NODE_ADDRESS_BYTE_0 + i)>>1)); + *(u16*)(&dev->dev_addr[i]) = tmp; + } + } + else + { + memcpy(dev->dev_addr, bMac_Tmp_Addr, 6); + //should I set IDR0 here? + } + RT_TRACE(COMP_EPROM, "MAC addr:"MAC_FMT"\n", MAC_ARG(dev->dev_addr)); + priv->rf_type = RTL819X_DEFAULT_RF_TYPE; //default 1T2R + priv->rf_chip = RF_8256; + + if (priv->card_8192_version == (u8)VERSION_819xU_A) + { + //read Tx power gain offset of legacy OFDM to HT rate + if (bLoad_From_EEPOM) + priv->EEPROMTxPowerDiff = (eprom_read(dev, (EEPROM_TxPowerDiff>>1))&0xff00) >> 8; + else + priv->EEPROMTxPowerDiff = EEPROM_Default_TxPower; + RT_TRACE(COMP_EPROM, "TxPowerDiff:%d\n", priv->EEPROMTxPowerDiff); + //read ThermalMeter from EEPROM + if (bLoad_From_EEPOM) + priv->EEPROMThermalMeter = (u8)(eprom_read(dev, (EEPROM_ThermalMeter>>1))&0x00ff); + else + priv->EEPROMThermalMeter = EEPROM_Default_ThermalMeter; + RT_TRACE(COMP_EPROM, "ThermalMeter:%d\n", priv->EEPROMThermalMeter); + //vivi, for tx power track + priv->TSSI_13dBm = priv->EEPROMThermalMeter *100; + //read antenna tx power offset of B/C/D to A from EEPROM + if (bLoad_From_EEPOM) + priv->EEPROMPwDiff = (eprom_read(dev, (EEPROM_PwDiff>>1))&0x0f00)>>8; + else + priv->EEPROMPwDiff = EEPROM_Default_PwDiff; + RT_TRACE(COMP_EPROM, "TxPwDiff:%d\n", priv->EEPROMPwDiff); + // Read CrystalCap from EEPROM + if (bLoad_From_EEPOM) + priv->EEPROMCrystalCap = (eprom_read(dev, (EEPROM_CrystalCap>>1))&0x0f); + else + priv->EEPROMCrystalCap = EEPROM_Default_CrystalCap; + RT_TRACE(COMP_EPROM, "CrystalCap = %d\n", priv->EEPROMCrystalCap); + //get per-channel Tx power level + if (bLoad_From_EEPOM) + priv->EEPROM_Def_Ver = (eprom_read(dev, (EEPROM_TxPwIndex_Ver>>1))&0xff00)>>8; + else + priv->EEPROM_Def_Ver = 1; + RT_TRACE(COMP_EPROM, "EEPROM_DEF_VER:%d\n", priv->EEPROM_Def_Ver); + if (priv->EEPROM_Def_Ver == 0) //old eeprom definition + { + int i; + if (bLoad_From_EEPOM) + priv->EEPROMTxPowerLevelCCK = (eprom_read(dev, (EEPROM_TxPwIndex_CCK>>1))&0xff) >> 8; + else + priv->EEPROMTxPowerLevelCCK = 0x10; + RT_TRACE(COMP_EPROM, "CCK Tx Power Levl: 0x%02x\n", priv->EEPROMTxPowerLevelCCK); + for (i=0; i<3; i++) + { + if (bLoad_From_EEPOM) + { + tmpValue = eprom_read(dev, (EEPROM_TxPwIndex_OFDM_24G+i)>>1); + if (((EEPROM_TxPwIndex_OFDM_24G+i) % 2) == 0) + tmpValue = tmpValue & 0x00ff; + else + tmpValue = (tmpValue & 0xff00) >> 8; + } + else + tmpValue = 0x10; + priv->EEPROMTxPowerLevelOFDM24G[i] = (u8) tmpValue; + RT_TRACE(COMP_EPROM, "OFDM 2.4G Tx Power Level, Index %d = 0x%02x\n", i, priv->EEPROMTxPowerLevelCCK); + } + }//end if EEPROM_DEF_VER == 0 + else if (priv->EEPROM_Def_Ver == 1) + { + if (bLoad_From_EEPOM) + { + tmpValue = eprom_read(dev, (EEPROM_TxPwIndex_CCK_V1>>1)); + tmpValue = (tmpValue & 0xff00) >> 8; + } + else + tmpValue = 0x10; + priv->EEPROMTxPowerLevelCCK_V1[0] = (u8)tmpValue; + + if (bLoad_From_EEPOM) + tmpValue = eprom_read(dev, (EEPROM_TxPwIndex_CCK_V1 + 2)>>1); + else + tmpValue = 0x1010; + *((u16*)(&priv->EEPROMTxPowerLevelCCK_V1[1])) = tmpValue; + if (bLoad_From_EEPOM) + tmpValue = eprom_read(dev, (EEPROM_TxPwIndex_OFDM_24G_V1>>1)); + else + tmpValue = 0x1010; + *((u16*)(&priv->EEPROMTxPowerLevelOFDM24G[0])) = tmpValue; + if (bLoad_From_EEPOM) + tmpValue = eprom_read(dev, (EEPROM_TxPwIndex_OFDM_24G_V1+2)>>1); + else + tmpValue = 0x10; + priv->EEPROMTxPowerLevelOFDM24G[2] = (u8)tmpValue; + }//endif EEPROM_Def_Ver == 1 + + //update HAL variables + // + { + int i; + for (i=0; i<14; i++) + { + if (i<=3) + priv->TxPowerLevelOFDM24G[i] = priv->EEPROMTxPowerLevelOFDM24G[0]; + else if (i>=4 && i<=9) + priv->TxPowerLevelOFDM24G[i] = priv->EEPROMTxPowerLevelOFDM24G[1]; + else + priv->TxPowerLevelOFDM24G[i] = priv->EEPROMTxPowerLevelOFDM24G[2]; + } + + for (i=0; i<14; i++) + { + if (priv->EEPROM_Def_Ver == 0) + { + if (i<=3) + priv->TxPowerLevelCCK[i] = priv->EEPROMTxPowerLevelOFDM24G[0] + (priv->EEPROMTxPowerLevelCCK - priv->EEPROMTxPowerLevelOFDM24G[1]); + else if (i>=4 && i<=9) + priv->TxPowerLevelCCK[i] = priv->EEPROMTxPowerLevelCCK; + else + priv->TxPowerLevelCCK[i] = priv->EEPROMTxPowerLevelOFDM24G[2] + (priv->EEPROMTxPowerLevelCCK - priv->EEPROMTxPowerLevelOFDM24G[1]); + } + else if (priv->EEPROM_Def_Ver == 1) + { + if (i<=3) + priv->TxPowerLevelCCK[i] = priv->EEPROMTxPowerLevelCCK_V1[0]; + else if (i>=4 && i<=9) + priv->TxPowerLevelCCK[i] = priv->EEPROMTxPowerLevelCCK_V1[1]; + else + priv->TxPowerLevelCCK[i] = priv->EEPROMTxPowerLevelCCK_V1[2]; + } + } + }//end update HAL variables + priv->TxPowerDiff = priv->EEPROMPwDiff; +// Antenna B gain offset to antenna A, bit0~3 + priv->AntennaTxPwDiff[0] = (priv->EEPROMTxPowerDiff & 0xf); + // Antenna C gain offset to antenna A, bit4~7 + priv->AntennaTxPwDiff[1] = ((priv->EEPROMTxPowerDiff & 0xf0)>>4); + // CrystalCap, bit12~15 + priv->CrystalCap = priv->EEPROMCrystalCap; + // ThermalMeter, bit0~3 for RFIC1, bit4~7 for RFIC2 + // 92U does not enable TX power tracking. + priv->ThermalMeter[0] = priv->EEPROMThermalMeter; + }//end if VersionID == VERSION_819xU_A + +//added by vivi, for dlink led, 20080416 + switch(priv->eeprom_CustomerID) + { + case EEPROM_CID_RUNTOP: + priv->CustomerID = RT_CID_819x_RUNTOP; + break; + + case EEPROM_CID_DLINK: + priv->CustomerID = RT_CID_DLINK; + break; + + default: + priv->CustomerID = RT_CID_DEFAULT; + break; + + } + + switch(priv->CustomerID) + { + case RT_CID_819x_RUNTOP: + priv->LedStrategy = SW_LED_MODE2; + break; + + case RT_CID_DLINK: + priv->LedStrategy = SW_LED_MODE4; + break; + + default: + priv->LedStrategy = SW_LED_MODE0; + break; + + } + + + if(priv->rf_type == RF_1T2R) + { + RT_TRACE(COMP_EPROM, "\n1T2R config\n"); + } + else + { + RT_TRACE(COMP_EPROM, "\n2T4R config\n"); + } + + // 2008/01/16 MH We can only know RF type in the function. So we have to init + // DIG RATR table again. + init_rate_adaptive(dev); + //we need init DIG RATR table here again. + + RT_TRACE(COMP_EPROM, "<===========%s()\n", __FUNCTION__); + return; +} +#endif + +short rtl8192_get_channel_map(struct net_device * dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); +#ifdef ENABLE_DOT11D + if(priv->ChannelPlan > COUNTRY_CODE_GLOBAL_DOMAIN){ + printk("rtl8180_init:Error channel plan! Set to default.\n"); + priv->ChannelPlan= 0; + } + RT_TRACE(COMP_INIT, "Channel plan is %d\n",priv->ChannelPlan); + + rtl819x_set_channel_map(priv->ChannelPlan, priv); +#else + int ch,i; + //Set Default Channel Plan + if(!channels){ + DMESG("No channels, aborting"); + return -1; + } + ch=channels; + priv->ChannelPlan= 0;//hikaru + // set channels 1..14 allowed in given locale + for (i=1; i<=14; i++) { + (priv->ieee80211->channel_map)[i] = (u8)(ch & 0x01); + ch >>= 1; + } +#endif + return 0; +} + +short rtl8192_init(struct net_device *dev) +{ + + struct r8192_priv *priv = ieee80211_priv(dev); + +#ifndef RTL8192SU + memset(&(priv->stats),0,sizeof(struct Stats)); + memset(priv->txqueue_to_outpipemap,0,9); +#ifdef PIPE12 + { + int i=0; + u8 queuetopipe[]={3,2,1,0,4,8,7,6,5}; + memcpy(priv->txqueue_to_outpipemap,queuetopipe,9); +/* for(i=0;i<9;i++) + printk("%d ",priv->txqueue_to_outpipemap[i]); + printk("\n");*/ + } +#else + { + u8 queuetopipe[]={3,2,1,0,4,4,0,4,4}; + memcpy(priv->txqueue_to_outpipemap,queuetopipe,9); +/* for(i=0;i<9;i++) + printk("%d ",priv->txqueue_to_outpipemap[i]); + printk("\n");*/ + } +#endif +#endif + rtl8192_init_priv_variable(dev); + rtl8192_init_priv_lock(priv); + rtl8192_init_priv_task(dev); + rtl8192_get_eeprom_size(dev); + priv->ops->rtl819x_read_eeprom_info(dev); + rtl8192_get_channel_map(dev); + init_hal_dm(dev); + init_timer(&priv->watch_dog_timer); + priv->watch_dog_timer.data = (unsigned long)dev; + priv->watch_dog_timer.function = watch_dog_timer_callback; + + //rtl8192_adapter_start(dev); +#ifdef DEBUG_EPROM + dump_eprom(dev); +#endif + return 0; +} + +/****************************************************************************** + *function: This function actually only set RRSR, RATR and BW_OPMODE registers + * not to do all the hw config as its name says + * input: net_device dev + * output: none + * return: none + * notice: This part need to modified according to the rate set we filtered + * ****************************************************************************/ +void rtl8192_hwconfig(struct net_device* dev) +{ + u32 regRATR = 0, regRRSR = 0; + u8 regBwOpMode = 0, regTmp = 0; + struct r8192_priv *priv = ieee80211_priv(dev); + +// Set RRSR, RATR, and BW_OPMODE registers + // + switch(priv->ieee80211->mode) + { + case WIRELESS_MODE_B: + regBwOpMode = BW_OPMODE_20MHZ; + regRATR = RATE_ALL_CCK; + regRRSR = RATE_ALL_CCK; + break; + case WIRELESS_MODE_A: + regBwOpMode = BW_OPMODE_5G |BW_OPMODE_20MHZ; + regRATR = RATE_ALL_OFDM_AG; + regRRSR = RATE_ALL_OFDM_AG; + break; + case WIRELESS_MODE_G: + regBwOpMode = BW_OPMODE_20MHZ; + regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; + regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; + break; + case WIRELESS_MODE_AUTO: +#ifdef TO_DO_LIST + if (Adapter->bInHctTest) + { + regBwOpMode = BW_OPMODE_20MHZ; + regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; + regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; + } + else +#endif + { + regBwOpMode = BW_OPMODE_20MHZ; + regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS; + regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; + } + break; + case WIRELESS_MODE_N_24G: + // It support CCK rate by default. + // CCK rate will be filtered out only when associated AP does not support it. + regBwOpMode = BW_OPMODE_20MHZ; + regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS; + regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; + break; + case WIRELESS_MODE_N_5G: + regBwOpMode = BW_OPMODE_5G; + regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS; + regRRSR = RATE_ALL_OFDM_AG; + break; + } + + write_nic_byte(dev, BW_OPMODE, regBwOpMode); + { + u32 ratr_value = 0; + ratr_value = regRATR; + if (priv->rf_type == RF_1T2R) + { + ratr_value &= ~(RATE_ALL_OFDM_2SS); + } + write_nic_dword(dev, RATR0, ratr_value); + write_nic_byte(dev, UFWP, 1); + } + regTmp = read_nic_byte(dev, 0x313); + regRRSR = ((regTmp) << 24) | (regRRSR & 0x00ffffff); + write_nic_dword(dev, RRSR, regRRSR); + + // + // Set Retry Limit here + // + write_nic_word(dev, RETRY_LIMIT, + priv->ShortRetryLimit << RETRY_LIMIT_SHORT_SHIFT | \ + priv->LongRetryLimit << RETRY_LIMIT_LONG_SHIFT); + // Set Contention Window here + + // Set Tx AGC + + // Set Tx Antenna including Feedback control + + // Set Auto Rate fallback control + + +} + +#ifdef RTL8192SU +#ifdef USB_RX_AGGREGATION_SUPPORT +u8 rtl8192SU_MapRxPageSizeToIdx(u16 RxPktSize ) +{ + switch(RxPktSize) + { + case 64: return 0; break; + case 128 : return 1; break; + case 256: return 2; break; + case 512: return 3; break; + case 1024: return 4; break; + default: return 0; // We use 64bytes in defult. + } +} +#endif + +// +// Description: +// Initial HW relted registers. +// +// Assumption: +// Config RTL8192S USB MAC, we should config MAC before download FW. +// +// 2008.09.03, Added by Roger. +// +static void rtl8192SU_MacConfigBeforeFwDownloadASIC(struct net_device *dev) +{ + u8 tmpU1b;// i; +// u16 tmpU2b; +// u32 tmpU4b; + u8 PollingCnt = 20; + + RT_TRACE(COMP_INIT, "--->MacConfigBeforeFwDownloadASIC()\n"); + + //2MAC Initialization for power on sequence, Revised by Roger. 2008.09.03. + + // + //<Roger_Notes> Set control path switch to HW control and reset Digital Core, CPU Core and + // MAC I/O to solve FW download fail when system from resume sate. + // 2008.11.04. + // + tmpU1b = read_nic_byte(dev, SYS_CLKR+1); + if(tmpU1b & 0x80) + { + tmpU1b &= 0x3f; + write_nic_byte(dev, SYS_CLKR+1, tmpU1b); + } + // Clear FW RPWM for FW control LPS. by tynli. 2009.02.23 + write_nic_byte(dev, RPWM, 0x0); + + tmpU1b = read_nic_byte(dev, SYS_FUNC_EN+1); + tmpU1b &= 0x73; + write_nic_byte(dev, SYS_FUNC_EN+1, tmpU1b); + udelay(1000); + + //Revised POS, suggested by SD1 Alex, 2008.09.27. + write_nic_byte(dev, SPS0_CTRL+1, 0x53); + write_nic_byte(dev, SPS0_CTRL, 0x57); + + //Enable AFE Macro Block's Bandgap adn Enable AFE Macro Block's Mbias + tmpU1b = read_nic_byte(dev, AFE_MISC); + write_nic_byte(dev, AFE_MISC, (tmpU1b|AFE_BGEN|AFE_MBEN)); + + //Enable PLL Power (LDOA15V) + tmpU1b = read_nic_byte(dev, LDOA15_CTRL); + write_nic_byte(dev, LDOA15_CTRL, (tmpU1b|LDA15_EN)); + + //Enable LDOV12D block + tmpU1b = read_nic_byte(dev, LDOV12D_CTRL); + write_nic_byte(dev, LDOV12D_CTRL, (tmpU1b|LDV12_EN)); + + //mpU1b = read_nic_byte(Adapter, SPS1_CTRL); + //write_nic_byte(dev, SPS1_CTRL, (tmpU1b|SPS1_LDEN)); + + //PlatformSleepUs(2000); + + //Enable Switch Regulator Block + //tmpU1b = read_nic_byte(Adapter, SPS1_CTRL); + //write_nic_byte(dev, SPS1_CTRL, (tmpU1b|SPS1_SWEN)); + + //write_nic_dword(Adapter, SPS1_CTRL, 0x00a7b267); + + tmpU1b = read_nic_byte(dev, SYS_ISO_CTRL+1); + write_nic_byte(dev, SYS_ISO_CTRL+1, (tmpU1b|0x08)); + + //Engineer Packet CP test Enable + tmpU1b = read_nic_byte(dev, SYS_FUNC_EN+1); + write_nic_byte(dev, SYS_FUNC_EN+1, (tmpU1b|0x20)); + + //Support 64k IMEM, suggested by SD1 Alex. + tmpU1b = read_nic_byte(dev, SYS_ISO_CTRL+1); + write_nic_byte(dev, SYS_ISO_CTRL+1, (tmpU1b& 0x68)); + + //Enable AFE clock + tmpU1b = read_nic_byte(dev, AFE_XTAL_CTRL+1); + write_nic_byte(dev, AFE_XTAL_CTRL+1, (tmpU1b& 0xfb)); + + //Enable AFE PLL Macro Block + tmpU1b = read_nic_byte(dev, AFE_PLL_CTRL); + write_nic_byte(dev, AFE_PLL_CTRL, (tmpU1b|0x11)); + + //Attatch AFE PLL to MACTOP/BB/PCIe Digital + tmpU1b = read_nic_byte(dev, SYS_ISO_CTRL); + write_nic_byte(dev, SYS_ISO_CTRL, (tmpU1b&0xEE)); + + // Switch to 40M clock + write_nic_byte(dev, SYS_CLKR, 0x00); + + //SSC Disable + tmpU1b = read_nic_byte(dev, SYS_CLKR); + //write_nic_byte(dev, SYS_CLKR, (tmpU1b&0x5f)); + write_nic_byte(dev, SYS_CLKR, (tmpU1b|0xa0)); + + //Enable MAC clock + tmpU1b = read_nic_byte(dev, SYS_CLKR+1); + write_nic_byte(dev, SYS_CLKR+1, (tmpU1b|0x18)); + + //Revised POS, suggested by SD1 Alex, 2008.09.27. + write_nic_byte(dev, PMC_FSM, 0x02); + + //Enable Core digital and enable IOREG R/W + tmpU1b = read_nic_byte(dev, SYS_FUNC_EN+1); + write_nic_byte(dev, SYS_FUNC_EN+1, (tmpU1b|0x08)); + + //Enable REG_EN + tmpU1b = read_nic_byte(dev, SYS_FUNC_EN+1); + write_nic_byte(dev, SYS_FUNC_EN+1, (tmpU1b|0x80)); + + //Switch the control path to FW + tmpU1b = read_nic_byte(dev, SYS_CLKR+1); + write_nic_byte(dev, SYS_CLKR+1, (tmpU1b|0x80)& 0xBF); + + write_nic_byte(dev, CMDR, 0xFC); + write_nic_byte(dev, CMDR+1, 0x37); + + //Fix the RX FIFO issue(usb error), 970410 + tmpU1b = read_nic_byte_E(dev, 0x5c); + write_nic_byte_E(dev, 0x5c, (tmpU1b|BIT7)); + + //For power save, used this in the bit file after 970621 + tmpU1b = read_nic_byte(dev, SYS_CLKR); + write_nic_byte(dev, SYS_CLKR, tmpU1b&(~SYS_CPU_CLKSEL)); + + // Revised for 8051 ROM code wrong operation. Added by Roger. 2008.10.16. + write_nic_byte_E(dev, 0x1c, 0x80); + + // + // <Roger_EXP> To make sure that TxDMA can ready to download FW. + // We should reset TxDMA if IMEM RPT was not ready. + // Suggested by SD1 Alex. 2008.10.23. + // + do + { + tmpU1b = read_nic_byte(dev, TCR); + if((tmpU1b & TXDMA_INIT_VALUE) == TXDMA_INIT_VALUE) + break; + //PlatformStallExecution(5); + udelay(5); + }while(PollingCnt--); // Delay 1ms + + if(PollingCnt <= 0 ) + { + RT_TRACE(COMP_INIT, "MacConfigBeforeFwDownloadASIC(): Polling TXDMA_INIT_VALUE timeout!! Current TCR(%#x)\n", tmpU1b); + tmpU1b = read_nic_byte(dev, CMDR); + write_nic_byte(dev, CMDR, tmpU1b&(~TXDMA_EN)); + udelay(2); + write_nic_byte(dev, CMDR, tmpU1b|TXDMA_EN);// Reset TxDMA + } + + + RT_TRACE(COMP_INIT, "<---MacConfigBeforeFwDownloadASIC()\n"); +} +#ifdef USB_RX_AGGREGATION_SUPPORT +void rtl8192SU_HalUsbRxAggr8192SUsb(struct net_device *dev, bool Value) +{ + struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev); + PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;; + + + // + // <Roger_Notes> We decrease Rx page aggregated threshold in B/G mode. + // 2008.10.29 + // + if(priv->ieee80211->mode == WIRELESS_MODE_B || priv->ieee80211->mode == WIRELESS_MODE_G) + {// Overwrite current settings to disable Rx Aggregation. + Value = false; + } + + // Alway set Rx Aggregation to Disable if current platform is Win2K USB 1.1, by Emily + //if(PLATFORM_LIMITED_RX_BUF_SIZE(Adapter)) + // Value = FALSE; + + // Always set Rx Aggregation to Disable if connected AP is Realtek AP, by Joseph + //if(pHTInfo->bCurrentRT2RTAggregation) + // Value = FALSE; + + // The RX aggregation may be enabled/disabled dynamically according current traffic stream. + //Enable Rx aggregation if downlink traffic is busier than uplink traffic. by Guangan + if(priv->bCurrentRxAggrEnable != Value) + { + priv->bCurrentRxAggrEnable = Value; + //Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_USB_RX_AGGR, (pu1Byte)&pHalData->bCurrentRxAggrEnable); + { + //u8 Setting = ((pu1Byte)(val))[0]; + u8 Setting = priv->bCurrentRxAggrEnable + u32 ulValue; + + if(Setting==0) + { + // + // <Roger_Notes> Reduce aggregated page threshold to 0x01 and set minimal threshold 0x0a. + // i.e., disable Rx aggregation. + // + ulValue = 0x0001000a; + } + else + { + //PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo; + //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + if (priv->bForcedUsbRxAggr) + {// Using forced settings. + ulValue = priv->ForcedUsbRxAggrInfo; + } + else + {// Using default settings. + + ulValue = (pHTInfo->UsbRxFwAggrEn<<24) | (pHTInfo->UsbRxFwAggrPageNum<<16) | + (pHTInfo->UsbRxFwAggrPacketNum<<8) | (pHTInfo->UsbRxFwAggrTimeout); + } + } + + write_nic_byte(dev, RXDMA_AGG_PG_TH, (u8)((ulValue&0xff0000)>>16)); + write_nic_byte_E(dev, USB_RX_AGG_TIMEOUT, (u8)(ulValue&0xff)); + + priv->LastUsbRxAggrInfoSetting = ulValue; + + RT_TRACE(COMP_HT|COMP_RECV, "Set HW_VAR_USB_RX_AGGR: ulValue(%#x)\n", ulValue); + } + RT_TRACE(COMP_RECV, "HalUsbRxAggr8192SUsb() : Set RxAggregation to %s\n", Value?"ON":"OFF"); + } + +} +#endif + +#ifdef USB_RX_AGGREGATION_SUPPORT +void rtl8192SU_HalUsbRxAggr8192SUsb(struct net_device *dev, bool Value) +{ + struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev); + PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;; + + + // + // <Roger_Notes> We decrease Rx page aggregated threshold in B/G mode. + // 2008.10.29 + // + if((priv->ieee80211->mode & WIRELESS_MODE_B) || (priv->ieee80211->mode & WIRELESS_MODE_G)) + {// Overwrite current settings to disable Rx Aggregation. + Value = false; + } + + // Alway set Rx Aggregation to Disable if current platform is Win2K USB 1.1, by Emily + //if(PLATFORM_LIMITED_RX_BUF_SIZE(Adapter)) + // Value = FALSE; + + // Always set Rx Aggregation to Disable if connected AP is Realtek AP, by Joseph + //if(pHTInfo->bCurrentRT2RTAggregation) + // Value = FALSE; + + // The RX aggregation may be enabled/disabled dynamically according current traffic stream. + //Enable Rx aggregation if downlink traffic is busier than uplink traffic. by Guangan + if(priv->bCurrentRxAggrEnable != Value) + { + priv->bCurrentRxAggrEnable = Value; + //Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_USB_RX_AGGR, (pu1Byte)&pHalData->bCurrentRxAggrEnable); + { + //u8 Setting = ((pu1Byte)(val))[0]; + u8 Setting = priv->bCurrentRxAggrEnable + u32 ulValue; + + if(Setting==0) + { + // + // <Roger_Notes> Reduce aggregated page threshold to 0x01 and set minimal threshold 0x0a. + // i.e., disable Rx aggregation. + // + ulValue = 0x0001000a; + } + else + { + //PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo; + //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + if (priv->bForcedUsbRxAggr) + {// Using forced settings. + ulValue = priv->ForcedUsbRxAggrInfo; + } + else + {// Using default settings. + + ulValue = (pHTInfo->UsbRxFwAggrEn<<24) | (pHTInfo->UsbRxFwAggrPageNum<<16) | + (pHTInfo->UsbRxFwAggrPacketNum<<8) | (pHTInfo->UsbRxFwAggrTimeout); + } + } + + write_nic_byte(dev, RXDMA_AGG_PG_TH, (u8)((ulValue&0xff0000)>>16)); + write_nic_byte_E(dev, USB_RX_AGG_TIMEOUT, (u8)(ulValue&0xff)); + + priv->LastUsbRxAggrInfoSetting = ulValue; + + RT_TRACE(COMP_HT|COMP_RECV, "Set HW_VAR_USB_RX_AGGR: ulValue(%#x)\n", ulValue); + } + RT_TRACE(COMP_RECV, "HalUsbRxAggr8192SUsb() : Set RxAggregation to %s\n", Value?"ON":"OFF"); + } + +} + +u8 rtl8192SU_MapRxPageSizeToIdx(u16 RxPktSize ) +{ + switch(RxPktSize) + { + case 64: return 0; break; + case 128 : return 1; break; + case 256: return 2; break; + case 512: return 3; break; + case 1024: return 4; break; + default: return 0; // We use 64bytes in defult. + } +} +#endif + +#if 0 +static void rtl8192SU_SetHwRegAmpduMinSpace(struct net_device *dev, u8 MinSpaceCfg) +{ + struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev); + struct ieee80211_device* ieee = priv->ieee80211; + u8 MinSpacingToSet; + u8 SecMinSpace; + +#ifdef RTL8192S_PREPARE_FOR_NORMAL_RELEASE + MinSpacingToSet = MinSpaceCfg; + if(MinSpacingToSet <= 7) + { + switch(ieee->pairwise_key_type) + { + case KEY_TYPE_NA: SecMinSpace = 0; break; + case KEY_TYPE_CCMP: + case KEY_TYPE_WEP40: + case KEY_TYPE_WEP104: + case KEY_TYPE_TKIP: SecMinSpace = 6; break; + default: SecMinSpace = 7; break; + } + + if(MinSpacingToSet < SecMinSpace) + MinSpacingToSet = SecMinSpace; + priv->MinSpaceCfg = ((priv->MinSpaceCfg&0xf8) |MinSpacingToSet); + RT_TRACE(COMP_SEC, "Set AMPDU_MIN_SPACE: %x\n", priv->MinSpaceCfg); + write_nic_byte(dev, AMPDU_MIN_SPACE, priv->MinSpaceCfg); + } + +#else + MinSpacingToSet = MinSpaceCfg; + MinSpacingToSet &= 0x07; // We only care about bit[2:0] + priv->MinSpaceCfg |= MinSpacingToSet; + RT_TRACE(COMP_SEC, "Set AMPDU_MIN_SPACE: %x\n", priv->MinSpaceCfg); + write_nic_byte(dev, AMPDU_MIN_SPACE, priv->MinSpaceCfg);//FIXLZM +#endif +} +#endif + +// +// Description: +// Initial HW relted registers. +// +// Assumption: +// 1. This function is only invoked at driver intialization once. +// 2. PASSIVE LEVEL. +// +// 2008.06.10, Added by Roger. +// +static void rtl8192SU_MacConfigAfterFwDownload(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev); + //PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo; + //u8 tmpU1b, RxPageCfg, i; + u16 tmpU2b; + u8 tmpU1b;//, i; + + + RT_TRACE(COMP_INIT, "--->MacConfigAfterFwDownload()\n"); + + // Enable Tx/Rx + tmpU2b = (BBRSTn|BB_GLB_RSTn|SCHEDULE_EN|MACRXEN|MACTXEN|DDMA_EN| + FW2HW_EN|RXDMA_EN|TXDMA_EN|HCI_RXDMA_EN|HCI_TXDMA_EN); //3 + //Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_COMMAND, &tmpU1b ); + write_nic_word(dev, CMDR, tmpU2b); //LZM REGISTER COM 090305 + + // Loopback mode or not + priv->LoopbackMode = RTL8192SU_NO_LOOPBACK; // Set no loopback as default. + if(priv->LoopbackMode == RTL8192SU_NO_LOOPBACK) + tmpU1b = LBK_NORMAL; + else if (priv->LoopbackMode == RTL8192SU_MAC_LOOPBACK ) + tmpU1b = LBK_MAC_DLB; + else + RT_TRACE(COMP_INIT, "Serious error: wrong loopback mode setting\n"); + + //Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_LBK_MODE, &tmpU1b); + write_nic_byte(dev, LBKMD_SEL, tmpU1b); + + // Set RCR + write_nic_dword(dev, RCR, priv->ReceiveConfig); + RT_TRACE(COMP_INIT, "MacConfigAfterFwDownload(): Current RCR settings(%#x)\n", priv->ReceiveConfig); + + + // Set RQPN + // + // <Roger_Notes> 2008.08.18. + // 6 endpoints: + // (1) Page number on CMDQ is 0x03. + // (2) Page number on BCNQ, HQ and MGTQ is 0. + // (3) Page number on BKQ, BEQ, VIQ and VOQ are 0x07. + // (4) Page number on PUBQ is 0xdd + // + // 11 endpoints: + // (1) Page number on CMDQ is 0x00. + // (2) Page number on BCNQ is 0x02, HQ and MGTQ are 0x03. + // (3) Page number on BKQ, BEQ, VIQ and VOQ are 0x07. + // (4) Page number on PUBQ is 0xd8 + // + //write_nic_dword(Adapter, 0xa0, 0x07070707); //BKQ, BEQ, VIQ and VOQ + //write_nic_byte(dev, 0xa4, 0x00); // HCCAQ +#if 0 //LZM 090219 +#ifdef USE_SIX_USB_ENDPOINT + //write_nic_dword(Adapter, 0xa5, 0x00000003); //CMDQ, MGTQ, HQ and BCNQ + //write_nic_byte(dev, 0xa9, 0xdd); // PUBQ + tmpU1b = read_nic_byte(dev, 0xab); // RQPN + write_nic_byte(dev, 0xab, tmpU1b|BIT7|BIT6);// reduce to 6 endpoints. +#else + write_nic_dword(dev, 0xa5, 0x02030300); //CMDQ, MGTQ, HQ and BCNQ + write_nic_byte(dev, 0xa9, 0xd8); // PUBQ + tmpU1b = read_nic_byte(dev, 0xab); // RQPN + write_nic_byte(dev, 0xab, (tmpU1b&(~BIT6))|BIT7); // Disable reduced endpoint. +#endif +#endif + +#ifdef USB_RX_AGGREGATION_SUPPORT + // Size of Tx/Rx packet buffer. + tmpU1b = read_nic_byte(dev, PBP); + RxPageCfg = rtl8192SU_MapRxPageSizeToIdx(priv->ieee80211->pHTInfo.UsbRxPageSize); + write_nic_byte(dev, PBP, tmpU1b|RxPageCfg); // Set page size of Rx packet buffer to 128 bytes. + tmpU1b = read_nic_byte(dev, RXDMA); + + write_nic_byte(dev, RXDMA, tmpU1b|RXDMA_AGG_EN); // Rx aggregation enable. + //PlatformIOWrite1Byte(Adapter, RXDMA_AGG_PG_TH, 0x14); // Set page size of RxDMA aggregation threshold, default: 20. + //write_nic_byte(dev, RXDMA_AGG_PG_TH, 0x40); // By Scott's suggestion, 2008.09.30.//92su del + //write_nic_byte(dev, USB_RX_AGG_TIMEOUT, RXDMA_AGG_TIMEOUT_17_4_MS); // Set aggregation time-out to 17ms/4. + rtl8192SU_HalUsbRxAggr8192SUsb(dev, true); +#endif + + // Fix the RX FIFO issue(USB error), Rivesed by Roger, 2008-06-14 + tmpU1b = read_nic_byte_E(dev, 0x5C); + write_nic_byte_E(dev, 0x5C, tmpU1b|BIT7); + + // + // Revise USB PHY to solve the issue of Rx payload error, Rivesed by Roger, 2008-04-10 + // Suggest by SD1 Alex. + // + // <Roger_Notes> The following operation are ONLY for USB PHY test chip. + // 2008.10.07. + // +#if RTL8192SU_USB_PHY_TEST + write_nic_byte(dev, 0x41,0xf4); + write_nic_byte(dev, 0x40,0x00); + write_nic_byte(dev, 0x42,0x00); + write_nic_byte(dev, 0x42,0x01); + write_nic_byte(dev, 0x40,0x0f); + write_nic_byte(dev, 0x42,0x00); + write_nic_byte(dev, 0x42,0x01); +#endif + +#if 0 //LZM 090219 + // + // Suggested by SD1 Alex, 2008-06-14. + // + write_nic_byte(dev, TXOP_STALL_CTRL, 0x80);//NAV + + + // + // Set Data Auto Rate Fallback Retry Count register. + // + write_nic_dword(dev, DARFRC, 0x04010000); + write_nic_dword(dev, DARFRC+4, 0x09070605); + write_nic_dword(dev, RARFRC, 0x04010000); + write_nic_dword(dev, RARFRC+4, 0x09070605); + + // Set Data Auto Rate Fallback Reg. Added by Roger, 2008.09.22. + for (i = 0; i < 8; i++) +#ifdef RTL8192SU_DISABLE_CCK_RATE + write_nic_dword(dev, ARFR0+i*4, 0x1f0ff0f0); +#else + write_nic_dword(dev, ARFR0+i*4, 0x1f0ffff0); +#endif + + // + // Set driver info, we only accept PHY status now. + // + //write_nic_byte(dev, RXDRVINFO_SZ, 4); + + // + // Aggregation length limit. Revised by Roger. 2008.09.22. + // + write_nic_dword(dev, AGGLEN_LMT_L, 0x66666666); // Long GI + write_nic_byte(dev, AGGLEN_LMT_H, 0x06); // Set AMPDU length to 12Kbytes for ShortGI case. + + // + // For Min Spacing configuration. + // + //Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_AMPDU_MIN_SPACE, (u8*)(&Adapter->MgntInfo.MinSpaceCfg)); + rtl8192SU_SetHwRegAmpduMinSpace(dev,priv->MinSpaceCfg); +#endif + + // For EFUSE init configuration. + //if (IS_BOOT_FROM_EFUSE(Adapter)) // We may R/W EFUSE in EFUSE mode + if (priv->bBootFromEfuse) + { + u8 tempval; + + tempval = read_nic_byte(dev, SYS_ISO_CTRL+1); + tempval &= 0xFE; + write_nic_byte(dev, SYS_ISO_CTRL+1, tempval); + + // Enable LDO 2.5V for write action + //tempval = read_nic_byte(Adapter, EFUSE_TEST+3); + //write_nic_byte(Adapter, EFUSE_TEST+3, (tempval | 0x80)); + + // Change Efuse Clock for write action + //write_nic_byte(Adapter, EFUSE_CLK, 0x03); + + // Change Program timing + write_nic_byte(dev, EFUSE_CTRL+3, 0x72); + //printk("!!!!!!!!!!!!!!!!!!!!!%s: write 0x33 with 0x72\n",__FUNCTION__); + RT_TRACE(COMP_INIT, "EFUSE CONFIG OK\n"); + } + + + RT_TRACE(COMP_INIT, "<---MacConfigAfterFwDownload()\n"); +} + +void rtl8192SU_HwConfigureRTL8192SUsb(struct net_device *dev) +{ + + struct r8192_priv *priv = ieee80211_priv(dev); + u8 regBwOpMode = 0; + u32 regRATR = 0, regRRSR = 0; + u8 regTmp = 0; + u32 i = 0; + + //1 This part need to modified according to the rate set we filtered!! + // + // Set RRSR, RATR, and BW_OPMODE registers + // + switch(priv->ieee80211->mode) + { + case WIRELESS_MODE_B: + regBwOpMode = BW_OPMODE_20MHZ; + regRATR = RATE_ALL_CCK; + regRRSR = RATE_ALL_CCK; + break; + case WIRELESS_MODE_A: + regBwOpMode = BW_OPMODE_5G |BW_OPMODE_20MHZ; + regRATR = RATE_ALL_OFDM_AG; + regRRSR = RATE_ALL_OFDM_AG; + break; + case WIRELESS_MODE_G: + regBwOpMode = BW_OPMODE_20MHZ; + regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; + regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; + break; + case WIRELESS_MODE_AUTO: + if (priv->bInHctTest) + { + regBwOpMode = BW_OPMODE_20MHZ; + regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; + regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; + } + else + { + regBwOpMode = BW_OPMODE_20MHZ; + regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS; + regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; + } + break; + case WIRELESS_MODE_N_24G: + // It support CCK rate by default. + // CCK rate will be filtered out only when associated AP does not support it. + regBwOpMode = BW_OPMODE_20MHZ; + regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS; + regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; + break; + case WIRELESS_MODE_N_5G: + regBwOpMode = BW_OPMODE_5G; + regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS; + regRRSR = RATE_ALL_OFDM_AG; + break; + } + + // + // <Roger_Notes> We disable CCK response rate until FIB CCK rate IC's back. + // 2008.09.23. + // + regTmp = read_nic_byte(dev, INIRTSMCS_SEL); +#ifdef RTL8192SU_DISABLE_CCK_RATE + regRRSR = ((regRRSR & 0x000ffff0)<<8) | regTmp; +#else + regRRSR = ((regRRSR & 0x000fffff)<<8) | regTmp; +#endif + + // + // Update SIFS timing. + // + //priv->SifsTime = 0x0e0e0a0a; + //Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_SIFS, (pu1Byte)&pHalData->SifsTime); + { u8 val[4] = {0x0e, 0x0e, 0x0a, 0x0a}; + // SIFS for CCK Data ACK + write_nic_byte(dev, SIFS_CCK, val[0]); + // SIFS for CCK consecutive tx like CTS data! + write_nic_byte(dev, SIFS_CCK+1, val[1]); + + // SIFS for OFDM Data ACK + write_nic_byte(dev, SIFS_OFDM, val[2]); + // SIFS for OFDM consecutive tx like CTS data! + write_nic_byte(dev, SIFS_OFDM+1, val[3]); + } + + write_nic_dword(dev, INIRTSMCS_SEL, regRRSR); + write_nic_byte(dev, BW_OPMODE, regBwOpMode); + + // + // Suggested by SD1 Alex, 2008-06-14. + // + //PlatformEFIOWrite1Byte(Adapter, TXOP_STALL_CTRL, 0x80);//NAV to protect all TXOP. + + // + // Set Data Auto Rate Fallback Retry Count register. + // + write_nic_dword(dev, DARFRC, 0x02010000); + write_nic_dword(dev, DARFRC+4, 0x06050403); + write_nic_dword(dev, RARFRC, 0x02010000); + write_nic_dword(dev, RARFRC+4, 0x06050403); + + // Set Data Auto Rate Fallback Reg. Added by Roger, 2008.09.22. + for (i = 0; i < 8; i++) +#ifdef RTL8192SU_DISABLE_CCK_RATE + write_nic_dword(dev, ARFR0+i*4, 0x1f0ff0f0); +#else + write_nic_dword(dev, ARFR0+i*4, 0x1f0ffff0); +#endif + + // + // Aggregation length limit. Revised by Roger. 2008.09.22. + // + write_nic_byte(dev, AGGLEN_LMT_H, 0x0f); // Set AMPDU length to 12Kbytes for ShortGI case. + write_nic_dword(dev, AGGLEN_LMT_L, 0xddd77442); // Long GI + write_nic_dword(dev, AGGLEN_LMT_L+4, 0xfffdd772); + + // Set NAV protection length + write_nic_word(dev, NAV_PROT_LEN, 0x0080); + + // Set TXOP stall control for several queue/HI/BCN/MGT/ + write_nic_byte(dev, TXOP_STALL_CTRL, 0x00); // NAV Protect next packet. + + // Set MSDU lifetime. + write_nic_byte(dev, MLT, 0x8f); + + // Set CCK/OFDM SIFS + write_nic_word(dev, SIFS_CCK, 0x0a0a); // CCK SIFS shall always be 10us. + write_nic_word(dev, SIFS_OFDM, 0x0e0e); + + write_nic_byte(dev, ACK_TIMEOUT, 0x40); + + // CF-END Threshold + write_nic_byte(dev, CFEND_TH, 0xFF); + + // + // For Min Spacing configuration. + // + switch(priv->rf_type) + { + case RF_1T2R: + case RF_1T1R: + RT_TRACE(COMP_INIT, "Initializeadapter: RF_Type%s\n", (priv->rf_type==RF_1T1R? "(1T1R)":"(1T2R)")); + priv->MinSpaceCfg = (MAX_MSS_DENSITY_1T<<3); + break; + case RF_2T2R: + case RF_2T2R_GREEN: + RT_TRACE(COMP_INIT, "Initializeadapter:RF_Type(2T2R)\n"); + priv->MinSpaceCfg = (MAX_MSS_DENSITY_2T<<3); + break; + } + write_nic_byte(dev, AMPDU_MIN_SPACE, priv->MinSpaceCfg); + + //LZM 090219 + // + // For Min Spacing configuration. + // + //priv->MinSpaceCfg = 0x00; + //rtl8192SU_SetHwRegAmpduMinSpace(dev, priv->MinSpaceCfg); +} + +#endif + +#ifdef RTL8192SU +// Description: Initial HW relted registers. +// +// Assumption: This function is only invoked at driver intialization once. +// +// 2008.06.10, Added by Roger. +bool rtl8192SU_adapter_start(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + //u32 dwRegRead = 0; + //bool init_status = true; + //u32 ulRegRead; + bool rtStatus = true; + //u8 PipeIndex; + //u8 eRFPath, tmpU1b; + u8 fw_download_times = 1; + + + RT_TRACE(COMP_INIT, "--->InitializeAdapter8192SUsb()\n"); + + //pHalData->bGPIOChangeRF = FALSE; + + + // + // <Roger_Notes> 2008.06.15. + // + // Initialization Steps on RTL8192SU: + // a. MAC initialization prior to sending down firmware code. + // b. Download firmware code step by step(i.e., IMEM, EMEM, DMEM). + // c. MAC configuration after firmware has been download successfully. + // d. Initialize BB related configurations. + // e. Initialize RF related configurations. + // f. Start to BulkIn transfer. + // + + // + //a. MAC initialization prior to send down firmware code. + // +start: + rtl8192SU_MacConfigBeforeFwDownloadASIC(dev); + + // + //b. Download firmware code step by step(i.e., IMEM, EMEM, DMEM). + // + rtStatus = FirmwareDownload92S(dev); + if(rtStatus != true) + { + if(fw_download_times == 1){ + RT_TRACE(COMP_INIT, "InitializeAdapter8192SUsb(): Download Firmware failed once, Download again!!\n"); + fw_download_times = fw_download_times + 1; + goto start; + }else{ + RT_TRACE(COMP_INIT, "InitializeAdapter8192SUsb(): Download Firmware failed twice, end!!\n"); + goto end; + } + } + // + //c. MAC configuration after firmware has been download successfully. + // + rtl8192SU_MacConfigAfterFwDownload(dev); + +#if (RTL8192S_DISABLE_FW_DM == 1) + write_nic_dword(dev, WFM5, FW_DM_DISABLE); +#endif + //priv->bLbusEnable = TRUE; + //if(priv->RegRfOff == TRUE) + // priv->eRFPowerState = eRfOff; + + // Save target channel + // <Roger_Notes> Current Channel will be updated again later. + //priv->CurrentChannel = Channel; + rtStatus = PHY_MACConfig8192S(dev);//===>ok + if(rtStatus != true) + { + RT_TRACE(COMP_INIT, "InitializeAdapter8192SUsb(): Fail to configure MAC!!\n"); + goto end; + } + if (1){ + int i; + for (i=0; i<4; i++) + write_nic_dword(dev,WDCAPARA_ADD[i], 0x5e4322); + write_nic_byte(dev,AcmHwCtrl, 0x01); + } + + + // + //d. Initialize BB related configurations. + // + + rtStatus = PHY_BBConfig8192S(dev);//===>ok + if(rtStatus != true) + { + RT_TRACE(COMP_INIT, "InitializeAdapter8192SUsb(): Fail to configure BB!!\n"); + goto end; + } + + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x58);//===>ok + + // + // e. Initialize RF related configurations. + // + // 2007/11/02 MH Before initalizing RF. We can not use FW to do RF-R/W. + priv->Rf_Mode = RF_OP_By_SW_3wire; + + // For RF test only from Scott's suggestion + //write_nic_byte(dev, 0x27, 0xDB); + //write_nic_byte(dev, 0x1B, 0x07); + + + write_nic_byte(dev, AFE_XTAL_CTRL+1, 0xDB); + + // <Roger_Notes> The following IOs are configured for each RF modules. + // Enable RF module and reset RF and SDM module. 2008.11.17. + if(priv->card_8192_version == VERSION_8192S_ACUT) + write_nic_byte(dev, SPS1_CTRL+3, (u8)(RF_EN|RF_RSTB|RF_SDMRSTB)); // Fix A-Cut bug. + else + write_nic_byte(dev, RF_CTRL, (u8)(RF_EN|RF_RSTB|RF_SDMRSTB)); + + rtStatus = PHY_RFConfig8192S(dev);//===>ok + if(rtStatus != true) + { + RT_TRACE(COMP_INIT, "InitializeAdapter8192SUsb(): Fail to configure RF!!\n"); + goto end; + } + + + // Set CCK and OFDM Block "ON" + rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn, 0x1); + rtl8192_setBBreg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1); + + // + // Turn off Radio B while RF type is 1T1R by SD3 Wilsion's request. + // Revised by Roger, 2008.12.18. + // + if(priv->rf_type == RF_1T1R) + { + // This is needed for PHY_REG after 20081219 + rtl8192_setBBreg(dev, rFPGA0_RFMOD, 0xff000000, 0x03); + // This is needed for PHY_REG before 20081219 + //PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, bMaskByte0, 0x11); + } + +#if (RTL8192SU_DISABLE_IQK==0) + // For 1T2R IQK only currently. + if (priv->card_8192_version == VERSION_8192S_BCUT) + { + PHY_IQCalibrateBcut(dev); + } + else if (priv->card_8192_version == VERSION_8192S_ACUT) + { + PHY_IQCalibrate(dev); + } +#endif + + //LZM 090219 + // Set CCK and OFDM Block "ON" + //rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn, 0x1); + //rtl8192_setBBreg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1); + + + //3//Get hardware version, do it in read eeprom? + //GetHardwareVersion819xUsb(Adapter); + + //3// + //3 //Set Hardware + //3// + rtl8192SU_HwConfigureRTL8192SUsb(dev);//==>ok + + // + // <Roger_Notes> We set MAC address here if autoload was failed before, + // otherwise IDR0 will NOT contain any value. + // + write_nic_dword(dev, IDR0, ((u32*)dev->dev_addr)[0]); + write_nic_word(dev, IDR4, ((u16*)(dev->dev_addr + 4))[0]); + if(!priv->bInHctTest) + { + if(priv->ResetProgress == RESET_TYPE_NORESET) + { + //RT_TRACE(COMP_MLME, DBG_LOUD, ("Initializeadapter8192SUsb():RegWirelessMode(%#x) \n", Adapter->RegWirelessMode)); + //Adapter->HalFunc.SetWirelessModeHandler(Adapter, Adapter->RegWirelessMode); + rtl8192_SetWirelessMode(dev, priv->ieee80211->mode);//===>ok + } + } + else + { + priv->ieee80211->mode = WIRELESS_MODE_G; + rtl8192_SetWirelessMode(dev, WIRELESS_MODE_G); + } + + //Security related. + //----------------------------------------------------------------------------- + // Set up security related. 070106, by rcnjko: + // 1. Clear all H/W keys. + // 2. Enable H/W encryption/decryption. + //----------------------------------------------------------------------------- + //CamResetAllEntry(Adapter); + //Adapter->HalFunc.EnableHWSecCfgHandler(Adapter); + + //SecClearAllKeys(Adapter); + CamResetAllEntry(dev); + //SecInit(Adapter); + { + u8 SECR_value = 0x0; + SECR_value |= SCR_TxEncEnable; + SECR_value |= SCR_RxDecEnable; + SECR_value |= SCR_NoSKMC; + write_nic_byte(dev, SECR, SECR_value); + } + +#if 0 + + if(pHalData->VersionID == VERSION_8192SU_A) + { + // cosa add for tx power level initialization. + GetTxPowerOriginalOffset(Adapter); + SetTxPowerLevel819xUsb(Adapter, Channel); + } +#endif + + +#ifdef TO_DO_LIST + + //PHY_UpdateInitialGain(dev); + + if(priv->RegRfOff == true) + { // User disable RF via registry. + u8 eRFPath = 0; + + RT_TRACE((COMP_INIT|COMP_RF), "InitializeAdapter8192SUsb(): Turn off RF for RegRfOff ----------\n"); + MgntActSet_RF_State(dev, eRfOff, RF_CHANGE_BY_SW); + // Those action will be discard in MgntActSet_RF_State because off the same state + for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++) + rtl8192_setBBreg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x0); + } + else if(priv->RfOffReason > RF_CHANGE_BY_PS) + { // H/W or S/W RF OFF before sleep. + RT_TRACE((COMP_INIT|COMP_RF), "InitializeAdapter8192SUsb(): Turn off RF for RfOffReason(%d) ----------\n", priv->RfOffReason); + MgntActSet_RF_State(dev, eRfOff, priv->RfOffReason); + } + else + { + priv->eRFPowerState = eRfOn; + priv->RfOffReason = 0; + RT_TRACE((COMP_INIT|COMP_RF), "InitializeAdapter8192SUsb(): RF is on ----------\n"); + } + +#endif + + +// +// f. Start to BulkIn transfer. +// +#ifdef TO_DO_LIST + +#ifndef UNDER_VISTA + { + u8 i; + PlatformAcquireSpinLock(Adapter, RT_RX_SPINLOCK); + + for(PipeIndex=0; PipeIndex < MAX_RX_QUEUE; PipeIndex++) + { + if (PipeIndex == 0) + { + for(i=0; i<32; i++) + HalUsbInMpdu(Adapter, PipeIndex); + } + else + { + //HalUsbInMpdu(Adapter, PipeIndex); + //HalUsbInMpdu(Adapter, PipeIndex); + //HalUsbInMpdu(Adapter, PipeIndex); + } + } + PlatformReleaseSpinLock(Adapter, RT_RX_SPINLOCK); + } +#else + // Joseph add to 819X code base for Vista USB platform. + // This part may need to be add to Hal819xU code base. too. + PlatformUsbEnableInPipes(Adapter); +#endif + + RT_TRACE(COMP_INIT, "HighestOperaRate = %x\n", Adapter->MgntInfo.HighestOperaRate); + + PlatformStartWorkItem( &(pHalData->RtUsbCheckForHangWorkItem) ); + + // + // <Roger_EXP> The following configurations are for ASIC verification temporally. + // 2008.07.10. + // + +#endif + + // + // Read EEPROM TX power index and PHY_REG_PG.txt to capture correct + // TX power index for different rate set. + // + //if(priv->card_8192_version >= VERSION_8192S_ACUT) + { + // Get original hw reg values + PHY_GetHWRegOriginalValue(dev); + + // Write correct tx power index//FIXLZM + PHY_SetTxPowerLevel8192S(dev, priv->chan); + } + + { + u8 tmpU1b = 0; + // EEPROM R/W workaround + tmpU1b = read_nic_byte(dev, MAC_PINMUX_CFG); + write_nic_byte(dev, MAC_PINMUX_CFG, tmpU1b&(~GPIOMUX_EN)); + } + +// +//<Roger_Notes> 2008.08.19. +// We return status here for temporal FPGA verification, 2008.08.19. + +#ifdef RTL8192SU_FW_IQK + write_nic_dword(dev, WFM5, FW_IQK_ENABLE); + ChkFwCmdIoDone(dev); +#endif + + // + // <Roger_Notes> We enable high power mechanism after NIC initialized. + // 2008.11.27. + // + write_nic_dword(dev, WFM5, FW_RA_RESET); + ChkFwCmdIoDone(dev); + write_nic_dword(dev, WFM5, FW_RA_ACTIVE); + ChkFwCmdIoDone(dev); + write_nic_dword(dev, WFM5, FW_RA_REFRESH); + ChkFwCmdIoDone(dev); + write_nic_dword(dev, WFM5, FW_BB_RESET_ENABLE); + +// <Roger_Notes> We return status here for temporal FPGA verification. 2008.05.12. +// +#if RTL8192SU_FPGA_UNSPECIFIED_NETWORK + // + // To send specific number of packets to verify MAC Lookback mode. + // + //SendRandomTxPkt(Adapter, 0); // Burst mode for verification. + //rtStatus = RT_STATUS_FAILURE; + rtStatus = true; + goto end; +#endif + +// The following IO was for FPGA verification purpose. Added by Roger, 2008.09.11. +#if 0 + // 2008/08/19 MH From SD1 Jong, we must write some register for true PHY/MAC FPGA. + write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x30); + write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x30); + + write_nic_byte(dev, rOFDM0_RxDetector1, 0x42); + + //write_nic_dword(Adapter, RCR, 0x817FF02F); + + write_nic_dword(Adapter, rTxAGC_Mcs15_Mcs12, 0x06060606); +#endif +end: +return rtStatus; +} + +#else + +//InitializeAdapter and PhyCfg +bool rtl8192_adapter_start(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + u32 dwRegRead = 0; + bool init_status = true; + RT_TRACE(COMP_INIT, "====>%s()\n", __FUNCTION__); + priv->Rf_Mode = RF_OP_By_SW_3wire; + //for ASIC power on sequence + write_nic_byte_E(dev, 0x5f, 0x80); + mdelay(50); + write_nic_byte_E(dev, 0x5f, 0xf0); + write_nic_byte_E(dev, 0x5d, 0x00); + write_nic_byte_E(dev, 0x5e, 0x80); + write_nic_byte(dev, 0x17, 0x37); + mdelay(10); +//#ifdef TO_DO_LIST + priv->pFirmware->firmware_status = FW_STATUS_0_INIT; + //config CPUReset Register + //Firmware Reset or not? + dwRegRead = read_nic_dword(dev, CPU_GEN); + if (priv->pFirmware->firmware_status == FW_STATUS_0_INIT) + dwRegRead |= CPU_GEN_SYSTEM_RESET; //do nothing here? + else if (priv->pFirmware->firmware_status == FW_STATUS_5_READY) + dwRegRead |= CPU_GEN_FIRMWARE_RESET; + else + RT_TRACE(COMP_ERR, "ERROR in %s(): undefined firmware state(%d)\n", __FUNCTION__, priv->pFirmware->firmware_status); + + write_nic_dword(dev, CPU_GEN, dwRegRead); + //mdelay(30); + //config BB. + rtl8192_BBConfig(dev); + +#if 1 + //Loopback mode or not + priv->LoopbackMode = RTL819xU_NO_LOOPBACK; +// priv->LoopbackMode = RTL819xU_MAC_LOOPBACK; + + dwRegRead = read_nic_dword(dev, CPU_GEN); + if (priv->LoopbackMode == RTL819xU_NO_LOOPBACK) + dwRegRead = ((dwRegRead & CPU_GEN_NO_LOOPBACK_MSK) | CPU_GEN_NO_LOOPBACK_SET); + else if (priv->LoopbackMode == RTL819xU_MAC_LOOPBACK) + dwRegRead |= CPU_CCK_LOOPBACK; + else + RT_TRACE(COMP_ERR, "Serious error in %s(): wrong loopback mode setting(%d)\n", __FUNCTION__, priv->LoopbackMode); + + write_nic_dword(dev, CPU_GEN, dwRegRead); + + //after reset cpu, we need wait for a seconds to write in register. + udelay(500); + + //xiong add for new bitfile:usb suspend reset pin set to 1. //do we need? + write_nic_byte_E(dev, 0x5f, (read_nic_byte_E(dev, 0x5f)|0x20)); + + //Set Hardware + rtl8192_hwconfig(dev); + + //turn on Tx/Rx + write_nic_byte(dev, CMDR, CR_RE|CR_TE); + + //set IDR0 here + write_nic_dword(dev, MAC0, ((u32*)dev->dev_addr)[0]); + write_nic_word(dev, MAC4, ((u16*)(dev->dev_addr + 4))[0]); + + //set RCR + write_nic_dword(dev, RCR, priv->ReceiveConfig); + + //Initialize Number of Reserved Pages in Firmware Queue + write_nic_dword(dev, RQPN1, NUM_OF_PAGE_IN_FW_QUEUE_BK << RSVD_FW_QUEUE_PAGE_BK_SHIFT |\ + NUM_OF_PAGE_IN_FW_QUEUE_BE << RSVD_FW_QUEUE_PAGE_BE_SHIFT | \ + NUM_OF_PAGE_IN_FW_QUEUE_VI << RSVD_FW_QUEUE_PAGE_VI_SHIFT | \ + NUM_OF_PAGE_IN_FW_QUEUE_VO <<RSVD_FW_QUEUE_PAGE_VO_SHIFT); + write_nic_dword(dev, RQPN2, NUM_OF_PAGE_IN_FW_QUEUE_MGNT << RSVD_FW_QUEUE_PAGE_MGNT_SHIFT |\ + NUM_OF_PAGE_IN_FW_QUEUE_CMD << RSVD_FW_QUEUE_PAGE_CMD_SHIFT); + write_nic_dword(dev, RQPN3, APPLIED_RESERVED_QUEUE_IN_FW| \ + NUM_OF_PAGE_IN_FW_QUEUE_BCN<<RSVD_FW_QUEUE_PAGE_BCN_SHIFT +// | NUM_OF_PAGE_IN_FW_QUEUE_PUB<<RSVD_FW_QUEUE_PAGE_PUB_SHIFT + ); + write_nic_dword(dev, RATR0+4*7, (RATE_ALL_OFDM_AG | RATE_ALL_CCK)); + + //Set AckTimeout + // TODO: (it value is only for FPGA version). need to be changed!!2006.12.18, by Emily + write_nic_byte(dev, ACK_TIMEOUT, 0x30); + +// RT_TRACE(COMP_INIT, "%s():priv->ResetProgress is %d\n", __FUNCTION__,priv->ResetProgress); + if(priv->ResetProgress == RESET_TYPE_NORESET) + rtl8192_SetWirelessMode(dev, priv->ieee80211->mode); + if(priv->ResetProgress == RESET_TYPE_NORESET){ + CamResetAllEntry(dev); + { + u8 SECR_value = 0x0; + SECR_value |= SCR_TxEncEnable; + SECR_value |= SCR_RxDecEnable; + SECR_value |= SCR_NoSKMC; + write_nic_byte(dev, SECR, SECR_value); + } + } + + //Beacon related + write_nic_word(dev, ATIMWND, 2); + write_nic_word(dev, BCN_INTERVAL, 100); + + { +#define DEFAULT_EDCA 0x005e4332 + int i; + for (i=0; i<QOS_QUEUE_NUM; i++) + write_nic_dword(dev, WDCAPARA_ADD[i], DEFAULT_EDCA); + } +#ifdef USB_RX_AGGREGATION_SUPPORT + //3 For usb rx firmware aggregation control + if(priv->ResetProgress == RESET_TYPE_NORESET) + { + u32 ulValue; + PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo; + ulValue = (pHTInfo->UsbRxFwAggrEn<<24) | (pHTInfo->UsbRxFwAggrPageNum<<16) | + (pHTInfo->UsbRxFwAggrPacketNum<<8) | (pHTInfo->UsbRxFwAggrTimeout); + /* + * If usb rx firmware aggregation is enabled, + * when anyone of three threshold conditions above is reached, + * firmware will send aggregated packet to driver. + */ + write_nic_dword(dev, 0x1a8, ulValue); + priv->bCurrentRxAggrEnable = true; + } +#endif + + rtl8192_phy_configmac(dev); + + if (priv->card_8192_version == (u8) VERSION_819xU_A) + { + rtl8192_phy_getTxPower(dev); + rtl8192_phy_setTxPower(dev, priv->chan); + } + + + priv->usb_error = false; + //Firmware download + init_status = init_firmware(dev); + if(!init_status) + { + RT_TRACE(COMP_ERR,"ERR!!! %s(): Firmware download is failed\n", __FUNCTION__); + return init_status; + } + RT_TRACE(COMP_INIT, "%s():after firmware download\n", __FUNCTION__); + // +#ifdef TO_DO_LIST +if(Adapter->ResetProgress == RESET_TYPE_NORESET) + { + if(pMgntInfo->RegRfOff == TRUE) + { // User disable RF via registry. + RT_TRACE((COMP_INIT|COMP_RF), DBG_LOUD, ("InitializeAdapter819xUsb(): Turn off RF for RegRfOff ----------\n")); + MgntActSet_RF_State(Adapter, eRfOff, RF_CHANGE_BY_SW); + // Those action will be discard in MgntActSet_RF_State because off the same state + for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++) + PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x0); + } + else if(pMgntInfo->RfOffReason > RF_CHANGE_BY_PS) + { // H/W or S/W RF OFF before sleep. + RT_TRACE((COMP_INIT|COMP_RF), DBG_LOUD, ("InitializeAdapter819xUsb(): Turn off RF for RfOffReason(%d) ----------\n", pMgntInfo->RfOffReason)); + MgntActSet_RF_State(Adapter, eRfOff, pMgntInfo->RfOffReason); + } + else + { + pHalData->eRFPowerState = eRfOn; + pMgntInfo->RfOffReason = 0; + RT_TRACE((COMP_INIT|COMP_RF), DBG_LOUD, ("InitializeAdapter819xUsb(): RF is on ----------\n")); + } + } + else + { + if(pHalData->eRFPowerState == eRfOff) + { + MgntActSet_RF_State(Adapter, eRfOff, pMgntInfo->RfOffReason); + // Those action will be discard in MgntActSet_RF_State because off the same state + for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++) + PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x0); + } + } +#endif + //config RF. + if(priv->ResetProgress == RESET_TYPE_NORESET){ + rtl8192_phy_RFConfig(dev); + RT_TRACE(COMP_INIT, "%s():after phy RF config\n", __FUNCTION__); + } + + + if(priv->ieee80211->FwRWRF) + // We can force firmware to do RF-R/W + priv->Rf_Mode = RF_OP_By_FW; + else + priv->Rf_Mode = RF_OP_By_SW_3wire; + + + rtl8192_phy_updateInitGain(dev); + /*--set CCK and OFDM Block "ON"--*/ + rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn, 0x1); + rtl8192_setBBreg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1); + + if(priv->ResetProgress == RESET_TYPE_NORESET) + { + //if D or C cut + u8 tmpvalue = read_nic_byte(dev, 0x301); + if(tmpvalue ==0x03) + { + priv->bDcut = TRUE; + RT_TRACE(COMP_POWER_TRACKING, "D-cut\n"); + } + else + { + priv->bDcut = FALSE; + RT_TRACE(COMP_POWER_TRACKING, "C-cut\n"); + } + dm_initialize_txpower_tracking(dev); + + if(priv->bDcut == TRUE) + { + u32 i, TempCCk; + u32 tmpRegA= rtl8192_QueryBBReg(dev,rOFDM0_XATxIQImbalance,bMaskDWord); + // u32 tmpRegC= rtl8192_QueryBBReg(dev,rOFDM0_XCTxIQImbalance,bMaskDWord); + for(i = 0; i<TxBBGainTableLength; i++) + { + if(tmpRegA == priv->txbbgain_table[i].txbbgain_value) + { + priv->rfa_txpowertrackingindex= (u8)i; + priv->rfa_txpowertrackingindex_real= (u8)i; + priv->rfa_txpowertracking_default= priv->rfa_txpowertrackingindex; + break; + } + } + + TempCCk = rtl8192_QueryBBReg(dev, rCCK0_TxFilter1, bMaskByte2); + + for(i=0 ; i<CCKTxBBGainTableLength ; i++) + { + + if(TempCCk == priv->cck_txbbgain_table[i].ccktxbb_valuearray[0]) + { + priv->cck_present_attentuation_20Mdefault=(u8) i; + break; + } + } + priv->cck_present_attentuation_40Mdefault= 0; + priv->cck_present_attentuation_difference= 0; + priv->cck_present_attentuation = priv->cck_present_attentuation_20Mdefault; + + // pMgntInfo->bTXPowerTracking = FALSE;//TEMPLY DISABLE + } + } + write_nic_byte(dev, 0x87, 0x0); + + +#endif + return init_status; +} + +#endif +/* this configures registers for beacon tx and enables it via + * rtl8192_beacon_tx_enable(). rtl8192_beacon_tx_disable() might + * be used to stop beacon transmission + */ +#if 0 +void rtl8192_start_tx_beacon(struct net_device *dev) +{ + int i; + struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + u16 word; + DMESG("Enabling beacon TX"); + //write_nic_byte(dev, TX_CONF,0xe6);// TX_CONF + //rtl8192_init_beacon(dev); + //set_nic_txring(dev); +// rtl8192_prepare_beacon(dev); + rtl8192_irq_disable(dev); +// rtl8192_beacon_tx_enable(dev); + rtl8192_set_mode(dev,EPROM_CMD_CONFIG); + //write_nic_byte(dev,0x9d,0x20); //DMA Poll + //write_nic_word(dev,0x7a,0); + //write_nic_word(dev,0x7a,0x8000); + + + word = read_nic_word(dev, BcnItv); + word &= ~BcnItv_BcnItv; // clear Bcn_Itv + write_nic_word(dev, BcnItv, word); + + write_nic_word(dev, AtimWnd, + read_nic_word(dev, AtimWnd) &~ AtimWnd_AtimWnd); + + word = read_nic_word(dev, BCN_INTR_ITV); + word &= ~BCN_INTR_ITV_MASK; + + //word |= priv->ieee80211->beacon_interval * + // ((priv->txbeaconcount > 1)?(priv->txbeaconcount-1):1); + // FIXME:FIXME check if correct ^^ worked with 0x3e8; + + write_nic_word(dev, BCN_INTR_ITV, word); + + //write_nic_word(dev,0x2e,0xe002); + //write_nic_dword(dev,0x30,0xb8c7832e); + for(i=0; i<ETH_ALEN; i++) + write_nic_byte(dev, BSSID+i, priv->ieee80211->beacon_cell_ssid[i]); + +// rtl8192_update_msr(dev); + + + //write_nic_byte(dev,CONFIG4,3); /* !!!!!!!!!! */ + + rtl8192_set_mode(dev, EPROM_CMD_NORMAL); + + rtl8192_irq_enable(dev); + + /* VV !!!!!!!!!! VV*/ + /* + rtl8192_set_mode(dev,EPROM_CMD_CONFIG); + write_nic_byte(dev,0x9d,0x00); + rtl8192_set_mode(dev,EPROM_CMD_NORMAL); +*/ +} +#endif +/*************************************************************************** + -------------------------------NET STUFF--------------------------- +***************************************************************************/ + +static struct net_device_stats *rtl8192_stats(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + + return &priv->ieee80211->stats; +} + +bool +HalTxCheckStuck819xUsb( + struct net_device *dev + ) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + u16 RegTxCounter = read_nic_word(dev, 0x128); + bool bStuck = FALSE; + RT_TRACE(COMP_RESET,"%s():RegTxCounter is %d,TxCounter is %d\n",__FUNCTION__,RegTxCounter,priv->TxCounter); + if(priv->TxCounter==RegTxCounter) + bStuck = TRUE; + + priv->TxCounter = RegTxCounter; + + return bStuck; +} + +/* +* <Assumption: RT_TX_SPINLOCK is acquired.> +* First added: 2006.11.19 by emily +*/ +RESET_TYPE +TxCheckStuck(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + u8 QueueID; +// PRT_TCB pTcb; +// u8 ResetThreshold; + bool bCheckFwTxCnt = false; + //unsigned long flags; + + // + // Decide Stuch threshold according to current power save mode + // + +// RT_TRACE(COMP_RESET, " ==> TxCheckStuck()\n"); +// PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK); +// spin_lock_irqsave(&priv->ieee80211->lock,flags); + for (QueueID = 0; QueueID<=BEACON_QUEUE;QueueID ++) + { + if(QueueID == TXCMD_QUEUE) + continue; +#if 1 +#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE + if((skb_queue_len(&priv->ieee80211->skb_waitQ[QueueID]) == 0) && (skb_queue_len(&priv->ieee80211->skb_aggQ[QueueID]) == 0) && (skb_queue_len(&priv->ieee80211->skb_drv_aggQ[QueueID]) == 0)) +#else + if((skb_queue_len(&priv->ieee80211->skb_waitQ[QueueID]) == 0) && (skb_queue_len(&priv->ieee80211->skb_aggQ[QueueID]) == 0)) +#endif + continue; +#endif + + bCheckFwTxCnt = true; + } +// PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK); +// spin_unlock_irqrestore(&priv->ieee80211->lock,flags); +// RT_TRACE(COMP_RESET,"bCheckFwTxCnt is %d\n",bCheckFwTxCnt); +#if 1 + if(bCheckFwTxCnt) + { + if(HalTxCheckStuck819xUsb(dev)) + { + RT_TRACE(COMP_RESET, "TxCheckStuck(): Fw indicates no Tx condition! \n"); + return RESET_TYPE_SILENT; + } + } +#endif + return RESET_TYPE_NORESET; +} + +bool +HalRxCheckStuck819xUsb(struct net_device *dev) +{ + u16 RegRxCounter = read_nic_word(dev, 0x130); + struct r8192_priv *priv = ieee80211_priv(dev); + bool bStuck = FALSE; +//#ifdef RTL8192SU + +//#else + static u8 rx_chk_cnt = 0; + RT_TRACE(COMP_RESET,"%s(): RegRxCounter is %d,RxCounter is %d\n",__FUNCTION__,RegRxCounter,priv->RxCounter); + // If rssi is small, we should check rx for long time because of bad rx. + // or maybe it will continuous silent reset every 2 seconds. + rx_chk_cnt++; + if(priv->undecorated_smoothed_pwdb >= (RateAdaptiveTH_High+5)) + { + rx_chk_cnt = 0; //high rssi, check rx stuck right now. + } + else if(priv->undecorated_smoothed_pwdb < (RateAdaptiveTH_High+5) && + ((priv->CurrentChannelBW!=HT_CHANNEL_WIDTH_20&&priv->undecorated_smoothed_pwdb>=RateAdaptiveTH_Low_40M) || + (priv->CurrentChannelBW==HT_CHANNEL_WIDTH_20&&priv->undecorated_smoothed_pwdb>=RateAdaptiveTH_Low_20M)) ) + { + if(rx_chk_cnt < 2) + { + return bStuck; + } + else + { + rx_chk_cnt = 0; + } + } + else if(((priv->CurrentChannelBW!=HT_CHANNEL_WIDTH_20&&priv->undecorated_smoothed_pwdb<RateAdaptiveTH_Low_40M) || + (priv->CurrentChannelBW==HT_CHANNEL_WIDTH_20&&priv->undecorated_smoothed_pwdb<RateAdaptiveTH_Low_20M)) && + priv->undecorated_smoothed_pwdb >= VeryLowRSSI) + { + if(rx_chk_cnt < 4) + { + //DbgPrint("RSSI < %d && RSSI >= %d, no check this time \n", RateAdaptiveTH_Low, VeryLowRSSI); + return bStuck; + } + else + { + rx_chk_cnt = 0; + //DbgPrint("RSSI < %d && RSSI >= %d, check this time \n", RateAdaptiveTH_Low, VeryLowRSSI); + } + } + else + { + if(rx_chk_cnt < 8) + { + //DbgPrint("RSSI <= %d, no check this time \n", VeryLowRSSI); + return bStuck; + } + else + { + rx_chk_cnt = 0; + //DbgPrint("RSSI <= %d, check this time \n", VeryLowRSSI); + } + } +//#endif + + if(priv->RxCounter==RegRxCounter) + bStuck = TRUE; + + priv->RxCounter = RegRxCounter; + + return bStuck; +} + +RESET_TYPE +RxCheckStuck(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + //int i; + bool bRxCheck = FALSE; + +// RT_TRACE(COMP_RESET," ==> RxCheckStuck()\n"); + //PlatformAcquireSpinLock(Adapter, RT_RX_SPINLOCK); + + if(priv->IrpPendingCount > 1) + bRxCheck = TRUE; + //PlatformReleaseSpinLock(Adapter, RT_RX_SPINLOCK); + +// RT_TRACE(COMP_RESET,"bRxCheck is %d \n",bRxCheck); + if(bRxCheck) + { + if(HalRxCheckStuck819xUsb(dev)) + { + RT_TRACE(COMP_RESET, "RxStuck Condition\n"); + return RESET_TYPE_SILENT; + } + } + return RESET_TYPE_NORESET; +} + + +/** +* This function is called by Checkforhang to check whether we should ask OS to reset driver +* +* \param pAdapter The adapter context for this miniport +* +* Note:NIC with USB interface sholud not call this function because we cannot scan descriptor +* to judge whether there is tx stuck. +* Note: This function may be required to be rewrite for Vista OS. +* <<<Assumption: Tx spinlock has been acquired >>> +* +* 8185 and 8185b does not implement this function. This is added by Emily at 2006.11.24 +*/ +RESET_TYPE +rtl819x_ifcheck_resetornot(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + RESET_TYPE TxResetType = RESET_TYPE_NORESET; + RESET_TYPE RxResetType = RESET_TYPE_NORESET; + RT_RF_POWER_STATE rfState; + +#if (defined (RTL8192SU_FPGA_2MAC_VERIFICATION)||defined (RTL8192SU_ASIC_VERIFICATION)) + return RESET_TYPE_NORESET; +#endif + + rfState = priv->ieee80211->eRFPowerState; + + TxResetType = TxCheckStuck(dev); +#if 1 + if( rfState != eRfOff || + /*ADAPTER_TEST_STATUS_FLAG(Adapter, ADAPTER_STATUS_FW_DOWNLOAD_FAILURE)) &&*/ + (priv->ieee80211->iw_mode != IW_MODE_ADHOC)) + { + // If driver is in the status of firmware download failure , driver skips RF initialization and RF is + // in turned off state. Driver should check whether Rx stuck and do silent reset. And + // if driver is in firmware download failure status, driver should initialize RF in the following + // silent reset procedure Emily, 2008.01.21 + + // Driver should not check RX stuck in IBSS mode because it is required to + // set Check BSSID in order to send beacon, however, if check BSSID is + // set, STA cannot hear any packet a all. Emily, 2008.04.12 + RxResetType = RxCheckStuck(dev); + } +#endif + if(TxResetType==RESET_TYPE_NORMAL || RxResetType==RESET_TYPE_NORMAL) + return RESET_TYPE_NORMAL; + else if(TxResetType==RESET_TYPE_SILENT || RxResetType==RESET_TYPE_SILENT){ + RT_TRACE(COMP_RESET,"%s():silent reset\n",__FUNCTION__); + return RESET_TYPE_SILENT; + } + else + return RESET_TYPE_NORESET; + +} + +void rtl8192_cancel_deferred_work(struct r8192_priv* priv); +int _rtl8192_up(struct net_device *dev); +int rtl8192_close(struct net_device *dev); + + + +void +CamRestoreAllEntry( struct net_device *dev) +{ + u8 EntryId = 0; + struct r8192_priv *priv = ieee80211_priv(dev); + u8* MacAddr = priv->ieee80211->current_network.bssid; + + static u8 CAM_CONST_ADDR[4][6] = { + {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x02}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}}; + static u8 CAM_CONST_BROAD[] = + {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + + RT_TRACE(COMP_SEC, "CamRestoreAllEntry: \n"); + + + if ((priv->ieee80211->pairwise_key_type == KEY_TYPE_WEP40)|| + (priv->ieee80211->pairwise_key_type == KEY_TYPE_WEP104)) + { + + for(EntryId=0; EntryId<4; EntryId++) + { + { + MacAddr = CAM_CONST_ADDR[EntryId]; + setKey(dev, + EntryId , + EntryId, + priv->ieee80211->pairwise_key_type, + MacAddr, + 0, + NULL); + } + } + + } + else if(priv->ieee80211->pairwise_key_type == KEY_TYPE_TKIP) + { + + { + if(priv->ieee80211->iw_mode == IW_MODE_ADHOC) + setKey(dev, + 4, + 0, + priv->ieee80211->pairwise_key_type, + (u8*)dev->dev_addr, + 0, + NULL); + else + setKey(dev, + 4, + 0, + priv->ieee80211->pairwise_key_type, + MacAddr, + 0, + NULL); + } + } + else if(priv->ieee80211->pairwise_key_type == KEY_TYPE_CCMP) + { + + { + if(priv->ieee80211->iw_mode == IW_MODE_ADHOC) + setKey(dev, + 4, + 0, + priv->ieee80211->pairwise_key_type, + (u8*)dev->dev_addr, + 0, + NULL); + else + setKey(dev, + 4, + 0, + priv->ieee80211->pairwise_key_type, + MacAddr, + 0, + NULL); + } + } + + + + if(priv->ieee80211->group_key_type == KEY_TYPE_TKIP) + { + MacAddr = CAM_CONST_BROAD; + for(EntryId=1 ; EntryId<4 ; EntryId++) + { + { + setKey(dev, + EntryId, + EntryId, + priv->ieee80211->group_key_type, + MacAddr, + 0, + NULL); + } + } + if(priv->ieee80211->iw_mode == IW_MODE_ADHOC) + setKey(dev, + 0, + 0, + priv->ieee80211->group_key_type, + CAM_CONST_ADDR[0], + 0, + NULL); + } + else if(priv->ieee80211->group_key_type == KEY_TYPE_CCMP) + { + MacAddr = CAM_CONST_BROAD; + for(EntryId=1; EntryId<4 ; EntryId++) + { + { + setKey(dev, + EntryId , + EntryId, + priv->ieee80211->group_key_type, + MacAddr, + 0, + NULL); + } + } + + if(priv->ieee80211->iw_mode == IW_MODE_ADHOC) + setKey(dev, + 0 , + 0, + priv->ieee80211->group_key_type, + CAM_CONST_ADDR[0], + 0, + NULL); + } +} +////////////////////////////////////////////////////////////// +// This function is used to fix Tx/Rx stop bug temporarily. +// This function will do "system reset" to NIC when Tx or Rx is stuck. +// The method checking Tx/Rx stuck of this function is supported by FW, +// which reports Tx and Rx counter to register 0x128 and 0x130. +////////////////////////////////////////////////////////////// +void +rtl819x_ifsilentreset(struct net_device *dev) +{ + //OCTET_STRING asocpdu; + struct r8192_priv *priv = ieee80211_priv(dev); + u8 reset_times = 0; + int reset_status = 0; + struct ieee80211_device *ieee = priv->ieee80211; + + + // 2007.07.20. If we need to check CCK stop, please uncomment this line. + //bStuck = Adapter->HalFunc.CheckHWStopHandler(Adapter); + + if(priv->ResetProgress==RESET_TYPE_NORESET) + { +RESET_START: + + RT_TRACE(COMP_RESET,"=========>Reset progress!! \n"); + + // Set the variable for reset. + priv->ResetProgress = RESET_TYPE_SILENT; +// rtl8192_close(dev); +#if 1 + down(&priv->wx_sem); + if(priv->up == 0) + { + RT_TRACE(COMP_ERR,"%s():the driver is not up! return\n",__FUNCTION__); + up(&priv->wx_sem); + return ; + } + priv->up = 0; + RT_TRACE(COMP_RESET,"%s():======>start to down the driver\n",__FUNCTION__); +// if(!netif_queue_stopped(dev)) +// netif_stop_queue(dev); + + rtl8192_rtx_disable(dev); + rtl8192_cancel_deferred_work(priv); + deinit_hal_dm(dev); + del_timer_sync(&priv->watch_dog_timer); + + ieee->sync_scan_hurryup = 1; + if(ieee->state == IEEE80211_LINKED) + { + down(&ieee->wx_sem); + printk("ieee->state is IEEE80211_LINKED\n"); + ieee80211_stop_send_beacons(priv->ieee80211); + del_timer_sync(&ieee->associate_timer); + #if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + cancel_delayed_work(&ieee->associate_retry_wq); + #endif + ieee80211_stop_scan(ieee); + netif_carrier_off(dev); + up(&ieee->wx_sem); + } + else{ + printk("ieee->state is NOT LINKED\n"); + ieee80211_softmac_stop_protocol(priv->ieee80211); } + up(&priv->wx_sem); + RT_TRACE(COMP_RESET,"%s():<==========down process is finished\n",__FUNCTION__); + //rtl8192_irq_disable(dev); + RT_TRACE(COMP_RESET,"%s():===========>start to up the driver\n",__FUNCTION__); + reset_status = _rtl8192_up(dev); + + RT_TRACE(COMP_RESET,"%s():<===========up process is finished\n",__FUNCTION__); + if(reset_status == -EAGAIN) + { + if(reset_times < 3) + { + reset_times++; + goto RESET_START; + } + else + { + RT_TRACE(COMP_ERR," ERR!!! %s(): Reset Failed!!\n", __FUNCTION__); + } + } +#endif + ieee->is_silent_reset = 1; +#if 1 + EnableHWSecurityConfig8192(dev); +#if 1 + if(ieee->state == IEEE80211_LINKED && ieee->iw_mode == IW_MODE_INFRA) + { + ieee->set_chan(ieee->dev, ieee->current_network.channel); + +#if 1 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + queue_work(ieee->wq, &ieee->associate_complete_wq); +#else + schedule_task(&ieee->associate_complete_wq); +#endif +#endif + + } + else if(ieee->state == IEEE80211_LINKED && ieee->iw_mode == IW_MODE_ADHOC) + { + ieee->set_chan(ieee->dev, ieee->current_network.channel); + ieee->link_change(ieee->dev); + + // notify_wx_assoc_event(ieee); + + ieee80211_start_send_beacons(ieee); + + if (ieee->data_hard_resume) + ieee->data_hard_resume(ieee->dev); + netif_carrier_on(ieee->dev); + } +#endif + + CamRestoreAllEntry(dev); + + priv->ResetProgress = RESET_TYPE_NORESET; + priv->reset_count++; + + priv->bForcedSilentReset =false; + priv->bResetInProgress = false; + + // For test --> force write UFWP. + write_nic_byte(dev, UFWP, 1); + RT_TRACE(COMP_RESET, "Reset finished!! ====>[%d]\n", priv->reset_count); +#endif + } +} + +void CAM_read_entry( + struct net_device *dev, + u32 iIndex +) +{ + u32 target_command=0; + u32 target_content=0; + u8 entry_i=0; + u32 ulStatus; + s32 i=100; +// printk("=======>start read CAM\n"); + for(entry_i=0;entry_i<CAM_CONTENT_COUNT;entry_i++) + { + // polling bit, and No Write enable, and address + target_command= entry_i+CAM_CONTENT_COUNT*iIndex; + target_command= target_command | BIT31; + + //Check polling bit is clear +// mdelay(1); +#if 1 + while((i--)>=0) + { + ulStatus = read_nic_dword(dev, RWCAM); + if(ulStatus & BIT31){ + continue; + } + else{ + break; + } + } +#endif + write_nic_dword(dev, RWCAM, target_command); + RT_TRACE(COMP_SEC,"CAM_read_entry(): WRITE A0: %x \n",target_command); + // printk("CAM_read_entry(): WRITE A0: %lx \n",target_command); + target_content = read_nic_dword(dev, RCAMO); + RT_TRACE(COMP_SEC, "CAM_read_entry(): WRITE A8: %x \n",target_content); + // printk("CAM_read_entry(): WRITE A8: %lx \n",target_content); + } + printk("\n"); +} + +void rtl819x_update_rxcounts( + struct r8192_priv *priv, + u32* TotalRxBcnNum, + u32* TotalRxDataNum +) +{ + u16 SlotIndex; + u8 i; + + *TotalRxBcnNum = 0; + *TotalRxDataNum = 0; + + SlotIndex = (priv->ieee80211->LinkDetectInfo.SlotIndex++)%(priv->ieee80211->LinkDetectInfo.SlotNum); + priv->ieee80211->LinkDetectInfo.RxBcnNum[SlotIndex] = priv->ieee80211->LinkDetectInfo.NumRecvBcnInPeriod; + priv->ieee80211->LinkDetectInfo.RxDataNum[SlotIndex] = priv->ieee80211->LinkDetectInfo.NumRecvDataInPeriod; + for( i=0; i<priv->ieee80211->LinkDetectInfo.SlotNum; i++ ){ + *TotalRxBcnNum += priv->ieee80211->LinkDetectInfo.RxBcnNum[i]; + *TotalRxDataNum += priv->ieee80211->LinkDetectInfo.RxDataNum[i]; + } +} + + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) +extern void rtl819x_watchdog_wqcallback(struct work_struct *work) +{ + struct delayed_work *dwork = container_of(work,struct delayed_work,work); + struct r8192_priv *priv = container_of(dwork,struct r8192_priv,watch_dog_wq); + struct net_device *dev = priv->ieee80211->dev; +#else +extern void rtl819x_watchdog_wqcallback(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); +#endif + struct ieee80211_device* ieee = priv->ieee80211; + RESET_TYPE ResetType = RESET_TYPE_NORESET; + static u8 check_reset_cnt=0; + bool bBusyTraffic = false; + + if(!priv->up) + return; + hal_dm_watchdog(dev); + + {//to get busy traffic condition + if(ieee->state == IEEE80211_LINKED) + { + //windows mod 666 to 100. + //if( ieee->LinkDetectInfo.NumRxOkInPeriod> 666 || + // ieee->LinkDetectInfo.NumTxOkInPeriod> 666 ) { + if( ieee->LinkDetectInfo.NumRxOkInPeriod> 100 || + ieee->LinkDetectInfo.NumTxOkInPeriod> 100 ) { + bBusyTraffic = true; + } + ieee->LinkDetectInfo.NumRxOkInPeriod = 0; + ieee->LinkDetectInfo.NumTxOkInPeriod = 0; + ieee->LinkDetectInfo.bBusyTraffic = bBusyTraffic; + } + } + //added by amy for AP roaming + { + if(priv->ieee80211->state == IEEE80211_LINKED && priv->ieee80211->iw_mode == IW_MODE_INFRA) + { + u32 TotalRxBcnNum = 0; + u32 TotalRxDataNum = 0; + + rtl819x_update_rxcounts(priv, &TotalRxBcnNum, &TotalRxDataNum); + if((TotalRxBcnNum+TotalRxDataNum) == 0) + { + #ifdef TODO + if(rfState == eRfOff) + RT_TRACE(COMP_ERR,"========>%s()\n",__FUNCTION__); + #endif + printk("===>%s(): AP is power off,connect another one\n",__FUNCTION__); + // Dot11d_Reset(dev); + priv->ieee80211->state = IEEE80211_ASSOCIATING; + notify_wx_assoc_event(priv->ieee80211); + RemovePeerTS(priv->ieee80211,priv->ieee80211->current_network.bssid); + ieee->is_roaming = true; + priv->ieee80211->link_change(dev); +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + queue_work(priv->ieee80211->wq, &priv->ieee80211->associate_procedure_wq); +#else + schedule_task(&priv->ieee80211->associate_procedure_wq); +#endif + + } + } + priv->ieee80211->LinkDetectInfo.NumRecvBcnInPeriod=0; + priv->ieee80211->LinkDetectInfo.NumRecvDataInPeriod=0; + } +// CAM_read_entry(dev,4); + //check if reset the driver + if(check_reset_cnt++ >= 3 && !ieee->is_roaming) + { + ResetType = rtl819x_ifcheck_resetornot(dev); + check_reset_cnt = 3; + //DbgPrint("Start to check silent reset\n"); + } + // RT_TRACE(COMP_RESET,"%s():priv->force_reset is %d,priv->ResetProgress is %d, priv->bForcedSilentReset is %d,priv->bDisableNormalResetCheck is %d,ResetType is %d\n",__FUNCTION__,priv->force_reset,priv->ResetProgress,priv->bForcedSilentReset,priv->bDisableNormalResetCheck,ResetType); +#if 1 + if( (priv->force_reset) || (priv->ResetProgress==RESET_TYPE_NORESET && + (priv->bForcedSilentReset || + (!priv->bDisableNormalResetCheck && ResetType==RESET_TYPE_SILENT)))) // This is control by OID set in Pomelo + { + RT_TRACE(COMP_RESET,"%s():priv->force_reset is %d,priv->ResetProgress is %d, priv->bForcedSilentReset is %d,priv->bDisableNormalResetCheck is %d,ResetType is %d\n",__FUNCTION__,priv->force_reset,priv->ResetProgress,priv->bForcedSilentReset,priv->bDisableNormalResetCheck,ResetType); + rtl819x_ifsilentreset(dev); + } +#endif + priv->force_reset = false; + priv->bForcedSilentReset = false; + priv->bResetInProgress = false; + RT_TRACE(COMP_TRACE, " <==RtUsbCheckForHangWorkItemCallback()\n"); + +} + +void watch_dog_timer_callback(unsigned long data) +{ + struct r8192_priv *priv = ieee80211_priv((struct net_device *) data); + //printk("===============>watch_dog timer\n"); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + queue_delayed_work(priv->priv_wq,&priv->watch_dog_wq, 0); +#else +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) + schedule_task(&priv->watch_dog_wq); +#else + queue_work(priv->priv_wq,&priv->watch_dog_wq); +#endif +#endif + mod_timer(&priv->watch_dog_timer, jiffies + MSECS(IEEE80211_WATCH_DOG_TIME)); +#if 0 + priv->watch_dog_timer.expires = jiffies + MSECS(IEEE80211_WATCH_DOG_TIME); + add_timer(&priv->watch_dog_timer); +#endif +} +int _rtl8192_up(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + //int i; + int init_status = 0; + priv->up=1; + priv->ieee80211->ieee_up=1; + RT_TRACE(COMP_INIT, "Bringing up iface"); + init_status = priv->ops->rtl819x_adapter_start(dev); + if(!init_status) + { + RT_TRACE(COMP_ERR,"ERR!!! %s(): initialization is failed!\n", __FUNCTION__); + priv->up=priv->ieee80211->ieee_up = 0; + return -EAGAIN; + } + RT_TRACE(COMP_INIT, "start adapter finished\n"); + rtl8192_rx_enable(dev); +// rtl8192_tx_enable(dev); + if(priv->ieee80211->state != IEEE80211_LINKED) + ieee80211_softmac_start_protocol(priv->ieee80211); + ieee80211_reset_queue(priv->ieee80211); + watch_dog_timer_callback((unsigned long) dev); + if(!netif_queue_stopped(dev)) + netif_start_queue(dev); + else + netif_wake_queue(dev); + + /* + * Make sure that drop_unencrypted is initialized as "0" + * No packets will be sent in non-security mode if we had set drop_unencrypted. + * ex, After kill wpa_supplicant process, make the driver up again. + * drop_unencrypted remains as "1", which is set by wpa_supplicant. 2008/12/04.john + */ + priv->ieee80211->drop_unencrypted = 0; + + return 0; +} + + +int rtl8192_open(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + int ret; + down(&priv->wx_sem); + ret = rtl8192_up(dev); + up(&priv->wx_sem); + return ret; + +} + + +int rtl8192_up(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + + if (priv->up == 1) return -1; + + return _rtl8192_up(dev); +} + + +int rtl8192_close(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + int ret; + + down(&priv->wx_sem); + + ret = rtl8192_down(dev); + + up(&priv->wx_sem); + + return ret; + +} + +int rtl8192_down(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + int i; + + if (priv->up == 0) return -1; + + priv->up=0; + priv->ieee80211->ieee_up = 0; + RT_TRACE(COMP_DOWN, "==========>%s()\n", __FUNCTION__); +/* FIXME */ + if (!netif_queue_stopped(dev)) + netif_stop_queue(dev); + + rtl8192_rtx_disable(dev); + //rtl8192_irq_disable(dev); + + /* Tx related queue release */ + for(i = 0; i < MAX_QUEUE_SIZE; i++) { + skb_queue_purge(&priv->ieee80211->skb_waitQ [i]); + } + for(i = 0; i < MAX_QUEUE_SIZE; i++) { + skb_queue_purge(&priv->ieee80211->skb_aggQ [i]); + } + + for(i = 0; i < MAX_QUEUE_SIZE; i++) { + skb_queue_purge(&priv->ieee80211->skb_drv_aggQ [i]); + } + + //as cancel_delayed_work will del work->timer, so if work is not definedas struct delayed_work, it will corrupt +// flush_scheduled_work(); + rtl8192_cancel_deferred_work(priv); + deinit_hal_dm(dev); + del_timer_sync(&priv->watch_dog_timer); + + + ieee80211_softmac_stop_protocol(priv->ieee80211); + memset(&priv->ieee80211->current_network, 0 , offsetof(struct ieee80211_network, list)); + RT_TRACE(COMP_DOWN, "<==========%s()\n", __FUNCTION__); + + return 0; +} + + +void rtl8192_commit(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + int reset_status = 0; + //u8 reset_times = 0; + if (priv->up == 0) return ; + priv->up = 0; + + rtl8192_cancel_deferred_work(priv); + del_timer_sync(&priv->watch_dog_timer); + //cancel_delayed_work(&priv->SwChnlWorkItem); + + ieee80211_softmac_stop_protocol(priv->ieee80211); + + //rtl8192_irq_disable(dev); + rtl8192_rtx_disable(dev); + reset_status = _rtl8192_up(dev); + +} + +/* +void rtl8192_restart(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); +*/ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) +void rtl8192_restart(struct work_struct *work) +{ + struct r8192_priv *priv = container_of(work, struct r8192_priv, reset_wq); + struct net_device *dev = priv->ieee80211->dev; +#else +void rtl8192_restart(struct net_device *dev) +{ + + struct r8192_priv *priv = ieee80211_priv(dev); +#endif + + down(&priv->wx_sem); + + rtl8192_commit(dev); + + up(&priv->wx_sem); +} + +static void r8192_set_multicast(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + short promisc; + + //down(&priv->wx_sem); + + /* FIXME FIXME */ + + promisc = (dev->flags & IFF_PROMISC) ? 1:0; + + if (promisc != priv->promisc) + // rtl8192_commit(dev); + + priv->promisc = promisc; + + //schedule_work(&priv->reset_wq); + //up(&priv->wx_sem); +} + + +int r8192_set_mac_adr(struct net_device *dev, void *mac) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + struct sockaddr *addr = mac; + + down(&priv->wx_sem); + + memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) + schedule_work(&priv->reset_wq); +#else + schedule_task(&priv->reset_wq); +#endif + up(&priv->wx_sem); + + return 0; +} + +/* based on ipw2200 driver */ +int rtl8192_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) +{ + struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + struct iwreq *wrq = (struct iwreq *)rq; + int ret=-1; + struct ieee80211_device *ieee = priv->ieee80211; + u32 key[4]; + u8 broadcast_addr[6] = {0xff,0xff,0xff,0xff,0xff,0xff}; + u8 zero_addr[6] = {0}; + struct iw_point *p = &wrq->u.data; + struct ieee_param *ipw = NULL;//(struct ieee_param *)wrq->u.data.pointer; + + down(&priv->wx_sem); + + + if (p->length < sizeof(struct ieee_param) || !p->pointer){ + ret = -EINVAL; + goto out; + } + + ipw = (struct ieee_param *)kmalloc(p->length, GFP_KERNEL); + if (ipw == NULL){ + ret = -ENOMEM; + goto out; + } + if (copy_from_user(ipw, p->pointer, p->length)) { + kfree(ipw); + ret = -EFAULT; + goto out; + } + + switch (cmd) { + case RTL_IOCTL_WPA_SUPPLICANT: + //parse here for HW security + if (ipw->cmd == IEEE_CMD_SET_ENCRYPTION) + { + if (ipw->u.crypt.set_tx) + { + if (strcmp(ipw->u.crypt.alg, "CCMP") == 0) + ieee->pairwise_key_type = KEY_TYPE_CCMP; + else if (strcmp(ipw->u.crypt.alg, "TKIP") == 0) + ieee->pairwise_key_type = KEY_TYPE_TKIP; + else if (strcmp(ipw->u.crypt.alg, "WEP") == 0) + { + if (ipw->u.crypt.key_len == 13) + ieee->pairwise_key_type = KEY_TYPE_WEP104; + else if (ipw->u.crypt.key_len == 5) + ieee->pairwise_key_type = KEY_TYPE_WEP40; + } + else + ieee->pairwise_key_type = KEY_TYPE_NA; + + if (ieee->pairwise_key_type) + { + // FIXME:these two lines below just to fix ipw interface bug, that is, it will never set mode down to driver. So treat it as ADHOC mode, if no association procedure. WB. 2009.02.04 + if (memcmp(ieee->ap_mac_addr, zero_addr, 6) == 0) + ieee->iw_mode = IW_MODE_ADHOC; + memcpy((u8*)key, ipw->u.crypt.key, 16); + EnableHWSecurityConfig8192(dev); + //we fill both index entry and 4th entry for pairwise key as in IPW interface, adhoc will only get here, so we need index entry for its default key serching! + //added by WB. + setKey(dev, 4, ipw->u.crypt.idx, ieee->pairwise_key_type, (u8*)ieee->ap_mac_addr, 0, key); + if (ieee->iw_mode == IW_MODE_ADHOC) + setKey(dev, ipw->u.crypt.idx, ipw->u.crypt.idx, ieee->pairwise_key_type, (u8*)ieee->ap_mac_addr, 0, key); + } + } + else //if (ipw->u.crypt.idx) //group key use idx > 0 + { + memcpy((u8*)key, ipw->u.crypt.key, 16); + if (strcmp(ipw->u.crypt.alg, "CCMP") == 0) + ieee->group_key_type= KEY_TYPE_CCMP; + else if (strcmp(ipw->u.crypt.alg, "TKIP") == 0) + ieee->group_key_type = KEY_TYPE_TKIP; + else if (strcmp(ipw->u.crypt.alg, "WEP") == 0) + { + if (ipw->u.crypt.key_len == 13) + ieee->group_key_type = KEY_TYPE_WEP104; + else if (ipw->u.crypt.key_len == 5) + ieee->group_key_type = KEY_TYPE_WEP40; + } + else + ieee->group_key_type = KEY_TYPE_NA; + + if (ieee->group_key_type) + { + setKey( dev, + ipw->u.crypt.idx, + ipw->u.crypt.idx, //KeyIndex + ieee->group_key_type, //KeyType + broadcast_addr, //MacAddr + 0, //DefaultKey + key); //KeyContent + } + } + } +#ifdef JOHN_HWSEC_DEBUG + //john's test 0711 + printk("@@ wrq->u pointer = "); + for(i=0;i<wrq->u.data.length;i++){ + if(i%10==0) printk("\n"); + printk( "%8x|", ((u32*)wrq->u.data.pointer)[i] ); + } + printk("\n"); +#endif /*JOHN_HWSEC_DEBUG*/ + ret = ieee80211_wpa_supplicant_ioctl(priv->ieee80211, &wrq->u.data); + break; + + default: + ret = -EOPNOTSUPP; + break; + } + kfree(ipw); + ipw = NULL; +out: + up(&priv->wx_sem); + return ret; +} + +#ifdef RTL8192SU +u8 rtl8192SU_HwRateToMRate(bool bIsHT, u8 rate,bool bFirstAMPDU) +{ + + u8 ret_rate = 0x02; + + if( bFirstAMPDU ) + { + if(!bIsHT) + { + switch(rate) + { + + case DESC92S_RATE1M: ret_rate = MGN_1M; break; + case DESC92S_RATE2M: ret_rate = MGN_2M; break; + case DESC92S_RATE5_5M: ret_rate = MGN_5_5M; break; + case DESC92S_RATE11M: ret_rate = MGN_11M; break; + case DESC92S_RATE6M: ret_rate = MGN_6M; break; + case DESC92S_RATE9M: ret_rate = MGN_9M; break; + case DESC92S_RATE12M: ret_rate = MGN_12M; break; + case DESC92S_RATE18M: ret_rate = MGN_18M; break; + case DESC92S_RATE24M: ret_rate = MGN_24M; break; + case DESC92S_RATE36M: ret_rate = MGN_36M; break; + case DESC92S_RATE48M: ret_rate = MGN_48M; break; + case DESC92S_RATE54M: ret_rate = MGN_54M; break; + + default: + RT_TRACE(COMP_RECV, "HwRateToMRate90(): Non supported Rate [%x], bIsHT = %d!!!\n", rate, bIsHT); + break; + } + } + else + { + switch(rate) + { + + case DESC92S_RATEMCS0: ret_rate = MGN_MCS0; break; + case DESC92S_RATEMCS1: ret_rate = MGN_MCS1; break; + case DESC92S_RATEMCS2: ret_rate = MGN_MCS2; break; + case DESC92S_RATEMCS3: ret_rate = MGN_MCS3; break; + case DESC92S_RATEMCS4: ret_rate = MGN_MCS4; break; + case DESC92S_RATEMCS5: ret_rate = MGN_MCS5; break; + case DESC92S_RATEMCS6: ret_rate = MGN_MCS6; break; + case DESC92S_RATEMCS7: ret_rate = MGN_MCS7; break; + case DESC92S_RATEMCS8: ret_rate = MGN_MCS8; break; + case DESC92S_RATEMCS9: ret_rate = MGN_MCS9; break; + case DESC92S_RATEMCS10: ret_rate = MGN_MCS10; break; + case DESC92S_RATEMCS11: ret_rate = MGN_MCS11; break; + case DESC92S_RATEMCS12: ret_rate = MGN_MCS12; break; + case DESC92S_RATEMCS13: ret_rate = MGN_MCS13; break; + case DESC92S_RATEMCS14: ret_rate = MGN_MCS14; break; + case DESC92S_RATEMCS15: ret_rate = MGN_MCS15; break; + case DESC92S_RATEMCS32: ret_rate = (0x80|0x20); break; + + default: + RT_TRACE(COMP_RECV, "HwRateToMRate92S(): Non supported Rate [%x], bIsHT = %d!!!\n",rate, bIsHT ); + break; + } + + } + } + else + { + switch(rate) + { + + case DESC92S_RATE1M: ret_rate = MGN_1M; break; + case DESC92S_RATE2M: ret_rate = MGN_2M; break; + case DESC92S_RATE5_5M: ret_rate = MGN_5_5M; break; + case DESC92S_RATE11M: ret_rate = MGN_11M; break; + case DESC92S_RATE6M: ret_rate = MGN_6M; break; + case DESC92S_RATE9M: ret_rate = MGN_9M; break; + case DESC92S_RATE12M: ret_rate = MGN_12M; break; + case DESC92S_RATE18M: ret_rate = MGN_18M; break; + case DESC92S_RATE24M: ret_rate = MGN_24M; break; + case DESC92S_RATE36M: ret_rate = MGN_36M; break; + case DESC92S_RATE48M: ret_rate = MGN_48M; break; + case DESC92S_RATE54M: ret_rate = MGN_54M; break; + case DESC92S_RATEMCS0: ret_rate = MGN_MCS0; break; + case DESC92S_RATEMCS1: ret_rate = MGN_MCS1; break; + case DESC92S_RATEMCS2: ret_rate = MGN_MCS2; break; + case DESC92S_RATEMCS3: ret_rate = MGN_MCS3; break; + case DESC92S_RATEMCS4: ret_rate = MGN_MCS4; break; + case DESC92S_RATEMCS5: ret_rate = MGN_MCS5; break; + case DESC92S_RATEMCS6: ret_rate = MGN_MCS6; break; + case DESC92S_RATEMCS7: ret_rate = MGN_MCS7; break; + case DESC92S_RATEMCS8: ret_rate = MGN_MCS8; break; + case DESC92S_RATEMCS9: ret_rate = MGN_MCS9; break; + case DESC92S_RATEMCS10: ret_rate = MGN_MCS10; break; + case DESC92S_RATEMCS11: ret_rate = MGN_MCS11; break; + case DESC92S_RATEMCS12: ret_rate = MGN_MCS12; break; + case DESC92S_RATEMCS13: ret_rate = MGN_MCS13; break; + case DESC92S_RATEMCS14: ret_rate = MGN_MCS14; break; + case DESC92S_RATEMCS15: ret_rate = MGN_MCS15; break; + case DESC92S_RATEMCS32: ret_rate = (0x80|0x20); break; + + default: + RT_TRACE(COMP_RECV, "HwRateToMRate92S(): Non supported Rate [%x], bIsHT = %d!!!\n",rate, bIsHT ); + break; + } + } + return ret_rate; +} +#endif + +u8 HwRateToMRate90(bool bIsHT, u8 rate) +{ + u8 ret_rate = 0xff; + + if(!bIsHT) { + switch(rate) { + case DESC90_RATE1M: ret_rate = MGN_1M; break; + case DESC90_RATE2M: ret_rate = MGN_2M; break; + case DESC90_RATE5_5M: ret_rate = MGN_5_5M; break; + case DESC90_RATE11M: ret_rate = MGN_11M; break; + case DESC90_RATE6M: ret_rate = MGN_6M; break; + case DESC90_RATE9M: ret_rate = MGN_9M; break; + case DESC90_RATE12M: ret_rate = MGN_12M; break; + case DESC90_RATE18M: ret_rate = MGN_18M; break; + case DESC90_RATE24M: ret_rate = MGN_24M; break; + case DESC90_RATE36M: ret_rate = MGN_36M; break; + case DESC90_RATE48M: ret_rate = MGN_48M; break; + case DESC90_RATE54M: ret_rate = MGN_54M; break; + + default: + ret_rate = 0xff; + RT_TRACE(COMP_RECV, "HwRateToMRate90(): Non supported Rate [%x], bIsHT = %d!!!\n", rate, bIsHT); + break; + } + + } else { + switch(rate) { + case DESC90_RATEMCS0: ret_rate = MGN_MCS0; break; + case DESC90_RATEMCS1: ret_rate = MGN_MCS1; break; + case DESC90_RATEMCS2: ret_rate = MGN_MCS2; break; + case DESC90_RATEMCS3: ret_rate = MGN_MCS3; break; + case DESC90_RATEMCS4: ret_rate = MGN_MCS4; break; + case DESC90_RATEMCS5: ret_rate = MGN_MCS5; break; + case DESC90_RATEMCS6: ret_rate = MGN_MCS6; break; + case DESC90_RATEMCS7: ret_rate = MGN_MCS7; break; + case DESC90_RATEMCS8: ret_rate = MGN_MCS8; break; + case DESC90_RATEMCS9: ret_rate = MGN_MCS9; break; + case DESC90_RATEMCS10: ret_rate = MGN_MCS10; break; + case DESC90_RATEMCS11: ret_rate = MGN_MCS11; break; + case DESC90_RATEMCS12: ret_rate = MGN_MCS12; break; + case DESC90_RATEMCS13: ret_rate = MGN_MCS13; break; + case DESC90_RATEMCS14: ret_rate = MGN_MCS14; break; + case DESC90_RATEMCS15: ret_rate = MGN_MCS15; break; + case DESC90_RATEMCS32: ret_rate = (0x80|0x20); break; + + default: + ret_rate = 0xff; + RT_TRACE(COMP_RECV, "HwRateToMRate90(): Non supported Rate [%x], bIsHT = %d!!!\n",rate, bIsHT); + break; + } + } + + return ret_rate; +} + +/** + * Function: UpdateRxPktTimeStamp + * Overview: Recored down the TSF time stamp when receiving a packet + * + * Input: + * PADAPTER Adapter + * PRT_RFD pRfd, + * + * Output: + * PRT_RFD pRfd + * (pRfd->Status.TimeStampHigh is updated) + * (pRfd->Status.TimeStampLow is updated) + * Return: + * None + */ +void UpdateRxPktTimeStamp8190 (struct net_device *dev, struct ieee80211_rx_stats *stats) +{ + struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + + if(stats->bIsAMPDU && !stats->bFirstMPDU) { + stats->mac_time[0] = priv->LastRxDescTSFLow; + stats->mac_time[1] = priv->LastRxDescTSFHigh; + } else { + priv->LastRxDescTSFLow = stats->mac_time[0]; + priv->LastRxDescTSFHigh = stats->mac_time[1]; + } +} + +//by amy 080606 + +long rtl819x_translate_todbm(u8 signal_strength_index )// 0-100 index. +{ + long signal_power; // in dBm. + + // Translate to dBm (x=0.5y-95). + signal_power = (long)((signal_strength_index + 1) >> 1); + signal_power -= 95; + + return signal_power; +} + + +/* 2008/01/22 MH We can not delcare RSSI/EVM total value of sliding window to + be a local static. Otherwise, it may increase when we return from S3/S4. The + value will be kept in memory or disk. We must delcare the value in adapter + and it will be reinitialized when return from S3/S4. */ +void rtl8192_process_phyinfo(struct r8192_priv * priv,u8* buffer, struct ieee80211_rx_stats * pprevious_stats, struct ieee80211_rx_stats * pcurrent_stats) +{ + bool bcheck = false; + u8 rfpath; + u32 nspatial_stream, tmp_val; + //u8 i; + static u32 slide_rssi_index=0, slide_rssi_statistics=0; + static u32 slide_evm_index=0, slide_evm_statistics=0; + static u32 last_rssi=0, last_evm=0; + + static u32 slide_beacon_adc_pwdb_index=0, slide_beacon_adc_pwdb_statistics=0; + static u32 last_beacon_adc_pwdb=0; + + struct ieee80211_hdr_3addr *hdr; + u16 sc ; + unsigned int frag,seq; + hdr = (struct ieee80211_hdr_3addr *)buffer; + sc = le16_to_cpu(hdr->seq_ctl); + frag = WLAN_GET_SEQ_FRAG(sc); + seq = WLAN_GET_SEQ_SEQ(sc); + //cosa add 04292008 to record the sequence number + pcurrent_stats->Seq_Num = seq; + // + // Check whether we should take the previous packet into accounting + // + if(!pprevious_stats->bIsAMPDU) + { + // if previous packet is not aggregated packet + bcheck = true; + }else + { + #if 0 + // if previous packet is aggregated packet, and current packet + // (1) is not AMPDU + // (2) is the first packet of one AMPDU + // that means the previous packet is the last one aggregated packet + if( !pcurrent_stats->bIsAMPDU || pcurrent_stats->bFirstMPDU) + bcheck = true; + #endif + } + + + if(slide_rssi_statistics++ >= PHY_RSSI_SLID_WIN_MAX) + { + slide_rssi_statistics = PHY_RSSI_SLID_WIN_MAX; + last_rssi = priv->stats.slide_signal_strength[slide_rssi_index]; + priv->stats.slide_rssi_total -= last_rssi; + } + priv->stats.slide_rssi_total += pprevious_stats->SignalStrength; + + priv->stats.slide_signal_strength[slide_rssi_index++] = pprevious_stats->SignalStrength; + if(slide_rssi_index >= PHY_RSSI_SLID_WIN_MAX) + slide_rssi_index = 0; + + // <1> Showed on UI for user, in dbm + tmp_val = priv->stats.slide_rssi_total/slide_rssi_statistics; + priv->stats.signal_strength = rtl819x_translate_todbm((u8)tmp_val); + pcurrent_stats->rssi = priv->stats.signal_strength; + // + // If the previous packet does not match the criteria, neglect it + // + if(!pprevious_stats->bPacketMatchBSSID) + { + if(!pprevious_stats->bToSelfBA) + return; + } + + if(!bcheck) + return; + + + //rtl8190_process_cck_rxpathsel(priv,pprevious_stats);//only rtl8190 supported + + // + // Check RSSI + // + priv->stats.num_process_phyinfo++; + + /* record the general signal strength to the sliding window. */ + + + // <2> Showed on UI for engineering + // hardware does not provide rssi information for each rf path in CCK + if(!pprevious_stats->bIsCCK && (pprevious_stats->bPacketToSelf || pprevious_stats->bToSelfBA)) + { + for (rfpath = RF90_PATH_A; rfpath < priv->NumTotalRFPath; rfpath++) + { + if (!rtl8192_phy_CheckIsLegalRFPath(priv->ieee80211->dev, rfpath)) + continue; + + //Fixed by Jacken 2008-03-20 + if(priv->stats.rx_rssi_percentage[rfpath] == 0) + { + priv->stats.rx_rssi_percentage[rfpath] = pprevious_stats->RxMIMOSignalStrength[rfpath]; + //DbgPrint("MIMO RSSI initialize \n"); + } + if(pprevious_stats->RxMIMOSignalStrength[rfpath] > priv->stats.rx_rssi_percentage[rfpath]) + { + priv->stats.rx_rssi_percentage[rfpath] = + ( (priv->stats.rx_rssi_percentage[rfpath]*(Rx_Smooth_Factor-1)) + + (pprevious_stats->RxMIMOSignalStrength[rfpath])) /(Rx_Smooth_Factor); + priv->stats.rx_rssi_percentage[rfpath] = priv->stats.rx_rssi_percentage[rfpath] + 1; + } + else + { + priv->stats.rx_rssi_percentage[rfpath] = + ( (priv->stats.rx_rssi_percentage[rfpath]*(Rx_Smooth_Factor-1)) + + (pprevious_stats->RxMIMOSignalStrength[rfpath])) /(Rx_Smooth_Factor); + } + RT_TRACE(COMP_DBG,"priv->stats.rx_rssi_percentage[rfPath] = %d \n" ,priv->stats.rx_rssi_percentage[rfpath] ); + } + } + + + // + // Check PWDB. + // + RT_TRACE(COMP_RXDESC, "Smooth %s PWDB = %d\n", + pprevious_stats->bIsCCK? "CCK": "OFDM", + pprevious_stats->RxPWDBAll); + + if(pprevious_stats->bPacketBeacon) + { +/* record the beacon pwdb to the sliding window. */ + if(slide_beacon_adc_pwdb_statistics++ >= PHY_Beacon_RSSI_SLID_WIN_MAX) + { + slide_beacon_adc_pwdb_statistics = PHY_Beacon_RSSI_SLID_WIN_MAX; + last_beacon_adc_pwdb = priv->stats.Slide_Beacon_pwdb[slide_beacon_adc_pwdb_index]; + priv->stats.Slide_Beacon_Total -= last_beacon_adc_pwdb; + //DbgPrint("slide_beacon_adc_pwdb_index = %d, last_beacon_adc_pwdb = %d, Adapter->RxStats.Slide_Beacon_Total = %d\n", + // slide_beacon_adc_pwdb_index, last_beacon_adc_pwdb, Adapter->RxStats.Slide_Beacon_Total); + } + priv->stats.Slide_Beacon_Total += pprevious_stats->RxPWDBAll; + priv->stats.Slide_Beacon_pwdb[slide_beacon_adc_pwdb_index] = pprevious_stats->RxPWDBAll; + //DbgPrint("slide_beacon_adc_pwdb_index = %d, pPreviousRfd->Status.RxPWDBAll = %d\n", slide_beacon_adc_pwdb_index, pPreviousRfd->Status.RxPWDBAll); + slide_beacon_adc_pwdb_index++; + if(slide_beacon_adc_pwdb_index >= PHY_Beacon_RSSI_SLID_WIN_MAX) + slide_beacon_adc_pwdb_index = 0; + pprevious_stats->RxPWDBAll = priv->stats.Slide_Beacon_Total/slide_beacon_adc_pwdb_statistics; + if(pprevious_stats->RxPWDBAll >= 3) + pprevious_stats->RxPWDBAll -= 3; + } + + RT_TRACE(COMP_RXDESC, "Smooth %s PWDB = %d\n", + pprevious_stats->bIsCCK? "CCK": "OFDM", + pprevious_stats->RxPWDBAll); + + + if(pprevious_stats->bPacketToSelf || pprevious_stats->bPacketBeacon || pprevious_stats->bToSelfBA) + { + if(priv->undecorated_smoothed_pwdb < 0) // initialize + { + priv->undecorated_smoothed_pwdb = pprevious_stats->RxPWDBAll; + //DbgPrint("First pwdb initialize \n"); + } +#if 1 + if(pprevious_stats->RxPWDBAll > (u32)priv->undecorated_smoothed_pwdb) + { + priv->undecorated_smoothed_pwdb = + ( ((priv->undecorated_smoothed_pwdb)*(Rx_Smooth_Factor-1)) + + (pprevious_stats->RxPWDBAll)) /(Rx_Smooth_Factor); + priv->undecorated_smoothed_pwdb = priv->undecorated_smoothed_pwdb + 1; + } + else + { + priv->undecorated_smoothed_pwdb = + ( ((priv->undecorated_smoothed_pwdb)*(Rx_Smooth_Factor-1)) + + (pprevious_stats->RxPWDBAll)) /(Rx_Smooth_Factor); + } +#else + //Fixed by Jacken 2008-03-20 + if(pPreviousRfd->Status.RxPWDBAll > (u32)pHalData->UndecoratedSmoothedPWDB) + { + pHalData->UndecoratedSmoothedPWDB = + ( ((pHalData->UndecoratedSmoothedPWDB)* 5) + (pPreviousRfd->Status.RxPWDBAll)) / 6; + pHalData->UndecoratedSmoothedPWDB = pHalData->UndecoratedSmoothedPWDB + 1; + } + else + { + pHalData->UndecoratedSmoothedPWDB = + ( ((pHalData->UndecoratedSmoothedPWDB)* 5) + (pPreviousRfd->Status.RxPWDBAll)) / 6; + } +#endif + + } + + // + // Check EVM + // + /* record the general EVM to the sliding window. */ + if(pprevious_stats->SignalQuality == 0) + { + } + else + { + if(pprevious_stats->bPacketToSelf || pprevious_stats->bPacketBeacon || pprevious_stats->bToSelfBA){ + if(slide_evm_statistics++ >= PHY_RSSI_SLID_WIN_MAX){ + slide_evm_statistics = PHY_RSSI_SLID_WIN_MAX; + last_evm = priv->stats.slide_evm[slide_evm_index]; + priv->stats.slide_evm_total -= last_evm; + } + + priv->stats.slide_evm_total += pprevious_stats->SignalQuality; + + priv->stats.slide_evm[slide_evm_index++] = pprevious_stats->SignalQuality; + if(slide_evm_index >= PHY_RSSI_SLID_WIN_MAX) + slide_evm_index = 0; + + // <1> Showed on UI for user, in percentage. + tmp_val = priv->stats.slide_evm_total/slide_evm_statistics; + priv->stats.signal_quality = tmp_val; + //cosa add 10/11/2007, Showed on UI for user in Windows Vista, for Link quality. + priv->stats.last_signal_strength_inpercent = tmp_val; + } + + // <2> Showed on UI for engineering + if(pprevious_stats->bPacketToSelf || pprevious_stats->bPacketBeacon || pprevious_stats->bToSelfBA) + { + for(nspatial_stream = 0; nspatial_stream<2 ; nspatial_stream++) // 2 spatial stream + { + if(pprevious_stats->RxMIMOSignalQuality[nspatial_stream] != -1) + { + if(priv->stats.rx_evm_percentage[nspatial_stream] == 0) // initialize + { + priv->stats.rx_evm_percentage[nspatial_stream] = pprevious_stats->RxMIMOSignalQuality[nspatial_stream]; + } + priv->stats.rx_evm_percentage[nspatial_stream] = + ( (priv->stats.rx_evm_percentage[nspatial_stream]* (Rx_Smooth_Factor-1)) + + (pprevious_stats->RxMIMOSignalQuality[nspatial_stream]* 1)) / (Rx_Smooth_Factor); + } + } + } + } + + +} + +/*----------------------------------------------------------------------------- + * Function: rtl819x_query_rxpwrpercentage() + * + * Overview: + * + * Input: char antpower + * + * Output: NONE + * + * Return: 0-100 percentage + * + * Revised History: + * When Who Remark + * 05/26/2008 amy Create Version 0 porting from windows code. + * + *---------------------------------------------------------------------------*/ +static u8 rtl819x_query_rxpwrpercentage( + char antpower + ) +{ + if ((antpower <= -100) || (antpower >= 20)) + { + return 0; + } + else if (antpower >= 0) + { + return 100; + } + else + { + return (100+antpower); + } + +} /* QueryRxPwrPercentage */ + +static u8 +rtl819x_evm_dbtopercentage( + char value + ) +{ + char ret_val; + + ret_val = value; + + if(ret_val >= 0) + ret_val = 0; + if(ret_val <= -33) + ret_val = -33; + ret_val = 0 - ret_val; + ret_val*=3; + if(ret_val == 99) + ret_val = 100; + return(ret_val); +} +// +// Description: +// We want good-looking for signal strength/quality +// 2007/7/19 01:09, by cosa. +// +long +rtl819x_signal_scale_mapping( + long currsig + ) +{ + long retsig; + + // Step 1. Scale mapping. + if(currsig >= 61 && currsig <= 100) + { + retsig = 90 + ((currsig - 60) / 4); + } + else if(currsig >= 41 && currsig <= 60) + { + retsig = 78 + ((currsig - 40) / 2); + } + else if(currsig >= 31 && currsig <= 40) + { + retsig = 66 + (currsig - 30); + } + else if(currsig >= 21 && currsig <= 30) + { + retsig = 54 + (currsig - 20); + } + else if(currsig >= 5 && currsig <= 20) + { + retsig = 42 + (((currsig - 5) * 2) / 3); + } + else if(currsig == 4) + { + retsig = 36; + } + else if(currsig == 3) + { + retsig = 27; + } + else if(currsig == 2) + { + retsig = 18; + } + else if(currsig == 1) + { + retsig = 9; + } + else + { + retsig = currsig; + } + + return retsig; +} + +#ifdef RTL8192SU +/*----------------------------------------------------------------------------- + * Function: QueryRxPhyStatus8192S() + * + * Overview: + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 06/01/2007 MHC Create Version 0. + * 06/05/2007 MHC Accordign to HW's new data sheet, we add CCK and OFDM + * descriptor definition. + * 07/04/2007 MHC According to Jerry and Bryant's document. We read + * ir_isolation and ext_lna for RF's init value and use + * to compensate RSSI after receiving packets. + * 09/10/2008 MHC Modify name and PHY status field for 92SE. + * 09/19/2008 MHC Add CCK/OFDM SS/SQ for 92S series. + * + *---------------------------------------------------------------------------*/ +static void rtl8192SU_query_rxphystatus( + struct r8192_priv * priv, + struct ieee80211_rx_stats * pstats, + rx_desc_819x_usb *pDesc, + rx_drvinfo_819x_usb * pdrvinfo, + struct ieee80211_rx_stats * precord_stats, + bool bpacket_match_bssid, + bool bpacket_toself, + bool bPacketBeacon, + bool bToSelfBA + ) +{ + //PRT_RFD_STATUS pRtRfdStatus = &(pRfd->Status); + //PHY_STS_CCK_8192S_T *pCck_buf; + phy_sts_cck_819xusb_t * pcck_buf; + phy_ofdm_rx_status_rxsc_sgien_exintfflag* prxsc; + //u8 *prxpkt; + //u8 i, max_spatial_stream, tmp_rxsnr, tmp_rxevm, rxsc_sgien_exflg; + u8 i, max_spatial_stream, rxsc_sgien_exflg; + char rx_pwr[4], rx_pwr_all=0; + //long rx_avg_pwr = 0; + //char rx_snrX, rx_evmX; + u8 evm, pwdb_all; + u32 RSSI, total_rssi=0;//, total_evm=0; +// long signal_strength_index = 0; + u8 is_cck_rate=0; + u8 rf_rx_num = 0; + + + + priv->stats.numqry_phystatus++; + + is_cck_rate = rx_hal_is_cck_rate(pDesc); + + // Record it for next packet processing + memset(precord_stats, 0, sizeof(struct ieee80211_rx_stats)); + pstats->bPacketMatchBSSID = precord_stats->bPacketMatchBSSID = bpacket_match_bssid; + pstats->bPacketToSelf = precord_stats->bPacketToSelf = bpacket_toself; + pstats->bIsCCK = precord_stats->bIsCCK = is_cck_rate;//RX_HAL_IS_CCK_RATE(pDrvInfo); + pstats->bPacketBeacon = precord_stats->bPacketBeacon = bPacketBeacon; + pstats->bToSelfBA = precord_stats->bToSelfBA = bToSelfBA; + +#ifndef RTL8192SU + phy_sts_ofdm_819xusb_t* pofdm_buf = NULL; + prxpkt = (u8*)pdrvinfo; + + /* Move pointer to the 16th bytes. Phy status start address. */ + prxpkt += sizeof(rx_drvinfo_819x_usb); + + /* Initial the cck and ofdm buffer pointer */ + pcck_buf = (phy_sts_cck_819xusb_t *)prxpkt; + pofdm_buf = (phy_sts_ofdm_819xusb_t *)prxpkt; +#endif + + pstats->RxMIMOSignalQuality[0] = -1; + pstats->RxMIMOSignalQuality[1] = -1; + precord_stats->RxMIMOSignalQuality[0] = -1; + precord_stats->RxMIMOSignalQuality[1] = -1; + + if(is_cck_rate) + { + u8 report;//, tmp_pwdb; + //char cck_adc_pwdb[4]; + + // CCK Driver info Structure is not the same as OFDM packet. + pcck_buf = (phy_sts_cck_819xusb_t *)pdrvinfo; + + // + // (1)Hardware does not provide RSSI for CCK + // + + // + // (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive) + // + + priv->stats.numqry_phystatusCCK++; + + if(!priv->bCckHighPower) + { + report = pcck_buf->cck_agc_rpt & 0xc0; + report = report>>6; + switch(report) + { + //Fixed by Jacken from Bryant 2008-03-20 + //Original value is -38 , -26 , -14 , -2 + //Fixed value is -35 , -23 , -11 , 6 + case 0x3: + rx_pwr_all = -35 - (pcck_buf->cck_agc_rpt & 0x3e); + break; + case 0x2: + rx_pwr_all = -23 - (pcck_buf->cck_agc_rpt & 0x3e); + break; + case 0x1: + rx_pwr_all = -11 - (pcck_buf->cck_agc_rpt & 0x3e); + break; + case 0x0: + rx_pwr_all = 8 - (pcck_buf->cck_agc_rpt & 0x3e);//6->8 + break; + } + } + else + { + report = pdrvinfo->cfosho[0] & 0x60; + report = report>>5; + switch(report) + { + case 0x3: + rx_pwr_all = -35 - ((pcck_buf->cck_agc_rpt & 0x1f)<<1) ; + break; + case 0x2: + rx_pwr_all = -23 - ((pcck_buf->cck_agc_rpt & 0x1f)<<1); + break; + case 0x1: + rx_pwr_all = -11 - ((pcck_buf->cck_agc_rpt & 0x1f)<<1) ; + break; + case 0x0: + rx_pwr_all = -8 - ((pcck_buf->cck_agc_rpt & 0x1f)<<1) ;//6->-8 + break; + } + } + + pwdb_all = rtl819x_query_rxpwrpercentage(rx_pwr_all);//check it + pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all; + //pstats->RecvSignalPower = pwdb_all; + pstats->RecvSignalPower = rx_pwr_all; + + // + // (3) Get Signal Quality (EVM) + // + //if(bpacket_match_bssid) + { + u8 sq; + + if(pstats->RxPWDBAll > 40) + { + sq = 100; + }else + { + sq = pcck_buf->sq_rpt; + + if(pcck_buf->sq_rpt > 64) + sq = 0; + else if (pcck_buf->sq_rpt < 20) + sq = 100; + else + sq = ((64-sq) * 100) / 44; + } + pstats->SignalQuality = precord_stats->SignalQuality = sq; + pstats->RxMIMOSignalQuality[0] = precord_stats->RxMIMOSignalQuality[0] = sq; + pstats->RxMIMOSignalQuality[1] = precord_stats->RxMIMOSignalQuality[1] = -1; + } + } + else + { + priv->stats.numqry_phystatusHT++; + + // 2008/09/19 MH For 92S debug, RX RF path always enable!! + priv->brfpath_rxenable[0] = priv->brfpath_rxenable[1] = TRUE; + + // + // (1)Get RSSI for HT rate + // + //for(i=RF90_PATH_A; i<priv->NumTotalRFPath; i++) + for(i=RF90_PATH_A; i<RF90_PATH_MAX; i++) + { + // 2008/01/30 MH we will judge RF RX path now. + if (priv->brfpath_rxenable[i]) + rf_rx_num++; + //else + // continue; + + //if (!rtl8192_phy_CheckIsLegalRFPath(priv->ieee80211->dev, i)) + // continue; + + //Fixed by Jacken from Bryant 2008-03-20 + //Original value is 106 + //rx_pwr[i] = ((pofdm_buf->trsw_gain_X[i]&0x3F)*2) - 106; + rx_pwr[i] = ((pdrvinfo->gain_trsw[i]&0x3F)*2) - 110; + + /* Translate DBM to percentage. */ + RSSI = rtl819x_query_rxpwrpercentage(rx_pwr[i]); //check ok + total_rssi += RSSI; + RT_TRACE(COMP_RF, "RF-%d RXPWR=%x RSSI=%d\n", i, rx_pwr[i], RSSI); + + //Get Rx snr value in DB + //tmp_rxsnr = pofdm_buf->rxsnr_X[i]; + //rx_snrX = (char)(tmp_rxsnr); + //rx_snrX /= 2; + //priv->stats.rxSNRdB[i] = (long)rx_snrX; + priv->stats.rxSNRdB[i] = (long)(pdrvinfo->rxsnr[i]/2); + + /* Translate DBM to percentage. */ + //RSSI = rtl819x_query_rxpwrpercentage(rx_pwr[i]); + //total_rssi += RSSI; + + /* Record Signal Strength for next packet */ + //if(bpacket_match_bssid) + { + pstats->RxMIMOSignalStrength[i] =(u8) RSSI; + precord_stats->RxMIMOSignalStrength[i] =(u8) RSSI; + } + } + + + // + // (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive) + // + //Fixed by Jacken from Bryant 2008-03-20 + //Original value is 106 + //rx_pwr_all = (((pofdm_buf->pwdb_all ) >> 1 )& 0x7f) -106; + rx_pwr_all = (((pdrvinfo->pwdb_all ) >> 1 )& 0x7f) -106; + pwdb_all = rtl819x_query_rxpwrpercentage(rx_pwr_all); + + pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all; + pstats->RxPower = precord_stats->RxPower = rx_pwr_all; + pstats->RecvSignalPower = rx_pwr_all; + + // + // (3)EVM of HT rate + // + //if(pdrvinfo->RxHT && pdrvinfo->RxRate>=DESC90_RATEMCS8 && + // pdrvinfo->RxRate<=DESC90_RATEMCS15) + if(pDesc->RxHT && pDesc->RxMCS>=DESC92S_RATEMCS8 && + pDesc->RxMCS<=DESC92S_RATEMCS15) + max_spatial_stream = 2; //both spatial stream make sense + else + max_spatial_stream = 1; //only spatial stream 1 makes sense + + for(i=0; i<max_spatial_stream; i++) + { + //tmp_rxevm = pofdm_buf->rxevm_X[i]; + //rx_evmX = (char)(tmp_rxevm); + + // Do not use shift operation like "rx_evmX >>= 1" because the compilor of free build environment + // fill most significant bit to "zero" when doing shifting operation which may change a negative + // value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore. + //rx_evmX /= 2; //dbm + + //evm = rtl819x_evm_dbtopercentage(rx_evmX); + evm = rtl819x_evm_dbtopercentage( (pdrvinfo->rxevm[i] /*/ 2*/)); //dbm + RT_TRACE(COMP_RF, "RXRATE=%x RXEVM=%x EVM=%s%d\n", pDesc->RxMCS, pdrvinfo->rxevm[i], "%", evm); +#if 0 + EVM = SignalScaleMapping(EVM);//make it good looking, from 0~100//=====>from here +#endif + + //if(bpacket_match_bssid) + { + if(i==0) // Fill value in RFD, Get the first spatial stream only + pstats->SignalQuality = precord_stats->SignalQuality = (u8)(evm & 0xff); + pstats->RxMIMOSignalQuality[i] = precord_stats->RxMIMOSignalQuality[i] = (u8)(evm & 0xff); + } + } + + + /* record rx statistics for debug */ + //rxsc_sgien_exflg = pofdm_buf->rxsc_sgien_exflg; + prxsc = (phy_ofdm_rx_status_rxsc_sgien_exintfflag *)&rxsc_sgien_exflg; + //if(pdrvinfo->BW) //40M channel + if(pDesc->BW) //40M channel + priv->stats.received_bwtype[1+pdrvinfo->rxsc]++; + else //20M channel + priv->stats.received_bwtype[0]++; + } + + //UI BSS List signal strength(in percentage), make it good looking, from 0~100. + //It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp(). + if(is_cck_rate) + { + pstats->SignalStrength = precord_stats->SignalStrength = (u8)(rtl819x_signal_scale_mapping((long)pwdb_all));//PWDB_ALL;//check ok + + } + else + { + //pRfd->Status.SignalStrength = pRecordRfd->Status.SignalStrength = (u8)(SignalScaleMapping(total_rssi/=RF90_PATH_MAX));//(u8)(total_rssi/=RF90_PATH_MAX); + // We can judge RX path number now. + if (rf_rx_num != 0) + pstats->SignalStrength = precord_stats->SignalStrength = (u8)(rtl819x_signal_scale_mapping((long)(total_rssi/=rf_rx_num))); + } +}/* QueryRxPhyStatus8192S */ +#else +static void rtl8192_query_rxphystatus( + struct r8192_priv * priv, + struct ieee80211_rx_stats * pstats, + rx_drvinfo_819x_usb * pdrvinfo, + struct ieee80211_rx_stats * precord_stats, + bool bpacket_match_bssid, + bool bpacket_toself, + bool bPacketBeacon, + bool bToSelfBA + ) +{ + //PRT_RFD_STATUS pRtRfdStatus = &(pRfd->Status); + phy_sts_ofdm_819xusb_t* pofdm_buf; + phy_sts_cck_819xusb_t * pcck_buf; + phy_ofdm_rx_status_rxsc_sgien_exintfflag* prxsc; + u8 *prxpkt; + u8 i, max_spatial_stream, tmp_rxsnr, tmp_rxevm, rxsc_sgien_exflg; + char rx_pwr[4], rx_pwr_all=0; + //long rx_avg_pwr = 0; + char rx_snrX, rx_evmX; + u8 evm, pwdb_all; + u32 RSSI, total_rssi=0;//, total_evm=0; +// long signal_strength_index = 0; + u8 is_cck_rate=0; + u8 rf_rx_num = 0; + + + priv->stats.numqry_phystatus++; + + is_cck_rate = rx_hal_is_cck_rate(pdrvinfo); + + // Record it for next packet processing + memset(precord_stats, 0, sizeof(struct ieee80211_rx_stats)); + pstats->bPacketMatchBSSID = precord_stats->bPacketMatchBSSID = bpacket_match_bssid; + pstats->bPacketToSelf = precord_stats->bPacketToSelf = bpacket_toself; + pstats->bIsCCK = precord_stats->bIsCCK = is_cck_rate;//RX_HAL_IS_CCK_RATE(pDrvInfo); + pstats->bPacketBeacon = precord_stats->bPacketBeacon = bPacketBeacon; + pstats->bToSelfBA = precord_stats->bToSelfBA = bToSelfBA; + + prxpkt = (u8*)pdrvinfo; + + /* Move pointer to the 16th bytes. Phy status start address. */ + prxpkt += sizeof(rx_drvinfo_819x_usb); + + /* Initial the cck and ofdm buffer pointer */ + pcck_buf = (phy_sts_cck_819xusb_t *)prxpkt; + pofdm_buf = (phy_sts_ofdm_819xusb_t *)prxpkt; + + pstats->RxMIMOSignalQuality[0] = -1; + pstats->RxMIMOSignalQuality[1] = -1; + precord_stats->RxMIMOSignalQuality[0] = -1; + precord_stats->RxMIMOSignalQuality[1] = -1; + + if(is_cck_rate) + { + // + // (1)Hardware does not provide RSSI for CCK + // + + // + // (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive) + // + u8 report;//, cck_agc_rpt; + + priv->stats.numqry_phystatusCCK++; + + if(!priv->bCckHighPower) + { + report = pcck_buf->cck_agc_rpt & 0xc0; + report = report>>6; + switch(report) + { + //Fixed by Jacken from Bryant 2008-03-20 + //Original value is -38 , -26 , -14 , -2 + //Fixed value is -35 , -23 , -11 , 6 + case 0x3: + rx_pwr_all = -35 - (pcck_buf->cck_agc_rpt & 0x3e); + break; + case 0x2: + rx_pwr_all = -23 - (pcck_buf->cck_agc_rpt & 0x3e); + break; + case 0x1: + rx_pwr_all = -11 - (pcck_buf->cck_agc_rpt & 0x3e); + break; + case 0x0: + rx_pwr_all = 6 - (pcck_buf->cck_agc_rpt & 0x3e); + break; + } + } + else + { + report = pcck_buf->cck_agc_rpt & 0x60; + report = report>>5; + switch(report) + { + case 0x3: + rx_pwr_all = -35 - ((pcck_buf->cck_agc_rpt & 0x1f)<<1) ; + break; + case 0x2: + rx_pwr_all = -23 - ((pcck_buf->cck_agc_rpt & 0x1f)<<1); + break; + case 0x1: + rx_pwr_all = -11 - ((pcck_buf->cck_agc_rpt & 0x1f)<<1) ; + break; + case 0x0: + rx_pwr_all = 6 - ((pcck_buf->cck_agc_rpt & 0x1f)<<1) ; + break; + } + } + + pwdb_all = rtl819x_query_rxpwrpercentage(rx_pwr_all); + pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all; + pstats->RecvSignalPower = pwdb_all; + + // + // (3) Get Signal Quality (EVM) + // + //if(bpacket_match_bssid) + { + u8 sq; + + if(pstats->RxPWDBAll > 40) + { + sq = 100; + }else + { + sq = pcck_buf->sq_rpt; + + if(pcck_buf->sq_rpt > 64) + sq = 0; + else if (pcck_buf->sq_rpt < 20) + sq = 100; + else + sq = ((64-sq) * 100) / 44; + } + pstats->SignalQuality = precord_stats->SignalQuality = sq; + pstats->RxMIMOSignalQuality[0] = precord_stats->RxMIMOSignalQuality[0] = sq; + pstats->RxMIMOSignalQuality[1] = precord_stats->RxMIMOSignalQuality[1] = -1; + } + } + else + { + priv->stats.numqry_phystatusHT++; + // + // (1)Get RSSI for HT rate + // + for(i=RF90_PATH_A; i<priv->NumTotalRFPath; i++) + { + // 2008/01/30 MH we will judge RF RX path now. + if (priv->brfpath_rxenable[i]) + rf_rx_num++; + else + continue; + + if (!rtl8192_phy_CheckIsLegalRFPath(priv->ieee80211->dev, i)) + continue; + + //Fixed by Jacken from Bryant 2008-03-20 + //Original value is 106 + rx_pwr[i] = ((pofdm_buf->trsw_gain_X[i]&0x3F)*2) - 106; + + //Get Rx snr value in DB + tmp_rxsnr = pofdm_buf->rxsnr_X[i]; + rx_snrX = (char)(tmp_rxsnr); + //rx_snrX >>= 1;; + rx_snrX /= 2; + priv->stats.rxSNRdB[i] = (long)rx_snrX; + + /* Translate DBM to percentage. */ + RSSI = rtl819x_query_rxpwrpercentage(rx_pwr[i]); + total_rssi += RSSI; + + /* Record Signal Strength for next packet */ + //if(bpacket_match_bssid) + { + pstats->RxMIMOSignalStrength[i] =(u8) RSSI; + precord_stats->RxMIMOSignalStrength[i] =(u8) RSSI; + } + } + + + // + // (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive) + // + //Fixed by Jacken from Bryant 2008-03-20 + //Original value is 106 + rx_pwr_all = (((pofdm_buf->pwdb_all ) >> 1 )& 0x7f) -106; + pwdb_all = rtl819x_query_rxpwrpercentage(rx_pwr_all); + + pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all; + pstats->RxPower = precord_stats->RxPower = rx_pwr_all; + + // + // (3)EVM of HT rate + // + if(pdrvinfo->RxHT && pdrvinfo->RxRate>=DESC90_RATEMCS8 && + pdrvinfo->RxRate<=DESC90_RATEMCS15) + max_spatial_stream = 2; //both spatial stream make sense + else + max_spatial_stream = 1; //only spatial stream 1 makes sense + + for(i=0; i<max_spatial_stream; i++) + { + tmp_rxevm = pofdm_buf->rxevm_X[i]; + rx_evmX = (char)(tmp_rxevm); + + // Do not use shift operation like "rx_evmX >>= 1" because the compilor of free build environment + // fill most significant bit to "zero" when doing shifting operation which may change a negative + // value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore. + rx_evmX /= 2; //dbm + + evm = rtl819x_evm_dbtopercentage(rx_evmX); +#if 0 + EVM = SignalScaleMapping(EVM);//make it good looking, from 0~100 +#endif + //if(bpacket_match_bssid) + { + if(i==0) // Fill value in RFD, Get the first spatial stream only + pstats->SignalQuality = precord_stats->SignalQuality = (u8)(evm & 0xff); + pstats->RxMIMOSignalQuality[i] = precord_stats->RxMIMOSignalQuality[i] = (u8)(evm & 0xff); + } + } + + + /* record rx statistics for debug */ + rxsc_sgien_exflg = pofdm_buf->rxsc_sgien_exflg; + prxsc = (phy_ofdm_rx_status_rxsc_sgien_exintfflag *)&rxsc_sgien_exflg; + if(pdrvinfo->BW) //40M channel + priv->stats.received_bwtype[1+prxsc->rxsc]++; + else //20M channel + priv->stats.received_bwtype[0]++; + } + + //UI BSS List signal strength(in percentage), make it good looking, from 0~100. + //It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp(). + if(is_cck_rate) + { + pstats->SignalStrength = precord_stats->SignalStrength = (u8)(rtl819x_signal_scale_mapping((long)pwdb_all));//PWDB_ALL; + + } + else + { + //pRfd->Status.SignalStrength = pRecordRfd->Status.SignalStrength = (u8)(SignalScaleMapping(total_rssi/=RF90_PATH_MAX));//(u8)(total_rssi/=RF90_PATH_MAX); + // We can judge RX path number now. + if (rf_rx_num != 0) + pstats->SignalStrength = precord_stats->SignalStrength = (u8)(rtl819x_signal_scale_mapping((long)(total_rssi/=rf_rx_num))); + } +} /* QueryRxPhyStatus8190Pci */ +#endif + +void +rtl8192_record_rxdesc_forlateruse( + struct ieee80211_rx_stats * psrc_stats, + struct ieee80211_rx_stats * ptarget_stats +) +{ + ptarget_stats->bIsAMPDU = psrc_stats->bIsAMPDU; + ptarget_stats->bFirstMPDU = psrc_stats->bFirstMPDU; + ptarget_stats->Seq_Num = psrc_stats->Seq_Num; +} + +#ifdef RTL8192SU +static void rtl8192SU_query_rxphystatus( + struct r8192_priv * priv, + struct ieee80211_rx_stats * pstats, + rx_desc_819x_usb *pDesc, + rx_drvinfo_819x_usb * pdrvinfo, + struct ieee80211_rx_stats * precord_stats, + bool bpacket_match_bssid, + bool bpacket_toself, + bool bPacketBeacon, + bool bToSelfBA + ); +void rtl8192SU_TranslateRxSignalStuff(struct sk_buff *skb, + struct ieee80211_rx_stats * pstats, + rx_desc_819x_usb *pDesc, + rx_drvinfo_819x_usb *pdrvinfo) +{ + // TODO: We must only check packet for current MAC address. Not finish + rtl8192_rx_info *info = (struct rtl8192_rx_info *)skb->cb; + struct net_device *dev=info->dev; + struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + bool bpacket_match_bssid, bpacket_toself; + bool bPacketBeacon=FALSE, bToSelfBA=FALSE; + static struct ieee80211_rx_stats previous_stats; + struct ieee80211_hdr_3addr *hdr;//by amy + u16 fc,type; + + // Get Signal Quality for only RX data queue (but not command queue) + + u8* tmp_buf; + //u16 tmp_buf_len = 0; + u8 *praddr; + + /* Get MAC frame start address. */ + tmp_buf = (u8*)skb->data;// + get_rxpacket_shiftbytes_819xusb(pstats); + + hdr = (struct ieee80211_hdr_3addr *)tmp_buf; + fc = le16_to_cpu(hdr->frame_ctl); + type = WLAN_FC_GET_TYPE(fc); + praddr = hdr->addr1; + + /* Check if the received packet is acceptabe. */ + bpacket_match_bssid = ((IEEE80211_FTYPE_CTL != type) && + (eqMacAddr(priv->ieee80211->current_network.bssid, (fc & IEEE80211_FCTL_TODS)? hdr->addr1 : (fc & IEEE80211_FCTL_FROMDS )? hdr->addr2 : hdr->addr3)) + && (!pstats->bHwError) && (!pstats->bCRC)&& (!pstats->bICV)); + bpacket_toself = bpacket_match_bssid & (eqMacAddr(praddr, priv->ieee80211->dev->dev_addr)); + +#if 1//cosa + if(WLAN_FC_GET_FRAMETYPE(fc)== IEEE80211_STYPE_BEACON) + { + bPacketBeacon = true; + //DbgPrint("Beacon 2, MatchBSSID = %d, ToSelf = %d \n", bPacketMatchBSSID, bPacketToSelf); + } + if(WLAN_FC_GET_FRAMETYPE(fc) == IEEE80211_STYPE_BLOCKACK) + { + if((eqMacAddr(praddr,dev->dev_addr))) + bToSelfBA = true; + //DbgPrint("BlockAck, MatchBSSID = %d, ToSelf = %d \n", bPacketMatchBSSID, bPacketToSelf); + } + +#endif + + + if(bpacket_match_bssid) + { + priv->stats.numpacket_matchbssid++; + } + if(bpacket_toself){ + priv->stats.numpacket_toself++; + } + // + // Process PHY information for previous packet (RSSI/PWDB/EVM) + // + // Because phy information is contained in the last packet of AMPDU only, so driver + // should process phy information of previous packet + rtl8192_process_phyinfo(priv, tmp_buf, &previous_stats, pstats); + rtl8192SU_query_rxphystatus(priv, pstats, pDesc, pdrvinfo, &previous_stats, bpacket_match_bssid,bpacket_toself,bPacketBeacon,bToSelfBA); + rtl8192_record_rxdesc_forlateruse(pstats, &previous_stats); + +} +#else +void TranslateRxSignalStuff819xUsb(struct sk_buff *skb, + struct ieee80211_rx_stats * pstats, + rx_drvinfo_819x_usb *pdrvinfo) +{ + // TODO: We must only check packet for current MAC address. Not finish + rtl8192_rx_info *info = (struct rtl8192_rx_info *)skb->cb; + struct net_device *dev=info->dev; + struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + bool bpacket_match_bssid, bpacket_toself; + bool bPacketBeacon=FALSE, bToSelfBA=FALSE; + static struct ieee80211_rx_stats previous_stats; + struct ieee80211_hdr_3addr *hdr;//by amy + u16 fc,type; + + // Get Signal Quality for only RX data queue (but not command queue) + + u8* tmp_buf; + //u16 tmp_buf_len = 0; + u8 *praddr; + + /* Get MAC frame start address. */ + tmp_buf = (u8*)skb->data;// + get_rxpacket_shiftbytes_819xusb(pstats); + + hdr = (struct ieee80211_hdr_3addr *)tmp_buf; + fc = le16_to_cpu(hdr->frame_ctl); + type = WLAN_FC_GET_TYPE(fc); + praddr = hdr->addr1; + + /* Check if the received packet is acceptabe. */ + bpacket_match_bssid = ((IEEE80211_FTYPE_CTL != type) && + (eqMacAddr(priv->ieee80211->current_network.bssid, (fc & IEEE80211_FCTL_TODS)? hdr->addr1 : (fc & IEEE80211_FCTL_FROMDS )? hdr->addr2 : hdr->addr3)) + && (!pstats->bHwError) && (!pstats->bCRC)&& (!pstats->bICV)); + bpacket_toself = bpacket_match_bssid & (eqMacAddr(praddr, priv->ieee80211->dev->dev_addr)); + +#if 1//cosa + if(WLAN_FC_GET_FRAMETYPE(fc)== IEEE80211_STYPE_BEACON) + { + bPacketBeacon = true; + //DbgPrint("Beacon 2, MatchBSSID = %d, ToSelf = %d \n", bPacketMatchBSSID, bPacketToSelf); + } + if(WLAN_FC_GET_FRAMETYPE(fc) == IEEE80211_STYPE_BLOCKACK) + { + if((eqMacAddr(praddr,dev->dev_addr))) + bToSelfBA = true; + //DbgPrint("BlockAck, MatchBSSID = %d, ToSelf = %d \n", bPacketMatchBSSID, bPacketToSelf); + } + +#endif + + + if(bpacket_match_bssid) + { + priv->stats.numpacket_matchbssid++; + } + if(bpacket_toself){ + priv->stats.numpacket_toself++; + } + // + // Process PHY information for previous packet (RSSI/PWDB/EVM) + // + // Because phy information is contained in the last packet of AMPDU only, so driver + // should process phy information of previous packet + rtl8192_process_phyinfo(priv, tmp_buf, &previous_stats, pstats); + rtl8192_query_rxphystatus(priv, pstats, pdrvinfo, &previous_stats, bpacket_match_bssid,bpacket_toself,bPacketBeacon,bToSelfBA); + rtl8192_record_rxdesc_forlateruse(pstats, &previous_stats); + +} +#endif + +/** +* Function: UpdateReceivedRateHistogramStatistics +* Overview: Recored down the received data rate +* +* Input: +* struct net_device *dev +* struct ieee80211_rx_stats *stats +* +* Output: +* +* (priv->stats.ReceivedRateHistogram[] is updated) +* Return: +* None +*/ +void +UpdateReceivedRateHistogramStatistics8190( + struct net_device *dev, + struct ieee80211_rx_stats *stats + ) +{ + struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + u32 rcvType=1; //0: Total, 1:OK, 2:CRC, 3:ICV + u32 rateIndex; + u32 preamble_guardinterval; //1: short preamble/GI, 0: long preamble/GI + + + if(stats->bCRC) + rcvType = 2; + else if(stats->bICV) + rcvType = 3; + + if(stats->bShortPreamble) + preamble_guardinterval = 1;// short + else + preamble_guardinterval = 0;// long + + switch(stats->rate) + { + // + // CCK rate + // + case MGN_1M: rateIndex = 0; break; + case MGN_2M: rateIndex = 1; break; + case MGN_5_5M: rateIndex = 2; break; + case MGN_11M: rateIndex = 3; break; + // + // Legacy OFDM rate + // + case MGN_6M: rateIndex = 4; break; + case MGN_9M: rateIndex = 5; break; + case MGN_12M: rateIndex = 6; break; + case MGN_18M: rateIndex = 7; break; + case MGN_24M: rateIndex = 8; break; + case MGN_36M: rateIndex = 9; break; + case MGN_48M: rateIndex = 10; break; + case MGN_54M: rateIndex = 11; break; + // + // 11n High throughput rate + // + case MGN_MCS0: rateIndex = 12; break; + case MGN_MCS1: rateIndex = 13; break; + case MGN_MCS2: rateIndex = 14; break; + case MGN_MCS3: rateIndex = 15; break; + case MGN_MCS4: rateIndex = 16; break; + case MGN_MCS5: rateIndex = 17; break; + case MGN_MCS6: rateIndex = 18; break; + case MGN_MCS7: rateIndex = 19; break; + case MGN_MCS8: rateIndex = 20; break; + case MGN_MCS9: rateIndex = 21; break; + case MGN_MCS10: rateIndex = 22; break; + case MGN_MCS11: rateIndex = 23; break; + case MGN_MCS12: rateIndex = 24; break; + case MGN_MCS13: rateIndex = 25; break; + case MGN_MCS14: rateIndex = 26; break; + case MGN_MCS15: rateIndex = 27; break; + default: rateIndex = 28; break; + } + priv->stats.received_preamble_GI[preamble_guardinterval][rateIndex]++; + priv->stats.received_rate_histogram[0][rateIndex]++; //total + priv->stats.received_rate_histogram[rcvType][rateIndex]++; +} + +#ifdef RTL8192SU +void rtl8192SU_query_rxdesc_status(struct sk_buff *skb, struct ieee80211_rx_stats *stats, bool bIsRxAggrSubframe) +{ + rtl8192_rx_info *info = (struct rtl8192_rx_info *)skb->cb; + struct net_device *dev=info->dev; + struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + //rx_desc_819x_usb *desc = (rx_desc_819x_usb *)skb->data; + rx_drvinfo_819x_usb *driver_info = NULL; + + //PRT_RFD_STATUS pRtRfdStatus = &pRfd->Status; + //PHAL_DATA_8192SUSB pHalData = GET_HAL_DATA(Adapter); + //pu1Byte pDesc = (pu1Byte)pDescIn; + //PRX_DRIVER_INFO_8192S pDrvInfo; + +#ifdef USB_RX_AGGREGATION_SUPPORT//FIXLZM + //if (bIsRxAggrSubframe) + rx_desc_819x_usb_aggr_subframe *desc = (rx_desc_819x_usb_aggr_subframe *)skb->data; + else +#endif + rx_desc_819x_usb *desc = (rx_desc_819x_usb *)skb->data; + + if(0) + { + int m = 0; + printk("========================"); + for(m=0; m<skb->len; m++){ + if((m%32) == 0) + printk("\n"); + printk("%2x ",((u8*)skb->data)[m]); + } + printk("\n========================\n"); + + } + + + // + //Get Rx Descriptor Raw Information + // + stats->Length = desc->Length ; + stats->RxDrvInfoSize = desc->RxDrvInfoSize*RX_DRV_INFO_SIZE_UNIT; + stats->RxBufShift = (desc->Shift)&0x03; + stats->bICV = desc->ICV; + stats->bCRC = desc->CRC32; + stats->bHwError = stats->bCRC|stats->bICV; + stats->Decrypted = !desc->SWDec;//RTL8190 set this bit to indicate that Hw does not decrypt packet + stats->bIsAMPDU = (desc->AMSDU==1); + stats->bFirstMPDU = (desc->PAGGR==1) && (desc->FAGGR==1); + stats->bShortPreamble = desc->SPLCP; + stats->RxIs40MHzPacket = (desc->BW==1); + stats->TimeStampLow = desc->TSFL; + + if((desc->FAGGR==1) || (desc->PAGGR==1)) + {// Rx A-MPDU + RT_TRACE(COMP_RXDESC, "FirstAGGR = %d, PartAggr = %d\n", desc->FAGGR, desc->PAGGR); + } +//YJ,test,090310 +if(stats->bHwError) +{ + if(stats->bICV) + printk("%s: Receive ICV error!!!!!!!!!!!!!!!!!!!!!!\n", __FUNCTION__); + if(stats->bCRC) + printk("%s: Receive CRC error!!!!!!!!!!!!!!!!!!!!!!\n", __FUNCTION__); +} + + if(IS_UNDER_11N_AES_MODE(priv->ieee80211)) + { + // Always received ICV error packets in AES mode. + // This fixed HW later MIC write bug. + if(stats->bICV && !stats->bCRC) + { + stats->bICV = FALSE; + stats->bHwError = FALSE; + } + } + + // Transform HwRate to MRate + if(!stats->bHwError) + //stats->DataRate = HwRateToMRate( + // (BOOLEAN)GET_RX_DESC_RXHT(pDesc), + // (u1Byte)GET_RX_DESC_RXMCS(pDesc), + // (BOOLEAN)GET_RX_DESC_PAGGR(pDesc)); + stats->rate = rtl8192SU_HwRateToMRate(desc->RxHT, desc->RxMCS, desc->PAGGR); + else + stats->rate = MGN_1M; + + // + // Collect Rx rate/AMPDU/TSFL + // + //UpdateRxdRateHistogramStatistics8192S(Adapter, pRfd); + //UpdateRxAMPDUHistogramStatistics8192S(Adapter, pRfd); + //UpdateRxPktTimeStamp8192S(Adapter, pRfd); + UpdateReceivedRateHistogramStatistics8190(dev, stats); + //UpdateRxAMPDUHistogramStatistics8192S(dev, stats); //FIXLZM + UpdateRxPktTimeStamp8190(dev, stats); + + // + // Get PHY Status and RSVD parts. + // <Roger_Notes> It only appears on last aggregated packet. + // + if (desc->PHYStatus) + { + //driver_info = (rx_drvinfo_819x_usb *)(skb->data + RX_DESC_SIZE + stats->RxBufShift); + driver_info = (rx_drvinfo_819x_usb *)(skb->data + sizeof(rx_desc_819x_usb) + \ + stats->RxBufShift); + if(0) + { + int m = 0; + printk("========================\n"); + printk("RX_DESC_SIZE:%d, RxBufShift:%d, RxDrvInfoSize:%d\n", + RX_DESC_SIZE, stats->RxBufShift, stats->RxDrvInfoSize); + for(m=0; m<32; m++){ + printk("%2x ",((u8*)driver_info)[m]); + } + printk("\n========================\n"); + + } + + } + + //YJ,add,090107 + skb_pull(skb, sizeof(rx_desc_819x_usb)); + //YJ,add,090107,end + + // + // Get Total offset of MPDU Frame Body + // + if((stats->RxBufShift + stats->RxDrvInfoSize) > 0) + { + stats->bShift = 1; + //YJ,add,090107 + skb_pull(skb, stats->RxBufShift + stats->RxDrvInfoSize); + //YJ,add,090107,end + } + + // + // Get PHY Status and RSVD parts. + // <Roger_Notes> It only appears on last aggregated packet. + // + if (desc->PHYStatus) + { + rtl8192SU_TranslateRxSignalStuff(skb, stats, desc, driver_info); + } +} +#else +void query_rxdesc_status(struct sk_buff *skb, struct ieee80211_rx_stats *stats, bool bIsRxAggrSubframe) +{ + rtl8192_rx_info *info = (struct rtl8192_rx_info *)skb->cb; + struct net_device *dev=info->dev; + struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + //rx_desc_819x_usb *desc = (rx_desc_819x_usb *)skb->data; + rx_drvinfo_819x_usb *driver_info = NULL; + + // + //Get Rx Descriptor Information + // +#ifdef USB_RX_AGGREGATION_SUPPORT + if (bIsRxAggrSubframe) + { + rx_desc_819x_usb_aggr_subframe *desc = (rx_desc_819x_usb_aggr_subframe *)skb->data; + stats->Length = desc->Length ; + stats->RxDrvInfoSize = desc->RxDrvInfoSize; + stats->RxBufShift = 0; //RxBufShift = 2 in RxDesc, but usb didn't shift bytes in fact. + stats->bICV = desc->ICV; + stats->bCRC = desc->CRC32; + stats->bHwError = stats->bCRC|stats->bICV; + stats->Decrypted = !desc->SWDec;//RTL8190 set this bit to indicate that Hw does not decrypt packet + } else +#endif + { + rx_desc_819x_usb *desc = (rx_desc_819x_usb *)skb->data; + + stats->Length = desc->Length; + stats->RxDrvInfoSize = desc->RxDrvInfoSize; + stats->RxBufShift = 0;//desc->Shift&0x03; + stats->bICV = desc->ICV; + stats->bCRC = desc->CRC32; + stats->bHwError = stats->bCRC|stats->bICV; + //RTL8190 set this bit to indicate that Hw does not decrypt packet + stats->Decrypted = !desc->SWDec; + } + + if((priv->ieee80211->pHTInfo->bCurrentHTSupport == true) && (priv->ieee80211->pairwise_key_type == KEY_TYPE_CCMP)) + { + stats->bHwError = false; + } + else + { + stats->bHwError = stats->bCRC|stats->bICV; + } + + if(stats->Length < 24 || stats->Length > MAX_8192U_RX_SIZE) + stats->bHwError |= 1; + // + //Get Driver Info + // + // TODO: Need to verify it on FGPA platform + //Driver info are written to the RxBuffer following rx desc + if (stats->RxDrvInfoSize != 0) { + driver_info = (rx_drvinfo_819x_usb *)(skb->data + sizeof(rx_desc_819x_usb) + \ + stats->RxBufShift); + /* unit: 0.5M */ + /* TODO */ + if(!stats->bHwError){ + u8 ret_rate; + ret_rate = HwRateToMRate90(driver_info->RxHT, driver_info->RxRate); + if(ret_rate == 0xff) + { + // Abnormal Case: Receive CRC OK packet with Rx descriptor indicating non supported rate. + // Special Error Handling here, 2008.05.16, by Emily + + stats->bHwError = 1; + stats->rate = MGN_1M; //Set 1M rate by default + }else + { + stats->rate = ret_rate; + } + } + else + stats->rate = 0x02; + + stats->bShortPreamble = driver_info->SPLCP; + + + UpdateReceivedRateHistogramStatistics8190(dev, stats); + + stats->bIsAMPDU = (driver_info->PartAggr==1); + stats->bFirstMPDU = (driver_info->PartAggr==1) && (driver_info->FirstAGGR==1); +#if 0 + // TODO: it is debug only. It should be disabled in released driver. 2007.1.12 by Joseph + UpdateRxAMPDUHistogramStatistics8190(Adapter, pRfd); +#endif + stats->TimeStampLow = driver_info->TSFL; + // xiong mask it, 070514 + //pRfd->Status.TimeStampHigh = PlatformEFIORead4Byte(Adapter, TSFR+4); + // stats->TimeStampHigh = read_nic_dword(dev, TSFR+4); + + UpdateRxPktTimeStamp8190(dev, stats); + + // + // Rx A-MPDU + // + if(driver_info->FirstAGGR==1 || driver_info->PartAggr == 1) + RT_TRACE(COMP_RXDESC, "driver_info->FirstAGGR = %d, driver_info->PartAggr = %d\n", + driver_info->FirstAGGR, driver_info->PartAggr); + + } + + skb_pull(skb,sizeof(rx_desc_819x_usb)); + // + // Get Total offset of MPDU Frame Body + // + if((stats->RxBufShift + stats->RxDrvInfoSize) > 0) { + stats->bShift = 1; + skb_pull(skb,stats->RxBufShift + stats->RxDrvInfoSize); + } + +#ifdef USB_RX_AGGREGATION_SUPPORT + /* for the rx aggregated sub frame, the redundant space truelly contained in the packet */ + if(bIsRxAggrSubframe) { + skb_pull(skb, 8); + } +#endif + /* for debug 2008.5.29 */ +#if 0 + { + int i; + printk("\n>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); + for(i = 0; i < skb->len; i++) { + if(i % 10 == 0) printk("\n"); + printk("%02x ", skb->data[i]); + } + printk("\n<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n"); + } +#endif + + //added by vivi, for MP, 20080108 + stats->RxIs40MHzPacket = driver_info->BW; + if(stats->RxDrvInfoSize != 0) + TranslateRxSignalStuff819xUsb(skb, stats, driver_info); + +} +#endif + +#ifdef RTL8192SU +#if 0 +/*----------------------------------------------------------------------------- + * Function: UpdateRxAMPDUHistogramStatistics8192S + * + * Overview: Recored down the received A-MPDU aggregation size and pkt number + * + * Input: Adapter + * + * Output: Adapter + * (Adapter->RxStats.RxAMPDUSizeHistogram[] is updated) + * (Adapter->RxStats.RxAMPDUNumHistogram[] is updated) + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 09/18/2008 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +static void +UpdateRxAMPDUHistogramStatistics8192S( + struct net_device *dev, + struct ieee80211_rx_stats *stats + ) +{ + //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u8 size_index; + u8 num_index; + u16 update_size = 0; + u8 update_num = 0; + + if(stats->bIsAMPDU) + { + if(stats->bFirstMPDU) + { + if(stats->nRxAMPDU_Size!=0 && stats->nRxAMPDU_AggrNum!=0) + { + update_size = stats->nRxAMPDU_Size; + update_num = stats->nRxAMPDU_AggrNum; + } + stats->nRxAMPDU_Size = stats->Length; + stats->nRxAMPDU_AggrNum = 1; + } + else + { + stats->nRxAMPDU_Size += stats->Length; + stats->nRxAMPDU_AggrNum++; + } + } + else + { + if(stats->nRxAMPDU_Size!=0 && stats->nRxAMPDU_AggrNum!=0) + { + update_size = stats->nRxAMPDU_Size; + update_num = stats->nRxAMPDU_AggrNum; + } + stats->nRxAMPDU_Size = 0; + stats->nRxAMPDU_AggrNum = 0; + } + + if(update_size!=0 && update_num!= 0) + { + if(update_size < 4096) + size_index = 0; + else if(update_size < 8192) + size_index = 1; + else if(update_size < 16384) + size_index = 2; + else if(update_size < 32768) + size_index = 3; + else if(update_size < 65536) + size_index = 4; + else + { + RT_TRACE(COMP_RXDESC, + ("UpdateRxAMPDUHistogramStatistics8192S(): A-MPDU too large\n"); + } + + Adapter->RxStats.RxAMPDUSizeHistogram[size_index]++; + + if(update_num < 5) + num_index = 0; + else if(update_num < 10) + num_index = 1; + else if(update_num < 20) + num_index = 2; + else if(update_num < 40) + num_index = 3; + else + num_index = 4; + + Adapter->RxStats.RxAMPDUNumHistogram[num_index]++; + } +} // UpdateRxAMPDUHistogramStatistics8192S +#endif + +#endif + + +#ifdef RTL8192SU +// +// Description: +// The strarting address of wireless lan header will shift 1 or 2 or 3 or "more" bytes for the following reason : +// (1) QoS control : shift 2 bytes +// (2) Mesh Network : shift 1 or 3 bytes +// (3) RxDriverInfo occupies the front parts of Rx Packets buffer(shift units is in 8Bytes) +// +// It is because Lextra CPU used by 8186 or 865x series assert exception if the statrting address +// of IP header is not double word alignment. +// This features is supported in 818xb and 8190 only, but not 818x. +// +// parameter: PRT_RFD, Pointer of Reeceive frame descriptor which is initialized according to +// Rx Descriptor +// return value: unsigned int, number of total shifted bytes +// +// Notes: 2008/06/28, created by Roger +// +u32 GetRxPacketShiftBytes8192SU(struct ieee80211_rx_stats *Status, bool bIsRxAggrSubframe) +{ + //PRT_RFD_STATUS pRtRfdStatus = &pRfd->Status; + + return (sizeof(rx_desc_819x_usb) + Status->RxDrvInfoSize + Status->RxBufShift); +} + +void rtl8192SU_rx_nomal(struct sk_buff* skb) +{ + rtl8192_rx_info *info = (struct rtl8192_rx_info *)skb->cb; + struct net_device *dev=info->dev; + struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + struct ieee80211_rx_stats stats = { + .signal = 0, + .noise = -98, + .rate = 0, + // .mac_time = jiffies, + .freq = IEEE80211_24GHZ_BAND, + }; + u32 rx_pkt_len = 0; + struct ieee80211_hdr_1addr *ieee80211_hdr = NULL; + bool unicast_packet = false; + +#ifdef USB_RX_AGGREGATION_SUPPORT + struct sk_buff *agg_skb = NULL; + u32 TotalLength = 0;//Total packet length for all aggregated packets. + u32 TempDWord = 0; + u32 PacketLength = 0;// Per-packet length include size of RxDesc. + u32 PacketOccupiedLendth = 0; + u8 TempByte = 0; + u32 PacketShiftBytes = 0; + rx_desc_819x_usb_aggr_subframe *RxDescr = NULL; + u8 PaddingBytes = 0; + //add just for testing + u8 testing; + + u8 TotalAggPkt = 0; + PRT_HIGH_THROUGHPUT pHTInfo =priv-> ieee80211->pHTInfo; + u16 RxPageSize = pHTInfo->UsbRxPageSize; + + stats->nTotalAggPkt = 0; + //stats->bIsRxAggrSubframe = FALSE; + +#endif + //printk("**********skb->len = %d\n", skb->len); + /* 20 is for ps-poll */ + if((skb->len >=(20 + sizeof(rx_desc_819x_usb))) && (skb->len < RX_URB_SIZE)) { + + /* first packet should not contain Rx aggregation header */ + rtl8192SU_query_rxdesc_status(skb, &stats, false); + /* TODO */ + + /* hardware related info */ +#ifdef USB_RX_AGGREGATION_SUPPORT + TotalAggPkt = stats->nTotalAggPkt; + PacketLength = stats->Length + GetRxPacketShiftBytes8192SU(&stats, false); + + agg_skb = skb; + skb = dev_alloc_skb(PacketLength); + memcpy(skb_put(skb,PacketLength),agg_skb->data,PacketLength); +#endif + priv->stats.rxoktotal++; //YJ,test,090108 + + /* Process the MPDU recevied */ + skb_trim(skb, skb->len - 4/*sCrcLng*/);//FIXLZM + + rx_pkt_len = skb->len; + ieee80211_hdr = (struct ieee80211_hdr_1addr *)skb->data; + unicast_packet = false; + if(is_broadcast_ether_addr(ieee80211_hdr->addr1)) { + //TODO + }else if(is_multicast_ether_addr(ieee80211_hdr->addr1)){ + //TODO + }else { + /* unicast packet */ + unicast_packet = true; + } + + if(!ieee80211_rx(priv->ieee80211,skb, &stats)) { + dev_kfree_skb_any(skb); + } else { + // priv->stats.rxoktotal++; //YJ,test,090108 + if(unicast_packet) { + priv->stats.rxbytesunicast += rx_pkt_len; + } + } + + //up is firs pkt, follow is next and next +#ifdef USB_RX_AGGREGATION_SUPPORT + // + // The following operations are for processing Rx aggregated packets. + // + if(TotalAggPkt>0) + TotalAggPkt--; + + while ( TotalAggPkt>0 ) + {// More aggregated packets need to process. + + u8 tmpCRC = 0, tmpICV = 0; + + //Page size must align to multiple of 128-Bytes. + if((PacketLength%RxPageSize) != 0) + //PacketLength = ((PacketLength/RxPageSize)+1)*RxPageSize; + PacketLength = ((PacketLength>>7)+1)*RxPageSize; // RxPageSize is 128bytes as default. + + // Current total packet occupied length in this buffer. + PacketOccupiedLendth += PacketLength; + +#if (defined (RTL8192SU_FPGA_2MAC_VERIFICATION)||defined (RTL8192SU_ASIC_VERIFICATION)) + //if(PacketOccupiedLendth>pContext->BufLenUsed) + if(PacketOccupiedLendth>skb->len) + { + RT_TRACE(COMP_RECV, "(1)HalUsbInMpduComplete8192SUsb(): pRtRfdStatus->Length(%#x)!!\n", stats->Length); + RT_TRACE(COMP_RECV, "(1)HalUsbInMpduComplete8192SUsb(): Invalid PacketOccupiedLendth(%#x)!!, BufLenUsed(%#x)\n", PacketOccupiedLendth, stats->BufLenUsed); + break; + } +#endif + + skb_pull(agg_skb, PacketLength); + + // + // Process the MPDU recevied. + // + //RT_TRACE(COMP_RECV,"%s:aggred pkt,total_len = %d\n",__FUNCTION__,agg_skb->len); + RxDescr = (rx_desc_819x_usb_aggr_subframe *)(agg_skb->data); + +#if 0//92SU del + tmpCRC = RxDescr->CRC32; + tmpICV = RxDescr->ICV; + memcpy(agg_skb->data, &agg_skb->data[44], 2); + RxDescr->CRC32 = tmpCRC; + RxDescr->ICV = tmpICV; +#endif + memset(&stats, 0, sizeof(struct ieee80211_rx_stats)); + stats.signal = 0; + stats.noise = -98; + stats.rate = 0; + stats.freq = IEEE80211_24GHZ_BAND; + + rtl8192SU_query_rxdesc_status(agg_skb, &stats, true); + //PacketLength = stats.Length; + PacketLength = stats.Length + GetRxPacketShiftBytes8192SU(&stats, true); + +#if (defined (RTL8192SU_FPGA_2MAC_VERIFICATION)||defined (RTL8192SU_ASIC_VERIFICATION)) + if((PacketOccupiedLendth+PacketLength)>skb->len) + { + RT_TRACE(COMP_RECV, "(2)HalUsbInMpduComplete8192SUsb(): Invalid PacketOccupiedLendth(%#x)+PacketLength(%#x)!!, BufLenUsed(%#x)\n", + PacketOccupiedLendth, PacketLength, pContext->BufLenUsed); + break; + } +#endif + + if(PacketLength > agg_skb->len) { + break; + } + + /* Process the MPDU recevied */ + skb = dev_alloc_skb(PacketLength); + memcpy(skb_put(skb,PacketLength),agg_skb->data, PacketLength); + skb_trim(skb, skb->len - 4/*sCrcLng*/); + + rx_pkt_len = skb->len; + ieee80211_hdr = (struct ieee80211_hdr_1addr *)skb->data; + unicast_packet = false; + if(is_broadcast_ether_addr(ieee80211_hdr->addr1)) { + //TODO + }else if(is_multicast_ether_addr(ieee80211_hdr->addr1)){ + //TODO + }else { + /* unicast packet */ + unicast_packet = true; + } + if(!ieee80211_rx(priv->ieee80211,skb, &stats)) { + dev_kfree_skb_any(skb); + } else { + priv->stats.rxoktotal++; + if(unicast_packet) { + priv->stats.rxbytesunicast += rx_pkt_len; + } + } + + TotalAggPkt--; + + skb_pull(agg_skb, TempDWord); + } + + dev_kfree_skb(agg_skb); +#endif + } + else + { + priv->stats.rxurberr++; + printk("actual_length:%d\n", skb->len); + dev_kfree_skb_any(skb); + } + +} +#else +u32 GetRxPacketShiftBytes819xUsb(struct ieee80211_rx_stats *Status, bool bIsRxAggrSubframe) +{ +#ifdef USB_RX_AGGREGATION_SUPPORT + if (bIsRxAggrSubframe) + return (sizeof(rx_desc_819x_usb) + Status->RxDrvInfoSize + + Status->RxBufShift + 8); + else +#endif + return (sizeof(rx_desc_819x_usb) + Status->RxDrvInfoSize + + Status->RxBufShift); +} + +void rtl8192_rx_nomal(struct sk_buff* skb) +{ + rtl8192_rx_info *info = (struct rtl8192_rx_info *)skb->cb; + struct net_device *dev=info->dev; + struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + struct ieee80211_rx_stats stats = { + .signal = 0, + .noise = -98, + .rate = 0, + // .mac_time = jiffies, + .freq = IEEE80211_24GHZ_BAND, + }; + u32 rx_pkt_len = 0; + struct ieee80211_hdr_1addr *ieee80211_hdr = NULL; + bool unicast_packet = false; +#ifdef USB_RX_AGGREGATION_SUPPORT + struct sk_buff *agg_skb = NULL; + u32 TotalLength = 0; + u32 TempDWord = 0; + u32 PacketLength = 0; + u32 PacketOccupiedLendth = 0; + u8 TempByte = 0; + u32 PacketShiftBytes = 0; + rx_desc_819x_usb_aggr_subframe *RxDescr = NULL; + u8 PaddingBytes = 0; + //add just for testing + u8 testing; + +#endif + + /* 20 is for ps-poll */ + if((skb->len >=(20 + sizeof(rx_desc_819x_usb))) && (skb->len < RX_URB_SIZE)) { +#ifdef USB_RX_AGGREGATION_SUPPORT + TempByte = *(skb->data + sizeof(rx_desc_819x_usb)); +#endif + /* first packet should not contain Rx aggregation header */ + query_rxdesc_status(skb, &stats, false); + /* TODO */ + /* hardware related info */ +#ifdef USB_RX_AGGREGATION_SUPPORT + if (TempByte & BIT0) { + agg_skb = skb; + //TotalLength = agg_skb->len - 4; /*sCrcLng*/ + TotalLength = stats.Length - 4; /*sCrcLng*/ + //RT_TRACE(COMP_RECV, "%s:first aggregated packet!Length=%d\n",__FUNCTION__,TotalLength); + /* though the head pointer has passed this position */ + TempDWord = *(u32 *)(agg_skb->data - 4); + PacketLength = (u16)(TempDWord & 0x3FFF); /*sCrcLng*/ + skb = dev_alloc_skb(PacketLength); + memcpy(skb_put(skb,PacketLength),agg_skb->data,PacketLength); + PacketShiftBytes = GetRxPacketShiftBytes819xUsb(&stats, false); + } +#endif + /* Process the MPDU recevied */ + skb_trim(skb, skb->len - 4/*sCrcLng*/); + + rx_pkt_len = skb->len; + ieee80211_hdr = (struct ieee80211_hdr_1addr *)skb->data; + unicast_packet = false; + if(is_broadcast_ether_addr(ieee80211_hdr->addr1)) { + //TODO + }else if(is_multicast_ether_addr(ieee80211_hdr->addr1)){ + //TODO + }else { + /* unicast packet */ + unicast_packet = true; + } + + if(!ieee80211_rx(priv->ieee80211,skb, &stats)) { + dev_kfree_skb_any(skb); + } else { + priv->stats.rxoktotal++; + if(unicast_packet) { + priv->stats.rxbytesunicast += rx_pkt_len; + } + } +#ifdef USB_RX_AGGREGATION_SUPPORT + testing = 1; + // (PipeIndex == 0) && (TempByte & BIT0) => TotalLength > 0. + if (TotalLength > 0) { + PacketOccupiedLendth = PacketLength + (PacketShiftBytes + 8); + if ((PacketOccupiedLendth & 0xFF) != 0) + PacketOccupiedLendth = (PacketOccupiedLendth & 0xFFFFFF00) + 256; + PacketOccupiedLendth -= 8; + TempDWord = PacketOccupiedLendth - PacketShiftBytes; /*- PacketLength */ + if (agg_skb->len > TempDWord) + skb_pull(agg_skb, TempDWord); + else + agg_skb->len = 0; + + while (agg_skb->len>=GetRxPacketShiftBytes819xUsb(&stats, true)) { + u8 tmpCRC = 0, tmpICV = 0; + //RT_TRACE(COMP_RECV,"%s:aggred pkt,total_len = %d\n",__FUNCTION__,agg_skb->len); + RxDescr = (rx_desc_819x_usb_aggr_subframe *)(agg_skb->data); + tmpCRC = RxDescr->CRC32; + tmpICV = RxDescr->ICV; + memcpy(agg_skb->data, &agg_skb->data[44], 2); + RxDescr->CRC32 = tmpCRC; + RxDescr->ICV = tmpICV; + + memset(&stats, 0, sizeof(struct ieee80211_rx_stats)); + stats.signal = 0; + stats.noise = -98; + stats.rate = 0; + stats.freq = IEEE80211_24GHZ_BAND; + query_rxdesc_status(agg_skb, &stats, true); + PacketLength = stats.Length; + + if(PacketLength > agg_skb->len) { + break; + } + /* Process the MPDU recevied */ + skb = dev_alloc_skb(PacketLength); + memcpy(skb_put(skb,PacketLength),agg_skb->data, PacketLength); + skb_trim(skb, skb->len - 4/*sCrcLng*/); + + rx_pkt_len = skb->len; + ieee80211_hdr = (struct ieee80211_hdr_1addr *)skb->data; + unicast_packet = false; + if(is_broadcast_ether_addr(ieee80211_hdr->addr1)) { + //TODO + }else if(is_multicast_ether_addr(ieee80211_hdr->addr1)){ + //TODO + }else { + /* unicast packet */ + unicast_packet = true; + } + if(!ieee80211_rx(priv->ieee80211,skb, &stats)) { + dev_kfree_skb_any(skb); + } else { + priv->stats.rxoktotal++; + if(unicast_packet) { + priv->stats.rxbytesunicast += rx_pkt_len; + } + } + /* should trim the packet which has been copied to target skb */ + skb_pull(agg_skb, PacketLength); + PacketShiftBytes = GetRxPacketShiftBytes819xUsb(&stats, true); + PacketOccupiedLendth = PacketLength + PacketShiftBytes; + if ((PacketOccupiedLendth & 0xFF) != 0) { + PaddingBytes = 256 - (PacketOccupiedLendth & 0xFF); + if (agg_skb->len > PaddingBytes) + skb_pull(agg_skb, PaddingBytes); + else + agg_skb->len = 0; + } + } + dev_kfree_skb(agg_skb); + } +#endif + } else { + priv->stats.rxurberr++; + printk("actual_length:%d\n", skb->len); + dev_kfree_skb_any(skb); + } + +} + +#endif + +void +rtl819xusb_process_received_packet( + struct net_device *dev, + struct ieee80211_rx_stats *pstats + ) +{ +// bool bfreerfd=false, bqueued=false; + u8* frame; + u16 frame_len=0; + struct r8192_priv *priv = ieee80211_priv(dev); +// u8 index = 0; +// u8 TID = 0; + //u16 seqnum = 0; + //PRX_TS_RECORD pts = NULL; + + // Get shifted bytes of Starting address of 802.11 header. 2006.09.28, by Emily + //porting by amy 080508 + pstats->virtual_address += get_rxpacket_shiftbytes_819xusb(pstats); + frame = pstats->virtual_address; + frame_len = pstats->packetlength; +#ifdef TODO // by amy about HCT + if(!Adapter->bInHctTest) + CountRxErrStatistics(Adapter, pRfd); +#endif + { + #ifdef ENABLE_PS //by amy for adding ps function in future + RT_RF_POWER_STATE rtState; + // When RF is off, we should not count the packet for hw/sw synchronize + // reason, ie. there may be a duration while sw switch is changed and hw + // switch is being changed. 2006.12.04, by shien chang. + Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (u8* )(&rtState)); + if (rtState == eRfOff) + { + return; + } + #endif + priv->stats.rxframgment++; + + } +#ifdef TODO + RmMonitorSignalStrength(Adapter, pRfd); +#endif + /* 2007/01/16 MH Add RX command packet handle here. */ + /* 2007/03/01 MH We have to release RFD and return if rx pkt is cmd pkt. */ + if (rtl819xusb_rx_command_packet(dev, pstats)) + { + return; + } + +#ifdef SW_CRC_CHECK + SwCrcCheck(); +#endif + + +} + +void query_rx_cmdpkt_desc_status(struct sk_buff *skb, struct ieee80211_rx_stats *stats) +{ +// rtl8192_rx_info *info = (struct rtl8192_rx_info *)skb->cb; +// struct net_device *dev=info->dev; +// struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + rx_desc_819x_usb *desc = (rx_desc_819x_usb *)skb->data; +// rx_drvinfo_819x_usb *driver_info; + + // + //Get Rx Descriptor Information + // + stats->virtual_address = (u8*)skb->data; + stats->Length = desc->Length; + stats->RxDrvInfoSize = 0; + stats->RxBufShift = 0; + stats->packetlength = stats->Length-scrclng; + stats->fraglength = stats->packetlength; + stats->fragoffset = 0; + stats->ntotalfrag = 1; +} + +#ifdef RTL8192SU +void rtl8192SU_rx_cmd(struct sk_buff *skb) +{ + struct rtl8192_rx_info *info = (struct rtl8192_rx_info *)skb->cb; + struct net_device *dev = info->dev; + + /* TODO */ + struct ieee80211_rx_stats stats = { + .signal = 0, + .noise = -98, + .rate = 0, + // .mac_time = jiffies, + .freq = IEEE80211_24GHZ_BAND, + }; + + // + // Check buffer length to determine if this is a valid MPDU. + // + if( (skb->len >= sizeof(rx_desc_819x_usb)) && (skb->len <= RX_URB_SIZE) )//&& + //(pHalData->SwChnlInProgress == FALSE)) + { + // + // Collection information in Rx descriptor. + // +#if 0 + pRxDesc = pContext->Buffer; + + pRfd->Buffer.VirtualAddress = pContext->Buffer; // 061109, rcnjko, for multi-platform consideration.. + + pRtRfdStatus->Length = (u2Byte)GET_RX_DESC_PKT_LEN(pRxDesc); + pRtRfdStatus->RxDrvInfoSize = 0; + pRtRfdStatus->RxBufShift = 0; + + pRfd->PacketLength = pRfd->Status.Length - sCrcLng; + pRfd->FragLength = pRfd->PacketLength; + pRfd->FragOffset = 0; + pRfd->nTotalFrag = 1; + pRfd->queue_id = PipeIndex; +#endif + query_rx_cmdpkt_desc_status(skb,&stats); + // this is to be done by amy 080508 prfd->queue_id = 1; + + // + // Process the MPDU recevied. + // + rtl819xusb_process_received_packet(dev,&stats); + + dev_kfree_skb_any(skb); + } + else + { + //RTInsertTailListWithCnt(&pAdapter->RfdIdleQueue, &pRfd->List, &pAdapter->NumIdleRfd); + //RT_ASSERT(pAdapter->NumIdleRfd <= pAdapter->NumRfd, ("HalUsbInCommandComplete8192SUsb(): Adapter->NumIdleRfd(%d)\n", pAdapter->NumIdleRfd)); + //RT_TRACE(COMP_RECV, DBG_LOUD, ("HalUsbInCommandComplete8192SUsb(): NOT enough Resources!! BufLenUsed(%d), NumIdleRfd(%d)\n", + //pContext->BufLenUsed, pAdapter->NumIdleRfd)); + } + + // + // Reuse USB_IN_CONTEXT since we had finished processing the + // buffer in USB_IN_CONTEXT. + // + //HalUsbReturnInContext(pAdapter, pContext); + + // + // Issue another bulk IN transfer. + // + //HalUsbInMpdu(pAdapter, PipeIndex); + + RT_TRACE(COMP_RECV, "<--- HalUsbInCommandComplete8192SUsb()\n"); + +} +#else +void rtl8192_rx_cmd(struct sk_buff *skb) +{ + struct rtl8192_rx_info *info = (struct rtl8192_rx_info *)skb->cb; + struct net_device *dev = info->dev; + //int ret; +// struct urb *rx_urb = info->urb; + /* TODO */ + struct ieee80211_rx_stats stats = { + .signal = 0, + .noise = -98, + .rate = 0, + // .mac_time = jiffies, + .freq = IEEE80211_24GHZ_BAND, + }; + + if((skb->len >=(20 + sizeof(rx_desc_819x_usb))) && (skb->len < RX_URB_SIZE)) + { + + query_rx_cmdpkt_desc_status(skb,&stats); + // this is to be done by amy 080508 prfd->queue_id = 1; + + + // + // Process the command packet received. + // + + rtl819xusb_process_received_packet(dev,&stats); + + dev_kfree_skb_any(skb); + } + else + ; + + +#if 0 + desc = (u32*)(skb->data); + cmd = (desc[0] >> 30) & 0x03; + + if(cmd == 0x00) {//beacon interrupt + //send beacon packet + skb = ieee80211_get_beacon(priv->ieee80211); + + if(!skb){ + DMESG("not enought memory for allocating beacon"); + return; + } + skb->cb[0] = BEACON_PRIORITY; + skb->cb[1] = 0; + skb->cb[2] = ieeerate2rtlrate(priv->ieee80211->basic_rate); + ret = rtl8192_tx(dev, skb); + + if( ret != 0 ){ + printk(KERN_ALERT "tx beacon packet error : %d !\n", ret); + } + dev_kfree_skb_any(skb); + } else {//0x00 + //{ log the device information + // At present, It is not implemented just now. + //} + } +#endif +} +#endif + +void rtl8192_irq_rx_tasklet(struct r8192_priv *priv) +{ + struct sk_buff *skb; + struct rtl8192_rx_info *info; + + while (NULL != (skb = skb_dequeue(&priv->skb_queue))) { + info = (struct rtl8192_rx_info *)skb->cb; + switch (info->out_pipe) { + /* Nomal packet pipe */ + case 3: + //RT_TRACE(COMP_RECV, "normal in-pipe index(%d)\n",info->out_pipe); + priv->IrpPendingCount--; + priv->ops->rtl819x_rx_nomal(skb); + break; + + /* Command packet pipe */ + case 9: + RT_TRACE(COMP_RECV, "command in-pipe index(%d)\n",\ + info->out_pipe); + priv->ops->rtl819x_rx_cmd(skb); + break; + + default: /* should never get here! */ + RT_TRACE(COMP_ERR, "Unknown in-pipe index(%d)\n",\ + info->out_pipe); + dev_kfree_skb(skb); + break; + + } + } +} + + + +/**************************************************************************** + ---------------------------- USB_STUFF--------------------------- +*****************************************************************************/ +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) +//LZM Merge from windows HalUsbSetQueuePipeMapping8192SUsb 090319 +static void HalUsbSetQueuePipeMapping8192SUsb(struct usb_interface *intf, struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + struct usb_host_interface *iface_desc; + struct usb_endpoint_descriptor *endpoint; + u8 i = 0; + + priv->ep_in_num = 0; + priv->ep_out_num = 0; + memset(priv->RtOutPipes,0,16); + memset(priv->RtInPipes,0,16); + +#ifndef USE_ONE_PIPE + iface_desc = intf->cur_altsetting; + priv->ep_num = iface_desc->desc.bNumEndpoints; + + for (i = 0; i < priv->ep_num; ++i) { + endpoint = &iface_desc->endpoint[i].desc; +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,23) + if (usb_endpoint_is_bulk_in(endpoint)) { + priv->RtInPipes[priv->ep_in_num] = usb_endpoint_num(endpoint); + priv->ep_in_num ++; + //printk("in_endpoint_idx = %d\n", usb_endpoint_num(endpoint)); + } else if (usb_endpoint_is_bulk_out(endpoint)) { + priv->RtOutPipes[priv->ep_out_num] = usb_endpoint_num(endpoint); + priv->ep_out_num ++; + //printk("out_endpoint_idx = %d\n", usb_endpoint_num(endpoint)); + } +#else + if ((endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK) && + ((endpoint->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK)) { + /* we found a bulk in endpoint */ + priv->RtInPipes[priv->ep_in_num] = (endpoint->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK); + priv->ep_in_num ++; + } else if (((endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK) == USB_DIR_OUT) && + ((endpoint->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK)) { + /* We found bulk out endpoint */ + priv->RtOutPipes[priv->ep_out_num] = endpoint->bEndpointAddress; + priv->ep_out_num ++; + } +#endif + } + { + memset(priv->txqueue_to_outpipemap,0,9); + if (priv->ep_num == 6) { + // BK, BE, VI, VO, HCCA, TXCMD, MGNT, HIGH, BEACON + u8 queuetopipe[] = {3, 2, 1, 0, 4, 4, 4, 4, 4}; + + memcpy(priv->txqueue_to_outpipemap,queuetopipe,9); + } else if (priv->ep_num == 4) { + // BK, BE, VI, VO, HCCA, TXCMD, MGNT, HIGH, BEACON + u8 queuetopipe[] = {1, 1, 0, 0, 2, 2, 2, 2, 2}; + + memcpy(priv->txqueue_to_outpipemap,queuetopipe,9); + } else if (priv->ep_num > 9) { + // BK, BE, VI, VO, HCCA, TXCMD, MGNT, HIGH, BEACON + u8 queuetopipe[] = {3, 2, 1, 0, 4, 8, 7, 6, 5}; + + memcpy(priv->txqueue_to_outpipemap,queuetopipe,9); + } else {//use sigle pipe + // BK, BE, VI, VO, HCCA, TXCMD, MGNT, HIGH, BEACON + u8 queuetopipe[] = {0, 0, 0, 0, 0, 0, 0, 0, 0}; + memcpy(priv->txqueue_to_outpipemap,queuetopipe,9); + } + } + printk("==>ep_num:%d, in_ep_num:%d, out_ep_num:%d\n", priv->ep_num, priv->ep_in_num, priv->ep_out_num); + + printk("==>RtInPipes:"); + for(i=0; i < priv->ep_in_num; i++) + printk("%d ", priv->RtInPipes[i]); + printk("\n"); + + printk("==>RtOutPipes:"); + for(i=0; i < priv->ep_out_num; i++) + printk("%d ", priv->RtOutPipes[i]); + printk("\n"); + + printk("==>txqueue_to_outpipemap for BK, BE, VI, VO, HCCA, TXCMD, MGNT, HIGH, BEACON:\n"); + for(i=0; i < 9; i++) + printk("%d ", priv->txqueue_to_outpipemap[i]); + printk("\n"); +#else + { + memset(priv->txqueue_to_outpipemap,0,9); + memset(priv->RtOutPipes,4,16);//all use endpoint 4 for out + } +#endif + + return; +} +#endif + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) +static int __devinit rtl8192_usb_probe(struct usb_interface *intf, + const struct usb_device_id *id) +#else +static void * __devinit rtl8192_usb_probe(struct usb_device *udev, + unsigned int ifnum, + const struct usb_device_id *id) +#endif +{ +// unsigned long ioaddr = 0; + struct net_device *dev = NULL; + struct r8192_priv *priv= NULL; +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + struct usb_device *udev = interface_to_usbdev(intf); +#endif + RT_TRACE(COMP_INIT, "Oops: i'm coming\n"); + + dev = alloc_ieee80211(sizeof(struct r8192_priv)); + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) + SET_MODULE_OWNER(dev); +#endif + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + usb_set_intfdata(intf, dev); + SET_NETDEV_DEV(dev, &intf->dev); +#endif + priv = ieee80211_priv(dev); +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + priv->ieee80211 = netdev_priv(dev); +#else + priv->ieee80211 = (struct net_device *)dev->priv; +#endif + priv->udev=udev; + +#ifdef RTL8192SU +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + HalUsbSetQueuePipeMapping8192SUsb(intf, dev); +#else//use one pipe + { + memset(priv->txqueue_to_outpipemap,0,9); + memset(priv->RtOutPipes,4,16);//all use endpoint 4 for out + } +#endif +#endif + +#ifdef RTL8192SU + //printk("===============>NIC 8192SU\n"); + priv->ops = &rtl8192su_ops; +#else + //printk("===============>NIC 8192U\n"); + priv->ops = &rtl8192u_ops; +#endif + + dev->open = rtl8192_open; + dev->stop = rtl8192_close; + //dev->hard_start_xmit = rtl8192_8023_hard_start_xmit; + dev->tx_timeout = tx_timeout; + //dev->wireless_handlers = &r8192_wx_handlers_def; + dev->do_ioctl = rtl8192_ioctl; + dev->set_multicast_list = r8192_set_multicast; + dev->set_mac_address = r8192_set_mac_adr; + dev->get_stats = rtl8192_stats; + + //DMESG("Oops: i'm coming\n"); +#if WIRELESS_EXT >= 12 +#if WIRELESS_EXT < 17 + dev->get_wireless_stats = r8192_get_wireless_stats; +#endif + dev->wireless_handlers = (struct iw_handler_def *) &r8192_wx_handlers_def; +#endif + dev->type=ARPHRD_ETHER; + + dev->watchdog_timeo = HZ*3; //modified by john, 0805 + + if (dev_alloc_name(dev, ifname) < 0){ + RT_TRACE(COMP_INIT, "Oops: devname already taken! Trying wlan%%d...\n"); + ifname = "wlan%d"; + dev_alloc_name(dev, ifname); + } + + RT_TRACE(COMP_INIT, "Driver probe completed1\n"); +#if 1 + if(rtl8192_init(dev)!=0){ + RT_TRACE(COMP_ERR, "Initialization failed"); + goto fail; + } +#endif + netif_carrier_off(dev); + netif_stop_queue(dev); + + register_netdev(dev); + RT_TRACE(COMP_INIT, "dev name=======> %s\n",dev->name); + rtl8192_proc_init_one(dev); + + + RT_TRACE(COMP_INIT, "Driver probe completed\n"); +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) + return dev; +#else + return 0; +#endif + + +fail: + free_ieee80211(dev); + + RT_TRACE(COMP_ERR, "wlan driver load failed\n"); +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) + return NULL; +#else + return -ENODEV; +#endif + +} + +//detach all the work and timer structure declared or inititialize in r8192U_init function. +void rtl8192_cancel_deferred_work(struct r8192_priv* priv) +{ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22) + cancel_work_sync(&priv->reset_wq); + cancel_work_sync(&priv->qos_activate); + cancel_delayed_work(&priv->watch_dog_wq); + cancel_delayed_work(&priv->update_beacon_wq); + cancel_delayed_work(&priv->ieee80211->hw_wakeup_wq); + cancel_delayed_work(&priv->ieee80211->hw_sleep_wq); + //cancel_work_sync(&priv->SetBWModeWorkItem); + //cancel_work_sync(&priv->SwChnlWorkItem); +#else +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + cancel_delayed_work(&priv->reset_wq); + cancel_delayed_work(&priv->qos_activate); + cancel_delayed_work(&priv->watch_dog_wq); + cancel_delayed_work(&priv->update_beacon_wq); + cancel_delayed_work(&priv->ieee80211->hw_wakeup_wq); + cancel_delayed_work(&priv->ieee80211->hw_sleep_wq); + + //cancel_delayed_work(&priv->SetBWModeWorkItem); + //cancel_delayed_work(&priv->SwChnlWorkItem); +#endif +#endif + +} + + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) +static void __devexit rtl8192_usb_disconnect(struct usb_interface *intf) +#else +static void __devexit rtl8192_usb_disconnect(struct usb_device *udev, void *ptr) +#endif +{ +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + struct net_device *dev = usb_get_intfdata(intf); +#else + struct net_device *dev = (struct net_device *)ptr; +#endif + + struct r8192_priv *priv = ieee80211_priv(dev); + if(dev){ + + unregister_netdev(dev); + + RT_TRACE(COMP_DOWN, "=============>wlan driver to be removed\n"); + rtl8192_proc_remove_one(dev); + + rtl8192_down(dev); + if (priv->pFirmware) + { + vfree(priv->pFirmware); + priv->pFirmware = NULL; + } + // priv->rf_close(dev); +// rtl8192_SetRFPowerState(dev, eRfOff); +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) + destroy_workqueue(priv->priv_wq); +#endif + //rtl8192_irq_disable(dev); + //rtl8192_reset(dev); + mdelay(10); + + } + free_ieee80211(dev); + RT_TRACE(COMP_DOWN, "wlan driver removed\n"); +} + +static int __init rtl8192_usb_module_init(void) +{ + printk(KERN_INFO "\nLinux kernel driver for RTL8192 based WLAN cards\n"); + printk(KERN_INFO "Copyright (c) 2007-2008, Realsil Wlan\n"); + RT_TRACE(COMP_INIT, "Initializing module"); + RT_TRACE(COMP_INIT, "Wireless extensions version %d", WIRELESS_EXT); + rtl8192_proc_module_init(); + return usb_register(&rtl8192_usb_driver); +} + + +static void __exit rtl8192_usb_module_exit(void) +{ + usb_deregister(&rtl8192_usb_driver); + + RT_TRACE(COMP_DOWN, "Exiting"); + rtl8192_proc_module_remove(); +} + + +void rtl8192_try_wake_queue(struct net_device *dev, int pri) +{ + unsigned long flags; + short enough_desc; + struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + + spin_lock_irqsave(&priv->tx_lock,flags); + enough_desc = check_nic_enough_desc(dev,pri); + spin_unlock_irqrestore(&priv->tx_lock,flags); + + if(enough_desc) + ieee80211_wake_queue(priv->ieee80211); +} + +#if 0 +void DisableHWSecurityConfig8192SUsb(struct net_device *dev) +{ + u8 SECR_value = 0x0; + write_nic_byte(dev, SECR, SECR_value);//SECR_value | SCR_UseDK ); +} +#endif + +void EnableHWSecurityConfig8192(struct net_device *dev) +{ + u8 SECR_value = 0x0; + struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev); + struct ieee80211_device* ieee = priv->ieee80211; + + SECR_value = SCR_TxEncEnable | SCR_RxDecEnable; +#if 1 + if (((KEY_TYPE_WEP40 == ieee->pairwise_key_type) || (KEY_TYPE_WEP104 == ieee->pairwise_key_type)) && (priv->ieee80211->auth_mode != 2)) + { + SECR_value |= SCR_RxUseDK; + SECR_value |= SCR_TxUseDK; + } + else if ((ieee->iw_mode == IW_MODE_ADHOC) && (ieee->pairwise_key_type & (KEY_TYPE_CCMP | KEY_TYPE_TKIP))) + { + SECR_value |= SCR_RxUseDK; + SECR_value |= SCR_TxUseDK; + } +#endif + //add HWSec active enable here. +//default using hwsec. when peer AP is in N mode only and pairwise_key_type is none_aes(which HT_IOT_ACT_PURE_N_MODE indicates it), use software security. when peer AP is in b,g,n mode mixed and pairwise_key_type is none_aes, use g mode hw security. WB on 2008.7.4 + + ieee->hwsec_active = 1; + + if ((ieee->pHTInfo->IOTAction&HT_IOT_ACT_PURE_N_MODE) || !hwwep)//!ieee->hwsec_support) //add hwsec_support flag to totol control hw_sec on/off + { + ieee->hwsec_active = 0; + SECR_value &= ~SCR_RxDecEnable; + } + + RT_TRACE(COMP_SEC,"%s:, hwsec:%d, pairwise_key:%d, SECR_value:%x\n", __FUNCTION__, \ + ieee->hwsec_active, ieee->pairwise_key_type, SECR_value); + { + write_nic_byte(dev, SECR, SECR_value);//SECR_value | SCR_UseDK ); + } +} + + +void setKey( struct net_device *dev, + u8 EntryNo, + u8 KeyIndex, + u16 KeyType, + u8 *MacAddr, + u8 DefaultKey, + u32 *KeyContent ) +{ + u32 TargetCommand = 0; + u32 TargetContent = 0; + u16 usConfig = 0; + u8 i; + if (EntryNo >= TOTAL_CAM_ENTRY) + RT_TRACE(COMP_ERR, "cam entry exceeds in setKey()\n"); + + RT_TRACE(COMP_SEC, "====>to setKey(), dev:%p, EntryNo:%d, KeyIndex:%d, KeyType:%d, MacAddr"MAC_FMT"\n", dev,EntryNo, KeyIndex, KeyType, MAC_ARG(MacAddr)); + + if (DefaultKey) + usConfig |= BIT15 | (KeyType<<2); + else + usConfig |= BIT15 | (KeyType<<2) | KeyIndex; +// usConfig |= BIT15 | (KeyType<<2) | (DefaultKey<<5) | KeyIndex; + + + for(i=0 ; i<CAM_CONTENT_COUNT; i++){ + TargetCommand = i+CAM_CONTENT_COUNT*EntryNo; + TargetCommand |= BIT31|BIT16; + + if(i==0){//MAC|Config + TargetContent = (u32)(*(MacAddr+0)) << 16| + (u32)(*(MacAddr+1)) << 24| + (u32)usConfig; + + write_nic_dword(dev, WCAMI, TargetContent); + write_nic_dword(dev, RWCAM, TargetCommand); + // printk("setkey cam =%8x\n", read_cam(dev, i+6*EntryNo)); + } + else if(i==1){//MAC + TargetContent = (u32)(*(MacAddr+2)) | + (u32)(*(MacAddr+3)) << 8| + (u32)(*(MacAddr+4)) << 16| + (u32)(*(MacAddr+5)) << 24; + write_nic_dword(dev, WCAMI, TargetContent); + write_nic_dword(dev, RWCAM, TargetCommand); + } + else { + //Key Material + if(KeyContent !=NULL){ + write_nic_dword(dev, WCAMI, (u32)(*(KeyContent+i-2)) ); + write_nic_dword(dev, RWCAM, TargetCommand); + } + } + } + +} + +/*************************************************************************** + ------------------- module init / exit stubs ---------------- +****************************************************************************/ +module_init(rtl8192_usb_module_init); +module_exit(rtl8192_usb_module_exit); diff --git a/drivers/staging/rtl8192su/r8192U_dm.c b/drivers/staging/rtl8192su/r8192U_dm.c new file mode 100644 index 000000000000..304274b886ea --- /dev/null +++ b/drivers/staging/rtl8192su/r8192U_dm.c @@ -0,0 +1,4521 @@ +/*++ +Copyright-c Realtek Semiconductor Corp. All rights reserved. + +Module Name: + r8192U_dm.c + +Abstract: + HW dynamic mechanism. + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2008-05-14 amy create version 0 porting from windows code. + +--*/ + + +#ifdef RTL8192SU +#include "r8192U.h" +#include "r8192U_dm.h" +//#include "r8190_rtl8256.h" +#include "r819xU_cmdpkt.h" +#include "r8192S_hw.h" +#include "r8192S_phy.h" +#include "r8192S_phyreg.h" +#else +#include "r8192U.h" +#include "r8192U_dm.h" +#include "r8192U_hw.h" +#include "r819xU_phy.h" +#include "r819xU_phyreg.h" +#include "r8190_rtl8256.h" +#include "r819xU_cmdpkt.h" +#endif + +/*---------------------------Define Local Constant---------------------------*/ +// +// Indicate different AP vendor for IOT issue. +// +#if 0 +typedef enum _HT_IOT_PEER +{ + HT_IOT_PEER_UNKNOWN = 0, + HT_IOT_PEER_REALTEK = 1, + HT_IOT_PEER_BROADCOM = 2, + HT_IOT_PEER_RALINK = 3, + HT_IOT_PEER_ATHEROS = 4, + HT_IOT_PEER_CISCO = 5, + HT_IOT_PEER_MAX = 6 +}HT_IOT_PEER_E, *PHTIOT_PEER_E; +#endif +#if 1 +#ifdef RTL8192SU + static u32 edca_setting_DL[HT_IOT_PEER_MAX] = + // UNKNOWN REALTEK_90 /*REALTEK_92SE*/ BROADCOM RALINK ATHEROS CISCO MARVELL 92U_AP SELF_AP + { 0xa44f, 0x5ea44f, 0x5ea44f, 0xa44f, 0xa44f, 0xa44f, 0xa630, 0xa42b, 0x5e4322, 0x5e4322}; + static u32 edca_setting_UL[HT_IOT_PEER_MAX] = + // UNKNOWN REALTEK /*REALTEK_92SE*/ BROADCOM RALINK ATHEROS CISCO MARVELL 92U_AP SELF_AP + { 0x5ea44f, 0xa44f, 0x5ea44f, 0x5e4322, 0x5ea422, 0x5e4322, 0x3ea44f, 0x5ea42b, 0x5e4322, 0x5e4322}; + +#else + +static u32 edca_setting_DL[HT_IOT_PEER_MAX] = + { 0x5e4322, 0x5e4322, 0x5ea44f, 0x5e4322, 0x604322, 0xa44f, 0x5ea44f}; +static u32 edca_setting_UL[HT_IOT_PEER_MAX] = + { 0x5e4322, 0xa44f, 0x5ea44f, 0x5e4322, 0x604322, 0x5ea44f, 0x5ea44f}; + +#endif +#endif + +#define RTK_UL_EDCA 0xa44f +#define RTK_DL_EDCA 0x5e4322 +/*---------------------------Define Local Constant---------------------------*/ + + +/*------------------------Define global variable-----------------------------*/ +// Debug variable ? +dig_t dm_digtable; +// Store current shoftware write register content for MAC PHY. +u8 dm_shadow[16][256] = {{0}}; +// For Dynamic Rx Path Selection by Signal Strength +DRxPathSel DM_RxPathSelTable; +/*------------------------Define global variable-----------------------------*/ + + +/*------------------------Define local variable------------------------------*/ +/*------------------------Define local variable------------------------------*/ + + +/*--------------------Define export function prototype-----------------------*/ +#ifdef TO_DO_LIST +static void dm_CheckProtection(struct net_device *dev); +#endif +extern void init_hal_dm(struct net_device *dev); +extern void deinit_hal_dm(struct net_device *dev); + +extern void hal_dm_watchdog(struct net_device *dev); + + +extern void init_rate_adaptive(struct net_device *dev); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) +extern void dm_txpower_trackingcallback(struct work_struct *work); +#else +extern void dm_txpower_trackingcallback(struct net_device *dev); +#endif + +extern void dm_cck_txpower_adjust(struct net_device *dev,bool binch14); +extern void dm_restore_dynamic_mechanism_state(struct net_device *dev); +extern void dm_backup_dynamic_mechanism_state(struct net_device *dev); +extern void dm_change_dynamic_initgain_thresh(struct net_device *dev, + u32 dm_type, + u32 dm_value); +extern void DM_ChangeFsyncSetting(struct net_device *dev, + s32 DM_Type, + s32 DM_Value); +extern void dm_force_tx_fw_info(struct net_device *dev, + u32 force_type, + u32 force_value); +extern void dm_init_edca_turbo(struct net_device *dev); +extern void dm_rf_operation_test_callback(unsigned long data); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) +extern void dm_rf_pathcheck_workitemcallback(struct work_struct *work); +#else +extern void dm_rf_pathcheck_workitemcallback(struct net_device *dev); +#endif +extern void dm_fsync_timer_callback(unsigned long data); +#if 0 +extern bool dm_check_lbus_status(struct net_device *dev); +#endif +extern void dm_check_fsync(struct net_device *dev); +extern void dm_shadow_init(struct net_device *dev); + + +/*--------------------Define export function prototype-----------------------*/ + + +/*---------------------Define local function prototype-----------------------*/ +// DM --> Rate Adaptive +static void dm_check_rate_adaptive(struct net_device *dev); + +// DM --> Bandwidth switch +static void dm_init_bandwidth_autoswitch(struct net_device *dev); +static void dm_bandwidth_autoswitch( struct net_device *dev); + +// DM --> TX power control +//static void dm_initialize_txpower_tracking(struct net_device *dev); + +static void dm_check_txpower_tracking(struct net_device *dev); + + + +//static void dm_txpower_reset_recovery(struct net_device *dev); + + +// DM --> BB init gain restore +#ifndef RTL8192U +static void dm_bb_initialgain_restore(struct net_device *dev); + + +// DM --> BB init gain backup +static void dm_bb_initialgain_backup(struct net_device *dev); +#endif +// DM --> Dynamic Init Gain by RSSI +static void dm_dig_init(struct net_device *dev); +static void dm_ctrl_initgain_byrssi(struct net_device *dev); +static void dm_ctrl_initgain_byrssi_highpwr(struct net_device *dev); +static void dm_ctrl_initgain_byrssi_by_driverrssi( struct net_device *dev); +static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(struct net_device *dev); +static void dm_initial_gain(struct net_device *dev); +static void dm_pd_th(struct net_device *dev); +static void dm_cs_ratio(struct net_device *dev); + +static void dm_init_ctstoself(struct net_device *dev); +// DM --> EDCA turboe mode control +static void dm_check_edca_turbo(struct net_device *dev); + +// DM --> HW RF control +static void dm_check_rfctrl_gpio(struct net_device *dev); + +#ifndef RTL8190P +//static void dm_gpio_change_rf(struct net_device *dev); +#endif +// DM --> Check PBC +static void dm_check_pbc_gpio(struct net_device *dev); + + +// DM --> Check current RX RF path state +static void dm_check_rx_path_selection(struct net_device *dev); +static void dm_init_rxpath_selection(struct net_device *dev); +static void dm_rxpath_sel_byrssi(struct net_device *dev); + + +// DM --> Fsync for broadcom ap +static void dm_init_fsync(struct net_device *dev); +static void dm_deInit_fsync(struct net_device *dev); + +//Added by vivi, 20080522 +static void dm_check_txrateandretrycount(struct net_device *dev); + +/*---------------------Define local function prototype-----------------------*/ + +/*---------------------Define of Tx Power Control For Near/Far Range --------*/ //Add by Jacken 2008/02/18 +static void dm_init_dynamic_txpower(struct net_device *dev); +static void dm_dynamic_txpower(struct net_device *dev); + + +// DM --> For rate adaptive and DIG, we must send RSSI to firmware +static void dm_send_rssi_tofw(struct net_device *dev); +static void dm_ctstoself(struct net_device *dev); +/*---------------------------Define function prototype------------------------*/ +//================================================================================ +// HW Dynamic mechanism interface. +//================================================================================ +#ifdef RTL8192SU +static void dm_CheckAggrPolicy(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo; + //u8 QueueId; + //PRT_TCB pTcb; + bool bAmsduEnable = false; + + static u8 lastTxOkCnt = 0; + static u8 lastRxOkCnt = 0; + u8 curTxOkCnt = 0; + u8 curRxOkCnt = 0; + + // Determine if A-MSDU policy. + if(priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_HYBRID_AGGREGATION) + { + if(read_nic_byte(dev, INIMCS_SEL) > DESC92S_RATE54M) + bAmsduEnable = true; + } + else if(priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_AMSDU_ENABLE) + { + if(read_nic_byte(dev, INIMCS_SEL) > DESC92S_RATE54M) + { + curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt; + curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt; + + if(curRxOkCnt <= 4*curTxOkCnt) + bAmsduEnable = true; + } + } + else + { + // Do not need to switch aggregation policy. + return; + } + + // Switch A-MSDU + if(bAmsduEnable && !pHTInfo->bCurrent_AMSDU_Support) + { + pHTInfo->bCurrent_AMSDU_Support = true; + } + else if(!bAmsduEnable && pHTInfo->bCurrent_AMSDU_Support) + { +#ifdef TO_DO_LIST + //PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK); + for(QueueId = 0; QueueId < MAX_TX_QUEUE; QueueId++) + { + while(!RTIsListEmpty(&dev->TcbAggrQueue[QueueId])) + { + pTcb = (PRT_TCB)RTRemoveHeadList(&dev->TcbAggrQueue[QueueId]); + dev->TcbCountInAggrQueue[QueueId]--; + PreTransmitTCB(dev, pTcb); + } + } + //PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK); + pHTInfo->bCurrent_AMSDU_Support = false; +#endif + } + + // Determine A-MPDU policy + if(priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_AMSDU_ENABLE) + { + if(!bAmsduEnable) + pHTInfo->bCurrentAMPDUEnable = true; + } + + // Update local static variables. + lastTxOkCnt = priv->stats.txbytesunicast; + lastRxOkCnt = priv->stats.rxbytesunicast; +} +#endif +// +// Description: +// Prepare SW resource for HW dynamic mechanism. +// +// Assumption: +// This function is only invoked at driver intialization once. +// +// +extern void +init_hal_dm(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + + // Undecorated Smoothed Signal Strength, it can utilized to dynamic mechanism. + priv->undecorated_smoothed_pwdb = -1; + + //Initial TX Power Control for near/far range , add by amy 2008/05/15, porting from windows code. + dm_init_dynamic_txpower(dev); + init_rate_adaptive(dev); +#ifdef RTL8192SU + dm_initialize_txpower_tracking(dev); +#else + //dm_initialize_txpower_tracking(dev); +#endif + dm_dig_init(dev); + dm_init_edca_turbo(dev); + dm_init_bandwidth_autoswitch(dev); + dm_init_fsync(dev); + dm_init_rxpath_selection(dev); + dm_init_ctstoself(dev); + +} // InitHalDm + +extern void deinit_hal_dm(struct net_device *dev) +{ + + dm_deInit_fsync(dev); + +} + + +#ifdef USB_RX_AGGREGATION_SUPPORT +void dm_CheckRxAggregation(struct net_device *dev) { + struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev); + PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo; + static unsigned long lastTxOkCnt = 0; + static unsigned long lastRxOkCnt = 0; + unsigned long curTxOkCnt = 0; + unsigned long curRxOkCnt = 0; + +/* + if (pHalData->bForcedUsbRxAggr) { + if (pHalData->ForcedUsbRxAggrInfo == 0) { + if (pHalData->bCurrentRxAggrEnable) { + Adapter->HalFunc.HalUsbRxAggrHandler(Adapter, FALSE); + } + } else { + if (!pHalData->bCurrentRxAggrEnable || (pHalData->ForcedUsbRxAggrInfo != pHalData->LastUsbRxAggrInfoSetting)) { + Adapter->HalFunc.HalUsbRxAggrHandler(Adapter, TRUE); + } + } + return; + } + +*/ +#ifdef RTL8192SU + if (priv->bForcedUsbRxAggr) { + if (priv->ForcedUsbRxAggrInfo == 0) { + if (priv->bCurrentRxAggrEnable) { + //Adapter->HalFunc.HalUsbRxAggrHandler(Adapter, FALSE); + write_nic_dword(dev, 0x1a8, 0); + priv->bCurrentRxAggrEnable = false; + } + } else { + if (!priv->bCurrentRxAggrEnable || (priv->ForcedUsbRxAggrInfo != priv->LastUsbRxAggrInfoSetting)) { + u32 ulValue; + ulValue = (pHTInfo->UsbRxFwAggrEn<<24) | (pHTInfo->UsbRxFwAggrPageNum<<16) | + (pHTInfo->UsbRxFwAggrPacketNum<<8) | (pHTInfo->UsbRxFwAggrTimeout); + /* + * If usb rx firmware aggregation is enabled, + * when anyone of three threshold conditions above is reached, + * firmware will send aggregated packet to driver. + */ + write_nic_dword(dev, 0x1a8, ulValue); + priv->bCurrentRxAggrEnable = true; + } + } + return; + } + + if((priv->ieee80211->mode & WIRELESS_MODE_B) || (priv->ieee80211->mode & WIRELESS_MODE_G)) + { + if (priv->bCurrentRxAggrEnable) + { + RT_TRACE(COMP_RECV, "dm_CheckRxAggregation() : Disable Rx Aggregation!!\n"); + write_nic_dword(dev, 0x1a8, 0); + priv->bCurrentRxAggrEnable = false; + return; + } + } +#endif + + curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt; + curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt; + + if((curTxOkCnt + curRxOkCnt) < 15000000) { + return; + } + + if(curTxOkCnt > 4*curRxOkCnt) { + if (priv->bCurrentRxAggrEnable) { + write_nic_dword(dev, 0x1a8, 0); + priv->bCurrentRxAggrEnable = false; + } + }else{ + if (!priv->bCurrentRxAggrEnable && !pHTInfo->bCurrentRT2RTAggregation) { + u32 ulValue; + ulValue = (pHTInfo->UsbRxFwAggrEn<<24) | (pHTInfo->UsbRxFwAggrPageNum<<16) | + (pHTInfo->UsbRxFwAggrPacketNum<<8) | (pHTInfo->UsbRxFwAggrTimeout); + /* + * If usb rx firmware aggregation is enabled, + * when anyone of three threshold conditions above is reached, + * firmware will send aggregated packet to driver. + */ + write_nic_dword(dev, 0x1a8, ulValue); + priv->bCurrentRxAggrEnable = true; + } + } + + lastTxOkCnt = priv->stats.txbytesunicast; + lastRxOkCnt = priv->stats.rxbytesunicast; +} // dm_CheckEdcaTurbo +#endif + + +#ifdef RTL8192SU +//#if 0 +extern void hal_dm_watchdog(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + + if(priv->bInHctTest) + return; + + + dm_check_rfctrl_gpio(dev); + + // Add by hpfan 2008-03-11 + dm_check_pbc_gpio(dev); + dm_check_txrateandretrycount(dev); //moved by tynli + dm_check_edca_turbo(dev); + + dm_CheckAggrPolicy(dev); + +#ifdef TO_DO_LIST + dm_CheckProtection(dev); +#endif + + // ==================================================== + // If any dynamic mechanism is ready, put it above this return; + // ==================================================== + //if (IS_HARDWARE_TYPE_8192S(dev)) + return; + +#ifdef USB_RX_AGGREGATION_SUPPORT + dm_CheckRxAggregation(dev); +#endif +#ifdef TO_DO_LIST + if(Adapter->MgntInfo.mActingAsAp) + { + AP_dm_CheckRateAdaptive(dev); + //return; + } + else +#endif + { + dm_check_rate_adaptive(dev); + } + dm_dynamic_txpower(dev); + + dm_check_txpower_tracking(dev); + dm_ctrl_initgain_byrssi(dev);//LZM TMP 090302 + + dm_bandwidth_autoswitch(dev); + + dm_check_rx_path_selection(dev);//LZM TMP 090302 + dm_check_fsync(dev); + + dm_send_rssi_tofw(dev); + + dm_ctstoself(dev); + +} //HalDmWatchDog +#else +extern void hal_dm_watchdog(struct net_device *dev) +{ + //struct r8192_priv *priv = ieee80211_priv(dev); + + //static u8 previous_bssid[6] ={0}; + + /*Add by amy 2008/05/15 ,porting from windows code.*/ + dm_check_rate_adaptive(dev); + dm_dynamic_txpower(dev); + dm_check_txrateandretrycount(dev); + dm_check_txpower_tracking(dev); + dm_ctrl_initgain_byrssi(dev); + dm_check_edca_turbo(dev); + dm_bandwidth_autoswitch(dev); + dm_check_rfctrl_gpio(dev); + dm_check_rx_path_selection(dev); + dm_check_fsync(dev); + + // Add by amy 2008-05-15 porting from windows code. + dm_check_pbc_gpio(dev); + dm_send_rssi_tofw(dev); + dm_ctstoself(dev); +#ifdef USB_RX_AGGREGATION_SUPPORT + dm_CheckRxAggregation(dev); +#endif +} //HalDmWatchDog +#endif + +/* + * Decide Rate Adaptive Set according to distance (signal strength) + * 01/11/2008 MHC Modify input arguments and RATR table level. + * 01/16/2008 MHC RF_Type is assigned in ReadAdapterInfo(). We must call + * the function after making sure RF_Type. + */ +extern void init_rate_adaptive(struct net_device * dev) +{ + + struct r8192_priv *priv = ieee80211_priv(dev); + prate_adaptive pra = (prate_adaptive)&priv->rate_adaptive; + + pra->ratr_state = DM_RATR_STA_MAX; + pra->high2low_rssi_thresh_for_ra = RateAdaptiveTH_High; + pra->low2high_rssi_thresh_for_ra20M = RateAdaptiveTH_Low_20M+5; + pra->low2high_rssi_thresh_for_ra40M = RateAdaptiveTH_Low_40M+5; + + pra->high_rssi_thresh_for_ra = RateAdaptiveTH_High+5; + pra->low_rssi_thresh_for_ra20M = RateAdaptiveTH_Low_20M; + pra->low_rssi_thresh_for_ra40M = RateAdaptiveTH_Low_40M; + + if(priv->CustomerID == RT_CID_819x_Netcore) + pra->ping_rssi_enable = 1; + else + pra->ping_rssi_enable = 0; + pra->ping_rssi_thresh_for_ra = 15; + + + if (priv->rf_type == RF_2T4R) + { + // 07/10/08 MH Modify for RA smooth scheme. + /* 2008/01/11 MH Modify 2T RATR table for different RSSI. 080515 porting by amy from windows code.*/ + pra->upper_rssi_threshold_ratr = 0x8f0f0000; + pra->middle_rssi_threshold_ratr = 0x8f0ff000; + pra->low_rssi_threshold_ratr = 0x8f0ff001; + pra->low_rssi_threshold_ratr_40M = 0x8f0ff005; + pra->low_rssi_threshold_ratr_20M = 0x8f0ff001; + pra->ping_rssi_ratr = 0x0000000d;//cosa add for test + } + else if (priv->rf_type == RF_1T2R) + { + pra->upper_rssi_threshold_ratr = 0x000f0000; + pra->middle_rssi_threshold_ratr = 0x000ff000; + pra->low_rssi_threshold_ratr = 0x000ff001; + pra->low_rssi_threshold_ratr_40M = 0x000ff005; + pra->low_rssi_threshold_ratr_20M = 0x000ff001; + pra->ping_rssi_ratr = 0x0000000d;//cosa add for test + } + +} // InitRateAdaptive + + +/*----------------------------------------------------------------------------- + * Function: dm_check_rate_adaptive() + * + * Overview: + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 05/26/08 amy Create version 0 proting from windows code. + * + *---------------------------------------------------------------------------*/ +static void dm_check_rate_adaptive(struct net_device * dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo; + prate_adaptive pra = (prate_adaptive)&priv->rate_adaptive; + u32 currentRATR, targetRATR = 0; + u32 LowRSSIThreshForRA = 0, HighRSSIThreshForRA = 0; + bool bshort_gi_enabled = false; + static u8 ping_rssi_state=0; + + + if(!priv->up) + { + RT_TRACE(COMP_RATE, "<---- dm_check_rate_adaptive(): driver is going to unload\n"); + return; + } + + if(pra->rate_adaptive_disabled)//this variable is set by ioctl. + return; + + // TODO: Only 11n mode is implemented currently, + if( !(priv->ieee80211->mode == WIRELESS_MODE_N_24G || + priv->ieee80211->mode == WIRELESS_MODE_N_5G)) + return; + + if( priv->ieee80211->state == IEEE80211_LINKED ) + { + // RT_TRACE(COMP_RATE, "dm_CheckRateAdaptive(): \t"); + + // + // Check whether Short GI is enabled + // + bshort_gi_enabled = (pHTInfo->bCurTxBW40MHz && pHTInfo->bCurShortGI40MHz) || + (!pHTInfo->bCurTxBW40MHz && pHTInfo->bCurShortGI20MHz); + + + pra->upper_rssi_threshold_ratr = + (pra->upper_rssi_threshold_ratr & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ; + + pra->middle_rssi_threshold_ratr = + (pra->middle_rssi_threshold_ratr & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ; + + if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) + { + pra->low_rssi_threshold_ratr = + (pra->low_rssi_threshold_ratr_40M & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ; + } + else + { + pra->low_rssi_threshold_ratr = + (pra->low_rssi_threshold_ratr_20M & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ; + } + //cosa add for test + pra->ping_rssi_ratr = + (pra->ping_rssi_ratr & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ; + + /* 2007/10/08 MH We support RA smooth scheme now. When it is the first + time to link with AP. We will not change upper/lower threshold. If + STA stay in high or low level, we must change two different threshold + to prevent jumping frequently. */ + if (pra->ratr_state == DM_RATR_STA_HIGH) + { + HighRSSIThreshForRA = pra->high2low_rssi_thresh_for_ra; + LowRSSIThreshForRA = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)? + (pra->low_rssi_thresh_for_ra40M):(pra->low_rssi_thresh_for_ra20M); + } + else if (pra->ratr_state == DM_RATR_STA_LOW) + { + HighRSSIThreshForRA = pra->high_rssi_thresh_for_ra; + LowRSSIThreshForRA = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)? + (pra->low2high_rssi_thresh_for_ra40M):(pra->low2high_rssi_thresh_for_ra20M); + } + else + { + HighRSSIThreshForRA = pra->high_rssi_thresh_for_ra; + LowRSSIThreshForRA = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)? + (pra->low_rssi_thresh_for_ra40M):(pra->low_rssi_thresh_for_ra20M); + } + + //DbgPrint("[DM] THresh H/L=%d/%d\n\r", RATR.HighRSSIThreshForRA, RATR.LowRSSIThreshForRA); + if(priv->undecorated_smoothed_pwdb >= (long)HighRSSIThreshForRA) + { + //DbgPrint("[DM] RSSI=%d STA=HIGH\n\r", pHalData->UndecoratedSmoothedPWDB); + pra->ratr_state = DM_RATR_STA_HIGH; + targetRATR = pra->upper_rssi_threshold_ratr; + }else if(priv->undecorated_smoothed_pwdb >= (long)LowRSSIThreshForRA) + { + //DbgPrint("[DM] RSSI=%d STA=Middle\n\r", pHalData->UndecoratedSmoothedPWDB); + pra->ratr_state = DM_RATR_STA_MIDDLE; + targetRATR = pra->middle_rssi_threshold_ratr; + }else + { + //DbgPrint("[DM] RSSI=%d STA=LOW\n\r", pHalData->UndecoratedSmoothedPWDB); + pra->ratr_state = DM_RATR_STA_LOW; + targetRATR = pra->low_rssi_threshold_ratr; + } + + //cosa add for test + if(pra->ping_rssi_enable) + { + //pHalData->UndecoratedSmoothedPWDB = 19; + if(priv->undecorated_smoothed_pwdb < (long)(pra->ping_rssi_thresh_for_ra+5)) + { + if( (priv->undecorated_smoothed_pwdb < (long)pra->ping_rssi_thresh_for_ra) || + ping_rssi_state ) + { + //DbgPrint("TestRSSI = %d, set RATR to 0x%x \n", pHalData->UndecoratedSmoothedPWDB, pRA->TestRSSIRATR); + pra->ratr_state = DM_RATR_STA_LOW; + targetRATR = pra->ping_rssi_ratr; + ping_rssi_state = 1; + } + //else + // DbgPrint("TestRSSI is between the range. \n"); + } + else + { + //DbgPrint("TestRSSI Recover to 0x%x \n", targetRATR); + ping_rssi_state = 0; + } + } + + // 2008.04.01 +#if 1 + // For RTL819X, if pairwisekey = wep/tkip, we support only MCS0~7. + if(priv->ieee80211->GetHalfNmodeSupportByAPsHandler(dev)) + targetRATR &= 0xf00fffff; +#endif + + // + // Check whether updating of RATR0 is required + // + currentRATR = read_nic_dword(dev, RATR0); + if( targetRATR != currentRATR ) + { + u32 ratr_value; + ratr_value = targetRATR; + RT_TRACE(COMP_RATE,"currentRATR = %x, targetRATR = %x\n", currentRATR, targetRATR); + if(priv->rf_type == RF_1T2R) + { + ratr_value &= ~(RATE_ALL_OFDM_2SS); + } + write_nic_dword(dev, RATR0, ratr_value); + write_nic_byte(dev, UFWP, 1); + + pra->last_ratr = targetRATR; + } + + } + else + { + pra->ratr_state = DM_RATR_STA_MAX; + } + +} // dm_CheckRateAdaptive + + +static void dm_init_bandwidth_autoswitch(struct net_device * dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + + priv->ieee80211->bandwidth_auto_switch.threshold_20Mhzto40Mhz = BW_AUTO_SWITCH_LOW_HIGH; + priv->ieee80211->bandwidth_auto_switch.threshold_40Mhzto20Mhz = BW_AUTO_SWITCH_HIGH_LOW; + priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz = false; + priv->ieee80211->bandwidth_auto_switch.bautoswitch_enable = false; + +} // dm_init_bandwidth_autoswitch + + +static void dm_bandwidth_autoswitch(struct net_device * dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + + if(priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20 ||!priv->ieee80211->bandwidth_auto_switch.bautoswitch_enable){ + return; + }else{ + if(priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz == false){//If send packets in 40 Mhz in 20/40 + if(priv->undecorated_smoothed_pwdb <= priv->ieee80211->bandwidth_auto_switch.threshold_40Mhzto20Mhz) + priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz = true; + }else{//in force send packets in 20 Mhz in 20/40 + if(priv->undecorated_smoothed_pwdb >= priv->ieee80211->bandwidth_auto_switch.threshold_20Mhzto40Mhz) + priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz = false; + + } + } +} // dm_BandwidthAutoSwitch + +//OFDM default at 0db, index=6. +static u32 OFDMSwingTable[OFDM_Table_Length] = { + 0x7f8001fe, // 0, +6db + 0x71c001c7, // 1, +5db + 0x65400195, // 2, +4db + 0x5a400169, // 3, +3db + 0x50800142, // 4, +2db + 0x47c0011f, // 5, +1db + 0x40000100, // 6, +0db ===> default, upper for higher temprature, lower for low temprature + 0x390000e4, // 7, -1db + 0x32c000cb, // 8, -2db + 0x2d4000b5, // 9, -3db + 0x288000a2, // 10, -4db + 0x24000090, // 11, -5db + 0x20000080, // 12, -6db + 0x1c800072, // 13, -7db + 0x19800066, // 14, -8db + 0x26c0005b, // 15, -9db + 0x24400051, // 16, -10db + 0x12000048, // 17, -11db + 0x10000040 // 18, -12db +}; + +static u8 CCKSwingTable_Ch1_Ch13[CCK_Table_length][8] = { + {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, // 0, +0db ===> CCK40M default + {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, // 1, -1db + {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, // 2, -2db + {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, // 3, -3db + {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, // 4, -4db + {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, // 5, -5db + {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, // 6, -6db ===> CCK20M default + {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, // 7, -7db + {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, // 8, -8db + {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, // 9, -9db + {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 10, -10db + {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01} // 11, -11db +}; + +static u8 CCKSwingTable_Ch14[CCK_Table_length][8] = { + {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, // 0, +0db ===> CCK40M default + {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, // 1, -1db + {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, // 2, -2db + {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, // 3, -3db + {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, // 4, -4db + {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, // 5, -5db + {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 6, -6db ===> CCK20M default + {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, // 7, -7db + {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 8, -8db + {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 9, -9db + {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 10, -10db + {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00} // 11, -11db +}; + +static void dm_TXPowerTrackingCallback_TSSI(struct net_device * dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + bool bHighpowerstate, viviflag = FALSE; + DCMD_TXCMD_T tx_cmd; + u8 powerlevelOFDM24G; + int i =0, j = 0, k = 0; + u8 RF_Type, tmp_report[5]={0, 0, 0, 0, 0}; + u32 Value; + u8 Pwr_Flag; + u16 Avg_TSSI_Meas, TSSI_13dBm, Avg_TSSI_Meas_from_driver=0; + //RT_STATUS rtStatus = RT_STATUS_SUCCESS; +#ifdef RTL8192U + bool rtStatus = true; +#endif + u32 delta=0; + + write_nic_byte(dev, 0x1ba, 0); + + priv->ieee80211->bdynamic_txpower_enable = false; + bHighpowerstate = priv->bDynamicTxHighPower; + + powerlevelOFDM24G = (u8)(priv->Pwr_Track>>24); + RF_Type = priv->rf_type; + Value = (RF_Type<<8) | powerlevelOFDM24G; + + RT_TRACE(COMP_POWER_TRACKING, "powerlevelOFDM24G = %x\n", powerlevelOFDM24G); + + for(j = 0; j<=30; j++) +{ //fill tx_cmd + + tx_cmd.Op = TXCMD_SET_TX_PWR_TRACKING; + tx_cmd.Length = 4; + tx_cmd.Value = Value; +#ifdef RTL8192U + rtStatus = SendTxCommandPacket(dev, &tx_cmd, 12); + if (rtStatus == false) + { + RT_TRACE(COMP_POWER_TRACKING, "Set configuration with tx cmd queue fail!\n"); + } +#else + cmpk_message_handle_tx(dev, (u8*)&tx_cmd, + DESC_PACKET_TYPE_INIT, sizeof(DCMD_TXCMD_T)); +#endif + mdelay(1); + //DbgPrint("hi, vivi, strange\n"); + for(i = 0;i <= 30; i++) + { + Pwr_Flag = read_nic_byte(dev, 0x1ba); + + if (Pwr_Flag == 0) + { + mdelay(1); + continue; + } +#ifdef RTL8190P + Avg_TSSI_Meas = read_nic_word(dev, 0x1bc); +#else + Avg_TSSI_Meas = read_nic_word(dev, 0x13c); +#endif + if(Avg_TSSI_Meas == 0) + { + write_nic_byte(dev, 0x1ba, 0); + break; + } + + for(k = 0;k < 5; k++) + { +#ifdef RTL8190P + tmp_report[k] = read_nic_byte(dev, 0x1d8+k); +#else + if(k !=4) + tmp_report[k] = read_nic_byte(dev, 0x134+k); + else + tmp_report[k] = read_nic_byte(dev, 0x13e); +#endif + RT_TRACE(COMP_POWER_TRACKING, "TSSI_report_value = %d\n", tmp_report[k]); + } + + //check if the report value is right + for(k = 0;k < 5; k++) + { + if(tmp_report[k] <= 20) + { + viviflag =TRUE; + break; + } + } + if(viviflag ==TRUE) + { + write_nic_byte(dev, 0x1ba, 0); + viviflag = FALSE; + RT_TRACE(COMP_POWER_TRACKING, "we filted this data\n"); + for(k = 0;k < 5; k++) + tmp_report[k] = 0; + break; + } + + for(k = 0;k < 5; k++) + { + Avg_TSSI_Meas_from_driver += tmp_report[k]; + } + + Avg_TSSI_Meas_from_driver = Avg_TSSI_Meas_from_driver*100/5; + RT_TRACE(COMP_POWER_TRACKING, "Avg_TSSI_Meas_from_driver = %d\n", Avg_TSSI_Meas_from_driver); + TSSI_13dBm = priv->TSSI_13dBm; + RT_TRACE(COMP_POWER_TRACKING, "TSSI_13dBm = %d\n", TSSI_13dBm); + + //if(abs(Avg_TSSI_Meas_from_driver - TSSI_13dBm) <= E_FOR_TX_POWER_TRACK) + // For MacOS-compatible + if(Avg_TSSI_Meas_from_driver > TSSI_13dBm) + delta = Avg_TSSI_Meas_from_driver - TSSI_13dBm; + else + delta = TSSI_13dBm - Avg_TSSI_Meas_from_driver; + + if(delta <= E_FOR_TX_POWER_TRACK) + { + priv->ieee80211->bdynamic_txpower_enable = TRUE; + write_nic_byte(dev, 0x1ba, 0); + RT_TRACE(COMP_POWER_TRACKING, "tx power track is done\n"); + RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex = %d\n", priv->rfa_txpowertrackingindex); + RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_real = %d\n", priv->rfa_txpowertrackingindex_real); +#ifdef RTL8190P + RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex = %d\n", priv->rfc_txpowertrackingindex); + RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex_real = %d\n", priv->rfc_txpowertrackingindex_real); +#endif + RT_TRACE(COMP_POWER_TRACKING, "priv->cck_present_attentuation_difference = %d\n", priv->cck_present_attentuation_difference); + RT_TRACE(COMP_POWER_TRACKING, "priv->cck_present_attentuation = %d\n", priv->cck_present_attentuation); + return; + } + else + { + if(Avg_TSSI_Meas_from_driver < TSSI_13dBm - E_FOR_TX_POWER_TRACK) + { + if((priv->rfa_txpowertrackingindex > 0) +#ifdef RTL8190P + &&(priv->rfc_txpowertrackingindex > 0) +#endif + ) + { + priv->rfa_txpowertrackingindex--; + if(priv->rfa_txpowertrackingindex_real > 4) + { + priv->rfa_txpowertrackingindex_real--; + rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex_real].txbbgain_value); + } +#ifdef RTL8190P + priv->rfc_txpowertrackingindex--; + if(priv->rfc_txpowertrackingindex_real > 4) + { + priv->rfc_txpowertrackingindex_real--; + rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex_real].txbbgain_value); + } +#endif + } + } + else + { + if((priv->rfa_txpowertrackingindex < 36) +#ifdef RTL8190P + &&(priv->rfc_txpowertrackingindex < 36) +#endif + ) + { + priv->rfa_txpowertrackingindex++; + priv->rfa_txpowertrackingindex_real++; + rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex_real].txbbgain_value); + +#ifdef RTL8190P + priv->rfc_txpowertrackingindex++; + priv->rfc_txpowertrackingindex_real++; + rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex_real].txbbgain_value); +#endif + } + } + priv->cck_present_attentuation_difference + = priv->rfa_txpowertrackingindex - priv->rfa_txpowertracking_default; + + if(priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) + priv->cck_present_attentuation + = priv->cck_present_attentuation_20Mdefault + priv->cck_present_attentuation_difference; + else + priv->cck_present_attentuation + = priv->cck_present_attentuation_40Mdefault + priv->cck_present_attentuation_difference; + + if(priv->cck_present_attentuation > -1&&priv->cck_present_attentuation <23) + { + if(priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14) + { + priv->bcck_in_ch14 = TRUE; + dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); + } + else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14) + { + priv->bcck_in_ch14 = FALSE; + dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); + } + else + dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); + } + RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex = %d\n", priv->rfa_txpowertrackingindex); + RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_real = %d\n", priv->rfa_txpowertrackingindex_real); +#ifdef RTL8190P + RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex = %d\n", priv->rfc_txpowertrackingindex); + RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex_real = %d\n", priv->rfc_txpowertrackingindex_real); +#endif + RT_TRACE(COMP_POWER_TRACKING, "priv->cck_present_attentuation_difference = %d\n", priv->cck_present_attentuation_difference); + RT_TRACE(COMP_POWER_TRACKING, "priv->cck_present_attentuation = %d\n", priv->cck_present_attentuation); + + if (priv->cck_present_attentuation_difference <= -12||priv->cck_present_attentuation_difference >= 24) + { + priv->ieee80211->bdynamic_txpower_enable = TRUE; + write_nic_byte(dev, 0x1ba, 0); + RT_TRACE(COMP_POWER_TRACKING, "tx power track--->limited\n"); + return; + } + + + } + write_nic_byte(dev, 0x1ba, 0); + Avg_TSSI_Meas_from_driver = 0; + for(k = 0;k < 5; k++) + tmp_report[k] = 0; + break; + } +} + priv->ieee80211->bdynamic_txpower_enable = TRUE; + write_nic_byte(dev, 0x1ba, 0); +} + +static void dm_TXPowerTrackingCallback_ThermalMeter(struct net_device * dev) +{ +#define ThermalMeterVal 9 + struct r8192_priv *priv = ieee80211_priv(dev); + u32 tmpRegA, TempCCk; + u8 tmpOFDMindex, tmpCCKindex, tmpCCK20Mindex, tmpCCK40Mindex, tmpval; + int i =0, CCKSwingNeedUpdate=0; + + if(!priv->btxpower_trackingInit) + { + //Query OFDM default setting + tmpRegA= rtl8192_QueryBBReg(dev, rOFDM0_XATxIQImbalance, bMaskDWord); + for(i=0; i<OFDM_Table_Length; i++) //find the index + { + if(tmpRegA == OFDMSwingTable[i]) + { + priv->OFDM_index= (u8)i; + RT_TRACE(COMP_POWER_TRACKING, "Initial reg0x%x = 0x%x, OFDM_index=0x%x\n", + rOFDM0_XATxIQImbalance, tmpRegA, priv->OFDM_index); + } + } + + //Query CCK default setting From 0xa22 + TempCCk = rtl8192_QueryBBReg(dev, rCCK0_TxFilter1, bMaskByte2); + for(i=0 ; i<CCK_Table_length ; i++) + { + if(TempCCk == (u32)CCKSwingTable_Ch1_Ch13[i][0]) + { + priv->CCK_index =(u8) i; + RT_TRACE(COMP_POWER_TRACKING, "Initial reg0x%x = 0x%x, CCK_index=0x%x\n", + rCCK0_TxFilter1, TempCCk, priv->CCK_index); + break; + } + } + priv->btxpower_trackingInit = TRUE; + //pHalData->TXPowercount = 0; + return; + } + + //========================== + // this is only for test, should be masked +#if 0 +{ + //UINT32 eRFPath; + //UINT32 start_rf, end_rf; + UINT32 curr_addr; + //UINT32 reg_addr; + //UINT32 reg_addr_end; + UINT32 reg_value; + //start_rf = RF90_PATH_A; + //end_rf = RF90_PATH_B;//RF90_PATH_MAX; + //reg_addr = 0x0; + //reg_addr_end = 0x2F; + + for (curr_addr = 0; curr_addr < 0x2d; curr_addr++) + { + reg_value = PHY_QueryRFReg( Adapter, (RF90_RADIO_PATH_E)RF90_PATH_A, + curr_addr, bMaskDWord); + } + + pHalData->TXPowercount = 0; + return; +} +#endif + //========================== + + // read and filter out unreasonable value + tmpRegA = rtl8192_phy_QueryRFReg(dev, RF90_PATH_A, 0x12, 0x078); // 0x12: RF Reg[10:7] + RT_TRACE(COMP_POWER_TRACKING, "Readback ThermalMeterA = %d \n", tmpRegA); + if(tmpRegA < 3 || tmpRegA > 13) + return; + if(tmpRegA >= 12) // if over 12, TP will be bad when high temprature + tmpRegA = 12; + RT_TRACE(COMP_POWER_TRACKING, "Valid ThermalMeterA = %d \n", tmpRegA); + priv->ThermalMeter[0] = ThermalMeterVal; //We use fixed value by Bryant's suggestion + priv->ThermalMeter[1] = ThermalMeterVal; //We use fixed value by Bryant's suggestion + + //Get current RF-A temprature index + if(priv->ThermalMeter[0] >= (u8)tmpRegA) //lower temprature + { + tmpOFDMindex = tmpCCK20Mindex = 6+(priv->ThermalMeter[0]-(u8)tmpRegA); + tmpCCK40Mindex = tmpCCK20Mindex - 6; + if(tmpOFDMindex >= OFDM_Table_Length) + tmpOFDMindex = OFDM_Table_Length-1; + if(tmpCCK20Mindex >= CCK_Table_length) + tmpCCK20Mindex = CCK_Table_length-1; + if(tmpCCK40Mindex >= CCK_Table_length) + tmpCCK40Mindex = CCK_Table_length-1; + } + else + { + tmpval = ((u8)tmpRegA - priv->ThermalMeter[0]); + if(tmpval >= 6) // higher temprature + tmpOFDMindex = tmpCCK20Mindex = 0; // max to +6dB + else + tmpOFDMindex = tmpCCK20Mindex = 6 - tmpval; + tmpCCK40Mindex = 0; + } + //DbgPrint("%ddb, tmpOFDMindex = %d, tmpCCK20Mindex = %d, tmpCCK40Mindex = %d", + //((u1Byte)tmpRegA - pHalData->ThermalMeter[0]), + //tmpOFDMindex, tmpCCK20Mindex, tmpCCK40Mindex); + if(priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) //40M + tmpCCKindex = tmpCCK40Mindex; + else + tmpCCKindex = tmpCCK20Mindex; + + if(priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14) + { + priv->bcck_in_ch14 = TRUE; + CCKSwingNeedUpdate = 1; + } + else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14) + { + priv->bcck_in_ch14 = FALSE; + CCKSwingNeedUpdate = 1; + } + + if(priv->CCK_index != tmpCCKindex) + { + priv->CCK_index = tmpCCKindex; + CCKSwingNeedUpdate = 1; + } + + if(CCKSwingNeedUpdate) + { + //DbgPrint("Update CCK Swing, CCK_index = %d\n", pHalData->CCK_index); + dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); + } + if(priv->OFDM_index != tmpOFDMindex) + { + priv->OFDM_index = tmpOFDMindex; + rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable[priv->OFDM_index]); + RT_TRACE(COMP_POWER_TRACKING, "Update OFDMSwing[%d] = 0x%x\n", + priv->OFDM_index, OFDMSwingTable[priv->OFDM_index]); + } + priv->txpower_count = 0; +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) +extern void dm_txpower_trackingcallback(struct work_struct *work) +{ + struct delayed_work *dwork = container_of(work,struct delayed_work,work); + struct r8192_priv *priv = container_of(dwork,struct r8192_priv,txpower_tracking_wq); + struct net_device *dev = priv->ieee80211->dev; +#else +extern void dm_txpower_trackingcallback(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); +#endif + +#ifdef RTL8190P + dm_TXPowerTrackingCallback_TSSI(dev); +#else + if(priv->bDcut == TRUE) + dm_TXPowerTrackingCallback_TSSI(dev); + else + dm_TXPowerTrackingCallback_ThermalMeter(dev); +#endif +} + + +static void dm_InitializeTXPowerTracking_TSSI(struct net_device *dev) +{ + + struct r8192_priv *priv = ieee80211_priv(dev); + + //Initial the Tx BB index and mapping value + priv->txbbgain_table[0].txbb_iq_amplifygain = 12; + priv->txbbgain_table[0].txbbgain_value=0x7f8001fe; + priv->txbbgain_table[1].txbb_iq_amplifygain = 11; + priv->txbbgain_table[1].txbbgain_value=0x788001e2; + priv->txbbgain_table[2].txbb_iq_amplifygain = 10; + priv->txbbgain_table[2].txbbgain_value=0x71c001c7; + priv->txbbgain_table[3].txbb_iq_amplifygain = 9; + priv->txbbgain_table[3].txbbgain_value=0x6b8001ae; + priv->txbbgain_table[4].txbb_iq_amplifygain = 8; + priv->txbbgain_table[4].txbbgain_value=0x65400195; + priv->txbbgain_table[5].txbb_iq_amplifygain = 7; + priv->txbbgain_table[5].txbbgain_value=0x5fc0017f; + priv->txbbgain_table[6].txbb_iq_amplifygain = 6; + priv->txbbgain_table[6].txbbgain_value=0x5a400169; + priv->txbbgain_table[7].txbb_iq_amplifygain = 5; + priv->txbbgain_table[7].txbbgain_value=0x55400155; + priv->txbbgain_table[8].txbb_iq_amplifygain = 4; + priv->txbbgain_table[8].txbbgain_value=0x50800142; + priv->txbbgain_table[9].txbb_iq_amplifygain = 3; + priv->txbbgain_table[9].txbbgain_value=0x4c000130; + priv->txbbgain_table[10].txbb_iq_amplifygain = 2; + priv->txbbgain_table[10].txbbgain_value=0x47c0011f; + priv->txbbgain_table[11].txbb_iq_amplifygain = 1; + priv->txbbgain_table[11].txbbgain_value=0x43c0010f; + priv->txbbgain_table[12].txbb_iq_amplifygain = 0; + priv->txbbgain_table[12].txbbgain_value=0x40000100; + priv->txbbgain_table[13].txbb_iq_amplifygain = -1; + priv->txbbgain_table[13].txbbgain_value=0x3c8000f2; + priv->txbbgain_table[14].txbb_iq_amplifygain = -2; + priv->txbbgain_table[14].txbbgain_value=0x390000e4; + priv->txbbgain_table[15].txbb_iq_amplifygain = -3; + priv->txbbgain_table[15].txbbgain_value=0x35c000d7; + priv->txbbgain_table[16].txbb_iq_amplifygain = -4; + priv->txbbgain_table[16].txbbgain_value=0x32c000cb; + priv->txbbgain_table[17].txbb_iq_amplifygain = -5; + priv->txbbgain_table[17].txbbgain_value=0x300000c0; + priv->txbbgain_table[18].txbb_iq_amplifygain = -6; + priv->txbbgain_table[18].txbbgain_value=0x2d4000b5; + priv->txbbgain_table[19].txbb_iq_amplifygain = -7; + priv->txbbgain_table[19].txbbgain_value=0x2ac000ab; + priv->txbbgain_table[20].txbb_iq_amplifygain = -8; + priv->txbbgain_table[20].txbbgain_value=0x288000a2; + priv->txbbgain_table[21].txbb_iq_amplifygain = -9; + priv->txbbgain_table[21].txbbgain_value=0x26000098; + priv->txbbgain_table[22].txbb_iq_amplifygain = -10; + priv->txbbgain_table[22].txbbgain_value=0x24000090; + priv->txbbgain_table[23].txbb_iq_amplifygain = -11; + priv->txbbgain_table[23].txbbgain_value=0x22000088; + priv->txbbgain_table[24].txbb_iq_amplifygain = -12; + priv->txbbgain_table[24].txbbgain_value=0x20000080; + priv->txbbgain_table[25].txbb_iq_amplifygain = -13; + priv->txbbgain_table[25].txbbgain_value=0x1a00006c; + priv->txbbgain_table[26].txbb_iq_amplifygain = -14; + priv->txbbgain_table[26].txbbgain_value=0x1c800072; + priv->txbbgain_table[27].txbb_iq_amplifygain = -15; + priv->txbbgain_table[27].txbbgain_value=0x18000060; + priv->txbbgain_table[28].txbb_iq_amplifygain = -16; + priv->txbbgain_table[28].txbbgain_value=0x19800066; + priv->txbbgain_table[29].txbb_iq_amplifygain = -17; + priv->txbbgain_table[29].txbbgain_value=0x15800056; + priv->txbbgain_table[30].txbb_iq_amplifygain = -18; + priv->txbbgain_table[30].txbbgain_value=0x26c0005b; + priv->txbbgain_table[31].txbb_iq_amplifygain = -19; + priv->txbbgain_table[31].txbbgain_value=0x14400051; + priv->txbbgain_table[32].txbb_iq_amplifygain = -20; + priv->txbbgain_table[32].txbbgain_value=0x24400051; + priv->txbbgain_table[33].txbb_iq_amplifygain = -21; + priv->txbbgain_table[33].txbbgain_value=0x1300004c; + priv->txbbgain_table[34].txbb_iq_amplifygain = -22; + priv->txbbgain_table[34].txbbgain_value=0x12000048; + priv->txbbgain_table[35].txbb_iq_amplifygain = -23; + priv->txbbgain_table[35].txbbgain_value=0x11000044; + priv->txbbgain_table[36].txbb_iq_amplifygain = -24; + priv->txbbgain_table[36].txbbgain_value=0x10000040; + + //ccktxbb_valuearray[0] is 0xA22 [1] is 0xA24 ...[7] is 0xA29 + //This Table is for CH1~CH13 + priv->cck_txbbgain_table[0].ccktxbb_valuearray[0] = 0x36; + priv->cck_txbbgain_table[0].ccktxbb_valuearray[1] = 0x35; + priv->cck_txbbgain_table[0].ccktxbb_valuearray[2] = 0x2e; + priv->cck_txbbgain_table[0].ccktxbb_valuearray[3] = 0x25; + priv->cck_txbbgain_table[0].ccktxbb_valuearray[4] = 0x1c; + priv->cck_txbbgain_table[0].ccktxbb_valuearray[5] = 0x12; + priv->cck_txbbgain_table[0].ccktxbb_valuearray[6] = 0x09; + priv->cck_txbbgain_table[0].ccktxbb_valuearray[7] = 0x04; + + priv->cck_txbbgain_table[1].ccktxbb_valuearray[0] = 0x33; + priv->cck_txbbgain_table[1].ccktxbb_valuearray[1] = 0x32; + priv->cck_txbbgain_table[1].ccktxbb_valuearray[2] = 0x2b; + priv->cck_txbbgain_table[1].ccktxbb_valuearray[3] = 0x23; + priv->cck_txbbgain_table[1].ccktxbb_valuearray[4] = 0x1a; + priv->cck_txbbgain_table[1].ccktxbb_valuearray[5] = 0x11; + priv->cck_txbbgain_table[1].ccktxbb_valuearray[6] = 0x08; + priv->cck_txbbgain_table[1].ccktxbb_valuearray[7] = 0x04; + + priv->cck_txbbgain_table[2].ccktxbb_valuearray[0] = 0x30; + priv->cck_txbbgain_table[2].ccktxbb_valuearray[1] = 0x2f; + priv->cck_txbbgain_table[2].ccktxbb_valuearray[2] = 0x29; + priv->cck_txbbgain_table[2].ccktxbb_valuearray[3] = 0x21; + priv->cck_txbbgain_table[2].ccktxbb_valuearray[4] = 0x19; + priv->cck_txbbgain_table[2].ccktxbb_valuearray[5] = 0x10; + priv->cck_txbbgain_table[2].ccktxbb_valuearray[6] = 0x08; + priv->cck_txbbgain_table[2].ccktxbb_valuearray[7] = 0x03; + + priv->cck_txbbgain_table[3].ccktxbb_valuearray[0] = 0x2d; + priv->cck_txbbgain_table[3].ccktxbb_valuearray[1] = 0x2d; + priv->cck_txbbgain_table[3].ccktxbb_valuearray[2] = 0x27; + priv->cck_txbbgain_table[3].ccktxbb_valuearray[3] = 0x1f; + priv->cck_txbbgain_table[3].ccktxbb_valuearray[4] = 0x18; + priv->cck_txbbgain_table[3].ccktxbb_valuearray[5] = 0x0f; + priv->cck_txbbgain_table[3].ccktxbb_valuearray[6] = 0x08; + priv->cck_txbbgain_table[3].ccktxbb_valuearray[7] = 0x03; + + priv->cck_txbbgain_table[4].ccktxbb_valuearray[0] = 0x2b; + priv->cck_txbbgain_table[4].ccktxbb_valuearray[1] = 0x2a; + priv->cck_txbbgain_table[4].ccktxbb_valuearray[2] = 0x25; + priv->cck_txbbgain_table[4].ccktxbb_valuearray[3] = 0x1e; + priv->cck_txbbgain_table[4].ccktxbb_valuearray[4] = 0x16; + priv->cck_txbbgain_table[4].ccktxbb_valuearray[5] = 0x0e; + priv->cck_txbbgain_table[4].ccktxbb_valuearray[6] = 0x07; + priv->cck_txbbgain_table[4].ccktxbb_valuearray[7] = 0x03; + + priv->cck_txbbgain_table[5].ccktxbb_valuearray[0] = 0x28; + priv->cck_txbbgain_table[5].ccktxbb_valuearray[1] = 0x28; + priv->cck_txbbgain_table[5].ccktxbb_valuearray[2] = 0x22; + priv->cck_txbbgain_table[5].ccktxbb_valuearray[3] = 0x1c; + priv->cck_txbbgain_table[5].ccktxbb_valuearray[4] = 0x15; + priv->cck_txbbgain_table[5].ccktxbb_valuearray[5] = 0x0d; + priv->cck_txbbgain_table[5].ccktxbb_valuearray[6] = 0x07; + priv->cck_txbbgain_table[5].ccktxbb_valuearray[7] = 0x03; + + priv->cck_txbbgain_table[6].ccktxbb_valuearray[0] = 0x26; + priv->cck_txbbgain_table[6].ccktxbb_valuearray[1] = 0x25; + priv->cck_txbbgain_table[6].ccktxbb_valuearray[2] = 0x21; + priv->cck_txbbgain_table[6].ccktxbb_valuearray[3] = 0x1b; + priv->cck_txbbgain_table[6].ccktxbb_valuearray[4] = 0x14; + priv->cck_txbbgain_table[6].ccktxbb_valuearray[5] = 0x0d; + priv->cck_txbbgain_table[6].ccktxbb_valuearray[6] = 0x06; + priv->cck_txbbgain_table[6].ccktxbb_valuearray[7] = 0x03; + + priv->cck_txbbgain_table[7].ccktxbb_valuearray[0] = 0x24; + priv->cck_txbbgain_table[7].ccktxbb_valuearray[1] = 0x23; + priv->cck_txbbgain_table[7].ccktxbb_valuearray[2] = 0x1f; + priv->cck_txbbgain_table[7].ccktxbb_valuearray[3] = 0x19; + priv->cck_txbbgain_table[7].ccktxbb_valuearray[4] = 0x13; + priv->cck_txbbgain_table[7].ccktxbb_valuearray[5] = 0x0c; + priv->cck_txbbgain_table[7].ccktxbb_valuearray[6] = 0x06; + priv->cck_txbbgain_table[7].ccktxbb_valuearray[7] = 0x03; + + priv->cck_txbbgain_table[8].ccktxbb_valuearray[0] = 0x22; + priv->cck_txbbgain_table[8].ccktxbb_valuearray[1] = 0x21; + priv->cck_txbbgain_table[8].ccktxbb_valuearray[2] = 0x1d; + priv->cck_txbbgain_table[8].ccktxbb_valuearray[3] = 0x18; + priv->cck_txbbgain_table[8].ccktxbb_valuearray[4] = 0x11; + priv->cck_txbbgain_table[8].ccktxbb_valuearray[5] = 0x0b; + priv->cck_txbbgain_table[8].ccktxbb_valuearray[6] = 0x06; + priv->cck_txbbgain_table[8].ccktxbb_valuearray[7] = 0x02; + + priv->cck_txbbgain_table[9].ccktxbb_valuearray[0] = 0x20; + priv->cck_txbbgain_table[9].ccktxbb_valuearray[1] = 0x20; + priv->cck_txbbgain_table[9].ccktxbb_valuearray[2] = 0x1b; + priv->cck_txbbgain_table[9].ccktxbb_valuearray[3] = 0x16; + priv->cck_txbbgain_table[9].ccktxbb_valuearray[4] = 0x11; + priv->cck_txbbgain_table[9].ccktxbb_valuearray[5] = 0x08; + priv->cck_txbbgain_table[9].ccktxbb_valuearray[6] = 0x05; + priv->cck_txbbgain_table[9].ccktxbb_valuearray[7] = 0x02; + + priv->cck_txbbgain_table[10].ccktxbb_valuearray[0] = 0x1f; + priv->cck_txbbgain_table[10].ccktxbb_valuearray[1] = 0x1e; + priv->cck_txbbgain_table[10].ccktxbb_valuearray[2] = 0x1a; + priv->cck_txbbgain_table[10].ccktxbb_valuearray[3] = 0x15; + priv->cck_txbbgain_table[10].ccktxbb_valuearray[4] = 0x10; + priv->cck_txbbgain_table[10].ccktxbb_valuearray[5] = 0x0a; + priv->cck_txbbgain_table[10].ccktxbb_valuearray[6] = 0x05; + priv->cck_txbbgain_table[10].ccktxbb_valuearray[7] = 0x02; + + priv->cck_txbbgain_table[11].ccktxbb_valuearray[0] = 0x1d; + priv->cck_txbbgain_table[11].ccktxbb_valuearray[1] = 0x1c; + priv->cck_txbbgain_table[11].ccktxbb_valuearray[2] = 0x18; + priv->cck_txbbgain_table[11].ccktxbb_valuearray[3] = 0x14; + priv->cck_txbbgain_table[11].ccktxbb_valuearray[4] = 0x0f; + priv->cck_txbbgain_table[11].ccktxbb_valuearray[5] = 0x0a; + priv->cck_txbbgain_table[11].ccktxbb_valuearray[6] = 0x05; + priv->cck_txbbgain_table[11].ccktxbb_valuearray[7] = 0x02; + + priv->cck_txbbgain_table[12].ccktxbb_valuearray[0] = 0x1b; + priv->cck_txbbgain_table[12].ccktxbb_valuearray[1] = 0x1a; + priv->cck_txbbgain_table[12].ccktxbb_valuearray[2] = 0x17; + priv->cck_txbbgain_table[12].ccktxbb_valuearray[3] = 0x13; + priv->cck_txbbgain_table[12].ccktxbb_valuearray[4] = 0x0e; + priv->cck_txbbgain_table[12].ccktxbb_valuearray[5] = 0x09; + priv->cck_txbbgain_table[12].ccktxbb_valuearray[6] = 0x04; + priv->cck_txbbgain_table[12].ccktxbb_valuearray[7] = 0x02; + + priv->cck_txbbgain_table[13].ccktxbb_valuearray[0] = 0x1a; + priv->cck_txbbgain_table[13].ccktxbb_valuearray[1] = 0x19; + priv->cck_txbbgain_table[13].ccktxbb_valuearray[2] = 0x16; + priv->cck_txbbgain_table[13].ccktxbb_valuearray[3] = 0x12; + priv->cck_txbbgain_table[13].ccktxbb_valuearray[4] = 0x0d; + priv->cck_txbbgain_table[13].ccktxbb_valuearray[5] = 0x09; + priv->cck_txbbgain_table[13].ccktxbb_valuearray[6] = 0x04; + priv->cck_txbbgain_table[13].ccktxbb_valuearray[7] = 0x02; + + priv->cck_txbbgain_table[14].ccktxbb_valuearray[0] = 0x18; + priv->cck_txbbgain_table[14].ccktxbb_valuearray[1] = 0x17; + priv->cck_txbbgain_table[14].ccktxbb_valuearray[2] = 0x15; + priv->cck_txbbgain_table[14].ccktxbb_valuearray[3] = 0x11; + priv->cck_txbbgain_table[14].ccktxbb_valuearray[4] = 0x0c; + priv->cck_txbbgain_table[14].ccktxbb_valuearray[5] = 0x08; + priv->cck_txbbgain_table[14].ccktxbb_valuearray[6] = 0x04; + priv->cck_txbbgain_table[14].ccktxbb_valuearray[7] = 0x02; + + priv->cck_txbbgain_table[15].ccktxbb_valuearray[0] = 0x17; + priv->cck_txbbgain_table[15].ccktxbb_valuearray[1] = 0x16; + priv->cck_txbbgain_table[15].ccktxbb_valuearray[2] = 0x13; + priv->cck_txbbgain_table[15].ccktxbb_valuearray[3] = 0x10; + priv->cck_txbbgain_table[15].ccktxbb_valuearray[4] = 0x0c; + priv->cck_txbbgain_table[15].ccktxbb_valuearray[5] = 0x08; + priv->cck_txbbgain_table[15].ccktxbb_valuearray[6] = 0x04; + priv->cck_txbbgain_table[15].ccktxbb_valuearray[7] = 0x02; + + priv->cck_txbbgain_table[16].ccktxbb_valuearray[0] = 0x16; + priv->cck_txbbgain_table[16].ccktxbb_valuearray[1] = 0x15; + priv->cck_txbbgain_table[16].ccktxbb_valuearray[2] = 0x12; + priv->cck_txbbgain_table[16].ccktxbb_valuearray[3] = 0x0f; + priv->cck_txbbgain_table[16].ccktxbb_valuearray[4] = 0x0b; + priv->cck_txbbgain_table[16].ccktxbb_valuearray[5] = 0x07; + priv->cck_txbbgain_table[16].ccktxbb_valuearray[6] = 0x04; + priv->cck_txbbgain_table[16].ccktxbb_valuearray[7] = 0x01; + + priv->cck_txbbgain_table[17].ccktxbb_valuearray[0] = 0x14; + priv->cck_txbbgain_table[17].ccktxbb_valuearray[1] = 0x14; + priv->cck_txbbgain_table[17].ccktxbb_valuearray[2] = 0x11; + priv->cck_txbbgain_table[17].ccktxbb_valuearray[3] = 0x0e; + priv->cck_txbbgain_table[17].ccktxbb_valuearray[4] = 0x0b; + priv->cck_txbbgain_table[17].ccktxbb_valuearray[5] = 0x07; + priv->cck_txbbgain_table[17].ccktxbb_valuearray[6] = 0x03; + priv->cck_txbbgain_table[17].ccktxbb_valuearray[7] = 0x02; + + priv->cck_txbbgain_table[18].ccktxbb_valuearray[0] = 0x13; + priv->cck_txbbgain_table[18].ccktxbb_valuearray[1] = 0x13; + priv->cck_txbbgain_table[18].ccktxbb_valuearray[2] = 0x10; + priv->cck_txbbgain_table[18].ccktxbb_valuearray[3] = 0x0d; + priv->cck_txbbgain_table[18].ccktxbb_valuearray[4] = 0x0a; + priv->cck_txbbgain_table[18].ccktxbb_valuearray[5] = 0x06; + priv->cck_txbbgain_table[18].ccktxbb_valuearray[6] = 0x03; + priv->cck_txbbgain_table[18].ccktxbb_valuearray[7] = 0x01; + + priv->cck_txbbgain_table[19].ccktxbb_valuearray[0] = 0x12; + priv->cck_txbbgain_table[19].ccktxbb_valuearray[1] = 0x12; + priv->cck_txbbgain_table[19].ccktxbb_valuearray[2] = 0x0f; + priv->cck_txbbgain_table[19].ccktxbb_valuearray[3] = 0x0c; + priv->cck_txbbgain_table[19].ccktxbb_valuearray[4] = 0x09; + priv->cck_txbbgain_table[19].ccktxbb_valuearray[5] = 0x06; + priv->cck_txbbgain_table[19].ccktxbb_valuearray[6] = 0x03; + priv->cck_txbbgain_table[19].ccktxbb_valuearray[7] = 0x01; + + priv->cck_txbbgain_table[20].ccktxbb_valuearray[0] = 0x11; + priv->cck_txbbgain_table[20].ccktxbb_valuearray[1] = 0x11; + priv->cck_txbbgain_table[20].ccktxbb_valuearray[2] = 0x0f; + priv->cck_txbbgain_table[20].ccktxbb_valuearray[3] = 0x0c; + priv->cck_txbbgain_table[20].ccktxbb_valuearray[4] = 0x09; + priv->cck_txbbgain_table[20].ccktxbb_valuearray[5] = 0x06; + priv->cck_txbbgain_table[20].ccktxbb_valuearray[6] = 0x03; + priv->cck_txbbgain_table[20].ccktxbb_valuearray[7] = 0x01; + + priv->cck_txbbgain_table[21].ccktxbb_valuearray[0] = 0x10; + priv->cck_txbbgain_table[21].ccktxbb_valuearray[1] = 0x10; + priv->cck_txbbgain_table[21].ccktxbb_valuearray[2] = 0x0e; + priv->cck_txbbgain_table[21].ccktxbb_valuearray[3] = 0x0b; + priv->cck_txbbgain_table[21].ccktxbb_valuearray[4] = 0x08; + priv->cck_txbbgain_table[21].ccktxbb_valuearray[5] = 0x05; + priv->cck_txbbgain_table[21].ccktxbb_valuearray[6] = 0x03; + priv->cck_txbbgain_table[21].ccktxbb_valuearray[7] = 0x01; + + priv->cck_txbbgain_table[22].ccktxbb_valuearray[0] = 0x0f; + priv->cck_txbbgain_table[22].ccktxbb_valuearray[1] = 0x0f; + priv->cck_txbbgain_table[22].ccktxbb_valuearray[2] = 0x0d; + priv->cck_txbbgain_table[22].ccktxbb_valuearray[3] = 0x0b; + priv->cck_txbbgain_table[22].ccktxbb_valuearray[4] = 0x08; + priv->cck_txbbgain_table[22].ccktxbb_valuearray[5] = 0x05; + priv->cck_txbbgain_table[22].ccktxbb_valuearray[6] = 0x03; + priv->cck_txbbgain_table[22].ccktxbb_valuearray[7] = 0x01; + + //ccktxbb_valuearray[0] is 0xA22 [1] is 0xA24 ...[7] is 0xA29 + //This Table is for CH14 + priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[0] = 0x36; + priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[1] = 0x35; + priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[2] = 0x2e; + priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[3] = 0x1b; + priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[4] = 0x00; + priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[5] = 0x00; + priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[6] = 0x00; + priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[7] = 0x00; + + priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[0] = 0x33; + priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[1] = 0x32; + priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[2] = 0x2b; + priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[3] = 0x19; + priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[4] = 0x00; + priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[5] = 0x00; + priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[6] = 0x00; + priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[7] = 0x00; + + priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[0] = 0x30; + priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[1] = 0x2f; + priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[2] = 0x29; + priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[3] = 0x18; + priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[4] = 0x00; + priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[5] = 0x00; + priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[6] = 0x00; + priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[7] = 0x00; + + priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[0] = 0x2d; + priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[1] = 0x2d; + priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[2] = 0x27; + priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[3] = 0x17; + priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[4] = 0x00; + priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[5] = 0x00; + priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[6] = 0x00; + priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[7] = 0x00; + + priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[0] = 0x2b; + priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[1] = 0x2a; + priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[2] = 0x25; + priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[3] = 0x15; + priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[4] = 0x00; + priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[5] = 0x00; + priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[6] = 0x00; + priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[7] = 0x00; + + priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[0] = 0x28; + priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[1] = 0x28; + priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[2] = 0x22; + priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[3] = 0x14; + priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[4] = 0x00; + priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[5] = 0x00; + priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[6] = 0x00; + priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[7] = 0x00; + + priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[0] = 0x26; + priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[1] = 0x25; + priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[2] = 0x21; + priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[3] = 0x13; + priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[4] = 0x00; + priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[5] = 0x00; + priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[6] = 0x00; + priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[7] = 0x00; + + priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[0] = 0x24; + priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[1] = 0x23; + priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[2] = 0x1f; + priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[3] = 0x12; + priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[4] = 0x00; + priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[5] = 0x00; + priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[6] = 0x00; + priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[7] = 0x00; + + priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[0] = 0x22; + priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[1] = 0x21; + priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[2] = 0x1d; + priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[3] = 0x11; + priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[4] = 0x00; + priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[5] = 0x00; + priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[6] = 0x00; + priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[7] = 0x00; + + priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[0] = 0x20; + priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[1] = 0x20; + priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[2] = 0x1b; + priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[3] = 0x10; + priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[4] = 0x00; + priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[5] = 0x00; + priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[6] = 0x00; + priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[7] = 0x00; + + priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[0] = 0x1f; + priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[1] = 0x1e; + priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[2] = 0x1a; + priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[3] = 0x0f; + priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[4] = 0x00; + priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[5] = 0x00; + priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[6] = 0x00; + priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[7] = 0x00; + + priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[0] = 0x1d; + priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[1] = 0x1c; + priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[2] = 0x18; + priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[3] = 0x0e; + priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[4] = 0x00; + priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[5] = 0x00; + priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[6] = 0x00; + priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[7] = 0x00; + + priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[0] = 0x1b; + priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[1] = 0x1a; + priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[2] = 0x17; + priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[3] = 0x0e; + priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[4] = 0x00; + priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[5] = 0x00; + priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[6] = 0x00; + priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[7] = 0x00; + + priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[0] = 0x1a; + priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[1] = 0x19; + priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[2] = 0x16; + priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[3] = 0x0d; + priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[4] = 0x00; + priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[5] = 0x00; + priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[6] = 0x00; + priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[7] = 0x00; + + priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[0] = 0x18; + priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[1] = 0x17; + priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[2] = 0x15; + priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[3] = 0x0c; + priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[4] = 0x00; + priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[5] = 0x00; + priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[6] = 0x00; + priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[7] = 0x00; + + priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[0] = 0x17; + priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[1] = 0x16; + priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[2] = 0x13; + priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[3] = 0x0b; + priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[4] = 0x00; + priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[5] = 0x00; + priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[6] = 0x00; + priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[7] = 0x00; + + priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[0] = 0x16; + priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[1] = 0x15; + priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[2] = 0x12; + priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[3] = 0x0b; + priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[4] = 0x00; + priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[5] = 0x00; + priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[6] = 0x00; + priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[7] = 0x00; + + priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[0] = 0x14; + priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[1] = 0x14; + priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[2] = 0x11; + priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[3] = 0x0a; + priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[4] = 0x00; + priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[5] = 0x00; + priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[6] = 0x00; + priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[7] = 0x00; + + priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[0] = 0x13; + priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[1] = 0x13; + priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[2] = 0x10; + priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[3] = 0x0a; + priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[4] = 0x00; + priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[5] = 0x00; + priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[6] = 0x00; + priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[7] = 0x00; + + priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[0] = 0x12; + priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[1] = 0x12; + priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[2] = 0x0f; + priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[3] = 0x09; + priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[4] = 0x00; + priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[5] = 0x00; + priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[6] = 0x00; + priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[7] = 0x00; + + priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[0] = 0x11; + priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[1] = 0x11; + priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[2] = 0x0f; + priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[3] = 0x09; + priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[4] = 0x00; + priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[5] = 0x00; + priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[6] = 0x00; + priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[7] = 0x00; + + priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[0] = 0x10; + priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[1] = 0x10; + priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[2] = 0x0e; + priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[3] = 0x08; + priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[4] = 0x00; + priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[5] = 0x00; + priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[6] = 0x00; + priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[7] = 0x00; + + priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[0] = 0x0f; + priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[1] = 0x0f; + priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[2] = 0x0d; + priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[3] = 0x08; + priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[4] = 0x00; + priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[5] = 0x00; + priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[6] = 0x00; + priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[7] = 0x00; + + priv->btxpower_tracking = TRUE; + priv->txpower_count = 0; + priv->btxpower_trackingInit = FALSE; + +} + +#ifndef RTL8192SU +static void dm_InitializeTXPowerTracking_ThermalMeter(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + + // Tx Power tracking by Theremal Meter require Firmware R/W 3-wire. This mechanism + // can be enabled only when Firmware R/W 3-wire is enabled. Otherwise, frequent r/w + // 3-wire by driver cause RF goes into wrong state. + if(priv->ieee80211->FwRWRF) + priv->btxpower_tracking = TRUE; + else + priv->btxpower_tracking = FALSE; + priv->txpower_count = 0; + priv->btxpower_trackingInit = FALSE; +} +#endif + +void dm_initialize_txpower_tracking(struct net_device *dev) +{ +#if (defined RTL8190P) + dm_InitializeTXPowerTracking_TSSI(dev); +#elif (defined RTL8192SU) + // 2009/01/12 MH Enable for 92S series channel 1-14 CCK tx pwer setting for MP. + // + dm_InitializeTXPowerTracking_TSSI(dev); +#else + struct r8192_priv *priv = ieee80211_priv(dev); + if(priv->bDcut == TRUE) + dm_InitializeTXPowerTracking_TSSI(dev); + else + dm_InitializeTXPowerTracking_ThermalMeter(dev); +#endif +}// dm_InitializeTXPowerTracking + + +static void dm_CheckTXPowerTracking_TSSI(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + static u32 tx_power_track_counter = 0; + + if(!priv->btxpower_tracking) + return; + else + { + if((tx_power_track_counter % 30 == 0)&&(tx_power_track_counter != 0)) + { + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + queue_delayed_work(priv->priv_wq,&priv->txpower_tracking_wq,0); + #else + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) + schedule_task(&priv->txpower_tracking_wq); + #else + queue_work(priv->priv_wq,&priv->txpower_tracking_wq); + #endif + #endif + } + tx_power_track_counter++; + } + +} + + +static void dm_CheckTXPowerTracking_ThermalMeter(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + static u8 TM_Trigger=0; +#if 0 + u1Byte i; + u4Byte tmpRegA; + for(i=0; i<50; i++) + { + tmpRegA = PHY_QueryRFReg(Adapter, RF90_PATH_A, 0x12, 0x078); // 0x12: RF Reg[10:7] + PHY_SetRFReg(Adapter, RF90_PATH_A, 0x02, bMask12Bits, 0x4d); + //delay_us(100); + PHY_SetRFReg(Adapter, RF90_PATH_A, 0x02, bMask12Bits, 0x4f); + //delay_us(100); + } + DbgPrint("Trigger and readback ThermalMeter, write RF reg0x2 = 0x4d to 0x4f for 50 times\n"); +#else + //DbgPrint("dm_CheckTXPowerTracking() \n"); + if(!priv->btxpower_tracking) + return; + else + { + if(priv->txpower_count <= 2) + { + priv->txpower_count++; + return; + } + } + + if(!TM_Trigger) + { + //Attention!! You have to wirte all 12bits data to RF, or it may cause RF to crash + //actually write reg0x02 bit1=0, then bit1=1. + //DbgPrint("Trigger ThermalMeter, write RF reg0x2 = 0x4d to 0x4f\n"); +#ifdef RTL8192SU + rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bRFRegOffsetMask, 0x4d); + rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bRFRegOffsetMask, 0x4f); + rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bRFRegOffsetMask, 0x4d); + rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bRFRegOffsetMask, 0x4f); +#else + rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4d); + rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4f); + rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4d); + rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4f); +#endif + TM_Trigger = 1; + return; + } + else + { + //DbgPrint("Schedule TxPowerTrackingWorkItem\n"); + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + queue_delayed_work(priv->priv_wq,&priv->txpower_tracking_wq,0); + #else + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) + schedule_task(&priv->txpower_tracking_wq); + #else + queue_work(priv->priv_wq,&priv->txpower_tracking_wq); + #endif + #endif + TM_Trigger = 0; + } +#endif +} + + +static void dm_check_txpower_tracking(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + //static u32 tx_power_track_counter = 0; + +#ifdef RTL8190P + dm_CheckTXPowerTracking_TSSI(dev); +#else + if(priv->bDcut == TRUE) + dm_CheckTXPowerTracking_TSSI(dev); + else + dm_CheckTXPowerTracking_ThermalMeter(dev); +#endif + +} // dm_CheckTXPowerTracking + + +static void dm_CCKTxPowerAdjust_TSSI(struct net_device *dev, bool bInCH14) +{ + u32 TempVal; + struct r8192_priv *priv = ieee80211_priv(dev); + //Write 0xa22 0xa23 + TempVal = 0; + if(!bInCH14){ + //Write 0xa22 0xa23 + TempVal = priv->cck_txbbgain_table[priv->cck_present_attentuation].ccktxbb_valuearray[0] + + (priv->cck_txbbgain_table[priv->cck_present_attentuation].ccktxbb_valuearray[1]<<8) ; + + rtl8192_setBBreg(dev, rCCK0_TxFilter1,bMaskHWord, TempVal); + //Write 0xa24 ~ 0xa27 + TempVal = 0; + TempVal = priv->cck_txbbgain_table[priv->cck_present_attentuation].ccktxbb_valuearray[2] + + (priv->cck_txbbgain_table[priv->cck_present_attentuation].ccktxbb_valuearray[3]<<8) + + (priv->cck_txbbgain_table[priv->cck_present_attentuation].ccktxbb_valuearray[4]<<16 )+ + (priv->cck_txbbgain_table[priv->cck_present_attentuation].ccktxbb_valuearray[5]<<24); + rtl8192_setBBreg(dev, rCCK0_TxFilter2,bMaskDWord, TempVal); + //Write 0xa28 0xa29 + TempVal = 0; + TempVal = priv->cck_txbbgain_table[priv->cck_present_attentuation].ccktxbb_valuearray[6] + + (priv->cck_txbbgain_table[priv->cck_present_attentuation].ccktxbb_valuearray[7]<<8) ; + + rtl8192_setBBreg(dev, rCCK0_DebugPort,bMaskLWord, TempVal); + } + else + { + TempVal = priv->cck_txbbgain_ch14_table[priv->cck_present_attentuation].ccktxbb_valuearray[0] + + (priv->cck_txbbgain_ch14_table[priv->cck_present_attentuation].ccktxbb_valuearray[1]<<8) ; + + rtl8192_setBBreg(dev, rCCK0_TxFilter1,bMaskHWord, TempVal); + //Write 0xa24 ~ 0xa27 + TempVal = 0; + TempVal = priv->cck_txbbgain_ch14_table[priv->cck_present_attentuation].ccktxbb_valuearray[2] + + (priv->cck_txbbgain_ch14_table[priv->cck_present_attentuation].ccktxbb_valuearray[3]<<8) + + (priv->cck_txbbgain_ch14_table[priv->cck_present_attentuation].ccktxbb_valuearray[4]<<16 )+ + (priv->cck_txbbgain_ch14_table[priv->cck_present_attentuation].ccktxbb_valuearray[5]<<24); + rtl8192_setBBreg(dev, rCCK0_TxFilter2,bMaskDWord, TempVal); + //Write 0xa28 0xa29 + TempVal = 0; + TempVal = priv->cck_txbbgain_ch14_table[priv->cck_present_attentuation].ccktxbb_valuearray[6] + + (priv->cck_txbbgain_ch14_table[priv->cck_present_attentuation].ccktxbb_valuearray[7]<<8) ; + + rtl8192_setBBreg(dev, rCCK0_DebugPort,bMaskLWord, TempVal); + } + + +} + +static void dm_CCKTxPowerAdjust_ThermalMeter(struct net_device *dev, bool bInCH14) +{ + u32 TempVal; + struct r8192_priv *priv = ieee80211_priv(dev); + + TempVal = 0; + if(!bInCH14) + { + //Write 0xa22 0xa23 + TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][0] + + (CCKSwingTable_Ch1_Ch13[priv->CCK_index][1]<<8) ; + rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal); + RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n", + rCCK0_TxFilter1, TempVal); + //Write 0xa24 ~ 0xa27 + TempVal = 0; + TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][2] + + (CCKSwingTable_Ch1_Ch13[priv->CCK_index][3]<<8) + + (CCKSwingTable_Ch1_Ch13[priv->CCK_index][4]<<16 )+ + (CCKSwingTable_Ch1_Ch13[priv->CCK_index][5]<<24); + rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal); + RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n", + rCCK0_TxFilter2, TempVal); + //Write 0xa28 0xa29 + TempVal = 0; + TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][6] + + (CCKSwingTable_Ch1_Ch13[priv->CCK_index][7]<<8) ; + + rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal); + RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n", + rCCK0_DebugPort, TempVal); + } + else + { +// priv->CCKTxPowerAdjustCntNotCh14++; //cosa add for debug. + //Write 0xa22 0xa23 + TempVal = CCKSwingTable_Ch14[priv->CCK_index][0] + + (CCKSwingTable_Ch14[priv->CCK_index][1]<<8) ; + + rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal); + RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n", + rCCK0_TxFilter1, TempVal); + //Write 0xa24 ~ 0xa27 + TempVal = 0; + TempVal = CCKSwingTable_Ch14[priv->CCK_index][2] + + (CCKSwingTable_Ch14[priv->CCK_index][3]<<8) + + (CCKSwingTable_Ch14[priv->CCK_index][4]<<16 )+ + (CCKSwingTable_Ch14[priv->CCK_index][5]<<24); + rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal); + RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n", + rCCK0_TxFilter2, TempVal); + //Write 0xa28 0xa29 + TempVal = 0; + TempVal = CCKSwingTable_Ch14[priv->CCK_index][6] + + (CCKSwingTable_Ch14[priv->CCK_index][7]<<8) ; + + rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal); + RT_TRACE(COMP_POWER_TRACKING,"CCK chnl 14, reg 0x%x = 0x%x\n", + rCCK0_DebugPort, TempVal); + } +} + + + +extern void dm_cck_txpower_adjust( + struct net_device *dev, + bool binch14 +) +{ // dm_CCKTxPowerAdjust + + struct r8192_priv *priv = ieee80211_priv(dev); +#ifdef RTL8190P + dm_CCKTxPowerAdjust_TSSI(dev, binch14); +#else + if(priv->bDcut == TRUE) + dm_CCKTxPowerAdjust_TSSI(dev, binch14); + else + dm_CCKTxPowerAdjust_ThermalMeter(dev, binch14); +#endif +} + + +#ifndef RTL8192U +static void dm_txpower_reset_recovery( + struct net_device *dev +) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + + RT_TRACE(COMP_POWER_TRACKING, "Start Reset Recovery ==>\n"); + rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbbgain_value); + RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in 0xc80 is %08x\n",priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbbgain_value); + RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in RFA_txPowerTrackingIndex is %x\n",priv->rfa_txpowertrackingindex); + RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery : RF A I/Q Amplify Gain is %ld\n",priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbb_iq_amplifygain); + RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: CCK Attenuation is %d dB\n",priv->cck_present_attentuation); + dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); + + rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbbgain_value); + RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in 0xc90 is %08x\n",priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbbgain_value); + RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in RFC_txPowerTrackingIndex is %x\n",priv->rfc_txpowertrackingindex); + RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery : RF C I/Q Amplify Gain is %ld\n",priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbb_iq_amplifygain); + +} // dm_TXPowerResetRecovery + +extern void dm_restore_dynamic_mechanism_state(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + u32 reg_ratr = priv->rate_adaptive.last_ratr; + + if(!priv->up) + { + RT_TRACE(COMP_RATE, "<---- dm_restore_dynamic_mechanism_state(): driver is going to unload\n"); + return; + } + + // + // Restore previous state for rate adaptive + // + if(priv->rate_adaptive.rate_adaptive_disabled) + return; + // TODO: Only 11n mode is implemented currently, + if( !(priv->ieee80211->mode==WIRELESS_MODE_N_24G || + priv->ieee80211->mode==WIRELESS_MODE_N_5G)) + return; + { + /* 2007/11/15 MH Copy from 8190PCI. */ + u32 ratr_value; + ratr_value = reg_ratr; + if(priv->rf_type == RF_1T2R) // 1T2R, Spatial Stream 2 should be disabled + { + ratr_value &=~ (RATE_ALL_OFDM_2SS); + //DbgPrint("HW_VAR_TATR_0 from 0x%x ==> 0x%x\n", ((pu4Byte)(val))[0], ratr_value); + } + //DbgPrint("set HW_VAR_TATR_0 = 0x%x\n", ratr_value); + //cosa PlatformEFIOWrite4Byte(Adapter, RATR0, ((pu4Byte)(val))[0]); + write_nic_dword(dev, RATR0, ratr_value); + write_nic_byte(dev, UFWP, 1); +#if 0 // Disable old code. + u1Byte index; + u4Byte input_value; + index = (u1Byte)((((pu4Byte)(val))[0]) >> 28); + input_value = (((pu4Byte)(val))[0]) & 0x0fffffff; + // TODO: Correct it. Emily 2007.01.11 + PlatformEFIOWrite4Byte(Adapter, RATR0+index*4, input_value); +#endif + } + //Resore TX Power Tracking Index + if(priv->btxpower_trackingInit && priv->btxpower_tracking){ + dm_txpower_reset_recovery(dev); + } + + // + //Restore BB Initial Gain + // + dm_bb_initialgain_restore(dev); + +} // DM_RestoreDynamicMechanismState + +static void dm_bb_initialgain_restore(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + u32 bit_mask = 0x7f; //Bit0~ Bit6 + + if(dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI) + return; + + //Disable Initial Gain + //PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x800); + rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite. + rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bit_mask, (u32)priv->initgain_backup.xaagccore1); + rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bit_mask, (u32)priv->initgain_backup.xbagccore1); + rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, bit_mask, (u32)priv->initgain_backup.xcagccore1); + rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, bit_mask, (u32)priv->initgain_backup.xdagccore1); + bit_mask = bMaskByte2; + rtl8192_setBBreg(dev, rCCK0_CCA, bit_mask, (u32)priv->initgain_backup.cca); + + RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1); + RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1); + RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1); + RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1); + RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca); + //Enable Initial Gain + //PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x100); + rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite. + +} // dm_BBInitialGainRestore + + +extern void dm_backup_dynamic_mechanism_state(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + + // Fsync to avoid reset + priv->bswitch_fsync = false; + priv->bfsync_processing = false; + //Backup BB InitialGain + dm_bb_initialgain_backup(dev); + +} // DM_BackupDynamicMechanismState + + +static void dm_bb_initialgain_backup(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + u32 bit_mask = bMaskByte0; //Bit0~ Bit6 + + if(dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI) + return; + + //PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x800); + rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite. + priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bit_mask); + priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bit_mask); + priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bit_mask); + priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bit_mask); + bit_mask = bMaskByte2; + priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, bit_mask); + + RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1); + RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1); + RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1); + RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1); + RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca); + +} // dm_BBInitialGainBakcup + +#endif +/*----------------------------------------------------------------------------- + * Function: dm_change_dynamic_initgain_thresh() + * + * Overview: + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 05/29/2008 amy Create Version 0 porting from windows code. + * + *---------------------------------------------------------------------------*/ +extern void dm_change_dynamic_initgain_thresh(struct net_device *dev, + u32 dm_type, + u32 dm_value) +{ +#ifdef RTL8192SU + struct r8192_priv *priv = ieee80211_priv(dev); + if(dm_type == DIG_TYPE_THRESH_HIGHPWR_HIGH) + priv->MidHighPwrTHR_L2 = (u8)dm_value; + else if(dm_type == DIG_TYPE_THRESH_HIGHPWR_LOW) + priv->MidHighPwrTHR_L1 = (u8)dm_value; + return; +#endif + if (dm_type == DIG_TYPE_THRESH_HIGH) + { + dm_digtable.rssi_high_thresh = dm_value; + } + else if (dm_type == DIG_TYPE_THRESH_LOW) + { + dm_digtable.rssi_low_thresh = dm_value; + } + else if (dm_type == DIG_TYPE_THRESH_HIGHPWR_HIGH) + { + dm_digtable.rssi_high_power_highthresh = dm_value; + } + else if (dm_type == DIG_TYPE_THRESH_HIGHPWR_HIGH) + { + dm_digtable.rssi_high_power_highthresh = dm_value; + } + else if (dm_type == DIG_TYPE_ENABLE) + { + dm_digtable.dig_state = DM_STA_DIG_MAX; + dm_digtable.dig_enable_flag = true; + } + else if (dm_type == DIG_TYPE_DISABLE) + { + dm_digtable.dig_state = DM_STA_DIG_MAX; + dm_digtable.dig_enable_flag = false; + } + else if (dm_type == DIG_TYPE_DBG_MODE) + { + if(dm_value >= DM_DBG_MAX) + dm_value = DM_DBG_OFF; + dm_digtable.dbg_mode = (u8)dm_value; + } + else if (dm_type == DIG_TYPE_RSSI) + { + if(dm_value > 100) + dm_value = 30; + dm_digtable.rssi_val = (long)dm_value; + } + else if (dm_type == DIG_TYPE_ALGORITHM) + { + if (dm_value >= DIG_ALGO_MAX) + dm_value = DIG_ALGO_BY_FALSE_ALARM; + if(dm_digtable.dig_algorithm != (u8)dm_value) + dm_digtable.dig_algorithm_switch = 1; + dm_digtable.dig_algorithm = (u8)dm_value; + } + else if (dm_type == DIG_TYPE_BACKOFF) + { + if(dm_value > 30) + dm_value = 30; + dm_digtable.backoff_val = (u8)dm_value; + } + else if(dm_type == DIG_TYPE_RX_GAIN_MIN) + { + if(dm_value == 0) + dm_value = 0x1; + dm_digtable.rx_gain_range_min = (u8)dm_value; + } + else if(dm_type == DIG_TYPE_RX_GAIN_MAX) + { + if(dm_value > 0x50) + dm_value = 0x50; + dm_digtable.rx_gain_range_max = (u8)dm_value; + } +} /* DM_ChangeDynamicInitGainThresh */ +extern void +dm_change_fsync_setting( + struct net_device *dev, + s32 DM_Type, + s32 DM_Value) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + + if (DM_Type == 0) // monitor 0xc38 register + { + if(DM_Value > 1) + DM_Value = 1; + priv->framesyncMonitor = (u8)DM_Value; + //DbgPrint("pHalData->framesyncMonitor = %d", pHalData->framesyncMonitor); + } +} + +extern void +dm_change_rxpath_selection_setting( + struct net_device *dev, + s32 DM_Type, + s32 DM_Value) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + prate_adaptive pRA = (prate_adaptive)&(priv->rate_adaptive); + + + if(DM_Type == 0) + { + if(DM_Value > 1) + DM_Value = 1; + DM_RxPathSelTable.Enable = (u8)DM_Value; + } + else if(DM_Type == 1) + { + if(DM_Value > 1) + DM_Value = 1; + DM_RxPathSelTable.DbgMode = (u8)DM_Value; + } + else if(DM_Type == 2) + { + if(DM_Value > 40) + DM_Value = 40; + DM_RxPathSelTable.SS_TH_low = (u8)DM_Value; + } + else if(DM_Type == 3) + { + if(DM_Value > 25) + DM_Value = 25; + DM_RxPathSelTable.diff_TH = (u8)DM_Value; + } + else if(DM_Type == 4) + { + if(DM_Value >= CCK_Rx_Version_MAX) + DM_Value = CCK_Rx_Version_1; + DM_RxPathSelTable.cck_method= (u8)DM_Value; + } + else if(DM_Type == 10) + { + if(DM_Value > 100) + DM_Value = 50; + DM_RxPathSelTable.rf_rssi[0] = (u8)DM_Value; + } + else if(DM_Type == 11) + { + if(DM_Value > 100) + DM_Value = 50; + DM_RxPathSelTable.rf_rssi[1] = (u8)DM_Value; + } + else if(DM_Type == 12) + { + if(DM_Value > 100) + DM_Value = 50; + DM_RxPathSelTable.rf_rssi[2] = (u8)DM_Value; + } + else if(DM_Type == 13) + { + if(DM_Value > 100) + DM_Value = 50; + DM_RxPathSelTable.rf_rssi[3] = (u8)DM_Value; + } + else if(DM_Type == 20) + { + if(DM_Value > 1) + DM_Value = 1; + pRA->ping_rssi_enable = (u8)DM_Value; + } + else if(DM_Type == 21) + { + if(DM_Value > 30) + DM_Value = 30; + pRA->ping_rssi_thresh_for_ra = DM_Value; + } +} + +#if 0 +extern void dm_force_tx_fw_info(struct net_device *dev, + u32 force_type, + u32 force_value) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + + if (force_type == 0) // don't force TxSC + { + //DbgPrint("Set Force SubCarrier Off\n"); + priv->tx_fwinfo_force_subcarriermode = 0; + } + else if(force_type == 1) //force + { + //DbgPrint("Set Force SubCarrier On\n"); + priv->tx_fwinfo_force_subcarriermode = 1; + if(force_value > 3) + force_value = 3; + priv->tx_fwinfo_force_subcarrierval = (u8)force_value; + } +} +#endif + +/*----------------------------------------------------------------------------- + * Function: dm_dig_init() + * + * Overview: Set DIG scheme init value. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 05/15/2008 amy Create Version 0 porting from windows code. + * + *---------------------------------------------------------------------------*/ +static void dm_dig_init(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + /* 2007/10/05 MH Disable DIG scheme now. Not tested. */ + dm_digtable.dig_enable_flag = true; + dm_digtable.dig_algorithm = DIG_ALGO_BY_RSSI; + dm_digtable.dbg_mode = DM_DBG_OFF; //off=by real rssi value, on=by DM_DigTable.Rssi_val for new dig + dm_digtable.dig_algorithm_switch = 0; + + /* 2007/10/04 MH Define init gain threshol. */ + dm_digtable.dig_state = DM_STA_DIG_MAX; + dm_digtable.dig_highpwr_state = DM_STA_DIG_MAX; + dm_digtable.initialgain_lowerbound_state = false; + + dm_digtable.rssi_low_thresh = DM_DIG_THRESH_LOW; + dm_digtable.rssi_high_thresh = DM_DIG_THRESH_HIGH; + + dm_digtable.rssi_high_power_lowthresh = DM_DIG_HIGH_PWR_THRESH_LOW; + dm_digtable.rssi_high_power_highthresh = DM_DIG_HIGH_PWR_THRESH_HIGH; + + dm_digtable.rssi_val = 50; //for new dig debug rssi value + dm_digtable.backoff_val = DM_DIG_BACKOFF; + dm_digtable.rx_gain_range_max = DM_DIG_MAX; + if(priv->CustomerID == RT_CID_819x_Netcore) + dm_digtable.rx_gain_range_min = DM_DIG_MIN_Netcore; + else + dm_digtable.rx_gain_range_min = DM_DIG_MIN; + +} /* dm_dig_init */ + + +/*----------------------------------------------------------------------------- + * Function: dm_ctrl_initgain_byrssi() + * + * Overview: Driver must monitor RSSI and notify firmware to change initial + * gain according to different threshold. BB team provide the + * suggested solution. + * + * Input: struct net_device *dev + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 05/27/2008 amy Create Version 0 porting from windows code. + *---------------------------------------------------------------------------*/ +static void dm_ctrl_initgain_byrssi(struct net_device *dev) +{ + + if (dm_digtable.dig_enable_flag == false) + return; + + if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) + dm_ctrl_initgain_byrssi_by_fwfalse_alarm(dev); + else if(dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI) + dm_ctrl_initgain_byrssi_by_driverrssi(dev); +// ; + else + return; +} + + +static void dm_ctrl_initgain_byrssi_by_driverrssi( + struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + u8 i; + static u8 fw_dig=0; + + if (dm_digtable.dig_enable_flag == false) + return; + + //DbgPrint("Dig by Sw Rssi \n"); + if(dm_digtable.dig_algorithm_switch) // if swithed algorithm, we have to disable FW Dig. + fw_dig = 0; + if(fw_dig <= 3) // execute several times to make sure the FW Dig is disabled + {// FW DIG Off + for(i=0; i<3; i++) + rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite. + fw_dig++; + dm_digtable.dig_state = DM_STA_DIG_OFF; //fw dig off. + } + + if(priv->ieee80211->state == IEEE80211_LINKED) + dm_digtable.cur_connect_state = DIG_CONNECT; + else + dm_digtable.cur_connect_state = DIG_DISCONNECT; + + //DbgPrint("DM_DigTable.PreConnectState = %d, DM_DigTable.CurConnectState = %d \n", + //DM_DigTable.PreConnectState, DM_DigTable.CurConnectState); + + if(dm_digtable.dbg_mode == DM_DBG_OFF) + dm_digtable.rssi_val = priv->undecorated_smoothed_pwdb; + //DbgPrint("DM_DigTable.Rssi_val = %d \n", DM_DigTable.Rssi_val); + dm_initial_gain(dev); + dm_pd_th(dev); + dm_cs_ratio(dev); + if(dm_digtable.dig_algorithm_switch) + dm_digtable.dig_algorithm_switch = 0; + dm_digtable.pre_connect_state = dm_digtable.cur_connect_state; + +} /* dm_CtrlInitGainByRssi */ + +static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm( + struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + static u32 reset_cnt = 0; + u8 i; + + if (dm_digtable.dig_enable_flag == false) + return; + + if(dm_digtable.dig_algorithm_switch) + { + dm_digtable.dig_state = DM_STA_DIG_MAX; + // Fw DIG On. + for(i=0; i<3; i++) + rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite. + dm_digtable.dig_algorithm_switch = 0; + } + + if (priv->ieee80211->state != IEEE80211_LINKED) + return; + + // For smooth, we can not change DIG state. + if ((priv->undecorated_smoothed_pwdb > dm_digtable.rssi_low_thresh) && + (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_thresh)) + { + return; + } + //DbgPrint("Dig by Fw False Alarm\n"); + //if (DM_DigTable.Dig_State == DM_STA_DIG_OFF) + /*DbgPrint("DIG Check\n\r RSSI=%d LOW=%d HIGH=%d STATE=%d", + pHalData->UndecoratedSmoothedPWDB, DM_DigTable.RssiLowThresh, + DM_DigTable.RssiHighThresh, DM_DigTable.Dig_State);*/ + /* 1. When RSSI decrease, We have to judge if it is smaller than a treshold + and then execute below step. */ + if ((priv->undecorated_smoothed_pwdb <= dm_digtable.rssi_low_thresh)) + { + /* 2008/02/05 MH When we execute silent reset, the DIG PHY parameters + will be reset to init value. We must prevent the condition. */ + if (dm_digtable.dig_state == DM_STA_DIG_OFF && + (priv->reset_count == reset_cnt)) + { + return; + } + else + { + reset_cnt = priv->reset_count; + } + + // If DIG is off, DIG high power state must reset. + dm_digtable.dig_highpwr_state = DM_STA_DIG_MAX; + dm_digtable.dig_state = DM_STA_DIG_OFF; + + // 1.1 DIG Off. + rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite. + + // 1.2 Set initial gain. + write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x17); + write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x17); + write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x17); + write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x17); + + // 1.3 Lower PD_TH for OFDM. + if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) + { + /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */ + // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same. +#ifdef RTL8192SU + rtl8192_setBBreg(dev, (rOFDM0_XATxAFE+3), bMaskByte0, 0x00); +#else + #ifdef RTL8190P + write_nic_byte(dev, rOFDM0_RxDetector1, 0x40); + #else + write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x00); + #endif +#endif + /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P) + write_nic_byte(pAdapter, rOFDM0_RxDetector1, 0x40); + */ + //else if (pAdapter->HardwareType == HARDWARE_TYPE_RTL8192E) + + + //else + //PlatformEFIOWrite1Byte(pAdapter, rOFDM0_RxDetector1, 0x40); + } + else + write_nic_byte(dev, rOFDM0_RxDetector1, 0x42); + + // 1.4 Lower CS ratio for CCK. + write_nic_byte(dev, 0xa0a, 0x08); + + // 1.5 Higher EDCCA. + //PlatformEFIOWrite4Byte(pAdapter, rOFDM0_ECCAThreshold, 0x325); + return; + + } + + /* 2. When RSSI increase, We have to judge if it is larger than a treshold + and then execute below step. */ + if ((priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_thresh) ) + { + u8 reset_flag = 0; + + if (dm_digtable.dig_state == DM_STA_DIG_ON && + (priv->reset_count == reset_cnt)) + { + dm_ctrl_initgain_byrssi_highpwr(dev); + return; + } + else + { + if (priv->reset_count != reset_cnt) + reset_flag = 1; + + reset_cnt = priv->reset_count; + } + + dm_digtable.dig_state = DM_STA_DIG_ON; + //DbgPrint("DIG ON\n\r"); + + // 2.1 Set initial gain. + // 2008/02/26 MH SD3-Jerry suggest to prevent dirty environment. + if (reset_flag == 1) + { + write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x2c); + write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x2c); + write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x2c); + write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x2c); + } + else + { + write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x20); + write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x20); + write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x20); + write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x20); + } + + // 2.2 Higher PD_TH for OFDM. + if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) + { + /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */ + // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same. + #ifdef RTL8190P + write_nic_byte(dev, rOFDM0_RxDetector1, 0x42); + #else + write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20); + #endif + /* + else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P) + write_nic_byte(dev, rOFDM0_RxDetector1, 0x42); + */ + //else if (pAdapter->HardwareType == HARDWARE_TYPE_RTL8192E) + + //else + //PlatformEFIOWrite1Byte(pAdapter, rOFDM0_RxDetector1, 0x42); + } + else + write_nic_byte(dev, rOFDM0_RxDetector1, 0x44); + + // 2.3 Higher CS ratio for CCK. + write_nic_byte(dev, 0xa0a, 0xcd); + + // 2.4 Lower EDCCA. + /* 2008/01/11 MH 90/92 series are the same. */ + //PlatformEFIOWrite4Byte(pAdapter, rOFDM0_ECCAThreshold, 0x346); + + // 2.5 DIG On. + rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite. + + } + + dm_ctrl_initgain_byrssi_highpwr(dev); + +} /* dm_CtrlInitGainByRssi */ + + +/*----------------------------------------------------------------------------- + * Function: dm_ctrl_initgain_byrssi_highpwr() + * + * Overview: + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 05/28/2008 amy Create Version 0 porting from windows code. + * + *---------------------------------------------------------------------------*/ +static void dm_ctrl_initgain_byrssi_highpwr( + struct net_device * dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + static u32 reset_cnt_highpwr = 0; + + // For smooth, we can not change high power DIG state in the range. + if ((priv->undecorated_smoothed_pwdb > dm_digtable.rssi_high_power_lowthresh) && + (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_power_highthresh)) + { + return; + } + + /* 3. When RSSI >75% or <70%, it is a high power issue. We have to judge if + it is larger than a treshold and then execute below step. */ + // 2008/02/05 MH SD3-Jerry Modify PD_TH for high power issue. + if (priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_power_highthresh) + { + if (dm_digtable.dig_highpwr_state == DM_STA_DIG_ON && + (priv->reset_count == reset_cnt_highpwr)) + return; + else + dm_digtable.dig_highpwr_state = DM_STA_DIG_ON; + + // 3.1 Higher PD_TH for OFDM for high power state. + if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) + { +#ifdef RTL8192SU + rtl8192_setBBreg(dev, (rOFDM0_XATxAFE+3), bMaskByte0, 0x10); +#else + #ifdef RTL8190P + write_nic_byte(dev, rOFDM0_RxDetector1, 0x41); + #else + write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x10); + #endif +#endif + /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P) + write_nic_byte(dev, rOFDM0_RxDetector1, 0x41); + */ + + } + else + write_nic_byte(dev, rOFDM0_RxDetector1, 0x43); + } + else + { + if (dm_digtable.dig_highpwr_state == DM_STA_DIG_OFF&& + (priv->reset_count == reset_cnt_highpwr)) + return; + else + dm_digtable.dig_highpwr_state = DM_STA_DIG_OFF; + + if (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_power_lowthresh && + priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_thresh) + { + // 3.2 Recover PD_TH for OFDM for normal power region. + if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) + { + #ifdef RTL8190P + write_nic_byte(dev, rOFDM0_RxDetector1, 0x42); + #else + write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20); + #endif + /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P) + write_nic_byte(dev, rOFDM0_RxDetector1, 0x42); + */ + + } + else + write_nic_byte(dev, rOFDM0_RxDetector1, 0x44); + } + } + + reset_cnt_highpwr = priv->reset_count; + +} /* dm_CtrlInitGainByRssiHighPwr */ + + +static void dm_initial_gain( + struct net_device * dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + u8 initial_gain=0; + static u8 initialized=0, force_write=0; + static u32 reset_cnt=0; + + if(dm_digtable.dig_algorithm_switch) + { + initialized = 0; + reset_cnt = 0; + } + + if(dm_digtable.pre_connect_state == dm_digtable.cur_connect_state) + { + if(dm_digtable.cur_connect_state == DIG_CONNECT) + { + if((dm_digtable.rssi_val+10-dm_digtable.backoff_val) > dm_digtable.rx_gain_range_max) + dm_digtable.cur_ig_value = dm_digtable.rx_gain_range_max; + else if((dm_digtable.rssi_val+10-dm_digtable.backoff_val) < dm_digtable.rx_gain_range_min) + dm_digtable.cur_ig_value = dm_digtable.rx_gain_range_min; + else + dm_digtable.cur_ig_value = dm_digtable.rssi_val+10-dm_digtable.backoff_val; + } + else //current state is disconnected + { + if(dm_digtable.cur_ig_value == 0) + dm_digtable.cur_ig_value = priv->DefaultInitialGain[0]; + else + dm_digtable.cur_ig_value = dm_digtable.pre_ig_value; + } + } + else // disconnected -> connected or connected -> disconnected + { + dm_digtable.cur_ig_value = priv->DefaultInitialGain[0]; + dm_digtable.pre_ig_value = 0; + } + //DbgPrint("DM_DigTable.CurIGValue = 0x%x, DM_DigTable.PreIGValue = 0x%x\n", DM_DigTable.CurIGValue, DM_DigTable.PreIGValue); + + // if silent reset happened, we should rewrite the values back + if(priv->reset_count != reset_cnt) + { + force_write = 1; + reset_cnt = priv->reset_count; + } + + if(dm_digtable.pre_ig_value != read_nic_byte(dev, rOFDM0_XAAGCCore1)) + force_write = 1; + + { + if((dm_digtable.pre_ig_value != dm_digtable.cur_ig_value) + || !initialized || force_write) + { + initial_gain = (u8)dm_digtable.cur_ig_value; + //DbgPrint("Write initial gain = 0x%x\n", initial_gain); + // Set initial gain. + write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain); + write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain); + write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain); + write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain); + dm_digtable.pre_ig_value = dm_digtable.cur_ig_value; + initialized = 1; + force_write = 0; + } + } +} + +static void dm_pd_th( + struct net_device * dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + static u8 initialized=0, force_write=0; + static u32 reset_cnt = 0; + + if(dm_digtable.dig_algorithm_switch) + { + initialized = 0; + reset_cnt = 0; + } + + if(dm_digtable.pre_connect_state == dm_digtable.cur_connect_state) + { + if(dm_digtable.cur_connect_state == DIG_CONNECT) + { + if (dm_digtable.rssi_val >= dm_digtable.rssi_high_power_highthresh) + dm_digtable.curpd_thstate = DIG_PD_AT_HIGH_POWER; + else if ((dm_digtable.rssi_val <= dm_digtable.rssi_low_thresh)) + dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER; + else if ((dm_digtable.rssi_val >= dm_digtable.rssi_high_thresh) && + (dm_digtable.rssi_val < dm_digtable.rssi_high_power_lowthresh)) + dm_digtable.curpd_thstate = DIG_PD_AT_NORMAL_POWER; + else + dm_digtable.curpd_thstate = dm_digtable.prepd_thstate; + } + else + { + dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER; + } + } + else // disconnected -> connected or connected -> disconnected + { + dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER; + } + + // if silent reset happened, we should rewrite the values back + if(priv->reset_count != reset_cnt) + { + force_write = 1; + reset_cnt = priv->reset_count; + } + + { + if((dm_digtable.prepd_thstate != dm_digtable.curpd_thstate) || + (initialized<=3) || force_write) + { + //DbgPrint("Write PD_TH state = %d\n", DM_DigTable.CurPD_THState); + if(dm_digtable.curpd_thstate == DIG_PD_AT_LOW_POWER) + { + // Lower PD_TH for OFDM. + if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) + { + /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */ + // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same. +#ifdef RTL8192SU + rtl8192_setBBreg(dev, (rOFDM0_XATxAFE+3), bMaskByte0, 0x00); +#else + #ifdef RTL8190P + write_nic_byte(dev, rOFDM0_RxDetector1, 0x40); + #else + write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x00); + #endif +#endif + /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P) + write_nic_byte(dev, rOFDM0_RxDetector1, 0x40); + */ + } + else + write_nic_byte(dev, rOFDM0_RxDetector1, 0x42); + } + else if(dm_digtable.curpd_thstate == DIG_PD_AT_NORMAL_POWER) + { + // Higher PD_TH for OFDM. + if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) + { + /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */ + // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same. + #ifdef RTL8190P + write_nic_byte(dev, rOFDM0_RxDetector1, 0x42); + #else + write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20); + #endif + /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P) + write_nic_byte(dev, rOFDM0_RxDetector1, 0x42); + */ + } + else + write_nic_byte(dev, rOFDM0_RxDetector1, 0x44); + } + else if(dm_digtable.curpd_thstate == DIG_PD_AT_HIGH_POWER) + { + // Higher PD_TH for OFDM for high power state. + if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) + { + #ifdef RTL8190P + write_nic_byte(dev, rOFDM0_RxDetector1, 0x41); + #else + write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x10); + #endif + /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P) + write_nic_byte(dev, rOFDM0_RxDetector1, 0x41); + */ + } + else + write_nic_byte(dev, rOFDM0_RxDetector1, 0x43); + } + dm_digtable.prepd_thstate = dm_digtable.curpd_thstate; + if(initialized <= 3) + initialized++; + force_write = 0; + } + } +} + +static void dm_cs_ratio( + struct net_device * dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + static u8 initialized=0,force_write=0; + static u32 reset_cnt = 0; + + if(dm_digtable.dig_algorithm_switch) + { + initialized = 0; + reset_cnt = 0; + } + + if(dm_digtable.pre_connect_state == dm_digtable.cur_connect_state) + { + if(dm_digtable.cur_connect_state == DIG_CONNECT) + { + if ((dm_digtable.rssi_val <= dm_digtable.rssi_low_thresh)) + dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER; + else if ((dm_digtable.rssi_val >= dm_digtable.rssi_high_thresh) ) + dm_digtable.curcs_ratio_state = DIG_CS_RATIO_HIGHER; + else + dm_digtable.curcs_ratio_state = dm_digtable.precs_ratio_state; + } + else + { + dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER; + } + } + else // disconnected -> connected or connected -> disconnected + { + dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER; + } + + // if silent reset happened, we should rewrite the values back + if(priv->reset_count != reset_cnt) + { + force_write = 1; + reset_cnt = priv->reset_count; + } + + + { + if((dm_digtable.precs_ratio_state != dm_digtable.curcs_ratio_state) || + !initialized || force_write) + { + //DbgPrint("Write CS_ratio state = %d\n", DM_DigTable.CurCS_ratioState); + if(dm_digtable.curcs_ratio_state == DIG_CS_RATIO_LOWER) + { + // Lower CS ratio for CCK. + write_nic_byte(dev, 0xa0a, 0x08); + } + else if(dm_digtable.curcs_ratio_state == DIG_CS_RATIO_HIGHER) + { + // Higher CS ratio for CCK. + write_nic_byte(dev, 0xa0a, 0xcd); + } + dm_digtable.precs_ratio_state = dm_digtable.curcs_ratio_state; + initialized = 1; + force_write = 0; + } + } +} + +extern void dm_init_edca_turbo(struct net_device * dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + + priv->bcurrent_turbo_EDCA = false; + priv->ieee80211->bis_any_nonbepkts = false; + priv->bis_cur_rdlstate = false; +} // dm_init_edca_turbo + +#if 1 +static void dm_check_edca_turbo( + struct net_device * dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo; + //PSTA_QOS pStaQos = pMgntInfo->pStaQos; + + // Keep past Tx/Rx packet count for RT-to-RT EDCA turbo. + static unsigned long lastTxOkCnt = 0; + static unsigned long lastRxOkCnt = 0; + unsigned long curTxOkCnt = 0; + unsigned long curRxOkCnt = 0; + + // + // Do not be Turbo if it's under WiFi config and Qos Enabled, because the EDCA parameters + // should follow the settings from QAP. By Bruce, 2007-12-07. + // + #if 1 + if(priv->ieee80211->state != IEEE80211_LINKED) + goto dm_CheckEdcaTurbo_EXIT; + #endif + // We do not turn on EDCA turbo mode for some AP that has IOT issue + if(priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_EDCA_TURBO) + goto dm_CheckEdcaTurbo_EXIT; + + { + u8* peername[11] = {"unknown", "realtek", "realtek_92se", "broadcom", "ralink", "atheros", "cisco", "marvell", "92u_softap", "self_softap"}; + static int wb_tmp = 0; + if (wb_tmp == 0){ + printk("%s():iot peer is %#x:%s, bssid:"MAC_FMT"\n",__FUNCTION__,pHTInfo->IOTPeer,peername[pHTInfo->IOTPeer], MAC_ARG(priv->ieee80211->current_network.bssid)); + wb_tmp = 1; + } + } + // Check the status for current condition. + if(!priv->ieee80211->bis_any_nonbepkts) + { + curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt; + curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt; +#ifdef RTL8192SU + // Modify EDCA parameters selection bias + // For some APs, use downlink EDCA parameters for uplink+downlink + if(priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_EDCA_BIAS_ON_RX) + { + if(curTxOkCnt > 4*curRxOkCnt) + { + if(priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA) + { + write_nic_dword(dev, EDCAPARA_BE, edca_setting_UL[pHTInfo->IOTPeer]); + priv->bis_cur_rdlstate = false; + } + } + else + { + if(!priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA) + { + write_nic_dword(dev, EDCAPARA_BE, edca_setting_DL[pHTInfo->IOTPeer]); + priv->bis_cur_rdlstate = true; + } + } + priv->bcurrent_turbo_EDCA = true; + } + else + { + if(curRxOkCnt > 4*curTxOkCnt) + { + if(!priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA) + { + write_nic_dword(dev, EDCAPARA_BE, edca_setting_DL[pHTInfo->IOTPeer]); + priv->bis_cur_rdlstate = true; + } + } + else + { + if(priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA) + { + write_nic_dword(dev, EDCAPARA_BE, edca_setting_UL[pHTInfo->IOTPeer]); + priv->bis_cur_rdlstate = false; + } + } + priv->bcurrent_turbo_EDCA = true; + } +#else + // For RT-AP, we needs to turn it on when Rx>Tx + if(curRxOkCnt > 4*curTxOkCnt) + { + //printk("%s():curRxOkCnt > 4*curTxOkCnt\n"); + if(!priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA) + { + write_nic_dword(dev, EDCAPARA_BE, edca_setting_DL[pHTInfo->IOTPeer]); + priv->bis_cur_rdlstate = true; + } + } + else + { + + //printk("%s():curRxOkCnt < 4*curTxOkCnt\n"); + if(priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA) + { + write_nic_dword(dev, EDCAPARA_BE, edca_setting_UL[pHTInfo->IOTPeer]); + priv->bis_cur_rdlstate = false; + } + + } + + priv->bcurrent_turbo_EDCA = true; +#endif + } + else + { + // + // Turn Off EDCA turbo here. + // Restore original EDCA according to the declaration of AP. + // + if(priv->bcurrent_turbo_EDCA) + { + + { + u8 u1bAIFS; + u32 u4bAcParam; + struct ieee80211_qos_parameters *qos_parameters = &priv->ieee80211->current_network.qos_data.parameters; + u8 mode = priv->ieee80211->mode; + + // For Each time updating EDCA parameter, reset EDCA turbo mode status. + dm_init_edca_turbo(dev); + u1bAIFS = qos_parameters->aifs[0] * ((mode&(IEEE_G|IEEE_N_24G)) ?9:20) + aSifsTime; + u4bAcParam = ((((u32)(qos_parameters->tx_op_limit[0]))<< AC_PARAM_TXOP_LIMIT_OFFSET)| + (((u32)(qos_parameters->cw_max[0]))<< AC_PARAM_ECW_MAX_OFFSET)| + (((u32)(qos_parameters->cw_min[0]))<< AC_PARAM_ECW_MIN_OFFSET)| + ((u32)u1bAIFS << AC_PARAM_AIFS_OFFSET)); + //write_nic_dword(dev, WDCAPARA_ADD[i], u4bAcParam); + write_nic_dword(dev, EDCAPARA_BE, u4bAcParam); + + // Check ACM bit. + // If it is set, immediately set ACM control bit to downgrading AC for passing WMM testplan. Annie, 2005-12-13. + { + // TODO: Modified this part and try to set acm control in only 1 IO processing!! + + PACI_AIFSN pAciAifsn = (PACI_AIFSN)&(qos_parameters->aifs[0]); + u8 AcmCtrl = read_nic_byte( dev, AcmHwCtrl ); + if( pAciAifsn->f.ACM ) + { // ACM bit is 1. + AcmCtrl |= AcmHw_BeqEn; + } + else + { // ACM bit is 0. + AcmCtrl &= (~AcmHw_BeqEn); + } + + RT_TRACE( COMP_QOS,"SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl ) ; + write_nic_byte(dev, AcmHwCtrl, AcmCtrl ); + } + } + priv->bcurrent_turbo_EDCA = false; + } + } + + +dm_CheckEdcaTurbo_EXIT: + // Set variables for next time. + priv->ieee80211->bis_any_nonbepkts = false; + lastTxOkCnt = priv->stats.txbytesunicast; + lastRxOkCnt = priv->stats.rxbytesunicast; +} // dm_CheckEdcaTurbo +#endif + +extern void DM_CTSToSelfSetting(struct net_device * dev,u32 DM_Type, u32 DM_Value) +{ + struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev); + + if (DM_Type == 0) // CTS to self disable/enable + { + if(DM_Value > 1) + DM_Value = 1; + priv->ieee80211->bCTSToSelfEnable = (bool)DM_Value; + //DbgPrint("pMgntInfo->bCTSToSelfEnable = %d\n", pMgntInfo->bCTSToSelfEnable); + } + else if(DM_Type == 1) //CTS to self Th + { + if(DM_Value >= 50) + DM_Value = 50; + priv->ieee80211->CTSToSelfTH = (u8)DM_Value; + //DbgPrint("pMgntInfo->CTSToSelfTH = %d\n", pMgntInfo->CTSToSelfTH); + } +} + +static void dm_init_ctstoself(struct net_device * dev) +{ + struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev); + + priv->ieee80211->bCTSToSelfEnable = TRUE; + priv->ieee80211->CTSToSelfTH = CTSToSelfTHVal; +} + +static void dm_ctstoself(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev); + PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo; + static unsigned long lastTxOkCnt = 0; + static unsigned long lastRxOkCnt = 0; + unsigned long curTxOkCnt = 0; + unsigned long curRxOkCnt = 0; + + if(priv->ieee80211->bCTSToSelfEnable != TRUE) + { + pHTInfo->IOTAction &= ~HT_IOT_ACT_FORCED_CTS2SELF; + return; + } + /* + 1. Uplink + 2. Linksys350/Linksys300N + 3. <50 disable, >55 enable + */ + + if(pHTInfo->IOTPeer == HT_IOT_PEER_BROADCOM) + { + curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt; + curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt; + if(curRxOkCnt > 4*curTxOkCnt) //downlink, disable CTS to self + { + pHTInfo->IOTAction &= ~HT_IOT_ACT_FORCED_CTS2SELF; + //DbgPrint("dm_CTSToSelf() ==> CTS to self disabled -- downlink\n"); + } + else //uplink + { + #if 1 + pHTInfo->IOTAction |= HT_IOT_ACT_FORCED_CTS2SELF; + #else + if(priv->undecorated_smoothed_pwdb < priv->ieee80211->CTSToSelfTH) // disable CTS to self + { + pHTInfo->IOTAction &= ~HT_IOT_ACT_FORCED_CTS2SELF; + //DbgPrint("dm_CTSToSelf() ==> CTS to self disabled\n"); + } + else if(priv->undecorated_smoothed_pwdb >= (priv->ieee80211->CTSToSelfTH+5)) // enable CTS to self + { + pHTInfo->IOTAction |= HT_IOT_ACT_FORCED_CTS2SELF; + //DbgPrint("dm_CTSToSelf() ==> CTS to self enabled\n"); + } + #endif + } + + lastTxOkCnt = priv->stats.txbytesunicast; + lastRxOkCnt = priv->stats.rxbytesunicast; + } +} + + +#if 0 +/*----------------------------------------------------------------------------- + * Function: dm_rf_operation_test_callback() + * + * Overview: Only for RF operation test now. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 05/29/2008 amy Create Version 0 porting from windows code. + * + *---------------------------------------------------------------------------*/ +extern void dm_rf_operation_test_callback(unsigned long dev) +{ +// struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev); + u8 erfpath; + + + for(erfpath=0; erfpath<4; erfpath++) + { + //DbgPrint("Set RF-%d\n\r", eRFPath); + //PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3d7); + udelay(100); + } + + { + //PlatformSetPeriodicTimer(Adapter, &pHalData->RfTest1Timer, 500); + } + + // For test + { + //u8 i; + //PlatformSetPeriodicTimer(Adapter, &pHalData->RfTest1Timer, 500); +#if 0 + for(i=0; i<50; i++) + { + // Write Test + PHY_SetRFReg(Adapter, RF90_PATH_A, 0x02, bMask12Bits, 0x4d); + //delay_us(100); + PHY_SetRFReg(Adapter, RF90_PATH_A, 0x02, bMask12Bits, 0x4f); + //delay_us(100); + PHY_SetRFReg(Adapter, RF90_PATH_C, 0x02, bMask12Bits, 0x4d); + //delay_us(100); + PHY_SetRFReg(Adapter, RF90_PATH_C, 0x02, bMask12Bits, 0x4f); + //delay_us(100); + +#if 0 + // Read test + PHY_QueryRFReg(Adapter, RF90_PATH_A, 0x02, bMask12Bits); + //delay_us(100); + PHY_QueryRFReg(Adapter, RF90_PATH_A, 0x02, bMask12Bits); + //delay_us(100); + PHY_QueryRFReg(Adapter, RF90_PATH_A, 0x12, bMask12Bits); + //delay_us(100); + PHY_QueryRFReg(Adapter, RF90_PATH_A, 0x12, bMask12Bits); + //delay_us(100); + PHY_QueryRFReg(Adapter, RF90_PATH_A, 0x21, bMask12Bits); + //delay_us(100); + PHY_QueryRFReg(Adapter, RF90_PATH_A, 0x21, bMask12Bits); + //delay_us(100); +#endif + } +#endif + } + +} /* DM_RfOperationTestCallBack */ +#endif + +/*----------------------------------------------------------------------------- + * Function: dm_check_rfctrl_gpio() + * + * Overview: Copy 8187B template for 9xseries. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 05/28/2008 amy Create Version 0 porting from windows code. + * + *---------------------------------------------------------------------------*/ +#if 1 +static void dm_check_rfctrl_gpio(struct net_device * dev) +{ + //struct r8192_priv *priv = ieee80211_priv(dev); + + // Walk around for DTM test, we will not enable HW - radio on/off because r/w + // page 1 register before Lextra bus is enabled cause system fails when resuming + // from S4. 20080218, Emily + + // Stop to execute workitem to prevent S3/S4 bug. +#ifdef RTL8190P + return; +#endif +#ifdef RTL8192U + return; +#endif +#ifdef RTL8192SU + return; +#endif +#ifdef RTL8192E + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + queue_delayed_work(priv->priv_wq,&priv->gpio_change_rf_wq,0); + #else + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) + schedule_task(&priv->gpio_change_rf_wq); + #else + queue_work(priv->priv_wq,&priv->gpio_change_rf_wq); + #endif + #endif +#endif + +} /* dm_CheckRfCtrlGPIO */ + +#endif +/*----------------------------------------------------------------------------- + * Function: dm_check_pbc_gpio() + * + * Overview: Check if PBC button is pressed. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 05/28/2008 amy Create Version 0 porting from windows code. + * + *---------------------------------------------------------------------------*/ +static void dm_check_pbc_gpio(struct net_device *dev) +{ +#ifdef RTL8192U + struct r8192_priv *priv = ieee80211_priv(dev); + u8 tmp1byte; + + + tmp1byte = read_nic_byte(dev,GPI); + if(tmp1byte == 0xff) + return; + + if (tmp1byte&BIT6 || tmp1byte&BIT0) + { + // Here we only set bPbcPressed to TRUE + // After trigger PBC, the variable will be set to FALSE + RT_TRACE(COMP_IO, "CheckPbcGPIO - PBC is pressed\n"); + priv->bpbc_pressed = true; + } +#endif +#ifdef RTL8192SU + struct r8192_priv *priv = ieee80211_priv(dev); + u8 tmp1byte; + + write_nic_byte(dev, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO)); + + tmp1byte = read_nic_byte(dev, GPIO_IO_SEL); + tmp1byte &= ~(HAL_8192S_HW_GPIO_WPS_BIT); + write_nic_byte(dev, GPIO_IO_SEL, tmp1byte); + + tmp1byte = read_nic_byte(dev, GPIO_IN); + + RT_TRACE(COMP_IO, "CheckPbcGPIO - %x\n", tmp1byte); + + // Add by hpfan 2008.07.07 to fix read GPIO error from S3 + if (tmp1byte == 0xff) + return ; + + if (tmp1byte&HAL_8192S_HW_GPIO_WPS_BIT) + { + // Here we only set bPbcPressed to TRUE + // After trigger PBC, the variable will be set to FALSE + RT_TRACE(COMP_IO, "CheckPbcGPIO - PBC is pressed\n"); + priv->bpbc_pressed = true; + } + +#endif + + +} + +#ifdef RTL8192E + +/*----------------------------------------------------------------------------- + * Function: dm_GPIOChangeRF + * Overview: PCI will not support workitem call back HW radio on-off control. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 02/21/2008 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) +extern void dm_gpio_change_rf_callback(struct work_struct *work) +{ + struct delayed_work *dwork = container_of(work,struct delayed_work,work); + struct r8192_priv *priv = container_of(dwork,struct r8192_priv,gpio_change_rf_wq); + struct net_device *dev = priv->ieee80211->dev; +#else +extern void dm_gpio_change_rf_callback(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); +#endif + u8 tmp1byte; + RT_RF_POWER_STATE eRfPowerStateToSet; + bool bActuallySet = false; + + do{ + bActuallySet=false; + + if(!priv->up) + { + RT_TRACE((COMP_INIT | COMP_POWER | COMP_RF),"dm_gpio_change_rf_callback(): Callback function breaks out!!\n"); + } + else + { + // 0x108 GPIO input register is read only + //set 0x108 B1= 1: RF-ON; 0: RF-OFF. + tmp1byte = read_nic_byte(dev,GPI); + + eRfPowerStateToSet = (tmp1byte&BIT1) ? eRfOn : eRfOff; + + if( (priv->bHwRadioOff == true) && (eRfPowerStateToSet == eRfOn)) + { + RT_TRACE(COMP_RF, "gpiochangeRF - HW Radio ON\n"); + + priv->bHwRadioOff = false; + bActuallySet = true; + } + else if ( (priv->bHwRadioOff == false) && (eRfPowerStateToSet == eRfOff)) + { + RT_TRACE(COMP_RF, "gpiochangeRF - HW Radio OFF\n"); + priv->bHwRadioOff = true; + bActuallySet = true; + } + + if(bActuallySet) + { + #ifdef TO_DO + MgntActSet_RF_State(dev, eRfPowerStateToSet, RF_CHANGE_BY_HW); + //DrvIFIndicateCurrentPhyStatus(pAdapter); + #endif + } + else + { + msleep(2000); + } + + } + }while(TRUE) + +} /* dm_GPIOChangeRF */ + +#endif +/*----------------------------------------------------------------------------- + * Function: DM_RFPathCheckWorkItemCallBack() + * + * Overview: Check if Current RF RX path is enabled + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 01/30/2008 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) +extern void dm_rf_pathcheck_workitemcallback(struct work_struct *work) +{ + struct delayed_work *dwork = container_of(work,struct delayed_work,work); + struct r8192_priv *priv = container_of(dwork,struct r8192_priv,rfpath_check_wq); + struct net_device *dev =priv->ieee80211->dev; +#else +extern void dm_rf_pathcheck_workitemcallback(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); +#endif + //bool bactually_set = false; + u8 rfpath = 0, i; + + + /* 2008/01/30 MH After discussing with SD3 Jerry, 0xc04/0xd04 register will + always be the same. We only read 0xc04 now. */ + rfpath = read_nic_byte(dev, 0xc04); + + // Check Bit 0-3, it means if RF A-D is enabled. + for (i = 0; i < RF90_PATH_MAX; i++) + { + if (rfpath & (0x01<<i)) + priv->brfpath_rxenable[i] = 1; + else + priv->brfpath_rxenable[i] = 0; + } + if(!DM_RxPathSelTable.Enable) + return; + + dm_rxpath_sel_byrssi(dev); +} /* DM_RFPathCheckWorkItemCallBack */ + +static void dm_init_rxpath_selection(struct net_device * dev) +{ + u8 i; + struct r8192_priv *priv = ieee80211_priv(dev); + DM_RxPathSelTable.Enable = 1; //default enabled + DM_RxPathSelTable.SS_TH_low = RxPathSelection_SS_TH_low; + DM_RxPathSelTable.diff_TH = RxPathSelection_diff_TH; + if(priv->CustomerID == RT_CID_819x_Netcore) + DM_RxPathSelTable.cck_method = CCK_Rx_Version_2; + else + DM_RxPathSelTable.cck_method = CCK_Rx_Version_1; + DM_RxPathSelTable.DbgMode = DM_DBG_OFF; + DM_RxPathSelTable.disabledRF = 0; + for(i=0; i<4; i++) + { + DM_RxPathSelTable.rf_rssi[i] = 50; + DM_RxPathSelTable.cck_pwdb_sta[i] = -64; + DM_RxPathSelTable.rf_enable_rssi_th[i] = 100; + } +} + +static void dm_rxpath_sel_byrssi(struct net_device * dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + u8 i, max_rssi_index=0, min_rssi_index=0, sec_rssi_index=0, rf_num=0; + u8 tmp_max_rssi=0, tmp_min_rssi=0, tmp_sec_rssi=0; + u8 cck_default_Rx=0x2; //RF-C + u8 cck_optional_Rx=0x3;//RF-D + long tmp_cck_max_pwdb=0, tmp_cck_min_pwdb=0, tmp_cck_sec_pwdb=0; + u8 cck_rx_ver2_max_index=0, cck_rx_ver2_min_index=0, cck_rx_ver2_sec_index=0; + u8 cur_rf_rssi; + long cur_cck_pwdb; + static u8 disabled_rf_cnt=0, cck_Rx_Path_initialized=0; + u8 update_cck_rx_path; + + if(priv->rf_type != RF_2T4R) + return; + + if(!cck_Rx_Path_initialized) + { + DM_RxPathSelTable.cck_Rx_path = (read_nic_byte(dev, 0xa07)&0xf); + cck_Rx_Path_initialized = 1; + } + + DM_RxPathSelTable.disabledRF = 0xf; + DM_RxPathSelTable.disabledRF &=~ (read_nic_byte(dev, 0xc04)); + + if(priv->ieee80211->mode == WIRELESS_MODE_B) + { + DM_RxPathSelTable.cck_method = CCK_Rx_Version_2; //pure B mode, fixed cck version2 + //DbgPrint("Pure B mode, use cck rx version2 \n"); + } + + //decide max/sec/min rssi index + for (i=0; i<RF90_PATH_MAX; i++) + { + if(!DM_RxPathSelTable.DbgMode) + DM_RxPathSelTable.rf_rssi[i] = priv->stats.rx_rssi_percentage[i]; + + if(priv->brfpath_rxenable[i]) + { + rf_num++; + cur_rf_rssi = DM_RxPathSelTable.rf_rssi[i]; + + if(rf_num == 1) // find first enabled rf path and the rssi values + { //initialize, set all rssi index to the same one + max_rssi_index = min_rssi_index = sec_rssi_index = i; + tmp_max_rssi = tmp_min_rssi = tmp_sec_rssi = cur_rf_rssi; + } + else if(rf_num == 2) + { // we pick up the max index first, and let sec and min to be the same one + if(cur_rf_rssi >= tmp_max_rssi) + { + tmp_max_rssi = cur_rf_rssi; + max_rssi_index = i; + } + else + { + tmp_sec_rssi = tmp_min_rssi = cur_rf_rssi; + sec_rssi_index = min_rssi_index = i; + } + } + else + { + if(cur_rf_rssi > tmp_max_rssi) + { + tmp_sec_rssi = tmp_max_rssi; + sec_rssi_index = max_rssi_index; + tmp_max_rssi = cur_rf_rssi; + max_rssi_index = i; + } + else if(cur_rf_rssi == tmp_max_rssi) + { // let sec and min point to the different index + tmp_sec_rssi = cur_rf_rssi; + sec_rssi_index = i; + } + else if((cur_rf_rssi < tmp_max_rssi) &&(cur_rf_rssi > tmp_sec_rssi)) + { + tmp_sec_rssi = cur_rf_rssi; + sec_rssi_index = i; + } + else if(cur_rf_rssi == tmp_sec_rssi) + { + if(tmp_sec_rssi == tmp_min_rssi) + { // let sec and min point to the different index + tmp_sec_rssi = cur_rf_rssi; + sec_rssi_index = i; + } + else + { + // This case we don't need to set any index + } + } + else if((cur_rf_rssi < tmp_sec_rssi) && (cur_rf_rssi > tmp_min_rssi)) + { + // This case we don't need to set any index + } + else if(cur_rf_rssi == tmp_min_rssi) + { + if(tmp_sec_rssi == tmp_min_rssi) + { // let sec and min point to the different index + tmp_min_rssi = cur_rf_rssi; + min_rssi_index = i; + } + else + { + // This case we don't need to set any index + } + } + else if(cur_rf_rssi < tmp_min_rssi) + { + tmp_min_rssi = cur_rf_rssi; + min_rssi_index = i; + } + } + } + } + + rf_num = 0; + // decide max/sec/min cck pwdb index + if(DM_RxPathSelTable.cck_method == CCK_Rx_Version_2) + { + for (i=0; i<RF90_PATH_MAX; i++) + { + if(priv->brfpath_rxenable[i]) + { + rf_num++; + cur_cck_pwdb = DM_RxPathSelTable.cck_pwdb_sta[i]; + + if(rf_num == 1) // find first enabled rf path and the rssi values + { //initialize, set all rssi index to the same one + cck_rx_ver2_max_index = cck_rx_ver2_min_index = cck_rx_ver2_sec_index = i; + tmp_cck_max_pwdb = tmp_cck_min_pwdb = tmp_cck_sec_pwdb = cur_cck_pwdb; + } + else if(rf_num == 2) + { // we pick up the max index first, and let sec and min to be the same one + if(cur_cck_pwdb >= tmp_cck_max_pwdb) + { + tmp_cck_max_pwdb = cur_cck_pwdb; + cck_rx_ver2_max_index = i; + } + else + { + tmp_cck_sec_pwdb = tmp_cck_min_pwdb = cur_cck_pwdb; + cck_rx_ver2_sec_index = cck_rx_ver2_min_index = i; + } + } + else + { + if(cur_cck_pwdb > tmp_cck_max_pwdb) + { + tmp_cck_sec_pwdb = tmp_cck_max_pwdb; + cck_rx_ver2_sec_index = cck_rx_ver2_max_index; + tmp_cck_max_pwdb = cur_cck_pwdb; + cck_rx_ver2_max_index = i; + } + else if(cur_cck_pwdb == tmp_cck_max_pwdb) + { // let sec and min point to the different index + tmp_cck_sec_pwdb = cur_cck_pwdb; + cck_rx_ver2_sec_index = i; + } + else if((cur_cck_pwdb < tmp_cck_max_pwdb) &&(cur_cck_pwdb > tmp_cck_sec_pwdb)) + { + tmp_cck_sec_pwdb = cur_cck_pwdb; + cck_rx_ver2_sec_index = i; + } + else if(cur_cck_pwdb == tmp_cck_sec_pwdb) + { + if(tmp_cck_sec_pwdb == tmp_cck_min_pwdb) + { // let sec and min point to the different index + tmp_cck_sec_pwdb = cur_cck_pwdb; + cck_rx_ver2_sec_index = i; + } + else + { + // This case we don't need to set any index + } + } + else if((cur_cck_pwdb < tmp_cck_sec_pwdb) && (cur_cck_pwdb > tmp_cck_min_pwdb)) + { + // This case we don't need to set any index + } + else if(cur_cck_pwdb == tmp_cck_min_pwdb) + { + if(tmp_cck_sec_pwdb == tmp_cck_min_pwdb) + { // let sec and min point to the different index + tmp_cck_min_pwdb = cur_cck_pwdb; + cck_rx_ver2_min_index = i; + } + else + { + // This case we don't need to set any index + } + } + else if(cur_cck_pwdb < tmp_cck_min_pwdb) + { + tmp_cck_min_pwdb = cur_cck_pwdb; + cck_rx_ver2_min_index = i; + } + } + + } + } + } + + + // Set CCK Rx path + // reg0xA07[3:2]=cck default rx path, reg0xa07[1:0]=cck optional rx path. + update_cck_rx_path = 0; + if(DM_RxPathSelTable.cck_method == CCK_Rx_Version_2) + { + cck_default_Rx = cck_rx_ver2_max_index; + cck_optional_Rx = cck_rx_ver2_sec_index; + if(tmp_cck_max_pwdb != -64) + update_cck_rx_path = 1; + } + + if(tmp_min_rssi < DM_RxPathSelTable.SS_TH_low && disabled_rf_cnt < 2) + { + if((tmp_max_rssi - tmp_min_rssi) >= DM_RxPathSelTable.diff_TH) + { + //record the enabled rssi threshold + DM_RxPathSelTable.rf_enable_rssi_th[min_rssi_index] = tmp_max_rssi+5; + //disable the BB Rx path, OFDM + rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x1<<min_rssi_index, 0x0); // 0xc04[3:0] + rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x1<<min_rssi_index, 0x0); // 0xd04[3:0] + disabled_rf_cnt++; + } + if(DM_RxPathSelTable.cck_method == CCK_Rx_Version_1) + { + cck_default_Rx = max_rssi_index; + cck_optional_Rx = sec_rssi_index; + if(tmp_max_rssi) + update_cck_rx_path = 1; + } + } + + if(update_cck_rx_path) + { + DM_RxPathSelTable.cck_Rx_path = (cck_default_Rx<<2)|(cck_optional_Rx); + rtl8192_setBBreg(dev, rCCK0_AFESetting, 0x0f000000, DM_RxPathSelTable.cck_Rx_path); + } + + if(DM_RxPathSelTable.disabledRF) + { + for(i=0; i<4; i++) + { + if((DM_RxPathSelTable.disabledRF>>i) & 0x1) //disabled rf + { + if(tmp_max_rssi >= DM_RxPathSelTable.rf_enable_rssi_th[i]) + { + //enable the BB Rx path + //DbgPrint("RF-%d is enabled. \n", 0x1<<i); + rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x1<<i, 0x1); // 0xc04[3:0] + rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x1<<i, 0x1); // 0xd04[3:0] + DM_RxPathSelTable.rf_enable_rssi_th[i] = 100; + disabled_rf_cnt--; + } + } + } + } +} + +/*----------------------------------------------------------------------------- + * Function: dm_check_rx_path_selection() + * + * Overview: Call a workitem to check current RXRF path and Rx Path selection by RSSI. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 05/28/2008 amy Create Version 0 porting from windows code. + * + *---------------------------------------------------------------------------*/ +static void dm_check_rx_path_selection(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + queue_delayed_work(priv->priv_wq,&priv->rfpath_check_wq,0); +#else +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) + schedule_task(&priv->rfpath_check_wq); +#else + queue_work(priv->priv_wq,&priv->rfpath_check_wq); +#endif +#endif +} /* dm_CheckRxRFPath */ + + +static void dm_init_fsync (struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + + priv->ieee80211->fsync_time_interval = 500; + priv->ieee80211->fsync_rate_bitmap = 0x0f000800; + priv->ieee80211->fsync_rssi_threshold = 30; +#ifdef RTL8190P + priv->ieee80211->bfsync_enable = true; +#else + priv->ieee80211->bfsync_enable = false; +#endif + priv->ieee80211->fsync_multiple_timeinterval = 3; + priv->ieee80211->fsync_firstdiff_ratethreshold= 100; + priv->ieee80211->fsync_seconddiff_ratethreshold= 200; + priv->ieee80211->fsync_state = Default_Fsync; + priv->framesyncMonitor = 1; // current default 0xc38 monitor on + + init_timer(&priv->fsync_timer); + priv->fsync_timer.data = (unsigned long)dev; + priv->fsync_timer.function = dm_fsync_timer_callback; +} + + +static void dm_deInit_fsync(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + del_timer_sync(&priv->fsync_timer); +} + +extern void dm_fsync_timer_callback(unsigned long data) +{ + struct net_device *dev = (struct net_device *)data; + struct r8192_priv *priv = ieee80211_priv((struct net_device *)data); + u32 rate_index, rate_count = 0, rate_count_diff=0; + bool bSwitchFromCountDiff = false; + bool bDoubleTimeInterval = false; + + if( priv->ieee80211->state == IEEE80211_LINKED && + priv->ieee80211->bfsync_enable && + (priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_CDD_FSYNC)) + { + // Count rate 54, MCS [7], [12, 13, 14, 15] + u32 rate_bitmap; + for(rate_index = 0; rate_index <= 27; rate_index++) + { + rate_bitmap = 1 << rate_index; + if(priv->ieee80211->fsync_rate_bitmap & rate_bitmap) + rate_count+= priv->stats.received_rate_histogram[1][rate_index]; + } + + if(rate_count < priv->rate_record) + rate_count_diff = 0xffffffff - rate_count + priv->rate_record; + else + rate_count_diff = rate_count - priv->rate_record; + if(rate_count_diff < priv->rateCountDiffRecord) + { + + u32 DiffNum = priv->rateCountDiffRecord - rate_count_diff; + // Contiune count + if(DiffNum >= priv->ieee80211->fsync_seconddiff_ratethreshold) + priv->ContiuneDiffCount++; + else + priv->ContiuneDiffCount = 0; + + // Contiune count over + if(priv->ContiuneDiffCount >=2) + { + bSwitchFromCountDiff = true; + priv->ContiuneDiffCount = 0; + } + } + else + { + // Stop contiune count + priv->ContiuneDiffCount = 0; + } + + //If Count diff <= FsyncRateCountThreshold + if(rate_count_diff <= priv->ieee80211->fsync_firstdiff_ratethreshold) + { + bSwitchFromCountDiff = true; + priv->ContiuneDiffCount = 0; + } + priv->rate_record = rate_count; + priv->rateCountDiffRecord = rate_count_diff; + RT_TRACE(COMP_HALDM, "rateRecord %d rateCount %d, rateCountdiff %d bSwitchFsync %d\n", priv->rate_record, rate_count, rate_count_diff , priv->bswitch_fsync); + // if we never receive those mcs rate and rssi > 30 % then switch fsyn + if(priv->undecorated_smoothed_pwdb > priv->ieee80211->fsync_rssi_threshold && bSwitchFromCountDiff) + { + bDoubleTimeInterval = true; + priv->bswitch_fsync = !priv->bswitch_fsync; + if(priv->bswitch_fsync) + { + #ifdef RTL8190P + write_nic_byte(dev, 0xC36, 0x00); + #else + write_nic_byte(dev,0xC36, 0x1c); + #endif + write_nic_byte(dev, 0xC3e, 0x90); + } + else + { + #ifdef RTL8190P + write_nic_byte(dev, 0xC36, 0x40); + #else + write_nic_byte(dev, 0xC36, 0x5c); + #endif + write_nic_byte(dev, 0xC3e, 0x96); + } + } + else if(priv->undecorated_smoothed_pwdb <= priv->ieee80211->fsync_rssi_threshold) + { + if(priv->bswitch_fsync) + { + priv->bswitch_fsync = false; + #ifdef RTL8190P + write_nic_byte(dev, 0xC36, 0x40); + #else + write_nic_byte(dev, 0xC36, 0x5c); + #endif + write_nic_byte(dev, 0xC3e, 0x96); + } + } + if(bDoubleTimeInterval){ + if(timer_pending(&priv->fsync_timer)) + del_timer_sync(&priv->fsync_timer); + priv->fsync_timer.expires = jiffies + MSECS(priv->ieee80211->fsync_time_interval*priv->ieee80211->fsync_multiple_timeinterval); + add_timer(&priv->fsync_timer); + } + else{ + if(timer_pending(&priv->fsync_timer)) + del_timer_sync(&priv->fsync_timer); + priv->fsync_timer.expires = jiffies + MSECS(priv->ieee80211->fsync_time_interval); + add_timer(&priv->fsync_timer); + } + } + else + { + // Let Register return to default value; + if(priv->bswitch_fsync) + { + priv->bswitch_fsync = false; + #ifdef RTL8190P + write_nic_byte(dev, 0xC36, 0x40); + #else + write_nic_byte(dev, 0xC36, 0x5c); + #endif + write_nic_byte(dev, 0xC3e, 0x96); + } + priv->ContiuneDiffCount = 0; +#ifdef RTL8192SU + rtl8192_setBBreg(dev, rOFDM0_RxDetector2, bMaskDWord, 0x164052cd); +#else + #ifdef RTL8190P + write_nic_dword(dev, rOFDM0_RxDetector2, 0x164052cd); + #else + write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd); + #endif +#endif + } + RT_TRACE(COMP_HALDM, "ContiuneDiffCount %d\n", priv->ContiuneDiffCount); + RT_TRACE(COMP_HALDM, "rateRecord %d rateCount %d, rateCountdiff %d bSwitchFsync %d\n", priv->rate_record, rate_count, rate_count_diff , priv->bswitch_fsync); +} + +static void dm_StartHWFsync(struct net_device *dev) +{ + RT_TRACE(COMP_HALDM, "%s\n", __FUNCTION__); + write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c12cf); + write_nic_byte(dev, 0xc3b, 0x41); +} + +static void dm_EndSWFsync(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + + RT_TRACE(COMP_HALDM, "%s\n", __FUNCTION__); + del_timer_sync(&(priv->fsync_timer)); + + // Let Register return to default value; + if(priv->bswitch_fsync) + { + priv->bswitch_fsync = false; + + #ifdef RTL8190P + write_nic_byte(dev, 0xC36, 0x40); + #else + write_nic_byte(dev, 0xC36, 0x5c); + #endif + + write_nic_byte(dev, 0xC3e, 0x96); + } + + priv->ContiuneDiffCount = 0; +#ifndef RTL8190P + write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd); +#endif + +} + +static void dm_StartSWFsync(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + u32 rateIndex; + u32 rateBitmap; + + RT_TRACE(COMP_HALDM,"%s\n", __FUNCTION__); + // Initial rate record to zero, start to record. + priv->rate_record = 0; + // Initial contiune diff count to zero, start to record. + priv->ContiuneDiffCount = 0; + priv->rateCountDiffRecord = 0; + priv->bswitch_fsync = false; + + if(priv->ieee80211->mode == WIRELESS_MODE_N_24G) + { + priv->ieee80211->fsync_firstdiff_ratethreshold= 600; + priv->ieee80211->fsync_seconddiff_ratethreshold = 0xffff; + } + else + { + priv->ieee80211->fsync_firstdiff_ratethreshold= 200; + priv->ieee80211->fsync_seconddiff_ratethreshold = 200; + } + for(rateIndex = 0; rateIndex <= 27; rateIndex++) + { + rateBitmap = 1 << rateIndex; + if(priv->ieee80211->fsync_rate_bitmap & rateBitmap) + priv->rate_record += priv->stats.received_rate_histogram[1][rateIndex]; + } + if(timer_pending(&priv->fsync_timer)) + del_timer_sync(&priv->fsync_timer); + priv->fsync_timer.expires = jiffies + MSECS(priv->ieee80211->fsync_time_interval); + add_timer(&priv->fsync_timer); + +#ifndef RTL8190P + write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c12cd); +#endif + +} + +static void dm_EndHWFsync(struct net_device *dev) +{ + RT_TRACE(COMP_HALDM,"%s\n", __FUNCTION__); + write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd); + write_nic_byte(dev, 0xc3b, 0x49); + +} + +void dm_check_fsync(struct net_device *dev) +{ +#define RegC38_Default 0 +#define RegC38_NonFsync_Other_AP 1 +#define RegC38_Fsync_AP_BCM 2 + struct r8192_priv *priv = ieee80211_priv(dev); + //u32 framesyncC34; + static u8 reg_c38_State=RegC38_Default; + static u32 reset_cnt=0; + + RT_TRACE(COMP_HALDM, "RSSI %d TimeInterval %d MultipleTimeInterval %d\n", priv->ieee80211->fsync_rssi_threshold, priv->ieee80211->fsync_time_interval, priv->ieee80211->fsync_multiple_timeinterval); + RT_TRACE(COMP_HALDM, "RateBitmap 0x%x FirstDiffRateThreshold %d SecondDiffRateThreshold %d\n", priv->ieee80211->fsync_rate_bitmap, priv->ieee80211->fsync_firstdiff_ratethreshold, priv->ieee80211->fsync_seconddiff_ratethreshold); + + if( priv->ieee80211->state == IEEE80211_LINKED && + (priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_CDD_FSYNC)) + { + if(priv->ieee80211->bfsync_enable == 0) + { + switch(priv->ieee80211->fsync_state) + { + case Default_Fsync: + dm_StartHWFsync(dev); + priv->ieee80211->fsync_state = HW_Fsync; + break; + case SW_Fsync: + dm_EndSWFsync(dev); + dm_StartHWFsync(dev); + priv->ieee80211->fsync_state = HW_Fsync; + break; + case HW_Fsync: + default: + break; + } + } + else + { + switch(priv->ieee80211->fsync_state) + { + case Default_Fsync: + dm_StartSWFsync(dev); + priv->ieee80211->fsync_state = SW_Fsync; + break; + case HW_Fsync: + dm_EndHWFsync(dev); + dm_StartSWFsync(dev); + priv->ieee80211->fsync_state = SW_Fsync; + break; + case SW_Fsync: + default: + break; + + } + } + if(priv->framesyncMonitor) + { + if(reg_c38_State != RegC38_Fsync_AP_BCM) + { //For broadcom AP we write different default value + #ifdef RTL8190P + write_nic_byte(dev, rOFDM0_RxDetector3, 0x15); + #else + write_nic_byte(dev, rOFDM0_RxDetector3, 0x95); + #endif + + reg_c38_State = RegC38_Fsync_AP_BCM; + } + } + } + else + { + switch(priv->ieee80211->fsync_state) + { + case HW_Fsync: + dm_EndHWFsync(dev); + priv->ieee80211->fsync_state = Default_Fsync; + break; + case SW_Fsync: + dm_EndSWFsync(dev); + priv->ieee80211->fsync_state = Default_Fsync; + break; + case Default_Fsync: + default: + break; + } + + if(priv->framesyncMonitor) + { + if(priv->ieee80211->state == IEEE80211_LINKED) + { + if(priv->undecorated_smoothed_pwdb <= RegC38_TH) + { + if(reg_c38_State != RegC38_NonFsync_Other_AP) + { + #ifdef RTL8190P + write_nic_byte(dev, rOFDM0_RxDetector3, 0x10); + #else + write_nic_byte(dev, rOFDM0_RxDetector3, 0x90); + #endif + + reg_c38_State = RegC38_NonFsync_Other_AP; + #if 0//cosa + if (Adapter->HardwareType == HARDWARE_TYPE_RTL8190P) + DbgPrint("Fsync is idle, rssi<=35, write 0xc38 = 0x%x \n", 0x10); + else + DbgPrint("Fsync is idle, rssi<=35, write 0xc38 = 0x%x \n", 0x90); + #endif + } + } + else if(priv->undecorated_smoothed_pwdb >= (RegC38_TH+5)) + { + if(reg_c38_State) + { + write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync); + reg_c38_State = RegC38_Default; + //DbgPrint("Fsync is idle, rssi>=40, write 0xc38 = 0x%x \n", pHalData->framesync); + } + } + } + else + { + if(reg_c38_State) + { + write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync); + reg_c38_State = RegC38_Default; + //DbgPrint("Fsync is idle, not connected, write 0xc38 = 0x%x \n", pHalData->framesync); + } + } + } + } + if(priv->framesyncMonitor) + { + if(priv->reset_count != reset_cnt) + { //After silent reset, the reg_c38_State will be returned to default value + write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync); + reg_c38_State = RegC38_Default; + reset_cnt = priv->reset_count; + //DbgPrint("reg_c38_State = 0 for silent reset. \n"); + } + } + else + { + if(reg_c38_State) + { + write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync); + reg_c38_State = RegC38_Default; + //DbgPrint("framesync no monitor, write 0xc38 = 0x%x \n", pHalData->framesync); + } + } +} + +#if 0 +/*----------------------------------------------------------------------------- + * Function: DM_CheckLBusStatus() + * + * Overview: For 9x series, we must make sure LBUS is active for IO. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 02/22/2008 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +extern s1Byte DM_CheckLBusStatus(IN PADAPTER Adapter) +{ + PMGNT_INFO pMgntInfo=&Adapter->MgntInfo; + +#if (HAL_CODE_BASE & RTL819X) + +#if (HAL_CODE_BASE == RTL8192) + +#if( DEV_BUS_TYPE==PCI_INTERFACE) + //return (pMgntInfo->bLbusEnable); // For debug only + return TRUE; +#endif + +#if( DEV_BUS_TYPE==USB_INTERFACE) + return TRUE; +#endif + +#endif // #if (HAL_CODE_BASE == RTL8192) + +#if (HAL_CODE_BASE == RTL8190) + return TRUE; +#endif // #if (HAL_CODE_BASE == RTL8190) + +#endif // #if (HAL_CODE_BASE & RTL819X) +} /* DM_CheckLBusStatus */ + +#endif + +/*----------------------------------------------------------------------------- + * Function: dm_shadow_init() + * + * Overview: Store all NIC MAC/BB register content. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 05/29/2008 amy Create Version 0 porting from windows code. + * + *---------------------------------------------------------------------------*/ +extern void dm_shadow_init(struct net_device *dev) +{ + u8 page; + u16 offset; + + for (page = 0; page < 5; page++) + for (offset = 0; offset < 256; offset++) + { + dm_shadow[page][offset] = read_nic_byte(dev, offset+page*256); + //DbgPrint("P-%d/O-%02x=%02x\r\n", page, offset, DM_Shadow[page][offset]); + } + + for (page = 8; page < 11; page++) + for (offset = 0; offset < 256; offset++) + dm_shadow[page][offset] = read_nic_byte(dev, offset+page*256); + + for (page = 12; page < 15; page++) + for (offset = 0; offset < 256; offset++) + dm_shadow[page][offset] = read_nic_byte(dev, offset+page*256); + +} /* dm_shadow_init */ + +/*---------------------------Define function prototype------------------------*/ +/*----------------------------------------------------------------------------- + * Function: DM_DynamicTxPower() + * + * Overview: Detect Signal strength to control TX Registry + Tx Power Control For Near/Far Range + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 03/06/2008 Jacken Create Version 0. + * + *---------------------------------------------------------------------------*/ +static void dm_init_dynamic_txpower(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + + //Initial TX Power Control for near/far range , add by amy 2008/05/15, porting from windows code. + priv->ieee80211->bdynamic_txpower_enable = true; //Default to enable Tx Power Control + priv->bLastDTPFlag_High = false; + priv->bLastDTPFlag_Low = false; + priv->bDynamicTxHighPower = false; + priv->bDynamicTxLowPower = false; +} + +static void dm_dynamic_txpower(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + unsigned int txhipower_threshhold=0; + unsigned int txlowpower_threshold=0; + if(priv->ieee80211->bdynamic_txpower_enable != true) + { + priv->bDynamicTxHighPower = false; + priv->bDynamicTxLowPower = false; + return; + } + //printk("priv->ieee80211->current_network.unknown_cap_exist is %d ,priv->ieee80211->current_network.broadcom_cap_exist is %d\n",priv->ieee80211->current_network.unknown_cap_exist,priv->ieee80211->current_network.broadcom_cap_exist); + if((priv->ieee80211->current_network.atheros_cap_exist ) && (priv->ieee80211->mode == IEEE_G)){ + txhipower_threshhold = TX_POWER_ATHEROAP_THRESH_HIGH; + txlowpower_threshold = TX_POWER_ATHEROAP_THRESH_LOW; + } + else + { + txhipower_threshhold = TX_POWER_NEAR_FIELD_THRESH_HIGH; + txlowpower_threshold = TX_POWER_NEAR_FIELD_THRESH_LOW; + } + +// printk("=======>%s(): txhipower_threshhold is %d,txlowpower_threshold is %d\n",__FUNCTION__,txhipower_threshhold,txlowpower_threshold); + RT_TRACE(COMP_TXAGC,"priv->undecorated_smoothed_pwdb = %ld \n" , priv->undecorated_smoothed_pwdb); + + if(priv->ieee80211->state == IEEE80211_LINKED) + { + if(priv->undecorated_smoothed_pwdb >= txhipower_threshhold) + { + priv->bDynamicTxHighPower = true; + priv->bDynamicTxLowPower = false; + } + else + { + // high power state check + if(priv->undecorated_smoothed_pwdb < txlowpower_threshold && priv->bDynamicTxHighPower == true) + { + priv->bDynamicTxHighPower = false; + } + // low power state check + if(priv->undecorated_smoothed_pwdb < 35) + { + priv->bDynamicTxLowPower = true; + } + else if(priv->undecorated_smoothed_pwdb >= 40) + { + priv->bDynamicTxLowPower = false; + } + } + } + else + { + //pHalData->bTXPowerCtrlforNearFarRange = !pHalData->bTXPowerCtrlforNearFarRange; + priv->bDynamicTxHighPower = false; + priv->bDynamicTxLowPower = false; + } + + if( (priv->bDynamicTxHighPower != priv->bLastDTPFlag_High ) || + (priv->bDynamicTxLowPower != priv->bLastDTPFlag_Low ) ) + { + RT_TRACE(COMP_TXAGC,"SetTxPowerLevel8190() channel = %d \n" , priv->ieee80211->current_network.channel); +#ifndef RTL8192SU +#if defined(RTL8190P) || defined(RTL8192E) + SetTxPowerLevel8190(Adapter,pHalData->CurrentChannel); +#endif + +#ifdef RTL8192U + rtl8192_phy_setTxPower(dev,priv->ieee80211->current_network.channel); + //pHalData->bStartTxCtrlByTPCNFR = FALSE; //Clear th flag of Set TX Power from Sitesurvey +#endif +#endif + } + priv->bLastDTPFlag_High = priv->bDynamicTxHighPower; + priv->bLastDTPFlag_Low = priv->bDynamicTxLowPower; + +} /* dm_dynamic_txpower */ + +//added by vivi, for read tx rate and retrycount +static void dm_check_txrateandretrycount(struct net_device * dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + struct ieee80211_device* ieee = priv->ieee80211; + //for 11n tx rate +// priv->stats.CurrentShowTxate = read_nic_byte(dev, Current_Tx_Rate_Reg); +#ifdef RTL8192SU + ieee->softmac_stats.CurrentShowTxate = read_nic_byte(dev, TX_RATE_REG); +#else + ieee->softmac_stats.CurrentShowTxate = read_nic_byte(dev, Current_Tx_Rate_Reg); +#endif + //printk("=============>tx_rate_reg:%x\n", ieee->softmac_stats.CurrentShowTxate); + //for initial tx rate +// priv->stats.last_packet_rate = read_nic_byte(dev, Initial_Tx_Rate_Reg); + ieee->softmac_stats.last_packet_rate = read_nic_byte(dev ,Initial_Tx_Rate_Reg); + //for tx tx retry count +// priv->stats.txretrycount = read_nic_dword(dev, Tx_Retry_Count_Reg); + ieee->softmac_stats.txretrycount = read_nic_dword(dev, Tx_Retry_Count_Reg); +} + +static void dm_send_rssi_tofw(struct net_device *dev) +{ +#ifndef RTL8192SU + DCMD_TXCMD_T tx_cmd; + struct r8192_priv *priv = ieee80211_priv(dev); + + // If we test chariot, we should stop the TX command ? + // Because 92E will always silent reset when we send tx command. We use register + // 0x1e0(byte) to botify driver. + write_nic_byte(dev, DRIVER_RSSI, (u8)priv->undecorated_smoothed_pwdb); + return; +#if 1 + tx_cmd.Op = TXCMD_SET_RX_RSSI; + tx_cmd.Length = 4; + tx_cmd.Value = priv->undecorated_smoothed_pwdb; + + cmpk_message_handle_tx(dev, (u8*)&tx_cmd, + DESC_PACKET_TYPE_INIT, sizeof(DCMD_TXCMD_T)); +#endif +#endif +} + +#ifdef TO_DO_LIST +static void +dm_CheckProtection(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + //PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + u8 CurRate; + + if(priv->ieee80211->pHTInfo->IOTAction & (HT_IOT_ACT_FORCED_RTS|HT_IOT_ACT_FORCED_CTS2SELF)) + { + CurRate = read_nic_byte(dev, INIMCS_SEL); + if(CurRate <= DESC92S_RATE11M) + priv->bDmDisableProtect = true; + else + priv->bDmDisableProtect = fasle; + } +} +#endif + +/*---------------------------Define function prototype------------------------*/ + diff --git a/drivers/staging/rtl8192su/r8192U_dm.h b/drivers/staging/rtl8192su/r8192U_dm.h new file mode 100644 index 000000000000..1e05d7579882 --- /dev/null +++ b/drivers/staging/rtl8192su/r8192U_dm.h @@ -0,0 +1,309 @@ +/***************************************************************************** + * Copyright(c) 2007, RealTEK Technology Inc. All Right Reserved. + * + * Module: Hal819xUsbDM.h (RTL8192 Header H File) + * + * + * Note: For dynamic control definition constant structure. + * + * + * Export: + * + * Abbrev: + * + * History: + * Data Who Remark + * 10/04/2007 MHC Create initial version. + * + *****************************************************************************/ + /* Check to see if the file has been included already. */ +#ifndef __R8192UDM_H__ +#define __R8192UDM_H__ + + +/*--------------------------Define Parameters-------------------------------*/ +#define DM_DIG_THRESH_HIGH 40 +#define DM_DIG_THRESH_LOW 35 + +#define DM_DIG_HIGH_PWR_THRESH_HIGH 75 +#define DM_DIG_HIGH_PWR_THRESH_LOW 70 + +#define BW_AUTO_SWITCH_HIGH_LOW 25 +#define BW_AUTO_SWITCH_LOW_HIGH 30 + +#define DM_check_fsync_time_interval 500 + + +#define DM_DIG_BACKOFF 12 +#define DM_DIG_MAX 0x36 +#define DM_DIG_MIN 0x1c +#define DM_DIG_MIN_Netcore 0x12 + +#define RxPathSelection_SS_TH_low 30 +#define RxPathSelection_diff_TH 18 + +#define RateAdaptiveTH_High 50 +#define RateAdaptiveTH_Low_20M 30 +#define RateAdaptiveTH_Low_40M 10 +#define VeryLowRSSI 15 +#define CTSToSelfTHVal 30 + +//defined by vivi, for tx power track +#define E_FOR_TX_POWER_TRACK 300 +//Dynamic Tx Power Control Threshold +#define TX_POWER_NEAR_FIELD_THRESH_HIGH 68 +#define TX_POWER_NEAR_FIELD_THRESH_LOW 62 +//added by amy for atheros AP +#define TX_POWER_ATHEROAP_THRESH_HIGH 78 +#define TX_POWER_ATHEROAP_THRESH_LOW 72 + +//defined by vivi, for showing on UI +#define Current_Tx_Rate_Reg 0x1b8 +#define Initial_Tx_Rate_Reg 0x1b9 +#define Tx_Retry_Count_Reg 0x1ac +#define RegC38_TH 20 +#if 0 +//---------------------------------------------------------------------------- +// 8190 Rate Adaptive Table Register (offset 0x320, 4 byte) +//---------------------------------------------------------------------------- + +//CCK +#define RATR_1M 0x00000001 +#define RATR_2M 0x00000002 +#define RATR_55M 0x00000004 +#define RATR_11M 0x00000008 +//OFDM +#define RATR_6M 0x00000010 +#define RATR_9M 0x00000020 +#define RATR_12M 0x00000040 +#define RATR_18M 0x00000080 +#define RATR_24M 0x00000100 +#define RATR_36M 0x00000200 +#define RATR_48M 0x00000400 +#define RATR_54M 0x00000800 +//MCS 1 Spatial Stream +#define RATR_MCS0 0x00001000 +#define RATR_MCS1 0x00002000 +#define RATR_MCS2 0x00004000 +#define RATR_MCS3 0x00008000 +#define RATR_MCS4 0x00010000 +#define RATR_MCS5 0x00020000 +#define RATR_MCS6 0x00040000 +#define RATR_MCS7 0x00080000 +//MCS 2 Spatial Stream +#define RATR_MCS8 0x00100000 +#define RATR_MCS9 0x00200000 +#define RATR_MCS10 0x00400000 +#define RATR_MCS11 0x00800000 +#define RATR_MCS12 0x01000000 +#define RATR_MCS13 0x02000000 +#define RATR_MCS14 0x04000000 +#define RATR_MCS15 0x08000000 +// ALL CCK Rate +#define RATE_ALL_CCK RATR_1M|RATR_2M|RATR_55M|RATR_11M +#define RATE_ALL_OFDM_AG RATR_6M|RATR_9M|RATR_12M|RATR_18M|RATR_24M\ + |RATR_36M|RATR_48M|RATR_54M +#define RATE_ALL_OFDM_2SS RATR_MCS8|RATR_MCS9 |RATR_MCS10|RATR_MCS11| \ + RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15 +#endif +/*--------------------------Define Parameters-------------------------------*/ + + +/*------------------------------Define structure----------------------------*/ +/* 2007/10/04 MH Define upper and lower threshold of DIG enable or disable. */ +typedef struct _dynamic_initial_gain_threshold_ +{ + u8 dig_enable_flag; + u8 dig_algorithm; + u8 dbg_mode; + u8 dig_algorithm_switch; + + long rssi_low_thresh; + long rssi_high_thresh; + + long rssi_high_power_lowthresh; + long rssi_high_power_highthresh; + + u8 dig_state; + u8 dig_highpwr_state; + u8 cur_connect_state; + u8 pre_connect_state; + + u8 curpd_thstate; + u8 prepd_thstate; + u8 curcs_ratio_state; + u8 precs_ratio_state; + + u32 pre_ig_value; + u32 cur_ig_value; + + u8 backoff_val; + u8 rx_gain_range_max; + u8 rx_gain_range_min; + bool initialgain_lowerbound_state; + + long rssi_val; +}dig_t; + +typedef enum tag_dynamic_init_gain_state_definition +{ + DM_STA_DIG_OFF = 0, + DM_STA_DIG_ON, + DM_STA_DIG_MAX +}dm_dig_sta_e; + + +/* 2007/10/08 MH Define RATR state. */ +typedef enum tag_dynamic_ratr_state_definition +{ + DM_RATR_STA_HIGH = 0, + DM_RATR_STA_MIDDLE = 1, + DM_RATR_STA_LOW = 2, + DM_RATR_STA_MAX +}dm_ratr_sta_e; + +/* 2007/10/11 MH Define DIG operation type. */ +typedef enum tag_dynamic_init_gain_operation_type_definition +{ + DIG_TYPE_THRESH_HIGH = 0, + DIG_TYPE_THRESH_LOW = 1, + DIG_TYPE_THRESH_HIGHPWR_HIGH = 2, + DIG_TYPE_THRESH_HIGHPWR_LOW = 3, + DIG_TYPE_DBG_MODE = 4, + DIG_TYPE_RSSI = 5, + DIG_TYPE_ALGORITHM = 6, + DIG_TYPE_BACKOFF = 7, + DIG_TYPE_PWDB_FACTOR = 8, + DIG_TYPE_RX_GAIN_MIN = 9, + DIG_TYPE_RX_GAIN_MAX = 10, + DIG_TYPE_ENABLE = 20, + DIG_TYPE_DISABLE = 30, + DIG_OP_TYPE_MAX +}dm_dig_op_e; + +typedef enum tag_dig_algorithm_definition +{ + DIG_ALGO_BY_FALSE_ALARM = 0, + DIG_ALGO_BY_RSSI = 1, + DIG_ALGO_MAX +}dm_dig_alg_e; + +typedef enum tag_dig_dbgmode_definition +{ + DIG_DBG_OFF = 0, + DIG_DBG_ON = 1, + DIG_DBG_MAX +}dm_dig_dbg_e; + +typedef enum tag_dig_connect_definition +{ + DIG_DISCONNECT = 0, + DIG_CONNECT = 1, + DIG_CONNECT_MAX +}dm_dig_connect_e; + +typedef enum tag_dig_packetdetection_threshold_definition +{ + DIG_PD_AT_LOW_POWER = 0, + DIG_PD_AT_NORMAL_POWER = 1, + DIG_PD_AT_HIGH_POWER = 2, + DIG_PD_MAX +}dm_dig_pd_th_e; + +typedef enum tag_dig_cck_cs_ratio_state_definition +{ + DIG_CS_RATIO_LOWER = 0, + DIG_CS_RATIO_HIGHER = 1, + DIG_CS_MAX +}dm_dig_cs_ratio_e; +typedef struct _Dynamic_Rx_Path_Selection_ +{ + u8 Enable; + u8 DbgMode; + u8 cck_method; + u8 cck_Rx_path; + + u8 SS_TH_low; + u8 diff_TH; + u8 disabledRF; + u8 reserved; + + u8 rf_rssi[4]; + u8 rf_enable_rssi_th[4]; + long cck_pwdb_sta[4]; +}DRxPathSel; + +typedef enum tag_CCK_Rx_Path_Method_Definition +{ + CCK_Rx_Version_1 = 0, + CCK_Rx_Version_2= 1, + CCK_Rx_Version_MAX +}DM_CCK_Rx_Path_Method; + +typedef enum tag_DM_DbgMode_Definition +{ + DM_DBG_OFF = 0, + DM_DBG_ON = 1, + DM_DBG_MAX +}DM_DBG_E; + +typedef struct tag_Tx_Config_Cmd_Format +{ + u32 Op; /* Command packet type. */ + u32 Length; /* Command packet length. */ + u32 Value; +}DCMD_TXCMD_T, *PDCMD_TXCMD_T; +/*------------------------------Define structure----------------------------*/ + + +/*------------------------Export global variable----------------------------*/ +extern dig_t dm_digtable; +extern u8 dm_shadow[16][256]; +extern DRxPathSel DM_RxPathSelTable; +/*------------------------Export global variable----------------------------*/ + + +/*------------------------Export Marco Definition---------------------------*/ + +/*------------------------Export Marco Definition---------------------------*/ + + +/*--------------------------Exported Function prototype---------------------*/ +extern void init_hal_dm(struct net_device *dev); +extern void deinit_hal_dm(struct net_device *dev); + +extern void hal_dm_watchdog(struct net_device *dev); + +extern void init_rate_adaptive(struct net_device *dev); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) +extern void dm_txpower_trackingcallback(struct work_struct *work); +#else +extern void dm_txpower_trackingcallback(struct net_device *dev); +#endif +extern void dm_restore_dynamic_mechanism_state(struct net_device *dev); +extern void dm_backup_dynamic_mechanism_state(struct net_device *dev); +extern void dm_change_dynamic_initgain_thresh(struct net_device *dev, + u32 dm_type, u32 dm_value); +extern void dm_force_tx_fw_info(struct net_device *dev,u32 force_type, u32 force_value); +extern void dm_init_edca_turbo(struct net_device *dev); +extern void dm_rf_operation_test_callback(unsigned long data); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) +extern void dm_rf_pathcheck_workitemcallback(struct work_struct *work); +#else +extern void dm_rf_pathcheck_workitemcallback(struct net_device *dev); +#endif +extern void dm_fsync_timer_callback(unsigned long data); +extern void dm_cck_txpower_adjust(struct net_device *dev,bool binch14); +#if 0 +extern char dm_check_lbus_status(IN PADAPTER Adapter); +#endif +extern void dm_shadow_init(struct net_device *dev); +extern void dm_initialize_txpower_tracking(struct net_device *dev); +/*--------------------------Exported Function prototype---------------------*/ + + +#endif /*__R8192UDM_H__ */ + + +/* End of r8192U_dm.h */ + diff --git a/drivers/staging/rtl8192su/r8192U_hw.h b/drivers/staging/rtl8192su/r8192U_hw.h new file mode 100644 index 000000000000..f2500e654a79 --- /dev/null +++ b/drivers/staging/rtl8192su/r8192U_hw.h @@ -0,0 +1,746 @@ +/* + This is part of rtl8187 OpenSource driver. + Copyright (C) Andrea Merello 2004-2005 <andreamrl@tiscali.it> + Released under the terms of GPL (General Public Licence) + + Parts of this driver are based on the GPL part of the + official Realtek driver. + Parts of this driver are based on the rtl8180 driver skeleton + from Patric Schenke & Andres Salomon. + Parts of this driver are based on the Intel Pro Wireless + 2100 GPL driver. + + We want to tanks the Authors of those projects + and the Ndiswrapper project Authors. +*/ + +/* Mariusz Matuszek added full registers definition with Realtek's name */ + +/* this file contains register definitions for the rtl8187 MAC controller */ +#ifndef R8192_HW +#define R8192_HW + +typedef enum _VERSION_819xU{ + VERSION_819xU_A, // A-cut + VERSION_819xU_B, // B-cut + VERSION_819xU_C,// C-cut +}VERSION_819xU,*PVERSION_819xU; +//added for different RF type +typedef enum _RT_RF_TYPE_DEF +{ + RF_1T2R = 0, + RF_2T4R, + + RF_819X_MAX_TYPE +}RT_RF_TYPE_DEF; + + +typedef enum _BaseBand_Config_Type{ + BaseBand_Config_PHY_REG = 0, //Radio Path A + BaseBand_Config_AGC_TAB = 1, //Radio Path B +}BaseBand_Config_Type, *PBaseBand_Config_Type; +#if 0 +typedef enum _RT_RF_TYPE_819xU{ + RF_TYPE_MIN = 0, + RF_8225, + RF_8256, + RF_8258, + RF_PSEUDO_11N = 4, +}RT_RF_TYPE_819xU, *PRT_RF_TYPE_819xU; +#endif +#define RTL8187_REQT_READ 0xc0 +#define RTL8187_REQT_WRITE 0x40 +#define RTL8187_REQ_GET_REGS 0x05 +#define RTL8187_REQ_SET_REGS 0x05 + +#define MAX_TX_URB 16 //less URB will cause 2.4.31 crash, need to fix it further +#define MAX_RX_URB 16 + +#define R8180_MAX_RETRY 255 +//#define MAX_RX_NORMAL_URB 3 +//#define MAX_RX_COMMAND_URB 2 +#define RX_URB_SIZE 9100 + +#define BB_ANTATTEN_CHAN14 0x0c +#define BB_ANTENNA_B 0x40 + +#define BB_HOST_BANG (1<<30) +#define BB_HOST_BANG_EN (1<<2) +#define BB_HOST_BANG_CLK (1<<1) +#define BB_HOST_BANG_RW (1<<3) +#define BB_HOST_BANG_DATA 1 + +//#if (RTL819X_FPGA_VER & RTL819X_FPGA_VIVI_070920) +#define AFR 0x010 +#define AFR_CardBEn (1<<0) +#define AFR_CLKRUN_SEL (1<<1) +#define AFR_FuncRegEn (1<<2) +#define RTL8190_EEPROM_ID 0x8129 +#define EEPROM_VID 0x02 +#define EEPROM_PID 0x04 +#define EEPROM_NODE_ADDRESS_BYTE_0 0x0C + +#define EEPROM_TxPowerDiff 0x1F +#define EEPROM_ThermalMeter 0x20 +#define EEPROM_PwDiff 0x21 //0x21 +#define EEPROM_CrystalCap 0x22 //0x22 + +#define EEPROM_TxPwIndex_CCK 0x23 //0x23 +#define EEPROM_TxPwIndex_OFDM_24G 0x24 //0x24~0x26 +#define EEPROM_TxPwIndex_CCK_V1 0x29 //0x29~0x2B +#define EEPROM_TxPwIndex_OFDM_24G_V1 0x2C //0x2C~0x2E +#define EEPROM_TxPwIndex_Ver 0x27 //0x27 + +#define EEPROM_Default_TxPowerDiff 0x0 +#define EEPROM_Default_ThermalMeter 0x7 +#define EEPROM_Default_PwDiff 0x4 +#define EEPROM_Default_CrystalCap 0x5 +#define EEPROM_Default_TxPower 0x1010 +#define EEPROM_Customer_ID 0x7B //0x7B:CustomerID +#define EEPROM_ChannelPlan 0x16 //0x7C +#define EEPROM_IC_VER 0x7d //0x7D +#define EEPROM_CRC 0x7e //0x7E~0x7F + +#define EEPROM_CID_DEFAULT 0x0 +#define EEPROM_CID_CAMEO 0x1 +#define EEPROM_CID_RUNTOP 0x2 +#define EEPROM_CID_Senao 0x3 +#define EEPROM_CID_TOSHIBA 0x4 // Toshiba setting, Merge by Jacken, 2008/01/31 +#define EEPROM_CID_NetCore 0x5 +#define EEPROM_CID_Nettronix 0x6 +#define EEPROM_CID_Pronet 0x7 +#define EEPROM_CID_DLINK 0x8 + +#define AC_PARAM_TXOP_LIMIT_OFFSET 16 +#define AC_PARAM_ECW_MAX_OFFSET 12 +#define AC_PARAM_ECW_MIN_OFFSET 8 +#define AC_PARAM_AIFS_OFFSET 0 + +//#endif +enum _RTL8192Usb_HW { + + PCIF = 0x009, // PCI Function Register 0x0009h~0x000bh +#define BB_GLOBAL_RESET_BIT 0x1 + BB_GLOBAL_RESET = 0x020, // BasebandGlobal Reset Register + BSSIDR = 0x02E, // BSSID Register + CMDR = 0x037, // Command register +#define CR_RST 0x10 +#define CR_RE 0x08 +#define CR_TE 0x04 +#define CR_MulRW 0x01 + SIFS = 0x03E, // SIFS register + TCR = 0x040, // Transmit Configuration Register + +#define TCR_MXDMA_2048 7 +#define TCR_LRL_OFFSET 0 +#define TCR_SRL_OFFSET 8 +#define TCR_MXDMA_OFFSET 21 +#define TCR_SAT BIT24 // Enable Rate depedent ack timeout timer + RCR = 0x044, // Receive Configuration Register +#define MAC_FILTER_MASK ((1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<5) | \ + (1<<12) | (1<<18) | (1<<19) | (1<<20) | (1<<21) | (1<<22) | (1<<23)) +#define RX_FIFO_THRESHOLD_MASK ((1<<13) | (1<<14) | (1<<15)) +#define RX_FIFO_THRESHOLD_SHIFT 13 +#define RX_FIFO_THRESHOLD_128 3 +#define RX_FIFO_THRESHOLD_256 4 +#define RX_FIFO_THRESHOLD_512 5 +#define RX_FIFO_THRESHOLD_1024 6 +#define RX_FIFO_THRESHOLD_NONE 7 +#define MAX_RX_DMA_MASK ((1<<8) | (1<<9) | (1<<10)) +#define RCR_MXDMA_OFFSET 8 +#define RCR_FIFO_OFFSET 13 +#define RCR_ONLYERLPKT BIT31 // Early Receiving based on Packet Size. +#define RCR_ENCS2 BIT30 // Enable Carrier Sense Detection Method 2 +#define RCR_ENCS1 BIT29 // Enable Carrier Sense Detection Method 1 +#define RCR_ENMBID BIT27 // Enable Multiple BssId. +#define RCR_ACKTXBW (BIT24|BIT25) // TXBW Setting of ACK frames +#define RCR_CBSSID BIT23 // Accept BSSID match packet +#define RCR_APWRMGT BIT22 // Accept power management packet +#define RCR_ADD3 BIT21 // Accept address 3 match packet +#define RCR_AMF BIT20 // Accept management type frame +#define RCR_ACF BIT19 // Accept control type frame +#define RCR_ADF BIT18 // Accept data type frame +#define RCR_RXFTH BIT13 // Rx FIFO Threshold +#define RCR_AICV BIT12 // Accept ICV error packet +#define RCR_ACRC32 BIT5 // Accept CRC32 error packet +#define RCR_AB BIT3 // Accept broadcast packet +#define RCR_AM BIT2 // Accept multicast packet +#define RCR_APM BIT1 // Accept physical match packet +#define RCR_AAP BIT0 // Accept all unicast packet + SLOT_TIME = 0x049, // Slot Time Register + ACK_TIMEOUT = 0x04c, // Ack Timeout Register + PIFS_TIME = 0x04d, // PIFS time + USTIME = 0x04e, // Microsecond Tuning Register, Sets the microsecond time unit used by MAC clock. + EDCAPARA_BE = 0x050, // EDCA Parameter of AC BE + EDCAPARA_BK = 0x054, // EDCA Parameter of AC BK + EDCAPARA_VO = 0x058, // EDCA Parameter of AC VO + EDCAPARA_VI = 0x05C, // EDCA Parameter of AC VI + RFPC = 0x05F, // Rx FIFO Packet Count + CWRR = 0x060, // Contention Window Report Register + BCN_TCFG = 0x062, // Beacon Time Configuration +#define BCN_TCFG_CW_SHIFT 8 +#define BCN_TCFG_IFS 0 + BCN_INTERVAL = 0x070, // Beacon Interval (TU) + ATIMWND = 0x072, // ATIM Window Size (TU) + BCN_DRV_EARLY_INT = 0x074, // Driver Early Interrupt Time (TU). Time to send interrupt to notify to change beacon content before TBTT + BCN_DMATIME = 0x076, // Beacon DMA and ATIM interrupt time (US). Indicates the time before TBTT to perform beacon queue DMA + BCN_ERR_THRESH = 0x078, // Beacon Error Threshold + RWCAM = 0x0A0, //IN 8190 Data Sheet is called CAMcmd + WCAMI = 0x0A4, // Software write CAM input content + RCAMO = 0x0A8, // Software read/write CAM config + SECR = 0x0B0, //Security Configuration Register +#define SCR_TxUseDK BIT0 //Force Tx Use Default Key +#define SCR_RxUseDK BIT1 //Force Rx Use Default Key +#define SCR_TxEncEnable BIT2 //Enable Tx Encryption +#define SCR_RxDecEnable BIT3 //Enable Rx Decryption +#define SCR_SKByA2 BIT4 //Search kEY BY A2 +#define SCR_NoSKMC BIT5 //No Key Search for Multicast +#define SCR_UseDK 0x01 +#define SCR_TxSecEnable 0x02 +#define SCR_RxSecEnable 0x04 + TPPoll = 0x0fd, // Transmit priority polling register + PSR = 0x0ff, // Page Select Register +#define CPU_CCK_LOOPBACK 0x00030000 +#define CPU_GEN_SYSTEM_RESET 0x00000001 +#define CPU_GEN_FIRMWARE_RESET 0x00000008 +#define CPU_GEN_BOOT_RDY 0x00000010 +#define CPU_GEN_FIRM_RDY 0x00000020 +#define CPU_GEN_PUT_CODE_OK 0x00000080 +#define CPU_GEN_BB_RST 0x00000100 +#define CPU_GEN_PWR_STB_CPU 0x00000004 +#define CPU_GEN_NO_LOOPBACK_MSK 0xFFF8FFFF // Set bit18,17,16 to 0. Set bit19 +#define CPU_GEN_NO_LOOPBACK_SET 0x00080000 // Set BIT19 to 1 + +//---------------------------------------------------------------------------- +// 8190 CPU General Register (offset 0x100, 4 byte) +//---------------------------------------------------------------------------- +#define CPU_CCK_LOOPBACK 0x00030000 +#define CPU_GEN_SYSTEM_RESET 0x00000001 +#define CPU_GEN_FIRMWARE_RESET 0x00000008 +#define CPU_GEN_BOOT_RDY 0x00000010 +#define CPU_GEN_FIRM_RDY 0x00000020 +#define CPU_GEN_PUT_CODE_OK 0x00000080 +#define CPU_GEN_BB_RST 0x00000100 +#define CPU_GEN_PWR_STB_CPU 0x00000004 +#define CPU_GEN_NO_LOOPBACK_MSK 0xFFF8FFFF // Set bit18,17,16 to 0. Set bit19 +#define CPU_GEN_NO_LOOPBACK_SET 0x00080000 // Set BIT19 to 1 + CPU_GEN = 0x100, // CPU Reset Register + LED1Cfg = 0x154,// LED1 Configuration Register + LED0Cfg = 0x155,// LED0 Configuration Register + + AcmAvg = 0x170, // ACM Average Period Register + AcmHwCtrl = 0x171, // ACM Hardware Control Register +//---------------------------------------------------------------------------- +//// +//// 8190 AcmHwCtrl bits (offset 0x171, 1 byte) +////---------------------------------------------------------------------------- +// +#define AcmHw_HwEn BIT0 +#define AcmHw_BeqEn BIT1 +#define AcmHw_ViqEn BIT2 +#define AcmHw_VoqEn BIT3 +#define AcmHw_BeqStatus BIT4 +#define AcmHw_ViqStatus BIT5 +#define AcmHw_VoqStatus BIT6 + + AcmFwCtrl = 0x172, // ACM Firmware Control Register + AES_11N_FIX = 0x173, + VOAdmTime = 0x174, // VO Queue Admitted Time Register + VIAdmTime = 0x178, // VI Queue Admitted Time Register + BEAdmTime = 0x17C, // BE Queue Admitted Time Register + RQPN1 = 0x180, // Reserved Queue Page Number , Vo Vi, Be, Bk + RQPN2 = 0x184, // Reserved Queue Page Number, HCCA, Cmd, Mgnt, High + RQPN3 = 0x188, // Reserved Queue Page Number, Bcn, Public, +// QPRR = 0x1E0, // Queue Page Report per TID + QPNR = 0x1D0, //0x1F0, // Queue Packet Number report per TID + BQDA = 0x200, // Beacon Queue Descriptor Address + HQDA = 0x204, // High Priority Queue Descriptor Address + CQDA = 0x208, // Command Queue Descriptor Address + MQDA = 0x20C, // Management Queue Descriptor Address + HCCAQDA = 0x210, // HCCA Queue Descriptor Address + VOQDA = 0x214, // VO Queue Descriptor Address + VIQDA = 0x218, // VI Queue Descriptor Address + BEQDA = 0x21C, // BE Queue Descriptor Address + BKQDA = 0x220, // BK Queue Descriptor Address + RCQDA = 0x224, // Receive command Queue Descriptor Address + RDQDA = 0x228, // Receive Queue Descriptor Start Address + + MAR0 = 0x240, // Multicast filter. + MAR4 = 0x244, + + CCX_PERIOD = 0x250, // CCX Measurement Period Register, in unit of TU. + CLM_RESULT = 0x251, // CCA Busy fraction register. + NHM_PERIOD = 0x252, // NHM Measurement Period register, in unit of TU. + + NHM_THRESHOLD0 = 0x253, // Noise Histogram Meashorement0. + NHM_THRESHOLD1 = 0x254, // Noise Histogram Meashorement1. + NHM_THRESHOLD2 = 0x255, // Noise Histogram Meashorement2. + NHM_THRESHOLD3 = 0x256, // Noise Histogram Meashorement3. + NHM_THRESHOLD4 = 0x257, // Noise Histogram Meashorement4. + NHM_THRESHOLD5 = 0x258, // Noise Histogram Meashorement5. + NHM_THRESHOLD6 = 0x259, // Noise Histogram Meashorement6 + + MCTRL = 0x25A, // Measurement Control + + NHM_RPI_COUNTER0 = 0x264, // Noise Histogram RPI counter0, the fraction of signal strength < NHM_THRESHOLD0. + NHM_RPI_COUNTER1 = 0x265, // Noise Histogram RPI counter1, the fraction of signal strength in (NHM_THRESHOLD0, NHM_THRESHOLD1]. + NHM_RPI_COUNTER2 = 0x266, // Noise Histogram RPI counter2, the fraction of signal strength in (NHM_THRESHOLD1, NHM_THRESHOLD2]. + NHM_RPI_COUNTER3 = 0x267, // Noise Histogram RPI counter3, the fraction of signal strength in (NHM_THRESHOLD2, NHM_THRESHOLD3]. + NHM_RPI_COUNTER4 = 0x268, // Noise Histogram RPI counter4, the fraction of signal strength in (NHM_THRESHOLD3, NHM_THRESHOLD4]. + NHM_RPI_COUNTER5 = 0x269, // Noise Histogram RPI counter5, the fraction of signal strength in (NHM_THRESHOLD4, NHM_THRESHOLD5]. + NHM_RPI_COUNTER6 = 0x26A, // Noise Histogram RPI counter6, the fraction of signal strength in (NHM_THRESHOLD5, NHM_THRESHOLD6]. + NHM_RPI_COUNTER7 = 0x26B, // Noise Histogram RPI counter7, the fraction of signal strength in (NHM_THRESHOLD6, NHM_THRESHOLD7]. +#define BW_OPMODE_11J BIT0 +#define BW_OPMODE_5G BIT1 +#define BW_OPMODE_20MHZ BIT2 + BW_OPMODE = 0x300, // Bandwidth operation mode + MSR = 0x303, // Media Status register +#define MSR_LINK_MASK ((1<<0)|(1<<1)) +#define MSR_LINK_MANAGED 2 +#define MSR_LINK_NONE 0 +#define MSR_LINK_SHIFT 0 +#define MSR_LINK_ADHOC 1 +#define MSR_LINK_MASTER 3 +#define MSR_LINK_ENEDCA (1<<4) + RETRY_LIMIT = 0x304, // Retry Limit [15:8]-short, [7:0]-long +#define RETRY_LIMIT_SHORT_SHIFT 8 +#define RETRY_LIMIT_LONG_SHIFT 0 + TSFR = 0x308, + RRSR = 0x310, // Response Rate Set +#define RRSR_RSC_OFFSET 21 +#define RRSR_SHORT_OFFSET 23 +#define RRSR_RSC_DUPLICATE 0x600000 +#define RRSR_RSC_LOWSUBCHNL 0x400000 +#define RRSR_RSC_UPSUBCHANL 0x200000 +#define RRSR_SHORT 0x800000 +#define RRSR_1M BIT0 +#define RRSR_2M BIT1 +#define RRSR_5_5M BIT2 +#define RRSR_11M BIT3 +#define RRSR_6M BIT4 +#define RRSR_9M BIT5 +#define RRSR_12M BIT6 +#define RRSR_18M BIT7 +#define RRSR_24M BIT8 +#define RRSR_36M BIT9 +#define RRSR_48M BIT10 +#define RRSR_54M BIT11 +#define RRSR_MCS0 BIT12 +#define RRSR_MCS1 BIT13 +#define RRSR_MCS2 BIT14 +#define RRSR_MCS3 BIT15 +#define RRSR_MCS4 BIT16 +#define RRSR_MCS5 BIT17 +#define RRSR_MCS6 BIT18 +#define RRSR_MCS7 BIT19 +#define BRSR_AckShortPmb BIT23 // CCK ACK: use Short Preamble or not. + RATR0 = 0x320, // Rate Adaptive Table register1 + UFWP = 0x318, + DRIVER_RSSI = 0x32c, // Driver tell Firmware current RSSI +//---------------------------------------------------------------------------- +// 8190 Rate Adaptive Table Register (offset 0x320, 4 byte) +//---------------------------------------------------------------------------- +//CCK +#define RATR_1M 0x00000001 +#define RATR_2M 0x00000002 +#define RATR_55M 0x00000004 +#define RATR_11M 0x00000008 +//OFDM +#define RATR_6M 0x00000010 +#define RATR_9M 0x00000020 +#define RATR_12M 0x00000040 +#define RATR_18M 0x00000080 +#define RATR_24M 0x00000100 +#define RATR_36M 0x00000200 +#define RATR_48M 0x00000400 +#define RATR_54M 0x00000800 +//MCS 1 Spatial Stream +#define RATR_MCS0 0x00001000 +#define RATR_MCS1 0x00002000 +#define RATR_MCS2 0x00004000 +#define RATR_MCS3 0x00008000 +#define RATR_MCS4 0x00010000 +#define RATR_MCS5 0x00020000 +#define RATR_MCS6 0x00040000 +#define RATR_MCS7 0x00080000 +//MCS 2 Spatial Stream +#define RATR_MCS8 0x00100000 +#define RATR_MCS9 0x00200000 +#define RATR_MCS10 0x00400000 +#define RATR_MCS11 0x00800000 +#define RATR_MCS12 0x01000000 +#define RATR_MCS13 0x02000000 +#define RATR_MCS14 0x04000000 +#define RATR_MCS15 0x08000000 +// ALL CCK Rate +#define RATE_ALL_CCK RATR_1M|RATR_2M|RATR_55M|RATR_11M +#define RATE_ALL_OFDM_AG RATR_6M|RATR_9M|RATR_12M|RATR_18M|RATR_24M\ + |RATR_36M|RATR_48M|RATR_54M +#define RATE_ALL_OFDM_1SS RATR_MCS0|RATR_MCS1|RATR_MCS2|RATR_MCS3 | \ + RATR_MCS4|RATR_MCS5|RATR_MCS6|RATR_MCS7 +#define RATE_ALL_OFDM_2SS RATR_MCS8|RATR_MCS9 |RATR_MCS10|RATR_MCS11| \ + RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15 + + MCS_TXAGC = 0x340, // MCS AGC + CCK_TXAGC = 0x348, // CCK AGC +// ISR = 0x350, // Interrupt Status Register +// IMR = 0x354, // Interrupt Mask Register +// IMR_POLL = 0x360, + MacBlkCtrl = 0x403, // Mac block on/off control register + + EPROM_CMD = 0xfe58, +#define Cmd9346CR_9356SEL (1<<4) +#define EPROM_CMD_RESERVED_MASK (1<<5) +#define EPROM_CMD_OPERATING_MODE_SHIFT 6 +#define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6)) +#define EPROM_CMD_CONFIG 0x3 +#define EPROM_CMD_NORMAL 0 +#define EPROM_CMD_LOAD 1 +#define EPROM_CMD_PROGRAM 2 +#define EPROM_CS_SHIFT 3 +#define EPROM_CK_SHIFT 2 +#define EPROM_W_SHIFT 1 +#define EPROM_R_SHIFT 0 + MAC0 = 0x000, + MAC1 = 0x001, + MAC2 = 0x002, + MAC3 = 0x003, + MAC4 = 0x004, + MAC5 = 0x005, + +#if 0 +/* 0x0006 - 0x0007 - reserved */ + RXFIFOCOUNT = 0x010, + TXFIFOCOUNT = 0x012, + BQREQ = 0x013, +/* 0x0010 - 0x0017 - reserved */ + TSFTR = 0x018, + TLPDA = 0x020, + TNPDA = 0x024, + THPDA = 0x028, + BSSID = 0x02E, + RESP_RATE = 0x034, + CMD = 0x037, +#define CMD_RST_SHIFT 4 +#define CMD_RESERVED_MASK ((1<<1) | (1<<5) | (1<<6) | (1<<7)) +#define CMD_RX_ENABLE_SHIFT 3 +#define CMD_TX_ENABLE_SHIFT 2 +#define CR_RST ((1<< 4)) +#define CR_RE ((1<< 3)) +#define CR_TE ((1<< 2)) +#define CR_MulRW ((1<< 0)) + + INTA_MASK = 0x03c, + INTA = 0x03e, +#define INTA_TXOVERFLOW (1<<15) +#define INTA_TIMEOUT (1<<14) +#define INTA_BEACONTIMEOUT (1<<13) +#define INTA_ATIM (1<<12) +#define INTA_BEACONDESCERR (1<<11) +#define INTA_BEACONDESCOK (1<<10) +#define INTA_HIPRIORITYDESCERR (1<<9) +#define INTA_HIPRIORITYDESCOK (1<<8) +#define INTA_NORMPRIORITYDESCERR (1<<7) +#define INTA_NORMPRIORITYDESCOK (1<<6) +#define INTA_RXOVERFLOW (1<<5) +#define INTA_RXDESCERR (1<<4) +#define INTA_LOWPRIORITYDESCERR (1<<3) +#define INTA_LOWPRIORITYDESCOK (1<<2) +#define INTA_RXCRCERR (1<<1) +#define INTA_RXOK (1) + TX_CONF = 0x040, +#define TX_CONF_HEADER_AUTOICREMENT_SHIFT 30 +#define TX_LOOPBACK_SHIFT 17 +#define TX_LOOPBACK_MAC 1 +#define TX_LOOPBACK_BASEBAND 2 +#define TX_LOOPBACK_NONE 0 +#define TX_LOOPBACK_CONTINUE 3 +#define TX_LOOPBACK_MASK ((1<<17)|(1<<18)) +#define TX_LRLRETRY_SHIFT 0 +#define TX_SRLRETRY_SHIFT 8 +#define TX_NOICV_SHIFT 19 +#define TX_NOCRC_SHIFT 16 +#define TCR_DurProcMode ((1<<30)) +#define TCR_DISReqQsize ((1<<28)) +#define TCR_HWVERID_MASK ((1<<27)|(1<<26)|(1<<25)) +#define TCR_HWVERID_SHIFT 25 +#define TCR_SWPLCPLEN ((1<<24)) +#define TCR_PLCP_LEN TCR_SAT // rtl8180 +#define TCR_MXDMA_MASK ((1<<23)|(1<<22)|(1<<21)) +#define TCR_MXDMA_1024 6 +#define TCR_MXDMA_2048 7 +#define TCR_MXDMA_SHIFT 21 +#define TCR_DISCW ((1<<20)) +#define TCR_ICV ((1<<19)) +#define TCR_LBK ((1<<18)|(1<<17)) +#define TCR_LBK1 ((1<<18)) +#define TCR_LBK0 ((1<<17)) +#define TCR_CRC ((1<<16)) +#define TCR_SRL_MASK ((1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(1<<10)|(1<<9)|(1<<8)) +#define TCR_LRL_MASK ((1<<0)|(1<<1)|(1<<2)|(1<<3)|(1<<4)|(1<<5)|(1<<6)|(1<<7)) +#define TCR_PROBE_NOTIMESTAMP_SHIFT 29 //rtl8185 + RX_CONF = 0x044, +#define MAC_FILTER_MASK ((1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<5) | \ +(1<<12) | (1<<18) | (1<<19) | (1<<20) | (1<<21) | (1<<22) | (1<<23)) +#define RX_CHECK_BSSID_SHIFT 23 +#define ACCEPT_PWR_FRAME_SHIFT 22 +#define ACCEPT_MNG_FRAME_SHIFT 20 +#define ACCEPT_CTL_FRAME_SHIFT 19 +#define ACCEPT_DATA_FRAME_SHIFT 18 +#define ACCEPT_ICVERR_FRAME_SHIFT 12 +#define ACCEPT_CRCERR_FRAME_SHIFT 5 +#define ACCEPT_BCAST_FRAME_SHIFT 3 +#define ACCEPT_MCAST_FRAME_SHIFT 2 +#define ACCEPT_ALLMAC_FRAME_SHIFT 0 +#define ACCEPT_NICMAC_FRAME_SHIFT 1 +#define RX_FIFO_THRESHOLD_MASK ((1<<13) | (1<<14) | (1<<15)) +#define RX_FIFO_THRESHOLD_SHIFT 13 +#define RX_FIFO_THRESHOLD_128 3 +#define RX_FIFO_THRESHOLD_256 4 +#define RX_FIFO_THRESHOLD_512 5 +#define RX_FIFO_THRESHOLD_1024 6 +#define RX_FIFO_THRESHOLD_NONE 7 +#define RX_AUTORESETPHY_SHIFT 28 +#define MAX_RX_DMA_MASK ((1<<8) | (1<<9) | (1<<10)) +#define MAX_RX_DMA_2048 7 +#define MAX_RX_DMA_1024 6 +#define MAX_RX_DMA_SHIFT 10 +#define RCR_ONLYERLPKT ((1<<31)) +#define RCR_CS_SHIFT 29 +#define RCR_CS_MASK ((1<<30) | (1<<29)) +#define RCR_ENMARP ((1<<28)) +#define RCR_CBSSID ((1<<23)) +#define RCR_APWRMGT ((1<<22)) +#define RCR_ADD3 ((1<<21)) +#define RCR_AMF ((1<<20)) +#define RCR_ACF ((1<<19)) +#define RCR_ADF ((1<<18)) +#define RCR_RXFTH ((1<<15)|(1<<14)|(1<<13)) +#define RCR_RXFTH2 ((1<<15)) +#define RCR_RXFTH1 ((1<<14)) +#define RCR_RXFTH0 ((1<<13)) +#define RCR_AICV ((1<<12)) +#define RCR_MXDMA ((1<<10)|(1<< 9)|(1<< 8)) +#define RCR_MXDMA2 ((1<<10)) +#define RCR_MXDMA1 ((1<< 9)) +#define RCR_MXDMA0 ((1<< 8)) +#define RCR_9356SEL ((1<< 6)) +#define RCR_ACRC32 ((1<< 5)) +#define RCR_AB ((1<< 3)) +#define RCR_AM ((1<< 2)) +#define RCR_APM ((1<< 1)) +#define RCR_AAP ((1<< 0)) + INT_TIMEOUT = 0x048, + TX_BEACON_RING_ADDR = 0x04c, + EPROM_CMD = 0x58, +#define EPROM_CMD_RESERVED_MASK ((1<<5)|(1<<4)) +#define EPROM_CMD_OPERATING_MODE_SHIFT 6 +#define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6)) +#define EPROM_CMD_CONFIG 0x3 +#define EPROM_CMD_NORMAL 0 +#define EPROM_CMD_LOAD 1 +#define EPROM_CMD_PROGRAM 2 +#define EPROM_CS_SHIFT 3 +#define EPROM_CK_SHIFT 2 +#define EPROM_W_SHIFT 1 +#define EPROM_R_SHIFT 0 + CONFIG0 = 0x051, +#define CONFIG0_WEP104 ((1<<6)) +#define CONFIG0_LEDGPO_En ((1<<4)) +#define CONFIG0_Aux_Status ((1<<3)) +#define CONFIG0_GL ((1<<1)|(1<<0)) +#define CONFIG0_GL1 ((1<<1)) +#define CONFIG0_GL0 ((1<<0)) + CONFIG1 = 0x052, +#define CONFIG1_LEDS ((1<<7)|(1<<6)) +#define CONFIG1_LEDS1 ((1<<7)) +#define CONFIG1_LEDS0 ((1<<6)) +#define CONFIG1_LWACT ((1<<4)) +#define CONFIG1_MEMMAP ((1<<3)) +#define CONFIG1_IOMAP ((1<<2)) +#define CONFIG1_VPD ((1<<1)) +#define CONFIG1_PMEn ((1<<0)) + CONFIG2 = 0x053, +#define CONFIG2_LCK ((1<<7)) +#define CONFIG2_ANT ((1<<6)) +#define CONFIG2_DPS ((1<<3)) +#define CONFIG2_PAPE_sign ((1<<2)) +#define CONFIG2_PAPE_time ((1<<1)|(1<<0)) +#define CONFIG2_PAPE_time1 ((1<<1)) +#define CONFIG2_PAPE_time0 ((1<<0)) + ANA_PARAM = 0x054, + CONFIG3 = 0x059, +#define CONFIG3_GNTSel ((1<<7)) +#define CONFIG3_PARM_En ((1<<6)) +#define CONFIG3_Magic ((1<<5)) +#define CONFIG3_CardB_En ((1<<3)) +#define CONFIG3_CLKRUN_En ((1<<2)) +#define CONFIG3_FuncRegEn ((1<<1)) +#define CONFIG3_FBtbEn ((1<<0)) +#define CONFIG3_CLKRUN_SHIFT 2 +#define CONFIG3_ANAPARAM_W_SHIFT 6 + CONFIG4 = 0x05a, +#define CONFIG4_VCOPDN ((1<<7)) +#define CONFIG4_PWROFF ((1<<6)) +#define CONFIG4_PWRMGT ((1<<5)) +#define CONFIG4_LWPME ((1<<4)) +#define CONFIG4_LWPTN ((1<<2)) +#define CONFIG4_RFTYPE ((1<<1)|(1<<0)) +#define CONFIG4_RFTYPE1 ((1<<1)) +#define CONFIG4_RFTYPE0 ((1<<0)) + TESTR = 0x05b, +#define TFPC_AC 0x05C + +#define SCR 0x05F + PGSELECT = 0x05e, +#define PGSELECT_PG_SHIFT 0 + SECURITY = 0x05f, +#define SECURITY_WEP_TX_ENABLE_SHIFT 1 +#define SECURITY_WEP_RX_ENABLE_SHIFT 0 +#define SECURITY_ENCRYP_104 1 +#define SECURITY_ENCRYP_SHIFT 4 +#define SECURITY_ENCRYP_MASK ((1<<4)|(1<<5)) + ANA_PARAM2 = 0x060, + BEACON_INTERVAL = 0x070, +#define BEACON_INTERVAL_MASK ((1<<0)|(1<<1)|(1<<2)|(1<<3)|(1<<4)|(1<<5)| \ +(1<<6)|(1<<7)|(1<<8)|(1<<9)) + ATIM_WND = 0x072, +#define ATIM_WND_MASK (0x01FF) + BCN_INTR_ITV = 0x074, +#define BCN_INTR_ITV_MASK (0x01FF) + ATIM_INTR_ITV = 0x076, +#define ATIM_INTR_ITV_MASK (0x01FF) + AckTimeOutReg = 0x079, //ACK timeout register, in unit of 4 us. + PHY_ADR = 0x07c, + PHY_READ = 0x07e, + RFPinsOutput = 0x080, + RFPinsEnable = 0x082, + +//Page 0 + RFPinsSelect = 0x084, +#define SW_CONTROL_GPIO 0x400 + RFPinsInput = 0x086, + RF_PARA = 0x088, + RF_TIMING = 0x08c, + GP_ENABLE = 0x090, + GPIO = 0x091, + TX_AGC_CTL = 0x09c, +#define TX_AGC_CTL_PER_PACKET_TXAGC 0x01 +#define TX_AGC_CTL_PERPACKET_GAIN_SHIFT 0 +#define TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT 1 +#define TX_AGC_CTL_FEEDBACK_ANT 2 +#define TXAGC_CTL_PER_PACKET_ANT_SEL 0x02 + OFDM_TXAGC = 0x09e, + ANTSEL = 0x09f, + WPA_CONFIG = 0x0b0, + SIFS = 0x0b4, + DIFS = 0x0b5, + SLOT = 0x0b6, + CW_CONF = 0x0bc, +#define CW_CONF_PERPACKET_RETRY_LIMIT 0x02 +#define CW_CONF_PERPACKET_CW 0x01 +#define CW_CONF_PERPACKET_RETRY_SHIFT 1 +#define CW_CONF_PERPACKET_CW_SHIFT 0 + CW_VAL = 0x0bd, + RATE_FALLBACK = 0x0be, +#define MAX_RESP_RATE_SHIFT 4 +#define MIN_RESP_RATE_SHIFT 0 +#define RATE_FALLBACK_CTL_ENABLE 0x80 +#define RATE_FALLBACK_CTL_AUTO_STEP0 0x00 + ACM_CONTROL = 0x0BF, // ACM Control Registe +//---------------------------------------------------------------------------- +// 8187B ACM_CONTROL bits (Offset 0xBF, 1 Byte) +//---------------------------------------------------------------------------- +#define VOQ_ACM_EN (0x01 << 7) //BIT7 +#define VIQ_ACM_EN (0x01 << 6) //BIT6 +#define BEQ_ACM_EN (0x01 << 5) //BIT5 +#define ACM_HW_EN (0x01 << 4) //BIT4 +#define TXOPSEL (0x01 << 3) //BIT3 +#define VOQ_ACM_CTL (0x01 << 2) //BIT2 // Set to 1 when AC_VO used time reaches or exceeds the admitted time +#define VIQ_ACM_CTL (0x01 << 1) //BIT1 // Set to 1 when AC_VI used time reaches or exceeds the admitted time +#define BEQ_ACM_CTL (0x01 << 0) //BIT0 // Set to 1 when AC_BE used time reaches or exceeds the admitted time + CONFIG5 = 0x0D8, +#define CONFIG5_TX_FIFO_OK ((1<<7)) +#define CONFIG5_RX_FIFO_OK ((1<<6)) +#define CONFIG5_CALON ((1<<5)) +#define CONFIG5_EACPI ((1<<2)) +#define CONFIG5_LANWake ((1<<1)) +#define CONFIG5_PME_STS ((1<<0)) + TX_DMA_POLLING = 0x0d9, +#define TX_DMA_POLLING_BEACON_SHIFT 7 +#define TX_DMA_POLLING_HIPRIORITY_SHIFT 6 +#define TX_DMA_POLLING_NORMPRIORITY_SHIFT 5 +#define TX_DMA_POLLING_LOWPRIORITY_SHIFT 4 +#define TX_DMA_STOP_BEACON_SHIFT 3 +#define TX_DMA_STOP_HIPRIORITY_SHIFT 2 +#define TX_DMA_STOP_NORMPRIORITY_SHIFT 1 +#define TX_DMA_STOP_LOWPRIORITY_SHIFT 0 + CWR = 0x0DC, + RetryCTR = 0x0DE, + INT_MIG = 0x0E2, // Interrupt Migration (0xE2 ~ 0xE3) + TID_AC_MAP = 0x0E8, // TID to AC Mapping Register + ANA_PARAM3 = 0x0EE, + + +//page 1 + Wakeup0 = 0x084, + Wakeup1 = 0x08C, + Wakeup2LD = 0x094, + Wakeup2HD = 0x09C, + Wakeup3LD = 0x0A4, + Wakeup3HD = 0x0AC, + Wakeup4LD = 0x0B4, + Wakeup4HD = 0x0BC, + CRC0 = 0x0C4, + CRC1 = 0x0C6, + CRC2 = 0x0C8, + CRC3 = 0x0CA, + CRC4 = 0x0CC, +/* 0x00CE - 0x00D3 - reserved */ + + RFSW_CTRL = 0x272, // 0x272-0x273. + +//Reg Diff between rtl8187 and rtl8187B +/**************************************************************************/ + BRSR_8187 = 0x02C, + BRSR_8187B = 0x034, +#define BRSR_BPLCP ((1<< 8)) +#define BRSR_MBR ((1<< 1)|(1<< 0)) +#define BRSR_MBR_8185 ((1<< 11)|(1<< 10)|(1<< 9)|(1<< 8)|(1<< 7)|(1<< 6)|(1<< 5)|(1<< 4)|(1<< 3)|(1<< 2)|(1<< 1)|(1<< 0)) +#define BRSR_MBR0 ((1<< 0)) +#define BRSR_MBR1 ((1<< 1)) + +/**************************************************************************/ + EIFS_8187 = 0x035, + EIFS_8187B = 0x02D, + +/**************************************************************************/ + FER = 0x0F0, + FEMR = 0x0F4, + FPSR = 0x0F8, + FFER = 0x0FC, + + AC_VO_PARAM = 0x0F0, // AC_VO Parameters Record + AC_VI_PARAM = 0x0F4, // AC_VI Parameters Record + AC_BE_PARAM = 0x0F8, // AC_BE Parameters Record + AC_BK_PARAM = 0x0FC, // AC_BK Parameters Record + TALLY_SEL = 0x0fc, +//---------------------------------------------------------------------------- +// 8187B AC_XX_PARAM bits +//---------------------------------------------------------------------------- +#define AC_PARAM_TXOP_LIMIT_OFFSET 16 +#define AC_PARAM_ECW_MAX_OFFSET 12 +#define AC_PARAM_ECW_MIN_OFFSET 8 +#define AC_PARAM_AIFS_OFFSET 0 + +#endif +}; +//---------------------------------------------------------------------------- +// 818xB AnaParm & AnaParm2 Register +//---------------------------------------------------------------------------- +//#define ANAPARM_ASIC_ON 0x45090658 +//#define ANAPARM2_ASIC_ON 0x727f3f52 +#define GPI 0x108 +#define GPO 0x109 +#define GPE 0x10a +#endif diff --git a/drivers/staging/rtl8192su/r8192U_pm.c b/drivers/staging/rtl8192su/r8192U_pm.c new file mode 100644 index 000000000000..92c95aa36638 --- /dev/null +++ b/drivers/staging/rtl8192su/r8192U_pm.c @@ -0,0 +1,77 @@ +/* + Power management interface routines. + Written by Mariusz Matuszek. + This code is currently just a placeholder for later work and + does not do anything useful. + + This is part of rtl8180 OpenSource driver. + Copyright (C) Andrea Merello 2004 <andreamrl@tiscali.it> + Released under the terms of GPL (General Public Licence) +*/ + +#ifdef CONFIG_RTL8192_PM +#include "r8192U.h" +#include "r8192U_pm.h" + +/*****************************************************************************/ +int rtl8192U_save_state (struct pci_dev *dev, u32 state) +{ + printk(KERN_NOTICE "r8192U save state call (state %u).\n", state); + return(-EAGAIN); +} + +int rtl8192U_suspend(struct usb_interface *intf, pm_message_t state) +{ +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + struct net_device *dev = usb_get_intfdata(intf); +#else + //struct net_device *dev = (struct net_device *)ptr; +#endif + RT_TRACE(COMP_POWER, "============> r8192U suspend call.\n"); + + if(dev) { + if (!netif_running(dev)) { + printk(KERN_WARNING "netif not running, go out suspend function\n"); + return 0; + } + + dev->stop(dev); + mdelay(10); + + netif_device_detach(dev); + } + + return 0; +} + +int rtl8192U_resume (struct usb_interface *intf) +{ +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + struct net_device *dev = usb_get_intfdata(intf); +#else + //struct net_device *dev = (struct net_device *)ptr; +#endif + + RT_TRACE(COMP_POWER, "================>r8192U resume call."); + + if(dev) { + if (!netif_running(dev)){ + printk(KERN_WARNING "netif not running, go out resume function\n"); + return 0; + } + + netif_device_attach(dev); + dev->open(dev); + } + + return 0; +} + +int rtl8192U_enable_wake (struct pci_dev *dev, u32 state, int enable) +{ + printk(KERN_NOTICE "r8192U enable wake call (state %u, enable %d).\n", + state, enable); + return(-EAGAIN); +} + +#endif //CONFIG_RTL8192_PM diff --git a/drivers/staging/rtl8192su/r8192U_pm.h b/drivers/staging/rtl8192su/r8192U_pm.h new file mode 100644 index 000000000000..ab025d64f5e2 --- /dev/null +++ b/drivers/staging/rtl8192su/r8192U_pm.h @@ -0,0 +1,27 @@ +/* + Power management interface routines. + Written by Mariusz Matuszek. + This code is currently just a placeholder for later work and + does not do anything useful. + + This is part of rtl8180 OpenSource driver. + Copyright (C) Andrea Merello 2004 <andreamrl@tiscali.it> + Released under the terms of GPL (General Public Licence) + +*/ + +#ifdef CONFIG_RTL8192_PM + +#ifndef R8192_PM_H +#define R8192_PM_H + +#include <linux/types.h> +#include <linux/usb.h> + +int rtl8192U_save_tate (struct pci_dev *dev, u32 state); +int rtl8192U_suspend(struct usb_interface *intf, pm_message_t state); +int rtl8192U_resume (struct usb_interface *intf); +int rtl8192U_enable_wake (struct pci_dev *dev, u32 state, int enable); + +#endif //R8192U_PM_H +#endif // CONFIG_RTL8192_PM diff --git a/drivers/staging/rtl8192su/r8192U_wx.c b/drivers/staging/rtl8192su/r8192U_wx.c new file mode 100644 index 000000000000..f9eafb16dbb7 --- /dev/null +++ b/drivers/staging/rtl8192su/r8192U_wx.c @@ -0,0 +1,1350 @@ +/* + This file contains wireless extension handlers. + + This is part of rtl8180 OpenSource driver. + Copyright (C) Andrea Merello 2004-2005 <andreamrl@tiscali.it> + Released under the terms of GPL (General Public Licence) + + Parts of this driver are based on the GPL part + of the official realtek driver. + + Parts of this driver are based on the rtl8180 driver skeleton + from Patric Schenke & Andres Salomon. + + Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver. + + We want to tanks the Authors of those projects and the Ndiswrapper + project Authors. +*/ + +#ifdef RTL8192SU +#include <linux/string.h> +#include "r8192U.h" +#include "r8192S_hw.h" +#else +#include <linux/string.h> +#include "r8192U.h" +#include "r8192U_hw.h" +#endif + +#ifdef ENABLE_DOT11D +#include "dot11d.h" +#endif + +#define RATE_COUNT 12 +u32 rtl8180_rates[] = {1000000,2000000,5500000,11000000, + 6000000,9000000,12000000,18000000,24000000,36000000,48000000,54000000}; + + +#ifndef ENETDOWN +#define ENETDOWN 1 +#endif + +static int r8192_wx_get_freq(struct net_device *dev, + struct iw_request_info *a, + union iwreq_data *wrqu, char *b) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + + return ieee80211_wx_get_freq(priv->ieee80211,a,wrqu,b); +} + + +#if 0 + +static int r8192_wx_set_beaconinterval(struct net_device *dev, struct iw_request_info *aa, + union iwreq_data *wrqu, char *b) +{ + int *parms = (int *)b; + int bi = parms[0]; + + struct r8192_priv *priv = ieee80211_priv(dev); + + down(&priv->wx_sem); + DMESG("setting beacon interval to %x",bi); + + priv->ieee80211->beacon_interval=bi; + rtl8180_commit(dev); + up(&priv->wx_sem); + + return 0; +} + + +static int r8192_wx_set_forceassociate(struct net_device *dev, struct iw_request_info *aa, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv=ieee80211_priv(dev); + int *parms = (int *)extra; + + priv->ieee80211->force_associate = (parms[0] > 0); + + + return 0; +} + +#endif +static int r8192_wx_get_mode(struct net_device *dev, struct iw_request_info *a, + union iwreq_data *wrqu, char *b) +{ + struct r8192_priv *priv=ieee80211_priv(dev); + + return ieee80211_wx_get_mode(priv->ieee80211,a,wrqu,b); +} + + + +static int r8192_wx_get_rate(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + return ieee80211_wx_get_rate(priv->ieee80211,info,wrqu,extra); +} + + + +static int r8192_wx_set_rate(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret; + struct r8192_priv *priv = ieee80211_priv(dev); + + down(&priv->wx_sem); + + ret = ieee80211_wx_set_rate(priv->ieee80211,info,wrqu,extra); + + up(&priv->wx_sem); + + return ret; +} + + +static int r8192_wx_set_rts(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret; + struct r8192_priv *priv = ieee80211_priv(dev); + + down(&priv->wx_sem); + + ret = ieee80211_wx_set_rts(priv->ieee80211,info,wrqu,extra); + + up(&priv->wx_sem); + + return ret; +} + +static int r8192_wx_get_rts(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + return ieee80211_wx_get_rts(priv->ieee80211,info,wrqu,extra); +} + +static int r8192_wx_set_power(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret; + struct r8192_priv *priv = ieee80211_priv(dev); + + down(&priv->wx_sem); + + ret = ieee80211_wx_set_power(priv->ieee80211,info,wrqu,extra); + + up(&priv->wx_sem); + + return ret; +} + +static int r8192_wx_get_power(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + return ieee80211_wx_get_power(priv->ieee80211,info,wrqu,extra); +} + +#ifdef JOHN_IOCTL +u16 read_rtl8225(struct net_device *dev, u8 addr); +void write_rtl8225(struct net_device *dev, u8 adr, u16 data); +u32 john_read_rtl8225(struct net_device *dev, u8 adr); +void _write_rtl8225(struct net_device *dev, u8 adr, u16 data); + +static int r8192_wx_read_regs(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + u8 addr; + u16 data1; + + down(&priv->wx_sem); + + + get_user(addr,(u8*)wrqu->data.pointer); + data1 = read_rtl8225(dev, addr); + wrqu->data.length = data1; + + up(&priv->wx_sem); + return 0; + +} + +static int r8192_wx_write_regs(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + u8 addr; + + down(&priv->wx_sem); + + get_user(addr, (u8*)wrqu->data.pointer); + write_rtl8225(dev, addr, wrqu->data.length); + + up(&priv->wx_sem); + return 0; + +} + +void rtl8187_write_phy(struct net_device *dev, u8 adr, u32 data); +u8 rtl8187_read_phy(struct net_device *dev,u8 adr, u32 data); + +static int r8192_wx_read_bb(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + u8 databb; +#if 0 + int i; + for(i=0;i<12;i++) printk("%8x\n", read_cam(dev, i) ); +#endif + + down(&priv->wx_sem); + + databb = rtl8187_read_phy(dev, (u8)wrqu->data.length, 0x00000000); + wrqu->data.length = databb; + + up(&priv->wx_sem); + return 0; +} + +void rtl8187_write_phy(struct net_device *dev, u8 adr, u32 data); +static int r8192_wx_write_bb(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + u8 databb; + + down(&priv->wx_sem); + + get_user(databb, (u8*)wrqu->data.pointer); + rtl8187_write_phy(dev, wrqu->data.length, databb); + + up(&priv->wx_sem); + return 0; + +} + + +static int r8192_wx_write_nicb(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + u32 addr; + + down(&priv->wx_sem); + + get_user(addr, (u32*)wrqu->data.pointer); + write_nic_byte(dev, addr, wrqu->data.length); + + up(&priv->wx_sem); + return 0; + +} +static int r8192_wx_read_nicb(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + u32 addr; + u16 data1; + + down(&priv->wx_sem); + + get_user(addr,(u32*)wrqu->data.pointer); + data1 = read_nic_byte(dev, addr); + wrqu->data.length = data1; + + up(&priv->wx_sem); + return 0; +} + +static int r8192_wx_get_ap_status(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + struct ieee80211_device *ieee = priv->ieee80211; + struct ieee80211_network *target; + int name_len; + + down(&priv->wx_sem); + + //count the length of input ssid + for(name_len=0 ; ((char*)wrqu->data.pointer)[name_len]!='\0' ; name_len++); + + //search for the correspoding info which is received + list_for_each_entry(target, &ieee->network_list, list) { + if ( (target->ssid_len == name_len) && + (strncmp(target->ssid, (char*)wrqu->data.pointer, name_len)==0)){ + if(target->wpa_ie_len>0 || target->rsn_ie_len>0 ) + //set flags=1 to indicate this ap is WPA + wrqu->data.flags = 1; + else wrqu->data.flags = 0; + + + break; + } + } + + up(&priv->wx_sem); + return 0; +} + + + +#endif +#if 0 +static int r8192_wx_null(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + return 0; +} +#endif +static int r8192_wx_force_reset(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + + down(&priv->wx_sem); + + printk("%s(): force reset ! extra is %d\n",__FUNCTION__, *extra); + priv->force_reset = *extra; + up(&priv->wx_sem); + return 0; + +} + +#ifdef RTL8192SU +static int r8191su_wx_get_firm_version(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *wrqu, char *extra) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + u16 firmware_version; + + down(&priv->wx_sem); + firmware_version = priv->pFirmware->FirmwareVersion; + wrqu->value = firmware_version; + wrqu->fixed = 1; + + up(&priv->wx_sem); + return 0; +} +#endif + + + +static int r8192_wx_set_rawtx(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + int ret; + + down(&priv->wx_sem); + + ret = ieee80211_wx_set_rawtx(priv->ieee80211, info, wrqu, extra); + + up(&priv->wx_sem); + + return ret; + +} + +static int r8192_wx_set_crcmon(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + int *parms = (int *)extra; + int enable = (parms[0] > 0); + short prev = priv->crcmon; + + down(&priv->wx_sem); + + if(enable) + priv->crcmon=1; + else + priv->crcmon=0; + + DMESG("bad CRC in monitor mode are %s", + priv->crcmon ? "accepted" : "rejected"); + + if(prev != priv->crcmon && priv->up){ + //rtl8180_down(dev); + //rtl8180_up(dev); + } + + up(&priv->wx_sem); + + return 0; +} + +static int r8192_wx_set_mode(struct net_device *dev, struct iw_request_info *a, + union iwreq_data *wrqu, char *b) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + int ret; + down(&priv->wx_sem); + + ret = ieee80211_wx_set_mode(priv->ieee80211,a,wrqu,b); + + rtl8192_set_rxconf(dev); + + up(&priv->wx_sem); + return ret; +} + +struct iw_range_with_scan_capa +{ + /* Informative stuff (to choose between different interface) */ + __u32 throughput; /* To give an idea... */ + /* In theory this value should be the maximum benchmarked + * TCP/IP throughput, because with most of these devices the + * bit rate is meaningless (overhead an co) to estimate how + * fast the connection will go and pick the fastest one. + * I suggest people to play with Netperf or any benchmark... + */ + + /* NWID (or domain id) */ + __u32 min_nwid; /* Minimal NWID we are able to set */ + __u32 max_nwid; /* Maximal NWID we are able to set */ + + /* Old Frequency (backward compat - moved lower ) */ + __u16 old_num_channels; + __u8 old_num_frequency; + + /* Scan capabilities */ + __u8 scan_capa; +}; +static int rtl8180_wx_get_range(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct iw_range *range = (struct iw_range *)extra; + struct iw_range_with_scan_capa* tmp = (struct iw_range_with_scan_capa*)range; + struct r8192_priv *priv = ieee80211_priv(dev); + u16 val; + int i; + + wrqu->data.length = sizeof(*range); + memset(range, 0, sizeof(*range)); + + /* Let's try to keep this struct in the same order as in + * linux/include/wireless.h + */ + + /* TODO: See what values we can set, and remove the ones we can't + * set, or fill them with some default data. + */ + + /* ~5 Mb/s real (802.11b) */ + range->throughput = 5 * 1000 * 1000; + + // TODO: Not used in 802.11b? +// range->min_nwid; /* Minimal NWID we are able to set */ + // TODO: Not used in 802.11b? +// range->max_nwid; /* Maximal NWID we are able to set */ + + /* Old Frequency (backward compat - moved lower ) */ +// range->old_num_channels; +// range->old_num_frequency; +// range->old_freq[6]; /* Filler to keep "version" at the same offset */ + if(priv->rf_set_sens != NULL) + range->sensitivity = priv->max_sens; /* signal level threshold range */ + + range->max_qual.qual = 100; + /* TODO: Find real max RSSI and stick here */ + range->max_qual.level = 0; + range->max_qual.noise = -98; + range->max_qual.updated = 7; /* Updated all three */ + + range->avg_qual.qual = 92; /* > 8% missed beacons is 'bad' */ + /* TODO: Find real 'good' to 'bad' threshol value for RSSI */ + range->avg_qual.level = 20 + -98; + range->avg_qual.noise = 0; + range->avg_qual.updated = 7; /* Updated all three */ + + range->num_bitrates = RATE_COUNT; + + for (i = 0; i < RATE_COUNT && i < IW_MAX_BITRATES; i++) { + range->bitrate[i] = rtl8180_rates[i]; + } + + range->min_frag = MIN_FRAG_THRESHOLD; + range->max_frag = MAX_FRAG_THRESHOLD; + + range->min_pmp=0; + range->max_pmp = 5000000; + range->min_pmt = 0; + range->max_pmt = 65535*1000; + range->pmp_flags = IW_POWER_PERIOD; + range->pmt_flags = IW_POWER_TIMEOUT; + range->pm_capa = IW_POWER_PERIOD | IW_POWER_TIMEOUT | IW_POWER_ALL_R; + + range->we_version_compiled = WIRELESS_EXT; + range->we_version_source = 16; + +// range->retry_capa; /* What retry options are supported */ +// range->retry_flags; /* How to decode max/min retry limit */ +// range->r_time_flags; /* How to decode max/min retry life */ +// range->min_retry; /* Minimal number of retries */ +// range->max_retry; /* Maximal number of retries */ +// range->min_r_time; /* Minimal retry lifetime */ +// range->max_r_time; /* Maximal retry lifetime */ + + + for (i = 0, val = 0; i < 14; i++) { + + // Include only legal frequencies for some countries +#ifdef ENABLE_DOT11D + if ((GET_DOT11D_INFO(priv->ieee80211)->channel_map)[i+1]) { +#else + if ((priv->ieee80211->channel_map)[i+1]) { +#endif + range->freq[val].i = i + 1; + range->freq[val].m = ieee80211_wlan_frequencies[i] * 100000; + range->freq[val].e = 1; + val++; + } else { + // FIXME: do we need to set anything for channels + // we don't use ? + } + + if (val == IW_MAX_FREQUENCIES) + break; + } + range->num_frequency = val; + range->num_channels = val; +#if WIRELESS_EXT > 17 + range->enc_capa = IW_ENC_CAPA_WPA|IW_ENC_CAPA_WPA2| + IW_ENC_CAPA_CIPHER_TKIP|IW_ENC_CAPA_CIPHER_CCMP; +#endif + tmp->scan_capa = 0x01; + return 0; +} + + +static int r8192_wx_set_scan(struct net_device *dev, struct iw_request_info *a, + union iwreq_data *wrqu, char *b) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + struct ieee80211_device* ieee = priv->ieee80211; + int ret = 0; + + if(!priv->up) return -ENETDOWN; + + if (priv->ieee80211->LinkDetectInfo.bBusyTraffic == true) + return -EAGAIN; +#if WIRELESS_EXT > 17 + if (wrqu->data.flags & IW_SCAN_THIS_ESSID) + { + struct iw_scan_req* req = (struct iw_scan_req*)b; + if (req->essid_len) + { + //printk("==**&*&*&**===>scan set ssid:%s\n", req->essid); + ieee->current_network.ssid_len = req->essid_len; + memcpy(ieee->current_network.ssid, req->essid, req->essid_len); + //printk("=====>network ssid:%s\n", ieee->current_network.ssid); + } + } +#endif + + down(&priv->wx_sem); + if(priv->ieee80211->state != IEEE80211_LINKED){ + priv->ieee80211->scanning = 0; + ieee80211_softmac_scan_syncro(priv->ieee80211); + ret = 0; + } + else + ret = ieee80211_wx_set_scan(priv->ieee80211,a,wrqu,b); + up(&priv->wx_sem); + return ret; +} + + +static int r8192_wx_get_scan(struct net_device *dev, struct iw_request_info *a, + union iwreq_data *wrqu, char *b) +{ + + int ret; + struct r8192_priv *priv = ieee80211_priv(dev); + + if(!priv->up) return -ENETDOWN; + + down(&priv->wx_sem); + + ret = ieee80211_wx_get_scan(priv->ieee80211,a,wrqu,b); + + up(&priv->wx_sem); + + return ret; +} + +static int r8192_wx_set_essid(struct net_device *dev, + struct iw_request_info *a, + union iwreq_data *wrqu, char *b) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + int ret; + down(&priv->wx_sem); + + ret = ieee80211_wx_set_essid(priv->ieee80211,a,wrqu,b); + + up(&priv->wx_sem); + + return ret; +} + + + + +static int r8192_wx_get_essid(struct net_device *dev, + struct iw_request_info *a, + union iwreq_data *wrqu, char *b) +{ + int ret; + struct r8192_priv *priv = ieee80211_priv(dev); + + down(&priv->wx_sem); + + ret = ieee80211_wx_get_essid(priv->ieee80211, a, wrqu, b); + + up(&priv->wx_sem); + + return ret; +} + + +static int r8192_wx_set_freq(struct net_device *dev, struct iw_request_info *a, + union iwreq_data *wrqu, char *b) +{ + int ret; + struct r8192_priv *priv = ieee80211_priv(dev); + + down(&priv->wx_sem); + + ret = ieee80211_wx_set_freq(priv->ieee80211, a, wrqu, b); + + up(&priv->wx_sem); + return ret; +} + +static int r8192_wx_get_name(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + return ieee80211_wx_get_name(priv->ieee80211, info, wrqu, extra); +} + + +static int r8192_wx_set_frag(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + + if (wrqu->frag.disabled) + priv->ieee80211->fts = DEFAULT_FRAG_THRESHOLD; + else { + if (wrqu->frag.value < MIN_FRAG_THRESHOLD || + wrqu->frag.value > MAX_FRAG_THRESHOLD) + return -EINVAL; + + priv->ieee80211->fts = wrqu->frag.value & ~0x1; + } + + return 0; +} + + +static int r8192_wx_get_frag(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + + wrqu->frag.value = priv->ieee80211->fts; + wrqu->frag.fixed = 0; /* no auto select */ + wrqu->frag.disabled = (wrqu->frag.value == DEFAULT_FRAG_THRESHOLD); + + return 0; +} + + +static int r8192_wx_set_wap(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *awrq, + char *extra) +{ + + int ret; + struct r8192_priv *priv = ieee80211_priv(dev); +// struct sockaddr *temp = (struct sockaddr *)awrq; + down(&priv->wx_sem); + + ret = ieee80211_wx_set_wap(priv->ieee80211,info,awrq,extra); + + up(&priv->wx_sem); + + return ret; + +} + + +static int r8192_wx_get_wap(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + + return ieee80211_wx_get_wap(priv->ieee80211,info,wrqu,extra); +} + + +static int r8192_wx_get_enc(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *key) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + + return ieee80211_wx_get_encode(priv->ieee80211, info, wrqu, key); +} + +static int r8192_wx_set_enc(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *key) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + struct ieee80211_device *ieee = priv->ieee80211; + int ret; + + //u32 TargetContent; + u32 hwkey[4]={0,0,0,0}; + u8 mask=0xff; + u32 key_idx=0; + //u8 broadcast_addr[6] ={ 0xff,0xff,0xff,0xff,0xff,0xff}; + u8 zero_addr[4][6] ={ {0x00,0x00,0x00,0x00,0x00,0x00}, + {0x00,0x00,0x00,0x00,0x00,0x01}, + {0x00,0x00,0x00,0x00,0x00,0x02}, + {0x00,0x00,0x00,0x00,0x00,0x03} }; + int i; + + if(!priv->up) return -ENETDOWN; + + down(&priv->wx_sem); + + RT_TRACE(COMP_SEC, "Setting SW wep key"); + ret = ieee80211_wx_set_encode(priv->ieee80211,info,wrqu,key); + + up(&priv->wx_sem); + + + + //sometimes, the length is zero while we do not type key value + if(wrqu->encoding.length!=0){ + + for(i=0 ; i<4 ; i++){ + hwkey[i] |= key[4*i+0]&mask; + if(i==1&&(4*i+1)==wrqu->encoding.length) mask=0x00; + if(i==3&&(4*i+1)==wrqu->encoding.length) mask=0x00; + hwkey[i] |= (key[4*i+1]&mask)<<8; + hwkey[i] |= (key[4*i+2]&mask)<<16; + hwkey[i] |= (key[4*i+3]&mask)<<24; + } + + #define CONF_WEP40 0x4 + #define CONF_WEP104 0x14 + + switch(wrqu->encoding.flags & IW_ENCODE_INDEX){ + case 0: key_idx = ieee->tx_keyidx; break; + case 1: key_idx = 0; break; + case 2: key_idx = 1; break; + case 3: key_idx = 2; break; + case 4: key_idx = 3; break; + default: break; + } + + if(wrqu->encoding.length==0x5){ + ieee->pairwise_key_type = KEY_TYPE_WEP40; + EnableHWSecurityConfig8192(dev); + + setKey( dev, + key_idx, //EntryNo + key_idx, //KeyIndex + KEY_TYPE_WEP40, //KeyType + zero_addr[key_idx], + 0, //DefaultKey + hwkey); //KeyContent + + } + + else if(wrqu->encoding.length==0xd){ + ieee->pairwise_key_type = KEY_TYPE_WEP104; + EnableHWSecurityConfig8192(dev); + + setKey( dev, + key_idx, //EntryNo + key_idx, //KeyIndex + KEY_TYPE_WEP104, //KeyType + zero_addr[key_idx], + 0, //DefaultKey + hwkey); //KeyContent + + } + else printk("wrong type in WEP, not WEP40 and WEP104\n"); + + } + + return ret; +} + + +static int r8192_wx_set_scan_type(struct net_device *dev, struct iw_request_info *aa, union + iwreq_data *wrqu, char *p){ + + struct r8192_priv *priv = ieee80211_priv(dev); + int *parms=(int*)p; + int mode=parms[0]; + + priv->ieee80211->active_scan = mode; + + return 1; +} + + + +static int r8192_wx_set_retry(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + int err = 0; + + down(&priv->wx_sem); + + if (wrqu->retry.flags & IW_RETRY_LIFETIME || + wrqu->retry.disabled){ + err = -EINVAL; + goto exit; + } + if (!(wrqu->retry.flags & IW_RETRY_LIMIT)){ + err = -EINVAL; + goto exit; + } + + if(wrqu->retry.value > R8180_MAX_RETRY){ + err= -EINVAL; + goto exit; + } + if (wrqu->retry.flags & IW_RETRY_MAX) { + priv->retry_rts = wrqu->retry.value; + DMESG("Setting retry for RTS/CTS data to %d", wrqu->retry.value); + + }else { + priv->retry_data = wrqu->retry.value; + DMESG("Setting retry for non RTS/CTS data to %d", wrqu->retry.value); + } + + /* FIXME ! + * We might try to write directly the TX config register + * or to restart just the (R)TX process. + * I'm unsure if whole reset is really needed + */ + + rtl8192_commit(dev); + /* + if(priv->up){ + rtl8180_rtx_disable(dev); + rtl8180_rx_enable(dev); + rtl8180_tx_enable(dev); + + } + */ +exit: + up(&priv->wx_sem); + + return err; +} + +static int r8192_wx_get_retry(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + + + wrqu->retry.disabled = 0; /* can't be disabled */ + + if ((wrqu->retry.flags & IW_RETRY_TYPE) == + IW_RETRY_LIFETIME) + return -EINVAL; + + if (wrqu->retry.flags & IW_RETRY_MAX) { + wrqu->retry.flags = IW_RETRY_LIMIT | IW_RETRY_MAX; + wrqu->retry.value = priv->retry_rts; + } else { + wrqu->retry.flags = IW_RETRY_LIMIT | IW_RETRY_MIN; + wrqu->retry.value = priv->retry_data; + } + //printk("returning %d",wrqu->retry.value); + + + return 0; +} + +static int r8192_wx_get_sens(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + if(priv->rf_set_sens == NULL) + return -1; /* we have not this support for this radio */ + wrqu->sens.value = priv->sens; + return 0; +} + + +static int r8192_wx_set_sens(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + struct r8192_priv *priv = ieee80211_priv(dev); + + short err = 0; + down(&priv->wx_sem); + //DMESG("attempt to set sensivity to %ddb",wrqu->sens.value); + if(priv->rf_set_sens == NULL) { + err= -1; /* we have not this support for this radio */ + goto exit; + } + if(priv->rf_set_sens(dev, wrqu->sens.value) == 0) + priv->sens = wrqu->sens.value; + else + err= -EINVAL; + +exit: + up(&priv->wx_sem); + + return err; +} + +#if (WIRELESS_EXT >= 18) +#if 0 +static int r8192_wx_get_enc_ext(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + int ret = 0; + ret = ieee80211_wx_get_encode_ext(priv->ieee80211, info, wrqu, extra); + return ret; +} +#endif +//hw security need to reorganized. +static int r8192_wx_set_enc_ext(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret=0; + #if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + struct r8192_priv *priv = ieee80211_priv(dev); + struct ieee80211_device* ieee = priv->ieee80211; + //printk("===>%s()\n", __FUNCTION__); + + + down(&priv->wx_sem); + ret = ieee80211_wx_set_encode_ext(priv->ieee80211, info, wrqu, extra); + + { + u8 broadcast_addr[6] = {0xff,0xff,0xff,0xff,0xff,0xff}; + u8 zero[6] = {0}; + u32 key[4] = {0}; + struct iw_encode_ext *ext = (struct iw_encode_ext *)extra; + struct iw_point *encoding = &wrqu->encoding; +#if 0 + static u8 CAM_CONST_ADDR[4][6] = { + {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x02}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}}; +#endif + u8 idx = 0, alg = 0, group = 0; + if ((encoding->flags & IW_ENCODE_DISABLED) || + ext->alg == IW_ENCODE_ALG_NONE) //none is not allowed to use hwsec WB 2008.07.01 + { + ieee->pairwise_key_type = ieee->group_key_type = KEY_TYPE_NA; + CamResetAllEntry(dev); + goto end_hw_sec; + } + alg = (ext->alg == IW_ENCODE_ALG_CCMP)?KEY_TYPE_CCMP:ext->alg; // as IW_ENCODE_ALG_CCMP is defined to be 3 and KEY_TYPE_CCMP is defined to 4; + idx = encoding->flags & IW_ENCODE_INDEX; + if (idx) + idx --; + group = ext->ext_flags & IW_ENCODE_EXT_GROUP_KEY; + + if ((!group) || (IW_MODE_ADHOC == ieee->iw_mode) || (alg == KEY_TYPE_WEP40)) + { + if ((ext->key_len == 13) && (alg == KEY_TYPE_WEP40) ) + alg = KEY_TYPE_WEP104; + ieee->pairwise_key_type = alg; + EnableHWSecurityConfig8192(dev); + } + memcpy((u8*)key, ext->key, 16); //we only get 16 bytes key.why? WB 2008.7.1 + + if ((alg & KEY_TYPE_WEP40) && (ieee->auth_mode !=2) ) + { + + setKey( dev, + idx,//EntryNo + idx, //KeyIndex + alg, //KeyType + zero, //MacAddr + 0, //DefaultKey + key); //KeyContent + } + else if (group) + { + ieee->group_key_type = alg; + setKey( dev, + idx,//EntryNo + idx, //KeyIndex + alg, //KeyType + broadcast_addr, //MacAddr + 0, //DefaultKey + key); //KeyContent + } + else //pairwise key + { + setKey( dev, + 4,//EntryNo + idx, //KeyIndex + alg, //KeyType + (u8*)ieee->ap_mac_addr, //MacAddr + 0, //DefaultKey + key); //KeyContent + } + + + } + +end_hw_sec: + + up(&priv->wx_sem); +#endif + return ret; + +} +static int r8192_wx_set_auth(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *data, char *extra) +{ + int ret=0; +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + //printk("====>%s()\n", __FUNCTION__); + struct r8192_priv *priv = ieee80211_priv(dev); + down(&priv->wx_sem); + ret = ieee80211_wx_set_auth(priv->ieee80211, info, &(data->param), extra); + up(&priv->wx_sem); +#endif + return ret; +} + +static int r8192_wx_set_mlme(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + //printk("====>%s()\n", __FUNCTION__); + + int ret=0; +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + struct r8192_priv *priv = ieee80211_priv(dev); + down(&priv->wx_sem); + ret = ieee80211_wx_set_mlme(priv->ieee80211, info, wrqu, extra); + + up(&priv->wx_sem); +#endif + return ret; +} +#endif +static int r8192_wx_set_gen_ie(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *data, char *extra) +{ + //printk("====>%s(), len:%d\n", __FUNCTION__, data->length); + int ret=0; +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + struct r8192_priv *priv = ieee80211_priv(dev); + down(&priv->wx_sem); +#if 1 + ret = ieee80211_wx_set_gen_ie(priv->ieee80211, extra, data->data.length); +#endif + up(&priv->wx_sem); + //printk("<======%s(), ret:%d\n", __FUNCTION__, ret); +#endif + return ret; + + +} + +static int dummy(struct net_device *dev, struct iw_request_info *a, + union iwreq_data *wrqu,char *b) +{ + return -1; +} + + +static iw_handler r8192_wx_handlers[] = +{ + NULL, /* SIOCSIWCOMMIT */ + r8192_wx_get_name, /* SIOCGIWNAME */ + dummy, /* SIOCSIWNWID */ + dummy, /* SIOCGIWNWID */ + r8192_wx_set_freq, /* SIOCSIWFREQ */ + r8192_wx_get_freq, /* SIOCGIWFREQ */ + r8192_wx_set_mode, /* SIOCSIWMODE */ + r8192_wx_get_mode, /* SIOCGIWMODE */ + r8192_wx_set_sens, /* SIOCSIWSENS */ + r8192_wx_get_sens, /* SIOCGIWSENS */ + NULL, /* SIOCSIWRANGE */ + rtl8180_wx_get_range, /* SIOCGIWRANGE */ + NULL, /* SIOCSIWPRIV */ + NULL, /* SIOCGIWPRIV */ + NULL, /* SIOCSIWSTATS */ + NULL, /* SIOCGIWSTATS */ + dummy, /* SIOCSIWSPY */ + dummy, /* SIOCGIWSPY */ + NULL, /* SIOCGIWTHRSPY */ + NULL, /* SIOCWIWTHRSPY */ + r8192_wx_set_wap, /* SIOCSIWAP */ + r8192_wx_get_wap, /* SIOCGIWAP */ +#if (WIRELESS_EXT >= 18) + r8192_wx_set_mlme, /* MLME-- */ +#else + NULL, +#endif + dummy, /* SIOCGIWAPLIST -- depricated */ + r8192_wx_set_scan, /* SIOCSIWSCAN */ + r8192_wx_get_scan, /* SIOCGIWSCAN */ + r8192_wx_set_essid, /* SIOCSIWESSID */ + r8192_wx_get_essid, /* SIOCGIWESSID */ + dummy, /* SIOCSIWNICKN */ + dummy, /* SIOCGIWNICKN */ + NULL, /* -- hole -- */ + NULL, /* -- hole -- */ + r8192_wx_set_rate, /* SIOCSIWRATE */ + r8192_wx_get_rate, /* SIOCGIWRATE */ + r8192_wx_set_rts, /* SIOCSIWRTS */ + r8192_wx_get_rts, /* SIOCGIWRTS */ + r8192_wx_set_frag, /* SIOCSIWFRAG */ + r8192_wx_get_frag, /* SIOCGIWFRAG */ + dummy, /* SIOCSIWTXPOW */ + dummy, /* SIOCGIWTXPOW */ + r8192_wx_set_retry, /* SIOCSIWRETRY */ + r8192_wx_get_retry, /* SIOCGIWRETRY */ + r8192_wx_set_enc, /* SIOCSIWENCODE */ + r8192_wx_get_enc, /* SIOCGIWENCODE */ + r8192_wx_set_power, /* SIOCSIWPOWER */ + r8192_wx_get_power, /* SIOCGIWPOWER */ + NULL, /*---hole---*/ + NULL, /*---hole---*/ + r8192_wx_set_gen_ie,//NULL, /* SIOCSIWGENIE */ + NULL, /* SIOCSIWGENIE */ + +#if (WIRELESS_EXT >= 18) + r8192_wx_set_auth,//NULL, /* SIOCSIWAUTH */ + NULL,//r8192_wx_get_auth,//NULL, /* SIOCSIWAUTH */ + r8192_wx_set_enc_ext, /* SIOCSIWENCODEEXT */ + NULL,//r8192_wx_get_enc_ext,//NULL, /* SIOCSIWENCODEEXT */ +#else + NULL, + NULL, + NULL, + NULL, +#endif + NULL, /* SIOCSIWPMKSA */ + NULL, /*---hole---*/ + +}; + + +static const struct iw_priv_args r8192_private_args[] = { + + { + SIOCIWFIRSTPRIV + 0x0, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "badcrc" + }, + + { + SIOCIWFIRSTPRIV + 0x1, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "activescan" + + }, + { + SIOCIWFIRSTPRIV + 0x2, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "rawtx" + } +#ifdef JOHN_IOCTL + , + { + SIOCIWFIRSTPRIV + 0x3, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "readRF" + } + , + { + SIOCIWFIRSTPRIV + 0x4, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "writeRF" + } + , + { + SIOCIWFIRSTPRIV + 0x5, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "readBB" + } + , + { + SIOCIWFIRSTPRIV + 0x6, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "writeBB" + } + , + { + SIOCIWFIRSTPRIV + 0x7, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "readnicb" + } + , + { + SIOCIWFIRSTPRIV + 0x8, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "writenicb" + } + , + { + SIOCIWFIRSTPRIV + 0x9, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "apinfo" + } + +#endif + , + { + SIOCIWFIRSTPRIV + 0x3, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "forcereset" + } + +#ifdef RTL8192SU + , + { + SIOCIWFIRSTPRIV + 0x5, + IW_PRIV_TYPE_NONE, IW_PRIV_TYPE_INT|IW_PRIV_SIZE_FIXED|1, + "firm_ver" + } +#endif +}; + + +static iw_handler r8192_private_handler[] = { +// r8192_wx_set_monitor, /* SIOCIWFIRSTPRIV */ + r8192_wx_set_crcmon, /*SIOCIWSECONDPRIV*/ +// r8192_wx_set_forceassociate, +// r8192_wx_set_beaconinterval, +// r8192_wx_set_monitor_type, + r8192_wx_set_scan_type, + r8192_wx_set_rawtx, +#ifdef JOHN_IOCTL + r8192_wx_read_regs, + r8192_wx_write_regs, + r8192_wx_read_bb, + r8192_wx_write_bb, + r8192_wx_read_nicb, + r8192_wx_write_nicb, + r8192_wx_get_ap_status, +#endif + r8192_wx_force_reset, + (iw_handler)NULL, +#ifdef RTL8192SU + (iw_handler)r8191su_wx_get_firm_version, +#endif +}; + +//#if WIRELESS_EXT >= 17 +struct iw_statistics *r8192_get_wireless_stats(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + struct ieee80211_device* ieee = priv->ieee80211; + struct iw_statistics* wstats = &priv->wstats; + int tmp_level = 0; + int tmp_qual = 0; + int tmp_noise = 0; + if(ieee->state < IEEE80211_LINKED) + { + wstats->qual.qual = 0; + wstats->qual.level = 0; + wstats->qual.noise = 0; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,14)) + wstats->qual.updated = IW_QUAL_ALL_UPDATED | IW_QUAL_DBM; +#else + wstats->qual.updated = 0x0f; +#endif + return wstats; + } + + tmp_level = (&ieee->current_network)->stats.rssi; + tmp_qual = (&ieee->current_network)->stats.signal; + tmp_noise = (&ieee->current_network)->stats.noise; + //printk("level:%d, qual:%d, noise:%d\n", tmp_level, tmp_qual, tmp_noise); + + wstats->qual.level = tmp_level; + wstats->qual.qual = tmp_qual; + wstats->qual.noise = tmp_noise; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,14)) + wstats->qual.updated = IW_QUAL_ALL_UPDATED| IW_QUAL_DBM; +#else + wstats->qual.updated = 0x0f; +#endif + return wstats; +} +//#endif + + +struct iw_handler_def r8192_wx_handlers_def={ + .standard = r8192_wx_handlers, + .num_standard = sizeof(r8192_wx_handlers) / sizeof(iw_handler), + .private = r8192_private_handler, + .num_private = sizeof(r8192_private_handler) / sizeof(iw_handler), + .num_private_args = sizeof(r8192_private_args) / sizeof(struct iw_priv_args), +#if WIRELESS_EXT >= 17 + .get_wireless_stats = r8192_get_wireless_stats, +#endif + .private_args = (struct iw_priv_args *)r8192_private_args, +}; diff --git a/drivers/staging/rtl8192su/r8192U_wx.h b/drivers/staging/rtl8192su/r8192U_wx.h new file mode 100644 index 000000000000..b2f7a571b1c8 --- /dev/null +++ b/drivers/staging/rtl8192su/r8192U_wx.h @@ -0,0 +1,23 @@ +/* + This is part of rtl8180 OpenSource driver - v 0.3 + Copyright (C) Andrea Merello 2004 <andreamrl@tiscali.it> + Released under the terms of GPL (General Public Licence) + + Parts of this driver are based on the GPL part of the official realtek driver + Parts of this driver are based on the rtl8180 driver skeleton from Patric Schenke & Andres Salomon + Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver + + We want to tanks the Authors of such projects and the Ndiswrapper project Authors. +*/ + +/* this file (will) contains wireless extension handlers*/ + +#ifndef R8180_WX_H +#define R8180_WX_H +//#include <linux/wireless.h> +//#include "ieee80211.h" +extern struct iw_handler_def r8192_wx_handlers_def; +/* Enable the rtl819x_core.c to share this function, david 2008.9.22 */ +extern struct iw_statistics *r8192_get_wireless_stats(struct net_device *dev); + +#endif diff --git a/drivers/staging/rtl8192su/r819xU_HTGen.h b/drivers/staging/rtl8192su/r819xU_HTGen.h new file mode 100644 index 000000000000..7a60480c4b8e --- /dev/null +++ b/drivers/staging/rtl8192su/r819xU_HTGen.h @@ -0,0 +1,22 @@ +// +// IOT Action for different AP +// +typedef enum _HT_IOT_ACTION{ + HT_IOT_ACT_TX_USE_AMSDU_4K = 0x00000001, + HT_IOT_ACT_TX_USE_AMSDU_8K = 0x00000002, + HT_IOT_ACT_DECLARE_MCS13 = 0x00000004, + HT_IOT_ACT_DISABLE_EDCA_TURBO = 0x00000008, + HT_IOT_ACT_MGNT_USE_CCK_6M = 0x00000010, + HT_IOT_ACT_CDD_FSYNC = 0x00000020, + HT_IOT_ACT_PURE_N_MODE = 0x00000040, + + //LZM ADD 090224 + HT_IOT_ACT_EDCA_BIAS_ON_RX = 0x00004000, + HT_IOT_ACT_HYBRID_AGGREGATION = 0x00010000, + HT_IOT_ACT_AMSDU_ENABLE = 0x00000800, + HT_IOT_ACT_DISABLE_SHORT_GI = 0x00020000, + HT_IOT_ACT_DISABLE_HIGH_POWER = 0x00040000, + HT_IOT_ACT_DISABLE_TX_2SS = 0x00200000, + HT_IOT_ACT_DISABLE_TX_40_MHZ = 0x00080000, +}HT_IOT_ACTION_E, *PHT_IOT_ACTION_E; + diff --git a/drivers/staging/rtl8192su/r819xU_HTType.h b/drivers/staging/rtl8192su/r819xU_HTType.h new file mode 100644 index 000000000000..2994aa0876ad --- /dev/null +++ b/drivers/staging/rtl8192su/r819xU_HTType.h @@ -0,0 +1,392 @@ +#ifndef _R819XU_HTTYPE_H_ +#define _R819XU_HTTYPE_H_ + + +//------------------------------------------------------------ +// The HT Capability element is present in beacons, association request, +// reassociation request and probe response frames +//------------------------------------------------------------ + +// +// Operation mode value +// +#define HT_OPMODE_NO_PROTECT 0 +#define HT_OPMODE_OPTIONAL 1 +#define HT_OPMODE_40MHZ_PROTECT 2 +#define HT_OPMODE_MIXED 3 + +// +// MIMO Power Save Setings +// +#define MIMO_PS_STATIC 0 +#define MIMO_PS_DYNAMIC 1 +#define MIMO_PS_NOLIMIT 3 + + +// +// There should be 128 bits to cover all of the MCS rates. However, since +// 8190 does not support too much rates, one integer is quite enough. +// + +#define sHTCLng 4 + + +#define HT_SUPPORTED_MCS_1SS_BITMAP 0x000000ff +#define HT_SUPPORTED_MCS_2SS_BITMAP 0x0000ff00 +#define HT_SUPPORTED_MCS_1SS_2SS_BITMAP HT_MCS_1SS_BITMAP|HT_MCS_1SS_2SS_BITMAP + + +typedef enum _HT_MCS_RATE{ + HT_MCS0 = 0x00000001, + HT_MCS1 = 0x00000002, + HT_MCS2 = 0x00000004, + HT_MCS3 = 0x00000008, + HT_MCS4 = 0x00000010, + HT_MCS5 = 0x00000020, + HT_MCS6 = 0x00000040, + HT_MCS7 = 0x00000080, + HT_MCS8 = 0x00000100, + HT_MCS9 = 0x00000200, + HT_MCS10 = 0x00000400, + HT_MCS11 = 0x00000800, + HT_MCS12 = 0x00001000, + HT_MCS13 = 0x00002000, + HT_MCS14 = 0x00004000, + HT_MCS15 = 0x00008000, + // Do not define MCS32 here although 8190 support MCS32 +}HT_MCS_RATE,*PHT_MCS_RATE; + +// +// Represent Channel Width in HT Capabilities +// +typedef enum _HT_CHANNEL_WIDTH{ + HT_CHANNEL_WIDTH_20 = 0, + HT_CHANNEL_WIDTH_20_40 = 1, +}HT_CHANNEL_WIDTH, *PHT_CHANNEL_WIDTH; + +// +// Represent Extention Channel Offset in HT Capabilities +// This is available only in 40Mhz mode. +// +typedef enum _HT_EXTCHNL_OFFSET{ + HT_EXTCHNL_OFFSET_NO_EXT = 0, + HT_EXTCHNL_OFFSET_UPPER = 1, + HT_EXTCHNL_OFFSET_NO_DEF = 2, + HT_EXTCHNL_OFFSET_LOWER = 3, +}HT_EXTCHNL_OFFSET, *PHT_EXTCHNL_OFFSET; + +typedef enum _CHNLOP{ + CHNLOP_NONE = 0, // No Action now + CHNLOP_SCAN = 1, // Scan in progress + CHNLOP_SWBW = 2, // Bandwidth switching in progress + CHNLOP_SWCHNL = 3, // Software Channel switching in progress +} CHNLOP, *PCHNLOP; + +// Determine if the Channel Operation is in progress +#define CHHLOP_IN_PROGRESS(_pHTInfo) \ + ((_pHTInfo)->ChnlOp > CHNLOP_NONE) ? TRUE : FALSE + + +typedef enum _HT_ACTION{ + ACT_RECOMMAND_WIDTH = 0, + ACT_MIMO_PWR_SAVE = 1, + ACT_PSMP = 2, + ACT_SET_PCO_PHASE = 3, + ACT_MIMO_CHL_MEASURE = 4, + ACT_RECIPROCITY_CORRECT = 5, + ACT_MIMO_CSI_MATRICS = 6, + ACT_MIMO_NOCOMPR_STEER = 7, + ACT_MIMO_COMPR_STEER = 8, + ACT_ANTENNA_SELECT = 9, +} HT_ACTION, *PHT_ACTION; + + +/* 2007/06/07 MH Define sub-carrier mode for 40MHZ. */ +typedef enum _HT_Bandwidth_40MHZ_Sub_Carrier{ + SC_MODE_DUPLICATE = 0, + SC_MODE_LOWER = 1, + SC_MODE_UPPER = 2, + SC_MODE_FULL40MHZ = 3, +}HT_BW40_SC_E; + +typedef struct _HT_CAPABILITY_ELE{ + + //HT capability info + u8 AdvCoding:1; + u8 ChlWidth:1; + u8 MimoPwrSave:2; + u8 GreenField:1; + u8 ShortGI20Mhz:1; + u8 ShortGI40Mhz:1; + u8 TxSTBC:1; + u8 RxSTBC:2; + u8 DelayBA:1; + u8 MaxAMSDUSize:1; + u8 DssCCk:1; + u8 PSMP:1; + u8 Rsvd1:1; + u8 LSigTxopProtect:1; + + //MAC HT parameters info + u8 MaxRxAMPDUFactor:2; + u8 MPDUDensity:3; + u8 Rsvd2:3; + + //Supported MCS set + u8 MCS[16]; + + + //Extended HT Capability Info + u16 ExtHTCapInfo; + + //TXBF Capabilities + u8 TxBFCap[4]; + + //Antenna Selection Capabilities + u8 ASCap; + +}__attribute__((packed)) HT_CAPABILITY_ELE, *PHT_CAPABILITY_ELE; + +//------------------------------------------------------------ +// The HT Information element is present in beacons +// Only AP is required to include this element +//------------------------------------------------------------ + +typedef struct _HT_INFORMATION_ELE{ + u8 ControlChl; + + u8 ExtChlOffset:2; + u8 RecommemdedTxWidth:1; + u8 RIFS:1; + u8 PSMPAccessOnly:1; + u8 SrvIntGranularity:3; + + u8 OptMode:2; + u8 NonGFDevPresent:1; + u8 Revd1:5; + u8 Revd2:8; + + u8 Rsvd3:6; + u8 DualBeacon:1; + u8 DualCTSProtect:1; + + u8 SecondaryBeacon:1; + u8 LSigTxopProtectFull:1; + u8 PcoActive:1; + u8 PcoPhase:1; + u8 Rsvd4:4; + + u8 BasicMSC[16]; +}__attribute__((packed)) HT_INFORMATION_ELE, *PHT_INFORMATION_ELE; + +// +// MIMO Power Save control field. +// This is appear in MIMO Power Save Action Frame +// +typedef struct _MIMOPS_CTRL{ + u8 MimoPsEnable:1; + u8 MimoPsMode:1; + u8 Reserved:6; +} MIMOPS_CTRL, *PMIMOPS_CTRL; + +typedef enum _HT_SPEC_VER{ + HT_SPEC_VER_IEEE = 0, + HT_SPEC_VER_EWC = 1, +}HT_SPEC_VER, *PHT_SPEC_VER; + +typedef enum _HT_AGGRE_MODE_E{ + HT_AGG_AUTO = 0, + HT_AGG_FORCE_ENABLE = 1, + HT_AGG_FORCE_DISABLE = 2, +}HT_AGGRE_MODE_E, *PHT_AGGRE_MODE_E; + +//------------------------------------------------------------ +// The Data structure is used to keep HT related variables when card is +// configured as non-AP STA mode. **Note** Current_xxx should be set +// to default value in HTInitializeHTInfo() +//------------------------------------------------------------ + +typedef struct _RT_HIGH_THROUGHPUT{ +// DECLARE_RT_OBJECT(_RT_HIGH_THROUGHPUT); + u8 bEnableHT; + u8 bCurrentHTSupport; + + u8 bRegBW40MHz; // Tx 40MHz channel capablity + u8 bCurBW40MHz; // Tx 40MHz channel capability + + u8 bRegShortGI40MHz; // Tx Short GI for 40Mhz + u8 bCurShortGI40MHz; // Tx Short GI for 40MHz + + u8 bRegShortGI20MHz; // Tx Short GI for 20MHz + u8 bCurShortGI20MHz; // Tx Short GI for 20MHz + + u8 bRegSuppCCK; // Tx CCK rate capability + u8 bCurSuppCCK; // Tx CCK rate capability + + // 802.11n spec version for "peer" + HT_SPEC_VER ePeerHTSpecVer; + + + // HT related information for "Self" + HT_CAPABILITY_ELE SelfHTCap; // This is HT cap element sent to peer STA, which also indicate HT Rx capabilities. + HT_INFORMATION_ELE SelfHTInfo; // This is HT info element sent to peer STA, which also indicate HT Rx capabilities. + + // HT related information for "Peer" + u8 PeerHTCapBuf[32]; + u8 PeerHTInfoBuf[32]; + + + // A-MSDU related + u8 bAMSDU_Support; // This indicates Tx A-MSDU capability + u16 nAMSDU_MaxSize; // This indicates Tx A-MSDU capability + u8 bCurrent_AMSDU_Support; // This indicates Tx A-MSDU capability + u16 nCurrent_AMSDU_MaxSize; // This indicates Tx A-MSDU capability + + + // AMPDU related <2006.08.10 Emily> + u8 bAMPDUEnable; // This indicate Tx A-MPDU capability + u8 bCurrentAMPDUEnable; // This indicate Tx A-MPDU capability + u8 AMPDU_Factor; // This indicate Tx A-MPDU capability + u8 CurrentAMPDUFactor; // This indicate Tx A-MPDU capability + u8 MPDU_Density; // This indicate Tx A-MPDU capability + u8 CurrentMPDUDensity; // This indicate Tx A-MPDU capability + + // Forced A-MPDU enable + HT_AGGRE_MODE_E ForcedAMPDUMode; + u8 ForcedAMPDUFactor; + u8 ForcedMPDUDensity; + + // Forced A-MSDU enable + HT_AGGRE_MODE_E ForcedAMSDUMode; + u16 ForcedAMSDUMaxSize; + + u8 bForcedShortGI; + + u8 CurrentOpMode; + + // MIMO PS related + u8 SelfMimoPs; + u8 PeerMimoPs; + + // 40MHz Channel Offset settings. + HT_EXTCHNL_OFFSET CurSTAExtChnlOffset; + u8 bCurTxBW40MHz; // If we use 40 MHz to Tx + u8 PeerBandwidth; + + // For Bandwidth Switching + u8 bSwBwInProgress; + CHNLOP ChnlOp; // software switching channel in progress. By Bruce, 2008-02-15. + u8 SwBwStep; + //RT_TIMER SwBwTimer; + struct timer_list SwBwTimer; + + // For Realtek proprietary A-MPDU factor for aggregation + u8 bRegRT2RTAggregation; + u8 bCurrentRT2RTAggregation; + u8 bCurrentRT2RTLongSlotTime; + u8 szRT2RTAggBuffer[10]; + + // Rx Reorder control + u8 bRegRxReorderEnable; + u8 bCurRxReorderEnable; + u8 RxReorderWinSize; + u8 RxReorderPendingTime; + u16 RxReorderDropCounter; + +#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE + u8 UsbTxAggrNum; +#endif +#ifdef USB_RX_AGGREGATION_SUPPORT + u8 UsbRxFwAggrEn; + u8 UsbRxFwAggrPageNum; + u8 UsbRxFwAggrPacketNum; + u8 UsbRxFwAggrTimeout; +#endif + + // Add for Broadcom(Linksys) IOT. Joseph + u8 bIsPeerBcm; + + // For IOT issue. + u32 IOTAction; +}RT_HIGH_THROUGHPUT, *PRT_HIGH_THROUGHPUT; + + +//------------------------------------------------------------ +// The Data structure is used to keep HT related variable for "each Sta" +// when card is configured as "AP mode" +//------------------------------------------------------------ + +typedef struct _RT_HTINFO_STA_ENTRY{ + u8 bEnableHT; + + u8 bSupportCck; + + u16 AMSDU_MaxSize; + + u8 AMPDU_Factor; + u8 MPDU_Density; + + u8 HTHighestOperaRate; + + u8 bBw40MHz; + + u8 MimoPs; + + u8 McsRateSet[16]; + + +}RT_HTINFO_STA_ENTRY, *PRT_HTINFO_STA_ENTRY; + + + + + +//------------------------------------------------------------ +// The Data structure is used to keep HT related variable for "each AP" +// when card is configured as "STA mode" +//------------------------------------------------------------ + +typedef struct _BSS_HT{ + + u8 bdSupportHT; + + // HT related elements + u8 bdHTCapBuf[32]; + u16 bdHTCapLen; + u8 bdHTInfoBuf[32]; + u16 bdHTInfoLen; + + HT_SPEC_VER bdHTSpecVer; + //HT_CAPABILITY_ELE bdHTCapEle; + //HT_INFORMATION_ELE bdHTInfoEle; + + u8 bdRT2RTAggregation; + u8 bdRT2RTLongSlotTime; + bool bdHT1R; +}BSS_HT, *PBSS_HT; + +typedef struct _MIMO_RSSI{ + u32 EnableAntenna; + u32 AntennaA; + u32 AntennaB; + u32 AntennaC; + u32 AntennaD; + u32 Average; +}MIMO_RSSI, *PMIMO_RSSI; + +typedef struct _MIMO_EVM{ + u32 EVM1; + u32 EVM2; +}MIMO_EVM, *PMIMO_EVM; + +typedef struct _FALSE_ALARM_STATISTICS{ + u32 Cnt_Parity_Fail; + u32 Cnt_Rate_Illegal; + u32 Cnt_Crc8_fail; + u32 Cnt_all; +}FALSE_ALARM_STATISTICS, *PFALSE_ALARM_STATISTICS; + + + +#endif //__INC_HTTYPE_H + diff --git a/drivers/staging/rtl8192su/r819xU_cmdpkt.c b/drivers/staging/rtl8192su/r819xU_cmdpkt.c new file mode 100644 index 000000000000..c1149c6f77bc --- /dev/null +++ b/drivers/staging/rtl8192su/r819xU_cmdpkt.c @@ -0,0 +1,826 @@ +/****************************************************************************** + + (c) Copyright 2008, RealTEK Technologies Inc. All Rights Reserved. + + Module: r819xusb_cmdpkt.c (RTL8190 TX/RX command packet handler Source C File) + + Note: The module is responsible for handling TX and RX command packet. + 1. TX : Send set and query configuration command packet. + 2. RX : Receive tx feedback, beacon state, query configuration + command packet. + + Function: + + Export: + + Abbrev: + + History: + Data Who Remark + + 05/06/2008 amy Create initial version porting from windows driver. + +******************************************************************************/ +#include "r8192U.h" +#include "r819xU_cmdpkt.h" +/*---------------------------Define Local Constant---------------------------*/ +/* Debug constant*/ +#define CMPK_DEBOUNCE_CNT 1 +/* 2007/10/24 MH Add for printing a range of data. */ +#define CMPK_PRINT(Address)\ +{\ + unsigned char i;\ + u32 temp[10];\ + \ + memcpy(temp, Address, 40);\ + for (i = 0; i <40; i+=4)\ + printk("\r\n %08x", temp[i]);\ +}\ +/*---------------------------Define functions---------------------------------*/ + +bool +SendTxCommandPacket( + struct net_device *dev, + void* pData, + u32 DataLen + ) +{ + bool rtStatus = true; + struct r8192_priv *priv = ieee80211_priv(dev); + struct sk_buff *skb; + cb_desc *tcb_desc; + unsigned char *ptr_buf; + //bool bLastInitPacket = false; + + //PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK); + + //Get TCB and local buffer from common pool. (It is shared by CmdQ, MgntQ, and USB coalesce DataQ) + skb = dev_alloc_skb(USB_HWDESC_HEADER_LEN + DataLen + 4); + memcpy((unsigned char *)(skb->cb),&dev,sizeof(dev)); + tcb_desc = (cb_desc*)(skb->cb + MAX_DEV_ADDR_SIZE); + tcb_desc->queue_index = TXCMD_QUEUE; + tcb_desc->bCmdOrInit = DESC_PACKET_TYPE_NORMAL; + tcb_desc->bLastIniPkt = 0; + skb_reserve(skb, USB_HWDESC_HEADER_LEN); + ptr_buf = skb_put(skb, DataLen); + memset(ptr_buf,0,DataLen); + memcpy(ptr_buf,pData,DataLen); + tcb_desc->txbuf_size= (u16)DataLen; + + if(!priv->ieee80211->check_nic_enough_desc(dev,tcb_desc->queue_index)|| + (!skb_queue_empty(&priv->ieee80211->skb_waitQ[tcb_desc->queue_index]))||\ + (priv->ieee80211->queue_stop) ) { + RT_TRACE(COMP_FIRMWARE,"===================NULL packet==================================> tx full!\n"); + skb_queue_tail(&priv->ieee80211->skb_waitQ[tcb_desc->queue_index], skb); + } else { + priv->ieee80211->softmac_hard_start_xmit(skb,dev); + } + + //PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK); + return rtStatus; +} + +/*----------------------------------------------------------------------------- + * Function: cmpk_message_handle_tx() + * + * Overview: Driver internal module can call the API to send message to + * firmware side. For example, you can send a debug command packet. + * Or you can send a request for FW to modify RLX4181 LBUS HW bank. + * Otherwise, you can change MAC/PHT/RF register by firmware at + * run time. We do not support message more than one segment now. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 05/06/2008 amy porting from windows code. + * + *---------------------------------------------------------------------------*/ + extern bool cmpk_message_handle_tx( + struct net_device *dev, + u8* codevirtualaddress, + u32 packettype, + u32 buffer_len) +{ + + bool rt_status = true; +#ifdef RTL8192SU + return rt_status; +#else +#ifdef RTL8192U + return rt_status; +#else + struct r8192_priv *priv = ieee80211_priv(dev); + u16 frag_threshold; + u16 frag_length, frag_offset = 0; + //u16 total_size; + //int i; + + rt_firmware *pfirmware = priv->pFirmware; + struct sk_buff *skb; + unsigned char *seg_ptr; + cb_desc *tcb_desc; + u8 bLastIniPkt; + + firmware_init_param(dev); + //Fragmentation might be required + frag_threshold = pfirmware->cmdpacket_frag_thresold; + do { + if((buffer_len - frag_offset) > frag_threshold) { + frag_length = frag_threshold ; + bLastIniPkt = 0; + + } else { + frag_length = buffer_len - frag_offset; + bLastIniPkt = 1; + + } + + /* Allocate skb buffer to contain firmware info and tx descriptor info + * add 4 to avoid packet appending overflow. + * */ + #ifdef RTL8192U + skb = dev_alloc_skb(USB_HWDESC_HEADER_LEN + frag_length + 4); + #else + skb = dev_alloc_skb(frag_length + 4); + #endif + memcpy((unsigned char *)(skb->cb),&dev,sizeof(dev)); + tcb_desc = (cb_desc*)(skb->cb + MAX_DEV_ADDR_SIZE); + tcb_desc->queue_index = TXCMD_QUEUE; + tcb_desc->bCmdOrInit = packettype; + tcb_desc->bLastIniPkt = bLastIniPkt; + + #ifdef RTL8192U + skb_reserve(skb, USB_HWDESC_HEADER_LEN); + #endif + + seg_ptr = skb_put(skb, buffer_len); + /* + * Transform from little endian to big endian + * and pending zero + */ + memcpy(seg_ptr,codevirtualaddress,buffer_len); + tcb_desc->txbuf_size= (u16)buffer_len; + + + if(!priv->ieee80211->check_nic_enough_desc(dev,tcb_desc->queue_index)|| + (!skb_queue_empty(&priv->ieee80211->skb_waitQ[tcb_desc->queue_index]))||\ + (priv->ieee80211->queue_stop) ) { + RT_TRACE(COMP_FIRMWARE,"=====================================================> tx full!\n"); + skb_queue_tail(&priv->ieee80211->skb_waitQ[tcb_desc->queue_index], skb); + } else { + priv->ieee80211->softmac_hard_start_xmit(skb,dev); + } + + codevirtualaddress += frag_length; + frag_offset += frag_length; + + }while(frag_offset < buffer_len); + + return rt_status; + + +#endif +#endif +} /* CMPK_Message_Handle_Tx */ + +/*----------------------------------------------------------------------------- + * Function: cmpk_counttxstatistic() + * + * Overview: + * + * Input: PADAPTER pAdapter - . + * CMPK_TXFB_T *psTx_FB - . + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 05/12/2008 amy Create Version 0 porting from windows code. + * + *---------------------------------------------------------------------------*/ +static void +cmpk_count_txstatistic( + struct net_device *dev, + cmpk_txfb_t *pstx_fb) +{ + struct r8192_priv *priv = ieee80211_priv(dev); +#ifdef ENABLE_PS + RT_RF_POWER_STATE rtState; + + pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); + + // When RF is off, we should not count the packet for hw/sw synchronize + // reason, ie. there may be a duration while sw switch is changed and hw + // switch is being changed. 2006.12.04, by shien chang. + if (rtState == eRfOff) + { + return; + } +#endif + +#ifdef TODO + if(pAdapter->bInHctTest) + return; +#endif + /* We can not know the packet length and transmit type: broadcast or uni + or multicast. So the relative statistics must be collected in tx + feedback info. */ + if (pstx_fb->tok) + { + priv->stats.txfeedbackok++; + priv->stats.txoktotal++; + priv->stats.txokbytestotal += pstx_fb->pkt_length; + priv->stats.txokinperiod++; + + /* We can not make sure broadcast/multicast or unicast mode. */ + if (pstx_fb->pkt_type == PACKET_MULTICAST) + { + priv->stats.txmulticast++; + priv->stats.txbytesmulticast += pstx_fb->pkt_length; + } + else if (pstx_fb->pkt_type == PACKET_BROADCAST) + { + priv->stats.txbroadcast++; + priv->stats.txbytesbroadcast += pstx_fb->pkt_length; + } + else + { + priv->stats.txunicast++; + priv->stats.txbytesunicast += pstx_fb->pkt_length; + } + } + else + { + priv->stats.txfeedbackfail++; + priv->stats.txerrtotal++; + priv->stats.txerrbytestotal += pstx_fb->pkt_length; + + /* We can not make sure broadcast/multicast or unicast mode. */ + if (pstx_fb->pkt_type == PACKET_MULTICAST) + { + priv->stats.txerrmulticast++; + } + else if (pstx_fb->pkt_type == PACKET_BROADCAST) + { + priv->stats.txerrbroadcast++; + } + else + { + priv->stats.txerrunicast++; + } + } + + priv->stats.txretrycount += pstx_fb->retry_cnt; + priv->stats.txfeedbackretry += pstx_fb->retry_cnt; + +} /* cmpk_CountTxStatistic */ + + + +/*----------------------------------------------------------------------------- + * Function: cmpk_handle_tx_feedback() + * + * Overview: The function is responsible for extract the message inside TX + * feedbck message from firmware. It will contain dedicated info in + * ws-06-0063-rtl8190-command-packet-specification. Please + * refer to chapter "TX Feedback Element". We have to read 20 bytes + * in the command packet. + * + * Input: struct net_device * dev + * u8 * pmsg - Msg Ptr of the command packet. + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 05/08/2008 amy Create Version 0 porting from windows code. + * + *---------------------------------------------------------------------------*/ +static void +cmpk_handle_tx_feedback( + struct net_device *dev, + u8 * pmsg) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + cmpk_txfb_t rx_tx_fb; /* */ + + priv->stats.txfeedback++; + + /* 0. Display received message. */ + //cmpk_Display_Message(CMPK_RX_TX_FB_SIZE, pMsg); + + /* 1. Extract TX feedback info from RFD to temp structure buffer. */ + /* It seems that FW use big endian(MIPS) and DRV use little endian in + windows OS. So we have to read the content byte by byte or transfer + endian type before copy the message copy. */ +#if 0 // The TX FEEDBACK packet element address + //rx_tx_fb.Element_ID = pMsg[0]; + //rx_tx_fb.Length = pMsg[1]; + rx_tx_fb.TOK = pMsg[2]>>7; + rx_tx_fb.Fail_Reason = (pMsg[2] & 0x70) >> 4; + rx_tx_fb.TID = (pMsg[2] & 0x0F); + rx_tx_fb.Qos_Pkt = pMsg[3] >> 7; + rx_tx_fb.Bandwidth = (pMsg[3] & 0x40) >> 6; + rx_tx_fb.Retry_Cnt = pMsg[5]; + rx_tx_fb.Pkt_ID = (pMsg[6] << 8) | pMsg[7]; + rx_tx_fb.Seq_Num = (pMsg[8] << 8) | pMsg[9]; + rx_tx_fb.S_Rate = pMsg[10]; + rx_tx_fb.F_Rate = pMsg[11]; + rx_tx_fb.S_RTS_Rate = pMsg[12]; + rx_tx_fb.F_RTS_Rate = pMsg[13]; + rx_tx_fb.pkt_length = (pMsg[14] << 8) | pMsg[15]; +#endif + /* 2007/07/05 MH Use pointer to transfer structure memory. */ + //memcpy((UINT8 *)&rx_tx_fb, pMsg, sizeof(CMPK_TXFB_T)); + memcpy((u8*)&rx_tx_fb, pmsg, sizeof(cmpk_txfb_t)); + /* 2. Use tx feedback info to count TX statistics. */ + cmpk_count_txstatistic(dev, &rx_tx_fb); +#if 0 + /* 2007/07/11 MH Assign current operate rate. */ + if (pAdapter->RegWirelessMode == WIRELESS_MODE_A || + pAdapter->RegWirelessMode == WIRELESS_MODE_B || + pAdapter->RegWirelessMode == WIRELESS_MODE_G) + { + pMgntInfo->CurrentOperaRate = (rx_tx_fb.F_Rate & 0x7F); + } + else if (pAdapter->RegWirelessMode == WIRELESS_MODE_N_24G || + pAdapter->RegWirelessMode == WIRELESS_MODE_N_5G) + { + pMgntInfo->HTCurrentOperaRate = (rx_tx_fb.F_Rate & 0x8F); + } +#endif + /* 2007/01/17 MH Comment previous method for TX statistic function. */ + /* Collect info TX feedback packet to fill TCB. */ + /* We can not know the packet length and transmit type: broadcast or uni + or multicast. */ + //CountTxStatistics( pAdapter, &tcb ); + +} /* cmpk_Handle_Tx_Feedback */ + +void +cmdpkt_beacontimerinterrupt_819xusb( + struct net_device *dev +) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + u16 tx_rate; + { + // + // 070117, rcnjko: 87B have to S/W beacon for DTM encryption_cmn. + // + if(priv->ieee80211->current_network.mode == IEEE_A || + priv->ieee80211->current_network.mode == IEEE_N_5G || + (priv->ieee80211->current_network.mode == IEEE_N_24G && (!priv->ieee80211->pHTInfo->bCurSuppCCK))) + { + tx_rate = 60; + DMESG("send beacon frame tx rate is 6Mbpm\n"); + } + else + { + tx_rate =10; + DMESG("send beacon frame tx rate is 1Mbpm\n"); + } + + rtl819xusb_beacon_tx(dev,tx_rate); // HW Beacon + + } + +} + + + + +/*----------------------------------------------------------------------------- + * Function: cmpk_handle_interrupt_status() + * + * Overview: The function is responsible for extract the message from + * firmware. It will contain dedicated info in + * ws-07-0063-v06-rtl819x-command-packet-specification-070315.doc. + * Please refer to chapter "Interrupt Status Element". + * + * Input: struct net_device *dev, + * u8* pmsg - Message Pointer of the command packet. + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 05/12/2008 amy Add this for rtl8192 porting from windows code. + * + *---------------------------------------------------------------------------*/ +static void +cmpk_handle_interrupt_status( + struct net_device *dev, + u8* pmsg) +{ + cmpk_intr_sta_t rx_intr_status; /* */ + struct r8192_priv *priv = ieee80211_priv(dev); + + DMESG("---> cmpk_Handle_Interrupt_Status()\n"); + + /* 0. Display received message. */ + //cmpk_Display_Message(CMPK_RX_BEACON_STATE_SIZE, pMsg); + + /* 1. Extract TX feedback info from RFD to temp structure buffer. */ + /* It seems that FW use big endian(MIPS) and DRV use little endian in + windows OS. So we have to read the content byte by byte or transfer + endian type before copy the message copy. */ + //rx_bcn_state.Element_ID = pMsg[0]; + //rx_bcn_state.Length = pMsg[1]; + rx_intr_status.length = pmsg[1]; + if (rx_intr_status.length != (sizeof(cmpk_intr_sta_t) - 2)) + { + DMESG("cmpk_Handle_Interrupt_Status: wrong length!\n"); + return; + } + + + // Statistics of beacon for ad-hoc mode. + if( priv->ieee80211->iw_mode == IW_MODE_ADHOC) + { + //2 maybe need endian transform? + rx_intr_status.interrupt_status = *((u32 *)(pmsg + 4)); + //rx_intr_status.InterruptStatus = N2H4BYTE(*((UINT32 *)(pMsg + 4))); + + DMESG("interrupt status = 0x%x\n", rx_intr_status.interrupt_status); + + if (rx_intr_status.interrupt_status & ISR_TxBcnOk) + { + priv->ieee80211->bibsscoordinator = true; + priv->stats.txbeaconokint++; + } + else if (rx_intr_status.interrupt_status & ISR_TxBcnErr) + { + priv->ieee80211->bibsscoordinator = false; + priv->stats.txbeaconerr++; + } + + if (rx_intr_status.interrupt_status & ISR_BcnTimerIntr) + { + cmdpkt_beacontimerinterrupt_819xusb(dev); + } + + } + + // Other informations in interrupt status we need? + + + DMESG("<---- cmpk_handle_interrupt_status()\n"); + +} /* cmpk_handle_interrupt_status */ + + +/*----------------------------------------------------------------------------- + * Function: cmpk_handle_query_config_rx() + * + * Overview: The function is responsible for extract the message from + * firmware. It will contain dedicated info in + * ws-06-0063-rtl8190-command-packet-specification. Please + * refer to chapter "Beacon State Element". + * + * Input: u8 * pmsg - Message Pointer of the command packet. + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 05/12/2008 amy Create Version 0 porting from windows code. + * + *---------------------------------------------------------------------------*/ +static void +cmpk_handle_query_config_rx( + struct net_device *dev, + u8* pmsg) +{ + cmpk_query_cfg_t rx_query_cfg; /* */ + + /* 0. Display received message. */ + //cmpk_Display_Message(CMPK_RX_BEACON_STATE_SIZE, pMsg); + + /* 1. Extract TX feedback info from RFD to temp structure buffer. */ + /* It seems that FW use big endian(MIPS) and DRV use little endian in + windows OS. So we have to read the content byte by byte or transfer + endian type before copy the message copy. */ + //rx_query_cfg.Element_ID = pMsg[0]; + //rx_query_cfg.Length = pMsg[1]; + rx_query_cfg.cfg_action = (pmsg[4] & 0x80000000)>>31; + rx_query_cfg.cfg_type = (pmsg[4] & 0x60) >> 5; + rx_query_cfg.cfg_size = (pmsg[4] & 0x18) >> 3; + rx_query_cfg.cfg_page = (pmsg[6] & 0x0F) >> 0; + rx_query_cfg.cfg_offset = pmsg[7]; + rx_query_cfg.value = (pmsg[8] << 24) | (pmsg[9] << 16) | + (pmsg[10] << 8) | (pmsg[11] << 0); + rx_query_cfg.mask = (pmsg[12] << 24) | (pmsg[13] << 16) | + (pmsg[14] << 8) | (pmsg[15] << 0); + +} /* cmpk_Handle_Query_Config_Rx */ + + +/*----------------------------------------------------------------------------- + * Function: cmpk_count_tx_status() + * + * Overview: Count aggregated tx status from firmwar of one type rx command + * packet element id = RX_TX_STATUS. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 05/12/2008 amy Create Version 0 porting from windows code. + * + *---------------------------------------------------------------------------*/ +static void cmpk_count_tx_status( struct net_device *dev, + cmpk_tx_status_t *pstx_status) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + +#ifdef ENABLE_PS + + RT_RF_POWER_STATE rtstate; + + pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); + + // When RF is off, we should not count the packet for hw/sw synchronize + // reason, ie. there may be a duration while sw switch is changed and hw + // switch is being changed. 2006.12.04, by shien chang. + if (rtState == eRfOff) + { + return; + } +#endif + + priv->stats.txfeedbackok += pstx_status->txok; + priv->stats.txoktotal += pstx_status->txok; + + priv->stats.txfeedbackfail += pstx_status->txfail; + priv->stats.txerrtotal += pstx_status->txfail; + + priv->stats.txretrycount += pstx_status->txretry; + priv->stats.txfeedbackretry += pstx_status->txretry; + + //pAdapter->TxStats.NumTxOkBytesTotal += psTx_FB->pkt_length; + //pAdapter->TxStats.NumTxErrBytesTotal += psTx_FB->pkt_length; + //pAdapter->MgntInfo.LinkDetectInfo.NumTxOkInPeriod++; + + priv->stats.txmulticast += pstx_status->txmcok; + priv->stats.txbroadcast += pstx_status->txbcok; + priv->stats.txunicast += pstx_status->txucok; + + priv->stats.txerrmulticast += pstx_status->txmcfail; + priv->stats.txerrbroadcast += pstx_status->txbcfail; + priv->stats.txerrunicast += pstx_status->txucfail; + + priv->stats.txbytesmulticast += pstx_status->txmclength; + priv->stats.txbytesbroadcast += pstx_status->txbclength; + priv->stats.txbytesunicast += pstx_status->txuclength; + + priv->stats.last_packet_rate = pstx_status->rate; +} /* cmpk_CountTxStatus */ + + + +/*----------------------------------------------------------------------------- + * Function: cmpk_handle_tx_status() + * + * Overview: Firmware add a new tx feedback status to reduce rx command + * packet buffer operation load. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 05/12/2008 amy Create Version 0 porting from windows code. + * + *---------------------------------------------------------------------------*/ +static void +cmpk_handle_tx_status( + struct net_device *dev, + u8* pmsg) +{ + cmpk_tx_status_t rx_tx_sts; /* */ + + memcpy((void*)&rx_tx_sts, (void*)pmsg, sizeof(cmpk_tx_status_t)); + /* 2. Use tx feedback info to count TX statistics. */ + cmpk_count_tx_status(dev, &rx_tx_sts); + +} /* cmpk_Handle_Tx_Status */ + + +/*----------------------------------------------------------------------------- + * Function: cmpk_handle_tx_rate_history() + * + * Overview: Firmware add a new tx rate history + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 05/12/2008 amy Create Version 0 porting from windows code. + * + *---------------------------------------------------------------------------*/ +static void +cmpk_handle_tx_rate_history( + struct net_device *dev, + u8* pmsg) +{ + cmpk_tx_rahis_t *ptxrate; +// RT_RF_POWER_STATE rtState; + u8 i, j; + u16 length = sizeof(cmpk_tx_rahis_t); + u32 *ptemp; + struct r8192_priv *priv = ieee80211_priv(dev); + + +#ifdef ENABLE_PS + pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); + + // When RF is off, we should not count the packet for hw/sw synchronize + // reason, ie. there may be a duration while sw switch is changed and hw + // switch is being changed. 2006.12.04, by shien chang. + if (rtState == eRfOff) + { + return; + } +#endif + + ptemp = (u32 *)pmsg; + + // + // Do endian transfer to word alignment(16 bits) for windows system. + // You must do different endian transfer for linux and MAC OS + // + for (i = 0; i < (length/4); i++) + { + u16 temp1, temp2; + + temp1 = ptemp[i]&0x0000FFFF; + temp2 = ptemp[i]>>16; + ptemp[i] = (temp1<<16)|temp2; + } + + ptxrate = (cmpk_tx_rahis_t *)pmsg; + + if (ptxrate == NULL ) + { + return; + } + + for (i = 0; i < 16; i++) + { + // Collect CCK rate packet num + if (i < 4) + priv->stats.txrate.cck[i] += ptxrate->cck[i]; + + // Collect OFDM rate packet num + if (i< 8) + priv->stats.txrate.ofdm[i] += ptxrate->ofdm[i]; + + for (j = 0; j < 4; j++) + priv->stats.txrate.ht_mcs[j][i] += ptxrate->ht_mcs[j][i]; + } + +} /* cmpk_Handle_Tx_Rate_History */ + + +/*----------------------------------------------------------------------------- + * Function: cmpk_message_handle_rx() + * + * Overview: In the function, we will capture different RX command packet + * info. Every RX command packet element has different message + * length and meaning in content. We only support three type of RX + * command packet now. Please refer to document + * ws-06-0063-rtl8190-command-packet-specification. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 05/06/2008 amy Create Version 0 porting from windows code. + * + *---------------------------------------------------------------------------*/ +extern u32 +cmpk_message_handle_rx( + struct net_device *dev, + struct ieee80211_rx_stats *pstats) +{ +// u32 debug_level = DBG_LOUD; + struct r8192_priv *priv = ieee80211_priv(dev); + int total_length; + u8 cmd_length, exe_cnt = 0; + u8 element_id; + u8 *pcmd_buff; + + /* 0. Check inpt arguments. If is is a command queue message or pointer is + null. */ + if (/*(prfd->queue_id != CMPK_RX_QUEUE_ID) || */(pstats== NULL)) + { + /* Print error message. */ + /*RT_TRACE(COMP_SEND, DebugLevel, + ("\n\r[CMPK]-->Err queue id or pointer"));*/ + return 0; /* This is not a command packet. */ + } + + /* 1. Read received command packet message length from RFD. */ + total_length = pstats->Length; + + /* 2. Read virtual address from RFD. */ + pcmd_buff = pstats->virtual_address; + + /* 3. Read command pakcet element id and length. */ + element_id = pcmd_buff[0]; + /*RT_TRACE(COMP_SEND, DebugLevel, + ("\n\r[CMPK]-->element ID=%d Len=%d", element_id, total_length));*/ + + /* 4. Check every received command packet conent according to different + element type. Because FW may aggregate RX command packet to minimize + transmit time between DRV and FW.*/ + // Add a counter to prevent to locked in the loop too long + while (total_length > 0 || exe_cnt++ >100) + { + /* 2007/01/17 MH We support aggregation of different cmd in the same packet. */ + element_id = pcmd_buff[0]; + + switch(element_id) + { + case RX_TX_FEEDBACK: + cmpk_handle_tx_feedback (dev, pcmd_buff); + cmd_length = CMPK_RX_TX_FB_SIZE; + break; + + case RX_INTERRUPT_STATUS: + cmpk_handle_interrupt_status(dev, pcmd_buff); + cmd_length = sizeof(cmpk_intr_sta_t); + break; + + case BOTH_QUERY_CONFIG: + cmpk_handle_query_config_rx(dev, pcmd_buff); + cmd_length = CMPK_BOTH_QUERY_CONFIG_SIZE; + break; + + case RX_TX_STATUS: + cmpk_handle_tx_status(dev, pcmd_buff); + cmd_length = CMPK_RX_TX_STS_SIZE; + break; + + case RX_TX_PER_PKT_FEEDBACK: + // You must at lease add a switch case element here, + // Otherwise, we will jump to default case. + //DbgPrint("CCX Test\r\n"); + cmd_length = CMPK_RX_TX_FB_SIZE; + break; + + case RX_TX_RATE_HISTORY: + //DbgPrint(" rx tx rate history\r\n"); + cmpk_handle_tx_rate_history(dev, pcmd_buff); + cmd_length = CMPK_TX_RAHIS_SIZE; + break; + + default: + + RT_TRACE(COMP_ERR, "---->cmpk_message_handle_rx():unknow CMD Element\n"); + return 1; /* This is a command packet. */ + } + // 2007/01/22 MH Display received rx command packet info. + //cmpk_Display_Message(cmd_length, pcmd_buff); + + // 2007/01/22 MH Add to display tx statistic. + //cmpk_DisplayTxStatistic(pAdapter); + + /* 2007/03/09 MH Collect sidderent cmd element pkt num. */ + priv->stats.rxcmdpkt[element_id]++; + + total_length -= cmd_length; + pcmd_buff += cmd_length; + } /* while (total_length > 0) */ + return 1; /* This is a command packet. */ + +} /* CMPK_Message_Handle_Rx */ diff --git a/drivers/staging/rtl8192su/r819xU_cmdpkt.h b/drivers/staging/rtl8192su/r819xU_cmdpkt.h new file mode 100644 index 000000000000..f67af6cfd201 --- /dev/null +++ b/drivers/staging/rtl8192su/r819xU_cmdpkt.h @@ -0,0 +1,219 @@ +#ifndef R819XUSB_CMDPKT_H +#define R819XUSB_CMDPKT_H +/* Different command packet have dedicated message length and definition. */ +#define CMPK_RX_TX_FB_SIZE sizeof(cmpk_txfb_t) //20 +#define CMPK_TX_SET_CONFIG_SIZE sizeof(cmpk_set_cfg_t) //16 +#define CMPK_BOTH_QUERY_CONFIG_SIZE sizeof(cmpk_set_cfg_t) //16 +#define CMPK_RX_TX_STS_SIZE sizeof(cmpk_tx_status_t)// +#define CMPK_RX_DBG_MSG_SIZE sizeof(cmpk_rx_dbginfo_t)// +#define CMPK_TX_RAHIS_SIZE sizeof(cmpk_tx_rahis_t) + +/* 2008/05/08 amy For USB constant. */ +#define ISR_TxBcnOk BIT27 // Transmit Beacon OK +#define ISR_TxBcnErr BIT26 // Transmit Beacon Error +#define ISR_BcnTimerIntr BIT13 // Beacon Timer Interrupt + +#if 0 +/* Define packet type. */ +typedef enum tag_packet_type +{ + PACKET_BROADCAST, + PACKET_MULTICAST, + PACKET_UNICAST, + PACKET_TYPE_MAX +}cmpk_pkt_type_e; +#endif + +/* Define element ID of command packet. */ + +/*------------------------------Define structure----------------------------*/ +/* Define different command packet structure. */ +/* 1. RX side: TX feedback packet. */ +typedef struct tag_cmd_pkt_tx_feedback +{ + // DWORD 0 + u8 element_id; /* Command packet type. */ + u8 length; /* Command packet length. */ + /* 2007/07/05 MH Change tx feedback info field. */ + /*------TX Feedback Info Field */ + u8 TID:4; /* */ + u8 fail_reason:3; /* */ + u8 tok:1; /* Transmit ok. */ + u8 reserve1:4; /* */ + u8 pkt_type:2; /* */ + u8 bandwidth:1; /* */ + u8 qos_pkt:1; /* */ + + // DWORD 1 + u8 reserve2; /* */ + /*------TX Feedback Info Field */ + u8 retry_cnt; /* */ + u16 pkt_id; /* */ + + // DWORD 3 + u16 seq_num; /* */ + u8 s_rate; /* Start rate. */ + u8 f_rate; /* Final rate. */ + + // DWORD 4 + u8 s_rts_rate; /* */ + u8 f_rts_rate; /* */ + u16 pkt_length; /* */ + + // DWORD 5 + u16 reserve3; /* */ + u16 duration; /* */ +}cmpk_txfb_t; + +/* 2. RX side: Interrupt status packet. It includes Beacon State, + Beacon Timer Interrupt and other useful informations in MAC ISR Reg. */ +typedef struct tag_cmd_pkt_interrupt_status +{ + u8 element_id; /* Command packet type. */ + u8 length; /* Command packet length. */ + u16 reserve; + u32 interrupt_status; /* Interrupt Status. */ +}cmpk_intr_sta_t; + + +/* 3. TX side: Set configuration packet. */ +typedef struct tag_cmd_pkt_set_configuration +{ + u8 element_id; /* Command packet type. */ + u8 length; /* Command packet length. */ + u16 reserve1; /* */ + u8 cfg_reserve1:3; + u8 cfg_size:2; /* Configuration info. */ + u8 cfg_type:2; /* Configuration info. */ + u8 cfg_action:1; /* Configuration info. */ + u8 cfg_reserve2; /* Configuration info. */ + u8 cfg_page:4; /* Configuration info. */ + u8 cfg_reserve3:4; /* Configuration info. */ + u8 cfg_offset; /* Configuration info. */ + u32 value; /* */ + u32 mask; /* */ +}cmpk_set_cfg_t; + +/* 4. Both side : TX/RX query configuraton packet. The query structure is the + same as set configuration. */ +#define cmpk_query_cfg_t cmpk_set_cfg_t + +/* 5. Multi packet feedback status. */ +typedef struct tag_tx_stats_feedback // PJ quick rxcmd 09042007 +{ + // For endian transfer --> Driver will not the same as firmware structure. + // DW 0 + u16 reserve1; + u8 length; // Command packet length + u8 element_id; // Command packet type + + // DW 1 + u16 txfail; // Tx Fail count + u16 txok; // Tx ok count + + // DW 2 + u16 txmcok; // tx multicast + u16 txretry; // Tx Retry count + + // DW 3 + u16 txucok; // tx unicast + u16 txbcok; // tx broadcast + + // DW 4 + u16 txbcfail; // + u16 txmcfail; // + + // DW 5 + u16 reserve2; // + u16 txucfail; // + + // DW 6-8 + u32 txmclength; + u32 txbclength; + u32 txuclength; + + // DW 9 + u16 reserve3_23; + u8 reserve3_1; + u8 rate; +}__attribute__((packed)) cmpk_tx_status_t; + +/* 6. Debug feedback message. */ +/* 2007/10/23 MH Define RX debug message */ +typedef struct tag_rx_debug_message_feedback +{ + // For endian transfer --> for driver + // DW 0 + u16 reserve1; + u8 length; // Command packet length + u8 element_id; // Command packet type + + // DW 1-?? + // Variable debug message. + +}cmpk_rx_dbginfo_t; + +/* 2008/03/20 MH Define transmit rate history. For big endian format. */ +typedef struct tag_tx_rate_history +{ + // For endian transfer --> for driver + // DW 0 + u8 element_id; // Command packet type + u8 length; // Command packet length + u16 reserved1; + + // DW 1-2 CCK rate counter + u16 cck[4]; + + // DW 3-6 + u16 ofdm[8]; + + // DW 7-14 + //UINT16 MCS_BW0_SG0[16]; + + // DW 15-22 + //UINT16 MCS_BW1_SG0[16]; + + // DW 23-30 + //UINT16 MCS_BW0_SG1[16]; + + // DW 31-38 + //UINT16 MCS_BW1_SG1[16]; + + // DW 7-14 BW=0 SG=0 + // DW 15-22 BW=1 SG=0 + // DW 23-30 BW=0 SG=1 + // DW 31-38 BW=1 SG=1 + u16 ht_mcs[4][16]; + +}__attribute__((packed)) cmpk_tx_rahis_t; + +typedef enum tag_command_packet_directories +{ + RX_TX_FEEDBACK = 0, + RX_INTERRUPT_STATUS = 1, + TX_SET_CONFIG = 2, + BOTH_QUERY_CONFIG = 3, + RX_TX_STATUS = 4, + RX_DBGINFO_FEEDBACK = 5, + RX_TX_PER_PKT_FEEDBACK = 6, + RX_TX_RATE_HISTORY = 7, + RX_CMD_ELE_MAX +}cmpk_element_e; + +#if 0 +typedef enum _rt_status{ + RT_STATUS_SUCCESS, + RT_STATUS_FAILURE, + RT_STATUS_PENDING, + RT_STATUS_RESOURCE +}rt_status,*prt_status; +#endif + +extern bool cmpk_message_handle_tx(struct net_device *dev, u8* codevirtualaddress, u32 packettype, u32 buffer_len); + +extern u32 cmpk_message_handle_rx(struct net_device *dev, struct ieee80211_rx_stats * pstats); +extern bool SendTxCommandPacket( struct net_device *dev, void* pData, u32 DataLen); + + +#endif diff --git a/drivers/staging/rtl8192su/r819xU_firmware.c b/drivers/staging/rtl8192su/r819xU_firmware.c new file mode 100644 index 000000000000..219f71e8cda7 --- /dev/null +++ b/drivers/staging/rtl8192su/r819xU_firmware.c @@ -0,0 +1,707 @@ +/************************************************************************************************** + * Procedure: Init boot code/firmware code/data session + * + * Description: This routine will intialize firmware. If any error occurs during the initialization + * process, the routine shall terminate immediately and return fail. + * NIC driver should call NdisOpenFile only from MiniportInitialize. + * + * Arguments: The pointer of the adapter + + * Returns: + * NDIS_STATUS_FAILURE - the following initialization process should be terminated + * NDIS_STATUS_SUCCESS - if firmware initialization process success +**************************************************************************************************/ +//#include "ieee80211.h" +#include "r8192U.h" +#include "r8192U_hw.h" +#include "r819xU_firmware_img.h" +#include "r819xU_firmware.h" +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) +#include <linux/firmware.h> +#endif +void firmware_init_param(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + rt_firmware *pfirmware = priv->pFirmware; + + pfirmware->cmdpacket_frag_thresold = GET_COMMAND_PACKET_FRAG_THRESHOLD(MAX_TRANSMIT_BUFFER_SIZE); +} + +/* + * segment the img and use the ptr and length to remember info on each segment + * + */ +bool fw_download_code(struct net_device *dev, u8 *code_virtual_address, u32 buffer_len) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + bool rt_status = true; + u16 frag_threshold; + u16 frag_length, frag_offset = 0; + //u16 total_size; + int i; + + rt_firmware *pfirmware = priv->pFirmware; + struct sk_buff *skb; + unsigned char *seg_ptr; + cb_desc *tcb_desc; + u8 bLastIniPkt; + + firmware_init_param(dev); + //Fragmentation might be required + frag_threshold = pfirmware->cmdpacket_frag_thresold; + do { + if((buffer_len - frag_offset) > frag_threshold) { + frag_length = frag_threshold ; + bLastIniPkt = 0; + + } else { + frag_length = buffer_len - frag_offset; + bLastIniPkt = 1; + + } + + /* Allocate skb buffer to contain firmware info and tx descriptor info + * add 4 to avoid packet appending overflow. + * */ + #ifdef RTL8192U + skb = dev_alloc_skb(USB_HWDESC_HEADER_LEN + frag_length + 4); + #else + skb = dev_alloc_skb(frag_length + 4); + #endif + memcpy((unsigned char *)(skb->cb),&dev,sizeof(dev)); + tcb_desc = (cb_desc*)(skb->cb + MAX_DEV_ADDR_SIZE); + tcb_desc->queue_index = TXCMD_QUEUE; + tcb_desc->bCmdOrInit = DESC_PACKET_TYPE_INIT; + tcb_desc->bLastIniPkt = bLastIniPkt; + + #ifdef RTL8192U + skb_reserve(skb, USB_HWDESC_HEADER_LEN); + #endif + seg_ptr = skb->data; + /* + * Transform from little endian to big endian + * and pending zero + */ + for(i=0 ; i < frag_length; i+=4) { + *seg_ptr++ = ((i+0)<frag_length)?code_virtual_address[i+3]:0; + *seg_ptr++ = ((i+1)<frag_length)?code_virtual_address[i+2]:0; + *seg_ptr++ = ((i+2)<frag_length)?code_virtual_address[i+1]:0; + *seg_ptr++ = ((i+3)<frag_length)?code_virtual_address[i+0]:0; + } + tcb_desc->txbuf_size= (u16)i; + skb_put(skb, i); + + if(!priv->ieee80211->check_nic_enough_desc(dev,tcb_desc->queue_index)|| + (!skb_queue_empty(&priv->ieee80211->skb_waitQ[tcb_desc->queue_index]))||\ + (priv->ieee80211->queue_stop) ) { + RT_TRACE(COMP_FIRMWARE,"=====================================================> tx full!\n"); + skb_queue_tail(&priv->ieee80211->skb_waitQ[tcb_desc->queue_index], skb); + } else { + priv->ieee80211->softmac_hard_start_xmit(skb,dev); + } + + code_virtual_address += frag_length; + frag_offset += frag_length; + + }while(frag_offset < buffer_len); + + return rt_status; + +#if 0 +cmdsend_downloadcode_fail: + rt_status = false; + RT_TRACE(COMP_ERR, "CmdSendDownloadCode fail !!\n"); + return rt_status; +#endif +} + +bool +fwSendNullPacket( + struct net_device *dev, + u32 Length +) +{ + bool rtStatus = true; + struct r8192_priv *priv = ieee80211_priv(dev); + struct sk_buff *skb; + cb_desc *tcb_desc; + unsigned char *ptr_buf; + bool bLastInitPacket = false; + + //PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK); + + //Get TCB and local buffer from common pool. (It is shared by CmdQ, MgntQ, and USB coalesce DataQ) + skb = dev_alloc_skb(Length+ 4); + memcpy((unsigned char *)(skb->cb),&dev,sizeof(dev)); + tcb_desc = (cb_desc*)(skb->cb + MAX_DEV_ADDR_SIZE); + tcb_desc->queue_index = TXCMD_QUEUE; + tcb_desc->bCmdOrInit = DESC_PACKET_TYPE_INIT; + tcb_desc->bLastIniPkt = bLastInitPacket; + ptr_buf = skb_put(skb, Length); + memset(ptr_buf,0,Length); + tcb_desc->txbuf_size= (u16)Length; + + if(!priv->ieee80211->check_nic_enough_desc(dev,tcb_desc->queue_index)|| + (!skb_queue_empty(&priv->ieee80211->skb_waitQ[tcb_desc->queue_index]))||\ + (priv->ieee80211->queue_stop) ) { + RT_TRACE(COMP_FIRMWARE,"===================NULL packet==================================> tx full!\n"); + skb_queue_tail(&priv->ieee80211->skb_waitQ[tcb_desc->queue_index], skb); + } else { + priv->ieee80211->softmac_hard_start_xmit(skb,dev); + } + + //PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK); + return rtStatus; +} + +#if 0 +/* + * Procedure : Download code into IMEM or DMEM + * Description: This routine will intialize firmware. If any error occurs during the initialization + * process, the routine shall terminate immediately and return fail. + * The routine copy virtual address get from opening of file into shared memory + * allocated during initialization. If code size larger than a conitneous shared + * memory may contain, the code should be divided into several section. + * !!!NOTES This finction should only be called during MPInitialization because + * A NIC driver should call NdisOpenFile only from MiniportInitialize. + * Arguments : The pointer of the adapter + * Code address (Virtual address, should fill descriptor with physical address) + * Code size + * Returns : + * RT_STATUS_FAILURE - the following initialization process should be terminated + * RT_STATUS_SUCCESS - if firmware initialization process success + */ +bool fwsend_download_code(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + rt_firmware *pfirmware = (rt_firmware*)(&priv->firmware); + + bool rt_status = true; + u16 length = 0; + u16 offset = 0; + u16 frag_threhold; + bool last_init_packet = false; + u32 check_txcmdwait_queueemptytime = 100000; + u16 cmd_buf_len; + u8 *ptr_cmd_buf; + + /* reset to 0 for first segment of img download */ + pfirmware->firmware_seg_index = 1; + + if(pfirmware->firmware_seg_index == pfirmware->firmware_seg_maxnum) { + last_init_packet = 1; + } + + cmd_buf_len = pfirmware->firmware_seg_container[pfirmware->firmware_seg_index-1].seg_size; + ptr_cmd_buf = pfirmware->firmware_seg_container[pfirmware->firmware_seg_index-1].seg_ptr; + rtl819xU_tx_cmd(dev, ptr_cmd_buf, cmd_buf_len, last_init_packet, DESC_PACKET_TYPE_INIT); + + rt_status = true; + return rt_status; +} +#endif + +//----------------------------------------------------------------------------- +// Procedure: Check whether main code is download OK. If OK, turn on CPU +// +// Description: CPU register locates in different page against general register. +// Switch to CPU register in the begin and switch back before return +// +// +// Arguments: The pointer of the adapter +// +// Returns: +// NDIS_STATUS_FAILURE - the following initialization process should be terminated +// NDIS_STATUS_SUCCESS - if firmware initialization process success +//----------------------------------------------------------------------------- +bool CPUcheck_maincodeok_turnonCPU(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + bool rt_status = true; + int check_putcodeOK_time = 200000, check_bootOk_time = 200000; + u32 CPU_status = 0; + + /* Check whether put code OK */ + do { + CPU_status = read_nic_dword(dev, CPU_GEN); + + if((CPU_status&CPU_GEN_PUT_CODE_OK) || (priv->usb_error==true)) + break; + + }while(check_putcodeOK_time--); + + if(!(CPU_status&CPU_GEN_PUT_CODE_OK)) { + RT_TRACE(COMP_ERR, "Download Firmware: Put code fail!\n"); + goto CPUCheckMainCodeOKAndTurnOnCPU_Fail; + } else { + RT_TRACE(COMP_FIRMWARE, "Download Firmware: Put code ok!\n"); + } + + /* Turn On CPU */ + CPU_status = read_nic_dword(dev, CPU_GEN); + write_nic_byte(dev, CPU_GEN, (u8)((CPU_status|CPU_GEN_PWR_STB_CPU)&0xff)); + mdelay(1000); + + /* Check whether CPU boot OK */ + do { + CPU_status = read_nic_dword(dev, CPU_GEN); + + if((CPU_status&CPU_GEN_BOOT_RDY)||(priv->usb_error == true)) + break; + }while(check_bootOk_time--); + + if(!(CPU_status&CPU_GEN_BOOT_RDY)) { + goto CPUCheckMainCodeOKAndTurnOnCPU_Fail; + } else { + RT_TRACE(COMP_FIRMWARE, "Download Firmware: Boot ready!\n"); + } + + return rt_status; + +CPUCheckMainCodeOKAndTurnOnCPU_Fail: + RT_TRACE(COMP_ERR, "ERR in %s()\n", __FUNCTION__); + rt_status = FALSE; + return rt_status; +} + +bool CPUcheck_firmware_ready(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + bool rt_status = true; + int check_time = 200000; + u32 CPU_status = 0; + + /* Check Firmware Ready */ + do { + CPU_status = read_nic_dword(dev, CPU_GEN); + + if((CPU_status&CPU_GEN_FIRM_RDY)||(priv->usb_error == true)) + break; + + }while(check_time--); + + if(!(CPU_status&CPU_GEN_FIRM_RDY)) + goto CPUCheckFirmwareReady_Fail; + else + RT_TRACE(COMP_FIRMWARE, "Download Firmware: Firmware ready!\n"); + + return rt_status; + +CPUCheckFirmwareReady_Fail: + RT_TRACE(COMP_ERR, "ERR in %s()\n", __FUNCTION__); + rt_status = false; + return rt_status; + +} + +bool init_firmware(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + bool rt_status = TRUE; + + u8 *firmware_img_buf[3] = { &rtl8190_fwboot_array[0], + &rtl8190_fwmain_array[0], + &rtl8190_fwdata_array[0]}; + + u32 firmware_img_len[3] = { sizeof(rtl8190_fwboot_array), + sizeof(rtl8190_fwmain_array), + sizeof(rtl8190_fwdata_array)}; + u32 file_length = 0; + u8 *mapped_file = NULL; + u32 init_step = 0; + opt_rst_type_e rst_opt = OPT_SYSTEM_RESET; + firmware_init_step_e starting_state = FW_INIT_STEP0_BOOT; + + rt_firmware *pfirmware = priv->pFirmware; + const struct firmware *fw_entry; + const char *fw_name[3] = { "RTL8192U/boot.img", + "RTL8192U/main.img", + "RTL8192U/data.img"}; + int rc; + + RT_TRACE(COMP_FIRMWARE, " PlatformInitFirmware()==>\n"); + + if (pfirmware->firmware_status == FW_STATUS_0_INIT ) { + /* it is called by reset */ + rst_opt = OPT_SYSTEM_RESET; + starting_state = FW_INIT_STEP0_BOOT; + // TODO: system reset + + }else if(pfirmware->firmware_status == FW_STATUS_5_READY) { + /* it is called by Initialize */ + rst_opt = OPT_FIRMWARE_RESET; + starting_state = FW_INIT_STEP2_DATA; + }else { + RT_TRACE(COMP_FIRMWARE, "PlatformInitFirmware: undefined firmware state\n"); + } + + /* + * Download boot, main, and data image for System reset. + * Download data image for firmware reseta + */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) + priv->firmware_source = FW_SOURCE_HEADER_FILE; +#else + priv->firmware_source = FW_SOURCE_IMG_FILE; +#endif + for(init_step = starting_state; init_step <= FW_INIT_STEP2_DATA; init_step++) { + /* + * Open Image file, and map file to contineous memory if open file success. + * or read image file from array. Default load from IMG file + */ + if(rst_opt == OPT_SYSTEM_RESET) { + switch(priv->firmware_source) { + case FW_SOURCE_IMG_FILE: +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + if(pfirmware->firmware_buf_size[init_step] == 0) { + rc = request_firmware(&fw_entry, fw_name[init_step],&priv->udev->dev); + if(rc < 0 ) { + RT_TRACE(COMP_ERR, "request firmware fail!\n"); + goto download_firmware_fail; + } + + if(fw_entry->size > sizeof(pfirmware->firmware_buf[init_step])) { + //RT_TRACE(COMP_ERR, "img file size exceed the container buffer fail!\n"); + RT_TRACE(COMP_FIRMWARE, "img file size exceed the container buffer fail!, entry_size = %d, buf_size = %d\n",fw_entry->size,sizeof(pfirmware->firmware_buf[init_step])); + + goto download_firmware_fail; + } + + if(init_step != FW_INIT_STEP1_MAIN) { + memcpy(pfirmware->firmware_buf[init_step],fw_entry->data,fw_entry->size); + pfirmware->firmware_buf_size[init_step] = fw_entry->size; + } else { +#ifdef RTL8190P + memcpy(pfirmware->firmware_buf[init_step],fw_entry->data,fw_entry->size); + pfirmware->firmware_buf_size[init_step] = fw_entry->size; +#else + memset(pfirmware->firmware_buf[init_step],0,128); + memcpy(&pfirmware->firmware_buf[init_step][128],fw_entry->data,fw_entry->size); + mapped_file = pfirmware->firmware_buf[init_step]; + pfirmware->firmware_buf_size[init_step] = fw_entry->size+128; +#endif + } + //pfirmware->firmware_buf_size = file_length; + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + if(rst_opt == OPT_SYSTEM_RESET) { + release_firmware(fw_entry); + } +#endif + } + mapped_file = pfirmware->firmware_buf[init_step]; + file_length = pfirmware->firmware_buf_size[init_step]; +#endif + + break; + + case FW_SOURCE_HEADER_FILE: + mapped_file = firmware_img_buf[init_step]; + file_length = firmware_img_len[init_step]; + if(init_step == FW_INIT_STEP2_DATA) { + memcpy(pfirmware->firmware_buf[init_step], mapped_file, file_length); + pfirmware->firmware_buf_size[init_step] = file_length; + } + break; + + default: + break; + } + + + }else if(rst_opt == OPT_FIRMWARE_RESET ) { + /* we only need to download data.img here */ + mapped_file = pfirmware->firmware_buf[init_step]; + file_length = pfirmware->firmware_buf_size[init_step]; + } + + /* Download image file */ + /* The firmware download process is just as following, + * 1. that is each packet will be segmented and inserted to the wait queue. + * 2. each packet segment will be put in the skb_buff packet. + * 3. each skb_buff packet data content will already include the firmware info + * and Tx descriptor info + * */ + rt_status = fw_download_code(dev,mapped_file,file_length); + + if(rt_status != TRUE) { + goto download_firmware_fail; + } + + switch(init_step) { + case FW_INIT_STEP0_BOOT: + /* Download boot + * initialize command descriptor. + * will set polling bit when firmware code is also configured + */ + pfirmware->firmware_status = FW_STATUS_1_MOVE_BOOT_CODE; +#ifdef RTL8190P + // To initialize IMEM, CPU move code from 0x80000080, hence, we send 0x80 byte packet + rt_status = fwSendNullPacket(dev, RTL8190_CPU_START_OFFSET); + if(rt_status != true) + { + RT_TRACE(COMP_INIT, "fwSendNullPacket() fail ! \n"); + goto download_firmware_fail; + } +#endif + //mdelay(1000); + /* + * To initialize IMEM, CPU move code from 0x80000080, + * hence, we send 0x80 byte packet + */ + break; + + case FW_INIT_STEP1_MAIN: + /* Download firmware code. Wait until Boot Ready and Turn on CPU */ + pfirmware->firmware_status = FW_STATUS_2_MOVE_MAIN_CODE; + + /* Check Put Code OK and Turn On CPU */ + rt_status = CPUcheck_maincodeok_turnonCPU(dev); + if(rt_status != TRUE) { + RT_TRACE(COMP_ERR, "CPUcheck_maincodeok_turnonCPU fail!\n"); + goto download_firmware_fail; + } + + pfirmware->firmware_status = FW_STATUS_3_TURNON_CPU; + break; + + case FW_INIT_STEP2_DATA: + /* download initial data code */ + pfirmware->firmware_status = FW_STATUS_4_MOVE_DATA_CODE; + mdelay(1); + + rt_status = CPUcheck_firmware_ready(dev); + if(rt_status != TRUE) { + RT_TRACE(COMP_ERR, "CPUcheck_firmware_ready fail(%d)!\n",rt_status); + goto download_firmware_fail; + } + + /* wait until data code is initialized ready.*/ + pfirmware->firmware_status = FW_STATUS_5_READY; + break; + } + } + + RT_TRACE(COMP_FIRMWARE, "Firmware Download Success\n"); + //assert(pfirmware->firmware_status == FW_STATUS_5_READY, ("Firmware Download Fail\n")); + + return rt_status; + +download_firmware_fail: + RT_TRACE(COMP_ERR, "ERR in %s()\n", __FUNCTION__); + rt_status = FALSE; + return rt_status; + +} + +#if 0 +/* + * Procedure: (1) Transform firmware code from little endian to big endian if required. + * (2) Number of bytes in Firmware downloading should be multiple + * of 4 bytes. If length is not multiple of 4 bytes, appending of zeros is required + * + */ +void CmdAppendZeroAndEndianTransform( + u1Byte *pDst, + u1Byte *pSrc, + u2Byte *pLength) +{ + + u2Byte ulAppendBytes = 0, i; + u2Byte ulLength = *pLength; + +//test only + //memset(pDst, 0xcc, 12); + + + /* Transform from little endian to big endian */ +//#if DEV_BUS_TYPE==PCI_INTERFACE +#if 0 + for( i=0 ; i<(*pLength) ; i+=4) + { + if((i+3) < (*pLength)) pDst[i+0] = pSrc[i+3]; + if((i+2) < (*pLength)) pDst[i+1] = pSrc[i+2]; + if((i+1) < (*pLength)) pDst[i+2] = pSrc[i+1]; + if((i+0) < (*pLength)) pDst[i+3] = pSrc[i+0]; + } +#else + pDst += USB_HWDESC_HEADER_LEN; + ulLength -= USB_HWDESC_HEADER_LEN; + + for( i=0 ; i<ulLength ; i+=4) { + if((i+3) < ulLength) pDst[i+0] = pSrc[i+3]; + if((i+2) < ulLength) pDst[i+1] = pSrc[i+2]; + if((i+1) < ulLength) pDst[i+2] = pSrc[i+1]; + if((i+0) < ulLength) pDst[i+3] = pSrc[i+0]; + + } +#endif + + //1(2) Append Zero + if( ((*pLength) % 4) >0) + { + ulAppendBytes = 4-((*pLength) % 4); + + for(i=0 ; i<ulAppendBytes; i++) + pDst[ 4*((*pLength)/4) + i ] = 0x0; + + *pLength += ulAppendBytes; + } +} +#endif + +#if 0 +RT_STATUS +CmdSendPacket( + PADAPTER Adapter, + PRT_TCB pTcb, + PRT_TX_LOCAL_BUFFER pBuf, + u4Byte BufferLen, + u4Byte PacketType, + BOOLEAN bLastInitPacket + ) +{ + s2Byte i; + u1Byte QueueID; + u2Byte firstDesc,curDesc = 0; + u2Byte FragIndex=0, FragBufferIndex=0; + + RT_STATUS rtStatus = RT_STATUS_SUCCESS; + + CmdInitTCB(Adapter, pTcb, pBuf, BufferLen); + + + if(CmdCheckFragment(Adapter, pTcb, pBuf)) + CmdFragmentTCB(Adapter, pTcb); + else + pTcb->FragLength[0] = (u2Byte)pTcb->BufferList[0].Length; + + QueueID=pTcb->SpecifiedQueueID; +#if DEV_BUS_TYPE!=USB_INTERFACE + firstDesc=curDesc=Adapter->NextTxDescToFill[QueueID]; +#endif + +#if DEV_BUS_TYPE!=USB_INTERFACE + if(VacancyTxDescNum(Adapter, QueueID) > pTcb->BufferCount) +#else + if(PlatformIsTxQueueAvailable(Adapter, QueueID, pTcb->BufferCount) && + RTIsListEmpty(&Adapter->TcbWaitQueue[QueueID])) +#endif + { + pTcb->nDescUsed=0; + + for(i=0 ; i<pTcb->BufferCount ; i++) + { + Adapter->HalFunc.TxFillCmdDescHandler( + Adapter, + pTcb, + QueueID, //QueueIndex + curDesc, //index + FragBufferIndex==0, //bFirstSeg + FragBufferIndex==(pTcb->FragBufCount[FragIndex]-1), //bLastSeg + pTcb->BufferList[i].VirtualAddress, //VirtualAddress + pTcb->BufferList[i].PhysicalAddressLow, //PhyAddressLow + pTcb->BufferList[i].Length, //BufferLen + i!=0, //bSetOwnBit + (i==(pTcb->BufferCount-1)) && bLastInitPacket, //bLastInitPacket + PacketType, //DescPacketType + pTcb->FragLength[FragIndex] //PktLen + ); + + if(FragBufferIndex==(pTcb->FragBufCount[FragIndex]-1)) + { // Last segment of the fragment. + pTcb->nFragSent++; + } + + FragBufferIndex++; + if(FragBufferIndex==pTcb->FragBufCount[FragIndex]) + { + FragIndex++; + FragBufferIndex=0; + } + +#if DEV_BUS_TYPE!=USB_INTERFACE + curDesc=(curDesc+1)%Adapter->NumTxDesc[QueueID]; +#endif + pTcb->nDescUsed++; + } + +#if DEV_BUS_TYPE!=USB_INTERFACE + RTInsertTailList(&Adapter->TcbBusyQueue[QueueID], &pTcb->List); + IncrementTxDescToFill(Adapter, QueueID, pTcb->nDescUsed); + Adapter->HalFunc.SetTxDescOWNHandler(Adapter, QueueID, firstDesc); + // TODO: should call poll use QueueID + Adapter->HalFunc.TxPollingHandler(Adapter, TXCMD_QUEUE); +#endif + } + else +#if DEV_BUS_TYPE!=USB_INTERFACE + goto CmdSendPacket_Fail; +#else + { + pTcb->bLastInitPacket = bLastInitPacket; + RTInsertTailList(&Adapter->TcbWaitQueue[pTcb->SpecifiedQueueID], &pTcb->List); + } +#endif + + return rtStatus; + +#if DEV_BUS_TYPE!=USB_INTERFACE +CmdSendPacket_Fail: + rtStatus = RT_STATUS_FAILURE; + return rtStatus; +#endif + +} +#endif + + + + +#if 0 +RT_STATUS +FWSendNullPacket( + IN PADAPTER Adapter, + IN u4Byte Length +) +{ + RT_STATUS rtStatus = RT_STATUS_SUCCESS; + + + PRT_TCB pTcb; + PRT_TX_LOCAL_BUFFER pBuf; + BOOLEAN bLastInitPacket = FALSE; + + PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK); + +#if DEV_BUS_TYPE==USB_INTERFACE + Length += USB_HWDESC_HEADER_LEN; +#endif + + //Get TCB and local buffer from common pool. (It is shared by CmdQ, MgntQ, and USB coalesce DataQ) + if(MgntGetBuffer(Adapter, &pTcb, &pBuf)) + { + PlatformZeroMemory(pBuf->Buffer.VirtualAddress, Length); + rtStatus = CmdSendPacket(Adapter, pTcb, pBuf, Length, DESC_PACKET_TYPE_INIT, bLastInitPacket); //0 : always set LastInitPacket to zero +//#if HAL_CODE_BASE != RTL8190HW +// // TODO: for test only +// ReturnTCB(Adapter, pTcb, RT_STATUS_SUCCESS); +//#endif + if(rtStatus == RT_STATUS_FAILURE) + goto CmdSendNullPacket_Fail; + }else + goto CmdSendNullPacket_Fail; + + PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK); + return rtStatus; + + +CmdSendNullPacket_Fail: + PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK); + rtStatus = RT_STATUS_FAILURE; + RT_ASSERT(rtStatus == RT_STATUS_SUCCESS, ("CmdSendDownloadCode fail !!\n")); + return rtStatus; +} +#endif + + diff --git a/drivers/staging/rtl8192su/r819xU_firmware.h b/drivers/staging/rtl8192su/r819xU_firmware.h new file mode 100644 index 000000000000..10801be014e0 --- /dev/null +++ b/drivers/staging/rtl8192su/r819xU_firmware.h @@ -0,0 +1,106 @@ +#ifndef __INC_FIRMWARE_H +#define __INC_FIRMWARE_H + +#define RTL8190_CPU_START_OFFSET 0x80 +/* TODO: this definition is TBD */ +//#define USB_HWDESC_HEADER_LEN 0 + +/* It should be double word alignment */ +//#if DEV_BUS_TYPE==PCI_INTERFACE +//#define GET_COMMAND_PACKET_FRAG_THRESHOLD(v) 4*(v/4) - 8 +//#else +#define GET_COMMAND_PACKET_FRAG_THRESHOLD(v) (4*(v/4) - 8 - USB_HWDESC_HEADER_LEN) +//#endif + +typedef enum _firmware_init_step{ + FW_INIT_STEP0_BOOT = 0, + FW_INIT_STEP1_MAIN = 1, + FW_INIT_STEP2_DATA = 2, +}firmware_init_step_e; + +typedef enum _opt_rst_type{ + OPT_SYSTEM_RESET = 0, + OPT_FIRMWARE_RESET = 1, +}opt_rst_type_e; + +/* due to rtl8192 firmware */ +typedef enum _desc_packet_type_e{ + DESC_PACKET_TYPE_INIT = 0, + DESC_PACKET_TYPE_NORMAL = 1, +}desc_packet_type_e; + +typedef enum _firmware_source{ + FW_SOURCE_IMG_FILE = 0, + FW_SOURCE_HEADER_FILE = 1, //from header file +}firmware_source_e, *pfirmware_source_e; + +typedef enum _firmware_status{ + FW_STATUS_0_INIT = 0, + FW_STATUS_1_MOVE_BOOT_CODE = 1, + FW_STATUS_2_MOVE_MAIN_CODE = 2, + FW_STATUS_3_TURNON_CPU = 3, + FW_STATUS_4_MOVE_DATA_CODE = 4, + FW_STATUS_5_READY = 5, +}firmware_status_e; + +typedef struct _rt_firmare_seg_container { + u16 seg_size; + u8 *seg_ptr; +}fw_seg_container, *pfw_seg_container; + +#define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000 //64k +#define MAX_FW_INIT_STEP 3 +typedef struct _rt_firmware{ + firmware_status_e firmware_status; + u16 cmdpacket_frag_thresold; + u8 firmware_buf[MAX_FW_INIT_STEP][RTL8190_MAX_FIRMWARE_CODE_SIZE]; + u16 firmware_buf_size[MAX_FW_INIT_STEP]; +}rt_firmware, *prt_firmware; + +typedef struct _rt_firmware_info_819xUsb{ + u8 sz_info[16]; +}rt_firmware_info_819xUsb, *prt_firmware_info_819xUsb; + +#if 0 +/* CPU related */ +RT_STATUS +CPUCheckMainCodeOKAndTurnOnCPU( + IN PADAPTER Adapter + ); + +RT_STATUS +CPUCheckFirmwareReady( + IN PADAPTER Adapter + ); + +/* Firmware related */ +VOID +FWInitializeParameters( + IN PADAPTER Adapter + ); + +RT_STATUS +FWSendDownloadCode( + IN PADAPTER Adapter, + IN pu1Byte CodeVirtualAddrress, + IN u4Byte BufferLen + ); + +RT_STATUS +FWSendNullPacket( + IN PADAPTER Adapter, + IN u4Byte Length + ); + +RT_STATUS +CmdSendPacket( + PADAPTER Adapter, + PRT_TCB pTcb, + PRT_TX_LOCAL_BUFFER pBuf, + u4Byte BufferLen, + u4Byte PacketType, + BOOLEAN bLastInitPacket + ); +#endif +#endif + diff --git a/drivers/staging/rtl8192su/r819xU_firmware_img.c b/drivers/staging/rtl8192su/r819xU_firmware_img.c new file mode 100644 index 000000000000..29b656d7d82b --- /dev/null +++ b/drivers/staging/rtl8192su/r819xU_firmware_img.c @@ -0,0 +1,3447 @@ +/*Created on 2008/ 7/16, 5:31*/ +#include <linux/types.h> + +u8 rtl8190_fwboot_array[] = { +0x10,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x3c,0x08,0xbf,0xc0,0x25,0x08,0x00,0x08, +0x3c,0x09,0xb0,0x03,0xad,0x28,0x00,0x20,0x40,0x80,0x68,0x00,0x00,0x00,0x00,0x00, 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+0xa0,0xc3,0x00,0x00,0x90,0xc4,0x00,0x00,0x27,0xbd,0xff,0xf8,0x3c,0x03,0xb0,0x07, +0x24,0x02,0xff,0x82,0xa3,0xa4,0x00,0x00,0xa0,0x62,0x00,0x00,0x90,0x64,0x00,0x00, +0x3c,0x02,0xb0,0x07,0x34,0x42,0x00,0x08,0xa3,0xa4,0x00,0x01,0xa0,0x40,0x00,0x00, +0x90,0x43,0x00,0x00,0x24,0x02,0x00,0x03,0x3c,0x05,0xb0,0x07,0xa3,0xa3,0x00,0x00, +0xa0,0xc2,0x00,0x00,0x90,0xc4,0x00,0x00,0x34,0xa5,0x00,0x10,0x24,0x02,0x00,0x06, +0x3c,0x03,0xb0,0x07,0xa3,0xa4,0x00,0x00,0x34,0x63,0x00,0x38,0xa0,0xa2,0x00,0x00, +0x90,0x64,0x00,0x00,0x3c,0x02,0xb0,0x07,0x34,0x42,0x00,0x20,0xa3,0xa4,0x00,0x00, +0xa0,0xa0,0x00,0x00,0x90,0xa3,0x00,0x00,0xaf,0x82,0xbf,0x20,0xa3,0xa3,0x00,0x00, +0xa0,0x40,0x00,0x00,0x90,0x43,0x00,0x00,0x03,0xe0,0x00,0x08,0x27,0xbd,0x00,0x08, +}; + +u8 rtl8190_fwdata_array[] ={ +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x10,0x00,0x08,0x00, +0x02,0xe9,0x01,0x74,0x02,0xab,0x01,0xc7,0x01,0x55,0x00,0xe4,0x00,0xab,0x00,0x72, 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+0x61,0x00,0x54,0x4c,0x42,0x53,0x00,0x00,0x00,0x00,0x00,0x00,0x41,0x64,0x45,0x4c, +0x5f,0x64,0x61,0x74,0x61,0x00,0x41,0x64,0x45,0x53,0x00,0x00,0x00,0x00,0x00,0x00, +0x45,0x78,0x63,0x43,0x6f,0x64,0x65,0x36,0x00,0x00,0x45,0x78,0x63,0x43,0x6f,0x64, +0x65,0x37,0x00,0x00,0x53,0x79,0x73,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x42,0x70, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x52,0x49,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x43,0x70,0x55,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x4f,0x76,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x01,0x0b,0x53, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x10,0x00,0x00,0x00,0x2c, +0x00,0x00,0x00,0x58,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x48,0x00,0x00,0x00,0x60, +0x00,0x00,0x00,0x90,0x00,0x00,0x00,0xc0,0x00,0x00,0x01,0x20,0x00,0x00,0x01,0x80, +0x00,0x00,0x01,0xb0,0x00,0x00,0x00,0x34,0x00,0x00,0x00,0x68,0x00,0x00,0x00,0x9c, +0x00,0x00,0x00,0xd0,0x00,0x00,0x01,0x38,0x00,0x00,0x01,0xa0,0x00,0x00,0x01,0xd4, +0x00,0x00,0x02,0x08,0x00,0x00,0x00,0x68,0x00,0x00,0x00,0xd0,0x00,0x00,0x01,0x38, +0x00,0x00,0x01,0xa0,0x00,0x00,0x02,0x6f,0x00,0x00,0x03,0x40,0x00,0x00,0x03,0xa8, +0x00,0x00,0x04,0x10,0x01,0x01,0x01,0x02,0x01,0x01,0x02,0x02,0x03,0x03,0x04,0x04, +0x01,0x01,0x02,0x02,0x03,0x03,0x04,0x04,0x02,0x03,0x03,0x04,0x05,0x06,0x07,0x08, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x07,0x74,0x80,0x00,0x07,0x88, +0x80,0x00,0x07,0x88,0x80,0x00,0x07,0x78,0x80,0x00,0x07,0x78,0x80,0x00,0x07,0x9c, +0x80,0x00,0x53,0xc4,0x80,0x00,0x54,0x24,0x80,0x00,0x54,0x38,0x80,0x00,0x54,0x5c, +0x80,0x00,0x54,0x68,0x80,0x00,0x54,0xa8,0x80,0x00,0x56,0xa8,0x80,0x00,0x57,0xec, +0x80,0x00,0x58,0x14,0x80,0x00,0x59,0x0c,0x80,0x00,0x59,0xc4,0x80,0x00,0x5a,0x6c, +0x80,0x00,0x5a,0xe0,0x80,0x00,0x5b,0xec,0x80,0x00,0x5c,0x24,0x80,0x00,0x5c,0x38, +0x80,0x00,0x5c,0x4c,0x80,0x00,0x5d,0x40,0x80,0x00,0x5d,0x80,0x80,0x00,0x5e,0x34, +0x80,0x00,0x5e,0x5c,0x80,0x00,0x56,0x68,0x80,0x00,0x5e,0x78,0x80,0x00,0x88,0xf8, +0x80,0x00,0x88,0xf8,0x80,0x00,0x88,0xf8,0x80,0x00,0x89,0x2c,0x80,0x00,0x89,0x6c, +0x80,0x00,0x89,0xa4,0x80,0x00,0x89,0xd4,0x80,0x00,0x8a,0x10,0x80,0x00,0x8a,0x50, +0x80,0x00,0x8a,0xb8,0x80,0x00,0x8a,0xcc,0x80,0x00,0x8b,0x08,0x80,0x00,0x8b,0x10, +0x80,0x00,0x8b,0x4c,0x80,0x00,0x8b,0x60,0x80,0x00,0x8b,0x68,0x80,0x00,0x8b,0x70, +0x80,0x00,0x8b,0x70,0x80,0x00,0x8b,0x70,0x80,0x00,0x8b,0x70,0x80,0x00,0x8a,0x90, +0x80,0x00,0x8b,0xa0,0x80,0x00,0x8b,0xb4,0x80,0x00,0x88,0x54,0x80,0x00,0x8e,0xc8, +0x80,0x00,0x8e,0xc8,0x80,0x00,0x8e,0xc8,0x80,0x00,0x8e,0xfc,0x80,0x00,0x8f,0x3c, +0x80,0x00,0x8f,0x74,0x80,0x00,0x8f,0xa4,0x80,0x00,0x8f,0xe0,0x80,0x00,0x90,0x20, +0x80,0x00,0x90,0x88,0x80,0x00,0x90,0x9c,0x80,0x00,0x90,0xd8,0x80,0x00,0x90,0xe0, +0x80,0x00,0x91,0x1c,0x80,0x00,0x91,0x30,0x80,0x00,0x91,0x38,0x80,0x00,0x91,0x40, +0x80,0x00,0x91,0x40,0x80,0x00,0x91,0x40,0x80,0x00,0x91,0x40,0x80,0x00,0x90,0x60, +0x80,0x00,0x91,0x70,0x80,0x00,0x91,0x84,0x80,0x00,0x8d,0x00,}; + +u32 Rtl8192UsbPHY_REGArray[] = { +0x0, }; + +u32 Rtl8192UsbPHY_REG_1T2RArray[] = { +0x800,0x00000000, +0x804,0x00000001, +0x808,0x0000fc00, +0x80c,0x0000001c, +0x810,0x801010aa, +0x814,0x008514d0, +0x818,0x00000040, +0x81c,0x00000000, +0x820,0x00000004, +0x824,0x00690000, +0x828,0x00000004, +0x82c,0x00e90000, +0x830,0x00000004, +0x834,0x00690000, +0x838,0x00000004, +0x83c,0x00e90000, +0x840,0x00000000, +0x844,0x00000000, +0x848,0x00000000, +0x84c,0x00000000, +0x850,0x00000000, +0x854,0x00000000, +0x858,0x65a965a9, +0x85c,0x65a965a9, +0x860,0x001f0010, +0x864,0x007f0010, +0x868,0x001f0010, +0x86c,0x007f0010, +0x870,0x0f100f70, +0x874,0x0f100f70, +0x878,0x00000000, +0x87c,0x00000000, +0x880,0x6870e36c, +0x884,0xe3573600, +0x888,0x4260c340, +0x88c,0x0000ff00, +0x890,0x00000000, +0x894,0xfffffffe, +0x898,0x4c42382f, +0x89c,0x00656056, +0x8b0,0x00000000, +0x8e0,0x00000000, +0x8e4,0x00000000, +0x900,0x00000000, +0x904,0x00000023, +0x908,0x00000000, +0x90c,0x31121311, +0xa00,0x00d0c7d8, +0xa04,0x811f0008, +0xa08,0x80cd8300, +0xa0c,0x2e62740f, +0xa10,0x95009b78, +0xa14,0x11145008, +0xa18,0x00881117, +0xa1c,0x89140fa0, +0xa20,0x1a1b0000, +0xa24,0x090e1317, +0xa28,0x00000204, +0xa2c,0x00000000, +0xc00,0x00000040, +0xc04,0x00005433, +0xc08,0x000000e4, +0xc0c,0x6c6c6c6c, +0xc10,0x08800000, +0xc14,0x40000100, +0xc18,0x08000000, +0xc1c,0x40000100, +0xc20,0x08000000, +0xc24,0x40000100, +0xc28,0x08000000, +0xc2c,0x40000100, +0xc30,0x6de9ac44, +0xc34,0x465c52cd, +0xc38,0x497f5994, +0xc3c,0x0a969764, +0xc40,0x1f7c403f, +0xc44,0x000100b7, +0xc48,0xec020000, +0xc4c,0x00000300, +0xc50,0x69543420, +0xc54,0x433c0094, +0xc58,0x69543420, +0xc5c,0x433c0094, +0xc60,0x69543420, +0xc64,0x433c0094, +0xc68,0x69543420, +0xc6c,0x433c0094, +0xc70,0x2c7f000d, +0xc74,0x0186175b, +0xc78,0x0000001f, +0xc7c,0x00b91612, +0xc80,0x40000100, +0xc84,0x20000000, +0xc88,0x40000100, +0xc8c,0x20200000, +0xc90,0x40000100, +0xc94,0x00000000, +0xc98,0x40000100, +0xc9c,0x00000000, +0xca0,0x00492492, +0xca4,0x00000000, +0xca8,0x00000000, +0xcac,0x00000000, +0xcb0,0x00000000, +0xcb4,0x00000000, +0xcb8,0x00000000, +0xcbc,0x00492492, +0xcc0,0x00000000, +0xcc4,0x00000000, +0xcc8,0x00000000, +0xccc,0x00000000, +0xcd0,0x00000000, +0xcd4,0x00000000, +0xcd8,0x64b22427, +0xcdc,0x00766932, +0xce0,0x00222222, +0xd00,0x00000750, +0xd04,0x00000403, +0xd08,0x0000907f, +0xd0c,0x00000001, +0xd10,0xa0633333, +0xd14,0x33333c63, +0xd18,0x6a8f5b6b, +0xd1c,0x00000000, +0xd20,0x00000000, +0xd24,0x00000000, +0xd28,0x00000000, +0xd2c,0xcc979975, +0xd30,0x00000000, +0xd34,0x00000000, +0xd38,0x00000000, +0xd3c,0x00027293, +0xd40,0x00000000, +0xd44,0x00000000, +0xd48,0x00000000, +0xd4c,0x00000000, +0xd50,0x6437140a, +0xd54,0x024dbd02, +0xd58,0x00000000, +0xd5c,0x04032064, +0xe00,0x161a1a1a, +0xe04,0x12121416, +0xe08,0x00001800, +0xe0c,0x00000000, +0xe10,0x161a1a1a, +0xe14,0x12121416, +0xe18,0x161a1a1a, +0xe1c,0x12121416, +}; + +u32 Rtl8192UsbRadioA_Array[] = { +0x019,0x00000003, +0x000,0x000000bf, +0x001,0x00000ee0, +0x002,0x0000004c, +0x003,0x000007f1, +0x004,0x00000975, +0x005,0x00000c58, +0x006,0x00000ae6, +0x007,0x000000ca, +0x008,0x00000e1c, +0x009,0x000007f0, +0x00a,0x000009d0, +0x00b,0x000001ba, +0x00c,0x00000240, +0x00e,0x00000020, +0x00f,0x00000990, +0x012,0x00000806, +0x014,0x000005ab, +0x015,0x00000f80, +0x016,0x00000020, +0x017,0x00000597, +0x018,0x0000050a, +0x01a,0x00000f80, +0x01b,0x00000f5e, +0x01c,0x00000008, +0x01d,0x00000607, +0x01e,0x000006cc, +0x01f,0x00000000, +0x020,0x000001a5, +0x01f,0x00000001, +0x020,0x00000165, +0x01f,0x00000002, +0x020,0x000000c6, +0x01f,0x00000003, +0x020,0x00000086, +0x01f,0x00000004, +0x020,0x00000046, +0x01f,0x00000005, +0x020,0x000001e6, +0x01f,0x00000006, +0x020,0x000001a6, +0x01f,0x00000007, +0x020,0x00000166, +0x01f,0x00000008, +0x020,0x000000c7, +0x01f,0x00000009, +0x020,0x00000087, +0x01f,0x0000000a, +0x020,0x000000f7, +0x01f,0x0000000b, +0x020,0x000000d7, +0x01f,0x0000000c, +0x020,0x000000b7, +0x01f,0x0000000d, +0x020,0x00000097, +0x01f,0x0000000e, +0x020,0x00000077, +0x01f,0x0000000f, +0x020,0x00000057, +0x01f,0x00000010, +0x020,0x00000037, +0x01f,0x00000011, +0x020,0x000000fb, +0x01f,0x00000012, +0x020,0x000000db, +0x01f,0x00000013, +0x020,0x000000bb, +0x01f,0x00000014, +0x020,0x000000ff, +0x01f,0x00000015, +0x020,0x000000e3, +0x01f,0x00000016, +0x020,0x000000c3, +0x01f,0x00000017, +0x020,0x000000a3, +0x01f,0x00000018, +0x020,0x00000083, +0x01f,0x00000019, +0x020,0x00000063, +0x01f,0x0000001a, +0x020,0x00000043, +0x01f,0x0000001b, +0x020,0x00000023, +0x01f,0x0000001c, +0x020,0x00000003, +0x01f,0x0000001d, +0x020,0x000001e3, +0x01f,0x0000001e, +0x020,0x000001c3, +0x01f,0x0000001f, +0x020,0x000001a3, +0x01f,0x00000020, +0x020,0x00000183, +0x01f,0x00000021, +0x020,0x00000163, +0x01f,0x00000022, +0x020,0x00000143, +0x01f,0x00000023, +0x020,0x00000123, +0x01f,0x00000024, +0x020,0x00000103, +0x023,0x00000203, +0x024,0x00000200, +0x00b,0x000001ba, +0x02c,0x000003d7, +0x02d,0x00000ff0, +0x000,0x00000037, +0x004,0x00000160, +0x007,0x00000080, +0x002,0x0000088d, +0x0fe,0x00000000, +0x0fe,0x00000000, +0x016,0x00000200, +0x016,0x00000380, +0x016,0x00000020, +0x016,0x000001a0, +0x000,0x000000bf, +0x00d,0x0000001f, +0x00d,0x00000c9f, +0x002,0x0000004d, +0x000,0x00000cbf, +0x004,0x00000975, +0x007,0x00000700, +}; + +u32 Rtl8192UsbRadioB_Array[] = { +0x019,0x00000003, +0x000,0x000000bf, +0x001,0x000006e0, +0x002,0x0000004c, +0x003,0x000007f1, +0x004,0x00000975, +0x005,0x00000c58, +0x006,0x00000ae6, +0x007,0x000000ca, +0x008,0x00000e1c, +0x000,0x000000b7, +0x00a,0x00000850, +0x000,0x000000bf, +0x00b,0x000001ba, +0x00c,0x00000240, +0x00e,0x00000020, +0x015,0x00000f80, +0x016,0x00000020, +0x017,0x00000597, +0x018,0x0000050a, +0x01a,0x00000e00, +0x01b,0x00000f5e, +0x01d,0x00000607, +0x01e,0x000006cc, +0x00b,0x000001ba, +0x023,0x00000203, +0x024,0x00000200, +0x000,0x00000037, +0x004,0x00000160, +0x016,0x00000200, +0x016,0x00000380, +0x016,0x00000020, +0x016,0x000001a0, +0x00d,0x00000ccc, +0x000,0x000000bf, +0x002,0x0000004d, +0x000,0x00000cbf, +0x004,0x00000975, +0x007,0x00000700, +}; + +u32 Rtl8192UsbRadioC_Array[] = { +0x0, }; + +u32 Rtl8192UsbRadioD_Array[] = { +0x0, }; + +u32 Rtl8192UsbMACPHY_Array[] = { +0x03c,0xffff0000,0x00000f0f, +0x340,0xffffffff,0x161a1a1a, +0x344,0xffffffff,0x12121416, +0x348,0x0000ffff,0x00001818, +0x12c,0xffffffff,0x04000802, +0x318,0x00000fff,0x00000100, +}; + +u32 Rtl8192UsbMACPHY_Array_PG[] = { +0x03c,0xffff0000,0x00000f0f, +0xe00,0xffffffff,0x06090909, +0xe04,0xffffffff,0x00030306, +0xe08,0x0000ff00,0x00000000, +0xe10,0xffffffff,0x0a0c0d0f, +0xe14,0xffffffff,0x06070809, +0xe18,0xffffffff,0x0a0c0d0f, +0xe1c,0xffffffff,0x06070809, +0x12c,0xffffffff,0x04000802, +0x318,0x00000fff,0x00000800, +}; + +u32 Rtl8192UsbAGCTAB_Array[] = { +0xc78,0x7d000001, +0xc78,0x7d010001, +0xc78,0x7d020001, +0xc78,0x7d030001, +0xc78,0x7d040001, +0xc78,0x7d050001, +0xc78,0x7c060001, +0xc78,0x7b070001, +0xc78,0x7a080001, +0xc78,0x79090001, +0xc78,0x780a0001, +0xc78,0x770b0001, +0xc78,0x760c0001, +0xc78,0x750d0001, +0xc78,0x740e0001, +0xc78,0x730f0001, +0xc78,0x72100001, +0xc78,0x71110001, +0xc78,0x70120001, +0xc78,0x6f130001, +0xc78,0x6e140001, +0xc78,0x6d150001, +0xc78,0x6c160001, +0xc78,0x6b170001, +0xc78,0x6a180001, +0xc78,0x69190001, +0xc78,0x681a0001, +0xc78,0x671b0001, +0xc78,0x661c0001, +0xc78,0x651d0001, +0xc78,0x641e0001, +0xc78,0x491f0001, +0xc78,0x48200001, +0xc78,0x47210001, +0xc78,0x46220001, +0xc78,0x45230001, +0xc78,0x44240001, +0xc78,0x43250001, +0xc78,0x28260001, +0xc78,0x27270001, +0xc78,0x26280001, +0xc78,0x25290001, +0xc78,0x242a0001, +0xc78,0x232b0001, +0xc78,0x222c0001, +0xc78,0x212d0001, +0xc78,0x202e0001, +0xc78,0x0a2f0001, +0xc78,0x08300001, +0xc78,0x06310001, +0xc78,0x05320001, +0xc78,0x04330001, +0xc78,0x03340001, +0xc78,0x02350001, +0xc78,0x01360001, +0xc78,0x00370001, +0xc78,0x00380001, +0xc78,0x00390001, +0xc78,0x003a0001, +0xc78,0x003b0001, +0xc78,0x003c0001, +0xc78,0x003d0001, +0xc78,0x003e0001, +0xc78,0x003f0001, +0xc78,0x7d400001, +0xc78,0x7d410001, +0xc78,0x7d420001, +0xc78,0x7d430001, +0xc78,0x7d440001, +0xc78,0x7d450001, +0xc78,0x7c460001, +0xc78,0x7b470001, +0xc78,0x7a480001, +0xc78,0x79490001, +0xc78,0x784a0001, +0xc78,0x774b0001, +0xc78,0x764c0001, +0xc78,0x754d0001, +0xc78,0x744e0001, +0xc78,0x734f0001, +0xc78,0x72500001, +0xc78,0x71510001, +0xc78,0x70520001, +0xc78,0x6f530001, +0xc78,0x6e540001, +0xc78,0x6d550001, +0xc78,0x6c560001, +0xc78,0x6b570001, +0xc78,0x6a580001, +0xc78,0x69590001, +0xc78,0x685a0001, +0xc78,0x675b0001, +0xc78,0x665c0001, +0xc78,0x655d0001, +0xc78,0x645e0001, +0xc78,0x495f0001, +0xc78,0x48600001, +0xc78,0x47610001, +0xc78,0x46620001, +0xc78,0x45630001, +0xc78,0x44640001, +0xc78,0x43650001, +0xc78,0x28660001, +0xc78,0x27670001, +0xc78,0x26680001, +0xc78,0x25690001, +0xc78,0x246a0001, +0xc78,0x236b0001, +0xc78,0x226c0001, +0xc78,0x216d0001, +0xc78,0x206e0001, +0xc78,0x0a6f0001, +0xc78,0x08700001, +0xc78,0x06710001, +0xc78,0x05720001, +0xc78,0x04730001, +0xc78,0x03740001, +0xc78,0x02750001, +0xc78,0x01760001, +0xc78,0x00770001, +0xc78,0x00780001, +0xc78,0x00790001, +0xc78,0x007a0001, +0xc78,0x007b0001, +0xc78,0x007c0001, +0xc78,0x007d0001, +0xc78,0x007e0001, +0xc78,0x007f0001, +0xc78,0x2e00001e, +0xc78,0x2e01001e, +0xc78,0x2e02001e, +0xc78,0x2e03001e, +0xc78,0x2e04001e, +0xc78,0x2e05001e, +0xc78,0x3006001e, +0xc78,0x3407001e, +0xc78,0x3908001e, +0xc78,0x3c09001e, +0xc78,0x3f0a001e, +0xc78,0x420b001e, +0xc78,0x440c001e, +0xc78,0x450d001e, +0xc78,0x460e001e, +0xc78,0x460f001e, +0xc78,0x4710001e, +0xc78,0x4811001e, +0xc78,0x4912001e, +0xc78,0x4a13001e, +0xc78,0x4b14001e, +0xc78,0x4b15001e, +0xc78,0x4c16001e, +0xc78,0x4d17001e, +0xc78,0x4e18001e, +0xc78,0x4f19001e, +0xc78,0x4f1a001e, +0xc78,0x501b001e, +0xc78,0x511c001e, +0xc78,0x521d001e, +0xc78,0x521e001e, +0xc78,0x531f001e, +0xc78,0x5320001e, +0xc78,0x5421001e, +0xc78,0x5522001e, +0xc78,0x5523001e, +0xc78,0x5624001e, +0xc78,0x5725001e, +0xc78,0x5726001e, +0xc78,0x5827001e, +0xc78,0x5828001e, +0xc78,0x5929001e, +0xc78,0x592a001e, +0xc78,0x5a2b001e, +0xc78,0x5b2c001e, +0xc78,0x5c2d001e, +0xc78,0x5c2e001e, +0xc78,0x5d2f001e, +0xc78,0x5e30001e, +0xc78,0x5f31001e, +0xc78,0x6032001e, +0xc78,0x6033001e, +0xc78,0x6134001e, +0xc78,0x6235001e, +0xc78,0x6336001e, +0xc78,0x6437001e, +0xc78,0x6438001e, +0xc78,0x6539001e, +0xc78,0x663a001e, +0xc78,0x673b001e, +0xc78,0x673c001e, +0xc78,0x683d001e, +0xc78,0x693e001e, +0xc78,0x6a3f001e, +}; diff --git a/drivers/staging/rtl8192su/r819xU_firmware_img.h b/drivers/staging/rtl8192su/r819xU_firmware_img.h new file mode 100644 index 000000000000..d9d9515a1e61 --- /dev/null +++ b/drivers/staging/rtl8192su/r819xU_firmware_img.h @@ -0,0 +1,35 @@ +#ifndef IMG_H +#define IMG_H + +#define BOOT_ARR_LEN 344 +#define MAIN_ARR_LEN 45136 +#define DATA_ARR_LEN 796 +#define MACPHY_Array_PGLength 30 +#define PHY_REG_1T2RArrayLength 296 +#define AGCTAB_ArrayLength 384 +#define MACPHY_ArrayLength 18 + +#define RadioA_ArrayLength 246 +#define RadioB_ArrayLength 78 +#define RadioC_ArrayLength 1 +#define RadioD_ArrayLength 1 +#define PHY_REGArrayLength 1 + + +extern u8 rtl8190_fwboot_array[BOOT_ARR_LEN]; +extern u8 rtl8190_fwmain_array[MAIN_ARR_LEN]; +extern u8 rtl8190_fwdata_array[DATA_ARR_LEN]; + +extern u32 Rtl8192UsbPHY_REGArray[]; +extern u32 Rtl8192UsbPHY_REG_1T2RArray[]; +extern u32 Rtl8192UsbRadioA_Array[]; +extern u32 Rtl8192UsbRadioB_Array[]; +extern u32 Rtl8192UsbRadioC_Array[]; +extern u32 Rtl8192UsbRadioD_Array[]; +extern u32 Rtl8192UsbMACPHY_Array[]; +extern u32 Rtl8192UsbMACPHY_Array_PG[]; +extern u32 Rtl8192UsbAGCTAB_Array[]; + + + +#endif diff --git a/drivers/staging/rtl8192su/r819xU_phy.c b/drivers/staging/rtl8192su/r819xU_phy.c new file mode 100644 index 000000000000..00497d313f9b --- /dev/null +++ b/drivers/staging/rtl8192su/r819xU_phy.c @@ -0,0 +1,1826 @@ +#include "r8192U.h" +#include "r8192U_hw.h" +#include "r819xU_phy.h" +#include "r819xU_phyreg.h" +#include "r8190_rtl8256.h" +#include "r8192U_dm.h" +#include "r819xU_firmware_img.h" + +#ifdef ENABLE_DOT11D +#include "dot11d.h" +#endif +static u32 RF_CHANNEL_TABLE_ZEBRA[] = { + 0, + 0x085c, //2412 1 + 0x08dc, //2417 2 + 0x095c, //2422 3 + 0x09dc, //2427 4 + 0x0a5c, //2432 5 + 0x0adc, //2437 6 + 0x0b5c, //2442 7 + 0x0bdc, //2447 8 + 0x0c5c, //2452 9 + 0x0cdc, //2457 10 + 0x0d5c, //2462 11 + 0x0ddc, //2467 12 + 0x0e5c, //2472 13 + 0x0f72, //2484 +}; + + +#define rtl819XPHY_REG_1T2RArray Rtl8192UsbPHY_REG_1T2RArray +#define rtl819XMACPHY_Array_PG Rtl8192UsbMACPHY_Array_PG +#define rtl819XMACPHY_Array Rtl8192UsbMACPHY_Array +#define rtl819XRadioA_Array Rtl8192UsbRadioA_Array +#define rtl819XRadioB_Array Rtl8192UsbRadioB_Array +#define rtl819XRadioC_Array Rtl8192UsbRadioC_Array +#define rtl819XRadioD_Array Rtl8192UsbRadioD_Array +#define rtl819XAGCTAB_Array Rtl8192UsbAGCTAB_Array + +/****************************************************************************** + *function: This function read BB parameters from Header file we gen, + * and do register read/write + * input: u32 dwBitMask //taget bit pos in the addr to be modified + * output: none + * return: u32 return the shift bit bit position of the mask + * ****************************************************************************/ +u32 rtl8192_CalculateBitShift(u32 dwBitMask) +{ + u32 i; + for (i=0; i<=31; i++) + { + if (((dwBitMask>>i)&0x1) == 1) + break; + } + return i; +} +/****************************************************************************** + *function: This function check different RF type to execute legal judgement. If RF Path is illegal, we will return false. + * input: none + * output: none + * return: 0(illegal, false), 1(legal,true) + * ***************************************************************************/ +u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath) +{ + u8 ret = 1; + struct r8192_priv *priv = ieee80211_priv(dev); + if (priv->rf_type == RF_2T4R) + ret = 0; + else if (priv->rf_type == RF_1T2R) + { + if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B) + ret = 1; + else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D) + ret = 0; + } + return ret; +} +/****************************************************************************** + *function: This function set specific bits to BB register + * input: net_device dev + * u32 dwRegAddr //target addr to be modified + * u32 dwBitMask //taget bit pos in the addr to be modified + * u32 dwData //value to be write + * output: none + * return: none + * notice: + * ****************************************************************************/ +void rtl8192_setBBreg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask, u32 dwData) +{ + + u32 OriginalValue, BitShift, NewValue; + + if(dwBitMask!= bMaskDWord) + {//if not "double word" write + OriginalValue = read_nic_dword(dev, dwRegAddr); + BitShift = rtl8192_CalculateBitShift(dwBitMask); + NewValue = (((OriginalValue) & (~dwBitMask)) | (dwData << BitShift)); + write_nic_dword(dev, dwRegAddr, NewValue); + }else + write_nic_dword(dev, dwRegAddr, dwData); + return; +} +/****************************************************************************** + *function: This function reads specific bits from BB register + * input: net_device dev + * u32 dwRegAddr //target addr to be readback + * u32 dwBitMask //taget bit pos in the addr to be readback + * output: none + * return: u32 Data //the readback register value + * notice: + * ****************************************************************************/ +u32 rtl8192_QueryBBReg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask) +{ + u32 Ret = 0, OriginalValue, BitShift; + + OriginalValue = read_nic_dword(dev, dwRegAddr); + BitShift = rtl8192_CalculateBitShift(dwBitMask); + Ret =(OriginalValue & dwBitMask) >> BitShift; + + return (Ret); +} +static u32 phy_FwRFSerialRead( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset ); + +static void phy_FwRFSerialWrite( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data); + +/****************************************************************************** + *function: This function read register from RF chip + * input: net_device dev + * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D + * u32 Offset //target address to be read + * output: none + * return: u32 readback value + * notice: There are three types of serial operations:(1) Software serial write.(2)Hardware LSSI-Low Speed Serial Interface.(3)Hardware HSSI-High speed serial write. Driver here need to implement (1) and (2)---need more spec for this information. + * ****************************************************************************/ +u32 rtl8192_phy_RFSerialRead(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + u32 ret = 0; + u32 NewOffset = 0; + BB_REGISTER_DEFINITION_T* pPhyReg = &priv->PHYRegDef[eRFPath]; + rtl8192_setBBreg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData, 0); + //make sure RF register offset is correct + Offset &= 0x3f; + + //switch page for 8256 RF IC + if (priv->rf_chip == RF_8256) + { + if (Offset >= 31) + { + priv->RfReg0Value[eRFPath] |= 0x140; + //Switch to Reg_Mode2 for Reg 31-45 + rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) ); + //modify offset + NewOffset = Offset -30; + } + else if (Offset >= 16) + { + priv->RfReg0Value[eRFPath] |= 0x100; + priv->RfReg0Value[eRFPath] &= (~0x40); + //Switch to Reg_Mode 1 for Reg16-30 + rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) ); + + NewOffset = Offset - 15; + } + else + NewOffset = Offset; + } + else + { + RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n"); + NewOffset = Offset; + } + //put desired read addr to LSSI control Register + rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, NewOffset); + //Issue a posedge trigger + // + rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0); + rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1); + + + // TODO: we should not delay such a long time. Ask help from SD3 + msleep(1); + + ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData); + + + // Switch back to Reg_Mode0; + if(priv->rf_chip == RF_8256) + { + priv->RfReg0Value[eRFPath] &= 0xebf; + + rtl8192_setBBreg( + dev, + pPhyReg->rf3wireOffset, + bMaskDWord, + (priv->RfReg0Value[eRFPath] << 16)); + } + + return ret; + +} + +/****************************************************************************** + *function: This function write data to RF register + * input: net_device dev + * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D + * u32 Offset //target address to be written + * u32 Data //The new register data to be written + * output: none + * return: none + * notice: For RF8256 only. + =========================================================== + *Reg Mode RegCTL[1] RegCTL[0] Note + * (Reg00[12]) (Reg00[10]) + *=========================================================== + *Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf) + *------------------------------------------------------------------ + *Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf) + *------------------------------------------------------------------ + * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf) + *------------------------------------------------------------------ + * ****************************************************************************/ +void rtl8192_phy_RFSerialWrite(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + u32 DataAndAddr = 0, NewOffset = 0; + BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath]; + + Offset &= 0x3f; + //spin_lock_irqsave(&priv->rf_lock, flags); +// down(&priv->rf_sem); + if (priv->rf_chip == RF_8256) + { + + if (Offset >= 31) + { + priv->RfReg0Value[eRFPath] |= 0x140; + rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath] << 16)); + NewOffset = Offset - 30; + } + else if (Offset >= 16) + { + priv->RfReg0Value[eRFPath] |= 0x100; + priv->RfReg0Value[eRFPath] &= (~0x40); + rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16)); + NewOffset = Offset - 15; + } + else + NewOffset = Offset; + } + else + { + RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n"); + NewOffset = Offset; + } + + // Put write addr in [5:0] and write data in [31:16] + DataAndAddr = (Data<<16) | (NewOffset&0x3f); + + // Write Operation + rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); + + + if(Offset==0x0) + priv->RfReg0Value[eRFPath] = Data; + + // Switch back to Reg_Mode0; + if(priv->rf_chip == RF_8256) + { + if(Offset != 0) + { + priv->RfReg0Value[eRFPath] &= 0xebf; + rtl8192_setBBreg( + dev, + pPhyReg->rf3wireOffset, + bMaskDWord, + (priv->RfReg0Value[eRFPath] << 16)); + } + } + //spin_unlock_irqrestore(&priv->rf_lock, flags); +// up(&priv->rf_sem); + return; +} + +/****************************************************************************** + *function: This function set specific bits to RF register + * input: net_device dev + * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D + * u32 RegAddr //target addr to be modified + * u32 BitMask //taget bit pos in the addr to be modified + * u32 Data //value to be write + * output: none + * return: none + * notice: + * ****************************************************************************/ +void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + u32 Original_Value, BitShift, New_Value; +// u8 time = 0; + + if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) + return; + + if (priv->Rf_Mode == RF_OP_By_FW) + { + if (BitMask != bMask12Bits) // RF data is 12 bits only + { + Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr); + BitShift = rtl8192_CalculateBitShift(BitMask); + New_Value = ((Original_Value) & (~BitMask)) | (Data<< BitShift); + + phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value); + }else + phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data); + + udelay(200); + + } + else + { + if (BitMask != bMask12Bits) // RF data is 12 bits only + { + Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr); + BitShift = rtl8192_CalculateBitShift(BitMask); + New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift)); + + rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, New_Value); + }else + rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, Data); + } + return; +} + +/****************************************************************************** + *function: This function reads specific bits from RF register + * input: net_device dev + * u32 RegAddr //target addr to be readback + * u32 BitMask //taget bit pos in the addr to be readback + * output: none + * return: u32 Data //the readback register value + * notice: + * ****************************************************************************/ +u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask) +{ + u32 Original_Value, Readback_Value, BitShift; + struct r8192_priv *priv = ieee80211_priv(dev); + + + if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) + return 0; + if (priv->Rf_Mode == RF_OP_By_FW) + { + Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr); + BitShift = rtl8192_CalculateBitShift(BitMask); + Readback_Value = (Original_Value & BitMask) >> BitShift; + udelay(200); + return (Readback_Value); + } + else + { + Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr); + BitShift = rtl8192_CalculateBitShift(BitMask); + Readback_Value = (Original_Value & BitMask) >> BitShift; + return (Readback_Value); + } +} +/****************************************************************************** + *function: We support firmware to execute RF-R/W. + * input: dev + * output: none + * return: none + * notice: + * ***************************************************************************/ +static u32 +phy_FwRFSerialRead( + struct net_device* dev, + RF90_RADIO_PATH_E eRFPath, + u32 Offset ) +{ + u32 retValue = 0; + u32 Data = 0; + u8 time = 0; + //DbgPrint("FW RF CTRL\n\r"); + /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can + not execute the scheme in the initial step. Otherwise, RF-R/W will waste + much time. This is only for site survey. */ + // 1. Read operation need not insert data. bit 0-11 + //Data &= bMask12Bits; + // 2. Write RF register address. Bit 12-19 + Data |= ((Offset&0xFF)<<12); + // 3. Write RF path. bit 20-21 + Data |= ((eRFPath&0x3)<<20); + // 4. Set RF read indicator. bit 22=0 + //Data |= 0x00000; + // 5. Trigger Fw to operate the command. bit 31 + Data |= 0x80000000; + // 6. We can not execute read operation if bit 31 is 1. + while (read_nic_dword(dev, QPNR)&0x80000000) + { + // If FW can not finish RF-R/W for more than ?? times. We must reset FW. + if (time++ < 100) + { + //DbgPrint("FW not finish RF-R Time=%d\n\r", time); + udelay(10); + } + else + break; + } + // 7. Execute read operation. + write_nic_dword(dev, QPNR, Data); + // 8. Check if firmawre send back RF content. + while (read_nic_dword(dev, QPNR)&0x80000000) + { + // If FW can not finish RF-R/W for more than ?? times. We must reset FW. + if (time++ < 100) + { + //DbgPrint("FW not finish RF-W Time=%d\n\r", time); + udelay(10); + } + else + return (0); + } + retValue = read_nic_dword(dev, RF_DATA); + + return (retValue); + +} /* phy_FwRFSerialRead */ + +/****************************************************************************** + *function: We support firmware to execute RF-R/W. + * input: dev + * output: none + * return: none + * notice: + * ***************************************************************************/ +static void +phy_FwRFSerialWrite( + struct net_device* dev, + RF90_RADIO_PATH_E eRFPath, + u32 Offset, + u32 Data ) +{ + u8 time = 0; + + //DbgPrint("N FW RF CTRL RF-%d OF%02x DATA=%03x\n\r", eRFPath, Offset, Data); + /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can + not execute the scheme in the initial step. Otherwise, RF-R/W will waste + much time. This is only for site survey. */ + + // 1. Set driver write bit and 12 bit data. bit 0-11 + //Data &= bMask12Bits; // Done by uper layer. + // 2. Write RF register address. bit 12-19 + Data |= ((Offset&0xFF)<<12); + // 3. Write RF path. bit 20-21 + Data |= ((eRFPath&0x3)<<20); + // 4. Set RF write indicator. bit 22=1 + Data |= 0x400000; + // 5. Trigger Fw to operate the command. bit 31=1 + Data |= 0x80000000; + + // 6. Write operation. We can not write if bit 31 is 1. + while (read_nic_dword(dev, QPNR)&0x80000000) + { + // If FW can not finish RF-R/W for more than ?? times. We must reset FW. + if (time++ < 100) + { + //DbgPrint("FW not finish RF-W Time=%d\n\r", time); + udelay(10); + } + else + break; + } + // 7. No matter check bit. We always force the write. Because FW will + // not accept the command. + write_nic_dword(dev, QPNR, Data); + /* 2007/11/02 MH Acoording to test, we must delay 20us to wait firmware + to finish RF write operation. */ + /* 2008/01/17 MH We support delay in firmware side now. */ + //delay_us(20); + +} /* phy_FwRFSerialWrite */ + + +/****************************************************************************** + *function: This function read BB parameters from Header file we gen, + * and do register read/write + * input: dev + * output: none + * return: none + * notice: BB parameters may change all the time, so please make + * sure it has been synced with the newest. + * ***************************************************************************/ +void rtl8192_phy_configmac(struct net_device* dev) +{ + u32 dwArrayLen = 0, i; + u32* pdwArray = NULL; + struct r8192_priv *priv = ieee80211_priv(dev); + + if(priv->btxpowerdata_readfromEEPORM) + { + RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n"); + dwArrayLen = MACPHY_Array_PGLength; + pdwArray = rtl819XMACPHY_Array_PG; + + } + else + { + RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array\n"); + dwArrayLen = MACPHY_ArrayLength; + pdwArray = rtl819XMACPHY_Array; + } + for(i = 0; i<dwArrayLen; i=i+3){ + if(pdwArray[i] == 0x318) + { + pdwArray[i+2] = 0x00000800; + //DbgPrint("ptrArray[i], ptrArray[i+1], ptrArray[i+2] = %x, %x, %x\n", + // ptrArray[i], ptrArray[i+1], ptrArray[i+2]); + } + + RT_TRACE(COMP_DBG, "The Rtl8190MACPHY_Array[0] is %x Rtl8190MACPHY_Array[1] is %x Rtl8190MACPHY_Array[2] is %x\n", + pdwArray[i], pdwArray[i+1], pdwArray[i+2]); + rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1], pdwArray[i+2]); + } + return; + +} + +/****************************************************************************** + *function: This function do dirty work + * input: dev + * output: none + * return: none + * notice: BB parameters may change all the time, so please make + * sure it has been synced with the newest. + * ***************************************************************************/ + +void rtl8192_phyConfigBB(struct net_device* dev, u8 ConfigType) +{ + u32 i; + +#ifdef TO_DO_LIST + u32 *rtl8192PhyRegArrayTable = NULL, *rtl8192AgcTabArrayTable = NULL; + if(Adapter->bInHctTest) + { + PHY_REGArrayLen = PHY_REGArrayLengthDTM; + AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM; + Rtl8190PHY_REGArray_Table = Rtl819XPHY_REGArrayDTM; + Rtl8190AGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM; + } +#endif + if (ConfigType == BaseBand_Config_PHY_REG) + { + for (i=0; i<PHY_REG_1T2RArrayLength; i+=2) + { + rtl8192_setBBreg(dev, rtl819XPHY_REG_1T2RArray[i], bMaskDWord, rtl819XPHY_REG_1T2RArray[i+1]); + RT_TRACE(COMP_DBG, "i: %x, The Rtl819xUsbPHY_REGArray[0] is %x Rtl819xUsbPHY_REGArray[1] is %x \n",i, rtl819XPHY_REG_1T2RArray[i], rtl819XPHY_REG_1T2RArray[i+1]); + } + } + else if (ConfigType == BaseBand_Config_AGC_TAB) + { + for (i=0; i<AGCTAB_ArrayLength; i+=2) + { + rtl8192_setBBreg(dev, rtl819XAGCTAB_Array[i], bMaskDWord, rtl819XAGCTAB_Array[i+1]); + RT_TRACE(COMP_DBG, "i:%x, The rtl819XAGCTAB_Array[0] is %x rtl819XAGCTAB_Array[1] is %x \n",i, rtl819XAGCTAB_Array[i], rtl819XAGCTAB_Array[i+1]); + } + } + return; + + +} +/****************************************************************************** + *function: This function initialize Register definition offset for Radio Path + * A/B/C/D + * input: net_device dev + * output: none + * return: none + * notice: Initialization value here is constant and it should never be changed + * ***************************************************************************/ +void rtl8192_InitBBRFRegDef(struct net_device* dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); +// RF Interface Sowrtware Control + priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870 + priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) + priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 LSBs if read 32-bit from 0x874 + priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) + + // RF Interface Readback Value + priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0 + priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) + priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 LSBs if read 32-bit from 0x8E4 + priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) + + // RF Interface Output (and Enable) + priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860 + priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x864 + priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x868 + priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x86C + + // RF Interface (Output and) Enable + priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) + priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) + priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A) + priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E) + + //Addr of LSSI. Wirte RF register by driver + priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter + priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; + priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter; + priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter; + + // RF parameter + priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; //BB Band Select + priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter; + priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter; + priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter; + + // Tx AGC Gain Stage (same for all path. Should we remove this?) + priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage + priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage + priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage + priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage + + // Tranceiver A~D HSSI Parameter-1 + priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; //wire control parameter1 + priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; //wire control parameter1 + priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1; //wire control parameter1 + priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1; //wire control parameter1 + + // Tranceiver A~D HSSI Parameter-2 + priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; //wire control parameter2 + priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; //wire control parameter2 + priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2; //wire control parameter2 + priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; //wire control parameter1 + + // RF switch Control + priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; //TR/Ant switch control + priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl; + priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl; + priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl; + + // AGC control 1 + priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1; + priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1; + priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1; + priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1; + + // AGC control 2 + priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2; + priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2; + priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2; + priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2; + + // RX AFE control 1 + priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance; + priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance; + priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance; + priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance; + + // RX AFE control 1 + priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE; + priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE; + priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE; + priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE; + + // Tx AFE control 1 + priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance; + priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance; + priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance; + priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance; + + // Tx AFE control 2 + priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE; + priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE; + priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE; + priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE; + + // Tranceiver LSSI Readback + priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack; + priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack; + priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack; + priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack; + +} +/****************************************************************************** + *function: This function is to write register and then readback to make sure whether BB and RF is OK + * input: net_device dev + * HW90_BLOCK_E CheckBlock + * RF90_RADIO_PATH_E eRFPath //only used when checkblock is HW90_BLOCK_RF + * output: none + * return: return whether BB and RF is ok(0:OK; 1:Fail) + * notice: This function may be removed in the ASIC + * ***************************************************************************/ +u8 rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath) +{ +// struct r8192_priv *priv = ieee80211_priv(dev); +// BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath]; + u8 ret = 0; + u32 i, CheckTimes = 4, dwRegRead = 0; + u32 WriteAddr[4]; + u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f}; + // Initialize register address offset to be checked + WriteAddr[HW90_BLOCK_MAC] = 0x100; + WriteAddr[HW90_BLOCK_PHY0] = 0x900; + WriteAddr[HW90_BLOCK_PHY1] = 0x800; + WriteAddr[HW90_BLOCK_RF] = 0x3; + RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __FUNCTION__, CheckBlock); + for(i=0 ; i < CheckTimes ; i++) + { + + // + // Write Data to register and readback + // + switch(CheckBlock) + { + case HW90_BLOCK_MAC: + RT_TRACE(COMP_ERR, "PHY_CheckBBRFOK(): Never Write 0x100 here!"); + break; + + case HW90_BLOCK_PHY0: + case HW90_BLOCK_PHY1: + write_nic_dword(dev, WriteAddr[CheckBlock], WriteData[i]); + dwRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]); + break; + + case HW90_BLOCK_RF: + WriteData[i] &= 0xfff; + rtl8192_phy_SetRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMask12Bits, WriteData[i]); + // TODO: we should not delay for such a long time. Ask SD3 + msleep(1); + dwRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMask12Bits); + msleep(1); + break; + + default: + ret = 1; + break; + } + + + // + // Check whether readback data is correct + // + if(dwRegRead != WriteData[i]) + { + RT_TRACE((COMP_PHY|COMP_ERR), "====>error=====dwRegRead: %x, WriteData: %x \n", dwRegRead, WriteData[i]); + ret = 1; + break; + } + } + + return ret; +} + + +/****************************************************************************** + *function: This function initialize BB&RF + * input: net_device dev + * output: none + * return: none + * notice: Initialization value may change all the time, so please make + * sure it has been synced with the newest. + * ***************************************************************************/ +void rtl8192_BB_Config_ParaFile(struct net_device* dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + u8 bRegValue = 0, eCheckItem = 0, rtStatus = 0; + u32 dwRegValue = 0; + /************************************** + //<1>Initialize BaseBand + **************************************/ + + /*--set BB Global Reset--*/ + bRegValue = read_nic_byte(dev, BB_GLOBAL_RESET); + write_nic_byte(dev, BB_GLOBAL_RESET,(bRegValue|BB_GLOBAL_RESET_BIT)); + mdelay(50); + /*---set BB reset Active---*/ + dwRegValue = read_nic_dword(dev, CPU_GEN); + write_nic_dword(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST))); + + /*----Ckeck FPGAPHY0 and PHY1 board is OK----*/ + // TODO: this function should be removed on ASIC , Emily 2007.2.2 + for(eCheckItem=(HW90_BLOCK_E)HW90_BLOCK_PHY0; eCheckItem<=HW90_BLOCK_PHY1; eCheckItem++) + { + rtStatus = rtl8192_phy_checkBBAndRF(dev, (HW90_BLOCK_E)eCheckItem, (RF90_RADIO_PATH_E)0); //don't care RF path + if(rtStatus != 0) + { + RT_TRACE((COMP_ERR | COMP_PHY), "PHY_RF8256_Config():Check PHY%d Fail!!\n", eCheckItem-1); + return ; + } + } + /*---- Set CCK and OFDM Block "OFF"----*/ + rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0); + /*----BB Register Initilazation----*/ + //==m==>Set PHY REG From Header<==m== + rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG); + + /*----Set BB reset de-Active----*/ + dwRegValue = read_nic_dword(dev, CPU_GEN); + write_nic_dword(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST)); + + /*----BB AGC table Initialization----*/ + //==m==>Set PHY REG From Header<==m== + rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB); + + /*----Enable XSTAL ----*/ + write_nic_byte_E(dev, 0x5e, 0x00); + if (priv->card_8192_version == (u8)VERSION_819xU_A) + { + //Antenna gain offset from B/C/D to A + dwRegValue = (priv->AntennaTxPwDiff[1]<<4 | priv->AntennaTxPwDiff[0]); + rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC), dwRegValue); + + //XSTALLCap + dwRegValue = priv->CrystalCap & 0xf; + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap, dwRegValue); + } + + // Check if the CCK HighPower is turned ON. + // This is used to calculate PWDB. + priv->bCckHighPower = (u8)(rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, 0x200)); + return; +} +/****************************************************************************** + *function: This function initialize BB&RF + * input: net_device dev + * output: none + * return: none + * notice: Initialization value may change all the time, so please make + * sure it has been synced with the newest. + * ***************************************************************************/ +void rtl8192_BBConfig(struct net_device* dev) +{ + rtl8192_InitBBRFRegDef(dev); + //config BB&RF. As hardCode based initialization has not been well + //implemented, so use file first.FIXME:should implement it for hardcode? + rtl8192_BB_Config_ParaFile(dev); + return; +} + +/****************************************************************************** + *function: This function obtains the initialization value of Tx power Level offset + * input: net_device dev + * output: none + * return: none + * ***************************************************************************/ +void rtl8192_phy_getTxPower(struct net_device* dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + priv->MCSTxPowerLevelOriginalOffset[0] = + read_nic_dword(dev, rTxAGC_Rate18_06); + priv->MCSTxPowerLevelOriginalOffset[1] = + read_nic_dword(dev, rTxAGC_Rate54_24); + priv->MCSTxPowerLevelOriginalOffset[2] = + read_nic_dword(dev, rTxAGC_Mcs03_Mcs00); + priv->MCSTxPowerLevelOriginalOffset[3] = + read_nic_dword(dev, rTxAGC_Mcs07_Mcs04); + priv->MCSTxPowerLevelOriginalOffset[4] = + read_nic_dword(dev, rTxAGC_Mcs11_Mcs08); + priv->MCSTxPowerLevelOriginalOffset[5] = + read_nic_dword(dev, rTxAGC_Mcs15_Mcs12); + + // read rx initial gain + priv->DefaultInitialGain[0] = read_nic_byte(dev, rOFDM0_XAAGCCore1); + priv->DefaultInitialGain[1] = read_nic_byte(dev, rOFDM0_XBAGCCore1); + priv->DefaultInitialGain[2] = read_nic_byte(dev, rOFDM0_XCAGCCore1); + priv->DefaultInitialGain[3] = read_nic_byte(dev, rOFDM0_XDAGCCore1); + RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n", + priv->DefaultInitialGain[0], priv->DefaultInitialGain[1], + priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]); + + // read framesync + priv->framesync = read_nic_byte(dev, rOFDM0_RxDetector3); + priv->framesyncC34 = read_nic_byte(dev, rOFDM0_RxDetector2); + RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n", + rOFDM0_RxDetector3, priv->framesync); + + // read SIFS (save the value read fome MACPHY_REG.txt) + priv->SifsTime = read_nic_word(dev, SIFS); + + return; +} + +/****************************************************************************** + *function: This function obtains the initialization value of Tx power Level offset + * input: net_device dev + * output: none + * return: none + * ***************************************************************************/ +void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + u8 powerlevel = priv->TxPowerLevelCCK[channel-1]; + u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1]; + + switch(priv->rf_chip) + { + case RF_8256: + PHY_SetRF8256CCKTxPower(dev, powerlevel); //need further implement + PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G); + break; + default: +// case RF_8225: +// case RF_8258: + RT_TRACE((COMP_PHY|COMP_ERR), "error RF chipID(8225 or 8258) in function %s()\n", __FUNCTION__); + break; + } + return; +} + +/****************************************************************************** + *function: This function check Rf chip to do RF config + * input: net_device dev + * output: none + * return: only 8256 is supported + * ***************************************************************************/ +void rtl8192_phy_RFConfig(struct net_device* dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + + switch(priv->rf_chip) + { + case RF_8256: + PHY_RF8256_Config(dev); + break; + // case RF_8225: + // case RF_8258: + default: + RT_TRACE(COMP_ERR, "error chip id\n"); + break; + } + return; +} + +/****************************************************************************** + *function: This function update Initial gain + * input: net_device dev + * output: none + * return: As Windows has not implemented this, wait for complement + * ***************************************************************************/ +void rtl8192_phy_updateInitGain(struct net_device* dev) +{ + return; +} + +/****************************************************************************** + *function: This function read RF parameters from general head file, and do RF 3-wire + * input: net_device dev + * output: none + * return: return code show if RF configuration is successful(0:pass, 1:fail) + * Note: Delay may be required for RF configuration + * ***************************************************************************/ +u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E eRFPath) +{ + + int i; + //u32* pRFArray; + u8 ret = 0; + + switch(eRFPath){ + case RF90_PATH_A: + for(i = 0;i<RadioA_ArrayLength; i=i+2){ + + if(rtl819XRadioA_Array[i] == 0xfe){ + mdelay(100); + continue; + } + rtl8192_phy_SetRFReg(dev, eRFPath, rtl819XRadioA_Array[i], bMask12Bits, rtl819XRadioA_Array[i+1]); + mdelay(1); + + } + break; + case RF90_PATH_B: + for(i = 0;i<RadioB_ArrayLength; i=i+2){ + + if(rtl819XRadioB_Array[i] == 0xfe){ + mdelay(100); + continue; + } + rtl8192_phy_SetRFReg(dev, eRFPath, rtl819XRadioB_Array[i], bMask12Bits, rtl819XRadioB_Array[i+1]); + mdelay(1); + + } + break; + case RF90_PATH_C: + for(i = 0;i<RadioC_ArrayLength; i=i+2){ + + if(rtl819XRadioC_Array[i] == 0xfe){ + mdelay(100); + continue; + } + rtl8192_phy_SetRFReg(dev, eRFPath, rtl819XRadioC_Array[i], bMask12Bits, rtl819XRadioC_Array[i+1]); + mdelay(1); + + } + break; + case RF90_PATH_D: + for(i = 0;i<RadioD_ArrayLength; i=i+2){ + + if(rtl819XRadioD_Array[i] == 0xfe){ + mdelay(100); + continue; + } + rtl8192_phy_SetRFReg(dev, eRFPath, rtl819XRadioD_Array[i], bMask12Bits, rtl819XRadioD_Array[i+1]); + mdelay(1); + + } + break; + default: + break; + } + + return ret;; + +} +/****************************************************************************** + *function: This function set Tx Power of the channel + * input: struct net_device *dev + * u8 channel + * output: none + * return: none + * Note: + * ***************************************************************************/ +void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + u8 powerlevel = priv->TxPowerLevelCCK[channel-1]; + u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1]; + + switch(priv->rf_chip) + { + case RF_8225: +#ifdef TO_DO_LIST + PHY_SetRF8225CckTxPower(Adapter, powerlevel); + PHY_SetRF8225OfdmTxPower(Adapter, powerlevelOFDM24G); +#endif + break; + + case RF_8256: + PHY_SetRF8256CCKTxPower(dev, powerlevel); + PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G); + break; + + case RF_8258: + break; + default: + RT_TRACE(COMP_ERR, "unknown rf chip ID in rtl8192_SetTxPowerLevel()\n"); + break; + } + return; +} + +/****************************************************************************** + *function: This function set RF state on or off + * input: struct net_device *dev + * RT_RF_POWER_STATE eRFPowerState //Power State to set + * output: none + * return: none + * Note: + * ***************************************************************************/ +bool rtl8192_SetRFPowerState(struct net_device *dev, RT_RF_POWER_STATE eRFPowerState) +{ + bool bResult = true; +// u8 eRFPath; + struct r8192_priv *priv = ieee80211_priv(dev); + + if(eRFPowerState == priv->ieee80211->eRFPowerState) + return false; + + if(priv->SetRFPowerStateInProgress == true) + return false; + + priv->SetRFPowerStateInProgress = true; + + switch(priv->rf_chip) + { + case RF_8256: + switch( eRFPowerState ) + { + case eRfOn: +#if 0 + rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1); // 0x860[4] + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3); // 0x88c[4] + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x3); // 0x880[6:5] + rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x3); // 0xc04[3:0] + rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x3); // 0xd04[3:0] + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0x7000, 0x3); // 0x884[14:12] + // for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++) + // PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x2); + + //SwChnl(Adapter->ChannelID); +#endif + //RF-A, RF-B + //enable RF-Chip A/B + rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1); // 0x860[4] + //analog to digital on + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8] + //digital to analog on + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x3); // 0x880[4:3] + //rx antenna on + rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3);// 0xc04[1:0] + //rx antenna on + rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3);// 0xd04[1:0] + //analog to digital part2 on + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x3); // 0x880[6:5] + + break; + + case eRfSleep: + + break; + + case eRfOff: +#if 0 + rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0); // 0x860[4] + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x0); // 0x88c[4] + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0); // 0x880[6:5] + rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0); // 0xc04[3:0] + rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0); // 0xd04[3:0] + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0x7000, 0x0); // 0x884[14:12] + // for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++) + // PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x0); +#endif + //RF-A, RF-B + //disable RF-Chip A/B + rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0); // 0x860[4] + //analog to digital off, for power save + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8] + //digital to analog off, for power save + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x0); // 0x880[4:3] + //rx antenna off + rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0);// 0xc04[3:0] + //rx antenna off + rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);// 0xd04[3:0] + //analog to digital part2 off, for power save + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0); // 0x880[6:5] + + break; + + default: + bResult = false; + RT_TRACE(COMP_ERR, "SetRFPowerState819xUsb(): unknow state to set: 0x%X!!!\n", eRFPowerState); + break; + } + break; + default: + RT_TRACE(COMP_ERR, "Not support rf_chip(%x)\n", priv->rf_chip); + break; + } +#ifdef TO_DO_LIST + if(bResult) + { + // Update current RF state variable. + pHalData->eRFPowerState = eRFPowerState; + switch(pHalData->RFChipID ) + { + case RF_8256: + switch(pHalData->eRFPowerState) + { + case eRfOff: + // + //If Rf off reason is from IPS, Led should blink with no link, by Maddest 071015 + // + if(pMgntInfo->RfOffReason==RF_CHANGE_BY_IPS ) + { + Adapter->HalFunc.LedControlHandler(Adapter,LED_CTL_NO_LINK); + } + else + { + // Turn off LED if RF is not ON. + Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_POWER_OFF); + } + break; + + case eRfOn: + // Turn on RF we are still linked, which might happen when + // we quickly turn off and on HW RF. 2006.05.12, by rcnjko. + if( pMgntInfo->bMediaConnect == TRUE ) + { + Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_LINK); + } + else + { + // Turn off LED if RF is not ON. + Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_NO_LINK); + } + break; + + default: + // do nothing. + break; + }// Switch RF state + break; + + default: + RT_TRACE(COMP_RF, DBG_LOUD, ("SetRFPowerState8190(): Unknown RF type\n")); + break; + } + + } +#endif + priv->SetRFPowerStateInProgress = false; + + return bResult; +} + +/**************************************************************************************** + *function: This function set command table variable(struct SwChnlCmd). + * input: SwChnlCmd* CmdTable //table to be set. + * u32 CmdTableIdx //variable index in table to be set + * u32 CmdTableSz //table size. + * SwChnlCmdID CmdID //command ID to set. + * u32 Para1 + * u32 Para2 + * u32 msDelay + * output: + * return: true if finished, false otherwise + * Note: + * ************************************************************************************/ +u8 rtl8192_phy_SetSwChnlCmdArray( + SwChnlCmd* CmdTable, + u32 CmdTableIdx, + u32 CmdTableSz, + SwChnlCmdID CmdID, + u32 Para1, + u32 Para2, + u32 msDelay + ) +{ + SwChnlCmd* pCmd; + + if(CmdTable == NULL) + { + RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n"); + return false; + } + if(CmdTableIdx >= CmdTableSz) + { + RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n", + CmdTableIdx, CmdTableSz); + return false; + } + + pCmd = CmdTable + CmdTableIdx; + pCmd->CmdID = CmdID; + pCmd->Para1 = Para1; + pCmd->Para2 = Para2; + pCmd->msDelay = msDelay; + + return true; +} +/****************************************************************************** + *function: This function set channel step by step + * input: struct net_device *dev + * u8 channel + * u8* stage //3 stages + * u8* step // + * u32* delay //whether need to delay + * output: store new stage, step and delay for next step(combine with function above) + * return: true if finished, false otherwise + * Note: Wait for simpler function to replace it //wb + * ***************************************************************************/ +u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8* stage, u8* step, u32* delay) +{ + struct r8192_priv *priv = ieee80211_priv(dev); +// PCHANNEL_ACCESS_SETTING pChnlAccessSetting; + SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT]; + u32 PreCommonCmdCnt; + SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT]; + u32 PostCommonCmdCnt; + SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT]; + u32 RfDependCmdCnt; + SwChnlCmd *CurrentCmd = NULL; + //RF90_RADIO_PATH_E eRFPath; + u8 eRFPath; +// u32 RfRetVal; +// u8 RetryCnt; + + RT_TRACE(COMP_CH, "====>%s()====stage:%d, step:%d, channel:%d\n", __FUNCTION__, *stage, *step, channel); +// RT_ASSERT(IsLegalChannel(Adapter, channel), ("illegal channel: %d\n", channel)); +#ifdef ENABLE_DOT11D + if (!IsLegalChannel(priv->ieee80211, channel)) + { + RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n", channel); + return true; //return true to tell upper caller function this channel setting is finished! Or it will in while loop. + } +#endif +//FIXME:need to check whether channel is legal or not here.WB + + + //for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++) +// for(eRFPath = 0; eRFPath <RF90_PATH_MAX; eRFPath++) +// { +// if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) +// continue; + // <1> Fill up pre common command. + PreCommonCmdCnt = 0; + rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT, + CmdID_SetTxPowerLevel, 0, 0, 0); + rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT, + CmdID_End, 0, 0, 0); + + // <2> Fill up post common command. + PostCommonCmdCnt = 0; + + rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT, + CmdID_End, 0, 0, 0); + + // <3> Fill up RF dependent command. + RfDependCmdCnt = 0; + switch( priv->rf_chip ) + { + case RF_8225: + if (!(channel >= 1 && channel <= 14)) + { + RT_TRACE(COMP_ERR, "illegal channel for Zebra 8225: %d\n", channel); + return true; + } + rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, + CmdID_RF_WriteReg, rZebra1_Channel, RF_CHANNEL_TABLE_ZEBRA[channel], 10); + rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, + CmdID_End, 0, 0, 0); + break; + + case RF_8256: + // TEST!! This is not the table for 8256!! + if (!(channel >= 1 && channel <= 14)) + { + RT_TRACE(COMP_ERR, "illegal channel for Zebra 8256: %d\n", channel); + return true; + } + rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, + CmdID_RF_WriteReg, rZebra1_Channel, channel, 10); + rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, + CmdID_End, 0, 0, 0); + break; + + case RF_8258: + break; + + default: + RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip); + return true; + break; + } + + + do{ + switch(*stage) + { + case 0: + CurrentCmd=&PreCommonCmd[*step]; + break; + case 1: + CurrentCmd=&RfDependCmd[*step]; + break; + case 2: + CurrentCmd=&PostCommonCmd[*step]; + break; + } + + if(CurrentCmd->CmdID==CmdID_End) + { + if((*stage)==2) + { + (*delay)=CurrentCmd->msDelay; + return true; + } + else + { + (*stage)++; + (*step)=0; + continue; + } + } + + switch(CurrentCmd->CmdID) + { + case CmdID_SetTxPowerLevel: + if(priv->card_8192_version == (u8)VERSION_819xU_A) //xiong: consider it later! + rtl8192_SetTxPowerLevel(dev,channel); + break; + case CmdID_WritePortUlong: + write_nic_dword(dev, CurrentCmd->Para1, CurrentCmd->Para2); + break; + case CmdID_WritePortUshort: + write_nic_word(dev, CurrentCmd->Para1, (u16)CurrentCmd->Para2); + break; + case CmdID_WritePortUchar: + write_nic_byte(dev, CurrentCmd->Para1, (u8)CurrentCmd->Para2); + break; + case CmdID_RF_WriteReg: + for(eRFPath = 0; eRFPath < RF90_PATH_MAX; eRFPath++) + { + rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bZebra1_ChannelNum, CurrentCmd->Para2); + } + break; + default: + break; + } + + break; + }while(true); +// }/*for(Number of RF paths)*/ + + (*delay)=CurrentCmd->msDelay; + (*step)++; + return false; +} + +/****************************************************************************** + *function: This function does acturally set channel work + * input: struct net_device *dev + * u8 channel + * output: none + * return: noin + * Note: We should not call this function directly + * ***************************************************************************/ +void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + u32 delay = 0; + + while(!rtl8192_phy_SwChnlStepByStep(dev,channel,&priv->SwChnlStage,&priv->SwChnlStep,&delay)) + { + // if(delay>0) + // msleep(delay);//or mdelay? need further consideration + if(!priv->up) + break; + } +} +/****************************************************************************** + *function: Callback routine of the work item for switch channel. + * input: + * + * output: none + * return: noin + * ***************************************************************************/ +void rtl8192_SwChnl_WorkItem(struct net_device *dev) +{ + + struct r8192_priv *priv = ieee80211_priv(dev); + + RT_TRACE(COMP_CH, "==> SwChnlCallback819xUsbWorkItem(), chan:%d\n", priv->chan); + + + rtl8192_phy_FinishSwChnlNow(dev , priv->chan); + + RT_TRACE(COMP_CH, "<== SwChnlCallback819xUsbWorkItem()\n"); +} + +/****************************************************************************** + *function: This function scheduled actural workitem to set channel + * input: net_device dev + * u8 channel //channel to set + * output: none + * return: return code show if workitem is scheduled(1:pass, 0:fail) + * Note: Delay may be required for RF configuration + * ***************************************************************************/ +u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + RT_TRACE(COMP_CH, "=====>%s(), SwChnlInProgress:%d\n", __FUNCTION__, priv->SwChnlInProgress); + if(!priv->up) + return false; + if(priv->SwChnlInProgress) + return false; + +// if(pHalData->SetBWModeInProgress) +// return; +if (0) //to test current channel from RF reg 0x7. +{ + u8 eRFPath; + for(eRFPath = 0; eRFPath < 2; eRFPath++){ + printk("====>set channel:%x\n",rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x7, bZebra1_ChannelNum)); + udelay(10); + } +} + //-------------------------------------------- + switch(priv->ieee80211->mode) + { + case WIRELESS_MODE_A: + case WIRELESS_MODE_N_5G: + if (channel<=14){ + RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14"); + return false; + } + break; + case WIRELESS_MODE_B: + if (channel>14){ + RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14"); + return false; + } + break; + case WIRELESS_MODE_G: + case WIRELESS_MODE_N_24G: + if (channel>14){ + RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14"); + return false; + } + break; + } + //-------------------------------------------- + + priv->SwChnlInProgress = true; + if(channel == 0) + channel = 1; + + priv->chan=channel; + + priv->SwChnlStage=0; + priv->SwChnlStep=0; +// schedule_work(&(priv->SwChnlWorkItem)); +// rtl8192_SwChnl_WorkItem(dev); + if(priv->up) { +// queue_work(priv->priv_wq,&(priv->SwChnlWorkItem)); + rtl8192_SwChnl_WorkItem(dev); + } + + priv->SwChnlInProgress = false; + return true; +} + + +// +/****************************************************************************** + *function: Callback routine of the work item for set bandwidth mode. + * input: struct net_device *dev + * HT_CHANNEL_WIDTH Bandwidth //20M or 40M + * HT_EXTCHNL_OFFSET Offset //Upper, Lower, or Don't care + * output: none + * return: none + * Note: I doubt whether SetBWModeInProgress flag is necessary as we can + * test whether current work in the queue or not.//do I? + * ***************************************************************************/ +void rtl8192_SetBWModeWorkItem(struct net_device *dev) +{ + + struct r8192_priv *priv = ieee80211_priv(dev); + u8 regBwOpMode; + + RT_TRACE(COMP_SWBW, "==>rtl8192_SetBWModeWorkItem() Switch to %s bandwidth\n", \ + priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz") + + + if(priv->rf_chip == RF_PSEUDO_11N) + { + priv->SetBWModeInProgress= false; + return; + } + + //<1>Set MAC register + regBwOpMode = read_nic_byte(dev, BW_OPMODE); + + switch(priv->CurrentChannelBW) + { + case HT_CHANNEL_WIDTH_20: + regBwOpMode |= BW_OPMODE_20MHZ; + // 2007/02/07 Mark by Emily becasue we have not verify whether this register works + write_nic_byte(dev, BW_OPMODE, regBwOpMode); + break; + + case HT_CHANNEL_WIDTH_20_40: + regBwOpMode &= ~BW_OPMODE_20MHZ; + // 2007/02/07 Mark by Emily becasue we have not verify whether this register works + write_nic_byte(dev, BW_OPMODE, regBwOpMode); + break; + + default: + RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",priv->CurrentChannelBW); + break; + } + + //<2>Set PHY related register + switch(priv->CurrentChannelBW) + { + case HT_CHANNEL_WIDTH_20: + // Add by Vivi 20071119 + rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); + rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0); + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1); + + // Correct the tx power for CCK rate in 20M. Suggest by YN, 20071207 +#if 0 + write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000); + write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317); + write_nic_dword(dev, rCCK0_DebugPort, 0x00000204); +#endif + priv->cck_present_attentuation = + priv->cck_present_attentuation_20Mdefault + priv->cck_present_attentuation_difference; + + if(priv->cck_present_attentuation > 22) + priv->cck_present_attentuation= 22; + if(priv->cck_present_attentuation< 0) + priv->cck_present_attentuation = 0; + RT_TRACE(COMP_INIT, "20M, pHalData->CCKPresentAttentuation = %d\n", priv->cck_present_attentuation); + + if(priv->chan == 14 && !priv->bcck_in_ch14) + { + priv->bcck_in_ch14 = TRUE; + dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); + } + else if(priv->chan != 14 && priv->bcck_in_ch14) + { + priv->bcck_in_ch14 = FALSE; + dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); + } + else + dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); + + break; + case HT_CHANNEL_WIDTH_20_40: + // Add by Vivi 20071119 + rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1); + rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1); + rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1)); + rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0); + rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC); +#if 0 + // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207 + write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000); + write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e); + write_nic_dword(dev, rCCK0_DebugPort, 0x00000409); +#endif + priv->cck_present_attentuation = + priv->cck_present_attentuation_40Mdefault + priv->cck_present_attentuation_difference; + + if(priv->cck_present_attentuation > 22) + priv->cck_present_attentuation = 22; + if(priv->cck_present_attentuation < 0) + priv->cck_present_attentuation = 0; + + RT_TRACE(COMP_INIT, "40M, pHalData->CCKPresentAttentuation = %d\n", priv->cck_present_attentuation); + if(priv->chan == 14 && !priv->bcck_in_ch14) + { + priv->bcck_in_ch14 = true; + dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); + } + else if(priv->chan!= 14 && priv->bcck_in_ch14) + { + priv->bcck_in_ch14 = false; + dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); + } + else + dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); + + break; + default: + RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n" ,priv->CurrentChannelBW); + break; + + } + //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315 + +#if 1 + //<3>Set RF related register + switch( priv->rf_chip ) + { + case RF_8225: +#ifdef TO_DO_LIST + PHY_SetRF8225Bandwidth(Adapter, pHalData->CurrentChannelBW); +#endif + break; + + case RF_8256: + PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW); + break; + + case RF_8258: + // PHY_SetRF8258Bandwidth(); + break; + + case RF_PSEUDO_11N: + // Do Nothing + break; + + default: + RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip); + break; + } +#endif + priv->SetBWModeInProgress= false; + + RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb(), %d", atomic_read(&(priv->ieee80211->atm_swbw)) ); +} + +/****************************************************************************** + *function: This function schedules bandwith switch work. + * input: struct net_device *dev + * HT_CHANNEL_WIDTH Bandwidth //20M or 40M + * HT_EXTCHNL_OFFSET Offset //Upper, Lower, or Don't care + * output: none + * return: none + * Note: I doubt whether SetBWModeInProgress flag is necessary as we can + * test whether current work in the queue or not.//do I? + * ***************************************************************************/ +void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + + if(priv->SetBWModeInProgress) + return; + priv->SetBWModeInProgress= true; + + priv->CurrentChannelBW = Bandwidth; + + if(Offset==HT_EXTCHNL_OFFSET_LOWER) + priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER; + else if(Offset==HT_EXTCHNL_OFFSET_UPPER) + priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER; + else + priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + + //queue_work(priv->priv_wq, &(priv->SetBWModeWorkItem)); + // schedule_work(&(priv->SetBWModeWorkItem)); + rtl8192_SetBWModeWorkItem(dev); + +} + +void InitialGain819xUsb(struct net_device *dev, u8 Operation) +{ + struct r8192_priv *priv = ieee80211_priv(dev); + + priv->InitialGainOperateType = Operation; + + if(priv->up) + { + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + queue_delayed_work(priv->priv_wq,&priv->initialgain_operate_wq,0); + #else + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) + schedule_task(&priv->initialgain_operate_wq); + #else + queue_work(priv->priv_wq,&priv->initialgain_operate_wq); + #endif + #endif + } +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) +extern void InitialGainOperateWorkItemCallBack(struct work_struct *work) +{ + struct delayed_work *dwork = container_of(work,struct delayed_work,work); + struct r8192_priv *priv = container_of(dwork,struct r8192_priv,initialgain_operate_wq); + struct net_device *dev = priv->ieee80211->dev; +#else +extern void InitialGainOperateWorkItemCallBack(struct net_device *dev) +{ + struct r8192_priv *priv = ieee80211_priv(dev); +#endif +#define SCAN_RX_INITIAL_GAIN 0x17 +#define POWER_DETECTION_TH 0x08 + u32 BitMask; + u8 initial_gain; + u8 Operation; + + Operation = priv->InitialGainOperateType; + + switch(Operation) + { + case IG_Backup: + RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n"); + initial_gain = SCAN_RX_INITIAL_GAIN;//priv->DefaultInitialGain[0];// + BitMask = bMaskByte0; + if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) + rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF + priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask); + priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask); + priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, BitMask); + priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, BitMask); + BitMask = bMaskByte2; + priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, BitMask); + + RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1); + RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1); + RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1); + RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1); + RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca); + + RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n", initial_gain); + write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain); + write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain); + write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain); + write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain); + RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n", POWER_DETECTION_TH); + write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH); + break; + case IG_Restore: + RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n"); + BitMask = 0x7f; //Bit0~ Bit6 + if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) + rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF + + rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1); + rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1); + rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, (u32)priv->initgain_backup.xcagccore1); + rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)priv->initgain_backup.xdagccore1); + BitMask = bMaskByte2; + rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, (u32)priv->initgain_backup.cca); + + RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1); + RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1); + RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1); + RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1); + RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca); + +#ifdef RTL8190P + SetTxPowerLevel8190(Adapter,priv->CurrentChannel); +#endif +#ifdef RTL8192E + SetTxPowerLevel8190(Adapter,priv->CurrentChannel); +#endif +//#ifdef RTL8192U + rtl8192_phy_setTxPower(dev,priv->ieee80211->current_network.channel); +//#endif + + if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) + rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // FW DIG ON + break; + default: + RT_TRACE(COMP_SCAN, "Unknown IG Operation. \n"); + break; + } +} + diff --git a/drivers/staging/rtl8192su/r819xU_phy.h b/drivers/staging/rtl8192su/r819xU_phy.h new file mode 100644 index 000000000000..c165ac1265d9 --- /dev/null +++ b/drivers/staging/rtl8192su/r819xU_phy.h @@ -0,0 +1,94 @@ +#ifndef _R819XU_PHY_H +#define _R819XU_PHY_H + +/* Channel switch:The size of command tables for switch channel*/ +#define MAX_PRECMD_CNT 16 +#define MAX_RFDEPENDCMD_CNT 16 +#define MAX_POSTCMD_CNT 16 + +typedef enum _SwChnlCmdID{ + CmdID_End, + CmdID_SetTxPowerLevel, + CmdID_BBRegWrite10, + CmdID_WritePortUlong, + CmdID_WritePortUshort, + CmdID_WritePortUchar, + CmdID_RF_WriteReg, +}SwChnlCmdID; + +/*--------------------------------Define structure--------------------------------*/ +/* 1. Switch channel related */ +typedef struct _SwChnlCmd{ + SwChnlCmdID CmdID; + u32 Para1; + u32 Para2; + u32 msDelay; +}__attribute__ ((packed)) SwChnlCmd; + +extern u32 rtl819XMACPHY_Array_PG[]; +extern u32 rtl819XPHY_REG_1T2RArray[]; +extern u32 rtl819XAGCTAB_Array[]; +extern u32 rtl819XRadioA_Array[]; +extern u32 rtl819XRadioB_Array[]; +extern u32 rtl819XRadioC_Array[]; +extern u32 rtl819XRadioD_Array[]; + +typedef enum _HW90_BLOCK{ + HW90_BLOCK_MAC = 0, + HW90_BLOCK_PHY0 = 1, + HW90_BLOCK_PHY1 = 2, + HW90_BLOCK_RF = 3, + HW90_BLOCK_MAXIMUM = 4, // Never use this +}HW90_BLOCK_E, *PHW90_BLOCK_E; + +typedef enum _RF90_RADIO_PATH{ + RF90_PATH_A = 0, //Radio Path A + RF90_PATH_B = 1, //Radio Path B + RF90_PATH_C = 2, //Radio Path C + RF90_PATH_D = 3, //Radio Path D + RF90_PATH_MAX //Max RF number 92 support +}RF90_RADIO_PATH_E, *PRF90_RADIO_PATH_E; + +#define bMaskByte0 0xff +#define bMaskByte1 0xff00 +#define bMaskByte2 0xff0000 +#define bMaskByte3 0xff000000 +#define bMaskHWord 0xffff0000 +#define bMaskLWord 0x0000ffff +#define bMaskDWord 0xffffffff + +//extern u32 rtl8192_CalculateBitShift(u32 dwBitMask); +extern u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath); +extern void rtl8192_setBBreg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask, u32 dwData); +extern u32 rtl8192_QueryBBReg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask); +//extern u32 rtl8192_phy_RFSerialRead(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset); +//extern void rtl8192_phy_RFSerialWrite(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data); +extern void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data); +extern u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask); +extern void rtl8192_phy_configmac(struct net_device* dev); +extern void rtl8192_phyConfigBB(struct net_device* dev, u8 ConfigType); +//extern void rtl8192_InitBBRFRegDef(struct net_device* dev); +extern u8 rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath); +//extern void rtl8192_BB_Config_ParaFile(struct net_device* dev); +extern void rtl8192_BBConfig(struct net_device* dev); +extern void rtl8192_phy_getTxPower(struct net_device* dev); +extern void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel); +extern void rtl8192_phy_RFConfig(struct net_device* dev); +extern void rtl8192_phy_updateInitGain(struct net_device* dev); +extern u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E eRFPath); + +extern u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel); +extern void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset); +extern void rtl8192_SwChnl_WorkItem(struct net_device *dev); +void rtl8192_SetBWModeWorkItem(struct net_device *dev); +extern bool rtl8192_SetRFPowerState(struct net_device *dev, RT_RF_POWER_STATE eRFPowerState); +//added by amy +extern void InitialGain819xUsb(struct net_device *dev, u8 Operation); + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) +extern void InitialGainOperateWorkItemCallBack(struct work_struct *work); +#else +extern void InitialGainOperateWorkItemCallBack(struct net_device *dev); +#endif + +#endif diff --git a/drivers/staging/rtl8192su/r819xU_phyreg.h b/drivers/staging/rtl8192su/r819xU_phyreg.h new file mode 100644 index 000000000000..b62f1a6fb1eb --- /dev/null +++ b/drivers/staging/rtl8192su/r819xU_phyreg.h @@ -0,0 +1,871 @@ +#ifndef _R819XU_PHYREG_H +#define _R819XU_PHYREG_H + + +#define RF_DATA 0x1d4 // FW will write RF data in the register. + +//Register //duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF +//page 1 +#define rPMAC_Reset 0x100 +#define rPMAC_TxStart 0x104 +#define rPMAC_TxLegacySIG 0x108 +#define rPMAC_TxHTSIG1 0x10c +#define rPMAC_TxHTSIG2 0x110 +#define rPMAC_PHYDebug 0x114 +#define rPMAC_TxPacketNum 0x118 +#define rPMAC_TxIdle 0x11c +#define rPMAC_TxMACHeader0 0x120 +#define rPMAC_TxMACHeader1 0x124 +#define rPMAC_TxMACHeader2 0x128 +#define rPMAC_TxMACHeader3 0x12c +#define rPMAC_TxMACHeader4 0x130 +#define rPMAC_TxMACHeader5 0x134 +#define rPMAC_TxDataType 0x138 +#define rPMAC_TxRandomSeed 0x13c +#define rPMAC_CCKPLCPPreamble 0x140 +#define rPMAC_CCKPLCPHeader 0x144 +#define rPMAC_CCKCRC16 0x148 +#define rPMAC_OFDMRxCRC32OK 0x170 +#define rPMAC_OFDMRxCRC32Er 0x174 +#define rPMAC_OFDMRxParityEr 0x178 +#define rPMAC_OFDMRxCRC8Er 0x17c +#define rPMAC_CCKCRxRC16Er 0x180 +#define rPMAC_CCKCRxRC32Er 0x184 +#define rPMAC_CCKCRxRC32OK 0x188 +#define rPMAC_TxStatus 0x18c + +//page8 +#define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC +#define rFPGA0_TxInfo 0x804 +#define rFPGA0_PSDFunction 0x808 +#define rFPGA0_TxGainStage 0x80c +#define rFPGA0_RFTiming1 0x810 +#define rFPGA0_RFTiming2 0x814 +//#define rFPGA0_XC_RFTiming 0x818 +//#define rFPGA0_XD_RFTiming 0x81c +#define rFPGA0_XA_HSSIParameter1 0x820 +#define rFPGA0_XA_HSSIParameter2 0x824 +#define rFPGA0_XB_HSSIParameter1 0x828 +#define rFPGA0_XB_HSSIParameter2 0x82c +#define rFPGA0_XC_HSSIParameter1 0x830 +#define rFPGA0_XC_HSSIParameter2 0x834 +#define rFPGA0_XD_HSSIParameter1 0x838 +#define rFPGA0_XD_HSSIParameter2 0x83c +#define rFPGA0_XA_LSSIParameter 0x840 +#define rFPGA0_XB_LSSIParameter 0x844 +#define rFPGA0_XC_LSSIParameter 0x848 +#define rFPGA0_XD_LSSIParameter 0x84c +#define rFPGA0_RFWakeUpParameter 0x850 +#define rFPGA0_RFSleepUpParameter 0x854 +#define rFPGA0_XAB_SwitchControl 0x858 +#define rFPGA0_XCD_SwitchControl 0x85c +#define rFPGA0_XA_RFInterfaceOE 0x860 +#define rFPGA0_XB_RFInterfaceOE 0x864 +#define rFPGA0_XC_RFInterfaceOE 0x868 +#define rFPGA0_XD_RFInterfaceOE 0x86c +#define rFPGA0_XAB_RFInterfaceSW 0x870 +#define rFPGA0_XCD_RFInterfaceSW 0x874 +#define rFPGA0_XAB_RFParameter 0x878 +#define rFPGA0_XCD_RFParameter 0x87c +#define rFPGA0_AnalogParameter1 0x880 +#define rFPGA0_AnalogParameter2 0x884 +#define rFPGA0_AnalogParameter3 0x888 +#define rFPGA0_AnalogParameter4 0x88c +#define rFPGA0_XA_LSSIReadBack 0x8a0 +#define rFPGA0_XB_LSSIReadBack 0x8a4 +#define rFPGA0_XC_LSSIReadBack 0x8a8 +#define rFPGA0_XD_LSSIReadBack 0x8ac +#define rFPGA0_PSDReport 0x8b4 +#define rFPGA0_XAB_RFInterfaceRB 0x8e0 +#define rFPGA0_XCD_RFInterfaceRB 0x8e4 + +//page 9 +#define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC +#define rFPGA1_TxBlock 0x904 +#define rFPGA1_DebugSelect 0x908 +#define rFPGA1_TxInfo 0x90c + +//page a +#define rCCK0_System 0xa00 +#define rCCK0_AFESetting 0xa04 +#define rCCK0_CCA 0xa08 +#define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level +#define rCCK0_RxAGC2 0xa10 //AGC & DAGC +#define rCCK0_RxHP 0xa14 +#define rCCK0_DSPParameter1 0xa18 //Timing recovery & Channel estimation threshold +#define rCCK0_DSPParameter2 0xa1c //SQ threshold +#define rCCK0_TxFilter1 0xa20 +#define rCCK0_TxFilter2 0xa24 +#define rCCK0_DebugPort 0xa28 //debug port and Tx filter3 +#define rCCK0_FalseAlarmReport 0xa2c //0xa2d +#define rCCK0_TRSSIReport 0xa50 +#define rCCK0_RxReport 0xa54 //0xa57 +#define rCCK0_FACounterLower 0xa5c //0xa5b +#define rCCK0_FACounterUpper 0xa58 //0xa5c + +//page c +#define rOFDM0_LSTF 0xc00 +#define rOFDM0_TRxPathEnable 0xc04 +#define rOFDM0_TRMuxPar 0xc08 +#define rOFDM0_TRSWIsolation 0xc0c +#define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter +#define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix +#define rOFDM0_XBRxAFE 0xc18 +#define rOFDM0_XBRxIQImbalance 0xc1c +#define rOFDM0_XCRxAFE 0xc20 +#define rOFDM0_XCRxIQImbalance 0xc24 +#define rOFDM0_XDRxAFE 0xc28 +#define rOFDM0_XDRxIQImbalance 0xc2c +#define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD +#define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync. +#define rOFDM0_RxDetector3 0xc38 //Frame Sync. +#define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI +#define rOFDM0_RxDSP 0xc40 //Rx Sync Path +#define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC +#define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold +#define rOFDM0_ECCAThreshold 0xc4c // energy CCA +#define rOFDM0_XAAGCCore1 0xc50 +#define rOFDM0_XAAGCCore2 0xc54 +#define rOFDM0_XBAGCCore1 0xc58 +#define rOFDM0_XBAGCCore2 0xc5c +#define rOFDM0_XCAGCCore1 0xc60 +#define rOFDM0_XCAGCCore2 0xc64 +#define rOFDM0_XDAGCCore1 0xc68 +#define rOFDM0_XDAGCCore2 0xc6c +#define rOFDM0_AGCParameter1 0xc70 +#define rOFDM0_AGCParameter2 0xc74 +#define rOFDM0_AGCRSSITable 0xc78 +#define rOFDM0_HTSTFAGC 0xc7c +#define rOFDM0_XATxIQImbalance 0xc80 +#define rOFDM0_XATxAFE 0xc84 +#define rOFDM0_XBTxIQImbalance 0xc88 +#define rOFDM0_XBTxAFE 0xc8c +#define rOFDM0_XCTxIQImbalance 0xc90 +#define rOFDM0_XCTxAFE 0xc94 +#define rOFDM0_XDTxIQImbalance 0xc98 +#define rOFDM0_XDTxAFE 0xc9c +#define rOFDM0_RxHPParameter 0xce0 +#define rOFDM0_TxPseudoNoiseWgt 0xce4 +#define rOFDM0_FrameSync 0xcf0 +#define rOFDM0_DFSReport 0xcf4 +#define rOFDM0_TxCoeff1 0xca4 +#define rOFDM0_TxCoeff2 0xca8 +#define rOFDM0_TxCoeff3 0xcac +#define rOFDM0_TxCoeff4 0xcb0 +#define rOFDM0_TxCoeff5 0xcb4 +#define rOFDM0_TxCoeff6 0xcb8 + + +//page d +#define rOFDM1_LSTF 0xd00 +#define rOFDM1_TRxPathEnable 0xd04 +#define rOFDM1_CFO 0xd08 +#define rOFDM1_CSI1 0xd10 +#define rOFDM1_SBD 0xd14 +#define rOFDM1_CSI2 0xd18 +#define rOFDM1_CFOTracking 0xd2c +#define rOFDM1_TRxMesaure1 0xd34 +#define rOFDM1_IntfDet 0xd3c +#define rOFDM1_PseudoNoiseStateAB 0xd50 +#define rOFDM1_PseudoNoiseStateCD 0xd54 +#define rOFDM1_RxPseudoNoiseWgt 0xd58 +#define rOFDM_PHYCounter1 0xda0 //cca, parity fail +#define rOFDM_PHYCounter2 0xda4 //rate illegal, crc8 fail +#define rOFDM_PHYCounter3 0xda8 //MCS not support +#define rOFDM_ShortCFOAB 0xdac +#define rOFDM_ShortCFOCD 0xdb0 +#define rOFDM_LongCFOAB 0xdb4 +#define rOFDM_LongCFOCD 0xdb8 +#define rOFDM_TailCFOAB 0xdbc +#define rOFDM_TailCFOCD 0xdc0 +#define rOFDM_PWMeasure1 0xdc4 +#define rOFDM_PWMeasure2 0xdc8 +#define rOFDM_BWReport 0xdcc +#define rOFDM_AGCReport 0xdd0 +#define rOFDM_RxSNR 0xdd4 +#define rOFDM_RxEVMCSI 0xdd8 +#define rOFDM_SIGReport 0xddc + +//page e +#define rTxAGC_Rate18_06 0xe00 +#define rTxAGC_Rate54_24 0xe04 +#define rTxAGC_CCK_Mcs32 0xe08 +#define rTxAGC_Mcs03_Mcs00 0xe10 +#define rTxAGC_Mcs07_Mcs04 0xe14 +#define rTxAGC_Mcs11_Mcs08 0xe18 +#define rTxAGC_Mcs15_Mcs12 0xe1c + + +//RF +//Zebra1 +#define rZebra1_HSSIEnable 0x0 +#define rZebra1_TRxEnable1 0x1 +#define rZebra1_TRxEnable2 0x2 +#define rZebra1_AGC 0x4 +#define rZebra1_ChargePump 0x5 +#define rZebra1_Channel 0x7 +#define rZebra1_TxGain 0x8 +#define rZebra1_TxLPF 0x9 +#define rZebra1_RxLPF 0xb +#define rZebra1_RxHPFCorner 0xc + +//Zebra4 +#define rGlobalCtrl 0 +#define rRTL8256_TxLPF 19 +#define rRTL8256_RxLPF 11 + +//RTL8258 +#define rRTL8258_TxLPF 0x11 +#define rRTL8258_RxLPF 0x13 +#define rRTL8258_RSSILPF 0xa + +//Bit Mask +//page-1 +#define bBBResetB 0x100 +#define bGlobalResetB 0x200 +#define bOFDMTxStart 0x4 +#define bCCKTxStart 0x8 +#define bCRC32Debug 0x100 +#define bPMACLoopback 0x10 +#define bTxLSIG 0xffffff +#define bOFDMTxRate 0xf +#define bOFDMTxReserved 0x10 +#define bOFDMTxLength 0x1ffe0 +#define bOFDMTxParity 0x20000 +#define bTxHTSIG1 0xffffff +#define bTxHTMCSRate 0x7f +#define bTxHTBW 0x80 +#define bTxHTLength 0xffff00 +#define bTxHTSIG2 0xffffff +#define bTxHTSmoothing 0x1 +#define bTxHTSounding 0x2 +#define bTxHTReserved 0x4 +#define bTxHTAggreation 0x8 +#define bTxHTSTBC 0x30 +#define bTxHTAdvanceCoding 0x40 +#define bTxHTShortGI 0x80 +#define bTxHTNumberHT_LTF 0x300 +#define bTxHTCRC8 0x3fc00 +#define bCounterReset 0x10000 +#define bNumOfOFDMTx 0xffff +#define bNumOfCCKTx 0xffff0000 +#define bTxIdleInterval 0xffff +#define bOFDMService 0xffff0000 +#define bTxMACHeader 0xffffffff +#define bTxDataInit 0xff +#define bTxHTMode 0x100 +#define bTxDataType 0x30000 +#define bTxRandomSeed 0xffffffff +#define bCCKTxPreamble 0x1 +#define bCCKTxSFD 0xffff0000 +#define bCCKTxSIG 0xff +#define bCCKTxService 0xff00 +#define bCCKLengthExt 0x8000 +#define bCCKTxLength 0xffff0000 +#define bCCKTxCRC16 0xffff +#define bCCKTxStatus 0x1 +#define bOFDMTxStatus 0x2 + +//page-8 +#define bRFMOD 0x1 +#define bJapanMode 0x2 +#define bCCKTxSC 0x30 +#define bCCKEn 0x1000000 +#define bOFDMEn 0x2000000 +#define bOFDMRxADCPhase 0x10000 +#define bOFDMTxDACPhase 0x40000 +#define bXATxAGC 0x3f +#define bXBTxAGC 0xf00 +#define bXCTxAGC 0xf000 +#define bXDTxAGC 0xf0000 +#define bPAStart 0xf0000000 +#define bTRStart 0x00f00000 +#define bRFStart 0x0000f000 +#define bBBStart 0x000000f0 +#define bBBCCKStart 0x0000000f +#define bPAEnd 0xf //Reg0x814 +#define bTREnd 0x0f000000 +#define bRFEnd 0x000f0000 +#define bCCAMask 0x000000f0 //T2R +#define bR2RCCAMask 0x00000f00 +#define bHSSI_R2TDelay 0xf8000000 +#define bHSSI_T2RDelay 0xf80000 +#define bContTxHSSI 0x400 //chane gain at continue Tx +#define bIGFromCCK 0x200 +#define bAGCAddress 0x3f +#define bRxHPTx 0x7000 +#define bRxHPT2R 0x38000 +#define bRxHPCCKIni 0xc0000 +#define bAGCTxCode 0xc00000 +#define bAGCRxCode 0x300000 +#define b3WireDataLength 0x800 +#define b3WireAddressLength 0x400 +#define b3WireRFPowerDown 0x1 +//#define bHWSISelect 0x8 +#define b5GPAPEPolarity 0x40000000 +#define b2GPAPEPolarity 0x80000000 +#define bRFSW_TxDefaultAnt 0x3 +#define bRFSW_TxOptionAnt 0x30 +#define bRFSW_RxDefaultAnt 0x300 +#define bRFSW_RxOptionAnt 0x3000 +#define bRFSI_3WireData 0x1 +#define bRFSI_3WireClock 0x2 +#define bRFSI_3WireLoad 0x4 +#define bRFSI_3WireRW 0x8 +#define bRFSI_3Wire 0xf //3-wire total control +#define bRFSI_RFENV 0x10 +#define bRFSI_TRSW 0x20 +#define bRFSI_TRSWB 0x40 +#define bRFSI_ANTSW 0x100 +#define bRFSI_ANTSWB 0x200 +#define bRFSI_PAPE 0x400 +#define bRFSI_PAPE5G 0x800 +#define bBandSelect 0x1 +#define bHTSIG2_GI 0x80 +#define bHTSIG2_Smoothing 0x01 +#define bHTSIG2_Sounding 0x02 +#define bHTSIG2_Aggreaton 0x08 +#define bHTSIG2_STBC 0x30 +#define bHTSIG2_AdvCoding 0x40 +#define bHTSIG2_NumOfHTLTF 0x300 +#define bHTSIG2_CRC8 0x3fc +#define bHTSIG1_MCS 0x7f +#define bHTSIG1_BandWidth 0x80 +#define bHTSIG1_HTLength 0xffff +#define bLSIG_Rate 0xf +#define bLSIG_Reserved 0x10 +#define bLSIG_Length 0x1fffe +#define bLSIG_Parity 0x20 +#define bCCKRxPhase 0x4 +#define bLSSIReadAddress 0x3f000000 //LSSI "Read" Address +#define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal +#define bLSSIReadBackData 0xfff +#define bLSSIReadOKFlag 0x1000 +#define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz + +#define bRegulator0Standby 0x1 +#define bRegulatorPLLStandby 0x2 +#define bRegulator1Standby 0x4 +#define bPLLPowerUp 0x8 +#define bDPLLPowerUp 0x10 +#define bDA10PowerUp 0x20 +#define bAD7PowerUp 0x200 +#define bDA6PowerUp 0x2000 +#define bXtalPowerUp 0x4000 +#define b40MDClkPowerUP 0x8000 +#define bDA6DebugMode 0x20000 +#define bDA6Swing 0x380000 +#define bADClkPhase 0x4000000 +#define b80MClkDelay 0x18000000 +#define bAFEWatchDogEnable 0x20000000 +#define bXtalCap 0x0f000000 +#define bIntDifClkEnable 0x400 +#define bExtSigClkEnable 0x800 +#define bBandgapMbiasPowerUp 0x10000 +#define bAD11SHGain 0xc0000 +#define bAD11InputRange 0x700000 +#define bAD11OPCurrent 0x3800000 +#define bIPathLoopback 0x4000000 +#define bQPathLoopback 0x8000000 +#define bAFELoopback 0x10000000 +#define bDA10Swing 0x7e0 +#define bDA10Reverse 0x800 +#define bDAClkSource 0x1000 +#define bAD7InputRange 0x6000 +#define bAD7Gain 0x38000 +#define bAD7OutputCMMode 0x40000 +#define bAD7InputCMMode 0x380000 +#define bAD7Current 0xc00000 +#define bRegulatorAdjust 0x7000000 +#define bAD11PowerUpAtTx 0x1 +#define bDA10PSAtTx 0x10 +#define bAD11PowerUpAtRx 0x100 +#define bDA10PSAtRx 0x1000 + +#define bCCKRxAGCFormat 0x200 + +#define bPSDFFTSamplepPoint 0xc000 +#define bPSDAverageNum 0x3000 +#define bIQPathControl 0xc00 +#define bPSDFreq 0x3ff +#define bPSDAntennaPath 0x30 +#define bPSDIQSwitch 0x40 +#define bPSDRxTrigger 0x400000 +#define bPSDTxTrigger 0x80000000 +#define bPSDSineToneScale 0x7f000000 +#define bPSDReport 0xffff + +//page-9 +#define bOFDMTxSC 0x30000000 +#define bCCKTxOn 0x1 +#define bOFDMTxOn 0x2 +#define bDebugPage 0xfff //reset debug page and also HWord, LWord +#define bDebugItem 0xff //reset debug page and LWord +#define bAntL 0x10 +#define bAntNonHT 0x100 +#define bAntHT1 0x1000 +#define bAntHT2 0x10000 +#define bAntHT1S1 0x100000 +#define bAntNonHTS1 0x1000000 + +//page-a +#define bCCKBBMode 0x3 +#define bCCKTxPowerSaving 0x80 +#define bCCKRxPowerSaving 0x40 +#define bCCKSideBand 0x10 +#define bCCKScramble 0x8 +#define bCCKAntDiversity 0x8000 +#define bCCKCarrierRecovery 0x4000 +#define bCCKTxRate 0x3000 +#define bCCKDCCancel 0x0800 +#define bCCKISICancel 0x0400 +#define bCCKMatchFilter 0x0200 +#define bCCKEqualizer 0x0100 +#define bCCKPreambleDetect 0x800000 +#define bCCKFastFalseCCA 0x400000 +#define bCCKChEstStart 0x300000 +#define bCCKCCACount 0x080000 +#define bCCKcs_lim 0x070000 +#define bCCKBistMode 0x80000000 +#define bCCKCCAMask 0x40000000 +#define bCCKTxDACPhase 0x4 +#define bCCKRxADCPhase 0x20000000 //r_rx_clk +#define bCCKr_cp_mode0 0x0100 +#define bCCKTxDCOffset 0xf0 +#define bCCKRxDCOffset 0xf +#define bCCKCCAMode 0xc000 +#define bCCKFalseCS_lim 0x3f00 +#define bCCKCS_ratio 0xc00000 +#define bCCKCorgBit_sel 0x300000 +#define bCCKPD_lim 0x0f0000 +#define bCCKNewCCA 0x80000000 +#define bCCKRxHPofIG 0x8000 +#define bCCKRxIG 0x7f00 +#define bCCKLNAPolarity 0x800000 +#define bCCKRx1stGain 0x7f0000 +#define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity +#define bCCKRxAGCSatLevel 0x1f000000 +#define bCCKRxAGCSatCount 0xe0 +#define bCCKRxRFSettle 0x1f //AGCsamp_dly +#define bCCKFixedRxAGC 0x8000 +//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824 +#define bCCKAntennaPolarity 0x2000 +#define bCCKTxFilterType 0x0c00 +#define bCCKRxAGCReportType 0x0300 +#define bCCKRxDAGCEn 0x80000000 +#define bCCKRxDAGCPeriod 0x20000000 +#define bCCKRxDAGCSatLevel 0x1f000000 +#define bCCKTimingRecovery 0x800000 +#define bCCKTxC0 0x3f0000 +#define bCCKTxC1 0x3f000000 +#define bCCKTxC2 0x3f +#define bCCKTxC3 0x3f00 +#define bCCKTxC4 0x3f0000 +#define bCCKTxC5 0x3f000000 +#define bCCKTxC6 0x3f +#define bCCKTxC7 0x3f00 +#define bCCKDebugPort 0xff0000 +#define bCCKDACDebug 0x0f000000 +#define bCCKFalseAlarmEnable 0x8000 +#define bCCKFalseAlarmRead 0x4000 +#define bCCKTRSSI 0x7f +#define bCCKRxAGCReport 0xfe +#define bCCKRxReport_AntSel 0x80000000 +#define bCCKRxReport_MFOff 0x40000000 +#define bCCKRxRxReport_SQLoss 0x20000000 +#define bCCKRxReport_Pktloss 0x10000000 +#define bCCKRxReport_Lockedbit 0x08000000 +#define bCCKRxReport_RateError 0x04000000 +#define bCCKRxReport_RxRate 0x03000000 +#define bCCKRxFACounterLower 0xff +#define bCCKRxFACounterUpper 0xff000000 +#define bCCKRxHPAGCStart 0xe000 +#define bCCKRxHPAGCFinal 0x1c00 + +#define bCCKRxFalseAlarmEnable 0x8000 +#define bCCKFACounterFreeze 0x4000 + +#define bCCKTxPathSel 0x10000000 +#define bCCKDefaultRxPath 0xc000000 +#define bCCKOptionRxPath 0x3000000 + +//page c +#define bNumOfSTF 0x3 +#define bShift_L 0xc0 +#define bGI_TH 0xc +#define bRxPathA 0x1 +#define bRxPathB 0x2 +#define bRxPathC 0x4 +#define bRxPathD 0x8 +#define bTxPathA 0x1 +#define bTxPathB 0x2 +#define bTxPathC 0x4 +#define bTxPathD 0x8 +#define bTRSSIFreq 0x200 +#define bADCBackoff 0x3000 +#define bDFIRBackoff 0xc000 +#define bTRSSILatchPhase 0x10000 +#define bRxIDCOffset 0xff +#define bRxQDCOffset 0xff00 +#define bRxDFIRMode 0x1800000 +#define bRxDCNFType 0xe000000 +#define bRXIQImb_A 0x3ff +#define bRXIQImb_B 0xfc00 +#define bRXIQImb_C 0x3f0000 +#define bRXIQImb_D 0xffc00000 +#define bDC_dc_Notch 0x60000 +#define bRxNBINotch 0x1f000000 +#define bPD_TH 0xf +#define bPD_TH_Opt2 0xc000 +#define bPWED_TH 0x700 +#define bIfMF_Win_L 0x800 +#define bPD_Option 0x1000 +#define bMF_Win_L 0xe000 +#define bBW_Search_L 0x30000 +#define bwin_enh_L 0xc0000 +#define bBW_TH 0x700000 +#define bED_TH2 0x3800000 +#define bBW_option 0x4000000 +#define bRatio_TH 0x18000000 +#define bWindow_L 0xe0000000 +#define bSBD_Option 0x1 +#define bFrame_TH 0x1c +#define bFS_Option 0x60 +#define bDC_Slope_check 0x80 +#define bFGuard_Counter_DC_L 0xe00 +#define bFrame_Weight_Short 0x7000 +#define bSub_Tune 0xe00000 +#define bFrame_DC_Length 0xe000000 +#define bSBD_start_offset 0x30000000 +#define bFrame_TH_2 0x7 +#define bFrame_GI2_TH 0x38 +#define bGI2_Sync_en 0x40 +#define bSarch_Short_Early 0x300 +#define bSarch_Short_Late 0xc00 +#define bSarch_GI2_Late 0x70000 +#define bCFOAntSum 0x1 +#define bCFOAcc 0x2 +#define bCFOStartOffset 0xc +#define bCFOLookBack 0x70 +#define bCFOSumWeight 0x80 +#define bDAGCEnable 0x10000 +#define bTXIQImb_A 0x3ff +#define bTXIQImb_B 0xfc00 +#define bTXIQImb_C 0x3f0000 +#define bTXIQImb_D 0xffc00000 +#define bTxIDCOffset 0xff +#define bTxQDCOffset 0xff00 +#define bTxDFIRMode 0x10000 +#define bTxPesudoNoiseOn 0x4000000 +#define bTxPesudoNoise_A 0xff +#define bTxPesudoNoise_B 0xff00 +#define bTxPesudoNoise_C 0xff0000 +#define bTxPesudoNoise_D 0xff000000 +#define bCCADropOption 0x20000 +#define bCCADropThres 0xfff00000 +#define bEDCCA_H 0xf +#define bEDCCA_L 0xf0 +#define bLambda_ED 0x300 +#define bRxInitialGain 0x7f +#define bRxAntDivEn 0x80 +#define bRxAGCAddressForLNA 0x7f00 +#define bRxHighPowerFlow 0x8000 +#define bRxAGCFreezeThres 0xc0000 +#define bRxFreezeStep_AGC1 0x300000 +#define bRxFreezeStep_AGC2 0xc00000 +#define bRxFreezeStep_AGC3 0x3000000 +#define bRxFreezeStep_AGC0 0xc000000 +#define bRxRssi_Cmp_En 0x10000000 +#define bRxQuickAGCEn 0x20000000 +#define bRxAGCFreezeThresMode 0x40000000 +#define bRxOverFlowCheckType 0x80000000 +#define bRxAGCShift 0x7f +#define bTRSW_Tri_Only 0x80 +#define bPowerThres 0x300 +#define bRxAGCEn 0x1 +#define bRxAGCTogetherEn 0x2 +#define bRxAGCMin 0x4 +#define bRxHP_Ini 0x7 +#define bRxHP_TRLNA 0x70 +#define bRxHP_RSSI 0x700 +#define bRxHP_BBP1 0x7000 +#define bRxHP_BBP2 0x70000 +#define bRxHP_BBP3 0x700000 +#define bRSSI_H 0x7f0000 //the threshold for high power +#define bRSSI_Gen 0x7f000000 //the threshold for ant diversity +#define bRxSettle_TRSW 0x7 +#define bRxSettle_LNA 0x38 +#define bRxSettle_RSSI 0x1c0 +#define bRxSettle_BBP 0xe00 +#define bRxSettle_RxHP 0x7000 +#define bRxSettle_AntSW_RSSI 0x38000 +#define bRxSettle_AntSW 0xc0000 +#define bRxProcessTime_DAGC 0x300000 +#define bRxSettle_HSSI 0x400000 +#define bRxProcessTime_BBPPW 0x800000 +#define bRxAntennaPowerShift 0x3000000 +#define bRSSITableSelect 0xc000000 +#define bRxHP_Final 0x7000000 +#define bRxHTSettle_BBP 0x7 +#define bRxHTSettle_HSSI 0x8 +#define bRxHTSettle_RxHP 0x70 +#define bRxHTSettle_BBPPW 0x80 +#define bRxHTSettle_Idle 0x300 +#define bRxHTSettle_Reserved 0x1c00 +#define bRxHTRxHPEn 0x8000 +#define bRxHTAGCFreezeThres 0x30000 +#define bRxHTAGCTogetherEn 0x40000 +#define bRxHTAGCMin 0x80000 +#define bRxHTAGCEn 0x100000 +#define bRxHTDAGCEn 0x200000 +#define bRxHTRxHP_BBP 0x1c00000 +#define bRxHTRxHP_Final 0xe0000000 +#define bRxPWRatioTH 0x3 +#define bRxPWRatioEn 0x4 +#define bRxMFHold 0x3800 +#define bRxPD_Delay_TH1 0x38 +#define bRxPD_Delay_TH2 0x1c0 +#define bRxPD_DC_COUNT_MAX 0x600 +//#define bRxMF_Hold 0x3800 +#define bRxPD_Delay_TH 0x8000 +#define bRxProcess_Delay 0xf0000 +#define bRxSearchrange_GI2_Early 0x700000 +#define bRxFrame_Guard_Counter_L 0x3800000 +#define bRxSGI_Guard_L 0xc000000 +#define bRxSGI_Search_L 0x30000000 +#define bRxSGI_TH 0xc0000000 +#define bDFSCnt0 0xff +#define bDFSCnt1 0xff00 +#define bDFSFlag 0xf0000 + +#define bMFWeightSum 0x300000 +#define bMinIdxTH 0x7f000000 + +#define bDAFormat 0x40000 + +#define bTxChEmuEnable 0x01000000 + +#define bTRSWIsolation_A 0x7f +#define bTRSWIsolation_B 0x7f00 +#define bTRSWIsolation_C 0x7f0000 +#define bTRSWIsolation_D 0x7f000000 + +#define bExtLNAGain 0x7c00 + +//page d +#define bSTBCEn 0x4 +#define bAntennaMapping 0x10 +#define bNss 0x20 +#define bCFOAntSumD 0x200 +#define bPHYCounterReset 0x8000000 +#define bCFOReportGet 0x4000000 +#define bOFDMContinueTx 0x10000000 +#define bOFDMSingleCarrier 0x20000000 +#define bOFDMSingleTone 0x40000000 +//#define bRxPath1 0x01 +//#define bRxPath2 0x02 +//#define bRxPath3 0x04 +//#define bRxPath4 0x08 +//#define bTxPath1 0x10 +//#define bTxPath2 0x20 +#define bHTDetect 0x100 +#define bCFOEn 0x10000 +#define bCFOValue 0xfff00000 +#define bSigTone_Re 0x3f +#define bSigTone_Im 0x7f00 +#define bCounter_CCA 0xffff +#define bCounter_ParityFail 0xffff0000 +#define bCounter_RateIllegal 0xffff +#define bCounter_CRC8Fail 0xffff0000 +#define bCounter_MCSNoSupport 0xffff +#define bCounter_FastSync 0xffff +#define bShortCFO 0xfff +#define bShortCFOTLength 12 //total +#define bShortCFOFLength 11 //fraction +#define bLongCFO 0x7ff +#define bLongCFOTLength 11 +#define bLongCFOFLength 11 +#define bTailCFO 0x1fff +#define bTailCFOTLength 13 +#define bTailCFOFLength 12 + +#define bmax_en_pwdB 0xffff +#define bCC_power_dB 0xffff0000 +#define bnoise_pwdB 0xffff +#define bPowerMeasTLength 10 +#define bPowerMeasFLength 3 +#define bRx_HT_BW 0x1 +#define bRxSC 0x6 +#define bRx_HT 0x8 + +#define bNB_intf_det_on 0x1 +#define bIntf_win_len_cfg 0x30 +#define bNB_Intf_TH_cfg 0x1c0 + +#define bRFGain 0x3f +#define bTableSel 0x40 +#define bTRSW 0x80 + +#define bRxSNR_A 0xff +#define bRxSNR_B 0xff00 +#define bRxSNR_C 0xff0000 +#define bRxSNR_D 0xff000000 +#define bSNREVMTLength 8 +#define bSNREVMFLength 1 + +#define bCSI1st 0xff +#define bCSI2nd 0xff00 +#define bRxEVM1st 0xff0000 +#define bRxEVM2nd 0xff000000 + +#define bSIGEVM 0xff +#define bPWDB 0xff00 +#define bSGIEN 0x10000 + +#define bSFactorQAM1 0xf +#define bSFactorQAM2 0xf0 +#define bSFactorQAM3 0xf00 +#define bSFactorQAM4 0xf000 +#define bSFactorQAM5 0xf0000 +#define bSFactorQAM6 0xf0000 +#define bSFactorQAM7 0xf00000 +#define bSFactorQAM8 0xf000000 +#define bSFactorQAM9 0xf0000000 +#define bCSIScheme 0x100000 + +#define bNoiseLvlTopSet 0x3 +#define bChSmooth 0x4 +#define bChSmoothCfg1 0x38 +#define bChSmoothCfg2 0x1c0 +#define bChSmoothCfg3 0xe00 +#define bChSmoothCfg4 0x7000 +#define bMRCMode 0x800000 +#define bTHEVMCfg 0x7000000 + +#define bLoopFitType 0x1 +#define bUpdCFO 0x40 +#define bUpdCFOOffData 0x80 +#define bAdvUpdCFO 0x100 +#define bAdvTimeCtrl 0x800 +#define bUpdClko 0x1000 +#define bFC 0x6000 +#define bTrackingMode 0x8000 +#define bPhCmpEnable 0x10000 +#define bUpdClkoLTF 0x20000 +#define bComChCFO 0x40000 +#define bCSIEstiMode 0x80000 +#define bAdvUpdEqz 0x100000 +#define bUChCfg 0x7000000 +#define bUpdEqz 0x8000000 + +//page e +#define bTxAGCRate18_06 0x7f7f7f7f +#define bTxAGCRate54_24 0x7f7f7f7f +#define bTxAGCRateMCS32 0x7f +#define bTxAGCRateCCK 0x7f00 +#define bTxAGCRateMCS3_MCS0 0x7f7f7f7f +#define bTxAGCRateMCS7_MCS4 0x7f7f7f7f +#define bTxAGCRateMCS11_MCS8 0x7f7f7f7f +#define bTxAGCRateMCS15_MCS12 0x7f7f7f7f + + +//Rx Pseduo noise +#define bRxPesudoNoiseOn 0x20000000 +#define bRxPesudoNoise_A 0xff +#define bRxPesudoNoise_B 0xff00 +#define bRxPesudoNoise_C 0xff0000 +#define bRxPesudoNoise_D 0xff000000 +#define bPesudoNoiseState_A 0xffff +#define bPesudoNoiseState_B 0xffff0000 +#define bPesudoNoiseState_C 0xffff +#define bPesudoNoiseState_D 0xffff0000 + +//RF +//Zebra1 +#define bZebra1_HSSIEnable 0x8 +#define bZebra1_TRxControl 0xc00 +#define bZebra1_TRxGainSetting 0x07f +#define bZebra1_RxCorner 0xc00 +#define bZebra1_TxChargePump 0x38 +#define bZebra1_RxChargePump 0x7 +#define bZebra1_ChannelNum 0xf80 +#define bZebra1_TxLPFBW 0x400 +#define bZebra1_RxLPFBW 0x600 + +//Zebra4 +#define bRTL8256RegModeCtrl1 0x100 +#define bRTL8256RegModeCtrl0 0x40 +#define bRTL8256_TxLPFBW 0x18 +#define bRTL8256_RxLPFBW 0x600 + +//RTL8258 +#define bRTL8258_TxLPFBW 0xc +#define bRTL8258_RxLPFBW 0xc00 +#define bRTL8258_RSSILPFBW 0xc0 + +//byte endable for sb_write +#define bByte0 0x1 +#define bByte1 0x2 +#define bByte2 0x4 +#define bByte3 0x8 +#define bWord0 0x3 +#define bWord1 0xc +#define bDWord 0xf + +//for PutRegsetting & GetRegSetting BitMask +#define bMaskByte0 0xff +#define bMaskByte1 0xff00 +#define bMaskByte2 0xff0000 +#define bMaskByte3 0xff000000 +#define bMaskHWord 0xffff0000 +#define bMaskLWord 0x0000ffff +#define bMaskDWord 0xffffffff + +//for PutRFRegsetting & GetRFRegSetting BitMask +#define bMask12Bits 0xfff + +#define bEnable 0x1 +#define bDisable 0x0 + +#define LeftAntenna 0x0 +#define RightAntenna 0x1 + +#define tCheckTxStatus 500 //500ms +#define tUpdateRxCounter 100 //100ms + +#define rateCCK 0 +#define rateOFDM 1 +#define rateHT 2 + +//define Register-End +#define bPMAC_End 0x1ff +#define bFPGAPHY0_End 0x8ff +#define bFPGAPHY1_End 0x9ff +#define bCCKPHY0_End 0xaff +#define bOFDMPHY0_End 0xcff +#define bOFDMPHY1_End 0xdff + +//define max debug item in each debug page +//#define bMaxItem_FPGA_PHY0 0x9 +//#define bMaxItem_FPGA_PHY1 0x3 +//#define bMaxItem_PHY_11B 0x16 +//#define bMaxItem_OFDM_PHY0 0x29 +//#define bMaxItem_OFDM_PHY1 0x0 + +#define bPMACControl 0x0 +#define bWMACControl 0x1 +#define bWNICControl 0x2 + +#define PathA 0x0 +#define PathB 0x1 +#define PathC 0x2 +#define PathD 0x3 + +#define rRTL8256RxMixerPole 0xb +#define bZebraRxMixerPole 0x6 +#define rRTL8256TxBBOPBias 0x9 +#define bRTL8256TxBBOPBias 0x400 +#define rRTL8256TxBBBW 19 +#define bRTL8256TxBBBW 0x18 + +#endif //__INC_HAL8190PCIPHYREG_H |