diff options
| author |   Aric Cyr <aric.cyr@amd.com> | 2019-04-22 17:45:11 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2019-06-22 09:34:11 -0500 |
| commit | 6bd8d7d3f75be1c327f3fd63e6f03ca68faffb33 (patch) | |
| tree | 16be276e45b389ef84a20669e77291d95fe98bff /drivers | |
| parent | drm/amd/display: Add support for extended DSC DPCD caps (diff) | |
| download | linux-dev-6bd8d7d3f75be1c327f3fd63e6f03ca68faffb33.tar.xz linux-dev-6bd8d7d3f75be1c327f3fd63e6f03ca68faffb33.zip | |
drm/amd/display: Intermittent DCN2 pipe hang on mode change
[Why]
GSL is being used to synchronize pipes when vsync is off but
on transition to vsync on during a mode change GSL is not
being reset correctly.
[How]
Disable GSL on any plane that is disabled.
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 15 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h | 2 |
2 files changed, 12 insertions, 5 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c index f9eae47f7be3..c7ae538611f7 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c @@ -467,6 +467,14 @@ static void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx); + /* In flip immediate with pipe splitting case GSL is used for + * synchronization so we must disable it when the plane is disabled. + */ + if (pipe_ctx->stream_res.gsl_group != 0) + dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false); + + dc->hwss.set_flip_control_gsl(pipe_ctx, false); + hubp->funcs->hubp_clk_cntl(hubp, false); dpp->funcs->dpp_dppclk_control(dpp, false, false); @@ -1900,14 +1908,14 @@ static int find_free_gsl_group(const struct dc *dc) void dcn20_setup_gsl_group_as_lock( const struct dc *dc, struct pipe_ctx *pipe_ctx, - bool flip_immediate) + bool enable) { struct gsl_params gsl; int group_idx; memset(&gsl, 0, sizeof(struct gsl_params)); - if (flip_immediate) { + if (enable) { /* return if group already assigned since GSL was set up * for vsync flip, we would unassign so it can't be "left over" */ @@ -1973,8 +1981,7 @@ void dcn20_setup_gsl_group_as_lock( &gsl); pipe_ctx->stream_res.tg->funcs->set_gsl_source_select( - pipe_ctx->stream_res.tg, group_idx, - flip_immediate ? 4 : 0); + pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0); } else BREAK_TO_DEBUGGER(); } diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h index 37699df685ee..b7892e8f4518 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h @@ -86,6 +86,6 @@ void dcn20_setup_vupdate_interrupt(struct pipe_ctx *pipe_ctx); void dcn20_setup_gsl_group_as_lock(const struct dc *dc, struct pipe_ctx *pipe_ctx, - bool flip_immediate); + bool enable); #endif /* __DC_HWSS_DCN20_H__ */ |