diff options
| author |   Daniel Vetter <daniel.vetter@ffwll.ch> | 2016-12-06 10:26:30 +0100 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2016-12-06 10:26:48 +0100 |
| commit | 75e75cbd55183ff12459666c0a1d3e71fe1481ab (patch) | |
| tree | a1dc32cc055770736397f9cf9b68f9e176184943 /drivers | |
| parent | drm/amdgpu: don't add files at control minor debugfs directory (diff) | |
| parent | Merge branch 'exynos-drm-next' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-next (diff) | |
| download | linux-dev-75e75cbd55183ff12459666c0a1d3e71fe1481ab.tar.xz linux-dev-75e75cbd55183ff12459666c0a1d3e71fe1481ab.zip | |
Merge remote-tracking branch 'airlied/drm-next' into drm-misc-next
Backmerge v4.9-rc8 to get at
commit e94bd1736f1f60e916a85a80c0b0ebeaae36cce5
Author: Michel Dänzer <michel.daenzer@amd.com>
Date: Wed Nov 30 17:30:01 2016 +0900
drm: Don't call drm_for_each_crtc with a non-KMS driver
so I can apply Michel's follow-up patch.
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Diffstat (limited to 'drivers')
694 files changed, 73308 insertions, 8906 deletions
diff --git a/drivers/acpi/acpi_apd.c b/drivers/acpi/acpi_apd.c index d58fbf7f04e6..7dd70927991e 100644 --- a/drivers/acpi/acpi_apd.c +++ b/drivers/acpi/acpi_apd.c @@ -122,7 +122,7 @@ static int acpi_apd_create_device(struct acpi_device *adev, int ret; if (!dev_desc) { - pdev = acpi_create_platform_device(adev); + pdev = acpi_create_platform_device(adev, NULL); return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1; } @@ -139,14 +139,8 @@ static int acpi_apd_create_device(struct acpi_device *adev, goto err_out; } - if (dev_desc->properties) { - ret = device_add_properties(&adev->dev, dev_desc->properties); - if (ret) - goto err_out; - } - adev->driver_data = pdata; - pdev = acpi_create_platform_device(adev); + pdev = acpi_create_platform_device(adev, dev_desc->properties); if (!IS_ERR_OR_NULL(pdev)) return 1; diff --git a/drivers/acpi/acpi_lpss.c b/drivers/acpi/acpi_lpss.c index 552010288135..373657f7e35a 100644 --- a/drivers/acpi/acpi_lpss.c +++ b/drivers/acpi/acpi_lpss.c @@ -395,7 +395,7 @@ static int acpi_lpss_create_device(struct acpi_device *adev, dev_desc = (const struct lpss_device_desc *)id->driver_data; if (!dev_desc) { - pdev = acpi_create_platform_device(adev); + pdev = acpi_create_platform_device(adev, NULL); return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1; } pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); @@ -451,14 +451,8 @@ static int acpi_lpss_create_device(struct acpi_device *adev, goto err_out; } - if (dev_desc->properties) { - ret = device_add_properties(&adev->dev, dev_desc->properties); - if (ret) - goto err_out; - } - adev->driver_data = pdata; - pdev = acpi_create_platform_device(adev); + pdev = acpi_create_platform_device(adev, dev_desc->properties); if (!IS_ERR_OR_NULL(pdev)) { return 1; } diff --git a/drivers/acpi/acpi_platform.c b/drivers/acpi/acpi_platform.c index b200ae1f3c6f..b4c1a6a51da4 100644 --- a/drivers/acpi/acpi_platform.c +++ b/drivers/acpi/acpi_platform.c @@ -50,6 +50,7 @@ static void acpi_platform_fill_resource(struct acpi_device *adev, /** * acpi_create_platform_device - Create platform device for ACPI device node * @adev: ACPI device node to create a platform device for. + * @properties: Optional collection of build-in properties. * * Check if the given @adev can be represented as a platform device and, if * that's the case, create and register a platform device, populate its common @@ -57,7 +58,8 @@ static void acpi_platform_fill_resource(struct acpi_device *adev, * * Name of the platform device will be the same as @adev's. */ -struct platform_device *acpi_create_platform_device(struct acpi_device *adev) +struct platform_device *acpi_create_platform_device(struct acpi_device *adev, + struct property_entry *properties) { struct platform_device *pdev = NULL; struct platform_device_info pdevinfo; @@ -106,6 +108,7 @@ struct platform_device *acpi_create_platform_device(struct acpi_device *adev) pdevinfo.res = resources; pdevinfo.num_res = count; pdevinfo.fwnode = acpi_fwnode_handle(adev); + pdevinfo.properties = properties; if (acpi_dma_supported(adev)) pdevinfo.dma_mask = DMA_BIT_MASK(32); diff --git a/drivers/acpi/acpica/tbfadt.c b/drivers/acpi/acpica/tbfadt.c index 046c4d0394ee..5fb838e592dc 100644 --- a/drivers/acpi/acpica/tbfadt.c +++ b/drivers/acpi/acpica/tbfadt.c @@ -480,19 +480,17 @@ static void acpi_tb_convert_fadt(void) u32 i; /* - * For ACPI 1.0 FADTs (revision 1), ensure that reserved fields which + * For ACPI 1.0 FADTs (revision 1 or 2), ensure that reserved fields which * should be zero are indeed zero. This will workaround BIOSs that * inadvertently place values in these fields. * * The ACPI 1.0 reserved fields that will be zeroed are the bytes located * at offset 45, 55, 95, and the word located at offset 109, 110. * - * Note: The FADT revision value is unreliable because of BIOS errors. - * The table length is instead used as the final word on the version. - * - * Note: FADT revision 3 is the ACPI 2.0 version of the FADT. + * Note: The FADT revision value is unreliable. Only the length can be + * trusted. */ - if (acpi_gbl_FADT.header.length <= ACPI_FADT_V3_SIZE) { + if (acpi_gbl_FADT.header.length <= ACPI_FADT_V2_SIZE) { acpi_gbl_FADT.preferred_profile = 0; acpi_gbl_FADT.pstate_control = 0; acpi_gbl_FADT.cst_control = 0; diff --git a/drivers/acpi/dptf/int340x_thermal.c b/drivers/acpi/dptf/int340x_thermal.c index 33505c651f62..86364097e236 100644 --- a/drivers/acpi/dptf/int340x_thermal.c +++ b/drivers/acpi/dptf/int340x_thermal.c @@ -34,11 +34,11 @@ static int int340x_thermal_handler_attach(struct acpi_device *adev, const struct acpi_device_id *id) { if (IS_ENABLED(CONFIG_INT340X_THERMAL)) - acpi_create_platform_device(adev); + acpi_create_platform_device(adev, NULL); /* Intel SoC DTS thermal driver needs INT3401 to set IRQ descriptor */ else if (IS_ENABLED(CONFIG_INTEL_SOC_DTS_THERMAL) && id->driver_data == INT3401_DEVICE) - acpi_create_platform_device(adev); + acpi_create_platform_device(adev, NULL); return 1; } diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c index 035ac646d8db..3d1856f1f4d0 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c @@ -1734,7 +1734,7 @@ static void acpi_default_enumeration(struct acpi_device *device) &is_spi_i2c_slave); acpi_dev_free_resource_list(&resource_list); if (!is_spi_i2c_slave) { - acpi_create_platform_device(device); + acpi_create_platform_device(device, NULL); acpi_device_set_enumerated(device); } else { blocking_notifier_call_chain(&acpi_reconfig_chain, diff --git a/drivers/acpi/sleep.c b/drivers/acpi/sleep.c index deb0ff78eba8..54abb26b7366 100644 --- a/drivers/acpi/sleep.c +++ b/drivers/acpi/sleep.c @@ -47,32 +47,15 @@ static void acpi_sleep_tts_switch(u32 acpi_state) } } -static void acpi_sleep_pts_switch(u32 acpi_state) -{ - acpi_status status; - - status = acpi_execute_simple_method(NULL, "\\_PTS", acpi_state); - if (ACPI_FAILURE(status) && status != AE_NOT_FOUND) { - /* - * OS can't evaluate the _PTS object correctly. Some warning - * message will be printed. But it won't break anything. - */ - printk(KERN_NOTICE "Failure in evaluating _PTS object\n"); - } -} - -static int sleep_notify_reboot(struct notifier_block *this, +static int tts_notify_reboot(struct notifier_block *this, unsigned long code, void *x) { acpi_sleep_tts_switch(ACPI_STATE_S5); - - acpi_sleep_pts_switch(ACPI_STATE_S5); - return NOTIFY_DONE; } -static struct notifier_block sleep_notifier = { - .notifier_call = sleep_notify_reboot, +static struct notifier_block tts_notifier = { + .notifier_call = tts_notify_reboot, .next = NULL, .priority = 0, }; @@ -916,9 +899,9 @@ int __init acpi_sleep_init(void) pr_info(PREFIX "(supports%s)\n", supported); /* - * Register the sleep_notifier to reboot notifier list so that the _TTS - * and _PTS object can also be evaluated when the system enters S5. + * Register the tts_notifier to reboot notifier list so that the _TTS + * object can also be evaluated when the system enters S5. */ - register_reboot_notifier(&sleep_notifier); + register_reboot_notifier(&tts_notifier); return 0; } diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index 9669fc7c19df..74f4c662f776 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c @@ -1436,13 +1436,6 @@ static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports, "ahci: MRSM is on, fallback to single MSI\n"); pci_free_irq_vectors(pdev); } - - /* - * -ENOSPC indicated we don't have enough vectors. Don't bother - * trying a single vectors for any other error: - */ - if (nvec < 0 && nvec != -ENOSPC) - return nvec; } /* diff --git a/drivers/ata/libata-scsi.c b/drivers/ata/libata-scsi.c index 9cceb4a875a5..c4eb4ae9c3aa 100644 --- a/drivers/ata/libata-scsi.c +++ b/drivers/ata/libata-scsi.c @@ -1088,7 +1088,7 @@ static void ata_gen_passthru_sense(struct ata_queued_cmd *qc) desc[1] = tf->command; /* status */ desc[2] = tf->device; desc[3] = tf->nsect; - desc[0] = 0; + desc[7] = 0; if (tf->flags & ATA_TFLAG_LBA48) { desc[8] |= 0x80; if (tf->hob_nsect) diff --git a/drivers/base/dd.c b/drivers/base/dd.c index d22a7260f42b..d76cd97a98b6 100644 --- a/drivers/base/dd.c +++ b/drivers/base/dd.c @@ -324,7 +324,8 @@ static int really_probe(struct device *dev, struct device_driver *drv) { int ret = -EPROBE_DEFER; int local_trigger_count = atomic_read(&deferred_trigger_count); - bool test_remove = IS_ENABLED(CONFIG_DEBUG_TEST_DRIVER_REMOVE); + bool test_remove = IS_ENABLED(CONFIG_DEBUG_TEST_DRIVER_REMOVE) && + !drv->suppress_bind_attrs; if (defer_all_probes) { /* @@ -383,7 +384,7 @@ re_probe: if (test_remove) { test_remove = false; - if (dev->bus && dev->bus->remove) + if (dev->bus->remove) dev->bus->remove(dev); else if (drv->remove) drv->remove(dev); diff --git a/drivers/base/power/main.c b/drivers/base/power/main.c index e44944f4be77..2932a5bd892f 100644 --- a/drivers/base/power/main.c +++ b/drivers/base/power/main.c @@ -1027,6 +1027,8 @@ static int __device_suspend_noirq(struct device *dev, pm_message_t state, bool a TRACE_DEVICE(dev); TRACE_SUSPEND(0); + dpm_wait_for_children(dev, async); + if (async_error) goto Complete; @@ -1038,8 +1040,6 @@ static int __device_suspend_noirq(struct device *dev, pm_message_t state, bool a if (dev->power.syscore || dev->power.direct_complete) goto Complete; - dpm_wait_for_children(dev, async); - if (dev->pm_domain) { info = "noirq power domain "; callback = pm_noirq_op(&dev->pm_domain->ops, state); @@ -1174,6 +1174,8 @@ static int __device_suspend_late(struct device *dev, pm_message_t state, bool as __pm_runtime_disable(dev, false); + dpm_wait_for_children(dev, async); + if (async_error) goto Complete; @@ -1185,8 +1187,6 @@ static int __device_suspend_late(struct device *dev, pm_message_t state, bool as if (dev->power.syscore || dev->power.direct_complete) goto Complete; - dpm_wait_for_children(dev, async); - if (dev->pm_domain) { info = "late power domain "; callback = pm_late_early_op(&dev->pm_domain->ops, state); diff --git a/drivers/block/aoe/aoecmd.c b/drivers/block/aoe/aoecmd.c index ab19adb07a12..3c606c09fd5a 100644 --- a/drivers/block/aoe/aoecmd.c +++ b/drivers/block/aoe/aoecmd.c @@ -853,45 +853,6 @@ rqbiocnt(struct request *r) return n; } -/* This can be removed if we are certain that no users of the block - * layer will ever use zero-count pages in bios. Otherwise we have to - * protect against the put_page sometimes done by the network layer. - * - * See http://oss.sgi.com/archives/xfs/2007-01/msg00594.html for - * discussion. - * - * We cannot use get_page in the workaround, because it insists on a - * positive page count as a precondition. So we use _refcount directly. - */ -static void -bio_pageinc(struct bio *bio) -{ - struct bio_vec bv; - struct page *page; - struct bvec_iter iter; - - bio_for_each_segment(bv, bio, iter) { - /* Non-zero page count for non-head members of - * compound pages is no longer allowed by the kernel. - */ - page = compound_head(bv.bv_page); - page_ref_inc(page); - } -} - -static void -bio_pagedec(struct bio *bio) -{ - struct page *page; - struct bio_vec bv; - struct bvec_iter iter; - - bio_for_each_segment(bv, bio, iter) { - page = compound_head(bv.bv_page); - page_ref_dec(page); - } -} - static void bufinit(struct buf *buf, struct request *rq, struct bio *bio) { @@ -899,7 +860,6 @@ bufinit(struct buf *buf, struct request *rq, struct bio *bio) buf->rq = rq; buf->bio = bio; buf->iter = bio->bi_iter; - bio_pageinc(bio); } static struct buf * @@ -1127,7 +1087,6 @@ aoe_end_buf(struct aoedev *d, struct buf *buf) if (buf == d->ip.buf) d->ip.buf = NULL; rq = buf->rq; - bio_pagedec(buf->bio); mempool_free(buf, d->bufpool); n = (unsigned long) rq->special; rq->special = (void *) --n; diff --git a/drivers/block/drbd/drbd_main.c b/drivers/block/drbd/drbd_main.c index 100be556e613..83482721bc01 100644 --- a/drivers/block/drbd/drbd_main.c +++ b/drivers/block/drbd/drbd_main.c @@ -1871,7 +1871,7 @@ int drbd_send(struct drbd_connection *connection, struct socket *sock, drbd_update_congested(connection); } do { - rv = kernel_sendmsg(sock, &msg, &iov, 1, size); + rv = kernel_sendmsg(sock, &msg, &iov, 1, iov.iov_len); if (rv == -EAGAIN) { if (we_should_drop_the_connection(connection, sock)) break; diff --git a/drivers/block/nbd.c b/drivers/block/nbd.c index 19a16b2dbb91..7a1048755914 100644 --- a/drivers/block/nbd.c +++ b/drivers/block/nbd.c @@ -599,7 +599,7 @@ static int __nbd_ioctl(struct block_device *bdev, struct nbd_device *nbd, return -EINVAL; sreq = blk_mq_alloc_request(bdev_get_queue(bdev), WRITE, 0); - if (!sreq) + if (IS_ERR(sreq)) return -ENOMEM; mutex_unlock(&nbd->tx_lock); diff --git a/drivers/block/zram/zram_drv.c b/drivers/block/zram/zram_drv.c index 04365b17ee67..5163c8f918cb 100644 --- a/drivers/block/zram/zram_drv.c +++ b/drivers/block/zram/zram_drv.c @@ -1403,7 +1403,8 @@ static ssize_t hot_remove_store(struct class *class, zram = idr_find(&zram_index_idr, dev_id); if (zram) { ret = zram_remove(zram); - idr_remove(&zram_index_idr, dev_id); + if (!ret) + idr_remove(&zram_index_idr, dev_id); } else { ret = -ENODEV; } diff --git a/drivers/char/ipmi/bt-bmc.c b/drivers/char/ipmi/bt-bmc.c index b49e61320952..fc9e8891eae3 100644 --- a/drivers/char/ipmi/bt-bmc.c +++ b/drivers/char/ipmi/bt-bmc.c @@ -484,7 +484,7 @@ static int bt_bmc_remove(struct platform_device *pdev) } static const struct of_device_id bt_bmc_match[] = { - { .compatible = "aspeed,ast2400-bt-bmc" }, + { .compatible = "aspeed,ast2400-ibt-bmc" }, { }, }; @@ -502,4 +502,4 @@ module_platform_driver(bt_bmc_driver); MODULE_DEVICE_TABLE(of, bt_bmc_match); MODULE_LICENSE("GPL"); MODULE_AUTHOR("Alistair Popple <alistair@popple.id.au>"); -MODULE_DESCRIPTION("Linux device interface to the BT interface"); +MODULE_DESCRIPTION("Linux device interface to the IPMI BT interface"); diff --git a/drivers/char/ppdev.c b/drivers/char/ppdev.c index d23368874710..6af1ce04b3da 100644 --- a/drivers/char/ppdev.c +++ b/drivers/char/ppdev.c @@ -748,10 +748,7 @@ static int pp_release(struct inode *inode, struct file *file) } if (pp->pdev) { - const char *name = pp->pdev->name; - parport_unregister_device(pp->pdev); - kfree(name); pp->pdev = NULL; pr_debug(CHRDEV "%x: unregistered pardevice\n", minor); } diff --git a/drivers/clk/bcm/Kconfig b/drivers/clk/bcm/Kconfig index f21e9b7afd1a..e3eed5a78404 100644 --- a/drivers/clk/bcm/Kconfig +++ b/drivers/clk/bcm/Kconfig @@ -20,7 +20,7 @@ config CLK_BCM_KONA config COMMON_CLK_IPROC bool "Broadcom iProc clock support" - depends on ARCH_BCM_IPROC || COMPILE_TEST + depends on ARCH_BCM_IPROC || ARCH_BCM_63XX || COMPILE_TEST depends on COMMON_CLK default ARCH_BCM_IPROC help diff --git a/drivers/clk/berlin/bg2.c b/drivers/clk/berlin/bg2.c index edf3b96b3b73..1d99292e2039 100644 --- a/drivers/clk/berlin/bg2.c +++ b/drivers/clk/berlin/bg2.c @@ -685,7 +685,7 @@ static void __init berlin2_clock_setup(struct device_node *np) } /* register clk-provider */ - of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data); + of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data); return; diff --git a/drivers/clk/berlin/bg2q.c b/drivers/clk/berlin/bg2q.c index 0718e831475f..3b784b593afd 100644 --- a/drivers/clk/berlin/bg2q.c +++ b/drivers/clk/berlin/bg2q.c @@ -382,7 +382,7 @@ static void __init berlin2q_clock_setup(struct device_node *np) } /* register clk-provider */ - of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data); + of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data); return; diff --git a/drivers/clk/clk-efm32gg.c b/drivers/clk/clk-efm32gg.c index 8802a2dd56ac..f674778fb3ac 100644 --- a/drivers/clk/clk-efm32gg.c +++ b/drivers/clk/clk-efm32gg.c @@ -82,6 +82,6 @@ static void __init efm32gg_cmu_init(struct device_node *np) hws[clk_HFPERCLKDAC0] = clk_hw_register_gate(NULL, "HFPERCLK.DAC0", "HFXO", 0, base + CMU_HFPERCLKEN0, 17, 0, NULL); - of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data); + of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data); } CLK_OF_DECLARE(efm32ggcmu, "efm32gg,cmu", efm32gg_cmu_init); diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c index 20b105584f82..80ae2a51452d 100644 --- a/drivers/clk/clk-qoriq.c +++ b/drivers/clk/clk-qoriq.c @@ -700,6 +700,7 @@ static struct clk * __init create_mux_common(struct clockgen *cg, struct mux_hwclock *hwc, const struct clk_ops *ops, unsigned long min_rate, + unsigned long max_rate, unsigned long pct80_rate, const char *fmt, int idx) { @@ -728,6 +729,8 @@ static struct clk * __init create_mux_common(struct clockgen *cg, continue; if (rate < min_rate) continue; + if (rate > max_rate) + continue; parent_names[j] = div->name; hwc->parent_to_clksel[j] = i; @@ -759,7 +762,7 @@ static struct clk * __init create_one_cmux(struct clockgen *cg, int idx) struct mux_hwclock *hwc; const struct clockgen_pll_div *div; unsigned long plat_rate, min_rate; - u64 pct80_rate; + u64 max_rate, pct80_rate; u32 clksel; hwc = kzalloc(sizeof(*hwc), GFP_KERNEL); @@ -787,8 +790,8 @@ static struct clk * __init create_one_cmux(struct clockgen *cg, int idx) return NULL; } - pct80_rate = clk_get_rate(div->clk); - pct80_rate *= 8; + max_rate = clk_get_rate(div->clk); + pct80_rate = max_rate * 8; do_div(pct80_rate, 10); plat_rate = clk_get_rate(cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk); @@ -798,7 +801,7 @@ static struct clk * __init create_one_cmux(struct clockgen *cg, int idx) else min_rate = plat_rate / 2; - return create_mux_common(cg, hwc, &cmux_ops, min_rate, + return create_mux_common(cg, hwc, &cmux_ops, min_rate, max_rate, pct80_rate, "cg-cmux%d", idx); } @@ -813,7 +816,7 @@ static struct clk * __init create_one_hwaccel(struct clockgen *cg, int idx) hwc->reg = cg->regs + 0x20 * idx + 0x10; hwc->info = cg->info.hwaccel[idx]; - return create_mux_common(cg, hwc, &hwaccel_ops, 0, 0, + return create_mux_common(cg, hwc, &hwaccel_ops, 0, ULONG_MAX, 0, "cg-hwaccel%d", idx); } diff --git a/drivers/clk/clk-xgene.c b/drivers/clk/clk-xgene.c index 5daddf5ecc4b..bc37030e38ba 100644 --- a/drivers/clk/clk-xgene.c +++ b/drivers/clk/clk-xgene.c @@ -463,22 +463,20 @@ static int xgene_clk_enable(struct clk_hw *hw) struct xgene_clk *pclk = to_xgene_clk(hw); unsigned long flags = 0; u32 data; - phys_addr_t reg; if (pclk->lock) spin_lock_irqsave(pclk->lock, flags); if (pclk->param.csr_reg != NULL) { pr_debug("%s clock enabled\n", clk_hw_get_name(hw)); - reg = __pa(pclk->param.csr_reg); /* First enable the clock */ data = xgene_clk_read(pclk->param.csr_reg + pclk->param.reg_clk_offset); data |= pclk->param.reg_clk_mask; xgene_clk_write(data, pclk->param.csr_reg + pclk->param.reg_clk_offset); - pr_debug("%s clock PADDR base %pa clk offset 0x%08X mask 0x%08X value 0x%08X\n", - clk_hw_get_name(hw), ®, + pr_debug("%s clk offset 0x%08X mask 0x%08X value 0x%08X\n", + clk_hw_get_name(hw), pclk->param.reg_clk_offset, pclk->param.reg_clk_mask, data); @@ -488,8 +486,8 @@ static int xgene_clk_enable(struct clk_hw *hw) data &= ~pclk->param.reg_csr_mask; xgene_clk_write(data, pclk->param.csr_reg + pclk->param.reg_csr_offset); - pr_debug("%s CSR RESET PADDR base %pa csr offset 0x%08X mask 0x%08X value 0x%08X\n", - clk_hw_get_name(hw), ®, + pr_debug("%s csr offset 0x%08X mask 0x%08X value 0x%08X\n", + clk_hw_get_name(hw), pclk->param.reg_csr_offset, pclk->param.reg_csr_mask, data); } diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c index 19f9b622981a..7a6acc3e4a92 100644 --- a/drivers/clk/imx/clk-pllv3.c +++ b/drivers/clk/imx/clk-pllv3.c @@ -223,7 +223,7 @@ static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw, temp64 *= mfn; do_div(temp64, mfd); - return (parent_rate * div) + (u32)temp64; + return parent_rate * div + (unsigned long)temp64; } static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate, @@ -247,7 +247,11 @@ static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate, do_div(temp64, parent_rate); mfn = temp64; - return parent_rate * div + parent_rate * mfn / mfd; + temp64 = (u64)parent_rate; + temp64 *= mfn; + do_div(temp64, mfd); + + return parent_rate * div + (unsigned long)temp64; } static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate, diff --git a/drivers/clk/mmp/clk-of-mmp2.c b/drivers/clk/mmp/clk-of-mmp2.c index 3a51fff1b0e7..9adaf48aea23 100644 --- a/drivers/clk/mmp/clk-of-mmp2.c +++ b/drivers/clk/mmp/clk-of-mmp2.c @@ -313,7 +313,7 @@ static void __init mmp2_clk_init(struct device_node *np) } pxa_unit->apmu_base = of_iomap(np, 1); - if (!pxa_unit->mpmu_base) { + if (!pxa_unit->apmu_base) { pr_err("failed to map apmu registers\n"); return; } diff --git a/drivers/clk/mmp/clk-of-pxa168.c b/drivers/clk/mmp/clk-of-pxa168.c index 87f2317b2a00..f110c02e83cb 100644 --- a/drivers/clk/mmp/clk-of-pxa168.c +++ b/drivers/clk/mmp/clk-of-pxa168.c @@ -262,7 +262,7 @@ static void __init pxa168_clk_init(struct device_node *np) } pxa_unit->apmu_base = of_iomap(np, 1); - if (!pxa_unit->mpmu_base) { + if (!pxa_unit->apmu_base) { pr_err("failed to map apmu registers\n"); return; } diff --git a/drivers/clk/mmp/clk-of-pxa910.c b/drivers/clk/mmp/clk-of-pxa910.c index e22a67f76d93..64d1ef49caeb 100644 --- a/drivers/clk/mmp/clk-of-pxa910.c +++ b/drivers/clk/mmp/clk-of-pxa910.c @@ -282,7 +282,7 @@ static void __init pxa910_clk_init(struct device_node *np) } pxa_unit->apmu_base = of_iomap(np, 1); - if (!pxa_unit->mpmu_base) { + if (!pxa_unit->apmu_base) { pr_err("failed to map apmu registers\n"); return; } @@ -294,7 +294,7 @@ static void __init pxa910_clk_init(struct device_node *np) } pxa_unit->apbcp_base = of_iomap(np, 3); - if (!pxa_unit->mpmu_base) { + if (!pxa_unit->apbcp_base) { pr_err("failed to map apbcp registers\n"); return; } diff --git a/drivers/clk/rockchip/clk-ddr.c b/drivers/clk/rockchip/clk-ddr.c index 8feba93672c5..e8075359366b 100644 --- a/drivers/clk/rockchip/clk-ddr.c +++ b/drivers/clk/rockchip/clk-ddr.c @@ -144,11 +144,8 @@ struct clk *rockchip_clk_register_ddrclk(const char *name, int flags, ddrclk->ddr_flag = ddr_flag; clk = clk_register(NULL, &ddrclk->hw); - if (IS_ERR(clk)) { - pr_err("%s: could not register ddrclk %s\n", __func__, name); + if (IS_ERR(clk)) kfree(ddrclk); - return NULL; - } return clk; } diff --git a/drivers/clk/samsung/clk-exynos-clkout.c b/drivers/clk/samsung/clk-exynos-clkout.c index 96fab6cfb202..6c6afb87b4ce 100644 --- a/drivers/clk/samsung/clk-exynos-clkout.c +++ b/drivers/clk/samsung/clk-exynos-clkout.c @@ -132,28 +132,34 @@ free_clkout: pr_err("%s: failed to register clkout clock\n", __func__); } +/* + * We use CLK_OF_DECLARE_DRIVER initialization method to avoid setting + * the OF_POPULATED flag on the pmu device tree node, so later the + * Exynos PMU platform device can be properly probed with PMU driver. + */ + static void __init exynos4_clkout_init(struct device_node *node) { exynos_clkout_init(node, EXYNOS4_CLKOUT_MUX_MASK); } -CLK_OF_DECLARE(exynos4210_clkout, "samsung,exynos4210-pmu", +CLK_OF_DECLARE_DRIVER(exynos4210_clkout, "samsung,exynos4210-pmu", exynos4_clkout_init); -CLK_OF_DECLARE(exynos4212_clkout, "samsung,exynos4212-pmu", +CLK_OF_DECLARE_DRIVER(exynos4212_clkout, "samsung,exynos4212-pmu", exynos4_clkout_init); -CLK_OF_DECLARE(exynos4412_clkout, "samsung,exynos4412-pmu", +CLK_OF_DECLARE_DRIVER(exynos4412_clkout, "samsung,exynos4412-pmu", exynos4_clkout_init); -CLK_OF_DECLARE(exynos3250_clkout, "samsung,exynos3250-pmu", +CLK_OF_DECLARE_DRIVER(exynos3250_clkout, "samsung,exynos3250-pmu", exynos4_clkout_init); static void __init exynos5_clkout_init(struct device_node *node) { exynos_clkout_init(node, EXYNOS5_CLKOUT_MUX_MASK); } -CLK_OF_DECLARE(exynos5250_clkout, "samsung,exynos5250-pmu", +CLK_OF_DECLARE_DRIVER(exynos5250_clkout, "samsung,exynos5250-pmu", exynos5_clkout_init); -CLK_OF_DECLARE(exynos5410_clkout, "samsung,exynos5410-pmu", +CLK_OF_DECLARE_DRIVER(exynos5410_clkout, "samsung,exynos5410-pmu", exynos5_clkout_init); -CLK_OF_DECLARE(exynos5420_clkout, "samsung,exynos5420-pmu", +CLK_OF_DECLARE_DRIVER(exynos5420_clkout, "samsung,exynos5420-pmu", exynos5_clkout_init); -CLK_OF_DECLARE(exynos5433_clkout, "samsung,exynos5433-pmu", +CLK_OF_DECLARE_DRIVER(exynos5433_clkout, "samsung,exynos5433-pmu", exynos5_clkout_init); diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c index 79596463e0d9..fc75a335a7ce 100644 --- a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c +++ b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c @@ -143,7 +143,7 @@ static SUNXI_CCU_NKM_WITH_MUX_GATE_LOCK(pll_mipi_clk, "pll-mipi", 4, 2, /* K */ 0, 4, /* M */ 21, 0, /* mux */ - BIT(31), /* gate */ + BIT(31) | BIT(23) | BIT(22), /* gate */ BIT(28), /* lock */ CLK_SET_RATE_UNGATE); @@ -191,6 +191,8 @@ static struct clk_div_table axi_div_table[] = { static SUNXI_CCU_DIV_TABLE(axi_clk, "axi", "cpu", 0x050, 0, 3, axi_div_table, 0); +#define SUN6I_A31_AHB1_REG 0x054 + static const char * const ahb1_parents[] = { "osc32k", "osc24M", "axi", "pll-periph" }; @@ -1230,6 +1232,16 @@ static void __init sun6i_a31_ccu_setup(struct device_node *node) val &= BIT(16); writel(val, reg + SUN6I_A31_PLL_MIPI_REG); + /* Force AHB1 to PLL6 / 3 */ + val = readl(reg + SUN6I_A31_AHB1_REG); + /* set PLL6 pre-div = 3 */ + val &= ~GENMASK(7, 6); + val |= 0x2 << 6; + /* select PLL6 / pre-div */ + val &= ~GENMASK(13, 12); + val |= 0x3 << 12; + writel(val, reg + SUN6I_A31_AHB1_REG); + sunxi_ccu_probe(node, reg, &sun6i_a31_ccu_desc); ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk, diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c index 96b40ca57697..9bd1f78a0547 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c @@ -131,7 +131,7 @@ static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_mipi_clk, "pll-mipi", 8, 4, /* N */ 4, 2, /* K */ 0, 4, /* M */ - BIT(31), /* gate */ + BIT(31) | BIT(23) | BIT(22), /* gate */ BIT(28), /* lock */ CLK_SET_RATE_UNGATE); diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c index 838b22aa8b67..f2c9274b8bd5 100644 --- a/drivers/clk/sunxi/clk-sunxi.c +++ b/drivers/clk/sunxi/clk-sunxi.c @@ -373,7 +373,7 @@ static void sun4i_get_apb1_factors(struct factors_request *req) else calcp = 3; - calcm = (req->parent_rate >> calcp) - 1; + calcm = (div >> calcp) - 1; req->rate = (req->parent_rate >> calcp) / (calcm + 1); req->m = calcm; diff --git a/drivers/crypto/caam/caamalg.c b/drivers/crypto/caam/caamalg.c index 156aad167cd6..954a64c7757b 100644 --- a/drivers/crypto/caam/caamalg.c +++ b/drivers/crypto/caam/caamalg.c @@ -137,7 +137,7 @@ static void dbg_dump_sg(const char *level, const char *prefix_str, } buf = it_page + it->offset; - len = min(tlen, it->length); + len = min_t(size_t, tlen, it->length); print_hex_dump(level, prefix_str, prefix_type, rowsize, groupsize, buf, len, ascii); tlen -= len; @@ -4583,6 +4583,15 @@ static int __init caam_algapi_init(void) if (!aes_inst && (alg_sel == OP_ALG_ALGSEL_AES)) continue; + /* + * Check support for AES modes not available + * on LP devices. + */ + if ((cha_vid & CHA_ID_LS_AES_MASK) == CHA_ID_LS_AES_LP) + if ((alg->class1_alg_type & OP_ALG_AAI_MASK) == + OP_ALG_AAI_XTS) + continue; + t_alg = caam_alg_alloc(alg); if (IS_ERR(t_alg)) { err = PTR_ERR(t_alg); diff --git a/drivers/dax/dax.c b/drivers/dax/dax.c index 0e499bfca41c..3d94ff20fdca 100644 --- a/drivers/dax/dax.c +++ b/drivers/dax/dax.c @@ -270,8 +270,8 @@ static int check_vma(struct dax_dev *dax_dev, struct vm_area_struct *vma, if (!dax_dev->alive) return -ENXIO; - /* prevent private / writable mappings from being established */ - if ((vma->vm_flags & (VM_NORESERVE|VM_SHARED|VM_WRITE)) == VM_WRITE) { + /* prevent private mappings from being established */ + if ((vma->vm_flags & VM_SHARED) != VM_SHARED) { dev_info(dev, "%s: %s: fail, attempted private mapping\n", current->comm, func); return -EINVAL; diff --git a/drivers/dax/pmem.c b/drivers/dax/pmem.c index 4a15fa5df98b..73c6ce93a0d9 100644 --- a/drivers/dax/pmem.c +++ b/drivers/dax/pmem.c @@ -78,7 +78,9 @@ static int dax_pmem_probe(struct device *dev) nsio = to_nd_namespace_io(&ndns->dev); /* parse the 'pfn' info block via ->rw_bytes */ - devm_nsio_enable(dev, nsio); + rc = devm_nsio_enable(dev, nsio); + if (rc) + return rc; altmap = nvdimm_setup_pfn(nd_pfn, &res, &__altmap); if (IS_ERR(altmap)) return PTR_ERR(altmap); diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index af63a6bcf564..141aefbe37ec 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -306,6 +306,7 @@ config MMP_TDMA depends on ARCH_MMP || COMPILE_TEST select DMA_ENGINE select MMP_SRAM if ARCH_MMP + select GENERIC_ALLOCATOR help Support the MMP Two-Channel DMA engine. This engine used for MMP Audio DMA and pxa910 SQU. diff --git a/drivers/dma/cppi41.c b/drivers/dma/cppi41.c index bac5f023013b..d5ba43a87a68 100644 --- a/drivers/dma/cppi41.c +++ b/drivers/dma/cppi41.c @@ -317,6 +317,12 @@ static irqreturn_t cppi41_irq(int irq, void *data) while (val) { u32 desc, len; + int error; + + error = pm_runtime_get(cdd->ddev.dev); + if (error < 0) + dev_err(cdd->ddev.dev, "%s pm runtime get: %i\n", + __func__, error); q_num = __fls(val); val &= ~(1 << q_num); @@ -338,7 +344,6 @@ static irqreturn_t cppi41_irq(int irq, void *data) dma_cookie_complete(&c->txd); dmaengine_desc_get_callback_invoke(&c->txd, NULL); - /* Paired with cppi41_dma_issue_pending */ pm_runtime_mark_last_busy(cdd->ddev.dev); pm_runtime_put_autosuspend(cdd->ddev.dev); } @@ -362,8 +367,13 @@ static int cppi41_dma_alloc_chan_resources(struct dma_chan *chan) int error; error = pm_runtime_get_sync(cdd->ddev.dev); - if (error < 0) + if (error < 0) { + dev_err(cdd->ddev.dev, "%s pm runtime get: %i\n", + __func__, error); + pm_runtime_put_noidle(cdd->ddev.dev); + return error; + } dma_cookie_init(chan); dma_async_tx_descriptor_init(&c->txd, chan); @@ -385,8 +395,11 @@ static void cppi41_dma_free_chan_resources(struct dma_chan *chan) int error; error = pm_runtime_get_sync(cdd->ddev.dev); - if (error < 0) + if (error < 0) { + pm_runtime_put_noidle(cdd->ddev.dev); + return; + } WARN_ON(!list_empty(&cdd->pending)); @@ -460,9 +473,9 @@ static void cppi41_dma_issue_pending(struct dma_chan *chan) struct cppi41_dd *cdd = c->cdd; int error; - /* PM runtime paired with dmaengine_desc_get_callback_invoke */ error = pm_runtime_get(cdd->ddev.dev); if ((error != -EINPROGRESS) && error < 0) { + pm_runtime_put_noidle(cdd->ddev.dev); dev_err(cdd->ddev.dev, "Failed to pm_runtime_get: %i\n", error); @@ -473,6 +486,9 @@ static void cppi41_dma_issue_pending(struct dma_chan *chan) push_desc_queue(c); else pending_desc(c); + + pm_runtime_mark_last_busy(cdd->ddev.dev); + pm_runtime_put_autosuspend(cdd->ddev.dev); } static u32 get_host_pd0(u32 length) @@ -1059,8 +1075,8 @@ err_chans: deinit_cppi41(dev, cdd); err_init_cppi: pm_runtime_dont_use_autosuspend(dev); - pm_runtime_put_sync(dev); err_get_sync: + pm_runtime_put_sync(dev); pm_runtime_disable(dev); iounmap(cdd->usbss_mem); iounmap(cdd->ctrl_mem); @@ -1072,7 +1088,12 @@ err_get_sync: static int cppi41_dma_remove(struct platform_device *pdev) { struct cppi41_dd *cdd = platform_get_drvdata(pdev); + int error; + error = pm_runtime_get_sync(&pdev->dev); + if (error < 0) + dev_err(&pdev->dev, "%s could not pm_runtime_get: %i\n", + __func__, error); of_dma_controller_free(pdev->dev.of_node); dma_async_device_unregister(&cdd->ddev); diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index e18a58068bca..77242b37ef87 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -1628,6 +1628,7 @@ static int edma_alloc_chan_resources(struct dma_chan *chan) if (echan->slot[0] < 0) { dev_err(dev, "Entry slot allocation failed for channel %u\n", EDMA_CHAN_SLOT(echan->ch_num)); + ret = echan->slot[0]; goto err_slot; } diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c index 83461994e418..a2358780ab2c 100644 --- a/drivers/dma/sun6i-dma.c +++ b/drivers/dma/sun6i-dma.c @@ -578,7 +578,7 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_memcpy( burst = convert_burst(8); width = convert_buswidth(DMA_SLAVE_BUSWIDTH_4_BYTES); - v_lli->cfg |= DMA_CHAN_CFG_SRC_DRQ(DRQ_SDRAM) | + v_lli->cfg = DMA_CHAN_CFG_SRC_DRQ(DRQ_SDRAM) | DMA_CHAN_CFG_DST_DRQ(DRQ_SDRAM) | DMA_CHAN_CFG_DST_LINEAR_MODE | DMA_CHAN_CFG_SRC_LINEAR_MODE | diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index d011cb89d25e..ed37e5908b91 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -22,10 +22,6 @@ menuconfig GPIOLIB if GPIOLIB -config GPIO_DEVRES - def_bool y - depends on HAS_IOMEM - config OF_GPIO def_bool y depends on OF diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index ab28a2daeacc..d074c2299393 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -2,7 +2,7 @@ ccflags-$(CONFIG_DEBUG_GPIO) += -DDEBUG -obj-$(CONFIG_GPIO_DEVRES) += devres.o +obj-$(CONFIG_GPIOLIB) += devres.o obj-$(CONFIG_GPIOLIB) += gpiolib.o obj-$(CONFIG_GPIOLIB) += gpiolib-legacy.o obj-$(CONFIG_OF_GPIO) += gpiolib-of.o diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c index e422568e14ad..fe731f094257 100644 --- a/drivers/gpio/gpio-pca953x.c +++ b/drivers/gpio/gpio-pca953x.c @@ -372,14 +372,15 @@ static void pca953x_gpio_set_multiple(struct gpio_chip *gc, bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); - memcpy(reg_val, chip->reg_output, NBANK(chip)); mutex_lock(&chip->i2c_lock); + memcpy(reg_val, chip->reg_output, NBANK(chip)); for (bank = 0; bank < NBANK(chip); bank++) { bank_mask = mask[bank / sizeof(*mask)] >> ((bank % sizeof(*mask)) * 8); if (bank_mask) { bank_val = bits[bank / sizeof(*bits)] >> ((bank % sizeof(*bits)) * 8); + bank_val &= bank_mask; reg_val[bank] = (reg_val[bank] & ~bank_mask) | bank_val; } } @@ -607,7 +608,6 @@ static int pca953x_irq_setup(struct pca953x_chip *chip, if (client->irq && irq_base != -1 && (chip->driver_data & PCA_INT)) { - ret = pca953x_read_regs(chip, chip->regs->input, chip->irq_stat); if (ret) diff --git a/drivers/gpio/gpio-tc3589x.c b/drivers/gpio/gpio-tc3589x.c index 5a5a6cb00eea..d6e21f1a70a9 100644 --- a/drivers/gpio/gpio-tc3589x.c +++ b/drivers/gpio/gpio-tc3589x.c @@ -97,7 +97,7 @@ static int tc3589x_gpio_get_direction(struct gpio_chip *chip, if (ret < 0) return ret; - return !!(ret & BIT(pos)); + return !(ret & BIT(pos)); } static int tc3589x_gpio_set_single_ended(struct gpio_chip *chip, diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index 93ed0e00c578..868128a676ba 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -2737,8 +2737,11 @@ int gpiochip_lock_as_irq(struct gpio_chip *chip, unsigned int offset) if (IS_ERR(desc)) return PTR_ERR(desc); - /* Flush direction if something changed behind our back */ - if (chip->get_direction) { + /* + * If it's fast: flush the direction setting if something changed + * behind our back + */ + if (!chip->can_sleep && chip->get_direction) { int dir = chip->get_direction(chip, offset); if (dir) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index c2b8496cdf63..f53e52f4d672 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -92,13 +92,13 @@ extern int amdgpu_vm_debug; extern int amdgpu_sched_jobs; extern int amdgpu_sched_hw_submission; extern int amdgpu_powerplay; -extern int amdgpu_powercontainment; +extern int amdgpu_no_evict; +extern int amdgpu_direct_gma_size; extern unsigned amdgpu_pcie_gen_cap; extern unsigned amdgpu_pcie_lane_cap; extern unsigned amdgpu_cg_mask; extern unsigned amdgpu_pg_mask; extern char *amdgpu_disable_cu; -extern int amdgpu_sclk_deep_sleep_en; extern char *amdgpu_virtual_display; extern unsigned amdgpu_pp_feature_mask; extern int amdgpu_vram_page_split; @@ -391,6 +391,7 @@ struct amdgpu_bo { u64 metadata_flags; void *metadata; u32 metadata_size; + unsigned prime_shared_count; /* list of all virtual address to which this bo * is associated to */ @@ -1632,7 +1633,6 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r)) #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc)) #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc)) -#define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev)) #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l)) #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e)) #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h)) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c index 2f9f96cc9f65..06879d1dcabd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c @@ -395,9 +395,12 @@ static int acp_hw_fini(void *handle) { int i, ret; struct device *dev; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + /* return early if no ACP */ + if (!adev->acp.acp_genpd) + return 0; + for (i = 0; i < ACP_DEVS ; i++) { dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i); ret = pm_genpd_remove_device(&adev->acp.acp_genpd->gpd, dev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c index dae35a96a694..6c343a933182 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c @@ -34,6 +34,7 @@ struct amdgpu_atpx { static struct amdgpu_atpx_priv { bool atpx_detected; + bool bridge_pm_usable; /* handle for device - and atpx */ acpi_handle dhandle; acpi_handle other_handle; @@ -205,7 +206,11 @@ static int amdgpu_atpx_validate(struct amdgpu_atpx *atpx) atpx->is_hybrid = false; if (valid_bits & ATPX_MS_HYBRID_GFX_SUPPORTED) { printk("ATPX Hybrid Graphics\n"); - atpx->functions.power_cntl = false; + /* + * Disable legacy PM methods only when pcie port PM is usable, + * otherwise the device might fail to power off or power on. + */ + atpx->functions.power_cntl = !amdgpu_atpx_priv.bridge_pm_usable; atpx->is_hybrid = true; } @@ -555,17 +560,25 @@ static bool amdgpu_atpx_detect(void) struct pci_dev *pdev = NULL; bool has_atpx = false; int vga_count = 0; + bool d3_supported = false; + struct pci_dev *parent_pdev; while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { vga_count++; has_atpx |= (amdgpu_atpx_pci_probe_handle(pdev) == true); + + parent_pdev = pci_upstream_bridge(pdev); + d3_supported |= parent_pdev && parent_pdev->bridge_d3; } while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) { vga_count++; has_atpx |= (amdgpu_atpx_pci_probe_handle(pdev) == true); + + parent_pdev = pci_upstream_bridge(pdev); + d3_supported |= parent_pdev && parent_pdev->bridge_d3; } if (has_atpx && vga_count == 2) { @@ -573,6 +586,7 @@ static bool amdgpu_atpx_detect(void) printk(KERN_INFO "vga_switcheroo: detected switching method %s handle\n", acpi_method_name); amdgpu_atpx_priv.atpx_detected = true; + amdgpu_atpx_priv.bridge_pm_usable = d3_supported; amdgpu_atpx_init(); return true; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c index 2b6afe123f3d..b7e2762fcdd2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c @@ -70,7 +70,7 @@ static bool igp_read_bios_from_vram(struct amdgpu_device *adev) return false; } adev->bios = kmalloc(size, GFP_KERNEL); - if (adev->bios == NULL) { + if (!adev->bios) { iounmap(bios); return false; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c index 651115dcce12..c02db01f6583 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c @@ -132,7 +132,7 @@ static int amdgpu_bo_list_set(struct amdgpu_device *adev, entry->priority = min(info[i].bo_priority, AMDGPU_BO_LIST_MAX_PRIORITY); entry->tv.bo = &entry->robj->tbo; - entry->tv.shared = true; + entry->tv.shared = !entry->robj->prime_shared_count; if (entry->robj->prefered_domains == AMDGPU_GEM_DOMAIN_GDS) gds_obj = entry->robj; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c index 017556ca22e6..7ded61e6dd81 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c @@ -809,10 +809,19 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device, if (!adev->pm.fw) { switch (adev->asic_type) { case CHIP_TOPAZ: - strcpy(fw_name, "amdgpu/topaz_smc.bin"); + if (((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x81)) || + ((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x83)) || + ((adev->pdev->device == 0x6907) && (adev->pdev->revision == 0x87))) + strcpy(fw_name, "amdgpu/topaz_k_smc.bin"); + else + strcpy(fw_name, "amdgpu/topaz_smc.bin"); break; case CHIP_TONGA: - strcpy(fw_name, "amdgpu/tonga_smc.bin"); + if (((adev->pdev->device == 0x6939) && (adev->pdev->revision == 0xf1)) || + ((adev->pdev->device == 0x6938) && (adev->pdev->revision == 0xf1))) + strcpy(fw_name, "amdgpu/tonga_k_smc.bin"); + else + strcpy(fw_name, "amdgpu/tonga_smc.bin"); break; case CHIP_FIJI: strcpy(fw_name, "amdgpu/fiji_smc.bin"); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c index 3af8ffb45b64..8d1cf2d3e663 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c @@ -769,7 +769,7 @@ static void amdgpu_connector_unregister(struct drm_connector *connector) { struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); - if (amdgpu_connector->ddc_bus->has_aux) { + if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) { drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux); amdgpu_connector->ddc_bus->has_aux = false; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 78da52f90099..5a277495d6a3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -841,16 +841,6 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev, return amdgpu_cs_sync_rings(p); } -static int amdgpu_cs_handle_lockup(struct amdgpu_device *adev, int r) -{ - if (r == -EDEADLK) { - r = amdgpu_gpu_reset(adev); - if (!r) - r = -EAGAIN; - } - return r; -} - static int amdgpu_cs_ib_fill(struct amdgpu_device *adev, struct amdgpu_cs_parser *parser) { @@ -1054,29 +1044,29 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) r = amdgpu_cs_parser_init(&parser, data); if (r) { DRM_ERROR("Failed to initialize parser !\n"); - amdgpu_cs_parser_fini(&parser, r, false); - r = amdgpu_cs_handle_lockup(adev, r); - return r; - } - r = amdgpu_cs_parser_bos(&parser, data); - if (r == -ENOMEM) - DRM_ERROR("Not enough memory for command submission!\n"); - else if (r && r != -ERESTARTSYS) - DRM_ERROR("Failed to process the buffer list %d!\n", r); - else if (!r) { - reserved_buffers = true; - r = amdgpu_cs_ib_fill(adev, &parser); + goto out; } - if (!r) { - r = amdgpu_cs_dependencies(adev, &parser); - if (r) - DRM_ERROR("Failed in the dependencies handling %d!\n", r); + r = amdgpu_cs_parser_bos(&parser, data); + if (r) { + if (r == -ENOMEM) + DRM_ERROR("Not enough memory for command submission!\n"); + else if (r != -ERESTARTSYS) + DRM_ERROR("Failed to process the buffer list %d!\n", r); + goto out; } + reserved_buffers = true; + r = amdgpu_cs_ib_fill(adev, &parser); if (r) goto out; + r = amdgpu_cs_dependencies(adev, &parser); + if (r) { + DRM_ERROR("Failed in the dependencies handling %d!\n", r); + goto out; + } + for (i = 0; i < parser.job->num_ibs; i++) trace_amdgpu_cs(&parser, i); @@ -1088,7 +1078,6 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) out: amdgpu_cs_parser_fini(&parser, r, reserved_buffers); - r = amdgpu_cs_handle_lockup(adev, r); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 76cc47a9a7fb..5cc0ea344d1a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -636,12 +636,10 @@ static bool amdgpu_vpost_needed(struct amdgpu_device *adev) return false; if (amdgpu_passthrough(adev)) { - /* for FIJI: In whole GPU pass-through virtualization case - * old smc fw won't clear some registers (e.g. MEM_SIZE, BIOS_SCRATCH) - * so amdgpu_card_posted return false and driver will incorrectly skip vPost. - * but if we force vPost do in pass-through case, the driver reload will hang. - * whether doing vPost depends on amdgpu_card_posted if smc version is above - * 00160e00 for FIJI. + /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot + * some old smc fw still need driver do vPost otherwise gpu hang, while + * those smc fw version above 22.15 doesn't have this flaw, so we force + * vpost executed for smc version below 22.15 */ if (adev->asic_type == CHIP_FIJI) { int err; @@ -652,22 +650,11 @@ static bool amdgpu_vpost_needed(struct amdgpu_device *adev) return true; fw_ver = *((uint32_t *)adev->pm.fw->data + 69); - if (fw_ver >= 0x00160e00) - return !amdgpu_card_posted(adev); + if (fw_ver < 0x00160e00) + return true; } - } else { - /* in bare-metal case, amdgpu_card_posted return false - * after system reboot/boot, and return true if driver - * reloaded. - * we shouldn't do vPost after driver reload otherwise GPU - * could hang. - */ - if (amdgpu_card_posted(adev)) - return false; } - - /* we assume vPost is neede for all other cases */ - return true; + return !amdgpu_card_posted(adev); } /** @@ -1030,8 +1017,8 @@ static void amdgpu_check_arguments(struct amdgpu_device *adev) amdgpu_vm_block_size = 9; } - if ((amdgpu_vram_page_split != -1 && amdgpu_vram_page_split < 16) || - !amdgpu_check_pot_argument(amdgpu_vram_page_split)) { + if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 || + !amdgpu_check_pot_argument(amdgpu_vram_page_split))) { dev_warn(adev->dev, "invalid VRAM page split (%d)\n", amdgpu_vram_page_split); amdgpu_vram_page_split = 1024; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h index bd85e35998e7..955d6f21e2b3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h @@ -52,6 +52,8 @@ enum amdgpu_dpm_event_src { AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 }; +#define SCLK_DEEP_SLEEP_MASK 0x8 + struct amdgpu_ps { u32 caps; /* vbios flags */ u32 class; /* vbios flags */ @@ -317,6 +319,11 @@ struct amdgpu_dpm_funcs { (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \ (adev)->pm.funcs->get_fan_speed_percent((adev), (s))) +#define amdgpu_dpm_get_fan_speed_rpm(adev, s) \ + ((adev)->pp_enabled ? \ + (adev)->powerplay.pp_funcs->get_fan_speed_rpm((adev)->powerplay.pp_handle, (s)) : \ + -EINVAL) + #define amdgpu_dpm_get_sclk(adev, l) \ ((adev)->pp_enabled ? \ (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 6bb4d9e9afe4..7914f999b1bc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -91,8 +91,8 @@ int amdgpu_exp_hw_support = 0; int amdgpu_sched_jobs = 32; int amdgpu_sched_hw_submission = 2; int amdgpu_powerplay = -1; -int amdgpu_powercontainment = 1; -int amdgpu_sclk_deep_sleep_en = 1; +int amdgpu_no_evict = 0; +int amdgpu_direct_gma_size = 0; unsigned amdgpu_pcie_gen_cap = 0; unsigned amdgpu_pcie_lane_cap = 0; unsigned amdgpu_cg_mask = 0xffffffff; @@ -182,14 +182,14 @@ module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); MODULE_PARM_DESC(powerplay, "Powerplay component (1 = enable, 0 = disable, -1 = auto (default))"); module_param_named(powerplay, amdgpu_powerplay, int, 0444); -MODULE_PARM_DESC(powercontainment, "Power Containment (1 = enable (default), 0 = disable)"); -module_param_named(powercontainment, amdgpu_powercontainment, int, 0444); - MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, int, 0444); -MODULE_PARM_DESC(sclkdeepsleep, "SCLK Deep Sleep (1 = enable (default), 0 = disable)"); -module_param_named(sclkdeepsleep, amdgpu_sclk_deep_sleep_en, int, 0444); +MODULE_PARM_DESC(no_evict, "Support pinning request from user space (1 = enable, 0 = disable (default))"); +module_param_named(no_evict, amdgpu_no_evict, int, 0444); + +MODULE_PARM_DESC(direct_gma_size, "Direct GMA size in megabytes (max 96MB)"); +module_param_named(direct_gma_size, amdgpu_direct_gma_size, int, 0444); MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); @@ -742,8 +742,20 @@ static struct pci_driver amdgpu_kms_pci_driver = { static int __init amdgpu_init(void) { - amdgpu_sync_init(); - amdgpu_fence_slab_init(); + int r; + + r = amdgpu_sync_init(); + if (r) + goto error_sync; + + r = amdgpu_fence_slab_init(); + if (r) + goto error_fence; + + r = amd_sched_fence_slab_init(); + if (r) + goto error_sched; + if (vgacon_text_force()) { DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); return -EINVAL; @@ -755,6 +767,15 @@ static int __init amdgpu_init(void) amdgpu_register_atpx_handler(); /* let modprobe override vga console setting */ return drm_pci_init(driver, pdriver); + +error_sched: + amdgpu_fence_slab_fini(); + +error_fence: + amdgpu_sync_fini(); + +error_sync: + return r; } static void __exit amdgpu_exit(void) @@ -763,6 +784,7 @@ static void __exit amdgpu_exit(void) drm_pci_exit(driver, pdriver); amdgpu_unregister_atpx_handler(); amdgpu_sync_fini(); + amd_sched_fence_slab_fini(); amdgpu_fence_slab_fini(); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index 97928d7281f6..7b60fb79c3a6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -382,24 +382,27 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, if (!ring->fence_drv.fences) return -ENOMEM; - timeout = msecs_to_jiffies(amdgpu_lockup_timeout); - if (timeout == 0) { - /* - * FIXME: - * Delayed workqueue cannot use it directly, - * so the scheduler will not use delayed workqueue if - * MAX_SCHEDULE_TIMEOUT is set. - * Currently keep it simple and silly. - */ - timeout = MAX_SCHEDULE_TIMEOUT; - } - r = amd_sched_init(&ring->sched, &amdgpu_sched_ops, - num_hw_submission, - timeout, ring->name); - if (r) { - DRM_ERROR("Failed to create scheduler on ring %s.\n", - ring->name); - return r; + /* No need to setup the GPU scheduler for KIQ ring */ + if (ring->funcs->type != AMDGPU_RING_TYPE_KIQ) { + timeout = msecs_to_jiffies(amdgpu_lockup_timeout); + if (timeout == 0) { + /* + * FIXME: + * Delayed workqueue cannot use it directly, + * so the scheduler will not use delayed workqueue if + * MAX_SCHEDULE_TIMEOUT is set. + * Currently keep it simple and silly. + */ + timeout = MAX_SCHEDULE_TIMEOUT; + } + r = amd_sched_init(&ring->sched, &amdgpu_sched_ops, + num_hw_submission, + timeout, ring->name); + if (r) { + DRM_ERROR("Failed to create scheduler on ring %s.\n", + ring->name); + return r; + } } return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c index 9fa809876339..fb902932f571 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c @@ -424,15 +424,6 @@ int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src, return 0; } -bool amdgpu_irq_get_delayed(struct amdgpu_device *adev, - struct amdgpu_irq_src *src, - unsigned type) -{ - if ((type >= src->num_types) || !src->enabled_types) - return false; - return atomic_inc_return(&src->enabled_types[type]) == 1; -} - /** * amdgpu_irq_put - disable interrupt * diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h index f016464035b8..1642f4108297 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h @@ -88,9 +88,6 @@ int amdgpu_irq_update(struct amdgpu_device *adev, struct amdgpu_irq_src *src, unsigned type); int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src, unsigned type); -bool amdgpu_irq_get_delayed(struct amdgpu_device *adev, - struct amdgpu_irq_src *src, - unsigned type); int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src, unsigned type); bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index ad908612aff9..d1cf9ac0dff1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -99,6 +99,8 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) if ((amdgpu_runtime_pm != 0) && amdgpu_has_atpx() && + (amdgpu_is_atpx_hybrid() || + amdgpu_has_atpx_dgpu_power_cntl()) && ((flags & AMD_IS_APU) == 0)) flags |= AMD_IS_PX; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 1e23334b07fb..202b4176b74e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -271,8 +271,6 @@ struct amdgpu_display_funcs { u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc); /* wait for vblank */ void (*vblank_wait)(struct amdgpu_device *adev, int crtc); - /* is dce hung */ - bool (*is_display_hung)(struct amdgpu_device *adev); /* set backlight level */ void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder, u8 level); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 1479d09bd4dd..bf79b73e1538 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -128,17 +128,6 @@ static void amdgpu_ttm_placement_init(struct amdgpu_device *adev, if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) lpfn = adev->mc.real_vram_size >> PAGE_SHIFT; - if (flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS && - !(flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) && - adev->mc.visible_vram_size < adev->mc.real_vram_size) { - places[c].fpfn = visible_pfn; - places[c].lpfn = lpfn; - places[c].flags = TTM_PL_FLAG_WC | - TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_VRAM | - TTM_PL_FLAG_TOPDOWN; - c++; - } - places[c].fpfn = 0; places[c].lpfn = lpfn; places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | @@ -382,39 +371,36 @@ int amdgpu_bo_create_restricted(struct amdgpu_device *adev, amdgpu_fill_placement_to_bo(bo, placement); /* Kernel allocation are uninterruptible */ + + if (!resv) { + bool locked; + + reservation_object_init(&bo->tbo.ttm_resv); + locked = ww_mutex_trylock(&bo->tbo.ttm_resv.lock); + WARN_ON(!locked); + } r = ttm_bo_init(&adev->mman.bdev, &bo->tbo, size, type, &bo->placement, page_align, !kernel, NULL, - acc_size, sg, resv, &amdgpu_ttm_bo_destroy); - if (unlikely(r != 0)) { + acc_size, sg, resv ? resv : &bo->tbo.ttm_resv, + &amdgpu_ttm_bo_destroy); + if (unlikely(r != 0)) return r; - } if (flags & AMDGPU_GEM_CREATE_VRAM_CLEARED && bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) { struct dma_fence *fence; - if (adev->mman.buffer_funcs_ring == NULL || - !adev->mman.buffer_funcs_ring->ready) { - r = -EBUSY; - goto fail_free; - } - - r = amdgpu_bo_reserve(bo, false); - if (unlikely(r != 0)) - goto fail_free; - - amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM); - r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); - if (unlikely(r != 0)) + r = amdgpu_fill_buffer(bo, 0, bo->tbo.resv, &fence); + if (unlikely(r)) goto fail_unreserve; - amdgpu_fill_buffer(bo, 0, bo->tbo.resv, &fence); amdgpu_bo_fence(bo, fence, false); - amdgpu_bo_unreserve(bo); dma_fence_put(bo->tbo.moving); bo->tbo.moving = dma_fence_get(fence); dma_fence_put(fence); } + if (!resv) + ww_mutex_unlock(&bo->tbo.resv->lock); *bo_ptr = bo; trace_amdgpu_bo_create(bo); @@ -422,8 +408,7 @@ int amdgpu_bo_create_restricted(struct amdgpu_device *adev, return 0; fail_unreserve: - amdgpu_bo_unreserve(bo); -fail_free: + ww_mutex_unlock(&bo->tbo.resv->lock); amdgpu_bo_unref(&bo); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c index 274f3309aec9..723ae682bf25 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c @@ -737,6 +737,21 @@ static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev, return sprintf(buf, "%i\n", speed); } +static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct amdgpu_device *adev = dev_get_drvdata(dev); + int err; + u32 speed; + + err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed); + if (err) + return err; + + return sprintf(buf, "%i\n", speed); +} + static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, 0); static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0); static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1); @@ -744,6 +759,7 @@ static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0); static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0); static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0); +static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0); static struct attribute *hwmon_attributes[] = { &sensor_dev_attr_temp1_input.dev_attr.attr, @@ -753,6 +769,7 @@ static struct attribute *hwmon_attributes[] = { &sensor_dev_attr_pwm1_enable.dev_attr.attr, &sensor_dev_attr_pwm1_min.dev_attr.attr, &sensor_dev_attr_pwm1_max.dev_attr.attr, + &sensor_dev_attr_fan1_input.dev_attr.attr, NULL }; @@ -804,6 +821,10 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj, attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) return 0; + /* requires powerplay */ + if (attr == &sensor_dev_attr_fan1_input.dev_attr.attr) + return 0; + return effective_mode; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c index fa6baf31a35d..fc592c2b0e16 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c @@ -155,9 +155,6 @@ static int amdgpu_pp_sw_init(void *handle) ret = adev->powerplay.ip_funcs->sw_init( adev->powerplay.pp_handle); - if (adev->pp_enabled) - adev->pm.dpm_enabled = true; - return ret; } @@ -187,6 +184,9 @@ static int amdgpu_pp_hw_init(void *handle) ret = adev->powerplay.ip_funcs->hw_init( adev->powerplay.pp_handle); + if ((amdgpu_dpm != 0) && !amdgpu_sriov_vf(adev)) + adev->pm.dpm_enabled = true; + return ret; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c index 7700dc22f243..3826d5aea0a6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c @@ -74,20 +74,36 @@ amdgpu_gem_prime_import_sg_table(struct drm_device *dev, if (ret) return ERR_PTR(ret); + bo->prime_shared_count = 1; return &bo->gem_base; } int amdgpu_gem_prime_pin(struct drm_gem_object *obj) { struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); - int ret = 0; + long ret = 0; ret = amdgpu_bo_reserve(bo, false); if (unlikely(ret != 0)) return ret; + /* + * Wait for all shared fences to complete before we switch to future + * use of exclusive fence on this prime shared bo. + */ + ret = reservation_object_wait_timeout_rcu(bo->tbo.resv, true, false, + MAX_SCHEDULE_TIMEOUT); + if (unlikely(ret < 0)) { + DRM_DEBUG_PRIME("Fence wait failed: %li\n", ret); + amdgpu_bo_unreserve(bo); + return ret; + } + /* pin buffer into GTT */ ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT, NULL); + if (likely(ret == 0)) + bo->prime_shared_count++; + amdgpu_bo_unreserve(bo); return ret; } @@ -102,6 +118,8 @@ void amdgpu_gem_prime_unpin(struct drm_gem_object *obj) return; amdgpu_bo_unpin(bo); + if (bo->prime_shared_count) + bo->prime_shared_count--; amdgpu_bo_unreserve(bo); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h index f2ad49c8e85b..574f0b79c690 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h @@ -44,7 +44,8 @@ enum amdgpu_ring_type { AMDGPU_RING_TYPE_COMPUTE, AMDGPU_RING_TYPE_SDMA, AMDGPU_RING_TYPE_UVD, - AMDGPU_RING_TYPE_VCE + AMDGPU_RING_TYPE_VCE, + AMDGPU_RING_TYPE_KIQ }; struct amdgpu_device; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c index 34a795463988..de9f919ae336 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c @@ -327,9 +327,8 @@ int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager, return -EINVAL; *sa_bo = kmalloc(sizeof(struct amdgpu_sa_bo), GFP_KERNEL); - if ((*sa_bo) == NULL) { + if (!(*sa_bo)) return -ENOMEM; - } (*sa_bo)->manager = sa_manager; (*sa_bo)->fence = NULL; INIT_LIST_HEAD(&(*sa_bo)->olist); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 1821c05484d0..8f18b8ed2b3a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -1382,28 +1382,40 @@ error_free: } int amdgpu_fill_buffer(struct amdgpu_bo *bo, - uint32_t src_data, - struct reservation_object *resv, - struct dma_fence **fence) + uint32_t src_data, + struct reservation_object *resv, + struct dma_fence **fence) { struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); - struct amdgpu_job *job; + uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes; struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; - uint32_t max_bytes, byte_count; - uint64_t dst_offset; + struct drm_mm_node *mm_node; + unsigned long num_pages; unsigned int num_loops, num_dw; - unsigned int i; + + struct amdgpu_job *job; int r; - byte_count = bo->tbo.num_pages << PAGE_SHIFT; - max_bytes = adev->mman.buffer_funcs->fill_max_bytes; - num_loops = DIV_ROUND_UP(byte_count, max_bytes); + if (!ring->ready) { + DRM_ERROR("Trying to clear memory with ring turned off.\n"); + return -EINVAL; + } + + num_pages = bo->tbo.num_pages; + mm_node = bo->tbo.mem.mm_node; + num_loops = 0; + while (num_pages) { + uint32_t byte_count = mm_node->size << PAGE_SHIFT; + + num_loops += DIV_ROUND_UP(byte_count, max_bytes); + num_pages -= mm_node->size; + ++mm_node; + } num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw; /* for IB padding */ - while (num_dw & 0x7) - num_dw++; + num_dw += 64; r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job); if (r) @@ -1411,28 +1423,43 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo, if (resv) { r = amdgpu_sync_resv(adev, &job->sync, resv, - AMDGPU_FENCE_OWNER_UNDEFINED); + AMDGPU_FENCE_OWNER_UNDEFINED); if (r) { DRM_ERROR("sync failed (%d).\n", r); goto error_free; } } - dst_offset = bo->tbo.mem.start << PAGE_SHIFT; - for (i = 0; i < num_loops; i++) { - uint32_t cur_size_in_bytes = min(byte_count, max_bytes); + num_pages = bo->tbo.num_pages; + mm_node = bo->tbo.mem.mm_node; - amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, - dst_offset, cur_size_in_bytes); + while (num_pages) { + uint32_t byte_count = mm_node->size << PAGE_SHIFT; + uint64_t dst_addr; - dst_offset += cur_size_in_bytes; - byte_count -= cur_size_in_bytes; + r = amdgpu_mm_node_addr(&bo->tbo, mm_node, + &bo->tbo.mem, &dst_addr); + if (r) + return r; + + while (byte_count) { + uint32_t cur_size_in_bytes = min(byte_count, max_bytes); + + amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, + dst_addr, cur_size_in_bytes); + + dst_addr += cur_size_in_bytes; + byte_count -= cur_size_in_bytes; + } + + num_pages -= mm_node->size; + ++mm_node; } amdgpu_ring_pad_ib(ring, &job->ibs[0]); WARN_ON(job->ibs[0].length_dw > num_dw); r = amdgpu_job_submit(job, ring, &adev->mman.entity, - AMDGPU_FENCE_OWNER_UNDEFINED, fence); + AMDGPU_FENCE_OWNER_UNDEFINED, fence); if (r) goto error_free; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c index fb270c7e7171..a81dfaeeb8c0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c @@ -360,6 +360,18 @@ static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo) } } +static u64 amdgpu_uvd_get_addr_from_ctx(struct amdgpu_uvd_cs_ctx *ctx) +{ + uint32_t lo, hi; + uint64_t addr; + + lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0); + hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1); + addr = ((uint64_t)lo) | (((uint64_t)hi) << 32); + + return addr; +} + /** * amdgpu_uvd_cs_pass1 - first parsing round * @@ -372,14 +384,10 @@ static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx) { struct amdgpu_bo_va_mapping *mapping; struct amdgpu_bo *bo; - uint32_t cmd, lo, hi; - uint64_t addr; + uint32_t cmd; + uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx); int r = 0; - lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0); - hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1); - addr = ((uint64_t)lo) | (((uint64_t)hi) << 32); - mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo); if (mapping == NULL) { DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); @@ -698,18 +706,16 @@ static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx) { struct amdgpu_bo_va_mapping *mapping; struct amdgpu_bo *bo; - uint32_t cmd, lo, hi; + uint32_t cmd; uint64_t start, end; - uint64_t addr; + uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx); int r; - lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0); - hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1); - addr = ((uint64_t)lo) | (((uint64_t)hi) << 32); - mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo); - if (mapping == NULL) + if (mapping == NULL) { + DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); return -EINVAL; + } start = amdgpu_bo_gpu_offset(bo); @@ -893,10 +899,13 @@ int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx) ctx.buf_sizes = buf_sizes; ctx.ib_idx = ib_idx; - /* first round, make sure the buffers are actually in the UVD segment */ - r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1); - if (r) - return r; + /* first round only required on chips without UVD 64 bit address support */ + if (!parser->adev->uvd.address_64_bit) { + /* first round, make sure the buffers are actually in the UVD segment */ + r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1); + if (r) + return r; + } /* second round, patch buffer addresses into the command stream */ r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 337c5b31d18d..1dda9321bd5a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -530,70 +530,6 @@ static void amdgpu_vm_do_copy_ptes(struct amdgpu_pte_update_params *params, } /** - * amdgpu_vm_clear_bo - initially clear the page dir/table - * - * @adev: amdgpu_device pointer - * @bo: bo to clear - * - * need to reserve bo first before calling it. - */ -static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, - struct amdgpu_vm *vm, - struct amdgpu_bo *bo) -{ - struct amdgpu_ring *ring; - struct dma_fence *fence = NULL; - struct amdgpu_job *job; - struct amdgpu_pte_update_params params; - unsigned entries; - uint64_t addr; - int r; - - ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); - - r = reservation_object_reserve_shared(bo->tbo.resv); - if (r) - return r; - - r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); - if (r) - goto error; - - r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem); - if (r) - goto error; - - addr = amdgpu_bo_gpu_offset(bo); - entries = amdgpu_bo_size(bo) / 8; - - r = amdgpu_job_alloc_with_ib(adev, 64, &job); - if (r) - goto error; - - memset(¶ms, 0, sizeof(params)); - params.adev = adev; - params.ib = &job->ibs[0]; - amdgpu_vm_do_set_ptes(¶ms, addr, 0, entries, 0, 0); - amdgpu_ring_pad_ib(ring, &job->ibs[0]); - - WARN_ON(job->ibs[0].length_dw > 64); - r = amdgpu_job_submit(job, ring, &vm->entity, - AMDGPU_FENCE_OWNER_VM, &fence); - if (r) - goto error_free; - - amdgpu_bo_fence(bo, fence, true); - dma_fence_put(fence); - return 0; - -error_free: - amdgpu_job_free(job); - -error: - return r; -} - -/** * amdgpu_vm_map_gart - Resolve gart mapping of addr * * @pages_addr: optional DMA address to use for lookup @@ -1435,7 +1371,8 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev, AMDGPU_GEM_DOMAIN_VRAM, AMDGPU_GEM_CREATE_NO_CPU_ACCESS | AMDGPU_GEM_CREATE_SHADOW | - AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, + AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | + AMDGPU_GEM_CREATE_VRAM_CLEARED, NULL, resv, &pt); if (r) goto error_free; @@ -1445,22 +1382,6 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev, */ pt->parent = amdgpu_bo_ref(vm->page_directory); - r = amdgpu_vm_clear_bo(adev, vm, pt); - if (r) { - amdgpu_bo_unref(&pt->shadow); - amdgpu_bo_unref(&pt); - goto error_free; - } - - if (pt->shadow) { - r = amdgpu_vm_clear_bo(adev, vm, pt->shadow); - if (r) { - amdgpu_bo_unref(&pt->shadow); - amdgpu_bo_unref(&pt); - goto error_free; - } - } - vm->page_tables[pt_idx].bo = pt; vm->page_tables[pt_idx].addr = 0; } @@ -1642,7 +1563,8 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm) AMDGPU_GEM_DOMAIN_VRAM, AMDGPU_GEM_CREATE_NO_CPU_ACCESS | AMDGPU_GEM_CREATE_SHADOW | - AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, + AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | + AMDGPU_GEM_CREATE_VRAM_CLEARED, NULL, NULL, &vm->page_directory); if (r) goto error_free_sched_entity; @@ -1651,24 +1573,11 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm) if (r) goto error_free_page_directory; - r = amdgpu_vm_clear_bo(adev, vm, vm->page_directory); - if (r) - goto error_unreserve; - - if (vm->page_directory->shadow) { - r = amdgpu_vm_clear_bo(adev, vm, vm->page_directory->shadow); - if (r) - goto error_unreserve; - } - vm->last_eviction_counter = atomic64_read(&adev->num_evictions); amdgpu_bo_unreserve(vm->page_directory); return 0; -error_unreserve: - amdgpu_bo_unreserve(vm->page_directory); - error_free_page_directory: amdgpu_bo_unref(&vm->page_directory->shadow); amdgpu_bo_unref(&vm->page_directory); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c index 180eed7c8bca..d710226a0fff 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c @@ -108,7 +108,7 @@ static int amdgpu_vram_mgr_new(struct ttm_mem_type_manager *man, lpfn = man->size; if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS || - amdgpu_vram_page_split == -1) { + place->lpfn || amdgpu_vram_page_split == -1) { pages_per_node = ~0ul; num_nodes = 1; } else { diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c index 1caff75ab9fc..1027f92de32b 100644 --- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c @@ -4202,11 +4202,6 @@ static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate) if (!gate) { /* turn the clocks on when decoding */ - ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, - AMD_CG_STATE_UNGATE); - if (ret) - return ret; - if (pi->caps_uvd_dpm || (adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0)) pi->smc_state_table.UvdBootLevel = 0; @@ -4223,9 +4218,6 @@ static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate) ret = ci_enable_uvd_dpm(adev, false); if (ret) return ret; - - ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, - AMD_CG_STATE_GATE); } return ret; @@ -5896,7 +5888,7 @@ static int ci_dpm_init(struct amdgpu_device *adev) pi->pcie_dpm_key_disabled = 0; pi->thermal_sclk_dpm_enabled = 0; - if (amdgpu_sclk_deep_sleep_en) + if (amdgpu_pp_feature_mask & SCLK_DEEP_SLEEP_MASK) pi->caps_sclk_ds = true; else pi->caps_sclk_ds = false; @@ -5999,7 +5991,7 @@ static int ci_dpm_init(struct amdgpu_device *adev) tmp |= CNB_PWRMGT_CNTL__DPM_ENABLED_MASK; break; default: - DRM_ERROR("Invalid PCC GPIO: %u!\n", gpio.shift); + DRM_INFO("Invalid PCC GPIO: %u!\n", gpio.shift); break; } WREG32_SMC(ixCNB_PWRMGT_CNTL, tmp); diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c index 352b5fad5a06..ba2b66be9022 100644 --- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c @@ -438,7 +438,7 @@ static int cz_dpm_init(struct amdgpu_device *adev) pi->caps_td_ramping = true; pi->caps_tcp_ramping = true; } - if (amdgpu_sclk_deep_sleep_en) + if (amdgpu_pp_feature_mask & SCLK_DEEP_SLEEP_MASK) pi->caps_sclk_ds = true; else pi->caps_sclk_ds = false; @@ -2111,9 +2111,8 @@ static void cz_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate) if (gate) { if (pi->caps_uvd_pg) { - /* disable clockgating so we can properly shut down the block */ ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, - AMD_CG_STATE_UNGATE); + AMD_CG_STATE_GATE); if (ret) { DRM_ERROR("UVD DPM Power Gating failed to set clockgating state\n"); return; @@ -2159,9 +2158,8 @@ static void cz_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate) return; } - /* enable clockgating. hw will dynamically gate/ungate clocks on the fly */ ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, - AMD_CG_STATE_GATE); + AMD_CG_STATE_UNGATE); if (ret) { DRM_ERROR("UVD DPM Power Gating Failed to set clockgating state\n"); return; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 65a954cb69ed..075aa0b1b075 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -3749,7 +3749,6 @@ static const struct amdgpu_display_funcs dce_v10_0_display_funcs = { .bandwidth_update = &dce_v10_0_bandwidth_update, .vblank_get_counter = &dce_v10_0_vblank_get_counter, .vblank_wait = &dce_v10_0_vblank_wait, - .is_display_hung = &dce_v10_0_is_display_hung, .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, .hpd_sense = &dce_v10_0_hpd_sense, diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index d807e876366b..a6717487ac78 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -3805,7 +3805,6 @@ static const struct amdgpu_display_funcs dce_v11_0_display_funcs = { .bandwidth_update = &dce_v11_0_bandwidth_update, .vblank_get_counter = &dce_v11_0_vblank_get_counter, .vblank_wait = &dce_v11_0_vblank_wait, - .is_display_hung = &dce_v11_0_is_display_hung, .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, .hpd_sense = &dce_v11_0_hpd_sense, diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index bc9f2f423270..15d98ef696a2 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -30,8 +30,19 @@ #include "atombios_encoders.h" #include "amdgpu_pll.h" #include "amdgpu_connectors.h" -#include "si/si_reg.h" -#include "si/sid.h" + +#include "bif/bif_3_0_d.h" +#include "bif/bif_3_0_sh_mask.h" +#include "oss/oss_1_0_d.h" +#include "oss/oss_1_0_sh_mask.h" +#include "gca/gfx_6_0_d.h" +#include "gca/gfx_6_0_sh_mask.h" +#include "gmc/gmc_6_0_d.h" +#include "gmc/gmc_6_0_sh_mask.h" +#include "dce/dce_6_0_d.h" +#include "dce/dce_6_0_sh_mask.h" +#include "gca/gfx_7_2_enum.h" +#include "si_enums.h" static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev); static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev); @@ -48,12 +59,12 @@ static const u32 crtc_offsets[6] = static const u32 hpd_offsets[] = { - DC_HPD1_INT_STATUS - DC_HPD1_INT_STATUS, - DC_HPD2_INT_STATUS - DC_HPD1_INT_STATUS, - DC_HPD3_INT_STATUS - DC_HPD1_INT_STATUS, - DC_HPD4_INT_STATUS - DC_HPD1_INT_STATUS, - DC_HPD5_INT_STATUS - DC_HPD1_INT_STATUS, - DC_HPD6_INT_STATUS - DC_HPD1_INT_STATUS, + mmDC_HPD1_INT_STATUS - mmDC_HPD1_INT_STATUS, + mmDC_HPD2_INT_STATUS - mmDC_HPD1_INT_STATUS, + mmDC_HPD3_INT_STATUS - mmDC_HPD1_INT_STATUS, + mmDC_HPD4_INT_STATUS - mmDC_HPD1_INT_STATUS, + mmDC_HPD5_INT_STATUS - mmDC_HPD1_INT_STATUS, + mmDC_HPD6_INT_STATUS - mmDC_HPD1_INT_STATUS, }; static const uint32_t dig_offsets[] = { @@ -73,32 +84,32 @@ static const struct { uint32_t hpd; } interrupt_status_offsets[6] = { { - .reg = DISP_INTERRUPT_STATUS, + .reg = mmDISP_INTERRUPT_STATUS, .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK, .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK, .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK }, { - .reg = DISP_INTERRUPT_STATUS_CONTINUE, + .reg = mmDISP_INTERRUPT_STATUS_CONTINUE, .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK, .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK, .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK }, { - .reg = DISP_INTERRUPT_STATUS_CONTINUE2, + .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2, .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK, .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK, .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK }, { - .reg = DISP_INTERRUPT_STATUS_CONTINUE3, + .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3, .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK, .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK, .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK }, { - .reg = DISP_INTERRUPT_STATUS_CONTINUE4, + .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4, .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK, .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK, .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK }, { - .reg = DISP_INTERRUPT_STATUS_CONTINUE5, + .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5, .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK, .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK, .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK @@ -119,7 +130,7 @@ static void dce_v6_0_audio_endpt_wreg(struct amdgpu_device *adev, static bool dce_v6_0_is_in_vblank(struct amdgpu_device *adev, int crtc) { - if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK) + if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) & CRTC_STATUS__CRTC_V_BLANK_MASK) return true; else return false; @@ -129,8 +140,8 @@ static bool dce_v6_0_is_counter_moving(struct amdgpu_device *adev, int crtc) { u32 pos1, pos2; - pos1 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]); - pos2 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]); + pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); + pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); if (pos1 != pos2) return true; @@ -152,7 +163,7 @@ static void dce_v6_0_vblank_wait(struct amdgpu_device *adev, int crtc) if (crtc >= adev->mode_info.num_crtc) return; - if (!(RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN)) + if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK)) return; /* depending on when we hit vblank, we may be close to active; if so, @@ -180,7 +191,7 @@ static u32 dce_v6_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) if (crtc >= adev->mode_info.num_crtc) return 0; else - return RREG32(CRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); + return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); } static void dce_v6_0_pageflip_interrupt_init(struct amdgpu_device *adev) @@ -220,16 +231,16 @@ static void dce_v6_0_page_flip(struct amdgpu_device *adev, struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; /* flip at hsync for async, default is vsync */ - WREG32(EVERGREEN_GRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ? - EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN : 0); + WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ? + GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0); /* update the scanout addresses */ - WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, + WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, upper_32_bits(crtc_base)); - WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, + WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, (u32)crtc_base); /* post the write */ - RREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); + RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); } static int dce_v6_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, @@ -237,8 +248,8 @@ static int dce_v6_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, { if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) return -EINVAL; - *vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + crtc_offsets[crtc]); - *position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]); + *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); + *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); return 0; @@ -261,7 +272,7 @@ static bool dce_v6_0_hpd_sense(struct amdgpu_device *adev, if (hpd >= adev->mode_info.num_hpd) return connected; - if (RREG32(DC_HPD1_INT_STATUS + hpd_offsets[hpd]) & DC_HPDx_SENSE) + if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) & DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK) connected = true; return connected; @@ -284,12 +295,12 @@ static void dce_v6_0_hpd_set_polarity(struct amdgpu_device *adev, if (hpd >= adev->mode_info.num_hpd) return; - tmp = RREG32(DC_HPD1_INT_CONTROL + hpd_offsets[hpd]); + tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); if (connected) - tmp &= ~DC_HPDx_INT_POLARITY; + tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK; else - tmp |= DC_HPDx_INT_POLARITY; - WREG32(DC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); + tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK; + WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); } /** @@ -312,9 +323,9 @@ static void dce_v6_0_hpd_init(struct amdgpu_device *adev) if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) continue; - tmp = RREG32(DC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); - tmp |= DC_HPDx_EN; - WREG32(DC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); + tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); + tmp |= DC_HPD1_CONTROL__DC_HPD1_EN_MASK; + WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { @@ -323,9 +334,9 @@ static void dce_v6_0_hpd_init(struct amdgpu_device *adev) * https://bugzilla.redhat.com/show_bug.cgi?id=726143 * also avoid interrupt storms during dpms. */ - tmp = RREG32(DC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); - tmp &= ~DC_HPDx_INT_EN; - WREG32(DC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); + tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); + tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK; + WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); continue; } @@ -355,9 +366,9 @@ static void dce_v6_0_hpd_fini(struct amdgpu_device *adev) if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) continue; - tmp = RREG32(DC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); - tmp &= ~DC_HPDx_EN; - WREG32(DC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0); + tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); + tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK; + WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0); amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); } @@ -365,14 +376,7 @@ static void dce_v6_0_hpd_fini(struct amdgpu_device *adev) static u32 dce_v6_0_hpd_get_gpio_reg(struct amdgpu_device *adev) { - return SI_DC_GPIO_HPD_A; -} - -static bool dce_v6_0_is_display_hung(struct amdgpu_device *adev) -{ - DRM_INFO("xxxx: dce_v6_0_is_display_hung ----no imp!!!!!\n"); - - return true; + return mmDC_GPIO_HPD_A; } static u32 evergreen_get_vblank_counter(struct amdgpu_device* adev, int crtc) @@ -380,7 +384,7 @@ static u32 evergreen_get_vblank_counter(struct amdgpu_device* adev, int crtc) if (crtc >= adev->mode_info.num_crtc) return 0; else - return RREG32(CRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); + return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); } static void dce_v6_0_stop_mc_access(struct amdgpu_device *adev, @@ -389,25 +393,25 @@ static void dce_v6_0_stop_mc_access(struct amdgpu_device *adev, u32 crtc_enabled, tmp, frame_count; int i, j; - save->vga_render_control = RREG32(VGA_RENDER_CONTROL); - save->vga_hdp_control = RREG32(VGA_HDP_CONTROL); + save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL); + save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL); /* disable VGA render */ - WREG32(VGA_RENDER_CONTROL, 0); + WREG32(mmVGA_RENDER_CONTROL, 0); /* blank the display controllers */ for (i = 0; i < adev->mode_info.num_crtc; i++) { - crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN; + crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK; if (crtc_enabled) { save->crtc_enabled[i] = true; - tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]); + tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); - if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) { + if (!(tmp & CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK)) { dce_v6_0_vblank_wait(adev, i); - WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); - tmp |= EVERGREEN_CRTC_BLANK_DATA_EN; - WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp); - WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); + WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); + tmp |= CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK; + WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); + WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); } /* wait for the next frame */ frame_count = evergreen_get_vblank_counter(adev, i); @@ -418,11 +422,11 @@ static void dce_v6_0_stop_mc_access(struct amdgpu_device *adev, } /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ - WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); - tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); - tmp &= ~EVERGREEN_CRTC_MASTER_EN; - WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); - WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); + WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); + tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); + tmp &= ~CRTC_CONTROL__CRTC_MASTER_EN_MASK; + WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); + WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); save->crtc_enabled[i] = false; /* ***** */ } else { @@ -439,41 +443,41 @@ static void dce_v6_0_resume_mc_access(struct amdgpu_device *adev, /* update crtc base addresses */ for (i = 0; i < adev->mode_info.num_crtc; i++) { - WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], + WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], upper_32_bits(adev->mc.vram_start)); - WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], + WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], upper_32_bits(adev->mc.vram_start)); - WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], + WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], (u32)adev->mc.vram_start); - WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], + WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], (u32)adev->mc.vram_start); } - WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start)); - WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)adev->mc.vram_start); + WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start)); + WREG32(mmVGA_MEMORY_BASE_ADDRESS, (u32)adev->mc.vram_start); /* unlock regs and wait for update */ for (i = 0; i < adev->mode_info.num_crtc; i++) { if (save->crtc_enabled[i]) { - tmp = RREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i]); + tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]); if ((tmp & 0x7) != 3) { tmp &= ~0x7; tmp |= 0x3; - WREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i], tmp); + WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp); } - tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]); - if (tmp & EVERGREEN_GRPH_UPDATE_LOCK) { - tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK; - WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp); + tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); + if (tmp & GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK) { + tmp &= ~GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK; + WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); } - tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]); + tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]); if (tmp & 1) { tmp &= ~1; - WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); + WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp); } for (j = 0; j < adev->usec_timeout; j++) { - tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]); - if ((tmp & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING) == 0) + tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); + if ((tmp & GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK) == 0) break; udelay(1); } @@ -481,9 +485,9 @@ static void dce_v6_0_resume_mc_access(struct amdgpu_device *adev, } /* Unlock vga access */ - WREG32(VGA_HDP_CONTROL, save->vga_hdp_control); + WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control); mdelay(1); - WREG32(VGA_RENDER_CONTROL, save->vga_render_control); + WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control); } @@ -491,8 +495,8 @@ static void dce_v6_0_set_vga_render_state(struct amdgpu_device *adev, bool render) { if (!render) - WREG32(R_000300_VGA_RENDER_CONTROL, - RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL); + WREG32(mmVGA_RENDER_CONTROL, + RREG32(mmVGA_RENDER_CONTROL) & VGA_VSTATUS_CNTL); } @@ -526,14 +530,14 @@ void dce_v6_0_disable_dce(struct amdgpu_device *adev) /*Disable crtc*/ for (i = 0; i < dce_v6_0_get_num_crtc(adev); i++) { - crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & - EVERGREEN_CRTC_MASTER_EN; + crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & + CRTC_CONTROL__CRTC_MASTER_EN_MASK; if (crtc_enabled) { - WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); - tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); - tmp &= ~EVERGREEN_CRTC_MASTER_EN; - WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); - WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); + WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); + tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); + tmp &= ~CRTC_CONTROL__CRTC_MASTER_EN_MASK; + WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); + WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); } } } @@ -569,19 +573,23 @@ static void dce_v6_0_program_fmt(struct drm_encoder *encoder) case 6: if (dither == AMDGPU_FMT_DITHER_ENABLE) /* XXX sort out optimal dither settings */ - tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE | - FMT_SPATIAL_DITHER_EN); + tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK | + FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK | + FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK); else - tmp |= FMT_TRUNCATE_EN; + tmp |= FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK; break; case 8: if (dither == AMDGPU_FMT_DITHER_ENABLE) /* XXX sort out optimal dither settings */ - tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE | - FMT_RGB_RANDOM_ENABLE | - FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH); + tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK | + FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK | + FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK | + FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK | + FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK); else - tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH); + tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK | + FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK); break; case 10: default: @@ -589,7 +597,7 @@ static void dce_v6_0_program_fmt(struct drm_encoder *encoder) break; } - WREG32(FMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); + WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); } /** @@ -603,7 +611,7 @@ static void dce_v6_0_program_fmt(struct drm_encoder *encoder) */ static u32 si_get_number_of_dram_channels(struct amdgpu_device *adev) { - u32 tmp = RREG32(MC_SHARED_CHMAP); + u32 tmp = RREG32(mmMC_SHARED_CHMAP); switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) { case 0: @@ -1100,28 +1108,28 @@ static void dce_v6_0_program_watermarks(struct amdgpu_device *adev, } /* select wm A */ - arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); + arb_control3 = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); tmp = arb_control3; tmp &= ~LATENCY_WATERMARK_MASK(3); tmp |= LATENCY_WATERMARK_MASK(1); - WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); - WREG32(DPG_PIPE_LATENCY_CONTROL + amdgpu_crtc->crtc_offset, - (LATENCY_LOW_WATERMARK(latency_watermark_a) | - LATENCY_HIGH_WATERMARK(line_time))); + WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); + WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, + ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) | + (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT))); /* select wm B */ - tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); + tmp = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); tmp &= ~LATENCY_WATERMARK_MASK(3); tmp |= LATENCY_WATERMARK_MASK(2); - WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); - WREG32(DPG_PIPE_LATENCY_CONTROL + amdgpu_crtc->crtc_offset, - (LATENCY_LOW_WATERMARK(latency_watermark_b) | - LATENCY_HIGH_WATERMARK(line_time))); + WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); + WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, + ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) | + (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT))); /* restore original selection */ - WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, arb_control3); + WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, arb_control3); /* write the priority marks */ - WREG32(PRIORITY_A_CNT + amdgpu_crtc->crtc_offset, priority_a_cnt); - WREG32(PRIORITY_B_CNT + amdgpu_crtc->crtc_offset, priority_b_cnt); + WREG32(mmPRIORITY_A_CNT + amdgpu_crtc->crtc_offset, priority_a_cnt); + WREG32(mmPRIORITY_B_CNT + amdgpu_crtc->crtc_offset, priority_b_cnt); /* save values for DPM */ amdgpu_crtc->line_time = line_time; @@ -1139,7 +1147,7 @@ static u32 dce_v6_0_line_buffer_adjust(struct amdgpu_device *adev, /* * Line Buffer Setup * There are 3 line buffers, each one shared by 2 display controllers. - * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between + * mmDC_LB_MEMORY_SPLIT controls how that line buffer is shared between * the display controllers. The paritioning is done via one of four * preset allocations specified in bits 21:20: * 0 - half lb @@ -1162,14 +1170,14 @@ static u32 dce_v6_0_line_buffer_adjust(struct amdgpu_device *adev, buffer_alloc = 0; } - WREG32(DC_LB_MEMORY_SPLIT + amdgpu_crtc->crtc_offset, + WREG32(mmDC_LB_MEMORY_SPLIT + amdgpu_crtc->crtc_offset, DC_LB_MEMORY_CONFIG(tmp)); - WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, - DMIF_BUFFERS_ALLOCATED(buffer_alloc)); + WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, + (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT)); for (i = 0; i < adev->usec_timeout; i++) { - if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & - DMIF_BUFFERS_ALLOCATED_COMPLETED) + if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & + PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK) break; udelay(1); } @@ -1411,12 +1419,12 @@ static void dce_v6_0_afmt_fini(struct amdgpu_device *adev) static const u32 vga_control_regs[6] = { - AVIVO_D1VGA_CONTROL, - AVIVO_D2VGA_CONTROL, - EVERGREEN_D3VGA_CONTROL, - EVERGREEN_D4VGA_CONTROL, - EVERGREEN_D5VGA_CONTROL, - EVERGREEN_D6VGA_CONTROL, + mmD1VGA_CONTROL, + mmD2VGA_CONTROL, + mmD3VGA_CONTROL, + mmD4VGA_CONTROL, + mmD5VGA_CONTROL, + mmD6VGA_CONTROL, }; static void dce_v6_0_vga_enable(struct drm_crtc *crtc, bool enable) @@ -1436,7 +1444,7 @@ static void dce_v6_0_grph_enable(struct drm_crtc *crtc, bool enable) struct drm_device *dev = crtc->dev; struct amdgpu_device *adev = dev->dev_private; - WREG32(EVERGREEN_GRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0); + WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0); } static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, @@ -1452,7 +1460,7 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, struct amdgpu_bo *abo; uint64_t fb_location, tiling_flags; uint32_t fb_format, fb_pitch_pixels, pipe_config; - u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE); + u32 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_NONE); u32 viewport_w, viewport_h; int r; bool bypass_lut = false; @@ -1496,64 +1504,64 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, switch (target_fb->pixel_format) { case DRM_FORMAT_C8: - fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) | - EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED)); + fb_format = (GRPH_DEPTH(GRPH_DEPTH_8BPP) | + GRPH_FORMAT(GRPH_FORMAT_INDEXED)); break; case DRM_FORMAT_XRGB4444: case DRM_FORMAT_ARGB4444: - fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | - EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB4444)); + fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) | + GRPH_FORMAT(GRPH_FORMAT_ARGB4444)); #ifdef __BIG_ENDIAN - fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); + fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16); #endif break; case DRM_FORMAT_XRGB1555: case DRM_FORMAT_ARGB1555: - fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | - EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555)); + fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) | + GRPH_FORMAT(GRPH_FORMAT_ARGB1555)); #ifdef __BIG_ENDIAN - fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); + fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16); #endif break; case DRM_FORMAT_BGRX5551: case DRM_FORMAT_BGRA5551: - fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | - EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA5551)); + fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) | + GRPH_FORMAT(GRPH_FORMAT_BGRA5551)); #ifdef __BIG_ENDIAN - fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); + fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16); #endif break; case DRM_FORMAT_RGB565: - fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | - EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565)); + fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) | + GRPH_FORMAT(GRPH_FORMAT_ARGB565)); #ifdef __BIG_ENDIAN - fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); + fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16); #endif break; case DRM_FORMAT_XRGB8888: case DRM_FORMAT_ARGB8888: - fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | - EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); + fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) | + GRPH_FORMAT(GRPH_FORMAT_ARGB8888)); #ifdef __BIG_ENDIAN - fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); + fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32); #endif break; case DRM_FORMAT_XRGB2101010: case DRM_FORMAT_ARGB2101010: - fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | - EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB2101010)); + fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) | + GRPH_FORMAT(GRPH_FORMAT_ARGB2101010)); #ifdef __BIG_ENDIAN - fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); + fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32); #endif /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ bypass_lut = true; break; case DRM_FORMAT_BGRX1010102: case DRM_FORMAT_BGRA1010102: - fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | - EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA1010102)); + fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) | + GRPH_FORMAT(GRPH_FORMAT_BGRA1010102)); #ifdef __BIG_ENDIAN - fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); + fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32); #endif /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ bypass_lut = true; @@ -1573,75 +1581,75 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); - fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks); - fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1); - fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split); - fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw); - fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh); - fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect); + fb_format |= GRPH_NUM_BANKS(num_banks); + fb_format |= GRPH_ARRAY_MODE(GRPH_ARRAY_2D_TILED_THIN1); + fb_format |= GRPH_TILE_SPLIT(tile_split); + fb_format |= GRPH_BANK_WIDTH(bankw); + fb_format |= GRPH_BANK_HEIGHT(bankh); + fb_format |= GRPH_MACRO_TILE_ASPECT(mtaspect); } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { - fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1); + fb_format |= GRPH_ARRAY_MODE(GRPH_ARRAY_1D_TILED_THIN1); } pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); - fb_format |= SI_GRPH_PIPE_CONFIG(pipe_config); + fb_format |= GRPH_PIPE_CONFIG(pipe_config); dce_v6_0_vga_enable(crtc, false); /* Make sure surface address is updated at vertical blank rather than * horizontal blank */ - WREG32(EVERGREEN_GRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0); + WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0); - WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, + WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, upper_32_bits(fb_location)); - WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, + WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, upper_32_bits(fb_location)); - WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, - (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); - WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, - (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); - WREG32(EVERGREEN_GRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); - WREG32(EVERGREEN_GRPH_SWAP_CONTROL + amdgpu_crtc->crtc_offset, fb_swap); + WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, + (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); + WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, + (u32) fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); + WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); + WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); /* * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to * retain the full precision throughout the pipeline. */ - WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + amdgpu_crtc->crtc_offset, - (bypass_lut ? EVERGREEN_LUT_10BIT_BYPASS_EN : 0), - ~EVERGREEN_LUT_10BIT_BYPASS_EN); + WREG32_P(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, + (bypass_lut ? GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK : 0), + ~GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK); if (bypass_lut) DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); - WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); - WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); - WREG32(EVERGREEN_GRPH_X_START + amdgpu_crtc->crtc_offset, 0); - WREG32(EVERGREEN_GRPH_Y_START + amdgpu_crtc->crtc_offset, 0); - WREG32(EVERGREEN_GRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); - WREG32(EVERGREEN_GRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); + WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); + WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); + WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); + WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); + WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); + WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); - WREG32(EVERGREEN_GRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); + WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); dce_v6_0_grph_enable(crtc, true); - WREG32(EVERGREEN_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, + WREG32(mmDESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, target_fb->height); x &= ~3; y &= ~1; - WREG32(EVERGREEN_VIEWPORT_START + amdgpu_crtc->crtc_offset, + WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, (x << 16) | y); viewport_w = crtc->mode.hdisplay; viewport_h = (crtc->mode.vdisplay + 1) & ~1; - WREG32(EVERGREEN_VIEWPORT_SIZE + amdgpu_crtc->crtc_offset, + WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, (viewport_w << 16) | viewport_h); /* set pageflip to happen anywhere in vblank interval */ - WREG32(EVERGREEN_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); + WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); if (!atomic && fb && fb != crtc->primary->fb) { amdgpu_fb = to_amdgpu_framebuffer(fb); @@ -1668,10 +1676,10 @@ static void dce_v6_0_set_interleave(struct drm_crtc *crtc, struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); if (mode->flags & DRM_MODE_FLAG_INTERLACE) - WREG32(EVERGREEN_DATA_FORMAT + amdgpu_crtc->crtc_offset, - EVERGREEN_INTERLEAVE_EN); + WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, + INTERLEAVE_EN); else - WREG32(EVERGREEN_DATA_FORMAT + amdgpu_crtc->crtc_offset, 0); + WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 0); } static void dce_v6_0_crtc_load_lut(struct drm_crtc *crtc) @@ -1684,54 +1692,52 @@ static void dce_v6_0_crtc_load_lut(struct drm_crtc *crtc) DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); - WREG32(NI_INPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, - (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) | - NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS))); - WREG32(NI_PRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, - NI_GRPH_PRESCALE_BYPASS); - WREG32(NI_PRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, - NI_OVL_PRESCALE_BYPASS); - WREG32(NI_INPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, - (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) | - NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT))); - - + WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, + ((0 << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) | + (0 << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT))); + WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, + PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK); + WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, + PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK); + WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, + ((0 << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) | + (0 << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT))); - WREG32(EVERGREEN_DC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); + WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); - WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); - WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); - WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); + WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); + WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); + WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); - WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); - WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); - WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); + WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); + WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); + WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); - WREG32(EVERGREEN_DC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); - WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); + WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); + WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); - WREG32(EVERGREEN_DC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); + WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); for (i = 0; i < 256; i++) { - WREG32(EVERGREEN_DC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, + WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, (amdgpu_crtc->lut_r[i] << 20) | (amdgpu_crtc->lut_g[i] << 10) | (amdgpu_crtc->lut_b[i] << 0)); } - WREG32(NI_DEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, - (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | - NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | - NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | - NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS))); - WREG32(NI_GAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, - (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) | - NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS))); - WREG32(NI_REGAMMA_CONTROL + amdgpu_crtc->crtc_offset, - (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) | - NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS))); - WREG32(NI_OUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, - (NI_OUTPUT_CSC_GRPH_MODE(0) | - NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS))); + WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, + ((0 << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) | + (0 << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) | + ICON_DEGAMMA_MODE(0) | + (0 << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT))); + WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, + ((0 << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) | + (0 << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT))); + WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, + ((0 << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) | + (0 << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT))); + WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, + ((0 << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) | + (0 << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT))); /* XXX match this to the depth of the crtc fmt block, move to modeset? */ WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0); @@ -1810,12 +1816,12 @@ static void dce_v6_0_lock_cursor(struct drm_crtc *crtc, bool lock) struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); uint32_t cur_lock; - cur_lock = RREG32(EVERGREEN_CUR_UPDATE + amdgpu_crtc->crtc_offset); + cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); if (lock) - cur_lock |= EVERGREEN_CURSOR_UPDATE_LOCK; + cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK; else - cur_lock &= ~EVERGREEN_CURSOR_UPDATE_LOCK; - WREG32(EVERGREEN_CUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); + cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK; + WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); } static void dce_v6_0_hide_cursor(struct drm_crtc *crtc) @@ -1823,9 +1829,9 @@ static void dce_v6_0_hide_cursor(struct drm_crtc *crtc) struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); struct amdgpu_device *adev = crtc->dev->dev_private; - WREG32_IDX(EVERGREEN_CUR_CONTROL + amdgpu_crtc->crtc_offset, - EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) | - EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2)); + WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, + (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) | + (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT)); } @@ -1835,15 +1841,15 @@ static void dce_v6_0_show_cursor(struct drm_crtc *crtc) struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); struct amdgpu_device *adev = crtc->dev->dev_private; - WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, + WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, upper_32_bits(amdgpu_crtc->cursor_addr)); - WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, + WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, lower_32_bits(amdgpu_crtc->cursor_addr)); - WREG32_IDX(EVERGREEN_CUR_CONTROL + amdgpu_crtc->crtc_offset, - EVERGREEN_CURSOR_EN | - EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) | - EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2)); + WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, + CUR_CONTROL__CURSOR_EN_MASK | + (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) | + (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT)); } @@ -1870,9 +1876,9 @@ static int dce_v6_0_cursor_move_locked(struct drm_crtc *crtc, y = 0; } - WREG32(EVERGREEN_CUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); - WREG32(EVERGREEN_CUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); - WREG32(EVERGREEN_CUR_SIZE + amdgpu_crtc->crtc_offset, + WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); + WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); + WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, ((w - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); amdgpu_crtc->cursor_x = x; @@ -2478,14 +2484,14 @@ static void dce_v6_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev, switch (state) { case AMDGPU_IRQ_STATE_DISABLE: - interrupt_mask = RREG32(INT_MASK + reg_block); + interrupt_mask = RREG32(mmINT_MASK + reg_block); interrupt_mask &= ~VBLANK_INT_MASK; - WREG32(INT_MASK + reg_block, interrupt_mask); + WREG32(mmINT_MASK + reg_block, interrupt_mask); break; case AMDGPU_IRQ_STATE_ENABLE: - interrupt_mask = RREG32(INT_MASK + reg_block); + interrupt_mask = RREG32(mmINT_MASK + reg_block); interrupt_mask |= VBLANK_INT_MASK; - WREG32(INT_MASK + reg_block, interrupt_mask); + WREG32(mmINT_MASK + reg_block, interrupt_mask); break; default: break; @@ -2513,14 +2519,14 @@ static int dce_v6_0_set_hpd_interrupt_state(struct amdgpu_device *adev, switch (state) { case AMDGPU_IRQ_STATE_DISABLE: - dc_hpd_int_cntl = RREG32(DC_HPD1_INT_CONTROL + hpd_offsets[type]); + dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]); dc_hpd_int_cntl &= ~DC_HPDx_INT_EN; - WREG32(DC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); + WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); break; case AMDGPU_IRQ_STATE_ENABLE: - dc_hpd_int_cntl = RREG32(DC_HPD1_INT_CONTROL + hpd_offsets[type]); + dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]); dc_hpd_int_cntl |= DC_HPDx_INT_EN; - WREG32(DC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); + WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); break; default: break; @@ -2588,7 +2594,7 @@ static int dce_v6_0_crtc_irq(struct amdgpu_device *adev, switch (entry->src_data) { case 0: /* vblank */ if (disp_int & interrupt_status_offsets[crtc].vblank) - WREG32(VBLANK_STATUS + crtc_offsets[crtc], VBLANK_ACK); + WREG32(mmVBLANK_STATUS + crtc_offsets[crtc], VBLANK_ACK); else DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); @@ -2599,7 +2605,7 @@ static int dce_v6_0_crtc_irq(struct amdgpu_device *adev, break; case 1: /* vline */ if (disp_int & interrupt_status_offsets[crtc].vline) - WREG32(VLINE_STATUS + crtc_offsets[crtc], VLINE_ACK); + WREG32(mmVLINE_STATUS + crtc_offsets[crtc], VLINE_ACK); else DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); @@ -2625,12 +2631,12 @@ static int dce_v6_0_set_pageflip_interrupt_state(struct amdgpu_device *adev, return -EINVAL; } - reg = RREG32(GRPH_INT_CONTROL + crtc_offsets[type]); + reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); if (state == AMDGPU_IRQ_STATE_DISABLE) - WREG32(GRPH_INT_CONTROL + crtc_offsets[type], + WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); else - WREG32(GRPH_INT_CONTROL + crtc_offsets[type], + WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); return 0; @@ -2653,9 +2659,9 @@ static int dce_v6_0_pageflip_irq(struct amdgpu_device *adev, return -EINVAL; } - if (RREG32(GRPH_INT_STATUS + crtc_offsets[crtc_id]) & + if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) & GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) - WREG32(GRPH_INT_STATUS + crtc_offsets[crtc_id], + WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id], GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); /* IRQ could occur when in initial stage */ @@ -2706,9 +2712,9 @@ static int dce_v6_0_hpd_irq(struct amdgpu_device *adev, mask = interrupt_status_offsets[hpd].hpd; if (disp_int & mask) { - tmp = RREG32(DC_HPD1_INT_CONTROL + hpd_offsets[hpd]); + tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK; - WREG32(DC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); + WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); schedule_work(&adev->hotplug_work); DRM_INFO("IH: HPD%d\n", hpd + 1); } @@ -3024,7 +3030,6 @@ static const struct amdgpu_display_funcs dce_v6_0_display_funcs = { .bandwidth_update = &dce_v6_0_bandwidth_update, .vblank_get_counter = &dce_v6_0_vblank_get_counter, .vblank_wait = &dce_v6_0_vblank_wait, - .is_display_hung = &dce_v6_0_is_display_hung, .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, .hpd_sense = &dce_v6_0_hpd_sense, diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index 4ae59914bc32..a699896eeabc 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -3586,7 +3586,6 @@ static const struct amdgpu_display_funcs dce_v8_0_display_funcs = { .bandwidth_update = &dce_v8_0_bandwidth_update, .vblank_get_counter = &dce_v8_0_vblank_get_counter, .vblank_wait = &dce_v8_0_vblank_wait, - .is_display_hung = &dce_v8_0_is_display_hung, .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, .hpd_sense = &dce_v8_0_hpd_sense, diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c index 1d93e123532d..e4a5a5ac0ff3 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c @@ -95,11 +95,6 @@ static u32 dce_virtual_hpd_get_gpio_reg(struct amdgpu_device *adev) return 0; } -static bool dce_virtual_is_display_hung(struct amdgpu_device *adev) -{ - return false; -} - static void dce_virtual_stop_mc_access(struct amdgpu_device *adev, struct amdgpu_mode_mc_save *save) { @@ -684,7 +679,6 @@ static const struct amdgpu_display_funcs dce_virtual_display_funcs = { .bandwidth_update = &dce_virtual_bandwidth_update, .vblank_get_counter = &dce_virtual_vblank_get_counter, .vblank_wait = &dce_virtual_vblank_wait, - .is_display_hung = &dce_virtual_is_display_hung, .backlight_set_level = NULL, .backlight_get_level = NULL, .hpd_sense = &dce_virtual_hpd_sense, diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index 21c086e02e7b..879a94bbfe12 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c @@ -26,15 +26,18 @@ #include "amdgpu_gfx.h" #include "amdgpu_ucode.h" #include "si/clearstate_si.h" -#include "si/sid.h" - -#define GFX6_NUM_GFX_RINGS 1 -#define GFX6_NUM_COMPUTE_RINGS 2 -#define STATIC_PER_CU_PG_ENABLE (1 << 3) -#define DYN_PER_CU_PG_ENABLE (1 << 2) -#define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90 -#define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D - +#include "bif/bif_3_0_d.h" +#include "bif/bif_3_0_sh_mask.h" +#include "oss/oss_1_0_d.h" +#include "oss/oss_1_0_sh_mask.h" +#include "gca/gfx_6_0_d.h" +#include "gca/gfx_6_0_sh_mask.h" +#include "gmc/gmc_6_0_d.h" +#include "gmc/gmc_6_0_sh_mask.h" +#include "dce/dce_6_0_d.h" +#include "dce/dce_6_0_sh_mask.h" +#include "gca/gfx_7_2_enum.h" +#include "si_enums.h" static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev); static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev); @@ -70,6 +73,15 @@ static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *bu //static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev); static void gfx_v6_0_init_pg(struct amdgpu_device *adev); +#define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT) +#define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT) +#define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT) +#define MICRO_TILE_MODE(x) ((x) << 0) +#define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT) +#define BANK_WIDTH(x) ((x) << 14) +#define BANK_HEIGHT(x) ((x) << 16) +#define MACRO_TILE_ASPECT(x) ((x) << 18) +#define NUM_BANKS(x) ((x) << 20) static const u32 verde_rlc_save_restore_register_list[] = { @@ -400,8 +412,8 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) } if (adev->asic_type == CHIP_VERDE || - adev->asic_type == CHIP_OLAND || - adev->asic_type == CHIP_HAINAN) { + adev->asic_type == CHIP_OLAND || + adev->asic_type == CHIP_HAINAN) { for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { switch (reg_offset) { case 0: @@ -414,7 +426,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); break; - case 1: + case 1: gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P4_8x16) | @@ -434,7 +446,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); break; - case 3: + case 3: gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P4_8x16) | @@ -444,7 +456,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); break; - case 4: + case 4: gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P4_8x16) | @@ -454,7 +466,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); break; - case 5: + case 5: gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P4_8x16) | @@ -464,7 +476,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); break; - case 6: + case 6: gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P4_8x16) | @@ -474,7 +486,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); break; - case 7: + case 7: gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P4_8x16) | @@ -484,7 +496,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); break; - case 8: + case 8: gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P4_8x16) | @@ -494,7 +506,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); break; - case 9: + case 9: gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P4_8x16) | @@ -504,7 +516,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); break; - case 10: + case 10: gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P4_8x16) | @@ -514,7 +526,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); break; - case 11: + case 11: gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P4_8x16) | @@ -524,7 +536,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); break; - case 12: + case 12: gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P4_8x16) | @@ -534,7 +546,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); break; - case 13: + case 13: gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P4_8x16) | @@ -544,7 +556,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); break; - case 14: + case 14: gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P4_8x16) | @@ -554,7 +566,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); break; - case 15: + case 15: gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P4_8x16) | @@ -564,7 +576,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); break; - case 16: + case 16: gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P4_8x16) | @@ -574,7 +586,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); break; - case 17: + case 17: gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P4_8x16) | @@ -584,7 +596,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); break; - case 21: + case 21: gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | @@ -594,7 +606,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); break; - case 22: + case 22: gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | @@ -604,7 +616,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); break; - case 23: + case 23: gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | @@ -614,7 +626,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); break; - case 24: + case 24: gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | @@ -624,7 +636,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); break; - case 25: + case 25: gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | @@ -639,7 +651,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) break; } adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; - WREG32(GB_TILE_MODE0 + reg_offset, gb_tile_moden); + WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); } } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) { for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { @@ -879,7 +891,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) break; } adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; - WREG32(GB_TILE_MODE0 + reg_offset, gb_tile_moden); + WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); } } else{ @@ -894,19 +906,23 @@ static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 data; if (instance == 0xffffffff) - data = INSTANCE_BROADCAST_WRITES; + data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); else - data = INSTANCE_INDEX(instance); + data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) - data |= SH_BROADCAST_WRITES | SE_BROADCAST_WRITES; + data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | + GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK; else if (se_num == 0xffffffff) - data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num); + data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK | + (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT); else if (sh_num == 0xffffffff) - data |= SH_BROADCAST_WRITES | SE_INDEX(se_num); + data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | + (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); else - data |= SH_INDEX(sh_num) | SE_INDEX(se_num); - WREG32(GRBM_GFX_INDEX, data); + data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) | + (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); + WREG32(mmGRBM_GFX_INDEX, data); } static u32 gfx_v6_0_create_bitmask(u32 bit_width) @@ -920,11 +936,11 @@ static u32 gfx_v6_0_get_rb_disabled(struct amdgpu_device *adev, { u32 data, mask; - data = RREG32(CC_RB_BACKEND_DISABLE); - data &= BACKEND_DISABLE_MASK; - data |= RREG32(GC_USER_RB_BACKEND_DISABLE); + data = RREG32(mmCC_RB_BACKEND_DISABLE); + data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; + data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE); - data >>= BACKEND_DISABLE_SHIFT; + data >>= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; mask = gfx_v6_0_create_bitmask(max_rb_num_per_se / sh_per_se); @@ -936,14 +952,23 @@ static void gfx_v6_0_raster_config(struct amdgpu_device *adev, u32 *rconf) switch (adev->asic_type) { case CHIP_TAHITI: case CHIP_PITCAIRN: - *rconf |= RB_XSEL2(2) | RB_XSEL | PKR_MAP(2) | PKR_YSEL(1) | - SE_MAP(2) | SE_XSEL(2) | SE_YSEL(2); + *rconf |= + (2 << PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT) | + (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) | + (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) | + (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT) | + (2 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT) | + (2 << PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT) | + (2 << PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT); break; case CHIP_VERDE: - *rconf |= RB_XSEL | PKR_MAP(2) | PKR_YSEL(1); + *rconf |= + (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) | + (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) | + (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT); break; case CHIP_OLAND: - *rconf |= RB_YSEL; + *rconf |= (1 << PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT); break; case CHIP_HAINAN: *rconf |= 0x0; @@ -981,24 +1006,24 @@ static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev, int idx = (se / 2) * 2; if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { - raster_config_se &= ~SE_MAP_MASK; + raster_config_se &= ~PA_SC_RASTER_CONFIG__SE_MAP_MASK; if (!se_mask[idx]) { - raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3); + raster_config_se |= RASTER_CONFIG_SE_MAP_3 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT; } else { - raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0); + raster_config_se |= RASTER_CONFIG_SE_MAP_0 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT; } } pkr0_mask &= rb_mask; pkr1_mask &= rb_mask; if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) { - raster_config_se &= ~PKR_MAP_MASK; + raster_config_se &= ~PA_SC_RASTER_CONFIG__PKR_MAP_MASK; if (!pkr0_mask) { - raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3); + raster_config_se |= RASTER_CONFIG_PKR_MAP_3 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT; } else { - raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0); + raster_config_se |= RASTER_CONFIG_PKR_MAP_0 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT; } } @@ -1009,14 +1034,14 @@ static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev, rb0_mask &= rb_mask; rb1_mask &= rb_mask; if (!rb0_mask || !rb1_mask) { - raster_config_se &= ~RB_MAP_PKR0_MASK; + raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK; if (!rb0_mask) { raster_config_se |= - RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3); + RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT; } else { raster_config_se |= - RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0); + RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT; } } @@ -1026,14 +1051,14 @@ static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev, rb0_mask &= rb_mask; rb1_mask &= rb_mask; if (!rb0_mask || !rb1_mask) { - raster_config_se &= ~RB_MAP_PKR1_MASK; + raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK; if (!rb0_mask) { raster_config_se |= - RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3); + RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT; } else { raster_config_se |= - RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0); + RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT; } } } @@ -1041,7 +1066,7 @@ static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev, /* GRBM_GFX_INDEX has a different offset on SI */ gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff); - WREG32(PA_SC_RASTER_CONFIG, raster_config_se); + WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se); } /* GRBM_GFX_INDEX has a different offset on SI */ @@ -1063,7 +1088,7 @@ static void gfx_v6_0_setup_rb(struct amdgpu_device *adev, for (j = 0; j < sh_per_se; j++) { gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff); data = gfx_v6_0_get_rb_disabled(adev, max_rb_num_per_se, sh_per_se); - disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH); + disabled_rbs |= data << ((i * sh_per_se + j) * 2); } } gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); @@ -1105,7 +1130,7 @@ static void gfx_v6_0_setup_rb(struct amdgpu_device *adev, if (!adev->gfx.config.backend_enable_mask || adev->gfx.config.num_rbs >= num_rb_pipes) - WREG32(PA_SC_RASTER_CONFIG, data); + WREG32(mmPA_SC_RASTER_CONFIG, data); else gfx_v6_0_write_harvested_raster_configs(adev, data, adev->gfx.config.backend_enable_mask, @@ -1124,11 +1149,11 @@ static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev, u32 cu_per_sh) { u32 data, mask; - data = RREG32(CC_GC_SHADER_ARRAY_CONFIG); - data &= INACTIVE_CUS_MASK; - data |= RREG32(GC_USER_SHADER_ARRAY_CONFIG); + data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG); + data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; + data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); - data >>= INACTIVE_CUS_SHIFT; + data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; mask = gfx_v6_0_create_bitmask(cu_per_sh); @@ -1148,7 +1173,7 @@ static void gfx_v6_0_setup_spi(struct amdgpu_device *adev, for (i = 0; i < se_num; i++) { for (j = 0; j < sh_per_se; j++) { gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff); - data = RREG32(SPI_STATIC_THREAD_MGMT_3); + data = RREG32(mmSPI_STATIC_THREAD_MGMT_3); active_cu = gfx_v6_0_get_cu_enabled(adev, cu_per_sh); mask = 1; @@ -1156,7 +1181,7 @@ static void gfx_v6_0_setup_spi(struct amdgpu_device *adev, mask <<= k; if (active_cu & mask) { data &= ~mask; - WREG32(SPI_STATIC_THREAD_MGMT_3, data); + WREG32(mmSPI_STATIC_THREAD_MGMT_3, data); break; } } @@ -1209,7 +1234,6 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device *adev) adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; break; - case CHIP_VERDE: adev->gfx.config.max_shader_engines = 1; adev->gfx.config.max_tile_pipes = 4; @@ -1266,18 +1290,18 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device *adev) break; } - WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); - WREG32(SRBM_INT_CNTL, 1); - WREG32(SRBM_INT_ACK, 1); + WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT)); + WREG32(mmSRBM_INT_CNTL, 1); + WREG32(mmSRBM_INT_ACK, 1); - WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN); + WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); - mc_shared_chmap = RREG32(MC_SHARED_CHMAP); - mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); + mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP); + mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; adev->gfx.config.mem_max_burst_length_bytes = 256; - tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT; + tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT; adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; if (adev->gfx.config.mem_row_size_in_kb > 4) adev->gfx.config.mem_row_size_in_kb = 4; @@ -1285,32 +1309,33 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device *adev) adev->gfx.config.num_gpus = 1; adev->gfx.config.multi_gpu_tile_size = 64; - gb_addr_config &= ~ROW_SIZE_MASK; + gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK; switch (adev->gfx.config.mem_row_size_in_kb) { case 1: default: - gb_addr_config |= ROW_SIZE(0); + gb_addr_config |= 0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; break; case 2: - gb_addr_config |= ROW_SIZE(1); + gb_addr_config |= 1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; break; case 4: - gb_addr_config |= ROW_SIZE(2); + gb_addr_config |= 2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; break; } adev->gfx.config.gb_addr_config = gb_addr_config; - WREG32(GB_ADDR_CONFIG, gb_addr_config); - WREG32(DMIF_ADDR_CONFIG, gb_addr_config); - WREG32(DMIF_ADDR_CALC, gb_addr_config); - WREG32(HDP_ADDR_CONFIG, gb_addr_config); - WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); - WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); + WREG32(mmGB_ADDR_CONFIG, gb_addr_config); + WREG32(mmDMIF_ADDR_CONFIG, gb_addr_config); + WREG32(mmDMIF_ADDR_CALC, gb_addr_config); + WREG32(mmHDP_ADDR_CONFIG, gb_addr_config); + WREG32(mmDMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); + WREG32(mmDMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); + #if 0 if (adev->has_uvd) { - WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config); - WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); - WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); + WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config); + WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); + WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); } #endif gfx_v6_0_tiling_mode_table_init(adev); @@ -1325,45 +1350,48 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device *adev) gfx_v6_0_get_cu_info(adev); - WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | - ROQ_IB2_START(0x2b))); - WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60)); + WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) | + (0x2b << CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT))); + WREG32(mmCP_MEQ_THRESHOLDS, (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) | + (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT)); - sx_debug_1 = RREG32(SX_DEBUG_1); - WREG32(SX_DEBUG_1, sx_debug_1); + sx_debug_1 = RREG32(mmSX_DEBUG_1); + WREG32(mmSX_DEBUG_1, sx_debug_1); - WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); + WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT)); - WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(adev->gfx.config.sc_prim_fifo_size_frontend) | - SC_BACKEND_PRIM_FIFO_SIZE(adev->gfx.config.sc_prim_fifo_size_backend) | - SC_HIZ_TILE_FIFO_SIZE(adev->gfx.config.sc_hiz_tile_fifo_size) | - SC_EARLYZ_TILE_FIFO_SIZE(adev->gfx.config.sc_earlyz_tile_fifo_size))); + WREG32(mmPA_SC_FIFO_SIZE, ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) | + (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | + (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | + (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT))); - WREG32(VGT_NUM_INSTANCES, 1); - WREG32(CP_PERFMON_CNTL, 0); - WREG32(SQ_CONFIG, 0); - WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | - FORCE_EOV_MAX_REZ_CNT(255))); + WREG32(mmVGT_NUM_INSTANCES, 1); + WREG32(mmCP_PERFMON_CNTL, 0); + WREG32(mmSQ_CONFIG, 0); + WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) | + (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT))); - WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) | - AUTO_INVLD_EN(ES_AND_GS_AUTO)); + WREG32(mmVGT_CACHE_INVALIDATION, + (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) | + (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT)); - WREG32(VGT_GS_VERTEX_REUSE, 16); - WREG32(PA_SC_LINE_STIPPLE_STATE, 0); + WREG32(mmVGT_GS_VERTEX_REUSE, 16); + WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0); - WREG32(CB_PERFCOUNTER0_SELECT0, 0); - WREG32(CB_PERFCOUNTER0_SELECT1, 0); - WREG32(CB_PERFCOUNTER1_SELECT0, 0); - WREG32(CB_PERFCOUNTER1_SELECT1, 0); - WREG32(CB_PERFCOUNTER2_SELECT0, 0); - WREG32(CB_PERFCOUNTER2_SELECT1, 0); - WREG32(CB_PERFCOUNTER3_SELECT0, 0); - WREG32(CB_PERFCOUNTER3_SELECT1, 0); + WREG32(mmCB_PERFCOUNTER0_SELECT0, 0); + WREG32(mmCB_PERFCOUNTER0_SELECT1, 0); + WREG32(mmCB_PERFCOUNTER1_SELECT0, 0); + WREG32(mmCB_PERFCOUNTER1_SELECT1, 0); + WREG32(mmCB_PERFCOUNTER2_SELECT0, 0); + WREG32(mmCB_PERFCOUNTER2_SELECT1, 0); + WREG32(mmCB_PERFCOUNTER3_SELECT0, 0); + WREG32(mmCB_PERFCOUNTER3_SELECT1, 0); - hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); - WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); + hdp_host_path_cntl = RREG32(mmHDP_HOST_PATH_CNTL); + WREG32(mmHDP_HOST_PATH_CNTL, hdp_host_path_cntl); - WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); + WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK | + (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT)); udelay(50); } @@ -1374,7 +1402,7 @@ static void gfx_v6_0_scratch_init(struct amdgpu_device *adev) int i; adev->gfx.scratch.num_reg = 7; - adev->gfx.scratch.reg_base = SCRATCH_REG0; + adev->gfx.scratch.reg_base = mmSCRATCH_REG0; for (i = 0; i < adev->gfx.scratch.num_reg; i++) { adev->gfx.scratch.free[i] = true; adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i; @@ -1430,11 +1458,18 @@ static void gfx_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | WRITE_DATA_DST_SEL(0))); - amdgpu_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL); + amdgpu_ring_write(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL); amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, 0x1); } +static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring) +{ + amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); + amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) | + EVENT_INDEX(0)); +} + /** * gfx_v6_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp * @@ -1448,7 +1483,7 @@ static void gfx_v6_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | WRITE_DATA_DST_SEL(0))); - amdgpu_ring_write(ring, HDP_DEBUG0); + amdgpu_ring_write(ring, mmHDP_DEBUG0); amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, 0x1); } @@ -1460,7 +1495,7 @@ static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; /* flush read cache over gart */ amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); - amdgpu_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START)); + amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START)); amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA | @@ -1475,7 +1510,8 @@ static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5)); amdgpu_ring_write(ring, addr & 0xfffffffc); amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | - DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); + ((write64bit ? 2 : 1) << CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT) | + ((int_sel ? 2 : 0) << CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT)); amdgpu_ring_write(ring, lower_32_bits(seq)); amdgpu_ring_write(ring, upper_32_bits(seq)); } @@ -1578,11 +1614,13 @@ err1: static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) { int i; - if (enable) - WREG32(CP_ME_CNTL, 0); - else { - WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT)); - WREG32(SCRATCH_UMSK, 0); + if (enable) { + WREG32(mmCP_ME_CNTL, 0); + } else { + WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | + CP_ME_CNTL__PFP_HALT_MASK | + CP_ME_CNTL__CE_HALT_MASK)); + WREG32(mmSCRATCH_UMSK, 0); for (i = 0; i < adev->gfx.num_gfx_rings; i++) adev->gfx.gfx_ring[i].ready = false; for (i = 0; i < adev->gfx.num_compute_rings; i++) @@ -1616,34 +1654,33 @@ static int gfx_v6_0_cp_gfx_load_microcode(struct amdgpu_device *adev) fw_data = (const __le32 *) (adev->gfx.pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; - WREG32(CP_PFP_UCODE_ADDR, 0); + WREG32(mmCP_PFP_UCODE_ADDR, 0); for (i = 0; i < fw_size; i++) - WREG32(CP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); - WREG32(CP_PFP_UCODE_ADDR, 0); + WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); + WREG32(mmCP_PFP_UCODE_ADDR, 0); /* CE */ fw_data = (const __le32 *) (adev->gfx.ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; - WREG32(CP_CE_UCODE_ADDR, 0); + WREG32(mmCP_CE_UCODE_ADDR, 0); for (i = 0; i < fw_size; i++) - WREG32(CP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); - WREG32(CP_CE_UCODE_ADDR, 0); + WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); + WREG32(mmCP_CE_UCODE_ADDR, 0); /* ME */ fw_data = (const __be32 *) (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; - WREG32(CP_ME_RAM_WADDR, 0); + WREG32(mmCP_ME_RAM_WADDR, 0); for (i = 0; i < fw_size; i++) - WREG32(CP_ME_RAM_DATA, le32_to_cpup(fw_data++)); - WREG32(CP_ME_RAM_WADDR, 0); - + WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); + WREG32(mmCP_ME_RAM_WADDR, 0); - WREG32(CP_PFP_UCODE_ADDR, 0); - WREG32(CP_CE_UCODE_ADDR, 0); - WREG32(CP_ME_RAM_WADDR, 0); - WREG32(CP_ME_RAM_RADDR, 0); + WREG32(mmCP_PFP_UCODE_ADDR, 0); + WREG32(mmCP_CE_UCODE_ADDR, 0); + WREG32(mmCP_ME_RAM_WADDR, 0); + WREG32(mmCP_ME_RAM_RADDR, 0); return 0; } @@ -1720,14 +1757,14 @@ static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev) int r; u64 rptr_addr; - WREG32(CP_SEM_WAIT_TIMER, 0x0); - WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); + WREG32(mmCP_SEM_WAIT_TIMER, 0x0); + WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); /* Set the write pointer delay */ - WREG32(CP_RB_WPTR_DELAY, 0); + WREG32(mmCP_RB_WPTR_DELAY, 0); - WREG32(CP_DEBUG, 0); - WREG32(SCRATCH_ADDR, 0); + WREG32(mmCP_DEBUG, 0); + WREG32(mmSCRATCH_ADDR, 0); /* ring 0 - compute and gfx */ /* Set ring buffer size */ @@ -1738,24 +1775,24 @@ static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev) #ifdef __BIG_ENDIAN tmp |= BUF_SWAP_32BIT; #endif - WREG32(CP_RB0_CNTL, tmp); + WREG32(mmCP_RB0_CNTL, tmp); /* Initialize the ring buffer's read and write pointers */ - WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); + WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); ring->wptr = 0; - WREG32(CP_RB0_WPTR, ring->wptr); + WREG32(mmCP_RB0_WPTR, ring->wptr); /* set the wb address whether it's enabled or not */ rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); - WREG32(CP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); - WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); + WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); + WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); - WREG32(SCRATCH_UMSK, 0); + WREG32(mmSCRATCH_UMSK, 0); mdelay(1); - WREG32(CP_RB0_CNTL, tmp); + WREG32(mmCP_RB0_CNTL, tmp); - WREG32(CP_RB0_BASE, ring->gpu_addr >> 8); + WREG32(mmCP_RB0_BASE, ring->gpu_addr >> 8); /* start the rings */ gfx_v6_0_cp_gfx_start(adev); @@ -1779,11 +1816,11 @@ static u32 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring) struct amdgpu_device *adev = ring->adev; if (ring == &adev->gfx.gfx_ring[0]) - return RREG32(CP_RB0_WPTR); + return RREG32(mmCP_RB0_WPTR); else if (ring == &adev->gfx.compute_ring[0]) - return RREG32(CP_RB1_WPTR); + return RREG32(mmCP_RB1_WPTR); else if (ring == &adev->gfx.compute_ring[1]) - return RREG32(CP_RB2_WPTR); + return RREG32(mmCP_RB2_WPTR); else BUG(); } @@ -1792,8 +1829,8 @@ static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; - WREG32(CP_RB0_WPTR, ring->wptr); - (void)RREG32(CP_RB0_WPTR); + WREG32(mmCP_RB0_WPTR, ring->wptr); + (void)RREG32(mmCP_RB0_WPTR); } static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring) @@ -1801,11 +1838,11 @@ static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring) struct amdgpu_device *adev = ring->adev; if (ring == &adev->gfx.compute_ring[0]) { - WREG32(CP_RB1_WPTR, ring->wptr); - (void)RREG32(CP_RB1_WPTR); + WREG32(mmCP_RB1_WPTR, ring->wptr); + (void)RREG32(mmCP_RB1_WPTR); } else if (ring == &adev->gfx.compute_ring[1]) { - WREG32(CP_RB2_WPTR, ring->wptr); - (void)RREG32(CP_RB2_WPTR); + WREG32(mmCP_RB2_WPTR, ring->wptr); + (void)RREG32(mmCP_RB2_WPTR); } else { BUG(); } @@ -1817,7 +1854,7 @@ static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev) struct amdgpu_ring *ring; u32 tmp; u32 rb_bufsz; - int r; + int i, r; u64 rptr_addr; /* ring1 - compute only */ @@ -1829,19 +1866,19 @@ static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev) #ifdef __BIG_ENDIAN tmp |= BUF_SWAP_32BIT; #endif - WREG32(CP_RB1_CNTL, tmp); + WREG32(mmCP_RB1_CNTL, tmp); - WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA); + WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK); ring->wptr = 0; - WREG32(CP_RB1_WPTR, ring->wptr); + WREG32(mmCP_RB1_WPTR, ring->wptr); rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); - WREG32(CP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); - WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); + WREG32(mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); + WREG32(mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); mdelay(1); - WREG32(CP_RB1_CNTL, tmp); - WREG32(CP_RB1_BASE, ring->gpu_addr >> 8); + WREG32(mmCP_RB1_CNTL, tmp); + WREG32(mmCP_RB1_BASE, ring->gpu_addr >> 8); ring = &adev->gfx.compute_ring[1]; rb_bufsz = order_base_2(ring->ring_size / 8); @@ -1849,32 +1886,27 @@ static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev) #ifdef __BIG_ENDIAN tmp |= BUF_SWAP_32BIT; #endif - WREG32(CP_RB2_CNTL, tmp); + WREG32(mmCP_RB2_CNTL, tmp); - WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA); + WREG32(mmCP_RB2_CNTL, tmp | CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK); ring->wptr = 0; - WREG32(CP_RB2_WPTR, ring->wptr); + WREG32(mmCP_RB2_WPTR, ring->wptr); rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); - WREG32(CP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr)); - WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); + WREG32(mmCP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr)); + WREG32(mmCP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); mdelay(1); - WREG32(CP_RB2_CNTL, tmp); - WREG32(CP_RB2_BASE, ring->gpu_addr >> 8); + WREG32(mmCP_RB2_CNTL, tmp); + WREG32(mmCP_RB2_BASE, ring->gpu_addr >> 8); - adev->gfx.compute_ring[0].ready = true; - adev->gfx.compute_ring[1].ready = true; + adev->gfx.compute_ring[0].ready = false; + adev->gfx.compute_ring[1].ready = false; - r = amdgpu_ring_test_ring(&adev->gfx.compute_ring[0]); - if (r) { - adev->gfx.compute_ring[0].ready = false; - return r; - } - - r = amdgpu_ring_test_ring(&adev->gfx.compute_ring[1]); - if (r) { - adev->gfx.compute_ring[1].ready = false; - return r; + for (i = 0; i < 2; i++) { + r = amdgpu_ring_test_ring(&adev->gfx.compute_ring[i]); + if (r) + return r; + adev->gfx.compute_ring[i].ready = true; } return 0; @@ -1892,24 +1924,26 @@ static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev) static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, bool enable) -{ - u32 tmp = RREG32(CP_INT_CNTL_RING0); +{ + u32 tmp = RREG32(mmCP_INT_CNTL_RING0); u32 mask; int i; if (enable) - tmp |= (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); + tmp |= (CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK | + CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK); else - tmp &= ~(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); - WREG32(CP_INT_CNTL_RING0, tmp); + tmp &= ~(CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK | + CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK); + WREG32(mmCP_INT_CNTL_RING0, tmp); if (!enable) { /* read a gfx register */ - tmp = RREG32(DB_DEPTH_INFO); + tmp = RREG32(mmDB_DEPTH_INFO); mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS; for (i = 0; i < adev->usec_timeout; i++) { - if ((RREG32(RLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS)) + if ((RREG32(mmRLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS)) break; udelay(1); } @@ -1973,9 +2007,9 @@ static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring, amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | WRITE_DATA_DST_SEL(0))); if (vm_id < 8) { - amdgpu_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id )); + amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id )); } else { - amdgpu_ring_write(ring, (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vm_id - 8))); + amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vm_id - 8))); } amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, pd_addr >> 12); @@ -1984,7 +2018,7 @@ static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring, amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | WRITE_DATA_DST_SEL(0))); - amdgpu_ring_write(ring, VM_INVALIDATE_REQUEST); + amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, 1 << vm_id); @@ -1992,7 +2026,7 @@ static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring, amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); amdgpu_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */ WAIT_REG_MEM_ENGINE(0))); /* me */ - amdgpu_ring_write(ring, VM_INVALIDATE_REQUEST); + amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, 0); /* ref */ amdgpu_ring_write(ring, 0); /* mask */ @@ -2071,7 +2105,6 @@ static int gfx_v6_0_rlc_init(struct amdgpu_device *adev) if (src_ptr) { /* save restore block */ if (adev->gfx.rlc.save_restore_obj == NULL) { - r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, @@ -2166,20 +2199,12 @@ static int gfx_v6_0_rlc_init(struct amdgpu_device *adev) static void gfx_v6_0_enable_lbpw(struct amdgpu_device *adev, bool enable) { - u32 tmp; - - tmp = RREG32(RLC_LB_CNTL); - if (enable) - tmp |= LOAD_BALANCE_ENABLE; - else - tmp &= ~LOAD_BALANCE_ENABLE; - WREG32(RLC_LB_CNTL, tmp); + WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); if (!enable) { gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); - WREG32(SPI_LB_CU_MASK, 0x00ff); + WREG32(mmSPI_LB_CU_MASK, 0x00ff); } - } static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev) @@ -2187,13 +2212,13 @@ static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev) int i; for (i = 0; i < adev->usec_timeout; i++) { - if (RREG32(RLC_SERDES_MASTER_BUSY_0) == 0) + if (RREG32(mmRLC_SERDES_MASTER_BUSY_0) == 0) break; udelay(1); } for (i = 0; i < adev->usec_timeout; i++) { - if (RREG32(RLC_SERDES_MASTER_BUSY_1) == 0) + if (RREG32(mmRLC_SERDES_MASTER_BUSY_1) == 0) break; udelay(1); } @@ -2203,20 +2228,20 @@ static void gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc) { u32 tmp; - tmp = RREG32(RLC_CNTL); + tmp = RREG32(mmRLC_CNTL); if (tmp != rlc) - WREG32(RLC_CNTL, rlc); + WREG32(mmRLC_CNTL, rlc); } static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev) { u32 data, orig; - orig = data = RREG32(RLC_CNTL); + orig = data = RREG32(mmRLC_CNTL); - if (data & RLC_ENABLE) { - data &= ~RLC_ENABLE; - WREG32(RLC_CNTL, data); + if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) { + data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK; + WREG32(mmRLC_CNTL, data); gfx_v6_0_wait_for_rlc_serdes(adev); } @@ -2226,7 +2251,7 @@ static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev) static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev) { - WREG32(RLC_CNTL, 0); + WREG32(mmRLC_CNTL, 0); gfx_v6_0_enable_gui_idle_interrupt(adev, false); gfx_v6_0_wait_for_rlc_serdes(adev); @@ -2234,7 +2259,7 @@ static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev) static void gfx_v6_0_rlc_start(struct amdgpu_device *adev) { - WREG32(RLC_CNTL, RLC_ENABLE); + WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); gfx_v6_0_enable_gui_idle_interrupt(adev, true); @@ -2243,13 +2268,9 @@ static void gfx_v6_0_rlc_start(struct amdgpu_device *adev) static void gfx_v6_0_rlc_reset(struct amdgpu_device *adev) { - u32 tmp = RREG32(GRBM_SOFT_RESET); - - tmp |= SOFT_RESET_RLC; - WREG32(GRBM_SOFT_RESET, tmp); + WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); udelay(50); - tmp &= ~SOFT_RESET_RLC; - WREG32(GRBM_SOFT_RESET, tmp); + WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); udelay(50); } @@ -2258,11 +2279,12 @@ static bool gfx_v6_0_lbpw_supported(struct amdgpu_device *adev) u32 tmp; /* Enable LBPW only for DDR3 */ - tmp = RREG32(MC_SEQ_MISC0); + tmp = RREG32(mmMC_SEQ_MISC0); if ((tmp & 0xF0000000) == 0xB0000000) return true; return false; } + static void gfx_v6_0_init_cg(struct amdgpu_device *adev) { } @@ -2283,15 +2305,15 @@ static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev) gfx_v6_0_init_pg(adev); gfx_v6_0_init_cg(adev); - WREG32(RLC_RL_BASE, 0); - WREG32(RLC_RL_SIZE, 0); - WREG32(RLC_LB_CNTL, 0); - WREG32(RLC_LB_CNTR_MAX, 0xffffffff); - WREG32(RLC_LB_CNTR_INIT, 0); - WREG32(RLC_LB_INIT_CU_MASK, 0xffffffff); + WREG32(mmRLC_RL_BASE, 0); + WREG32(mmRLC_RL_SIZE, 0); + WREG32(mmRLC_LB_CNTL, 0); + WREG32(mmRLC_LB_CNTR_MAX, 0xffffffff); + WREG32(mmRLC_LB_CNTR_INIT, 0); + WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff); - WREG32(RLC_MC_CNTL, 0); - WREG32(RLC_UCODE_CNTL, 0); + WREG32(mmRLC_MC_CNTL, 0); + WREG32(mmRLC_UCODE_CNTL, 0); hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; @@ -2301,10 +2323,10 @@ static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev) amdgpu_ucode_print_rlc_hdr(&hdr->header); for (i = 0; i < fw_size; i++) { - WREG32(RLC_UCODE_ADDR, i); - WREG32(RLC_UCODE_DATA, le32_to_cpup(fw_data++)); + WREG32(mmRLC_UCODE_ADDR, i); + WREG32(mmRLC_UCODE_DATA, le32_to_cpup(fw_data++)); } - WREG32(RLC_UCODE_ADDR, 0); + WREG32(mmRLC_UCODE_ADDR, 0); gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev)); gfx_v6_0_rlc_start(adev); @@ -2316,38 +2338,38 @@ static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable) { u32 data, orig, tmp; - orig = data = RREG32(RLC_CGCG_CGLS_CTRL); + orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL); if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { gfx_v6_0_enable_gui_idle_interrupt(adev, true); - WREG32(RLC_GCPM_GENERAL_3, 0x00000080); + WREG32(mmRLC_GCPM_GENERAL_3, 0x00000080); tmp = gfx_v6_0_halt_rlc(adev); - WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); - WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); - WREG32(RLC_SERDES_WR_CTRL, 0x00b000ff); + WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); + WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); + WREG32(mmRLC_SERDES_WR_CTRL, 0x00b000ff); gfx_v6_0_wait_for_rlc_serdes(adev); gfx_v6_0_update_rlc(adev, tmp); - WREG32(RLC_SERDES_WR_CTRL, 0x007000ff); + WREG32(mmRLC_SERDES_WR_CTRL, 0x007000ff); - data |= CGCG_EN | CGLS_EN; + data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; } else { gfx_v6_0_enable_gui_idle_interrupt(adev, false); - RREG32(CB_CGTT_SCLK_CTRL); - RREG32(CB_CGTT_SCLK_CTRL); - RREG32(CB_CGTT_SCLK_CTRL); - RREG32(CB_CGTT_SCLK_CTRL); + RREG32(mmCB_CGTT_SCLK_CTRL); + RREG32(mmCB_CGTT_SCLK_CTRL); + RREG32(mmCB_CGTT_SCLK_CTRL); + RREG32(mmCB_CGTT_SCLK_CTRL); - data &= ~(CGCG_EN | CGLS_EN); + data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); } if (orig != data) - WREG32(RLC_CGCG_CGLS_CTRL, data); + WREG32(mmRLC_CGCG_CGLS_CTRL, data); } @@ -2357,51 +2379,51 @@ static void gfx_v6_0_enable_mgcg(struct amdgpu_device *adev, bool enable) u32 data, orig, tmp = 0; if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { - orig = data = RREG32(CGTS_SM_CTRL_REG); + orig = data = RREG32(mmCGTS_SM_CTRL_REG); data = 0x96940200; if (orig != data) - WREG32(CGTS_SM_CTRL_REG, data); + WREG32(mmCGTS_SM_CTRL_REG, data); if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { - orig = data = RREG32(CP_MEM_SLP_CNTL); - data |= CP_MEM_LS_EN; + orig = data = RREG32(mmCP_MEM_SLP_CNTL); + data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; if (orig != data) - WREG32(CP_MEM_SLP_CNTL, data); + WREG32(mmCP_MEM_SLP_CNTL, data); } - orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE); + orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); data &= 0xffffffc0; if (orig != data) - WREG32(RLC_CGTT_MGCG_OVERRIDE, data); + WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); tmp = gfx_v6_0_halt_rlc(adev); - WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); - WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); - WREG32(RLC_SERDES_WR_CTRL, 0x00d000ff); + WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); + WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); + WREG32(mmRLC_SERDES_WR_CTRL, 0x00d000ff); gfx_v6_0_update_rlc(adev, tmp); } else { - orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE); + orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); data |= 0x00000003; if (orig != data) - WREG32(RLC_CGTT_MGCG_OVERRIDE, data); + WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); - data = RREG32(CP_MEM_SLP_CNTL); - if (data & CP_MEM_LS_EN) { - data &= ~CP_MEM_LS_EN; - WREG32(CP_MEM_SLP_CNTL, data); + data = RREG32(mmCP_MEM_SLP_CNTL); + if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { + data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; + WREG32(mmCP_MEM_SLP_CNTL, data); } - orig = data = RREG32(CGTS_SM_CTRL_REG); - data |= LS_OVERRIDE | OVERRIDE; + orig = data = RREG32(mmCGTS_SM_CTRL_REG); + data |= CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK | CGTS_SM_CTRL_REG__OVERRIDE_MASK; if (orig != data) - WREG32(CGTS_SM_CTRL_REG, data); + WREG32(mmCGTS_SM_CTRL_REG, data); tmp = gfx_v6_0_halt_rlc(adev); - WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); - WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); - WREG32(RLC_SERDES_WR_CTRL, 0x00e000ff); + WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); + WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); + WREG32(mmRLC_SERDES_WR_CTRL, 0x00e000ff); gfx_v6_0_update_rlc(adev, tmp); } @@ -2421,6 +2443,7 @@ static void gfx_v6_0_update_cg(struct amdgpu_device *adev, gfx_v6_0_enable_gui_idle_interrupt(adev, true); } */ + static void gfx_v6_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev, bool enable) { @@ -2435,13 +2458,13 @@ static void gfx_v6_0_enable_cp_pg(struct amdgpu_device *adev, bool enable) { u32 data, orig; - orig = data = RREG32(RLC_PG_CNTL); + orig = data = RREG32(mmRLC_PG_CNTL); if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP)) data &= ~0x8000; else data |= 0x8000; if (orig != data) - WREG32(RLC_PG_CNTL, data); + WREG32(mmRLC_PG_CNTL, data); } static void gfx_v6_0_enable_gds_pg(struct amdgpu_device *adev, bool enable) @@ -2518,26 +2541,13 @@ static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev) static void gfx_v6_0_enable_gfx_cgpg(struct amdgpu_device *adev, bool enable) { - - u32 tmp; - if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { - tmp = RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10); - WREG32(RLC_TTOP_D, tmp); - - tmp = RREG32(RLC_PG_CNTL); - tmp |= GFX_PG_ENABLE; - WREG32(RLC_PG_CNTL, tmp); - - tmp = RREG32(RLC_AUTO_PG_CTRL); - tmp |= AUTO_PG_EN; - WREG32(RLC_AUTO_PG_CTRL, tmp); + WREG32(mmRLC_TTOP_D, RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10)); + WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, 1); + WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 1); } else { - tmp = RREG32(RLC_AUTO_PG_CTRL); - tmp &= ~AUTO_PG_EN; - WREG32(RLC_AUTO_PG_CTRL, tmp); - - tmp = RREG32(DB_RENDER_CONTROL); + WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 0); + (void)RREG32(mmDB_RENDER_CONTROL); } } @@ -2550,8 +2560,8 @@ static u32 gfx_v6_0_get_cu_active_bitmap(struct amdgpu_device *adev, mutex_lock(&adev->grbm_idx_mutex); gfx_v6_0_select_se_sh(adev, se, sh, 0xffffffff); - tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG); - tmp1 = RREG32(GC_USER_SHADER_ARRAY_CONFIG); + tmp = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG); + tmp1 = RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); mutex_unlock(&adev->grbm_idx_mutex); @@ -2594,12 +2604,8 @@ static void gfx_v6_0_init_ao_cu_mask(struct amdgpu_device *adev) } } - WREG32(RLC_PG_AO_CU_MASK, tmp); - - tmp = RREG32(RLC_MAX_PG_CU); - tmp &= ~MAX_PU_CU_MASK; - tmp |= MAX_PU_CU(active_cu_number); - WREG32(RLC_MAX_PG_CU, tmp); + WREG32(mmRLC_PG_AO_CU_MASK, tmp); + WREG32_FIELD(RLC_MAX_PG_CU, MAX_POWERED_UP_CU, active_cu_number); } static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev, @@ -2607,13 +2613,13 @@ static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev, { u32 data, orig; - orig = data = RREG32(RLC_PG_CNTL); + orig = data = RREG32(mmRLC_PG_CNTL); if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG)) - data |= STATIC_PER_CU_PG_ENABLE; + data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; else - data &= ~STATIC_PER_CU_PG_ENABLE; + data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; if (orig != data) - WREG32(RLC_PG_CNTL, data); + WREG32(mmRLC_PG_CNTL, data); } static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev, @@ -2621,33 +2627,28 @@ static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev, { u32 data, orig; - orig = data = RREG32(RLC_PG_CNTL); + orig = data = RREG32(mmRLC_PG_CNTL); if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG)) - data |= DYN_PER_CU_PG_ENABLE; + data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; else - data &= ~DYN_PER_CU_PG_ENABLE; + data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; if (orig != data) - WREG32(RLC_PG_CNTL, data); + WREG32(mmRLC_PG_CNTL, data); } static void gfx_v6_0_init_gfx_cgpg(struct amdgpu_device *adev) { u32 tmp; - WREG32(RLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); - - tmp = RREG32(RLC_PG_CNTL); - tmp |= GFX_PG_SRC; - WREG32(RLC_PG_CNTL, tmp); - - WREG32(RLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); + WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); + WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_SRC, 1); + WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); - tmp = RREG32(RLC_AUTO_PG_CTRL); - - tmp &= ~GRBM_REG_SGIT_MASK; - tmp |= GRBM_REG_SGIT(0x700); - tmp &= ~PG_AFTER_GRBM_REG_ST_MASK; - WREG32(RLC_AUTO_PG_CTRL, tmp); + tmp = RREG32(mmRLC_AUTO_PG_CTRL); + tmp &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK; + tmp |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); + tmp &= ~RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK; + WREG32(mmRLC_AUTO_PG_CTRL, tmp); } static void gfx_v6_0_update_gfx_pg(struct amdgpu_device *adev, bool enable) @@ -2703,7 +2704,6 @@ static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); - buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); buffer[count++] = cpu_to_le32(0x80000000); buffer[count++] = cpu_to_le32(0x80000000); @@ -2723,7 +2723,7 @@ static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, } buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); - buffer[count++] = cpu_to_le32(PA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); + buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); switch (adev->asic_type) { case CHIP_TAHITI: @@ -2766,16 +2766,16 @@ static void gfx_v6_0_init_pg(struct amdgpu_device *adev) gfx_v6_0_enable_cp_pg(adev, true); gfx_v6_0_enable_gds_pg(adev, true); } else { - WREG32(RLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); - WREG32(RLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); + WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); + WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); } gfx_v6_0_init_ao_cu_mask(adev); gfx_v6_0_update_gfx_pg(adev, true); } else { - WREG32(RLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); - WREG32(RLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); + WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); + WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); } } @@ -2800,23 +2800,61 @@ static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev) uint64_t clock; mutex_lock(&adev->gfx.gpu_clock_mutex); - WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); - clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) | - ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); + WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); + clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) | + ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); mutex_unlock(&adev->gfx.gpu_clock_mutex); return clock; } static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) { + if (flags & AMDGPU_HAVE_CTX_SWITCH) + gfx_v6_0_ring_emit_vgt_flush(ring); amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); amdgpu_ring_write(ring, 0x80000000); amdgpu_ring_write(ring, 0); } + +static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) +{ + WREG32(mmSQ_IND_INDEX, + (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | + (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | + (address << SQ_IND_INDEX__INDEX__SHIFT) | + (SQ_IND_INDEX__FORCE_READ_MASK)); + return RREG32(mmSQ_IND_DATA); +} + +static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) +{ + /* type 0 wave data */ + dst[(*no_fields)++] = 0; + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); +} + static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = { .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter, .select_se_sh = &gfx_v6_0_select_se_sh, + .read_wave_data = &gfx_v6_0_read_wave_data, }; static int gfx_v6_0_early_init(void *handle) @@ -2967,7 +3005,7 @@ static bool gfx_v6_0_is_idle(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; - if (RREG32(GRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK) + if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK) return false; else return true; @@ -2998,14 +3036,14 @@ static void gfx_v6_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, switch (state) { case AMDGPU_IRQ_STATE_DISABLE: - cp_int_cntl = RREG32(CP_INT_CNTL_RING0); - cp_int_cntl &= ~CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK; - WREG32(CP_INT_CNTL_RING0, cp_int_cntl); + cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); + cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; + WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); break; case AMDGPU_IRQ_STATE_ENABLE: - cp_int_cntl = RREG32(CP_INT_CNTL_RING0); - cp_int_cntl |= CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK; - WREG32(CP_INT_CNTL_RING0, cp_int_cntl); + cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); + cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; + WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); break; default: break; @@ -3020,27 +3058,27 @@ static void gfx_v6_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, switch (state){ case AMDGPU_IRQ_STATE_DISABLE: if (ring == 0) { - cp_int_cntl = RREG32(CP_INT_CNTL_RING1); - cp_int_cntl &= ~CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK; - WREG32(CP_INT_CNTL_RING1, cp_int_cntl); + cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1); + cp_int_cntl &= ~CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK; + WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl); break; } else { - cp_int_cntl = RREG32(CP_INT_CNTL_RING2); - cp_int_cntl &= ~CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK; - WREG32(CP_INT_CNTL_RING2, cp_int_cntl); + cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2); + cp_int_cntl &= ~CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK; + WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl); break; } case AMDGPU_IRQ_STATE_ENABLE: if (ring == 0) { - cp_int_cntl = RREG32(CP_INT_CNTL_RING1); - cp_int_cntl |= CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK; - WREG32(CP_INT_CNTL_RING1, cp_int_cntl); + cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1); + cp_int_cntl |= CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK; + WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl); break; } else { - cp_int_cntl = RREG32(CP_INT_CNTL_RING2); - cp_int_cntl |= CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK; - WREG32(CP_INT_CNTL_RING2, cp_int_cntl); + cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2); + cp_int_cntl |= CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK; + WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl); break; } @@ -3061,14 +3099,14 @@ static int gfx_v6_0_set_priv_reg_fault_state(struct amdgpu_device *adev, switch (state) { case AMDGPU_IRQ_STATE_DISABLE: - cp_int_cntl = RREG32(CP_INT_CNTL_RING0); + cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; - WREG32(CP_INT_CNTL_RING0, cp_int_cntl); + WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); break; case AMDGPU_IRQ_STATE_ENABLE: - cp_int_cntl = RREG32(CP_INT_CNTL_RING0); + cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; - WREG32(CP_INT_CNTL_RING0, cp_int_cntl); + WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); break; default: break; @@ -3086,14 +3124,14 @@ static int gfx_v6_0_set_priv_inst_fault_state(struct amdgpu_device *adev, switch (state) { case AMDGPU_IRQ_STATE_DISABLE: - cp_int_cntl = RREG32(CP_INT_CNTL_RING0); + cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; - WREG32(CP_INT_CNTL_RING0, cp_int_cntl); + WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); break; case AMDGPU_IRQ_STATE_ENABLE: - cp_int_cntl = RREG32(CP_INT_CNTL_RING0); + cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; - WREG32(CP_INT_CNTL_RING0, cp_int_cntl); + WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); break; default: break; @@ -3133,7 +3171,7 @@ static int gfx_v6_0_eop_irq(struct amdgpu_device *adev, break; case 1: case 2: - amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id -1]); + amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id - 1]); break; default: break; @@ -3236,7 +3274,7 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ 7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */ 17 + 6 + /* gfx_v6_0_ring_emit_vm_flush */ - 3, /* gfx_v6_ring_emit_cntxcntl */ + 3 + 2, /* gfx_v6_ring_emit_cntxcntl including vgt flush */ .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */ .emit_ib = gfx_v6_0_ring_emit_ib, .emit_fence = gfx_v6_0_ring_emit_fence, diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 5b631fd1a879..1a745cf93f47 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -2105,6 +2105,18 @@ static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) amdgpu_ring_write(ring, 0x20); /* poll interval */ } +static void gfx_v7_0_ring_emit_vgt_flush(struct amdgpu_ring *ring) +{ + amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); + amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) | + EVENT_INDEX(4)); + + amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); + amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) | + EVENT_INDEX(0)); +} + + /** * gfx_v7_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp * @@ -2260,6 +2272,7 @@ static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ if (flags & AMDGPU_HAVE_CTX_SWITCH) { + gfx_v7_0_ring_emit_vgt_flush(ring); /* set load_global_config & load_global_uconfig */ dw2 |= 0x8001; /* set load_cs_sh_regs */ @@ -4359,7 +4372,11 @@ static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring, static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) { - WREG32(mmSQ_IND_INDEX, (wave & 0xF) | ((simd & 0x3) << 4) | (address << 16) | (1 << 13)); + WREG32(mmSQ_IND_INDEX, + (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | + (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | + (address << SQ_IND_INDEX__INDEX__SHIFT) | + (SQ_IND_INDEX__FORCE_READ_MASK)); return RREG32(mmSQ_IND_DATA); } @@ -5149,7 +5166,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { 12 + 12 + 12 + /* gfx_v7_0_ring_emit_fence_gfx x3 for user fence, vm fence */ 7 + 4 + /* gfx_v7_0_ring_emit_pipeline_sync */ 17 + 6 + /* gfx_v7_0_ring_emit_vm_flush */ - 3, /* gfx_v7_ring_emit_cntxcntl */ + 3 + 4, /* gfx_v7_ring_emit_cntxcntl including vgt flush*/ .emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_gfx */ .emit_ib = gfx_v7_0_ring_emit_ib_gfx, .emit_fence = gfx_v7_0_ring_emit_fence_gfx, diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 23f1bc94ad3e..a3684891c6e1 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -3904,7 +3904,7 @@ static int gfx_v8_0_init_save_restore_list(struct amdgpu_device *adev) int list_size; unsigned int *register_list_format = kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL); - if (register_list_format == NULL) + if (!register_list_format) return -ENOMEM; memcpy(register_list_format, adev->gfx.rlc.register_list_format, adev->gfx.rlc.reg_list_format_size_bytes); @@ -5442,7 +5442,11 @@ static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring, static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) { - WREG32(mmSQ_IND_INDEX, (wave & 0xF) | ((simd & 0x3) << 4) | (address << 16) | (1 << 13)); + WREG32(mmSQ_IND_INDEX, + (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | + (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | + (address << SQ_IND_INDEX__INDEX__SHIFT) | + (SQ_IND_INDEX__FORCE_READ_MASK)); return RREG32(mmSQ_IND_DATA); } @@ -6182,6 +6186,18 @@ static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) amdgpu_ring_write(ring, 0x20); /* poll interval */ } +static void gfx_v8_0_ring_emit_vgt_flush(struct amdgpu_ring *ring) +{ + amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); + amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) | + EVENT_INDEX(4)); + + amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); + amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) | + EVENT_INDEX(0)); +} + + static void gfx_v8_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) { amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); @@ -6367,6 +6383,7 @@ static void gfx_v8_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ if (flags & AMDGPU_HAVE_CTX_SWITCH) { + gfx_v8_0_ring_emit_vgt_flush(ring); /* set load_global_config & load_global_uconfig */ dw2 |= 0x8001; /* set load_cs_sh_regs */ @@ -6570,7 +6587,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = { 7 + /* gfx_v8_0_ring_emit_pipeline_sync */ 128 + 19 + /* gfx_v8_0_ring_emit_vm_flush */ 2 + /* gfx_v8_ring_emit_sb */ - 3, /* gfx_v8_ring_emit_cntxcntl */ + 3 + 4, /* gfx_v8_ring_emit_cntxcntl including vgt flush */ .emit_ib_size = 4, /* gfx_v8_0_ring_emit_ib_gfx */ .emit_ib = gfx_v8_0_ring_emit_ib_gfx, .emit_fence = gfx_v8_0_ring_emit_fence_gfx, diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index 1940d36bc304..64d3c1e6014c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -1,4 +1,3 @@ - /* * Copyright 2014 Advanced Micro Devices, Inc. * @@ -26,7 +25,16 @@ #include "amdgpu.h" #include "gmc_v6_0.h" #include "amdgpu_ucode.h" -#include "si/sid.h" + +#include "bif/bif_3_0_d.h" +#include "bif/bif_3_0_sh_mask.h" +#include "oss/oss_1_0_d.h" +#include "oss/oss_1_0_sh_mask.h" +#include "gmc/gmc_6_0_d.h" +#include "gmc/gmc_6_0_sh_mask.h" +#include "dce/dce_6_0_d.h" +#include "dce/dce_6_0_sh_mask.h" +#include "si_enums.h" static void gmc_v6_0_set_gart_funcs(struct amdgpu_device *adev); static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev); @@ -37,6 +45,16 @@ MODULE_FIRMWARE("radeon/pitcairn_mc.bin"); MODULE_FIRMWARE("radeon/verde_mc.bin"); MODULE_FIRMWARE("radeon/oland_mc.bin"); +#define MC_SEQ_MISC0__MT__MASK 0xf0000000 +#define MC_SEQ_MISC0__MT__GDDR1 0x10000000 +#define MC_SEQ_MISC0__MT__DDR2 0x20000000 +#define MC_SEQ_MISC0__MT__GDDR3 0x30000000 +#define MC_SEQ_MISC0__MT__GDDR4 0x40000000 +#define MC_SEQ_MISC0__MT__GDDR5 0x50000000 +#define MC_SEQ_MISC0__MT__HBM 0x60000000 +#define MC_SEQ_MISC0__MT__DDR3 0xB0000000 + + static const u32 crtc_offsets[6] = { SI_CRTC0_REGISTER_OFFSET, @@ -57,14 +75,14 @@ static void gmc_v6_0_mc_stop(struct amdgpu_device *adev, gmc_v6_0_wait_for_idle((void *)adev); - blackout = RREG32(MC_SHARED_BLACKOUT_CNTL); - if (REG_GET_FIELD(blackout, mmMC_SHARED_BLACKOUT_CNTL, xxBLACKOUT_MODE) != 1) { + blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); + if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { /* Block CPU access */ - WREG32(BIF_FB_EN, 0); + WREG32(mmBIF_FB_EN, 0); /* blackout the MC */ blackout = REG_SET_FIELD(blackout, - mmMC_SHARED_BLACKOUT_CNTL, xxBLACKOUT_MODE, 0); - WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1); + MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); + WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1); } /* wait for the MC to settle */ udelay(100); @@ -77,13 +95,13 @@ static void gmc_v6_0_mc_resume(struct amdgpu_device *adev, u32 tmp; /* unblackout the MC */ - tmp = RREG32(MC_SHARED_BLACKOUT_CNTL); - tmp = REG_SET_FIELD(tmp, mmMC_SHARED_BLACKOUT_CNTL, xxBLACKOUT_MODE, 0); - WREG32(MC_SHARED_BLACKOUT_CNTL, tmp); + tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); + tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); + WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); /* allow CPU access */ - tmp = REG_SET_FIELD(0, mmBIF_FB_EN, xxFB_READ_EN, 1); - tmp = REG_SET_FIELD(tmp, mmBIF_FB_EN, xxFB_WRITE_EN, 1); - WREG32(BIF_FB_EN, tmp); + tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); + tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); + WREG32(mmBIF_FB_EN, tmp); if (adev->mode_info.num_crtc) amdgpu_display_resume_mc_access(adev, save); @@ -158,37 +176,37 @@ static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev) new_fw_data = (const __le32 *) (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); - running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK; + running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK; if (running == 0) { /* reset the engine and set to writable */ - WREG32(MC_SEQ_SUP_CNTL, 0x00000008); - WREG32(MC_SEQ_SUP_CNTL, 0x00000010); + WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); + WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); /* load mc io regs */ for (i = 0; i < regs_size; i++) { - WREG32(MC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++)); - WREG32(MC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++)); + WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++)); + WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++)); } /* load the MC ucode */ for (i = 0; i < ucode_size; i++) { - WREG32(MC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++)); + WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++)); } /* put the engine back into the active state */ - WREG32(MC_SEQ_SUP_CNTL, 0x00000008); - WREG32(MC_SEQ_SUP_CNTL, 0x00000004); - WREG32(MC_SEQ_SUP_CNTL, 0x00000001); + WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); + WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); + WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); /* wait for training to complete */ for (i = 0; i < adev->usec_timeout; i++) { - if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0) + if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK) break; udelay(1); } for (i = 0; i < adev->usec_timeout; i++) { - if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1) + if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK) break; udelay(1); } @@ -225,7 +243,7 @@ static void gmc_v6_0_mc_program(struct amdgpu_device *adev) WREG32((0xb08 + j), 0x00000000); WREG32((0xb09 + j), 0x00000000); } - WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); + WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); gmc_v6_0_mc_stop(adev, &save); @@ -233,24 +251,24 @@ static void gmc_v6_0_mc_program(struct amdgpu_device *adev) dev_warn(adev->dev, "Wait for MC idle timedout !\n"); } - WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); + WREG32(mmVGA_HDP_CONTROL, VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK); /* Update configuration */ - WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, + WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, adev->mc.vram_start >> 12); - WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, + WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, adev->mc.vram_end >> 12); - WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, + WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, adev->vram_scratch.gpu_addr >> 12); tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16; tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF); - WREG32(MC_VM_FB_LOCATION, tmp); + WREG32(mmMC_VM_FB_LOCATION, tmp); /* XXX double check these! */ - WREG32(HDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8)); - WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); - WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); - WREG32(MC_VM_AGP_BASE, 0); - WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); - WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); + WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8)); + WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); + WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF); + WREG32(mmMC_VM_AGP_BASE, 0); + WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF); + WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF); if (gmc_v6_0_wait_for_idle((void *)adev)) { dev_warn(adev->dev, "Wait for MC idle timedout !\n"); @@ -265,16 +283,16 @@ static int gmc_v6_0_mc_init(struct amdgpu_device *adev) u32 tmp; int chansize, numchan; - tmp = RREG32(MC_ARB_RAMCFG); - if (tmp & CHANSIZE_OVERRIDE) { + tmp = RREG32(mmMC_ARB_RAMCFG); + if (tmp & (1 << 11)) { chansize = 16; - } else if (tmp & CHANSIZE_MASK) { + } else if (tmp & MC_ARB_RAMCFG__CHANSIZE_MASK) { chansize = 64; } else { chansize = 32; } - tmp = RREG32(MC_SHARED_CHMAP); - switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { + tmp = RREG32(mmMC_SHARED_CHMAP); + switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) { case 0: default: numchan = 1; @@ -309,8 +327,8 @@ static int gmc_v6_0_mc_init(struct amdgpu_device *adev) adev->mc.aper_base = pci_resource_start(adev->pdev, 0); adev->mc.aper_size = pci_resource_len(adev->pdev, 0); /* size in MB on si */ - adev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL; - adev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL; + adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; + adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; adev->mc.visible_vram_size = adev->mc.aper_size; /* unless the user had overridden it, set the gart @@ -329,9 +347,9 @@ static int gmc_v6_0_mc_init(struct amdgpu_device *adev) static void gmc_v6_0_gart_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid) { - WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0); + WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0); - WREG32(VM_INVALIDATE_REQUEST, 1 << vmid); + WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); } static int gmc_v6_0_gart_set_pte_pde(struct amdgpu_device *adev, @@ -355,20 +373,20 @@ static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev, { u32 tmp; - tmp = RREG32(VM_CONTEXT1_CNTL); - tmp = REG_SET_FIELD(tmp, mmVM_CONTEXT1_CNTL, - xxRANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); - tmp = REG_SET_FIELD(tmp, mmVM_CONTEXT1_CNTL, - xxDUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); - tmp = REG_SET_FIELD(tmp, mmVM_CONTEXT1_CNTL, - xxPDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); - tmp = REG_SET_FIELD(tmp, mmVM_CONTEXT1_CNTL, - xxVALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); - tmp = REG_SET_FIELD(tmp, mmVM_CONTEXT1_CNTL, - xxREAD_PROTECTION_FAULT_ENABLE_DEFAULT, value); - tmp = REG_SET_FIELD(tmp, mmVM_CONTEXT1_CNTL, - xxWRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); - WREG32(VM_CONTEXT1_CNTL, tmp); + tmp = RREG32(mmVM_CONTEXT1_CNTL); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); + WREG32(mmVM_CONTEXT1_CNTL, tmp); } static int gmc_v6_0_gart_enable(struct amdgpu_device *adev) @@ -383,33 +401,39 @@ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev) if (r) return r; /* Setup TLB control */ - WREG32(MC_VM_MX_L1_TLB_CNTL, + WREG32(mmMC_VM_MX_L1_TLB_CNTL, (0xA << 7) | - ENABLE_L1_TLB | - ENABLE_L1_FRAGMENT_PROCESSING | - SYSTEM_ACCESS_MODE_NOT_IN_SYS | - ENABLE_ADVANCED_DRIVER_MODEL | - SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU); + MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK | + MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK | + MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK | + MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK | + (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT)); /* Setup L2 cache */ - WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | - ENABLE_L2_FRAGMENT_PROCESSING | - ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | - ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | - EFFECTIVE_L2_QUEUE_SIZE(7) | - CONTEXT1_IDENTITY_ACCESS_MODE(1)); - WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); - WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | - BANK_SELECT(4) | - L2_CACHE_BIGK_FRAGMENT_SIZE(4)); + WREG32(mmVM_L2_CNTL, + VM_L2_CNTL__ENABLE_L2_CACHE_MASK | + VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK | + VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK | + VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK | + (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) | + (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT)); + WREG32(mmVM_L2_CNTL2, + VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK | + VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK); + WREG32(mmVM_L2_CNTL3, + VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK | + (4UL << VM_L2_CNTL3__BANK_SELECT__SHIFT) | + (4UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT)); /* setup context0 */ - WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12); - WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12); - WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12); - WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, + WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12); + WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12); + WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12); + WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, (u32)(adev->dummy_page.addr >> 12)); - WREG32(VM_CONTEXT0_CNTL2, 0); - WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | - RANGE_PROTECTION_FAULT_ENABLE_DEFAULT)); + WREG32(mmVM_CONTEXT0_CNTL2, 0); + WREG32(mmVM_CONTEXT0_CNTL, + VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK | + (0UL << VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT) | + VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK); WREG32(0x575, 0); WREG32(0x576, 0); @@ -417,39 +441,41 @@ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev) /* empty context1-15 */ /* set vm size, must be a multiple of 4 */ - WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); - WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); + WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); + WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); /* Assign the pt base to something valid for now; the pts used for * the VMs are determined by the application and setup and assigned * on the fly in the vm part of radeon_gart.c */ for (i = 1; i < 16; i++) { if (i < 8) - WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, + WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, adev->gart.table_addr >> 12); else - WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, + WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, adev->gart.table_addr >> 12); } /* enable context1-15 */ - WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, + WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, (u32)(adev->dummy_page.addr >> 12)); - WREG32(VM_CONTEXT1_CNTL2, 4); - WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | - PAGE_TABLE_BLOCK_SIZE(amdgpu_vm_block_size - 9) | - RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT | - RANGE_PROTECTION_FAULT_ENABLE_DEFAULT | - DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT | - DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT | - PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT | - PDE0_PROTECTION_FAULT_ENABLE_DEFAULT | - VALID_PROTECTION_FAULT_ENABLE_INTERRUPT | - VALID_PROTECTION_FAULT_ENABLE_DEFAULT | - READ_PROTECTION_FAULT_ENABLE_INTERRUPT | - READ_PROTECTION_FAULT_ENABLE_DEFAULT | - WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT | - WRITE_PROTECTION_FAULT_ENABLE_DEFAULT); + WREG32(mmVM_CONTEXT1_CNTL2, 4); + WREG32(mmVM_CONTEXT1_CNTL, + VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK | + (1UL << VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT) | + ((amdgpu_vm_block_size - 9) << VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT) | + VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK | + VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK | + VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK | + VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK | + VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK | + VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK); gmc_v6_0_gart_flush_gpu_tlb(adev, 0); dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n", @@ -488,19 +514,22 @@ static void gmc_v6_0_gart_disable(struct amdgpu_device *adev) }*/ /* Disable all tables */ - WREG32(VM_CONTEXT0_CNTL, 0); - WREG32(VM_CONTEXT1_CNTL, 0); + WREG32(mmVM_CONTEXT0_CNTL, 0); + WREG32(mmVM_CONTEXT1_CNTL, 0); /* Setup TLB control */ - WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS | - SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU); + WREG32(mmMC_VM_MX_L1_TLB_CNTL, + MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK | + (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT)); /* Setup L2 cache */ - WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | - ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | - EFFECTIVE_L2_QUEUE_SIZE(7) | - CONTEXT1_IDENTITY_ACCESS_MODE(1)); - WREG32(VM_L2_CNTL2, 0); - WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | - L2_CACHE_BIGK_FRAGMENT_SIZE(0)); + WREG32(mmVM_L2_CNTL, + VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK | + VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK | + (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) | + (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT)); + WREG32(mmVM_L2_CNTL2, 0); + WREG32(mmVM_L2_CNTL3, + VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK | + (0UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT)); amdgpu_gart_table_vram_unpin(adev); } @@ -523,7 +552,7 @@ static int gmc_v6_0_vm_init(struct amdgpu_device *adev) /* base offset of vram pages */ if (adev->flags & AMD_IS_APU) { - u64 tmp = RREG32(MC_VM_FB_OFFSET); + u64 tmp = RREG32(mmMC_VM_FB_OFFSET); tmp <<= 22; adev->vm_manager.vram_base_offset = tmp; } else @@ -540,19 +569,19 @@ static void gmc_v6_0_vm_decode_fault(struct amdgpu_device *adev, u32 status, u32 addr, u32 mc_client) { u32 mc_id; - u32 vmid = REG_GET_FIELD(status, mmVM_CONTEXT1_PROTECTION_FAULT_STATUS, xxVMID); - u32 protections = REG_GET_FIELD(status, mmVM_CONTEXT1_PROTECTION_FAULT_STATUS, - xxPROTECTIONS); + u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); + u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, + PROTECTIONS); char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; - mc_id = REG_GET_FIELD(status, mmVM_CONTEXT1_PROTECTION_FAULT_STATUS, - xxMEMORY_CLIENT_ID); + mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, + MEMORY_CLIENT_ID); dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", protections, vmid, addr, - REG_GET_FIELD(status, mmVM_CONTEXT1_PROTECTION_FAULT_STATUS, - xxMEMORY_CLIENT_RW) ? + REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, + MEMORY_CLIENT_RW) ? "write" : "read", block, mc_client, mc_id); } @@ -655,7 +684,7 @@ static void gmc_v6_0_enable_hdp_mgcg(struct amdgpu_device *adev, { u32 orig, data; - orig = data = RREG32(HDP_HOST_PATH_CNTL); + orig = data = RREG32(mmHDP_HOST_PATH_CNTL); if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG)) data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0); @@ -663,7 +692,7 @@ static void gmc_v6_0_enable_hdp_mgcg(struct amdgpu_device *adev, data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1); if (orig != data) - WREG32(HDP_HOST_PATH_CNTL, data); + WREG32(mmHDP_HOST_PATH_CNTL, data); } static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev, @@ -671,7 +700,7 @@ static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev, { u32 orig, data; - orig = data = RREG32(HDP_MEM_POWER_LS); + orig = data = RREG32(mmHDP_MEM_POWER_LS); if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS)) data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1); @@ -679,7 +708,7 @@ static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev, data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0); if (orig != data) - WREG32(HDP_MEM_POWER_LS, data); + WREG32(mmHDP_MEM_POWER_LS, data); } */ @@ -713,7 +742,7 @@ static int gmc_v6_0_early_init(void *handle) if (adev->flags & AMD_IS_APU) { adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; } else { - u32 tmp = RREG32(MC_SEQ_MISC0); + u32 tmp = RREG32(mmMC_SEQ_MISC0); tmp &= MC_SEQ_MISC0__MT__MASK; adev->mc.vram_type = gmc_v6_0_convert_vram_type(tmp); } @@ -879,7 +908,7 @@ static int gmc_v6_0_resume(void *handle) static bool gmc_v6_0_is_idle(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; - u32 tmp = RREG32(SRBM_STATUS); + u32 tmp = RREG32(mmSRBM_STATUS); if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK)) @@ -895,7 +924,7 @@ static int gmc_v6_0_wait_for_idle(void *handle) struct amdgpu_device *adev = (struct amdgpu_device *)handle; for (i = 0; i < adev->usec_timeout; i++) { - tmp = RREG32(SRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | + tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | @@ -913,17 +942,17 @@ static int gmc_v6_0_soft_reset(void *handle) struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_mode_mc_save save; u32 srbm_soft_reset = 0; - u32 tmp = RREG32(SRBM_STATUS); + u32 tmp = RREG32(mmSRBM_STATUS); if (tmp & SRBM_STATUS__VMC_BUSY_MASK) srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, - mmSRBM_SOFT_RESET, xxSOFT_RESET_VMC, 1); + SRBM_SOFT_RESET, SOFT_RESET_VMC, 1); if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { if (!(adev->flags & AMD_IS_APU)) srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, - mmSRBM_SOFT_RESET, xxSOFT_RESET_MC, 1); + SRBM_SOFT_RESET, SOFT_RESET_MC, 1); } if (srbm_soft_reset) { @@ -933,17 +962,17 @@ static int gmc_v6_0_soft_reset(void *handle) } - tmp = RREG32(SRBM_SOFT_RESET); + tmp = RREG32(mmSRBM_SOFT_RESET); tmp |= srbm_soft_reset; dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); - WREG32(SRBM_SOFT_RESET, tmp); - tmp = RREG32(SRBM_SOFT_RESET); + WREG32(mmSRBM_SOFT_RESET, tmp); + tmp = RREG32(mmSRBM_SOFT_RESET); udelay(50); tmp &= ~srbm_soft_reset; - WREG32(SRBM_SOFT_RESET, tmp); - tmp = RREG32(SRBM_SOFT_RESET); + WREG32(mmSRBM_SOFT_RESET, tmp); + tmp = RREG32(mmSRBM_SOFT_RESET); udelay(50); @@ -969,20 +998,20 @@ static int gmc_v6_0_vm_fault_interrupt_state(struct amdgpu_device *adev, switch (state) { case AMDGPU_IRQ_STATE_DISABLE: - tmp = RREG32(VM_CONTEXT0_CNTL); + tmp = RREG32(mmVM_CONTEXT0_CNTL); tmp &= ~bits; - WREG32(VM_CONTEXT0_CNTL, tmp); - tmp = RREG32(VM_CONTEXT1_CNTL); + WREG32(mmVM_CONTEXT0_CNTL, tmp); + tmp = RREG32(mmVM_CONTEXT1_CNTL); tmp &= ~bits; - WREG32(VM_CONTEXT1_CNTL, tmp); + WREG32(mmVM_CONTEXT1_CNTL, tmp); break; case AMDGPU_IRQ_STATE_ENABLE: - tmp = RREG32(VM_CONTEXT0_CNTL); + tmp = RREG32(mmVM_CONTEXT0_CNTL); tmp |= bits; - WREG32(VM_CONTEXT0_CNTL, tmp); - tmp = RREG32(VM_CONTEXT1_CNTL); + WREG32(mmVM_CONTEXT0_CNTL, tmp); + tmp = RREG32(mmVM_CONTEXT1_CNTL); tmp |= bits; - WREG32(VM_CONTEXT1_CNTL, tmp); + WREG32(mmVM_CONTEXT1_CNTL, tmp); break; default: break; @@ -997,9 +1026,9 @@ static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev, { u32 addr, status; - addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR); - status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS); - WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1); + addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); + status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); + WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); if (!addr && !status) return 0; @@ -1007,13 +1036,15 @@ static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev, if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) gmc_v6_0_set_fault_enable_default(adev, false); - dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", - entry->src_id, entry->src_data); - dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", - addr); - dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", - status); - gmc_v6_0_vm_decode_fault(adev, status, addr, 0); + if (printk_ratelimit()) { + dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", + entry->src_id, entry->src_data); + dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", + addr); + dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", + status); + gmc_v6_0_vm_decode_fault(adev, status, addr, 0); + } return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index 3a25f72980c1..fbe1d9ac500a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -711,7 +711,7 @@ static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev, mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, MEMORY_CLIENT_ID); - printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", + dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", protections, vmid, addr, REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, MEMORY_CLIENT_RW) ? @@ -1198,13 +1198,15 @@ static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev, if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) gmc_v7_0_set_fault_enable_default(adev, false); - dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", - entry->src_id, entry->src_data); - dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", - addr); - dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", - status); - gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client); + if (printk_ratelimit()) { + dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", + entry->src_id, entry->src_data); + dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", + addr); + dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", + status); + gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client); + } return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index f7372d32b8e7..12ea3404dd65 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -837,7 +837,7 @@ static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev, mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, MEMORY_CLIENT_ID); - printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", + dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", protections, vmid, addr, REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, MEMORY_CLIENT_RW) ? @@ -1242,13 +1242,15 @@ static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev, if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) gmc_v8_0_set_fault_enable_default(adev, false); - dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", - entry->src_id, entry->src_data); - dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", - addr); - dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", - status); - gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client); + if (printk_ratelimit()) { + dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", + entry->src_id, entry->src_data); + dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", + addr); + dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", + status); + gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client); + } return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c index 61172d4a0657..5a1bc358bcb1 100644 --- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c @@ -2845,7 +2845,7 @@ static int kv_dpm_init(struct amdgpu_device *adev) pi->caps_tcp_ramping = true; } - if (amdgpu_sclk_deep_sleep_en) + if (amdgpu_pp_feature_mask & SCLK_DEEP_SLEEP_MASK) pi->caps_sclk_ds = true; else pi->caps_sclk_ds = false; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c index e81aa4682760..fbe74a33899c 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c @@ -775,11 +775,11 @@ static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, unsigned ndw = count * 2; ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | - SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); + SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); ib->ptr[ib->length_dw++] = pe; ib->ptr[ib->length_dw++] = upper_32_bits(pe); ib->ptr[ib->length_dw++] = ndw; - for (; ndw > 0; ndw -= 2, --count, pe += 8) { + for (; ndw > 0; ndw -= 2) { ib->ptr[ib->length_dw++] = lower_32_bits(value); ib->ptr[ib->length_dw++] = upper_32_bits(value); value += incr; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index 77f146587c60..1170a64a3184 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -977,11 +977,11 @@ static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, unsigned ndw = count * 2; ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | - SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); + SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); ib->ptr[ib->length_dw++] = lower_32_bits(pe); ib->ptr[ib->length_dw++] = upper_32_bits(pe); ib->ptr[ib->length_dw++] = ndw; - for (; ndw > 0; ndw -= 2, --count, pe += 8) { + for (; ndw > 0; ndw -= 2) { ib->ptr[ib->length_dw++] = lower_32_bits(value); ib->ptr[ib->length_dw++] = upper_32_bits(value); value += incr; diff --git a/drivers/gpu/drm/amd/amdgpu/si_enums.h b/drivers/gpu/drm/amd/amdgpu/si_enums.h new file mode 100644 index 000000000000..fde2086246fa --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/si_enums.h @@ -0,0 +1,272 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef SI_ENUMS_H +#define SI_ENUMS_H + +#define VBLANK_INT_MASK (1 << 0) +#define DC_HPDx_INT_EN (1 << 16) +#define VBLANK_ACK (1 << 4) +#define VLINE_ACK (1 << 4) + +#define CURSOR_WIDTH 64 +#define CURSOR_HEIGHT 64 + +#define VGA_VSTATUS_CNTL 0xFFFCFFFF +#define PRIORITY_MARK_MASK 0x7fff +#define PRIORITY_OFF (1 << 16) +#define PRIORITY_ALWAYS_ON (1 << 20) +#define INTERLEAVE_EN (1 << 0) + +#define LATENCY_WATERMARK_MASK(x) ((x) << 16) +#define DC_LB_MEMORY_CONFIG(x) ((x) << 20) +#define ICON_DEGAMMA_MODE(x) (((x) & 0x3) << 8) + +#define GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0) +#define GRPH_ENDIAN_NONE 0 +#define GRPH_ENDIAN_8IN16 1 +#define GRPH_ENDIAN_8IN32 2 +#define GRPH_ENDIAN_8IN64 3 + +#define GRPH_DEPTH(x) (((x) & 0x3) << 0) +#define GRPH_DEPTH_8BPP 0 +#define GRPH_DEPTH_16BPP 1 +#define GRPH_DEPTH_32BPP 2 + +#define GRPH_FORMAT(x) (((x) & 0x7) << 8) +#define GRPH_FORMAT_INDEXED 0 +#define GRPH_FORMAT_ARGB1555 0 +#define GRPH_FORMAT_ARGB565 1 +#define GRPH_FORMAT_ARGB4444 2 +#define GRPH_FORMAT_AI88 3 +#define GRPH_FORMAT_MONO16 4 +#define GRPH_FORMAT_BGRA5551 5 +#define GRPH_FORMAT_ARGB8888 0 +#define GRPH_FORMAT_ARGB2101010 1 +#define GRPH_FORMAT_32BPP_DIG 2 +#define GRPH_FORMAT_8B_ARGB2101010 3 +#define GRPH_FORMAT_BGRA1010102 4 +#define GRPH_FORMAT_8B_BGRA1010102 5 +#define GRPH_FORMAT_RGB111110 6 +#define GRPH_FORMAT_BGR101111 7 + +#define GRPH_NUM_BANKS(x) (((x) & 0x3) << 2) +#define GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20) +#define GRPH_ARRAY_LINEAR_GENERAL 0 +#define GRPH_ARRAY_LINEAR_ALIGNED 1 +#define GRPH_ARRAY_1D_TILED_THIN1 2 +#define GRPH_ARRAY_2D_TILED_THIN1 4 +#define GRPH_TILE_SPLIT(x) (((x) & 0x7) << 13) +#define GRPH_BANK_WIDTH(x) (((x) & 0x3) << 6) +#define GRPH_BANK_HEIGHT(x) (((x) & 0x3) << 11) +#define GRPH_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 18) +#define GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20) +#define GRPH_PIPE_CONFIG(x) (((x) & 0x1f) << 24) + +#define CURSOR_EN (1 << 0) +#define CURSOR_MODE(x) (((x) & 0x3) << 8) +#define CURSOR_MONO 0 +#define CURSOR_24_1 1 +#define CURSOR_24_8_PRE_MULT 2 +#define CURSOR_24_8_UNPRE_MULT 3 +#define CURSOR_2X_MAGNIFY (1 << 16) +#define CURSOR_FORCE_MC_ON (1 << 20) +#define CURSOR_URGENT_CONTROL(x) (((x) & 0x7) << 24) +#define CURSOR_URGENT_ALWAYS 0 +#define CURSOR_URGENT_1_8 1 +#define CURSOR_URGENT_1_4 2 +#define CURSOR_URGENT_3_8 3 +#define CURSOR_URGENT_1_2 4 +#define CURSOR_UPDATE_PENDING (1 << 0) +#define CURSOR_UPDATE_TAKEN (1 << 1) +#define CURSOR_UPDATE_LOCK (1 << 16) +#define CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24) + +#define AMDGPU_NUM_OF_VMIDS 8 +#define SI_CRTC0_REGISTER_OFFSET 0 +#define SI_CRTC1_REGISTER_OFFSET 0x300 +#define SI_CRTC2_REGISTER_OFFSET 0x2600 +#define SI_CRTC3_REGISTER_OFFSET 0x2900 +#define SI_CRTC4_REGISTER_OFFSET 0x2c00 +#define SI_CRTC5_REGISTER_OFFSET 0x2f00 + +#define DMA0_REGISTER_OFFSET 0x000 +#define DMA1_REGISTER_OFFSET 0x200 +#define ES_AND_GS_AUTO 3 +#define RADEON_PACKET_TYPE3 3 +#define CE_PARTITION_BASE 3 +#define BUF_SWAP_32BIT (2 << 16) + +#define GFX_POWER_STATUS (1 << 1) +#define GFX_CLOCK_STATUS (1 << 2) +#define GFX_LS_STATUS (1 << 3) +#define RLC_BUSY_STATUS (1 << 0) + +#define RLC_PUD(x) ((x) << 0) +#define RLC_PUD_MASK (0xff << 0) +#define RLC_PDD(x) ((x) << 8) +#define RLC_PDD_MASK (0xff << 8) +#define RLC_TTPD(x) ((x) << 16) +#define RLC_TTPD_MASK (0xff << 16) +#define RLC_MSD(x) ((x) << 24) +#define RLC_MSD_MASK (0xff << 24) +#define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) +#define WRITE_DATA_DST_SEL(x) ((x) << 8) +#define EVENT_TYPE(x) ((x) << 0) +#define EVENT_INDEX(x) ((x) << 8) +#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) +#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) +#define WAIT_REG_MEM_ENGINE(x) ((x) << 8) + +#define GFX6_NUM_GFX_RINGS 1 +#define GFX6_NUM_COMPUTE_RINGS 2 +#define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90 +#define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D + +#define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003 +#define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002 +#define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x02010001 + +#define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ + (((op) & 0xFF) << 8) | \ + ((n) & 0x3FFF) << 16) +#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) +#define PACKET3_NOP 0x10 +#define PACKET3_SET_BASE 0x11 +#define PACKET3_BASE_INDEX(x) ((x) << 0) +#define PACKET3_CLEAR_STATE 0x12 +#define PACKET3_INDEX_BUFFER_SIZE 0x13 +#define PACKET3_DISPATCH_DIRECT 0x15 +#define PACKET3_DISPATCH_INDIRECT 0x16 +#define PACKET3_ALLOC_GDS 0x1B +#define PACKET3_WRITE_GDS_RAM 0x1C +#define PACKET3_ATOMIC_GDS 0x1D +#define PACKET3_ATOMIC 0x1E +#define PACKET3_OCCLUSION_QUERY 0x1F +#define PACKET3_SET_PREDICATION 0x20 +#define PACKET3_REG_RMW 0x21 +#define PACKET3_COND_EXEC 0x22 +#define PACKET3_PRED_EXEC 0x23 +#define PACKET3_DRAW_INDIRECT 0x24 +#define PACKET3_DRAW_INDEX_INDIRECT 0x25 +#define PACKET3_INDEX_BASE 0x26 +#define PACKET3_DRAW_INDEX_2 0x27 +#define PACKET3_CONTEXT_CONTROL 0x28 +#define PACKET3_INDEX_TYPE 0x2A +#define PACKET3_DRAW_INDIRECT_MULTI 0x2C +#define PACKET3_DRAW_INDEX_AUTO 0x2D +#define PACKET3_DRAW_INDEX_IMMD 0x2E +#define PACKET3_NUM_INSTANCES 0x2F +#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 +#define PACKET3_INDIRECT_BUFFER_CONST 0x31 +#define PACKET3_INDIRECT_BUFFER 0x3F +#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 +#define PACKET3_DRAW_INDEX_OFFSET_2 0x35 +#define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 +#define PACKET3_WRITE_DATA 0x37 +#define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 +#define PACKET3_MEM_SEMAPHORE 0x39 +#define PACKET3_MPEG_INDEX 0x3A +#define PACKET3_COPY_DW 0x3B +#define PACKET3_WAIT_REG_MEM 0x3C +#define PACKET3_MEM_WRITE 0x3D +#define PACKET3_COPY_DATA 0x40 +#define PACKET3_CP_DMA 0x41 +# define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20) +# define PACKET3_CP_DMA_ENGINE(x) ((x) << 27) +# define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29) +# define PACKET3_CP_DMA_CP_SYNC (1 << 31) +# define PACKET3_CP_DMA_DIS_WC (1 << 21) +# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22) +# define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) +# define PACKET3_CP_DMA_CMD_SAS (1 << 26) +# define PACKET3_CP_DMA_CMD_DAS (1 << 27) +# define PACKET3_CP_DMA_CMD_SAIC (1 << 28) +# define PACKET3_CP_DMA_CMD_DAIC (1 << 29) +# define PACKET3_CP_DMA_CMD_RAW_WAIT (1 << 30) +#define PACKET3_PFP_SYNC_ME 0x42 +#define PACKET3_SURFACE_SYNC 0x43 +# define PACKET3_DEST_BASE_0_ENA (1 << 0) +# define PACKET3_DEST_BASE_1_ENA (1 << 1) +# define PACKET3_CB0_DEST_BASE_ENA (1 << 6) +# define PACKET3_CB1_DEST_BASE_ENA (1 << 7) +# define PACKET3_CB2_DEST_BASE_ENA (1 << 8) +# define PACKET3_CB3_DEST_BASE_ENA (1 << 9) +# define PACKET3_CB4_DEST_BASE_ENA (1 << 10) +# define PACKET3_CB5_DEST_BASE_ENA (1 << 11) +# define PACKET3_CB6_DEST_BASE_ENA (1 << 12) +# define PACKET3_CB7_DEST_BASE_ENA (1 << 13) +# define PACKET3_DB_DEST_BASE_ENA (1 << 14) +# define PACKET3_DEST_BASE_2_ENA (1 << 19) +# define PACKET3_DEST_BASE_3_ENA (1 << 21) +# define PACKET3_TCL1_ACTION_ENA (1 << 22) +# define PACKET3_TC_ACTION_ENA (1 << 23) +# define PACKET3_CB_ACTION_ENA (1 << 25) +# define PACKET3_DB_ACTION_ENA (1 << 26) +# define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) +# define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) +#define PACKET3_ME_INITIALIZE 0x44 +#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) +#define PACKET3_COND_WRITE 0x45 +#define PACKET3_EVENT_WRITE 0x46 +#define PACKET3_EVENT_WRITE_EOP 0x47 +#define PACKET3_EVENT_WRITE_EOS 0x48 +#define PACKET3_PREAMBLE_CNTL 0x4A +# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) +# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) +#define PACKET3_ONE_REG_WRITE 0x57 +#define PACKET3_LOAD_CONFIG_REG 0x5F +#define PACKET3_LOAD_CONTEXT_REG 0x60 +#define PACKET3_LOAD_SH_REG 0x61 +#define PACKET3_SET_CONFIG_REG 0x68 +#define PACKET3_SET_CONFIG_REG_START 0x00002000 +#define PACKET3_SET_CONFIG_REG_END 0x00002c00 +#define PACKET3_SET_CONTEXT_REG 0x69 +#define PACKET3_SET_CONTEXT_REG_START 0x000a000 +#define PACKET3_SET_CONTEXT_REG_END 0x000a400 +#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 +#define PACKET3_SET_RESOURCE_INDIRECT 0x74 +#define PACKET3_SET_SH_REG 0x76 +#define PACKET3_SET_SH_REG_START 0x00002c00 +#define PACKET3_SET_SH_REG_END 0x00003000 +#define PACKET3_SET_SH_REG_OFFSET 0x77 +#define PACKET3_ME_WRITE 0x7A +#define PACKET3_SCRATCH_RAM_WRITE 0x7D +#define PACKET3_SCRATCH_RAM_READ 0x7E +#define PACKET3_CE_WRITE 0x7F +#define PACKET3_LOAD_CONST_RAM 0x80 +#define PACKET3_WRITE_CONST_RAM 0x81 +#define PACKET3_WRITE_CONST_RAM_OFFSET 0x82 +#define PACKET3_DUMP_CONST_RAM 0x83 +#define PACKET3_INCREMENT_CE_COUNTER 0x84 +#define PACKET3_INCREMENT_DE_COUNTER 0x85 +#define PACKET3_WAIT_ON_CE_COUNTER 0x86 +#define PACKET3_WAIT_ON_DE_COUNTER 0x87 +#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 +#define PACKET3_SET_CE_DE_COUNTERS 0x89 +#define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A +#define PACKET3_SWITCH_BUFFER 0x8B +#define PACKET3_SEM_WAIT_ON_SIGNAL (0x1 << 12) +#define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) +#define PACKET3_SEM_SEL_WAIT (0x7 << 29) + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c index 8f9c7d55ddda..96444e4d862a 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c @@ -45,7 +45,8 @@ static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev); static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev); static int uvd_v4_2_start(struct amdgpu_device *adev); static void uvd_v4_2_stop(struct amdgpu_device *adev); - +static int uvd_v4_2_set_clockgating_state(void *handle, + enum amd_clockgating_state state); /** * uvd_v4_2_ring_get_rptr - get read pointer * @@ -154,9 +155,9 @@ static int uvd_v4_2_hw_init(void *handle) uint32_t tmp; int r; - /* raise clocks while booting up the VCPU */ - amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); - + uvd_v4_2_init_cg(adev); + uvd_v4_2_set_clockgating_state(adev, AMD_CG_STATE_GATE); + amdgpu_asic_set_uvd_clocks(adev, 10000, 10000); r = uvd_v4_2_start(adev); if (r) goto done; @@ -196,8 +197,6 @@ static int uvd_v4_2_hw_init(void *handle) amdgpu_ring_commit(ring); done: - /* lower clocks again */ - amdgpu_asic_set_uvd_clocks(adev, 0, 0); if (!r) DRM_INFO("UVD initialized successfully.\n"); @@ -274,9 +273,6 @@ static int uvd_v4_2_start(struct amdgpu_device *adev) uvd_v4_2_mc_resume(adev); - /* disable clock gating */ - WREG32(mmUVD_CGC_GATE, 0); - /* disable interupt */ WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); @@ -568,8 +564,6 @@ static void uvd_v4_2_mc_resume(struct amdgpu_device *adev) WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); - - uvd_v4_2_init_cg(adev); } static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev, @@ -579,7 +573,7 @@ static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev, if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) { data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); - data = 0xfff; + data |= 0xfff; WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); orig = data = RREG32(mmUVD_CGC_CTRL); @@ -603,6 +597,8 @@ static void uvd_v4_2_set_dcm(struct amdgpu_device *adev, { u32 tmp, tmp2; + WREG32_FIELD(UVD_CGC_GATE, REGS, 0); + tmp = RREG32(mmUVD_CGC_CTRL); tmp &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); tmp |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | @@ -686,34 +682,18 @@ static int uvd_v4_2_process_interrupt(struct amdgpu_device *adev, return 0; } -static void uvd_v5_0_set_bypass_mode(struct amdgpu_device *adev, bool enable) -{ - u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL); - - if (enable) - tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK | - GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK); - else - tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK | - GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK); - - WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp); -} - static int uvd_v4_2_set_clockgating_state(void *handle, enum amd_clockgating_state state) { bool gate = false; struct amdgpu_device *adev = (struct amdgpu_device *)handle; - if (state == AMD_CG_STATE_GATE) - gate = true; - - uvd_v5_0_set_bypass_mode(adev, gate); - if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) return 0; + if (state == AMD_CG_STATE_GATE) + gate = true; + uvd_v4_2_enable_mgcg(adev, gate); return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c index 95303e2d5f92..95cabeafc18e 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c @@ -40,7 +40,10 @@ static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev); static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev); static int uvd_v5_0_start(struct amdgpu_device *adev); static void uvd_v5_0_stop(struct amdgpu_device *adev); - +static int uvd_v5_0_set_clockgating_state(void *handle, + enum amd_clockgating_state state); +static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev, + bool enable); /** * uvd_v5_0_ring_get_rptr - get read pointer * @@ -149,9 +152,6 @@ static int uvd_v5_0_hw_init(void *handle) uint32_t tmp; int r; - /* raise clocks while booting up the VCPU */ - amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); - r = uvd_v5_0_start(adev); if (r) goto done; @@ -189,11 +189,7 @@ static int uvd_v5_0_hw_init(void *handle) amdgpu_ring_write(ring, 3); amdgpu_ring_commit(ring); - done: - /* lower clocks again */ - amdgpu_asic_set_uvd_clocks(adev, 0, 0); - if (!r) DRM_INFO("UVD initialized successfully.\n"); @@ -226,6 +222,7 @@ static int uvd_v5_0_suspend(void *handle) r = uvd_v5_0_hw_fini(adev); if (r) return r; + uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_GATE); r = amdgpu_uvd_suspend(adev); if (r) @@ -313,8 +310,9 @@ static int uvd_v5_0_start(struct amdgpu_device *adev) uvd_v5_0_mc_resume(adev); - /* disable clock gating */ - WREG32(mmUVD_CGC_GATE, 0); + amdgpu_asic_set_uvd_clocks(adev, 10000, 10000); + uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE); + uvd_v5_0_enable_mgcg(adev, true); /* disable interupt */ WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); @@ -628,16 +626,12 @@ static int uvd_v5_0_process_interrupt(struct amdgpu_device *adev, return 0; } -static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev) +static void uvd_v5_0_enable_clock_gating(struct amdgpu_device *adev, bool enable) { - uint32_t data, data1, data2, suvd_flags; + uint32_t data1, data3, suvd_flags; - data = RREG32(mmUVD_CGC_CTRL); data1 = RREG32(mmUVD_SUVD_CGC_GATE); - data2 = RREG32(mmUVD_SUVD_CGC_CTRL); - - data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | - UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); + data3 = RREG32(mmUVD_CGC_GATE); suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | UVD_SUVD_CGC_GATE__SIT_MASK | @@ -645,6 +639,49 @@ static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev) UVD_SUVD_CGC_GATE__SCM_MASK | UVD_SUVD_CGC_GATE__SDB_MASK; + if (enable) { + data3 |= (UVD_CGC_GATE__SYS_MASK | + UVD_CGC_GATE__UDEC_MASK | + UVD_CGC_GATE__MPEG2_MASK | + UVD_CGC_GATE__RBC_MASK | + UVD_CGC_GATE__LMI_MC_MASK | + UVD_CGC_GATE__IDCT_MASK | + UVD_CGC_GATE__MPRD_MASK | + UVD_CGC_GATE__MPC_MASK | + UVD_CGC_GATE__LBSI_MASK | + UVD_CGC_GATE__LRBBM_MASK | + UVD_CGC_GATE__UDEC_RE_MASK | + UVD_CGC_GATE__UDEC_CM_MASK | + UVD_CGC_GATE__UDEC_IT_MASK | + UVD_CGC_GATE__UDEC_DB_MASK | + UVD_CGC_GATE__UDEC_MP_MASK | + UVD_CGC_GATE__WCB_MASK | + UVD_CGC_GATE__VCPU_MASK | + UVD_CGC_GATE__JPEG_MASK | + UVD_CGC_GATE__SCPU_MASK); + data3 &= ~UVD_CGC_GATE__REGS_MASK; + data1 |= suvd_flags; + } else { + data3 = 0; + data1 = 0; + } + + WREG32(mmUVD_SUVD_CGC_GATE, data1); + WREG32(mmUVD_CGC_GATE, data3); +} + +static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev) +{ + uint32_t data, data2; + + data = RREG32(mmUVD_CGC_CTRL); + data2 = RREG32(mmUVD_SUVD_CGC_CTRL); + + + data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | + UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); + + data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) | (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY)); @@ -675,11 +712,8 @@ static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev) UVD_SUVD_CGC_CTRL__SMP_MODE_MASK | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK); - data1 |= suvd_flags; WREG32(mmUVD_CGC_CTRL, data); - WREG32(mmUVD_CGC_GATE, 0); - WREG32(mmUVD_SUVD_CGC_GATE, data1); WREG32(mmUVD_SUVD_CGC_CTRL, data2); } @@ -724,18 +758,30 @@ static void uvd_v5_0_set_hw_clock_gating(struct amdgpu_device *adev) } #endif -static void uvd_v5_0_set_bypass_mode(struct amdgpu_device *adev, bool enable) +static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev, + bool enable) { - u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL); + u32 orig, data; - if (enable) - tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK | - GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK); - else - tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK | - GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK); + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) { + data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); + data |= 0xfff; + WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); - WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp); + orig = data = RREG32(mmUVD_CGC_CTRL); + data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; + if (orig != data) + WREG32(mmUVD_CGC_CTRL, data); + } else { + data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); + data &= ~0xfff; + WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); + + orig = data = RREG32(mmUVD_CGC_CTRL); + data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; + if (orig != data) + WREG32(mmUVD_CGC_CTRL, data); + } } static int uvd_v5_0_set_clockgating_state(void *handle, @@ -745,8 +791,6 @@ static int uvd_v5_0_set_clockgating_state(void *handle, bool enable = (state == AMD_CG_STATE_GATE) ? true : false; static int curstate = -1; - uvd_v5_0_set_bypass_mode(adev, enable); - if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) return 0; @@ -755,17 +799,18 @@ static int uvd_v5_0_set_clockgating_state(void *handle, curstate = state; if (enable) { - /* disable HW gating and enable Sw gating */ - uvd_v5_0_set_sw_clock_gating(adev); - } else { /* wait for STATUS to clear */ if (uvd_v5_0_wait_for_idle(handle)) return -EBUSY; + uvd_v5_0_enable_clock_gating(adev, true); /* enable HW gates because UVD is idle */ /* uvd_v5_0_set_hw_clock_gating(adev); */ + } else { + uvd_v5_0_enable_clock_gating(adev, false); } + uvd_v5_0_set_sw_clock_gating(adev); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c index a339b5ccb296..00fad6951d82 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c @@ -151,6 +151,8 @@ static int uvd_v6_0_hw_init(void *handle) uint32_t tmp; int r; + amdgpu_asic_set_uvd_clocks(adev, 10000, 10000); + r = uvd_v6_0_start(adev); if (r) goto done; @@ -935,28 +937,12 @@ static void uvd_v6_0_set_hw_clock_gating(struct amdgpu_device *adev) } #endif -static void uvd_v6_0_set_bypass_mode(struct amdgpu_device *adev, bool enable) -{ - u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL); - - if (enable) - tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK | - GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK); - else - tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK | - GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK); - - WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp); -} - static int uvd_v6_0_set_clockgating_state(void *handle, enum amd_clockgating_state state) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; bool enable = (state == AMD_CG_STATE_GATE) ? true : false; - uvd_v6_0_set_bypass_mode(adev, enable); - if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index 52d0a83e6ad1..243dcf7bae47 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -80,7 +80,9 @@ #include "dce_virtual.h" MODULE_FIRMWARE("amdgpu/topaz_smc.bin"); +MODULE_FIRMWARE("amdgpu/topaz_k_smc.bin"); MODULE_FIRMWARE("amdgpu/tonga_smc.bin"); +MODULE_FIRMWARE("amdgpu/tonga_k_smc.bin"); MODULE_FIRMWARE("amdgpu/fiji_smc.bin"); MODULE_FIRMWARE("amdgpu/polaris10_smc.bin"); MODULE_FIRMWARE("amdgpu/polaris10_smc_sk.bin"); @@ -924,7 +926,8 @@ static int vi_common_early_init(void *handle) AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_ROM_MGCG | AMD_CG_SUPPORT_MC_MGCG | - AMD_CG_SUPPORT_MC_LS; + AMD_CG_SUPPORT_MC_LS | + AMD_CG_SUPPORT_UVD_MGCG; adev->pg_flags = 0; adev->external_rev_id = adev->rev_id + 0x3c; break; @@ -934,12 +937,12 @@ static int vi_common_early_init(void *handle) adev->external_rev_id = adev->rev_id + 0x14; break; case CHIP_POLARIS11: - adev->cg_flags = 0; + adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG; adev->pg_flags = 0; adev->external_rev_id = adev->rev_id + 0x5A; break; case CHIP_POLARIS10: - adev->cg_flags = 0; + adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG; adev->pg_flags = 0; adev->external_rev_id = adev->rev_id + 0x50; break; diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_d.h new file mode 100644 index 000000000000..7138fbf7256a --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_d.h @@ -0,0 +1,661 @@ +/* + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef BIF_3_0_D_H +#define BIF_3_0_D_H + +#define ixPB0_DFT_DEBUG_CTRL_REG0 0x1300C +#define ixPB0_DFT_JIT_INJ_REG0 0x13000 +#define ixPB0_DFT_JIT_INJ_REG1 0x13004 +#define ixPB0_DFT_JIT_INJ_REG2 0x13008 +#define ixPB0_GLB_CTRL_REG0 0x10004 +#define ixPB0_GLB_CTRL_REG1 0x10008 +#define ixPB0_GLB_CTRL_REG2 0x1000C +#define ixPB0_GLB_CTRL_REG3 0x10010 +#define ixPB0_GLB_CTRL_REG4 0x10014 +#define ixPB0_GLB_CTRL_REG5 0x10018 +#define ixPB0_GLB_OVRD_REG0 0x10030 +#define ixPB0_GLB_OVRD_REG1 0x10034 +#define ixPB0_GLB_OVRD_REG2 0x10038 +#define ixPB0_GLB_SCI_STAT_OVRD_REG0 0x1001C +#define ixPB0_GLB_SCI_STAT_OVRD_REG1 0x10020 +#define ixPB0_GLB_SCI_STAT_OVRD_REG2 0x10024 +#define ixPB0_GLB_SCI_STAT_OVRD_REG3 0x10028 +#define ixPB0_GLB_SCI_STAT_OVRD_REG4 0x1002C +#define ixPB0_HW_DEBUG 0x12004 +#define ixPB0_PIF_CNTL 0x0010 +#define ixPB0_PIF_CNTL2 0x0014 +#define ixPB0_PIF_HW_DEBUG 0x0002 +#define ixPB0_PIF_PAIRING 0x0011 +#define ixPB0_PIF_PDNB_OVERRIDE_0 0x0020 +#define ixPB0_PIF_PDNB_OVERRIDE_10 0x0032 +#define ixPB0_PIF_PDNB_OVERRIDE_1 0x0021 +#define ixPB0_PIF_PDNB_OVERRIDE_11 0x0033 +#define ixPB0_PIF_PDNB_OVERRIDE_12 0x0034 +#define ixPB0_PIF_PDNB_OVERRIDE_13 0x0035 +#define ixPB0_PIF_PDNB_OVERRIDE_14 0x0036 +#define ixPB0_PIF_PDNB_OVERRIDE_15 0x0037 +#define ixPB0_PIF_PDNB_OVERRIDE_2 0x0022 +#define ixPB0_PIF_PDNB_OVERRIDE_3 0x0023 +#define ixPB0_PIF_PDNB_OVERRIDE_4 0x0024 +#define ixPB0_PIF_PDNB_OVERRIDE_5 0x0025 +#define ixPB0_PIF_PDNB_OVERRIDE_6 0x0026 +#define ixPB0_PIF_PDNB_OVERRIDE_7 0x0027 +#define ixPB0_PIF_PDNB_OVERRIDE_8 0x0030 +#define ixPB0_PIF_PDNB_OVERRIDE_9 0x0031 +#define ixPB0_PIF_PWRDOWN_0 0x0012 +#define ixPB0_PIF_PWRDOWN_1 0x0013 +#define ixPB0_PIF_PWRDOWN_2 0x0017 +#define ixPB0_PIF_PWRDOWN_3 0x0018 +#define ixPB0_PIF_SC_CTL 0x0016 +#define ixPB0_PIF_SCRATCH 0x0001 +#define ixPB0_PIF_SEQ_STATUS_0 0x0028 +#define ixPB0_PIF_SEQ_STATUS_10 0x003A +#define ixPB0_PIF_SEQ_STATUS_1 0x0029 +#define ixPB0_PIF_SEQ_STATUS_11 0x003B +#define ixPB0_PIF_SEQ_STATUS_12 0x003C +#define ixPB0_PIF_SEQ_STATUS_13 0x003D +#define ixPB0_PIF_SEQ_STATUS_14 0x003E +#define ixPB0_PIF_SEQ_STATUS_15 0x003F +#define ixPB0_PIF_SEQ_STATUS_2 0x002A +#define ixPB0_PIF_SEQ_STATUS_3 0x002B +#define ixPB0_PIF_SEQ_STATUS_4 0x002C +#define ixPB0_PIF_SEQ_STATUS_5 0x002D +#define ixPB0_PIF_SEQ_STATUS_6 0x002E +#define ixPB0_PIF_SEQ_STATUS_7 0x002F +#define ixPB0_PIF_SEQ_STATUS_8 0x0038 +#define ixPB0_PIF_SEQ_STATUS_9 0x0039 +#define ixPB0_PIF_TXPHYSTATUS 0x0015 +#define ixPB0_PLL_LC0_CTRL_REG0 0x14480 +#define ixPB0_PLL_LC0_OVRD_REG0 0x14490 +#define ixPB0_PLL_LC0_OVRD_REG1 0x14494 +#define ixPB0_PLL_LC0_SCI_STAT_OVRD_REG0 0x14500 +#define ixPB0_PLL_LC1_SCI_STAT_OVRD_REG0 0x14504 +#define ixPB0_PLL_LC2_SCI_STAT_OVRD_REG0 0x14508 +#define ixPB0_PLL_LC3_SCI_STAT_OVRD_REG0 0x1450C +#define ixPB0_PLL_RO0_CTRL_REG0 0x14440 +#define ixPB0_PLL_RO0_OVRD_REG0 0x14450 +#define ixPB0_PLL_RO0_OVRD_REG1 0x14454 +#define ixPB0_PLL_RO0_SCI_STAT_OVRD_REG0 0x14460 +#define ixPB0_PLL_RO1_SCI_STAT_OVRD_REG0 0x14464 +#define ixPB0_PLL_RO2_SCI_STAT_OVRD_REG0 0x14468 +#define ixPB0_PLL_RO3_SCI_STAT_OVRD_REG0 0x1446C +#define ixPB0_PLL_RO_GLB_CTRL_REG0 0x14000 +#define ixPB0_PLL_RO_GLB_OVRD_REG0 0x14010 +#define ixPB0_RX_GLB_CTRL_REG0 0x16000 +#define ixPB0_RX_GLB_CTRL_REG1 0x16004 +#define ixPB0_RX_GLB_CTRL_REG2 0x16008 +#define ixPB0_RX_GLB_CTRL_REG3 0x1600C +#define ixPB0_RX_GLB_CTRL_REG4 0x16010 +#define ixPB0_RX_GLB_CTRL_REG5 0x16014 +#define ixPB0_RX_GLB_CTRL_REG6 0x16018 +#define ixPB0_RX_GLB_CTRL_REG7 0x1601C +#define ixPB0_RX_GLB_CTRL_REG8 0x16020 +#define ixPB0_RX_GLB_OVRD_REG0 0x16030 +#define ixPB0_RX_GLB_OVRD_REG1 0x16034 +#define ixPB0_RX_GLB_SCI_STAT_OVRD_REG0 0x16028 +#define ixPB0_RX_LANE0_CTRL_REG0 0x16440 +#define ixPB0_RX_LANE0_SCI_STAT_OVRD_REG0 0x16448 +#define ixPB0_RX_LANE10_CTRL_REG0 0x17500 +#define ixPB0_RX_LANE10_SCI_STAT_OVRD_REG0 0x17508 +#define ixPB0_RX_LANE11_CTRL_REG0 0x17600 +#define ixPB0_RX_LANE11_SCI_STAT_OVRD_REG0 0x17608 +#define ixPB0_RX_LANE12_CTRL_REG0 0x17840 +#define ixPB0_RX_LANE12_SCI_STAT_OVRD_REG0 0x17848 +#define ixPB0_RX_LANE13_CTRL_REG0 0x17880 +#define ixPB0_RX_LANE13_SCI_STAT_OVRD_REG0 0x17888 +#define ixPB0_RX_LANE14_CTRL_REG0 0x17900 +#define ixPB0_RX_LANE14_SCI_STAT_OVRD_REG0 0x17908 +#define ixPB0_RX_LANE15_CTRL_REG0 0x17A00 +#define ixPB0_RX_LANE15_SCI_STAT_OVRD_REG0 0x17A08 +#define ixPB0_RX_LANE1_CTRL_REG0 0x16480 +#define ixPB0_RX_LANE1_SCI_STAT_OVRD_REG0 0x16488 +#define ixPB0_RX_LANE2_CTRL_REG0 0x16500 +#define ixPB0_RX_LANE2_SCI_STAT_OVRD_REG0 0x16508 +#define ixPB0_RX_LANE3_CTRL_REG0 0x16600 +#define ixPB0_RX_LANE3_SCI_STAT_OVRD_REG0 0x16608 +#define ixPB0_RX_LANE4_CTRL_REG0 0x16800 +#define ixPB0_RX_LANE4_SCI_STAT_OVRD_REG0 0x16848 +#define ixPB0_RX_LANE5_CTRL_REG0 0x16880 +#define ixPB0_RX_LANE5_SCI_STAT_OVRD_REG0 0x16888 +#define ixPB0_RX_LANE6_CTRL_REG0 0x16900 +#define ixPB0_RX_LANE6_SCI_STAT_OVRD_REG0 0x16908 +#define ixPB0_RX_LANE7_CTRL_REG0 0x16A00 +#define ixPB0_RX_LANE7_SCI_STAT_OVRD_REG0 0x16A08 +#define ixPB0_RX_LANE8_CTRL_REG0 0x17440 +#define ixPB0_RX_LANE8_SCI_STAT_OVRD_REG0 0x17448 +#define ixPB0_RX_LANE9_CTRL_REG0 0x17480 +#define ixPB0_RX_LANE9_SCI_STAT_OVRD_REG0 0x17488 +#define ixPB0_STRAP_GLB_REG0 0x12020 +#define ixPB0_STRAP_PLL_REG0 0x12030 +#define ixPB0_STRAP_RX_REG0 0x12028 +#define ixPB0_STRAP_RX_REG1 0x1202C +#define ixPB0_STRAP_TX_REG0 0x12024 +#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0 0x18014 +#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1 0x18018 +#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2 0x1801C +#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3 0x18020 +#define ixPB0_TX_GLB_CTRL_REG0 0x18000 +#define ixPB0_TX_GLB_LANE_SKEW_CTRL 0x18004 +#define ixPB0_TX_GLB_OVRD_REG0 0x18030 +#define ixPB0_TX_GLB_OVRD_REG1 0x18034 +#define ixPB0_TX_GLB_OVRD_REG2 0x18038 +#define ixPB0_TX_GLB_OVRD_REG3 0x1803C +#define ixPB0_TX_GLB_OVRD_REG4 0x18040 +#define ixPB0_TX_GLB_SCI_STAT_OVRD_REG0 0x18010 +#define ixPB0_TX_LANE0_CTRL_REG0 0x18440 +#define ixPB0_TX_LANE0_OVRD_REG0 0x18444 +#define ixPB0_TX_LANE0_SCI_STAT_OVRD_REG0 0x18448 +#define ixPB0_TX_LANE10_CTRL_REG0 0x19500 +#define ixPB0_TX_LANE10_OVRD_REG0 0x19504 +#define ixPB0_TX_LANE10_SCI_STAT_OVRD_REG0 0x19508 +#define ixPB0_TX_LANE11_CTRL_REG0 0x19600 +#define ixPB0_TX_LANE11_OVRD_REG0 0x19604 +#define ixPB0_TX_LANE11_SCI_STAT_OVRD_REG0 0x19608 +#define ixPB0_TX_LANE12_CTRL_REG0 0x19840 +#define ixPB0_TX_LANE12_OVRD_REG0 0x19844 +#define ixPB0_TX_LANE12_SCI_STAT_OVRD_REG0 0x19848 +#define ixPB0_TX_LANE13_CTRL_REG0 0x19880 +#define ixPB0_TX_LANE13_OVRD_REG0 0x19884 +#define ixPB0_TX_LANE13_SCI_STAT_OVRD_REG0 0x19888 +#define ixPB0_TX_LANE14_CTRL_REG0 0x19900 +#define ixPB0_TX_LANE14_OVRD_REG0 0x19904 +#define ixPB0_TX_LANE14_SCI_STAT_OVRD_REG0 0x19908 +#define ixPB0_TX_LANE15_CTRL_REG0 0x19A00 +#define ixPB0_TX_LANE15_OVRD_REG0 0x19A04 +#define ixPB0_TX_LANE15_SCI_STAT_OVRD_REG0 0x19A08 +#define ixPB0_TX_LANE1_CTRL_REG0 0x18480 +#define ixPB0_TX_LANE1_OVRD_REG0 0x18484 +#define ixPB0_TX_LANE1_SCI_STAT_OVRD_REG0 0x18488 +#define ixPB0_TX_LANE2_CTRL_REG0 0x18500 +#define ixPB0_TX_LANE2_OVRD_REG0 0x18504 +#define ixPB0_TX_LANE2_SCI_STAT_OVRD_REG0 0x18508 +#define ixPB0_TX_LANE3_CTRL_REG0 0x18600 +#define ixPB0_TX_LANE3_OVRD_REG0 0x18604 +#define ixPB0_TX_LANE3_SCI_STAT_OVRD_REG0 0x18608 +#define ixPB0_TX_LANE4_CTRL_REG0 0x18840 +#define ixPB0_TX_LANE4_OVRD_REG0 0x18844 +#define ixPB0_TX_LANE4_SCI_STAT_OVRD_REG0 0x18848 +#define ixPB0_TX_LANE5_CTRL_REG0 0x18880 +#define ixPB0_TX_LANE5_OVRD_REG0 0x18884 +#define ixPB0_TX_LANE5_SCI_STAT_OVRD_REG0 0x18888 +#define ixPB0_TX_LANE6_CTRL_REG0 0x18900 +#define ixPB0_TX_LANE6_OVRD_REG0 0x18904 +#define ixPB0_TX_LANE6_SCI_STAT_OVRD_REG0 0x18908 +#define ixPB0_TX_LANE7_CTRL_REG0 0x18A00 +#define ixPB0_TX_LANE7_OVRD_REG0 0x18A04 +#define ixPB0_TX_LANE7_SCI_STAT_OVRD_REG0 0x18A08 +#define ixPB0_TX_LANE8_CTRL_REG0 0x19440 +#define ixPB0_TX_LANE8_OVRD_REG0 0x19444 +#define ixPB0_TX_LANE8_SCI_STAT_OVRD_REG0 0x19448 +#define ixPB0_TX_LANE9_CTRL_REG0 0x19480 +#define ixPB0_TX_LANE9_OVRD_REG0 0x19484 +#define ixPB0_TX_LANE9_SCI_STAT_OVRD_REG0 0x19488 +#define ixPB1_DFT_DEBUG_CTRL_REG0 0x1300C +#define ixPB1_DFT_JIT_INJ_REG0 0x13000 +#define ixPB1_DFT_JIT_INJ_REG1 0x13004 +#define ixPB1_DFT_JIT_INJ_REG2 0x13008 +#define ixPB1_GLB_CTRL_REG0 0x10004 +#define ixPB1_GLB_CTRL_REG1 0x10008 +#define ixPB1_GLB_CTRL_REG2 0x1000C +#define ixPB1_GLB_CTRL_REG3 0x10010 +#define ixPB1_GLB_CTRL_REG4 0x10014 +#define ixPB1_GLB_CTRL_REG5 0x10018 +#define ixPB1_GLB_OVRD_REG0 0x10030 +#define ixPB1_GLB_OVRD_REG1 0x10034 +#define ixPB1_GLB_OVRD_REG2 0x10038 +#define ixPB1_GLB_SCI_STAT_OVRD_REG0 0x1001C +#define ixPB1_GLB_SCI_STAT_OVRD_REG1 0x10020 +#define ixPB1_GLB_SCI_STAT_OVRD_REG2 0x10024 +#define ixPB1_GLB_SCI_STAT_OVRD_REG3 0x10028 +#define ixPB1_GLB_SCI_STAT_OVRD_REG4 0x1002C +#define ixPB1_HW_DEBUG 0x12004 +#define ixPB1_PIF_CNTL 0x0010 +#define ixPB1_PIF_CNTL2 0x0014 +#define ixPB1_PIF_HW_DEBUG 0x0002 +#define ixPB1_PIF_PAIRING 0x0011 +#define ixPB1_PIF_PDNB_OVERRIDE_0 0x0020 +#define ixPB1_PIF_PDNB_OVERRIDE_10 0x0032 +#define ixPB1_PIF_PDNB_OVERRIDE_1 0x0021 +#define ixPB1_PIF_PDNB_OVERRIDE_11 0x0033 +#define ixPB1_PIF_PDNB_OVERRIDE_12 0x0034 +#define ixPB1_PIF_PDNB_OVERRIDE_13 0x0035 +#define ixPB1_PIF_PDNB_OVERRIDE_14 0x0036 +#define ixPB1_PIF_PDNB_OVERRIDE_15 0x0037 +#define ixPB1_PIF_PDNB_OVERRIDE_2 0x0022 +#define ixPB1_PIF_PDNB_OVERRIDE_3 0x0023 +#define ixPB1_PIF_PDNB_OVERRIDE_4 0x0024 +#define ixPB1_PIF_PDNB_OVERRIDE_5 0x0025 +#define ixPB1_PIF_PDNB_OVERRIDE_6 0x0026 +#define ixPB1_PIF_PDNB_OVERRIDE_7 0x0027 +#define ixPB1_PIF_PDNB_OVERRIDE_8 0x0030 +#define ixPB1_PIF_PDNB_OVERRIDE_9 0x0031 +#define ixPB1_PIF_PWRDOWN_0 0x0012 +#define ixPB1_PIF_PWRDOWN_1 0x0013 +#define ixPB1_PIF_PWRDOWN_2 0x0017 +#define ixPB1_PIF_PWRDOWN_3 0x0018 +#define ixPB1_PIF_SC_CTL 0x0016 +#define ixPB1_PIF_SCRATCH 0x0001 +#define ixPB1_PIF_SEQ_STATUS_0 0x0028 +#define ixPB1_PIF_SEQ_STATUS_10 0x003A +#define ixPB1_PIF_SEQ_STATUS_1 0x0029 +#define ixPB1_PIF_SEQ_STATUS_11 0x003B +#define ixPB1_PIF_SEQ_STATUS_12 0x003C +#define ixPB1_PIF_SEQ_STATUS_13 0x003D +#define ixPB1_PIF_SEQ_STATUS_14 0x003E +#define ixPB1_PIF_SEQ_STATUS_15 0x003F +#define ixPB1_PIF_SEQ_STATUS_2 0x002A +#define ixPB1_PIF_SEQ_STATUS_3 0x002B +#define ixPB1_PIF_SEQ_STATUS_4 0x002C +#define ixPB1_PIF_SEQ_STATUS_5 0x002D +#define ixPB1_PIF_SEQ_STATUS_6 0x002E +#define ixPB1_PIF_SEQ_STATUS_7 0x002F +#define ixPB1_PIF_SEQ_STATUS_8 0x0038 +#define ixPB1_PIF_SEQ_STATUS_9 0x0039 +#define ixPB1_PIF_TXPHYSTATUS 0x0015 +#define ixPB1_PLL_LC0_CTRL_REG0 0x14480 +#define ixPB1_PLL_LC0_OVRD_REG0 0x14490 +#define ixPB1_PLL_LC0_OVRD_REG1 0x14494 +#define ixPB1_PLL_LC0_SCI_STAT_OVRD_REG0 0x14500 +#define ixPB1_PLL_LC1_SCI_STAT_OVRD_REG0 0x14504 +#define ixPB1_PLL_LC2_SCI_STAT_OVRD_REG0 0x14508 +#define ixPB1_PLL_LC3_SCI_STAT_OVRD_REG0 0x1450C +#define ixPB1_PLL_RO0_CTRL_REG0 0x14440 +#define ixPB1_PLL_RO0_OVRD_REG0 0x14450 +#define ixPB1_PLL_RO0_OVRD_REG1 0x14454 +#define ixPB1_PLL_RO0_SCI_STAT_OVRD_REG0 0x14460 +#define ixPB1_PLL_RO1_SCI_STAT_OVRD_REG0 0x14464 +#define ixPB1_PLL_RO2_SCI_STAT_OVRD_REG0 0x14468 +#define ixPB1_PLL_RO3_SCI_STAT_OVRD_REG0 0x1446C +#define ixPB1_PLL_RO_GLB_CTRL_REG0 0x14000 +#define ixPB1_PLL_RO_GLB_OVRD_REG0 0x14010 +#define ixPB1_RX_GLB_CTRL_REG0 0x16000 +#define ixPB1_RX_GLB_CTRL_REG1 0x16004 +#define ixPB1_RX_GLB_CTRL_REG2 0x16008 +#define ixPB1_RX_GLB_CTRL_REG3 0x1600C +#define ixPB1_RX_GLB_CTRL_REG4 0x16010 +#define ixPB1_RX_GLB_CTRL_REG5 0x16014 +#define ixPB1_RX_GLB_CTRL_REG6 0x16018 +#define ixPB1_RX_GLB_CTRL_REG7 0x1601C +#define ixPB1_RX_GLB_CTRL_REG8 0x16020 +#define ixPB1_RX_GLB_OVRD_REG0 0x16030 +#define ixPB1_RX_GLB_OVRD_REG1 0x16034 +#define ixPB1_RX_GLB_SCI_STAT_OVRD_REG0 0x16028 +#define ixPB1_RX_LANE0_CTRL_REG0 0x16440 +#define ixPB1_RX_LANE0_SCI_STAT_OVRD_REG0 0x16448 +#define ixPB1_RX_LANE10_CTRL_REG0 0x17500 +#define ixPB1_RX_LANE10_SCI_STAT_OVRD_REG0 0x17508 +#define ixPB1_RX_LANE11_CTRL_REG0 0x17600 +#define ixPB1_RX_LANE11_SCI_STAT_OVRD_REG0 0x17608 +#define ixPB1_RX_LANE12_CTRL_REG0 0x17840 +#define ixPB1_RX_LANE12_SCI_STAT_OVRD_REG0 0x17848 +#define ixPB1_RX_LANE13_CTRL_REG0 0x17880 +#define ixPB1_RX_LANE13_SCI_STAT_OVRD_REG0 0x17888 +#define ixPB1_RX_LANE14_CTRL_REG0 0x17900 +#define ixPB1_RX_LANE14_SCI_STAT_OVRD_REG0 0x17908 +#define ixPB1_RX_LANE15_CTRL_REG0 0x17A00 +#define ixPB1_RX_LANE15_SCI_STAT_OVRD_REG0 0x17A08 +#define ixPB1_RX_LANE1_CTRL_REG0 0x16480 +#define ixPB1_RX_LANE1_SCI_STAT_OVRD_REG0 0x16488 +#define ixPB1_RX_LANE2_CTRL_REG0 0x16500 +#define ixPB1_RX_LANE2_SCI_STAT_OVRD_REG0 0x16508 +#define ixPB1_RX_LANE3_CTRL_REG0 0x16600 +#define ixPB1_RX_LANE3_SCI_STAT_OVRD_REG0 0x16608 +#define ixPB1_RX_LANE4_CTRL_REG0 0x16800 +#define ixPB1_RX_LANE4_SCI_STAT_OVRD_REG0 0x16848 +#define ixPB1_RX_LANE5_CTRL_REG0 0x16880 +#define ixPB1_RX_LANE5_SCI_STAT_OVRD_REG0 0x16888 +#define ixPB1_RX_LANE6_CTRL_REG0 0x16900 +#define ixPB1_RX_LANE6_SCI_STAT_OVRD_REG0 0x16908 +#define ixPB1_RX_LANE7_CTRL_REG0 0x16A00 +#define ixPB1_RX_LANE7_SCI_STAT_OVRD_REG0 0x16A08 +#define ixPB1_RX_LANE8_CTRL_REG0 0x17440 +#define ixPB1_RX_LANE8_SCI_STAT_OVRD_REG0 0x17448 +#define ixPB1_RX_LANE9_CTRL_REG0 0x17480 +#define ixPB1_RX_LANE9_SCI_STAT_OVRD_REG0 0x17488 +#define ixPB1_STRAP_GLB_REG0 0x12020 +#define ixPB1_STRAP_PLL_REG0 0x12030 +#define ixPB1_STRAP_RX_REG0 0x12028 +#define ixPB1_STRAP_RX_REG1 0x1202C +#define ixPB1_STRAP_TX_REG0 0x12024 +#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0 0x18014 +#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1 0x18018 +#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2 0x1801C +#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3 0x18020 +#define ixPB1_TX_GLB_CTRL_REG0 0x18000 +#define ixPB1_TX_GLB_LANE_SKEW_CTRL 0x18004 +#define ixPB1_TX_GLB_OVRD_REG0 0x18030 +#define ixPB1_TX_GLB_OVRD_REG1 0x18034 +#define ixPB1_TX_GLB_OVRD_REG2 0x18038 +#define ixPB1_TX_GLB_OVRD_REG3 0x1803C +#define ixPB1_TX_GLB_OVRD_REG4 0x18040 +#define ixPB1_TX_GLB_SCI_STAT_OVRD_REG0 0x18010 +#define ixPB1_TX_LANE0_CTRL_REG0 0x18440 +#define ixPB1_TX_LANE0_OVRD_REG0 0x18444 +#define ixPB1_TX_LANE0_SCI_STAT_OVRD_REG0 0x18448 +#define ixPB1_TX_LANE10_CTRL_REG0 0x19500 +#define ixPB1_TX_LANE10_OVRD_REG0 0x19504 +#define ixPB1_TX_LANE10_SCI_STAT_OVRD_REG0 0x19508 +#define ixPB1_TX_LANE11_CTRL_REG0 0x19600 +#define ixPB1_TX_LANE11_OVRD_REG0 0x19604 +#define ixPB1_TX_LANE11_SCI_STAT_OVRD_REG0 0x19608 +#define ixPB1_TX_LANE12_CTRL_REG0 0x19840 +#define ixPB1_TX_LANE12_OVRD_REG0 0x19844 +#define ixPB1_TX_LANE12_SCI_STAT_OVRD_REG0 0x19848 +#define ixPB1_TX_LANE13_CTRL_REG0 0x19880 +#define ixPB1_TX_LANE13_OVRD_REG0 0x19884 +#define ixPB1_TX_LANE13_SCI_STAT_OVRD_REG0 0x19888 +#define ixPB1_TX_LANE14_CTRL_REG0 0x19900 +#define ixPB1_TX_LANE14_OVRD_REG0 0x19904 +#define ixPB1_TX_LANE14_SCI_STAT_OVRD_REG0 0x19908 +#define ixPB1_TX_LANE15_CTRL_REG0 0x19A00 +#define ixPB1_TX_LANE15_OVRD_REG0 0x19A04 +#define ixPB1_TX_LANE15_SCI_STAT_OVRD_REG0 0x19A08 +#define ixPB1_TX_LANE1_CTRL_REG0 0x18480 +#define ixPB1_TX_LANE1_OVRD_REG0 0x18484 +#define ixPB1_TX_LANE1_SCI_STAT_OVRD_REG0 0x18488 +#define ixPB1_TX_LANE2_CTRL_REG0 0x18500 +#define ixPB1_TX_LANE2_OVRD_REG0 0x18504 +#define ixPB1_TX_LANE2_SCI_STAT_OVRD_REG0 0x18508 +#define ixPB1_TX_LANE3_CTRL_REG0 0x18600 +#define ixPB1_TX_LANE3_OVRD_REG0 0x18604 +#define ixPB1_TX_LANE3_SCI_STAT_OVRD_REG0 0x18608 +#define ixPB1_TX_LANE4_CTRL_REG0 0x18840 +#define ixPB1_TX_LANE4_OVRD_REG0 0x18844 +#define ixPB1_TX_LANE4_SCI_STAT_OVRD_REG0 0x18848 +#define ixPB1_TX_LANE5_CTRL_REG0 0x18880 +#define ixPB1_TX_LANE5_OVRD_REG0 0x18884 +#define ixPB1_TX_LANE5_SCI_STAT_OVRD_REG0 0x18888 +#define ixPB1_TX_LANE6_CTRL_REG0 0x18900 +#define ixPB1_TX_LANE6_OVRD_REG0 0x18904 +#define ixPB1_TX_LANE6_SCI_STAT_OVRD_REG0 0x18908 +#define ixPB1_TX_LANE7_CTRL_REG0 0x18A00 +#define ixPB1_TX_LANE7_OVRD_REG0 0x18A04 +#define ixPB1_TX_LANE7_SCI_STAT_OVRD_REG0 0x18A08 +#define ixPB1_TX_LANE8_CTRL_REG0 0x19440 +#define ixPB1_TX_LANE8_OVRD_REG0 0x19444 +#define ixPB1_TX_LANE8_SCI_STAT_OVRD_REG0 0x19448 +#define ixPB1_TX_LANE9_CTRL_REG0 0x19480 +#define ixPB1_TX_LANE9_OVRD_REG0 0x19484 +#define ixPB1_TX_LANE9_SCI_STAT_OVRD_REG0 0x19488 +#define ixPCIE_BUS_CNTL 0x0021 +#define ixPCIE_CFG_CNTL 0x003C +#define ixPCIE_CI_CNTL 0x0020 +#define ixPCIE_CNTL 0x0010 +#define ixPCIE_CNTL2 0x001C +#define ixPCIE_CONFIG_CNTL 0x0011 +#define ixPCIE_DEBUG_CNTL 0x0012 +#define ixPCIE_ERR_CNTL 0x006A +#define ixPCIE_F0_DPA_CAP 0x00E0 +#define ixPCIE_F0_DPA_CNTL 0x00E5 +#define ixPCIE_F0_DPA_LATENCY_INDICATOR 0x00E4 +#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x00E7 +#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x00E8 +#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x00E9 +#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x00EA +#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x00EB +#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x00EC +#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x00ED +#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x00EE +#define ixPCIE_FC_CPL 0x0062 +#define ixPCIE_FC_NP 0x0061 +#define ixPCIE_FC_P 0x0060 +#define ixPCIE_HW_DEBUG 0x0002 +#define ixPCIE_I2C_REG_ADDR_EXPAND 0x003A +#define ixPCIE_I2C_REG_DATA 0x003B +#define ixPCIE_INT_CNTL 0x001A +#define ixPCIE_INT_STATUS 0x001B +#define ixPCIE_LC_BEST_EQ_SETTINGS 0x00B9 +#define ixPCIE_LC_BW_CHANGE_CNTL 0x00B2 +#define ixPCIE_LC_CDR_CNTL 0x00B3 +#define ixPCIE_LC_CNTL 0x00A0 +#define ixPCIE_LC_CNTL2 0x00B1 +#define ixPCIE_LC_CNTL3 0x00B5 +#define ixPCIE_LC_CNTL4 0x00B6 +#define ixPCIE_LC_CNTL5 0x00B7 +#define ixPCIE_LC_FORCE_COEFF 0x00B8 +#define ixPCIE_LC_FORCE_EQ_REQ_COEFF 0x00BA +#define ixPCIE_LC_LANE_CNTL 0x00B4 +#define ixPCIE_LC_LINK_WIDTH_CNTL 0x00A2 +#define ixPCIE_LC_N_FTS_CNTL 0x00A3 +#define ixPCIE_LC_SPEED_CNTL 0x00A4 +#define ixPCIE_LC_STATE0 0x00A5 +#define ixPCIE_LC_STATE10 0x0026 +#define ixPCIE_LC_STATE1 0x00A6 +#define ixPCIE_LC_STATE11 0x0027 +#define ixPCIE_LC_STATE2 0x00A7 +#define ixPCIE_LC_STATE3 0x00A8 +#define ixPCIE_LC_STATE4 0x00A9 +#define ixPCIE_LC_STATE5 0x00AA +#define ixPCIE_LC_STATE6 0x0022 +#define ixPCIE_LC_STATE7 0x0023 +#define ixPCIE_LC_STATE8 0x0024 +#define ixPCIE_LC_STATE9 0x0025 +#define ixPCIE_LC_STATUS1 0x0028 +#define ixPCIE_LC_STATUS2 0x0029 +#define ixPCIE_LC_TRAINING_CNTL 0x00A1 +#define ixPCIE_P_BUF_STATUS 0x0041 +#define ixPCIE_P_CNTL 0x0040 +#define ixPCIE_P_DECODER_STATUS 0x0042 +#define ixPCIE_PERF_CNTL_EVENT0_PORT_SEL 0x0093 +#define ixPCIE_PERF_CNTL_EVENT1_PORT_SEL 0x0094 +#define ixPCIE_PERF_CNTL_MST_C_CLK 0x0087 +#define ixPCIE_PERF_CNTL_MST_R_CLK 0x0084 +#define ixPCIE_PERF_CNTL_SLV_NS_C_CLK 0x0090 +#define ixPCIE_PERF_CNTL_SLV_R_CLK 0x008A +#define ixPCIE_PERF_CNTL_SLV_S_C_CLK 0x008D +#define ixPCIE_PERF_CNTL_TXCLK 0x0081 +#define ixPCIE_PERF_CNTL_TXCLK2 0x0095 +#define ixPCIE_PERF_COUNT0_MST_C_CLK 0x0088 +#define ixPCIE_PERF_COUNT0_MST_R_CLK 0x0085 +#define ixPCIE_PERF_COUNT0_SLV_NS_C_CLK 0x0091 +#define ixPCIE_PERF_COUNT0_SLV_R_CLK 0x008B +#define ixPCIE_PERF_COUNT0_SLV_S_C_CLK 0x008E +#define ixPCIE_PERF_COUNT0_TXCLK 0x0082 +#define ixPCIE_PERF_COUNT0_TXCLK2 0x0096 +#define ixPCIE_PERF_COUNT1_MST_C_CLK 0x0089 +#define ixPCIE_PERF_COUNT1_MST_R_CLK 0x0086 +#define ixPCIE_PERF_COUNT1_SLV_NS_C_CLK 0x0092 +#define ixPCIE_PERF_COUNT1_SLV_R_CLK 0x008C +#define ixPCIE_PERF_COUNT1_SLV_S_C_CLK 0x008F +#define ixPCIE_PERF_COUNT1_TXCLK 0x0083 +#define ixPCIE_PERF_COUNT1_TXCLK2 0x0097 +#define ixPCIE_PERF_COUNT_CNTL 0x0080 +#define ixPCIEP_HW_DEBUG 0x0002 +#define ixPCIE_P_MISC_STATUS 0x0043 +#define ixPCIEP_PORT_CNTL 0x0010 +#define ixPCIE_P_PORT_LANE_STATUS 0x0050 +#define ixPCIE_PRBS_CLR 0x00C8 +#define ixPCIE_PRBS_ERRCNT_0 0x00D0 +#define ixPCIE_PRBS_ERRCNT_10 0x00DA +#define ixPCIE_PRBS_ERRCNT_1 0x00D1 +#define ixPCIE_PRBS_ERRCNT_11 0x00DB +#define ixPCIE_PRBS_ERRCNT_12 0x00DC +#define ixPCIE_PRBS_ERRCNT_13 0x00DD +#define ixPCIE_PRBS_ERRCNT_14 0x00DE +#define ixPCIE_PRBS_ERRCNT_15 0x00DF +#define ixPCIE_PRBS_ERRCNT_2 0x00D2 +#define ixPCIE_PRBS_ERRCNT_3 0x00D3 +#define ixPCIE_PRBS_ERRCNT_4 0x00D4 +#define ixPCIE_PRBS_ERRCNT_5 0x00D5 +#define ixPCIE_PRBS_ERRCNT_6 0x00D6 +#define ixPCIE_PRBS_ERRCNT_7 0x00D7 +#define ixPCIE_PRBS_ERRCNT_8 0x00D8 +#define ixPCIE_PRBS_ERRCNT_9 0x00D9 +#define ixPCIE_PRBS_FREERUN 0x00CB +#define ixPCIE_PRBS_HI_BITCNT 0x00CF +#define ixPCIE_PRBS_LO_BITCNT 0x00CE +#define ixPCIE_PRBS_MISC 0x00CC +#define ixPCIE_PRBS_STATUS1 0x00C9 +#define ixPCIE_PRBS_STATUS2 0x00CA +#define ixPCIE_PRBS_USER_PATTERN 0x00CD +#define ixPCIE_P_RCV_L0S_FTS_DET 0x0050 +#define ixPCIEP_RESERVED 0x0000 +#define ixPCIEP_SCRATCH 0x0001 +#define ixPCIEP_STRAP_LC 0x00C0 +#define ixPCIEP_STRAP_MISC 0x00C1 +#define ixPCIE_RESERVED 0x0000 +#define ixPCIE_RX_CNTL 0x0070 +#define ixPCIE_RX_CNTL2 0x001D +#define ixPCIE_RX_CNTL3 0x0074 +#define ixPCIE_RX_CREDITS_ALLOCATED_CPL 0x0082 +#define ixPCIE_RX_CREDITS_ALLOCATED_NP 0x0081 +#define ixPCIE_RX_CREDITS_ALLOCATED_P 0x0080 +#define ixPCIE_RX_EXPECTED_SEQNUM 0x0071 +#define ixPCIE_RX_LAST_TLP0 0x0031 +#define ixPCIE_RX_LAST_TLP1 0x0032 +#define ixPCIE_RX_LAST_TLP2 0x0033 +#define ixPCIE_RX_LAST_TLP3 0x0034 +#define ixPCIE_RX_NUM_NAK 0x000E +#define ixPCIE_RX_NUM_NAK_GENERATED 0x000F +#define ixPCIE_RX_VENDOR_SPECIFIC 0x0072 +#define ixPCIE_SCRATCH 0x0001 +#define ixPCIE_STRAP_F0 0x00B0 +#define ixPCIE_STRAP_F1 0x00B1 +#define ixPCIE_STRAP_F2 0x00B2 +#define ixPCIE_STRAP_F3 0x00B3 +#define ixPCIE_STRAP_F4 0x00B4 +#define ixPCIE_STRAP_F5 0x00B5 +#define ixPCIE_STRAP_F6 0x00B6 +#define ixPCIE_STRAP_F7 0x00B7 +#define ixPCIE_STRAP_I2C_BD 0x00C4 +#define ixPCIE_STRAP_MISC 0x00C0 +#define ixPCIE_STRAP_MISC2 0x00C1 +#define ixPCIE_STRAP_PI 0x00C2 +#define ixPCIE_TX_ACK_LATENCY_LIMIT 0x0026 +#define ixPCIE_TX_CNTL 0x0020 +#define ixPCIE_TX_CREDITS_ADVT_CPL 0x0032 +#define ixPCIE_TX_CREDITS_ADVT_NP 0x0031 +#define ixPCIE_TX_CREDITS_ADVT_P 0x0030 +#define ixPCIE_TX_CREDITS_FCU_THRESHOLD 0x0037 +#define ixPCIE_TX_CREDITS_INIT_CPL 0x0035 +#define ixPCIE_TX_CREDITS_INIT_NP 0x0034 +#define ixPCIE_TX_CREDITS_INIT_P 0x0033 +#define ixPCIE_TX_CREDITS_STATUS 0x0036 +#define ixPCIE_TX_LAST_TLP0 0x0035 +#define ixPCIE_TX_LAST_TLP1 0x0036 +#define ixPCIE_TX_LAST_TLP2 0x0037 +#define ixPCIE_TX_LAST_TLP3 0x0038 +#define ixPCIE_TX_REPLAY 0x0025 +#define ixPCIE_TX_REQUESTER_ID 0x0021 +#define ixPCIE_TX_REQUEST_NUM_CNTL 0x0023 +#define ixPCIE_TX_SEQ 0x0024 +#define ixPCIE_TX_VENDOR_SPECIFIC 0x0022 +#define ixPCIE_WPR_CNTL 0x0030 +#define mmBACO_CNTL 0x14E5 +#define mmBF_ANA_ISO_CNTL 0x14C7 +#define mmBIF_BACO_DEBUG 0x14DF +#define mmBIF_BACO_DEBUG_LATCH 0x14DC +#define mmBIF_BACO_MSIC 0x14DE +#define mmBIF_BUSNUM_CNTL1 0x1525 +#define mmBIF_BUSNUM_CNTL2 0x152B +#define mmBIF_BUSNUM_LIST0 0x1526 +#define mmBIF_BUSNUM_LIST1 0x1527 +#define mmBIF_BUSY_DELAY_CNTR 0x1529 +#define mmBIF_CLK_PDWN_DELAY_TIMER 0x151F +#define mmBIF_DEBUG_CNTL 0x151C +#define mmBIF_DEBUG_MUX 0x151D +#define mmBIF_DEBUG_OUT 0x151E +#define mmBIF_DEVFUNCNUM_LIST0 0x14E8 +#define mmBIF_DEVFUNCNUM_LIST1 0x14E7 +#define mmBIF_FB_EN 0x1524 +#define mmBIF_FEATURES_CONTROL_MISC 0x14C2 +#define mmBIF_PERFCOUNTER0_RESULT 0x152D +#define mmBIF_PERFCOUNTER1_RESULT 0x152E +#define mmBIF_PERFMON_CNTL 0x152C +#define mmBIF_PIF_TXCLK_SWITCH_TIMER 0x152F +#define mmBIF_RESET_EN 0x1511 +#define mmBIF_SCRATCH0 0x150E +#define mmBIF_SCRATCH1 0x150F +#define mmBIF_SSA_DISP_LOWER 0x14D2 +#define mmBIF_SSA_DISP_UPPER 0x14D3 +#define mmBIF_SSA_GFX0_LOWER 0x14CA +#define mmBIF_SSA_GFX0_UPPER 0x14CB +#define mmBIF_SSA_GFX1_LOWER 0x14CC +#define mmBIF_SSA_GFX1_UPPER 0x14CD +#define mmBIF_SSA_GFX2_LOWER 0x14CE +#define mmBIF_SSA_GFX2_UPPER 0x14CF +#define mmBIF_SSA_GFX3_LOWER 0x14D0 +#define mmBIF_SSA_GFX3_UPPER 0x14D1 +#define mmBIF_SSA_MC_LOWER 0x14D4 +#define mmBIF_SSA_MC_UPPER 0x14D5 +#define mmBIF_SSA_PWR_STATUS 0x14C8 +#define mmBIF_XDMA_HI 0x14C1 +#define mmBIF_XDMA_LO 0x14C0 +#define mmBIOS_SCRATCH_0 0x05C9 +#define mmBIOS_SCRATCH_10 0x05D3 +#define mmBIOS_SCRATCH_1 0x05CA +#define mmBIOS_SCRATCH_11 0x05D4 +#define mmBIOS_SCRATCH_12 0x05D5 +#define mmBIOS_SCRATCH_13 0x05D6 +#define mmBIOS_SCRATCH_14 0x05D7 +#define mmBIOS_SCRATCH_15 0x05D8 +#define mmBIOS_SCRATCH_2 0x05CB +#define mmBIOS_SCRATCH_3 0x05CC +#define mmBIOS_SCRATCH_4 0x05CD +#define mmBIOS_SCRATCH_5 0x05CE +#define mmBIOS_SCRATCH_6 0x05CF +#define mmBIOS_SCRATCH_7 0x05D0 +#define mmBIOS_SCRATCH_8 0x05D1 +#define mmBIOS_SCRATCH_9 0x05D2 +#define mmBUS_CNTL 0x1508 +#define mmCAPTURE_HOST_BUSNUM 0x153C +#define mmCLKREQB_PAD_CNTL 0x1521 +#define mmCONFIG_APER_SIZE 0x150C +#define mmCONFIG_CNTL 0x1509 +#define mmCONFIG_F0_BASE 0x150B +#define mmCONFIG_MEMSIZE 0x150A +#define mmCONFIG_REG_APER_SIZE 0x150D +#define mmHDP_MEM_COHERENCY_FLUSH_CNTL 0x1520 +#define mmHDP_REG_COHERENCY_FLUSH_CNTL 0x1528 +#define mmHOST_BUSNUM 0x153D +#define mmHW_DEBUG 0x1515 +#define mmIMPCTL_RESET 0x14F5 +#define mmINTERRUPT_CNTL 0x151A +#define mmINTERRUPT_CNTL2 0x151B +#define mmMASTER_CREDIT_CNTL 0x1516 +#define mmMM_CFGREGS_CNTL 0x1513 +#define mmMM_DATA 0x0001 +#define mmMM_INDEX 0x0000 +#define mmMM_INDEX_HI 0x0006 +#define mmNEW_REFCLKB_TIMER 0x14EA +#define mmNEW_REFCLKB_TIMER_1 0x14E9 +#define mmPCIE_DATA 0x000D +#define mmPCIE_INDEX 0x000C +#define mmPEER0_FB_OFFSET_HI 0x14F3 +#define mmPEER0_FB_OFFSET_LO 0x14F2 +#define mmPEER1_FB_OFFSET_HI 0x14F1 +#define mmPEER1_FB_OFFSET_LO 0x14F0 +#define mmPEER2_FB_OFFSET_HI 0x14EF +#define mmPEER2_FB_OFFSET_LO 0x14EE +#define mmPEER3_FB_OFFSET_HI 0x14ED +#define mmPEER3_FB_OFFSET_LO 0x14EC +#define mmPEER_REG_RANGE0 0x153E +#define mmPEER_REG_RANGE1 0x153F +#define mmSLAVE_HANG_ERROR 0x153B +#define mmSLAVE_HANG_PROTECTION_CNTL 0x1536 +#define mmSLAVE_REQ_CREDIT_CNTL 0x1517 +#define mmSMBCLK_PAD_CNTL 0x1523 +#define mmSMBDAT_PAD_CNTL 0x1522 +#define mmSMBUS_BACO_DUMMY 0x14C6 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_sh_mask.h new file mode 100644 index 000000000000..e94445acf3c6 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_sh_mask.h @@ -0,0 +1,8127 @@ +/* + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef BIF_3_0_SH_MASK_H +#define BIF_3_0_SH_MASK_H + +#define BACO_CNTL__BACO_ANA_ISO_DIS_MASK 0x00000080L +#define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT 0x00000007 +#define BACO_CNTL__BACO_BCLK_OFF_MASK 0x00000002L +#define BACO_CNTL__BACO_BCLK_OFF__SHIFT 0x00000001 +#define BACO_CNTL__BACO_EN_MASK 0x00000001L +#define BACO_CNTL__BACO_EN__SHIFT 0x00000000 +#define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK 0x00000020L +#define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT 0x00000005 +#define BACO_CNTL__BACO_ISO_DIS_MASK 0x00000004L +#define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x00000002 +#define BACO_CNTL__BACO_MODE_MASK 0x00000040L +#define BACO_CNTL__BACO_MODE__SHIFT 0x00000006 +#define BACO_CNTL__BACO_POWER_OFF_MASK 0x00000008L +#define BACO_CNTL__BACO_POWER_OFF__SHIFT 0x00000003 +#define BACO_CNTL__BACO_RESET_EN_MASK 0x00000010L +#define BACO_CNTL__BACO_RESET_EN__SHIFT 0x00000004 +#define BACO_CNTL__PWRGOOD_BF_MASK 0x00000200L +#define BACO_CNTL__PWRGOOD_BF__SHIFT 0x00000009 +#define BACO_CNTL__PWRGOOD_DVO_MASK 0x00001000L +#define BACO_CNTL__PWRGOOD_DVO__SHIFT 0x0000000c +#define BACO_CNTL__PWRGOOD_GPIO_MASK 0x00000400L +#define BACO_CNTL__PWRGOOD_GPIO__SHIFT 0x0000000a +#define BACO_CNTL__PWRGOOD_MEM_MASK 0x00000800L +#define BACO_CNTL__PWRGOOD_MEM__SHIFT 0x0000000b +#define BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x00000100L +#define BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x00000008 +#define BF_ANA_ISO_CNTL__BF_ANA_ISO_DIS_MASK_MASK 0x00000001L +#define BF_ANA_ISO_CNTL__BF_ANA_ISO_DIS_MASK__SHIFT 0x00000000 +#define BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK_MASK 0x00000002L +#define BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK__SHIFT 0x00000001 +#define BIF_BACO_DEBUG__BIF_BACO_SCANDUMP_FLG_MASK 0x00000001L +#define BIF_BACO_DEBUG__BIF_BACO_SCANDUMP_FLG__SHIFT 0x00000000 +#define BIF_BACO_DEBUG_LATCH__BIF_BACO_LATCH_FLG_MASK 0x00000001L +#define BIF_BACO_DEBUG_LATCH__BIF_BACO_LATCH_FLG__SHIFT 0x00000000 +#define BIF_BACO_MSIC__BIF_XTALIN_SEL_MASK 0x00000001L +#define BIF_BACO_MSIC__BIF_XTALIN_SEL__SHIFT 0x00000000 +#define BIF_BUSNUM_CNTL1__ID_MASK_MASK 0x000000ffL +#define BIF_BUSNUM_CNTL1__ID_MASK__SHIFT 0x00000000 +#define BIF_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK 0x00000100L +#define BIF_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x00000008 +#define BIF_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK 0x000000ffL +#define BIF_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x00000000 +#define BIF_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK 0x00020000L +#define BIF_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x00000011 +#define BIF_BUSNUM_CNTL2__HDPREG_CNTL_MASK 0x00010000L +#define BIF_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x00000010 +#define BIF_BUSNUM_LIST0__ID0_MASK 0x000000ffL +#define BIF_BUSNUM_LIST0__ID0__SHIFT 0x00000000 +#define BIF_BUSNUM_LIST0__ID1_MASK 0x0000ff00L +#define BIF_BUSNUM_LIST0__ID1__SHIFT 0x00000008 +#define BIF_BUSNUM_LIST0__ID2_MASK 0x00ff0000L +#define BIF_BUSNUM_LIST0__ID2__SHIFT 0x00000010 +#define BIF_BUSNUM_LIST0__ID3_MASK 0xff000000L +#define BIF_BUSNUM_LIST0__ID3__SHIFT 0x00000018 +#define BIF_BUSNUM_LIST1__ID4_MASK 0x000000ffL +#define BIF_BUSNUM_LIST1__ID4__SHIFT 0x00000000 +#define BIF_BUSNUM_LIST1__ID5_MASK 0x0000ff00L +#define BIF_BUSNUM_LIST1__ID5__SHIFT 0x00000008 +#define BIF_BUSNUM_LIST1__ID6_MASK 0x00ff0000L +#define BIF_BUSNUM_LIST1__ID6__SHIFT 0x00000010 +#define BIF_BUSNUM_LIST1__ID7_MASK 0xff000000L +#define BIF_BUSNUM_LIST1__ID7__SHIFT 0x00000018 +#define BIF_BUSY_DELAY_CNTR__DELAY_CNT_MASK 0x0000003fL +#define BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT 0x00000000 +#define BIF_CLK_PDWN_DELAY_TIMER__TIMER_MASK 0x000003ffL +#define BIF_CLK_PDWN_DELAY_TIMER__TIMER__SHIFT 0x00000000 +#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1_MASK 0x00000010L +#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1__SHIFT 0x00000004 +#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK2_MASK 0x00000020L +#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK2__SHIFT 0x00000005 +#define BIF_DEBUG_CNTL__DEBUG_EN_MASK 0x00000001L +#define BIF_DEBUG_CNTL__DEBUG_EN__SHIFT 0x00000000 +#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1_MASK 0x00001f00L +#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1__SHIFT 0x00000008 +#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK2_MASK 0x001f0000L +#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK2__SHIFT 0x00000010 +#define BIF_DEBUG_CNTL__DEBUG_IDSEL_XSP_MASK 0x01000000L +#define BIF_DEBUG_CNTL__DEBUG_IDSEL_XSP__SHIFT 0x00000018 +#define BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN_MASK 0x00000002L +#define BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN__SHIFT 0x00000001 +#define BIF_DEBUG_CNTL__DEBUG_OUT_EN_MASK 0x00000004L +#define BIF_DEBUG_CNTL__DEBUG_OUT_EN__SHIFT 0x00000002 +#define BIF_DEBUG_CNTL__DEBUG_PAD_SEL_MASK 0x00000008L +#define BIF_DEBUG_CNTL__DEBUG_PAD_SEL__SHIFT 0x00000003 +#define BIF_DEBUG_CNTL__DEBUG_SWAP_MASK 0x00000080L +#define BIF_DEBUG_CNTL__DEBUG_SWAP__SHIFT 0x00000007 +#define BIF_DEBUG_CNTL__DEBUG_SYNC_CLKSEL_MASK 0xc0000000L +#define BIF_DEBUG_CNTL__DEBUG_SYNC_CLKSEL__SHIFT 0x0000001e +#define BIF_DEBUG_CNTL__DEBUG_SYNC_EN_MASK 0x00000040L +#define BIF_DEBUG_CNTL__DEBUG_SYNC_EN__SHIFT 0x00000006 +#define BIF_DEBUG_MUX__DEBUG_MUX_BLK1_MASK 0x0000003fL +#define BIF_DEBUG_MUX__DEBUG_MUX_BLK1__SHIFT 0x00000000 +#define BIF_DEBUG_MUX__DEBUG_MUX_BLK2_MASK 0x00003f00L +#define BIF_DEBUG_MUX__DEBUG_MUX_BLK2__SHIFT 0x00000008 +#define BIF_DEBUG_OUT__DEBUG_OUTPUT_MASK 0x0001ffffL +#define BIF_DEBUG_OUT__DEBUG_OUTPUT__SHIFT 0x00000000 +#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK 0x000000ffL +#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT 0x00000000 +#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK 0x0000ff00L +#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT 0x00000008 +#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK 0x00ff0000L +#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT 0x00000010 +#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK 0xff000000L +#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT 0x00000018 +#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK 0x000000ffL +#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT 0x00000000 +#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK 0x0000ff00L +#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT 0x00000008 +#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK 0x00ff0000L +#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT 0x00000010 +#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK 0xff000000L +#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT 0x00000018 +#define BIF_FB_EN__FB_READ_EN_MASK 0x00000001L +#define BIF_FB_EN__FB_READ_EN__SHIFT 0x00000000 +#define BIF_FB_EN__FB_WRITE_EN_MASK 0x00000002L +#define BIF_FB_EN__FB_WRITE_EN__SHIFT 0x00000001 +#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x00000008L +#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x00000003 +#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x00000004L +#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x00000002 +#define BIF_FEATURES_CONTROL_MISC__IGNORE_BE_CHECK_GASKET_COMB_DIS_MASK 0x00000100L +#define BIF_FEATURES_CONTROL_MISC__IGNORE_BE_CHECK_GASKET_COMB_DIS__SHIFT 0x00000008 +#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x00000001L +#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x00000000 +#define BIF_FEATURES_CONTROL_MISC__PLL_SWITCH_IMPCTL_CAL_DONE_DIS_MASK 0x00000080L +#define BIF_FEATURES_CONTROL_MISC__PLL_SWITCH_IMPCTL_CAL_DONE_DIS__SHIFT 0x00000007 +#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS_MASK 0x00000020L +#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT 0x00000005 +#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS_MASK 0x00000040L +#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT 0x00000006 +#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x00000002L +#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x00000001 +#define BIF_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS_MASK 0x00000010L +#define BIF_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT 0x00000004 +#define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT_MASK 0xffffffffL +#define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT__SHIFT 0x00000000 +#define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT_MASK 0xffffffffL +#define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT__SHIFT 0x00000000 +#define BIF_PERFMON_CNTL__PERFCOUNTER_EN_MASK 0x00000001L +#define BIF_PERFMON_CNTL__PERFCOUNTER_EN__SHIFT 0x00000000 +#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0_MASK 0x00000002L +#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0__SHIFT 0x00000001 +#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1_MASK 0x00000004L +#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1__SHIFT 0x00000002 +#define BIF_PERFMON_CNTL__PERF_SEL0_MASK 0x00001f00L +#define BIF_PERFMON_CNTL__PERF_SEL0__SHIFT 0x00000008 +#define BIF_PERFMON_CNTL__PERF_SEL1_MASK 0x0003e000L +#define BIF_PERFMON_CNTL__PERF_SEL1__SHIFT 0x0000000d +#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL0_ACK_TIMER_MASK 0x00000007L +#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL0_ACK_TIMER__SHIFT 0x00000000 +#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL1_ACK_TIMER_MASK 0x00000038L +#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL1_ACK_TIMER__SHIFT 0x00000003 +#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL_SWITCH_TIMER_MASK 0x000003c0L +#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL_SWITCH_TIMER__SHIFT 0x00000006 +#define BIF_RESET_EN__BIF_COR_RESET_EN_MASK 0x00400000L +#define BIF_RESET_EN__BIF_COR_RESET_EN__SHIFT 0x00000016 +#define BIF_RESET_EN__CFG_RESET_EN_MASK 0x00000040L +#define BIF_RESET_EN__CFG_RESET_EN__SHIFT 0x00000006 +#define BIF_RESET_EN__CFG_RESET_PULSE_WIDTH_MASK 0x0003f000L +#define BIF_RESET_EN__CFG_RESET_PULSE_WIDTH__SHIFT 0x0000000c +#define BIF_RESET_EN__COR_RESET_EN_MASK 0x00000008L +#define BIF_RESET_EN__COR_RESET_EN__SHIFT 0x00000003 +#define BIF_RESET_EN__DRV_RESET_DELAY_SEL_MASK 0x000c0000L +#define BIF_RESET_EN__DRV_RESET_DELAY_SEL__SHIFT 0x00000012 +#define BIF_RESET_EN__DRV_RESET_EN_MASK 0x00000080L +#define BIF_RESET_EN__DRV_RESET_EN__SHIFT 0x00000007 +#define BIF_RESET_EN__FUNC0_FLR_EN_MASK 0x00800000L +#define BIF_RESET_EN__FUNC0_FLR_EN__SHIFT 0x00000017 +#define BIF_RESET_EN__FUNC0_RESET_DELAY_SEL_MASK 0x0c000000L +#define BIF_RESET_EN__FUNC0_RESET_DELAY_SEL__SHIFT 0x0000001a +#define BIF_RESET_EN__FUNC1_FLR_EN_MASK 0x01000000L +#define BIF_RESET_EN__FUNC1_FLR_EN__SHIFT 0x00000018 +#define BIF_RESET_EN__FUNC1_RESET_DELAY_SEL_MASK 0x30000000L +#define BIF_RESET_EN__FUNC1_RESET_DELAY_SEL__SHIFT 0x0000001c +#define BIF_RESET_EN__FUNC2_FLR_EN_MASK 0x02000000L +#define BIF_RESET_EN__FUNC2_FLR_EN__SHIFT 0x00000019 +#define BIF_RESET_EN__FUNC2_RESET_DELAY_SEL_MASK 0xc0000000L +#define BIF_RESET_EN__FUNC2_RESET_DELAY_SEL__SHIFT 0x0000001e +#define BIF_RESET_EN__HOT_RESET_EN_MASK 0x00000200L +#define BIF_RESET_EN__HOT_RESET_EN__SHIFT 0x00000009 +#define BIF_RESET_EN__LINK_DISABLE_RESET_EN_MASK 0x00000400L +#define BIF_RESET_EN__LINK_DISABLE_RESET_EN__SHIFT 0x0000000a +#define BIF_RESET_EN__LINK_DOWN_RESET_EN_MASK 0x00000800L +#define BIF_RESET_EN__LINK_DOWN_RESET_EN__SHIFT 0x0000000b +#define BIF_RESET_EN__PHY_RESET_EN_MASK 0x00000004L +#define BIF_RESET_EN__PHY_RESET_EN__SHIFT 0x00000002 +#define BIF_RESET_EN__PIF_RSTB_EN_MASK 0x00100000L +#define BIF_RESET_EN__PIF_RSTB_EN__SHIFT 0x00000014 +#define BIF_RESET_EN__PIF_STRAP_ALLVALID_EN_MASK 0x00200000L +#define BIF_RESET_EN__PIF_STRAP_ALLVALID_EN__SHIFT 0x00000015 +#define BIF_RESET_EN__REG_RESET_EN_MASK 0x00000010L +#define BIF_RESET_EN__REG_RESET_EN__SHIFT 0x00000004 +#define BIF_RESET_EN__RESET_CFGREG_ONLY_EN_MASK 0x00000100L +#define BIF_RESET_EN__RESET_CFGREG_ONLY_EN__SHIFT 0x00000008 +#define BIF_RESET_EN__SOFT_RST_MODE_MASK 0x00000002L +#define BIF_RESET_EN__SOFT_RST_MODE__SHIFT 0x00000001 +#define BIF_RESET_EN__STY_RESET_EN_MASK 0x00000020L +#define BIF_RESET_EN__STY_RESET_EN__SHIFT 0x00000005 +#define BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xffffffffL +#define BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x00000000 +#define BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xffffffffL +#define BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x00000000 +#define BIF_SSA_DISP_LOWER__SSA_DISP_LOWER_MASK 0x0003fffcL +#define BIF_SSA_DISP_LOWER__SSA_DISP_LOWER__SHIFT 0x00000002 +#define BIF_SSA_DISP_LOWER__SSA_DISP_REG_CMP_EN_MASK 0x40000000L +#define BIF_SSA_DISP_LOWER__SSA_DISP_REG_CMP_EN__SHIFT 0x0000001e +#define BIF_SSA_DISP_LOWER__SSA_DISP_REG_STALL_EN_MASK 0x80000000L +#define BIF_SSA_DISP_LOWER__SSA_DISP_REG_STALL_EN__SHIFT 0x0000001f +#define BIF_SSA_DISP_UPPER__SSA_DISP_UPPER_MASK 0x0003fffcL +#define BIF_SSA_DISP_UPPER__SSA_DISP_UPPER__SHIFT 0x00000002 +#define BIF_SSA_GFX0_LOWER__SSA_GFX0_LOWER_MASK 0x0003fffcL +#define BIF_SSA_GFX0_LOWER__SSA_GFX0_LOWER__SHIFT 0x00000002 +#define BIF_SSA_GFX0_LOWER__SSA_GFX0_REG_CMP_EN_MASK 0x40000000L +#define BIF_SSA_GFX0_LOWER__SSA_GFX0_REG_CMP_EN__SHIFT 0x0000001e +#define BIF_SSA_GFX0_LOWER__SSA_GFX0_REG_STALL_EN_MASK 0x80000000L +#define BIF_SSA_GFX0_LOWER__SSA_GFX0_REG_STALL_EN__SHIFT 0x0000001f +#define BIF_SSA_GFX0_UPPER__SSA_GFX0_UPPER_MASK 0x0003fffcL +#define BIF_SSA_GFX0_UPPER__SSA_GFX0_UPPER__SHIFT 0x00000002 +#define BIF_SSA_GFX1_LOWER__SSA_GFX1_LOWER_MASK 0x0003fffcL +#define BIF_SSA_GFX1_LOWER__SSA_GFX1_LOWER__SHIFT 0x00000002 +#define BIF_SSA_GFX1_LOWER__SSA_GFX1_REG_CMP_EN_MASK 0x40000000L +#define BIF_SSA_GFX1_LOWER__SSA_GFX1_REG_CMP_EN__SHIFT 0x0000001e +#define BIF_SSA_GFX1_LOWER__SSA_GFX1_REG_STALL_EN_MASK 0x80000000L +#define BIF_SSA_GFX1_LOWER__SSA_GFX1_REG_STALL_EN__SHIFT 0x0000001f +#define BIF_SSA_GFX1_UPPER__SSA_GFX1_UPPER_MASK 0x0003fffcL +#define BIF_SSA_GFX1_UPPER__SSA_GFX1_UPPER__SHIFT 0x00000002 +#define BIF_SSA_GFX2_LOWER__SSA_GFX2_LOWER_MASK 0x0003fffcL +#define BIF_SSA_GFX2_LOWER__SSA_GFX2_LOWER__SHIFT 0x00000002 +#define BIF_SSA_GFX2_LOWER__SSA_GFX2_REG_CMP_EN_MASK 0x40000000L +#define BIF_SSA_GFX2_LOWER__SSA_GFX2_REG_CMP_EN__SHIFT 0x0000001e +#define BIF_SSA_GFX2_LOWER__SSA_GFX2_REG_STALL_EN_MASK 0x80000000L +#define BIF_SSA_GFX2_LOWER__SSA_GFX2_REG_STALL_EN__SHIFT 0x0000001f +#define BIF_SSA_GFX2_UPPER__SSA_GFX2_UPPER_MASK 0x0003fffcL +#define BIF_SSA_GFX2_UPPER__SSA_GFX2_UPPER__SHIFT 0x00000002 +#define BIF_SSA_GFX3_LOWER__SSA_GFX3_LOWER_MASK 0x0003fffcL +#define BIF_SSA_GFX3_LOWER__SSA_GFX3_LOWER__SHIFT 0x00000002 +#define BIF_SSA_GFX3_LOWER__SSA_GFX3_REG_CMP_EN_MASK 0x40000000L +#define BIF_SSA_GFX3_LOWER__SSA_GFX3_REG_CMP_EN__SHIFT 0x0000001e +#define BIF_SSA_GFX3_LOWER__SSA_GFX3_REG_STALL_EN_MASK 0x80000000L +#define BIF_SSA_GFX3_LOWER__SSA_GFX3_REG_STALL_EN__SHIFT 0x0000001f +#define BIF_SSA_GFX3_UPPER__SSA_GFX3_UPPER_MASK 0x0003fffcL +#define BIF_SSA_GFX3_UPPER__SSA_GFX3_UPPER__SHIFT 0x00000002 +#define BIF_SSA_MC_LOWER__SSA_MC_FB_STALL_EN_MASK 0x20000000L +#define BIF_SSA_MC_LOWER__SSA_MC_FB_STALL_EN__SHIFT 0x0000001d +#define BIF_SSA_MC_LOWER__SSA_MC_LOWER_MASK 0x0003fffcL +#define BIF_SSA_MC_LOWER__SSA_MC_LOWER__SHIFT 0x00000002 +#define BIF_SSA_MC_LOWER__SSA_MC_REG_CMP_EN_MASK 0x40000000L +#define BIF_SSA_MC_LOWER__SSA_MC_REG_CMP_EN__SHIFT 0x0000001e +#define BIF_SSA_MC_LOWER__SSA_MC_REG_STALL_EN_MASK 0x80000000L +#define BIF_SSA_MC_LOWER__SSA_MC_REG_STALL_EN__SHIFT 0x0000001f +#define BIF_SSA_MC_UPPER__SSA_MC_UPPER_MASK 0x0003fffcL +#define BIF_SSA_MC_UPPER__SSA_MC_UPPER__SHIFT 0x00000002 +#define BIF_SSA_PWR_STATUS__SSA_DISP_PWR_STATUS_MASK 0x00000002L +#define BIF_SSA_PWR_STATUS__SSA_DISP_PWR_STATUS__SHIFT 0x00000001 +#define BIF_SSA_PWR_STATUS__SSA_GFX_PWR_STATUS_MASK 0x00000001L +#define BIF_SSA_PWR_STATUS__SSA_GFX_PWR_STATUS__SHIFT 0x00000000 +#define BIF_SSA_PWR_STATUS__SSA_MC_PWR_STATUS_MASK 0x00000004L +#define BIF_SSA_PWR_STATUS__SSA_MC_PWR_STATUS__SHIFT 0x00000002 +#define BIF_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK 0x1fffffffL +#define BIF_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x00000000 +#define BIF_XDMA_LO__BIF_XDMA_APER_EN_MASK 0x80000000L +#define BIF_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x0000001f +#define BIF_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK 0x1fffffffL +#define BIF_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x00000000 +#define BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xffffffffL +#define BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x00000000 +#define BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xffffffffL +#define BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x00000000 +#define BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xffffffffL +#define BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x00000000 +#define BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xffffffffL +#define BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x00000000 +#define BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xffffffffL +#define BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x00000000 +#define BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xffffffffL +#define BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x00000000 +#define BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xffffffffL +#define BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x00000000 +#define BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xffffffffL +#define BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x00000000 +#define BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xffffffffL +#define BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x00000000 +#define BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xffffffffL +#define BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x00000000 +#define BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xffffffffL +#define BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x00000000 +#define BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xffffffffL +#define BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x00000000 +#define BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xffffffffL +#define BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x00000000 +#define BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xffffffffL +#define BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x00000000 +#define BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xffffffffL +#define BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x00000000 +#define BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xffffffffL +#define BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x00000000 +#define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN_MASK 0x00000100L +#define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN__SHIFT 0x00000008 +#define BUS_CNTL__BIOS_ROM_DIS_MASK 0x00000002L +#define BUS_CNTL__BIOS_ROM_DIS__SHIFT 0x00000001 +#define BUS_CNTL__BIOS_ROM_WRT_EN_MASK 0x00000001L +#define BUS_CNTL__BIOS_ROM_WRT_EN__SHIFT 0x00000000 +#define BUS_CNTL__PMI_BM_DIS_MASK 0x00000010L +#define BUS_CNTL__PMI_BM_DIS__SHIFT 0x00000004 +#define BUS_CNTL__PMI_INT_DIS_MASK 0x00000020L +#define BUS_CNTL__PMI_INT_DIS__SHIFT 0x00000005 +#define BUS_CNTL__PMI_IO_DIS_MASK 0x00000004L +#define BUS_CNTL__PMI_IO_DIS__SHIFT 0x00000002 +#define BUS_CNTL__PMI_MEM_DIS_MASK 0x00000008L +#define BUS_CNTL__PMI_MEM_DIS__SHIFT 0x00000003 +#define BUS_CNTL__RD_STALL_IO_WR_MASK 0x00040000L +#define BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x00000012 +#define BUS_CNTL__SET_AZ_TC_MASK 0x00001c00L +#define BUS_CNTL__SET_AZ_TC__SHIFT 0x0000000a +#define BUS_CNTL__SET_MC_TC_MASK 0x0000e000L +#define BUS_CNTL__SET_MC_TC__SHIFT 0x0000000d +#define BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x00000080L +#define BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x00000007 +#define BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x00000040L +#define BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x00000006 +#define BUS_CNTL__ZERO_BE_RD_EN_MASK 0x00020000L +#define BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x00000011 +#define BUS_CNTL__ZERO_BE_WR_EN_MASK 0x00010000L +#define BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x00000010 +#define CAPTURE_HOST_BUSNUM__CHECK_EN_MASK 0x00000001L +#define CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x00000000 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x00000001L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x00000000 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x00001000L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0x0000000c +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x00000004L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x00000002 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x00000800L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0x0000000b +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x00000002L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x00000001 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x00000200L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x00000009 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x00000020L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x00000005 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x00000040L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x00000006 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x00000080L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x00000007 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x00000100L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x00000008 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x00000018L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x00000003 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x00000400L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0x0000000a +#define CONFIG_APER_SIZE__APER_SIZE_MASK 0xffffffffL +#define CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x00000000 +#define CONFIG_CNTL__CFG_VGA_RAM_EN_MASK 0x00000001L +#define CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x00000000 +#define CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x00000004L +#define CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x00000002 +#define CONFIG_CNTL__GRPH_ADRSEL_MASK 0x00000018L +#define CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x00000003 +#define CONFIG_CNTL__VGA_DIS_MASK 0x00000002L +#define CONFIG_CNTL__VGA_DIS__SHIFT 0x00000001 +#define CONFIG_F0_BASE__F0_BASE_MASK 0xffffffffL +#define CONFIG_F0_BASE__F0_BASE__SHIFT 0x00000000 +#define CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xffffffffL +#define CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x00000000 +#define CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK 0x000fffffL +#define CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x00000000 +#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x00000000 +#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x00000000 +#define HOST_BUSNUM__HOST_ID_MASK 0x0000ffffL +#define HOST_BUSNUM__HOST_ID__SHIFT 0x00000000 +#define HW_DEBUG__HW_00_DEBUG_MASK 0x00000001L +#define HW_DEBUG__HW_00_DEBUG__SHIFT 0x00000000 +#define HW_DEBUG__HW_01_DEBUG_MASK 0x00000002L +#define HW_DEBUG__HW_01_DEBUG__SHIFT 0x00000001 +#define HW_DEBUG__HW_02_DEBUG_MASK 0x00000004L +#define HW_DEBUG__HW_02_DEBUG__SHIFT 0x00000002 +#define HW_DEBUG__HW_03_DEBUG_MASK 0x00000008L +#define HW_DEBUG__HW_03_DEBUG__SHIFT 0x00000003 +#define HW_DEBUG__HW_04_DEBUG_MASK 0x00000010L +#define HW_DEBUG__HW_04_DEBUG__SHIFT 0x00000004 +#define HW_DEBUG__HW_05_DEBUG_MASK 0x00000020L +#define HW_DEBUG__HW_05_DEBUG__SHIFT 0x00000005 +#define HW_DEBUG__HW_06_DEBUG_MASK 0x00000040L +#define HW_DEBUG__HW_06_DEBUG__SHIFT 0x00000006 +#define HW_DEBUG__HW_07_DEBUG_MASK 0x00000080L +#define HW_DEBUG__HW_07_DEBUG__SHIFT 0x00000007 +#define HW_DEBUG__HW_08_DEBUG_MASK 0x00000100L +#define HW_DEBUG__HW_08_DEBUG__SHIFT 0x00000008 +#define HW_DEBUG__HW_09_DEBUG_MASK 0x00000200L +#define HW_DEBUG__HW_09_DEBUG__SHIFT 0x00000009 +#define HW_DEBUG__HW_10_DEBUG_MASK 0x00000400L +#define HW_DEBUG__HW_10_DEBUG__SHIFT 0x0000000a +#define HW_DEBUG__HW_11_DEBUG_MASK 0x00000800L +#define HW_DEBUG__HW_11_DEBUG__SHIFT 0x0000000b +#define HW_DEBUG__HW_12_DEBUG_MASK 0x00001000L +#define HW_DEBUG__HW_12_DEBUG__SHIFT 0x0000000c +#define HW_DEBUG__HW_13_DEBUG_MASK 0x00002000L +#define HW_DEBUG__HW_13_DEBUG__SHIFT 0x0000000d +#define HW_DEBUG__HW_14_DEBUG_MASK 0x00004000L +#define HW_DEBUG__HW_14_DEBUG__SHIFT 0x0000000e +#define HW_DEBUG__HW_15_DEBUG_MASK 0x00008000L +#define HW_DEBUG__HW_15_DEBUG__SHIFT 0x0000000f +#define HW_DEBUG__HW_16_DEBUG_MASK 0x00010000L +#define HW_DEBUG__HW_16_DEBUG__SHIFT 0x00000010 +#define HW_DEBUG__HW_17_DEBUG_MASK 0x00020000L +#define HW_DEBUG__HW_17_DEBUG__SHIFT 0x00000011 +#define HW_DEBUG__HW_18_DEBUG_MASK 0x00040000L +#define HW_DEBUG__HW_18_DEBUG__SHIFT 0x00000012 +#define HW_DEBUG__HW_19_DEBUG_MASK 0x00080000L +#define HW_DEBUG__HW_19_DEBUG__SHIFT 0x00000013 +#define HW_DEBUG__HW_20_DEBUG_MASK 0x00100000L +#define HW_DEBUG__HW_20_DEBUG__SHIFT 0x00000014 +#define HW_DEBUG__HW_21_DEBUG_MASK 0x00200000L +#define HW_DEBUG__HW_21_DEBUG__SHIFT 0x00000015 +#define HW_DEBUG__HW_22_DEBUG_MASK 0x00400000L +#define HW_DEBUG__HW_22_DEBUG__SHIFT 0x00000016 +#define HW_DEBUG__HW_23_DEBUG_MASK 0x00800000L +#define HW_DEBUG__HW_23_DEBUG__SHIFT 0x00000017 +#define HW_DEBUG__HW_24_DEBUG_MASK 0x01000000L +#define HW_DEBUG__HW_24_DEBUG__SHIFT 0x00000018 +#define HW_DEBUG__HW_25_DEBUG_MASK 0x02000000L +#define HW_DEBUG__HW_25_DEBUG__SHIFT 0x00000019 +#define HW_DEBUG__HW_26_DEBUG_MASK 0x04000000L +#define HW_DEBUG__HW_26_DEBUG__SHIFT 0x0000001a +#define HW_DEBUG__HW_27_DEBUG_MASK 0x08000000L +#define HW_DEBUG__HW_27_DEBUG__SHIFT 0x0000001b +#define HW_DEBUG__HW_28_DEBUG_MASK 0x10000000L +#define HW_DEBUG__HW_28_DEBUG__SHIFT 0x0000001c +#define HW_DEBUG__HW_29_DEBUG_MASK 0x20000000L +#define HW_DEBUG__HW_29_DEBUG__SHIFT 0x0000001d +#define HW_DEBUG__HW_30_DEBUG_MASK 0x40000000L +#define HW_DEBUG__HW_30_DEBUG__SHIFT 0x0000001e +#define HW_DEBUG__HW_31_DEBUG_MASK 0x80000000L +#define HW_DEBUG__HW_31_DEBUG__SHIFT 0x0000001f +#define IMPCTL_RESET__IMP_SW_RESET_MASK 0x00000001L +#define IMPCTL_RESET__IMP_SW_RESET__SHIFT 0x00000000 +#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xffffffffL +#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x00000000 +#define INTERRUPT_CNTL__GEN_GPIO_INT_EN_MASK 0x00001e00L +#define INTERRUPT_CNTL__GEN_GPIO_INT_EN__SHIFT 0x00000009 +#define INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x00000100L +#define INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x00000008 +#define INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x00000002L +#define INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x00000001 +#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x00000001L +#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x00000000 +#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0x000000f0L +#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x00000004 +#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x00000008L +#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x00000003 +#define INTERRUPT_CNTL__SELECT_INT_GPIO_OUTPUT_MASK 0x00006000L +#define INTERRUPT_CNTL__SELECT_INT_GPIO_OUTPUT__SHIFT 0x0000000d +#define MASTER_CREDIT_CNTL__BIF_AZ_RDRET_CREDIT_MASK 0x003f0000L +#define MASTER_CREDIT_CNTL__BIF_AZ_RDRET_CREDIT__SHIFT 0x00000010 +#define MASTER_CREDIT_CNTL__BIF_MC_RDRET_CREDIT_MASK 0x0000003fL +#define MASTER_CREDIT_CNTL__BIF_MC_RDRET_CREDIT__SHIFT 0x00000000 +#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x00000007L +#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x00000000 +#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x00000008L +#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x00000003 +#define MM_DATA__MM_DATA_MASK 0xffffffffL +#define MM_DATA__MM_DATA__SHIFT 0x00000000 +#define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffffL +#define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x00000000 +#define MM_INDEX__MM_APER_MASK 0x80000000L +#define MM_INDEX__MM_APER__SHIFT 0x0000001f +#define MM_INDEX__MM_OFFSET_MASK 0x7fffffffL +#define MM_INDEX__MM_OFFSET__SHIFT 0x00000000 +#define NEW_REFCLKB_TIMER_1__PHY_PLL_PDWN_TIMER_MASK 0x000003ffL +#define NEW_REFCLKB_TIMER_1__PHY_PLL_PDWN_TIMER__SHIFT 0x00000000 +#define NEW_REFCLKB_TIMER_1__PLL0_PDNB_EN_MASK 0x00000400L +#define NEW_REFCLKB_TIMER_1__PLL0_PDNB_EN__SHIFT 0x0000000a +#define NEW_REFCLKB_TIMER__REFCLK_ON_MASK 0x00200000L +#define NEW_REFCLKB_TIMER__REFCLK_ON__SHIFT 0x00000015 +#define NEW_REFCLKB_TIMER__REG_STOP_REFCLK_EN_MASK 0x00000001L +#define NEW_REFCLKB_TIMER__REG_STOP_REFCLK_EN__SHIFT 0x00000000 +#define NEW_REFCLKB_TIMER__STOP_REFCLK_TIMER_MASK 0x001ffffeL +#define NEW_REFCLKB_TIMER__STOP_REFCLK_TIMER__SHIFT 0x00000001 +#define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN_MASK 0x00000001L +#define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN__SHIFT 0x00000000 +#define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE_MASK 0x0000003eL +#define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE__SHIFT 0x00000001 +#define PB0_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP_MASK 0x00000f00L +#define PB0_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP__SHIFT 0x00000008 +#define PB0_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN_MASK 0x00800000L +#define PB0_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN__SHIFT 0x00000017 +#define PB0_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN_MASK 0x00400000L +#define PB0_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN__SHIFT 0x00000016 +#define PB0_DFT_JIT_INJ_REG0__DFT_NUM_STEPS_MASK 0x0000001fL +#define PB0_DFT_JIT_INJ_REG0__DFT_NUM_STEPS__SHIFT 0x00000000 +#define PB0_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME_MASK 0xff000000L +#define PB0_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME__SHIFT 0x00000018 +#define PB0_DFT_JIT_INJ_REG1__DFT_BLOCK_EN_MASK 0x00010000L +#define PB0_DFT_JIT_INJ_REG1__DFT_BLOCK_EN__SHIFT 0x00000010 +#define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_EN_MASK 0x00000100L +#define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_EN__SHIFT 0x00000008 +#define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE_MASK 0x000000ffL +#define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE__SHIFT 0x00000000 +#define PB0_DFT_JIT_INJ_REG2__DFT_LANE_EN_MASK 0x0000ffffL +#define PB0_DFT_JIT_INJ_REG2__DFT_LANE_EN__SHIFT 0x00000000 +#define PB0_GLB_CTRL_REG0__BACKUP_MASK 0x0000ffffL +#define PB0_GLB_CTRL_REG0__BACKUP__SHIFT 0x00000000 +#define PB0_GLB_CTRL_REG0__CFG_IDLEDET_TH_MASK 0x00030000L +#define PB0_GLB_CTRL_REG0__CFG_IDLEDET_TH__SHIFT 0x00000010 +#define PB0_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL_MASK 0x00700000L +#define PB0_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL__SHIFT 0x00000014 +#define PB0_GLB_CTRL_REG0__DBG_RXFEBYP_EN_MASK 0x00800000L +#define PB0_GLB_CTRL_REG0__DBG_RXFEBYP_EN__SHIFT 0x00000017 +#define PB0_GLB_CTRL_REG0__DBG_RXPRBS_CLR_MASK 0x01000000L +#define PB0_GLB_CTRL_REG0__DBG_RXPRBS_CLR__SHIFT 0x00000018 +#define PB0_GLB_CTRL_REG0__DBG_RXTOGGLE_EN_MASK 0x02000000L +#define PB0_GLB_CTRL_REG0__DBG_RXTOGGLE_EN__SHIFT 0x00000019 +#define PB0_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN_MASK 0x04000000L +#define PB0_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN__SHIFT 0x0000001a +#define PB0_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE_MASK 0xc0000000L +#define PB0_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE__SHIFT 0x0000001e +#define PB0_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV_MASK 0x80000000L +#define PB0_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV__SHIFT 0x0000001f +#define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN_MASK 0x00000001L +#define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN__SHIFT 0x00000000 +#define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL_MASK 0x0000007eL +#define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL__SHIFT 0x00000001 +#define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN_MASK 0x00000080L +#define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN__SHIFT 0x00000007 +#define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL_MASK 0x00003f00L +#define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL__SHIFT 0x00000008 +#define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN_MASK 0x00004000L +#define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN__SHIFT 0x0000000e +#define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL_MASK 0x003f8000L +#define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL__SHIFT 0x0000000f +#define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN_MASK 0x00400000L +#define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN__SHIFT 0x00000016 +#define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL_MASK 0x3f800000L +#define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL__SHIFT 0x00000017 +#define PB0_GLB_CTRL_REG1__TST_LOSPDTST_EN_MASK 0x40000000L +#define PB0_GLB_CTRL_REG1__TST_LOSPDTST_EN__SHIFT 0x0000001e +#define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN_MASK 0x00000001L +#define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN__SHIFT 0x00000000 +#define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL_MASK 0x000000feL +#define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL__SHIFT 0x00000001 +#define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN_MASK 0x00000100L +#define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN__SHIFT 0x00000008 +#define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL_MASK 0x0000fe00L +#define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL__SHIFT 0x00000009 +#define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN_MASK 0x00010000L +#define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN__SHIFT 0x00000010 +#define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL_MASK 0x00fe0000L +#define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL__SHIFT 0x00000011 +#define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN_MASK 0x01000000L +#define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN__SHIFT 0x00000018 +#define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL_MASK 0xfe000000L +#define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL__SHIFT 0x00000019 +#define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL_MASK 0x00000060L +#define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL__SHIFT 0x00000005 +#define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL_MASK 0x00000180L +#define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL__SHIFT 0x00000007 +#define PB0_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL_MASK 0x00000600L +#define PB0_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL__SHIFT 0x00000009 +#define PB0_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL_MASK 0x0001c000L +#define PB0_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL__SHIFT 0x0000000e +#define PB0_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN_MASK 0x00001000L +#define PB0_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN__SHIFT 0x0000000c +#define PB0_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN_MASK 0x00000800L +#define PB0_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN__SHIFT 0x0000000b +#define PB0_GLB_CTRL_REG3__DBG_DLL_CLK_SEL_MASK 0x001c0000L +#define PB0_GLB_CTRL_REG3__DBG_DLL_CLK_SEL__SHIFT 0x00000012 +#define PB0_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE_MASK 0x80000000L +#define PB0_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE__SHIFT 0x0000001f +#define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN_MASK 0x00400000L +#define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN__SHIFT 0x00000016 +#define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL_MASK 0x07800000L +#define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL__SHIFT 0x00000017 +#define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN_MASK 0x08000000L +#define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN__SHIFT 0x0000001b +#define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL_MASK 0x70000000L +#define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL__SHIFT 0x0000001c +#define PB0_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL_MASK 0x00200000L +#define PB0_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL__SHIFT 0x00000015 +#define PB0_GLB_CTRL_REG3__RXDBG_SEL_MASK 0x0000001fL +#define PB0_GLB_CTRL_REG3__RXDBG_SEL__SHIFT 0x00000000 +#define PB0_GLB_CTRL_REG4__DBG_RXAPU_EXEC_MASK 0x03c00000L +#define PB0_GLB_CTRL_REG4__DBG_RXAPU_EXEC__SHIFT 0x00000016 +#define PB0_GLB_CTRL_REG4__DBG_RXAPU_INST_MASK 0x0000ffffL +#define PB0_GLB_CTRL_REG4__DBG_RXAPU_INST__SHIFT 0x00000000 +#define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN_MASK 0x00040000L +#define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN__SHIFT 0x00000012 +#define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL_MASK 0x00030000L +#define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL__SHIFT 0x00000010 +#define PB0_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL_MASK 0x04000000L +#define PB0_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL__SHIFT 0x0000001a +#define PB0_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE_MASK 0x10000000L +#define PB0_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE__SHIFT 0x0000001c +#define PB0_GLB_CTRL_REG4__PWRGOOD_OVRD_MASK 0x08000000L +#define PB0_GLB_CTRL_REG4__PWRGOOD_OVRD__SHIFT 0x0000001b +#define PB0_GLB_CTRL_REG5__DBG_RXAPU_MODE_MASK 0x000000ffL +#define PB0_GLB_CTRL_REG5__DBG_RXAPU_MODE__SHIFT 0x00000000 +#define PB0_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL_MASK 0x0000ffffL +#define PB0_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL__SHIFT 0x00000000 +#define PB0_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL_MASK 0xffff0000L +#define PB0_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL__SHIFT 0x00000010 +#define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN_MASK 0x00008000L +#define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN__SHIFT 0x0000000f +#define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL_MASK 0xffff0000L +#define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL__SHIFT 0x00000010 +#define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN_MASK 0x00000004L +#define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN__SHIFT 0x00000002 +#define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL_MASK 0x00000008L +#define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL__SHIFT 0x00000003 +#define PB0_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN_MASK 0x00000001L +#define PB0_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN__SHIFT 0x00000000 +#define PB0_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN_MASK 0x00000002L +#define PB0_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN__SHIFT 0x00000001 +#define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_EN_MASK 0x00000001L +#define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_EN__SHIFT 0x00000000 +#define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL_MASK 0x00000002L +#define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL__SHIFT 0x00000001 +#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L0T3_MASK 0x00000001L +#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L0T3__SHIFT 0x00000000 +#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L12T15_MASK 0x00000008L +#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L12T15__SHIFT 0x00000003 +#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L4T7_MASK 0x00000002L +#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L4T7__SHIFT 0x00000001 +#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L8T11_MASK 0x00000004L +#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L8T11__SHIFT 0x00000002 +#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_SCI_UPDT_MASK 0x00000010L +#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_SCI_UPDT__SHIFT 0x00000004 +#define PB0_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE_MASK 0x00100000L +#define PB0_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE__SHIFT 0x00000014 +#define PB0_GLB_SCI_STAT_OVRD_REG0__RXIMP_MASK 0x000f0000L +#define PB0_GLB_SCI_STAT_OVRD_REG0__RXIMP__SHIFT 0x00000010 +#define PB0_GLB_SCI_STAT_OVRD_REG0__TXNIMP_MASK 0x00000f00L +#define PB0_GLB_SCI_STAT_OVRD_REG0__TXNIMP__SHIFT 0x00000008 +#define PB0_GLB_SCI_STAT_OVRD_REG0__TXPIMP_MASK 0x0000f000L +#define PB0_GLB_SCI_STAT_OVRD_REG0__TXPIMP__SHIFT 0x0000000c +#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0_MASK 0x00001000L +#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0__SHIFT 0x0000000c +#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1_MASK 0x00002000L +#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1__SHIFT 0x0000000d +#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2_MASK 0x00004000L +#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2__SHIFT 0x0000000e +#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3_MASK 0x00008000L +#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3__SHIFT 0x0000000f +#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0_MASK 0x000c0000L +#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0__SHIFT 0x00000012 +#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1_MASK 0x00c00000L +#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1__SHIFT 0x00000016 +#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2_MASK 0x0c000000L +#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2__SHIFT 0x0000001a +#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3_MASK 0xc0000000L +#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3__SHIFT 0x0000001e +#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_SCI_UPDT_L0T3_MASK 0x00000004L +#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_SCI_UPDT_L0T3__SHIFT 0x00000002 +#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_SCI_UPDT_L0T3_MASK 0x00000002L +#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_SCI_UPDT_L0T3__SHIFT 0x00000001 +#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_MODE_SCI_UPDT_L0T3_MASK 0x00000001L +#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_MODE_SCI_UPDT_L0T3__SHIFT 0x00000000 +#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_0_MASK 0x00030000L +#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_0__SHIFT 0x00000010 +#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_1_MASK 0x00300000L +#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_1__SHIFT 0x00000014 +#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_2_MASK 0x03000000L +#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_2__SHIFT 0x00000018 +#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_3_MASK 0x30000000L +#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_3__SHIFT 0x0000001c +#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4_MASK 0x00001000L +#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4__SHIFT 0x0000000c +#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5_MASK 0x00002000L +#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5__SHIFT 0x0000000d +#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6_MASK 0x00004000L +#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6__SHIFT 0x0000000e +#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7_MASK 0x00008000L +#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7__SHIFT 0x0000000f +#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4_MASK 0x000c0000L +#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4__SHIFT 0x00000012 +#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5_MASK 0x00c00000L +#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5__SHIFT 0x00000016 +#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6_MASK 0x0c000000L +#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6__SHIFT 0x0000001a +#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7_MASK 0xc0000000L +#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7__SHIFT 0x0000001e +#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_SCI_UPDT_L4T7_MASK 0x00000004L +#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_SCI_UPDT_L4T7__SHIFT 0x00000002 +#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_SCI_UPDT_L4T7_MASK 0x00000002L +#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_SCI_UPDT_L4T7__SHIFT 0x00000001 +#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_MODE_SCI_UPDT_L4T7_MASK 0x00000001L +#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_MODE_SCI_UPDT_L4T7__SHIFT 0x00000000 +#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_4_MASK 0x00030000L +#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_4__SHIFT 0x00000010 +#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_5_MASK 0x00300000L +#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_5__SHIFT 0x00000014 +#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_6_MASK 0x03000000L +#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_6__SHIFT 0x00000018 +#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_7_MASK 0x30000000L +#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_7__SHIFT 0x0000001c +#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10_MASK 0x00004000L +#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10__SHIFT 0x0000000e +#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11_MASK 0x00008000L +#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11__SHIFT 0x0000000f +#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8_MASK 0x00001000L +#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8__SHIFT 0x0000000c +#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9_MASK 0x00002000L +#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9__SHIFT 0x0000000d +#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10_MASK 0x0c000000L +#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10__SHIFT 0x0000001a +#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11_MASK 0xc0000000L +#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11__SHIFT 0x0000001e +#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8_MASK 0x000c0000L +#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8__SHIFT 0x00000012 +#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9_MASK 0x00c00000L +#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9__SHIFT 0x00000016 +#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_SCI_UPDT_L8T11_MASK 0x00000004L +#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_SCI_UPDT_L8T11__SHIFT 0x00000002 +#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_SCI_UPDT_L8T11_MASK 0x00000002L +#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_SCI_UPDT_L8T11__SHIFT 0x00000001 +#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_MODE_SCI_UPDT_L8T11_MASK 0x00000001L +#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_MODE_SCI_UPDT_L8T11__SHIFT 0x00000000 +#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_10_MASK 0x03000000L +#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_10__SHIFT 0x00000018 +#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_11_MASK 0x30000000L +#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_11__SHIFT 0x0000001c +#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_8_MASK 0x00030000L +#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_8__SHIFT 0x00000010 +#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_9_MASK 0x00300000L +#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_9__SHIFT 0x00000014 +#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12_MASK 0x00001000L +#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12__SHIFT 0x0000000c +#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13_MASK 0x00002000L +#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13__SHIFT 0x0000000d +#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14_MASK 0x00004000L +#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14__SHIFT 0x0000000e +#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15_MASK 0x00008000L +#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15__SHIFT 0x0000000f +#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12_MASK 0x000c0000L +#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12__SHIFT 0x00000012 +#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13_MASK 0x00c00000L +#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13__SHIFT 0x00000016 +#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14_MASK 0x0c000000L +#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14__SHIFT 0x0000001a +#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15_MASK 0xc0000000L +#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15__SHIFT 0x0000001e +#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_SCI_UPDT_L12T15_MASK 0x00000004L +#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_SCI_UPDT_L12T15__SHIFT 0x00000002 +#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_SCI_UPDT_L12T15_MASK 0x00000002L +#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_SCI_UPDT_L12T15__SHIFT 0x00000001 +#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_MODE_SCI_UPDT_L12T15_MASK 0x00000001L +#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_MODE_SCI_UPDT_L12T15__SHIFT 0x00000000 +#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_12_MASK 0x00030000L +#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_12__SHIFT 0x00000010 +#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_13_MASK 0x00300000L +#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_13__SHIFT 0x00000014 +#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_14_MASK 0x03000000L +#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_14__SHIFT 0x00000018 +#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_15_MASK 0x30000000L +#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_15__SHIFT 0x0000001c +#define PB0_HW_DEBUG__PB0_HW_00_DEBUG_MASK 0x00000001L +#define PB0_HW_DEBUG__PB0_HW_00_DEBUG__SHIFT 0x00000000 +#define PB0_HW_DEBUG__PB0_HW_01_DEBUG_MASK 0x00000002L +#define PB0_HW_DEBUG__PB0_HW_01_DEBUG__SHIFT 0x00000001 +#define PB0_HW_DEBUG__PB0_HW_02_DEBUG_MASK 0x00000004L +#define PB0_HW_DEBUG__PB0_HW_02_DEBUG__SHIFT 0x00000002 +#define PB0_HW_DEBUG__PB0_HW_03_DEBUG_MASK 0x00000008L +#define PB0_HW_DEBUG__PB0_HW_03_DEBUG__SHIFT 0x00000003 +#define PB0_HW_DEBUG__PB0_HW_04_DEBUG_MASK 0x00000010L +#define PB0_HW_DEBUG__PB0_HW_04_DEBUG__SHIFT 0x00000004 +#define PB0_HW_DEBUG__PB0_HW_05_DEBUG_MASK 0x00000020L +#define PB0_HW_DEBUG__PB0_HW_05_DEBUG__SHIFT 0x00000005 +#define PB0_HW_DEBUG__PB0_HW_06_DEBUG_MASK 0x00000040L +#define PB0_HW_DEBUG__PB0_HW_06_DEBUG__SHIFT 0x00000006 +#define PB0_HW_DEBUG__PB0_HW_07_DEBUG_MASK 0x00000080L +#define PB0_HW_DEBUG__PB0_HW_07_DEBUG__SHIFT 0x00000007 +#define PB0_HW_DEBUG__PB0_HW_08_DEBUG_MASK 0x00000100L +#define PB0_HW_DEBUG__PB0_HW_08_DEBUG__SHIFT 0x00000008 +#define PB0_HW_DEBUG__PB0_HW_09_DEBUG_MASK 0x00000200L +#define PB0_HW_DEBUG__PB0_HW_09_DEBUG__SHIFT 0x00000009 +#define PB0_HW_DEBUG__PB0_HW_10_DEBUG_MASK 0x00000400L +#define PB0_HW_DEBUG__PB0_HW_10_DEBUG__SHIFT 0x0000000a +#define PB0_HW_DEBUG__PB0_HW_11_DEBUG_MASK 0x00000800L +#define PB0_HW_DEBUG__PB0_HW_11_DEBUG__SHIFT 0x0000000b +#define PB0_HW_DEBUG__PB0_HW_12_DEBUG_MASK 0x00001000L +#define PB0_HW_DEBUG__PB0_HW_12_DEBUG__SHIFT 0x0000000c +#define PB0_HW_DEBUG__PB0_HW_13_DEBUG_MASK 0x00002000L +#define PB0_HW_DEBUG__PB0_HW_13_DEBUG__SHIFT 0x0000000d +#define PB0_HW_DEBUG__PB0_HW_14_DEBUG_MASK 0x00004000L +#define PB0_HW_DEBUG__PB0_HW_14_DEBUG__SHIFT 0x0000000e +#define PB0_HW_DEBUG__PB0_HW_15_DEBUG_MASK 0x00008000L +#define PB0_HW_DEBUG__PB0_HW_15_DEBUG__SHIFT 0x0000000f +#define PB0_HW_DEBUG__PB0_HW_16_DEBUG_MASK 0x00010000L +#define PB0_HW_DEBUG__PB0_HW_16_DEBUG__SHIFT 0x00000010 +#define PB0_HW_DEBUG__PB0_HW_17_DEBUG_MASK 0x00020000L +#define PB0_HW_DEBUG__PB0_HW_17_DEBUG__SHIFT 0x00000011 +#define PB0_HW_DEBUG__PB0_HW_18_DEBUG_MASK 0x00040000L +#define PB0_HW_DEBUG__PB0_HW_18_DEBUG__SHIFT 0x00000012 +#define PB0_HW_DEBUG__PB0_HW_19_DEBUG_MASK 0x00080000L +#define PB0_HW_DEBUG__PB0_HW_19_DEBUG__SHIFT 0x00000013 +#define PB0_HW_DEBUG__PB0_HW_20_DEBUG_MASK 0x00100000L +#define PB0_HW_DEBUG__PB0_HW_20_DEBUG__SHIFT 0x00000014 +#define PB0_HW_DEBUG__PB0_HW_21_DEBUG_MASK 0x00200000L +#define PB0_HW_DEBUG__PB0_HW_21_DEBUG__SHIFT 0x00000015 +#define PB0_HW_DEBUG__PB0_HW_22_DEBUG_MASK 0x00400000L +#define PB0_HW_DEBUG__PB0_HW_22_DEBUG__SHIFT 0x00000016 +#define PB0_HW_DEBUG__PB0_HW_23_DEBUG_MASK 0x00800000L +#define PB0_HW_DEBUG__PB0_HW_23_DEBUG__SHIFT 0x00000017 +#define PB0_HW_DEBUG__PB0_HW_24_DEBUG_MASK 0x01000000L +#define PB0_HW_DEBUG__PB0_HW_24_DEBUG__SHIFT 0x00000018 +#define PB0_HW_DEBUG__PB0_HW_25_DEBUG_MASK 0x02000000L +#define PB0_HW_DEBUG__PB0_HW_25_DEBUG__SHIFT 0x00000019 +#define PB0_HW_DEBUG__PB0_HW_26_DEBUG_MASK 0x04000000L +#define PB0_HW_DEBUG__PB0_HW_26_DEBUG__SHIFT 0x0000001a +#define PB0_HW_DEBUG__PB0_HW_27_DEBUG_MASK 0x08000000L +#define PB0_HW_DEBUG__PB0_HW_27_DEBUG__SHIFT 0x0000001b +#define PB0_HW_DEBUG__PB0_HW_28_DEBUG_MASK 0x10000000L +#define PB0_HW_DEBUG__PB0_HW_28_DEBUG__SHIFT 0x0000001c +#define PB0_HW_DEBUG__PB0_HW_29_DEBUG_MASK 0x20000000L +#define PB0_HW_DEBUG__PB0_HW_29_DEBUG__SHIFT 0x0000001d +#define PB0_HW_DEBUG__PB0_HW_30_DEBUG_MASK 0x40000000L +#define PB0_HW_DEBUG__PB0_HW_30_DEBUG__SHIFT 0x0000001e +#define PB0_HW_DEBUG__PB0_HW_31_DEBUG_MASK 0x80000000L +#define PB0_HW_DEBUG__PB0_HW_31_DEBUG__SHIFT 0x0000001f +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_EN_MASK 0x00000080L +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_EN__SHIFT 0x00000007 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_0_MASK 0x00000100L +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_0__SHIFT 0x00000008 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_10_MASK 0x00040000L +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_10__SHIFT 0x00000012 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_11_MASK 0x00080000L +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_11__SHIFT 0x00000013 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_12_MASK 0x00100000L +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_12__SHIFT 0x00000014 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_13_MASK 0x00200000L +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_13__SHIFT 0x00000015 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_14_MASK 0x00400000L +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_14__SHIFT 0x00000016 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_15_MASK 0x00800000L +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_15__SHIFT 0x00000017 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_1_MASK 0x00000200L +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_1__SHIFT 0x00000009 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_2_MASK 0x00000400L +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_2__SHIFT 0x0000000a +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_3_MASK 0x00000800L +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_3__SHIFT 0x0000000b +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_4_MASK 0x00001000L +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_4__SHIFT 0x0000000c +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_5_MASK 0x00002000L +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_5__SHIFT 0x0000000d +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_6_MASK 0x00004000L +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_6__SHIFT 0x0000000e +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_7_MASK 0x00008000L +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_7__SHIFT 0x0000000f +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_8_MASK 0x00010000L +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_8__SHIFT 0x00000010 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_9_MASK 0x00020000L +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_9__SHIFT 0x00000011 +#define PB0_PIF_CNTL2__RXDETECT_SAMPL_TIME_MASK 0x00000006L +#define PB0_PIF_CNTL2__RXDETECT_SAMPL_TIME__SHIFT 0x00000001 +#define PB0_PIF_CNTL2__RXPHYSTATUS_DELAY_MASK 0x07000000L +#define PB0_PIF_CNTL2__RXPHYSTATUS_DELAY__SHIFT 0x00000018 +#define PB0_PIF_CNTL__DA_FIFO_RESET_0_MASK 0x00000002L +#define PB0_PIF_CNTL__DA_FIFO_RESET_0__SHIFT 0x00000001 +#define PB0_PIF_CNTL__DA_FIFO_RESET_1_MASK 0x00000020L +#define PB0_PIF_CNTL__DA_FIFO_RESET_1__SHIFT 0x00000005 +#define PB0_PIF_CNTL__DA_FIFO_RESET_2_MASK 0x00000200L +#define PB0_PIF_CNTL__DA_FIFO_RESET_2__SHIFT 0x00000009 +#define PB0_PIF_CNTL__DA_FIFO_RESET_3_MASK 0x00002000L +#define PB0_PIF_CNTL__DA_FIFO_RESET_3__SHIFT 0x0000000d +#define PB0_PIF_CNTL__DIVINIT_MODE_MASK 0x00000100L +#define PB0_PIF_CNTL__DIVINIT_MODE__SHIFT 0x00000008 +#define PB0_PIF_CNTL__EI_CYCLE_OFF_TIME_MASK 0x00700000L +#define PB0_PIF_CNTL__EI_CYCLE_OFF_TIME__SHIFT 0x00000014 +#define PB0_PIF_CNTL__EI_DET_CYCLE_MODE_MASK 0x00000010L +#define PB0_PIF_CNTL__EI_DET_CYCLE_MODE__SHIFT 0x00000004 +#define PB0_PIF_CNTL__EXIT_L0S_INIT_DIS_MASK 0x00800000L +#define PB0_PIF_CNTL__EXIT_L0S_INIT_DIS__SHIFT 0x00000017 +#define PB0_PIF_CNTL__EXTEND_WAIT_FOR_RAMPUP_MASK 0x10000000L +#define PB0_PIF_CNTL__EXTEND_WAIT_FOR_RAMPUP__SHIFT 0x0000001c +#define PB0_PIF_CNTL__IGNORE_TxDataValid_EP_DIS_MASK 0x20000000L +#define PB0_PIF_CNTL__IGNORE_TxDataValid_EP_DIS__SHIFT 0x0000001d +#define PB0_PIF_CNTL__LS2_EXIT_TIME_MASK 0x000e0000L +#define PB0_PIF_CNTL__LS2_EXIT_TIME__SHIFT 0x00000011 +#define PB0_PIF_CNTL__PHYCMD_CR_EN_MODE_MASK 0x00000008L +#define PB0_PIF_CNTL__PHYCMD_CR_EN_MODE__SHIFT 0x00000003 +#define PB0_PIF_CNTL__PHY_CR_EN_MODE_MASK 0x00000004L +#define PB0_PIF_CNTL__PHY_CR_EN_MODE__SHIFT 0x00000002 +#define PB0_PIF_CNTL__PLL_BINDING_ENABLE_MASK 0x00000400L +#define PB0_PIF_CNTL__PLL_BINDING_ENABLE__SHIFT 0x0000000a +#define PB0_PIF_CNTL__RXDETECT_FIFO_RESET_MODE_MASK 0x00000040L +#define PB0_PIF_CNTL__RXDETECT_FIFO_RESET_MODE__SHIFT 0x00000006 +#define PB0_PIF_CNTL__RXDETECT_TX_PWR_MODE_MASK 0x00000080L +#define PB0_PIF_CNTL__RXDETECT_TX_PWR_MODE__SHIFT 0x00000007 +#define PB0_PIF_CNTL__RXEN_GATER_MASK 0x0f000000L +#define PB0_PIF_CNTL__RXEN_GATER__SHIFT 0x00000018 +#define PB0_PIF_CNTL__SC_CALIB_DONE_CNTL_MASK 0x00000800L +#define PB0_PIF_CNTL__SC_CALIB_DONE_CNTL__SHIFT 0x0000000b +#define PB0_PIF_CNTL__SERIAL_CFG_ENABLE_MASK 0x00000001L +#define PB0_PIF_CNTL__SERIAL_CFG_ENABLE__SHIFT 0x00000000 +#define PB0_PIF_CNTL__TXGND_TIME_MASK 0x00010000L +#define PB0_PIF_CNTL__TXGND_TIME__SHIFT 0x00000010 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_00_DEBUG_MASK 0x00000001L +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_00_DEBUG__SHIFT 0x00000000 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_01_DEBUG_MASK 0x00000002L +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_01_DEBUG__SHIFT 0x00000001 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_02_DEBUG_MASK 0x00000004L +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_02_DEBUG__SHIFT 0x00000002 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_03_DEBUG_MASK 0x00000008L +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_03_DEBUG__SHIFT 0x00000003 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_04_DEBUG_MASK 0x00000010L +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_04_DEBUG__SHIFT 0x00000004 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_05_DEBUG_MASK 0x00000020L +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_05_DEBUG__SHIFT 0x00000005 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_06_DEBUG_MASK 0x00000040L +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_06_DEBUG__SHIFT 0x00000006 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_07_DEBUG_MASK 0x00000080L +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_07_DEBUG__SHIFT 0x00000007 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_08_DEBUG_MASK 0x00000100L +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_08_DEBUG__SHIFT 0x00000008 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_09_DEBUG_MASK 0x00000200L +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_09_DEBUG__SHIFT 0x00000009 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_10_DEBUG_MASK 0x00000400L +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_10_DEBUG__SHIFT 0x0000000a +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_11_DEBUG_MASK 0x00000800L +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_11_DEBUG__SHIFT 0x0000000b +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_12_DEBUG_MASK 0x00001000L +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_12_DEBUG__SHIFT 0x0000000c +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_13_DEBUG_MASK 0x00002000L +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_13_DEBUG__SHIFT 0x0000000d +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_14_DEBUG_MASK 0x00004000L +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_14_DEBUG__SHIFT 0x0000000e +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_15_DEBUG_MASK 0x00008000L +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_15_DEBUG__SHIFT 0x0000000f +#define PB0_PIF_PAIRING__MULTI_PIF_MASK 0x02000000L +#define PB0_PIF_PAIRING__MULTI_PIF__SHIFT 0x00000019 +#define PB0_PIF_PAIRING__X16_LANE_15_0_MASK 0x00100000L +#define PB0_PIF_PAIRING__X16_LANE_15_0__SHIFT 0x00000014 +#define PB0_PIF_PAIRING__X2_LANE_1_0_MASK 0x00000001L +#define PB0_PIF_PAIRING__X2_LANE_1_0__SHIFT 0x00000000 +#define PB0_PIF_PAIRING__X2_LANE_11_10_MASK 0x00000020L +#define PB0_PIF_PAIRING__X2_LANE_11_10__SHIFT 0x00000005 +#define PB0_PIF_PAIRING__X2_LANE_13_12_MASK 0x00000040L +#define PB0_PIF_PAIRING__X2_LANE_13_12__SHIFT 0x00000006 +#define PB0_PIF_PAIRING__X2_LANE_15_14_MASK 0x00000080L +#define PB0_PIF_PAIRING__X2_LANE_15_14__SHIFT 0x00000007 +#define PB0_PIF_PAIRING__X2_LANE_3_2_MASK 0x00000002L +#define PB0_PIF_PAIRING__X2_LANE_3_2__SHIFT 0x00000001 +#define PB0_PIF_PAIRING__X2_LANE_5_4_MASK 0x00000004L +#define PB0_PIF_PAIRING__X2_LANE_5_4__SHIFT 0x00000002 +#define PB0_PIF_PAIRING__X2_LANE_7_6_MASK 0x00000008L +#define PB0_PIF_PAIRING__X2_LANE_7_6__SHIFT 0x00000003 +#define PB0_PIF_PAIRING__X2_LANE_9_8_MASK 0x00000010L +#define PB0_PIF_PAIRING__X2_LANE_9_8__SHIFT 0x00000004 +#define PB0_PIF_PAIRING__X4_LANE_11_8_MASK 0x00000400L +#define PB0_PIF_PAIRING__X4_LANE_11_8__SHIFT 0x0000000a +#define PB0_PIF_PAIRING__X4_LANE_15_12_MASK 0x00000800L +#define PB0_PIF_PAIRING__X4_LANE_15_12__SHIFT 0x0000000b +#define PB0_PIF_PAIRING__X4_LANE_3_0_MASK 0x00000100L +#define PB0_PIF_PAIRING__X4_LANE_3_0__SHIFT 0x00000008 +#define PB0_PIF_PAIRING__X4_LANE_7_4_MASK 0x00000200L +#define PB0_PIF_PAIRING__X4_LANE_7_4__SHIFT 0x00000009 +#define PB0_PIF_PAIRING__X8_LANE_15_8_MASK 0x00020000L +#define PB0_PIF_PAIRING__X8_LANE_15_8__SHIFT 0x00000011 +#define PB0_PIF_PAIRING__X8_LANE_7_0_MASK 0x00010000L +#define PB0_PIF_PAIRING__X8_LANE_7_0__SHIFT 0x00000010 +#define PB0_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_EN_0_MASK 0x00000100L +#define PB0_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_EN_0__SHIFT 0x00000008 +#define PB0_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_VAL_0_MASK 0x00000200L +#define PB0_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_VAL_0__SHIFT 0x00000009 +#define PB0_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_EN_0_MASK 0x00000010L +#define PB0_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_EN_0__SHIFT 0x00000004 +#define PB0_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_VAL_0_MASK 0x000000e0L +#define PB0_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_VAL_0__SHIFT 0x00000005 +#define PB0_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_EN_0_MASK 0x00004000L +#define PB0_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_EN_0__SHIFT 0x0000000e +#define PB0_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_VAL_0_MASK 0x00038000L +#define PB0_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_VAL_0__SHIFT 0x0000000f +#define PB0_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_EN_0_MASK 0x00000001L +#define PB0_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_EN_0__SHIFT 0x00000000 +#define PB0_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_VAL_0_MASK 0x0000000eL +#define PB0_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_VAL_0__SHIFT 0x00000001 +#define PB0_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_EN_0_MASK 0x00000400L +#define PB0_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_EN_0__SHIFT 0x0000000a +#define PB0_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_VAL_0_MASK 0x00003800L +#define PB0_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_VAL_0__SHIFT 0x0000000b +#define PB0_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_EN_10_MASK 0x00000100L +#define PB0_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_EN_10__SHIFT 0x00000008 +#define PB0_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_VAL_10_MASK 0x00000200L +#define PB0_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_VAL_10__SHIFT 0x00000009 +#define PB0_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_EN_10_MASK 0x00000010L +#define PB0_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_EN_10__SHIFT 0x00000004 +#define PB0_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_VAL_10_MASK 0x000000e0L +#define PB0_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_VAL_10__SHIFT 0x00000005 +#define PB0_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_EN_10_MASK 0x00004000L +#define PB0_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_EN_10__SHIFT 0x0000000e +#define PB0_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_VAL_10_MASK 0x00038000L +#define PB0_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_VAL_10__SHIFT 0x0000000f +#define PB0_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_EN_10_MASK 0x00000001L +#define PB0_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_EN_10__SHIFT 0x00000000 +#define PB0_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_VAL_10_MASK 0x0000000eL +#define PB0_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_VAL_10__SHIFT 0x00000001 +#define PB0_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_EN_10_MASK 0x00000400L +#define PB0_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_EN_10__SHIFT 0x0000000a +#define PB0_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_VAL_10_MASK 0x00003800L +#define PB0_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_VAL_10__SHIFT 0x0000000b +#define PB0_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_EN_11_MASK 0x00000100L +#define PB0_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_EN_11__SHIFT 0x00000008 +#define PB0_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_VAL_11_MASK 0x00000200L +#define PB0_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_VAL_11__SHIFT 0x00000009 +#define PB0_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_EN_11_MASK 0x00000010L +#define PB0_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_EN_11__SHIFT 0x00000004 +#define PB0_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_VAL_11_MASK 0x000000e0L +#define PB0_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_VAL_11__SHIFT 0x00000005 +#define PB0_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_EN_11_MASK 0x00004000L +#define PB0_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_EN_11__SHIFT 0x0000000e +#define PB0_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_VAL_11_MASK 0x00038000L +#define PB0_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_VAL_11__SHIFT 0x0000000f +#define PB0_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_EN_11_MASK 0x00000001L +#define PB0_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_EN_11__SHIFT 0x00000000 +#define PB0_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_VAL_11_MASK 0x0000000eL +#define PB0_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_VAL_11__SHIFT 0x00000001 +#define PB0_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_EN_11_MASK 0x00000400L +#define PB0_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_EN_11__SHIFT 0x0000000a +#define PB0_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_VAL_11_MASK 0x00003800L +#define PB0_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_VAL_11__SHIFT 0x0000000b +#define PB0_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_EN_12_MASK 0x00000100L +#define PB0_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_EN_12__SHIFT 0x00000008 +#define PB0_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_VAL_12_MASK 0x00000200L +#define PB0_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_VAL_12__SHIFT 0x00000009 +#define PB0_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_EN_12_MASK 0x00000010L +#define PB0_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_EN_12__SHIFT 0x00000004 +#define PB0_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_VAL_12_MASK 0x000000e0L +#define PB0_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_VAL_12__SHIFT 0x00000005 +#define PB0_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_EN_12_MASK 0x00004000L +#define PB0_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_EN_12__SHIFT 0x0000000e +#define PB0_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_VAL_12_MASK 0x00038000L +#define PB0_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_VAL_12__SHIFT 0x0000000f +#define PB0_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_EN_12_MASK 0x00000001L +#define PB0_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_EN_12__SHIFT 0x00000000 +#define PB0_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_VAL_12_MASK 0x0000000eL +#define PB0_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_VAL_12__SHIFT 0x00000001 +#define PB0_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_EN_12_MASK 0x00000400L +#define PB0_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_EN_12__SHIFT 0x0000000a +#define PB0_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_VAL_12_MASK 0x00003800L +#define PB0_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_VAL_12__SHIFT 0x0000000b +#define PB0_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_EN_13_MASK 0x00000100L +#define PB0_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_EN_13__SHIFT 0x00000008 +#define PB0_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_VAL_13_MASK 0x00000200L +#define PB0_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_VAL_13__SHIFT 0x00000009 +#define PB0_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_EN_13_MASK 0x00000010L +#define PB0_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_EN_13__SHIFT 0x00000004 +#define PB0_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_VAL_13_MASK 0x000000e0L +#define PB0_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_VAL_13__SHIFT 0x00000005 +#define PB0_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_EN_13_MASK 0x00004000L +#define PB0_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_EN_13__SHIFT 0x0000000e +#define PB0_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_VAL_13_MASK 0x00038000L +#define PB0_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_VAL_13__SHIFT 0x0000000f +#define PB0_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_EN_13_MASK 0x00000001L +#define PB0_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_EN_13__SHIFT 0x00000000 +#define PB0_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_VAL_13_MASK 0x0000000eL +#define PB0_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_VAL_13__SHIFT 0x00000001 +#define PB0_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_EN_13_MASK 0x00000400L +#define PB0_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_EN_13__SHIFT 0x0000000a +#define PB0_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_VAL_13_MASK 0x00003800L +#define PB0_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_VAL_13__SHIFT 0x0000000b +#define PB0_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_EN_14_MASK 0x00000100L +#define PB0_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_EN_14__SHIFT 0x00000008 +#define PB0_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_VAL_14_MASK 0x00000200L +#define PB0_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_VAL_14__SHIFT 0x00000009 +#define PB0_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_EN_14_MASK 0x00000010L +#define PB0_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_EN_14__SHIFT 0x00000004 +#define PB0_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_VAL_14_MASK 0x000000e0L +#define PB0_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_VAL_14__SHIFT 0x00000005 +#define PB0_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_EN_14_MASK 0x00004000L +#define PB0_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_EN_14__SHIFT 0x0000000e +#define PB0_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_VAL_14_MASK 0x00038000L +#define PB0_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_VAL_14__SHIFT 0x0000000f +#define PB0_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_EN_14_MASK 0x00000001L +#define PB0_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_EN_14__SHIFT 0x00000000 +#define PB0_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_VAL_14_MASK 0x0000000eL +#define PB0_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_VAL_14__SHIFT 0x00000001 +#define PB0_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_EN_14_MASK 0x00000400L +#define PB0_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_EN_14__SHIFT 0x0000000a +#define PB0_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_VAL_14_MASK 0x00003800L +#define PB0_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_VAL_14__SHIFT 0x0000000b +#define PB0_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_EN_15_MASK 0x00000100L +#define PB0_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_EN_15__SHIFT 0x00000008 +#define PB0_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_VAL_15_MASK 0x00000200L +#define PB0_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_VAL_15__SHIFT 0x00000009 +#define PB0_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_EN_15_MASK 0x00000010L +#define PB0_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_EN_15__SHIFT 0x00000004 +#define PB0_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_VAL_15_MASK 0x000000e0L +#define PB0_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_VAL_15__SHIFT 0x00000005 +#define PB0_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_EN_15_MASK 0x00004000L +#define PB0_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_EN_15__SHIFT 0x0000000e +#define PB0_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_VAL_15_MASK 0x00038000L +#define PB0_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_VAL_15__SHIFT 0x0000000f +#define PB0_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_EN_15_MASK 0x00000001L +#define PB0_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_EN_15__SHIFT 0x00000000 +#define PB0_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_VAL_15_MASK 0x0000000eL +#define PB0_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_VAL_15__SHIFT 0x00000001 +#define PB0_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_EN_15_MASK 0x00000400L +#define PB0_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_EN_15__SHIFT 0x0000000a +#define PB0_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_VAL_15_MASK 0x00003800L +#define PB0_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_VAL_15__SHIFT 0x0000000b +#define PB0_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_EN_1_MASK 0x00000100L +#define PB0_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_EN_1__SHIFT 0x00000008 +#define PB0_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_VAL_1_MASK 0x00000200L +#define PB0_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_VAL_1__SHIFT 0x00000009 +#define PB0_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_EN_1_MASK 0x00000010L +#define PB0_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_EN_1__SHIFT 0x00000004 +#define PB0_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_VAL_1_MASK 0x000000e0L +#define PB0_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_VAL_1__SHIFT 0x00000005 +#define PB0_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_EN_1_MASK 0x00004000L +#define PB0_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_EN_1__SHIFT 0x0000000e +#define PB0_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_VAL_1_MASK 0x00038000L +#define PB0_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_VAL_1__SHIFT 0x0000000f +#define PB0_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_EN_1_MASK 0x00000001L +#define PB0_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_EN_1__SHIFT 0x00000000 +#define PB0_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_VAL_1_MASK 0x0000000eL +#define PB0_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_VAL_1__SHIFT 0x00000001 +#define PB0_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_EN_1_MASK 0x00000400L +#define PB0_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_EN_1__SHIFT 0x0000000a +#define PB0_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_VAL_1_MASK 0x00003800L +#define PB0_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_VAL_1__SHIFT 0x0000000b +#define PB0_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_EN_2_MASK 0x00000100L +#define PB0_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_EN_2__SHIFT 0x00000008 +#define PB0_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_VAL_2_MASK 0x00000200L +#define PB0_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_VAL_2__SHIFT 0x00000009 +#define PB0_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_EN_2_MASK 0x00000010L +#define PB0_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_EN_2__SHIFT 0x00000004 +#define PB0_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_VAL_2_MASK 0x000000e0L +#define PB0_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_VAL_2__SHIFT 0x00000005 +#define PB0_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_EN_2_MASK 0x00004000L +#define PB0_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_EN_2__SHIFT 0x0000000e +#define PB0_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_VAL_2_MASK 0x00038000L +#define PB0_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_VAL_2__SHIFT 0x0000000f +#define PB0_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_EN_2_MASK 0x00000001L +#define PB0_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_EN_2__SHIFT 0x00000000 +#define PB0_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_VAL_2_MASK 0x0000000eL +#define PB0_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_VAL_2__SHIFT 0x00000001 +#define PB0_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_EN_2_MASK 0x00000400L +#define PB0_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_EN_2__SHIFT 0x0000000a +#define PB0_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_VAL_2_MASK 0x00003800L +#define PB0_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_VAL_2__SHIFT 0x0000000b +#define PB0_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_EN_3_MASK 0x00000100L +#define PB0_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_EN_3__SHIFT 0x00000008 +#define PB0_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_VAL_3_MASK 0x00000200L +#define PB0_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_VAL_3__SHIFT 0x00000009 +#define PB0_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_EN_3_MASK 0x00000010L +#define PB0_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_EN_3__SHIFT 0x00000004 +#define PB0_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_VAL_3_MASK 0x000000e0L +#define PB0_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_VAL_3__SHIFT 0x00000005 +#define PB0_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_EN_3_MASK 0x00004000L +#define PB0_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_EN_3__SHIFT 0x0000000e +#define PB0_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_VAL_3_MASK 0x00038000L +#define PB0_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_VAL_3__SHIFT 0x0000000f +#define PB0_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_EN_3_MASK 0x00000001L +#define PB0_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_EN_3__SHIFT 0x00000000 +#define PB0_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_VAL_3_MASK 0x0000000eL +#define PB0_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_VAL_3__SHIFT 0x00000001 +#define PB0_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_EN_3_MASK 0x00000400L +#define PB0_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_EN_3__SHIFT 0x0000000a +#define PB0_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_VAL_3_MASK 0x00003800L +#define PB0_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_VAL_3__SHIFT 0x0000000b +#define PB0_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_EN_4_MASK 0x00000100L +#define PB0_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_EN_4__SHIFT 0x00000008 +#define PB0_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_VAL_4_MASK 0x00000200L +#define PB0_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_VAL_4__SHIFT 0x00000009 +#define PB0_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_EN_4_MASK 0x00000010L +#define PB0_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_EN_4__SHIFT 0x00000004 +#define PB0_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_VAL_4_MASK 0x000000e0L +#define PB0_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_VAL_4__SHIFT 0x00000005 +#define PB0_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_EN_4_MASK 0x00004000L +#define PB0_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_EN_4__SHIFT 0x0000000e +#define PB0_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_VAL_4_MASK 0x00038000L +#define PB0_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_VAL_4__SHIFT 0x0000000f +#define PB0_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_EN_4_MASK 0x00000001L +#define PB0_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_EN_4__SHIFT 0x00000000 +#define PB0_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_VAL_4_MASK 0x0000000eL +#define PB0_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_VAL_4__SHIFT 0x00000001 +#define PB0_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_EN_4_MASK 0x00000400L +#define PB0_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_EN_4__SHIFT 0x0000000a +#define PB0_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_VAL_4_MASK 0x00003800L +#define PB0_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_VAL_4__SHIFT 0x0000000b +#define PB0_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_EN_5_MASK 0x00000100L +#define PB0_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_EN_5__SHIFT 0x00000008 +#define PB0_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_VAL_5_MASK 0x00000200L +#define PB0_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_VAL_5__SHIFT 0x00000009 +#define PB0_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_EN_5_MASK 0x00000010L +#define PB0_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_EN_5__SHIFT 0x00000004 +#define PB0_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_VAL_5_MASK 0x000000e0L +#define PB0_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_VAL_5__SHIFT 0x00000005 +#define PB0_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_EN_5_MASK 0x00004000L +#define PB0_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_EN_5__SHIFT 0x0000000e +#define PB0_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_VAL_5_MASK 0x00038000L +#define PB0_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_VAL_5__SHIFT 0x0000000f +#define PB0_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_EN_5_MASK 0x00000001L +#define PB0_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_EN_5__SHIFT 0x00000000 +#define PB0_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_VAL_5_MASK 0x0000000eL +#define PB0_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_VAL_5__SHIFT 0x00000001 +#define PB0_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_EN_5_MASK 0x00000400L +#define PB0_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_EN_5__SHIFT 0x0000000a +#define PB0_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_VAL_5_MASK 0x00003800L +#define PB0_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_VAL_5__SHIFT 0x0000000b +#define PB0_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_EN_6_MASK 0x00000100L +#define PB0_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_EN_6__SHIFT 0x00000008 +#define PB0_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_VAL_6_MASK 0x00000200L +#define PB0_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_VAL_6__SHIFT 0x00000009 +#define PB0_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_EN_6_MASK 0x00000010L +#define PB0_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_EN_6__SHIFT 0x00000004 +#define PB0_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_VAL_6_MASK 0x000000e0L +#define PB0_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_VAL_6__SHIFT 0x00000005 +#define PB0_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_EN_6_MASK 0x00004000L +#define PB0_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_EN_6__SHIFT 0x0000000e +#define PB0_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_VAL_6_MASK 0x00038000L +#define PB0_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_VAL_6__SHIFT 0x0000000f +#define PB0_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_EN_6_MASK 0x00000001L +#define PB0_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_EN_6__SHIFT 0x00000000 +#define PB0_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_VAL_6_MASK 0x0000000eL +#define PB0_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_VAL_6__SHIFT 0x00000001 +#define PB0_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_EN_6_MASK 0x00000400L +#define PB0_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_EN_6__SHIFT 0x0000000a +#define PB0_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_VAL_6_MASK 0x00003800L +#define PB0_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_VAL_6__SHIFT 0x0000000b +#define PB0_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_EN_7_MASK 0x00000100L +#define PB0_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_EN_7__SHIFT 0x00000008 +#define PB0_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_VAL_7_MASK 0x00000200L +#define PB0_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_VAL_7__SHIFT 0x00000009 +#define PB0_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_EN_7_MASK 0x00000010L +#define PB0_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_EN_7__SHIFT 0x00000004 +#define PB0_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_VAL_7_MASK 0x000000e0L +#define PB0_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_VAL_7__SHIFT 0x00000005 +#define PB0_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_EN_7_MASK 0x00004000L +#define PB0_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_EN_7__SHIFT 0x0000000e +#define PB0_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_VAL_7_MASK 0x00038000L +#define PB0_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_VAL_7__SHIFT 0x0000000f +#define PB0_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_EN_7_MASK 0x00000001L +#define PB0_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_EN_7__SHIFT 0x00000000 +#define PB0_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_VAL_7_MASK 0x0000000eL +#define PB0_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_VAL_7__SHIFT 0x00000001 +#define PB0_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_EN_7_MASK 0x00000400L +#define PB0_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_EN_7__SHIFT 0x0000000a +#define PB0_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_VAL_7_MASK 0x00003800L +#define PB0_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_VAL_7__SHIFT 0x0000000b +#define PB0_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_EN_8_MASK 0x00000100L +#define PB0_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_EN_8__SHIFT 0x00000008 +#define PB0_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_VAL_8_MASK 0x00000200L +#define PB0_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_VAL_8__SHIFT 0x00000009 +#define PB0_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_EN_8_MASK 0x00000010L +#define PB0_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_EN_8__SHIFT 0x00000004 +#define PB0_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_VAL_8_MASK 0x000000e0L +#define PB0_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_VAL_8__SHIFT 0x00000005 +#define PB0_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_EN_8_MASK 0x00004000L +#define PB0_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_EN_8__SHIFT 0x0000000e +#define PB0_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_VAL_8_MASK 0x00038000L +#define PB0_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_VAL_8__SHIFT 0x0000000f +#define PB0_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_EN_8_MASK 0x00000001L +#define PB0_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_EN_8__SHIFT 0x00000000 +#define PB0_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_VAL_8_MASK 0x0000000eL +#define PB0_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_VAL_8__SHIFT 0x00000001 +#define PB0_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_EN_8_MASK 0x00000400L +#define PB0_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_EN_8__SHIFT 0x0000000a +#define PB0_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_VAL_8_MASK 0x00003800L +#define PB0_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_VAL_8__SHIFT 0x0000000b +#define PB0_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_EN_9_MASK 0x00000100L +#define PB0_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_EN_9__SHIFT 0x00000008 +#define PB0_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_VAL_9_MASK 0x00000200L +#define PB0_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_VAL_9__SHIFT 0x00000009 +#define PB0_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_EN_9_MASK 0x00000010L +#define PB0_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_EN_9__SHIFT 0x00000004 +#define PB0_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_VAL_9_MASK 0x000000e0L +#define PB0_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_VAL_9__SHIFT 0x00000005 +#define PB0_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_EN_9_MASK 0x00004000L +#define PB0_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_EN_9__SHIFT 0x0000000e +#define PB0_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_VAL_9_MASK 0x00038000L +#define PB0_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_VAL_9__SHIFT 0x0000000f +#define PB0_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_EN_9_MASK 0x00000001L +#define PB0_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_EN_9__SHIFT 0x00000000 +#define PB0_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_VAL_9_MASK 0x0000000eL +#define PB0_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_VAL_9__SHIFT 0x00000001 +#define PB0_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_EN_9_MASK 0x00000400L +#define PB0_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_EN_9__SHIFT 0x0000000a +#define PB0_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_VAL_9_MASK 0x00003800L +#define PB0_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_VAL_9__SHIFT 0x0000000b +#define PB0_PIF_PWRDOWN_0__FORCE_RXEN_IN_L0s_0_MASK 0x00000008L +#define PB0_PIF_PWRDOWN_0__FORCE_RXEN_IN_L0s_0__SHIFT 0x00000003 +#define PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK 0x00001c00L +#define PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT 0x0000000a +#define PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK 0x00000380L +#define PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT 0x00000007 +#define PB0_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_EN_0_MASK 0x10000000L +#define PB0_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_EN_0__SHIFT 0x0000001c +#define PB0_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_VAL_0_MASK 0xe0000000L +#define PB0_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_VAL_0__SHIFT 0x0000001d +#define PB0_PIF_PWRDOWN_0__PLL_RAMP_UP_TIME_0_MASK 0x07000000L +#define PB0_PIF_PWRDOWN_0__PLL_RAMP_UP_TIME_0__SHIFT 0x00000018 +#define PB0_PIF_PWRDOWN_0__RX_POWER_STATE_IN_RXS2_0_MASK 0x00000070L +#define PB0_PIF_PWRDOWN_0__RX_POWER_STATE_IN_RXS2_0__SHIFT 0x00000004 +#define PB0_PIF_PWRDOWN_0__TX2P5CLK_CLOCK_GATING_EN_0_MASK 0x00010000L +#define PB0_PIF_PWRDOWN_0__TX2P5CLK_CLOCK_GATING_EN_0__SHIFT 0x00000010 +#define PB0_PIF_PWRDOWN_0__TX_POWER_STATE_IN_TXS2_0_MASK 0x00000007L +#define PB0_PIF_PWRDOWN_0__TX_POWER_STATE_IN_TXS2_0__SHIFT 0x00000000 +#define PB0_PIF_PWRDOWN_1__FORCE_RXEN_IN_L0s_1_MASK 0x00000008L +#define PB0_PIF_PWRDOWN_1__FORCE_RXEN_IN_L0s_1__SHIFT 0x00000003 +#define PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK 0x00001c00L +#define PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT 0x0000000a +#define PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK 0x00000380L +#define PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT 0x00000007 +#define PB0_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_EN_1_MASK 0x10000000L +#define PB0_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_EN_1__SHIFT 0x0000001c +#define PB0_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_VAL_1_MASK 0xe0000000L +#define PB0_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_VAL_1__SHIFT 0x0000001d +#define PB0_PIF_PWRDOWN_1__PLL_RAMP_UP_TIME_1_MASK 0x07000000L +#define PB0_PIF_PWRDOWN_1__PLL_RAMP_UP_TIME_1__SHIFT 0x00000018 +#define PB0_PIF_PWRDOWN_1__RX_POWER_STATE_IN_RXS2_1_MASK 0x00000070L +#define PB0_PIF_PWRDOWN_1__RX_POWER_STATE_IN_RXS2_1__SHIFT 0x00000004 +#define PB0_PIF_PWRDOWN_1__TX2P5CLK_CLOCK_GATING_EN_1_MASK 0x00010000L +#define PB0_PIF_PWRDOWN_1__TX2P5CLK_CLOCK_GATING_EN_1__SHIFT 0x00000010 +#define PB0_PIF_PWRDOWN_1__TX_POWER_STATE_IN_TXS2_1_MASK 0x00000007L +#define PB0_PIF_PWRDOWN_1__TX_POWER_STATE_IN_TXS2_1__SHIFT 0x00000000 +#define PB0_PIF_PWRDOWN_2__FORCE_RXEN_IN_L0s_2_MASK 0x00000008L +#define PB0_PIF_PWRDOWN_2__FORCE_RXEN_IN_L0s_2__SHIFT 0x00000003 +#define PB0_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_OFF_2_MASK 0x00001c00L +#define PB0_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_OFF_2__SHIFT 0x0000000a +#define PB0_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_TXS2_2_MASK 0x00000380L +#define PB0_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_TXS2_2__SHIFT 0x00000007 +#define PB0_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_EN_2_MASK 0x10000000L +#define PB0_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_EN_2__SHIFT 0x0000001c +#define PB0_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_VAL_2_MASK 0xe0000000L +#define PB0_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_VAL_2__SHIFT 0x0000001d +#define PB0_PIF_PWRDOWN_2__PLL_RAMP_UP_TIME_2_MASK 0x07000000L +#define PB0_PIF_PWRDOWN_2__PLL_RAMP_UP_TIME_2__SHIFT 0x00000018 +#define PB0_PIF_PWRDOWN_2__RX_POWER_STATE_IN_RXS2_2_MASK 0x00000070L +#define PB0_PIF_PWRDOWN_2__RX_POWER_STATE_IN_RXS2_2__SHIFT 0x00000004 +#define PB0_PIF_PWRDOWN_2__TX2P5CLK_CLOCK_GATING_EN_2_MASK 0x00010000L +#define PB0_PIF_PWRDOWN_2__TX2P5CLK_CLOCK_GATING_EN_2__SHIFT 0x00000010 +#define PB0_PIF_PWRDOWN_2__TX_POWER_STATE_IN_TXS2_2_MASK 0x00000007L +#define PB0_PIF_PWRDOWN_2__TX_POWER_STATE_IN_TXS2_2__SHIFT 0x00000000 +#define PB0_PIF_PWRDOWN_3__FORCE_RXEN_IN_L0s_3_MASK 0x00000008L +#define PB0_PIF_PWRDOWN_3__FORCE_RXEN_IN_L0s_3__SHIFT 0x00000003 +#define PB0_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_OFF_3_MASK 0x00001c00L +#define PB0_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_OFF_3__SHIFT 0x0000000a +#define PB0_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_TXS2_3_MASK 0x00000380L +#define PB0_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_TXS2_3__SHIFT 0x00000007 +#define PB0_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_EN_3_MASK 0x10000000L +#define PB0_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_EN_3__SHIFT 0x0000001c +#define PB0_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_VAL_3_MASK 0xe0000000L +#define PB0_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_VAL_3__SHIFT 0x0000001d +#define PB0_PIF_PWRDOWN_3__PLL_RAMP_UP_TIME_3_MASK 0x07000000L +#define PB0_PIF_PWRDOWN_3__PLL_RAMP_UP_TIME_3__SHIFT 0x00000018 +#define PB0_PIF_PWRDOWN_3__RX_POWER_STATE_IN_RXS2_3_MASK 0x00000070L +#define PB0_PIF_PWRDOWN_3__RX_POWER_STATE_IN_RXS2_3__SHIFT 0x00000004 +#define PB0_PIF_PWRDOWN_3__TX2P5CLK_CLOCK_GATING_EN_3_MASK 0x00010000L +#define PB0_PIF_PWRDOWN_3__TX2P5CLK_CLOCK_GATING_EN_3__SHIFT 0x00000010 +#define PB0_PIF_PWRDOWN_3__TX_POWER_STATE_IN_TXS2_3_MASK 0x00000007L +#define PB0_PIF_PWRDOWN_3__TX_POWER_STATE_IN_TXS2_3__SHIFT 0x00000000 +#define PB0_PIF_SC_CTL__SC_CALIBRATION_MASK 0x00000001L +#define PB0_PIF_SC_CTL__SC_CALIBRATION__SHIFT 0x00000000 +#define PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0_MASK 0x00000020L +#define PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0__SHIFT 0x00000005 +#define PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0S_MASK 0x00000010L +#define PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0S__SHIFT 0x00000004 +#define PB0_PIF_SC_CTL__SC_EXIT_L1_TO_L0_MASK 0x00000008L +#define PB0_PIF_SC_CTL__SC_EXIT_L1_TO_L0__SHIFT 0x00000003 +#define PB0_PIF_SC_CTL__SC_EXIT_L1_TO_L0S_MASK 0x00000004L +#define PB0_PIF_SC_CTL__SC_EXIT_L1_TO_L0S__SHIFT 0x00000002 +#define PB0_PIF_SC_CTL__SC_LANE_0_RESUME_MASK 0x00010000L +#define PB0_PIF_SC_CTL__SC_LANE_0_RESUME__SHIFT 0x00000010 +#define PB0_PIF_SC_CTL__SC_LANE_10_RESUME_MASK 0x04000000L +#define PB0_PIF_SC_CTL__SC_LANE_10_RESUME__SHIFT 0x0000001a +#define PB0_PIF_SC_CTL__SC_LANE_11_RESUME_MASK 0x08000000L +#define PB0_PIF_SC_CTL__SC_LANE_11_RESUME__SHIFT 0x0000001b +#define PB0_PIF_SC_CTL__SC_LANE_12_RESUME_MASK 0x10000000L +#define PB0_PIF_SC_CTL__SC_LANE_12_RESUME__SHIFT 0x0000001c +#define PB0_PIF_SC_CTL__SC_LANE_13_RESUME_MASK 0x20000000L +#define PB0_PIF_SC_CTL__SC_LANE_13_RESUME__SHIFT 0x0000001d +#define PB0_PIF_SC_CTL__SC_LANE_14_RESUME_MASK 0x40000000L +#define PB0_PIF_SC_CTL__SC_LANE_14_RESUME__SHIFT 0x0000001e +#define PB0_PIF_SC_CTL__SC_LANE_15_RESUME_MASK 0x80000000L +#define PB0_PIF_SC_CTL__SC_LANE_15_RESUME__SHIFT 0x0000001f +#define PB0_PIF_SC_CTL__SC_LANE_1_RESUME_MASK 0x00020000L +#define PB0_PIF_SC_CTL__SC_LANE_1_RESUME__SHIFT 0x00000011 +#define PB0_PIF_SC_CTL__SC_LANE_2_RESUME_MASK 0x00040000L +#define PB0_PIF_SC_CTL__SC_LANE_2_RESUME__SHIFT 0x00000012 +#define PB0_PIF_SC_CTL__SC_LANE_3_RESUME_MASK 0x00080000L +#define PB0_PIF_SC_CTL__SC_LANE_3_RESUME__SHIFT 0x00000013 +#define PB0_PIF_SC_CTL__SC_LANE_4_RESUME_MASK 0x00100000L +#define PB0_PIF_SC_CTL__SC_LANE_4_RESUME__SHIFT 0x00000014 +#define PB0_PIF_SC_CTL__SC_LANE_5_RESUME_MASK 0x00200000L +#define PB0_PIF_SC_CTL__SC_LANE_5_RESUME__SHIFT 0x00000015 +#define PB0_PIF_SC_CTL__SC_LANE_6_RESUME_MASK 0x00400000L +#define PB0_PIF_SC_CTL__SC_LANE_6_RESUME__SHIFT 0x00000016 +#define PB0_PIF_SC_CTL__SC_LANE_7_RESUME_MASK 0x00800000L +#define PB0_PIF_SC_CTL__SC_LANE_7_RESUME__SHIFT 0x00000017 +#define PB0_PIF_SC_CTL__SC_LANE_8_RESUME_MASK 0x01000000L +#define PB0_PIF_SC_CTL__SC_LANE_8_RESUME__SHIFT 0x00000018 +#define PB0_PIF_SC_CTL__SC_LANE_9_RESUME_MASK 0x02000000L +#define PB0_PIF_SC_CTL__SC_LANE_9_RESUME__SHIFT 0x00000019 +#define PB0_PIF_SC_CTL__SC_PHASE_1_MASK 0x00000100L +#define PB0_PIF_SC_CTL__SC_PHASE_1__SHIFT 0x00000008 +#define PB0_PIF_SC_CTL__SC_PHASE_2_MASK 0x00000200L +#define PB0_PIF_SC_CTL__SC_PHASE_2__SHIFT 0x00000009 +#define PB0_PIF_SC_CTL__SC_PHASE_3_MASK 0x00000400L +#define PB0_PIF_SC_CTL__SC_PHASE_3__SHIFT 0x0000000a +#define PB0_PIF_SC_CTL__SC_PHASE_4_MASK 0x00000800L +#define PB0_PIF_SC_CTL__SC_PHASE_4__SHIFT 0x0000000b +#define PB0_PIF_SC_CTL__SC_PHASE_5_MASK 0x00001000L +#define PB0_PIF_SC_CTL__SC_PHASE_5__SHIFT 0x0000000c +#define PB0_PIF_SC_CTL__SC_PHASE_6_MASK 0x00002000L +#define PB0_PIF_SC_CTL__SC_PHASE_6__SHIFT 0x0000000d +#define PB0_PIF_SC_CTL__SC_PHASE_7_MASK 0x00004000L +#define PB0_PIF_SC_CTL__SC_PHASE_7__SHIFT 0x0000000e +#define PB0_PIF_SC_CTL__SC_PHASE_8_MASK 0x00008000L +#define PB0_PIF_SC_CTL__SC_PHASE_8__SHIFT 0x0000000f +#define PB0_PIF_SC_CTL__SC_RXDETECT_MASK 0x00000002L +#define PB0_PIF_SC_CTL__SC_RXDETECT__SHIFT 0x00000001 +#define PB0_PIF_SC_CTL__SC_SPEED_CHANGE_MASK 0x00000040L +#define PB0_PIF_SC_CTL__SC_SPEED_CHANGE__SHIFT 0x00000006 +#define PB0_PIF_SCRATCH__PIF_SCRATCH_MASK 0xffffffffL +#define PB0_PIF_SCRATCH__PIF_SCRATCH__SHIFT 0x00000000 +#define PB0_PIF_SEQ_STATUS_0__SEQ_CALIBRATION_0_MASK 0x00000001L +#define PB0_PIF_SEQ_STATUS_0__SEQ_CALIBRATION_0__SHIFT 0x00000000 +#define PB0_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0_0_MASK 0x00000020L +#define PB0_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0_0__SHIFT 0x00000005 +#define PB0_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0S_0_MASK 0x00000010L +#define PB0_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0S_0__SHIFT 0x00000004 +#define PB0_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0_0_MASK 0x00000008L +#define PB0_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0_0__SHIFT 0x00000003 +#define PB0_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0S_0_MASK 0x00000004L +#define PB0_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0S_0__SHIFT 0x00000002 +#define PB0_PIF_SEQ_STATUS_0__SEQ_PHASE_0_MASK 0x00000700L +#define PB0_PIF_SEQ_STATUS_0__SEQ_PHASE_0__SHIFT 0x00000008 +#define PB0_PIF_SEQ_STATUS_0__SEQ_RXDETECT_0_MASK 0x00000002L +#define PB0_PIF_SEQ_STATUS_0__SEQ_RXDETECT_0__SHIFT 0x00000001 +#define PB0_PIF_SEQ_STATUS_0__SEQ_SPEED_CHANGE_0_MASK 0x00000040L +#define PB0_PIF_SEQ_STATUS_0__SEQ_SPEED_CHANGE_0__SHIFT 0x00000006 +#define PB0_PIF_SEQ_STATUS_10__SEQ_CALIBRATION_10_MASK 0x00000001L +#define PB0_PIF_SEQ_STATUS_10__SEQ_CALIBRATION_10__SHIFT 0x00000000 +#define PB0_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0_10_MASK 0x00000020L +#define PB0_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0_10__SHIFT 0x00000005 +#define PB0_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0S_10_MASK 0x00000010L +#define PB0_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0S_10__SHIFT 0x00000004 +#define PB0_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0_10_MASK 0x00000008L +#define PB0_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0_10__SHIFT 0x00000003 +#define PB0_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0S_10_MASK 0x00000004L +#define PB0_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0S_10__SHIFT 0x00000002 +#define PB0_PIF_SEQ_STATUS_10__SEQ_PHASE_10_MASK 0x00000700L +#define PB0_PIF_SEQ_STATUS_10__SEQ_PHASE_10__SHIFT 0x00000008 +#define PB0_PIF_SEQ_STATUS_10__SEQ_RXDETECT_10_MASK 0x00000002L +#define PB0_PIF_SEQ_STATUS_10__SEQ_RXDETECT_10__SHIFT 0x00000001 +#define PB0_PIF_SEQ_STATUS_10__SEQ_SPEED_CHANGE_10_MASK 0x00000040L +#define PB0_PIF_SEQ_STATUS_10__SEQ_SPEED_CHANGE_10__SHIFT 0x00000006 +#define PB0_PIF_SEQ_STATUS_11__SEQ_CALIBRATION_11_MASK 0x00000001L +#define PB0_PIF_SEQ_STATUS_11__SEQ_CALIBRATION_11__SHIFT 0x00000000 +#define PB0_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0_11_MASK 0x00000020L +#define PB0_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0_11__SHIFT 0x00000005 +#define PB0_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0S_11_MASK 0x00000010L +#define PB0_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0S_11__SHIFT 0x00000004 +#define PB0_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0_11_MASK 0x00000008L +#define PB0_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0_11__SHIFT 0x00000003 +#define PB0_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0S_11_MASK 0x00000004L +#define PB0_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0S_11__SHIFT 0x00000002 +#define PB0_PIF_SEQ_STATUS_11__SEQ_PHASE_11_MASK 0x00000700L +#define PB0_PIF_SEQ_STATUS_11__SEQ_PHASE_11__SHIFT 0x00000008 +#define PB0_PIF_SEQ_STATUS_11__SEQ_RXDETECT_11_MASK 0x00000002L +#define PB0_PIF_SEQ_STATUS_11__SEQ_RXDETECT_11__SHIFT 0x00000001 +#define PB0_PIF_SEQ_STATUS_11__SEQ_SPEED_CHANGE_11_MASK 0x00000040L +#define PB0_PIF_SEQ_STATUS_11__SEQ_SPEED_CHANGE_11__SHIFT 0x00000006 +#define PB0_PIF_SEQ_STATUS_12__SEQ_CALIBRATION_12_MASK 0x00000001L +#define PB0_PIF_SEQ_STATUS_12__SEQ_CALIBRATION_12__SHIFT 0x00000000 +#define PB0_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0_12_MASK 0x00000020L +#define PB0_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0_12__SHIFT 0x00000005 +#define PB0_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0S_12_MASK 0x00000010L +#define PB0_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0S_12__SHIFT 0x00000004 +#define PB0_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0_12_MASK 0x00000008L +#define PB0_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0_12__SHIFT 0x00000003 +#define PB0_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0S_12_MASK 0x00000004L +#define PB0_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0S_12__SHIFT 0x00000002 +#define PB0_PIF_SEQ_STATUS_12__SEQ_PHASE_12_MASK 0x00000700L +#define PB0_PIF_SEQ_STATUS_12__SEQ_PHASE_12__SHIFT 0x00000008 +#define PB0_PIF_SEQ_STATUS_12__SEQ_RXDETECT_12_MASK 0x00000002L +#define PB0_PIF_SEQ_STATUS_12__SEQ_RXDETECT_12__SHIFT 0x00000001 +#define PB0_PIF_SEQ_STATUS_12__SEQ_SPEED_CHANGE_12_MASK 0x00000040L +#define PB0_PIF_SEQ_STATUS_12__SEQ_SPEED_CHANGE_12__SHIFT 0x00000006 +#define PB0_PIF_SEQ_STATUS_13__SEQ_CALIBRATION_13_MASK 0x00000001L +#define PB0_PIF_SEQ_STATUS_13__SEQ_CALIBRATION_13__SHIFT 0x00000000 +#define PB0_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0_13_MASK 0x00000020L +#define PB0_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0_13__SHIFT 0x00000005 +#define PB0_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0S_13_MASK 0x00000010L +#define PB0_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0S_13__SHIFT 0x00000004 +#define PB0_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0_13_MASK 0x00000008L +#define PB0_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0_13__SHIFT 0x00000003 +#define PB0_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0S_13_MASK 0x00000004L +#define PB0_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0S_13__SHIFT 0x00000002 +#define PB0_PIF_SEQ_STATUS_13__SEQ_PHASE_13_MASK 0x00000700L +#define PB0_PIF_SEQ_STATUS_13__SEQ_PHASE_13__SHIFT 0x00000008 +#define PB0_PIF_SEQ_STATUS_13__SEQ_RXDETECT_13_MASK 0x00000002L +#define PB0_PIF_SEQ_STATUS_13__SEQ_RXDETECT_13__SHIFT 0x00000001 +#define PB0_PIF_SEQ_STATUS_13__SEQ_SPEED_CHANGE_13_MASK 0x00000040L +#define PB0_PIF_SEQ_STATUS_13__SEQ_SPEED_CHANGE_13__SHIFT 0x00000006 +#define PB0_PIF_SEQ_STATUS_14__SEQ_CALIBRATION_14_MASK 0x00000001L +#define PB0_PIF_SEQ_STATUS_14__SEQ_CALIBRATION_14__SHIFT 0x00000000 +#define PB0_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0_14_MASK 0x00000020L +#define PB0_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0_14__SHIFT 0x00000005 +#define PB0_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0S_14_MASK 0x00000010L +#define PB0_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0S_14__SHIFT 0x00000004 +#define PB0_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0_14_MASK 0x00000008L +#define PB0_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0_14__SHIFT 0x00000003 +#define PB0_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0S_14_MASK 0x00000004L +#define PB0_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0S_14__SHIFT 0x00000002 +#define PB0_PIF_SEQ_STATUS_14__SEQ_PHASE_14_MASK 0x00000700L +#define PB0_PIF_SEQ_STATUS_14__SEQ_PHASE_14__SHIFT 0x00000008 +#define PB0_PIF_SEQ_STATUS_14__SEQ_RXDETECT_14_MASK 0x00000002L +#define PB0_PIF_SEQ_STATUS_14__SEQ_RXDETECT_14__SHIFT 0x00000001 +#define PB0_PIF_SEQ_STATUS_14__SEQ_SPEED_CHANGE_14_MASK 0x00000040L +#define PB0_PIF_SEQ_STATUS_14__SEQ_SPEED_CHANGE_14__SHIFT 0x00000006 +#define PB0_PIF_SEQ_STATUS_15__SEQ_CALIBRATION_15_MASK 0x00000001L +#define PB0_PIF_SEQ_STATUS_15__SEQ_CALIBRATION_15__SHIFT 0x00000000 +#define PB0_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0_15_MASK 0x00000020L +#define PB0_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0_15__SHIFT 0x00000005 +#define PB0_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0S_15_MASK 0x00000010L +#define PB0_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0S_15__SHIFT 0x00000004 +#define PB0_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0_15_MASK 0x00000008L +#define PB0_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0_15__SHIFT 0x00000003 +#define PB0_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0S_15_MASK 0x00000004L +#define PB0_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0S_15__SHIFT 0x00000002 +#define PB0_PIF_SEQ_STATUS_15__SEQ_PHASE_15_MASK 0x00000700L +#define PB0_PIF_SEQ_STATUS_15__SEQ_PHASE_15__SHIFT 0x00000008 +#define PB0_PIF_SEQ_STATUS_15__SEQ_RXDETECT_15_MASK 0x00000002L +#define PB0_PIF_SEQ_STATUS_15__SEQ_RXDETECT_15__SHIFT 0x00000001 +#define PB0_PIF_SEQ_STATUS_15__SEQ_SPEED_CHANGE_15_MASK 0x00000040L +#define PB0_PIF_SEQ_STATUS_15__SEQ_SPEED_CHANGE_15__SHIFT 0x00000006 +#define PB0_PIF_SEQ_STATUS_1__SEQ_CALIBRATION_1_MASK 0x00000001L +#define PB0_PIF_SEQ_STATUS_1__SEQ_CALIBRATION_1__SHIFT 0x00000000 +#define PB0_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0_1_MASK 0x00000020L +#define PB0_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0_1__SHIFT 0x00000005 +#define PB0_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0S_1_MASK 0x00000010L +#define PB0_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0S_1__SHIFT 0x00000004 +#define PB0_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0_1_MASK 0x00000008L +#define PB0_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0_1__SHIFT 0x00000003 +#define PB0_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0S_1_MASK 0x00000004L +#define PB0_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0S_1__SHIFT 0x00000002 +#define PB0_PIF_SEQ_STATUS_1__SEQ_PHASE_1_MASK 0x00000700L +#define PB0_PIF_SEQ_STATUS_1__SEQ_PHASE_1__SHIFT 0x00000008 +#define PB0_PIF_SEQ_STATUS_1__SEQ_RXDETECT_1_MASK 0x00000002L +#define PB0_PIF_SEQ_STATUS_1__SEQ_RXDETECT_1__SHIFT 0x00000001 +#define PB0_PIF_SEQ_STATUS_1__SEQ_SPEED_CHANGE_1_MASK 0x00000040L +#define PB0_PIF_SEQ_STATUS_1__SEQ_SPEED_CHANGE_1__SHIFT 0x00000006 +#define PB0_PIF_SEQ_STATUS_2__SEQ_CALIBRATION_2_MASK 0x00000001L +#define PB0_PIF_SEQ_STATUS_2__SEQ_CALIBRATION_2__SHIFT 0x00000000 +#define PB0_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0_2_MASK 0x00000020L +#define PB0_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0_2__SHIFT 0x00000005 +#define PB0_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0S_2_MASK 0x00000010L +#define PB0_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0S_2__SHIFT 0x00000004 +#define PB0_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0_2_MASK 0x00000008L +#define PB0_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0_2__SHIFT 0x00000003 +#define PB0_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0S_2_MASK 0x00000004L +#define PB0_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0S_2__SHIFT 0x00000002 +#define PB0_PIF_SEQ_STATUS_2__SEQ_PHASE_2_MASK 0x00000700L +#define PB0_PIF_SEQ_STATUS_2__SEQ_PHASE_2__SHIFT 0x00000008 +#define PB0_PIF_SEQ_STATUS_2__SEQ_RXDETECT_2_MASK 0x00000002L +#define PB0_PIF_SEQ_STATUS_2__SEQ_RXDETECT_2__SHIFT 0x00000001 +#define PB0_PIF_SEQ_STATUS_2__SEQ_SPEED_CHANGE_2_MASK 0x00000040L +#define PB0_PIF_SEQ_STATUS_2__SEQ_SPEED_CHANGE_2__SHIFT 0x00000006 +#define PB0_PIF_SEQ_STATUS_3__SEQ_CALIBRATION_3_MASK 0x00000001L +#define PB0_PIF_SEQ_STATUS_3__SEQ_CALIBRATION_3__SHIFT 0x00000000 +#define PB0_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0_3_MASK 0x00000020L +#define PB0_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0_3__SHIFT 0x00000005 +#define PB0_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0S_3_MASK 0x00000010L +#define PB0_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0S_3__SHIFT 0x00000004 +#define PB0_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0_3_MASK 0x00000008L +#define PB0_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0_3__SHIFT 0x00000003 +#define PB0_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0S_3_MASK 0x00000004L +#define PB0_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0S_3__SHIFT 0x00000002 +#define PB0_PIF_SEQ_STATUS_3__SEQ_PHASE_3_MASK 0x00000700L +#define PB0_PIF_SEQ_STATUS_3__SEQ_PHASE_3__SHIFT 0x00000008 +#define PB0_PIF_SEQ_STATUS_3__SEQ_RXDETECT_3_MASK 0x00000002L +#define PB0_PIF_SEQ_STATUS_3__SEQ_RXDETECT_3__SHIFT 0x00000001 +#define PB0_PIF_SEQ_STATUS_3__SEQ_SPEED_CHANGE_3_MASK 0x00000040L +#define PB0_PIF_SEQ_STATUS_3__SEQ_SPEED_CHANGE_3__SHIFT 0x00000006 +#define PB0_PIF_SEQ_STATUS_4__SEQ_CALIBRATION_4_MASK 0x00000001L +#define PB0_PIF_SEQ_STATUS_4__SEQ_CALIBRATION_4__SHIFT 0x00000000 +#define PB0_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0_4_MASK 0x00000020L +#define PB0_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0_4__SHIFT 0x00000005 +#define PB0_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0S_4_MASK 0x00000010L +#define PB0_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0S_4__SHIFT 0x00000004 +#define PB0_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0_4_MASK 0x00000008L +#define PB0_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0_4__SHIFT 0x00000003 +#define PB0_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0S_4_MASK 0x00000004L +#define PB0_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0S_4__SHIFT 0x00000002 +#define PB0_PIF_SEQ_STATUS_4__SEQ_PHASE_4_MASK 0x00000700L +#define PB0_PIF_SEQ_STATUS_4__SEQ_PHASE_4__SHIFT 0x00000008 +#define PB0_PIF_SEQ_STATUS_4__SEQ_RXDETECT_4_MASK 0x00000002L +#define PB0_PIF_SEQ_STATUS_4__SEQ_RXDETECT_4__SHIFT 0x00000001 +#define PB0_PIF_SEQ_STATUS_4__SEQ_SPEED_CHANGE_4_MASK 0x00000040L +#define PB0_PIF_SEQ_STATUS_4__SEQ_SPEED_CHANGE_4__SHIFT 0x00000006 +#define PB0_PIF_SEQ_STATUS_5__SEQ_CALIBRATION_5_MASK 0x00000001L +#define PB0_PIF_SEQ_STATUS_5__SEQ_CALIBRATION_5__SHIFT 0x00000000 +#define PB0_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0_5_MASK 0x00000020L +#define PB0_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0_5__SHIFT 0x00000005 +#define PB0_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0S_5_MASK 0x00000010L +#define PB0_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0S_5__SHIFT 0x00000004 +#define PB0_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0_5_MASK 0x00000008L +#define PB0_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0_5__SHIFT 0x00000003 +#define PB0_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0S_5_MASK 0x00000004L +#define PB0_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0S_5__SHIFT 0x00000002 +#define PB0_PIF_SEQ_STATUS_5__SEQ_PHASE_5_MASK 0x00000700L +#define PB0_PIF_SEQ_STATUS_5__SEQ_PHASE_5__SHIFT 0x00000008 +#define PB0_PIF_SEQ_STATUS_5__SEQ_RXDETECT_5_MASK 0x00000002L +#define PB0_PIF_SEQ_STATUS_5__SEQ_RXDETECT_5__SHIFT 0x00000001 +#define PB0_PIF_SEQ_STATUS_5__SEQ_SPEED_CHANGE_5_MASK 0x00000040L +#define PB0_PIF_SEQ_STATUS_5__SEQ_SPEED_CHANGE_5__SHIFT 0x00000006 +#define PB0_PIF_SEQ_STATUS_6__SEQ_CALIBRATION_6_MASK 0x00000001L +#define PB0_PIF_SEQ_STATUS_6__SEQ_CALIBRATION_6__SHIFT 0x00000000 +#define PB0_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0_6_MASK 0x00000020L +#define PB0_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0_6__SHIFT 0x00000005 +#define PB0_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0S_6_MASK 0x00000010L +#define PB0_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0S_6__SHIFT 0x00000004 +#define PB0_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0_6_MASK 0x00000008L +#define PB0_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0_6__SHIFT 0x00000003 +#define PB0_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0S_6_MASK 0x00000004L +#define PB0_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0S_6__SHIFT 0x00000002 +#define PB0_PIF_SEQ_STATUS_6__SEQ_PHASE_6_MASK 0x00000700L +#define PB0_PIF_SEQ_STATUS_6__SEQ_PHASE_6__SHIFT 0x00000008 +#define PB0_PIF_SEQ_STATUS_6__SEQ_RXDETECT_6_MASK 0x00000002L +#define PB0_PIF_SEQ_STATUS_6__SEQ_RXDETECT_6__SHIFT 0x00000001 +#define PB0_PIF_SEQ_STATUS_6__SEQ_SPEED_CHANGE_6_MASK 0x00000040L +#define PB0_PIF_SEQ_STATUS_6__SEQ_SPEED_CHANGE_6__SHIFT 0x00000006 +#define PB0_PIF_SEQ_STATUS_7__SEQ_CALIBRATION_7_MASK 0x00000001L +#define PB0_PIF_SEQ_STATUS_7__SEQ_CALIBRATION_7__SHIFT 0x00000000 +#define PB0_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0_7_MASK 0x00000020L +#define PB0_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0_7__SHIFT 0x00000005 +#define PB0_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0S_7_MASK 0x00000010L +#define PB0_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0S_7__SHIFT 0x00000004 +#define PB0_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0_7_MASK 0x00000008L +#define PB0_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0_7__SHIFT 0x00000003 +#define PB0_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0S_7_MASK 0x00000004L +#define PB0_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0S_7__SHIFT 0x00000002 +#define PB0_PIF_SEQ_STATUS_7__SEQ_PHASE_7_MASK 0x00000700L +#define PB0_PIF_SEQ_STATUS_7__SEQ_PHASE_7__SHIFT 0x00000008 +#define PB0_PIF_SEQ_STATUS_7__SEQ_RXDETECT_7_MASK 0x00000002L +#define PB0_PIF_SEQ_STATUS_7__SEQ_RXDETECT_7__SHIFT 0x00000001 +#define PB0_PIF_SEQ_STATUS_7__SEQ_SPEED_CHANGE_7_MASK 0x00000040L +#define PB0_PIF_SEQ_STATUS_7__SEQ_SPEED_CHANGE_7__SHIFT 0x00000006 +#define PB0_PIF_SEQ_STATUS_8__SEQ_CALIBRATION_8_MASK 0x00000001L +#define PB0_PIF_SEQ_STATUS_8__SEQ_CALIBRATION_8__SHIFT 0x00000000 +#define PB0_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0_8_MASK 0x00000020L +#define PB0_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0_8__SHIFT 0x00000005 +#define PB0_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0S_8_MASK 0x00000010L +#define PB0_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0S_8__SHIFT 0x00000004 +#define PB0_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0_8_MASK 0x00000008L +#define PB0_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0_8__SHIFT 0x00000003 +#define PB0_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0S_8_MASK 0x00000004L +#define PB0_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0S_8__SHIFT 0x00000002 +#define PB0_PIF_SEQ_STATUS_8__SEQ_PHASE_8_MASK 0x00000700L +#define PB0_PIF_SEQ_STATUS_8__SEQ_PHASE_8__SHIFT 0x00000008 +#define PB0_PIF_SEQ_STATUS_8__SEQ_RXDETECT_8_MASK 0x00000002L +#define PB0_PIF_SEQ_STATUS_8__SEQ_RXDETECT_8__SHIFT 0x00000001 +#define PB0_PIF_SEQ_STATUS_8__SEQ_SPEED_CHANGE_8_MASK 0x00000040L +#define PB0_PIF_SEQ_STATUS_8__SEQ_SPEED_CHANGE_8__SHIFT 0x00000006 +#define PB0_PIF_SEQ_STATUS_9__SEQ_CALIBRATION_9_MASK 0x00000001L +#define PB0_PIF_SEQ_STATUS_9__SEQ_CALIBRATION_9__SHIFT 0x00000000 +#define PB0_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0_9_MASK 0x00000020L +#define PB0_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0_9__SHIFT 0x00000005 +#define PB0_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0S_9_MASK 0x00000010L +#define PB0_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0S_9__SHIFT 0x00000004 +#define PB0_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0_9_MASK 0x00000008L +#define PB0_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0_9__SHIFT 0x00000003 +#define PB0_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0S_9_MASK 0x00000004L +#define PB0_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0S_9__SHIFT 0x00000002 +#define PB0_PIF_SEQ_STATUS_9__SEQ_PHASE_9_MASK 0x00000700L +#define PB0_PIF_SEQ_STATUS_9__SEQ_PHASE_9__SHIFT 0x00000008 +#define PB0_PIF_SEQ_STATUS_9__SEQ_RXDETECT_9_MASK 0x00000002L +#define PB0_PIF_SEQ_STATUS_9__SEQ_RXDETECT_9__SHIFT 0x00000001 +#define PB0_PIF_SEQ_STATUS_9__SEQ_SPEED_CHANGE_9_MASK 0x00000040L +#define PB0_PIF_SEQ_STATUS_9__SEQ_SPEED_CHANGE_9__SHIFT 0x00000006 +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_0_MASK 0x00000001L +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_0__SHIFT 0x00000000 +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_10_MASK 0x00000400L +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_10__SHIFT 0x0000000a +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_11_MASK 0x00000800L +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_11__SHIFT 0x0000000b +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_12_MASK 0x00001000L +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_12__SHIFT 0x0000000c +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_13_MASK 0x00002000L +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_13__SHIFT 0x0000000d +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_14_MASK 0x00004000L +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_14__SHIFT 0x0000000e +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_15_MASK 0x00008000L +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_15__SHIFT 0x0000000f +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_1_MASK 0x00000002L +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_1__SHIFT 0x00000001 +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_2_MASK 0x00000004L +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_2__SHIFT 0x00000002 +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_3_MASK 0x00000008L +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_3__SHIFT 0x00000003 +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_4_MASK 0x00000010L +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_4__SHIFT 0x00000004 +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_5_MASK 0x00000020L +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_5__SHIFT 0x00000005 +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_6_MASK 0x00000040L +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_6__SHIFT 0x00000006 +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_7_MASK 0x00000080L +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_7__SHIFT 0x00000007 +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_8_MASK 0x00000100L +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_8__SHIFT 0x00000008 +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_9_MASK 0x00000200L +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_9__SHIFT 0x00000009 +#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0_MASK 0x00000003L +#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0__SHIFT 0x00000000 +#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0_MASK 0x00000004L +#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0__SHIFT 0x00000002 +#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0_MASK 0x00000008L +#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0__SHIFT 0x00000003 +#define PB0_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0_MASK 0x00000010L +#define PB0_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0__SHIFT 0x00000004 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0_MASK 0x00000008L +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0__SHIFT 0x00000003 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0_MASK 0x00000007L +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0__SHIFT 0x00000000 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0_MASK 0x00000080L +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0__SHIFT 0x00000007 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0_MASK 0x00000070L +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x00000004 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0_MASK 0x00000200L +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0__SHIFT 0x00000009 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0_MASK 0x00000100L +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0__SHIFT 0x00000008 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0_MASK 0x00040000L +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0__SHIFT 0x00000012 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0_MASK 0x0003fc00L +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0__SHIFT 0x0000000a +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0_MASK 0x10000000L +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0__SHIFT 0x0000001c +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0_MASK 0x0ff80000L +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0__SHIFT 0x00000013 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0_MASK 0x80000000L +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0__SHIFT 0x0000001f +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0_MASK 0x60000000L +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0__SHIFT 0x0000001d +#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0_MASK 0x00000008L +#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0__SHIFT 0x00000003 +#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0_MASK 0x00000007L +#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x00000000 +#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0_MASK 0x00040000L +#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0__SHIFT 0x00000012 +#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0_MASK 0x0003c000L +#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0__SHIFT 0x0000000e +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x00000020L +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0x00000005 +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x00000010L +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x00000004 +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x00000080L +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0x00000007 +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x00000040L +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0x00000006 +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0_MASK 0x00000200L +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0__SHIFT 0x00000009 +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0_MASK 0x00000100L +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0__SHIFT 0x00000008 +#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_FREQMODE_MASK 0x00000300L +#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_FREQMODE__SHIFT 0x00000008 +#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L +#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001 +#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L +#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000 +#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR_MASK 0x00000070L +#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR__SHIFT 0x00000004 +#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_FREQMODE_MASK 0x00000300L +#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_FREQMODE__SHIFT 0x00000008 +#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L +#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001 +#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L +#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000 +#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR_MASK 0x00000070L +#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR__SHIFT 0x00000004 +#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_FREQMODE_MASK 0x00000300L +#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_FREQMODE__SHIFT 0x00000008 +#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L +#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001 +#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L +#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000 +#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR_MASK 0x00000070L +#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR__SHIFT 0x00000004 +#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_FREQMODE_MASK 0x00000300L +#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_FREQMODE__SHIFT 0x00000008 +#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L +#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001 +#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L +#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000 +#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR_MASK 0x00000070L +#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR__SHIFT 0x00000004 +#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0_MASK 0x00000003L +#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0__SHIFT 0x00000000 +#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0_MASK 0x00000004L +#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0__SHIFT 0x00000002 +#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0_MASK 0x000007f0L +#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0__SHIFT 0x00000004 +#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0_MASK 0x00000008L +#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0__SHIFT 0x00000003 +#define PB0_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0_MASK 0x00000800L +#define PB0_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0__SHIFT 0x0000000b +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0_MASK 0x00000100L +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0__SHIFT 0x00000008 +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0_MASK 0x000000ffL +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0__SHIFT 0x00000000 +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0_MASK 0x00001000L +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0__SHIFT 0x0000000c +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0_MASK 0x00000e00L +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x00000009 +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0_MASK 0x00004000L +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0__SHIFT 0x0000000e +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0_MASK 0x00002000L +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0__SHIFT 0x0000000d +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0_MASK 0x10000000L +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0__SHIFT 0x0000001c +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0_MASK 0x0fff8000L +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0__SHIFT 0x0000000f +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0_MASK 0x80000000L +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0__SHIFT 0x0000001f +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0_MASK 0x40000000L +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0__SHIFT 0x0000001e +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0_MASK 0x00400000L +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0__SHIFT 0x00000016 +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0_MASK 0x00380000L +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x00000013 +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0_MASK 0x00000020L +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0__SHIFT 0x00000005 +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0_MASK 0x0000001fL +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0__SHIFT 0x00000000 +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0_MASK 0x00000100L +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0__SHIFT 0x00000008 +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0_MASK 0x000000c0L +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0__SHIFT 0x00000006 +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x00000400L +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0x0000000a +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x00000200L +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x00000009 +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x00001000L +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0x0000000c +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x00000800L +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0x0000000b +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0_MASK 0x00004000L +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0__SHIFT 0x0000000e +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0_MASK 0x00002000L +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0__SHIFT 0x0000000d +#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_FREQMODE_MASK 0x00000300L +#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_FREQMODE__SHIFT 0x00000008 +#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L +#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001 +#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L +#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000 +#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR_MASK 0x00000070L +#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR__SHIFT 0x00000004 +#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_FREQMODE_MASK 0x00000300L +#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_FREQMODE__SHIFT 0x00000008 +#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L +#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001 +#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L +#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000 +#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR_MASK 0x00000070L +#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR__SHIFT 0x00000004 +#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_FREQMODE_MASK 0x00000300L +#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_FREQMODE__SHIFT 0x00000008 +#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L +#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001 +#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L +#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000 +#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR_MASK 0x00000070L +#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR__SHIFT 0x00000004 +#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_FREQMODE_MASK 0x00000300L +#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_FREQMODE__SHIFT 0x00000008 +#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L +#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001 +#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L +#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000 +#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR_MASK 0x00000070L +#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR__SHIFT 0x00000004 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x00000200L +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x00000009 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x00000400L +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0x0000000a +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x00000800L +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0x0000000b +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN_MASK 0x00100000L +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN__SHIFT 0x00000014 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN_MASK 0x00200000L +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN__SHIFT 0x00000015 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x00001000L +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0x0000000c +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x00002000L +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0x0000000d +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x00004000L +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0x0000000e +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN_MASK 0x00400000L +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN__SHIFT 0x00000016 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN_MASK 0x00800000L +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN__SHIFT 0x00000017 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2_MASK 0x00000100L +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2__SHIFT 0x00000008 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x00000002L +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x00000001 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x00000004L +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0x00000002 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x00000008L +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0x00000003 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN_MASK 0x00010000L +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN__SHIFT 0x00000010 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN_MASK 0x00020000L +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN__SHIFT 0x00000011 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x00000010L +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0x00000004 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x00000020L +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0x00000005 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x00000040L +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0x00000006 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN_MASK 0x00040000L +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN__SHIFT 0x00000012 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN_MASK 0x00080000L +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN__SHIFT 0x00000013 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2_MASK 0x00000080L +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2__SHIFT 0x00000007 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC_MASK 0x00000001L +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC__SHIFT 0x00000000 +#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1_MASK 0x000003ffL +#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1__SHIFT 0x00000000 +#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2_MASK 0x000ffc00L +#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2__SHIFT 0x0000000a +#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3_MASK 0x3ff00000L +#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3__SHIFT 0x00000014 +#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_RST_MODE_MASK 0xc0000000L +#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_RST_MODE__SHIFT 0x0000001e +#define PB0_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN_MASK 0xc0000000L +#define PB0_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN__SHIFT 0x0000001e +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1_MASK 0x0000000fL +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1__SHIFT 0x00000000 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2_MASK 0x000000f0L +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2__SHIFT 0x00000004 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3_MASK 0x00000f00L +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3__SHIFT 0x00000008 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1_MASK 0x0000f000L +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1__SHIFT 0x0000000c +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2_MASK 0x000f0000L +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2__SHIFT 0x00000010 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3_MASK 0x00f00000L +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3__SHIFT 0x00000014 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1_MASK 0x01000000L +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1__SHIFT 0x00000018 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2_MASK 0x02000000L +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2__SHIFT 0x00000019 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3_MASK 0x04000000L +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3__SHIFT 0x0000001a +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1_MASK 0x08000000L +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1__SHIFT 0x0000001b +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2_MASK 0x10000000L +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2__SHIFT 0x0000001c +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3_MASK 0x20000000L +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3__SHIFT 0x0000001d +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1_MASK 0x0000f000L +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1__SHIFT 0x0000000c +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2_MASK 0x000f0000L +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2__SHIFT 0x00000010 +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3_MASK 0x00f00000L +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3__SHIFT 0x00000014 +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1_MASK 0x03000000L +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1__SHIFT 0x00000018 +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2_MASK 0x0c000000L +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2__SHIFT 0x0000001a +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3_MASK 0x30000000L +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3__SHIFT 0x0000001c +#define PB0_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD_MASK 0xc0000000L +#define PB0_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD__SHIFT 0x0000001e +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1_MASK 0x00000001L +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1__SHIFT 0x00000000 +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2_MASK 0x00000002L +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2__SHIFT 0x00000001 +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3_MASK 0x00000004L +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3__SHIFT 0x00000002 +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1_MASK 0x00f00000L +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1__SHIFT 0x00000014 +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2_MASK 0x0f000000L +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2__SHIFT 0x00000018 +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3_MASK 0xf0000000L +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3__SHIFT 0x0000001c +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1_MASK 0x00000007L +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1__SHIFT 0x00000000 +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2_MASK 0x00000038L +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2__SHIFT 0x00000003 +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3_MASK 0x000001c0L +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3__SHIFT 0x00000006 +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1_MASK 0x00f00000L +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1__SHIFT 0x00000014 +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2_MASK 0x0f000000L +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2__SHIFT 0x00000018 +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3_MASK 0xf0000000L +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3__SHIFT 0x0000001c +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1_MASK 0x00000e00L +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1__SHIFT 0x00000009 +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2_MASK 0x00007000L +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2__SHIFT 0x0000000c +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3_MASK 0x00038000L +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3__SHIFT 0x0000000f +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1_MASK 0x0000001fL +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1__SHIFT 0x00000000 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2_MASK 0x000003e0L +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2__SHIFT 0x00000005 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3_MASK 0x00007c00L +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3__SHIFT 0x0000000a +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1_MASK 0x00008000L +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1__SHIFT 0x0000000f +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2_MASK 0x00010000L +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2__SHIFT 0x00000010 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3_MASK 0x00020000L +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3__SHIFT 0x00000011 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1_MASK 0x00040000L +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1__SHIFT 0x00000012 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2_MASK 0x00080000L +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2__SHIFT 0x00000013 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3_MASK 0x00100000L +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3__SHIFT 0x00000014 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1_MASK 0x08000000L +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1__SHIFT 0x0000001b +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2_MASK 0x10000000L +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2__SHIFT 0x0000001c +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3_MASK 0x20000000L +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3__SHIFT 0x0000001d +#define PB0_RX_GLB_CTRL_REG5__RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0_MASK 0x40000000L +#define PB0_RX_GLB_CTRL_REG5__RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0__SHIFT 0x0000001e +#define PB0_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2_MASK 0x08000000L +#define PB0_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2__SHIFT 0x0000001b +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1_MASK 0x0000000fL +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1__SHIFT 0x00000000 +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2_MASK 0x000000f0L +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2__SHIFT 0x00000004 +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3_MASK 0x00000f00L +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3__SHIFT 0x00000008 +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1_MASK 0x0000f000L +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1__SHIFT 0x0000000c +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2_MASK 0x000f0000L +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2__SHIFT 0x00000010 +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3_MASK 0x00f00000L +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3__SHIFT 0x00000014 +#define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x01000000L +#define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0x00000018 +#define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2_MASK 0x04000000L +#define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2__SHIFT 0x0000001a +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1_MASK 0x001c0000L +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1__SHIFT 0x00000012 +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2_MASK 0x00e00000L +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2__SHIFT 0x00000015 +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3_MASK 0x07000000L +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3__SHIFT 0x00000018 +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1_MASK 0x08000000L +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1__SHIFT 0x0000001b +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2_MASK 0x10000000L +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2__SHIFT 0x0000001c +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3_MASK 0x20000000L +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3__SHIFT 0x0000001d +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1_MASK 0x0000000fL +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1__SHIFT 0x00000000 +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2_MASK 0x000000f0L +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2__SHIFT 0x00000004 +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3_MASK 0x00000f00L +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3__SHIFT 0x00000008 +#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x00001000L +#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0x0000000c +#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2_MASK 0x00002000L +#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2__SHIFT 0x0000000d +#define PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_LS2_MASK 0x00020000L +#define PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_LS2__SHIFT 0x00000011 +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN_MASK 0x80000000L +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN__SHIFT 0x0000001f +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL_MASK 0x40000000L +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL__SHIFT 0x0000001e +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN_MASK 0x00000002L +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN__SHIFT 0x00000001 +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL_MASK 0x00000001L +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL__SHIFT 0x00000000 +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN_MASK 0x00000008L +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN__SHIFT 0x00000003 +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL_MASK 0x00000004L +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL__SHIFT 0x00000002 +#define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN_MASK 0x20000000L +#define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN__SHIFT 0x0000001d +#define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL_MASK 0x10000000L +#define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL__SHIFT 0x0000001c +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN_MASK 0x00000100L +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x00000008 +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL_MASK 0x000000c0L +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x00000006 +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN_MASK 0x00000400L +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN__SHIFT 0x0000000a +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL_MASK 0x00000200L +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL__SHIFT 0x00000009 +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x00001000L +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0x0000000c +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x00000800L +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0x0000000b +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN_MASK 0x00004000L +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN__SHIFT 0x0000000e +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL_MASK 0x00002000L +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL__SHIFT 0x0000000d +#define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN_MASK 0x00010000L +#define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN__SHIFT 0x00000010 +#define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL_MASK 0x00008000L +#define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL__SHIFT 0x0000000f +#define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN_MASK 0x00040000L +#define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN__SHIFT 0x00000012 +#define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL_MASK 0x00020000L +#define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL__SHIFT 0x00000011 +#define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN_MASK 0x00100000L +#define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN__SHIFT 0x00000014 +#define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL_MASK 0x00080000L +#define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL__SHIFT 0x00000013 +#define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN_MASK 0x00400000L +#define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN__SHIFT 0x00000016 +#define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL_MASK 0x00200000L +#define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL__SHIFT 0x00000015 +#define PB0_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_EN_MASK 0x01000000L +#define PB0_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_EN__SHIFT 0x00000018 +#define PB0_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_VAL_MASK 0x00800000L +#define PB0_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_VAL__SHIFT 0x00000017 +#define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN_MASK 0x00000002L +#define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN__SHIFT 0x00000001 +#define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL_MASK 0x00000001L +#define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL__SHIFT 0x00000000 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3_MASK 0x00000010L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3__SHIFT 0x00000004 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15_MASK 0x00000080L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15__SHIFT 0x00000007 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7_MASK 0x00000020L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7__SHIFT 0x00000005 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11_MASK 0x00000040L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11__SHIFT 0x00000006 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L0T3_MASK 0x00001000L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L0T3__SHIFT 0x0000000c +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L12T15_MASK 0x00008000L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L12T15__SHIFT 0x0000000f +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L4T7_MASK 0x00002000L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L4T7__SHIFT 0x0000000d +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L8T11_MASK 0x00004000L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L8T11__SHIFT 0x0000000e +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L0T3_MASK 0x00010000L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L0T3__SHIFT 0x00000010 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L12T15_MASK 0x00080000L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L12T15__SHIFT 0x00000013 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L4T7_MASK 0x00020000L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L4T7__SHIFT 0x00000011 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L8T11_MASK 0x00040000L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L8T11__SHIFT 0x00000012 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L0T3_MASK 0x00100000L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L0T3__SHIFT 0x00000014 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L12T15_MASK 0x00800000L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L12T15__SHIFT 0x00000017 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L4T7_MASK 0x00200000L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L4T7__SHIFT 0x00000015 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L8T11_MASK 0x00400000L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L8T11__SHIFT 0x00000016 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L0T3_MASK 0x00000100L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L0T3__SHIFT 0x00000008 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L12T15_MASK 0x00000800L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L12T15__SHIFT 0x0000000b +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L4T7_MASK 0x00000200L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L4T7__SHIFT 0x00000009 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L8T11_MASK 0x00000400L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L8T11__SHIFT 0x0000000a +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L0T3_MASK 0x00000001L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L0T3__SHIFT 0x00000000 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L12T15_MASK 0x00000008L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L12T15__SHIFT 0x00000003 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L4T7_MASK 0x00000002L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L4T7__SHIFT 0x00000001 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L8T11_MASK 0x00000004L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L8T11__SHIFT 0x00000002 +#define PB0_RX_LANE0_CTRL_REG0__RX_BACKUP_0_MASK 0x000000ffL +#define PB0_RX_LANE0_CTRL_REG0__RX_BACKUP_0__SHIFT 0x00000000 +#define PB0_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0_MASK 0x00002000L +#define PB0_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0__SHIFT 0x0000000d +#define PB0_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0_MASK 0x00000c00L +#define PB0_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0__SHIFT 0x0000000a +#define PB0_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0_MASK 0x00001000L +#define PB0_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0__SHIFT 0x0000000c +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0_MASK 0x00000008L +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0__SHIFT 0x00000003 +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0_MASK 0x00000080L +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0__SHIFT 0x00000007 +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0_MASK 0x00000100L +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0__SHIFT 0x00000008 +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0_MASK 0x00000200L +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0__SHIFT 0x00000009 +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPRESETHINT_0_MASK 0x00000070L +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPRESETHINT_0__SHIFT 0x00000004 +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0_MASK 0x00000007L +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0__SHIFT 0x00000000 +#define PB0_RX_LANE10_CTRL_REG0__RX_BACKUP_10_MASK 0x000000ffL +#define PB0_RX_LANE10_CTRL_REG0__RX_BACKUP_10__SHIFT 0x00000000 +#define PB0_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10_MASK 0x00002000L +#define PB0_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10__SHIFT 0x0000000d +#define PB0_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10_MASK 0x00000c00L +#define PB0_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10__SHIFT 0x0000000a +#define PB0_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10_MASK 0x00001000L +#define PB0_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10__SHIFT 0x0000000c +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10_MASK 0x00000008L +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10__SHIFT 0x00000003 +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10_MASK 0x00000080L +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10__SHIFT 0x00000007 +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10_MASK 0x00000100L +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10__SHIFT 0x00000008 +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10_MASK 0x00000200L +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10__SHIFT 0x00000009 +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPRESETHINT_10_MASK 0x00000070L +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPRESETHINT_10__SHIFT 0x00000004 +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10_MASK 0x00000007L +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10__SHIFT 0x00000000 +#define PB0_RX_LANE11_CTRL_REG0__RX_BACKUP_11_MASK 0x000000ffL +#define PB0_RX_LANE11_CTRL_REG0__RX_BACKUP_11__SHIFT 0x00000000 +#define PB0_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11_MASK 0x00002000L +#define PB0_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11__SHIFT 0x0000000d +#define PB0_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11_MASK 0x00000c00L +#define PB0_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11__SHIFT 0x0000000a +#define PB0_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11_MASK 0x00001000L +#define PB0_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11__SHIFT 0x0000000c +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11_MASK 0x00000008L +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11__SHIFT 0x00000003 +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11_MASK 0x00000080L +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11__SHIFT 0x00000007 +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11_MASK 0x00000100L +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11__SHIFT 0x00000008 +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11_MASK 0x00000200L +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11__SHIFT 0x00000009 +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPRESETHINT_11_MASK 0x00000070L +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPRESETHINT_11__SHIFT 0x00000004 +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11_MASK 0x00000007L +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11__SHIFT 0x00000000 +#define PB0_RX_LANE12_CTRL_REG0__RX_BACKUP_12_MASK 0x000000ffL +#define PB0_RX_LANE12_CTRL_REG0__RX_BACKUP_12__SHIFT 0x00000000 +#define PB0_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12_MASK 0x00002000L +#define PB0_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12__SHIFT 0x0000000d +#define PB0_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12_MASK 0x00000c00L +#define PB0_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12__SHIFT 0x0000000a +#define PB0_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12_MASK 0x00001000L +#define PB0_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12__SHIFT 0x0000000c +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12_MASK 0x00000008L +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12__SHIFT 0x00000003 +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12_MASK 0x00000080L +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12__SHIFT 0x00000007 +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12_MASK 0x00000100L +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12__SHIFT 0x00000008 +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12_MASK 0x00000200L +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12__SHIFT 0x00000009 +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPRESETHINT_12_MASK 0x00000070L +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPRESETHINT_12__SHIFT 0x00000004 +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12_MASK 0x00000007L +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12__SHIFT 0x00000000 +#define PB0_RX_LANE13_CTRL_REG0__RX_BACKUP_13_MASK 0x000000ffL +#define PB0_RX_LANE13_CTRL_REG0__RX_BACKUP_13__SHIFT 0x00000000 +#define PB0_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13_MASK 0x00002000L +#define PB0_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13__SHIFT 0x0000000d +#define PB0_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13_MASK 0x00000c00L +#define PB0_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13__SHIFT 0x0000000a +#define PB0_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13_MASK 0x00001000L +#define PB0_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13__SHIFT 0x0000000c +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13_MASK 0x00000008L +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13__SHIFT 0x00000003 +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13_MASK 0x00000080L +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13__SHIFT 0x00000007 +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13_MASK 0x00000100L +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13__SHIFT 0x00000008 +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13_MASK 0x00000200L +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13__SHIFT 0x00000009 +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPRESETHINT_13_MASK 0x00000070L +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPRESETHINT_13__SHIFT 0x00000004 +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13_MASK 0x00000007L +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13__SHIFT 0x00000000 +#define PB0_RX_LANE14_CTRL_REG0__RX_BACKUP_14_MASK 0x000000ffL +#define PB0_RX_LANE14_CTRL_REG0__RX_BACKUP_14__SHIFT 0x00000000 +#define PB0_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14_MASK 0x00002000L +#define PB0_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14__SHIFT 0x0000000d +#define PB0_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14_MASK 0x00000c00L +#define PB0_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14__SHIFT 0x0000000a +#define PB0_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14_MASK 0x00001000L +#define PB0_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14__SHIFT 0x0000000c +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14_MASK 0x00000008L +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14__SHIFT 0x00000003 +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14_MASK 0x00000080L +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14__SHIFT 0x00000007 +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14_MASK 0x00000100L +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14__SHIFT 0x00000008 +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14_MASK 0x00000200L +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14__SHIFT 0x00000009 +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPRESETHINT_14_MASK 0x00000070L +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPRESETHINT_14__SHIFT 0x00000004 +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14_MASK 0x00000007L +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14__SHIFT 0x00000000 +#define PB0_RX_LANE15_CTRL_REG0__RX_BACKUP_15_MASK 0x000000ffL +#define PB0_RX_LANE15_CTRL_REG0__RX_BACKUP_15__SHIFT 0x00000000 +#define PB0_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15_MASK 0x00002000L +#define PB0_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15__SHIFT 0x0000000d +#define PB0_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15_MASK 0x00000c00L +#define PB0_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15__SHIFT 0x0000000a +#define PB0_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15_MASK 0x00001000L +#define PB0_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15__SHIFT 0x0000000c +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15_MASK 0x00000008L +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15__SHIFT 0x00000003 +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15_MASK 0x00000080L +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15__SHIFT 0x00000007 +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15_MASK 0x00000100L +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15__SHIFT 0x00000008 +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15_MASK 0x00000200L +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15__SHIFT 0x00000009 +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPRESETHINT_15_MASK 0x00000070L +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPRESETHINT_15__SHIFT 0x00000004 +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15_MASK 0x00000007L +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15__SHIFT 0x00000000 +#define PB0_RX_LANE1_CTRL_REG0__RX_BACKUP_1_MASK 0x000000ffL +#define PB0_RX_LANE1_CTRL_REG0__RX_BACKUP_1__SHIFT 0x00000000 +#define PB0_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1_MASK 0x00002000L +#define PB0_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1__SHIFT 0x0000000d +#define PB0_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1_MASK 0x00000c00L +#define PB0_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1__SHIFT 0x0000000a +#define PB0_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1_MASK 0x00001000L +#define PB0_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1__SHIFT 0x0000000c +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1_MASK 0x00000008L +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1__SHIFT 0x00000003 +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1_MASK 0x00000080L +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1__SHIFT 0x00000007 +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1_MASK 0x00000100L +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1__SHIFT 0x00000008 +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1_MASK 0x00000200L +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1__SHIFT 0x00000009 +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPRESETHINT_1_MASK 0x00000070L +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPRESETHINT_1__SHIFT 0x00000004 +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1_MASK 0x00000007L +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1__SHIFT 0x00000000 +#define PB0_RX_LANE2_CTRL_REG0__RX_BACKUP_2_MASK 0x000000ffL +#define PB0_RX_LANE2_CTRL_REG0__RX_BACKUP_2__SHIFT 0x00000000 +#define PB0_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2_MASK 0x00002000L +#define PB0_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2__SHIFT 0x0000000d +#define PB0_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2_MASK 0x00000c00L +#define PB0_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2__SHIFT 0x0000000a +#define PB0_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2_MASK 0x00001000L +#define PB0_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2__SHIFT 0x0000000c +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2_MASK 0x00000008L +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2__SHIFT 0x00000003 +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2_MASK 0x00000080L +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2__SHIFT 0x00000007 +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2_MASK 0x00000100L +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2__SHIFT 0x00000008 +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2_MASK 0x00000200L +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2__SHIFT 0x00000009 +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPRESETHINT_2_MASK 0x00000070L +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPRESETHINT_2__SHIFT 0x00000004 +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2_MASK 0x00000007L +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2__SHIFT 0x00000000 +#define PB0_RX_LANE3_CTRL_REG0__RX_BACKUP_3_MASK 0x000000ffL +#define PB0_RX_LANE3_CTRL_REG0__RX_BACKUP_3__SHIFT 0x00000000 +#define PB0_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3_MASK 0x00002000L +#define PB0_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3__SHIFT 0x0000000d +#define PB0_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3_MASK 0x00000c00L +#define PB0_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3__SHIFT 0x0000000a +#define PB0_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3_MASK 0x00001000L +#define PB0_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3__SHIFT 0x0000000c +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3_MASK 0x00000008L +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3__SHIFT 0x00000003 +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3_MASK 0x00000080L +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3__SHIFT 0x00000007 +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3_MASK 0x00000100L +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3__SHIFT 0x00000008 +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3_MASK 0x00000200L +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3__SHIFT 0x00000009 +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPRESETHINT_3_MASK 0x00000070L +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPRESETHINT_3__SHIFT 0x00000004 +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3_MASK 0x00000007L +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3__SHIFT 0x00000000 +#define PB0_RX_LANE4_CTRL_REG0__RX_BACKUP_4_MASK 0x000000ffL +#define PB0_RX_LANE4_CTRL_REG0__RX_BACKUP_4__SHIFT 0x00000000 +#define PB0_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4_MASK 0x00002000L +#define PB0_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4__SHIFT 0x0000000d +#define PB0_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4_MASK 0x00000c00L +#define PB0_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4__SHIFT 0x0000000a +#define PB0_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4_MASK 0x00001000L +#define PB0_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4__SHIFT 0x0000000c +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4_MASK 0x00000008L +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4__SHIFT 0x00000003 +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4_MASK 0x00000080L +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4__SHIFT 0x00000007 +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4_MASK 0x00000100L +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4__SHIFT 0x00000008 +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4_MASK 0x00000200L +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4__SHIFT 0x00000009 +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPRESETHINT_4_MASK 0x00000070L +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPRESETHINT_4__SHIFT 0x00000004 +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4_MASK 0x00000007L +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4__SHIFT 0x00000000 +#define PB0_RX_LANE5_CTRL_REG0__RX_BACKUP_5_MASK 0x000000ffL +#define PB0_RX_LANE5_CTRL_REG0__RX_BACKUP_5__SHIFT 0x00000000 +#define PB0_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5_MASK 0x00002000L +#define PB0_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5__SHIFT 0x0000000d +#define PB0_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5_MASK 0x00000c00L +#define PB0_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5__SHIFT 0x0000000a +#define PB0_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5_MASK 0x00001000L +#define PB0_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5__SHIFT 0x0000000c +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5_MASK 0x00000008L +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5__SHIFT 0x00000003 +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5_MASK 0x00000080L +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5__SHIFT 0x00000007 +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5_MASK 0x00000100L +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5__SHIFT 0x00000008 +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5_MASK 0x00000200L +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5__SHIFT 0x00000009 +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPRESETHINT_5_MASK 0x00000070L +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPRESETHINT_5__SHIFT 0x00000004 +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5_MASK 0x00000007L +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5__SHIFT 0x00000000 +#define PB0_RX_LANE6_CTRL_REG0__RX_BACKUP_6_MASK 0x000000ffL +#define PB0_RX_LANE6_CTRL_REG0__RX_BACKUP_6__SHIFT 0x00000000 +#define PB0_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6_MASK 0x00002000L +#define PB0_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6__SHIFT 0x0000000d +#define PB0_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6_MASK 0x00000c00L +#define PB0_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6__SHIFT 0x0000000a +#define PB0_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6_MASK 0x00001000L +#define PB0_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6__SHIFT 0x0000000c +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6_MASK 0x00000008L +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6__SHIFT 0x00000003 +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6_MASK 0x00000080L +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6__SHIFT 0x00000007 +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6_MASK 0x00000100L +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6__SHIFT 0x00000008 +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6_MASK 0x00000200L +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6__SHIFT 0x00000009 +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPRESETHINT_6_MASK 0x00000070L +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPRESETHINT_6__SHIFT 0x00000004 +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6_MASK 0x00000007L +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6__SHIFT 0x00000000 +#define PB0_RX_LANE7_CTRL_REG0__RX_BACKUP_7_MASK 0x000000ffL +#define PB0_RX_LANE7_CTRL_REG0__RX_BACKUP_7__SHIFT 0x00000000 +#define PB0_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7_MASK 0x00002000L +#define PB0_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7__SHIFT 0x0000000d +#define PB0_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7_MASK 0x00000c00L +#define PB0_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7__SHIFT 0x0000000a +#define PB0_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7_MASK 0x00001000L +#define PB0_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7__SHIFT 0x0000000c +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7_MASK 0x00000008L +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7__SHIFT 0x00000003 +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7_MASK 0x00000080L +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7__SHIFT 0x00000007 +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7_MASK 0x00000100L +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7__SHIFT 0x00000008 +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7_MASK 0x00000200L +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7__SHIFT 0x00000009 +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPRESETHINT_7_MASK 0x00000070L +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPRESETHINT_7__SHIFT 0x00000004 +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7_MASK 0x00000007L +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7__SHIFT 0x00000000 +#define PB0_RX_LANE8_CTRL_REG0__RX_BACKUP_8_MASK 0x000000ffL +#define PB0_RX_LANE8_CTRL_REG0__RX_BACKUP_8__SHIFT 0x00000000 +#define PB0_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8_MASK 0x00002000L +#define PB0_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8__SHIFT 0x0000000d +#define PB0_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8_MASK 0x00000c00L +#define PB0_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8__SHIFT 0x0000000a +#define PB0_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8_MASK 0x00001000L +#define PB0_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8__SHIFT 0x0000000c +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8_MASK 0x00000008L +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8__SHIFT 0x00000003 +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8_MASK 0x00000080L +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8__SHIFT 0x00000007 +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8_MASK 0x00000100L +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8__SHIFT 0x00000008 +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8_MASK 0x00000200L +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8__SHIFT 0x00000009 +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPRESETHINT_8_MASK 0x00000070L +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPRESETHINT_8__SHIFT 0x00000004 +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8_MASK 0x00000007L +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8__SHIFT 0x00000000 +#define PB0_RX_LANE9_CTRL_REG0__RX_BACKUP_9_MASK 0x000000ffL +#define PB0_RX_LANE9_CTRL_REG0__RX_BACKUP_9__SHIFT 0x00000000 +#define PB0_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9_MASK 0x00002000L +#define PB0_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9__SHIFT 0x0000000d +#define PB0_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9_MASK 0x00000c00L +#define PB0_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9__SHIFT 0x0000000a +#define PB0_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9_MASK 0x00001000L +#define PB0_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9__SHIFT 0x0000000c +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9_MASK 0x00000008L +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9__SHIFT 0x00000003 +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9_MASK 0x00000080L +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9__SHIFT 0x00000007 +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9_MASK 0x00000100L +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9__SHIFT 0x00000008 +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9_MASK 0x00000200L +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9__SHIFT 0x00000009 +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPRESETHINT_9_MASK 0x00000070L +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPRESETHINT_9__SHIFT 0x00000004 +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9_MASK 0x00000007L +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9__SHIFT 0x00000000 +#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL_MASK 0x00008000L +#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL__SHIFT 0x0000000f +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0_MASK 0x00000001L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0__SHIFT 0x00000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10_MASK 0x00000400L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10__SHIFT 0x0000000a +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11_MASK 0x00000800L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11__SHIFT 0x0000000b +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12_MASK 0x00001000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12__SHIFT 0x0000000c +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13_MASK 0x00002000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13__SHIFT 0x0000000d +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14_MASK 0x00004000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14__SHIFT 0x0000000e +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15_MASK 0x00008000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15__SHIFT 0x0000000f +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16_MASK 0x00010000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16__SHIFT 0x00000010 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17_MASK 0x00020000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17__SHIFT 0x00000011 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18_MASK 0x00040000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18__SHIFT 0x00000012 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19_MASK 0x00080000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19__SHIFT 0x00000013 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1_MASK 0x00000002L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1__SHIFT 0x00000001 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20_MASK 0x00100000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20__SHIFT 0x00000014 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21_MASK 0x00200000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21__SHIFT 0x00000015 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22_MASK 0x00400000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22__SHIFT 0x00000016 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23_MASK 0x00800000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23__SHIFT 0x00000017 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24_MASK 0x01000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24__SHIFT 0x00000018 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25_MASK 0x02000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25__SHIFT 0x00000019 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26_MASK 0x04000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26__SHIFT 0x0000001a +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27_MASK 0x08000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27__SHIFT 0x0000001b +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28_MASK 0x10000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28__SHIFT 0x0000001c +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29_MASK 0x20000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29__SHIFT 0x0000001d +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2_MASK 0x00000004L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2__SHIFT 0x00000002 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30_MASK 0x40000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30__SHIFT 0x0000001e +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31_MASK 0x80000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31__SHIFT 0x0000001f +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3_MASK 0x00000008L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3__SHIFT 0x00000003 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4_MASK 0x00000010L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4__SHIFT 0x00000004 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5_MASK 0x00000020L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5__SHIFT 0x00000005 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6_MASK 0x00000040L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6__SHIFT 0x00000006 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7_MASK 0x00000080L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7__SHIFT 0x00000007 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8_MASK 0x00000100L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8__SHIFT 0x00000008 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9_MASK 0x00000200L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9__SHIFT 0x00000009 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32_MASK 0x00000001L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32__SHIFT 0x00000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33_MASK 0x00000002L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33__SHIFT 0x00000001 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34_MASK 0x00000004L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34__SHIFT 0x00000002 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35_MASK 0x00000008L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35__SHIFT 0x00000003 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36_MASK 0x00000010L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36__SHIFT 0x00000004 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37_MASK 0x00000020L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37__SHIFT 0x00000005 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38_MASK 0x00000040L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38__SHIFT 0x00000006 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39_MASK 0x00000080L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39__SHIFT 0x00000007 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40_MASK 0x00000100L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40__SHIFT 0x00000008 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41_MASK 0x00000200L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41__SHIFT 0x00000009 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42_MASK 0x00000400L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42__SHIFT 0x0000000a +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43_MASK 0x00000800L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43__SHIFT 0x0000000b +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44_MASK 0x00001000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44__SHIFT 0x0000000c +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45_MASK 0x00002000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45__SHIFT 0x0000000d +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46_MASK 0x00004000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46__SHIFT 0x0000000e +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47_MASK 0x00008000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47__SHIFT 0x0000000f +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48_MASK 0x00010000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48__SHIFT 0x00000010 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49_MASK 0x00020000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49__SHIFT 0x00000011 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50_MASK 0x00040000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50__SHIFT 0x00000012 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51_MASK 0x00080000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51__SHIFT 0x00000013 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52_MASK 0x00100000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52__SHIFT 0x00000014 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53_MASK 0x00200000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53__SHIFT 0x00000015 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54_MASK 0x00400000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54__SHIFT 0x00000016 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55_MASK 0x00800000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55__SHIFT 0x00000017 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56_MASK 0x01000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56__SHIFT 0x00000018 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57_MASK 0x02000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57__SHIFT 0x00000019 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58_MASK 0x04000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58__SHIFT 0x0000001a +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59_MASK 0x08000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59__SHIFT 0x0000001b +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60_MASK 0x10000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60__SHIFT 0x0000001c +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61_MASK 0x20000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61__SHIFT 0x0000001d +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62_MASK 0x40000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62__SHIFT 0x0000001e +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63_MASK 0x80000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63__SHIFT 0x0000001f +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64_MASK 0x00000001L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64__SHIFT 0x00000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65_MASK 0x00000002L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65__SHIFT 0x00000001 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66_MASK 0x00000004L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66__SHIFT 0x00000002 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67_MASK 0x00000008L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67__SHIFT 0x00000003 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68_MASK 0x00000010L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68__SHIFT 0x00000004 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69_MASK 0x00000020L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69__SHIFT 0x00000005 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70_MASK 0x00000040L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70__SHIFT 0x00000006 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71_MASK 0x00000080L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71__SHIFT 0x00000007 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72_MASK 0x00000100L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72__SHIFT 0x00000008 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73_MASK 0x00000200L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73__SHIFT 0x00000009 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74_MASK 0x00000400L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74__SHIFT 0x0000000a +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75_MASK 0x00000800L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75__SHIFT 0x0000000b +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76_MASK 0x00001000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76__SHIFT 0x0000000c +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77_MASK 0x00002000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77__SHIFT 0x0000000d +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78_MASK 0x00004000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78__SHIFT 0x0000000e +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79_MASK 0x00008000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79__SHIFT 0x0000000f +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80_MASK 0x00010000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80__SHIFT 0x00000010 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81_MASK 0x00020000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81__SHIFT 0x00000011 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82_MASK 0x00040000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82__SHIFT 0x00000012 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83_MASK 0x00080000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83__SHIFT 0x00000013 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84_MASK 0x00100000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84__SHIFT 0x00000014 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85_MASK 0x00200000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85__SHIFT 0x00000015 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86_MASK 0x00400000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86__SHIFT 0x00000016 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87_MASK 0x00800000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87__SHIFT 0x00000017 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88_MASK 0x01000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88__SHIFT 0x00000018 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89_MASK 0x02000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89__SHIFT 0x00000019 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90_MASK 0x04000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90__SHIFT 0x0000001a +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91_MASK 0x08000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91__SHIFT 0x0000001b +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92_MASK 0x10000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92__SHIFT 0x0000001c +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93_MASK 0x20000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93__SHIFT 0x0000001d +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94_MASK 0x40000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94__SHIFT 0x0000001e +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95_MASK 0x80000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95__SHIFT 0x0000001f +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100_MASK 0x00000010L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100__SHIFT 0x00000004 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101_MASK 0x00000020L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101__SHIFT 0x00000005 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102_MASK 0x00000040L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102__SHIFT 0x00000006 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103_MASK 0x00000080L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103__SHIFT 0x00000007 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104_MASK 0x00000100L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104__SHIFT 0x00000008 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105_MASK 0x00000200L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105__SHIFT 0x00000009 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106_MASK 0x00000400L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106__SHIFT 0x0000000a +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107_MASK 0x00000800L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107__SHIFT 0x0000000b +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108_MASK 0x00001000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108__SHIFT 0x0000000c +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109_MASK 0x00002000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109__SHIFT 0x0000000d +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96_MASK 0x00000001L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96__SHIFT 0x00000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97_MASK 0x00000002L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97__SHIFT 0x00000001 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98_MASK 0x00000004L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98__SHIFT 0x00000002 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99_MASK 0x00000008L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99__SHIFT 0x00000003 +#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1_MASK 0x00000700L +#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1__SHIFT 0x00000008 +#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2_MASK 0x00003800L +#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2__SHIFT 0x0000000b +#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3_MASK 0x0001c000L +#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3__SHIFT 0x0000000e +#define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER_MASK 0x00400000L +#define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER__SHIFT 0x00000016 +#define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN_MASK 0x00200000L +#define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN__SHIFT 0x00000015 +#define PB0_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING_MASK 0x00080000L +#define PB0_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING__SHIFT 0x00000013 +#define PB0_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON_MASK 0x00800000L +#define PB0_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON__SHIFT 0x00000017 +#define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL_MASK 0x00000007L +#define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL__SHIFT 0x00000000 +#define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL_MASK 0x00000038L +#define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL__SHIFT 0x00000003 +#define PB0_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_OFF_MASK 0x01000000L +#define PB0_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_OFF__SHIFT 0x00000018 +#define PB0_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS_MASK 0x00100000L +#define PB0_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS__SHIFT 0x00000014 +#define PB0_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL_MASK 0x00060000L +#define PB0_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL__SHIFT 0x00000011 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15_MASK 0x40000000L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15__SHIFT 0x0000001e +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0_MASK 0x00000001L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0__SHIFT 0x00000000 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10_MASK 0x00000400L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10__SHIFT 0x0000000a +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11_MASK 0x00000800L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11__SHIFT 0x0000000b +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12_MASK 0x00001000L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12__SHIFT 0x0000000c +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13_MASK 0x00002000L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13__SHIFT 0x0000000d +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14_MASK 0x00004000L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14__SHIFT 0x0000000e +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15_MASK 0x00008000L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15__SHIFT 0x0000000f +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1_MASK 0x00000002L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1__SHIFT 0x00000001 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2_MASK 0x00000004L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2__SHIFT 0x00000002 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3_MASK 0x00000008L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3__SHIFT 0x00000003 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4_MASK 0x00000010L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4__SHIFT 0x00000004 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5_MASK 0x00000020L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5__SHIFT 0x00000005 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6_MASK 0x00000040L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6__SHIFT 0x00000006 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7_MASK 0x00000080L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7__SHIFT 0x00000007 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8_MASK 0x00000100L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8__SHIFT 0x00000008 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9_MASK 0x00000200L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9__SHIFT 0x00000009 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1_MASK 0x00010000L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1__SHIFT 0x00000010 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11_MASK 0x00200000L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11__SHIFT 0x00000015 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13_MASK 0x00400000L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13__SHIFT 0x00000016 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15_MASK 0x00800000L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15__SHIFT 0x00000017 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3_MASK 0x00020000L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3__SHIFT 0x00000011 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5_MASK 0x00040000L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5__SHIFT 0x00000012 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7_MASK 0x00080000L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7__SHIFT 0x00000013 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9_MASK 0x00100000L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9__SHIFT 0x00000014 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3_MASK 0x01000000L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3__SHIFT 0x00000018 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15_MASK 0x08000000L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15__SHIFT 0x0000001b +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7_MASK 0x02000000L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7__SHIFT 0x00000019 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11_MASK 0x04000000L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11__SHIFT 0x0000001a +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7_MASK 0x10000000L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7__SHIFT 0x0000001c +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15_MASK 0x20000000L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15__SHIFT 0x0000001d +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN_MASK 0x00000008L +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x00000003 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL_MASK 0x00000007L +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x00000000 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL_MASK 0x000000f0L +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL__SHIFT 0x00000004 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN_MASK 0x00000100L +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN__SHIFT 0x00000008 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL_MASK 0x00001e00L +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x00000009 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN_MASK 0x00002000L +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN__SHIFT 0x0000000d +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL_MASK 0x0007c000L +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL__SHIFT 0x0000000e +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN_MASK 0x00080000L +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN__SHIFT 0x00000013 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL_MASK 0x01f00000L +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x00000014 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN_MASK 0x02000000L +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN__SHIFT 0x00000019 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL_MASK 0x3c000000L +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL__SHIFT 0x0000001a +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN_MASK 0x40000000L +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN__SHIFT 0x0000001e +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL_MASK 0x0000000fL +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x00000000 +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN_MASK 0x00000010L +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN__SHIFT 0x00000004 +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL_MASK 0x00000020L +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL__SHIFT 0x00000005 +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN_MASK 0x00000040L +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN__SHIFT 0x00000006 +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL_MASK 0x00000080L +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x00000007 +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN_MASK 0x00000100L +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN__SHIFT 0x00000008 +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x00000400L +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0x0000000a +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x00000200L +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0x00000009 +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN_MASK 0x00001000L +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN__SHIFT 0x0000000c +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL_MASK 0x00000800L +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL__SHIFT 0x0000000b +#define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN_MASK 0x00004000L +#define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN__SHIFT 0x0000000e +#define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL_MASK 0x00002000L +#define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL__SHIFT 0x0000000d +#define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN_MASK 0x02000000L +#define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN__SHIFT 0x00000019 +#define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL_MASK 0x01ff8000L +#define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL__SHIFT 0x0000000f +#define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN_MASK 0x08000000L +#define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN__SHIFT 0x0000001b +#define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL_MASK 0x04000000L +#define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL__SHIFT 0x0000001a +#define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN_MASK 0x20000000L +#define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN__SHIFT 0x0000001d +#define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL_MASK 0x10000000L +#define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL__SHIFT 0x0000001c +#define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN_MASK 0x80000000L +#define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN__SHIFT 0x0000001f +#define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL_MASK 0x40000000L +#define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL__SHIFT 0x0000001e +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL_MASK 0x0000f000L +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL__SHIFT 0x0000000c +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL_MASK 0x000f0000L +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x00000010 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL_MASK 0x01f00000L +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL__SHIFT 0x00000014 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL_MASK 0x3e000000L +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x00000019 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN_MASK 0x00000800L +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN__SHIFT 0x0000000b +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL_MASK 0x00000400L +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL__SHIFT 0x0000000a +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN_MASK 0x00000008L +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN__SHIFT 0x00000003 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL_MASK 0x00000004L +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL__SHIFT 0x00000002 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN_MASK 0x00000020L +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN__SHIFT 0x00000005 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL_MASK 0x00000010L +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL__SHIFT 0x00000004 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN_MASK 0x00000080L +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN__SHIFT 0x00000007 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL_MASK 0x00000040L +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL__SHIFT 0x00000006 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN_MASK 0x00000200L +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN__SHIFT 0x00000009 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL_MASK 0x00000100L +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL__SHIFT 0x00000008 +#define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN_MASK 0x00000002L +#define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN__SHIFT 0x00000001 +#define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL_MASK 0x00000001L +#define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL__SHIFT 0x00000000 +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL_MASK 0x00003c00L +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL__SHIFT 0x0000000a +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL_MASK 0x0003c000L +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x0000000e +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL_MASK 0x007c0000L +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL__SHIFT 0x00000012 +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL_MASK 0x0f800000L +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x00000017 +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL_MASK 0x0000000fL +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL__SHIFT 0x00000000 +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL_MASK 0xf0000000L +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL__SHIFT 0x0000001c +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL_MASK 0x000000f0L +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x00000004 +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL_MASK 0x00000100L +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL__SHIFT 0x00000008 +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL_MASK 0x00000200L +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x00000009 +#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL_MASK 0x0000000fL +#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x00000000 +#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL_MASK 0x00000010L +#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL__SHIFT 0x00000004 +#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL_MASK 0x00000020L +#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x00000005 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L0T3_MASK 0x00000100L +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L0T3__SHIFT 0x00000008 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L12T15_MASK 0x00000800L +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L12T15__SHIFT 0x0000000b +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L4T7_MASK 0x00000200L +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L4T7__SHIFT 0x00000009 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L8T11_MASK 0x00000400L +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L8T11__SHIFT 0x0000000a +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L0T3_MASK 0x00001000L +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L0T3__SHIFT 0x0000000c +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L12T15_MASK 0x00008000L +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L12T15__SHIFT 0x0000000f +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L4T7_MASK 0x00002000L +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L4T7__SHIFT 0x0000000d +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L8T11_MASK 0x00004000L +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L8T11__SHIFT 0x0000000e +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L0T3_MASK 0x00000010L +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L0T3__SHIFT 0x00000004 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L12T15_MASK 0x00000080L +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L12T15__SHIFT 0x00000007 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L4T7_MASK 0x00000020L +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L4T7__SHIFT 0x00000005 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L8T11_MASK 0x00000040L +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L8T11__SHIFT 0x00000006 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L0T3_MASK 0x00000001L +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L0T3__SHIFT 0x00000000 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L12T15_MASK 0x00000008L +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L12T15__SHIFT 0x00000003 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L4T7_MASK 0x00000002L +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L4T7__SHIFT 0x00000001 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L8T11_MASK 0x00000004L +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L8T11__SHIFT 0x00000002 +#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0_MASK 0x00000001L +#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0__SHIFT 0x00000000 +#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0_MASK 0x00000002L +#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0__SHIFT 0x00000001 +#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0_MASK 0x00000004L +#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0__SHIFT 0x00000002 +#define PB0_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0_MASK 0x00000008L +#define PB0_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0__SHIFT 0x00000003 +#define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0_MASK 0x00000002L +#define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0__SHIFT 0x00000001 +#define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0_MASK 0x00000001L +#define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0__SHIFT 0x00000000 +#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0_MASK 0x00000008L +#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0__SHIFT 0x00000003 +#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0_MASK 0x00000004L +#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0__SHIFT 0x00000002 +#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0_MASK 0x00000020L +#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0__SHIFT 0x00000005 +#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0_MASK 0x00000010L +#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0__SHIFT 0x00000004 +#define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0_MASK 0x00000080L +#define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0__SHIFT 0x00000007 +#define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0_MASK 0x00000040L +#define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0__SHIFT 0x00000006 +#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0_MASK 0x0000fc00L +#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0__SHIFT 0x0000000a +#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0_MASK 0x00000300L +#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0__SHIFT 0x00000008 +#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0_MASK 0x00000080L +#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0__SHIFT 0x00000007 +#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__INCOHERENTCK_0_MASK 0x00000008L +#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__INCOHERENTCK_0__SHIFT 0x00000003 +#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0_MASK 0x00000070L +#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0__SHIFT 0x00000004 +#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0_MASK 0x00000007L +#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0__SHIFT 0x00000000 +#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10_MASK 0x00000001L +#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10__SHIFT 0x00000000 +#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10_MASK 0x00000002L +#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10__SHIFT 0x00000001 +#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10_MASK 0x00000004L +#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10__SHIFT 0x00000002 +#define PB0_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10_MASK 0x00000008L +#define PB0_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10__SHIFT 0x00000003 +#define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10_MASK 0x00000002L +#define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10__SHIFT 0x00000001 +#define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10_MASK 0x00000001L +#define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10__SHIFT 0x00000000 +#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10_MASK 0x00000008L +#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10__SHIFT 0x00000003 +#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10_MASK 0x00000004L +#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10__SHIFT 0x00000002 +#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10_MASK 0x00000020L +#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10__SHIFT 0x00000005 +#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10_MASK 0x00000010L +#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10__SHIFT 0x00000004 +#define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10_MASK 0x00000080L +#define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10__SHIFT 0x00000007 +#define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10_MASK 0x00000040L +#define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10__SHIFT 0x00000006 +#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10_MASK 0x0000fc00L +#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10__SHIFT 0x0000000a +#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10_MASK 0x00000300L +#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10__SHIFT 0x00000008 +#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10_MASK 0x00000080L +#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10__SHIFT 0x00000007 +#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__INCOHERENTCK_10_MASK 0x00000008L +#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__INCOHERENTCK_10__SHIFT 0x00000003 +#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10_MASK 0x00000070L +#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10__SHIFT 0x00000004 +#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10_MASK 0x00000007L +#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10__SHIFT 0x00000000 +#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11_MASK 0x00000001L +#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11__SHIFT 0x00000000 +#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11_MASK 0x00000002L +#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11__SHIFT 0x00000001 +#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11_MASK 0x00000004L +#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11__SHIFT 0x00000002 +#define PB0_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11_MASK 0x00000008L +#define PB0_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11__SHIFT 0x00000003 +#define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11_MASK 0x00000002L +#define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11__SHIFT 0x00000001 +#define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11_MASK 0x00000001L +#define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11__SHIFT 0x00000000 +#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11_MASK 0x00000008L +#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11__SHIFT 0x00000003 +#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11_MASK 0x00000004L +#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11__SHIFT 0x00000002 +#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11_MASK 0x00000020L +#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11__SHIFT 0x00000005 +#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11_MASK 0x00000010L +#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11__SHIFT 0x00000004 +#define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11_MASK 0x00000080L +#define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11__SHIFT 0x00000007 +#define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11_MASK 0x00000040L +#define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11__SHIFT 0x00000006 +#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11_MASK 0x0000fc00L +#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11__SHIFT 0x0000000a +#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11_MASK 0x00000300L +#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11__SHIFT 0x00000008 +#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11_MASK 0x00000080L +#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11__SHIFT 0x00000007 +#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__INCOHERENTCK_11_MASK 0x00000008L +#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__INCOHERENTCK_11__SHIFT 0x00000003 +#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11_MASK 0x00000070L +#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11__SHIFT 0x00000004 +#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11_MASK 0x00000007L +#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11__SHIFT 0x00000000 +#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12_MASK 0x00000001L +#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12__SHIFT 0x00000000 +#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12_MASK 0x00000002L +#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12__SHIFT 0x00000001 +#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12_MASK 0x00000004L +#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12__SHIFT 0x00000002 +#define PB0_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12_MASK 0x00000008L +#define PB0_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12__SHIFT 0x00000003 +#define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12_MASK 0x00000002L +#define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12__SHIFT 0x00000001 +#define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12_MASK 0x00000001L +#define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12__SHIFT 0x00000000 +#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12_MASK 0x00000008L +#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12__SHIFT 0x00000003 +#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12_MASK 0x00000004L +#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12__SHIFT 0x00000002 +#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12_MASK 0x00000020L +#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12__SHIFT 0x00000005 +#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12_MASK 0x00000010L +#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12__SHIFT 0x00000004 +#define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12_MASK 0x00000080L +#define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12__SHIFT 0x00000007 +#define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12_MASK 0x00000040L +#define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12__SHIFT 0x00000006 +#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12_MASK 0x0000fc00L +#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12__SHIFT 0x0000000a +#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12_MASK 0x00000300L +#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12__SHIFT 0x00000008 +#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12_MASK 0x00000080L +#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12__SHIFT 0x00000007 +#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__INCOHERENTCK_12_MASK 0x00000008L +#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__INCOHERENTCK_12__SHIFT 0x00000003 +#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12_MASK 0x00000070L +#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12__SHIFT 0x00000004 +#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12_MASK 0x00000007L +#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12__SHIFT 0x00000000 +#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13_MASK 0x00000001L +#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13__SHIFT 0x00000000 +#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13_MASK 0x00000002L +#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13__SHIFT 0x00000001 +#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13_MASK 0x00000004L +#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13__SHIFT 0x00000002 +#define PB0_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13_MASK 0x00000008L +#define PB0_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13__SHIFT 0x00000003 +#define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13_MASK 0x00000002L +#define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13__SHIFT 0x00000001 +#define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13_MASK 0x00000001L +#define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13__SHIFT 0x00000000 +#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13_MASK 0x00000008L +#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13__SHIFT 0x00000003 +#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13_MASK 0x00000004L +#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13__SHIFT 0x00000002 +#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13_MASK 0x00000020L +#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13__SHIFT 0x00000005 +#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13_MASK 0x00000010L +#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13__SHIFT 0x00000004 +#define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13_MASK 0x00000080L +#define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13__SHIFT 0x00000007 +#define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13_MASK 0x00000040L +#define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13__SHIFT 0x00000006 +#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13_MASK 0x0000fc00L +#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13__SHIFT 0x0000000a +#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13_MASK 0x00000300L +#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13__SHIFT 0x00000008 +#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13_MASK 0x00000080L +#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13__SHIFT 0x00000007 +#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__INCOHERENTCK_13_MASK 0x00000008L +#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__INCOHERENTCK_13__SHIFT 0x00000003 +#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13_MASK 0x00000070L +#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13__SHIFT 0x00000004 +#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13_MASK 0x00000007L +#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13__SHIFT 0x00000000 +#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14_MASK 0x00000001L +#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14__SHIFT 0x00000000 +#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14_MASK 0x00000002L +#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14__SHIFT 0x00000001 +#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14_MASK 0x00000004L +#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14__SHIFT 0x00000002 +#define PB0_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14_MASK 0x00000008L +#define PB0_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14__SHIFT 0x00000003 +#define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14_MASK 0x00000002L +#define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14__SHIFT 0x00000001 +#define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14_MASK 0x00000001L +#define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14__SHIFT 0x00000000 +#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14_MASK 0x00000008L +#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14__SHIFT 0x00000003 +#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14_MASK 0x00000004L +#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14__SHIFT 0x00000002 +#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14_MASK 0x00000020L +#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14__SHIFT 0x00000005 +#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14_MASK 0x00000010L +#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14__SHIFT 0x00000004 +#define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14_MASK 0x00000080L +#define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14__SHIFT 0x00000007 +#define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14_MASK 0x00000040L +#define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14__SHIFT 0x00000006 +#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14_MASK 0x0000fc00L +#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14__SHIFT 0x0000000a +#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14_MASK 0x00000300L +#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14__SHIFT 0x00000008 +#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14_MASK 0x00000080L +#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14__SHIFT 0x00000007 +#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__INCOHERENTCK_14_MASK 0x00000008L +#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__INCOHERENTCK_14__SHIFT 0x00000003 +#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14_MASK 0x00000070L +#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14__SHIFT 0x00000004 +#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14_MASK 0x00000007L +#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14__SHIFT 0x00000000 +#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15_MASK 0x00000001L +#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15__SHIFT 0x00000000 +#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15_MASK 0x00000002L +#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15__SHIFT 0x00000001 +#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15_MASK 0x00000004L +#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15__SHIFT 0x00000002 +#define PB0_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15_MASK 0x00000008L +#define PB0_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15__SHIFT 0x00000003 +#define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15_MASK 0x00000002L +#define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15__SHIFT 0x00000001 +#define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15_MASK 0x00000001L +#define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15__SHIFT 0x00000000 +#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15_MASK 0x00000008L +#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15__SHIFT 0x00000003 +#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15_MASK 0x00000004L +#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15__SHIFT 0x00000002 +#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15_MASK 0x00000020L +#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15__SHIFT 0x00000005 +#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15_MASK 0x00000010L +#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15__SHIFT 0x00000004 +#define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15_MASK 0x00000080L +#define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15__SHIFT 0x00000007 +#define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15_MASK 0x00000040L +#define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15__SHIFT 0x00000006 +#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15_MASK 0x0000fc00L +#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15__SHIFT 0x0000000a +#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15_MASK 0x00000300L +#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15__SHIFT 0x00000008 +#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15_MASK 0x00000080L +#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15__SHIFT 0x00000007 +#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__INCOHERENTCK_15_MASK 0x00000008L +#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__INCOHERENTCK_15__SHIFT 0x00000003 +#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15_MASK 0x00000070L +#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15__SHIFT 0x00000004 +#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15_MASK 0x00000007L +#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15__SHIFT 0x00000000 +#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1_MASK 0x00000001L +#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1__SHIFT 0x00000000 +#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1_MASK 0x00000002L +#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1__SHIFT 0x00000001 +#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1_MASK 0x00000004L +#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1__SHIFT 0x00000002 +#define PB0_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1_MASK 0x00000008L +#define PB0_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1__SHIFT 0x00000003 +#define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1_MASK 0x00000002L +#define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1__SHIFT 0x00000001 +#define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1_MASK 0x00000001L +#define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1__SHIFT 0x00000000 +#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1_MASK 0x00000008L +#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1__SHIFT 0x00000003 +#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1_MASK 0x00000004L +#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1__SHIFT 0x00000002 +#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1_MASK 0x00000020L +#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1__SHIFT 0x00000005 +#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1_MASK 0x00000010L +#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1__SHIFT 0x00000004 +#define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1_MASK 0x00000080L +#define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1__SHIFT 0x00000007 +#define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1_MASK 0x00000040L +#define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1__SHIFT 0x00000006 +#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1_MASK 0x0000fc00L +#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1__SHIFT 0x0000000a +#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1_MASK 0x00000300L +#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1__SHIFT 0x00000008 +#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1_MASK 0x00000080L +#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1__SHIFT 0x00000007 +#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__INCOHERENTCK_1_MASK 0x00000008L +#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__INCOHERENTCK_1__SHIFT 0x00000003 +#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1_MASK 0x00000070L +#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1__SHIFT 0x00000004 +#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1_MASK 0x00000007L +#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1__SHIFT 0x00000000 +#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2_MASK 0x00000001L +#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2__SHIFT 0x00000000 +#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2_MASK 0x00000002L +#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2__SHIFT 0x00000001 +#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2_MASK 0x00000004L +#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2__SHIFT 0x00000002 +#define PB0_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2_MASK 0x00000008L +#define PB0_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2__SHIFT 0x00000003 +#define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2_MASK 0x00000002L +#define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2__SHIFT 0x00000001 +#define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2_MASK 0x00000001L +#define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2__SHIFT 0x00000000 +#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2_MASK 0x00000008L +#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2__SHIFT 0x00000003 +#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2_MASK 0x00000004L +#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2__SHIFT 0x00000002 +#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2_MASK 0x00000020L +#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2__SHIFT 0x00000005 +#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2_MASK 0x00000010L +#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2__SHIFT 0x00000004 +#define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2_MASK 0x00000080L +#define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2__SHIFT 0x00000007 +#define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2_MASK 0x00000040L +#define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2__SHIFT 0x00000006 +#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2_MASK 0x0000fc00L +#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2__SHIFT 0x0000000a +#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2_MASK 0x00000300L +#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2__SHIFT 0x00000008 +#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2_MASK 0x00000080L +#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2__SHIFT 0x00000007 +#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__INCOHERENTCK_2_MASK 0x00000008L +#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__INCOHERENTCK_2__SHIFT 0x00000003 +#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2_MASK 0x00000070L +#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2__SHIFT 0x00000004 +#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2_MASK 0x00000007L +#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2__SHIFT 0x00000000 +#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3_MASK 0x00000001L +#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3__SHIFT 0x00000000 +#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3_MASK 0x00000002L +#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3__SHIFT 0x00000001 +#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3_MASK 0x00000004L +#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3__SHIFT 0x00000002 +#define PB0_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3_MASK 0x00000008L +#define PB0_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3__SHIFT 0x00000003 +#define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3_MASK 0x00000002L +#define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3__SHIFT 0x00000001 +#define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3_MASK 0x00000001L +#define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3__SHIFT 0x00000000 +#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3_MASK 0x00000008L +#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3__SHIFT 0x00000003 +#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3_MASK 0x00000004L +#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3__SHIFT 0x00000002 +#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3_MASK 0x00000020L +#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3__SHIFT 0x00000005 +#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3_MASK 0x00000010L +#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3__SHIFT 0x00000004 +#define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3_MASK 0x00000080L +#define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3__SHIFT 0x00000007 +#define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3_MASK 0x00000040L +#define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3__SHIFT 0x00000006 +#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3_MASK 0x0000fc00L +#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3__SHIFT 0x0000000a +#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3_MASK 0x00000300L +#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3__SHIFT 0x00000008 +#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3_MASK 0x00000080L +#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3__SHIFT 0x00000007 +#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__INCOHERENTCK_3_MASK 0x00000008L +#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__INCOHERENTCK_3__SHIFT 0x00000003 +#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3_MASK 0x00000070L +#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3__SHIFT 0x00000004 +#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3_MASK 0x00000007L +#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3__SHIFT 0x00000000 +#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4_MASK 0x00000001L +#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4__SHIFT 0x00000000 +#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4_MASK 0x00000002L +#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4__SHIFT 0x00000001 +#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4_MASK 0x00000004L +#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4__SHIFT 0x00000002 +#define PB0_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4_MASK 0x00000008L +#define PB0_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4__SHIFT 0x00000003 +#define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4_MASK 0x00000002L +#define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4__SHIFT 0x00000001 +#define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4_MASK 0x00000001L +#define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4__SHIFT 0x00000000 +#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4_MASK 0x00000008L +#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4__SHIFT 0x00000003 +#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4_MASK 0x00000004L +#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4__SHIFT 0x00000002 +#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4_MASK 0x00000020L +#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4__SHIFT 0x00000005 +#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4_MASK 0x00000010L +#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4__SHIFT 0x00000004 +#define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4_MASK 0x00000080L +#define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4__SHIFT 0x00000007 +#define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4_MASK 0x00000040L +#define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4__SHIFT 0x00000006 +#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4_MASK 0x0000fc00L +#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4__SHIFT 0x0000000a +#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4_MASK 0x00000300L +#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4__SHIFT 0x00000008 +#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4_MASK 0x00000080L +#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4__SHIFT 0x00000007 +#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__INCOHERENTCK_4_MASK 0x00000008L +#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__INCOHERENTCK_4__SHIFT 0x00000003 +#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4_MASK 0x00000070L +#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4__SHIFT 0x00000004 +#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4_MASK 0x00000007L +#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4__SHIFT 0x00000000 +#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5_MASK 0x00000001L +#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5__SHIFT 0x00000000 +#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5_MASK 0x00000002L +#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5__SHIFT 0x00000001 +#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5_MASK 0x00000004L +#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5__SHIFT 0x00000002 +#define PB0_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5_MASK 0x00000008L +#define PB0_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5__SHIFT 0x00000003 +#define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5_MASK 0x00000002L +#define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5__SHIFT 0x00000001 +#define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5_MASK 0x00000001L +#define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5__SHIFT 0x00000000 +#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5_MASK 0x00000008L +#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5__SHIFT 0x00000003 +#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5_MASK 0x00000004L +#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5__SHIFT 0x00000002 +#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5_MASK 0x00000020L +#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5__SHIFT 0x00000005 +#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5_MASK 0x00000010L +#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5__SHIFT 0x00000004 +#define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5_MASK 0x00000080L +#define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5__SHIFT 0x00000007 +#define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5_MASK 0x00000040L +#define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5__SHIFT 0x00000006 +#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5_MASK 0x0000fc00L +#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5__SHIFT 0x0000000a +#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5_MASK 0x00000300L +#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5__SHIFT 0x00000008 +#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5_MASK 0x00000080L +#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5__SHIFT 0x00000007 +#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__INCOHERENTCK_5_MASK 0x00000008L +#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__INCOHERENTCK_5__SHIFT 0x00000003 +#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5_MASK 0x00000070L +#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5__SHIFT 0x00000004 +#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5_MASK 0x00000007L +#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5__SHIFT 0x00000000 +#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6_MASK 0x00000001L +#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6__SHIFT 0x00000000 +#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6_MASK 0x00000002L +#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6__SHIFT 0x00000001 +#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6_MASK 0x00000004L +#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6__SHIFT 0x00000002 +#define PB0_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6_MASK 0x00000008L +#define PB0_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6__SHIFT 0x00000003 +#define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6_MASK 0x00000002L +#define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6__SHIFT 0x00000001 +#define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6_MASK 0x00000001L +#define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6__SHIFT 0x00000000 +#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6_MASK 0x00000008L +#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6__SHIFT 0x00000003 +#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6_MASK 0x00000004L +#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6__SHIFT 0x00000002 +#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6_MASK 0x00000020L +#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6__SHIFT 0x00000005 +#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6_MASK 0x00000010L +#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6__SHIFT 0x00000004 +#define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6_MASK 0x00000080L +#define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6__SHIFT 0x00000007 +#define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6_MASK 0x00000040L +#define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6__SHIFT 0x00000006 +#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6_MASK 0x0000fc00L +#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6__SHIFT 0x0000000a +#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6_MASK 0x00000300L +#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6__SHIFT 0x00000008 +#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6_MASK 0x00000080L +#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6__SHIFT 0x00000007 +#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__INCOHERENTCK_6_MASK 0x00000008L +#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__INCOHERENTCK_6__SHIFT 0x00000003 +#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6_MASK 0x00000070L +#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6__SHIFT 0x00000004 +#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6_MASK 0x00000007L +#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6__SHIFT 0x00000000 +#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7_MASK 0x00000001L +#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7__SHIFT 0x00000000 +#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7_MASK 0x00000002L +#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7__SHIFT 0x00000001 +#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7_MASK 0x00000004L +#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7__SHIFT 0x00000002 +#define PB0_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7_MASK 0x00000008L +#define PB0_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7__SHIFT 0x00000003 +#define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7_MASK 0x00000002L +#define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7__SHIFT 0x00000001 +#define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7_MASK 0x00000001L +#define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7__SHIFT 0x00000000 +#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7_MASK 0x00000008L +#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7__SHIFT 0x00000003 +#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7_MASK 0x00000004L +#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7__SHIFT 0x00000002 +#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7_MASK 0x00000020L +#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7__SHIFT 0x00000005 +#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7_MASK 0x00000010L +#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7__SHIFT 0x00000004 +#define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7_MASK 0x00000080L +#define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7__SHIFT 0x00000007 +#define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7_MASK 0x00000040L +#define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7__SHIFT 0x00000006 +#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7_MASK 0x0000fc00L +#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7__SHIFT 0x0000000a +#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7_MASK 0x00000300L +#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7__SHIFT 0x00000008 +#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7_MASK 0x00000080L +#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7__SHIFT 0x00000007 +#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__INCOHERENTCK_7_MASK 0x00000008L +#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__INCOHERENTCK_7__SHIFT 0x00000003 +#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7_MASK 0x00000070L +#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7__SHIFT 0x00000004 +#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7_MASK 0x00000007L +#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7__SHIFT 0x00000000 +#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8_MASK 0x00000001L +#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8__SHIFT 0x00000000 +#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8_MASK 0x00000002L +#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8__SHIFT 0x00000001 +#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8_MASK 0x00000004L +#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8__SHIFT 0x00000002 +#define PB0_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8_MASK 0x00000008L +#define PB0_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8__SHIFT 0x00000003 +#define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8_MASK 0x00000002L +#define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8__SHIFT 0x00000001 +#define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8_MASK 0x00000001L +#define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8__SHIFT 0x00000000 +#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8_MASK 0x00000008L +#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8__SHIFT 0x00000003 +#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8_MASK 0x00000004L +#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8__SHIFT 0x00000002 +#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8_MASK 0x00000020L +#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8__SHIFT 0x00000005 +#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8_MASK 0x00000010L +#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8__SHIFT 0x00000004 +#define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8_MASK 0x00000080L +#define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8__SHIFT 0x00000007 +#define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8_MASK 0x00000040L +#define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8__SHIFT 0x00000006 +#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8_MASK 0x0000fc00L +#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8__SHIFT 0x0000000a +#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8_MASK 0x00000300L +#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8__SHIFT 0x00000008 +#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8_MASK 0x00000080L +#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8__SHIFT 0x00000007 +#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__INCOHERENTCK_8_MASK 0x00000008L +#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__INCOHERENTCK_8__SHIFT 0x00000003 +#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8_MASK 0x00000070L +#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8__SHIFT 0x00000004 +#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8_MASK 0x00000007L +#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8__SHIFT 0x00000000 +#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9_MASK 0x00000001L +#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9__SHIFT 0x00000000 +#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9_MASK 0x00000002L +#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9__SHIFT 0x00000001 +#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9_MASK 0x00000004L +#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9__SHIFT 0x00000002 +#define PB0_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9_MASK 0x00000008L +#define PB0_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9__SHIFT 0x00000003 +#define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9_MASK 0x00000002L +#define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9__SHIFT 0x00000001 +#define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9_MASK 0x00000001L +#define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9__SHIFT 0x00000000 +#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9_MASK 0x00000008L +#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9__SHIFT 0x00000003 +#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9_MASK 0x00000004L +#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9__SHIFT 0x00000002 +#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9_MASK 0x00000020L +#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9__SHIFT 0x00000005 +#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9_MASK 0x00000010L +#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9__SHIFT 0x00000004 +#define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9_MASK 0x00000080L +#define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9__SHIFT 0x00000007 +#define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9_MASK 0x00000040L +#define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9__SHIFT 0x00000006 +#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9_MASK 0x0000fc00L +#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9__SHIFT 0x0000000a +#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9_MASK 0x00000300L +#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9__SHIFT 0x00000008 +#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9_MASK 0x00000080L +#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9__SHIFT 0x00000007 +#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__INCOHERENTCK_9_MASK 0x00000008L +#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__INCOHERENTCK_9__SHIFT 0x00000003 +#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9_MASK 0x00000070L +#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9__SHIFT 0x00000004 +#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9_MASK 0x00000007L +#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9__SHIFT 0x00000000 +#define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN_MASK 0x00000001L +#define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN__SHIFT 0x00000000 +#define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE_MASK 0x0000003eL +#define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE__SHIFT 0x00000001 +#define PB1_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP_MASK 0x00000f00L +#define PB1_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP__SHIFT 0x00000008 +#define PB1_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN_MASK 0x00800000L +#define PB1_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN__SHIFT 0x00000017 +#define PB1_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN_MASK 0x00400000L +#define PB1_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN__SHIFT 0x00000016 +#define PB1_DFT_JIT_INJ_REG0__DFT_NUM_STEPS_MASK 0x0000001fL +#define PB1_DFT_JIT_INJ_REG0__DFT_NUM_STEPS__SHIFT 0x00000000 +#define PB1_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME_MASK 0xff000000L +#define PB1_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME__SHIFT 0x00000018 +#define PB1_DFT_JIT_INJ_REG1__DFT_BLOCK_EN_MASK 0x00010000L +#define PB1_DFT_JIT_INJ_REG1__DFT_BLOCK_EN__SHIFT 0x00000010 +#define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_EN_MASK 0x00000100L +#define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_EN__SHIFT 0x00000008 +#define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE_MASK 0x000000ffL +#define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE__SHIFT 0x00000000 +#define PB1_DFT_JIT_INJ_REG2__DFT_LANE_EN_MASK 0x0000ffffL +#define PB1_DFT_JIT_INJ_REG2__DFT_LANE_EN__SHIFT 0x00000000 +#define PB1_GLB_CTRL_REG0__BACKUP_MASK 0x0000ffffL +#define PB1_GLB_CTRL_REG0__BACKUP__SHIFT 0x00000000 +#define PB1_GLB_CTRL_REG0__CFG_IDLEDET_TH_MASK 0x00030000L +#define PB1_GLB_CTRL_REG0__CFG_IDLEDET_TH__SHIFT 0x00000010 +#define PB1_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL_MASK 0x00700000L +#define PB1_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL__SHIFT 0x00000014 +#define PB1_GLB_CTRL_REG0__DBG_RXFEBYP_EN_MASK 0x00800000L +#define PB1_GLB_CTRL_REG0__DBG_RXFEBYP_EN__SHIFT 0x00000017 +#define PB1_GLB_CTRL_REG0__DBG_RXPRBS_CLR_MASK 0x01000000L +#define PB1_GLB_CTRL_REG0__DBG_RXPRBS_CLR__SHIFT 0x00000018 +#define PB1_GLB_CTRL_REG0__DBG_RXTOGGLE_EN_MASK 0x02000000L +#define PB1_GLB_CTRL_REG0__DBG_RXTOGGLE_EN__SHIFT 0x00000019 +#define PB1_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN_MASK 0x04000000L +#define PB1_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN__SHIFT 0x0000001a +#define PB1_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE_MASK 0xc0000000L +#define PB1_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE__SHIFT 0x0000001e +#define PB1_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV_MASK 0x80000000L +#define PB1_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV__SHIFT 0x0000001f +#define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN_MASK 0x00000001L +#define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN__SHIFT 0x00000000 +#define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL_MASK 0x0000007eL +#define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL__SHIFT 0x00000001 +#define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN_MASK 0x00000080L +#define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN__SHIFT 0x00000007 +#define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL_MASK 0x00003f00L +#define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL__SHIFT 0x00000008 +#define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN_MASK 0x00004000L +#define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN__SHIFT 0x0000000e +#define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL_MASK 0x003f8000L +#define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL__SHIFT 0x0000000f +#define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN_MASK 0x00400000L +#define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN__SHIFT 0x00000016 +#define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL_MASK 0x3f800000L +#define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL__SHIFT 0x00000017 +#define PB1_GLB_CTRL_REG1__TST_LOSPDTST_EN_MASK 0x40000000L +#define PB1_GLB_CTRL_REG1__TST_LOSPDTST_EN__SHIFT 0x0000001e +#define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN_MASK 0x00000001L +#define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN__SHIFT 0x00000000 +#define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL_MASK 0x000000feL +#define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL__SHIFT 0x00000001 +#define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN_MASK 0x00000100L +#define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN__SHIFT 0x00000008 +#define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL_MASK 0x0000fe00L +#define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL__SHIFT 0x00000009 +#define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN_MASK 0x00010000L +#define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN__SHIFT 0x00000010 +#define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL_MASK 0x00fe0000L +#define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL__SHIFT 0x00000011 +#define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN_MASK 0x01000000L +#define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN__SHIFT 0x00000018 +#define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL_MASK 0xfe000000L +#define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL__SHIFT 0x00000019 +#define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL_MASK 0x00000060L +#define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL__SHIFT 0x00000005 +#define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL_MASK 0x00000180L +#define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL__SHIFT 0x00000007 +#define PB1_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL_MASK 0x00000600L +#define PB1_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL__SHIFT 0x00000009 +#define PB1_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL_MASK 0x0001c000L +#define PB1_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL__SHIFT 0x0000000e +#define PB1_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN_MASK 0x00001000L +#define PB1_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN__SHIFT 0x0000000c +#define PB1_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN_MASK 0x00000800L +#define PB1_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN__SHIFT 0x0000000b +#define PB1_GLB_CTRL_REG3__DBG_DLL_CLK_SEL_MASK 0x001c0000L +#define PB1_GLB_CTRL_REG3__DBG_DLL_CLK_SEL__SHIFT 0x00000012 +#define PB1_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE_MASK 0x80000000L +#define PB1_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE__SHIFT 0x0000001f +#define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN_MASK 0x00400000L +#define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN__SHIFT 0x00000016 +#define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL_MASK 0x07800000L +#define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL__SHIFT 0x00000017 +#define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN_MASK 0x08000000L +#define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN__SHIFT 0x0000001b +#define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL_MASK 0x70000000L +#define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL__SHIFT 0x0000001c +#define PB1_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL_MASK 0x00200000L +#define PB1_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL__SHIFT 0x00000015 +#define PB1_GLB_CTRL_REG3__RXDBG_SEL_MASK 0x0000001fL +#define PB1_GLB_CTRL_REG3__RXDBG_SEL__SHIFT 0x00000000 +#define PB1_GLB_CTRL_REG4__DBG_RXAPU_EXEC_MASK 0x03c00000L +#define PB1_GLB_CTRL_REG4__DBG_RXAPU_EXEC__SHIFT 0x00000016 +#define PB1_GLB_CTRL_REG4__DBG_RXAPU_INST_MASK 0x0000ffffL +#define PB1_GLB_CTRL_REG4__DBG_RXAPU_INST__SHIFT 0x00000000 +#define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN_MASK 0x00040000L +#define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN__SHIFT 0x00000012 +#define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL_MASK 0x00030000L +#define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL__SHIFT 0x00000010 +#define PB1_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL_MASK 0x04000000L +#define PB1_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL__SHIFT 0x0000001a +#define PB1_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE_MASK 0x10000000L +#define PB1_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE__SHIFT 0x0000001c +#define PB1_GLB_CTRL_REG4__PWRGOOD_OVRD_MASK 0x08000000L +#define PB1_GLB_CTRL_REG4__PWRGOOD_OVRD__SHIFT 0x0000001b +#define PB1_GLB_CTRL_REG5__DBG_RXAPU_MODE_MASK 0x000000ffL +#define PB1_GLB_CTRL_REG5__DBG_RXAPU_MODE__SHIFT 0x00000000 +#define PB1_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL_MASK 0x0000ffffL +#define PB1_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL__SHIFT 0x00000000 +#define PB1_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL_MASK 0xffff0000L +#define PB1_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL__SHIFT 0x00000010 +#define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN_MASK 0x00008000L +#define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN__SHIFT 0x0000000f +#define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL_MASK 0xffff0000L +#define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL__SHIFT 0x00000010 +#define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN_MASK 0x00000004L +#define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN__SHIFT 0x00000002 +#define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL_MASK 0x00000008L +#define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL__SHIFT 0x00000003 +#define PB1_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN_MASK 0x00000001L +#define PB1_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN__SHIFT 0x00000000 +#define PB1_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN_MASK 0x00000002L +#define PB1_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN__SHIFT 0x00000001 +#define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_EN_MASK 0x00000001L +#define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_EN__SHIFT 0x00000000 +#define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL_MASK 0x00000002L +#define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL__SHIFT 0x00000001 +#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L0T3_MASK 0x00000001L +#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L0T3__SHIFT 0x00000000 +#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L12T15_MASK 0x00000008L +#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L12T15__SHIFT 0x00000003 +#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L4T7_MASK 0x00000002L +#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L4T7__SHIFT 0x00000001 +#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L8T11_MASK 0x00000004L +#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L8T11__SHIFT 0x00000002 +#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_SCI_UPDT_MASK 0x00000010L +#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_SCI_UPDT__SHIFT 0x00000004 +#define PB1_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE_MASK 0x00100000L +#define PB1_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE__SHIFT 0x00000014 +#define PB1_GLB_SCI_STAT_OVRD_REG0__RXIMP_MASK 0x000f0000L +#define PB1_GLB_SCI_STAT_OVRD_REG0__RXIMP__SHIFT 0x00000010 +#define PB1_GLB_SCI_STAT_OVRD_REG0__TXNIMP_MASK 0x00000f00L +#define PB1_GLB_SCI_STAT_OVRD_REG0__TXNIMP__SHIFT 0x00000008 +#define PB1_GLB_SCI_STAT_OVRD_REG0__TXPIMP_MASK 0x0000f000L +#define PB1_GLB_SCI_STAT_OVRD_REG0__TXPIMP__SHIFT 0x0000000c +#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0_MASK 0x00001000L +#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0__SHIFT 0x0000000c +#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1_MASK 0x00002000L +#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1__SHIFT 0x0000000d +#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2_MASK 0x00004000L +#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2__SHIFT 0x0000000e +#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3_MASK 0x00008000L +#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3__SHIFT 0x0000000f +#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0_MASK 0x000c0000L +#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0__SHIFT 0x00000012 +#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1_MASK 0x00c00000L +#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1__SHIFT 0x00000016 +#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2_MASK 0x0c000000L +#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2__SHIFT 0x0000001a +#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3_MASK 0xc0000000L +#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3__SHIFT 0x0000001e +#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_SCI_UPDT_L0T3_MASK 0x00000004L +#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_SCI_UPDT_L0T3__SHIFT 0x00000002 +#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_SCI_UPDT_L0T3_MASK 0x00000002L +#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_SCI_UPDT_L0T3__SHIFT 0x00000001 +#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_MODE_SCI_UPDT_L0T3_MASK 0x00000001L +#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_MODE_SCI_UPDT_L0T3__SHIFT 0x00000000 +#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_0_MASK 0x00030000L +#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_0__SHIFT 0x00000010 +#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_1_MASK 0x00300000L +#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_1__SHIFT 0x00000014 +#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_2_MASK 0x03000000L +#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_2__SHIFT 0x00000018 +#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_3_MASK 0x30000000L +#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_3__SHIFT 0x0000001c +#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4_MASK 0x00001000L +#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4__SHIFT 0x0000000c +#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5_MASK 0x00002000L +#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5__SHIFT 0x0000000d +#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6_MASK 0x00004000L +#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6__SHIFT 0x0000000e +#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7_MASK 0x00008000L +#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7__SHIFT 0x0000000f +#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4_MASK 0x000c0000L +#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4__SHIFT 0x00000012 +#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5_MASK 0x00c00000L +#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5__SHIFT 0x00000016 +#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6_MASK 0x0c000000L +#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6__SHIFT 0x0000001a +#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7_MASK 0xc0000000L +#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7__SHIFT 0x0000001e +#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_SCI_UPDT_L4T7_MASK 0x00000004L +#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_SCI_UPDT_L4T7__SHIFT 0x00000002 +#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_SCI_UPDT_L4T7_MASK 0x00000002L +#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_SCI_UPDT_L4T7__SHIFT 0x00000001 +#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_MODE_SCI_UPDT_L4T7_MASK 0x00000001L +#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_MODE_SCI_UPDT_L4T7__SHIFT 0x00000000 +#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_4_MASK 0x00030000L +#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_4__SHIFT 0x00000010 +#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_5_MASK 0x00300000L +#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_5__SHIFT 0x00000014 +#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_6_MASK 0x03000000L +#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_6__SHIFT 0x00000018 +#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_7_MASK 0x30000000L +#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_7__SHIFT 0x0000001c +#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10_MASK 0x00004000L +#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10__SHIFT 0x0000000e +#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11_MASK 0x00008000L +#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11__SHIFT 0x0000000f +#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8_MASK 0x00001000L +#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8__SHIFT 0x0000000c +#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9_MASK 0x00002000L +#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9__SHIFT 0x0000000d +#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10_MASK 0x0c000000L +#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10__SHIFT 0x0000001a +#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11_MASK 0xc0000000L +#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11__SHIFT 0x0000001e +#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8_MASK 0x000c0000L +#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8__SHIFT 0x00000012 +#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9_MASK 0x00c00000L +#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9__SHIFT 0x00000016 +#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_SCI_UPDT_L8T11_MASK 0x00000004L +#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_SCI_UPDT_L8T11__SHIFT 0x00000002 +#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_SCI_UPDT_L8T11_MASK 0x00000002L +#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_SCI_UPDT_L8T11__SHIFT 0x00000001 +#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_MODE_SCI_UPDT_L8T11_MASK 0x00000001L +#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_MODE_SCI_UPDT_L8T11__SHIFT 0x00000000 +#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_10_MASK 0x03000000L +#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_10__SHIFT 0x00000018 +#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_11_MASK 0x30000000L +#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_11__SHIFT 0x0000001c +#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_8_MASK 0x00030000L +#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_8__SHIFT 0x00000010 +#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_9_MASK 0x00300000L +#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_9__SHIFT 0x00000014 +#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12_MASK 0x00001000L +#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12__SHIFT 0x0000000c +#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13_MASK 0x00002000L +#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13__SHIFT 0x0000000d +#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14_MASK 0x00004000L +#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14__SHIFT 0x0000000e +#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15_MASK 0x00008000L +#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15__SHIFT 0x0000000f +#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12_MASK 0x000c0000L +#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12__SHIFT 0x00000012 +#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13_MASK 0x00c00000L +#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13__SHIFT 0x00000016 +#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14_MASK 0x0c000000L +#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14__SHIFT 0x0000001a +#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15_MASK 0xc0000000L +#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15__SHIFT 0x0000001e +#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_SCI_UPDT_L12T15_MASK 0x00000004L +#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_SCI_UPDT_L12T15__SHIFT 0x00000002 +#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_SCI_UPDT_L12T15_MASK 0x00000002L +#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_SCI_UPDT_L12T15__SHIFT 0x00000001 +#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_MODE_SCI_UPDT_L12T15_MASK 0x00000001L +#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_MODE_SCI_UPDT_L12T15__SHIFT 0x00000000 +#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_12_MASK 0x00030000L +#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_12__SHIFT 0x00000010 +#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_13_MASK 0x00300000L +#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_13__SHIFT 0x00000014 +#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_14_MASK 0x03000000L +#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_14__SHIFT 0x00000018 +#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_15_MASK 0x30000000L +#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_15__SHIFT 0x0000001c +#define PB1_HW_DEBUG__PB1_HW_00_DEBUG_MASK 0x00000001L +#define PB1_HW_DEBUG__PB1_HW_00_DEBUG__SHIFT 0x00000000 +#define PB1_HW_DEBUG__PB1_HW_01_DEBUG_MASK 0x00000002L +#define PB1_HW_DEBUG__PB1_HW_01_DEBUG__SHIFT 0x00000001 +#define PB1_HW_DEBUG__PB1_HW_02_DEBUG_MASK 0x00000004L +#define PB1_HW_DEBUG__PB1_HW_02_DEBUG__SHIFT 0x00000002 +#define PB1_HW_DEBUG__PB1_HW_03_DEBUG_MASK 0x00000008L +#define PB1_HW_DEBUG__PB1_HW_03_DEBUG__SHIFT 0x00000003 +#define PB1_HW_DEBUG__PB1_HW_04_DEBUG_MASK 0x00000010L +#define PB1_HW_DEBUG__PB1_HW_04_DEBUG__SHIFT 0x00000004 +#define PB1_HW_DEBUG__PB1_HW_05_DEBUG_MASK 0x00000020L +#define PB1_HW_DEBUG__PB1_HW_05_DEBUG__SHIFT 0x00000005 +#define PB1_HW_DEBUG__PB1_HW_06_DEBUG_MASK 0x00000040L +#define PB1_HW_DEBUG__PB1_HW_06_DEBUG__SHIFT 0x00000006 +#define PB1_HW_DEBUG__PB1_HW_07_DEBUG_MASK 0x00000080L +#define PB1_HW_DEBUG__PB1_HW_07_DEBUG__SHIFT 0x00000007 +#define PB1_HW_DEBUG__PB1_HW_08_DEBUG_MASK 0x00000100L +#define PB1_HW_DEBUG__PB1_HW_08_DEBUG__SHIFT 0x00000008 +#define PB1_HW_DEBUG__PB1_HW_09_DEBUG_MASK 0x00000200L +#define PB1_HW_DEBUG__PB1_HW_09_DEBUG__SHIFT 0x00000009 +#define PB1_HW_DEBUG__PB1_HW_10_DEBUG_MASK 0x00000400L +#define PB1_HW_DEBUG__PB1_HW_10_DEBUG__SHIFT 0x0000000a +#define PB1_HW_DEBUG__PB1_HW_11_DEBUG_MASK 0x00000800L +#define PB1_HW_DEBUG__PB1_HW_11_DEBUG__SHIFT 0x0000000b +#define PB1_HW_DEBUG__PB1_HW_12_DEBUG_MASK 0x00001000L +#define PB1_HW_DEBUG__PB1_HW_12_DEBUG__SHIFT 0x0000000c +#define PB1_HW_DEBUG__PB1_HW_13_DEBUG_MASK 0x00002000L +#define PB1_HW_DEBUG__PB1_HW_13_DEBUG__SHIFT 0x0000000d +#define PB1_HW_DEBUG__PB1_HW_14_DEBUG_MASK 0x00004000L +#define PB1_HW_DEBUG__PB1_HW_14_DEBUG__SHIFT 0x0000000e +#define PB1_HW_DEBUG__PB1_HW_15_DEBUG_MASK 0x00008000L +#define PB1_HW_DEBUG__PB1_HW_15_DEBUG__SHIFT 0x0000000f +#define PB1_HW_DEBUG__PB1_HW_16_DEBUG_MASK 0x00010000L +#define PB1_HW_DEBUG__PB1_HW_16_DEBUG__SHIFT 0x00000010 +#define PB1_HW_DEBUG__PB1_HW_17_DEBUG_MASK 0x00020000L +#define PB1_HW_DEBUG__PB1_HW_17_DEBUG__SHIFT 0x00000011 +#define PB1_HW_DEBUG__PB1_HW_18_DEBUG_MASK 0x00040000L +#define PB1_HW_DEBUG__PB1_HW_18_DEBUG__SHIFT 0x00000012 +#define PB1_HW_DEBUG__PB1_HW_19_DEBUG_MASK 0x00080000L +#define PB1_HW_DEBUG__PB1_HW_19_DEBUG__SHIFT 0x00000013 +#define PB1_HW_DEBUG__PB1_HW_20_DEBUG_MASK 0x00100000L +#define PB1_HW_DEBUG__PB1_HW_20_DEBUG__SHIFT 0x00000014 +#define PB1_HW_DEBUG__PB1_HW_21_DEBUG_MASK 0x00200000L +#define PB1_HW_DEBUG__PB1_HW_21_DEBUG__SHIFT 0x00000015 +#define PB1_HW_DEBUG__PB1_HW_22_DEBUG_MASK 0x00400000L +#define PB1_HW_DEBUG__PB1_HW_22_DEBUG__SHIFT 0x00000016 +#define PB1_HW_DEBUG__PB1_HW_23_DEBUG_MASK 0x00800000L +#define PB1_HW_DEBUG__PB1_HW_23_DEBUG__SHIFT 0x00000017 +#define PB1_HW_DEBUG__PB1_HW_24_DEBUG_MASK 0x01000000L +#define PB1_HW_DEBUG__PB1_HW_24_DEBUG__SHIFT 0x00000018 +#define PB1_HW_DEBUG__PB1_HW_25_DEBUG_MASK 0x02000000L +#define PB1_HW_DEBUG__PB1_HW_25_DEBUG__SHIFT 0x00000019 +#define PB1_HW_DEBUG__PB1_HW_26_DEBUG_MASK 0x04000000L +#define PB1_HW_DEBUG__PB1_HW_26_DEBUG__SHIFT 0x0000001a +#define PB1_HW_DEBUG__PB1_HW_27_DEBUG_MASK 0x08000000L +#define PB1_HW_DEBUG__PB1_HW_27_DEBUG__SHIFT 0x0000001b +#define PB1_HW_DEBUG__PB1_HW_28_DEBUG_MASK 0x10000000L +#define PB1_HW_DEBUG__PB1_HW_28_DEBUG__SHIFT 0x0000001c +#define PB1_HW_DEBUG__PB1_HW_29_DEBUG_MASK 0x20000000L +#define PB1_HW_DEBUG__PB1_HW_29_DEBUG__SHIFT 0x0000001d +#define PB1_HW_DEBUG__PB1_HW_30_DEBUG_MASK 0x40000000L +#define PB1_HW_DEBUG__PB1_HW_30_DEBUG__SHIFT 0x0000001e +#define PB1_HW_DEBUG__PB1_HW_31_DEBUG_MASK 0x80000000L +#define PB1_HW_DEBUG__PB1_HW_31_DEBUG__SHIFT 0x0000001f +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_EN_MASK 0x00000080L +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_EN__SHIFT 0x00000007 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_0_MASK 0x00000100L +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_0__SHIFT 0x00000008 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_10_MASK 0x00040000L +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_10__SHIFT 0x00000012 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_11_MASK 0x00080000L +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_11__SHIFT 0x00000013 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_12_MASK 0x00100000L +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_12__SHIFT 0x00000014 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_13_MASK 0x00200000L +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_13__SHIFT 0x00000015 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_14_MASK 0x00400000L +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_14__SHIFT 0x00000016 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_15_MASK 0x00800000L +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_15__SHIFT 0x00000017 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_1_MASK 0x00000200L +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_1__SHIFT 0x00000009 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_2_MASK 0x00000400L +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_2__SHIFT 0x0000000a +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_3_MASK 0x00000800L +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_3__SHIFT 0x0000000b +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_4_MASK 0x00001000L +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_4__SHIFT 0x0000000c +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_5_MASK 0x00002000L +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_5__SHIFT 0x0000000d +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_6_MASK 0x00004000L +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_6__SHIFT 0x0000000e +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_7_MASK 0x00008000L +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_7__SHIFT 0x0000000f +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_8_MASK 0x00010000L +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_8__SHIFT 0x00000010 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_9_MASK 0x00020000L +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_9__SHIFT 0x00000011 +#define PB1_PIF_CNTL2__RXDETECT_SAMPL_TIME_MASK 0x00000006L +#define PB1_PIF_CNTL2__RXDETECT_SAMPL_TIME__SHIFT 0x00000001 +#define PB1_PIF_CNTL2__RXPHYSTATUS_DELAY_MASK 0x07000000L +#define PB1_PIF_CNTL2__RXPHYSTATUS_DELAY__SHIFT 0x00000018 +#define PB1_PIF_CNTL__DA_FIFO_RESET_0_MASK 0x00000002L +#define PB1_PIF_CNTL__DA_FIFO_RESET_0__SHIFT 0x00000001 +#define PB1_PIF_CNTL__DA_FIFO_RESET_1_MASK 0x00000020L +#define PB1_PIF_CNTL__DA_FIFO_RESET_1__SHIFT 0x00000005 +#define PB1_PIF_CNTL__DA_FIFO_RESET_2_MASK 0x00000200L +#define PB1_PIF_CNTL__DA_FIFO_RESET_2__SHIFT 0x00000009 +#define PB1_PIF_CNTL__DA_FIFO_RESET_3_MASK 0x00002000L +#define PB1_PIF_CNTL__DA_FIFO_RESET_3__SHIFT 0x0000000d +#define PB1_PIF_CNTL__DIVINIT_MODE_MASK 0x00000100L +#define PB1_PIF_CNTL__DIVINIT_MODE__SHIFT 0x00000008 +#define PB1_PIF_CNTL__EI_CYCLE_OFF_TIME_MASK 0x00700000L +#define PB1_PIF_CNTL__EI_CYCLE_OFF_TIME__SHIFT 0x00000014 +#define PB1_PIF_CNTL__EI_DET_CYCLE_MODE_MASK 0x00000010L +#define PB1_PIF_CNTL__EI_DET_CYCLE_MODE__SHIFT 0x00000004 +#define PB1_PIF_CNTL__EXIT_L0S_INIT_DIS_MASK 0x00800000L +#define PB1_PIF_CNTL__EXIT_L0S_INIT_DIS__SHIFT 0x00000017 +#define PB1_PIF_CNTL__EXTEND_WAIT_FOR_RAMPUP_MASK 0x10000000L +#define PB1_PIF_CNTL__EXTEND_WAIT_FOR_RAMPUP__SHIFT 0x0000001c +#define PB1_PIF_CNTL__IGNORE_TxDataValid_EP_DIS_MASK 0x20000000L +#define PB1_PIF_CNTL__IGNORE_TxDataValid_EP_DIS__SHIFT 0x0000001d +#define PB1_PIF_CNTL__LS2_EXIT_TIME_MASK 0x000e0000L +#define PB1_PIF_CNTL__LS2_EXIT_TIME__SHIFT 0x00000011 +#define PB1_PIF_CNTL__PHYCMD_CR_EN_MODE_MASK 0x00000008L +#define PB1_PIF_CNTL__PHYCMD_CR_EN_MODE__SHIFT 0x00000003 +#define PB1_PIF_CNTL__PHY_CR_EN_MODE_MASK 0x00000004L +#define PB1_PIF_CNTL__PHY_CR_EN_MODE__SHIFT 0x00000002 +#define PB1_PIF_CNTL__PLL_BINDING_ENABLE_MASK 0x00000400L +#define PB1_PIF_CNTL__PLL_BINDING_ENABLE__SHIFT 0x0000000a +#define PB1_PIF_CNTL__RXDETECT_FIFO_RESET_MODE_MASK 0x00000040L +#define PB1_PIF_CNTL__RXDETECT_FIFO_RESET_MODE__SHIFT 0x00000006 +#define PB1_PIF_CNTL__RXDETECT_TX_PWR_MODE_MASK 0x00000080L +#define PB1_PIF_CNTL__RXDETECT_TX_PWR_MODE__SHIFT 0x00000007 +#define PB1_PIF_CNTL__RXEN_GATER_MASK 0x0f000000L +#define PB1_PIF_CNTL__RXEN_GATER__SHIFT 0x00000018 +#define PB1_PIF_CNTL__SC_CALIB_DONE_CNTL_MASK 0x00000800L +#define PB1_PIF_CNTL__SC_CALIB_DONE_CNTL__SHIFT 0x0000000b +#define PB1_PIF_CNTL__SERIAL_CFG_ENABLE_MASK 0x00000001L +#define PB1_PIF_CNTL__SERIAL_CFG_ENABLE__SHIFT 0x00000000 +#define PB1_PIF_CNTL__TXGND_TIME_MASK 0x00010000L +#define PB1_PIF_CNTL__TXGND_TIME__SHIFT 0x00000010 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_00_DEBUG_MASK 0x00000001L +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_00_DEBUG__SHIFT 0x00000000 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_01_DEBUG_MASK 0x00000002L +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_01_DEBUG__SHIFT 0x00000001 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_02_DEBUG_MASK 0x00000004L +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_02_DEBUG__SHIFT 0x00000002 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_03_DEBUG_MASK 0x00000008L +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_03_DEBUG__SHIFT 0x00000003 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_04_DEBUG_MASK 0x00000010L +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_04_DEBUG__SHIFT 0x00000004 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_05_DEBUG_MASK 0x00000020L +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_05_DEBUG__SHIFT 0x00000005 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_06_DEBUG_MASK 0x00000040L +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_06_DEBUG__SHIFT 0x00000006 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_07_DEBUG_MASK 0x00000080L +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_07_DEBUG__SHIFT 0x00000007 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_08_DEBUG_MASK 0x00000100L +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_08_DEBUG__SHIFT 0x00000008 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_09_DEBUG_MASK 0x00000200L +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_09_DEBUG__SHIFT 0x00000009 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_10_DEBUG_MASK 0x00000400L +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_10_DEBUG__SHIFT 0x0000000a +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_11_DEBUG_MASK 0x00000800L +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_11_DEBUG__SHIFT 0x0000000b +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_12_DEBUG_MASK 0x00001000L +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_12_DEBUG__SHIFT 0x0000000c +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_13_DEBUG_MASK 0x00002000L +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_13_DEBUG__SHIFT 0x0000000d +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_14_DEBUG_MASK 0x00004000L +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_14_DEBUG__SHIFT 0x0000000e +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_15_DEBUG_MASK 0x00008000L +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_15_DEBUG__SHIFT 0x0000000f +#define PB1_PIF_PAIRING__MULTI_PIF_MASK 0x02000000L +#define PB1_PIF_PAIRING__MULTI_PIF__SHIFT 0x00000019 +#define PB1_PIF_PAIRING__X16_LANE_15_0_MASK 0x00100000L +#define PB1_PIF_PAIRING__X16_LANE_15_0__SHIFT 0x00000014 +#define PB1_PIF_PAIRING__X2_LANE_1_0_MASK 0x00000001L +#define PB1_PIF_PAIRING__X2_LANE_1_0__SHIFT 0x00000000 +#define PB1_PIF_PAIRING__X2_LANE_11_10_MASK 0x00000020L +#define PB1_PIF_PAIRING__X2_LANE_11_10__SHIFT 0x00000005 +#define PB1_PIF_PAIRING__X2_LANE_13_12_MASK 0x00000040L +#define PB1_PIF_PAIRING__X2_LANE_13_12__SHIFT 0x00000006 +#define PB1_PIF_PAIRING__X2_LANE_15_14_MASK 0x00000080L +#define PB1_PIF_PAIRING__X2_LANE_15_14__SHIFT 0x00000007 +#define PB1_PIF_PAIRING__X2_LANE_3_2_MASK 0x00000002L +#define PB1_PIF_PAIRING__X2_LANE_3_2__SHIFT 0x00000001 +#define PB1_PIF_PAIRING__X2_LANE_5_4_MASK 0x00000004L +#define PB1_PIF_PAIRING__X2_LANE_5_4__SHIFT 0x00000002 +#define PB1_PIF_PAIRING__X2_LANE_7_6_MASK 0x00000008L +#define PB1_PIF_PAIRING__X2_LANE_7_6__SHIFT 0x00000003 +#define PB1_PIF_PAIRING__X2_LANE_9_8_MASK 0x00000010L +#define PB1_PIF_PAIRING__X2_LANE_9_8__SHIFT 0x00000004 +#define PB1_PIF_PAIRING__X4_LANE_11_8_MASK 0x00000400L +#define PB1_PIF_PAIRING__X4_LANE_11_8__SHIFT 0x0000000a +#define PB1_PIF_PAIRING__X4_LANE_15_12_MASK 0x00000800L +#define PB1_PIF_PAIRING__X4_LANE_15_12__SHIFT 0x0000000b +#define PB1_PIF_PAIRING__X4_LANE_3_0_MASK 0x00000100L +#define PB1_PIF_PAIRING__X4_LANE_3_0__SHIFT 0x00000008 +#define PB1_PIF_PAIRING__X4_LANE_7_4_MASK 0x00000200L +#define PB1_PIF_PAIRING__X4_LANE_7_4__SHIFT 0x00000009 +#define PB1_PIF_PAIRING__X8_LANE_15_8_MASK 0x00020000L +#define PB1_PIF_PAIRING__X8_LANE_15_8__SHIFT 0x00000011 +#define PB1_PIF_PAIRING__X8_LANE_7_0_MASK 0x00010000L +#define PB1_PIF_PAIRING__X8_LANE_7_0__SHIFT 0x00000010 +#define PB1_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_EN_0_MASK 0x00000100L +#define PB1_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_EN_0__SHIFT 0x00000008 +#define PB1_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_VAL_0_MASK 0x00000200L +#define PB1_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_VAL_0__SHIFT 0x00000009 +#define PB1_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_EN_0_MASK 0x00000010L +#define PB1_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_EN_0__SHIFT 0x00000004 +#define PB1_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_VAL_0_MASK 0x000000e0L +#define PB1_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_VAL_0__SHIFT 0x00000005 +#define PB1_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_EN_0_MASK 0x00004000L +#define PB1_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_EN_0__SHIFT 0x0000000e +#define PB1_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_VAL_0_MASK 0x00038000L +#define PB1_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_VAL_0__SHIFT 0x0000000f +#define PB1_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_EN_0_MASK 0x00000001L +#define PB1_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_EN_0__SHIFT 0x00000000 +#define PB1_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_VAL_0_MASK 0x0000000eL +#define PB1_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_VAL_0__SHIFT 0x00000001 +#define PB1_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_EN_0_MASK 0x00000400L +#define PB1_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_EN_0__SHIFT 0x0000000a +#define PB1_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_VAL_0_MASK 0x00003800L +#define PB1_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_VAL_0__SHIFT 0x0000000b +#define PB1_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_EN_10_MASK 0x00000100L +#define PB1_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_EN_10__SHIFT 0x00000008 +#define PB1_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_VAL_10_MASK 0x00000200L +#define PB1_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_VAL_10__SHIFT 0x00000009 +#define PB1_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_EN_10_MASK 0x00000010L +#define PB1_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_EN_10__SHIFT 0x00000004 +#define PB1_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_VAL_10_MASK 0x000000e0L +#define PB1_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_VAL_10__SHIFT 0x00000005 +#define PB1_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_EN_10_MASK 0x00004000L +#define PB1_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_EN_10__SHIFT 0x0000000e +#define PB1_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_VAL_10_MASK 0x00038000L +#define PB1_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_VAL_10__SHIFT 0x0000000f +#define PB1_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_EN_10_MASK 0x00000001L +#define PB1_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_EN_10__SHIFT 0x00000000 +#define PB1_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_VAL_10_MASK 0x0000000eL +#define PB1_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_VAL_10__SHIFT 0x00000001 +#define PB1_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_EN_10_MASK 0x00000400L +#define PB1_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_EN_10__SHIFT 0x0000000a +#define PB1_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_VAL_10_MASK 0x00003800L +#define PB1_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_VAL_10__SHIFT 0x0000000b +#define PB1_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_EN_11_MASK 0x00000100L +#define PB1_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_EN_11__SHIFT 0x00000008 +#define PB1_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_VAL_11_MASK 0x00000200L +#define PB1_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_VAL_11__SHIFT 0x00000009 +#define PB1_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_EN_11_MASK 0x00000010L +#define PB1_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_EN_11__SHIFT 0x00000004 +#define PB1_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_VAL_11_MASK 0x000000e0L +#define PB1_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_VAL_11__SHIFT 0x00000005 +#define PB1_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_EN_11_MASK 0x00004000L +#define PB1_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_EN_11__SHIFT 0x0000000e +#define PB1_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_VAL_11_MASK 0x00038000L +#define PB1_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_VAL_11__SHIFT 0x0000000f +#define PB1_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_EN_11_MASK 0x00000001L +#define PB1_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_EN_11__SHIFT 0x00000000 +#define PB1_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_VAL_11_MASK 0x0000000eL +#define PB1_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_VAL_11__SHIFT 0x00000001 +#define PB1_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_EN_11_MASK 0x00000400L +#define PB1_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_EN_11__SHIFT 0x0000000a +#define PB1_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_VAL_11_MASK 0x00003800L +#define PB1_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_VAL_11__SHIFT 0x0000000b +#define PB1_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_EN_12_MASK 0x00000100L +#define PB1_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_EN_12__SHIFT 0x00000008 +#define PB1_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_VAL_12_MASK 0x00000200L +#define PB1_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_VAL_12__SHIFT 0x00000009 +#define PB1_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_EN_12_MASK 0x00000010L +#define PB1_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_EN_12__SHIFT 0x00000004 +#define PB1_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_VAL_12_MASK 0x000000e0L +#define PB1_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_VAL_12__SHIFT 0x00000005 +#define PB1_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_EN_12_MASK 0x00004000L +#define PB1_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_EN_12__SHIFT 0x0000000e +#define PB1_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_VAL_12_MASK 0x00038000L +#define PB1_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_VAL_12__SHIFT 0x0000000f +#define PB1_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_EN_12_MASK 0x00000001L +#define PB1_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_EN_12__SHIFT 0x00000000 +#define PB1_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_VAL_12_MASK 0x0000000eL +#define PB1_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_VAL_12__SHIFT 0x00000001 +#define PB1_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_EN_12_MASK 0x00000400L +#define PB1_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_EN_12__SHIFT 0x0000000a +#define PB1_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_VAL_12_MASK 0x00003800L +#define PB1_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_VAL_12__SHIFT 0x0000000b +#define PB1_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_EN_13_MASK 0x00000100L +#define PB1_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_EN_13__SHIFT 0x00000008 +#define PB1_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_VAL_13_MASK 0x00000200L +#define PB1_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_VAL_13__SHIFT 0x00000009 +#define PB1_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_EN_13_MASK 0x00000010L +#define PB1_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_EN_13__SHIFT 0x00000004 +#define PB1_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_VAL_13_MASK 0x000000e0L +#define PB1_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_VAL_13__SHIFT 0x00000005 +#define PB1_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_EN_13_MASK 0x00004000L +#define PB1_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_EN_13__SHIFT 0x0000000e +#define PB1_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_VAL_13_MASK 0x00038000L +#define PB1_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_VAL_13__SHIFT 0x0000000f +#define PB1_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_EN_13_MASK 0x00000001L +#define PB1_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_EN_13__SHIFT 0x00000000 +#define PB1_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_VAL_13_MASK 0x0000000eL +#define PB1_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_VAL_13__SHIFT 0x00000001 +#define PB1_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_EN_13_MASK 0x00000400L +#define PB1_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_EN_13__SHIFT 0x0000000a +#define PB1_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_VAL_13_MASK 0x00003800L +#define PB1_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_VAL_13__SHIFT 0x0000000b +#define PB1_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_EN_14_MASK 0x00000100L +#define PB1_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_EN_14__SHIFT 0x00000008 +#define PB1_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_VAL_14_MASK 0x00000200L +#define PB1_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_VAL_14__SHIFT 0x00000009 +#define PB1_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_EN_14_MASK 0x00000010L +#define PB1_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_EN_14__SHIFT 0x00000004 +#define PB1_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_VAL_14_MASK 0x000000e0L +#define PB1_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_VAL_14__SHIFT 0x00000005 +#define PB1_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_EN_14_MASK 0x00004000L +#define PB1_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_EN_14__SHIFT 0x0000000e +#define PB1_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_VAL_14_MASK 0x00038000L +#define PB1_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_VAL_14__SHIFT 0x0000000f +#define PB1_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_EN_14_MASK 0x00000001L +#define PB1_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_EN_14__SHIFT 0x00000000 +#define PB1_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_VAL_14_MASK 0x0000000eL +#define PB1_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_VAL_14__SHIFT 0x00000001 +#define PB1_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_EN_14_MASK 0x00000400L +#define PB1_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_EN_14__SHIFT 0x0000000a +#define PB1_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_VAL_14_MASK 0x00003800L +#define PB1_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_VAL_14__SHIFT 0x0000000b +#define PB1_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_EN_15_MASK 0x00000100L +#define PB1_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_EN_15__SHIFT 0x00000008 +#define PB1_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_VAL_15_MASK 0x00000200L +#define PB1_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_VAL_15__SHIFT 0x00000009 +#define PB1_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_EN_15_MASK 0x00000010L +#define PB1_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_EN_15__SHIFT 0x00000004 +#define PB1_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_VAL_15_MASK 0x000000e0L +#define PB1_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_VAL_15__SHIFT 0x00000005 +#define PB1_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_EN_15_MASK 0x00004000L +#define PB1_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_EN_15__SHIFT 0x0000000e +#define PB1_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_VAL_15_MASK 0x00038000L +#define PB1_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_VAL_15__SHIFT 0x0000000f +#define PB1_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_EN_15_MASK 0x00000001L +#define PB1_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_EN_15__SHIFT 0x00000000 +#define PB1_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_VAL_15_MASK 0x0000000eL +#define PB1_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_VAL_15__SHIFT 0x00000001 +#define PB1_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_EN_15_MASK 0x00000400L +#define PB1_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_EN_15__SHIFT 0x0000000a +#define PB1_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_VAL_15_MASK 0x00003800L +#define PB1_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_VAL_15__SHIFT 0x0000000b +#define PB1_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_EN_1_MASK 0x00000100L +#define PB1_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_EN_1__SHIFT 0x00000008 +#define PB1_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_VAL_1_MASK 0x00000200L +#define PB1_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_VAL_1__SHIFT 0x00000009 +#define PB1_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_EN_1_MASK 0x00000010L +#define PB1_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_EN_1__SHIFT 0x00000004 +#define PB1_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_VAL_1_MASK 0x000000e0L +#define PB1_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_VAL_1__SHIFT 0x00000005 +#define PB1_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_EN_1_MASK 0x00004000L +#define PB1_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_EN_1__SHIFT 0x0000000e +#define PB1_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_VAL_1_MASK 0x00038000L +#define PB1_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_VAL_1__SHIFT 0x0000000f +#define PB1_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_EN_1_MASK 0x00000001L +#define PB1_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_EN_1__SHIFT 0x00000000 +#define PB1_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_VAL_1_MASK 0x0000000eL +#define PB1_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_VAL_1__SHIFT 0x00000001 +#define PB1_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_EN_1_MASK 0x00000400L +#define PB1_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_EN_1__SHIFT 0x0000000a +#define PB1_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_VAL_1_MASK 0x00003800L +#define PB1_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_VAL_1__SHIFT 0x0000000b +#define PB1_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_EN_2_MASK 0x00000100L +#define PB1_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_EN_2__SHIFT 0x00000008 +#define PB1_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_VAL_2_MASK 0x00000200L +#define PB1_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_VAL_2__SHIFT 0x00000009 +#define PB1_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_EN_2_MASK 0x00000010L +#define PB1_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_EN_2__SHIFT 0x00000004 +#define PB1_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_VAL_2_MASK 0x000000e0L +#define PB1_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_VAL_2__SHIFT 0x00000005 +#define PB1_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_EN_2_MASK 0x00004000L +#define PB1_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_EN_2__SHIFT 0x0000000e +#define PB1_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_VAL_2_MASK 0x00038000L +#define PB1_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_VAL_2__SHIFT 0x0000000f +#define PB1_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_EN_2_MASK 0x00000001L +#define PB1_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_EN_2__SHIFT 0x00000000 +#define PB1_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_VAL_2_MASK 0x0000000eL +#define PB1_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_VAL_2__SHIFT 0x00000001 +#define PB1_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_EN_2_MASK 0x00000400L +#define PB1_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_EN_2__SHIFT 0x0000000a +#define PB1_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_VAL_2_MASK 0x00003800L +#define PB1_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_VAL_2__SHIFT 0x0000000b +#define PB1_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_EN_3_MASK 0x00000100L +#define PB1_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_EN_3__SHIFT 0x00000008 +#define PB1_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_VAL_3_MASK 0x00000200L +#define PB1_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_VAL_3__SHIFT 0x00000009 +#define PB1_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_EN_3_MASK 0x00000010L +#define PB1_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_EN_3__SHIFT 0x00000004 +#define PB1_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_VAL_3_MASK 0x000000e0L +#define PB1_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_VAL_3__SHIFT 0x00000005 +#define PB1_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_EN_3_MASK 0x00004000L +#define PB1_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_EN_3__SHIFT 0x0000000e +#define PB1_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_VAL_3_MASK 0x00038000L +#define PB1_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_VAL_3__SHIFT 0x0000000f +#define PB1_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_EN_3_MASK 0x00000001L +#define PB1_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_EN_3__SHIFT 0x00000000 +#define PB1_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_VAL_3_MASK 0x0000000eL +#define PB1_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_VAL_3__SHIFT 0x00000001 +#define PB1_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_EN_3_MASK 0x00000400L +#define PB1_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_EN_3__SHIFT 0x0000000a +#define PB1_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_VAL_3_MASK 0x00003800L +#define PB1_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_VAL_3__SHIFT 0x0000000b +#define PB1_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_EN_4_MASK 0x00000100L +#define PB1_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_EN_4__SHIFT 0x00000008 +#define PB1_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_VAL_4_MASK 0x00000200L +#define PB1_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_VAL_4__SHIFT 0x00000009 +#define PB1_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_EN_4_MASK 0x00000010L +#define PB1_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_EN_4__SHIFT 0x00000004 +#define PB1_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_VAL_4_MASK 0x000000e0L +#define PB1_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_VAL_4__SHIFT 0x00000005 +#define PB1_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_EN_4_MASK 0x00004000L +#define PB1_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_EN_4__SHIFT 0x0000000e +#define PB1_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_VAL_4_MASK 0x00038000L +#define PB1_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_VAL_4__SHIFT 0x0000000f +#define PB1_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_EN_4_MASK 0x00000001L +#define PB1_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_EN_4__SHIFT 0x00000000 +#define PB1_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_VAL_4_MASK 0x0000000eL +#define PB1_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_VAL_4__SHIFT 0x00000001 +#define PB1_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_EN_4_MASK 0x00000400L +#define PB1_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_EN_4__SHIFT 0x0000000a +#define PB1_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_VAL_4_MASK 0x00003800L +#define PB1_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_VAL_4__SHIFT 0x0000000b +#define PB1_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_EN_5_MASK 0x00000100L +#define PB1_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_EN_5__SHIFT 0x00000008 +#define PB1_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_VAL_5_MASK 0x00000200L +#define PB1_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_VAL_5__SHIFT 0x00000009 +#define PB1_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_EN_5_MASK 0x00000010L +#define PB1_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_EN_5__SHIFT 0x00000004 +#define PB1_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_VAL_5_MASK 0x000000e0L +#define PB1_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_VAL_5__SHIFT 0x00000005 +#define PB1_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_EN_5_MASK 0x00004000L +#define PB1_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_EN_5__SHIFT 0x0000000e +#define PB1_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_VAL_5_MASK 0x00038000L +#define PB1_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_VAL_5__SHIFT 0x0000000f +#define PB1_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_EN_5_MASK 0x00000001L +#define PB1_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_EN_5__SHIFT 0x00000000 +#define PB1_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_VAL_5_MASK 0x0000000eL +#define PB1_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_VAL_5__SHIFT 0x00000001 +#define PB1_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_EN_5_MASK 0x00000400L +#define PB1_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_EN_5__SHIFT 0x0000000a +#define PB1_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_VAL_5_MASK 0x00003800L +#define PB1_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_VAL_5__SHIFT 0x0000000b +#define PB1_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_EN_6_MASK 0x00000100L +#define PB1_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_EN_6__SHIFT 0x00000008 +#define PB1_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_VAL_6_MASK 0x00000200L +#define PB1_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_VAL_6__SHIFT 0x00000009 +#define PB1_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_EN_6_MASK 0x00000010L +#define PB1_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_EN_6__SHIFT 0x00000004 +#define PB1_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_VAL_6_MASK 0x000000e0L +#define PB1_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_VAL_6__SHIFT 0x00000005 +#define PB1_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_EN_6_MASK 0x00004000L +#define PB1_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_EN_6__SHIFT 0x0000000e +#define PB1_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_VAL_6_MASK 0x00038000L +#define PB1_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_VAL_6__SHIFT 0x0000000f +#define PB1_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_EN_6_MASK 0x00000001L +#define PB1_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_EN_6__SHIFT 0x00000000 +#define PB1_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_VAL_6_MASK 0x0000000eL +#define PB1_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_VAL_6__SHIFT 0x00000001 +#define PB1_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_EN_6_MASK 0x00000400L +#define PB1_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_EN_6__SHIFT 0x0000000a +#define PB1_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_VAL_6_MASK 0x00003800L +#define PB1_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_VAL_6__SHIFT 0x0000000b +#define PB1_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_EN_7_MASK 0x00000100L +#define PB1_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_EN_7__SHIFT 0x00000008 +#define PB1_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_VAL_7_MASK 0x00000200L +#define PB1_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_VAL_7__SHIFT 0x00000009 +#define PB1_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_EN_7_MASK 0x00000010L +#define PB1_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_EN_7__SHIFT 0x00000004 +#define PB1_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_VAL_7_MASK 0x000000e0L +#define PB1_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_VAL_7__SHIFT 0x00000005 +#define PB1_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_EN_7_MASK 0x00004000L +#define PB1_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_EN_7__SHIFT 0x0000000e +#define PB1_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_VAL_7_MASK 0x00038000L +#define PB1_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_VAL_7__SHIFT 0x0000000f +#define PB1_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_EN_7_MASK 0x00000001L +#define PB1_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_EN_7__SHIFT 0x00000000 +#define PB1_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_VAL_7_MASK 0x0000000eL +#define PB1_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_VAL_7__SHIFT 0x00000001 +#define PB1_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_EN_7_MASK 0x00000400L +#define PB1_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_EN_7__SHIFT 0x0000000a +#define PB1_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_VAL_7_MASK 0x00003800L +#define PB1_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_VAL_7__SHIFT 0x0000000b +#define PB1_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_EN_8_MASK 0x00000100L +#define PB1_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_EN_8__SHIFT 0x00000008 +#define PB1_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_VAL_8_MASK 0x00000200L +#define PB1_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_VAL_8__SHIFT 0x00000009 +#define PB1_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_EN_8_MASK 0x00000010L +#define PB1_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_EN_8__SHIFT 0x00000004 +#define PB1_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_VAL_8_MASK 0x000000e0L +#define PB1_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_VAL_8__SHIFT 0x00000005 +#define PB1_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_EN_8_MASK 0x00004000L +#define PB1_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_EN_8__SHIFT 0x0000000e +#define PB1_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_VAL_8_MASK 0x00038000L +#define PB1_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_VAL_8__SHIFT 0x0000000f +#define PB1_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_EN_8_MASK 0x00000001L +#define PB1_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_EN_8__SHIFT 0x00000000 +#define PB1_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_VAL_8_MASK 0x0000000eL +#define PB1_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_VAL_8__SHIFT 0x00000001 +#define PB1_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_EN_8_MASK 0x00000400L +#define PB1_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_EN_8__SHIFT 0x0000000a +#define PB1_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_VAL_8_MASK 0x00003800L +#define PB1_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_VAL_8__SHIFT 0x0000000b +#define PB1_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_EN_9_MASK 0x00000100L +#define PB1_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_EN_9__SHIFT 0x00000008 +#define PB1_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_VAL_9_MASK 0x00000200L +#define PB1_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_VAL_9__SHIFT 0x00000009 +#define PB1_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_EN_9_MASK 0x00000010L +#define PB1_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_EN_9__SHIFT 0x00000004 +#define PB1_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_VAL_9_MASK 0x000000e0L +#define PB1_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_VAL_9__SHIFT 0x00000005 +#define PB1_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_EN_9_MASK 0x00004000L +#define PB1_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_EN_9__SHIFT 0x0000000e +#define PB1_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_VAL_9_MASK 0x00038000L +#define PB1_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_VAL_9__SHIFT 0x0000000f +#define PB1_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_EN_9_MASK 0x00000001L +#define PB1_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_EN_9__SHIFT 0x00000000 +#define PB1_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_VAL_9_MASK 0x0000000eL +#define PB1_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_VAL_9__SHIFT 0x00000001 +#define PB1_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_EN_9_MASK 0x00000400L +#define PB1_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_EN_9__SHIFT 0x0000000a +#define PB1_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_VAL_9_MASK 0x00003800L +#define PB1_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_VAL_9__SHIFT 0x0000000b +#define PB1_PIF_PWRDOWN_0__FORCE_RXEN_IN_L0s_0_MASK 0x00000008L +#define PB1_PIF_PWRDOWN_0__FORCE_RXEN_IN_L0s_0__SHIFT 0x00000003 +#define PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK 0x00001c00L +#define PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT 0x0000000a +#define PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK 0x00000380L +#define PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT 0x00000007 +#define PB1_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_EN_0_MASK 0x10000000L +#define PB1_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_EN_0__SHIFT 0x0000001c +#define PB1_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_VAL_0_MASK 0xe0000000L +#define PB1_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_VAL_0__SHIFT 0x0000001d +#define PB1_PIF_PWRDOWN_0__PLL_RAMP_UP_TIME_0_MASK 0x07000000L +#define PB1_PIF_PWRDOWN_0__PLL_RAMP_UP_TIME_0__SHIFT 0x00000018 +#define PB1_PIF_PWRDOWN_0__RX_POWER_STATE_IN_RXS2_0_MASK 0x00000070L +#define PB1_PIF_PWRDOWN_0__RX_POWER_STATE_IN_RXS2_0__SHIFT 0x00000004 +#define PB1_PIF_PWRDOWN_0__TX2P5CLK_CLOCK_GATING_EN_0_MASK 0x00010000L +#define PB1_PIF_PWRDOWN_0__TX2P5CLK_CLOCK_GATING_EN_0__SHIFT 0x00000010 +#define PB1_PIF_PWRDOWN_0__TX_POWER_STATE_IN_TXS2_0_MASK 0x00000007L +#define PB1_PIF_PWRDOWN_0__TX_POWER_STATE_IN_TXS2_0__SHIFT 0x00000000 +#define PB1_PIF_PWRDOWN_1__FORCE_RXEN_IN_L0s_1_MASK 0x00000008L +#define PB1_PIF_PWRDOWN_1__FORCE_RXEN_IN_L0s_1__SHIFT 0x00000003 +#define PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK 0x00001c00L +#define PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT 0x0000000a +#define PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK 0x00000380L +#define PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT 0x00000007 +#define PB1_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_EN_1_MASK 0x10000000L +#define PB1_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_EN_1__SHIFT 0x0000001c +#define PB1_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_VAL_1_MASK 0xe0000000L +#define PB1_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_VAL_1__SHIFT 0x0000001d +#define PB1_PIF_PWRDOWN_1__PLL_RAMP_UP_TIME_1_MASK 0x07000000L +#define PB1_PIF_PWRDOWN_1__PLL_RAMP_UP_TIME_1__SHIFT 0x00000018 +#define PB1_PIF_PWRDOWN_1__RX_POWER_STATE_IN_RXS2_1_MASK 0x00000070L +#define PB1_PIF_PWRDOWN_1__RX_POWER_STATE_IN_RXS2_1__SHIFT 0x00000004 +#define PB1_PIF_PWRDOWN_1__TX2P5CLK_CLOCK_GATING_EN_1_MASK 0x00010000L +#define PB1_PIF_PWRDOWN_1__TX2P5CLK_CLOCK_GATING_EN_1__SHIFT 0x00000010 +#define PB1_PIF_PWRDOWN_1__TX_POWER_STATE_IN_TXS2_1_MASK 0x00000007L +#define PB1_PIF_PWRDOWN_1__TX_POWER_STATE_IN_TXS2_1__SHIFT 0x00000000 +#define PB1_PIF_PWRDOWN_2__FORCE_RXEN_IN_L0s_2_MASK 0x00000008L +#define PB1_PIF_PWRDOWN_2__FORCE_RXEN_IN_L0s_2__SHIFT 0x00000003 +#define PB1_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_OFF_2_MASK 0x00001c00L +#define PB1_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_OFF_2__SHIFT 0x0000000a +#define PB1_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_TXS2_2_MASK 0x00000380L +#define PB1_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_TXS2_2__SHIFT 0x00000007 +#define PB1_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_EN_2_MASK 0x10000000L +#define PB1_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_EN_2__SHIFT 0x0000001c +#define PB1_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_VAL_2_MASK 0xe0000000L +#define PB1_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_VAL_2__SHIFT 0x0000001d +#define PB1_PIF_PWRDOWN_2__PLL_RAMP_UP_TIME_2_MASK 0x07000000L +#define PB1_PIF_PWRDOWN_2__PLL_RAMP_UP_TIME_2__SHIFT 0x00000018 +#define PB1_PIF_PWRDOWN_2__RX_POWER_STATE_IN_RXS2_2_MASK 0x00000070L +#define PB1_PIF_PWRDOWN_2__RX_POWER_STATE_IN_RXS2_2__SHIFT 0x00000004 +#define PB1_PIF_PWRDOWN_2__TX2P5CLK_CLOCK_GATING_EN_2_MASK 0x00010000L +#define PB1_PIF_PWRDOWN_2__TX2P5CLK_CLOCK_GATING_EN_2__SHIFT 0x00000010 +#define PB1_PIF_PWRDOWN_2__TX_POWER_STATE_IN_TXS2_2_MASK 0x00000007L +#define PB1_PIF_PWRDOWN_2__TX_POWER_STATE_IN_TXS2_2__SHIFT 0x00000000 +#define PB1_PIF_PWRDOWN_3__FORCE_RXEN_IN_L0s_3_MASK 0x00000008L +#define PB1_PIF_PWRDOWN_3__FORCE_RXEN_IN_L0s_3__SHIFT 0x00000003 +#define PB1_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_OFF_3_MASK 0x00001c00L +#define PB1_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_OFF_3__SHIFT 0x0000000a +#define PB1_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_TXS2_3_MASK 0x00000380L +#define PB1_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_TXS2_3__SHIFT 0x00000007 +#define PB1_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_EN_3_MASK 0x10000000L +#define PB1_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_EN_3__SHIFT 0x0000001c +#define PB1_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_VAL_3_MASK 0xe0000000L +#define PB1_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_VAL_3__SHIFT 0x0000001d +#define PB1_PIF_PWRDOWN_3__PLL_RAMP_UP_TIME_3_MASK 0x07000000L +#define PB1_PIF_PWRDOWN_3__PLL_RAMP_UP_TIME_3__SHIFT 0x00000018 +#define PB1_PIF_PWRDOWN_3__RX_POWER_STATE_IN_RXS2_3_MASK 0x00000070L +#define PB1_PIF_PWRDOWN_3__RX_POWER_STATE_IN_RXS2_3__SHIFT 0x00000004 +#define PB1_PIF_PWRDOWN_3__TX2P5CLK_CLOCK_GATING_EN_3_MASK 0x00010000L +#define PB1_PIF_PWRDOWN_3__TX2P5CLK_CLOCK_GATING_EN_3__SHIFT 0x00000010 +#define PB1_PIF_PWRDOWN_3__TX_POWER_STATE_IN_TXS2_3_MASK 0x00000007L +#define PB1_PIF_PWRDOWN_3__TX_POWER_STATE_IN_TXS2_3__SHIFT 0x00000000 +#define PB1_PIF_SC_CTL__SC_CALIBRATION_MASK 0x00000001L +#define PB1_PIF_SC_CTL__SC_CALIBRATION__SHIFT 0x00000000 +#define PB1_PIF_SC_CTL__SC_ENTER_L1_FROM_L0_MASK 0x00000020L +#define PB1_PIF_SC_CTL__SC_ENTER_L1_FROM_L0__SHIFT 0x00000005 +#define PB1_PIF_SC_CTL__SC_ENTER_L1_FROM_L0S_MASK 0x00000010L +#define PB1_PIF_SC_CTL__SC_ENTER_L1_FROM_L0S__SHIFT 0x00000004 +#define PB1_PIF_SC_CTL__SC_EXIT_L1_TO_L0_MASK 0x00000008L +#define PB1_PIF_SC_CTL__SC_EXIT_L1_TO_L0__SHIFT 0x00000003 +#define PB1_PIF_SC_CTL__SC_EXIT_L1_TO_L0S_MASK 0x00000004L +#define PB1_PIF_SC_CTL__SC_EXIT_L1_TO_L0S__SHIFT 0x00000002 +#define PB1_PIF_SC_CTL__SC_LANE_0_RESUME_MASK 0x00010000L +#define PB1_PIF_SC_CTL__SC_LANE_0_RESUME__SHIFT 0x00000010 +#define PB1_PIF_SC_CTL__SC_LANE_10_RESUME_MASK 0x04000000L +#define PB1_PIF_SC_CTL__SC_LANE_10_RESUME__SHIFT 0x0000001a +#define PB1_PIF_SC_CTL__SC_LANE_11_RESUME_MASK 0x08000000L +#define PB1_PIF_SC_CTL__SC_LANE_11_RESUME__SHIFT 0x0000001b +#define PB1_PIF_SC_CTL__SC_LANE_12_RESUME_MASK 0x10000000L +#define PB1_PIF_SC_CTL__SC_LANE_12_RESUME__SHIFT 0x0000001c +#define PB1_PIF_SC_CTL__SC_LANE_13_RESUME_MASK 0x20000000L +#define PB1_PIF_SC_CTL__SC_LANE_13_RESUME__SHIFT 0x0000001d +#define PB1_PIF_SC_CTL__SC_LANE_14_RESUME_MASK 0x40000000L +#define PB1_PIF_SC_CTL__SC_LANE_14_RESUME__SHIFT 0x0000001e +#define PB1_PIF_SC_CTL__SC_LANE_15_RESUME_MASK 0x80000000L +#define PB1_PIF_SC_CTL__SC_LANE_15_RESUME__SHIFT 0x0000001f +#define PB1_PIF_SC_CTL__SC_LANE_1_RESUME_MASK 0x00020000L +#define PB1_PIF_SC_CTL__SC_LANE_1_RESUME__SHIFT 0x00000011 +#define PB1_PIF_SC_CTL__SC_LANE_2_RESUME_MASK 0x00040000L +#define PB1_PIF_SC_CTL__SC_LANE_2_RESUME__SHIFT 0x00000012 +#define PB1_PIF_SC_CTL__SC_LANE_3_RESUME_MASK 0x00080000L +#define PB1_PIF_SC_CTL__SC_LANE_3_RESUME__SHIFT 0x00000013 +#define PB1_PIF_SC_CTL__SC_LANE_4_RESUME_MASK 0x00100000L +#define PB1_PIF_SC_CTL__SC_LANE_4_RESUME__SHIFT 0x00000014 +#define PB1_PIF_SC_CTL__SC_LANE_5_RESUME_MASK 0x00200000L +#define PB1_PIF_SC_CTL__SC_LANE_5_RESUME__SHIFT 0x00000015 +#define PB1_PIF_SC_CTL__SC_LANE_6_RESUME_MASK 0x00400000L +#define PB1_PIF_SC_CTL__SC_LANE_6_RESUME__SHIFT 0x00000016 +#define PB1_PIF_SC_CTL__SC_LANE_7_RESUME_MASK 0x00800000L +#define PB1_PIF_SC_CTL__SC_LANE_7_RESUME__SHIFT 0x00000017 +#define PB1_PIF_SC_CTL__SC_LANE_8_RESUME_MASK 0x01000000L +#define PB1_PIF_SC_CTL__SC_LANE_8_RESUME__SHIFT 0x00000018 +#define PB1_PIF_SC_CTL__SC_LANE_9_RESUME_MASK 0x02000000L +#define PB1_PIF_SC_CTL__SC_LANE_9_RESUME__SHIFT 0x00000019 +#define PB1_PIF_SC_CTL__SC_PHASE_1_MASK 0x00000100L +#define PB1_PIF_SC_CTL__SC_PHASE_1__SHIFT 0x00000008 +#define PB1_PIF_SC_CTL__SC_PHASE_2_MASK 0x00000200L +#define PB1_PIF_SC_CTL__SC_PHASE_2__SHIFT 0x00000009 +#define PB1_PIF_SC_CTL__SC_PHASE_3_MASK 0x00000400L +#define PB1_PIF_SC_CTL__SC_PHASE_3__SHIFT 0x0000000a +#define PB1_PIF_SC_CTL__SC_PHASE_4_MASK 0x00000800L +#define PB1_PIF_SC_CTL__SC_PHASE_4__SHIFT 0x0000000b +#define PB1_PIF_SC_CTL__SC_PHASE_5_MASK 0x00001000L +#define PB1_PIF_SC_CTL__SC_PHASE_5__SHIFT 0x0000000c +#define PB1_PIF_SC_CTL__SC_PHASE_6_MASK 0x00002000L +#define PB1_PIF_SC_CTL__SC_PHASE_6__SHIFT 0x0000000d +#define PB1_PIF_SC_CTL__SC_PHASE_7_MASK 0x00004000L +#define PB1_PIF_SC_CTL__SC_PHASE_7__SHIFT 0x0000000e +#define PB1_PIF_SC_CTL__SC_PHASE_8_MASK 0x00008000L +#define PB1_PIF_SC_CTL__SC_PHASE_8__SHIFT 0x0000000f +#define PB1_PIF_SC_CTL__SC_RXDETECT_MASK 0x00000002L +#define PB1_PIF_SC_CTL__SC_RXDETECT__SHIFT 0x00000001 +#define PB1_PIF_SC_CTL__SC_SPEED_CHANGE_MASK 0x00000040L +#define PB1_PIF_SC_CTL__SC_SPEED_CHANGE__SHIFT 0x00000006 +#define PB1_PIF_SCRATCH__PIF_SCRATCH_MASK 0xffffffffL +#define PB1_PIF_SCRATCH__PIF_SCRATCH__SHIFT 0x00000000 +#define PB1_PIF_SEQ_STATUS_0__SEQ_CALIBRATION_0_MASK 0x00000001L +#define PB1_PIF_SEQ_STATUS_0__SEQ_CALIBRATION_0__SHIFT 0x00000000 +#define PB1_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0_0_MASK 0x00000020L +#define PB1_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0_0__SHIFT 0x00000005 +#define PB1_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0S_0_MASK 0x00000010L +#define PB1_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0S_0__SHIFT 0x00000004 +#define PB1_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0_0_MASK 0x00000008L +#define PB1_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0_0__SHIFT 0x00000003 +#define PB1_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0S_0_MASK 0x00000004L +#define PB1_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0S_0__SHIFT 0x00000002 +#define PB1_PIF_SEQ_STATUS_0__SEQ_PHASE_0_MASK 0x00000700L +#define PB1_PIF_SEQ_STATUS_0__SEQ_PHASE_0__SHIFT 0x00000008 +#define PB1_PIF_SEQ_STATUS_0__SEQ_RXDETECT_0_MASK 0x00000002L +#define PB1_PIF_SEQ_STATUS_0__SEQ_RXDETECT_0__SHIFT 0x00000001 +#define PB1_PIF_SEQ_STATUS_0__SEQ_SPEED_CHANGE_0_MASK 0x00000040L +#define PB1_PIF_SEQ_STATUS_0__SEQ_SPEED_CHANGE_0__SHIFT 0x00000006 +#define PB1_PIF_SEQ_STATUS_10__SEQ_CALIBRATION_10_MASK 0x00000001L +#define PB1_PIF_SEQ_STATUS_10__SEQ_CALIBRATION_10__SHIFT 0x00000000 +#define PB1_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0_10_MASK 0x00000020L +#define PB1_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0_10__SHIFT 0x00000005 +#define PB1_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0S_10_MASK 0x00000010L +#define PB1_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0S_10__SHIFT 0x00000004 +#define PB1_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0_10_MASK 0x00000008L +#define PB1_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0_10__SHIFT 0x00000003 +#define PB1_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0S_10_MASK 0x00000004L +#define PB1_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0S_10__SHIFT 0x00000002 +#define PB1_PIF_SEQ_STATUS_10__SEQ_PHASE_10_MASK 0x00000700L +#define PB1_PIF_SEQ_STATUS_10__SEQ_PHASE_10__SHIFT 0x00000008 +#define PB1_PIF_SEQ_STATUS_10__SEQ_RXDETECT_10_MASK 0x00000002L +#define PB1_PIF_SEQ_STATUS_10__SEQ_RXDETECT_10__SHIFT 0x00000001 +#define PB1_PIF_SEQ_STATUS_10__SEQ_SPEED_CHANGE_10_MASK 0x00000040L +#define PB1_PIF_SEQ_STATUS_10__SEQ_SPEED_CHANGE_10__SHIFT 0x00000006 +#define PB1_PIF_SEQ_STATUS_11__SEQ_CALIBRATION_11_MASK 0x00000001L +#define PB1_PIF_SEQ_STATUS_11__SEQ_CALIBRATION_11__SHIFT 0x00000000 +#define PB1_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0_11_MASK 0x00000020L +#define PB1_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0_11__SHIFT 0x00000005 +#define PB1_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0S_11_MASK 0x00000010L +#define PB1_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0S_11__SHIFT 0x00000004 +#define PB1_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0_11_MASK 0x00000008L +#define PB1_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0_11__SHIFT 0x00000003 +#define PB1_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0S_11_MASK 0x00000004L +#define PB1_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0S_11__SHIFT 0x00000002 +#define PB1_PIF_SEQ_STATUS_11__SEQ_PHASE_11_MASK 0x00000700L +#define PB1_PIF_SEQ_STATUS_11__SEQ_PHASE_11__SHIFT 0x00000008 +#define PB1_PIF_SEQ_STATUS_11__SEQ_RXDETECT_11_MASK 0x00000002L +#define PB1_PIF_SEQ_STATUS_11__SEQ_RXDETECT_11__SHIFT 0x00000001 +#define PB1_PIF_SEQ_STATUS_11__SEQ_SPEED_CHANGE_11_MASK 0x00000040L +#define PB1_PIF_SEQ_STATUS_11__SEQ_SPEED_CHANGE_11__SHIFT 0x00000006 +#define PB1_PIF_SEQ_STATUS_12__SEQ_CALIBRATION_12_MASK 0x00000001L +#define PB1_PIF_SEQ_STATUS_12__SEQ_CALIBRATION_12__SHIFT 0x00000000 +#define PB1_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0_12_MASK 0x00000020L +#define PB1_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0_12__SHIFT 0x00000005 +#define PB1_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0S_12_MASK 0x00000010L +#define PB1_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0S_12__SHIFT 0x00000004 +#define PB1_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0_12_MASK 0x00000008L +#define PB1_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0_12__SHIFT 0x00000003 +#define PB1_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0S_12_MASK 0x00000004L +#define PB1_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0S_12__SHIFT 0x00000002 +#define PB1_PIF_SEQ_STATUS_12__SEQ_PHASE_12_MASK 0x00000700L +#define PB1_PIF_SEQ_STATUS_12__SEQ_PHASE_12__SHIFT 0x00000008 +#define PB1_PIF_SEQ_STATUS_12__SEQ_RXDETECT_12_MASK 0x00000002L +#define PB1_PIF_SEQ_STATUS_12__SEQ_RXDETECT_12__SHIFT 0x00000001 +#define PB1_PIF_SEQ_STATUS_12__SEQ_SPEED_CHANGE_12_MASK 0x00000040L +#define PB1_PIF_SEQ_STATUS_12__SEQ_SPEED_CHANGE_12__SHIFT 0x00000006 +#define PB1_PIF_SEQ_STATUS_13__SEQ_CALIBRATION_13_MASK 0x00000001L +#define PB1_PIF_SEQ_STATUS_13__SEQ_CALIBRATION_13__SHIFT 0x00000000 +#define PB1_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0_13_MASK 0x00000020L +#define PB1_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0_13__SHIFT 0x00000005 +#define PB1_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0S_13_MASK 0x00000010L +#define PB1_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0S_13__SHIFT 0x00000004 +#define PB1_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0_13_MASK 0x00000008L +#define PB1_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0_13__SHIFT 0x00000003 +#define PB1_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0S_13_MASK 0x00000004L +#define PB1_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0S_13__SHIFT 0x00000002 +#define PB1_PIF_SEQ_STATUS_13__SEQ_PHASE_13_MASK 0x00000700L +#define PB1_PIF_SEQ_STATUS_13__SEQ_PHASE_13__SHIFT 0x00000008 +#define PB1_PIF_SEQ_STATUS_13__SEQ_RXDETECT_13_MASK 0x00000002L +#define PB1_PIF_SEQ_STATUS_13__SEQ_RXDETECT_13__SHIFT 0x00000001 +#define PB1_PIF_SEQ_STATUS_13__SEQ_SPEED_CHANGE_13_MASK 0x00000040L +#define PB1_PIF_SEQ_STATUS_13__SEQ_SPEED_CHANGE_13__SHIFT 0x00000006 +#define PB1_PIF_SEQ_STATUS_14__SEQ_CALIBRATION_14_MASK 0x00000001L +#define PB1_PIF_SEQ_STATUS_14__SEQ_CALIBRATION_14__SHIFT 0x00000000 +#define PB1_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0_14_MASK 0x00000020L +#define PB1_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0_14__SHIFT 0x00000005 +#define PB1_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0S_14_MASK 0x00000010L +#define PB1_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0S_14__SHIFT 0x00000004 +#define PB1_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0_14_MASK 0x00000008L +#define PB1_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0_14__SHIFT 0x00000003 +#define PB1_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0S_14_MASK 0x00000004L +#define PB1_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0S_14__SHIFT 0x00000002 +#define PB1_PIF_SEQ_STATUS_14__SEQ_PHASE_14_MASK 0x00000700L +#define PB1_PIF_SEQ_STATUS_14__SEQ_PHASE_14__SHIFT 0x00000008 +#define PB1_PIF_SEQ_STATUS_14__SEQ_RXDETECT_14_MASK 0x00000002L +#define PB1_PIF_SEQ_STATUS_14__SEQ_RXDETECT_14__SHIFT 0x00000001 +#define PB1_PIF_SEQ_STATUS_14__SEQ_SPEED_CHANGE_14_MASK 0x00000040L +#define PB1_PIF_SEQ_STATUS_14__SEQ_SPEED_CHANGE_14__SHIFT 0x00000006 +#define PB1_PIF_SEQ_STATUS_15__SEQ_CALIBRATION_15_MASK 0x00000001L +#define PB1_PIF_SEQ_STATUS_15__SEQ_CALIBRATION_15__SHIFT 0x00000000 +#define PB1_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0_15_MASK 0x00000020L +#define PB1_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0_15__SHIFT 0x00000005 +#define PB1_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0S_15_MASK 0x00000010L +#define PB1_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0S_15__SHIFT 0x00000004 +#define PB1_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0_15_MASK 0x00000008L +#define PB1_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0_15__SHIFT 0x00000003 +#define PB1_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0S_15_MASK 0x00000004L +#define PB1_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0S_15__SHIFT 0x00000002 +#define PB1_PIF_SEQ_STATUS_15__SEQ_PHASE_15_MASK 0x00000700L +#define PB1_PIF_SEQ_STATUS_15__SEQ_PHASE_15__SHIFT 0x00000008 +#define PB1_PIF_SEQ_STATUS_15__SEQ_RXDETECT_15_MASK 0x00000002L +#define PB1_PIF_SEQ_STATUS_15__SEQ_RXDETECT_15__SHIFT 0x00000001 +#define PB1_PIF_SEQ_STATUS_15__SEQ_SPEED_CHANGE_15_MASK 0x00000040L +#define PB1_PIF_SEQ_STATUS_15__SEQ_SPEED_CHANGE_15__SHIFT 0x00000006 +#define PB1_PIF_SEQ_STATUS_1__SEQ_CALIBRATION_1_MASK 0x00000001L +#define PB1_PIF_SEQ_STATUS_1__SEQ_CALIBRATION_1__SHIFT 0x00000000 +#define PB1_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0_1_MASK 0x00000020L +#define PB1_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0_1__SHIFT 0x00000005 +#define PB1_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0S_1_MASK 0x00000010L +#define PB1_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0S_1__SHIFT 0x00000004 +#define PB1_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0_1_MASK 0x00000008L +#define PB1_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0_1__SHIFT 0x00000003 +#define PB1_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0S_1_MASK 0x00000004L +#define PB1_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0S_1__SHIFT 0x00000002 +#define PB1_PIF_SEQ_STATUS_1__SEQ_PHASE_1_MASK 0x00000700L +#define PB1_PIF_SEQ_STATUS_1__SEQ_PHASE_1__SHIFT 0x00000008 +#define PB1_PIF_SEQ_STATUS_1__SEQ_RXDETECT_1_MASK 0x00000002L +#define PB1_PIF_SEQ_STATUS_1__SEQ_RXDETECT_1__SHIFT 0x00000001 +#define PB1_PIF_SEQ_STATUS_1__SEQ_SPEED_CHANGE_1_MASK 0x00000040L +#define PB1_PIF_SEQ_STATUS_1__SEQ_SPEED_CHANGE_1__SHIFT 0x00000006 +#define PB1_PIF_SEQ_STATUS_2__SEQ_CALIBRATION_2_MASK 0x00000001L +#define PB1_PIF_SEQ_STATUS_2__SEQ_CALIBRATION_2__SHIFT 0x00000000 +#define PB1_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0_2_MASK 0x00000020L +#define PB1_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0_2__SHIFT 0x00000005 +#define PB1_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0S_2_MASK 0x00000010L +#define PB1_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0S_2__SHIFT 0x00000004 +#define PB1_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0_2_MASK 0x00000008L +#define PB1_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0_2__SHIFT 0x00000003 +#define PB1_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0S_2_MASK 0x00000004L +#define PB1_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0S_2__SHIFT 0x00000002 +#define PB1_PIF_SEQ_STATUS_2__SEQ_PHASE_2_MASK 0x00000700L +#define PB1_PIF_SEQ_STATUS_2__SEQ_PHASE_2__SHIFT 0x00000008 +#define PB1_PIF_SEQ_STATUS_2__SEQ_RXDETECT_2_MASK 0x00000002L +#define PB1_PIF_SEQ_STATUS_2__SEQ_RXDETECT_2__SHIFT 0x00000001 +#define PB1_PIF_SEQ_STATUS_2__SEQ_SPEED_CHANGE_2_MASK 0x00000040L +#define PB1_PIF_SEQ_STATUS_2__SEQ_SPEED_CHANGE_2__SHIFT 0x00000006 +#define PB1_PIF_SEQ_STATUS_3__SEQ_CALIBRATION_3_MASK 0x00000001L +#define PB1_PIF_SEQ_STATUS_3__SEQ_CALIBRATION_3__SHIFT 0x00000000 +#define PB1_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0_3_MASK 0x00000020L +#define PB1_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0_3__SHIFT 0x00000005 +#define PB1_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0S_3_MASK 0x00000010L +#define PB1_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0S_3__SHIFT 0x00000004 +#define PB1_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0_3_MASK 0x00000008L +#define PB1_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0_3__SHIFT 0x00000003 +#define PB1_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0S_3_MASK 0x00000004L +#define PB1_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0S_3__SHIFT 0x00000002 +#define PB1_PIF_SEQ_STATUS_3__SEQ_PHASE_3_MASK 0x00000700L +#define PB1_PIF_SEQ_STATUS_3__SEQ_PHASE_3__SHIFT 0x00000008 +#define PB1_PIF_SEQ_STATUS_3__SEQ_RXDETECT_3_MASK 0x00000002L +#define PB1_PIF_SEQ_STATUS_3__SEQ_RXDETECT_3__SHIFT 0x00000001 +#define PB1_PIF_SEQ_STATUS_3__SEQ_SPEED_CHANGE_3_MASK 0x00000040L +#define PB1_PIF_SEQ_STATUS_3__SEQ_SPEED_CHANGE_3__SHIFT 0x00000006 +#define PB1_PIF_SEQ_STATUS_4__SEQ_CALIBRATION_4_MASK 0x00000001L +#define PB1_PIF_SEQ_STATUS_4__SEQ_CALIBRATION_4__SHIFT 0x00000000 +#define PB1_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0_4_MASK 0x00000020L +#define PB1_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0_4__SHIFT 0x00000005 +#define PB1_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0S_4_MASK 0x00000010L +#define PB1_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0S_4__SHIFT 0x00000004 +#define PB1_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0_4_MASK 0x00000008L +#define PB1_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0_4__SHIFT 0x00000003 +#define PB1_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0S_4_MASK 0x00000004L +#define PB1_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0S_4__SHIFT 0x00000002 +#define PB1_PIF_SEQ_STATUS_4__SEQ_PHASE_4_MASK 0x00000700L +#define PB1_PIF_SEQ_STATUS_4__SEQ_PHASE_4__SHIFT 0x00000008 +#define PB1_PIF_SEQ_STATUS_4__SEQ_RXDETECT_4_MASK 0x00000002L +#define PB1_PIF_SEQ_STATUS_4__SEQ_RXDETECT_4__SHIFT 0x00000001 +#define PB1_PIF_SEQ_STATUS_4__SEQ_SPEED_CHANGE_4_MASK 0x00000040L +#define PB1_PIF_SEQ_STATUS_4__SEQ_SPEED_CHANGE_4__SHIFT 0x00000006 +#define PB1_PIF_SEQ_STATUS_5__SEQ_CALIBRATION_5_MASK 0x00000001L +#define PB1_PIF_SEQ_STATUS_5__SEQ_CALIBRATION_5__SHIFT 0x00000000 +#define PB1_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0_5_MASK 0x00000020L +#define PB1_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0_5__SHIFT 0x00000005 +#define PB1_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0S_5_MASK 0x00000010L +#define PB1_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0S_5__SHIFT 0x00000004 +#define PB1_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0_5_MASK 0x00000008L +#define PB1_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0_5__SHIFT 0x00000003 +#define PB1_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0S_5_MASK 0x00000004L +#define PB1_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0S_5__SHIFT 0x00000002 +#define PB1_PIF_SEQ_STATUS_5__SEQ_PHASE_5_MASK 0x00000700L +#define PB1_PIF_SEQ_STATUS_5__SEQ_PHASE_5__SHIFT 0x00000008 +#define PB1_PIF_SEQ_STATUS_5__SEQ_RXDETECT_5_MASK 0x00000002L +#define PB1_PIF_SEQ_STATUS_5__SEQ_RXDETECT_5__SHIFT 0x00000001 +#define PB1_PIF_SEQ_STATUS_5__SEQ_SPEED_CHANGE_5_MASK 0x00000040L +#define PB1_PIF_SEQ_STATUS_5__SEQ_SPEED_CHANGE_5__SHIFT 0x00000006 +#define PB1_PIF_SEQ_STATUS_6__SEQ_CALIBRATION_6_MASK 0x00000001L +#define PB1_PIF_SEQ_STATUS_6__SEQ_CALIBRATION_6__SHIFT 0x00000000 +#define PB1_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0_6_MASK 0x00000020L +#define PB1_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0_6__SHIFT 0x00000005 +#define PB1_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0S_6_MASK 0x00000010L +#define PB1_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0S_6__SHIFT 0x00000004 +#define PB1_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0_6_MASK 0x00000008L +#define PB1_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0_6__SHIFT 0x00000003 +#define PB1_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0S_6_MASK 0x00000004L +#define PB1_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0S_6__SHIFT 0x00000002 +#define PB1_PIF_SEQ_STATUS_6__SEQ_PHASE_6_MASK 0x00000700L +#define PB1_PIF_SEQ_STATUS_6__SEQ_PHASE_6__SHIFT 0x00000008 +#define PB1_PIF_SEQ_STATUS_6__SEQ_RXDETECT_6_MASK 0x00000002L +#define PB1_PIF_SEQ_STATUS_6__SEQ_RXDETECT_6__SHIFT 0x00000001 +#define PB1_PIF_SEQ_STATUS_6__SEQ_SPEED_CHANGE_6_MASK 0x00000040L +#define PB1_PIF_SEQ_STATUS_6__SEQ_SPEED_CHANGE_6__SHIFT 0x00000006 +#define PB1_PIF_SEQ_STATUS_7__SEQ_CALIBRATION_7_MASK 0x00000001L +#define PB1_PIF_SEQ_STATUS_7__SEQ_CALIBRATION_7__SHIFT 0x00000000 +#define PB1_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0_7_MASK 0x00000020L +#define PB1_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0_7__SHIFT 0x00000005 +#define PB1_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0S_7_MASK 0x00000010L +#define PB1_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0S_7__SHIFT 0x00000004 +#define PB1_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0_7_MASK 0x00000008L +#define PB1_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0_7__SHIFT 0x00000003 +#define PB1_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0S_7_MASK 0x00000004L +#define PB1_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0S_7__SHIFT 0x00000002 +#define PB1_PIF_SEQ_STATUS_7__SEQ_PHASE_7_MASK 0x00000700L +#define PB1_PIF_SEQ_STATUS_7__SEQ_PHASE_7__SHIFT 0x00000008 +#define PB1_PIF_SEQ_STATUS_7__SEQ_RXDETECT_7_MASK 0x00000002L +#define PB1_PIF_SEQ_STATUS_7__SEQ_RXDETECT_7__SHIFT 0x00000001 +#define PB1_PIF_SEQ_STATUS_7__SEQ_SPEED_CHANGE_7_MASK 0x00000040L +#define PB1_PIF_SEQ_STATUS_7__SEQ_SPEED_CHANGE_7__SHIFT 0x00000006 +#define PB1_PIF_SEQ_STATUS_8__SEQ_CALIBRATION_8_MASK 0x00000001L +#define PB1_PIF_SEQ_STATUS_8__SEQ_CALIBRATION_8__SHIFT 0x00000000 +#define PB1_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0_8_MASK 0x00000020L +#define PB1_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0_8__SHIFT 0x00000005 +#define PB1_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0S_8_MASK 0x00000010L +#define PB1_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0S_8__SHIFT 0x00000004 +#define PB1_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0_8_MASK 0x00000008L +#define PB1_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0_8__SHIFT 0x00000003 +#define PB1_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0S_8_MASK 0x00000004L +#define PB1_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0S_8__SHIFT 0x00000002 +#define PB1_PIF_SEQ_STATUS_8__SEQ_PHASE_8_MASK 0x00000700L +#define PB1_PIF_SEQ_STATUS_8__SEQ_PHASE_8__SHIFT 0x00000008 +#define PB1_PIF_SEQ_STATUS_8__SEQ_RXDETECT_8_MASK 0x00000002L +#define PB1_PIF_SEQ_STATUS_8__SEQ_RXDETECT_8__SHIFT 0x00000001 +#define PB1_PIF_SEQ_STATUS_8__SEQ_SPEED_CHANGE_8_MASK 0x00000040L +#define PB1_PIF_SEQ_STATUS_8__SEQ_SPEED_CHANGE_8__SHIFT 0x00000006 +#define PB1_PIF_SEQ_STATUS_9__SEQ_CALIBRATION_9_MASK 0x00000001L +#define PB1_PIF_SEQ_STATUS_9__SEQ_CALIBRATION_9__SHIFT 0x00000000 +#define PB1_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0_9_MASK 0x00000020L +#define PB1_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0_9__SHIFT 0x00000005 +#define PB1_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0S_9_MASK 0x00000010L +#define PB1_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0S_9__SHIFT 0x00000004 +#define PB1_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0_9_MASK 0x00000008L +#define PB1_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0_9__SHIFT 0x00000003 +#define PB1_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0S_9_MASK 0x00000004L +#define PB1_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0S_9__SHIFT 0x00000002 +#define PB1_PIF_SEQ_STATUS_9__SEQ_PHASE_9_MASK 0x00000700L +#define PB1_PIF_SEQ_STATUS_9__SEQ_PHASE_9__SHIFT 0x00000008 +#define PB1_PIF_SEQ_STATUS_9__SEQ_RXDETECT_9_MASK 0x00000002L +#define PB1_PIF_SEQ_STATUS_9__SEQ_RXDETECT_9__SHIFT 0x00000001 +#define PB1_PIF_SEQ_STATUS_9__SEQ_SPEED_CHANGE_9_MASK 0x00000040L +#define PB1_PIF_SEQ_STATUS_9__SEQ_SPEED_CHANGE_9__SHIFT 0x00000006 +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_0_MASK 0x00000001L +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_0__SHIFT 0x00000000 +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_10_MASK 0x00000400L +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_10__SHIFT 0x0000000a +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_11_MASK 0x00000800L +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_11__SHIFT 0x0000000b +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_12_MASK 0x00001000L +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_12__SHIFT 0x0000000c +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_13_MASK 0x00002000L +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_13__SHIFT 0x0000000d +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_14_MASK 0x00004000L +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_14__SHIFT 0x0000000e +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_15_MASK 0x00008000L +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_15__SHIFT 0x0000000f +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_1_MASK 0x00000002L +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_1__SHIFT 0x00000001 +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_2_MASK 0x00000004L +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_2__SHIFT 0x00000002 +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_3_MASK 0x00000008L +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_3__SHIFT 0x00000003 +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_4_MASK 0x00000010L +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_4__SHIFT 0x00000004 +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_5_MASK 0x00000020L +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_5__SHIFT 0x00000005 +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_6_MASK 0x00000040L +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_6__SHIFT 0x00000006 +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_7_MASK 0x00000080L +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_7__SHIFT 0x00000007 +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_8_MASK 0x00000100L +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_8__SHIFT 0x00000008 +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_9_MASK 0x00000200L +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_9__SHIFT 0x00000009 +#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0_MASK 0x00000003L +#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0__SHIFT 0x00000000 +#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0_MASK 0x00000004L +#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0__SHIFT 0x00000002 +#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0_MASK 0x00000008L +#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0__SHIFT 0x00000003 +#define PB1_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0_MASK 0x00000010L +#define PB1_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0__SHIFT 0x00000004 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0_MASK 0x00000008L +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0__SHIFT 0x00000003 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0_MASK 0x00000007L +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0__SHIFT 0x00000000 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0_MASK 0x00000080L +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0__SHIFT 0x00000007 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0_MASK 0x00000070L +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x00000004 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0_MASK 0x00000200L +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0__SHIFT 0x00000009 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0_MASK 0x00000100L +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0__SHIFT 0x00000008 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0_MASK 0x00040000L +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0__SHIFT 0x00000012 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0_MASK 0x0003fc00L +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0__SHIFT 0x0000000a +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0_MASK 0x10000000L +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0__SHIFT 0x0000001c +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0_MASK 0x0ff80000L +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0__SHIFT 0x00000013 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0_MASK 0x80000000L +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0__SHIFT 0x0000001f +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0_MASK 0x60000000L +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0__SHIFT 0x0000001d +#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0_MASK 0x00000008L +#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0__SHIFT 0x00000003 +#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0_MASK 0x00000007L +#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x00000000 +#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0_MASK 0x00040000L +#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0__SHIFT 0x00000012 +#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0_MASK 0x0003c000L +#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0__SHIFT 0x0000000e +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x00000020L +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0x00000005 +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x00000010L +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x00000004 +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x00000080L +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0x00000007 +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x00000040L +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0x00000006 +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0_MASK 0x00000200L +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0__SHIFT 0x00000009 +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0_MASK 0x00000100L +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0__SHIFT 0x00000008 +#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_FREQMODE_MASK 0x00000300L +#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_FREQMODE__SHIFT 0x00000008 +#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L +#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001 +#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L +#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000 +#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR_MASK 0x00000070L +#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR__SHIFT 0x00000004 +#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_FREQMODE_MASK 0x00000300L +#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_FREQMODE__SHIFT 0x00000008 +#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L +#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001 +#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L +#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000 +#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR_MASK 0x00000070L +#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR__SHIFT 0x00000004 +#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_FREQMODE_MASK 0x00000300L +#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_FREQMODE__SHIFT 0x00000008 +#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L +#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001 +#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L +#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000 +#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR_MASK 0x00000070L +#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR__SHIFT 0x00000004 +#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_FREQMODE_MASK 0x00000300L +#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_FREQMODE__SHIFT 0x00000008 +#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L +#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001 +#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L +#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000 +#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR_MASK 0x00000070L +#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR__SHIFT 0x00000004 +#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0_MASK 0x00000003L +#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0__SHIFT 0x00000000 +#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0_MASK 0x00000004L +#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0__SHIFT 0x00000002 +#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0_MASK 0x000007f0L +#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0__SHIFT 0x00000004 +#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0_MASK 0x00000008L +#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0__SHIFT 0x00000003 +#define PB1_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0_MASK 0x00000800L +#define PB1_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0__SHIFT 0x0000000b +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0_MASK 0x00000100L +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0__SHIFT 0x00000008 +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0_MASK 0x000000ffL +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0__SHIFT 0x00000000 +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0_MASK 0x00001000L +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0__SHIFT 0x0000000c +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0_MASK 0x00000e00L +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x00000009 +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0_MASK 0x00004000L +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0__SHIFT 0x0000000e +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0_MASK 0x00002000L +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0__SHIFT 0x0000000d +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0_MASK 0x10000000L +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0__SHIFT 0x0000001c +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0_MASK 0x0fff8000L +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0__SHIFT 0x0000000f +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0_MASK 0x80000000L +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0__SHIFT 0x0000001f +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0_MASK 0x40000000L +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0__SHIFT 0x0000001e +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0_MASK 0x00400000L +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0__SHIFT 0x00000016 +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0_MASK 0x00380000L +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x00000013 +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0_MASK 0x00000020L +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0__SHIFT 0x00000005 +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0_MASK 0x0000001fL +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0__SHIFT 0x00000000 +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0_MASK 0x00000100L +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0__SHIFT 0x00000008 +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0_MASK 0x000000c0L +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0__SHIFT 0x00000006 +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x00000400L +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0x0000000a +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x00000200L +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x00000009 +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x00001000L +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0x0000000c +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x00000800L +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0x0000000b +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0_MASK 0x00004000L +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0__SHIFT 0x0000000e +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0_MASK 0x00002000L +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0__SHIFT 0x0000000d +#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_FREQMODE_MASK 0x00000300L +#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_FREQMODE__SHIFT 0x00000008 +#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L +#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001 +#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L +#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000 +#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR_MASK 0x00000070L +#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR__SHIFT 0x00000004 +#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_FREQMODE_MASK 0x00000300L +#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_FREQMODE__SHIFT 0x00000008 +#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L +#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001 +#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L +#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000 +#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR_MASK 0x00000070L +#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR__SHIFT 0x00000004 +#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_FREQMODE_MASK 0x00000300L +#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_FREQMODE__SHIFT 0x00000008 +#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L +#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001 +#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L +#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000 +#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR_MASK 0x00000070L +#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR__SHIFT 0x00000004 +#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_FREQMODE_MASK 0x00000300L +#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_FREQMODE__SHIFT 0x00000008 +#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L +#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001 +#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L +#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000 +#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR_MASK 0x00000070L +#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR__SHIFT 0x00000004 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x00000200L +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x00000009 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x00000400L +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0x0000000a +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x00000800L +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0x0000000b +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN_MASK 0x00100000L +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN__SHIFT 0x00000014 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN_MASK 0x00200000L +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN__SHIFT 0x00000015 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x00001000L +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0x0000000c +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x00002000L +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0x0000000d +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x00004000L +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0x0000000e +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN_MASK 0x00400000L +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN__SHIFT 0x00000016 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN_MASK 0x00800000L +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN__SHIFT 0x00000017 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2_MASK 0x00000100L +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2__SHIFT 0x00000008 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x00000002L +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x00000001 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x00000004L +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0x00000002 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x00000008L +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0x00000003 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN_MASK 0x00010000L +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN__SHIFT 0x00000010 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN_MASK 0x00020000L +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN__SHIFT 0x00000011 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x00000010L +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0x00000004 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x00000020L +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0x00000005 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x00000040L +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0x00000006 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN_MASK 0x00040000L +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN__SHIFT 0x00000012 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN_MASK 0x00080000L +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN__SHIFT 0x00000013 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2_MASK 0x00000080L +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2__SHIFT 0x00000007 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC_MASK 0x00000001L +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC__SHIFT 0x00000000 +#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1_MASK 0x000003ffL +#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1__SHIFT 0x00000000 +#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2_MASK 0x000ffc00L +#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2__SHIFT 0x0000000a +#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3_MASK 0x3ff00000L +#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3__SHIFT 0x00000014 +#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_RST_MODE_MASK 0xc0000000L +#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_RST_MODE__SHIFT 0x0000001e +#define PB1_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN_MASK 0xc0000000L +#define PB1_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN__SHIFT 0x0000001e +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1_MASK 0x0000000fL +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1__SHIFT 0x00000000 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2_MASK 0x000000f0L +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2__SHIFT 0x00000004 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3_MASK 0x00000f00L +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3__SHIFT 0x00000008 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1_MASK 0x0000f000L +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1__SHIFT 0x0000000c +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2_MASK 0x000f0000L +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2__SHIFT 0x00000010 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3_MASK 0x00f00000L +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3__SHIFT 0x00000014 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1_MASK 0x01000000L +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1__SHIFT 0x00000018 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2_MASK 0x02000000L +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2__SHIFT 0x00000019 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3_MASK 0x04000000L +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3__SHIFT 0x0000001a +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1_MASK 0x08000000L +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1__SHIFT 0x0000001b +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2_MASK 0x10000000L +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2__SHIFT 0x0000001c +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3_MASK 0x20000000L +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3__SHIFT 0x0000001d +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1_MASK 0x0000f000L +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1__SHIFT 0x0000000c +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2_MASK 0x000f0000L +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2__SHIFT 0x00000010 +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3_MASK 0x00f00000L +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3__SHIFT 0x00000014 +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1_MASK 0x03000000L +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1__SHIFT 0x00000018 +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2_MASK 0x0c000000L +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2__SHIFT 0x0000001a +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3_MASK 0x30000000L +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3__SHIFT 0x0000001c +#define PB1_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD_MASK 0xc0000000L +#define PB1_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD__SHIFT 0x0000001e +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1_MASK 0x00000001L +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1__SHIFT 0x00000000 +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2_MASK 0x00000002L +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2__SHIFT 0x00000001 +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3_MASK 0x00000004L +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3__SHIFT 0x00000002 +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1_MASK 0x00f00000L +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1__SHIFT 0x00000014 +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2_MASK 0x0f000000L +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2__SHIFT 0x00000018 +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3_MASK 0xf0000000L +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3__SHIFT 0x0000001c +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1_MASK 0x00000007L +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1__SHIFT 0x00000000 +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2_MASK 0x00000038L +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2__SHIFT 0x00000003 +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3_MASK 0x000001c0L +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3__SHIFT 0x00000006 +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1_MASK 0x00f00000L +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1__SHIFT 0x00000014 +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2_MASK 0x0f000000L +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2__SHIFT 0x00000018 +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3_MASK 0xf0000000L +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3__SHIFT 0x0000001c +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1_MASK 0x00000e00L +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1__SHIFT 0x00000009 +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2_MASK 0x00007000L +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2__SHIFT 0x0000000c +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3_MASK 0x00038000L +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3__SHIFT 0x0000000f +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1_MASK 0x0000001fL +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1__SHIFT 0x00000000 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2_MASK 0x000003e0L +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2__SHIFT 0x00000005 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3_MASK 0x00007c00L +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3__SHIFT 0x0000000a +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1_MASK 0x00008000L +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1__SHIFT 0x0000000f +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2_MASK 0x00010000L +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2__SHIFT 0x00000010 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3_MASK 0x00020000L +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3__SHIFT 0x00000011 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1_MASK 0x00040000L +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1__SHIFT 0x00000012 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2_MASK 0x00080000L +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2__SHIFT 0x00000013 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3_MASK 0x00100000L +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3__SHIFT 0x00000014 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1_MASK 0x08000000L +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1__SHIFT 0x0000001b +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2_MASK 0x10000000L +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2__SHIFT 0x0000001c +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3_MASK 0x20000000L +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3__SHIFT 0x0000001d +#define PB1_RX_GLB_CTRL_REG5__RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0_MASK 0x40000000L +#define PB1_RX_GLB_CTRL_REG5__RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0__SHIFT 0x0000001e +#define PB1_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2_MASK 0x08000000L +#define PB1_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2__SHIFT 0x0000001b +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1_MASK 0x0000000fL +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1__SHIFT 0x00000000 +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2_MASK 0x000000f0L +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2__SHIFT 0x00000004 +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3_MASK 0x00000f00L +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3__SHIFT 0x00000008 +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1_MASK 0x0000f000L +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1__SHIFT 0x0000000c +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2_MASK 0x000f0000L +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2__SHIFT 0x00000010 +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3_MASK 0x00f00000L +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3__SHIFT 0x00000014 +#define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x01000000L +#define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0x00000018 +#define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2_MASK 0x04000000L +#define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2__SHIFT 0x0000001a +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1_MASK 0x001c0000L +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1__SHIFT 0x00000012 +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2_MASK 0x00e00000L +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2__SHIFT 0x00000015 +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3_MASK 0x07000000L +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3__SHIFT 0x00000018 +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1_MASK 0x08000000L +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1__SHIFT 0x0000001b +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2_MASK 0x10000000L +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2__SHIFT 0x0000001c +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3_MASK 0x20000000L +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3__SHIFT 0x0000001d +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1_MASK 0x0000000fL +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1__SHIFT 0x00000000 +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2_MASK 0x000000f0L +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2__SHIFT 0x00000004 +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3_MASK 0x00000f00L +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3__SHIFT 0x00000008 +#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x00001000L +#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0x0000000c +#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2_MASK 0x00002000L +#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2__SHIFT 0x0000000d +#define PB1_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_LS2_MASK 0x00020000L +#define PB1_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_LS2__SHIFT 0x00000011 +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN_MASK 0x80000000L +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN__SHIFT 0x0000001f +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL_MASK 0x40000000L +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL__SHIFT 0x0000001e +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN_MASK 0x00000002L +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN__SHIFT 0x00000001 +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL_MASK 0x00000001L +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL__SHIFT 0x00000000 +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN_MASK 0x00000008L +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN__SHIFT 0x00000003 +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL_MASK 0x00000004L +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL__SHIFT 0x00000002 +#define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN_MASK 0x20000000L +#define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN__SHIFT 0x0000001d +#define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL_MASK 0x10000000L +#define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL__SHIFT 0x0000001c +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN_MASK 0x00000100L +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x00000008 +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL_MASK 0x000000c0L +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x00000006 +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN_MASK 0x00000400L +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN__SHIFT 0x0000000a +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL_MASK 0x00000200L +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL__SHIFT 0x00000009 +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x00001000L +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0x0000000c +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x00000800L +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0x0000000b +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN_MASK 0x00004000L +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN__SHIFT 0x0000000e +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL_MASK 0x00002000L +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL__SHIFT 0x0000000d +#define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN_MASK 0x00010000L +#define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN__SHIFT 0x00000010 +#define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL_MASK 0x00008000L +#define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL__SHIFT 0x0000000f +#define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN_MASK 0x00040000L +#define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN__SHIFT 0x00000012 +#define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL_MASK 0x00020000L +#define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL__SHIFT 0x00000011 +#define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN_MASK 0x00100000L +#define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN__SHIFT 0x00000014 +#define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL_MASK 0x00080000L +#define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL__SHIFT 0x00000013 +#define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN_MASK 0x00400000L +#define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN__SHIFT 0x00000016 +#define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL_MASK 0x00200000L +#define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL__SHIFT 0x00000015 +#define PB1_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_EN_MASK 0x01000000L +#define PB1_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_EN__SHIFT 0x00000018 +#define PB1_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_VAL_MASK 0x00800000L +#define PB1_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_VAL__SHIFT 0x00000017 +#define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN_MASK 0x00000002L +#define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN__SHIFT 0x00000001 +#define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL_MASK 0x00000001L +#define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL__SHIFT 0x00000000 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3_MASK 0x00000010L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3__SHIFT 0x00000004 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15_MASK 0x00000080L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15__SHIFT 0x00000007 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7_MASK 0x00000020L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7__SHIFT 0x00000005 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11_MASK 0x00000040L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11__SHIFT 0x00000006 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L0T3_MASK 0x00001000L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L0T3__SHIFT 0x0000000c +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L12T15_MASK 0x00008000L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L12T15__SHIFT 0x0000000f +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L4T7_MASK 0x00002000L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L4T7__SHIFT 0x0000000d +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L8T11_MASK 0x00004000L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L8T11__SHIFT 0x0000000e +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L0T3_MASK 0x00010000L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L0T3__SHIFT 0x00000010 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L12T15_MASK 0x00080000L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L12T15__SHIFT 0x00000013 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L4T7_MASK 0x00020000L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L4T7__SHIFT 0x00000011 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L8T11_MASK 0x00040000L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L8T11__SHIFT 0x00000012 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L0T3_MASK 0x00100000L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L0T3__SHIFT 0x00000014 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L12T15_MASK 0x00800000L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L12T15__SHIFT 0x00000017 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L4T7_MASK 0x00200000L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L4T7__SHIFT 0x00000015 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L8T11_MASK 0x00400000L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L8T11__SHIFT 0x00000016 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L0T3_MASK 0x00000100L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L0T3__SHIFT 0x00000008 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L12T15_MASK 0x00000800L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L12T15__SHIFT 0x0000000b +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L4T7_MASK 0x00000200L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L4T7__SHIFT 0x00000009 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L8T11_MASK 0x00000400L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L8T11__SHIFT 0x0000000a +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L0T3_MASK 0x00000001L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L0T3__SHIFT 0x00000000 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L12T15_MASK 0x00000008L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L12T15__SHIFT 0x00000003 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L4T7_MASK 0x00000002L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L4T7__SHIFT 0x00000001 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L8T11_MASK 0x00000004L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L8T11__SHIFT 0x00000002 +#define PB1_RX_LANE0_CTRL_REG0__RX_BACKUP_0_MASK 0x000000ffL +#define PB1_RX_LANE0_CTRL_REG0__RX_BACKUP_0__SHIFT 0x00000000 +#define PB1_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0_MASK 0x00002000L +#define PB1_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0__SHIFT 0x0000000d +#define PB1_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0_MASK 0x00000c00L +#define PB1_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0__SHIFT 0x0000000a +#define PB1_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0_MASK 0x00001000L +#define PB1_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0__SHIFT 0x0000000c +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0_MASK 0x00000008L +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0__SHIFT 0x00000003 +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0_MASK 0x00000080L +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0__SHIFT 0x00000007 +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0_MASK 0x00000100L +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0__SHIFT 0x00000008 +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0_MASK 0x00000200L +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0__SHIFT 0x00000009 +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXPRESETHINT_0_MASK 0x00000070L +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXPRESETHINT_0__SHIFT 0x00000004 +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0_MASK 0x00000007L +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0__SHIFT 0x00000000 +#define PB1_RX_LANE10_CTRL_REG0__RX_BACKUP_10_MASK 0x000000ffL +#define PB1_RX_LANE10_CTRL_REG0__RX_BACKUP_10__SHIFT 0x00000000 +#define PB1_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10_MASK 0x00002000L +#define PB1_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10__SHIFT 0x0000000d +#define PB1_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10_MASK 0x00000c00L +#define PB1_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10__SHIFT 0x0000000a +#define PB1_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10_MASK 0x00001000L +#define PB1_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10__SHIFT 0x0000000c +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10_MASK 0x00000008L +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10__SHIFT 0x00000003 +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10_MASK 0x00000080L +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10__SHIFT 0x00000007 +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10_MASK 0x00000100L +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10__SHIFT 0x00000008 +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10_MASK 0x00000200L +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10__SHIFT 0x00000009 +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXPRESETHINT_10_MASK 0x00000070L +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXPRESETHINT_10__SHIFT 0x00000004 +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10_MASK 0x00000007L +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10__SHIFT 0x00000000 +#define PB1_RX_LANE11_CTRL_REG0__RX_BACKUP_11_MASK 0x000000ffL +#define PB1_RX_LANE11_CTRL_REG0__RX_BACKUP_11__SHIFT 0x00000000 +#define PB1_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11_MASK 0x00002000L +#define PB1_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11__SHIFT 0x0000000d +#define PB1_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11_MASK 0x00000c00L +#define PB1_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11__SHIFT 0x0000000a +#define PB1_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11_MASK 0x00001000L +#define PB1_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11__SHIFT 0x0000000c +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11_MASK 0x00000008L +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11__SHIFT 0x00000003 +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11_MASK 0x00000080L +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11__SHIFT 0x00000007 +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11_MASK 0x00000100L +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11__SHIFT 0x00000008 +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11_MASK 0x00000200L +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11__SHIFT 0x00000009 +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXPRESETHINT_11_MASK 0x00000070L +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXPRESETHINT_11__SHIFT 0x00000004 +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11_MASK 0x00000007L +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11__SHIFT 0x00000000 +#define PB1_RX_LANE12_CTRL_REG0__RX_BACKUP_12_MASK 0x000000ffL +#define PB1_RX_LANE12_CTRL_REG0__RX_BACKUP_12__SHIFT 0x00000000 +#define PB1_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12_MASK 0x00002000L +#define PB1_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12__SHIFT 0x0000000d +#define PB1_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12_MASK 0x00000c00L +#define PB1_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12__SHIFT 0x0000000a +#define PB1_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12_MASK 0x00001000L +#define PB1_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12__SHIFT 0x0000000c +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12_MASK 0x00000008L +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12__SHIFT 0x00000003 +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12_MASK 0x00000080L +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12__SHIFT 0x00000007 +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12_MASK 0x00000100L +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12__SHIFT 0x00000008 +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12_MASK 0x00000200L +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12__SHIFT 0x00000009 +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXPRESETHINT_12_MASK 0x00000070L +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXPRESETHINT_12__SHIFT 0x00000004 +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12_MASK 0x00000007L +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12__SHIFT 0x00000000 +#define PB1_RX_LANE13_CTRL_REG0__RX_BACKUP_13_MASK 0x000000ffL +#define PB1_RX_LANE13_CTRL_REG0__RX_BACKUP_13__SHIFT 0x00000000 +#define PB1_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13_MASK 0x00002000L +#define PB1_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13__SHIFT 0x0000000d +#define PB1_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13_MASK 0x00000c00L +#define PB1_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13__SHIFT 0x0000000a +#define PB1_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13_MASK 0x00001000L +#define PB1_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13__SHIFT 0x0000000c +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13_MASK 0x00000008L +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13__SHIFT 0x00000003 +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13_MASK 0x00000080L +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13__SHIFT 0x00000007 +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13_MASK 0x00000100L +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13__SHIFT 0x00000008 +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13_MASK 0x00000200L +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13__SHIFT 0x00000009 +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXPRESETHINT_13_MASK 0x00000070L +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXPRESETHINT_13__SHIFT 0x00000004 +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13_MASK 0x00000007L +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13__SHIFT 0x00000000 +#define PB1_RX_LANE14_CTRL_REG0__RX_BACKUP_14_MASK 0x000000ffL +#define PB1_RX_LANE14_CTRL_REG0__RX_BACKUP_14__SHIFT 0x00000000 +#define PB1_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14_MASK 0x00002000L +#define PB1_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14__SHIFT 0x0000000d +#define PB1_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14_MASK 0x00000c00L +#define PB1_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14__SHIFT 0x0000000a +#define PB1_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14_MASK 0x00001000L +#define PB1_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14__SHIFT 0x0000000c +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14_MASK 0x00000008L +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14__SHIFT 0x00000003 +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14_MASK 0x00000080L +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14__SHIFT 0x00000007 +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14_MASK 0x00000100L +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14__SHIFT 0x00000008 +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14_MASK 0x00000200L +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14__SHIFT 0x00000009 +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXPRESETHINT_14_MASK 0x00000070L +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXPRESETHINT_14__SHIFT 0x00000004 +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14_MASK 0x00000007L +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14__SHIFT 0x00000000 +#define PB1_RX_LANE15_CTRL_REG0__RX_BACKUP_15_MASK 0x000000ffL +#define PB1_RX_LANE15_CTRL_REG0__RX_BACKUP_15__SHIFT 0x00000000 +#define PB1_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15_MASK 0x00002000L +#define PB1_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15__SHIFT 0x0000000d +#define PB1_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15_MASK 0x00000c00L +#define PB1_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15__SHIFT 0x0000000a +#define PB1_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15_MASK 0x00001000L +#define PB1_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15__SHIFT 0x0000000c +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15_MASK 0x00000008L +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15__SHIFT 0x00000003 +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15_MASK 0x00000080L +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15__SHIFT 0x00000007 +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15_MASK 0x00000100L +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15__SHIFT 0x00000008 +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15_MASK 0x00000200L +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15__SHIFT 0x00000009 +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXPRESETHINT_15_MASK 0x00000070L +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXPRESETHINT_15__SHIFT 0x00000004 +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15_MASK 0x00000007L +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15__SHIFT 0x00000000 +#define PB1_RX_LANE1_CTRL_REG0__RX_BACKUP_1_MASK 0x000000ffL +#define PB1_RX_LANE1_CTRL_REG0__RX_BACKUP_1__SHIFT 0x00000000 +#define PB1_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1_MASK 0x00002000L +#define PB1_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1__SHIFT 0x0000000d +#define PB1_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1_MASK 0x00000c00L +#define PB1_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1__SHIFT 0x0000000a +#define PB1_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1_MASK 0x00001000L +#define PB1_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1__SHIFT 0x0000000c +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1_MASK 0x00000008L +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1__SHIFT 0x00000003 +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1_MASK 0x00000080L +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1__SHIFT 0x00000007 +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1_MASK 0x00000100L +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1__SHIFT 0x00000008 +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1_MASK 0x00000200L +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1__SHIFT 0x00000009 +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXPRESETHINT_1_MASK 0x00000070L +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXPRESETHINT_1__SHIFT 0x00000004 +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1_MASK 0x00000007L +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1__SHIFT 0x00000000 +#define PB1_RX_LANE2_CTRL_REG0__RX_BACKUP_2_MASK 0x000000ffL +#define PB1_RX_LANE2_CTRL_REG0__RX_BACKUP_2__SHIFT 0x00000000 +#define PB1_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2_MASK 0x00002000L +#define PB1_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2__SHIFT 0x0000000d +#define PB1_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2_MASK 0x00000c00L +#define PB1_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2__SHIFT 0x0000000a +#define PB1_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2_MASK 0x00001000L +#define PB1_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2__SHIFT 0x0000000c +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2_MASK 0x00000008L +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2__SHIFT 0x00000003 +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2_MASK 0x00000080L +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2__SHIFT 0x00000007 +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2_MASK 0x00000100L +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2__SHIFT 0x00000008 +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2_MASK 0x00000200L +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2__SHIFT 0x00000009 +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXPRESETHINT_2_MASK 0x00000070L +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXPRESETHINT_2__SHIFT 0x00000004 +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2_MASK 0x00000007L +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2__SHIFT 0x00000000 +#define PB1_RX_LANE3_CTRL_REG0__RX_BACKUP_3_MASK 0x000000ffL +#define PB1_RX_LANE3_CTRL_REG0__RX_BACKUP_3__SHIFT 0x00000000 +#define PB1_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3_MASK 0x00002000L +#define PB1_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3__SHIFT 0x0000000d +#define PB1_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3_MASK 0x00000c00L +#define PB1_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3__SHIFT 0x0000000a +#define PB1_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3_MASK 0x00001000L +#define PB1_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3__SHIFT 0x0000000c +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3_MASK 0x00000008L +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3__SHIFT 0x00000003 +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3_MASK 0x00000080L +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3__SHIFT 0x00000007 +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3_MASK 0x00000100L +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3__SHIFT 0x00000008 +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3_MASK 0x00000200L +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3__SHIFT 0x00000009 +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXPRESETHINT_3_MASK 0x00000070L +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXPRESETHINT_3__SHIFT 0x00000004 +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3_MASK 0x00000007L +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3__SHIFT 0x00000000 +#define PB1_RX_LANE4_CTRL_REG0__RX_BACKUP_4_MASK 0x000000ffL +#define PB1_RX_LANE4_CTRL_REG0__RX_BACKUP_4__SHIFT 0x00000000 +#define PB1_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4_MASK 0x00002000L +#define PB1_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4__SHIFT 0x0000000d +#define PB1_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4_MASK 0x00000c00L +#define PB1_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4__SHIFT 0x0000000a +#define PB1_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4_MASK 0x00001000L +#define PB1_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4__SHIFT 0x0000000c +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4_MASK 0x00000008L +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4__SHIFT 0x00000003 +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4_MASK 0x00000080L +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4__SHIFT 0x00000007 +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4_MASK 0x00000100L +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4__SHIFT 0x00000008 +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4_MASK 0x00000200L +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4__SHIFT 0x00000009 +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXPRESETHINT_4_MASK 0x00000070L +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXPRESETHINT_4__SHIFT 0x00000004 +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4_MASK 0x00000007L +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4__SHIFT 0x00000000 +#define PB1_RX_LANE5_CTRL_REG0__RX_BACKUP_5_MASK 0x000000ffL +#define PB1_RX_LANE5_CTRL_REG0__RX_BACKUP_5__SHIFT 0x00000000 +#define PB1_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5_MASK 0x00002000L +#define PB1_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5__SHIFT 0x0000000d +#define PB1_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5_MASK 0x00000c00L +#define PB1_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5__SHIFT 0x0000000a +#define PB1_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5_MASK 0x00001000L +#define PB1_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5__SHIFT 0x0000000c +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5_MASK 0x00000008L +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5__SHIFT 0x00000003 +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5_MASK 0x00000080L +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5__SHIFT 0x00000007 +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5_MASK 0x00000100L +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5__SHIFT 0x00000008 +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5_MASK 0x00000200L +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5__SHIFT 0x00000009 +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXPRESETHINT_5_MASK 0x00000070L +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXPRESETHINT_5__SHIFT 0x00000004 +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5_MASK 0x00000007L +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5__SHIFT 0x00000000 +#define PB1_RX_LANE6_CTRL_REG0__RX_BACKUP_6_MASK 0x000000ffL +#define PB1_RX_LANE6_CTRL_REG0__RX_BACKUP_6__SHIFT 0x00000000 +#define PB1_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6_MASK 0x00002000L +#define PB1_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6__SHIFT 0x0000000d +#define PB1_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6_MASK 0x00000c00L +#define PB1_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6__SHIFT 0x0000000a +#define PB1_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6_MASK 0x00001000L +#define PB1_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6__SHIFT 0x0000000c +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6_MASK 0x00000008L +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6__SHIFT 0x00000003 +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6_MASK 0x00000080L +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6__SHIFT 0x00000007 +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6_MASK 0x00000100L +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6__SHIFT 0x00000008 +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6_MASK 0x00000200L +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6__SHIFT 0x00000009 +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXPRESETHINT_6_MASK 0x00000070L +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXPRESETHINT_6__SHIFT 0x00000004 +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6_MASK 0x00000007L +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6__SHIFT 0x00000000 +#define PB1_RX_LANE7_CTRL_REG0__RX_BACKUP_7_MASK 0x000000ffL +#define PB1_RX_LANE7_CTRL_REG0__RX_BACKUP_7__SHIFT 0x00000000 +#define PB1_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7_MASK 0x00002000L +#define PB1_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7__SHIFT 0x0000000d +#define PB1_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7_MASK 0x00000c00L +#define PB1_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7__SHIFT 0x0000000a +#define PB1_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7_MASK 0x00001000L +#define PB1_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7__SHIFT 0x0000000c +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7_MASK 0x00000008L +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7__SHIFT 0x00000003 +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7_MASK 0x00000080L +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7__SHIFT 0x00000007 +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7_MASK 0x00000100L +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7__SHIFT 0x00000008 +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7_MASK 0x00000200L +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7__SHIFT 0x00000009 +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXPRESETHINT_7_MASK 0x00000070L +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXPRESETHINT_7__SHIFT 0x00000004 +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7_MASK 0x00000007L +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7__SHIFT 0x00000000 +#define PB1_RX_LANE8_CTRL_REG0__RX_BACKUP_8_MASK 0x000000ffL +#define PB1_RX_LANE8_CTRL_REG0__RX_BACKUP_8__SHIFT 0x00000000 +#define PB1_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8_MASK 0x00002000L +#define PB1_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8__SHIFT 0x0000000d +#define PB1_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8_MASK 0x00000c00L +#define PB1_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8__SHIFT 0x0000000a +#define PB1_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8_MASK 0x00001000L +#define PB1_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8__SHIFT 0x0000000c +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8_MASK 0x00000008L +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8__SHIFT 0x00000003 +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8_MASK 0x00000080L +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8__SHIFT 0x00000007 +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8_MASK 0x00000100L +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8__SHIFT 0x00000008 +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8_MASK 0x00000200L +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8__SHIFT 0x00000009 +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXPRESETHINT_8_MASK 0x00000070L +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXPRESETHINT_8__SHIFT 0x00000004 +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8_MASK 0x00000007L +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8__SHIFT 0x00000000 +#define PB1_RX_LANE9_CTRL_REG0__RX_BACKUP_9_MASK 0x000000ffL +#define PB1_RX_LANE9_CTRL_REG0__RX_BACKUP_9__SHIFT 0x00000000 +#define PB1_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9_MASK 0x00002000L +#define PB1_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9__SHIFT 0x0000000d +#define PB1_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9_MASK 0x00000c00L +#define PB1_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9__SHIFT 0x0000000a +#define PB1_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9_MASK 0x00001000L +#define PB1_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9__SHIFT 0x0000000c +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9_MASK 0x00000008L +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9__SHIFT 0x00000003 +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9_MASK 0x00000080L +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9__SHIFT 0x00000007 +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9_MASK 0x00000100L +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9__SHIFT 0x00000008 +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9_MASK 0x00000200L +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9__SHIFT 0x00000009 +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXPRESETHINT_9_MASK 0x00000070L +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXPRESETHINT_9__SHIFT 0x00000004 +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9_MASK 0x00000007L +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9__SHIFT 0x00000000 +#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL_MASK 0x00008000L +#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL__SHIFT 0x0000000f +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0_MASK 0x00000001L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0__SHIFT 0x00000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10_MASK 0x00000400L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10__SHIFT 0x0000000a +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11_MASK 0x00000800L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11__SHIFT 0x0000000b +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12_MASK 0x00001000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12__SHIFT 0x0000000c +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13_MASK 0x00002000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13__SHIFT 0x0000000d +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14_MASK 0x00004000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14__SHIFT 0x0000000e +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15_MASK 0x00008000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15__SHIFT 0x0000000f +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16_MASK 0x00010000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16__SHIFT 0x00000010 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17_MASK 0x00020000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17__SHIFT 0x00000011 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18_MASK 0x00040000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18__SHIFT 0x00000012 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19_MASK 0x00080000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19__SHIFT 0x00000013 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1_MASK 0x00000002L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1__SHIFT 0x00000001 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20_MASK 0x00100000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20__SHIFT 0x00000014 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21_MASK 0x00200000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21__SHIFT 0x00000015 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22_MASK 0x00400000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22__SHIFT 0x00000016 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23_MASK 0x00800000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23__SHIFT 0x00000017 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24_MASK 0x01000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24__SHIFT 0x00000018 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25_MASK 0x02000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25__SHIFT 0x00000019 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26_MASK 0x04000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26__SHIFT 0x0000001a +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27_MASK 0x08000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27__SHIFT 0x0000001b +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28_MASK 0x10000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28__SHIFT 0x0000001c +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29_MASK 0x20000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29__SHIFT 0x0000001d +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2_MASK 0x00000004L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2__SHIFT 0x00000002 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30_MASK 0x40000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30__SHIFT 0x0000001e +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31_MASK 0x80000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31__SHIFT 0x0000001f +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3_MASK 0x00000008L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3__SHIFT 0x00000003 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4_MASK 0x00000010L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4__SHIFT 0x00000004 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5_MASK 0x00000020L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5__SHIFT 0x00000005 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6_MASK 0x00000040L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6__SHIFT 0x00000006 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7_MASK 0x00000080L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7__SHIFT 0x00000007 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8_MASK 0x00000100L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8__SHIFT 0x00000008 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9_MASK 0x00000200L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9__SHIFT 0x00000009 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32_MASK 0x00000001L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32__SHIFT 0x00000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33_MASK 0x00000002L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33__SHIFT 0x00000001 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34_MASK 0x00000004L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34__SHIFT 0x00000002 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35_MASK 0x00000008L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35__SHIFT 0x00000003 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36_MASK 0x00000010L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36__SHIFT 0x00000004 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37_MASK 0x00000020L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37__SHIFT 0x00000005 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38_MASK 0x00000040L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38__SHIFT 0x00000006 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39_MASK 0x00000080L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39__SHIFT 0x00000007 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40_MASK 0x00000100L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40__SHIFT 0x00000008 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41_MASK 0x00000200L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41__SHIFT 0x00000009 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42_MASK 0x00000400L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42__SHIFT 0x0000000a +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43_MASK 0x00000800L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43__SHIFT 0x0000000b +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44_MASK 0x00001000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44__SHIFT 0x0000000c +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45_MASK 0x00002000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45__SHIFT 0x0000000d +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46_MASK 0x00004000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46__SHIFT 0x0000000e +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47_MASK 0x00008000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47__SHIFT 0x0000000f +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48_MASK 0x00010000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48__SHIFT 0x00000010 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49_MASK 0x00020000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49__SHIFT 0x00000011 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50_MASK 0x00040000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50__SHIFT 0x00000012 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51_MASK 0x00080000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51__SHIFT 0x00000013 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52_MASK 0x00100000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52__SHIFT 0x00000014 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53_MASK 0x00200000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53__SHIFT 0x00000015 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54_MASK 0x00400000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54__SHIFT 0x00000016 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55_MASK 0x00800000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55__SHIFT 0x00000017 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56_MASK 0x01000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56__SHIFT 0x00000018 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57_MASK 0x02000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57__SHIFT 0x00000019 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58_MASK 0x04000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58__SHIFT 0x0000001a +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59_MASK 0x08000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59__SHIFT 0x0000001b +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60_MASK 0x10000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60__SHIFT 0x0000001c +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61_MASK 0x20000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61__SHIFT 0x0000001d +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62_MASK 0x40000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62__SHIFT 0x0000001e +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63_MASK 0x80000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63__SHIFT 0x0000001f +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64_MASK 0x00000001L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64__SHIFT 0x00000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65_MASK 0x00000002L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65__SHIFT 0x00000001 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66_MASK 0x00000004L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66__SHIFT 0x00000002 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67_MASK 0x00000008L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67__SHIFT 0x00000003 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68_MASK 0x00000010L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68__SHIFT 0x00000004 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69_MASK 0x00000020L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69__SHIFT 0x00000005 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70_MASK 0x00000040L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70__SHIFT 0x00000006 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71_MASK 0x00000080L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71__SHIFT 0x00000007 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72_MASK 0x00000100L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72__SHIFT 0x00000008 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73_MASK 0x00000200L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73__SHIFT 0x00000009 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74_MASK 0x00000400L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74__SHIFT 0x0000000a +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75_MASK 0x00000800L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75__SHIFT 0x0000000b +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76_MASK 0x00001000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76__SHIFT 0x0000000c +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77_MASK 0x00002000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77__SHIFT 0x0000000d +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78_MASK 0x00004000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78__SHIFT 0x0000000e +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79_MASK 0x00008000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79__SHIFT 0x0000000f +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80_MASK 0x00010000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80__SHIFT 0x00000010 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81_MASK 0x00020000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81__SHIFT 0x00000011 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82_MASK 0x00040000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82__SHIFT 0x00000012 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83_MASK 0x00080000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83__SHIFT 0x00000013 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84_MASK 0x00100000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84__SHIFT 0x00000014 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85_MASK 0x00200000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85__SHIFT 0x00000015 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86_MASK 0x00400000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86__SHIFT 0x00000016 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87_MASK 0x00800000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87__SHIFT 0x00000017 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88_MASK 0x01000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88__SHIFT 0x00000018 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89_MASK 0x02000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89__SHIFT 0x00000019 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90_MASK 0x04000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90__SHIFT 0x0000001a +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91_MASK 0x08000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91__SHIFT 0x0000001b +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92_MASK 0x10000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92__SHIFT 0x0000001c +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93_MASK 0x20000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93__SHIFT 0x0000001d +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94_MASK 0x40000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94__SHIFT 0x0000001e +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95_MASK 0x80000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95__SHIFT 0x0000001f +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100_MASK 0x00000010L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100__SHIFT 0x00000004 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101_MASK 0x00000020L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101__SHIFT 0x00000005 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102_MASK 0x00000040L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102__SHIFT 0x00000006 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103_MASK 0x00000080L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103__SHIFT 0x00000007 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104_MASK 0x00000100L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104__SHIFT 0x00000008 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105_MASK 0x00000200L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105__SHIFT 0x00000009 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106_MASK 0x00000400L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106__SHIFT 0x0000000a +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107_MASK 0x00000800L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107__SHIFT 0x0000000b +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108_MASK 0x00001000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108__SHIFT 0x0000000c +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109_MASK 0x00002000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109__SHIFT 0x0000000d +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96_MASK 0x00000001L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96__SHIFT 0x00000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97_MASK 0x00000002L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97__SHIFT 0x00000001 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98_MASK 0x00000004L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98__SHIFT 0x00000002 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99_MASK 0x00000008L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99__SHIFT 0x00000003 +#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1_MASK 0x00000700L +#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1__SHIFT 0x00000008 +#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2_MASK 0x00003800L +#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2__SHIFT 0x0000000b +#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3_MASK 0x0001c000L +#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3__SHIFT 0x0000000e +#define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER_MASK 0x00400000L +#define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER__SHIFT 0x00000016 +#define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN_MASK 0x00200000L +#define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN__SHIFT 0x00000015 +#define PB1_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING_MASK 0x00080000L +#define PB1_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING__SHIFT 0x00000013 +#define PB1_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON_MASK 0x00800000L +#define PB1_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON__SHIFT 0x00000017 +#define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL_MASK 0x00000007L +#define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL__SHIFT 0x00000000 +#define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL_MASK 0x00000038L +#define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL__SHIFT 0x00000003 +#define PB1_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_OFF_MASK 0x01000000L +#define PB1_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_OFF__SHIFT 0x00000018 +#define PB1_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS_MASK 0x00100000L +#define PB1_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS__SHIFT 0x00000014 +#define PB1_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL_MASK 0x00060000L +#define PB1_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL__SHIFT 0x00000011 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15_MASK 0x40000000L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15__SHIFT 0x0000001e +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0_MASK 0x00000001L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0__SHIFT 0x00000000 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10_MASK 0x00000400L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10__SHIFT 0x0000000a +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11_MASK 0x00000800L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11__SHIFT 0x0000000b +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12_MASK 0x00001000L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12__SHIFT 0x0000000c +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13_MASK 0x00002000L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13__SHIFT 0x0000000d +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14_MASK 0x00004000L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14__SHIFT 0x0000000e +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15_MASK 0x00008000L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15__SHIFT 0x0000000f +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1_MASK 0x00000002L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1__SHIFT 0x00000001 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2_MASK 0x00000004L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2__SHIFT 0x00000002 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3_MASK 0x00000008L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3__SHIFT 0x00000003 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4_MASK 0x00000010L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4__SHIFT 0x00000004 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5_MASK 0x00000020L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5__SHIFT 0x00000005 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6_MASK 0x00000040L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6__SHIFT 0x00000006 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7_MASK 0x00000080L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7__SHIFT 0x00000007 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8_MASK 0x00000100L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8__SHIFT 0x00000008 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9_MASK 0x00000200L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9__SHIFT 0x00000009 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1_MASK 0x00010000L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1__SHIFT 0x00000010 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11_MASK 0x00200000L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11__SHIFT 0x00000015 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13_MASK 0x00400000L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13__SHIFT 0x00000016 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15_MASK 0x00800000L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15__SHIFT 0x00000017 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3_MASK 0x00020000L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3__SHIFT 0x00000011 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5_MASK 0x00040000L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5__SHIFT 0x00000012 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7_MASK 0x00080000L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7__SHIFT 0x00000013 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9_MASK 0x00100000L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9__SHIFT 0x00000014 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3_MASK 0x01000000L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3__SHIFT 0x00000018 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15_MASK 0x08000000L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15__SHIFT 0x0000001b +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7_MASK 0x02000000L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7__SHIFT 0x00000019 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11_MASK 0x04000000L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11__SHIFT 0x0000001a +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7_MASK 0x10000000L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7__SHIFT 0x0000001c +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15_MASK 0x20000000L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15__SHIFT 0x0000001d +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN_MASK 0x00000008L +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x00000003 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL_MASK 0x00000007L +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x00000000 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL_MASK 0x000000f0L +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL__SHIFT 0x00000004 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN_MASK 0x00000100L +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN__SHIFT 0x00000008 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL_MASK 0x00001e00L +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x00000009 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN_MASK 0x00002000L +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN__SHIFT 0x0000000d +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL_MASK 0x0007c000L +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL__SHIFT 0x0000000e +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN_MASK 0x00080000L +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN__SHIFT 0x00000013 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL_MASK 0x01f00000L +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x00000014 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN_MASK 0x02000000L +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN__SHIFT 0x00000019 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL_MASK 0x3c000000L +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL__SHIFT 0x0000001a +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN_MASK 0x40000000L +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN__SHIFT 0x0000001e +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL_MASK 0x0000000fL +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x00000000 +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN_MASK 0x00000010L +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN__SHIFT 0x00000004 +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL_MASK 0x00000020L +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL__SHIFT 0x00000005 +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN_MASK 0x00000040L +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN__SHIFT 0x00000006 +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL_MASK 0x00000080L +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x00000007 +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN_MASK 0x00000100L +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN__SHIFT 0x00000008 +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x00000400L +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0x0000000a +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x00000200L +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0x00000009 +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN_MASK 0x00001000L +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN__SHIFT 0x0000000c +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL_MASK 0x00000800L +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL__SHIFT 0x0000000b +#define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN_MASK 0x00004000L +#define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN__SHIFT 0x0000000e +#define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL_MASK 0x00002000L +#define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL__SHIFT 0x0000000d +#define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN_MASK 0x02000000L +#define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN__SHIFT 0x00000019 +#define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL_MASK 0x01ff8000L +#define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL__SHIFT 0x0000000f +#define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN_MASK 0x08000000L +#define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN__SHIFT 0x0000001b +#define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL_MASK 0x04000000L +#define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL__SHIFT 0x0000001a +#define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN_MASK 0x20000000L +#define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN__SHIFT 0x0000001d +#define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL_MASK 0x10000000L +#define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL__SHIFT 0x0000001c +#define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN_MASK 0x80000000L +#define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN__SHIFT 0x0000001f +#define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL_MASK 0x40000000L +#define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL__SHIFT 0x0000001e +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL_MASK 0x0000f000L +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL__SHIFT 0x0000000c +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL_MASK 0x000f0000L +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x00000010 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL_MASK 0x01f00000L +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL__SHIFT 0x00000014 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL_MASK 0x3e000000L +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x00000019 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN_MASK 0x00000800L +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN__SHIFT 0x0000000b +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL_MASK 0x00000400L +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL__SHIFT 0x0000000a +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN_MASK 0x00000008L +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN__SHIFT 0x00000003 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL_MASK 0x00000004L +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL__SHIFT 0x00000002 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN_MASK 0x00000020L +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN__SHIFT 0x00000005 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL_MASK 0x00000010L +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL__SHIFT 0x00000004 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN_MASK 0x00000080L +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN__SHIFT 0x00000007 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL_MASK 0x00000040L +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL__SHIFT 0x00000006 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN_MASK 0x00000200L +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN__SHIFT 0x00000009 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL_MASK 0x00000100L +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL__SHIFT 0x00000008 +#define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN_MASK 0x00000002L +#define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN__SHIFT 0x00000001 +#define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL_MASK 0x00000001L +#define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL__SHIFT 0x00000000 +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL_MASK 0x00003c00L +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL__SHIFT 0x0000000a +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL_MASK 0x0003c000L +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x0000000e +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL_MASK 0x007c0000L +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL__SHIFT 0x00000012 +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL_MASK 0x0f800000L +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x00000017 +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL_MASK 0x0000000fL +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL__SHIFT 0x00000000 +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL_MASK 0xf0000000L +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL__SHIFT 0x0000001c +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL_MASK 0x000000f0L +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x00000004 +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL_MASK 0x00000100L +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL__SHIFT 0x00000008 +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL_MASK 0x00000200L +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x00000009 +#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL_MASK 0x0000000fL +#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x00000000 +#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL_MASK 0x00000010L +#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL__SHIFT 0x00000004 +#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL_MASK 0x00000020L +#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x00000005 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L0T3_MASK 0x00000100L +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L0T3__SHIFT 0x00000008 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L12T15_MASK 0x00000800L +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L12T15__SHIFT 0x0000000b +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L4T7_MASK 0x00000200L +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L4T7__SHIFT 0x00000009 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L8T11_MASK 0x00000400L +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L8T11__SHIFT 0x0000000a +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L0T3_MASK 0x00001000L +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L0T3__SHIFT 0x0000000c +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L12T15_MASK 0x00008000L +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L12T15__SHIFT 0x0000000f +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L4T7_MASK 0x00002000L +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L4T7__SHIFT 0x0000000d +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L8T11_MASK 0x00004000L +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L8T11__SHIFT 0x0000000e +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L0T3_MASK 0x00000010L +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L0T3__SHIFT 0x00000004 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L12T15_MASK 0x00000080L +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L12T15__SHIFT 0x00000007 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L4T7_MASK 0x00000020L +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L4T7__SHIFT 0x00000005 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L8T11_MASK 0x00000040L +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L8T11__SHIFT 0x00000006 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L0T3_MASK 0x00000001L +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L0T3__SHIFT 0x00000000 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L12T15_MASK 0x00000008L +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L12T15__SHIFT 0x00000003 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L4T7_MASK 0x00000002L +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L4T7__SHIFT 0x00000001 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L8T11_MASK 0x00000004L +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L8T11__SHIFT 0x00000002 +#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0_MASK 0x00000001L +#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0__SHIFT 0x00000000 +#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0_MASK 0x00000002L +#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0__SHIFT 0x00000001 +#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0_MASK 0x00000004L +#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0__SHIFT 0x00000002 +#define PB1_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0_MASK 0x00000008L +#define PB1_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0__SHIFT 0x00000003 +#define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0_MASK 0x00000002L +#define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0__SHIFT 0x00000001 +#define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0_MASK 0x00000001L +#define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0__SHIFT 0x00000000 +#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0_MASK 0x00000008L +#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0__SHIFT 0x00000003 +#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0_MASK 0x00000004L +#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0__SHIFT 0x00000002 +#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0_MASK 0x00000020L +#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0__SHIFT 0x00000005 +#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0_MASK 0x00000010L +#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0__SHIFT 0x00000004 +#define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0_MASK 0x00000080L +#define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0__SHIFT 0x00000007 +#define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0_MASK 0x00000040L +#define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0__SHIFT 0x00000006 +#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0_MASK 0x0000fc00L +#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0__SHIFT 0x0000000a +#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0_MASK 0x00000300L +#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0__SHIFT 0x00000008 +#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0_MASK 0x00000080L +#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0__SHIFT 0x00000007 +#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__INCOHERENTCK_0_MASK 0x00000008L +#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__INCOHERENTCK_0__SHIFT 0x00000003 +#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0_MASK 0x00000070L +#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0__SHIFT 0x00000004 +#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0_MASK 0x00000007L +#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0__SHIFT 0x00000000 +#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10_MASK 0x00000001L +#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10__SHIFT 0x00000000 +#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10_MASK 0x00000002L +#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10__SHIFT 0x00000001 +#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10_MASK 0x00000004L +#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10__SHIFT 0x00000002 +#define PB1_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10_MASK 0x00000008L +#define PB1_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10__SHIFT 0x00000003 +#define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10_MASK 0x00000002L +#define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10__SHIFT 0x00000001 +#define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10_MASK 0x00000001L +#define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10__SHIFT 0x00000000 +#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10_MASK 0x00000008L +#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10__SHIFT 0x00000003 +#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10_MASK 0x00000004L +#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10__SHIFT 0x00000002 +#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10_MASK 0x00000020L +#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10__SHIFT 0x00000005 +#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10_MASK 0x00000010L +#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10__SHIFT 0x00000004 +#define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10_MASK 0x00000080L +#define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10__SHIFT 0x00000007 +#define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10_MASK 0x00000040L +#define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10__SHIFT 0x00000006 +#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10_MASK 0x0000fc00L +#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10__SHIFT 0x0000000a +#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10_MASK 0x00000300L +#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10__SHIFT 0x00000008 +#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10_MASK 0x00000080L +#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10__SHIFT 0x00000007 +#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__INCOHERENTCK_10_MASK 0x00000008L +#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__INCOHERENTCK_10__SHIFT 0x00000003 +#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10_MASK 0x00000070L +#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10__SHIFT 0x00000004 +#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10_MASK 0x00000007L +#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10__SHIFT 0x00000000 +#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11_MASK 0x00000001L +#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11__SHIFT 0x00000000 +#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11_MASK 0x00000002L +#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11__SHIFT 0x00000001 +#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11_MASK 0x00000004L +#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11__SHIFT 0x00000002 +#define PB1_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11_MASK 0x00000008L +#define PB1_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11__SHIFT 0x00000003 +#define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11_MASK 0x00000002L +#define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11__SHIFT 0x00000001 +#define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11_MASK 0x00000001L +#define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11__SHIFT 0x00000000 +#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11_MASK 0x00000008L +#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11__SHIFT 0x00000003 +#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11_MASK 0x00000004L +#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11__SHIFT 0x00000002 +#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11_MASK 0x00000020L +#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11__SHIFT 0x00000005 +#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11_MASK 0x00000010L +#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11__SHIFT 0x00000004 +#define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11_MASK 0x00000080L +#define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11__SHIFT 0x00000007 +#define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11_MASK 0x00000040L +#define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11__SHIFT 0x00000006 +#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11_MASK 0x0000fc00L +#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11__SHIFT 0x0000000a +#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11_MASK 0x00000300L +#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11__SHIFT 0x00000008 +#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11_MASK 0x00000080L +#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11__SHIFT 0x00000007 +#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__INCOHERENTCK_11_MASK 0x00000008L +#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__INCOHERENTCK_11__SHIFT 0x00000003 +#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11_MASK 0x00000070L +#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11__SHIFT 0x00000004 +#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11_MASK 0x00000007L +#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11__SHIFT 0x00000000 +#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12_MASK 0x00000001L +#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12__SHIFT 0x00000000 +#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12_MASK 0x00000002L +#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12__SHIFT 0x00000001 +#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12_MASK 0x00000004L +#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12__SHIFT 0x00000002 +#define PB1_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12_MASK 0x00000008L +#define PB1_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12__SHIFT 0x00000003 +#define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12_MASK 0x00000002L +#define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12__SHIFT 0x00000001 +#define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12_MASK 0x00000001L +#define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12__SHIFT 0x00000000 +#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12_MASK 0x00000008L +#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12__SHIFT 0x00000003 +#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12_MASK 0x00000004L +#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12__SHIFT 0x00000002 +#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12_MASK 0x00000020L +#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12__SHIFT 0x00000005 +#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12_MASK 0x00000010L +#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12__SHIFT 0x00000004 +#define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12_MASK 0x00000080L +#define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12__SHIFT 0x00000007 +#define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12_MASK 0x00000040L +#define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12__SHIFT 0x00000006 +#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12_MASK 0x0000fc00L +#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12__SHIFT 0x0000000a +#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12_MASK 0x00000300L +#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12__SHIFT 0x00000008 +#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12_MASK 0x00000080L +#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12__SHIFT 0x00000007 +#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__INCOHERENTCK_12_MASK 0x00000008L +#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__INCOHERENTCK_12__SHIFT 0x00000003 +#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12_MASK 0x00000070L +#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12__SHIFT 0x00000004 +#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12_MASK 0x00000007L +#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12__SHIFT 0x00000000 +#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13_MASK 0x00000001L +#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13__SHIFT 0x00000000 +#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13_MASK 0x00000002L +#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13__SHIFT 0x00000001 +#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13_MASK 0x00000004L +#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13__SHIFT 0x00000002 +#define PB1_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13_MASK 0x00000008L +#define PB1_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13__SHIFT 0x00000003 +#define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13_MASK 0x00000002L +#define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13__SHIFT 0x00000001 +#define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13_MASK 0x00000001L +#define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13__SHIFT 0x00000000 +#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13_MASK 0x00000008L +#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13__SHIFT 0x00000003 +#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13_MASK 0x00000004L +#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13__SHIFT 0x00000002 +#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13_MASK 0x00000020L +#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13__SHIFT 0x00000005 +#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13_MASK 0x00000010L +#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13__SHIFT 0x00000004 +#define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13_MASK 0x00000080L +#define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13__SHIFT 0x00000007 +#define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13_MASK 0x00000040L +#define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13__SHIFT 0x00000006 +#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13_MASK 0x0000fc00L +#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13__SHIFT 0x0000000a +#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13_MASK 0x00000300L +#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13__SHIFT 0x00000008 +#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13_MASK 0x00000080L +#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13__SHIFT 0x00000007 +#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__INCOHERENTCK_13_MASK 0x00000008L +#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__INCOHERENTCK_13__SHIFT 0x00000003 +#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13_MASK 0x00000070L +#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13__SHIFT 0x00000004 +#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13_MASK 0x00000007L +#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13__SHIFT 0x00000000 +#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14_MASK 0x00000001L +#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14__SHIFT 0x00000000 +#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14_MASK 0x00000002L +#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14__SHIFT 0x00000001 +#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14_MASK 0x00000004L +#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14__SHIFT 0x00000002 +#define PB1_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14_MASK 0x00000008L +#define PB1_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14__SHIFT 0x00000003 +#define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14_MASK 0x00000002L +#define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14__SHIFT 0x00000001 +#define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14_MASK 0x00000001L +#define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14__SHIFT 0x00000000 +#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14_MASK 0x00000008L +#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14__SHIFT 0x00000003 +#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14_MASK 0x00000004L +#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14__SHIFT 0x00000002 +#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14_MASK 0x00000020L +#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14__SHIFT 0x00000005 +#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14_MASK 0x00000010L +#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14__SHIFT 0x00000004 +#define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14_MASK 0x00000080L +#define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14__SHIFT 0x00000007 +#define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14_MASK 0x00000040L +#define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14__SHIFT 0x00000006 +#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14_MASK 0x0000fc00L +#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14__SHIFT 0x0000000a +#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14_MASK 0x00000300L +#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14__SHIFT 0x00000008 +#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14_MASK 0x00000080L +#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14__SHIFT 0x00000007 +#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__INCOHERENTCK_14_MASK 0x00000008L +#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__INCOHERENTCK_14__SHIFT 0x00000003 +#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14_MASK 0x00000070L +#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14__SHIFT 0x00000004 +#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14_MASK 0x00000007L +#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14__SHIFT 0x00000000 +#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15_MASK 0x00000001L +#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15__SHIFT 0x00000000 +#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15_MASK 0x00000002L +#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15__SHIFT 0x00000001 +#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15_MASK 0x00000004L +#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15__SHIFT 0x00000002 +#define PB1_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15_MASK 0x00000008L +#define PB1_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15__SHIFT 0x00000003 +#define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15_MASK 0x00000002L +#define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15__SHIFT 0x00000001 +#define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15_MASK 0x00000001L +#define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15__SHIFT 0x00000000 +#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15_MASK 0x00000008L +#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15__SHIFT 0x00000003 +#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15_MASK 0x00000004L +#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15__SHIFT 0x00000002 +#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15_MASK 0x00000020L +#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15__SHIFT 0x00000005 +#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15_MASK 0x00000010L +#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15__SHIFT 0x00000004 +#define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15_MASK 0x00000080L +#define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15__SHIFT 0x00000007 +#define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15_MASK 0x00000040L +#define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15__SHIFT 0x00000006 +#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15_MASK 0x0000fc00L +#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15__SHIFT 0x0000000a +#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15_MASK 0x00000300L +#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15__SHIFT 0x00000008 +#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15_MASK 0x00000080L +#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15__SHIFT 0x00000007 +#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__INCOHERENTCK_15_MASK 0x00000008L +#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__INCOHERENTCK_15__SHIFT 0x00000003 +#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15_MASK 0x00000070L +#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15__SHIFT 0x00000004 +#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15_MASK 0x00000007L +#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15__SHIFT 0x00000000 +#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1_MASK 0x00000001L +#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1__SHIFT 0x00000000 +#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1_MASK 0x00000002L +#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1__SHIFT 0x00000001 +#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1_MASK 0x00000004L +#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1__SHIFT 0x00000002 +#define PB1_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1_MASK 0x00000008L +#define PB1_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1__SHIFT 0x00000003 +#define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1_MASK 0x00000002L +#define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1__SHIFT 0x00000001 +#define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1_MASK 0x00000001L +#define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1__SHIFT 0x00000000 +#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1_MASK 0x00000008L +#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1__SHIFT 0x00000003 +#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1_MASK 0x00000004L +#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1__SHIFT 0x00000002 +#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1_MASK 0x00000020L +#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1__SHIFT 0x00000005 +#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1_MASK 0x00000010L +#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1__SHIFT 0x00000004 +#define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1_MASK 0x00000080L +#define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1__SHIFT 0x00000007 +#define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1_MASK 0x00000040L +#define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1__SHIFT 0x00000006 +#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1_MASK 0x0000fc00L +#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1__SHIFT 0x0000000a +#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1_MASK 0x00000300L +#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1__SHIFT 0x00000008 +#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1_MASK 0x00000080L +#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1__SHIFT 0x00000007 +#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__INCOHERENTCK_1_MASK 0x00000008L +#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__INCOHERENTCK_1__SHIFT 0x00000003 +#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1_MASK 0x00000070L +#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1__SHIFT 0x00000004 +#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1_MASK 0x00000007L +#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1__SHIFT 0x00000000 +#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2_MASK 0x00000001L +#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2__SHIFT 0x00000000 +#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2_MASK 0x00000002L +#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2__SHIFT 0x00000001 +#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2_MASK 0x00000004L +#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2__SHIFT 0x00000002 +#define PB1_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2_MASK 0x00000008L +#define PB1_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2__SHIFT 0x00000003 +#define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2_MASK 0x00000002L +#define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2__SHIFT 0x00000001 +#define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2_MASK 0x00000001L +#define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2__SHIFT 0x00000000 +#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2_MASK 0x00000008L +#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2__SHIFT 0x00000003 +#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2_MASK 0x00000004L +#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2__SHIFT 0x00000002 +#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2_MASK 0x00000020L +#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2__SHIFT 0x00000005 +#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2_MASK 0x00000010L +#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2__SHIFT 0x00000004 +#define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2_MASK 0x00000080L +#define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2__SHIFT 0x00000007 +#define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2_MASK 0x00000040L +#define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2__SHIFT 0x00000006 +#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2_MASK 0x0000fc00L +#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2__SHIFT 0x0000000a +#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2_MASK 0x00000300L +#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2__SHIFT 0x00000008 +#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2_MASK 0x00000080L +#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2__SHIFT 0x00000007 +#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__INCOHERENTCK_2_MASK 0x00000008L +#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__INCOHERENTCK_2__SHIFT 0x00000003 +#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2_MASK 0x00000070L +#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2__SHIFT 0x00000004 +#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2_MASK 0x00000007L +#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2__SHIFT 0x00000000 +#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3_MASK 0x00000001L +#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3__SHIFT 0x00000000 +#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3_MASK 0x00000002L +#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3__SHIFT 0x00000001 +#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3_MASK 0x00000004L +#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3__SHIFT 0x00000002 +#define PB1_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3_MASK 0x00000008L +#define PB1_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3__SHIFT 0x00000003 +#define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3_MASK 0x00000002L +#define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3__SHIFT 0x00000001 +#define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3_MASK 0x00000001L +#define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3__SHIFT 0x00000000 +#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3_MASK 0x00000008L +#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3__SHIFT 0x00000003 +#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3_MASK 0x00000004L +#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3__SHIFT 0x00000002 +#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3_MASK 0x00000020L +#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3__SHIFT 0x00000005 +#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3_MASK 0x00000010L +#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3__SHIFT 0x00000004 +#define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3_MASK 0x00000080L +#define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3__SHIFT 0x00000007 +#define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3_MASK 0x00000040L +#define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3__SHIFT 0x00000006 +#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3_MASK 0x0000fc00L +#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3__SHIFT 0x0000000a +#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3_MASK 0x00000300L +#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3__SHIFT 0x00000008 +#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3_MASK 0x00000080L +#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3__SHIFT 0x00000007 +#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__INCOHERENTCK_3_MASK 0x00000008L +#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__INCOHERENTCK_3__SHIFT 0x00000003 +#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3_MASK 0x00000070L +#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3__SHIFT 0x00000004 +#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3_MASK 0x00000007L +#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3__SHIFT 0x00000000 +#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4_MASK 0x00000001L +#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4__SHIFT 0x00000000 +#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4_MASK 0x00000002L +#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4__SHIFT 0x00000001 +#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4_MASK 0x00000004L +#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4__SHIFT 0x00000002 +#define PB1_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4_MASK 0x00000008L +#define PB1_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4__SHIFT 0x00000003 +#define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4_MASK 0x00000002L +#define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4__SHIFT 0x00000001 +#define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4_MASK 0x00000001L +#define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4__SHIFT 0x00000000 +#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4_MASK 0x00000008L +#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4__SHIFT 0x00000003 +#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4_MASK 0x00000004L +#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4__SHIFT 0x00000002 +#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4_MASK 0x00000020L +#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4__SHIFT 0x00000005 +#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4_MASK 0x00000010L +#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4__SHIFT 0x00000004 +#define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4_MASK 0x00000080L +#define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4__SHIFT 0x00000007 +#define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4_MASK 0x00000040L +#define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4__SHIFT 0x00000006 +#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4_MASK 0x0000fc00L +#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4__SHIFT 0x0000000a +#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4_MASK 0x00000300L +#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4__SHIFT 0x00000008 +#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4_MASK 0x00000080L +#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4__SHIFT 0x00000007 +#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__INCOHERENTCK_4_MASK 0x00000008L +#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__INCOHERENTCK_4__SHIFT 0x00000003 +#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4_MASK 0x00000070L +#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4__SHIFT 0x00000004 +#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4_MASK 0x00000007L +#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4__SHIFT 0x00000000 +#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5_MASK 0x00000001L +#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5__SHIFT 0x00000000 +#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5_MASK 0x00000002L +#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5__SHIFT 0x00000001 +#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5_MASK 0x00000004L +#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5__SHIFT 0x00000002 +#define PB1_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5_MASK 0x00000008L +#define PB1_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5__SHIFT 0x00000003 +#define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5_MASK 0x00000002L +#define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5__SHIFT 0x00000001 +#define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5_MASK 0x00000001L +#define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5__SHIFT 0x00000000 +#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5_MASK 0x00000008L +#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5__SHIFT 0x00000003 +#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5_MASK 0x00000004L +#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5__SHIFT 0x00000002 +#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5_MASK 0x00000020L +#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5__SHIFT 0x00000005 +#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5_MASK 0x00000010L +#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5__SHIFT 0x00000004 +#define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5_MASK 0x00000080L +#define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5__SHIFT 0x00000007 +#define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5_MASK 0x00000040L +#define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5__SHIFT 0x00000006 +#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5_MASK 0x0000fc00L +#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5__SHIFT 0x0000000a +#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5_MASK 0x00000300L +#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5__SHIFT 0x00000008 +#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5_MASK 0x00000080L +#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5__SHIFT 0x00000007 +#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__INCOHERENTCK_5_MASK 0x00000008L +#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__INCOHERENTCK_5__SHIFT 0x00000003 +#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5_MASK 0x00000070L +#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5__SHIFT 0x00000004 +#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5_MASK 0x00000007L +#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5__SHIFT 0x00000000 +#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6_MASK 0x00000001L +#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6__SHIFT 0x00000000 +#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6_MASK 0x00000002L +#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6__SHIFT 0x00000001 +#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6_MASK 0x00000004L +#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6__SHIFT 0x00000002 +#define PB1_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6_MASK 0x00000008L +#define PB1_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6__SHIFT 0x00000003 +#define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6_MASK 0x00000002L +#define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6__SHIFT 0x00000001 +#define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6_MASK 0x00000001L +#define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6__SHIFT 0x00000000 +#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6_MASK 0x00000008L +#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6__SHIFT 0x00000003 +#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6_MASK 0x00000004L +#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6__SHIFT 0x00000002 +#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6_MASK 0x00000020L +#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6__SHIFT 0x00000005 +#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6_MASK 0x00000010L +#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6__SHIFT 0x00000004 +#define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6_MASK 0x00000080L +#define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6__SHIFT 0x00000007 +#define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6_MASK 0x00000040L +#define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6__SHIFT 0x00000006 +#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6_MASK 0x0000fc00L +#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6__SHIFT 0x0000000a +#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6_MASK 0x00000300L +#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6__SHIFT 0x00000008 +#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6_MASK 0x00000080L +#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6__SHIFT 0x00000007 +#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__INCOHERENTCK_6_MASK 0x00000008L +#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__INCOHERENTCK_6__SHIFT 0x00000003 +#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6_MASK 0x00000070L +#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6__SHIFT 0x00000004 +#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6_MASK 0x00000007L +#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6__SHIFT 0x00000000 +#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7_MASK 0x00000001L +#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7__SHIFT 0x00000000 +#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7_MASK 0x00000002L +#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7__SHIFT 0x00000001 +#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7_MASK 0x00000004L +#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7__SHIFT 0x00000002 +#define PB1_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7_MASK 0x00000008L +#define PB1_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7__SHIFT 0x00000003 +#define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7_MASK 0x00000002L +#define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7__SHIFT 0x00000001 +#define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7_MASK 0x00000001L +#define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7__SHIFT 0x00000000 +#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7_MASK 0x00000008L +#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7__SHIFT 0x00000003 +#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7_MASK 0x00000004L +#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7__SHIFT 0x00000002 +#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7_MASK 0x00000020L +#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7__SHIFT 0x00000005 +#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7_MASK 0x00000010L +#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7__SHIFT 0x00000004 +#define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7_MASK 0x00000080L +#define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7__SHIFT 0x00000007 +#define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7_MASK 0x00000040L +#define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7__SHIFT 0x00000006 +#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7_MASK 0x0000fc00L +#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7__SHIFT 0x0000000a +#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7_MASK 0x00000300L +#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7__SHIFT 0x00000008 +#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7_MASK 0x00000080L +#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7__SHIFT 0x00000007 +#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__INCOHERENTCK_7_MASK 0x00000008L +#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__INCOHERENTCK_7__SHIFT 0x00000003 +#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7_MASK 0x00000070L +#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7__SHIFT 0x00000004 +#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7_MASK 0x00000007L +#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7__SHIFT 0x00000000 +#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8_MASK 0x00000001L +#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8__SHIFT 0x00000000 +#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8_MASK 0x00000002L +#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8__SHIFT 0x00000001 +#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8_MASK 0x00000004L +#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8__SHIFT 0x00000002 +#define PB1_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8_MASK 0x00000008L +#define PB1_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8__SHIFT 0x00000003 +#define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8_MASK 0x00000002L +#define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8__SHIFT 0x00000001 +#define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8_MASK 0x00000001L +#define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8__SHIFT 0x00000000 +#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8_MASK 0x00000008L +#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8__SHIFT 0x00000003 +#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8_MASK 0x00000004L +#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8__SHIFT 0x00000002 +#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8_MASK 0x00000020L +#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8__SHIFT 0x00000005 +#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8_MASK 0x00000010L +#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8__SHIFT 0x00000004 +#define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8_MASK 0x00000080L +#define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8__SHIFT 0x00000007 +#define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8_MASK 0x00000040L +#define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8__SHIFT 0x00000006 +#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8_MASK 0x0000fc00L +#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8__SHIFT 0x0000000a +#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8_MASK 0x00000300L +#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8__SHIFT 0x00000008 +#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8_MASK 0x00000080L +#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8__SHIFT 0x00000007 +#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__INCOHERENTCK_8_MASK 0x00000008L +#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__INCOHERENTCK_8__SHIFT 0x00000003 +#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8_MASK 0x00000070L +#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8__SHIFT 0x00000004 +#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8_MASK 0x00000007L +#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8__SHIFT 0x00000000 +#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9_MASK 0x00000001L +#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9__SHIFT 0x00000000 +#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9_MASK 0x00000002L +#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9__SHIFT 0x00000001 +#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9_MASK 0x00000004L +#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9__SHIFT 0x00000002 +#define PB1_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9_MASK 0x00000008L +#define PB1_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9__SHIFT 0x00000003 +#define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9_MASK 0x00000002L +#define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9__SHIFT 0x00000001 +#define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9_MASK 0x00000001L +#define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9__SHIFT 0x00000000 +#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9_MASK 0x00000008L +#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9__SHIFT 0x00000003 +#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9_MASK 0x00000004L +#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9__SHIFT 0x00000002 +#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9_MASK 0x00000020L +#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9__SHIFT 0x00000005 +#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9_MASK 0x00000010L +#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9__SHIFT 0x00000004 +#define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9_MASK 0x00000080L +#define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9__SHIFT 0x00000007 +#define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9_MASK 0x00000040L +#define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9__SHIFT 0x00000006 +#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9_MASK 0x0000fc00L +#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9__SHIFT 0x0000000a +#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9_MASK 0x00000300L +#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9__SHIFT 0x00000008 +#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9_MASK 0x00000080L +#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9__SHIFT 0x00000007 +#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__INCOHERENTCK_9_MASK 0x00000008L +#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__INCOHERENTCK_9__SHIFT 0x00000003 +#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9_MASK 0x00000070L +#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9__SHIFT 0x00000004 +#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9_MASK 0x00000007L +#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9__SHIFT 0x00000000 +#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L +#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x00000007 +#define PCIE_BUS_CNTL__PMI_INT_DIS_MASK 0x00000040L +#define PCIE_BUS_CNTL__PMI_INT_DIS__SHIFT 0x00000006 +#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000001L +#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x00000000 +#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L +#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x00000002 +#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000002L +#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x00000001 +#define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA_MASK 0x00000010L +#define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA__SHIFT 0x00000004 +#define PCIE_CI_CNTL__CI_MST_IGNORE_PAGE_ALIGNED_REQUEST_MASK 0x00002000L +#define PCIE_CI_CNTL__CI_MST_IGNORE_PAGE_ALIGNED_REQUEST__SHIFT 0x0000000d +#define PCIE_CI_CNTL__CI_RC_ORDERING_DIS_MASK 0x00000200L +#define PCIE_CI_CNTL__CI_RC_ORDERING_DIS__SHIFT 0x00000009 +#define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS_MASK 0x00000008L +#define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS__SHIFT 0x00000003 +#define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE_MASK 0x00000004L +#define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE__SHIFT 0x00000002 +#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS_MASK 0x00000400L +#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS__SHIFT 0x0000000a +#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE_MASK 0x00000800L +#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE__SHIFT 0x0000000b +#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR_MASK 0x00001000L +#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR__SHIFT 0x0000000c +#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS_MASK 0x00000100L +#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS__SHIFT 0x00000008 +#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE_MASK 0x000000c0L +#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE__SHIFT 0x00000006 +#define PCIE_CNTL2__MST_MEM_LS_EN_MASK 0x00040000L +#define PCIE_CNTL2__MST_MEM_LS_EN__SHIFT 0x00000012 +#define PCIE_CNTL2__MST_MEM_SD_EN_MASK 0x00400000L +#define PCIE_CNTL2__MST_MEM_SD_EN__SHIFT 0x00000016 +#define PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK 0x00080000L +#define PCIE_CNTL2__REPLAY_MEM_LS_EN__SHIFT 0x00000013 +#define PCIE_CNTL2__REPLAY_MEM_SD_EN_MASK 0x00800000L +#define PCIE_CNTL2__REPLAY_MEM_SD_EN__SHIFT 0x00000017 +#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING_MASK 0x1f000000L +#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING__SHIFT 0x00000018 +#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN_MASK 0x00020000L +#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN__SHIFT 0x00000011 +#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN_MASK 0x00200000L +#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN__SHIFT 0x00000015 +#define PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x00010000L +#define PCIE_CNTL2__SLV_MEM_LS_EN__SHIFT 0x00000010 +#define PCIE_CNTL2__SLV_MEM_SD_EN_MASK 0x00100000L +#define PCIE_CNTL2__SLV_MEM_SD_EN__SHIFT 0x00000014 +#define PCIE_CNTL2__TX_ARB_MST_LIMIT_MASK 0x000007c0L +#define PCIE_CNTL2__TX_ARB_MST_LIMIT__SHIFT 0x00000006 +#define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN_MASK 0x00000001L +#define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN__SHIFT 0x00000000 +#define PCIE_CNTL2__TX_ARB_SLV_LIMIT_MASK 0x0000003eL +#define PCIE_CNTL2__TX_ARB_SLV_LIMIT__SHIFT 0x00000001 +#define PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L +#define PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x00000000 +#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL_MASK 0x0000000eL +#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL__SHIFT 0x00000001 +#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE_MASK 0x00000200L +#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE__SHIFT 0x00000009 +#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L +#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x00000008 +#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS_MASK 0x00800000L +#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS__SHIFT 0x00000017 +#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN_MASK 0x80000000L +#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN__SHIFT 0x0000001f +#define PCIE_CNTL__RX_RCB_ATS_UC_DIS_MASK 0x00008000L +#define PCIE_CNTL__RX_RCB_ATS_UC_DIS__SHIFT 0x0000000f +#define PCIE_CNTL__RX_RCB_CHANNEL_ORDERING_MASK 0x00100000L +#define PCIE_CNTL__RX_RCB_CHANNEL_ORDERING__SHIFT 0x00000014 +#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE_MASK 0x00080000L +#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE__SHIFT 0x00000013 +#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS_MASK 0x00020000L +#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS__SHIFT 0x00000011 +#define PCIE_CNTL__RX_RCB_REORDER_EN_MASK 0x00010000L +#define PCIE_CNTL__RX_RCB_REORDER_EN__SHIFT 0x00000010 +#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS_MASK 0x00040000L +#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS__SHIFT 0x00000012 +#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS_MASK 0x00200000L +#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS__SHIFT 0x00000015 +#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS_MASK 0x00400000L +#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS__SHIFT 0x00000016 +#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE_MASK 0x00001c00L +#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE__SHIFT 0x0000000a +#define PCIE_CNTL__TX_CPL_DEBUG_MASK 0x3f000000L +#define PCIE_CNTL__TX_CPL_DEBUG__SHIFT 0x00000018 +#define PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L +#define PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x00000007 +#define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x02000000L +#define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x00000019 +#define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE_MASK 0x00010000L +#define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x00000010 +#define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE_MASK 0x00100000L +#define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x00000014 +#define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE_MASK 0x01000000L +#define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE__SHIFT 0x00000018 +#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE_MASK 0x000e0000L +#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x00000011 +#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK 0x00e00000L +#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x00000015 +#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK 0x0000000fL +#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT 0x00000000 +#define PCIE_DATA__PCIE_DATA_MASK 0xffffffffL +#define PCIE_DATA__PCIE_DATA__SHIFT 0x00000000 +#define PCIE_DEBUG_CNTL__DEBUG_LANE_EN_MASK 0xffff0000L +#define PCIE_DEBUG_CNTL__DEBUG_LANE_EN__SHIFT 0x00000010 +#define PCIE_DEBUG_CNTL__DEBUG_PORT_EN_MASK 0x000000ffL +#define PCIE_DEBUG_CNTL__DEBUG_PORT_EN__SHIFT 0x00000000 +#define PCIE_DEBUG_CNTL__DEBUG_SELECT_MASK 0x00000100L +#define PCIE_DEBUG_CNTL__DEBUG_SELECT__SHIFT 0x00000008 +#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L +#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x0000000b +#define PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x00001000L +#define PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x0000000c +#define PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x00002000L +#define PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x0000000d +#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x00000008 +#define PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x00008000L +#define PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0x0000000f +#define PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x00004000L +#define PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0x0000000e +#define PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x00010000L +#define PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x00000010 +#define PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x00000000 +#define PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x00000080L +#define PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x00000007 +#define PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x00000020L +#define PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x00000005 +#define PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x00000002L +#define PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x00000001 +#define PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x00000040L +#define PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x00000006 +#define PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x00000010L +#define PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x00000004 +#define PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0x0000000c +#define PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x00000008 +#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00ff0000L +#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x00000010 +#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xff000000L +#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x00000018 +#define PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x0000001fL +#define PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x00000000 +#define PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000ffL +#define PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x00000000 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0x000000ffL +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x00000000 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0x000000ffL +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x00000000 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0x000000ffL +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x00000000 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0x000000ffL +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x00000000 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0x000000ffL +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x00000000 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0x000000ffL +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x00000000 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0x000000ffL +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x00000000 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0x000000ffL +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x00000000 +#define PCIE_FC_CPL__CPLD_CREDITS_MASK 0x000000ffL +#define PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x00000000 +#define PCIE_FC_CPL__CPLH_CREDITS_MASK 0x0000ff00L +#define PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x00000008 +#define PCIE_FC_NP__NPD_CREDITS_MASK 0x000000ffL +#define PCIE_FC_NP__NPD_CREDITS__SHIFT 0x00000000 +#define PCIE_FC_NP__NPH_CREDITS_MASK 0x0000ff00L +#define PCIE_FC_NP__NPH_CREDITS__SHIFT 0x00000008 +#define PCIE_FC_P__PD_CREDITS_MASK 0x000000ffL +#define PCIE_FC_P__PD_CREDITS__SHIFT 0x00000000 +#define PCIE_FC_P__PH_CREDITS_MASK 0x0000ff00L +#define PCIE_FC_P__PH_CREDITS__SHIFT 0x00000008 +#define PCIE_HW_DEBUG__HW_00_DEBUG_MASK 0x00000001L +#define PCIE_HW_DEBUG__HW_00_DEBUG__SHIFT 0x00000000 +#define PCIE_HW_DEBUG__HW_01_DEBUG_MASK 0x00000002L +#define PCIE_HW_DEBUG__HW_01_DEBUG__SHIFT 0x00000001 +#define PCIE_HW_DEBUG__HW_02_DEBUG_MASK 0x00000004L +#define PCIE_HW_DEBUG__HW_02_DEBUG__SHIFT 0x00000002 +#define PCIE_HW_DEBUG__HW_03_DEBUG_MASK 0x00000008L +#define PCIE_HW_DEBUG__HW_03_DEBUG__SHIFT 0x00000003 +#define PCIE_HW_DEBUG__HW_04_DEBUG_MASK 0x00000010L +#define PCIE_HW_DEBUG__HW_04_DEBUG__SHIFT 0x00000004 +#define PCIE_HW_DEBUG__HW_05_DEBUG_MASK 0x00000020L +#define PCIE_HW_DEBUG__HW_05_DEBUG__SHIFT 0x00000005 +#define PCIE_HW_DEBUG__HW_06_DEBUG_MASK 0x00000040L +#define PCIE_HW_DEBUG__HW_06_DEBUG__SHIFT 0x00000006 +#define PCIE_HW_DEBUG__HW_07_DEBUG_MASK 0x00000080L +#define PCIE_HW_DEBUG__HW_07_DEBUG__SHIFT 0x00000007 +#define PCIE_HW_DEBUG__HW_08_DEBUG_MASK 0x00000100L +#define PCIE_HW_DEBUG__HW_08_DEBUG__SHIFT 0x00000008 +#define PCIE_HW_DEBUG__HW_09_DEBUG_MASK 0x00000200L +#define PCIE_HW_DEBUG__HW_09_DEBUG__SHIFT 0x00000009 +#define PCIE_HW_DEBUG__HW_10_DEBUG_MASK 0x00000400L +#define PCIE_HW_DEBUG__HW_10_DEBUG__SHIFT 0x0000000a +#define PCIE_HW_DEBUG__HW_11_DEBUG_MASK 0x00000800L +#define PCIE_HW_DEBUG__HW_11_DEBUG__SHIFT 0x0000000b +#define PCIE_HW_DEBUG__HW_12_DEBUG_MASK 0x00001000L +#define PCIE_HW_DEBUG__HW_12_DEBUG__SHIFT 0x0000000c +#define PCIE_HW_DEBUG__HW_13_DEBUG_MASK 0x00002000L +#define PCIE_HW_DEBUG__HW_13_DEBUG__SHIFT 0x0000000d +#define PCIE_HW_DEBUG__HW_14_DEBUG_MASK 0x00004000L +#define PCIE_HW_DEBUG__HW_14_DEBUG__SHIFT 0x0000000e +#define PCIE_HW_DEBUG__HW_15_DEBUG_MASK 0x00008000L +#define PCIE_HW_DEBUG__HW_15_DEBUG__SHIFT 0x0000000f +#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR_MASK 0x0001ffffL +#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR__SHIFT 0x00000000 +#define PCIE_I2C_REG_DATA__I2C_REG_DATA_MASK 0xffffffffL +#define PCIE_I2C_REG_DATA__I2C_REG_DATA__SHIFT 0x00000000 +#define PCIE_INDEX__PCIE_INDEX_MASK 0x000000ffL +#define PCIE_INDEX__PCIE_INDEX__SHIFT 0x00000000 +#define PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L +#define PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x00000000 +#define PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L +#define PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x00000002 +#define PCIE_INT_CNTL__LINK_BW_INT_EN_MASK 0x00000080L +#define PCIE_INT_CNTL__LINK_BW_INT_EN__SHIFT 0x00000007 +#define PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L +#define PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x00000004 +#define PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L +#define PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x00000001 +#define PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L +#define PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x00000006 +#define PCIE_INT_CNTL__QUIESCE_RCVD_INT_EN_MASK 0x00000100L +#define PCIE_INT_CNTL__QUIESCE_RCVD_INT_EN__SHIFT 0x00000008 +#define PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L +#define PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x00000003 +#define PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L +#define PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x00000000 +#define PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L +#define PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x00000002 +#define PCIE_INT_STATUS__LINK_BW_INT_STATUS_MASK 0x00000080L +#define PCIE_INT_STATUS__LINK_BW_INT_STATUS__SHIFT 0x00000007 +#define PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L +#define PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x00000004 +#define PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L +#define PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x00000001 +#define PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L +#define PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x00000006 +#define PCIE_INT_STATUS__QUIESCE_RCVD_INT_STATUS_MASK 0x00000100L +#define PCIE_INT_STATUS__QUIESCE_RCVD_INT_STATUS__SHIFT 0x00000008 +#define PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L +#define PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x00000003 +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0x0000fc00L +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0x0000000a +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000L +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x00000016 +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x003f0000L +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x00000010 +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x000003f0L +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x00000004 +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0x0000000fL +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x00000000 +#define PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x00000001L +#define PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x00000000 +#define PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x00000020L +#define PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x00000005 +#define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x00000002L +#define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x00000001 +#define PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x00000400L +#define PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0x0000000a +#define PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x00000040L +#define PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x00000006 +#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x00000200L +#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x00000009 +#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x00000100L +#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x00000008 +#define PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x00000008L +#define PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x00000003 +#define PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x00000010L +#define PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x00000004 +#define PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x00000080L +#define PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x00000007 +#define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x00000004L +#define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x00000002 +#define PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x03000000L +#define PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x00000018 +#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0x00000fffL +#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x00000000 +#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0x00fff000L +#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0x0000000c +#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x00020000L +#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x00000011 +#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x00040000L +#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x00000012 +#define PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x00400000L +#define PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x00000016 +#define PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x00100000L +#define PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x00000014 +#define PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x00080000L +#define PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x00000013 +#define PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x00010000L +#define PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x00000010 +#define PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x04000000L +#define PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x0000001a +#define PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0x0000c000L +#define PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0x0000000e +#define PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000L +#define PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x0000001f +#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x00000800L +#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x00001000L +#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0x0000000c +#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0x0000000b +#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L +#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x0000001b +#define PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x00000400L +#define PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0x0000000a +#define PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x00000080L +#define PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x00000007 +#define PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x00000100L +#define PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x00000008 +#define PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000L +#define PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x0000001c +#define PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x02000000L +#define PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x00000019 +#define PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x00200000L +#define PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x00000015 +#define PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x00000040L +#define PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x00000006 +#define PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000L +#define PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x0000001d +#define PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x0000003fL +#define PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x00000000 +#define PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x01800000L +#define PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x00000017 +#define PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x00002000L +#define PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0x0000000d +#define PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x00000200L +#define PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x00000009 +#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x00040000L +#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x00000012 +#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x00180000L +#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x00000013 +#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000100L +#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x00000008 +#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x000000c0L +#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x00000006 +#define PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x00010000L +#define PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x00000010 +#define PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x00000200L +#define PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x00000009 +#define PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x00000010L +#define PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x00000004 +#define PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x00800000L +#define PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x00000017 +#define PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x00003000L +#define PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0x0000000c +#define PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0x0000c000L +#define PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0x0000000e +#define PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x00000400L +#define PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x0000000a +#define PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x00200000L +#define PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x00000015 +#define PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000L +#define PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x0000001e +#define PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x03000000L +#define PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x00000018 +#define PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x00020000L +#define PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x00000011 +#define PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000L +#define PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x0000001f +#define PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x00000008L +#define PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x00000003 +#define PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x00000800L +#define PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0x0000000b +#define PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x00000020L +#define PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x00000005 +#define PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x00400000L +#define PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x00000016 +#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x00000006L +#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x00000001 +#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x00000001L +#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x00000000 +#define PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000L +#define PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x0000001a +#define PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x02000000L +#define PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x00000019 +#define PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x00000010L +#define PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x00010000L +#define PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x00000010 +#define PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x00000004 +#define PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x00000400L +#define PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0x0000000a +#define PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x00000300L +#define PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x00000008 +#define PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x01000000L +#define PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x00000018 +#define PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x00000040L +#define PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x00000006 +#define PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x00020000L +#define PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x00000011 +#define PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x003c0000L +#define PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x00000012 +#define PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x00000080L +#define PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x00000007 +#define PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x00800000L +#define PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x00000017 +#define PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x00004000L +#define PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0x0000000e +#define PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x00000020L +#define PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x00000005 +#define PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x00002000L +#define PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0x0000000d +#define PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x00000003L +#define PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x00000000 +#define PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x00008000L +#define PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0x0000000f +#define PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x00400000L +#define PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x00000016 +#define PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x00000800L +#define PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0x0000000b +#define PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x00001000L +#define PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0x0000000c +#define PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000L +#define PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x0000001a +#define PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x0000003fL +#define PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x00000000 +#define PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0x00000fc0L +#define PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x00000006 +#define PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x0003f000L +#define PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0x0000000c +#define PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0x00fc0000L +#define PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x00000012 +#define PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0x000000f0L +#define PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x00000004 +#define PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x01000000L +#define PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x00000018 +#define PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x06000000L +#define PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x00000019 +#define PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x08000000L +#define PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x0000001b +#define PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000L +#define PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x0000001c +#define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x00000002L +#define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x00000001 +#define PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000L +#define PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x0000001e +#define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000L +#define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x0000001d +#define PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x00100000L +#define PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x00000014 +#define PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000L +#define PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x0000001f +#define PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x00020000L +#define PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x00000011 +#define PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0x00000f00L +#define PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x00000008 +#define PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x00800000L +#define PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x00000017 +#define PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0x0000f000L +#define PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0x0000000c +#define PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0x000c0000L +#define PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x00000012 +#define PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x00010000L +#define PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x00000010 +#define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x00000004L +#define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x00000002 +#define PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x00000008L +#define PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x00000003 +#define PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x00200000L +#define PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x00000015 +#define PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x00400000L +#define PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x00000016 +#define PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x00080000L +#define PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x00000013 +#define PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x00000001L +#define PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x00000000 +#define PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x00001f80L +#define PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x00000007 +#define PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x0007e000L +#define PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0x0000000d +#define PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x0000007eL +#define PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x00000001 +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x00000001L +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x00000000 +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x00001f80L +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x00000007 +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x0007e000L +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0x0000000d +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x0000007eL +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x00000001 +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x01f80000L +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x00000013 +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000L +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x00000019 +#define PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0x0000ffffL +#define PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x00000000 +#define PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000L +#define PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x00000010 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x00010000L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x00000010 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x00080000L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x00000013 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x00600000L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x00000015 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x00040000L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x00000012 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x00800000L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x00000017 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x00020000L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x00000011 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x00000007L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x00000004 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x00000000 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x00000080L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x00000007 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x00000100L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x00000008 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x00000400L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0x0000000a +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x00000200L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x00000009 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x00000800L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0x0000000b +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x00008000L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0x0000000f +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x00004000L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0x0000000e +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x00100000L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x00000014 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x00002000L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0x0000000d +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x00001000L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0x0000000c +#define PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000L +#define PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x00000018 +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x00000200L +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x00000009 +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0x00ff0000L +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x00000010 +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0x000000ffL +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x00000100L +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x00000008 +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x00000000 +#define PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x00020000L +#define PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x00000011 +#define PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x00400000L +#define PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x00000016 +#define PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x04000000L +#define PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x0000001a +#define PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x00010000L +#define PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x00000010 +#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x00006000L +#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0x0000000d +#define PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x03000000L +#define PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x00000018 +#define PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000L +#define PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x0000001f +#define PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000L +#define PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x0000001e +#define PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x00008000L +#define PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0x0000000f +#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x00000100L +#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x00000008 +#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x00000040L +#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x00000006 +#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x00000080L +#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x00000007 +#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x00000020L +#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x00000005 +#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x00000000 +#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x00000001 +#define PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x00000200L +#define PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x00000009 +#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000L +#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x0000001c +#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000L +#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x0000001d +#define PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x08000000L +#define PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x0000001b +#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x00040000L +#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x00000012 +#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x00100000L +#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x00000014 +#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x00080000L +#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x00000013 +#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x00200000L +#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x00000015 +#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00001000L +#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x0000000c +#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x00000c00L +#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x0000000a +#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x00800000L +#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x00000017 +#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x00000004L +#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x00000002 +#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x00000018L +#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x00000003 +#define PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x0000003fL +#define PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x00000000 +#define PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x00003f00L +#define PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x00000008 +#define PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x003f0000L +#define PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x00000010 +#define PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000L +#define PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x00000018 +#define PCIE_LC_STATE10__LC_PREV_STATE40_MASK 0x0000003fL +#define PCIE_LC_STATE10__LC_PREV_STATE40__SHIFT 0x00000000 +#define PCIE_LC_STATE10__LC_PREV_STATE41_MASK 0x00003f00L +#define PCIE_LC_STATE10__LC_PREV_STATE41__SHIFT 0x00000008 +#define PCIE_LC_STATE10__LC_PREV_STATE42_MASK 0x003f0000L +#define PCIE_LC_STATE10__LC_PREV_STATE42__SHIFT 0x00000010 +#define PCIE_LC_STATE10__LC_PREV_STATE43_MASK 0x3f000000L +#define PCIE_LC_STATE10__LC_PREV_STATE43__SHIFT 0x00000018 +#define PCIE_LC_STATE11__LC_PREV_STATE44_MASK 0x0000003fL +#define PCIE_LC_STATE11__LC_PREV_STATE44__SHIFT 0x00000000 +#define PCIE_LC_STATE11__LC_PREV_STATE45_MASK 0x00003f00L +#define PCIE_LC_STATE11__LC_PREV_STATE45__SHIFT 0x00000008 +#define PCIE_LC_STATE11__LC_PREV_STATE46_MASK 0x003f0000L +#define PCIE_LC_STATE11__LC_PREV_STATE46__SHIFT 0x00000010 +#define PCIE_LC_STATE11__LC_PREV_STATE47_MASK 0x3f000000L +#define PCIE_LC_STATE11__LC_PREV_STATE47__SHIFT 0x00000018 +#define PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x0000003fL +#define PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x00000000 +#define PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x00003f00L +#define PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x00000008 +#define PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x003f0000L +#define PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x00000010 +#define PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000L +#define PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x00000018 +#define PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x003f0000L +#define PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x00000010 +#define PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000L +#define PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x00000018 +#define PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x0000003fL +#define PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x00000000 +#define PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x00003f00L +#define PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x00000008 +#define PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x0000003fL +#define PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x00000000 +#define PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x00003f00L +#define PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x00000008 +#define PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x003f0000L +#define PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x00000010 +#define PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000L +#define PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x00000018 +#define PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x0000003fL +#define PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x00000000 +#define PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x00003f00L +#define PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x00000008 +#define PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x003f0000L +#define PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x00000010 +#define PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000L +#define PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x00000018 +#define PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x0000003fL +#define PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x00000000 +#define PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x00003f00L +#define PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x00000008 +#define PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x003f0000L +#define PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x00000010 +#define PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000L +#define PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x00000018 +#define PCIE_LC_STATE6__LC_PREV_STATE24_MASK 0x0000003fL +#define PCIE_LC_STATE6__LC_PREV_STATE24__SHIFT 0x00000000 +#define PCIE_LC_STATE6__LC_PREV_STATE25_MASK 0x00003f00L +#define PCIE_LC_STATE6__LC_PREV_STATE25__SHIFT 0x00000008 +#define PCIE_LC_STATE6__LC_PREV_STATE26_MASK 0x003f0000L +#define PCIE_LC_STATE6__LC_PREV_STATE26__SHIFT 0x00000010 +#define PCIE_LC_STATE6__LC_PREV_STATE27_MASK 0x3f000000L +#define PCIE_LC_STATE6__LC_PREV_STATE27__SHIFT 0x00000018 +#define PCIE_LC_STATE7__LC_PREV_STATE28_MASK 0x0000003fL +#define PCIE_LC_STATE7__LC_PREV_STATE28__SHIFT 0x00000000 +#define PCIE_LC_STATE7__LC_PREV_STATE29_MASK 0x00003f00L +#define PCIE_LC_STATE7__LC_PREV_STATE29__SHIFT 0x00000008 +#define PCIE_LC_STATE7__LC_PREV_STATE30_MASK 0x003f0000L +#define PCIE_LC_STATE7__LC_PREV_STATE30__SHIFT 0x00000010 +#define PCIE_LC_STATE7__LC_PREV_STATE31_MASK 0x3f000000L +#define PCIE_LC_STATE7__LC_PREV_STATE31__SHIFT 0x00000018 +#define PCIE_LC_STATE8__LC_PREV_STATE32_MASK 0x0000003fL +#define PCIE_LC_STATE8__LC_PREV_STATE32__SHIFT 0x00000000 +#define PCIE_LC_STATE8__LC_PREV_STATE33_MASK 0x00003f00L +#define PCIE_LC_STATE8__LC_PREV_STATE33__SHIFT 0x00000008 +#define PCIE_LC_STATE8__LC_PREV_STATE34_MASK 0x003f0000L +#define PCIE_LC_STATE8__LC_PREV_STATE34__SHIFT 0x00000010 +#define PCIE_LC_STATE8__LC_PREV_STATE35_MASK 0x3f000000L +#define PCIE_LC_STATE8__LC_PREV_STATE35__SHIFT 0x00000018 +#define PCIE_LC_STATE9__LC_PREV_STATE36_MASK 0x0000003fL +#define PCIE_LC_STATE9__LC_PREV_STATE36__SHIFT 0x00000000 +#define PCIE_LC_STATE9__LC_PREV_STATE37_MASK 0x00003f00L +#define PCIE_LC_STATE9__LC_PREV_STATE37__SHIFT 0x00000008 +#define PCIE_LC_STATE9__LC_PREV_STATE38_MASK 0x003f0000L +#define PCIE_LC_STATE9__LC_PREV_STATE38__SHIFT 0x00000010 +#define PCIE_LC_STATE9__LC_PREV_STATE39_MASK 0x3f000000L +#define PCIE_LC_STATE9__LC_PREV_STATE39__SHIFT 0x00000018 +#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0x000000e0L +#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT 0x00000005 +#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK 0x0000001cL +#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT 0x00000002 +#define PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK 0x00000001L +#define PCIE_LC_STATUS1__LC_REVERSE_RCVR__SHIFT 0x00000000 +#define PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK 0x00000002L +#define PCIE_LC_STATUS1__LC_REVERSE_XMIT__SHIFT 0x00000001 +#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES_MASK 0x0000ffffL +#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES__SHIFT 0x00000000 +#define PCIE_LC_STATUS2__LC_TURN_ON_LANE_MASK 0xffff0000L +#define PCIE_LC_STATUS2__LC_TURN_ON_LANE__SHIFT 0x00000010 +#define PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000L +#define PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x0000001c +#define PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0x00c00000L +#define PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x00000016 +#define PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x00020000L +#define PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x00000011 +#define PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x00000010L +#define PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x00000004 +#define PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x00002000L +#define PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0x0000000d +#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x01000000L +#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x00000018 +#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x02000000L +#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x00000019 +#define PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x00000800L +#define PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0x0000000b +#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000L +#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x0000001e +#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x00010000L +#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x00000010 +#define PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x00080000L +#define PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x00000013 +#define PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x00001000L +#define PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0x0000000c +#define PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x00000040L +#define PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x00000006 +#define PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x00000080L +#define PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x00000007 +#define PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x00100000L +#define PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x00000014 +#define PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x00000020L +#define PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x00000005 +#define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x00000700L +#define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x00000008 +#define PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x04000000L +#define PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x0000001a +#define PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x08000000L +#define PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x0000001b +#define PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x00200000L +#define PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x00000015 +#define PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0x0000000fL +#define PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x00000000 +#define PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x00040000L +#define PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x00000012 +#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000L +#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x0000001d +#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR_MASK 0x0000ffffL +#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR__SHIFT 0x00000000 +#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR_MASK 0xffff0000L +#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR__SHIFT 0x00000010 +#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK_MASK 0x00002000L +#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK__SHIFT 0x0000000d +#define PCIE_P_CNTL__P_BLK_LOCK_MODE_MASK 0x00001000L +#define PCIE_P_CNTL__P_BLK_LOCK_MODE__SHIFT 0x0000000c +#define PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG_MASK 0x00000008L +#define PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG__SHIFT 0x00000003 +#define PCIE_P_CNTL__P_ELEC_IDLE_MODE_MASK 0x0000c000L +#define PCIE_P_CNTL__P_ELEC_IDLE_MODE__SHIFT 0x0000000e +#define PCIE_P_CNTL__P_IGNORE_CRC_ERR_MASK 0x00000010L +#define PCIE_P_CNTL__P_IGNORE_CRC_ERR__SHIFT 0x00000004 +#define PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK 0x00000040L +#define PCIE_P_CNTL__P_IGNORE_EDB_ERR__SHIFT 0x00000006 +#define PCIE_P_CNTL__P_IGNORE_IDL_ERR_MASK 0x00000080L +#define PCIE_P_CNTL__P_IGNORE_IDL_ERR__SHIFT 0x00000007 +#define PCIE_P_CNTL__P_IGNORE_LEN_ERR_MASK 0x00000020L +#define PCIE_P_CNTL__P_IGNORE_LEN_ERR__SHIFT 0x00000005 +#define PCIE_P_CNTL__P_IGNORE_TOK_ERR_MASK 0x00000100L +#define PCIE_P_CNTL__P_IGNORE_TOK_ERR__SHIFT 0x00000008 +#define PCIE_P_CNTL__P_PWRDN_EN_MASK 0x00000001L +#define PCIE_P_CNTL__P_PWRDN_EN__SHIFT 0x00000000 +#define PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG_MASK 0x00000004L +#define PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG__SHIFT 0x00000002 +#define PCIE_P_CNTL__P_SYMALIGN_MODE_MASK 0x00000002L +#define PCIE_P_CNTL__P_SYMALIGN_MODE__SHIFT 0x00000001 +#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_MASK 0x0000ffffL +#define PCIE_P_DECODER_STATUS__P_DECODE_ERR__SHIFT 0x00000000 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK_MASK 0x00000f00L +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK__SHIFT 0x00000008 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK_MASK 0x000000f0L +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK__SHIFT 0x00000004 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK_MASK 0x00f00000L +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x00000014 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK_MASK 0x0000f000L +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK__SHIFT 0x0000000c +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK_MASK 0x000f0000L +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK__SHIFT 0x00000010 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2_MASK 0x0f000000L +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2__SHIFT 0x00000018 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK_MASK 0x0000000fL +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK__SHIFT 0x00000000 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK_MASK 0x00000f00L +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK__SHIFT 0x00000008 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK_MASK 0x000000f0L +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK__SHIFT 0x00000004 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK_MASK 0x00f00000L +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x00000014 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK_MASK 0x0000f000L +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK__SHIFT 0x0000000c +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK_MASK 0x000f0000L +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK__SHIFT 0x00000010 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2_MASK 0x0f000000L +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2__SHIFT 0x00000018 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK_MASK 0x0000000fL +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK__SHIFT 0x00000000 +#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER_MASK 0x00ff0000L +#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER__SHIFT 0x00000010 +#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER_MASK 0xff000000L +#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER__SHIFT 0x00000018 +#define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL_MASK 0x000000ffL +#define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL__SHIFT 0x00000000 +#define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL_MASK 0x0000ff00L +#define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL__SHIFT 0x00000008 +#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER_MASK 0x00ff0000L +#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER__SHIFT 0x00000010 +#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER_MASK 0xff000000L +#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER__SHIFT 0x00000018 +#define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL_MASK 0x000000ffL +#define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL__SHIFT 0x00000000 +#define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL_MASK 0x0000ff00L +#define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL__SHIFT 0x00000008 +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER_MASK 0x00ff0000L +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER__SHIFT 0x00000010 +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER_MASK 0xff000000L +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER__SHIFT 0x00000018 +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL_MASK 0x000000ffL +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL__SHIFT 0x00000000 +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL_MASK 0x0000ff00L +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL__SHIFT 0x00000008 +#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER_MASK 0x00ff0000L +#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER__SHIFT 0x00000010 +#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER_MASK 0xff000000L +#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER__SHIFT 0x00000018 +#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL_MASK 0x000000ffL +#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL__SHIFT 0x00000000 +#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL_MASK 0x0000ff00L +#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL__SHIFT 0x00000008 +#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER_MASK 0x00ff0000L +#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER__SHIFT 0x00000010 +#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER_MASK 0xff000000L +#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER__SHIFT 0x00000018 +#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL_MASK 0x000000ffL +#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL__SHIFT 0x00000000 +#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL_MASK 0x0000ff00L +#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL__SHIFT 0x00000008 +#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER_MASK 0x00ff0000L +#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER__SHIFT 0x00000010 +#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER_MASK 0xff000000L +#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER__SHIFT 0x00000018 +#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL_MASK 0x000000ffL +#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL__SHIFT 0x00000000 +#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL_MASK 0x0000ff00L +#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL__SHIFT 0x00000008 +#define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER_MASK 0x00ff0000L +#define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER__SHIFT 0x00000010 +#define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER_MASK 0xff000000L +#define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER__SHIFT 0x00000018 +#define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL_MASK 0x000000ffL +#define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL__SHIFT 0x00000000 +#define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL_MASK 0x0000ff00L +#define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL__SHIFT 0x00000008 +#define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0_MASK 0xffffffffL +#define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0__SHIFT 0x00000000 +#define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0_MASK 0xffffffffL +#define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0__SHIFT 0x00000000 +#define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0_MASK 0xffffffffL +#define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0__SHIFT 0x00000000 +#define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0_MASK 0xffffffffL +#define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0__SHIFT 0x00000000 +#define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0_MASK 0xffffffffL +#define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0__SHIFT 0x00000000 +#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0_MASK 0xffffffffL +#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0__SHIFT 0x00000000 +#define PCIE_PERF_COUNT0_TXCLK__COUNTER0_MASK 0xffffffffL +#define PCIE_PERF_COUNT0_TXCLK__COUNTER0__SHIFT 0x00000000 +#define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1_MASK 0xffffffffL +#define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1__SHIFT 0x00000000 +#define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1_MASK 0xffffffffL +#define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1__SHIFT 0x00000000 +#define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1_MASK 0xffffffffL +#define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1__SHIFT 0x00000000 +#define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1_MASK 0xffffffffL +#define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1__SHIFT 0x00000000 +#define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1_MASK 0xffffffffL +#define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1__SHIFT 0x00000000 +#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK 0xffffffffL +#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT 0x00000000 +#define PCIE_PERF_COUNT1_TXCLK__COUNTER1_MASK 0xffffffffL +#define PCIE_PERF_COUNT1_TXCLK__COUNTER1__SHIFT 0x00000000 +#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN_MASK 0x00000001L +#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN__SHIFT 0x00000000 +#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET_MASK 0x00000004L +#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT 0x00000002 +#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK 0x00000002L +#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR__SHIFT 0x00000001 +#define PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x00000001L +#define PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x00000000 +#define PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x00000002L +#define PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x00000001 +#define PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x00000004L +#define PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x00000002 +#define PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x00000008L +#define PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x00000003 +#define PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x00000010L +#define PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x00000004 +#define PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x00000020L +#define PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x00000005 +#define PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x00000040L +#define PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x00000006 +#define PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x00000080L +#define PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x00000007 +#define PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x00000100L +#define PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x00000008 +#define PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x00000200L +#define PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x00000009 +#define PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x00000400L +#define PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0x0000000a +#define PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x00000800L +#define PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0x0000000b +#define PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x00001000L +#define PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0x0000000c +#define PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x00002000L +#define PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0x0000000d +#define PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x00004000L +#define PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0x0000000e +#define PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x00008000L +#define PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0x0000000f +#define PCIE_P_MISC_STATUS__P_DESKEW_ERR_MASK 0x000000ffL +#define PCIE_P_MISC_STATUS__P_DESKEW_ERR__SHIFT 0x00000000 +#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR_MASK 0xffff0000L +#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR__SHIFT 0x00000010 +#define PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffffL +#define PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x00000000 +#define PCIE_PORT_INDEX__PCIE_INDEX_MASK 0x000000ffL +#define PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x00000000 +#define PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x00007f00L +#define PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x00000008 +#define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x00000002L +#define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x00000001 +#define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x00000004L +#define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x00000002 +#define PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x00000008L +#define PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x00000003 +#define PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x00000020L +#define PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x00000005 +#define PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x00000010L +#define PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x00000004 +#define PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x00000040L +#define PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x00000006 +#define PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x00000001L +#define PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x00000000 +#define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x0000007eL +#define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x00000001 +#define PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x00000001L +#define PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x00000000 +#define PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT_MASK 0x000f0000L +#define PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT__SHIFT 0x00000010 +#define PCIE_PRBS_CLR__PRBS_CLR_MASK 0x0000ffffL +#define PCIE_PRBS_CLR__PRBS_CLR__SHIFT 0x00000000 +#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0_MASK 0xffffffffL +#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0__SHIFT 0x00000000 +#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10_MASK 0xffffffffL +#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10__SHIFT 0x00000000 +#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11_MASK 0xffffffffL +#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11__SHIFT 0x00000000 +#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12_MASK 0xffffffffL +#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12__SHIFT 0x00000000 +#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13_MASK 0xffffffffL +#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13__SHIFT 0x00000000 +#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14_MASK 0xffffffffL +#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14__SHIFT 0x00000000 +#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15_MASK 0xffffffffL +#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15__SHIFT 0x00000000 +#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1_MASK 0xffffffffL +#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1__SHIFT 0x00000000 +#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2_MASK 0xffffffffL +#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2__SHIFT 0x00000000 +#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3_MASK 0xffffffffL +#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3__SHIFT 0x00000000 +#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4_MASK 0xffffffffL +#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4__SHIFT 0x00000000 +#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5_MASK 0xffffffffL +#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5__SHIFT 0x00000000 +#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6_MASK 0xffffffffL +#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6__SHIFT 0x00000000 +#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7_MASK 0xffffffffL +#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7__SHIFT 0x00000000 +#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8_MASK 0xffffffffL +#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8__SHIFT 0x00000000 +#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9_MASK 0xffffffffL +#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9__SHIFT 0x00000000 +#define PCIE_PRBS_FREERUN__PRBS_FREERUN_MASK 0x0000ffffL +#define PCIE_PRBS_FREERUN__PRBS_FREERUN__SHIFT 0x00000000 +#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT_MASK 0x000000ffL +#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT__SHIFT 0x00000000 +#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT_MASK 0xffffffffL +#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT__SHIFT 0x00000000 +#define PCIE_PRBS_MISC__PRBS_8BIT_SEL_MASK 0x00000010L +#define PCIE_PRBS_MISC__PRBS_8BIT_SEL__SHIFT 0x00000004 +#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK_MASK 0xffff0000L +#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK__SHIFT 0x00000010 +#define PCIE_PRBS_MISC__PRBS_COMMA_NUM_MASK 0x00000060L +#define PCIE_PRBS_MISC__PRBS_COMMA_NUM__SHIFT 0x00000005 +#define PCIE_PRBS_MISC__PRBS_DATA_RATE_MASK 0x0000c000L +#define PCIE_PRBS_MISC__PRBS_DATA_RATE__SHIFT 0x0000000e +#define PCIE_PRBS_MISC__PRBS_EN_MASK 0x00000001L +#define PCIE_PRBS_MISC__PRBS_EN__SHIFT 0x00000000 +#define PCIE_PRBS_MISC__PRBS_LOCK_CNT_MASK 0x00000f80L +#define PCIE_PRBS_MISC__PRBS_LOCK_CNT__SHIFT 0x00000007 +#define PCIE_PRBS_MISC__PRBS_TEST_MODE_MASK 0x00000006L +#define PCIE_PRBS_MISC__PRBS_TEST_MODE__SHIFT 0x00000001 +#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE_MASK 0x00000008L +#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE__SHIFT 0x00000003 +#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT_MASK 0x0000ffffL +#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT__SHIFT 0x00000000 +#define PCIE_PRBS_STATUS1__PRBS_LOCKED_MASK 0xffff0000L +#define PCIE_PRBS_STATUS1__PRBS_LOCKED__SHIFT 0x00000010 +#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE_MASK 0x0000ffffL +#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE__SHIFT 0x00000000 +#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN_MASK 0x3fffffffL +#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN__SHIFT 0x00000000 +#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX_MASK 0x0000ff00L +#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX__SHIFT 0x00000008 +#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN_MASK 0x000000ffL +#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN__SHIFT 0x00000000 +#define PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffffL +#define PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x00000000 +#define PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffffL +#define PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x00000000 +#define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x00008000L +#define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x0000000f +#define PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x00000800L +#define PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0x0000000b +#define PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x00001000L +#define PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0x0000000c +#define PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x00002000L +#define PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0x0000000d +#define PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x00000003L +#define PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x00000000 +#define PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x00070000L +#define PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x00000010 +#define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0x0000000cL +#define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x00000002 +#define PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x00000030L +#define PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x00000004 +#define PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x00004000L +#define PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0x0000000e +#define PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0x000000c0L +#define PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x00000006 +#define PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x00000700L +#define PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x00000008 +#define PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x00000002L +#define PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x00000001 +#define PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x00000004L +#define PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x00000002 +#define PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x00000018L +#define PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x00000003 +#define PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x00000001L +#define PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x00000000 +#define PCIE_RESERVED__PCIE_RESERVED_MASK 0xffffffffL +#define PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x00000000 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR_MASK 0x00000008L +#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR__SHIFT 0x00000003 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L +#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x00000000 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR_MASK 0x00000020L +#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR__SHIFT 0x00000005 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR_MASK 0x00000010L +#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR__SHIFT 0x00000004 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK 0x00000002L +#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR__SHIFT 0x00000001 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR_MASK 0x00000004L +#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT 0x00000002 +#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x00000010L +#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x00000004 +#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x00000008L +#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x00000003 +#define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x00000004L +#define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x00000002 +#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x00000001L +#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x00000000 +#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x00000002L +#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x00000001 +#define PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x00008000L +#define PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0x0000000f +#define PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x00004000L +#define PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0x0000000e +#define PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x00001000L +#define PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0x0000000c +#define PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x00000002L +#define PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x00000001 +#define PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x00000010L +#define PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x00000004 +#define PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x00000400L +#define PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0x0000000a +#define PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x00000020L +#define PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x00000005 +#define PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x00800000L +#define PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x00000017 +#define PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x00000008L +#define PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x00000003 +#define PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x00000040L +#define PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x00000006 +#define PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L +#define PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x00000018 +#define PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x00000001L +#define PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x00000000 +#define PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x00000800L +#define PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0x0000000b +#define PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x00000080L +#define PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x00000007 +#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x00000008 +#define PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L +#define PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x00000016 +#define PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x00000004L +#define PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x00000002 +#define PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L +#define PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x00000019 +#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L +#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x00000015 +#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L +#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x00000009 +#define PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x00002000L +#define PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0x0000000d +#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x00000014 +#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x00070000L +#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x00080000L +#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x00000013 +#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x00000010 +#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0x00000fffL +#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x00000000 +#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0x00ff0000L +#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x00000010 +#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0x00000fffL +#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x00000000 +#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0x00ff0000L +#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x00000010 +#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0x00000fffL +#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x00000000 +#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0x00ff0000L +#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x00000010 +#define PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0x00000fffL +#define PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x00000000 +#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0_MASK 0xffffffffL +#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0__SHIFT 0x00000000 +#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1_MASK 0xffffffffL +#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1__SHIFT 0x00000000 +#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2_MASK 0xffffffffL +#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2__SHIFT 0x00000000 +#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3_MASK 0xffffffffL +#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3__SHIFT 0x00000000 +#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED_MASK 0xffffffffL +#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED__SHIFT 0x00000000 +#define PCIE_RX_NUM_NAK__RX_NUM_NAK_MASK 0xffffffffL +#define PCIE_RX_NUM_NAK__RX_NUM_NAK__SHIFT 0x00000000 +#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0x00ffffffL +#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x00000000 +#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x01000000L +#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x00000018 +#define PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xffffffffL +#define PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x00000000 +#define PCIE_STRAP_F0__STRAP_F0_ACS_EN_MASK 0x00000040L +#define PCIE_STRAP_F0__STRAP_F0_ACS_EN__SHIFT 0x00000006 +#define PCIE_STRAP_F0__STRAP_F0_AER_EN_MASK 0x00000020L +#define PCIE_STRAP_F0__STRAP_F0_AER_EN__SHIFT 0x00000005 +#define PCIE_STRAP_F0__STRAP_F0_ATS_EN_MASK 0x00000400L +#define PCIE_STRAP_F0__STRAP_F0_ATS_EN__SHIFT 0x0000000a +#define PCIE_STRAP_F0__STRAP_F0_BAR_EN_MASK 0x00000080L +#define PCIE_STRAP_F0__STRAP_F0_BAR_EN__SHIFT 0x00000007 +#define PCIE_STRAP_F0__STRAP_F0_DPA_EN_MASK 0x00000200L +#define PCIE_STRAP_F0__STRAP_F0_DPA_EN__SHIFT 0x00000009 +#define PCIE_STRAP_F0__STRAP_F0_DSN_EN_MASK 0x00000010L +#define PCIE_STRAP_F0__STRAP_F0_DSN_EN__SHIFT 0x00000004 +#define PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x00000001L +#define PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x00000000 +#define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN_MASK 0x00000002L +#define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN__SHIFT 0x00000001 +#define PCIE_STRAP_F0__STRAP_F0_MSI_EN_MASK 0x00000004L +#define PCIE_STRAP_F0__STRAP_F0_MSI_EN__SHIFT 0x00000002 +#define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN_MASK 0x00000800L +#define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN__SHIFT 0x0000000b +#define PCIE_STRAP_F0__STRAP_F0_PASID_EN_MASK 0x00001000L +#define PCIE_STRAP_F0__STRAP_F0_PASID_EN__SHIFT 0x0000000c +#define PCIE_STRAP_F0__STRAP_F0_PWR_EN_MASK 0x00000100L +#define PCIE_STRAP_F0__STRAP_F0_PWR_EN__SHIFT 0x00000008 +#define PCIE_STRAP_F0__STRAP_F0_VC_EN_MASK 0x00000008L +#define PCIE_STRAP_F0__STRAP_F0_VC_EN__SHIFT 0x00000003 +#define PCIE_STRAP_F1__STRAP_F1_ACS_EN_MASK 0x00000040L +#define PCIE_STRAP_F1__STRAP_F1_ACS_EN__SHIFT 0x00000006 +#define PCIE_STRAP_F1__STRAP_F1_AER_EN_MASK 0x00000020L +#define PCIE_STRAP_F1__STRAP_F1_AER_EN__SHIFT 0x00000005 +#define PCIE_STRAP_F1__STRAP_F1_ATS_EN_MASK 0x00000400L +#define PCIE_STRAP_F1__STRAP_F1_ATS_EN__SHIFT 0x0000000a +#define PCIE_STRAP_F1__STRAP_F1_BAR_EN_MASK 0x00000080L +#define PCIE_STRAP_F1__STRAP_F1_BAR_EN__SHIFT 0x00000007 +#define PCIE_STRAP_F1__STRAP_F1_DPA_EN_MASK 0x00000200L +#define PCIE_STRAP_F1__STRAP_F1_DPA_EN__SHIFT 0x00000009 +#define PCIE_STRAP_F1__STRAP_F1_DSN_EN_MASK 0x00000010L +#define PCIE_STRAP_F1__STRAP_F1_DSN_EN__SHIFT 0x00000004 +#define PCIE_STRAP_F1__STRAP_F1_EN_MASK 0x00000001L +#define PCIE_STRAP_F1__STRAP_F1_EN__SHIFT 0x00000000 +#define PCIE_STRAP_F1__STRAP_F1_LEGACY_DEVICE_TYPE_EN_MASK 0x00000002L +#define PCIE_STRAP_F1__STRAP_F1_LEGACY_DEVICE_TYPE_EN__SHIFT 0x00000001 +#define PCIE_STRAP_F1__STRAP_F1_MSI_EN_MASK 0x00000004L +#define PCIE_STRAP_F1__STRAP_F1_MSI_EN__SHIFT 0x00000002 +#define PCIE_STRAP_F1__STRAP_F1_PAGE_REQ_EN_MASK 0x00000800L +#define PCIE_STRAP_F1__STRAP_F1_PAGE_REQ_EN__SHIFT 0x0000000b +#define PCIE_STRAP_F1__STRAP_F1_PASID_EN_MASK 0x00001000L +#define PCIE_STRAP_F1__STRAP_F1_PASID_EN__SHIFT 0x0000000c +#define PCIE_STRAP_F1__STRAP_F1_PWR_EN_MASK 0x00000100L +#define PCIE_STRAP_F1__STRAP_F1_PWR_EN__SHIFT 0x00000008 +#define PCIE_STRAP_F1__STRAP_F1_VC_EN_MASK 0x00000008L +#define PCIE_STRAP_F1__STRAP_F1_VC_EN__SHIFT 0x00000003 +#define PCIE_STRAP_F2__STRAP_F2_ACS_EN_MASK 0x00000040L +#define PCIE_STRAP_F2__STRAP_F2_ACS_EN__SHIFT 0x00000006 +#define PCIE_STRAP_F2__STRAP_F2_AER_EN_MASK 0x00000020L +#define PCIE_STRAP_F2__STRAP_F2_AER_EN__SHIFT 0x00000005 +#define PCIE_STRAP_F2__STRAP_F2_ATS_EN_MASK 0x00000400L +#define PCIE_STRAP_F2__STRAP_F2_ATS_EN__SHIFT 0x0000000a +#define PCIE_STRAP_F2__STRAP_F2_BAR_EN_MASK 0x00000080L +#define PCIE_STRAP_F2__STRAP_F2_BAR_EN__SHIFT 0x00000007 +#define PCIE_STRAP_F2__STRAP_F2_DPA_EN_MASK 0x00000200L +#define PCIE_STRAP_F2__STRAP_F2_DPA_EN__SHIFT 0x00000009 +#define PCIE_STRAP_F2__STRAP_F2_DSN_EN_MASK 0x00000010L +#define PCIE_STRAP_F2__STRAP_F2_DSN_EN__SHIFT 0x00000004 +#define PCIE_STRAP_F2__STRAP_F2_EN_MASK 0x00000001L +#define PCIE_STRAP_F2__STRAP_F2_EN__SHIFT 0x00000000 +#define PCIE_STRAP_F2__STRAP_F2_LEGACY_DEVICE_TYPE_EN_MASK 0x00000002L +#define PCIE_STRAP_F2__STRAP_F2_LEGACY_DEVICE_TYPE_EN__SHIFT 0x00000001 +#define PCIE_STRAP_F2__STRAP_F2_MSI_EN_MASK 0x00000004L +#define PCIE_STRAP_F2__STRAP_F2_MSI_EN__SHIFT 0x00000002 +#define PCIE_STRAP_F2__STRAP_F2_PAGE_REQ_EN_MASK 0x00000800L +#define PCIE_STRAP_F2__STRAP_F2_PAGE_REQ_EN__SHIFT 0x0000000b +#define PCIE_STRAP_F2__STRAP_F2_PASID_EN_MASK 0x00001000L +#define PCIE_STRAP_F2__STRAP_F2_PASID_EN__SHIFT 0x0000000c +#define PCIE_STRAP_F2__STRAP_F2_PWR_EN_MASK 0x00000100L +#define PCIE_STRAP_F2__STRAP_F2_PWR_EN__SHIFT 0x00000008 +#define PCIE_STRAP_F2__STRAP_F2_VC_EN_MASK 0x00000008L +#define PCIE_STRAP_F2__STRAP_F2_VC_EN__SHIFT 0x00000003 +#define PCIE_STRAP_F3__RESERVED_MASK 0xffffffffL +#define PCIE_STRAP_F3__RESERVED__SHIFT 0x00000000 +#define PCIE_STRAP_F4__RESERVED_MASK 0xffffffffL +#define PCIE_STRAP_F4__RESERVED__SHIFT 0x00000000 +#define PCIE_STRAP_F5__RESERVED_MASK 0xffffffffL +#define PCIE_STRAP_F5__RESERVED__SHIFT 0x00000000 +#define PCIE_STRAP_F6__RESERVED_MASK 0xffffffffL +#define PCIE_STRAP_F6__RESERVED__SHIFT 0x00000000 +#define PCIE_STRAP_F7__RESERVED_MASK 0xffffffffL +#define PCIE_STRAP_F7__RESERVED__SHIFT 0x00000000 +#define PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN_MASK 0x00000080L +#define PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN__SHIFT 0x00000007 +#define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR_MASK 0x0000007fL +#define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR__SHIFT 0x00000000 +#define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE_MASK 0x00000002L +#define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE__SHIFT 0x00000001 +#define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE_MASK 0x00000008L +#define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE__SHIFT 0x00000003 +#define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x00000004L +#define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x00000002 +#define PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x01000000L +#define PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x00000018 +#define PCIE_STRAP_MISC__STRAP_ECN1P1_EN_MASK 0x02000000L +#define PCIE_STRAP_MISC__STRAP_ECN1P1_EN__SHIFT 0x00000019 +#define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT_MASK 0x04000000L +#define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT__SHIFT 0x0000001a +#define PCIE_STRAP_MISC__STRAP_FLR_EN_MASK 0x40000000L +#define PCIE_STRAP_MISC__STRAP_FLR_EN__SHIFT 0x0000001e +#define PCIE_STRAP_MISC__STRAP_LINK_CONFIG_MASK 0x0000000fL +#define PCIE_STRAP_MISC__STRAP_LINK_CONFIG__SHIFT 0x00000000 +#define PCIE_STRAP_MISC__STRAP_MAX_PASID_WIDTH_MASK 0x00001f00L +#define PCIE_STRAP_MISC__STRAP_MAX_PASID_WIDTH__SHIFT 0x00000008 +#define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L +#define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x0000001d +#define PCIE_STRAP_MISC__STRAP_PASID_EXE_PERMISSION_SUPPORTED_MASK 0x00002000L +#define PCIE_STRAP_MISC__STRAP_PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x0000000d +#define PCIE_STRAP_MISC__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_MASK 0x00008000L +#define PCIE_STRAP_MISC__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x0000000f +#define PCIE_STRAP_MISC__STRAP_PASID_PRIV_MODE_SUPPORTED_MASK 0x00004000L +#define PCIE_STRAP_MISC__STRAP_PASID_PRIV_MODE_SUPPORTED__SHIFT 0x0000000e +#define PCIE_STRAP_MISC__STRAP_REVERSE_ALL_MASK 0x10000000L +#define PCIE_STRAP_MISC__STRAP_REVERSE_ALL__SHIFT 0x0000001c +#define PCIE_STRAP_PI__STRAP_QUICKSIM_START_MASK 0x00000001L +#define PCIE_STRAP_PI__STRAP_QUICKSIM_START__SHIFT 0x00000000 +#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE_MASK 0x20000000L +#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE__SHIFT 0x0000001d +#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN_MASK 0x10000000L +#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN__SHIFT 0x0000001c +#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0x00000fffL +#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x00001000L +#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0x0000000c +#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x00000000 +#define PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x00400000L +#define PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x00000016 +#define PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x00100000L +#define PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x00000014 +#define PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x00800000L +#define PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x00000017 +#define PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x00008000L +#define PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0x0000000f +#define PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x00200000L +#define PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x00000015 +#define PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x00004000L +#define PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0x0000000e +#define PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L +#define PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0x0000000c +#define PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000c00L +#define PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0x0000000a +#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0x00000fffL +#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x00000000 +#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0x00ff0000L +#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x00000010 +#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0x00000fffL +#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x00000000 +#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0x00ff0000L +#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x00000010 +#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0x00000fffL +#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x00000000 +#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0x00ff0000L +#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x00000010 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x00000700L +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x00000008 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x07000000L +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x00000018 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x00000070L +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x00000004 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x00700000L +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x00000014 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x00000007L +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x00000000 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x00070000L +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x00000010 +#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0x00000fffL +#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x00000000 +#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0x00ff0000L +#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x00000010 +#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0x00000fffL +#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x00000000 +#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0x00ff0000L +#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x00000010 +#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0x00000fffL +#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x00000000 +#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0x00ff0000L +#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x00000010 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x00100000L +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x00000014 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x00200000L +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x00000015 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x00040000L +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x00000012 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x00080000L +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x00000013 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x00010000L +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x00000010 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x00020000L +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x00000011 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x00000010L +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x00000004 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x00000020L +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x00000005 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x00000004L +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x00000002 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x00000008L +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x00000003 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x00000001L +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x00000000 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x00000002L +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x00000001 +#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0_MASK 0xffffffffL +#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0__SHIFT 0x00000000 +#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1_MASK 0xffffffffL +#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1__SHIFT 0x00000000 +#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2_MASK 0xffffffffL +#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2__SHIFT 0x00000000 +#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3_MASK 0xffffffffL +#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3__SHIFT 0x00000000 +#define PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x00000007L +#define PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x00000000 +#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000L +#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x00008000L +#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0x0000000f +#define PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x00000010 +#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000ff00L +#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x00000008 +#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000f8L +#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x00000003 +#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L +#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x00000000 +#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000L +#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x0000001f +#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000L +#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x00000018 +#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000L +#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x0000001e +#define PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0x0fff0000L +#define PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x00000010 +#define PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0x00000fffL +#define PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x00000000 +#define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0x00ffffffL +#define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x00000000 +#define PCIE_WPR_CNTL__WPR_RESET_COR_EN_MASK 0x00000008L +#define PCIE_WPR_CNTL__WPR_RESET_COR_EN__SHIFT 0x00000003 +#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN_MASK 0x00000001L +#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN__SHIFT 0x00000000 +#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN_MASK 0x00000004L +#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT 0x00000002 +#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK 0x00000002L +#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN__SHIFT 0x00000001 +#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN_MASK 0x00000040L +#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN__SHIFT 0x00000006 +#define PCIE_WPR_CNTL__WPR_RESET_REG_EN_MASK 0x00000010L +#define PCIE_WPR_CNTL__WPR_RESET_REG_EN__SHIFT 0x00000004 +#define PCIE_WPR_CNTL__WPR_RESET_STY_EN_MASK 0x00000020L +#define PCIE_WPR_CNTL__WPR_RESET_STY_EN__SHIFT 0x00000005 +#define PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK 0x000fffffL +#define PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x00000000 +#define PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK 0x80000000L +#define PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x0000001f +#define PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK 0x000fffffL +#define PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x00000000 +#define PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK 0x000fffffL +#define PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x00000000 +#define PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK 0x80000000L +#define PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x0000001f +#define PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK 0x000fffffL +#define PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x00000000 +#define PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK 0x000fffffL +#define PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x00000000 +#define PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK 0x80000000L +#define PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x0000001f +#define PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK 0x000fffffL +#define PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x00000000 +#define PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK 0x000fffffL +#define PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x00000000 +#define PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK 0x80000000L +#define PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x0000001f +#define PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK 0x000fffffL +#define PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x00000000 +#define PEER_REG_RANGE0__END_ADDR_MASK 0xffff0000L +#define PEER_REG_RANGE0__END_ADDR__SHIFT 0x00000010 +#define PEER_REG_RANGE0__START_ADDR_MASK 0x0000ffffL +#define PEER_REG_RANGE0__START_ADDR__SHIFT 0x00000000 +#define PEER_REG_RANGE1__END_ADDR_MASK 0xffff0000L +#define PEER_REG_RANGE1__END_ADDR__SHIFT 0x00000010 +#define PEER_REG_RANGE1__START_ADDR_MASK 0x0000ffffL +#define PEER_REG_RANGE1__START_ADDR__SHIFT 0x00000000 +#define SLAVE_HANG_ERROR__AUDIO_HANG_ERROR_MASK 0x00000010L +#define SLAVE_HANG_ERROR__AUDIO_HANG_ERROR__SHIFT 0x00000004 +#define SLAVE_HANG_ERROR__CEC_HANG_ERROR_MASK 0x00000020L +#define SLAVE_HANG_ERROR__CEC_HANG_ERROR__SHIFT 0x00000005 +#define SLAVE_HANG_ERROR__HDP_HANG_ERROR_MASK 0x00000002L +#define SLAVE_HANG_ERROR__HDP_HANG_ERROR__SHIFT 0x00000001 +#define SLAVE_HANG_ERROR__ROM_HANG_ERROR_MASK 0x00000008L +#define SLAVE_HANG_ERROR__ROM_HANG_ERROR__SHIFT 0x00000003 +#define SLAVE_HANG_ERROR__SRBM_HANG_ERROR_MASK 0x00000001L +#define SLAVE_HANG_ERROR__SRBM_HANG_ERROR__SHIFT 0x00000000 +#define SLAVE_HANG_ERROR__VGA_HANG_ERROR_MASK 0x00000004L +#define SLAVE_HANG_ERROR__VGA_HANG_ERROR__SHIFT 0x00000002 +#define SLAVE_HANG_PROTECTION_CNTL__HANG_PROTECTION_TIMER_SEL_MASK 0x0000000eL +#define SLAVE_HANG_PROTECTION_CNTL__HANG_PROTECTION_TIMER_SEL__SHIFT 0x00000001 +#define SLAVE_REQ_CREDIT_CNTL__BIF_AZ_REQ_CREDIT_MASK 0x00100000L +#define SLAVE_REQ_CREDIT_CNTL__BIF_AZ_REQ_CREDIT__SHIFT 0x00000014 +#define SLAVE_REQ_CREDIT_CNTL__BIF_HDP_REQ_CREDIT_MASK 0x00007c00L +#define SLAVE_REQ_CREDIT_CNTL__BIF_HDP_REQ_CREDIT__SHIFT 0x0000000a +#define SLAVE_REQ_CREDIT_CNTL__BIF_ROM_REQ_CREDIT_MASK 0x00008000L +#define SLAVE_REQ_CREDIT_CNTL__BIF_ROM_REQ_CREDIT__SHIFT 0x0000000f +#define SLAVE_REQ_CREDIT_CNTL__BIF_SRBM_REQ_CREDIT_MASK 0x0000001fL +#define SLAVE_REQ_CREDIT_CNTL__BIF_SRBM_REQ_CREDIT__SHIFT 0x00000000 +#define SLAVE_REQ_CREDIT_CNTL__BIF_VGA_REQ_CREDIT_MASK 0x000001e0L +#define SLAVE_REQ_CREDIT_CNTL__BIF_VGA_REQ_CREDIT__SHIFT 0x00000005 +#define SLAVE_REQ_CREDIT_CNTL__BIF_XDMA_REQ_CREDIT_MASK 0x7e000000L +#define SLAVE_REQ_CREDIT_CNTL__BIF_XDMA_REQ_CREDIT__SHIFT 0x00000019 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_A_MASK 0x00000001L +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_A__SHIFT 0x00000000 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_CNTL_EN_MASK 0x00001000L +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_CNTL_EN__SHIFT 0x0000000c +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_MODE_MASK 0x00000004L +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_MODE__SHIFT 0x00000002 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SCHMEN_MASK 0x00000800L +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SCHMEN__SHIFT 0x0000000b +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SEL_MASK 0x00000002L +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SEL__SHIFT 0x00000001 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SLEWN_MASK 0x00000200L +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SLEWN__SHIFT 0x00000009 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN0_MASK 0x00000020L +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN0__SHIFT 0x00000005 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN1_MASK 0x00000040L +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN1__SHIFT 0x00000006 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN2_MASK 0x00000080L +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN2__SHIFT 0x00000007 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN3_MASK 0x00000100L +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN3__SHIFT 0x00000008 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SPARE_MASK 0x00000018L +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SPARE__SHIFT 0x00000003 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_WAKE_MASK 0x00000400L +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_WAKE__SHIFT 0x0000000a +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_A_MASK 0x00000001L +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_A__SHIFT 0x00000000 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_CNTL_EN_MASK 0x00001000L +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_CNTL_EN__SHIFT 0x0000000c +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_MODE_MASK 0x00000004L +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_MODE__SHIFT 0x00000002 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SCHMEN_MASK 0x00000800L +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SCHMEN__SHIFT 0x0000000b +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SEL_MASK 0x00000002L +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SEL__SHIFT 0x00000001 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SLEWN_MASK 0x00000200L +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SLEWN__SHIFT 0x00000009 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN0_MASK 0x00000020L +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN0__SHIFT 0x00000005 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN1_MASK 0x00000040L +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN1__SHIFT 0x00000006 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN2_MASK 0x00000080L +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN2__SHIFT 0x00000007 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN3_MASK 0x00000100L +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN3__SHIFT 0x00000008 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SPARE_MASK 0x00000018L +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SPARE__SHIFT 0x00000003 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_WAKE_MASK 0x00000400L +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_WAKE__SHIFT 0x0000000a +#define SMBUS_BACO_DUMMY__SMBUS_BACO_DUMMY_DATA_MASK 0xffffffffL +#define SMBUS_BACO_DUMMY__SMBUS_BACO_DUMMY_DATA__SHIFT 0x00000000 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h new file mode 100644 index 000000000000..ae798f768853 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h @@ -0,0 +1,4457 @@ +/* + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef DCE_6_0_D_H +#define DCE_6_0_D_H + +#define ixATTR00 0x0000 +#define ixATTR01 0x0001 +#define ixATTR02 0x0002 +#define ixATTR03 0x0003 +#define ixATTR04 0x0004 +#define ixATTR05 0x0005 +#define ixATTR06 0x0006 +#define ixATTR07 0x0007 +#define ixATTR08 0x0008 +#define ixATTR09 0x0009 +#define ixATTR0A 0x000A +#define ixATTR0B 0x000B +#define ixATTR0C 0x000C +#define ixATTR0D 0x000D +#define ixATTR0E 0x000E +#define ixATTR0F 0x000F +#define ixATTR10 0x0010 +#define ixATTR11 0x0011 +#define ixATTR12 0x0012 +#define ixATTR13 0x0013 +#define ixATTR14 0x0014 +#define ixAUDIO_DESCRIPTOR0 0x0001 +#define ixAUDIO_DESCRIPTOR10 0x000B +#define ixAUDIO_DESCRIPTOR1 0x0002 +#define ixAUDIO_DESCRIPTOR11 0x000C +#define ixAUDIO_DESCRIPTOR12 0x000D +#define ixAUDIO_DESCRIPTOR13 0x000E +#define ixAUDIO_DESCRIPTOR2 0x0003 +#define ixAUDIO_DESCRIPTOR3 0x0004 +#define ixAUDIO_DESCRIPTOR4 0x0005 +#define ixAUDIO_DESCRIPTOR5 0x0006 +#define ixAUDIO_DESCRIPTOR6 0x0007 +#define ixAUDIO_DESCRIPTOR7 0x0008 +#define ixAUDIO_DESCRIPTOR8 0x0009 +#define ixAUDIO_DESCRIPTOR9 0x000A +#define ixAZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 +#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG 0x0000 +#define ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002A +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002B +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002C +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002D +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002E +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002F +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003A +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003B +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003C +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003D +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003E +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003F +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005A +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005B +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005C +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005D +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005E +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005F +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270D +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270E +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273E +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2F09 +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2F0B +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2F0A +#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17FF +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1F05 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1F0F +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1F0B +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1F04 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1F0A +#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377C +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377B +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377A +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371C +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371D +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371E +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371F +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3F09 +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3F0C +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3F0E +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0x0F02 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0x0F04 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0F00 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378A +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378B +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378C +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378D +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378E +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378F +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 +#define ixAZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZALIA_STREAM_DEBUG 0x0005 +#define ixAZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixCRT00 0x0000 +#define ixCRT01 0x0001 +#define ixCRT02 0x0002 +#define ixCRT03 0x0003 +#define ixCRT04 0x0004 +#define ixCRT05 0x0005 +#define ixCRT06 0x0006 +#define ixCRT07 0x0007 +#define ixCRT08 0x0008 +#define ixCRT09 0x0009 +#define ixCRT0A 0x000A +#define ixCRT0B 0x000B +#define ixCRT0C 0x000C +#define ixCRT0D 0x000D +#define ixCRT0E 0x000E +#define ixCRT0F 0x000F +#define ixCRT10 0x0010 +#define ixCRT11 0x0011 +#define ixCRT12 0x0012 +#define ixCRT13 0x0013 +#define ixCRT14 0x0014 +#define ixCRT15 0x0015 +#define ixCRT16 0x0016 +#define ixCRT17 0x0017 +#define ixCRT18 0x0018 +#define ixCRT1E 0x001E +#define ixCRT1F 0x001F +#define ixCRT22 0x0022 +#define ixDCIO_DEBUG10 0x0010 +#define ixDCIO_DEBUG1 0x0001 +#define ixDCIO_DEBUG11 0x0011 +#define ixDCIO_DEBUG12 0x0012 +#define ixDCIO_DEBUG13 0x0013 +#define ixDCIO_DEBUG2 0x0002 +#define ixDCIO_DEBUG3 0x0003 +#define ixDCIO_DEBUG4 0x0004 +#define ixDCIO_DEBUG5 0x0005 +#define ixDCIO_DEBUG6 0x0006 +#define ixDCIO_DEBUG7 0x0007 +#define ixDCIO_DEBUG8 0x0008 +#define ixDCIO_DEBUG9 0x0009 +#define ixDCIO_DEBUGA 0x000A +#define ixDCIO_DEBUGB 0x000B +#define ixDCIO_DEBUGC 0x000C +#define ixDCIO_DEBUGD 0x000D +#define ixDCIO_DEBUGE 0x000E +#define ixDCIO_DEBUGF 0x000F +#define ixDCIO_DEBUG_ID 0x0000 +#define ixDMIF_DEBUG02_CORE0 0x0002 +#define ixDMIF_DEBUG02_CORE1 0x000A +#define ixDP_AUX1_DEBUG_A 0x0010 +#define ixDP_AUX1_DEBUG_B 0x0011 +#define ixDP_AUX1_DEBUG_C 0x0012 +#define ixDP_AUX1_DEBUG_D 0x0013 +#define ixDP_AUX1_DEBUG_E 0x0014 +#define ixDP_AUX1_DEBUG_F 0x0015 +#define ixDP_AUX1_DEBUG_G 0x0016 +#define ixDP_AUX1_DEBUG_H 0x0017 +#define ixDP_AUX1_DEBUG_I 0x0018 +#define ixDP_AUX2_DEBUG_A 0x0020 +#define ixDP_AUX2_DEBUG_B 0x0021 +#define ixDP_AUX2_DEBUG_C 0x0022 +#define ixDP_AUX2_DEBUG_D 0x0023 +#define ixDP_AUX2_DEBUG_E 0x0024 +#define ixDP_AUX2_DEBUG_F 0x0025 +#define ixDP_AUX2_DEBUG_G 0x0026 +#define ixDP_AUX2_DEBUG_H 0x0027 +#define ixDP_AUX2_DEBUG_I 0x0028 +#define ixDP_AUX3_DEBUG_A 0x0030 +#define ixDP_AUX3_DEBUG_B 0x0031 +#define ixDP_AUX3_DEBUG_C 0x0032 +#define ixDP_AUX3_DEBUG_D 0x0033 +#define ixDP_AUX3_DEBUG_E 0x0034 +#define ixDP_AUX3_DEBUG_F 0x0035 +#define ixDP_AUX3_DEBUG_G 0x0036 +#define ixDP_AUX3_DEBUG_H 0x0037 +#define ixDP_AUX3_DEBUG_I 0x0038 +#define ixDP_AUX4_DEBUG_A 0x0040 +#define ixDP_AUX4_DEBUG_B 0x0041 +#define ixDP_AUX4_DEBUG_C 0x0042 +#define ixDP_AUX4_DEBUG_D 0x0043 +#define ixDP_AUX4_DEBUG_E 0x0044 +#define ixDP_AUX4_DEBUG_F 0x0045 +#define ixDP_AUX4_DEBUG_G 0x0046 +#define ixDP_AUX4_DEBUG_H 0x0047 +#define ixDP_AUX4_DEBUG_I 0x0048 +#define ixDP_AUX5_DEBUG_A 0x0070 +#define ixDP_AUX5_DEBUG_B 0x0071 +#define ixDP_AUX5_DEBUG_C 0x0072 +#define ixDP_AUX5_DEBUG_D 0x0073 +#define ixDP_AUX5_DEBUG_E 0x0074 +#define ixDP_AUX5_DEBUG_F 0x0075 +#define ixDP_AUX5_DEBUG_G 0x0076 +#define ixDP_AUX5_DEBUG_H 0x0077 +#define ixDP_AUX5_DEBUG_I 0x0078 +#define ixDP_AUX6_DEBUG_A 0x0080 +#define ixDP_AUX6_DEBUG_B 0x0081 +#define ixDP_AUX6_DEBUG_C 0x0082 +#define ixDP_AUX6_DEBUG_D 0x0083 +#define ixDP_AUX6_DEBUG_E 0x0084 +#define ixDP_AUX6_DEBUG_F 0x0085 +#define ixDP_AUX6_DEBUG_G 0x0086 +#define ixDP_AUX6_DEBUG_H 0x0087 +#define ixDP_AUX6_DEBUG_I 0x0088 +#define ixFMT_DEBUG0 0x0001 +#define ixFMT_DEBUG1 0x0002 +#define ixFMT_DEBUG2 0x0003 +#define ixFMT_DEBUG_ID 0x0000 +#define ixGRA00 0x0000 +#define ixGRA01 0x0001 +#define ixGRA02 0x0002 +#define ixGRA03 0x0003 +#define ixGRA04 0x0004 +#define ixGRA05 0x0005 +#define ixGRA06 0x0006 +#define ixGRA07 0x0007 +#define ixGRA08 0x0008 +#define ixIDDCCIF02_DBG_DCCIF_C 0x0009 +#define ixIDDCCIF04_DBG_DCCIF_E 0x000B +#define ixIDDCCIF05_DBG_DCCIF_F 0x000C +#define ixMVP_DEBUG_12 0x000C +#define ixMVP_DEBUG_13 0x000D +#define ixMVP_DEBUG_14 0x000E +#define ixMVP_DEBUG_15 0x000F +#define ixMVP_DEBUG_16 0x0010 +#define ixMVP_DEBUG_17 0x0011 +#define ixSEQ00 0x0000 +#define ixSEQ01 0x0001 +#define ixSEQ02 0x0002 +#define ixSEQ03 0x0003 +#define ixSEQ04 0x0004 +#define ixSINK_DESCRIPTION0 0x0005 +#define ixSINK_DESCRIPTION10 0x000F +#define ixSINK_DESCRIPTION1 0x0006 +#define ixSINK_DESCRIPTION11 0x0010 +#define ixSINK_DESCRIPTION12 0x0011 +#define ixSINK_DESCRIPTION13 0x0012 +#define ixSINK_DESCRIPTION14 0x0013 +#define ixSINK_DESCRIPTION15 0x0014 +#define ixSINK_DESCRIPTION16 0x0015 +#define ixSINK_DESCRIPTION17 0x0016 +#define ixSINK_DESCRIPTION2 0x0007 +#define ixSINK_DESCRIPTION3 0x0008 +#define ixSINK_DESCRIPTION4 0x0009 +#define ixSINK_DESCRIPTION5 0x000A +#define ixSINK_DESCRIPTION6 0x000B +#define ixSINK_DESCRIPTION7 0x000C +#define ixSINK_DESCRIPTION8 0x000D +#define ixSINK_DESCRIPTION9 0x000E +#define ixVGADCC_DBG_DCCIF_C 0x007E +#define mmABM_TEST_DEBUG_DATA 0x169F +#define mmABM_TEST_DEBUG_INDEX 0x169E +#define mmAFMT_60958_0 0x1C41 +#define mmAFMT_60958_1 0x1C42 +#define mmAFMT_60958_2 0x1C48 +#define mmAFMT_AUDIO_CRC_CONTROL 0x1C43 +#define mmAFMT_AUDIO_CRC_RESULT 0x1C49 +#define mmAFMT_AUDIO_DBG_DTO_CNTL 0x1C52 +#define mmAFMT_AUDIO_INFO0 0x1C3F +#define mmAFMT_AUDIO_INFO1 0x1C40 +#define mmAFMT_AUDIO_PACKET_CONTROL 0x1C4B +#define mmAFMT_AUDIO_PACKET_CONTROL2 0x1C17 +#define mmAFMT_AUDIO_SRC_CONTROL 0x1C4F +#define mmAFMT_AVI_INFO0 0x1C21 +#define mmAFMT_AVI_INFO1 0x1C22 +#define mmAFMT_AVI_INFO2 0x1C23 +#define mmAFMT_AVI_INFO3 0x1C24 +#define mmAFMT_GENERIC_0 0x1C28 +#define mmAFMT_GENERIC_1 0x1C29 +#define mmAFMT_GENERIC_2 0x1C2A +#define mmAFMT_GENERIC_3 0x1C2B +#define mmAFMT_GENERIC_4 0x1C2C +#define mmAFMT_GENERIC_5 0x1C2D +#define mmAFMT_GENERIC_6 0x1C2E +#define mmAFMT_GENERIC_7 0x1C2F +#define mmAFMT_GENERIC_HDR 0x1C27 +#define mmAFMT_INFOFRAME_CONTROL0 0x1C4D +#define mmAFMT_INTERRUPT_STATUS 0x1C14 +#define mmAFMT_ISRC1_0 0x1C18 +#define mmAFMT_ISRC1_1 0x1C19 +#define mmAFMT_ISRC1_2 0x1C1A +#define mmAFMT_ISRC1_3 0x1C1B +#define mmAFMT_ISRC1_4 0x1C1C +#define mmAFMT_ISRC2_0 0x1C1D +#define mmAFMT_ISRC2_1 0x1C1E +#define mmAFMT_ISRC2_2 0x1C1F +#define mmAFMT_ISRC2_3 0x1C20 +#define mmAFMT_MPEG_INFO0 0x1C25 +#define mmAFMT_MPEG_INFO1 0x1C26 +#define mmAFMT_RAMP_CONTROL0 0x1C44 +#define mmAFMT_RAMP_CONTROL1 0x1C45 +#define mmAFMT_RAMP_CONTROL2 0x1C46 +#define mmAFMT_RAMP_CONTROL3 0x1C47 +#define mmAFMT_STATUS 0x1C4A +#define mmAFMT_VBI_PACKET_CONTROL 0x1C4C +#define mmATTRDR 0x00F0 +#define mmATTRDW 0x00F0 +#define mmATTRX 0x00F0 +#define mmAUX_ARB_CONTROL 0x1882 +#define mmAUX_CONTROL 0x1880 +#define mmAUX_DPHY_RX_CONTROL0 0x188A +#define mmAUX_DPHY_RX_CONTROL1 0x188B +#define mmAUX_DPHY_RX_STATUS 0x188D +#define mmAUX_DPHY_TX_CONTROL 0x1889 +#define mmAUX_DPHY_TX_REF_CONTROL 0x1888 +#define mmAUX_DPHY_TX_STATUS 0x188C +#define mmAUX_GTC_SYNC_CONTROL 0x188E +#define mmAUX_GTC_SYNC_DATA 0x1890 +#define mmAUX_INTERRUPT_CONTROL 0x1883 +#define mmAUX_LS_DATA 0x1887 +#define mmAUX_LS_STATUS 0x1885 +#define mmAUXN_IMPCAL 0x190C +#define mmAUXP_IMPCAL 0x190B +#define mmAUX_SW_CONTROL 0x1881 +#define mmAUX_SW_DATA 0x1886 +#define mmAUX_SW_STATUS 0x1884 +#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x17C9 +#define mmAZALIA_AUDIO_DTO 0x17BA +#define mmAZALIA_AUDIO_DTO_CONTROL 0x17BB +#define mmAZALIA_BDL_DMA_CONTROL 0x17BF +#define mmAZALIA_CONTROLLER_DEBUG 0x17CF +#define mmAZALIA_CORB_DMA_CONTROL 0x17C1 +#define mmAZALIA_CYCLIC_BUFFER_SYNC 0x17CA +#define mmAZALIA_DATA_DMA_CONTROL 0x17BE +#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x17D5 +#define mmAZALIA_F0_CODEC_DEBUG 0x17DF +#define mmAZALIA_F0_CODEC_ENDPOINT_DATA 0x1781 +#define mmAZALIA_F0_CODEC_ENDPOINT_INDEX 0x1780 +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x17DE +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x17DB +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x17DC +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x17DD +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x17D7 +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x17DA +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x17D9 +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x17D8 +#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x17D6 +#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x17D3 +#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x17D2 +#define mmAZALIA_GLOBAL_CAPABILITIES 0x17CB +#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x17CC +#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x17CD +#define mmAZALIA_RIRB_AND_DP_CONTROL 0x17C0 +#define mmAZALIA_SCLK_CONTROL 0x17BC +#define mmAZALIA_STREAM_DATA 0x17E9 +#define mmAZALIA_STREAM_INDEX 0x17E8 +#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x17BD +#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1781 +#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1780 +#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1787 +#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1786 +#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x178D +#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x178C +#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1793 +#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1792 +#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1799 +#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1798 +#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x179F +#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x179E +#define mmAZF0STREAM0_AZALIA_STREAM_DATA 0x17E9 +#define mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x17E8 +#define mmAZF0STREAM1_AZALIA_STREAM_DATA 0x17ED +#define mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x17EC +#define mmAZF0STREAM2_AZALIA_STREAM_DATA 0x17F1 +#define mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x17F0 +#define mmAZF0STREAM3_AZALIA_STREAM_DATA 0x17F5 +#define mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x17F4 +#define mmAZF0STREAM4_AZALIA_STREAM_DATA 0x17F9 +#define mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x17F8 +#define mmAZF0STREAM5_AZALIA_STREAM_DATA 0x17FD +#define mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x17FC +#define mmAZ_TEST_DEBUG_DATA 0x17D1 +#define mmAZ_TEST_DEBUG_INDEX 0x17D0 +#define mmBL1_PWM_ABM_CNTL 0x162E +#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL 0x1628 +#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 0x162F +#define mmBL1_PWM_CURRENT_ABM_LEVEL 0x162B +#define mmBL1_PWM_FINAL_DUTY_CYCLE 0x162C +#define mmBL1_PWM_GRP2_REG_LOCK 0x1630 +#define mmBL1_PWM_MINIMUM_DUTY_CYCLE 0x162D +#define mmBL1_PWM_TARGET_ABM_LEVEL 0x162A +#define mmBL1_PWM_USER_LEVEL 0x1629 +#define mmBL_PWM_CNTL 0x191E +#define mmBL_PWM_CNTL2 0x191F +#define mmBL_PWM_GRP1_REG_LOCK 0x1921 +#define mmBL_PWM_PERIOD_CNTL 0x1920 +#define mmBPHYC_DAC_AUTO_CALIB_CONTROL 0x19FE +#define mmBPHYC_DAC_MACRO_CNTL 0x19FD +#define mmCC_DC_PIPE_DIS 0x177F +#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x17D4 +#define mmCOMM_MATRIXA_TRANS_C11_C12 0x1A43 +#define mmCOMM_MATRIXA_TRANS_C13_C14 0x1A44 +#define mmCOMM_MATRIXA_TRANS_C21_C22 0x1A45 +#define mmCOMM_MATRIXA_TRANS_C23_C24 0x1A46 +#define mmCOMM_MATRIXA_TRANS_C31_C32 0x1A47 +#define mmCOMM_MATRIXA_TRANS_C33_C34 0x1A48 +#define mmCOMM_MATRIXB_TRANS_C11_C12 0x1A49 +#define mmCOMM_MATRIXB_TRANS_C13_C14 0x1A4A +#define mmCOMM_MATRIXB_TRANS_C21_C22 0x1A4B +#define mmCOMM_MATRIXB_TRANS_C23_C24 0x1A4C +#define mmCOMM_MATRIXB_TRANS_C31_C32 0x1A4D +#define mmCOMM_MATRIXB_TRANS_C33_C34 0x1A4E +#define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL 0x1B78 +#define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT 0x1BC3 +#define mmCRTC0_CRTC_BLACK_COLOR 0x1BA2 +#define mmCRTC0_CRTC_BLANK_CONTROL 0x1B9D +#define mmCRTC0_CRTC_BLANK_DATA_COLOR 0x1BA1 +#define mmCRTC0_CRTC_CONTROL 0x1B9C +#define mmCRTC0_CRTC_COUNT_CONTROL 0x1BA9 +#define mmCRTC0_CRTC_COUNT_RESET 0x1BAA +#define mmCRTC0_CRTC_DCFE_CLOCK_CONTROL 0x1B7C +#define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL 0x1BB6 +#define mmCRTC0_CRTC_DTMTEST_CNTL 0x1B92 +#define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION 0x1B93 +#define mmCRTC0_CRTC_FLOW_CONTROL 0x1B99 +#define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL 0x1B98 +#define mmCRTC0_CRTC_GSL_CONTROL 0x1B7B +#define mmCRTC0_CRTC_GSL_VSYNC_GAP 0x1B79 +#define mmCRTC0_CRTC_GSL_WINDOW 0x1B7A +#define mmCRTC0_CRTC_H_BLANK_EARLY_NUM 0x1B7D +#define mmCRTC0_CRTC_H_BLANK_START_END 0x1B81 +#define mmCRTC0_CRTC_H_SYNC_A 0x1B82 +#define mmCRTC0_CRTC_H_SYNC_A_CNTL 0x1B83 +#define mmCRTC0_CRTC_H_SYNC_B 0x1B84 +#define mmCRTC0_CRTC_H_SYNC_B_CNTL 0x1B85 +#define mmCRTC0_CRTC_H_TOTAL 0x1B80 +#define mmCRTC0_CRTC_INTERLACE_CONTROL 0x1B9E +#define mmCRTC0_CRTC_INTERLACE_STATUS 0x1B9F +#define mmCRTC0_CRTC_INTERRUPT_CONTROL 0x1BB4 +#define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1BAB +#define mmCRTC0_CRTC_MASTER_EN 0x1BC2 +#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT 0x1BBF +#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1BC0 +#define mmCRTC0_CRTC_MVP_STATUS 0x1BC1 +#define mmCRTC0_CRTC_NOM_VERT_POSITION 0x1BA5 +#define mmCRTC0_CRTC_OVERSCAN_COLOR 0x1BA0 +#define mmCRTC0_CRTC_SNAPSHOT_CONTROL 0x1BB0 +#define mmCRTC0_CRTC_SNAPSHOT_FRAME 0x1BB2 +#define mmCRTC0_CRTC_SNAPSHOT_POSITION 0x1BB1 +#define mmCRTC0_CRTC_SNAPSHOT_STATUS 0x1BAF +#define mmCRTC0_CRTC_START_LINE_CONTROL 0x1BB3 +#define mmCRTC0_CRTC_STATUS 0x1BA3 +#define mmCRTC0_CRTC_STATUS_FRAME_COUNT 0x1BA6 +#define mmCRTC0_CRTC_STATUS_HV_COUNT 0x1BA8 +#define mmCRTC0_CRTC_STATUS_POSITION 0x1BA4 +#define mmCRTC0_CRTC_STATUS_VF_COUNT 0x1BA7 +#define mmCRTC0_CRTC_STEREO_CONTROL 0x1BAE +#define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE 0x1B9B +#define mmCRTC0_CRTC_STEREO_STATUS 0x1BAD +#define mmCRTC0_CRTC_TEST_DEBUG_DATA 0x1BC7 +#define mmCRTC0_CRTC_TEST_DEBUG_INDEX 0x1BC6 +#define mmCRTC0_CRTC_TEST_PATTERN_COLOR 0x1BBC +#define mmCRTC0_CRTC_TEST_PATTERN_CONTROL 0x1BBA +#define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS 0x1BBB +#define mmCRTC0_CRTC_TRIGA_CNTL 0x1B94 +#define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG 0x1B95 +#define mmCRTC0_CRTC_TRIGB_CNTL 0x1B96 +#define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG 0x1B97 +#define mmCRTC0_CRTC_UPDATE_LOCK 0x1BB5 +#define mmCRTC0_CRTC_VBI_END 0x1B86 +#define mmCRTC0_CRTC_V_BLANK_START_END 0x1B8D +#define mmCRTC0_CRTC_VERT_SYNC_CONTROL 0x1BAC +#define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1BB7 +#define mmCRTC0_CRTC_V_SYNC_A 0x1B8E +#define mmCRTC0_CRTC_V_SYNC_A_CNTL 0x1B8F +#define mmCRTC0_CRTC_V_SYNC_B 0x1B90 +#define mmCRTC0_CRTC_V_SYNC_B_CNTL 0x1B91 +#define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS 0x1B8C +#define mmCRTC0_CRTC_V_TOTAL 0x1B87 +#define mmCRTC0_CRTC_V_TOTAL_CONTROL 0x1B8A +#define mmCRTC0_CRTC_V_TOTAL_INT_STATUS 0x1B8B +#define mmCRTC0_CRTC_V_TOTAL_MAX 0x1B89 +#define mmCRTC0_CRTC_V_TOTAL_MIN 0x1B88 +#define mmCRTC0_CRTC_V_UPDATE_INT_STATUS 0x1BC4 +#define mmCRTC0_DCFE_DBG_SEL 0x1B7E +#define mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL 0x1B7F +#define mmCRTC0_MASTER_UPDATE_LOCK 0x1BBD +#define mmCRTC0_MASTER_UPDATE_MODE 0x1BBE +#define mmCRTC0_PIXEL_RATE_CNTL 0x0140 +#define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL 0x1E78 +#define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT 0x1EC3 +#define mmCRTC1_CRTC_BLACK_COLOR 0x1EA2 +#define mmCRTC1_CRTC_BLANK_CONTROL 0x1E9D +#define mmCRTC1_CRTC_BLANK_DATA_COLOR 0x1EA1 +#define mmCRTC1_CRTC_CONTROL 0x1E9C +#define mmCRTC1_CRTC_COUNT_CONTROL 0x1EA9 +#define mmCRTC1_CRTC_COUNT_RESET 0x1EAA +#define mmCRTC1_CRTC_DCFE_CLOCK_CONTROL 0x1E7C +#define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL 0x1EB6 +#define mmCRTC1_CRTC_DTMTEST_CNTL 0x1E92 +#define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION 0x1E93 +#define mmCRTC1_CRTC_FLOW_CONTROL 0x1E99 +#define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL 0x1E98 +#define mmCRTC1_CRTC_GSL_CONTROL 0x1E7B +#define mmCRTC1_CRTC_GSL_VSYNC_GAP 0x1E79 +#define mmCRTC1_CRTC_GSL_WINDOW 0x1E7A +#define mmCRTC1_CRTC_H_BLANK_EARLY_NUM 0x1E7D +#define mmCRTC1_CRTC_H_BLANK_START_END 0x1E81 +#define mmCRTC1_CRTC_H_SYNC_A 0x1E82 +#define mmCRTC1_CRTC_H_SYNC_A_CNTL 0x1E83 +#define mmCRTC1_CRTC_H_SYNC_B 0x1E84 +#define mmCRTC1_CRTC_H_SYNC_B_CNTL 0x1E85 +#define mmCRTC1_CRTC_H_TOTAL 0x1E80 +#define mmCRTC1_CRTC_INTERLACE_CONTROL 0x1E9E +#define mmCRTC1_CRTC_INTERLACE_STATUS 0x1E9F +#define mmCRTC1_CRTC_INTERRUPT_CONTROL 0x1EB4 +#define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1EAB +#define mmCRTC1_CRTC_MASTER_EN 0x1EC2 +#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT 0x1EBF +#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1EC0 +#define mmCRTC1_CRTC_MVP_STATUS 0x1EC1 +#define mmCRTC1_CRTC_NOM_VERT_POSITION 0x1EA5 +#define mmCRTC1_CRTC_OVERSCAN_COLOR 0x1EA0 +#define mmCRTC1_CRTC_SNAPSHOT_CONTROL 0x1EB0 +#define mmCRTC1_CRTC_SNAPSHOT_FRAME 0x1EB2 +#define mmCRTC1_CRTC_SNAPSHOT_POSITION 0x1EB1 +#define mmCRTC1_CRTC_SNAPSHOT_STATUS 0x1EAF +#define mmCRTC1_CRTC_START_LINE_CONTROL 0x1EB3 +#define mmCRTC1_CRTC_STATUS 0x1EA3 +#define mmCRTC1_CRTC_STATUS_FRAME_COUNT 0x1EA6 +#define mmCRTC1_CRTC_STATUS_HV_COUNT 0x1EA8 +#define mmCRTC1_CRTC_STATUS_POSITION 0x1EA4 +#define mmCRTC1_CRTC_STATUS_VF_COUNT 0x1EA7 +#define mmCRTC1_CRTC_STEREO_CONTROL 0x1EAE +#define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE 0x1E9B +#define mmCRTC1_CRTC_STEREO_STATUS 0x1EAD +#define mmCRTC1_CRTC_TEST_DEBUG_DATA 0x1EC7 +#define mmCRTC1_CRTC_TEST_DEBUG_INDEX 0x1EC6 +#define mmCRTC1_CRTC_TEST_PATTERN_COLOR 0x1EBC +#define mmCRTC1_CRTC_TEST_PATTERN_CONTROL 0x1EBA +#define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS 0x1EBB +#define mmCRTC1_CRTC_TRIGA_CNTL 0x1E94 +#define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG 0x1E95 +#define mmCRTC1_CRTC_TRIGB_CNTL 0x1E96 +#define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG 0x1E97 +#define mmCRTC1_CRTC_UPDATE_LOCK 0x1EB5 +#define mmCRTC1_CRTC_VBI_END 0x1E86 +#define mmCRTC1_CRTC_V_BLANK_START_END 0x1E8D +#define mmCRTC1_CRTC_VERT_SYNC_CONTROL 0x1EAC +#define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1EB7 +#define mmCRTC1_CRTC_V_SYNC_A 0x1E8E +#define mmCRTC1_CRTC_V_SYNC_A_CNTL 0x1E8F +#define mmCRTC1_CRTC_V_SYNC_B 0x1E90 +#define mmCRTC1_CRTC_V_SYNC_B_CNTL 0x1E91 +#define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS 0x1E8C +#define mmCRTC1_CRTC_V_TOTAL 0x1E87 +#define mmCRTC1_CRTC_V_TOTAL_CONTROL 0x1E8A +#define mmCRTC1_CRTC_V_TOTAL_INT_STATUS 0x1E8B +#define mmCRTC1_CRTC_V_TOTAL_MAX 0x1E89 +#define mmCRTC1_CRTC_V_TOTAL_MIN 0x1E88 +#define mmCRTC1_CRTC_V_UPDATE_INT_STATUS 0x1EC4 +#define mmCRTC1_DCFE_DBG_SEL 0x1E7E +#define mmCRTC1_DCFE_MEM_LIGHT_SLEEP_CNTL 0x1E7F +#define mmCRTC1_MASTER_UPDATE_LOCK 0x1EBD +#define mmCRTC1_MASTER_UPDATE_MODE 0x1EBE +#define mmCRTC1_PIXEL_RATE_CNTL 0x0144 +#define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL 0x4178 +#define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT 0x41C3 +#define mmCRTC2_CRTC_BLACK_COLOR 0x41A2 +#define mmCRTC2_CRTC_BLANK_CONTROL 0x419D +#define mmCRTC2_CRTC_BLANK_DATA_COLOR 0x41A1 +#define mmCRTC2_CRTC_CONTROL 0x419C +#define mmCRTC2_CRTC_COUNT_CONTROL 0x41A9 +#define mmCRTC2_CRTC_COUNT_RESET 0x41AA +#define mmCRTC2_CRTC_DCFE_CLOCK_CONTROL 0x417C +#define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL 0x41B6 +#define mmCRTC2_CRTC_DTMTEST_CNTL 0x4192 +#define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION 0x4193 +#define mmCRTC2_CRTC_FLOW_CONTROL 0x4199 +#define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL 0x4198 +#define mmCRTC2_CRTC_GSL_CONTROL 0x417B +#define mmCRTC2_CRTC_GSL_VSYNC_GAP 0x4179 +#define mmCRTC2_CRTC_GSL_WINDOW 0x417A +#define mmCRTC2_CRTC_H_BLANK_EARLY_NUM 0x417D +#define mmCRTC2_CRTC_H_BLANK_START_END 0x4181 +#define mmCRTC2_CRTC_H_SYNC_A 0x4182 +#define mmCRTC2_CRTC_H_SYNC_A_CNTL 0x4183 +#define mmCRTC2_CRTC_H_SYNC_B 0x4184 +#define mmCRTC2_CRTC_H_SYNC_B_CNTL 0x4185 +#define mmCRTC2_CRTC_H_TOTAL 0x4180 +#define mmCRTC2_CRTC_INTERLACE_CONTROL 0x419E +#define mmCRTC2_CRTC_INTERLACE_STATUS 0x419F +#define mmCRTC2_CRTC_INTERRUPT_CONTROL 0x41B4 +#define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x41AB +#define mmCRTC2_CRTC_MASTER_EN 0x41C2 +#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT 0x41BF +#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x41C0 +#define mmCRTC2_CRTC_MVP_STATUS 0x41C1 +#define mmCRTC2_CRTC_NOM_VERT_POSITION 0x41A5 +#define mmCRTC2_CRTC_OVERSCAN_COLOR 0x41A0 +#define mmCRTC2_CRTC_SNAPSHOT_CONTROL 0x41B0 +#define mmCRTC2_CRTC_SNAPSHOT_FRAME 0x41B2 +#define mmCRTC2_CRTC_SNAPSHOT_POSITION 0x41B1 +#define mmCRTC2_CRTC_SNAPSHOT_STATUS 0x41AF +#define mmCRTC2_CRTC_START_LINE_CONTROL 0x41B3 +#define mmCRTC2_CRTC_STATUS 0x41A3 +#define mmCRTC2_CRTC_STATUS_FRAME_COUNT 0x41A6 +#define mmCRTC2_CRTC_STATUS_HV_COUNT 0x41A8 +#define mmCRTC2_CRTC_STATUS_POSITION 0x41A4 +#define mmCRTC2_CRTC_STATUS_VF_COUNT 0x41A7 +#define mmCRTC2_CRTC_STEREO_CONTROL 0x41AE +#define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE 0x419B +#define mmCRTC2_CRTC_STEREO_STATUS 0x41AD +#define mmCRTC2_CRTC_TEST_DEBUG_DATA 0x41C7 +#define mmCRTC2_CRTC_TEST_DEBUG_INDEX 0x41C6 +#define mmCRTC2_CRTC_TEST_PATTERN_COLOR 0x41BC +#define mmCRTC2_CRTC_TEST_PATTERN_CONTROL 0x41BA +#define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS 0x41BB +#define mmCRTC2_CRTC_TRIGA_CNTL 0x4194 +#define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG 0x4195 +#define mmCRTC2_CRTC_TRIGB_CNTL 0x4196 +#define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG 0x4197 +#define mmCRTC2_CRTC_UPDATE_LOCK 0x41B5 +#define mmCRTC2_CRTC_VBI_END 0x4186 +#define mmCRTC2_CRTC_V_BLANK_START_END 0x418D +#define mmCRTC2_CRTC_VERT_SYNC_CONTROL 0x41AC +#define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x41B7 +#define mmCRTC2_CRTC_V_SYNC_A 0x418E +#define mmCRTC2_CRTC_V_SYNC_A_CNTL 0x418F +#define mmCRTC2_CRTC_V_SYNC_B 0x4190 +#define mmCRTC2_CRTC_V_SYNC_B_CNTL 0x4191 +#define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS 0x418C +#define mmCRTC2_CRTC_V_TOTAL 0x4187 +#define mmCRTC2_CRTC_V_TOTAL_CONTROL 0x418A +#define mmCRTC2_CRTC_V_TOTAL_INT_STATUS 0x418B +#define mmCRTC2_CRTC_V_TOTAL_MAX 0x4189 +#define mmCRTC2_CRTC_V_TOTAL_MIN 0x4188 +#define mmCRTC2_CRTC_V_UPDATE_INT_STATUS 0x41C4 +#define mmCRTC2_DCFE_DBG_SEL 0x417E +#define mmCRTC2_DCFE_MEM_LIGHT_SLEEP_CNTL 0x417F +#define mmCRTC2_MASTER_UPDATE_LOCK 0x41BD +#define mmCRTC2_MASTER_UPDATE_MODE 0x41BE +#define mmCRTC2_PIXEL_RATE_CNTL 0x0148 +#define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL 0x4478 +#define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT 0x44C3 +#define mmCRTC3_CRTC_BLACK_COLOR 0x44A2 +#define mmCRTC3_CRTC_BLANK_CONTROL 0x449D +#define mmCRTC3_CRTC_BLANK_DATA_COLOR 0x44A1 +#define mmCRTC3_CRTC_CONTROL 0x449C +#define mmCRTC3_CRTC_COUNT_CONTROL 0x44A9 +#define mmCRTC3_CRTC_COUNT_RESET 0x44AA +#define mmCRTC3_CRTC_DCFE_CLOCK_CONTROL 0x447C +#define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL 0x44B6 +#define mmCRTC3_CRTC_DTMTEST_CNTL 0x4492 +#define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION 0x4493 +#define mmCRTC3_CRTC_FLOW_CONTROL 0x4499 +#define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL 0x4498 +#define mmCRTC3_CRTC_GSL_CONTROL 0x447B +#define mmCRTC3_CRTC_GSL_VSYNC_GAP 0x4479 +#define mmCRTC3_CRTC_GSL_WINDOW 0x447A +#define mmCRTC3_CRTC_H_BLANK_EARLY_NUM 0x447D +#define mmCRTC3_CRTC_H_BLANK_START_END 0x4481 +#define mmCRTC3_CRTC_H_SYNC_A 0x4482 +#define mmCRTC3_CRTC_H_SYNC_A_CNTL 0x4483 +#define mmCRTC3_CRTC_H_SYNC_B 0x4484 +#define mmCRTC3_CRTC_H_SYNC_B_CNTL 0x4485 +#define mmCRTC3_CRTC_H_TOTAL 0x4480 +#define mmCRTC3_CRTC_INTERLACE_CONTROL 0x449E +#define mmCRTC3_CRTC_INTERLACE_STATUS 0x449F +#define mmCRTC3_CRTC_INTERRUPT_CONTROL 0x44B4 +#define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x44AB +#define mmCRTC3_CRTC_MASTER_EN 0x44C2 +#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT 0x44BF +#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x44C0 +#define mmCRTC3_CRTC_MVP_STATUS 0x44C1 +#define mmCRTC3_CRTC_NOM_VERT_POSITION 0x44A5 +#define mmCRTC3_CRTC_OVERSCAN_COLOR 0x44A0 +#define mmCRTC3_CRTC_SNAPSHOT_CONTROL 0x44B0 +#define mmCRTC3_CRTC_SNAPSHOT_FRAME 0x44B2 +#define mmCRTC3_CRTC_SNAPSHOT_POSITION 0x44B1 +#define mmCRTC3_CRTC_SNAPSHOT_STATUS 0x44AF +#define mmCRTC3_CRTC_START_LINE_CONTROL 0x44B3 +#define mmCRTC3_CRTC_STATUS 0x44A3 +#define mmCRTC3_CRTC_STATUS_FRAME_COUNT 0x44A6 +#define mmCRTC3_CRTC_STATUS_HV_COUNT 0x44A8 +#define mmCRTC3_CRTC_STATUS_POSITION 0x44A4 +#define mmCRTC3_CRTC_STATUS_VF_COUNT 0x44A7 +#define mmCRTC3_CRTC_STEREO_CONTROL 0x44AE +#define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE 0x449B +#define mmCRTC3_CRTC_STEREO_STATUS 0x44AD +#define mmCRTC3_CRTC_TEST_DEBUG_DATA 0x44C7 +#define mmCRTC3_CRTC_TEST_DEBUG_INDEX 0x44C6 +#define mmCRTC3_CRTC_TEST_PATTERN_COLOR 0x44BC +#define mmCRTC3_CRTC_TEST_PATTERN_CONTROL 0x44BA +#define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS 0x44BB +#define mmCRTC3_CRTC_TRIGA_CNTL 0x4494 +#define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG 0x4495 +#define mmCRTC3_CRTC_TRIGB_CNTL 0x4496 +#define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG 0x4497 +#define mmCRTC3_CRTC_UPDATE_LOCK 0x44B5 +#define mmCRTC3_CRTC_VBI_END 0x4486 +#define mmCRTC3_CRTC_V_BLANK_START_END 0x448D +#define mmCRTC3_CRTC_VERT_SYNC_CONTROL 0x44AC +#define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x44B7 +#define mmCRTC3_CRTC_V_SYNC_A 0x448E +#define mmCRTC3_CRTC_V_SYNC_A_CNTL 0x448F +#define mmCRTC3_CRTC_V_SYNC_B 0x4490 +#define mmCRTC3_CRTC_V_SYNC_B_CNTL 0x4491 +#define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS 0x448C +#define mmCRTC3_CRTC_V_TOTAL 0x4487 +#define mmCRTC3_CRTC_V_TOTAL_CONTROL 0x448A +#define mmCRTC3_CRTC_V_TOTAL_INT_STATUS 0x448B +#define mmCRTC3_CRTC_V_TOTAL_MAX 0x4489 +#define mmCRTC3_CRTC_V_TOTAL_MIN 0x4488 +#define mmCRTC3_CRTC_V_UPDATE_INT_STATUS 0x44C4 +#define mmCRTC3_DCFE_DBG_SEL 0x447E +#define mmCRTC3_DCFE_MEM_LIGHT_SLEEP_CNTL 0x447F +#define mmCRTC_3D_STRUCTURE_CONTROL 0x1B78 +#define mmCRTC3_MASTER_UPDATE_LOCK 0x44BD +#define mmCRTC3_MASTER_UPDATE_MODE 0x44BE +#define mmCRTC3_PIXEL_RATE_CNTL 0x014C +#define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL 0x4778 +#define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT 0x47C3 +#define mmCRTC4_CRTC_BLACK_COLOR 0x47A2 +#define mmCRTC4_CRTC_BLANK_CONTROL 0x479D +#define mmCRTC4_CRTC_BLANK_DATA_COLOR 0x47A1 +#define mmCRTC4_CRTC_CONTROL 0x479C +#define mmCRTC4_CRTC_COUNT_CONTROL 0x47A9 +#define mmCRTC4_CRTC_COUNT_RESET 0x47AA +#define mmCRTC4_CRTC_DCFE_CLOCK_CONTROL 0x477C +#define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL 0x47B6 +#define mmCRTC4_CRTC_DTMTEST_CNTL 0x4792 +#define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION 0x4793 +#define mmCRTC4_CRTC_FLOW_CONTROL 0x4799 +#define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL 0x4798 +#define mmCRTC4_CRTC_GSL_CONTROL 0x477B +#define mmCRTC4_CRTC_GSL_VSYNC_GAP 0x4779 +#define mmCRTC4_CRTC_GSL_WINDOW 0x477A +#define mmCRTC4_CRTC_H_BLANK_EARLY_NUM 0x477D +#define mmCRTC4_CRTC_H_BLANK_START_END 0x4781 +#define mmCRTC4_CRTC_H_SYNC_A 0x4782 +#define mmCRTC4_CRTC_H_SYNC_A_CNTL 0x4783 +#define mmCRTC4_CRTC_H_SYNC_B 0x4784 +#define mmCRTC4_CRTC_H_SYNC_B_CNTL 0x4785 +#define mmCRTC4_CRTC_H_TOTAL 0x4780 +#define mmCRTC4_CRTC_INTERLACE_CONTROL 0x479E +#define mmCRTC4_CRTC_INTERLACE_STATUS 0x479F +#define mmCRTC4_CRTC_INTERRUPT_CONTROL 0x47B4 +#define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x47AB +#define mmCRTC4_CRTC_MASTER_EN 0x47C2 +#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT 0x47BF +#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x47C0 +#define mmCRTC4_CRTC_MVP_STATUS 0x47C1 +#define mmCRTC4_CRTC_NOM_VERT_POSITION 0x47A5 +#define mmCRTC4_CRTC_OVERSCAN_COLOR 0x47A0 +#define mmCRTC4_CRTC_SNAPSHOT_CONTROL 0x47B0 +#define mmCRTC4_CRTC_SNAPSHOT_FRAME 0x47B2 +#define mmCRTC4_CRTC_SNAPSHOT_POSITION 0x47B1 +#define mmCRTC4_CRTC_SNAPSHOT_STATUS 0x47AF +#define mmCRTC4_CRTC_START_LINE_CONTROL 0x47B3 +#define mmCRTC4_CRTC_STATUS 0x47A3 +#define mmCRTC4_CRTC_STATUS_FRAME_COUNT 0x47A6 +#define mmCRTC4_CRTC_STATUS_HV_COUNT 0x47A8 +#define mmCRTC4_CRTC_STATUS_POSITION 0x47A4 +#define mmCRTC4_CRTC_STATUS_VF_COUNT 0x47A7 +#define mmCRTC4_CRTC_STEREO_CONTROL 0x47AE +#define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE 0x479B +#define mmCRTC4_CRTC_STEREO_STATUS 0x47AD +#define mmCRTC4_CRTC_TEST_DEBUG_DATA 0x47C7 +#define mmCRTC4_CRTC_TEST_DEBUG_INDEX 0x47C6 +#define mmCRTC4_CRTC_TEST_PATTERN_COLOR 0x47BC +#define mmCRTC4_CRTC_TEST_PATTERN_CONTROL 0x47BA +#define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS 0x47BB +#define mmCRTC4_CRTC_TRIGA_CNTL 0x4794 +#define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG 0x4795 +#define mmCRTC4_CRTC_TRIGB_CNTL 0x4796 +#define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG 0x4797 +#define mmCRTC4_CRTC_UPDATE_LOCK 0x47B5 +#define mmCRTC4_CRTC_VBI_END 0x4786 +#define mmCRTC4_CRTC_V_BLANK_START_END 0x478D +#define mmCRTC4_CRTC_VERT_SYNC_CONTROL 0x47AC +#define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x47B7 +#define mmCRTC4_CRTC_V_SYNC_A 0x478E +#define mmCRTC4_CRTC_V_SYNC_A_CNTL 0x478F +#define mmCRTC4_CRTC_V_SYNC_B 0x4790 +#define mmCRTC4_CRTC_V_SYNC_B_CNTL 0x4791 +#define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS 0x478C +#define mmCRTC4_CRTC_V_TOTAL 0x4787 +#define mmCRTC4_CRTC_V_TOTAL_CONTROL 0x478A +#define mmCRTC4_CRTC_V_TOTAL_INT_STATUS 0x478B +#define mmCRTC4_CRTC_V_TOTAL_MAX 0x4789 +#define mmCRTC4_CRTC_V_TOTAL_MIN 0x4788 +#define mmCRTC4_CRTC_V_UPDATE_INT_STATUS 0x47C4 +#define mmCRTC4_DCFE_DBG_SEL 0x477E +#define mmCRTC4_DCFE_MEM_LIGHT_SLEEP_CNTL 0x477F +#define mmCRTC4_MASTER_UPDATE_LOCK 0x47BD +#define mmCRTC4_MASTER_UPDATE_MODE 0x47BE +#define mmCRTC4_PIXEL_RATE_CNTL 0x0150 +#define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL 0x4A78 +#define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT 0x4AC3 +#define mmCRTC5_CRTC_BLACK_COLOR 0x4AA2 +#define mmCRTC5_CRTC_BLANK_CONTROL 0x4A9D +#define mmCRTC5_CRTC_BLANK_DATA_COLOR 0x4AA1 +#define mmCRTC5_CRTC_CONTROL 0x4A9C +#define mmCRTC5_CRTC_COUNT_CONTROL 0x4AA9 +#define mmCRTC5_CRTC_COUNT_RESET 0x4AAA +#define mmCRTC5_CRTC_DCFE_CLOCK_CONTROL 0x4A7C +#define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL 0x4AB6 +#define mmCRTC5_CRTC_DTMTEST_CNTL 0x4A92 +#define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION 0x4A93 +#define mmCRTC5_CRTC_FLOW_CONTROL 0x4A99 +#define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL 0x4A98 +#define mmCRTC5_CRTC_GSL_CONTROL 0x4A7B +#define mmCRTC5_CRTC_GSL_VSYNC_GAP 0x4A79 +#define mmCRTC5_CRTC_GSL_WINDOW 0x4A7A +#define mmCRTC5_CRTC_H_BLANK_EARLY_NUM 0x4A7D +#define mmCRTC5_CRTC_H_BLANK_START_END 0x4A81 +#define mmCRTC5_CRTC_H_SYNC_A 0x4A82 +#define mmCRTC5_CRTC_H_SYNC_A_CNTL 0x4A83 +#define mmCRTC5_CRTC_H_SYNC_B 0x4A84 +#define mmCRTC5_CRTC_H_SYNC_B_CNTL 0x4A85 +#define mmCRTC5_CRTC_H_TOTAL 0x4A80 +#define mmCRTC5_CRTC_INTERLACE_CONTROL 0x4A9E +#define mmCRTC5_CRTC_INTERLACE_STATUS 0x4A9F +#define mmCRTC5_CRTC_INTERRUPT_CONTROL 0x4AB4 +#define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x4AAB +#define mmCRTC5_CRTC_MASTER_EN 0x4AC2 +#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT 0x4ABF +#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x4AC0 +#define mmCRTC5_CRTC_MVP_STATUS 0x4AC1 +#define mmCRTC5_CRTC_NOM_VERT_POSITION 0x4AA5 +#define mmCRTC5_CRTC_OVERSCAN_COLOR 0x4AA0 +#define mmCRTC5_CRTC_SNAPSHOT_CONTROL 0x4AB0 +#define mmCRTC5_CRTC_SNAPSHOT_FRAME 0x4AB2 +#define mmCRTC5_CRTC_SNAPSHOT_POSITION 0x4AB1 +#define mmCRTC5_CRTC_SNAPSHOT_STATUS 0x4AAF +#define mmCRTC5_CRTC_START_LINE_CONTROL 0x4AB3 +#define mmCRTC5_CRTC_STATUS 0x4AA3 +#define mmCRTC5_CRTC_STATUS_FRAME_COUNT 0x4AA6 +#define mmCRTC5_CRTC_STATUS_HV_COUNT 0x4AA8 +#define mmCRTC5_CRTC_STATUS_POSITION 0x4AA4 +#define mmCRTC5_CRTC_STATUS_VF_COUNT 0x4AA7 +#define mmCRTC5_CRTC_STEREO_CONTROL 0x4AAE +#define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE 0x4A9B +#define mmCRTC5_CRTC_STEREO_STATUS 0x4AAD +#define mmCRTC5_CRTC_TEST_DEBUG_DATA 0x4AC7 +#define mmCRTC5_CRTC_TEST_DEBUG_INDEX 0x4AC6 +#define mmCRTC5_CRTC_TEST_PATTERN_COLOR 0x4ABC +#define mmCRTC5_CRTC_TEST_PATTERN_CONTROL 0x4ABA +#define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS 0x4ABB +#define mmCRTC5_CRTC_TRIGA_CNTL 0x4A94 +#define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG 0x4A95 +#define mmCRTC5_CRTC_TRIGB_CNTL 0x4A96 +#define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG 0x4A97 +#define mmCRTC5_CRTC_UPDATE_LOCK 0x4AB5 +#define mmCRTC5_CRTC_VBI_END 0x4A86 +#define mmCRTC5_CRTC_V_BLANK_START_END 0x4A8D +#define mmCRTC5_CRTC_VERT_SYNC_CONTROL 0x4AAC +#define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x4AB7 +#define mmCRTC5_CRTC_V_SYNC_A 0x4A8E +#define mmCRTC5_CRTC_V_SYNC_A_CNTL 0x4A8F +#define mmCRTC5_CRTC_V_SYNC_B 0x4A90 +#define mmCRTC5_CRTC_V_SYNC_B_CNTL 0x4A91 +#define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS 0x4A8C +#define mmCRTC5_CRTC_V_TOTAL 0x4A87 +#define mmCRTC5_CRTC_V_TOTAL_CONTROL 0x4A8A +#define mmCRTC5_CRTC_V_TOTAL_INT_STATUS 0x4A8B +#define mmCRTC5_CRTC_V_TOTAL_MAX 0x4A89 +#define mmCRTC5_CRTC_V_TOTAL_MIN 0x4A88 +#define mmCRTC5_CRTC_V_UPDATE_INT_STATUS 0x4AC4 +#define mmCRTC5_DCFE_DBG_SEL 0x4A7E +#define mmCRTC5_DCFE_MEM_LIGHT_SLEEP_CNTL 0x4A7F +#define mmCRTC5_MASTER_UPDATE_LOCK 0x4ABD +#define mmCRTC5_MASTER_UPDATE_MODE 0x4ABE +#define mmCRTC5_PIXEL_RATE_CNTL 0x0154 +#define mmCRTC8_DATA 0x00ED +#define mmCRTC8_IDX 0x00ED +#define mmCRTC_ALLOW_STOP_OFF_V_CNT 0x1BC3 +#define mmCRTC_BLACK_COLOR 0x1BA2 +#define mmCRTC_BLANK_CONTROL 0x1B9D +#define mmCRTC_BLANK_DATA_COLOR 0x1BA1 +#define mmCRTC_CONTROL 0x1B9C +#define mmCRTC_COUNT_CONTROL 0x1BA9 +#define mmCRTC_COUNT_RESET 0x1BAA +#define mmCRTC_DCFE_CLOCK_CONTROL 0x1B7C +#define mmCRTC_DOUBLE_BUFFER_CONTROL 0x1BB6 +#define mmCRTC_DTMTEST_CNTL 0x1B92 +#define mmCRTC_DTMTEST_STATUS_POSITION 0x1B93 +#define mmCRTC_FLOW_CONTROL 0x1B99 +#define mmCRTC_FORCE_COUNT_NOW_CNTL 0x1B98 +#define mmCRTC_GSL_CONTROL 0x1B7B +#define mmCRTC_GSL_VSYNC_GAP 0x1B79 +#define mmCRTC_GSL_WINDOW 0x1B7A +#define mmCRTC_H_BLANK_EARLY_NUM 0x1B7D +#define mmCRTC_H_BLANK_START_END 0x1B81 +#define mmCRTC_H_SYNC_A 0x1B82 +#define mmCRTC_H_SYNC_A_CNTL 0x1B83 +#define mmCRTC_H_SYNC_B 0x1B84 +#define mmCRTC_H_SYNC_B_CNTL 0x1B85 +#define mmCRTC_H_TOTAL 0x1B80 +#define mmCRTC_INTERLACE_CONTROL 0x1B9E +#define mmCRTC_INTERLACE_STATUS 0x1B9F +#define mmCRTC_INTERRUPT_CONTROL 0x1BB4 +#define mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1BAB +#define mmCRTC_MASTER_EN 0x1BC2 +#define mmCRTC_MVP_INBAND_CNTL_INSERT 0x1BBF +#define mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1BC0 +#define mmCRTC_MVP_STATUS 0x1BC1 +#define mmCRTC_NOM_VERT_POSITION 0x1BA5 +#define mmCRTC_OVERSCAN_COLOR 0x1BA0 +#define mmCRTC_SNAPSHOT_CONTROL 0x1BB0 +#define mmCRTC_SNAPSHOT_FRAME 0x1BB2 +#define mmCRTC_SNAPSHOT_POSITION 0x1BB1 +#define mmCRTC_SNAPSHOT_STATUS 0x1BAF +#define mmCRTC_START_LINE_CONTROL 0x1BB3 +#define mmCRTC_STATUS 0x1BA3 +#define mmCRTC_STATUS_FRAME_COUNT 0x1BA6 +#define mmCRTC_STATUS_HV_COUNT 0x1BA8 +#define mmCRTC_STATUS_POSITION 0x1BA4 +#define mmCRTC_STATUS_VF_COUNT 0x1BA7 +#define mmCRTC_STEREO_CONTROL 0x1BAE +#define mmCRTC_STEREO_FORCE_NEXT_EYE 0x1B9B +#define mmCRTC_STEREO_STATUS 0x1BAD +#define mmCRTC_TEST_DEBUG_DATA 0x1BC7 +#define mmCRTC_TEST_DEBUG_INDEX 0x1BC6 +#define mmCRTC_TEST_PATTERN_COLOR 0x1BBC +#define mmCRTC_TEST_PATTERN_CONTROL 0x1BBA +#define mmCRTC_TEST_PATTERN_PARAMETERS 0x1BBB +#define mmCRTC_TRIGA_CNTL 0x1B94 +#define mmCRTC_TRIGA_MANUAL_TRIG 0x1B95 +#define mmCRTC_TRIGB_CNTL 0x1B96 +#define mmCRTC_TRIGB_MANUAL_TRIG 0x1B97 +#define mmCRTC_UPDATE_LOCK 0x1BB5 +#define mmCRTC_VBI_END 0x1B86 +#define mmCRTC_V_BLANK_START_END 0x1B8D +#define mmCRTC_VERT_SYNC_CONTROL 0x1BAC +#define mmCRTC_VGA_PARAMETER_CAPTURE_MODE 0x1BB7 +#define mmCRTC_V_SYNC_A 0x1B8E +#define mmCRTC_V_SYNC_A_CNTL 0x1B8F +#define mmCRTC_V_SYNC_B 0x1B90 +#define mmCRTC_V_SYNC_B_CNTL 0x1B91 +#define mmCRTC_VSYNC_NOM_INT_STATUS 0x1B8C +#define mmCRTC_V_TOTAL 0x1B87 +#define mmCRTC_V_TOTAL_CONTROL 0x1B8A +#define mmCRTC_V_TOTAL_INT_STATUS 0x1B8B +#define mmCRTC_V_TOTAL_MAX 0x1B89 +#define mmCRTC_V_TOTAL_MIN 0x1B88 +#define mmCRTC_V_UPDATE_INT_STATUS 0x1BC4 +#define mmCUR_COLOR1 0x1A6C +#define mmCUR_COLOR2 0x1A6D +#define mmCUR_CONTROL 0x1A66 +#define mmCUR_HOT_SPOT 0x1A6B +#define mmCUR_POSITION 0x1A6A +#define mmCUR_REQUEST_FILTER_CNTL 0x1A99 +#define mmCUR_SIZE 0x1A68 +#define mmCUR_SURFACE_ADDRESS 0x1A67 +#define mmCUR_SURFACE_ADDRESS_HIGH 0x1A69 +#define mmCUR_UPDATE 0x1A6E +#define mmD1VGA_CONTROL 0x00CC +#define mmD2VGA_CONTROL 0x00CE +#define mmD3VGA_CONTROL 0x00F8 +#define mmD4VGA_CONTROL 0x00F9 +#define mmD5VGA_CONTROL 0x00FA +#define mmD6VGA_CONTROL 0x00FB +#define mmDAC_AUTODETECT_CONTROL 0x19EE +#define mmDAC_AUTODETECT_CONTROL2 0x19EF +#define mmDAC_AUTODETECT_CONTROL3 0x19F0 +#define mmDAC_AUTODETECT_INT_CONTROL 0x19F2 +#define mmDAC_AUTODETECT_STATUS 0x19F1 +#define mmDAC_CLK_ENABLE 0x0128 +#define mmDAC_COMPARATOR_ENABLE 0x19F7 +#define mmDAC_COMPARATOR_OUTPUT 0x19F8 +#define mmDAC_CONTROL 0x19F6 +#define mmDAC_CRC_CONTROL 0x19E7 +#define mmDAC_CRC_EN 0x19E6 +#define mmDAC_CRC_SIG_CONTROL 0x19EB +#define mmDAC_CRC_SIG_CONTROL_MASK 0x19E9 +#define mmDAC_CRC_SIG_RGB 0x19EA +#define mmDAC_CRC_SIG_RGB_MASK 0x19E8 +#define mmDAC_DATA 0x00F2 +#define mmDAC_DFT_CONFIG 0x19FA +#define mmDAC_ENABLE 0x19E4 +#define mmDAC_FIFO_STATUS 0x19FB +#define mmDAC_FORCE_DATA 0x19F4 +#define mmDAC_FORCE_OUTPUT_CNTL 0x19F3 +#define mmDAC_MACRO_CNTL_RESERVED0 0x19FC +#define mmDAC_MACRO_CNTL_RESERVED1 0x19FD +#define mmDAC_MACRO_CNTL_RESERVED2 0x19FE +#define mmDAC_MACRO_CNTL_RESERVED3 0x19FF +#define mmDAC_MASK 0x00F1 +#define mmDAC_POWERDOWN 0x19F5 +#define mmDAC_PWR_CNTL 0x19F9 +#define mmDAC_R_INDEX 0x00F1 +#define mmDAC_SOURCE_SELECT 0x19E5 +#define mmDAC_STEREOSYNC_SELECT 0x19ED +#define mmDAC_SYNC_TRISTATE_CONTROL 0x19EC +#define mmDAC_W_INDEX 0x00F2 +#define mmDC_ABM1_ACE_CNTL_MISC 0x1641 +#define mmDC_ABM1_ACE_OFFSET_SLOPE_0 0x163A +#define mmDC_ABM1_ACE_OFFSET_SLOPE_1 0x163B +#define mmDC_ABM1_ACE_OFFSET_SLOPE_2 0x163C +#define mmDC_ABM1_ACE_OFFSET_SLOPE_3 0x163D +#define mmDC_ABM1_ACE_OFFSET_SLOPE_4 0x163E +#define mmDC_ABM1_ACE_THRES_12 0x163F +#define mmDC_ABM1_ACE_THRES_34 0x1640 +#define mmDC_ABM1_BL_MASTER_LOCK 0x169C +#define mmDC_ABM1_CNTL 0x1638 +#define mmDC_ABM1_DEBUG_MISC 0x1649 +#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x1656 +#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x1659 +#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x1657 +#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x165A +#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x1658 +#define mmDC_ABM1_HGLS_REG_READ_PROGRESS 0x164A +#define mmDC_ABM1_HG_MISC_CTRL 0x164B +#define mmDC_ABM1_HG_RESULT_10 0x1664 +#define mmDC_ABM1_HG_RESULT_1 0x165B +#define mmDC_ABM1_HG_RESULT_11 0x1665 +#define mmDC_ABM1_HG_RESULT_12 0x1666 +#define mmDC_ABM1_HG_RESULT_13 0x1667 +#define mmDC_ABM1_HG_RESULT_14 0x1668 +#define mmDC_ABM1_HG_RESULT_15 0x1669 +#define mmDC_ABM1_HG_RESULT_16 0x166A +#define mmDC_ABM1_HG_RESULT_17 0x166B +#define mmDC_ABM1_HG_RESULT_18 0x166C +#define mmDC_ABM1_HG_RESULT_19 0x166D +#define mmDC_ABM1_HG_RESULT_20 0x166E +#define mmDC_ABM1_HG_RESULT_2 0x165C +#define mmDC_ABM1_HG_RESULT_21 0x166F +#define mmDC_ABM1_HG_RESULT_22 0x1670 +#define mmDC_ABM1_HG_RESULT_23 0x1671 +#define mmDC_ABM1_HG_RESULT_24 0x1672 +#define mmDC_ABM1_HG_RESULT_3 0x165D +#define mmDC_ABM1_HG_RESULT_4 0x165E +#define mmDC_ABM1_HG_RESULT_5 0x165F +#define mmDC_ABM1_HG_RESULT_6 0x1660 +#define mmDC_ABM1_HG_RESULT_7 0x1661 +#define mmDC_ABM1_HG_RESULT_8 0x1662 +#define mmDC_ABM1_HG_RESULT_9 0x1663 +#define mmDC_ABM1_HG_SAMPLE_RATE 0x1654 +#define mmDC_ABM1_IPCSC_COEFF_SEL 0x1639 +#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x164E +#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x1653 +#define mmDC_ABM1_LS_MIN_MAX_LUMA 0x164D +#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x1651 +#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x1652 +#define mmDC_ABM1_LS_OVR_SCAN_BIN 0x1650 +#define mmDC_ABM1_LS_PIXEL_COUNT 0x164F +#define mmDC_ABM1_LS_SAMPLE_RATE 0x1655 +#define mmDC_ABM1_LS_SUM_OF_LUMA 0x164C +#define mmDC_ABM1_OVERSCAN_PIXEL_VALUE 0x169B +#define mmDCCG_AUDIO_DTO0_MODULE 0x016D +#define mmDCCG_AUDIO_DTO0_PHASE 0x016C +#define mmDCCG_AUDIO_DTO1_MODULE 0x0171 +#define mmDCCG_AUDIO_DTO1_PHASE 0x0170 +#define mmDCCG_AUDIO_DTO_SOURCE 0x016B +#define mmDCCG_CAC_STATUS 0x0137 +#define mmDCCG_GATE_DISABLE_CNTL 0x0134 +#define mmDCCG_GTC_CNTL 0x0120 +#define mmDCCG_GTC_CURRENT 0x0123 +#define mmDCCG_GTC_DTO_MODULO 0x0122 +#define mmDCCG_PERFMON_CNTL 0x0133 +#define mmDCCG_PLL0_PLL_ANALOG 0x1708 +#define mmDCCG_PLL0_PLL_CNTL 0x1707 +#define mmDCCG_PLL0_PLL_DEBUG_CNTL 0x170B +#define mmDCCG_PLL0_PLL_DISPCLK_CURRENT_DTO_PHASE 0x170F +#define mmDCCG_PLL0_PLL_DISPCLK_DTO_CNTL 0x170E +#define mmDCCG_PLL0_PLL_DS_CNTL 0x1705 +#define mmDCCG_PLL0_PLL_FB_DIV 0x1701 +#define mmDCCG_PLL0_PLL_IDCLK_CNTL 0x1706 +#define mmDCCG_PLL0_PLL_POST_DIV 0x1702 +#define mmDCCG_PLL0_PLL_REF_DIV 0x1700 +#define mmDCCG_PLL0_PLL_SS_AMOUNT_DSFRAC 0x1703 +#define mmDCCG_PLL0_PLL_SS_CNTL 0x1704 +#define mmDCCG_PLL0_PLL_UNLOCK_DETECT_CNTL 0x170A +#define mmDCCG_PLL0_PLL_UPDATE_CNTL 0x170D +#define mmDCCG_PLL0_PLL_UPDATE_LOCK 0x170C +#define mmDCCG_PLL0_PLL_VREG_CNTL 0x1709 +#define mmDCCG_PLL1_PLL_ANALOG 0x1718 +#define mmDCCG_PLL1_PLL_CNTL 0x1717 +#define mmDCCG_PLL1_PLL_DEBUG_CNTL 0x171B +#define mmDCCG_PLL1_PLL_DISPCLK_CURRENT_DTO_PHASE 0x171F +#define mmDCCG_PLL1_PLL_DISPCLK_DTO_CNTL 0x171E +#define mmDCCG_PLL1_PLL_DS_CNTL 0x1715 +#define mmDCCG_PLL1_PLL_FB_DIV 0x1711 +#define mmDCCG_PLL1_PLL_IDCLK_CNTL 0x1716 +#define mmDCCG_PLL1_PLL_POST_DIV 0x1712 +#define mmDCCG_PLL1_PLL_REF_DIV 0x1710 +#define mmDCCG_PLL1_PLL_SS_AMOUNT_DSFRAC 0x1713 +#define mmDCCG_PLL1_PLL_SS_CNTL 0x1714 +#define mmDCCG_PLL1_PLL_UNLOCK_DETECT_CNTL 0x171A +#define mmDCCG_PLL1_PLL_UPDATE_CNTL 0x171D +#define mmDCCG_PLL1_PLL_UPDATE_LOCK 0x171C +#define mmDCCG_PLL1_PLL_VREG_CNTL 0x1719 +#define mmDCCG_PLL2_PLL_ANALOG 0x1728 +#define mmDCCG_PLL2_PLL_CNTL 0x1727 +#define mmDCCG_PLL2_PLL_DEBUG_CNTL 0x172B +#define mmDCCG_PLL2_PLL_DISPCLK_CURRENT_DTO_PHASE 0x172F +#define mmDCCG_PLL2_PLL_DISPCLK_DTO_CNTL 0x172E +#define mmDCCG_PLL2_PLL_DS_CNTL 0x1725 +#define mmDCCG_PLL2_PLL_FB_DIV 0x1721 +#define mmDCCG_PLL2_PLL_IDCLK_CNTL 0x1726 +#define mmDCCG_PLL2_PLL_POST_DIV 0x1722 +#define mmDCCG_PLL2_PLL_REF_DIV 0x1720 +#define mmDCCG_PLL2_PLL_SS_AMOUNT_DSFRAC 0x1723 +#define mmDCCG_PLL2_PLL_SS_CNTL 0x1724 +#define mmDCCG_PLL2_PLL_UNLOCK_DETECT_CNTL 0x172A +#define mmDCCG_PLL2_PLL_UPDATE_CNTL 0x172D +#define mmDCCG_PLL2_PLL_UPDATE_LOCK 0x172C +#define mmDCCG_PLL2_PLL_VREG_CNTL 0x1729 +#define mmDCCG_SOFT_RESET 0x015F +#define mmDCCG_TEST_CLK_SEL 0x017E +#define mmDCCG_TEST_DEBUG_DATA 0x017D +#define mmDCCG_TEST_DEBUG_INDEX 0x017C +#define mmDCCG_VPCLK_CNTL 0x031F +#define mmDCDEBUG_BUS_CLK1_SEL 0x1860 +#define mmDCDEBUG_BUS_CLK2_SEL 0x1861 +#define mmDCDEBUG_BUS_CLK3_SEL 0x1862 +#define mmDCDEBUG_BUS_CLK4_SEL 0x1863 +#define mmDCDEBUG_OUT_CNTL 0x186B +#define mmDCDEBUG_OUT_DATA 0x186E +#define mmDCDEBUG_OUT_PIN_OVERRIDE 0x186A +#define mmDC_DMCU_SCRATCH 0x1618 +#define mmDC_DVODATA_CONFIG 0x1905 +#define mmDCFE0_SOFT_RESET 0x0158 +#define mmDCFE1_SOFT_RESET 0x0159 +#define mmDCFE2_SOFT_RESET 0x015A +#define mmDCFE3_SOFT_RESET 0x015B +#define mmDCFE4_SOFT_RESET 0x015C +#define mmDCFE5_SOFT_RESET 0x015D +#define mmDCFE_DBG_SEL 0x1B7E +#define mmDCFE_MEM_LIGHT_SLEEP_CNTL 0x1B7F +#define mmDC_GENERICA 0x1900 +#define mmDC_GENERICB 0x1901 +#define mmDC_GPIO_DDC1_A 0x194D +#define mmDC_GPIO_DDC1_EN 0x194E +#define mmDC_GPIO_DDC1_MASK 0x194C +#define mmDC_GPIO_DDC1_Y 0x194F +#define mmDC_GPIO_DDC2_A 0x1951 +#define mmDC_GPIO_DDC2_EN 0x1952 +#define mmDC_GPIO_DDC2_MASK 0x1950 +#define mmDC_GPIO_DDC2_Y 0x1953 +#define mmDC_GPIO_DDC3_A 0x1955 +#define mmDC_GPIO_DDC3_EN 0x1956 +#define mmDC_GPIO_DDC3_MASK 0x1954 +#define mmDC_GPIO_DDC3_Y 0x1957 +#define mmDC_GPIO_DDC4_A 0x1959 +#define mmDC_GPIO_DDC4_EN 0x195A +#define mmDC_GPIO_DDC4_MASK 0x1958 +#define mmDC_GPIO_DDC4_Y 0x195B +#define mmDC_GPIO_DDC5_A 0x195D +#define mmDC_GPIO_DDC5_EN 0x195E +#define mmDC_GPIO_DDC5_MASK 0x195C +#define mmDC_GPIO_DDC5_Y 0x195F +#define mmDC_GPIO_DDC6_A 0x1961 +#define mmDC_GPIO_DDC6_EN 0x1962 +#define mmDC_GPIO_DDC6_MASK 0x1960 +#define mmDC_GPIO_DDC6_Y 0x1963 +#define mmDC_GPIO_DDCVGA_A 0x1971 +#define mmDC_GPIO_DDCVGA_EN 0x1972 +#define mmDC_GPIO_DDCVGA_MASK 0x1970 +#define mmDC_GPIO_DDCVGA_Y 0x1973 +#define mmDC_GPIO_DEBUG 0x1904 +#define mmDC_GPIO_DVODATA_A 0x1949 +#define mmDC_GPIO_DVODATA_EN 0x194A +#define mmDC_GPIO_DVODATA_MASK 0x1948 +#define mmDC_GPIO_DVODATA_Y 0x194B +#define mmDC_GPIO_GENERIC_A 0x1945 +#define mmDC_GPIO_GENERIC_EN 0x1946 +#define mmDC_GPIO_GENERIC_MASK 0x1944 +#define mmDC_GPIO_GENERIC_Y 0x1947 +#define mmDC_GPIO_GENLK_A 0x1969 +#define mmDC_GPIO_GENLK_EN 0x196A +#define mmDC_GPIO_GENLK_MASK 0x1968 +#define mmDC_GPIO_GENLK_Y 0x196B +#define mmDC_GPIO_HPD_A 0x196D +#define mmDC_GPIO_HPD_EN 0x196E +#define mmDC_GPIO_HPD_MASK 0x196C +#define mmDC_GPIO_HPD_Y 0x196F +#define mmDC_GPIO_I2CPAD_A 0x1975 +#define mmDC_GPIO_I2CPAD_EN 0x1976 +#define mmDC_GPIO_I2CPAD_MASK 0x1974 +#define mmDC_GPIO_I2CPAD_STRENGTH 0x197A +#define mmDC_GPIO_I2CPAD_Y 0x1977 +#define mmDC_GPIO_PAD_STRENGTH_1 0x1978 +#define mmDC_GPIO_PAD_STRENGTH_2 0x1979 +#define mmDC_GPIO_PWRSEQ_A 0x1941 +#define mmDC_GPIO_PWRSEQ_EN 0x1942 +#define mmDC_GPIO_PWRSEQ_MASK 0x1940 +#define mmDC_GPIO_PWRSEQ_Y 0x1943 +#define mmDC_GPIO_SYNCA_A 0x1965 +#define mmDC_GPIO_SYNCA_EN 0x1966 +#define mmDC_GPIO_SYNCA_MASK 0x1964 +#define mmDC_GPIO_SYNCA_Y 0x1967 +#define mmDC_GPU_TIMER_READ 0x1929 +#define mmDC_GPU_TIMER_READ_CNTL 0x192A +#define mmDC_GPU_TIMER_START_POSITION_P_FLIP 0x1928 +#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x1927 +#define mmDC_HPD1_CONTROL 0x1809 +#define mmDC_HPD1_FAST_TRAIN_CNTL 0x1864 +#define mmDC_HPD1_INT_CONTROL 0x1808 +#define mmDC_HPD1_INT_STATUS 0x1807 +#define mmDC_HPD1_TOGGLE_FILT_CNTL 0x18BC +#define mmDC_HPD2_CONTROL 0x180C +#define mmDC_HPD2_FAST_TRAIN_CNTL 0x1865 +#define mmDC_HPD2_INT_CONTROL 0x180B +#define mmDC_HPD2_INT_STATUS 0x180A +#define mmDC_HPD2_TOGGLE_FILT_CNTL 0x18BD +#define mmDC_HPD3_CONTROL 0x180F +#define mmDC_HPD3_FAST_TRAIN_CNTL 0x1866 +#define mmDC_HPD3_INT_CONTROL 0x180E +#define mmDC_HPD3_INT_STATUS 0x180D +#define mmDC_HPD3_TOGGLE_FILT_CNTL 0x18BE +#define mmDC_HPD4_CONTROL 0x1812 +#define mmDC_HPD4_FAST_TRAIN_CNTL 0x1867 +#define mmDC_HPD4_INT_CONTROL 0x1811 +#define mmDC_HPD4_INT_STATUS 0x1810 +#define mmDC_HPD4_TOGGLE_FILT_CNTL 0x18FC +#define mmDC_HPD5_CONTROL 0x1815 +#define mmDC_HPD5_FAST_TRAIN_CNTL 0x1868 +#define mmDC_HPD5_INT_CONTROL 0x1814 +#define mmDC_HPD5_INT_STATUS 0x1813 +#define mmDC_HPD5_TOGGLE_FILT_CNTL 0x18FD +#define mmDC_HPD6_CONTROL 0x1818 +#define mmDC_HPD6_FAST_TRAIN_CNTL 0x1869 +#define mmDC_HPD6_INT_CONTROL 0x1817 +#define mmDC_HPD6_INT_STATUS 0x1816 +#define mmDC_HPD6_TOGGLE_FILT_CNTL 0x18FE +#define mmDC_I2C_ARBITRATION 0x181A +#define mmDC_I2C_CONTROL 0x1819 +#define mmDC_I2C_DATA 0x1833 +#define mmDC_I2C_DDC1_HW_STATUS 0x181D +#define mmDC_I2C_DDC1_SETUP 0x1824 +#define mmDC_I2C_DDC1_SPEED 0x1823 +#define mmDC_I2C_DDC2_HW_STATUS 0x181E +#define mmDC_I2C_DDC2_SETUP 0x1826 +#define mmDC_I2C_DDC2_SPEED 0x1825 +#define mmDC_I2C_DDC3_HW_STATUS 0x181F +#define mmDC_I2C_DDC3_SETUP 0x1828 +#define mmDC_I2C_DDC3_SPEED 0x1827 +#define mmDC_I2C_DDC4_HW_STATUS 0x1820 +#define mmDC_I2C_DDC4_SETUP 0x182A +#define mmDC_I2C_DDC4_SPEED 0x1829 +#define mmDC_I2C_DDC5_HW_STATUS 0x1821 +#define mmDC_I2C_DDC5_SETUP 0x182C +#define mmDC_I2C_DDC5_SPEED 0x182B +#define mmDC_I2C_DDC6_HW_STATUS 0x1822 +#define mmDC_I2C_DDC6_SETUP 0x182E +#define mmDC_I2C_DDC6_SPEED 0x182D +#define mmDC_I2C_DDCVGA_HW_STATUS 0x1855 +#define mmDC_I2C_DDCVGA_SETUP 0x1857 +#define mmDC_I2C_DDCVGA_SPEED 0x1856 +#define mmDC_I2C_EDID_DETECT_CTRL 0x186F +#define mmDC_I2C_INTERRUPT_CONTROL 0x181B +#define mmDC_I2C_SW_STATUS 0x181C +#define mmDC_I2C_TRANSACTION0 0x182F +#define mmDC_I2C_TRANSACTION1 0x1830 +#define mmDC_I2C_TRANSACTION2 0x1831 +#define mmDC_I2C_TRANSACTION3 0x1832 +#define mmDCI_CLK_CNTL 0x031E +#define mmDCI_CLK_RAMP_CNTL 0x0324 +#define mmDCI_DEBUG_CONFIG 0x0323 +#define mmDCI_MEM_PWR_CNTL 0x0326 +#define mmDCI_MEM_PWR_STATE 0x031B +#define mmDCI_MEM_PWR_STATE2 0x0322 +#define mmDCIO_DEBUG 0x192E +#define mmDCIO_GSL0_CNTL 0x1924 +#define mmDCIO_GSL1_CNTL 0x1925 +#define mmDCIO_GSL2_CNTL 0x1926 +#define mmDCIO_GSL_GENLK_PAD_CNTL 0x1922 +#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x1923 +#define mmDCIO_IMPCAL_CNTL_AB 0x190D +#define mmDCIO_IMPCAL_CNTL_CD 0x1911 +#define mmDCIO_IMPCAL_CNTL_EF 0x1915 +#define mmDCIO_TEST_DEBUG_DATA 0x1930 +#define mmDCIO_TEST_DEBUG_INDEX 0x192F +#define mmDCIO_UNIPHY0_UNIPHY_ANG_BIST_CNTL 0x198C +#define mmDCIO_UNIPHY0_UNIPHY_CHANNEL_XBAR_CNTL 0x198E +#define mmDCIO_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION 0x198A +#define mmDCIO_UNIPHY0_UNIPHY_LINK_CNTL 0x198D +#define mmDCIO_UNIPHY0_UNIPHY_PLL_CONTROL1 0x1986 +#define mmDCIO_UNIPHY0_UNIPHY_PLL_CONTROL2 0x1987 +#define mmDCIO_UNIPHY0_UNIPHY_PLL_FBDIV 0x1985 +#define mmDCIO_UNIPHY0_UNIPHY_PLL_SS_CNTL 0x1989 +#define mmDCIO_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE 0x1988 +#define mmDCIO_UNIPHY0_UNIPHY_POWER_CONTROL 0x1984 +#define mmDCIO_UNIPHY0_UNIPHY_REG_TEST_OUTPUT 0x198B +#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL1 0x1980 +#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL2 0x1981 +#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL3 0x1982 +#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL4 0x1983 +#define mmDCIO_UNIPHY1_UNIPHY_ANG_BIST_CNTL 0x199C +#define mmDCIO_UNIPHY1_UNIPHY_CHANNEL_XBAR_CNTL 0x199E +#define mmDCIO_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION 0x199A +#define mmDCIO_UNIPHY1_UNIPHY_LINK_CNTL 0x199D +#define mmDCIO_UNIPHY1_UNIPHY_PLL_CONTROL1 0x1996 +#define mmDCIO_UNIPHY1_UNIPHY_PLL_CONTROL2 0x1997 +#define mmDCIO_UNIPHY1_UNIPHY_PLL_FBDIV 0x1995 +#define mmDCIO_UNIPHY1_UNIPHY_PLL_SS_CNTL 0x1999 +#define mmDCIO_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE 0x1998 +#define mmDCIO_UNIPHY1_UNIPHY_POWER_CONTROL 0x1994 +#define mmDCIO_UNIPHY1_UNIPHY_REG_TEST_OUTPUT 0x199B +#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL1 0x1990 +#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL2 0x1991 +#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL3 0x1992 +#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL4 0x1993 +#define mmDCIO_UNIPHY2_UNIPHY_ANG_BIST_CNTL 0x19AC +#define mmDCIO_UNIPHY2_UNIPHY_CHANNEL_XBAR_CNTL 0x19AE +#define mmDCIO_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION 0x19AA +#define mmDCIO_UNIPHY2_UNIPHY_LINK_CNTL 0x19AD +#define mmDCIO_UNIPHY2_UNIPHY_PLL_CONTROL1 0x19A6 +#define mmDCIO_UNIPHY2_UNIPHY_PLL_CONTROL2 0x19A7 +#define mmDCIO_UNIPHY2_UNIPHY_PLL_FBDIV 0x19A5 +#define mmDCIO_UNIPHY2_UNIPHY_PLL_SS_CNTL 0x19A9 +#define mmDCIO_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE 0x19A8 +#define mmDCIO_UNIPHY2_UNIPHY_POWER_CONTROL 0x19A4 +#define mmDCIO_UNIPHY2_UNIPHY_REG_TEST_OUTPUT 0x19AB +#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL1 0x19A0 +#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL2 0x19A1 +#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL3 0x19A2 +#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL4 0x19A3 +#define mmDCIO_UNIPHY3_UNIPHY_ANG_BIST_CNTL 0x19BC +#define mmDCIO_UNIPHY3_UNIPHY_CHANNEL_XBAR_CNTL 0x19BE +#define mmDCIO_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION 0x19BA +#define mmDCIO_UNIPHY3_UNIPHY_LINK_CNTL 0x19BD +#define mmDCIO_UNIPHY3_UNIPHY_PLL_CONTROL1 0x19B6 +#define mmDCIO_UNIPHY3_UNIPHY_PLL_CONTROL2 0x19B7 +#define mmDCIO_UNIPHY3_UNIPHY_PLL_FBDIV 0x19B5 +#define mmDCIO_UNIPHY3_UNIPHY_PLL_SS_CNTL 0x19B9 +#define mmDCIO_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE 0x19B8 +#define mmDCIO_UNIPHY3_UNIPHY_POWER_CONTROL 0x19B4 +#define mmDCIO_UNIPHY3_UNIPHY_REG_TEST_OUTPUT 0x19BB +#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL1 0x19B0 +#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL2 0x19B1 +#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL3 0x19B2 +#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL4 0x19B3 +#define mmDCIO_UNIPHY4_UNIPHY_ANG_BIST_CNTL 0x19CC +#define mmDCIO_UNIPHY4_UNIPHY_CHANNEL_XBAR_CNTL 0x19CE +#define mmDCIO_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION 0x19CA +#define mmDCIO_UNIPHY4_UNIPHY_LINK_CNTL 0x19CD +#define mmDCIO_UNIPHY4_UNIPHY_PLL_CONTROL1 0x19C6 +#define mmDCIO_UNIPHY4_UNIPHY_PLL_CONTROL2 0x19C7 +#define mmDCIO_UNIPHY4_UNIPHY_PLL_FBDIV 0x19C5 +#define mmDCIO_UNIPHY4_UNIPHY_PLL_SS_CNTL 0x19C9 +#define mmDCIO_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE 0x19C8 +#define mmDCIO_UNIPHY4_UNIPHY_POWER_CONTROL 0x19C4 +#define mmDCIO_UNIPHY4_UNIPHY_REG_TEST_OUTPUT 0x19CB +#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL1 0x19C0 +#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL2 0x19C1 +#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL3 0x19C2 +#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL4 0x19C3 +#define mmDCIO_UNIPHY5_UNIPHY_ANG_BIST_CNTL 0x19DC +#define mmDCIO_UNIPHY5_UNIPHY_CHANNEL_XBAR_CNTL 0x19DE +#define mmDCIO_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION 0x19DA +#define mmDCIO_UNIPHY5_UNIPHY_LINK_CNTL 0x19DD +#define mmDCIO_UNIPHY5_UNIPHY_PLL_CONTROL1 0x19D6 +#define mmDCIO_UNIPHY5_UNIPHY_PLL_CONTROL2 0x19D7 +#define mmDCIO_UNIPHY5_UNIPHY_PLL_FBDIV 0x19D5 +#define mmDCIO_UNIPHY5_UNIPHY_PLL_SS_CNTL 0x19D9 +#define mmDCIO_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE 0x19D8 +#define mmDCIO_UNIPHY5_UNIPHY_POWER_CONTROL 0x19D4 +#define mmDCIO_UNIPHY5_UNIPHY_REG_TEST_OUTPUT 0x19DB +#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL1 0x19D0 +#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL2 0x19D1 +#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL3 0x19D2 +#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL4 0x19D3 +#define mmDCI_SOFT_RESET 0x015E +#define mmDCI_TEST_DEBUG_DATA 0x0321 +#define mmDCI_TEST_DEBUG_INDEX 0x0320 +#define mmDC_LUT_30_COLOR 0x1A7C +#define mmDC_LUT_AUTOFILL 0x1A7F +#define mmDC_LUT_BLACK_OFFSET_BLUE 0x1A81 +#define mmDC_LUT_BLACK_OFFSET_GREEN 0x1A82 +#define mmDC_LUT_BLACK_OFFSET_RED 0x1A83 +#define mmDC_LUT_CONTROL 0x1A80 +#define mmDC_LUT_PWL_DATA 0x1A7B +#define mmDC_LUT_RW_INDEX 0x1A79 +#define mmDC_LUT_RW_MODE 0x1A78 +#define mmDC_LUT_SEQ_COLOR 0x1A7A +#define mmDC_LUT_VGA_ACCESS_ENABLE 0x1A7D +#define mmDC_LUT_WHITE_OFFSET_BLUE 0x1A84 +#define mmDC_LUT_WHITE_OFFSET_GREEN 0x1A85 +#define mmDC_LUT_WHITE_OFFSET_RED 0x1A86 +#define mmDC_LUT_WRITE_EN_MASK 0x1A7E +#define mmDC_MVP_LB_CONTROL 0x1ADB +#define mmDCO_CLK_CNTL 0x192B +#define mmDCO_CLK_RAMP_CNTL 0x192C +#define mmDCO_LIGHT_SLEEP_DIS 0x1907 +#define mmDCO_MEM_POWER_STATE 0x1906 +#define mmDCO_SOFT_RESET 0x0167 +#define mmDCP0_COMM_MATRIXA_TRANS_C11_C12 0x1A43 +#define mmDCP0_COMM_MATRIXA_TRANS_C13_C14 0x1A44 +#define mmDCP0_COMM_MATRIXA_TRANS_C21_C22 0x1A45 +#define mmDCP0_COMM_MATRIXA_TRANS_C23_C24 0x1A46 +#define mmDCP0_COMM_MATRIXA_TRANS_C31_C32 0x1A47 +#define mmDCP0_COMM_MATRIXA_TRANS_C33_C34 0x1A48 +#define mmDCP0_COMM_MATRIXB_TRANS_C11_C12 0x1A49 +#define mmDCP0_COMM_MATRIXB_TRANS_C13_C14 0x1A4A +#define mmDCP0_COMM_MATRIXB_TRANS_C21_C22 0x1A4B +#define mmDCP0_COMM_MATRIXB_TRANS_C23_C24 0x1A4C +#define mmDCP0_COMM_MATRIXB_TRANS_C31_C32 0x1A4D +#define mmDCP0_COMM_MATRIXB_TRANS_C33_C34 0x1A4E +#define mmDCP0_CUR_COLOR1 0x1A6C +#define mmDCP0_CUR_COLOR2 0x1A6D +#define mmDCP0_CUR_CONTROL 0x1A66 +#define mmDCP0_CUR_HOT_SPOT 0x1A6B +#define mmDCP0_CUR_POSITION 0x1A6A +#define mmDCP0_CUR_REQUEST_FILTER_CNTL 0x1A99 +#define mmDCP0_CUR_SIZE 0x1A68 +#define mmDCP0_CUR_SURFACE_ADDRESS 0x1A67 +#define mmDCP0_CUR_SURFACE_ADDRESS_HIGH 0x1A69 +#define mmDCP0_CUR_UPDATE 0x1A6E +#define mmDCP0_DC_LUT_30_COLOR 0x1A7C +#define mmDCP0_DC_LUT_AUTOFILL 0x1A7F +#define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE 0x1A81 +#define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN 0x1A82 +#define mmDCP0_DC_LUT_BLACK_OFFSET_RED 0x1A83 +#define mmDCP0_DC_LUT_CONTROL 0x1A80 +#define mmDCP0_DC_LUT_PWL_DATA 0x1A7B +#define mmDCP0_DC_LUT_RW_INDEX 0x1A79 +#define mmDCP0_DC_LUT_RW_MODE 0x1A78 +#define mmDCP0_DC_LUT_SEQ_COLOR 0x1A7A +#define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE 0x1A7D +#define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE 0x1A84 +#define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN 0x1A85 +#define mmDCP0_DC_LUT_WHITE_OFFSET_RED 0x1A86 +#define mmDCP0_DC_LUT_WRITE_EN_MASK 0x1A7E +#define mmDCP0_DCP_CRC_CONTROL 0x1A87 +#define mmDCP0_DCP_CRC_CURRENT 0x1A89 +#define mmDCP0_DCP_CRC_LAST 0x1A8B +#define mmDCP0_DCP_CRC_MASK 0x1A88 +#define mmDCP0_DCP_DEBUG 0x1A8D +#define mmDCP0_DCP_DEBUG2 0x1A98 +#define mmDCP0_DCP_FP_CONVERTED_FIELD 0x1A65 +#define mmDCP0_DCP_GSL_CONTROL 0x1A90 +#define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1A91 +#define mmDCP0_DCP_RANDOM_SEEDS 0x1A61 +#define mmDCP0_DCP_SPATIAL_DITHER_CNTL 0x1A60 +#define mmDCP0_DCP_TEST_DEBUG_DATA 0x1A96 +#define mmDCP0_DCP_TEST_DEBUG_INDEX 0x1A95 +#define mmDCP0_DEGAMMA_CONTROL 0x1A58 +#define mmDCP0_DENORM_CONTROL 0x1A50 +#define mmDCP0_GAMUT_REMAP_C11_C12 0x1A5A +#define mmDCP0_GAMUT_REMAP_C13_C14 0x1A5B +#define mmDCP0_GAMUT_REMAP_C21_C22 0x1A5C +#define mmDCP0_GAMUT_REMAP_C23_C24 0x1A5D +#define mmDCP0_GAMUT_REMAP_C31_C32 0x1A5E +#define mmDCP0_GAMUT_REMAP_C33_C34 0x1A5F +#define mmDCP0_GAMUT_REMAP_CONTROL 0x1A59 +#define mmDCP0_GRPH_COMPRESS_PITCH 0x1A1A +#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS 0x1A19 +#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1A1B +#define mmDCP0_GRPH_CONTROL 0x1A01 +#define mmDCP0_GRPH_DFQ_CONTROL 0x1A14 +#define mmDCP0_GRPH_DFQ_STATUS 0x1A15 +#define mmDCP0_GRPH_ENABLE 0x1A00 +#define mmDCP0_GRPH_FLIP_CONTROL 0x1A12 +#define mmDCP0_GRPH_INTERRUPT_CONTROL 0x1A17 +#define mmDCP0_GRPH_INTERRUPT_STATUS 0x1A16 +#define mmDCP0_GRPH_LUT_10BIT_BYPASS 0x1A02 +#define mmDCP0_GRPH_PITCH 0x1A06 +#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS 0x1A04 +#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1A07 +#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS 0x1A05 +#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1A08 +#define mmDCP0_GRPH_STEREOSYNC_FLIP 0x1A97 +#define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1A18 +#define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE 0x1A13 +#define mmDCP0_GRPH_SURFACE_OFFSET_X 0x1A09 +#define mmDCP0_GRPH_SURFACE_OFFSET_Y 0x1A0A +#define mmDCP0_GRPH_SWAP_CNTL 0x1A03 +#define mmDCP0_GRPH_UPDATE 0x1A11 +#define mmDCP0_GRPH_X_END 0x1A0D +#define mmDCP0_GRPH_X_START 0x1A0B +#define mmDCP0_GRPH_Y_END 0x1A0E +#define mmDCP0_GRPH_Y_START 0x1A0C +#define mmDCP0_INPUT_CSC_C11_C12 0x1A36 +#define mmDCP0_INPUT_CSC_C13_C14 0x1A37 +#define mmDCP0_INPUT_CSC_C21_C22 0x1A38 +#define mmDCP0_INPUT_CSC_C23_C24 0x1A39 +#define mmDCP0_INPUT_CSC_C31_C32 0x1A3A +#define mmDCP0_INPUT_CSC_C33_C34 0x1A3B +#define mmDCP0_INPUT_CSC_CONTROL 0x1A35 +#define mmDCP0_INPUT_GAMMA_CONTROL 0x1A10 +#define mmDCP0_KEY_CONTROL 0x1A53 +#define mmDCP0_KEY_RANGE_ALPHA 0x1A54 +#define mmDCP0_KEY_RANGE_BLUE 0x1A57 +#define mmDCP0_KEY_RANGE_GREEN 0x1A56 +#define mmDCP0_KEY_RANGE_RED 0x1A55 +#define mmDCP0_OUTPUT_CSC_C11_C12 0x1A3D +#define mmDCP0_OUTPUT_CSC_C13_C14 0x1A3E +#define mmDCP0_OUTPUT_CSC_C21_C22 0x1A3F +#define mmDCP0_OUTPUT_CSC_C23_C24 0x1A40 +#define mmDCP0_OUTPUT_CSC_C31_C32 0x1A41 +#define mmDCP0_OUTPUT_CSC_C33_C34 0x1A42 +#define mmDCP0_OUTPUT_CSC_CONTROL 0x1A3C +#define mmDCP0_OUT_ROUND_CONTROL 0x1A51 +#define mmDCP0_OVL_CONTROL1 0x1A1D +#define mmDCP0_OVL_CONTROL2 0x1A1E +#define mmDCP0_OVL_DFQ_CONTROL 0x1A29 +#define mmDCP0_OVL_DFQ_STATUS 0x1A2A +#define mmDCP0_OVL_ENABLE 0x1A1C +#define mmDCP0_OVL_END 0x1A26 +#define mmDCP0_OVL_PITCH 0x1A21 +#define mmDCP0_OVLSCL_EDGE_PIXEL_CNTL 0x1A2C +#define mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS 0x1A92 +#define mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1A94 +#define mmDCP0_OVL_START 0x1A25 +#define mmDCP0_OVL_STEREOSYNC_FLIP 0x1A93 +#define mmDCP0_OVL_SURFACE_ADDRESS 0x1A20 +#define mmDCP0_OVL_SURFACE_ADDRESS_HIGH 0x1A22 +#define mmDCP0_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x1A2B +#define mmDCP0_OVL_SURFACE_ADDRESS_INUSE 0x1A28 +#define mmDCP0_OVL_SURFACE_OFFSET_X 0x1A23 +#define mmDCP0_OVL_SURFACE_OFFSET_Y 0x1A24 +#define mmDCP0_OVL_SWAP_CNTL 0x1A1F +#define mmDCP0_OVL_UPDATE 0x1A27 +#define mmDCP0_PRESCALE_GRPH_CONTROL 0x1A2D +#define mmDCP0_PRESCALE_OVL_CONTROL 0x1A31 +#define mmDCP0_PRESCALE_VALUES_GRPH_B 0x1A30 +#define mmDCP0_PRESCALE_VALUES_GRPH_G 0x1A2F +#define mmDCP0_PRESCALE_VALUES_GRPH_R 0x1A2E +#define mmDCP0_PRESCALE_VALUES_OVL_CB 0x1A32 +#define mmDCP0_PRESCALE_VALUES_OVL_CR 0x1A34 +#define mmDCP0_PRESCALE_VALUES_OVL_Y 0x1A33 +#define mmDCP0_REGAMMA_CNTLA_END_CNTL1 0x1AA6 +#define mmDCP0_REGAMMA_CNTLA_END_CNTL2 0x1AA7 +#define mmDCP0_REGAMMA_CNTLA_REGION_0_1 0x1AA8 +#define mmDCP0_REGAMMA_CNTLA_REGION_10_11 0x1AAD +#define mmDCP0_REGAMMA_CNTLA_REGION_12_13 0x1AAE +#define mmDCP0_REGAMMA_CNTLA_REGION_14_15 0x1AAF +#define mmDCP0_REGAMMA_CNTLA_REGION_2_3 0x1AA9 +#define mmDCP0_REGAMMA_CNTLA_REGION_4_5 0x1AAA +#define mmDCP0_REGAMMA_CNTLA_REGION_6_7 0x1AAB +#define mmDCP0_REGAMMA_CNTLA_REGION_8_9 0x1AAC +#define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL 0x1AA5 +#define mmDCP0_REGAMMA_CNTLA_START_CNTL 0x1AA4 +#define mmDCP0_REGAMMA_CNTLB_END_CNTL1 0x1AB2 +#define mmDCP0_REGAMMA_CNTLB_END_CNTL2 0x1AB3 +#define mmDCP0_REGAMMA_CNTLB_REGION_0_1 0x1AB4 +#define mmDCP0_REGAMMA_CNTLB_REGION_10_11 0x1AB9 +#define mmDCP0_REGAMMA_CNTLB_REGION_12_13 0x1ABA +#define mmDCP0_REGAMMA_CNTLB_REGION_14_15 0x1ABB +#define mmDCP0_REGAMMA_CNTLB_REGION_2_3 0x1AB5 +#define mmDCP0_REGAMMA_CNTLB_REGION_4_5 0x1AB6 +#define mmDCP0_REGAMMA_CNTLB_REGION_6_7 0x1AB7 +#define mmDCP0_REGAMMA_CNTLB_REGION_8_9 0x1AB8 +#define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL 0x1AB1 +#define mmDCP0_REGAMMA_CNTLB_START_CNTL 0x1AB0 +#define mmDCP0_REGAMMA_CONTROL 0x1AA0 +#define mmDCP0_REGAMMA_LUT_DATA 0x1AA2 +#define mmDCP0_REGAMMA_LUT_INDEX 0x1AA1 +#define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK 0x1AA3 +#define mmDCP1_COMM_MATRIXA_TRANS_C11_C12 0x1D43 +#define mmDCP1_COMM_MATRIXA_TRANS_C13_C14 0x1D44 +#define mmDCP1_COMM_MATRIXA_TRANS_C21_C22 0x1D45 +#define mmDCP1_COMM_MATRIXA_TRANS_C23_C24 0x1D46 +#define mmDCP1_COMM_MATRIXA_TRANS_C31_C32 0x1D47 +#define mmDCP1_COMM_MATRIXA_TRANS_C33_C34 0x1D48 +#define mmDCP1_COMM_MATRIXB_TRANS_C11_C12 0x1D49 +#define mmDCP1_COMM_MATRIXB_TRANS_C13_C14 0x1D4A +#define mmDCP1_COMM_MATRIXB_TRANS_C21_C22 0x1D4B +#define mmDCP1_COMM_MATRIXB_TRANS_C23_C24 0x1D4C +#define mmDCP1_COMM_MATRIXB_TRANS_C31_C32 0x1D4D +#define mmDCP1_COMM_MATRIXB_TRANS_C33_C34 0x1D4E +#define mmDCP1_CUR_COLOR1 0x1D6C +#define mmDCP1_CUR_COLOR2 0x1D6D +#define mmDCP1_CUR_CONTROL 0x1D66 +#define mmDCP1_CUR_HOT_SPOT 0x1D6B +#define mmDCP1_CUR_POSITION 0x1D6A +#define mmDCP1_CUR_REQUEST_FILTER_CNTL 0x1D99 +#define mmDCP1_CUR_SIZE 0x1D68 +#define mmDCP1_CUR_SURFACE_ADDRESS 0x1D67 +#define mmDCP1_CUR_SURFACE_ADDRESS_HIGH 0x1D69 +#define mmDCP1_CUR_UPDATE 0x1D6E +#define mmDCP1_DC_LUT_30_COLOR 0x1D7C +#define mmDCP1_DC_LUT_AUTOFILL 0x1D7F +#define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE 0x1D81 +#define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN 0x1D82 +#define mmDCP1_DC_LUT_BLACK_OFFSET_RED 0x1D83 +#define mmDCP1_DC_LUT_CONTROL 0x1D80 +#define mmDCP1_DC_LUT_PWL_DATA 0x1D7B +#define mmDCP1_DC_LUT_RW_INDEX 0x1D79 +#define mmDCP1_DC_LUT_RW_MODE 0x1D78 +#define mmDCP1_DC_LUT_SEQ_COLOR 0x1D7A +#define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE 0x1D7D +#define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE 0x1D84 +#define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN 0x1D85 +#define mmDCP1_DC_LUT_WHITE_OFFSET_RED 0x1D86 +#define mmDCP1_DC_LUT_WRITE_EN_MASK 0x1D7E +#define mmDCP1_DCP_CRC_CONTROL 0x1D87 +#define mmDCP1_DCP_CRC_CURRENT 0x1D89 +#define mmDCP1_DCP_CRC_LAST 0x1D8B +#define mmDCP1_DCP_CRC_MASK 0x1D88 +#define mmDCP1_DCP_DEBUG 0x1D8D +#define mmDCP1_DCP_DEBUG2 0x1D98 +#define mmDCP1_DCP_FP_CONVERTED_FIELD 0x1D65 +#define mmDCP1_DCP_GSL_CONTROL 0x1D90 +#define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1D91 +#define mmDCP1_DCP_RANDOM_SEEDS 0x1D61 +#define mmDCP1_DCP_SPATIAL_DITHER_CNTL 0x1D60 +#define mmDCP1_DCP_TEST_DEBUG_DATA 0x1D96 +#define mmDCP1_DCP_TEST_DEBUG_INDEX 0x1D95 +#define mmDCP1_DEGAMMA_CONTROL 0x1D58 +#define mmDCP1_DENORM_CONTROL 0x1D50 +#define mmDCP1_GAMUT_REMAP_C11_C12 0x1D5A +#define mmDCP1_GAMUT_REMAP_C13_C14 0x1D5B +#define mmDCP1_GAMUT_REMAP_C21_C22 0x1D5C +#define mmDCP1_GAMUT_REMAP_C23_C24 0x1D5D +#define mmDCP1_GAMUT_REMAP_C31_C32 0x1D5E +#define mmDCP1_GAMUT_REMAP_C33_C34 0x1D5F +#define mmDCP1_GAMUT_REMAP_CONTROL 0x1D59 +#define mmDCP1_GRPH_COMPRESS_PITCH 0x1D1A +#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS 0x1D19 +#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1D1B +#define mmDCP1_GRPH_CONTROL 0x1D01 +#define mmDCP1_GRPH_DFQ_CONTROL 0x1D14 +#define mmDCP1_GRPH_DFQ_STATUS 0x1D15 +#define mmDCP1_GRPH_ENABLE 0x1D00 +#define mmDCP1_GRPH_FLIP_CONTROL 0x1D12 +#define mmDCP1_GRPH_INTERRUPT_CONTROL 0x1D17 +#define mmDCP1_GRPH_INTERRUPT_STATUS 0x1D16 +#define mmDCP1_GRPH_LUT_10BIT_BYPASS 0x1D02 +#define mmDCP1_GRPH_PITCH 0x1D06 +#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS 0x1D04 +#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1D07 +#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS 0x1D05 +#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1D08 +#define mmDCP1_GRPH_STEREOSYNC_FLIP 0x1D97 +#define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1D18 +#define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE 0x1D13 +#define mmDCP1_GRPH_SURFACE_OFFSET_X 0x1D09 +#define mmDCP1_GRPH_SURFACE_OFFSET_Y 0x1D0A +#define mmDCP1_GRPH_SWAP_CNTL 0x1D03 +#define mmDCP1_GRPH_UPDATE 0x1D11 +#define mmDCP1_GRPH_X_END 0x1D0D +#define mmDCP1_GRPH_X_START 0x1D0B +#define mmDCP1_GRPH_Y_END 0x1D0E +#define mmDCP1_GRPH_Y_START 0x1D0C +#define mmDCP1_INPUT_CSC_C11_C12 0x1D36 +#define mmDCP1_INPUT_CSC_C13_C14 0x1D37 +#define mmDCP1_INPUT_CSC_C21_C22 0x1D38 +#define mmDCP1_INPUT_CSC_C23_C24 0x1D39 +#define mmDCP1_INPUT_CSC_C31_C32 0x1D3A +#define mmDCP1_INPUT_CSC_C33_C34 0x1D3B +#define mmDCP1_INPUT_CSC_CONTROL 0x1D35 +#define mmDCP1_INPUT_GAMMA_CONTROL 0x1D10 +#define mmDCP1_KEY_CONTROL 0x1D53 +#define mmDCP1_KEY_RANGE_ALPHA 0x1D54 +#define mmDCP1_KEY_RANGE_BLUE 0x1D57 +#define mmDCP1_KEY_RANGE_GREEN 0x1D56 +#define mmDCP1_KEY_RANGE_RED 0x1D55 +#define mmDCP1_OUTPUT_CSC_C11_C12 0x1D3D +#define mmDCP1_OUTPUT_CSC_C13_C14 0x1D3E +#define mmDCP1_OUTPUT_CSC_C21_C22 0x1D3F +#define mmDCP1_OUTPUT_CSC_C23_C24 0x1D40 +#define mmDCP1_OUTPUT_CSC_C31_C32 0x1D41 +#define mmDCP1_OUTPUT_CSC_C33_C34 0x1D42 +#define mmDCP1_OUTPUT_CSC_CONTROL 0x1D3C +#define mmDCP1_OUT_ROUND_CONTROL 0x1D51 +#define mmDCP1_OVL_CONTROL1 0x1D1D +#define mmDCP1_OVL_CONTROL2 0x1D1E +#define mmDCP1_OVL_DFQ_CONTROL 0x1D29 +#define mmDCP1_OVL_DFQ_STATUS 0x1D2A +#define mmDCP1_OVL_ENABLE 0x1D1C +#define mmDCP1_OVL_END 0x1D26 +#define mmDCP1_OVL_PITCH 0x1D21 +#define mmDCP1_OVLSCL_EDGE_PIXEL_CNTL 0x1D2C +#define mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS 0x1D92 +#define mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1D94 +#define mmDCP1_OVL_START 0x1D25 +#define mmDCP1_OVL_STEREOSYNC_FLIP 0x1D93 +#define mmDCP1_OVL_SURFACE_ADDRESS 0x1D20 +#define mmDCP1_OVL_SURFACE_ADDRESS_HIGH 0x1D22 +#define mmDCP1_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x1D2B +#define mmDCP1_OVL_SURFACE_ADDRESS_INUSE 0x1D28 +#define mmDCP1_OVL_SURFACE_OFFSET_X 0x1D23 +#define mmDCP1_OVL_SURFACE_OFFSET_Y 0x1D24 +#define mmDCP1_OVL_SWAP_CNTL 0x1D1F +#define mmDCP1_OVL_UPDATE 0x1D27 +#define mmDCP1_PRESCALE_GRPH_CONTROL 0x1D2D +#define mmDCP1_PRESCALE_OVL_CONTROL 0x1D31 +#define mmDCP1_PRESCALE_VALUES_GRPH_B 0x1D30 +#define mmDCP1_PRESCALE_VALUES_GRPH_G 0x1D2F +#define mmDCP1_PRESCALE_VALUES_GRPH_R 0x1D2E +#define mmDCP1_PRESCALE_VALUES_OVL_CB 0x1D32 +#define mmDCP1_PRESCALE_VALUES_OVL_CR 0x1D34 +#define mmDCP1_PRESCALE_VALUES_OVL_Y 0x1D33 +#define mmDCP1_REGAMMA_CNTLA_END_CNTL1 0x1DA6 +#define mmDCP1_REGAMMA_CNTLA_END_CNTL2 0x1DA7 +#define mmDCP1_REGAMMA_CNTLA_REGION_0_1 0x1DA8 +#define mmDCP1_REGAMMA_CNTLA_REGION_10_11 0x1DAD +#define mmDCP1_REGAMMA_CNTLA_REGION_12_13 0x1DAE +#define mmDCP1_REGAMMA_CNTLA_REGION_14_15 0x1DAF +#define mmDCP1_REGAMMA_CNTLA_REGION_2_3 0x1DA9 +#define mmDCP1_REGAMMA_CNTLA_REGION_4_5 0x1DAA +#define mmDCP1_REGAMMA_CNTLA_REGION_6_7 0x1DAB +#define mmDCP1_REGAMMA_CNTLA_REGION_8_9 0x1DAC +#define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL 0x1DA5 +#define mmDCP1_REGAMMA_CNTLA_START_CNTL 0x1DA4 +#define mmDCP1_REGAMMA_CNTLB_END_CNTL1 0x1DB2 +#define mmDCP1_REGAMMA_CNTLB_END_CNTL2 0x1DB3 +#define mmDCP1_REGAMMA_CNTLB_REGION_0_1 0x1DB4 +#define mmDCP1_REGAMMA_CNTLB_REGION_10_11 0x1DB9 +#define mmDCP1_REGAMMA_CNTLB_REGION_12_13 0x1DBA +#define mmDCP1_REGAMMA_CNTLB_REGION_14_15 0x1DBB +#define mmDCP1_REGAMMA_CNTLB_REGION_2_3 0x1DB5 +#define mmDCP1_REGAMMA_CNTLB_REGION_4_5 0x1DB6 +#define mmDCP1_REGAMMA_CNTLB_REGION_6_7 0x1DB7 +#define mmDCP1_REGAMMA_CNTLB_REGION_8_9 0x1DB8 +#define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL 0x1DB1 +#define mmDCP1_REGAMMA_CNTLB_START_CNTL 0x1DB0 +#define mmDCP1_REGAMMA_CONTROL 0x1DA0 +#define mmDCP1_REGAMMA_LUT_DATA 0x1DA2 +#define mmDCP1_REGAMMA_LUT_INDEX 0x1DA1 +#define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK 0x1DA3 +#define mmDCP2_COMM_MATRIXA_TRANS_C11_C12 0x4043 +#define mmDCP2_COMM_MATRIXA_TRANS_C13_C14 0x4044 +#define mmDCP2_COMM_MATRIXA_TRANS_C21_C22 0x4045 +#define mmDCP2_COMM_MATRIXA_TRANS_C23_C24 0x4046 +#define mmDCP2_COMM_MATRIXA_TRANS_C31_C32 0x4047 +#define mmDCP2_COMM_MATRIXA_TRANS_C33_C34 0x4048 +#define mmDCP2_COMM_MATRIXB_TRANS_C11_C12 0x4049 +#define mmDCP2_COMM_MATRIXB_TRANS_C13_C14 0x404A +#define mmDCP2_COMM_MATRIXB_TRANS_C21_C22 0x404B +#define mmDCP2_COMM_MATRIXB_TRANS_C23_C24 0x404C +#define mmDCP2_COMM_MATRIXB_TRANS_C31_C32 0x404D +#define mmDCP2_COMM_MATRIXB_TRANS_C33_C34 0x404E +#define mmDCP2_CUR_COLOR1 0x406C +#define mmDCP2_CUR_COLOR2 0x406D +#define mmDCP2_CUR_CONTROL 0x4066 +#define mmDCP2_CUR_HOT_SPOT 0x406B +#define mmDCP2_CUR_POSITION 0x406A +#define mmDCP2_CUR_REQUEST_FILTER_CNTL 0x4099 +#define mmDCP2_CUR_SIZE 0x4068 +#define mmDCP2_CUR_SURFACE_ADDRESS 0x4067 +#define mmDCP2_CUR_SURFACE_ADDRESS_HIGH 0x4069 +#define mmDCP2_CUR_UPDATE 0x406E +#define mmDCP2_DC_LUT_30_COLOR 0x407C +#define mmDCP2_DC_LUT_AUTOFILL 0x407F +#define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE 0x4081 +#define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN 0x4082 +#define mmDCP2_DC_LUT_BLACK_OFFSET_RED 0x4083 +#define mmDCP2_DC_LUT_CONTROL 0x4080 +#define mmDCP2_DC_LUT_PWL_DATA 0x407B +#define mmDCP2_DC_LUT_RW_INDEX 0x4079 +#define mmDCP2_DC_LUT_RW_MODE 0x4078 +#define mmDCP2_DC_LUT_SEQ_COLOR 0x407A +#define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE 0x407D +#define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE 0x4084 +#define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN 0x4085 +#define mmDCP2_DC_LUT_WHITE_OFFSET_RED 0x4086 +#define mmDCP2_DC_LUT_WRITE_EN_MASK 0x407E +#define mmDCP2_DCP_CRC_CONTROL 0x4087 +#define mmDCP2_DCP_CRC_CURRENT 0x4089 +#define mmDCP2_DCP_CRC_LAST 0x408B +#define mmDCP2_DCP_CRC_MASK 0x4088 +#define mmDCP2_DCP_DEBUG 0x408D +#define mmDCP2_DCP_DEBUG2 0x4098 +#define mmDCP2_DCP_FP_CONVERTED_FIELD 0x4065 +#define mmDCP2_DCP_GSL_CONTROL 0x4090 +#define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4091 +#define mmDCP2_DCP_RANDOM_SEEDS 0x4061 +#define mmDCP2_DCP_SPATIAL_DITHER_CNTL 0x4060 +#define mmDCP2_DCP_TEST_DEBUG_DATA 0x4096 +#define mmDCP2_DCP_TEST_DEBUG_INDEX 0x4095 +#define mmDCP2_DEGAMMA_CONTROL 0x4058 +#define mmDCP2_DENORM_CONTROL 0x4050 +#define mmDCP2_GAMUT_REMAP_C11_C12 0x405A +#define mmDCP2_GAMUT_REMAP_C13_C14 0x405B +#define mmDCP2_GAMUT_REMAP_C21_C22 0x405C +#define mmDCP2_GAMUT_REMAP_C23_C24 0x405D +#define mmDCP2_GAMUT_REMAP_C31_C32 0x405E +#define mmDCP2_GAMUT_REMAP_C33_C34 0x405F +#define mmDCP2_GAMUT_REMAP_CONTROL 0x4059 +#define mmDCP2_GRPH_COMPRESS_PITCH 0x401A +#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS 0x4019 +#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x401B +#define mmDCP2_GRPH_CONTROL 0x4001 +#define mmDCP2_GRPH_DFQ_CONTROL 0x4014 +#define mmDCP2_GRPH_DFQ_STATUS 0x4015 +#define mmDCP2_GRPH_ENABLE 0x4000 +#define mmDCP2_GRPH_FLIP_CONTROL 0x4012 +#define mmDCP2_GRPH_INTERRUPT_CONTROL 0x4017 +#define mmDCP2_GRPH_INTERRUPT_STATUS 0x4016 +#define mmDCP2_GRPH_LUT_10BIT_BYPASS 0x4002 +#define mmDCP2_GRPH_PITCH 0x4006 +#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS 0x4004 +#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4007 +#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS 0x4005 +#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4008 +#define mmDCP2_GRPH_STEREOSYNC_FLIP 0x4097 +#define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4018 +#define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE 0x4013 +#define mmDCP2_GRPH_SURFACE_OFFSET_X 0x4009 +#define mmDCP2_GRPH_SURFACE_OFFSET_Y 0x400A +#define mmDCP2_GRPH_SWAP_CNTL 0x4003 +#define mmDCP2_GRPH_UPDATE 0x4011 +#define mmDCP2_GRPH_X_END 0x400D +#define mmDCP2_GRPH_X_START 0x400B +#define mmDCP2_GRPH_Y_END 0x400E +#define mmDCP2_GRPH_Y_START 0x400C +#define mmDCP2_INPUT_CSC_C11_C12 0x4036 +#define mmDCP2_INPUT_CSC_C13_C14 0x4037 +#define mmDCP2_INPUT_CSC_C21_C22 0x4038 +#define mmDCP2_INPUT_CSC_C23_C24 0x4039 +#define mmDCP2_INPUT_CSC_C31_C32 0x403A +#define mmDCP2_INPUT_CSC_C33_C34 0x403B +#define mmDCP2_INPUT_CSC_CONTROL 0x4035 +#define mmDCP2_INPUT_GAMMA_CONTROL 0x4010 +#define mmDCP2_KEY_CONTROL 0x4053 +#define mmDCP2_KEY_RANGE_ALPHA 0x4054 +#define mmDCP2_KEY_RANGE_BLUE 0x4057 +#define mmDCP2_KEY_RANGE_GREEN 0x4056 +#define mmDCP2_KEY_RANGE_RED 0x4055 +#define mmDCP2_OUTPUT_CSC_C11_C12 0x403D +#define mmDCP2_OUTPUT_CSC_C13_C14 0x403E +#define mmDCP2_OUTPUT_CSC_C21_C22 0x403F +#define mmDCP2_OUTPUT_CSC_C23_C24 0x4040 +#define mmDCP2_OUTPUT_CSC_C31_C32 0x4041 +#define mmDCP2_OUTPUT_CSC_C33_C34 0x4042 +#define mmDCP2_OUTPUT_CSC_CONTROL 0x403C +#define mmDCP2_OUT_ROUND_CONTROL 0x4051 +#define mmDCP2_OVL_CONTROL1 0x401D +#define mmDCP2_OVL_CONTROL2 0x401E +#define mmDCP2_OVL_DFQ_CONTROL 0x4029 +#define mmDCP2_OVL_DFQ_STATUS 0x402A +#define mmDCP2_OVL_ENABLE 0x401C +#define mmDCP2_OVL_END 0x4026 +#define mmDCP2_OVL_PITCH 0x4021 +#define mmDCP2_OVLSCL_EDGE_PIXEL_CNTL 0x402C +#define mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS 0x4092 +#define mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4094 +#define mmDCP2_OVL_START 0x4025 +#define mmDCP2_OVL_STEREOSYNC_FLIP 0x4093 +#define mmDCP2_OVL_SURFACE_ADDRESS 0x4020 +#define mmDCP2_OVL_SURFACE_ADDRESS_HIGH 0x4022 +#define mmDCP2_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x402B +#define mmDCP2_OVL_SURFACE_ADDRESS_INUSE 0x4028 +#define mmDCP2_OVL_SURFACE_OFFSET_X 0x4023 +#define mmDCP2_OVL_SURFACE_OFFSET_Y 0x4024 +#define mmDCP2_OVL_SWAP_CNTL 0x401F +#define mmDCP2_OVL_UPDATE 0x4027 +#define mmDCP2_PRESCALE_GRPH_CONTROL 0x402D +#define mmDCP2_PRESCALE_OVL_CONTROL 0x4031 +#define mmDCP2_PRESCALE_VALUES_GRPH_B 0x4030 +#define mmDCP2_PRESCALE_VALUES_GRPH_G 0x402F +#define mmDCP2_PRESCALE_VALUES_GRPH_R 0x402E +#define mmDCP2_PRESCALE_VALUES_OVL_CB 0x4032 +#define mmDCP2_PRESCALE_VALUES_OVL_CR 0x4034 +#define mmDCP2_PRESCALE_VALUES_OVL_Y 0x4033 +#define mmDCP2_REGAMMA_CNTLA_END_CNTL1 0x40A6 +#define mmDCP2_REGAMMA_CNTLA_END_CNTL2 0x40A7 +#define mmDCP2_REGAMMA_CNTLA_REGION_0_1 0x40A8 +#define mmDCP2_REGAMMA_CNTLA_REGION_10_11 0x40AD +#define mmDCP2_REGAMMA_CNTLA_REGION_12_13 0x40AE +#define mmDCP2_REGAMMA_CNTLA_REGION_14_15 0x40AF +#define mmDCP2_REGAMMA_CNTLA_REGION_2_3 0x40A9 +#define mmDCP2_REGAMMA_CNTLA_REGION_4_5 0x40AA +#define mmDCP2_REGAMMA_CNTLA_REGION_6_7 0x40AB +#define mmDCP2_REGAMMA_CNTLA_REGION_8_9 0x40AC +#define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL 0x40A5 +#define mmDCP2_REGAMMA_CNTLA_START_CNTL 0x40A4 +#define mmDCP2_REGAMMA_CNTLB_END_CNTL1 0x40B2 +#define mmDCP2_REGAMMA_CNTLB_END_CNTL2 0x40B3 +#define mmDCP2_REGAMMA_CNTLB_REGION_0_1 0x40B4 +#define mmDCP2_REGAMMA_CNTLB_REGION_10_11 0x40B9 +#define mmDCP2_REGAMMA_CNTLB_REGION_12_13 0x40BA +#define mmDCP2_REGAMMA_CNTLB_REGION_14_15 0x40BB +#define mmDCP2_REGAMMA_CNTLB_REGION_2_3 0x40B5 +#define mmDCP2_REGAMMA_CNTLB_REGION_4_5 0x40B6 +#define mmDCP2_REGAMMA_CNTLB_REGION_6_7 0x40B7 +#define mmDCP2_REGAMMA_CNTLB_REGION_8_9 0x40B8 +#define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL 0x40B1 +#define mmDCP2_REGAMMA_CNTLB_START_CNTL 0x40B0 +#define mmDCP2_REGAMMA_CONTROL 0x40A0 +#define mmDCP2_REGAMMA_LUT_DATA 0x40A2 +#define mmDCP2_REGAMMA_LUT_INDEX 0x40A1 +#define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK 0x40A3 +#define mmDCP3_COMM_MATRIXA_TRANS_C11_C12 0x4343 +#define mmDCP3_COMM_MATRIXA_TRANS_C13_C14 0x4344 +#define mmDCP3_COMM_MATRIXA_TRANS_C21_C22 0x4345 +#define mmDCP3_COMM_MATRIXA_TRANS_C23_C24 0x4346 +#define mmDCP3_COMM_MATRIXA_TRANS_C31_C32 0x4347 +#define mmDCP3_COMM_MATRIXA_TRANS_C33_C34 0x4348 +#define mmDCP3_COMM_MATRIXB_TRANS_C11_C12 0x4349 +#define mmDCP3_COMM_MATRIXB_TRANS_C13_C14 0x434A +#define mmDCP3_COMM_MATRIXB_TRANS_C21_C22 0x434B +#define mmDCP3_COMM_MATRIXB_TRANS_C23_C24 0x434C +#define mmDCP3_COMM_MATRIXB_TRANS_C31_C32 0x434D +#define mmDCP3_COMM_MATRIXB_TRANS_C33_C34 0x434E +#define mmDCP3_CUR_COLOR1 0x436C +#define mmDCP3_CUR_COLOR2 0x436D +#define mmDCP3_CUR_CONTROL 0x4366 +#define mmDCP3_CUR_HOT_SPOT 0x436B +#define mmDCP3_CUR_POSITION 0x436A +#define mmDCP3_CUR_REQUEST_FILTER_CNTL 0x4399 +#define mmDCP3_CUR_SIZE 0x4368 +#define mmDCP3_CUR_SURFACE_ADDRESS 0x4367 +#define mmDCP3_CUR_SURFACE_ADDRESS_HIGH 0x4369 +#define mmDCP3_CUR_UPDATE 0x436E +#define mmDCP3_DC_LUT_30_COLOR 0x437C +#define mmDCP3_DC_LUT_AUTOFILL 0x437F +#define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE 0x4381 +#define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN 0x4382 +#define mmDCP3_DC_LUT_BLACK_OFFSET_RED 0x4383 +#define mmDCP3_DC_LUT_CONTROL 0x4380 +#define mmDCP3_DC_LUT_PWL_DATA 0x437B +#define mmDCP3_DC_LUT_RW_INDEX 0x4379 +#define mmDCP3_DC_LUT_RW_MODE 0x4378 +#define mmDCP3_DC_LUT_SEQ_COLOR 0x437A +#define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE 0x437D +#define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE 0x4384 +#define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN 0x4385 +#define mmDCP3_DC_LUT_WHITE_OFFSET_RED 0x4386 +#define mmDCP3_DC_LUT_WRITE_EN_MASK 0x437E +#define mmDCP3_DCP_CRC_CONTROL 0x4387 +#define mmDCP3_DCP_CRC_CURRENT 0x4389 +#define mmDCP3_DCP_CRC_LAST 0x438B +#define mmDCP3_DCP_CRC_MASK 0x4388 +#define mmDCP3_DCP_DEBUG 0x438D +#define mmDCP3_DCP_DEBUG2 0x4398 +#define mmDCP3_DCP_FP_CONVERTED_FIELD 0x4365 +#define mmDCP3_DCP_GSL_CONTROL 0x4390 +#define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4391 +#define mmDCP3_DCP_RANDOM_SEEDS 0x4361 +#define mmDCP3_DCP_SPATIAL_DITHER_CNTL 0x4360 +#define mmDCP3_DCP_TEST_DEBUG_DATA 0x4396 +#define mmDCP3_DCP_TEST_DEBUG_INDEX 0x4395 +#define mmDCP3_DEGAMMA_CONTROL 0x4358 +#define mmDCP3_DENORM_CONTROL 0x4350 +#define mmDCP3_GAMUT_REMAP_C11_C12 0x435A +#define mmDCP3_GAMUT_REMAP_C13_C14 0x435B +#define mmDCP3_GAMUT_REMAP_C21_C22 0x435C +#define mmDCP3_GAMUT_REMAP_C23_C24 0x435D +#define mmDCP3_GAMUT_REMAP_C31_C32 0x435E +#define mmDCP3_GAMUT_REMAP_C33_C34 0x435F +#define mmDCP3_GAMUT_REMAP_CONTROL 0x4359 +#define mmDCP3_GRPH_COMPRESS_PITCH 0x431A +#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS 0x4319 +#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x431B +#define mmDCP3_GRPH_CONTROL 0x4301 +#define mmDCP3_GRPH_DFQ_CONTROL 0x4314 +#define mmDCP3_GRPH_DFQ_STATUS 0x4315 +#define mmDCP3_GRPH_ENABLE 0x4300 +#define mmDCP3_GRPH_FLIP_CONTROL 0x4312 +#define mmDCP3_GRPH_INTERRUPT_CONTROL 0x4317 +#define mmDCP3_GRPH_INTERRUPT_STATUS 0x4316 +#define mmDCP3_GRPH_LUT_10BIT_BYPASS 0x4302 +#define mmDCP3_GRPH_PITCH 0x4306 +#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS 0x4304 +#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4307 +#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS 0x4305 +#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4308 +#define mmDCP3_GRPH_STEREOSYNC_FLIP 0x4397 +#define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4318 +#define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE 0x4313 +#define mmDCP3_GRPH_SURFACE_OFFSET_X 0x4309 +#define mmDCP3_GRPH_SURFACE_OFFSET_Y 0x430A +#define mmDCP3_GRPH_SWAP_CNTL 0x4303 +#define mmDCP3_GRPH_UPDATE 0x4311 +#define mmDCP3_GRPH_X_END 0x430D +#define mmDCP3_GRPH_X_START 0x430B +#define mmDCP3_GRPH_Y_END 0x430E +#define mmDCP3_GRPH_Y_START 0x430C +#define mmDCP3_INPUT_CSC_C11_C12 0x4336 +#define mmDCP3_INPUT_CSC_C13_C14 0x4337 +#define mmDCP3_INPUT_CSC_C21_C22 0x4338 +#define mmDCP3_INPUT_CSC_C23_C24 0x4339 +#define mmDCP3_INPUT_CSC_C31_C32 0x433A +#define mmDCP3_INPUT_CSC_C33_C34 0x433B +#define mmDCP3_INPUT_CSC_CONTROL 0x4335 +#define mmDCP3_INPUT_GAMMA_CONTROL 0x4310 +#define mmDCP3_KEY_CONTROL 0x4353 +#define mmDCP3_KEY_RANGE_ALPHA 0x4354 +#define mmDCP3_KEY_RANGE_BLUE 0x4357 +#define mmDCP3_KEY_RANGE_GREEN 0x4356 +#define mmDCP3_KEY_RANGE_RED 0x4355 +#define mmDCP3_OUTPUT_CSC_C11_C12 0x433D +#define mmDCP3_OUTPUT_CSC_C13_C14 0x433E +#define mmDCP3_OUTPUT_CSC_C21_C22 0x433F +#define mmDCP3_OUTPUT_CSC_C23_C24 0x4340 +#define mmDCP3_OUTPUT_CSC_C31_C32 0x4341 +#define mmDCP3_OUTPUT_CSC_C33_C34 0x4342 +#define mmDCP3_OUTPUT_CSC_CONTROL 0x433C +#define mmDCP3_OUT_ROUND_CONTROL 0x4351 +#define mmDCP3_OVL_CONTROL1 0x431D +#define mmDCP3_OVL_CONTROL2 0x431E +#define mmDCP3_OVL_DFQ_CONTROL 0x4329 +#define mmDCP3_OVL_DFQ_STATUS 0x432A +#define mmDCP3_OVL_ENABLE 0x431C +#define mmDCP3_OVL_END 0x4326 +#define mmDCP3_OVL_PITCH 0x4321 +#define mmDCP3_OVLSCL_EDGE_PIXEL_CNTL 0x432C +#define mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS 0x4392 +#define mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4394 +#define mmDCP3_OVL_START 0x4325 +#define mmDCP3_OVL_STEREOSYNC_FLIP 0x4393 +#define mmDCP3_OVL_SURFACE_ADDRESS 0x4320 +#define mmDCP3_OVL_SURFACE_ADDRESS_HIGH 0x4322 +#define mmDCP3_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x432B +#define mmDCP3_OVL_SURFACE_ADDRESS_INUSE 0x4328 +#define mmDCP3_OVL_SURFACE_OFFSET_X 0x4323 +#define mmDCP3_OVL_SURFACE_OFFSET_Y 0x4324 +#define mmDCP3_OVL_SWAP_CNTL 0x431F +#define mmDCP3_OVL_UPDATE 0x4327 +#define mmDCP3_PRESCALE_GRPH_CONTROL 0x432D +#define mmDCP3_PRESCALE_OVL_CONTROL 0x4331 +#define mmDCP3_PRESCALE_VALUES_GRPH_B 0x4330 +#define mmDCP3_PRESCALE_VALUES_GRPH_G 0x432F +#define mmDCP3_PRESCALE_VALUES_GRPH_R 0x432E +#define mmDCP3_PRESCALE_VALUES_OVL_CB 0x4332 +#define mmDCP3_PRESCALE_VALUES_OVL_CR 0x4334 +#define mmDCP3_PRESCALE_VALUES_OVL_Y 0x4333 +#define mmDCP3_REGAMMA_CNTLA_END_CNTL1 0x43A6 +#define mmDCP3_REGAMMA_CNTLA_END_CNTL2 0x43A7 +#define mmDCP3_REGAMMA_CNTLA_REGION_0_1 0x43A8 +#define mmDCP3_REGAMMA_CNTLA_REGION_10_11 0x43AD +#define mmDCP3_REGAMMA_CNTLA_REGION_12_13 0x43AE +#define mmDCP3_REGAMMA_CNTLA_REGION_14_15 0x43AF +#define mmDCP3_REGAMMA_CNTLA_REGION_2_3 0x43A9 +#define mmDCP3_REGAMMA_CNTLA_REGION_4_5 0x43AA +#define mmDCP3_REGAMMA_CNTLA_REGION_6_7 0x43AB +#define mmDCP3_REGAMMA_CNTLA_REGION_8_9 0x43AC +#define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL 0x43A5 +#define mmDCP3_REGAMMA_CNTLA_START_CNTL 0x43A4 +#define mmDCP3_REGAMMA_CNTLB_END_CNTL1 0x43B2 +#define mmDCP3_REGAMMA_CNTLB_END_CNTL2 0x43B3 +#define mmDCP3_REGAMMA_CNTLB_REGION_0_1 0x43B4 +#define mmDCP3_REGAMMA_CNTLB_REGION_10_11 0x43B9 +#define mmDCP3_REGAMMA_CNTLB_REGION_12_13 0x43BA +#define mmDCP3_REGAMMA_CNTLB_REGION_14_15 0x43BB +#define mmDCP3_REGAMMA_CNTLB_REGION_2_3 0x43B5 +#define mmDCP3_REGAMMA_CNTLB_REGION_4_5 0x43B6 +#define mmDCP3_REGAMMA_CNTLB_REGION_6_7 0x43B7 +#define mmDCP3_REGAMMA_CNTLB_REGION_8_9 0x43B8 +#define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL 0x43B1 +#define mmDCP3_REGAMMA_CNTLB_START_CNTL 0x43B0 +#define mmDCP3_REGAMMA_CONTROL 0x43A0 +#define mmDCP3_REGAMMA_LUT_DATA 0x43A2 +#define mmDCP3_REGAMMA_LUT_INDEX 0x43A1 +#define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK 0x43A3 +#define mmDCP4_COMM_MATRIXA_TRANS_C11_C12 0x4643 +#define mmDCP4_COMM_MATRIXA_TRANS_C13_C14 0x4644 +#define mmDCP4_COMM_MATRIXA_TRANS_C21_C22 0x4645 +#define mmDCP4_COMM_MATRIXA_TRANS_C23_C24 0x4646 +#define mmDCP4_COMM_MATRIXA_TRANS_C31_C32 0x4647 +#define mmDCP4_COMM_MATRIXA_TRANS_C33_C34 0x4648 +#define mmDCP4_COMM_MATRIXB_TRANS_C11_C12 0x4649 +#define mmDCP4_COMM_MATRIXB_TRANS_C13_C14 0x464A +#define mmDCP4_COMM_MATRIXB_TRANS_C21_C22 0x464B +#define mmDCP4_COMM_MATRIXB_TRANS_C23_C24 0x464C +#define mmDCP4_COMM_MATRIXB_TRANS_C31_C32 0x464D +#define mmDCP4_COMM_MATRIXB_TRANS_C33_C34 0x464E +#define mmDCP4_CUR_COLOR1 0x466C +#define mmDCP4_CUR_COLOR2 0x466D +#define mmDCP4_CUR_CONTROL 0x4666 +#define mmDCP4_CUR_HOT_SPOT 0x466B +#define mmDCP4_CUR_POSITION 0x466A +#define mmDCP4_CUR_REQUEST_FILTER_CNTL 0x4699 +#define mmDCP4_CUR_SIZE 0x4668 +#define mmDCP4_CUR_SURFACE_ADDRESS 0x4667 +#define mmDCP4_CUR_SURFACE_ADDRESS_HIGH 0x4669 +#define mmDCP4_CUR_UPDATE 0x466E +#define mmDCP4_DC_LUT_30_COLOR 0x467C +#define mmDCP4_DC_LUT_AUTOFILL 0x467F +#define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE 0x4681 +#define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN 0x4682 +#define mmDCP4_DC_LUT_BLACK_OFFSET_RED 0x4683 +#define mmDCP4_DC_LUT_CONTROL 0x4680 +#define mmDCP4_DC_LUT_PWL_DATA 0x467B +#define mmDCP4_DC_LUT_RW_INDEX 0x4679 +#define mmDCP4_DC_LUT_RW_MODE 0x4678 +#define mmDCP4_DC_LUT_SEQ_COLOR 0x467A +#define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE 0x467D +#define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE 0x4684 +#define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN 0x4685 +#define mmDCP4_DC_LUT_WHITE_OFFSET_RED 0x4686 +#define mmDCP4_DC_LUT_WRITE_EN_MASK 0x467E +#define mmDCP4_DCP_CRC_CONTROL 0x4687 +#define mmDCP4_DCP_CRC_CURRENT 0x4689 +#define mmDCP4_DCP_CRC_LAST 0x468B +#define mmDCP4_DCP_CRC_MASK 0x4688 +#define mmDCP4_DCP_DEBUG 0x468D +#define mmDCP4_DCP_DEBUG2 0x4698 +#define mmDCP4_DCP_FP_CONVERTED_FIELD 0x4665 +#define mmDCP4_DCP_GSL_CONTROL 0x4690 +#define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4691 +#define mmDCP4_DCP_RANDOM_SEEDS 0x4661 +#define mmDCP4_DCP_SPATIAL_DITHER_CNTL 0x4660 +#define mmDCP4_DCP_TEST_DEBUG_DATA 0x4696 +#define mmDCP4_DCP_TEST_DEBUG_INDEX 0x4695 +#define mmDCP4_DEGAMMA_CONTROL 0x4658 +#define mmDCP4_DENORM_CONTROL 0x4650 +#define mmDCP4_GAMUT_REMAP_C11_C12 0x465A +#define mmDCP4_GAMUT_REMAP_C13_C14 0x465B +#define mmDCP4_GAMUT_REMAP_C21_C22 0x465C +#define mmDCP4_GAMUT_REMAP_C23_C24 0x465D +#define mmDCP4_GAMUT_REMAP_C31_C32 0x465E +#define mmDCP4_GAMUT_REMAP_C33_C34 0x465F +#define mmDCP4_GAMUT_REMAP_CONTROL 0x4659 +#define mmDCP4_GRPH_COMPRESS_PITCH 0x461A +#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS 0x4619 +#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x461B +#define mmDCP4_GRPH_CONTROL 0x4601 +#define mmDCP4_GRPH_DFQ_CONTROL 0x4614 +#define mmDCP4_GRPH_DFQ_STATUS 0x4615 +#define mmDCP4_GRPH_ENABLE 0x4600 +#define mmDCP4_GRPH_FLIP_CONTROL 0x4612 +#define mmDCP4_GRPH_INTERRUPT_CONTROL 0x4617 +#define mmDCP4_GRPH_INTERRUPT_STATUS 0x4616 +#define mmDCP4_GRPH_LUT_10BIT_BYPASS 0x4602 +#define mmDCP4_GRPH_PITCH 0x4606 +#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS 0x4604 +#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4607 +#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS 0x4605 +#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4608 +#define mmDCP4_GRPH_STEREOSYNC_FLIP 0x4697 +#define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4618 +#define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE 0x4613 +#define mmDCP4_GRPH_SURFACE_OFFSET_X 0x4609 +#define mmDCP4_GRPH_SURFACE_OFFSET_Y 0x460A +#define mmDCP4_GRPH_SWAP_CNTL 0x4603 +#define mmDCP4_GRPH_UPDATE 0x4611 +#define mmDCP4_GRPH_X_END 0x460D +#define mmDCP4_GRPH_X_START 0x460B +#define mmDCP4_GRPH_Y_END 0x460E +#define mmDCP4_GRPH_Y_START 0x460C +#define mmDCP4_INPUT_CSC_C11_C12 0x4636 +#define mmDCP4_INPUT_CSC_C13_C14 0x4637 +#define mmDCP4_INPUT_CSC_C21_C22 0x4638 +#define mmDCP4_INPUT_CSC_C23_C24 0x4639 +#define mmDCP4_INPUT_CSC_C31_C32 0x463A +#define mmDCP4_INPUT_CSC_C33_C34 0x463B +#define mmDCP4_INPUT_CSC_CONTROL 0x4635 +#define mmDCP4_INPUT_GAMMA_CONTROL 0x4610 +#define mmDCP4_KEY_CONTROL 0x4653 +#define mmDCP4_KEY_RANGE_ALPHA 0x4654 +#define mmDCP4_KEY_RANGE_BLUE 0x4657 +#define mmDCP4_KEY_RANGE_GREEN 0x4656 +#define mmDCP4_KEY_RANGE_RED 0x4655 +#define mmDCP4_OUTPUT_CSC_C11_C12 0x463D +#define mmDCP4_OUTPUT_CSC_C13_C14 0x463E +#define mmDCP4_OUTPUT_CSC_C21_C22 0x463F +#define mmDCP4_OUTPUT_CSC_C23_C24 0x4640 +#define mmDCP4_OUTPUT_CSC_C31_C32 0x4641 +#define mmDCP4_OUTPUT_CSC_C33_C34 0x4642 +#define mmDCP4_OUTPUT_CSC_CONTROL 0x463C +#define mmDCP4_OUT_ROUND_CONTROL 0x4651 +#define mmDCP4_OVL_CONTROL1 0x461D +#define mmDCP4_OVL_CONTROL2 0x461E +#define mmDCP4_OVL_DFQ_CONTROL 0x4629 +#define mmDCP4_OVL_DFQ_STATUS 0x462A +#define mmDCP4_OVL_ENABLE 0x461C +#define mmDCP4_OVL_END 0x4626 +#define mmDCP4_OVL_PITCH 0x4621 +#define mmDCP4_OVLSCL_EDGE_PIXEL_CNTL 0x462C +#define mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS 0x4692 +#define mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4694 +#define mmDCP4_OVL_START 0x4625 +#define mmDCP4_OVL_STEREOSYNC_FLIP 0x4693 +#define mmDCP4_OVL_SURFACE_ADDRESS 0x4620 +#define mmDCP4_OVL_SURFACE_ADDRESS_HIGH 0x4622 +#define mmDCP4_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x462B +#define mmDCP4_OVL_SURFACE_ADDRESS_INUSE 0x4628 +#define mmDCP4_OVL_SURFACE_OFFSET_X 0x4623 +#define mmDCP4_OVL_SURFACE_OFFSET_Y 0x4624 +#define mmDCP4_OVL_SWAP_CNTL 0x461F +#define mmDCP4_OVL_UPDATE 0x4627 +#define mmDCP4_PRESCALE_GRPH_CONTROL 0x462D +#define mmDCP4_PRESCALE_OVL_CONTROL 0x4631 +#define mmDCP4_PRESCALE_VALUES_GRPH_B 0x4630 +#define mmDCP4_PRESCALE_VALUES_GRPH_G 0x462F +#define mmDCP4_PRESCALE_VALUES_GRPH_R 0x462E +#define mmDCP4_PRESCALE_VALUES_OVL_CB 0x4632 +#define mmDCP4_PRESCALE_VALUES_OVL_CR 0x4634 +#define mmDCP4_PRESCALE_VALUES_OVL_Y 0x4633 +#define mmDCP4_REGAMMA_CNTLA_END_CNTL1 0x46A6 +#define mmDCP4_REGAMMA_CNTLA_END_CNTL2 0x46A7 +#define mmDCP4_REGAMMA_CNTLA_REGION_0_1 0x46A8 +#define mmDCP4_REGAMMA_CNTLA_REGION_10_11 0x46AD +#define mmDCP4_REGAMMA_CNTLA_REGION_12_13 0x46AE +#define mmDCP4_REGAMMA_CNTLA_REGION_14_15 0x46AF +#define mmDCP4_REGAMMA_CNTLA_REGION_2_3 0x46A9 +#define mmDCP4_REGAMMA_CNTLA_REGION_4_5 0x46AA +#define mmDCP4_REGAMMA_CNTLA_REGION_6_7 0x46AB +#define mmDCP4_REGAMMA_CNTLA_REGION_8_9 0x46AC +#define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL 0x46A5 +#define mmDCP4_REGAMMA_CNTLA_START_CNTL 0x46A4 +#define mmDCP4_REGAMMA_CNTLB_END_CNTL1 0x46B2 +#define mmDCP4_REGAMMA_CNTLB_END_CNTL2 0x46B3 +#define mmDCP4_REGAMMA_CNTLB_REGION_0_1 0x46B4 +#define mmDCP4_REGAMMA_CNTLB_REGION_10_11 0x46B9 +#define mmDCP4_REGAMMA_CNTLB_REGION_12_13 0x46BA +#define mmDCP4_REGAMMA_CNTLB_REGION_14_15 0x46BB +#define mmDCP4_REGAMMA_CNTLB_REGION_2_3 0x46B5 +#define mmDCP4_REGAMMA_CNTLB_REGION_4_5 0x46B6 +#define mmDCP4_REGAMMA_CNTLB_REGION_6_7 0x46B7 +#define mmDCP4_REGAMMA_CNTLB_REGION_8_9 0x46B8 +#define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL 0x46B1 +#define mmDCP4_REGAMMA_CNTLB_START_CNTL 0x46B0 +#define mmDCP4_REGAMMA_CONTROL 0x46A0 +#define mmDCP4_REGAMMA_LUT_DATA 0x46A2 +#define mmDCP4_REGAMMA_LUT_INDEX 0x46A1 +#define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK 0x46A3 +#define mmDCP5_COMM_MATRIXA_TRANS_C11_C12 0x4943 +#define mmDCP5_COMM_MATRIXA_TRANS_C13_C14 0x4944 +#define mmDCP5_COMM_MATRIXA_TRANS_C21_C22 0x4945 +#define mmDCP5_COMM_MATRIXA_TRANS_C23_C24 0x4946 +#define mmDCP5_COMM_MATRIXA_TRANS_C31_C32 0x4947 +#define mmDCP5_COMM_MATRIXA_TRANS_C33_C34 0x4948 +#define mmDCP5_COMM_MATRIXB_TRANS_C11_C12 0x4949 +#define mmDCP5_COMM_MATRIXB_TRANS_C13_C14 0x494A +#define mmDCP5_COMM_MATRIXB_TRANS_C21_C22 0x494B +#define mmDCP5_COMM_MATRIXB_TRANS_C23_C24 0x494C +#define mmDCP5_COMM_MATRIXB_TRANS_C31_C32 0x494D +#define mmDCP5_COMM_MATRIXB_TRANS_C33_C34 0x494E +#define mmDCP5_CUR_COLOR1 0x496C +#define mmDCP5_CUR_COLOR2 0x496D +#define mmDCP5_CUR_CONTROL 0x4966 +#define mmDCP5_CUR_HOT_SPOT 0x496B +#define mmDCP5_CUR_POSITION 0x496A +#define mmDCP5_CUR_REQUEST_FILTER_CNTL 0x4999 +#define mmDCP5_CUR_SIZE 0x4968 +#define mmDCP5_CUR_SURFACE_ADDRESS 0x4967 +#define mmDCP5_CUR_SURFACE_ADDRESS_HIGH 0x4969 +#define mmDCP5_CUR_UPDATE 0x496E +#define mmDCP5_DC_LUT_30_COLOR 0x497C +#define mmDCP5_DC_LUT_AUTOFILL 0x497F +#define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE 0x4981 +#define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN 0x4982 +#define mmDCP5_DC_LUT_BLACK_OFFSET_RED 0x4983 +#define mmDCP5_DC_LUT_CONTROL 0x4980 +#define mmDCP5_DC_LUT_PWL_DATA 0x497B +#define mmDCP5_DC_LUT_RW_INDEX 0x4979 +#define mmDCP5_DC_LUT_RW_MODE 0x4978 +#define mmDCP5_DC_LUT_SEQ_COLOR 0x497A +#define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE 0x497D +#define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE 0x4984 +#define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN 0x4985 +#define mmDCP5_DC_LUT_WHITE_OFFSET_RED 0x4986 +#define mmDCP5_DC_LUT_WRITE_EN_MASK 0x497E +#define mmDCP5_DCP_CRC_CONTROL 0x4987 +#define mmDCP5_DCP_CRC_CURRENT 0x4989 +#define mmDCP5_DCP_CRC_LAST 0x498B +#define mmDCP5_DCP_CRC_MASK 0x4988 +#define mmDCP5_DCP_DEBUG 0x498D +#define mmDCP5_DCP_DEBUG2 0x4998 +#define mmDCP5_DCP_FP_CONVERTED_FIELD 0x4965 +#define mmDCP5_DCP_GSL_CONTROL 0x4990 +#define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4991 +#define mmDCP5_DCP_RANDOM_SEEDS 0x4961 +#define mmDCP5_DCP_SPATIAL_DITHER_CNTL 0x4960 +#define mmDCP5_DCP_TEST_DEBUG_DATA 0x4996 +#define mmDCP5_DCP_TEST_DEBUG_INDEX 0x4995 +#define mmDCP5_DEGAMMA_CONTROL 0x4958 +#define mmDCP5_DENORM_CONTROL 0x4950 +#define mmDCP5_GAMUT_REMAP_C11_C12 0x495A +#define mmDCP5_GAMUT_REMAP_C13_C14 0x495B +#define mmDCP5_GAMUT_REMAP_C21_C22 0x495C +#define mmDCP5_GAMUT_REMAP_C23_C24 0x495D +#define mmDCP5_GAMUT_REMAP_C31_C32 0x495E +#define mmDCP5_GAMUT_REMAP_C33_C34 0x495F +#define mmDCP5_GAMUT_REMAP_CONTROL 0x4959 +#define mmDCP5_GRPH_COMPRESS_PITCH 0x491A +#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS 0x4919 +#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x491B +#define mmDCP5_GRPH_CONTROL 0x4901 +#define mmDCP5_GRPH_DFQ_CONTROL 0x4914 +#define mmDCP5_GRPH_DFQ_STATUS 0x4915 +#define mmDCP5_GRPH_ENABLE 0x4900 +#define mmDCP5_GRPH_FLIP_CONTROL 0x4912 +#define mmDCP5_GRPH_INTERRUPT_CONTROL 0x4917 +#define mmDCP5_GRPH_INTERRUPT_STATUS 0x4916 +#define mmDCP5_GRPH_LUT_10BIT_BYPASS 0x4902 +#define mmDCP5_GRPH_PITCH 0x4906 +#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS 0x4904 +#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4907 +#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS 0x4905 +#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4908 +#define mmDCP5_GRPH_STEREOSYNC_FLIP 0x4997 +#define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4918 +#define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE 0x4913 +#define mmDCP5_GRPH_SURFACE_OFFSET_X 0x4909 +#define mmDCP5_GRPH_SURFACE_OFFSET_Y 0x490A +#define mmDCP5_GRPH_SWAP_CNTL 0x4903 +#define mmDCP5_GRPH_UPDATE 0x4911 +#define mmDCP5_GRPH_X_END 0x490D +#define mmDCP5_GRPH_X_START 0x490B +#define mmDCP5_GRPH_Y_END 0x490E +#define mmDCP5_GRPH_Y_START 0x490C +#define mmDCP5_INPUT_CSC_C11_C12 0x4936 +#define mmDCP5_INPUT_CSC_C13_C14 0x4937 +#define mmDCP5_INPUT_CSC_C21_C22 0x4938 +#define mmDCP5_INPUT_CSC_C23_C24 0x4939 +#define mmDCP5_INPUT_CSC_C31_C32 0x493A +#define mmDCP5_INPUT_CSC_C33_C34 0x493B +#define mmDCP5_INPUT_CSC_CONTROL 0x4935 +#define mmDCP5_INPUT_GAMMA_CONTROL 0x4910 +#define mmDCP5_KEY_CONTROL 0x4953 +#define mmDCP5_KEY_RANGE_ALPHA 0x4954 +#define mmDCP5_KEY_RANGE_BLUE 0x4957 +#define mmDCP5_KEY_RANGE_GREEN 0x4956 +#define mmDCP5_KEY_RANGE_RED 0x4955 +#define mmDCP5_OUTPUT_CSC_C11_C12 0x493D +#define mmDCP5_OUTPUT_CSC_C13_C14 0x493E +#define mmDCP5_OUTPUT_CSC_C21_C22 0x493F +#define mmDCP5_OUTPUT_CSC_C23_C24 0x4940 +#define mmDCP5_OUTPUT_CSC_C31_C32 0x4941 +#define mmDCP5_OUTPUT_CSC_C33_C34 0x4942 +#define mmDCP5_OUTPUT_CSC_CONTROL 0x493C +#define mmDCP5_OUT_ROUND_CONTROL 0x4951 +#define mmDCP5_OVL_CONTROL1 0x491D +#define mmDCP5_OVL_CONTROL2 0x491E +#define mmDCP5_OVL_DFQ_CONTROL 0x4929 +#define mmDCP5_OVL_DFQ_STATUS 0x492A +#define mmDCP5_OVL_ENABLE 0x491C +#define mmDCP5_OVL_END 0x4926 +#define mmDCP5_OVL_PITCH 0x4921 +#define mmDCP5_OVLSCL_EDGE_PIXEL_CNTL 0x492C +#define mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS 0x4992 +#define mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4994 +#define mmDCP5_OVL_START 0x4925 +#define mmDCP5_OVL_STEREOSYNC_FLIP 0x4993 +#define mmDCP5_OVL_SURFACE_ADDRESS 0x4920 +#define mmDCP5_OVL_SURFACE_ADDRESS_HIGH 0x4922 +#define mmDCP5_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x492B +#define mmDCP5_OVL_SURFACE_ADDRESS_INUSE 0x4928 +#define mmDCP5_OVL_SURFACE_OFFSET_X 0x4923 +#define mmDCP5_OVL_SURFACE_OFFSET_Y 0x4924 +#define mmDCP5_OVL_SWAP_CNTL 0x491F +#define mmDCP5_OVL_UPDATE 0x4927 +#define mmDCP5_PRESCALE_GRPH_CONTROL 0x492D +#define mmDCP5_PRESCALE_OVL_CONTROL 0x4931 +#define mmDCP5_PRESCALE_VALUES_GRPH_B 0x4930 +#define mmDCP5_PRESCALE_VALUES_GRPH_G 0x492F +#define mmDCP5_PRESCALE_VALUES_GRPH_R 0x492E +#define mmDCP5_PRESCALE_VALUES_OVL_CB 0x4932 +#define mmDCP5_PRESCALE_VALUES_OVL_CR 0x4934 +#define mmDCP5_PRESCALE_VALUES_OVL_Y 0x4933 +#define mmDCP5_REGAMMA_CNTLA_END_CNTL1 0x49A6 +#define mmDCP5_REGAMMA_CNTLA_END_CNTL2 0x49A7 +#define mmDCP5_REGAMMA_CNTLA_REGION_0_1 0x49A8 +#define mmDCP5_REGAMMA_CNTLA_REGION_10_11 0x49AD +#define mmDCP5_REGAMMA_CNTLA_REGION_12_13 0x49AE +#define mmDCP5_REGAMMA_CNTLA_REGION_14_15 0x49AF +#define mmDCP5_REGAMMA_CNTLA_REGION_2_3 0x49A9 +#define mmDCP5_REGAMMA_CNTLA_REGION_4_5 0x49AA +#define mmDCP5_REGAMMA_CNTLA_REGION_6_7 0x49AB +#define mmDCP5_REGAMMA_CNTLA_REGION_8_9 0x49AC +#define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL 0x49A5 +#define mmDCP5_REGAMMA_CNTLA_START_CNTL 0x49A4 +#define mmDCP5_REGAMMA_CNTLB_END_CNTL1 0x49B2 +#define mmDCP5_REGAMMA_CNTLB_END_CNTL2 0x49B3 +#define mmDCP5_REGAMMA_CNTLB_REGION_0_1 0x49B4 +#define mmDCP5_REGAMMA_CNTLB_REGION_10_11 0x49B9 +#define mmDCP5_REGAMMA_CNTLB_REGION_12_13 0x49BA +#define mmDCP5_REGAMMA_CNTLB_REGION_14_15 0x49BB +#define mmDCP5_REGAMMA_CNTLB_REGION_2_3 0x49B5 +#define mmDCP5_REGAMMA_CNTLB_REGION_4_5 0x49B6 +#define mmDCP5_REGAMMA_CNTLB_REGION_6_7 0x49B7 +#define mmDCP5_REGAMMA_CNTLB_REGION_8_9 0x49B8 +#define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL 0x49B1 +#define mmDCP5_REGAMMA_CNTLB_START_CNTL 0x49B0 +#define mmDCP5_REGAMMA_CONTROL 0x49A0 +#define mmDCP5_REGAMMA_LUT_DATA 0x49A2 +#define mmDCP5_REGAMMA_LUT_INDEX 0x49A1 +#define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK 0x49A3 +#define mmDC_PAD_EXTERN_SIG 0x1902 +#define mmDCP_CRC_CONTROL 0x1A87 +#define mmDCP_CRC_CURRENT 0x1A89 +#define mmDCP_CRC_LAST 0x1A8B +#define mmDCP_CRC_MASK 0x1A88 +#define mmDCP_DEBUG 0x1A8D +#define mmDCP_DEBUG2 0x1A98 +#define mmDCP_FP_CONVERTED_FIELD 0x1A65 +#define mmDC_PGCNTL_STATUS_REG 0x177E +#define mmDC_PGFSM_CONFIG_REG 0x177C +#define mmDC_PGFSM_WRITE_REG 0x177D +#define mmDCP_GSL_CONTROL 0x1A90 +#define mmDCPG_TEST_DEBUG_DATA 0x177B +#define mmDCPG_TEST_DEBUG_INDEX 0x1779 +#define mmDC_PINSTRAPS 0x1917 +#define mmDCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1A91 +#define mmDCP_RANDOM_SEEDS 0x1A61 +#define mmDCP_SPATIAL_DITHER_CNTL 0x1A60 +#define mmDCP_TEST_DEBUG_DATA 0x1A96 +#define mmDCP_TEST_DEBUG_INDEX 0x1A95 +#define mmDC_RBBMIF_RDWR_CNTL1 0x031A +#define mmDC_RBBMIF_RDWR_CNTL2 0x031D +#define mmDC_REF_CLK_CNTL 0x1903 +#define mmDC_XDMA_INTERFACE_CNTL 0x0327 +#define mmDEGAMMA_CONTROL 0x1A58 +#define mmDENORM_CONTROL 0x1A50 +#define mmDENTIST_DISPCLK_CNTL 0x0124 +#define mmDIG0_AFMT_60958_0 0x1C41 +#define mmDIG0_AFMT_60958_1 0x1C42 +#define mmDIG0_AFMT_60958_2 0x1C48 +#define mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x1C43 +#define mmDIG0_AFMT_AUDIO_CRC_RESULT 0x1C49 +#define mmDIG0_AFMT_AUDIO_DBG_DTO_CNTL 0x1C52 +#define mmDIG0_AFMT_AUDIO_INFO0 0x1C3F +#define mmDIG0_AFMT_AUDIO_INFO1 0x1C40 +#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x1C4B +#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x1C17 +#define mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x1C4F +#define mmDIG0_AFMT_AVI_INFO0 0x1C21 +#define mmDIG0_AFMT_AVI_INFO1 0x1C22 +#define mmDIG0_AFMT_AVI_INFO2 0x1C23 +#define mmDIG0_AFMT_AVI_INFO3 0x1C24 +#define mmDIG0_AFMT_GENERIC_0 0x1C28 +#define mmDIG0_AFMT_GENERIC_1 0x1C29 +#define mmDIG0_AFMT_GENERIC_2 0x1C2A +#define mmDIG0_AFMT_GENERIC_3 0x1C2B +#define mmDIG0_AFMT_GENERIC_4 0x1C2C +#define mmDIG0_AFMT_GENERIC_5 0x1C2D +#define mmDIG0_AFMT_GENERIC_6 0x1C2E +#define mmDIG0_AFMT_GENERIC_7 0x1C2F +#define mmDIG0_AFMT_GENERIC_HDR 0x1C27 +#define mmDIG0_AFMT_INFOFRAME_CONTROL0 0x1C4D +#define mmDIG0_AFMT_INTERRUPT_STATUS 0x1C14 +#define mmDIG0_AFMT_ISRC1_0 0x1C18 +#define mmDIG0_AFMT_ISRC1_1 0x1C19 +#define mmDIG0_AFMT_ISRC1_2 0x1C1A +#define mmDIG0_AFMT_ISRC1_3 0x1C1B +#define mmDIG0_AFMT_ISRC1_4 0x1C1C +#define mmDIG0_AFMT_ISRC2_0 0x1C1D +#define mmDIG0_AFMT_ISRC2_1 0x1C1E +#define mmDIG0_AFMT_ISRC2_2 0x1C1F +#define mmDIG0_AFMT_ISRC2_3 0x1C20 +#define mmDIG0_AFMT_MPEG_INFO0 0x1C25 +#define mmDIG0_AFMT_MPEG_INFO1 0x1C26 +#define mmDIG0_AFMT_RAMP_CONTROL0 0x1C44 +#define mmDIG0_AFMT_RAMP_CONTROL1 0x1C45 +#define mmDIG0_AFMT_RAMP_CONTROL2 0x1C46 +#define mmDIG0_AFMT_RAMP_CONTROL3 0x1C47 +#define mmDIG0_AFMT_STATUS 0x1C4A +#define mmDIG0_AFMT_VBI_PACKET_CONTROL 0x1C4C +#define mmDIG0_DIG_BE_CNTL 0x1C50 +#define mmDIG0_DIG_BE_EN_CNTL 0x1C51 +#define mmDIG0_DIG_CLOCK_PATTERN 0x1C03 +#define mmDIG0_DIG_DISPCLK_SWITCH_CNTL 0x1C08 +#define mmDIG0_DIG_DISPCLK_SWITCH_STATUS 0x1C09 +#define mmDIG0_DIG_FE_CNTL 0x1C00 +#define mmDIG0_DIG_FIFO_STATUS 0x1C0A +#define mmDIG0_DIG_LANE_ENABLE 0x1C8D +#define mmDIG0_DIG_OUTPUT_CRC_CNTL 0x1C01 +#define mmDIG0_DIG_OUTPUT_CRC_RESULT 0x1C02 +#define mmDIG0_DIG_RANDOM_PATTERN_SEED 0x1C05 +#define mmDIG0_DIG_TEST_PATTERN 0x1C04 +#define mmDIG0_HDMI_ACR_32_0 0x1C37 +#define mmDIG0_HDMI_ACR_32_1 0x1C38 +#define mmDIG0_HDMI_ACR_44_0 0x1C39 +#define mmDIG0_HDMI_ACR_44_1 0x1C3A +#define mmDIG0_HDMI_ACR_48_0 0x1C3B +#define mmDIG0_HDMI_ACR_48_1 0x1C3C +#define mmDIG0_HDMI_ACR_PACKET_CONTROL 0x1C0F +#define mmDIG0_HDMI_ACR_STATUS_0 0x1C3D +#define mmDIG0_HDMI_ACR_STATUS_1 0x1C3E +#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x1C0E +#define mmDIG0_HDMI_CONTROL 0x1C0C +#define mmDIG0_HDMI_GC 0x1C16 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x1C13 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x1C30 +#define mmDIG0_HDMI_INFOFRAME_CONTROL0 0x1C11 +#define mmDIG0_HDMI_INFOFRAME_CONTROL1 0x1C12 +#define mmDIG0_HDMI_STATUS 0x1C0D +#define mmDIG0_HDMI_VBI_PACKET_CONTROL 0x1C10 +#define mmDIG0_LVDS_DATA_CNTL 0x1C8C +#define mmDIG0_TMDS_CNTL 0x1C7C +#define mmDIG0_TMDS_CONTROL0_FEEDBACK 0x1C7E +#define mmDIG0_TMDS_CONTROL_CHAR 0x1C7D +#define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x1C86 +#define mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x1C87 +#define mmDIG0_TMDS_CTL_BITS 0x1C83 +#define mmDIG0_TMDS_DCBALANCER_CONTROL 0x1C84 +#define mmDIG0_TMDS_DEBUG 0x1C82 +#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x1C7F +#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x1C80 +#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x1C81 +#define mmDIG1_AFMT_60958_0 0x1F41 +#define mmDIG1_AFMT_60958_1 0x1F42 +#define mmDIG1_AFMT_60958_2 0x1F48 +#define mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x1F43 +#define mmDIG1_AFMT_AUDIO_CRC_RESULT 0x1F49 +#define mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL 0x1F52 +#define mmDIG1_AFMT_AUDIO_INFO0 0x1F3F +#define mmDIG1_AFMT_AUDIO_INFO1 0x1F40 +#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x1F4B +#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x1F17 +#define mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x1F4F +#define mmDIG1_AFMT_AVI_INFO0 0x1F21 +#define mmDIG1_AFMT_AVI_INFO1 0x1F22 +#define mmDIG1_AFMT_AVI_INFO2 0x1F23 +#define mmDIG1_AFMT_AVI_INFO3 0x1F24 +#define mmDIG1_AFMT_GENERIC_0 0x1F28 +#define mmDIG1_AFMT_GENERIC_1 0x1F29 +#define mmDIG1_AFMT_GENERIC_2 0x1F2A +#define mmDIG1_AFMT_GENERIC_3 0x1F2B +#define mmDIG1_AFMT_GENERIC_4 0x1F2C +#define mmDIG1_AFMT_GENERIC_5 0x1F2D +#define mmDIG1_AFMT_GENERIC_6 0x1F2E +#define mmDIG1_AFMT_GENERIC_7 0x1F2F +#define mmDIG1_AFMT_GENERIC_HDR 0x1F27 +#define mmDIG1_AFMT_INFOFRAME_CONTROL0 0x1F4D +#define mmDIG1_AFMT_INTERRUPT_STATUS 0x1F14 +#define mmDIG1_AFMT_ISRC1_0 0x1F18 +#define mmDIG1_AFMT_ISRC1_1 0x1F19 +#define mmDIG1_AFMT_ISRC1_2 0x1F1A +#define mmDIG1_AFMT_ISRC1_3 0x1F1B +#define mmDIG1_AFMT_ISRC1_4 0x1F1C +#define mmDIG1_AFMT_ISRC2_0 0x1F1D +#define mmDIG1_AFMT_ISRC2_1 0x1F1E +#define mmDIG1_AFMT_ISRC2_2 0x1F1F +#define mmDIG1_AFMT_ISRC2_3 0x1F20 +#define mmDIG1_AFMT_MPEG_INFO0 0x1F25 +#define mmDIG1_AFMT_MPEG_INFO1 0x1F26 +#define mmDIG1_AFMT_RAMP_CONTROL0 0x1F44 +#define mmDIG1_AFMT_RAMP_CONTROL1 0x1F45 +#define mmDIG1_AFMT_RAMP_CONTROL2 0x1F46 +#define mmDIG1_AFMT_RAMP_CONTROL3 0x1F47 +#define mmDIG1_AFMT_STATUS 0x1F4A +#define mmDIG1_AFMT_VBI_PACKET_CONTROL 0x1F4C +#define mmDIG1_DIG_BE_CNTL 0x1F50 +#define mmDIG1_DIG_BE_EN_CNTL 0x1F51 +#define mmDIG1_DIG_CLOCK_PATTERN 0x1F03 +#define mmDIG1_DIG_DISPCLK_SWITCH_CNTL 0x1F08 +#define mmDIG1_DIG_DISPCLK_SWITCH_STATUS 0x1F09 +#define mmDIG1_DIG_FE_CNTL 0x1F00 +#define mmDIG1_DIG_FIFO_STATUS 0x1F0A +#define mmDIG1_DIG_LANE_ENABLE 0x1F8D +#define mmDIG1_DIG_OUTPUT_CRC_CNTL 0x1F01 +#define mmDIG1_DIG_OUTPUT_CRC_RESULT 0x1F02 +#define mmDIG1_DIG_RANDOM_PATTERN_SEED 0x1F05 +#define mmDIG1_DIG_TEST_PATTERN 0x1F04 +#define mmDIG1_HDMI_ACR_32_0 0x1F37 +#define mmDIG1_HDMI_ACR_32_1 0x1F38 +#define mmDIG1_HDMI_ACR_44_0 0x1F39 +#define mmDIG1_HDMI_ACR_44_1 0x1F3A +#define mmDIG1_HDMI_ACR_48_0 0x1F3B +#define mmDIG1_HDMI_ACR_48_1 0x1F3C +#define mmDIG1_HDMI_ACR_PACKET_CONTROL 0x1F0F +#define mmDIG1_HDMI_ACR_STATUS_0 0x1F3D +#define mmDIG1_HDMI_ACR_STATUS_1 0x1F3E +#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x1F0E +#define mmDIG1_HDMI_CONTROL 0x1F0C +#define mmDIG1_HDMI_GC 0x1F16 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x1F13 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x1F30 +#define mmDIG1_HDMI_INFOFRAME_CONTROL0 0x1F11 +#define mmDIG1_HDMI_INFOFRAME_CONTROL1 0x1F12 +#define mmDIG1_HDMI_STATUS 0x1F0D +#define mmDIG1_HDMI_VBI_PACKET_CONTROL 0x1F10 +#define mmDIG1_LVDS_DATA_CNTL 0x1F8C +#define mmDIG1_TMDS_CNTL 0x1F7C +#define mmDIG1_TMDS_CONTROL0_FEEDBACK 0x1F7E +#define mmDIG1_TMDS_CONTROL_CHAR 0x1F7D +#define mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x1F86 +#define mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x1F87 +#define mmDIG1_TMDS_CTL_BITS 0x1F83 +#define mmDIG1_TMDS_DCBALANCER_CONTROL 0x1F84 +#define mmDIG1_TMDS_DEBUG 0x1F82 +#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x1F7F +#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x1F80 +#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x1F81 +#define mmDIG2_AFMT_60958_0 0x4241 +#define mmDIG2_AFMT_60958_1 0x4242 +#define mmDIG2_AFMT_60958_2 0x4248 +#define mmDIG2_AFMT_AUDIO_CRC_CONTROL 0x4243 +#define mmDIG2_AFMT_AUDIO_CRC_RESULT 0x4249 +#define mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL 0x4252 +#define mmDIG2_AFMT_AUDIO_INFO0 0x423F +#define mmDIG2_AFMT_AUDIO_INFO1 0x4240 +#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0x424B +#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0x4217 +#define mmDIG2_AFMT_AUDIO_SRC_CONTROL 0x424F +#define mmDIG2_AFMT_AVI_INFO0 0x4221 +#define mmDIG2_AFMT_AVI_INFO1 0x4222 +#define mmDIG2_AFMT_AVI_INFO2 0x4223 +#define mmDIG2_AFMT_AVI_INFO3 0x4224 +#define mmDIG2_AFMT_GENERIC_0 0x4228 +#define mmDIG2_AFMT_GENERIC_1 0x4229 +#define mmDIG2_AFMT_GENERIC_2 0x422A +#define mmDIG2_AFMT_GENERIC_3 0x422B +#define mmDIG2_AFMT_GENERIC_4 0x422C +#define mmDIG2_AFMT_GENERIC_5 0x422D +#define mmDIG2_AFMT_GENERIC_6 0x422E +#define mmDIG2_AFMT_GENERIC_7 0x422F +#define mmDIG2_AFMT_GENERIC_HDR 0x4227 +#define mmDIG2_AFMT_INFOFRAME_CONTROL0 0x424D +#define mmDIG2_AFMT_INTERRUPT_STATUS 0x4214 +#define mmDIG2_AFMT_ISRC1_0 0x4218 +#define mmDIG2_AFMT_ISRC1_1 0x4219 +#define mmDIG2_AFMT_ISRC1_2 0x421A +#define mmDIG2_AFMT_ISRC1_3 0x421B +#define mmDIG2_AFMT_ISRC1_4 0x421C +#define mmDIG2_AFMT_ISRC2_0 0x421D +#define mmDIG2_AFMT_ISRC2_1 0x421E +#define mmDIG2_AFMT_ISRC2_2 0x421F +#define mmDIG2_AFMT_ISRC2_3 0x4220 +#define mmDIG2_AFMT_MPEG_INFO0 0x4225 +#define mmDIG2_AFMT_MPEG_INFO1 0x4226 +#define mmDIG2_AFMT_RAMP_CONTROL0 0x4244 +#define mmDIG2_AFMT_RAMP_CONTROL1 0x4245 +#define mmDIG2_AFMT_RAMP_CONTROL2 0x4246 +#define mmDIG2_AFMT_RAMP_CONTROL3 0x4247 +#define mmDIG2_AFMT_STATUS 0x424A +#define mmDIG2_AFMT_VBI_PACKET_CONTROL 0x424C +#define mmDIG2_DIG_BE_CNTL 0x4250 +#define mmDIG2_DIG_BE_EN_CNTL 0x4251 +#define mmDIG2_DIG_CLOCK_PATTERN 0x4203 +#define mmDIG2_DIG_DISPCLK_SWITCH_CNTL 0x4208 +#define mmDIG2_DIG_DISPCLK_SWITCH_STATUS 0x4209 +#define mmDIG2_DIG_FE_CNTL 0x4200 +#define mmDIG2_DIG_FIFO_STATUS 0x420A +#define mmDIG2_DIG_LANE_ENABLE 0x428D +#define mmDIG2_DIG_OUTPUT_CRC_CNTL 0x4201 +#define mmDIG2_DIG_OUTPUT_CRC_RESULT 0x4202 +#define mmDIG2_DIG_RANDOM_PATTERN_SEED 0x4205 +#define mmDIG2_DIG_TEST_PATTERN 0x4204 +#define mmDIG2_HDMI_ACR_32_0 0x4237 +#define mmDIG2_HDMI_ACR_32_1 0x4238 +#define mmDIG2_HDMI_ACR_44_0 0x4239 +#define mmDIG2_HDMI_ACR_44_1 0x423A +#define mmDIG2_HDMI_ACR_48_0 0x423B +#define mmDIG2_HDMI_ACR_48_1 0x423C +#define mmDIG2_HDMI_ACR_PACKET_CONTROL 0x420F +#define mmDIG2_HDMI_ACR_STATUS_0 0x423D +#define mmDIG2_HDMI_ACR_STATUS_1 0x423E +#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x420E +#define mmDIG2_HDMI_CONTROL 0x420C +#define mmDIG2_HDMI_GC 0x4216 +#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x4213 +#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x4230 +#define mmDIG2_HDMI_INFOFRAME_CONTROL0 0x4211 +#define mmDIG2_HDMI_INFOFRAME_CONTROL1 0x4212 +#define mmDIG2_HDMI_STATUS 0x420D +#define mmDIG2_HDMI_VBI_PACKET_CONTROL 0x4210 +#define mmDIG2_LVDS_DATA_CNTL 0x428C +#define mmDIG2_TMDS_CNTL 0x427C +#define mmDIG2_TMDS_CONTROL0_FEEDBACK 0x427E +#define mmDIG2_TMDS_CONTROL_CHAR 0x427D +#define mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x4286 +#define mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x4287 +#define mmDIG2_TMDS_CTL_BITS 0x4283 +#define mmDIG2_TMDS_DCBALANCER_CONTROL 0x4284 +#define mmDIG2_TMDS_DEBUG 0x4282 +#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x427F +#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x4280 +#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x4281 +#define mmDIG3_AFMT_60958_0 0x4541 +#define mmDIG3_AFMT_60958_1 0x4542 +#define mmDIG3_AFMT_60958_2 0x4548 +#define mmDIG3_AFMT_AUDIO_CRC_CONTROL 0x4543 +#define mmDIG3_AFMT_AUDIO_CRC_RESULT 0x4549 +#define mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL 0x4552 +#define mmDIG3_AFMT_AUDIO_INFO0 0x453F +#define mmDIG3_AFMT_AUDIO_INFO1 0x4540 +#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0x454B +#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0x4517 +#define mmDIG3_AFMT_AUDIO_SRC_CONTROL 0x454F +#define mmDIG3_AFMT_AVI_INFO0 0x4521 +#define mmDIG3_AFMT_AVI_INFO1 0x4522 +#define mmDIG3_AFMT_AVI_INFO2 0x4523 +#define mmDIG3_AFMT_AVI_INFO3 0x4524 +#define mmDIG3_AFMT_GENERIC_0 0x4528 +#define mmDIG3_AFMT_GENERIC_1 0x4529 +#define mmDIG3_AFMT_GENERIC_2 0x452A +#define mmDIG3_AFMT_GENERIC_3 0x452B +#define mmDIG3_AFMT_GENERIC_4 0x452C +#define mmDIG3_AFMT_GENERIC_5 0x452D +#define mmDIG3_AFMT_GENERIC_6 0x452E +#define mmDIG3_AFMT_GENERIC_7 0x452F +#define mmDIG3_AFMT_GENERIC_HDR 0x4527 +#define mmDIG3_AFMT_INFOFRAME_CONTROL0 0x454D +#define mmDIG3_AFMT_INTERRUPT_STATUS 0x4514 +#define mmDIG3_AFMT_ISRC1_0 0x4518 +#define mmDIG3_AFMT_ISRC1_1 0x4519 +#define mmDIG3_AFMT_ISRC1_2 0x451A +#define mmDIG3_AFMT_ISRC1_3 0x451B +#define mmDIG3_AFMT_ISRC1_4 0x451C +#define mmDIG3_AFMT_ISRC2_0 0x451D +#define mmDIG3_AFMT_ISRC2_1 0x451E +#define mmDIG3_AFMT_ISRC2_2 0x451F +#define mmDIG3_AFMT_ISRC2_3 0x4520 +#define mmDIG3_AFMT_MPEG_INFO0 0x4525 +#define mmDIG3_AFMT_MPEG_INFO1 0x4526 +#define mmDIG3_AFMT_RAMP_CONTROL0 0x4544 +#define mmDIG3_AFMT_RAMP_CONTROL1 0x4545 +#define mmDIG3_AFMT_RAMP_CONTROL2 0x4546 +#define mmDIG3_AFMT_RAMP_CONTROL3 0x4547 +#define mmDIG3_AFMT_STATUS 0x454A +#define mmDIG3_AFMT_VBI_PACKET_CONTROL 0x454C +#define mmDIG3_DIG_BE_CNTL 0x4550 +#define mmDIG3_DIG_BE_EN_CNTL 0x4551 +#define mmDIG3_DIG_CLOCK_PATTERN 0x4503 +#define mmDIG3_DIG_DISPCLK_SWITCH_CNTL 0x4508 +#define mmDIG3_DIG_DISPCLK_SWITCH_STATUS 0x4509 +#define mmDIG3_DIG_FE_CNTL 0x4500 +#define mmDIG3_DIG_FIFO_STATUS 0x450A +#define mmDIG3_DIG_LANE_ENABLE 0x458D +#define mmDIG3_DIG_OUTPUT_CRC_CNTL 0x4501 +#define mmDIG3_DIG_OUTPUT_CRC_RESULT 0x4502 +#define mmDIG3_DIG_RANDOM_PATTERN_SEED 0x4505 +#define mmDIG3_DIG_TEST_PATTERN 0x4504 +#define mmDIG3_HDMI_ACR_32_0 0x4537 +#define mmDIG3_HDMI_ACR_32_1 0x4538 +#define mmDIG3_HDMI_ACR_44_0 0x4539 +#define mmDIG3_HDMI_ACR_44_1 0x453A +#define mmDIG3_HDMI_ACR_48_0 0x453B +#define mmDIG3_HDMI_ACR_48_1 0x453C +#define mmDIG3_HDMI_ACR_PACKET_CONTROL 0x450F +#define mmDIG3_HDMI_ACR_STATUS_0 0x453D +#define mmDIG3_HDMI_ACR_STATUS_1 0x453E +#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x450E +#define mmDIG3_HDMI_CONTROL 0x450C +#define mmDIG3_HDMI_GC 0x4516 +#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x4513 +#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x4530 +#define mmDIG3_HDMI_INFOFRAME_CONTROL0 0x4511 +#define mmDIG3_HDMI_INFOFRAME_CONTROL1 0x4512 +#define mmDIG3_HDMI_STATUS 0x450D +#define mmDIG3_HDMI_VBI_PACKET_CONTROL 0x4510 +#define mmDIG3_LVDS_DATA_CNTL 0x458C +#define mmDIG3_TMDS_CNTL 0x457C +#define mmDIG3_TMDS_CONTROL0_FEEDBACK 0x457E +#define mmDIG3_TMDS_CONTROL_CHAR 0x457D +#define mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x4586 +#define mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x4587 +#define mmDIG3_TMDS_CTL_BITS 0x4583 +#define mmDIG3_TMDS_DCBALANCER_CONTROL 0x4584 +#define mmDIG3_TMDS_DEBUG 0x4582 +#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x457F +#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x4580 +#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x4581 +#define mmDIG4_AFMT_60958_0 0x4841 +#define mmDIG4_AFMT_60958_1 0x4842 +#define mmDIG4_AFMT_60958_2 0x4848 +#define mmDIG4_AFMT_AUDIO_CRC_CONTROL 0x4843 +#define mmDIG4_AFMT_AUDIO_CRC_RESULT 0x4849 +#define mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL 0x4852 +#define mmDIG4_AFMT_AUDIO_INFO0 0x483F +#define mmDIG4_AFMT_AUDIO_INFO1 0x4840 +#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0x484B +#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0x4817 +#define mmDIG4_AFMT_AUDIO_SRC_CONTROL 0x484F +#define mmDIG4_AFMT_AVI_INFO0 0x4821 +#define mmDIG4_AFMT_AVI_INFO1 0x4822 +#define mmDIG4_AFMT_AVI_INFO2 0x4823 +#define mmDIG4_AFMT_AVI_INFO3 0x4824 +#define mmDIG4_AFMT_GENERIC_0 0x4828 +#define mmDIG4_AFMT_GENERIC_1 0x4829 +#define mmDIG4_AFMT_GENERIC_2 0x482A +#define mmDIG4_AFMT_GENERIC_3 0x482B +#define mmDIG4_AFMT_GENERIC_4 0x482C +#define mmDIG4_AFMT_GENERIC_5 0x482D +#define mmDIG4_AFMT_GENERIC_6 0x482E +#define mmDIG4_AFMT_GENERIC_7 0x482F +#define mmDIG4_AFMT_GENERIC_HDR 0x4827 +#define mmDIG4_AFMT_INFOFRAME_CONTROL0 0x484D +#define mmDIG4_AFMT_INTERRUPT_STATUS 0x4814 +#define mmDIG4_AFMT_ISRC1_0 0x4818 +#define mmDIG4_AFMT_ISRC1_1 0x4819 +#define mmDIG4_AFMT_ISRC1_2 0x481A +#define mmDIG4_AFMT_ISRC1_3 0x481B +#define mmDIG4_AFMT_ISRC1_4 0x481C +#define mmDIG4_AFMT_ISRC2_0 0x481D +#define mmDIG4_AFMT_ISRC2_1 0x481E +#define mmDIG4_AFMT_ISRC2_2 0x481F +#define mmDIG4_AFMT_ISRC2_3 0x4820 +#define mmDIG4_AFMT_MPEG_INFO0 0x4825 +#define mmDIG4_AFMT_MPEG_INFO1 0x4826 +#define mmDIG4_AFMT_RAMP_CONTROL0 0x4844 +#define mmDIG4_AFMT_RAMP_CONTROL1 0x4845 +#define mmDIG4_AFMT_RAMP_CONTROL2 0x4846 +#define mmDIG4_AFMT_RAMP_CONTROL3 0x4847 +#define mmDIG4_AFMT_STATUS 0x484A +#define mmDIG4_AFMT_VBI_PACKET_CONTROL 0x484C +#define mmDIG4_DIG_BE_CNTL 0x4850 +#define mmDIG4_DIG_BE_EN_CNTL 0x4851 +#define mmDIG4_DIG_CLOCK_PATTERN 0x4803 +#define mmDIG4_DIG_DISPCLK_SWITCH_CNTL 0x4808 +#define mmDIG4_DIG_DISPCLK_SWITCH_STATUS 0x4809 +#define mmDIG4_DIG_FE_CNTL 0x4800 +#define mmDIG4_DIG_FIFO_STATUS 0x480A +#define mmDIG4_DIG_LANE_ENABLE 0x488D +#define mmDIG4_DIG_OUTPUT_CRC_CNTL 0x4801 +#define mmDIG4_DIG_OUTPUT_CRC_RESULT 0x4802 +#define mmDIG4_DIG_RANDOM_PATTERN_SEED 0x4805 +#define mmDIG4_DIG_TEST_PATTERN 0x4804 +#define mmDIG4_HDMI_ACR_32_0 0x4837 +#define mmDIG4_HDMI_ACR_32_1 0x4838 +#define mmDIG4_HDMI_ACR_44_0 0x4839 +#define mmDIG4_HDMI_ACR_44_1 0x483A +#define mmDIG4_HDMI_ACR_48_0 0x483B +#define mmDIG4_HDMI_ACR_48_1 0x483C +#define mmDIG4_HDMI_ACR_PACKET_CONTROL 0x480F +#define mmDIG4_HDMI_ACR_STATUS_0 0x483D +#define mmDIG4_HDMI_ACR_STATUS_1 0x483E +#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x480E +#define mmDIG4_HDMI_CONTROL 0x480C +#define mmDIG4_HDMI_GC 0x4816 +#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x4813 +#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x4830 +#define mmDIG4_HDMI_INFOFRAME_CONTROL0 0x4811 +#define mmDIG4_HDMI_INFOFRAME_CONTROL1 0x4812 +#define mmDIG4_HDMI_STATUS 0x480D +#define mmDIG4_HDMI_VBI_PACKET_CONTROL 0x4810 +#define mmDIG4_LVDS_DATA_CNTL 0x488C +#define mmDIG4_TMDS_CNTL 0x487C +#define mmDIG4_TMDS_CONTROL0_FEEDBACK 0x487E +#define mmDIG4_TMDS_CONTROL_CHAR 0x487D +#define mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x4886 +#define mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x4887 +#define mmDIG4_TMDS_CTL_BITS 0x4883 +#define mmDIG4_TMDS_DCBALANCER_CONTROL 0x4884 +#define mmDIG4_TMDS_DEBUG 0x4882 +#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x487F +#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x4880 +#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x4881 +#define mmDIG5_AFMT_60958_0 0x4B41 +#define mmDIG5_AFMT_60958_1 0x4B42 +#define mmDIG5_AFMT_60958_2 0x4B48 +#define mmDIG5_AFMT_AUDIO_CRC_CONTROL 0x4B43 +#define mmDIG5_AFMT_AUDIO_CRC_RESULT 0x4B49 +#define mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL 0x4B52 +#define mmDIG5_AFMT_AUDIO_INFO0 0x4B3F +#define mmDIG5_AFMT_AUDIO_INFO1 0x4B40 +#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0x4B4B +#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0x4B17 +#define mmDIG5_AFMT_AUDIO_SRC_CONTROL 0x4B4F +#define mmDIG5_AFMT_AVI_INFO0 0x4B21 +#define mmDIG5_AFMT_AVI_INFO1 0x4B22 +#define mmDIG5_AFMT_AVI_INFO2 0x4B23 +#define mmDIG5_AFMT_AVI_INFO3 0x4B24 +#define mmDIG5_AFMT_GENERIC_0 0x4B28 +#define mmDIG5_AFMT_GENERIC_1 0x4B29 +#define mmDIG5_AFMT_GENERIC_2 0x4B2A +#define mmDIG5_AFMT_GENERIC_3 0x4B2B +#define mmDIG5_AFMT_GENERIC_4 0x4B2C +#define mmDIG5_AFMT_GENERIC_5 0x4B2D +#define mmDIG5_AFMT_GENERIC_6 0x4B2E +#define mmDIG5_AFMT_GENERIC_7 0x4B2F +#define mmDIG5_AFMT_GENERIC_HDR 0x4B27 +#define mmDIG5_AFMT_INFOFRAME_CONTROL0 0x4B4D +#define mmDIG5_AFMT_INTERRUPT_STATUS 0x4B14 +#define mmDIG5_AFMT_ISRC1_0 0x4B18 +#define mmDIG5_AFMT_ISRC1_1 0x4B19 +#define mmDIG5_AFMT_ISRC1_2 0x4B1A +#define mmDIG5_AFMT_ISRC1_3 0x4B1B +#define mmDIG5_AFMT_ISRC1_4 0x4B1C +#define mmDIG5_AFMT_ISRC2_0 0x4B1D +#define mmDIG5_AFMT_ISRC2_1 0x4B1E +#define mmDIG5_AFMT_ISRC2_2 0x4B1F +#define mmDIG5_AFMT_ISRC2_3 0x4B20 +#define mmDIG5_AFMT_MPEG_INFO0 0x4B25 +#define mmDIG5_AFMT_MPEG_INFO1 0x4B26 +#define mmDIG5_AFMT_RAMP_CONTROL0 0x4B44 +#define mmDIG5_AFMT_RAMP_CONTROL1 0x4B45 +#define mmDIG5_AFMT_RAMP_CONTROL2 0x4B46 +#define mmDIG5_AFMT_RAMP_CONTROL3 0x4B47 +#define mmDIG5_AFMT_STATUS 0x4B4A +#define mmDIG5_AFMT_VBI_PACKET_CONTROL 0x4B4C +#define mmDIG5_DIG_BE_CNTL 0x4B50 +#define mmDIG5_DIG_BE_EN_CNTL 0x4B51 +#define mmDIG5_DIG_CLOCK_PATTERN 0x4B03 +#define mmDIG5_DIG_DISPCLK_SWITCH_CNTL 0x4B08 +#define mmDIG5_DIG_DISPCLK_SWITCH_STATUS 0x4B09 +#define mmDIG5_DIG_FE_CNTL 0x4B00 +#define mmDIG5_DIG_FIFO_STATUS 0x4B0A +#define mmDIG5_DIG_LANE_ENABLE 0x4B8D +#define mmDIG5_DIG_OUTPUT_CRC_CNTL 0x4B01 +#define mmDIG5_DIG_OUTPUT_CRC_RESULT 0x4B02 +#define mmDIG5_DIG_RANDOM_PATTERN_SEED 0x4B05 +#define mmDIG5_DIG_TEST_PATTERN 0x4B04 +#define mmDIG5_HDMI_ACR_32_0 0x4B37 +#define mmDIG5_HDMI_ACR_32_1 0x4B38 +#define mmDIG5_HDMI_ACR_44_0 0x4B39 +#define mmDIG5_HDMI_ACR_44_1 0x4B3A +#define mmDIG5_HDMI_ACR_48_0 0x4B3B +#define mmDIG5_HDMI_ACR_48_1 0x4B3C +#define mmDIG5_HDMI_ACR_PACKET_CONTROL 0x4B0F +#define mmDIG5_HDMI_ACR_STATUS_0 0x4B3D +#define mmDIG5_HDMI_ACR_STATUS_1 0x4B3E +#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x4B0E +#define mmDIG5_HDMI_CONTROL 0x4B0C +#define mmDIG5_HDMI_GC 0x4B16 +#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x4B13 +#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x4B30 +#define mmDIG5_HDMI_INFOFRAME_CONTROL0 0x4B11 +#define mmDIG5_HDMI_INFOFRAME_CONTROL1 0x4B12 +#define mmDIG5_HDMI_STATUS 0x4B0D +#define mmDIG5_HDMI_VBI_PACKET_CONTROL 0x4B10 +#define mmDIG5_LVDS_DATA_CNTL 0x4B8C +#define mmDIG5_TMDS_CNTL 0x4B7C +#define mmDIG5_TMDS_CONTROL0_FEEDBACK 0x4B7E +#define mmDIG5_TMDS_CONTROL_CHAR 0x4B7D +#define mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x4B86 +#define mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x4B87 +#define mmDIG5_TMDS_CTL_BITS 0x4B83 +#define mmDIG5_TMDS_DCBALANCER_CONTROL 0x4B84 +#define mmDIG5_TMDS_DEBUG 0x4B82 +#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x4B7F +#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x4B80 +#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x4B81 +#define mmDIG_BE_CNTL 0x1C50 +#define mmDIG_BE_EN_CNTL 0x1C51 +#define mmDIG_CLOCK_PATTERN 0x1C03 +#define mmDIG_DISPCLK_SWITCH_CNTL 0x1C08 +#define mmDIG_DISPCLK_SWITCH_STATUS 0x1C09 +#define mmDIG_FE_CNTL 0x1C00 +#define mmDIG_FIFO_STATUS 0x1C0A +#define mmDIG_LANE_ENABLE 0x1C8D +#define mmDIG_OUTPUT_CRC_CNTL 0x1C01 +#define mmDIG_OUTPUT_CRC_RESULT 0x1C02 +#define mmDIG_RANDOM_PATTERN_SEED 0x1C05 +#define mmDIG_SOFT_RESET 0x013D +#define mmDIG_TEST_PATTERN 0x1C04 +#define mmDISPCLK_CGTT_BLK_CTRL_REG 0x0135 +#define mmDISPCLK_FREQ_CHANGE_CNTL 0x0131 +#define mmDISP_INTERRUPT_STATUS 0x183D +#define mmDISP_INTERRUPT_STATUS_CONTINUE 0x183E +#define mmDISP_INTERRUPT_STATUS_CONTINUE2 0x183F +#define mmDISP_INTERRUPT_STATUS_CONTINUE3 0x1840 +#define mmDISP_INTERRUPT_STATUS_CONTINUE4 0x1853 +#define mmDISP_INTERRUPT_STATUS_CONTINUE5 0x1854 +#define mmDISPOUT_STEREOSYNC_SEL 0x18BF +#define mmDISPPLL_BG_CNTL 0x013C +#define mmDISP_TIMER_CONTROL 0x1842 +#define mmDMCU_CTRL 0x1600 +#define mmDMCU_ERAM_RD_CTRL 0x160B +#define mmDMCU_ERAM_RD_DATA 0x160C +#define mmDMCU_ERAM_WR_CTRL 0x1609 +#define mmDMCU_ERAM_WR_DATA 0x160A +#define mmDMCU_EVENT_TRIGGER 0x1611 +#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x161A +#define mmDMCU_FW_CS_HI 0x1606 +#define mmDMCU_FW_CS_LO 0x1607 +#define mmDMCU_FW_END_ADDR 0x1604 +#define mmDMCU_FW_ISR_START_ADDR 0x1605 +#define mmDMCU_FW_START_ADDR 0x1603 +#define mmDMCU_INT_CNT 0x1619 +#define mmDMCU_INTERRUPT_STATUS 0x1614 +#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x1615 +#define mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x1616 +#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x1617 +#define mmDMCU_IRAM_RD_CTRL 0x160F +#define mmDMCU_IRAM_RD_DATA 0x1610 +#define mmDMCU_IRAM_WR_CTRL 0x160D +#define mmDMCU_IRAM_WR_DATA 0x160E +#define mmDMCU_PC_START_ADDR 0x1602 +#define mmDMCU_RAM_ACCESS_CTRL 0x1608 +#define mmDMCU_STATUS 0x1601 +#define mmDMCU_TEST_DEBUG_DATA 0x1627 +#define mmDMCU_TEST_DEBUG_INDEX 0x1626 +#define mmDMCU_UC_CLK_GATING_CNTL 0x161B +#define mmDMCU_UC_INTERNAL_INT_STATUS 0x1612 +#define mmDMIF_ADDR_CALC 0x0300 +#define mmDMIF_ADDR_CONFIG 0x02F5 +#define mmDMIF_ARBITRATION_CONTROL 0x02F9 +#define mmDMIF_CONTROL 0x02F6 +#define mmDMIF_HW_DEBUG 0x02F8 +#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 0x1B30 +#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2 0x1B31 +#define mmDMIF_PG0_DPG_PIPE_DPM_CONTROL 0x1B34 +#define mmDMIF_PG0_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1B36 +#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL 0x1B35 +#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1B37 +#define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL 0x1B33 +#define mmDMIF_PG0_DPG_TEST_DEBUG_DATA 0x1B39 +#define mmDMIF_PG0_DPG_TEST_DEBUG_INDEX 0x1B38 +#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1 0x1E30 +#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2 0x1E31 +#define mmDMIF_PG1_DPG_PIPE_DPM_CONTROL 0x1E34 +#define mmDMIF_PG1_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1E36 +#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL 0x1E35 +#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1E37 +#define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL 0x1E33 +#define mmDMIF_PG1_DPG_TEST_DEBUG_DATA 0x1E39 +#define mmDMIF_PG1_DPG_TEST_DEBUG_INDEX 0x1E38 +#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1 0x4130 +#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2 0x4131 +#define mmDMIF_PG2_DPG_PIPE_DPM_CONTROL 0x4134 +#define mmDMIF_PG2_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4136 +#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL 0x4135 +#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4137 +#define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL 0x4133 +#define mmDMIF_PG2_DPG_TEST_DEBUG_DATA 0x4139 +#define mmDMIF_PG2_DPG_TEST_DEBUG_INDEX 0x4138 +#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1 0x4430 +#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2 0x4431 +#define mmDMIF_PG3_DPG_PIPE_DPM_CONTROL 0x4434 +#define mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4436 +#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL 0x4435 +#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4437 +#define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL 0x4433 +#define mmDMIF_PG3_DPG_TEST_DEBUG_DATA 0x4439 +#define mmDMIF_PG3_DPG_TEST_DEBUG_INDEX 0x4438 +#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1 0x4730 +#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2 0x4731 +#define mmDMIF_PG4_DPG_PIPE_DPM_CONTROL 0x4734 +#define mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4736 +#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL 0x4735 +#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4737 +#define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL 0x4733 +#define mmDMIF_PG4_DPG_TEST_DEBUG_DATA 0x4739 +#define mmDMIF_PG4_DPG_TEST_DEBUG_INDEX 0x4738 +#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1 0x4A30 +#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2 0x4A31 +#define mmDMIF_PG5_DPG_PIPE_DPM_CONTROL 0x4A34 +#define mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4A36 +#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL 0x4A35 +#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4A37 +#define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL 0x4A33 +#define mmDMIF_PG5_DPG_TEST_DEBUG_DATA 0x4A39 +#define mmDMIF_PG5_DPG_TEST_DEBUG_INDEX 0x4A38 +#define mmDMIF_STATUS 0x02F7 +#define mmDMIF_STATUS2 0x0301 +#define mmDMIF_TEST_DEBUG_DATA 0x0313 +#define mmDMIF_TEST_DEBUG_INDEX 0x0312 +#define mmDOUT_DCE_VCE_CONTROL 0x18FF +#define mmDOUT_POWER_MANAGEMENT_CNTL 0x1841 +#define mmDOUT_SCRATCH0 0x1844 +#define mmDOUT_SCRATCH1 0x1845 +#define mmDOUT_SCRATCH2 0x1846 +#define mmDOUT_SCRATCH3 0x1847 +#define mmDOUT_SCRATCH4 0x1848 +#define mmDOUT_SCRATCH5 0x1849 +#define mmDOUT_SCRATCH6 0x184A +#define mmDOUT_SCRATCH7 0x184B +#define mmDOUT_TEST_DEBUG_DATA 0x184E +#define mmDOUT_TEST_DEBUG_INDEX 0x184D +#define mmDP0_DP_CONFIG 0x1CC2 +#define mmDP0_DP_DPHY_8B10B_CNTL 0x1CD3 +#define mmDP0_DP_DPHY_CNTL 0x1CD0 +#define mmDP0_DP_DPHY_CRC_CNTL 0x1CD7 +#define mmDP0_DP_DPHY_CRC_EN 0x1CD6 +#define mmDP0_DP_DPHY_CRC_MST_CNTL 0x1CC6 +#define mmDP0_DP_DPHY_CRC_MST_STATUS 0x1CC7 +#define mmDP0_DP_DPHY_CRC_RESULT 0x1CD8 +#define mmDP0_DP_DPHY_FAST_TRAINING 0x1CCE +#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x1CE9 +#define mmDP0_DP_DPHY_PRBS_CNTL 0x1CD4 +#define mmDP0_DP_DPHY_SYM0 0x1CD2 +#define mmDP0_DP_DPHY_SYM1 0x1CE0 +#define mmDP0_DP_DPHY_SYM2 0x1CDF +#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x1CD1 +#define mmDP0_DP_HBR2_EYE_PATTERN 0x1CC8 +#define mmDP0_DP_LINK_CNTL 0x1CC0 +#define mmDP0_DP_LINK_FRAMING_CNTL 0x1CCC +#define mmDP0_DP_MSA_COLORIMETRY 0x1CDA +#define mmDP0_DP_MSA_MISC 0x1CC5 +#define mmDP0_DP_MSA_V_TIMING_OVERRIDE1 0x1CEA +#define mmDP0_DP_MSA_V_TIMING_OVERRIDE2 0x1CEB +#define mmDP0_DP_MSE_LINK_TIMING 0x1CE8 +#define mmDP0_DP_MSE_MISC_CNTL 0x1CDB +#define mmDP0_DP_MSE_RATE_CNTL 0x1CE1 +#define mmDP0_DP_MSE_RATE_UPDATE 0x1CE3 +#define mmDP0_DP_MSE_SAT0 0x1CE4 +#define mmDP0_DP_MSE_SAT1 0x1CE5 +#define mmDP0_DP_MSE_SAT2 0x1CE6 +#define mmDP0_DP_MSE_SAT_UPDATE 0x1CE7 +#define mmDP0_DP_PIXEL_FORMAT 0x1CC1 +#define mmDP0_DP_SEC_AUD_M 0x1CA7 +#define mmDP0_DP_SEC_AUD_M_READBACK 0x1CA8 +#define mmDP0_DP_SEC_AUD_N 0x1CA5 +#define mmDP0_DP_SEC_AUD_N_READBACK 0x1CA6 +#define mmDP0_DP_SEC_CNTL 0x1CA0 +#define mmDP0_DP_SEC_CNTL1 0x1CAB +#define mmDP0_DP_SEC_FRAMING1 0x1CA1 +#define mmDP0_DP_SEC_FRAMING2 0x1CA2 +#define mmDP0_DP_SEC_FRAMING3 0x1CA3 +#define mmDP0_DP_SEC_FRAMING4 0x1CA4 +#define mmDP0_DP_SEC_PACKET_CNTL 0x1CAA +#define mmDP0_DP_SEC_TIMESTAMP 0x1CA9 +#define mmDP0_DP_STEER_FIFO 0x1CC4 +#define mmDP0_DP_TEST_DEBUG_DATA 0x1CFD +#define mmDP0_DP_TEST_DEBUG_INDEX 0x1CFC +#define mmDP0_DP_VID_INTERRUPT_CNTL 0x1CCF +#define mmDP0_DP_VID_M 0x1CCB +#define mmDP0_DP_VID_MSA_VBID 0x1CCD +#define mmDP0_DP_VID_N 0x1CCA +#define mmDP0_DP_VID_STREAM_CNTL 0x1CC3 +#define mmDP0_DP_VID_TIMING 0x1CC9 +#define mmDP1_DP_CONFIG 0x1FC2 +#define mmDP1_DP_DPHY_8B10B_CNTL 0x1FD3 +#define mmDP1_DP_DPHY_CNTL 0x1FD0 +#define mmDP1_DP_DPHY_CRC_CNTL 0x1FD7 +#define mmDP1_DP_DPHY_CRC_EN 0x1FD6 +#define mmDP1_DP_DPHY_CRC_MST_CNTL 0x1FC6 +#define mmDP1_DP_DPHY_CRC_MST_STATUS 0x1FC7 +#define mmDP1_DP_DPHY_CRC_RESULT 0x1FD8 +#define mmDP1_DP_DPHY_FAST_TRAINING 0x1FCE +#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x1FE9 +#define mmDP1_DP_DPHY_PRBS_CNTL 0x1FD4 +#define mmDP1_DP_DPHY_SYM0 0x1FD2 +#define mmDP1_DP_DPHY_SYM1 0x1FE0 +#define mmDP1_DP_DPHY_SYM2 0x1FDF +#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x1FD1 +#define mmDP1_DP_HBR2_EYE_PATTERN 0x1FC8 +#define mmDP1_DP_LINK_CNTL 0x1FC0 +#define mmDP1_DP_LINK_FRAMING_CNTL 0x1FCC +#define mmDP1_DP_MSA_COLORIMETRY 0x1FDA +#define mmDP1_DP_MSA_MISC 0x1FC5 +#define mmDP1_DP_MSA_V_TIMING_OVERRIDE1 0x1FEA +#define mmDP1_DP_MSA_V_TIMING_OVERRIDE2 0x1FEB +#define mmDP1_DP_MSE_LINK_TIMING 0x1FE8 +#define mmDP1_DP_MSE_MISC_CNTL 0x1FDB +#define mmDP1_DP_MSE_RATE_CNTL 0x1FE1 +#define mmDP1_DP_MSE_RATE_UPDATE 0x1FE3 +#define mmDP1_DP_MSE_SAT0 0x1FE4 +#define mmDP1_DP_MSE_SAT1 0x1FE5 +#define mmDP1_DP_MSE_SAT2 0x1FE6 +#define mmDP1_DP_MSE_SAT_UPDATE 0x1FE7 +#define mmDP1_DP_PIXEL_FORMAT 0x1FC1 +#define mmDP1_DP_SEC_AUD_M 0x1FA7 +#define mmDP1_DP_SEC_AUD_M_READBACK 0x1FA8 +#define mmDP1_DP_SEC_AUD_N 0x1FA5 +#define mmDP1_DP_SEC_AUD_N_READBACK 0x1FA6 +#define mmDP1_DP_SEC_CNTL 0x1FA0 +#define mmDP1_DP_SEC_CNTL1 0x1FAB +#define mmDP1_DP_SEC_FRAMING1 0x1FA1 +#define mmDP1_DP_SEC_FRAMING2 0x1FA2 +#define mmDP1_DP_SEC_FRAMING3 0x1FA3 +#define mmDP1_DP_SEC_FRAMING4 0x1FA4 +#define mmDP1_DP_SEC_PACKET_CNTL 0x1FAA +#define mmDP1_DP_SEC_TIMESTAMP 0x1FA9 +#define mmDP1_DP_STEER_FIFO 0x1FC4 +#define mmDP1_DP_TEST_DEBUG_DATA 0x1FFD +#define mmDP1_DP_TEST_DEBUG_INDEX 0x1FFC +#define mmDP1_DP_VID_INTERRUPT_CNTL 0x1FCF +#define mmDP1_DP_VID_M 0x1FCB +#define mmDP1_DP_VID_MSA_VBID 0x1FCD +#define mmDP1_DP_VID_N 0x1FCA +#define mmDP1_DP_VID_STREAM_CNTL 0x1FC3 +#define mmDP1_DP_VID_TIMING 0x1FC9 +#define mmDP2_DP_CONFIG 0x42C2 +#define mmDP2_DP_DPHY_8B10B_CNTL 0x42D3 +#define mmDP2_DP_DPHY_CNTL 0x42D0 +#define mmDP2_DP_DPHY_CRC_CNTL 0x42D7 +#define mmDP2_DP_DPHY_CRC_EN 0x42D6 +#define mmDP2_DP_DPHY_CRC_MST_CNTL 0x42C6 +#define mmDP2_DP_DPHY_CRC_MST_STATUS 0x42C7 +#define mmDP2_DP_DPHY_CRC_RESULT 0x42D8 +#define mmDP2_DP_DPHY_FAST_TRAINING 0x42CE +#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x42E9 +#define mmDP2_DP_DPHY_PRBS_CNTL 0x42D4 +#define mmDP2_DP_DPHY_SYM0 0x42D2 +#define mmDP2_DP_DPHY_SYM1 0x42E0 +#define mmDP2_DP_DPHY_SYM2 0x42DF +#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x42D1 +#define mmDP2_DP_HBR2_EYE_PATTERN 0x42C8 +#define mmDP2_DP_LINK_CNTL 0x42C0 +#define mmDP2_DP_LINK_FRAMING_CNTL 0x42CC +#define mmDP2_DP_MSA_COLORIMETRY 0x42DA +#define mmDP2_DP_MSA_MISC 0x42C5 +#define mmDP2_DP_MSA_V_TIMING_OVERRIDE1 0x42EA +#define mmDP2_DP_MSA_V_TIMING_OVERRIDE2 0x42EB +#define mmDP2_DP_MSE_LINK_TIMING 0x42E8 +#define mmDP2_DP_MSE_MISC_CNTL 0x42DB +#define mmDP2_DP_MSE_RATE_CNTL 0x42E1 +#define mmDP2_DP_MSE_RATE_UPDATE 0x42E3 +#define mmDP2_DP_MSE_SAT0 0x42E4 +#define mmDP2_DP_MSE_SAT1 0x42E5 +#define mmDP2_DP_MSE_SAT2 0x42E6 +#define mmDP2_DP_MSE_SAT_UPDATE 0x42E7 +#define mmDP2_DP_PIXEL_FORMAT 0x42C1 +#define mmDP2_DP_SEC_AUD_M 0x42A7 +#define mmDP2_DP_SEC_AUD_M_READBACK 0x42A8 +#define mmDP2_DP_SEC_AUD_N 0x42A5 +#define mmDP2_DP_SEC_AUD_N_READBACK 0x42A6 +#define mmDP2_DP_SEC_CNTL 0x42A0 +#define mmDP2_DP_SEC_CNTL1 0x42AB +#define mmDP2_DP_SEC_FRAMING1 0x42A1 +#define mmDP2_DP_SEC_FRAMING2 0x42A2 +#define mmDP2_DP_SEC_FRAMING3 0x42A3 +#define mmDP2_DP_SEC_FRAMING4 0x42A4 +#define mmDP2_DP_SEC_PACKET_CNTL 0x42AA +#define mmDP2_DP_SEC_TIMESTAMP 0x42A9 +#define mmDP2_DP_STEER_FIFO 0x42C4 +#define mmDP2_DP_TEST_DEBUG_DATA 0x42FD +#define mmDP2_DP_TEST_DEBUG_INDEX 0x42FC +#define mmDP2_DP_VID_INTERRUPT_CNTL 0x42CF +#define mmDP2_DP_VID_M 0x42CB +#define mmDP2_DP_VID_MSA_VBID 0x42CD +#define mmDP2_DP_VID_N 0x42CA +#define mmDP2_DP_VID_STREAM_CNTL 0x42C3 +#define mmDP2_DP_VID_TIMING 0x42C9 +#define mmDP3_DP_CONFIG 0x45C2 +#define mmDP3_DP_DPHY_8B10B_CNTL 0x45D3 +#define mmDP3_DP_DPHY_CNTL 0x45D0 +#define mmDP3_DP_DPHY_CRC_CNTL 0x45D7 +#define mmDP3_DP_DPHY_CRC_EN 0x45D6 +#define mmDP3_DP_DPHY_CRC_MST_CNTL 0x45C6 +#define mmDP3_DP_DPHY_CRC_MST_STATUS 0x45C7 +#define mmDP3_DP_DPHY_CRC_RESULT 0x45D8 +#define mmDP3_DP_DPHY_FAST_TRAINING 0x45CE +#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x45E9 +#define mmDP3_DP_DPHY_PRBS_CNTL 0x45D4 +#define mmDP3_DP_DPHY_SYM0 0x45D2 +#define mmDP3_DP_DPHY_SYM1 0x45E0 +#define mmDP3_DP_DPHY_SYM2 0x45DF +#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x45D1 +#define mmDP3_DP_HBR2_EYE_PATTERN 0x45C8 +#define mmDP3_DP_LINK_CNTL 0x45C0 +#define mmDP3_DP_LINK_FRAMING_CNTL 0x45CC +#define mmDP3_DP_MSA_COLORIMETRY 0x45DA +#define mmDP3_DP_MSA_MISC 0x45C5 +#define mmDP3_DP_MSA_V_TIMING_OVERRIDE1 0x45EA +#define mmDP3_DP_MSA_V_TIMING_OVERRIDE2 0x45EB +#define mmDP3_DP_MSE_LINK_TIMING 0x45E8 +#define mmDP3_DP_MSE_MISC_CNTL 0x45DB +#define mmDP3_DP_MSE_RATE_CNTL 0x45E1 +#define mmDP3_DP_MSE_RATE_UPDATE 0x45E3 +#define mmDP3_DP_MSE_SAT0 0x45E4 +#define mmDP3_DP_MSE_SAT1 0x45E5 +#define mmDP3_DP_MSE_SAT2 0x45E6 +#define mmDP3_DP_MSE_SAT_UPDATE 0x45E7 +#define mmDP3_DP_PIXEL_FORMAT 0x45C1 +#define mmDP3_DP_SEC_AUD_M 0x45A7 +#define mmDP3_DP_SEC_AUD_M_READBACK 0x45A8 +#define mmDP3_DP_SEC_AUD_N 0x45A5 +#define mmDP3_DP_SEC_AUD_N_READBACK 0x45A6 +#define mmDP3_DP_SEC_CNTL 0x45A0 +#define mmDP3_DP_SEC_CNTL1 0x45AB +#define mmDP3_DP_SEC_FRAMING1 0x45A1 +#define mmDP3_DP_SEC_FRAMING2 0x45A2 +#define mmDP3_DP_SEC_FRAMING3 0x45A3 +#define mmDP3_DP_SEC_FRAMING4 0x45A4 +#define mmDP3_DP_SEC_PACKET_CNTL 0x45AA +#define mmDP3_DP_SEC_TIMESTAMP 0x45A9 +#define mmDP3_DP_STEER_FIFO 0x45C4 +#define mmDP3_DP_TEST_DEBUG_DATA 0x45FD +#define mmDP3_DP_TEST_DEBUG_INDEX 0x45FC +#define mmDP3_DP_VID_INTERRUPT_CNTL 0x45CF +#define mmDP3_DP_VID_M 0x45CB +#define mmDP3_DP_VID_MSA_VBID 0x45CD +#define mmDP3_DP_VID_N 0x45CA +#define mmDP3_DP_VID_STREAM_CNTL 0x45C3 +#define mmDP3_DP_VID_TIMING 0x45C9 +#define mmDP4_DP_CONFIG 0x48C2 +#define mmDP4_DP_DPHY_8B10B_CNTL 0x48D3 +#define mmDP4_DP_DPHY_CNTL 0x48D0 +#define mmDP4_DP_DPHY_CRC_CNTL 0x48D7 +#define mmDP4_DP_DPHY_CRC_EN 0x48D6 +#define mmDP4_DP_DPHY_CRC_MST_CNTL 0x48C6 +#define mmDP4_DP_DPHY_CRC_MST_STATUS 0x48C7 +#define mmDP4_DP_DPHY_CRC_RESULT 0x48D8 +#define mmDP4_DP_DPHY_FAST_TRAINING 0x48CE +#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x48E9 +#define mmDP4_DP_DPHY_PRBS_CNTL 0x48D4 +#define mmDP4_DP_DPHY_SYM0 0x48D2 +#define mmDP4_DP_DPHY_SYM1 0x48E0 +#define mmDP4_DP_DPHY_SYM2 0x48DF +#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x48D1 +#define mmDP4_DP_HBR2_EYE_PATTERN 0x48C8 +#define mmDP4_DP_LINK_CNTL 0x48C0 +#define mmDP4_DP_LINK_FRAMING_CNTL 0x48CC +#define mmDP4_DP_MSA_COLORIMETRY 0x48DA +#define mmDP4_DP_MSA_MISC 0x48C5 +#define mmDP4_DP_MSA_V_TIMING_OVERRIDE1 0x48EA +#define mmDP4_DP_MSA_V_TIMING_OVERRIDE2 0x48EB +#define mmDP4_DP_MSE_LINK_TIMING 0x48E8 +#define mmDP4_DP_MSE_MISC_CNTL 0x48DB +#define mmDP4_DP_MSE_RATE_CNTL 0x48E1 +#define mmDP4_DP_MSE_RATE_UPDATE 0x48E3 +#define mmDP4_DP_MSE_SAT0 0x48E4 +#define mmDP4_DP_MSE_SAT1 0x48E5 +#define mmDP4_DP_MSE_SAT2 0x48E6 +#define mmDP4_DP_MSE_SAT_UPDATE 0x48E7 +#define mmDP4_DP_PIXEL_FORMAT 0x48C1 +#define mmDP4_DP_SEC_AUD_M 0x48A7 +#define mmDP4_DP_SEC_AUD_M_READBACK 0x48A8 +#define mmDP4_DP_SEC_AUD_N 0x48A5 +#define mmDP4_DP_SEC_AUD_N_READBACK 0x48A6 +#define mmDP4_DP_SEC_CNTL 0x48A0 +#define mmDP4_DP_SEC_CNTL1 0x48AB +#define mmDP4_DP_SEC_FRAMING1 0x48A1 +#define mmDP4_DP_SEC_FRAMING2 0x48A2 +#define mmDP4_DP_SEC_FRAMING3 0x48A3 +#define mmDP4_DP_SEC_FRAMING4 0x48A4 +#define mmDP4_DP_SEC_PACKET_CNTL 0x48AA +#define mmDP4_DP_SEC_TIMESTAMP 0x48A9 +#define mmDP4_DP_STEER_FIFO 0x48C4 +#define mmDP4_DP_TEST_DEBUG_DATA 0x48FD +#define mmDP4_DP_TEST_DEBUG_INDEX 0x48FC +#define mmDP4_DP_VID_INTERRUPT_CNTL 0x48CF +#define mmDP4_DP_VID_M 0x48CB +#define mmDP4_DP_VID_MSA_VBID 0x48CD +#define mmDP4_DP_VID_N 0x48CA +#define mmDP4_DP_VID_STREAM_CNTL 0x48C3 +#define mmDP4_DP_VID_TIMING 0x48C9 +#define mmDP5_DP_CONFIG 0x4BC2 +#define mmDP5_DP_DPHY_8B10B_CNTL 0x4BD3 +#define mmDP5_DP_DPHY_CNTL 0x4BD0 +#define mmDP5_DP_DPHY_CRC_CNTL 0x4BD7 +#define mmDP5_DP_DPHY_CRC_EN 0x4BD6 +#define mmDP5_DP_DPHY_CRC_MST_CNTL 0x4BC6 +#define mmDP5_DP_DPHY_CRC_MST_STATUS 0x4BC7 +#define mmDP5_DP_DPHY_CRC_RESULT 0x4BD8 +#define mmDP5_DP_DPHY_FAST_TRAINING 0x4BCE +#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x4BE9 +#define mmDP5_DP_DPHY_PRBS_CNTL 0x4BD4 +#define mmDP5_DP_DPHY_SYM0 0x4BD2 +#define mmDP5_DP_DPHY_SYM1 0x4BE0 +#define mmDP5_DP_DPHY_SYM2 0x4BDF +#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x4BD1 +#define mmDP5_DP_HBR2_EYE_PATTERN 0x4BC8 +#define mmDP5_DP_LINK_CNTL 0x4BC0 +#define mmDP5_DP_LINK_FRAMING_CNTL 0x4BCC +#define mmDP5_DP_MSA_COLORIMETRY 0x4BDA +#define mmDP5_DP_MSA_MISC 0x4BC5 +#define mmDP5_DP_MSA_V_TIMING_OVERRIDE1 0x4BEA +#define mmDP5_DP_MSA_V_TIMING_OVERRIDE2 0x4BEB +#define mmDP5_DP_MSE_LINK_TIMING 0x4BE8 +#define mmDP5_DP_MSE_MISC_CNTL 0x4BDB +#define mmDP5_DP_MSE_RATE_CNTL 0x4BE1 +#define mmDP5_DP_MSE_RATE_UPDATE 0x4BE3 +#define mmDP5_DP_MSE_SAT0 0x4BE4 +#define mmDP5_DP_MSE_SAT1 0x4BE5 +#define mmDP5_DP_MSE_SAT2 0x4BE6 +#define mmDP5_DP_MSE_SAT_UPDATE 0x4BE7 +#define mmDP5_DP_PIXEL_FORMAT 0x4BC1 +#define mmDP5_DP_SEC_AUD_M 0x4BA7 +#define mmDP5_DP_SEC_AUD_M_READBACK 0x4BA8 +#define mmDP5_DP_SEC_AUD_N 0x4BA5 +#define mmDP5_DP_SEC_AUD_N_READBACK 0x4BA6 +#define mmDP5_DP_SEC_CNTL 0x4BA0 +#define mmDP5_DP_SEC_CNTL1 0x4BAB +#define mmDP5_DP_SEC_FRAMING1 0x4BA1 +#define mmDP5_DP_SEC_FRAMING2 0x4BA2 +#define mmDP5_DP_SEC_FRAMING3 0x4BA3 +#define mmDP5_DP_SEC_FRAMING4 0x4BA4 +#define mmDP5_DP_SEC_PACKET_CNTL 0x4BAA +#define mmDP5_DP_SEC_TIMESTAMP 0x4BA9 +#define mmDP5_DP_STEER_FIFO 0x4BC4 +#define mmDP5_DP_TEST_DEBUG_DATA 0x4BFD +#define mmDP5_DP_TEST_DEBUG_INDEX 0x4BFC +#define mmDP5_DP_VID_INTERRUPT_CNTL 0x4BCF +#define mmDP5_DP_VID_M 0x4BCB +#define mmDP5_DP_VID_MSA_VBID 0x4BCD +#define mmDP5_DP_VID_N 0x4BCA +#define mmDP5_DP_VID_STREAM_CNTL 0x4BC3 +#define mmDP5_DP_VID_TIMING 0x4BC9 +#define mmDP_AUX0_AUX_ARB_CONTROL 0x1882 +#define mmDP_AUX0_AUX_CONTROL 0x1880 +#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x188A +#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x188B +#define mmDP_AUX0_AUX_DPHY_RX_STATUS 0x188D +#define mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x1889 +#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x1888 +#define mmDP_AUX0_AUX_DPHY_TX_STATUS 0x188C +#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL 0x188E +#define mmDP_AUX0_AUX_GTC_SYNC_DATA 0x1890 +#define mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x1883 +#define mmDP_AUX0_AUX_LS_DATA 0x1887 +#define mmDP_AUX0_AUX_LS_STATUS 0x1885 +#define mmDP_AUX0_AUX_SW_CONTROL 0x1881 +#define mmDP_AUX0_AUX_SW_DATA 0x1886 +#define mmDP_AUX0_AUX_SW_STATUS 0x1884 +#define mmDP_AUX1_AUX_ARB_CONTROL 0x1896 +#define mmDP_AUX1_AUX_CONTROL 0x1894 +#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x189E +#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x189F +#define mmDP_AUX1_AUX_DPHY_RX_STATUS 0x18A1 +#define mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x189D +#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x189C +#define mmDP_AUX1_AUX_DPHY_TX_STATUS 0x18A0 +#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL 0x18A2 +#define mmDP_AUX1_AUX_GTC_SYNC_DATA 0x18A4 +#define mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x1897 +#define mmDP_AUX1_AUX_LS_DATA 0x189B +#define mmDP_AUX1_AUX_LS_STATUS 0x1899 +#define mmDP_AUX1_AUX_SW_CONTROL 0x1895 +#define mmDP_AUX1_AUX_SW_DATA 0x189A +#define mmDP_AUX1_AUX_SW_STATUS 0x1898 +#define mmDP_AUX2_AUX_ARB_CONTROL 0x18AA +#define mmDP_AUX2_AUX_CONTROL 0x18A8 +#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x18B2 +#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x18B3 +#define mmDP_AUX2_AUX_DPHY_RX_STATUS 0x18B5 +#define mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x18B1 +#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x18B0 +#define mmDP_AUX2_AUX_DPHY_TX_STATUS 0x18B4 +#define mmDP_AUX2_AUX_GTC_SYNC_CONTROL 0x18B6 +#define mmDP_AUX2_AUX_GTC_SYNC_DATA 0x18B8 +#define mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x18AB +#define mmDP_AUX2_AUX_LS_DATA 0x18AF +#define mmDP_AUX2_AUX_LS_STATUS 0x18AD +#define mmDP_AUX2_AUX_SW_CONTROL 0x18A9 +#define mmDP_AUX2_AUX_SW_DATA 0x18AE +#define mmDP_AUX2_AUX_SW_STATUS 0x18AC +#define mmDP_AUX3_AUX_ARB_CONTROL 0x18C2 +#define mmDP_AUX3_AUX_CONTROL 0x18C0 +#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x18CA +#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x18CB +#define mmDP_AUX3_AUX_DPHY_RX_STATUS 0x18CD +#define mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x18C9 +#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x18C8 +#define mmDP_AUX3_AUX_DPHY_TX_STATUS 0x18CC +#define mmDP_AUX3_AUX_GTC_SYNC_CONTROL 0x18CE +#define mmDP_AUX3_AUX_GTC_SYNC_DATA 0x18D0 +#define mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x18C3 +#define mmDP_AUX3_AUX_LS_DATA 0x18C7 +#define mmDP_AUX3_AUX_LS_STATUS 0x18C5 +#define mmDP_AUX3_AUX_SW_CONTROL 0x18C1 +#define mmDP_AUX3_AUX_SW_DATA 0x18C6 +#define mmDP_AUX3_AUX_SW_STATUS 0x18C4 +#define mmDP_AUX4_AUX_ARB_CONTROL 0x18D6 +#define mmDP_AUX4_AUX_CONTROL 0x18D4 +#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x18DE +#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x18DF +#define mmDP_AUX4_AUX_DPHY_RX_STATUS 0x18E1 +#define mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x18DD +#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x18DC +#define mmDP_AUX4_AUX_DPHY_TX_STATUS 0x18E0 +#define mmDP_AUX4_AUX_GTC_SYNC_CONTROL 0x18E2 +#define mmDP_AUX4_AUX_GTC_SYNC_DATA 0x18E4 +#define mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x18D7 +#define mmDP_AUX4_AUX_LS_DATA 0x18DB +#define mmDP_AUX4_AUX_LS_STATUS 0x18D9 +#define mmDP_AUX4_AUX_SW_CONTROL 0x18D5 +#define mmDP_AUX4_AUX_SW_DATA 0x18DA +#define mmDP_AUX4_AUX_SW_STATUS 0x18D8 +#define mmDP_AUX5_AUX_ARB_CONTROL 0x18EA +#define mmDP_AUX5_AUX_CONTROL 0x18E8 +#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x18F2 +#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x18F3 +#define mmDP_AUX5_AUX_DPHY_RX_STATUS 0x18F5 +#define mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x18F1 +#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x18F0 +#define mmDP_AUX5_AUX_DPHY_TX_STATUS 0x18F4 +#define mmDP_AUX5_AUX_GTC_SYNC_CONTROL 0x18F6 +#define mmDP_AUX5_AUX_GTC_SYNC_DATA 0x18F8 +#define mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x18EB +#define mmDP_AUX5_AUX_LS_DATA 0x18EF +#define mmDP_AUX5_AUX_LS_STATUS 0x18ED +#define mmDP_AUX5_AUX_SW_CONTROL 0x18E9 +#define mmDP_AUX5_AUX_SW_DATA 0x18EE +#define mmDP_AUX5_AUX_SW_STATUS 0x18EC +#define mmDP_CONFIG 0x1CC2 +#define mmDP_DPHY_8B10B_CNTL 0x1CD3 +#define mmDP_DPHY_CNTL 0x1CD0 +#define mmDP_DPHY_CRC_CNTL 0x1CD7 +#define mmDP_DPHY_CRC_EN 0x1CD6 +#define mmDP_DPHY_CRC_MST_CNTL 0x1CC6 +#define mmDP_DPHY_CRC_MST_STATUS 0x1CC7 +#define mmDP_DPHY_CRC_RESULT 0x1CD8 +#define mmDP_DPHY_FAST_TRAINING 0x1CCE +#define mmDP_DPHY_FAST_TRAINING_STATUS 0x1CE9 +#define mmDP_DPHY_PRBS_CNTL 0x1CD4 +#define mmDP_DPHY_SYM0 0x1CD2 +#define mmDP_DPHY_SYM1 0x1CE0 +#define mmDP_DPHY_SYM2 0x1CDF +#define mmDP_DPHY_TRAINING_PATTERN_SEL 0x1CD1 +#define mmDP_DTO0_MODULO 0x0142 +#define mmDP_DTO0_PHASE 0x0141 +#define mmDP_DTO1_MODULO 0x0146 +#define mmDP_DTO1_PHASE 0x0145 +#define mmDP_DTO2_MODULO 0x014A +#define mmDP_DTO2_PHASE 0x0149 +#define mmDP_DTO3_MODULO 0x014E +#define mmDP_DTO3_PHASE 0x014D +#define mmDP_DTO4_MODULO 0x0152 +#define mmDP_DTO4_PHASE 0x0151 +#define mmDP_DTO5_MODULO 0x0156 +#define mmDP_DTO5_PHASE 0x0155 +#define mmDPG_PIPE_ARBITRATION_CONTROL1 0x1B30 +#define mmDPG_PIPE_ARBITRATION_CONTROL2 0x1B31 +#define mmDPG_PIPE_DPM_CONTROL 0x1B34 +#define mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1B36 +#define mmDPG_PIPE_STUTTER_CONTROL 0x1B35 +#define mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1B37 +#define mmDPG_PIPE_URGENCY_CONTROL 0x1B33 +#define mmDPG_TEST_DEBUG_DATA 0x1B39 +#define mmDPG_TEST_DEBUG_INDEX 0x1B38 +#define mmDP_HBR2_EYE_PATTERN 0x1CC8 +#define mmDP_LINK_CNTL 0x1CC0 +#define mmDP_LINK_FRAMING_CNTL 0x1CCC +#define mmDP_MSA_COLORIMETRY 0x1CDA +#define mmDP_MSA_MISC 0x1CC5 +#define mmDP_MSA_V_TIMING_OVERRIDE1 0x1CEA +#define mmDP_MSA_V_TIMING_OVERRIDE2 0x1CEB +#define mmDP_MSE_LINK_TIMING 0x1CE8 +#define mmDP_MSE_MISC_CNTL 0x1CDB +#define mmDP_MSE_RATE_CNTL 0x1CE1 +#define mmDP_MSE_RATE_UPDATE 0x1CE3 +#define mmDP_MSE_SAT0 0x1CE4 +#define mmDP_MSE_SAT1 0x1CE5 +#define mmDP_MSE_SAT2 0x1CE6 +#define mmDP_MSE_SAT_UPDATE 0x1CE7 +#define mmDP_PIXEL_FORMAT 0x1CC1 +#define mmDP_SEC_AUD_M 0x1CA7 +#define mmDP_SEC_AUD_M_READBACK 0x1CA8 +#define mmDP_SEC_AUD_N 0x1CA5 +#define mmDP_SEC_AUD_N_READBACK 0x1CA6 +#define mmDP_SEC_CNTL 0x1CA0 +#define mmDP_SEC_CNTL1 0x1CAB +#define mmDP_SEC_FRAMING1 0x1CA1 +#define mmDP_SEC_FRAMING2 0x1CA2 +#define mmDP_SEC_FRAMING3 0x1CA3 +#define mmDP_SEC_FRAMING4 0x1CA4 +#define mmDP_SEC_PACKET_CNTL 0x1CAA +#define mmDP_SEC_TIMESTAMP 0x1CA9 +#define mmDP_STEER_FIFO 0x1CC4 +#define mmDP_TEST_DEBUG_DATA 0x1CFD +#define mmDP_TEST_DEBUG_INDEX 0x1CFC +#define mmDP_VID_INTERRUPT_CNTL 0x1CCF +#define mmDP_VID_M 0x1CCB +#define mmDP_VID_MSA_VBID 0x1CCD +#define mmDP_VID_N 0x1CCA +#define mmDP_VID_STREAM_CNTL 0x1CC3 +#define mmDP_VID_TIMING 0x1CC9 +#define mmDVOACLKC_CNTL 0x016A +#define mmDVOACLKC_MVP_CNTL 0x0169 +#define mmDVOACLKD_CNTL 0x0168 +#define mmDVO_CLK_ENABLE 0x0129 +#define mmDVO_CONTROL 0x185B +#define mmDVO_CRC2_SIG_MASK 0x185D +#define mmDVO_CRC2_SIG_RESULT 0x185E +#define mmDVO_CRC_EN 0x185C +#define mmDVO_ENABLE 0x1858 +#define mmDVO_FIFO_ERROR_STATUS 0x185F +#define mmDVO_OUTPUT 0x185A +#define mmDVO_SKEW_ADJUST 0x197D +#define mmDVO_SOURCE_SELECT 0x1859 +#define mmDVO_STRENGTH_CONTROL 0x197B +#define mmDVO_VREF_CONTROL 0x197C +#define mmEXT_OVERSCAN_LEFT_RIGHT 0x1B5E +#define mmEXT_OVERSCAN_TOP_BOTTOM 0x1B5F +#define mmFBC_CLIENT_REGION_MASK 0x16EB +#define mmFBC_CNTL 0x16D0 +#define mmFBC_COMP_CNTL 0x16D4 +#define mmFBC_COMP_MODE 0x16D5 +#define mmFBC_CSM_REGION_OFFSET_01 0x16E9 +#define mmFBC_CSM_REGION_OFFSET_23 0x16EA +#define mmFBC_DEBUG0 0x16D6 +#define mmFBC_DEBUG1 0x16D7 +#define mmFBC_DEBUG2 0x16D8 +#define mmFBC_DEBUG_COMP 0x16EC +#define mmFBC_DEBUG_CSR 0x16ED +#define mmFBC_DEBUG_CSR_RDATA 0x16EE +#define mmFBC_DEBUG_CSR_RDATA_HI 0x16F6 +#define mmFBC_DEBUG_CSR_WDATA 0x16EF +#define mmFBC_DEBUG_CSR_WDATA_HI 0x16F7 +#define mmFBC_IDLE_FORCE_CLEAR_MASK 0x16D2 +#define mmFBC_IDLE_MASK 0x16D1 +#define mmFBC_IND_LUT0 0x16D9 +#define mmFBC_IND_LUT10 0x16E3 +#define mmFBC_IND_LUT1 0x16DA +#define mmFBC_IND_LUT11 0x16E4 +#define mmFBC_IND_LUT12 0x16E5 +#define mmFBC_IND_LUT13 0x16E6 +#define mmFBC_IND_LUT14 0x16E7 +#define mmFBC_IND_LUT15 0x16E8 +#define mmFBC_IND_LUT2 0x16DB +#define mmFBC_IND_LUT3 0x16DC +#define mmFBC_IND_LUT4 0x16DD +#define mmFBC_IND_LUT5 0x16DE +#define mmFBC_IND_LUT6 0x16DF +#define mmFBC_IND_LUT7 0x16E0 +#define mmFBC_IND_LUT8 0x16E1 +#define mmFBC_IND_LUT9 0x16E2 +#define mmFBC_MISC 0x16F0 +#define mmFBC_START_STOP_DELAY 0x16D3 +#define mmFBC_STATUS 0x16F1 +#define mmFBC_TEST_DEBUG_DATA 0x16F5 +#define mmFBC_TEST_DEBUG_INDEX 0x16F4 +#define mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1BF2 +#define mmFMT0_FMT_CLAMP_CNTL 0x1BF9 +#define mmFMT0_FMT_CONTROL 0x1BEE +#define mmFMT0_FMT_CRC_CNTL 0x1BFA +#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL 0x1BFE +#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1BFC +#define mmFMT0_FMT_CRC_SIG_RED_GREEN 0x1BFD +#define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK 0x1BFB +#define mmFMT0_FMT_DEBUG_CNTL 0x1BFF +#define mmFMT0_FMT_DITHER_RAND_B_SEED 0x1BF5 +#define mmFMT0_FMT_DITHER_RAND_G_SEED 0x1BF4 +#define mmFMT0_FMT_DITHER_RAND_R_SEED 0x1BF3 +#define mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x1BED +#define mmFMT0_FMT_FORCE_DATA_0_1 0x1BF0 +#define mmFMT0_FMT_FORCE_DATA_2_3 0x1BF1 +#define mmFMT0_FMT_FORCE_OUTPUT_CNTL 0x1BEF +#define mmFMT0_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1BF6 +#define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1BF7 +#define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1BF8 +#define mmFMT0_FMT_TEST_DEBUG_DATA 0x1BEC +#define mmFMT0_FMT_TEST_DEBUG_INDEX 0x1BEB +#define mmFMT1_FMT_BIT_DEPTH_CONTROL 0x1EF2 +#define mmFMT1_FMT_CLAMP_CNTL 0x1EF9 +#define mmFMT1_FMT_CONTROL 0x1EEE +#define mmFMT1_FMT_CRC_CNTL 0x1EFA +#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL 0x1EFE +#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1EFC +#define mmFMT1_FMT_CRC_SIG_RED_GREEN 0x1EFD +#define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK 0x1EFB +#define mmFMT1_FMT_DEBUG_CNTL 0x1EFF +#define mmFMT1_FMT_DITHER_RAND_B_SEED 0x1EF5 +#define mmFMT1_FMT_DITHER_RAND_G_SEED 0x1EF4 +#define mmFMT1_FMT_DITHER_RAND_R_SEED 0x1EF3 +#define mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1EED +#define mmFMT1_FMT_FORCE_DATA_0_1 0x1EF0 +#define mmFMT1_FMT_FORCE_DATA_2_3 0x1EF1 +#define mmFMT1_FMT_FORCE_OUTPUT_CNTL 0x1EEF +#define mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1EF6 +#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1EF7 +#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1EF8 +#define mmFMT1_FMT_TEST_DEBUG_DATA 0x1EEC +#define mmFMT1_FMT_TEST_DEBUG_INDEX 0x1EEB +#define mmFMT2_FMT_BIT_DEPTH_CONTROL 0x41F2 +#define mmFMT2_FMT_CLAMP_CNTL 0x41F9 +#define mmFMT2_FMT_CONTROL 0x41EE +#define mmFMT2_FMT_CRC_CNTL 0x41FA +#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL 0x41FE +#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x41FC +#define mmFMT2_FMT_CRC_SIG_RED_GREEN 0x41FD +#define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK 0x41FB +#define mmFMT2_FMT_DEBUG_CNTL 0x41FF +#define mmFMT2_FMT_DITHER_RAND_B_SEED 0x41F5 +#define mmFMT2_FMT_DITHER_RAND_G_SEED 0x41F4 +#define mmFMT2_FMT_DITHER_RAND_R_SEED 0x41F3 +#define mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x41ED +#define mmFMT2_FMT_FORCE_DATA_0_1 0x41F0 +#define mmFMT2_FMT_FORCE_DATA_2_3 0x41F1 +#define mmFMT2_FMT_FORCE_OUTPUT_CNTL 0x41EF +#define mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x41F6 +#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x41F7 +#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x41F8 +#define mmFMT2_FMT_TEST_DEBUG_DATA 0x41EC +#define mmFMT2_FMT_TEST_DEBUG_INDEX 0x41EB +#define mmFMT3_FMT_BIT_DEPTH_CONTROL 0x44F2 +#define mmFMT3_FMT_CLAMP_CNTL 0x44F9 +#define mmFMT3_FMT_CONTROL 0x44EE +#define mmFMT3_FMT_CRC_CNTL 0x44FA +#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL 0x44FE +#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x44FC +#define mmFMT3_FMT_CRC_SIG_RED_GREEN 0x44FD +#define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK 0x44FB +#define mmFMT3_FMT_DEBUG_CNTL 0x44FF +#define mmFMT3_FMT_DITHER_RAND_B_SEED 0x44F5 +#define mmFMT3_FMT_DITHER_RAND_G_SEED 0x44F4 +#define mmFMT3_FMT_DITHER_RAND_R_SEED 0x44F3 +#define mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x44ED +#define mmFMT3_FMT_FORCE_DATA_0_1 0x44F0 +#define mmFMT3_FMT_FORCE_DATA_2_3 0x44F1 +#define mmFMT3_FMT_FORCE_OUTPUT_CNTL 0x44EF +#define mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x44F6 +#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x44F7 +#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x44F8 +#define mmFMT3_FMT_TEST_DEBUG_DATA 0x44EC +#define mmFMT3_FMT_TEST_DEBUG_INDEX 0x44EB +#define mmFMT4_FMT_BIT_DEPTH_CONTROL 0x47F2 +#define mmFMT4_FMT_CLAMP_CNTL 0x47F9 +#define mmFMT4_FMT_CONTROL 0x47EE +#define mmFMT4_FMT_CRC_CNTL 0x47FA +#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL 0x47FE +#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x47FC +#define mmFMT4_FMT_CRC_SIG_RED_GREEN 0x47FD +#define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK 0x47FB +#define mmFMT4_FMT_DEBUG_CNTL 0x47FF +#define mmFMT4_FMT_DITHER_RAND_B_SEED 0x47F5 +#define mmFMT4_FMT_DITHER_RAND_G_SEED 0x47F4 +#define mmFMT4_FMT_DITHER_RAND_R_SEED 0x47F3 +#define mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x47ED +#define mmFMT4_FMT_FORCE_DATA_0_1 0x47F0 +#define mmFMT4_FMT_FORCE_DATA_2_3 0x47F1 +#define mmFMT4_FMT_FORCE_OUTPUT_CNTL 0x47EF +#define mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x47F6 +#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x47F7 +#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x47F8 +#define mmFMT4_FMT_TEST_DEBUG_DATA 0x47EC +#define mmFMT4_FMT_TEST_DEBUG_INDEX 0x47EB +#define mmFMT5_FMT_BIT_DEPTH_CONTROL 0x4AF2 +#define mmFMT5_FMT_CLAMP_CNTL 0x4AF9 +#define mmFMT5_FMT_CONTROL 0x4AEE +#define mmFMT5_FMT_CRC_CNTL 0x4AFA +#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL 0x4AFE +#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x4AFC +#define mmFMT5_FMT_CRC_SIG_RED_GREEN 0x4AFD +#define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK 0x4AFB +#define mmFMT5_FMT_DEBUG_CNTL 0x4AFF +#define mmFMT5_FMT_DITHER_RAND_B_SEED 0x4AF5 +#define mmFMT5_FMT_DITHER_RAND_G_SEED 0x4AF4 +#define mmFMT5_FMT_DITHER_RAND_R_SEED 0x4AF3 +#define mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x4AED +#define mmFMT5_FMT_FORCE_DATA_0_1 0x4AF0 +#define mmFMT5_FMT_FORCE_DATA_2_3 0x4AF1 +#define mmFMT5_FMT_FORCE_OUTPUT_CNTL 0x4AEF +#define mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x4AF6 +#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x4AF7 +#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x4AF8 +#define mmFMT5_FMT_TEST_DEBUG_DATA 0x4AEC +#define mmFMT5_FMT_TEST_DEBUG_INDEX 0x4AEB +#define mmFMT_BIT_DEPTH_CONTROL 0x1BF2 +#define mmFMT_CLAMP_CNTL 0x1BF9 +#define mmFMT_CONTROL 0x1BEE +#define mmFMT_CRC_CNTL 0x1BFA +#define mmFMT_CRC_SIG_BLUE_CONTROL 0x1BFE +#define mmFMT_CRC_SIG_BLUE_CONTROL_MASK 0x1BFC +#define mmFMT_CRC_SIG_RED_GREEN 0x1BFD +#define mmFMT_CRC_SIG_RED_GREEN_MASK 0x1BFB +#define mmFMT_DEBUG_CNTL 0x1BFF +#define mmFMT_DITHER_RAND_B_SEED 0x1BF5 +#define mmFMT_DITHER_RAND_G_SEED 0x1BF4 +#define mmFMT_DITHER_RAND_R_SEED 0x1BF3 +#define mmFMT_DYNAMIC_EXP_CNTL 0x1BED +#define mmFMT_FORCE_DATA_0_1 0x1BF0 +#define mmFMT_FORCE_DATA_2_3 0x1BF1 +#define mmFMT_FORCE_OUTPUT_CNTL 0x1BEF +#define mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1BF6 +#define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1BF7 +#define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1BF8 +#define mmFMT_TEST_DEBUG_DATA 0x1BEC +#define mmFMT_TEST_DEBUG_INDEX 0x1BEB +#define mmGAMUT_REMAP_C11_C12 0x1A5A +#define mmGAMUT_REMAP_C13_C14 0x1A5B +#define mmGAMUT_REMAP_C21_C22 0x1A5C +#define mmGAMUT_REMAP_C23_C24 0x1A5D +#define mmGAMUT_REMAP_C31_C32 0x1A5E +#define mmGAMUT_REMAP_C33_C34 0x1A5F +#define mmGAMUT_REMAP_CONTROL 0x1A59 +#define mmGENENB 0x00F0 +#define mmGENERIC_I2C_CONTROL 0x1834 +#define mmGENERIC_I2C_DATA 0x183A +#define mmGENERIC_I2C_INTERRUPT_CONTROL 0x1835 +#define mmGENERIC_I2C_PIN_DEBUG 0x183C +#define mmGENERIC_I2C_PIN_SELECTION 0x183B +#define mmGENERIC_I2C_SETUP 0x1838 +#define mmGENERIC_I2C_SPEED 0x1837 +#define mmGENERIC_I2C_STATUS 0x1836 +#define mmGENERIC_I2C_TRANSACTION 0x1839 +#define mmGENFC_RD 0x00F2 +#define mmGENFC_WT 0x00EE +#define mmGENMO_RD 0x00F3 +#define mmGENMO_WT 0x00F0 +#define mmGENS0 0x00F0 +#define mmGENS1 0x00EE +#define mmGRPH8_DATA 0x00F3 +#define mmGRPH8_IDX 0x00F3 +#define mmGRPH_COMPRESS_PITCH 0x1A1A +#define mmGRPH_COMPRESS_SURFACE_ADDRESS 0x1A19 +#define mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1A1B +#define mmGRPH_CONTROL 0x1A01 +#define mmGRPH_DFQ_CONTROL 0x1A14 +#define mmGRPH_DFQ_STATUS 0x1A15 +#define mmGRPH_ENABLE 0x1A00 +#define mmGRPH_FLIP_CONTROL 0x1A12 +#define mmGRPH_INTERRUPT_CONTROL 0x1A17 +#define mmGRPH_INTERRUPT_STATUS 0x1A16 +#define mmGRPH_LUT_10BIT_BYPASS 0x1A02 +#define mmGRPH_PITCH 0x1A06 +#define mmGRPH_PRIMARY_SURFACE_ADDRESS 0x1A04 +#define mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1A07 +#define mmGRPH_SECONDARY_SURFACE_ADDRESS 0x1A05 +#define mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1A08 +#define mmGRPH_STEREOSYNC_FLIP 0x1A97 +#define mmGRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1A18 +#define mmGRPH_SURFACE_ADDRESS_INUSE 0x1A13 +#define mmGRPH_SURFACE_OFFSET_X 0x1A09 +#define mmGRPH_SURFACE_OFFSET_Y 0x1A0A +#define mmGRPH_SWAP_CNTL 0x1A03 +#define mmGRPH_UPDATE 0x1A11 +#define mmGRPH_X_END 0x1A0D +#define mmGRPH_X_START 0x1A0B +#define mmGRPH_Y_END 0x1A0E +#define mmGRPH_Y_START 0x1A0C +#define mmHDMI_ACR_32_0 0x1C37 +#define mmHDMI_ACR_32_1 0x1C38 +#define mmHDMI_ACR_44_0 0x1C39 +#define mmHDMI_ACR_44_1 0x1C3A +#define mmHDMI_ACR_48_0 0x1C3B +#define mmHDMI_ACR_48_1 0x1C3C +#define mmHDMI_ACR_PACKET_CONTROL 0x1C0F +#define mmHDMI_ACR_STATUS_0 0x1C3D +#define mmHDMI_ACR_STATUS_1 0x1C3E +#define mmHDMI_AUDIO_PACKET_CONTROL 0x1C0E +#define mmHDMI_CONTROL 0x1C0C +#define mmHDMI_GC 0x1C16 +#define mmHDMI_GENERIC_PACKET_CONTROL0 0x1C13 +#define mmHDMI_GENERIC_PACKET_CONTROL1 0x1C30 +#define mmHDMI_INFOFRAME_CONTROL0 0x1C11 +#define mmHDMI_INFOFRAME_CONTROL1 0x1C12 +#define mmHDMI_STATUS 0x1C0D +#define mmHDMI_VBI_PACKET_CONTROL 0x1C10 +#define mmINPUT_CSC_C11_C12 0x1A36 +#define mmINPUT_CSC_C13_C14 0x1A37 +#define mmINPUT_CSC_C21_C22 0x1A38 +#define mmINPUT_CSC_C23_C24 0x1A39 +#define mmINPUT_CSC_C31_C32 0x1A3A +#define mmINPUT_CSC_C33_C34 0x1A3B +#define mmINPUT_CSC_CONTROL 0x1A35 +#define mmINPUT_GAMMA_CONTROL 0x1A10 +#define mmKEY_CONTROL 0x1A53 +#define mmKEY_RANGE_ALPHA 0x1A54 +#define mmKEY_RANGE_BLUE 0x1A57 +#define mmKEY_RANGE_GREEN 0x1A56 +#define mmKEY_RANGE_RED 0x1A55 +#define mmLB0_DC_MVP_LB_CONTROL 0x1ADB +#define mmLB0_LB_DEBUG 0x1AFC +#define mmLB0_LB_DEBUG2 0x1AC9 +#define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS 0x1AC8 +#define mmLB0_LB_SYNC_RESET_SEL 0x1ACA +#define mmLB0_LB_TEST_DEBUG_DATA 0x1AFF +#define mmLB0_LB_TEST_DEBUG_INDEX 0x1AFE +#define mmLB0_MVP_AFR_FLIP_FIFO_CNTL 0x1AD9 +#define mmLB0_MVP_AFR_FLIP_MODE 0x1AD8 +#define mmLB0_MVP_FLIP_LINE_NUM_INSERT 0x1ADA +#define mmLB1_DC_MVP_LB_CONTROL 0x1DDB +#define mmLB1_LB_DEBUG 0x1DFC +#define mmLB1_LB_DEBUG2 0x1DC9 +#define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS 0x1DC8 +#define mmLB1_LB_SYNC_RESET_SEL 0x1DCA +#define mmLB1_LB_TEST_DEBUG_DATA 0x1DFF +#define mmLB1_LB_TEST_DEBUG_INDEX 0x1DFE +#define mmLB1_MVP_AFR_FLIP_FIFO_CNTL 0x1DD9 +#define mmLB1_MVP_AFR_FLIP_MODE 0x1DD8 +#define mmLB1_MVP_FLIP_LINE_NUM_INSERT 0x1DDA +#define mmLB2_DC_MVP_LB_CONTROL 0x40DB +#define mmLB2_LB_DEBUG 0x40FC +#define mmLB2_LB_DEBUG2 0x40C9 +#define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS 0x40C8 +#define mmLB2_LB_SYNC_RESET_SEL 0x40CA +#define mmLB2_LB_TEST_DEBUG_DATA 0x40FF +#define mmLB2_LB_TEST_DEBUG_INDEX 0x40FE +#define mmLB2_MVP_AFR_FLIP_FIFO_CNTL 0x40D9 +#define mmLB2_MVP_AFR_FLIP_MODE 0x40D8 +#define mmLB2_MVP_FLIP_LINE_NUM_INSERT 0x40DA +#define mmLB3_DC_MVP_LB_CONTROL 0x43DB +#define mmLB3_LB_DEBUG 0x43FC +#define mmLB3_LB_DEBUG2 0x43C9 +#define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS 0x43C8 +#define mmLB3_LB_SYNC_RESET_SEL 0x43CA +#define mmLB3_LB_TEST_DEBUG_DATA 0x43FF +#define mmLB3_LB_TEST_DEBUG_INDEX 0x43FE +#define mmLB3_MVP_AFR_FLIP_FIFO_CNTL 0x43D9 +#define mmLB3_MVP_AFR_FLIP_MODE 0x43D8 +#define mmLB3_MVP_FLIP_LINE_NUM_INSERT 0x43DA +#define mmLB4_DC_MVP_LB_CONTROL 0x46DB +#define mmLB4_LB_DEBUG 0x46FC +#define mmLB4_LB_DEBUG2 0x46C9 +#define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS 0x46C8 +#define mmLB4_LB_SYNC_RESET_SEL 0x46CA +#define mmLB4_LB_TEST_DEBUG_DATA 0x46FF +#define mmLB4_LB_TEST_DEBUG_INDEX 0x46FE +#define mmLB4_MVP_AFR_FLIP_FIFO_CNTL 0x46D9 +#define mmLB4_MVP_AFR_FLIP_MODE 0x46D8 +#define mmLB4_MVP_FLIP_LINE_NUM_INSERT 0x46DA +#define mmLB5_DC_MVP_LB_CONTROL 0x49DB +#define mmLB5_LB_DEBUG 0x49FC +#define mmLB5_LB_DEBUG2 0x49C9 +#define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS 0x49C8 +#define mmLB5_LB_SYNC_RESET_SEL 0x49CA +#define mmLB5_LB_TEST_DEBUG_DATA 0x49FF +#define mmLB5_LB_TEST_DEBUG_INDEX 0x49FE +#define mmLB5_MVP_AFR_FLIP_FIFO_CNTL 0x49D9 +#define mmLB5_MVP_AFR_FLIP_MODE 0x49D8 +#define mmLB5_MVP_FLIP_LINE_NUM_INSERT 0x49DA +#define mmLB_DEBUG 0x1AFC +#define mmLB_DEBUG2 0x1AC9 +#define mmLB_NO_OUTSTANDING_REQ_STATUS 0x1AC8 +#define mmLB_SYNC_RESET_SEL 0x1ACA +#define mmLB_TEST_DEBUG_DATA 0x1AFF +#define mmLB_TEST_DEBUG_INDEX 0x1AFE +#define mmLIGHT_SLEEP_CNTL 0x0132 +#define mmLOW_POWER_TILING_CONTROL 0x0325 +#define mmLVDS_DATA_CNTL 0x1C8C +#define mmLVTMA_PWRSEQ_CNTL 0x1919 +#define mmLVTMA_PWRSEQ_DELAY1 0x191C +#define mmLVTMA_PWRSEQ_DELAY2 0x191D +#define mmLVTMA_PWRSEQ_REF_DIV 0x191B +#define mmLVTMA_PWRSEQ_STATE 0x191A +#define mmMASTER_COMM_CMD_REG 0x161F +#define mmMASTER_COMM_CNTL_REG 0x1620 +#define mmMASTER_COMM_DATA_REG1 0x161C +#define mmMASTER_COMM_DATA_REG2 0x161D +#define mmMASTER_COMM_DATA_REG3 0x161E +#define mmMASTER_UPDATE_LOCK 0x1BBD +#define mmMASTER_UPDATE_MODE 0x1BBE +#define mmMC_DC_INTERFACE_NACK_STATUS 0x031C +#define mmMCIF_CONTROL 0x0314 +#define mmMCIF_MEM_CONTROL 0x0319 +#define mmMCIF_TEST_DEBUG_DATA 0x0317 +#define mmMCIF_TEST_DEBUG_INDEX 0x0316 +#define mmMCIF_VMID 0x0318 +#define mmMCIF_WRITE_COMBINE_CONTROL 0x0315 +#define mmMICROSECOND_TIME_BASE_DIV 0x013B +#define mmMILLISECOND_TIME_BASE_DIV 0x0130 +#define mmMVP_AFR_FLIP_FIFO_CNTL 0x1AD9 +#define mmMVP_AFR_FLIP_MODE 0x1AD8 +#define mmMVP_BLACK_KEYER 0x1686 +#define mmMVP_CONTROL1 0x1680 +#define mmMVP_CONTROL2 0x1681 +#define mmMVP_CONTROL3 0x168A +#define mmMVP_CRC_CNTL 0x1687 +#define mmMVP_CRC_RESULT_BLUE_GREEN 0x1688 +#define mmMVP_CRC_RESULT_RED 0x1689 +#define mmMVP_DEBUG 0x168F +#define mmMVP_FIFO_CONTROL 0x1682 +#define mmMVP_FIFO_STATUS 0x1683 +#define mmMVP_FLIP_LINE_NUM_INSERT 0x1ADA +#define mmMVP_INBAND_CNTL_CAP 0x1685 +#define mmMVP_RECEIVE_CNT_CNTL1 0x168B +#define mmMVP_RECEIVE_CNT_CNTL2 0x168C +#define mmMVP_SLAVE_STATUS 0x1684 +#define mmMVP_TEST_DEBUG_DATA 0x168E +#define mmMVP_TEST_DEBUG_INDEX 0x168D +#define mmOUTPUT_CSC_C11_C12 0x1A3D +#define mmOUTPUT_CSC_C13_C14 0x1A3E +#define mmOUTPUT_CSC_C21_C22 0x1A3F +#define mmOUTPUT_CSC_C23_C24 0x1A40 +#define mmOUTPUT_CSC_C31_C32 0x1A41 +#define mmOUTPUT_CSC_C33_C34 0x1A42 +#define mmOUTPUT_CSC_CONTROL 0x1A3C +#define mmOUT_ROUND_CONTROL 0x1A51 +#define mmOVL_CONTROL1 0x1A1D +#define mmOVL_CONTROL2 0x1A1E +#define mmOVL_DFQ_CONTROL 0x1A29 +#define mmOVL_DFQ_STATUS 0x1A2A +#define mmOVL_ENABLE 0x1A1C +#define mmOVL_END 0x1A26 +#define mmOVL_PITCH 0x1A21 +#define mmOVLSCL_EDGE_PIXEL_CNTL 0x1A2C +#define mmOVL_SECONDARY_SURFACE_ADDRESS 0x1A92 +#define mmOVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1A94 +#define mmOVL_START 0x1A25 +#define mmOVL_STEREOSYNC_FLIP 0x1A93 +#define mmOVL_SURFACE_ADDRESS 0x1A20 +#define mmOVL_SURFACE_ADDRESS_HIGH 0x1A22 +#define mmOVL_SURFACE_ADDRESS_HIGH_INUSE 0x1A2B +#define mmOVL_SURFACE_ADDRESS_INUSE 0x1A28 +#define mmOVL_SURFACE_OFFSET_X 0x1A23 +#define mmOVL_SURFACE_OFFSET_Y 0x1A24 +#define mmOVL_SWAP_CNTL 0x1A1F +#define mmOVL_UPDATE 0x1A27 +#define mmPHY_AUX_CNTL 0x197F +#define mmPIPE0_ARBITRATION_CONTROL3 0x02FA +#define mmPIPE0_DMIF_BUFFER_CONTROL 0x0328 +#define mmPIPE0_MAX_REQUESTS 0x0302 +#define mmPIPE0_PG_CONFIG 0x1760 +#define mmPIPE0_PG_ENABLE 0x1761 +#define mmPIPE0_PG_STATUS 0x1762 +#define mmPIPE1_ARBITRATION_CONTROL3 0x02FB +#define mmPIPE1_DMIF_BUFFER_CONTROL 0x0330 +#define mmPIPE1_MAX_REQUESTS 0x0303 +#define mmPIPE1_PG_CONFIG 0x1764 +#define mmPIPE1_PG_ENABLE 0x1765 +#define mmPIPE1_PG_STATUS 0x1766 +#define mmPIPE2_ARBITRATION_CONTROL3 0x02FC +#define mmPIPE2_DMIF_BUFFER_CONTROL 0x0338 +#define mmPIPE2_MAX_REQUESTS 0x0304 +#define mmPIPE2_PG_CONFIG 0x1768 +#define mmPIPE2_PG_ENABLE 0x1769 +#define mmPIPE2_PG_STATUS 0x176A +#define mmPIPE3_ARBITRATION_CONTROL3 0x02FD +#define mmPIPE3_DMIF_BUFFER_CONTROL 0x0340 +#define mmPIPE3_MAX_REQUESTS 0x0305 +#define mmPIPE3_PG_CONFIG 0x176C +#define mmPIPE3_PG_ENABLE 0x176D +#define mmPIPE3_PG_STATUS 0x176E +#define mmPIPE4_ARBITRATION_CONTROL3 0x02FE +#define mmPIPE4_DMIF_BUFFER_CONTROL 0x0348 +#define mmPIPE4_MAX_REQUESTS 0x0306 +#define mmPIPE4_PG_CONFIG 0x1770 +#define mmPIPE4_PG_ENABLE 0x1771 +#define mmPIPE4_PG_STATUS 0x1772 +#define mmPIPE5_ARBITRATION_CONTROL3 0x02FF +#define mmPIPE5_DMIF_BUFFER_CONTROL 0x0350 +#define mmPIPE5_MAX_REQUESTS 0x0307 +#define mmPIPE5_PG_CONFIG 0x1774 +#define mmPIPE5_PG_ENABLE 0x1775 +#define mmPIPE5_PG_STATUS 0x1776 +#define mmPIXCLK0_RESYNC_CNTL 0x013A +#define mmPIXCLK1_RESYNC_CNTL 0x0138 +#define mmPIXCLK2_RESYNC_CNTL 0x0139 +#define mmPLL_ANALOG 0x1708 +#define mmPLL_CNTL 0x1707 +#define mmPLL_DEBUG_CNTL 0x170B +#define mmPLL_DISPCLK_CURRENT_DTO_PHASE 0x170F +#define mmPLL_DISPCLK_DTO_CNTL 0x170E +#define mmPLL_DS_CNTL 0x1705 +#define mmPLL_FB_DIV 0x1701 +#define mmPLL_IDCLK_CNTL 0x1706 +#define mmPLL_POST_DIV 0x1702 +#define mmPLL_REF_DIV 0x1700 +#define mmPLL_SS_AMOUNT_DSFRAC 0x1703 +#define mmPLL_SS_CNTL 0x1704 +#define mmPLL_UNLOCK_DETECT_CNTL 0x170A +#define mmPLL_UPDATE_CNTL 0x170D +#define mmPLL_UPDATE_LOCK 0x170C +#define mmPLL_VREG_CNTL 0x1709 +#define mmPRESCALE_GRPH_CONTROL 0x1A2D +#define mmPRESCALE_OVL_CONTROL 0x1A31 +#define mmPRESCALE_VALUES_GRPH_B 0x1A30 +#define mmPRESCALE_VALUES_GRPH_G 0x1A2F +#define mmPRESCALE_VALUES_GRPH_R 0x1A2E +#define mmPRESCALE_VALUES_OVL_CB 0x1A32 +#define mmPRESCALE_VALUES_OVL_CR 0x1A34 +#define mmPRESCALE_VALUES_OVL_Y 0x1A33 +#define mmREGAMMA_CNTLA_END_CNTL1 0x1AA6 +#define mmREGAMMA_CNTLA_END_CNTL2 0x1AA7 +#define mmREGAMMA_CNTLA_REGION_0_1 0x1AA8 +#define mmREGAMMA_CNTLA_REGION_10_11 0x1AAD +#define mmREGAMMA_CNTLA_REGION_12_13 0x1AAE +#define mmREGAMMA_CNTLA_REGION_14_15 0x1AAF +#define mmREGAMMA_CNTLA_REGION_2_3 0x1AA9 +#define mmREGAMMA_CNTLA_REGION_4_5 0x1AAA +#define mmREGAMMA_CNTLA_REGION_6_7 0x1AAB +#define mmREGAMMA_CNTLA_REGION_8_9 0x1AAC +#define mmREGAMMA_CNTLA_SLOPE_CNTL 0x1AA5 +#define mmREGAMMA_CNTLA_START_CNTL 0x1AA4 +#define mmREGAMMA_CNTLB_END_CNTL1 0x1AB2 +#define mmREGAMMA_CNTLB_END_CNTL2 0x1AB3 +#define mmREGAMMA_CNTLB_REGION_0_1 0x1AB4 +#define mmREGAMMA_CNTLB_REGION_10_11 0x1AB9 +#define mmREGAMMA_CNTLB_REGION_12_13 0x1ABA +#define mmREGAMMA_CNTLB_REGION_14_15 0x1ABB +#define mmREGAMMA_CNTLB_REGION_2_3 0x1AB5 +#define mmREGAMMA_CNTLB_REGION_4_5 0x1AB6 +#define mmREGAMMA_CNTLB_REGION_6_7 0x1AB7 +#define mmREGAMMA_CNTLB_REGION_8_9 0x1AB8 +#define mmREGAMMA_CNTLB_SLOPE_CNTL 0x1AB1 +#define mmREGAMMA_CNTLB_START_CNTL 0x1AB0 +#define mmREGAMMA_CONTROL 0x1AA0 +#define mmREGAMMA_LUT_DATA 0x1AA2 +#define mmREGAMMA_LUT_INDEX 0x1AA1 +#define mmREGAMMA_LUT_WRITE_EN_MASK 0x1AA3 +#define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT 0x1B5E +#define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM 0x1B5F +#define mmSCL0_SCL_ALU_CONTROL 0x1B54 +#define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL 0x1B47 +#define mmSCL0_SCL_BYPASS_CONTROL 0x1B45 +#define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS 0x1B55 +#define mmSCL0_SCL_COEF_RAM_SELECT 0x1B40 +#define mmSCL0_SCL_COEF_RAM_TAP_DATA 0x1B41 +#define mmSCL0_SCL_CONTROL 0x1B44 +#define mmSCL0_SCL_DEBUG 0x1B6A +#define mmSCL0_SCL_DEBUG2 0x1B69 +#define mmSCL0_SCL_F_SHARP_CONTROL 0x1B53 +#define mmSCL0_SCL_HORZ_FILTER_CONTROL 0x1B4A +#define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x1B4B +#define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x1B46 +#define mmSCL0_SCL_MODE_CHANGE_DET1 0x1B60 +#define mmSCL0_SCL_MODE_CHANGE_DET2 0x1B61 +#define mmSCL0_SCL_MODE_CHANGE_DET3 0x1B62 +#define mmSCL0_SCL_MODE_CHANGE_MASK 0x1B63 +#define mmSCL0_SCL_TAP_CONTROL 0x1B43 +#define mmSCL0_SCL_TEST_DEBUG_DATA 0x1B6C +#define mmSCL0_SCL_TEST_DEBUG_INDEX 0x1B6B +#define mmSCL0_SCL_UPDATE 0x1B51 +#define mmSCL0_SCL_VERT_FILTER_CONTROL 0x1B4E +#define mmSCL0_SCL_VERT_FILTER_INIT 0x1B50 +#define mmSCL0_SCL_VERT_FILTER_INIT_BOT 0x1B57 +#define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x1B4F +#define mmSCL0_VIEWPORT_SIZE 0x1B5D +#define mmSCL0_VIEWPORT_START 0x1B5C +#define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT 0x1E5E +#define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM 0x1E5F +#define mmSCL1_SCL_ALU_CONTROL 0x1E54 +#define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL 0x1E47 +#define mmSCL1_SCL_BYPASS_CONTROL 0x1E45 +#define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS 0x1E55 +#define mmSCL1_SCL_COEF_RAM_SELECT 0x1E40 +#define mmSCL1_SCL_COEF_RAM_TAP_DATA 0x1E41 +#define mmSCL1_SCL_CONTROL 0x1E44 +#define mmSCL1_SCL_DEBUG 0x1E6A +#define mmSCL1_SCL_DEBUG2 0x1E69 +#define mmSCL1_SCL_F_SHARP_CONTROL 0x1E53 +#define mmSCL1_SCL_HORZ_FILTER_CONTROL 0x1E4A +#define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x1E4B +#define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x1E46 +#define mmSCL1_SCL_MODE_CHANGE_DET1 0x1E60 +#define mmSCL1_SCL_MODE_CHANGE_DET2 0x1E61 +#define mmSCL1_SCL_MODE_CHANGE_DET3 0x1E62 +#define mmSCL1_SCL_MODE_CHANGE_MASK 0x1E63 +#define mmSCL1_SCL_TAP_CONTROL 0x1E43 +#define mmSCL1_SCL_TEST_DEBUG_DATA 0x1E6C +#define mmSCL1_SCL_TEST_DEBUG_INDEX 0x1E6B +#define mmSCL1_SCL_UPDATE 0x1E51 +#define mmSCL1_SCL_VERT_FILTER_CONTROL 0x1E4E +#define mmSCL1_SCL_VERT_FILTER_INIT 0x1E50 +#define mmSCL1_SCL_VERT_FILTER_INIT_BOT 0x1E57 +#define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x1E4F +#define mmSCL1_VIEWPORT_SIZE 0x1E5D +#define mmSCL1_VIEWPORT_START 0x1E5C +#define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT 0x415E +#define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM 0x415F +#define mmSCL2_SCL_ALU_CONTROL 0x4154 +#define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL 0x4147 +#define mmSCL2_SCL_BYPASS_CONTROL 0x4145 +#define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS 0x4155 +#define mmSCL2_SCL_COEF_RAM_SELECT 0x4140 +#define mmSCL2_SCL_COEF_RAM_TAP_DATA 0x4141 +#define mmSCL2_SCL_CONTROL 0x4144 +#define mmSCL2_SCL_DEBUG 0x416A +#define mmSCL2_SCL_DEBUG2 0x4169 +#define mmSCL2_SCL_F_SHARP_CONTROL 0x4153 +#define mmSCL2_SCL_HORZ_FILTER_CONTROL 0x414A +#define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x414B +#define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x4146 +#define mmSCL2_SCL_MODE_CHANGE_DET1 0x4160 +#define mmSCL2_SCL_MODE_CHANGE_DET2 0x4161 +#define mmSCL2_SCL_MODE_CHANGE_DET3 0x4162 +#define mmSCL2_SCL_MODE_CHANGE_MASK 0x4163 +#define mmSCL2_SCL_TAP_CONTROL 0x4143 +#define mmSCL2_SCL_TEST_DEBUG_DATA 0x416C +#define mmSCL2_SCL_TEST_DEBUG_INDEX 0x416B +#define mmSCL2_SCL_UPDATE 0x4151 +#define mmSCL2_SCL_VERT_FILTER_CONTROL 0x414E +#define mmSCL2_SCL_VERT_FILTER_INIT 0x4150 +#define mmSCL2_SCL_VERT_FILTER_INIT_BOT 0x4157 +#define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x414F +#define mmSCL2_VIEWPORT_SIZE 0x415D +#define mmSCL2_VIEWPORT_START 0x415C +#define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT 0x445E +#define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM 0x445F +#define mmSCL3_SCL_ALU_CONTROL 0x4454 +#define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL 0x4447 +#define mmSCL3_SCL_BYPASS_CONTROL 0x4445 +#define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS 0x4455 +#define mmSCL3_SCL_COEF_RAM_SELECT 0x4440 +#define mmSCL3_SCL_COEF_RAM_TAP_DATA 0x4441 +#define mmSCL3_SCL_CONTROL 0x4444 +#define mmSCL3_SCL_DEBUG 0x446A +#define mmSCL3_SCL_DEBUG2 0x4469 +#define mmSCL3_SCL_F_SHARP_CONTROL 0x4453 +#define mmSCL3_SCL_HORZ_FILTER_CONTROL 0x444A +#define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x444B +#define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x4446 +#define mmSCL3_SCL_MODE_CHANGE_DET1 0x4460 +#define mmSCL3_SCL_MODE_CHANGE_DET2 0x4461 +#define mmSCL3_SCL_MODE_CHANGE_DET3 0x4462 +#define mmSCL3_SCL_MODE_CHANGE_MASK 0x4463 +#define mmSCL3_SCL_TAP_CONTROL 0x4443 +#define mmSCL3_SCL_TEST_DEBUG_DATA 0x446C +#define mmSCL3_SCL_TEST_DEBUG_INDEX 0x446B +#define mmSCL3_SCL_UPDATE 0x4451 +#define mmSCL3_SCL_VERT_FILTER_CONTROL 0x444E +#define mmSCL3_SCL_VERT_FILTER_INIT 0x4450 +#define mmSCL3_SCL_VERT_FILTER_INIT_BOT 0x4457 +#define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x444F +#define mmSCL3_VIEWPORT_SIZE 0x445D +#define mmSCL3_VIEWPORT_START 0x445C +#define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT 0x475E +#define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM 0x475F +#define mmSCL4_SCL_ALU_CONTROL 0x4754 +#define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL 0x4747 +#define mmSCL4_SCL_BYPASS_CONTROL 0x4745 +#define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS 0x4755 +#define mmSCL4_SCL_COEF_RAM_SELECT 0x4740 +#define mmSCL4_SCL_COEF_RAM_TAP_DATA 0x4741 +#define mmSCL4_SCL_CONTROL 0x4744 +#define mmSCL4_SCL_DEBUG 0x476A +#define mmSCL4_SCL_DEBUG2 0x4769 +#define mmSCL4_SCL_F_SHARP_CONTROL 0x4753 +#define mmSCL4_SCL_HORZ_FILTER_CONTROL 0x474A +#define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO 0x474B +#define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL 0x4746 +#define mmSCL4_SCL_MODE_CHANGE_DET1 0x4760 +#define mmSCL4_SCL_MODE_CHANGE_DET2 0x4761 +#define mmSCL4_SCL_MODE_CHANGE_DET3 0x4762 +#define mmSCL4_SCL_MODE_CHANGE_MASK 0x4763 +#define mmSCL4_SCL_TAP_CONTROL 0x4743 +#define mmSCL4_SCL_TEST_DEBUG_DATA 0x476C +#define mmSCL4_SCL_TEST_DEBUG_INDEX 0x476B +#define mmSCL4_SCL_UPDATE 0x4751 +#define mmSCL4_SCL_VERT_FILTER_CONTROL 0x474E +#define mmSCL4_SCL_VERT_FILTER_INIT 0x4750 +#define mmSCL4_SCL_VERT_FILTER_INIT_BOT 0x4757 +#define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO 0x474F +#define mmSCL4_VIEWPORT_SIZE 0x475D +#define mmSCL4_VIEWPORT_START 0x475C +#define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT 0x4A5E +#define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM 0x4A5F +#define mmSCL5_SCL_ALU_CONTROL 0x4A54 +#define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL 0x4A47 +#define mmSCL5_SCL_BYPASS_CONTROL 0x4A45 +#define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS 0x4A55 +#define mmSCL5_SCL_COEF_RAM_SELECT 0x4A40 +#define mmSCL5_SCL_COEF_RAM_TAP_DATA 0x4A41 +#define mmSCL5_SCL_CONTROL 0x4A44 +#define mmSCL5_SCL_DEBUG 0x4A6A +#define mmSCL5_SCL_DEBUG2 0x4A69 +#define mmSCL5_SCL_F_SHARP_CONTROL 0x4A53 +#define mmSCL5_SCL_HORZ_FILTER_CONTROL 0x4A4A +#define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO 0x4A4B +#define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL 0x4A46 +#define mmSCL5_SCL_MODE_CHANGE_DET1 0x4A60 +#define mmSCL5_SCL_MODE_CHANGE_DET2 0x4A61 +#define mmSCL5_SCL_MODE_CHANGE_DET3 0x4A62 +#define mmSCL5_SCL_MODE_CHANGE_MASK 0x4A63 +#define mmSCL5_SCL_TAP_CONTROL 0x4A43 +#define mmSCL5_SCL_TEST_DEBUG_DATA 0x4A6C +#define mmSCL5_SCL_TEST_DEBUG_INDEX 0x4A6B +#define mmSCL5_SCL_UPDATE 0x4A51 +#define mmSCL5_SCL_VERT_FILTER_CONTROL 0x4A4E +#define mmSCL5_SCL_VERT_FILTER_INIT 0x4A50 +#define mmSCL5_SCL_VERT_FILTER_INIT_BOT 0x4A57 +#define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO 0x4A4F +#define mmSCL5_VIEWPORT_SIZE 0x4A5D +#define mmSCL5_VIEWPORT_START 0x4A5C +#define mmSCL_ALU_CONTROL 0x1B54 +#define mmSCL_AUTOMATIC_MODE_CONTROL 0x1B47 +#define mmSCL_BYPASS_CONTROL 0x1B45 +#define mmSCL_COEF_RAM_CONFLICT_STATUS 0x1B55 +#define mmSCL_COEF_RAM_SELECT 0x1B40 +#define mmSCL_COEF_RAM_TAP_DATA 0x1B41 +#define mmSCL_CONTROL 0x1B44 +#define mmSCL_DEBUG 0x1B6A +#define mmSCL_DEBUG2 0x1B69 +#define mmSCL_F_SHARP_CONTROL 0x1B53 +#define mmSCL_HORZ_FILTER_CONTROL 0x1B4A +#define mmSCL_HORZ_FILTER_SCALE_RATIO 0x1B4B +#define mmSCLK_CGTT_BLK_CTRL_REG 0x0136 +#define mmSCL_MANUAL_REPLICATE_CONTROL 0x1B46 +#define mmSCL_MODE_CHANGE_DET1 0x1B60 +#define mmSCL_MODE_CHANGE_DET2 0x1B61 +#define mmSCL_MODE_CHANGE_DET3 0x1B62 +#define mmSCL_MODE_CHANGE_MASK 0x1B63 +#define mmSCL_TAP_CONTROL 0x1B43 +#define mmSCL_TEST_DEBUG_DATA 0x1B6C +#define mmSCL_TEST_DEBUG_INDEX 0x1B6B +#define mmSCL_UPDATE 0x1B51 +#define mmSCL_VERT_FILTER_CONTROL 0x1B4E +#define mmSCL_VERT_FILTER_INIT 0x1B50 +#define mmSCL_VERT_FILTER_INIT_BOT 0x1B57 +#define mmSCL_VERT_FILTER_SCALE_RATIO 0x1B4F +#define mmSEQ8_DATA 0x00F1 +#define mmSEQ8_IDX 0x00F1 +#define mmSLAVE_COMM_CMD_REG 0x1624 +#define mmSLAVE_COMM_CNTL_REG 0x1625 +#define mmSLAVE_COMM_DATA_REG1 0x1621 +#define mmSLAVE_COMM_DATA_REG2 0x1622 +#define mmSLAVE_COMM_DATA_REG3 0x1623 +#define mmSYMCLKA_CLOCK_ENABLE 0x0160 +#define mmSYMCLKB_CLOCK_ENABLE 0x0161 +#define mmSYMCLKC_CLOCK_ENABLE 0x0162 +#define mmSYMCLKD_CLOCK_ENABLE 0x0163 +#define mmSYMCLKE_CLOCK_ENABLE 0x0164 +#define mmSYMCLKF_CLOCK_ENABLE 0x0165 +#define mmTMDS_CNTL 0x1C7C +#define mmTMDS_CONTROL0_FEEDBACK 0x1C7E +#define mmTMDS_CONTROL_CHAR 0x1C7D +#define mmTMDS_CTL0_1_GEN_CNTL 0x1C86 +#define mmTMDS_CTL2_3_GEN_CNTL 0x1C87 +#define mmTMDS_CTL_BITS 0x1C83 +#define mmTMDS_DCBALANCER_CONTROL 0x1C84 +#define mmTMDS_DEBUG 0x1C82 +#define mmTMDS_STEREOSYNC_CTL_SEL 0x1C7F +#define mmTMDS_SYNC_CHAR_PATTERN_0_1 0x1C80 +#define mmTMDS_SYNC_CHAR_PATTERN_2_3 0x1C81 +#define mmUNIPHYAB_TPG_CONTROL 0x1931 +#define mmUNIPHYAB_TPG_SEED 0x1932 +#define mmUNIPHY_ANG_BIST_CNTL 0x198C +#define mmUNIPHYCD_TPG_CONTROL 0x1933 +#define mmUNIPHYCD_TPG_SEED 0x1934 +#define mmUNIPHY_CHANNEL_XBAR_CNTL 0x198E +#define mmUNIPHY_DATA_SYNCHRONIZATION 0x198A +#define mmUNIPHYEF_TPG_CONTROL 0x1935 +#define mmUNIPHYEF_TPG_SEED 0x1936 +#define mmUNIPHY_IMPCAL_LINKA 0x1908 +#define mmUNIPHY_IMPCAL_LINKB 0x1909 +#define mmUNIPHY_IMPCAL_LINKC 0x190F +#define mmUNIPHY_IMPCAL_LINKD 0x1910 +#define mmUNIPHY_IMPCAL_LINKE 0x1913 +#define mmUNIPHY_IMPCAL_LINKF 0x1914 +#define mmUNIPHY_IMPCAL_PERIOD 0x190A +#define mmUNIPHY_IMPCAL_PSW_AB 0x190E +#define mmUNIPHY_IMPCAL_PSW_CD 0x1912 +#define mmUNIPHY_IMPCAL_PSW_EF 0x1916 +#define mmUNIPHY_LINK_CNTL 0x198D +#define mmUNIPHY_PLL_CONTROL1 0x1986 +#define mmUNIPHY_PLL_CONTROL2 0x1987 +#define mmUNIPHY_PLL_FBDIV 0x1985 +#define mmUNIPHY_PLL_SS_CNTL 0x1989 +#define mmUNIPHY_PLL_SS_STEP_SIZE 0x1988 +#define mmUNIPHY_POWER_CONTROL 0x1984 +#define mmUNIPHY_REG_TEST_OUTPUT 0x198B +#define mmUNIPHY_SOFT_RESET 0x0166 +#define mmUNIPHY_TX_CONTROL1 0x1980 +#define mmUNIPHY_TX_CONTROL2 0x1981 +#define mmUNIPHY_TX_CONTROL3 0x1982 +#define mmUNIPHY_TX_CONTROL4 0x1983 +#define mmVGA25_PPLL_ANALOG 0x00E4 +#define mmVGA25_PPLL_FB_DIV 0x00DC +#define mmVGA25_PPLL_POST_DIV 0x00E0 +#define mmVGA25_PPLL_REF_DIV 0x00D8 +#define mmVGA28_PPLL_ANALOG 0x00E5 +#define mmVGA28_PPLL_FB_DIV 0x00DD +#define mmVGA28_PPLL_POST_DIV 0x00E1 +#define mmVGA28_PPLL_REF_DIV 0x00D9 +#define mmVGA41_PPLL_ANALOG 0x00E6 +#define mmVGA41_PPLL_FB_DIV 0x00DE +#define mmVGA41_PPLL_POST_DIV 0x00E2 +#define mmVGA41_PPLL_REF_DIV 0x00DA +#define mmVGA_CACHE_CONTROL 0x00CB +#define mmVGA_DEBUG_READBACK_DATA 0x00D7 +#define mmVGA_DEBUG_READBACK_INDEX 0x00D6 +#define mmVGA_DISPBUF1_SURFACE_ADDR 0x00C6 +#define mmVGA_DISPBUF2_SURFACE_ADDR 0x00C8 +#define mmVGA_HDP_CONTROL 0x00CA +#define mmVGA_HW_DEBUG 0x00CF +#define mmVGA_INTERRUPT_CONTROL 0x00D1 +#define mmVGA_INTERRUPT_STATUS 0x00D3 +#define mmVGA_MAIN_CONTROL 0x00D4 +#define mmVGA_MEMORY_BASE_ADDRESS 0x00C4 +#define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0x00C9 +#define mmVGA_MEM_READ_PAGE_ADDR 0x0013 +#define mmVGA_MEM_WRITE_PAGE_ADDR 0x0012 +#define mmVGA_MODE_CONTROL 0x00C2 +#define mmVGA_RENDER_CONTROL 0x00C0 +#define mmVGA_SEQUENCER_RESET_CONTROL 0x00C1 +#define mmVGA_SOURCE_SELECT 0x00FC +#define mmVGA_STATUS 0x00D0 +#define mmVGA_STATUS_CLEAR 0x00D2 +#define mmVGA_SURFACE_PITCH_SELECT 0x00C3 +#define mmVGA_TEST_CONTROL 0x00D5 +#define mmVGA_TEST_DEBUG_DATA 0x00C7 +#define mmVGA_TEST_DEBUG_INDEX 0x00C5 +#define mmVIEWPORT_SIZE 0x1B5D +#define mmVIEWPORT_START 0x1B5C +#define mmXDMA_CLOCK_GATING_CNTL 0x0409 +#define mmXDMA_IF_BIF_STATUS 0x0418 +#define mmXDMA_INTERRUPT 0x0406 +#define mmXDMA_LOCAL_SURFACE_TILING1 0x03F4 +#define mmXDMA_LOCAL_SURFACE_TILING2 0x03F5 +#define mmXDMA_MC_PCIE_CLIENT_CONFIG 0x03E9 +#define mmXDMA_MEM_POWER_CNTL 0x040B +#define mmXDMA_MSTR_CMD_URGENT_CNTL 0x03F6 +#define mmXDMA_MSTR_CNTL 0x03E0 +#define mmXDMA_MSTR_HEIGHT 0x03E3 +#define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR 0x03F1 +#define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH 0x03F2 +#define mmXDMA_MSTR_LOCAL_SURFACE_PITCH 0x03F3 +#define mmXDMA_MSTR_MEM_CLIENT_CONFIG 0x03EA +#define mmXDMA_MSTR_MEM_NACK_STATUS 0x040D +#define mmXDMA_MSTR_MEM_URGENT_CNTL 0x03F7 +#define mmXDMA_MSTR_PCIE_NACK_STATUS 0x040C +#define mmXDMA_MSTR_READ_COMMAND 0x03E1 +#define mmXDMA_MSTR_REMOTE_GPU_ADDRESS 0x03E6 +#define mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x03E7 +#define mmXDMA_MSTR_REMOTE_SURFACE_BASE 0x03E4 +#define mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x03E5 +#define mmXDMA_MSTR_STATUS 0x03E8 +#define mmXDMA_RBBMIF_RDWR_CNTL 0x040A +#define mmXDMA_SLV_CNTL 0x03FB +#define mmXDMA_SLV_FLIP_PENDING 0x0407 +#define mmXDMA_SLV_MEM_CLIENT_CONFIG 0x03FD +#define mmXDMA_SLV_MEM_NACK_STATUS 0x040F +#define mmXDMA_SLV_PCIE_NACK_STATUS 0x040E +#define mmXDMA_SLV_READ_LATENCY_AVE 0x0405 +#define mmXDMA_SLV_READ_LATENCY_MINMAX 0x0404 +#define mmXDMA_SLV_READ_LATENCY_TIMER 0x0412 +#define mmXDMA_SLV_READ_URGENT_CNTL 0x03FF +#define mmXDMA_SLV_REMOTE_GPU_ADDRESS 0x0402 +#define mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x0403 +#define mmXDMA_SLV_SLS_PITCH 0x03FE +#define mmXDMA_SLV_WB_RATE_CNTL 0x0401 +#define mmXDMA_SLV_WRITE_URGENT_CNTL 0x0400 +#define mmXDMA_TEST_DEBUG_DATA 0x041D +#define mmXDMA_TEST_DEBUG_INDEX 0x041C + +/* Registers that spilled out of sid.h */ +#define mmDATA_FORMAT 0x1AC0 +#define mmDESKTOP_HEIGHT 0x1AC1 +#define mmDC_LB_MEMORY_SPLIT 0x1AC3 +#define mmPRIORITY_A_CNT 0x1AC6 +#define mmPRIORITY_B_CNT 0x1AC7 +#define mmDPG_PIPE_ARBITRATION_CONTROL3 0x1B32 +#define mmINT_MASK 0x1AD0 +#define mmVLINE_STATUS 0x1AEE +#define mmVBLANK_STATUS 0x1AEF + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h new file mode 100644 index 000000000000..9a4d4c299d5b --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h @@ -0,0 +1,9836 @@ +/* + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef DCE_6_0_SH_MASK_H +#define DCE_6_0_SH_MASK_H + +#define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA_MASK 0xffffffffL +#define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L +#define AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x00000000 +#define AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L +#define AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x00000001 +#define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000ff00L +#define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x00000008 +#define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00f00000L +#define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x00000014 +#define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +#define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x0000001c +#define AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L +#define AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x00000002 +#define AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L +#define AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x00000003 +#define AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000c0L +#define AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x00000006 +#define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0f000000L +#define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x00000018 +#define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000f0000L +#define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x00000010 +#define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00f00000L +#define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x00000014 +#define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000f0L +#define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x00000004 +#define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000fL +#define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x00000000 +#define AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L +#define AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x00000010 +#define AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L +#define AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x00000012 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000fL +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x00000000 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000f0L +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x00000004 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000f00L +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x00000008 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000f000L +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x0000000c +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000f0000L +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x00000010 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00f00000L +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x00000014 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000f000L +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0x0000000c +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x00000004 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xffff0000L +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x00000010 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x00000000 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x00000008 +#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L +#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x00000000 +#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xffffff00L +#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x00000008 +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE_MASK 0x00000100L +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE__SHIFT 0x00000008 +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV_MASK 0x00070000L +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV__SHIFT 0x00000010 +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI_MASK 0x00007000L +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI__SHIFT 0x0000000c +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL_MASK 0x00000007L +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL__SHIFT 0x00000000 +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x00000008 +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000ffL +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00ff0000L +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x00000010 +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x00000000 +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0x0000000b +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1f000000L +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x00000018 +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000ffL +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x00000000 +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0x0000000f +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x00000010 +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0x0000000b +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x0000001c +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000ff00L +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x00000008 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x00000000 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x00000001 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00ff0000L +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x00000010 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x00000018 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x0000001a +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x00000018 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x00000017 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x00000000 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0x0000000c +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0x0000000e +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x0000001e +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000L +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x0000001f +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0x0000000b +#define AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L +#define AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x00000000 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK 0x00001000L +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT 0x0000000c +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK 0x00000c00L +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT 0x0000000a +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK 0x000000ffL +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT 0x00000000 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK 0x00c00000L +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT 0x00000016 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK 0x70000000L +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT 0x0000001c +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK 0x80000000L +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT 0x0000001f +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK 0x00300000L +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT 0x00000014 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_PB1_RSVD_MASK 0x00008000L +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_PB1_RSVD__SHIFT 0x0000000f +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK 0x0c000000L +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT 0x0000001a +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK 0x000f0000L +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT 0x00000010 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK 0x03000000L +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT 0x00000018 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK 0x00000300L +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT 0x00000008 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK 0x00006000L +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT 0x0000000d +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK 0x00003000L +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT 0x0000000c +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PB4_RSVD_MASK 0x00000080L +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PB4_RSVD__SHIFT 0x00000007 +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK 0x00000f00L +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT 0x00000008 +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK 0xffff0000L +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT 0x00000010 +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK 0x0000007fL +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT 0x00000000 +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK 0x0000c000L +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT 0x0000000e +#define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK 0x0000ffffL +#define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT 0x00000000 +#define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK 0xffff0000L +#define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT 0x00000010 +#define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK 0x0000ffffL +#define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT 0x00000000 +#define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK 0xff000000L +#define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT 0x00000018 +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000ffL +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x00000000 +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000ff00L +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x00000008 +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00ff0000L +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x00000010 +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xff000000L +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x00000018 +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000ffL +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x00000000 +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000ff00L +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x00000008 +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00ff0000L +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x00000010 +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xff000000L +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x00000018 +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00ff0000L +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x00000010 +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xff000000L +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x00000018 +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000ffL +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x00000000 +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000ff00L +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x00000008 +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000ffL +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x00000000 +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000ff00L +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x00000008 +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00ff0000L +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x00000010 +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xff000000L +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x00000018 +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000ffL +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x00000000 +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000ff00L +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x00000008 +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00ff0000L +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x00000010 +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xff000000L +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x00000018 +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000ffL +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x00000000 +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000ff00L +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x00000008 +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00ff0000L +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x00000010 +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xff000000L +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x00000018 +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000ffL +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x00000000 +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000ff00L +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x00000008 +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00ff0000L +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x00000010 +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xff000000L +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x00000018 +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000ffL +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x00000000 +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000ff00L +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x00000008 +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00ff0000L +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x00000010 +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xff000000L +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x00000018 +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000ffL +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x00000000 +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000ff00L +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x00000008 +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00ff0000L +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x00000010 +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xff000000L +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x00000018 +#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L +#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x00000006 +#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L +#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x00000007 +#define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L +#define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0x0000000a +#define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L +#define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x00000006 +#define AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L +#define AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x00000000 +#define AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L +#define AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x00000007 +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000ffL +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x00000000 +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000ff00L +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x00000008 +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00ff0000L +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x00000010 +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xff000000L +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x00000018 +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000ffL +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x00000000 +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000ff00L +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x00000008 +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00ff0000L +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x00000010 +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xff000000L +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x00000018 +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00ff0000L +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x00000010 +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xff000000L +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x00000018 +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000ffL +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x00000000 +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000ff00L +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x00000008 +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000ffL +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x00000000 +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000ff00L +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x00000008 +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00ff0000L +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x00000010 +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xff000000L +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x00000018 +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000ffL +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x00000000 +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000ff00L +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x00000008 +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00ff0000L +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x00000010 +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xff000000L +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x00000018 +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000ffL +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x00000000 +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000ff00L +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x00000008 +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00ff0000L +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x00000010 +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xff000000L +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x00000018 +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000ffL +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x00000000 +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000ff00L +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x00000008 +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00ff0000L +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x00000010 +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xff000000L +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x00000018 +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000ffL +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x00000000 +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000ff00L +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x00000008 +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00ff0000L +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x00000010 +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xff000000L +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x00000018 +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000ffL +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x00000000 +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000ff00L +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x00000008 +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00ff0000L +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x00000010 +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xff000000L +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x00000018 +#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L +#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0x0000000c +#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000ffL +#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x00000000 +#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L +#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x00000008 +#define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L +#define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x0000001f +#define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00ffffffL +#define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x00000000 +#define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xff000000L +#define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x00000018 +#define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00ffffffL +#define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x00000000 +#define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00ffffffL +#define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x00000000 +#define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00ffffffL +#define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x00000000 +#define AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L +#define AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x00000004 +#define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L +#define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x00000018 +#define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L +#define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x0000001e +#define AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L +#define AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x00000008 +#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK 0x00000004L +#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT 0x00000002 +#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK 0x00000008L +#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT 0x00000003 +#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xc0000000L +#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x0000001e +#define ATTR00__ATTR_PAL_MASK 0x0000003fL +#define ATTR00__ATTR_PAL__SHIFT 0x00000000 +#define ATTR01__ATTR_PAL_MASK 0x0000003fL +#define ATTR01__ATTR_PAL__SHIFT 0x00000000 +#define ATTR02__ATTR_PAL_MASK 0x0000003fL +#define ATTR02__ATTR_PAL__SHIFT 0x00000000 +#define ATTR03__ATTR_PAL_MASK 0x0000003fL +#define ATTR03__ATTR_PAL__SHIFT 0x00000000 +#define ATTR04__ATTR_PAL_MASK 0x0000003fL +#define ATTR04__ATTR_PAL__SHIFT 0x00000000 +#define ATTR05__ATTR_PAL_MASK 0x0000003fL +#define ATTR05__ATTR_PAL__SHIFT 0x00000000 +#define ATTR06__ATTR_PAL_MASK 0x0000003fL +#define ATTR06__ATTR_PAL__SHIFT 0x00000000 +#define ATTR07__ATTR_PAL_MASK 0x0000003fL +#define ATTR07__ATTR_PAL__SHIFT 0x00000000 +#define ATTR08__ATTR_PAL_MASK 0x0000003fL +#define ATTR08__ATTR_PAL__SHIFT 0x00000000 +#define ATTR09__ATTR_PAL_MASK 0x0000003fL +#define ATTR09__ATTR_PAL__SHIFT 0x00000000 +#define ATTR0A__ATTR_PAL_MASK 0x0000003fL +#define ATTR0A__ATTR_PAL__SHIFT 0x00000000 +#define ATTR0B__ATTR_PAL_MASK 0x0000003fL +#define ATTR0B__ATTR_PAL__SHIFT 0x00000000 +#define ATTR0C__ATTR_PAL_MASK 0x0000003fL +#define ATTR0C__ATTR_PAL__SHIFT 0x00000000 +#define ATTR0D__ATTR_PAL_MASK 0x0000003fL +#define ATTR0D__ATTR_PAL__SHIFT 0x00000000 +#define ATTR0E__ATTR_PAL_MASK 0x0000003fL +#define ATTR0E__ATTR_PAL__SHIFT 0x00000000 +#define ATTR0F__ATTR_PAL_MASK 0x0000003fL +#define ATTR0F__ATTR_PAL__SHIFT 0x00000000 +#define ATTR10__ATTR_BLINK_EN_MASK 0x00000008L +#define ATTR10__ATTR_BLINK_EN__SHIFT 0x00000003 +#define ATTR10__ATTR_CSEL_EN_MASK 0x00000080L +#define ATTR10__ATTR_CSEL_EN__SHIFT 0x00000007 +#define ATTR10__ATTR_GRPH_MODE_MASK 0x00000001L +#define ATTR10__ATTR_GRPH_MODE__SHIFT 0x00000000 +#define ATTR10__ATTR_LGRPH_EN_MASK 0x00000004L +#define ATTR10__ATTR_LGRPH_EN__SHIFT 0x00000002 +#define ATTR10__ATTR_MONO_EN_MASK 0x00000002L +#define ATTR10__ATTR_MONO_EN__SHIFT 0x00000001 +#define ATTR10__ATTR_PANTOPONLY_MASK 0x00000020L +#define ATTR10__ATTR_PANTOPONLY__SHIFT 0x00000005 +#define ATTR10__ATTR_PCLKBY2_MASK 0x00000040L +#define ATTR10__ATTR_PCLKBY2__SHIFT 0x00000006 +#define ATTR11__ATTR_OVSC_MASK 0x000000ffL +#define ATTR11__ATTR_OVSC__SHIFT 0x00000000 +#define ATTR12__ATTR_MAP_EN_MASK 0x0000000fL +#define ATTR12__ATTR_MAP_EN__SHIFT 0x00000000 +#define ATTR12__ATTR_VSMUX_MASK 0x00000030L +#define ATTR12__ATTR_VSMUX__SHIFT 0x00000004 +#define ATTR13__ATTR_PPAN_MASK 0x0000000fL +#define ATTR13__ATTR_PPAN__SHIFT 0x00000000 +#define ATTR14__ATTR_CSEL1_MASK 0x00000003L +#define ATTR14__ATTR_CSEL1__SHIFT 0x00000000 +#define ATTR14__ATTR_CSEL2_MASK 0x0000000cL +#define ATTR14__ATTR_CSEL2__SHIFT 0x00000002 +#define ATTRDR__ATTR_DATA_MASK 0x000000ffL +#define ATTRDR__ATTR_DATA__SHIFT 0x00000000 +#define ATTRDW__ATTR_DATA_MASK 0x000000ffL +#define ATTRDW__ATTR_DATA__SHIFT 0x00000000 +#define ATTRX__ATTR_IDX_MASK 0x0000001fL +#define ATTRX__ATTR_IDX__SHIFT 0x00000000 +#define ATTRX__ATTR_PAL_RW_ENB_MASK 0x00000020L +#define ATTRX__ATTR_PAL_RW_ENB__SHIFT 0x00000005 +#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x00000000 +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x00000000 +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x00000000 +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x00000000 +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x00000000 +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x00000000 +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x00000000 +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x00000000 +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x00000000 +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x00000000 +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x00000000 +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x00000000 +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x00000000 +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x00000000 +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L +#define AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x00000000 +#define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L +#define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x00000019 +#define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L +#define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x00000018 +#define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L +#define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x00000018 +#define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L +#define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0x0000000a +#define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L +#define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x00000008 +#define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000cL +#define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x00000002 +#define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L +#define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x00000011 +#define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L +#define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x00000010 +#define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L +#define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x00000010 +#define AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L +#define AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x0000001d +#define AUX_CONTROL__AUX_EN_MASK 0x00000001L +#define AUX_CONTROL__AUX_EN__SHIFT 0x00000000 +#define AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L +#define AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x00000014 +#define AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L +#define AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x00000010 +#define AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L +#define AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x00000018 +#define AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L +#define AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x00000008 +#define AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L +#define AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0x0000000c +#define AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L +#define AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x00000012 +#define AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L +#define AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x0000001c +#define AUX_CONTROL__SPARE_0_MASK 0x40000000L +#define AUX_CONTROL__SPARE_0__SHIFT 0x0000001e +#define AUX_CONTROL__SPARE_1_MASK 0x80000000L +#define AUX_CONTROL__SPARE_1__SHIFT 0x0000001f +#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L +#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x00000011 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L +#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x00000012 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L +#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x00000013 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L +#define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x0000001c +#define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L +#define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0x0000000c +#define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L +#define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x00000014 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L +#define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x00000008 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L +#define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x00000004 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x07000000L +#define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x00000018 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L +#define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x00000010 +#define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000ffL +#define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x00000000 +#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001f0000L +#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x00000010 +#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3fe00000L +#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x00000015 +#define AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L +#define AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x00000000 +#define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001f00L +#define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x00000008 +#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x00000007L +#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x00000000 +#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003f00L +#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x00000008 +#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L +#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x00000004 +#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01ff0000L +#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x00000010 +#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L +#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x00000000 +#define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L +#define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x00000000 +#define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01ff0000L +#define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x00000010 +#define AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L +#define AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x00000004 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x00000001L +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x00000000 +#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L +#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x00000005 +#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L +#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x00000004 +#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L +#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x00000006 +#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L +#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x00000001 +#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L +#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x00000000 +#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L +#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x00000002 +#define AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000ff00L +#define AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x00000008 +#define AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001f0000L +#define AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x00000010 +#define AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L +#define AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x0000001d +#define AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L +#define AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x00000000 +#define AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L +#define AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x00000009 +#define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L +#define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0x0000000b +#define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1f000000L +#define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x00000018 +#define AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L +#define AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x00000001 +#define AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L +#define AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x00000013 +#define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L +#define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0x0000000e +#define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0x0000000c +#define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L +#define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x00000008 +#define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L +#define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0x0000000a +#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L +#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x00000016 +#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L +#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x00000017 +#define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L +#define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x00000014 +#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L +#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x00000012 +#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L +#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x00000011 +#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L +#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x00000007 +#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L +#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x00000004 +#define AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L +#define AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x0000001f +#define AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L +#define AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x0000001e +#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK_MASK 0x00000400L +#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK__SHIFT 0x0000000a +#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_MASK 0x00000200L +#define AUXN_IMPCAL__AUXN_CALOUT_ERROR__SHIFT 0x00000009 +#define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT_MASK 0x00000100L +#define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT__SHIFT 0x00000008 +#define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE_MASK 0x00000001L +#define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE__SHIFT 0x00000000 +#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000L +#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x0000001c +#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_MASK 0x0f000000L +#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE__SHIFT 0x00000018 +#define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY_MASK 0x00f00000L +#define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY__SHIFT 0x00000014 +#define AUXN_IMPCAL__AUXN_IMPCAL_VALUE_MASK 0x000f0000L +#define AUXN_IMPCAL__AUXN_IMPCAL_VALUE__SHIFT 0x00000010 +#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK_MASK 0x00000400L +#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK__SHIFT 0x0000000a +#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_MASK 0x00000200L +#define AUXP_IMPCAL__AUXP_CALOUT_ERROR__SHIFT 0x00000009 +#define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT_MASK 0x00000100L +#define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT__SHIFT 0x00000008 +#define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE_MASK 0x00000001L +#define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE__SHIFT 0x00000000 +#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000L +#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x0000001c +#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_MASK 0x0f000000L +#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE__SHIFT 0x00000018 +#define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY_MASK 0x00f00000L +#define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY__SHIFT 0x00000014 +#define AUXP_IMPCAL__AUXP_IMPCAL_VALUE_MASK 0x000f0000L +#define AUXP_IMPCAL__AUXP_IMPCAL_VALUE__SHIFT 0x00000010 +#define AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L +#define AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x00000002 +#define AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L +#define AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x00000000 +#define AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000f0L +#define AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x00000004 +#define AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001f0000L +#define AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x00000010 +#define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L +#define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x0000001f +#define AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000ff00L +#define AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L +#define AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x00000000 +#define AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x00000008 +#define AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001f0000L +#define AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x00000010 +#define AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xc0000000L +#define AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x0000001e +#define AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L +#define AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x00000000 +#define AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L +#define AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x00000009 +#define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L +#define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0x0000000b +#define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1f000000L +#define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x00000018 +#define AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L +#define AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x00000001 +#define AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L +#define AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x00000013 +#define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L +#define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0x0000000e +#define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0x0000000c +#define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L +#define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x00000008 +#define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L +#define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0x0000000a +#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L +#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x00000016 +#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L +#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x00000017 +#define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L +#define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x00000014 +#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L +#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x00000012 +#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L +#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x00000011 +#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L +#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x00000007 +#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L +#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x00000004 +#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER_MASK 0xffffffffL +#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER__SHIFT 0x00000000 +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK 0xffff0000L +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT 0x00000010 +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK 0x0000ffffL +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT 0x00000000 +#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK 0x00000300L +#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT 0x00000008 +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK 0x00000030L +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT 0x00000004 +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK 0x00000003L +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT 0x00000000 +#define AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG_MASK 0xffffffffL +#define AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG__SHIFT 0x00000000 +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK 0x00000010L +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT 0x00000004 +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK 0x00000001L +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT 0x00000000 +#define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xffffffffL +#define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x00000000 +#define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xffffffffL +#define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x00000000 +#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE_MASK 0x00000001L +#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE__SHIFT 0x00000000 +#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK 0x00010000L +#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT 0x00000010 +#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK 0x00020000L +#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT 0x00000011 +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK 0x00000030L +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT 0x00000004 +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK 0x00000003L +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK 0x00000070L +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT 0x00000004 +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK 0x00000007L +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000fL +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000f0L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x00000004 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x00000004 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000fL +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0x0000000b +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0x0000000e +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0x0000000f +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007f00L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x00000004 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x00000017 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x00000007 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x00000005 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x00000003 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x00000006 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x00000002 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x00000001 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000ffL +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x00000003 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000f0000L +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x00000009 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x00000004 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x00000001 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0x0000000b +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x00000002 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0x0000000a +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x00000006 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x00000005 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00f00000L +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x00000014 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x00000007 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffffL +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001f0000L +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000fffL +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x00000014 +#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG_MASK 0xffffffffL +#define AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xffffffffL +#define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x000000ffL +#define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x0000003fL +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x00000200L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x00000009 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0x000000f0L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x00000004 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0x0000000fL +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x00000400L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0x0000000a +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x00000001L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0x000000ffL +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xff000000L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x00000018 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xffffffffL +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3fffffffL +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000L +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x0000001e +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000L +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x0000001f +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xffffffffL +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001f0000L +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000fffL +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xffffffffL +#define AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x0000001f +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x00000011 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00fc0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x00000012 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x0000001b +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007fL +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x0000001f +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000f0L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x00000004 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x00000001 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000f000L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x0000000c +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x00000009 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00f00000L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x00000014 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x00000011 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x0000001c +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x00000018 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x00000019 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000f0L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x00000004 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x00000001 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000f000L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0x0000000c +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x00000009 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00f00000L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x00000014 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x00000011 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xf0000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x0000001c +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x00000018 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x00000019 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000f000L +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0x0000000c +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000f0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000f0L +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x00000004 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00f00000L +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x00000014 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x00000018 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000f00L +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x0000001e +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000fL +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x00000004 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000ffL +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffffL +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000ffffL +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xffff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000ffL +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xffffffffL +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xffffffffL +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000ffL +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xff000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x00000018 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000ffL +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xff000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x00000018 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xff000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x00000018 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000ffL +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000ffL +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xff000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x00000018 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000ffL +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x00000007 +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x0000001c +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03ffffffL +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003fL +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +#define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x00000006 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x00000003 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000f0000L +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x00000009 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x00000001 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0x0000000b +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x00000002 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0x0000000a +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x00000006 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x00000005 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00f00000L +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x00000014 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x00000007 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x00000006 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x00000018 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x00000007 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x00000003 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x00000005 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x00000002 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x00000004 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x00000001 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK 0x0000003fL +#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xffffffffL +#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xffffffffL +#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x00000000 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x00000000 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003cL +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x00000002 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x00000002 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x00000000 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x00000007 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x00000003 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003fL +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x00000006 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x00000000 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000fL +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x00000004 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x00000000 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x00000005 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x00000007 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x00000004 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000fL +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x00000000 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000fL +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x00000000 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000f0L +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x00000004 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000fL +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x00000000 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000f0L +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x00000004 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000fL +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x00000000 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000f0L +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x00000004 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000fL +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x00000000 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000f0L +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000fL +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000f0L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000fL +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x00000008 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0x0000000b +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0x0000000e +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK 0x00008000L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT 0x0000000f +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0x0000000f +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK 0x0000007fL +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK 0x00000080L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT 0x00000007 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007f00L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x00000008 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x00000017 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x00000007 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x00000005 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x00000003 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x00000006 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x00000002 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x00000001 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000ffL +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x00000003 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000f0000L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x00000010 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x00000008 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x00000009 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x00000001 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0x0000000b +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x00000002 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0x0000000a +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x00000006 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x00000005 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00f00000L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x00000014 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x00000007 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffffL +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001f0000L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x00000010 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000fffL +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x00000014 +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x0000003fL +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x00000200L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x00000009 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0x000000f0L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0x0000000fL +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x00000400L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0x0000000a +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x00000001L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK 0x000000ffL +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK 0x000000ffL +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK 0x000000ffL +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0x000000ffL +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0x0000ff00L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x00000008 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0x00ff0000L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x00000010 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xff000000L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x00000018 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xffffffffL +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3fffffffL +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000L +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x0000001e +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000L +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x0000001f +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xffffffffL +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xffffffffL +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001f0000L +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x00000010 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000fffL +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xffffffffL +#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK 0xffffffffL +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK 0x00000078L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT 0x00000003 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK 0xffffffffL +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK 0x000000ffL +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000ffL +#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK 0x00000080L +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT 0x00000007 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK 0x00000078L +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT 0x00000003 +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x00000010L +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000ff00L +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x00000008 +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000ffL +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK 0x0000ffffL +#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000f0L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x00000001 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000f0L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x00000001 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x000000f0L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x00000001 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0x000000f0L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x00000001 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x000000f0L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x00000001 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0x000000f0L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x00000001 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0x000000f0L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x00000001 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0x000000f0L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x00000001 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK 0xffffffffL +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK 0xffffffffL +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK 0x0000ffffL +#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0x000000f0L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0x0000000fL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0x0000000fL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0x000000f0L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x0000003fL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0x000000c0L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x00000006 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000f000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0x0000000c +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000f0000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x00000010 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000f0L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00f00000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x00000014 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x00000018 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000f00L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x00000008 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x0000001e +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000fL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK 0xffffffffL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffffL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x0000001f +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK 0x00000200L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT 0x00000009 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK 0x0000fc00L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT 0x0000000a +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK 0x00000100L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT 0x00000008 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK 0x0000007fL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK 0x000000ffL +#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x00000007 +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003fL +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x00000006 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x00000003 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000f0000L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x00000010 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x00000008 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x00000009 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x00000001 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0x0000000b +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x00000002 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0x0000000a +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x00000006 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x00000005 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00f00000L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x00000014 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x00000007 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x00000006 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x00000018 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x00000010 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x00000007 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x00000003 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x00000005 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x00000002 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x00000001 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000ff00L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x00000008 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK 0xffffffffL +#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xffffffffL +#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xffffffffL +#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xffffffffL +#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x00000000 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x00000000 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003cL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x00000002 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x00000002 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x00000000 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x00000007 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x00000003 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003fL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x00000006 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x00000000 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000fL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x00000004 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x00000000 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x00000005 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x00000007 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x00000004 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000fL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x00000000 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000fL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x00000000 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000f0L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x00000004 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000fL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x00000000 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000f0L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x00000004 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000fL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x00000000 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000f0L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x00000004 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000fL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x00000000 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000f0L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x00000004 +#define AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007f00L +#define AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x00000008 +#define AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00ff0000L +#define AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x00000010 +#define AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007fL +#define AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x00000000 +#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x00000006L +#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x00000001 +#define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +#define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x00000000 +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0x0000ffffL +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x00000000 +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xffff0000L +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x00000010 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK 0x000000ffL +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT 0x00000000 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK 0x00000100L +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT 0x00000008 +#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK 0x00000010L +#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT 0x00000004 +#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK 0x00000001L +#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT 0x00000000 +#define AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL_MASK 0x00000030L +#define AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL__SHIFT 0x00000004 +#define AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xffffffffL +#define AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x00000000 +#define AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xffffffffL +#define AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x00000000 +#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000ffL +#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x00000000 +#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x00000008 +#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK 0xffffffffL +#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT 0x00000000 +#define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xffffffffL +#define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x00000000 +#define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA_MASK 0xffffffffL +#define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x00000008L +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x00000003 +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x00000004L +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x00000002 +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xffff0000L +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x00000010 +#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x00000001L +#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x00000000 +#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x00000002L +#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x00000001 +#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x0001ffffL +#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x00000000 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x0000001f +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00ff0000L +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x00000010 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x00000001 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x00000000 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000ff00L +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x00000008 +#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x0001ffffL +#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x00000000 +#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x0001ffffL +#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x00000000 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0x000e0000L +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x00000011 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x0000001f +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x00000018 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x00000001L +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x00000000 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x00000100L +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x00000008 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x00010000L +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x00000010 +#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x0001ffffL +#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x00000000 +#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x0001ffffL +#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x00000000 +#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x0001ffffL +#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x00000000 +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK 0x40000000L +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT 0x0000001e +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_MASK 0x80000000L +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN__SHIFT 0x0000001f +#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK 0x0000ffffL +#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT 0x00000000 +#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT_MASK 0x30000000L +#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT__SHIFT 0x0000001c +#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK 0x0000ffffL +#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT 0x00000000 +#define BL_PWM_CNTL__BL_PWM_EN_MASK 0x80000000L +#define BL_PWM_CNTL__BL_PWM_EN__SHIFT 0x0000001f +#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK 0x40000000L +#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT 0x0000001e +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL_MASK 0x000e0000L +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL__SHIFT 0x00000011 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT 0x0000001f +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT 0x00000018 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK 0x00000001L +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT 0x00000000 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK 0x00000100L +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT 0x00000008 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK 0x00010000L +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT 0x00000010 +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK 0x000f0000L +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT 0x00000010 +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK 0x0000ffffL +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT 0x00000000 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE_MASK 0x10000000L +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE__SHIFT 0x0000001c +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN_MASK 0x00000004L +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN__SHIFT 0x00000002 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN_MASK 0x00000002L +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN__SHIFT 0x00000001 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB_MASK 0x00000001L +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB__SHIFT 0x00000000 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK_MASK 0x00700000L +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK__SHIFT 0x00000014 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST_MASK 0x00003ff0L +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST__SHIFT 0x00000004 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR_MASK 0x0f000000L +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR__SHIFT 0x00000018 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT_MASK 0x003f0000L +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT__SHIFT 0x00000010 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON_MASK 0x10000000L +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON__SHIFT 0x0000001c +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL_MASK 0x00003f00L +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL__SHIFT 0x00000008 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL_MASK 0x00000003L +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL__SHIFT 0x00000000 +#define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK 0x0000007eL +#define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT 0x00000001 +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK 0x00000007L +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x00000004 +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT 0x00000000 +#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK 0x0000ffffL +#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT 0x00000000 +#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK 0xffff0000L +#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT 0x00000010 +#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK 0x0000ffffL +#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT 0x00000000 +#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK 0xffff0000L +#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT 0x00000010 +#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK 0x0000ffffL +#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT 0x00000000 +#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK 0xffff0000L +#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT 0x00000010 +#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK 0x0000ffffL +#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT 0x00000000 +#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK 0xffff0000L +#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT 0x00000010 +#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK 0x0000ffffL +#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT 0x00000000 +#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK 0xffff0000L +#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT 0x00000010 +#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK 0x0000ffffL +#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT 0x00000000 +#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK 0xffff0000L +#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT 0x00000010 +#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK 0x0000ffffL +#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT 0x00000000 +#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK 0xffff0000L +#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT 0x00000010 +#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK 0x0000ffffL +#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT 0x00000000 +#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK 0xffff0000L +#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT 0x00000010 +#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK 0x0000ffffL +#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT 0x00000000 +#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK 0xffff0000L +#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT 0x00000010 +#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK 0x0000ffffL +#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT 0x00000000 +#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK 0xffff0000L +#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT 0x00000010 +#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK 0x0000ffffL +#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT 0x00000000 +#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK 0xffff0000L +#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT 0x00000010 +#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK 0x0000ffffL +#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT 0x00000000 +#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK 0xffff0000L +#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT 0x00000010 +#define CRT00__H_TOTAL_MASK 0x000000ffL +#define CRT00__H_TOTAL__SHIFT 0x00000000 +#define CRT01__H_DISP_END_MASK 0x000000ffL +#define CRT01__H_DISP_END__SHIFT 0x00000000 +#define CRT02__H_BLANK_START_MASK 0x000000ffL +#define CRT02__H_BLANK_START__SHIFT 0x00000000 +#define CRT03__CR10CR11_R_DIS_B_MASK 0x00000080L +#define CRT03__CR10CR11_R_DIS_B__SHIFT 0x00000007 +#define CRT03__H_BLANK_END_MASK 0x0000001fL +#define CRT03__H_BLANK_END__SHIFT 0x00000000 +#define CRT03__H_DE_SKEW_MASK 0x00000060L +#define CRT03__H_DE_SKEW__SHIFT 0x00000005 +#define CRT04__H_SYNC_START_MASK 0x000000ffL +#define CRT04__H_SYNC_START__SHIFT 0x00000000 +#define CRT05__H_BLANK_END_B5_MASK 0x00000080L +#define CRT05__H_BLANK_END_B5__SHIFT 0x00000007 +#define CRT05__H_SYNC_END_MASK 0x0000001fL +#define CRT05__H_SYNC_END__SHIFT 0x00000000 +#define CRT05__H_SYNC_SKEW_MASK 0x00000060L +#define CRT05__H_SYNC_SKEW__SHIFT 0x00000005 +#define CRT06__V_TOTAL_MASK 0x000000ffL +#define CRT06__V_TOTAL__SHIFT 0x00000000 +#define CRT07__LINE_CMP_B8_MASK 0x00000010L +#define CRT07__LINE_CMP_B8__SHIFT 0x00000004 +#define CRT07__V_BLANK_START_B8_MASK 0x00000008L +#define CRT07__V_BLANK_START_B8__SHIFT 0x00000003 +#define CRT07__V_DISP_END_B8_MASK 0x00000002L +#define CRT07__V_DISP_END_B8__SHIFT 0x00000001 +#define CRT07__V_DISP_END_B9_MASK 0x00000040L +#define CRT07__V_DISP_END_B9__SHIFT 0x00000006 +#define CRT07__V_SYNC_START_B8_MASK 0x00000004L +#define CRT07__V_SYNC_START_B8__SHIFT 0x00000002 +#define CRT07__V_SYNC_START_B9_MASK 0x00000080L +#define CRT07__V_SYNC_START_B9__SHIFT 0x00000007 +#define CRT07__V_TOTAL_B8_MASK 0x00000001L +#define CRT07__V_TOTAL_B8__SHIFT 0x00000000 +#define CRT07__V_TOTAL_B9_MASK 0x00000020L +#define CRT07__V_TOTAL_B9__SHIFT 0x00000005 +#define CRT08__BYTE_PAN_MASK 0x00000060L +#define CRT08__BYTE_PAN__SHIFT 0x00000005 +#define CRT08__ROW_SCAN_START_MASK 0x0000001fL +#define CRT08__ROW_SCAN_START__SHIFT 0x00000000 +#define CRT09__DOUBLE_CHAR_HEIGHT_MASK 0x00000080L +#define CRT09__DOUBLE_CHAR_HEIGHT__SHIFT 0x00000007 +#define CRT09__LINE_CMP_B9_MASK 0x00000040L +#define CRT09__LINE_CMP_B9__SHIFT 0x00000006 +#define CRT09__MAX_ROW_SCAN_MASK 0x0000001fL +#define CRT09__MAX_ROW_SCAN__SHIFT 0x00000000 +#define CRT09__V_BLANK_START_B9_MASK 0x00000020L +#define CRT09__V_BLANK_START_B9__SHIFT 0x00000005 +#define CRT0A__CURSOR_DISABLE_MASK 0x00000020L +#define CRT0A__CURSOR_DISABLE__SHIFT 0x00000005 +#define CRT0A__CURSOR_START_MASK 0x0000001fL +#define CRT0A__CURSOR_START__SHIFT 0x00000000 +#define CRT0B__CURSOR_END_MASK 0x0000001fL +#define CRT0B__CURSOR_END__SHIFT 0x00000000 +#define CRT0B__CURSOR_SKEW_MASK 0x00000060L +#define CRT0B__CURSOR_SKEW__SHIFT 0x00000005 +#define CRT0C__DISP_START_MASK 0x000000ffL +#define CRT0C__DISP_START__SHIFT 0x00000000 +#define CRT0D__DISP_START_MASK 0x000000ffL +#define CRT0D__DISP_START__SHIFT 0x00000000 +#define CRT0E__CURSOR_LOC_HI_MASK 0x000000ffL +#define CRT0E__CURSOR_LOC_HI__SHIFT 0x00000000 +#define CRT0F__CURSOR_LOC_LO_MASK 0x000000ffL +#define CRT0F__CURSOR_LOC_LO__SHIFT 0x00000000 +#define CRT10__V_SYNC_START_MASK 0x000000ffL +#define CRT10__V_SYNC_START__SHIFT 0x00000000 +#define CRT11__C0T7_WR_ONLY_MASK 0x00000080L +#define CRT11__C0T7_WR_ONLY__SHIFT 0x00000007 +#define CRT11__SEL5_REFRESH_CYC_MASK 0x00000040L +#define CRT11__SEL5_REFRESH_CYC__SHIFT 0x00000006 +#define CRT11__V_INTR_CLR_MASK 0x00000010L +#define CRT11__V_INTR_CLR__SHIFT 0x00000004 +#define CRT11__V_INTR_EN_MASK 0x00000020L +#define CRT11__V_INTR_EN__SHIFT 0x00000005 +#define CRT11__V_SYNC_END_MASK 0x0000000fL +#define CRT11__V_SYNC_END__SHIFT 0x00000000 +#define CRT12__V_DISP_END_MASK 0x000000ffL +#define CRT12__V_DISP_END__SHIFT 0x00000000 +#define CRT13__DISP_PITCH_MASK 0x000000ffL +#define CRT13__DISP_PITCH__SHIFT 0x00000000 +#define CRT14__ADDR_CNT_BY4_MASK 0x00000020L +#define CRT14__ADDR_CNT_BY4__SHIFT 0x00000005 +#define CRT14__DOUBLE_WORD_MASK 0x00000040L +#define CRT14__DOUBLE_WORD__SHIFT 0x00000006 +#define CRT14__UNDRLN_LOC_MASK 0x0000001fL +#define CRT14__UNDRLN_LOC__SHIFT 0x00000000 +#define CRT15__V_BLANK_START_MASK 0x000000ffL +#define CRT15__V_BLANK_START__SHIFT 0x00000000 +#define CRT16__V_BLANK_END_MASK 0x000000ffL +#define CRT16__V_BLANK_END__SHIFT 0x00000000 +#define CRT17__ADDR_CNT_BY2_MASK 0x00000008L +#define CRT17__ADDR_CNT_BY2__SHIFT 0x00000003 +#define CRT17__BYTE_MODE_MASK 0x00000040L +#define CRT17__BYTE_MODE__SHIFT 0x00000006 +#define CRT17__CRTC_SYNC_EN_MASK 0x00000080L +#define CRT17__CRTC_SYNC_EN__SHIFT 0x00000007 +#define CRT17__RA0_AS_A13B_MASK 0x00000001L +#define CRT17__RA0_AS_A13B__SHIFT 0x00000000 +#define CRT17__RA1_AS_A14B_MASK 0x00000002L +#define CRT17__RA1_AS_A14B__SHIFT 0x00000001 +#define CRT17__VCOUNT_BY2_MASK 0x00000004L +#define CRT17__VCOUNT_BY2__SHIFT 0x00000002 +#define CRT17__WRAP_A15TOA0_MASK 0x00000020L +#define CRT17__WRAP_A15TOA0__SHIFT 0x00000005 +#define CRT18__LINE_CMP_MASK 0x000000ffL +#define CRT18__LINE_CMP__SHIFT 0x00000000 +#define CRT1E__GRPH_DEC_RD1_MASK 0x00000002L +#define CRT1E__GRPH_DEC_RD1__SHIFT 0x00000001 +#define CRT1F__GRPH_DEC_RD0_MASK 0x000000ffL +#define CRT1F__GRPH_DEC_RD0__SHIFT 0x00000000 +#define CRT22__GRPH_LATCH_DATA_MASK 0x000000ffL +#define CRT22__GRPH_LATCH_DATA__SHIFT 0x00000000 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL_MASK 0x00000100L +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL__SHIFT 0x00000008 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT_MASK 0x0fff0000L +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT__SHIFT 0x00000010 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR_MASK 0x0000c000L +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR__SHIFT 0x0000000e +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL_MASK 0x00000200L +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL__SHIFT 0x00000009 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE__SHIFT 0x00000000 +#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK 0x00000010L +#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT 0x00000004 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL_MASK 0x00000100L +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL__SHIFT 0x00000008 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT_MASK 0x0fff0000L +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT__SHIFT 0x00000010 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR_MASK 0x0000c000L +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR__SHIFT 0x0000000e +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL_MASK 0x00000200L +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL__SHIFT 0x00000009 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE__SHIFT 0x00000000 +#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK 0x00000010L +#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT 0x00000004 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL_MASK 0x00000100L +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL__SHIFT 0x00000008 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT_MASK 0x0fff0000L +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT__SHIFT 0x00000010 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR_MASK 0x0000c000L +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR__SHIFT 0x0000000e +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL_MASK 0x00000200L +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL__SHIFT 0x00000009 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE__SHIFT 0x00000000 +#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK 0x00000010L +#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT 0x00000004 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x00000010L +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x00000004 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x00000001L +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x00000000 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0x000c0000L +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x00000011 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x00000010 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x00000012 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0x0000000c +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x00000008 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL_MASK 0x00000100L +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL__SHIFT 0x00000008 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT_MASK 0x0fff0000L +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT__SHIFT 0x00000010 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR_MASK 0x0000c000L +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR__SHIFT 0x0000000e +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL_MASK 0x00000200L +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL__SHIFT 0x00000009 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE__SHIFT 0x00000000 +#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK 0x00000010L +#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT 0x00000004 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL_MASK 0x00000100L +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL__SHIFT 0x00000008 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT_MASK 0x0fff0000L +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT__SHIFT 0x00000010 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR_MASK 0x0000c000L +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR__SHIFT 0x0000000e +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL_MASK 0x00000200L +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL__SHIFT 0x00000009 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE__SHIFT 0x00000000 +#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE_MASK 0x00000010L +#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE__SHIFT 0x00000004 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL_MASK 0x00000100L +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL__SHIFT 0x00000008 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT_MASK 0x0fff0000L +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT__SHIFT 0x00000010 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR_MASK 0x0000c000L +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR__SHIFT 0x0000000e +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL_MASK 0x00000200L +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL__SHIFT 0x00000009 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE__SHIFT 0x00000000 +#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE_MASK 0x00000010L +#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE__SHIFT 0x00000004 +#define CRTC8_DATA__VCRTC_DATA_MASK 0x000000ffL +#define CRTC8_DATA__VCRTC_DATA__SHIFT 0x00000000 +#define CRTC8_IDX__VCRTC_IDX_MASK 0x0000003fL +#define CRTC8_IDX__VCRTC_IDX__SHIFT 0x00000000 +#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0x000000ffL +#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x00000000 +#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x00010000L +#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x00000010 +#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x000003ffL +#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x00000000 +#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0x000ffc00L +#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0x0000000a +#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3ff00000L +#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x00000014 +#define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x00000100L +#define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x00000008 +#define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x00010000L +#define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x00000010 +#define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x00000001L +#define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x00000000 +#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003ffL +#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x00000000 +#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000ffc00L +#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0x0000000a +#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3ff00000L +#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x00000014 +#define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x00010000L +#define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x00000010 +#define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x00000300L +#define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x00000008 +#define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE_MASK 0x01000000L +#define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE__SHIFT 0x00000018 +#define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x00002000L +#define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0x0000000d +#define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x00700000L +#define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x00000014 +#define CRTC_CONTROL__CRTC_MASTER_EN_MASK 0x00000001L +#define CRTC_CONTROL__CRTC_MASTER_EN__SHIFT 0x00000000 +#define CRTC_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000L +#define CRTC_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x0000001d +#define CRTC_CONTROL__CRTC_START_POINT_CNTL_MASK 0x00001000L +#define CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0x0000000c +#define CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x00000010L +#define CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x00000004 +#define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x00000001L +#define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x00000000 +#define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x0000001eL +#define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x00000001 +#define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x00000001L +#define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x00000000 +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE_MASK 0x80000000L +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE__SHIFT 0x0000001f +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_TEST_CLK_SEL_MASK 0x1f000000L +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_TEST_CLK_SEL__SHIFT 0x00000018 +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_DCP_GATE_DISABLE_MASK 0x00000100L +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_DCP_GATE_DISABLE__SHIFT 0x00000008 +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_SCL_GATE_DISABLE_MASK 0x00001000L +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_SCL_GATE_DISABLE__SHIFT 0x0000000c +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_R_DCFE_GATE_DISABLE_MASK 0x00000010L +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_R_DCFE_GATE_DISABLE__SHIFT 0x00000004 +#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L +#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x00000010 +#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x00000100L +#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x00000008 +#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x00000001L +#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x00000000 +#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x0000001eL +#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x00000001 +#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x00000001L +#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x00000000 +#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x1fff0000L +#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x00000010 +#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x00001fffL +#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x00000000 +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x00000010 +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x00000018 +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x00000100L +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x00000008 +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001fL +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x00000000 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x00000004 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x00000018 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x00000003L +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x00000000 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x00000010 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x00000008 +#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L +#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x0000001c +#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x00001fffL +#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x00000000 +#define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x001f0000L +#define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x00000010 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x00000013 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0x0000ff00L +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x00000008 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0x000000ffL +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x00000000 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xff000000L +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x00000017 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x00060000L +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x00000011 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x00000014 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x00000018 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x00000010 +#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x1fff0000L +#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x00000010 +#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x00001fffL +#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x00000000 +#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x00010000L +#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x00000010 +#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x000003ffL +#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x00000000 +#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x1fff0000L +#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x00000010 +#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x00001fffL +#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x00000000 +#define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x00010000L +#define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x00000010 +#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x00020000L +#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x00000011 +#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x00000001L +#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x00000000 +#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x1fff0000L +#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x00000010 +#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x00001fffL +#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x00000000 +#define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x00010000L +#define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x00000010 +#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x00020000L +#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x00000011 +#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x00000001L +#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x00000000 +#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x1fff0000L +#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x00000010 +#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x00001fffL +#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x00000000 +#define CRTC_H_TOTAL__CRTC_H_TOTAL_MASK 0x00001fffL +#define CRTC_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x00000000 +#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x00000001L +#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x00000000 +#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L +#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x00000010 +#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x00000001L +#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x00000000 +#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x00000002L +#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x00000001 +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x00000008 +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x00000009 +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x00000010 +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x00000011 +#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L +#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x0000001e +#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L +#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x0000001f +#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x00000001L +#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x00000000 +#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x00000002L +#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x00000001 +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x01000000L +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x00000018 +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x04000000L +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x0000001a +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x02000000L +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x00000019 +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x08000000L +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x0000001b +#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000L +#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x0000001c +#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000L +#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x0000001d +#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x00000010L +#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x00000004 +#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x00000020L +#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x00000005 +#define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L +#define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x00000000 +#define CRTC_MASTER_EN__CRTC_MASTER_EN_MASK 0x00000001L +#define CRTC_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x00000000 +#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xffffff00L +#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x00000008 +#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x00000003L +#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x00000000 +#define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0x000000ffL +#define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x00000000 +#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x00100000L +#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x00000014 +#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x00000010L +#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x00000004 +#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x00010000L +#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x00000010 +#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x00000001L +#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x00000000 +#define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x00001fffL +#define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x00000000 +#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x000003ffL +#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x00000000 +#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0x000ffc00L +#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0x0000000a +#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3ff00000L +#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x00000014 +#define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L +#define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x00000000 +#define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0x00ffffffL +#define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x00000000 +#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x1fff0000L +#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x00000010 +#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x00001fffL +#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x00000000 +#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x00000002L +#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x00000001 +#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L +#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x00000002 +#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x00000001L +#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x00000000 +#define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0x000f0000L +#define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0x00000010 +#define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x00000100L +#define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x00000008 +#define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x00000001L +#define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x00000000 +#define CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x00020000L +#define CRTC_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x00000011 +#define CRTC_STATUS__CRTC_H_BLANK_MASK 0x00010000L +#define CRTC_STATUS__CRTC_H_BLANK__SHIFT 0x00000010 +#define CRTC_STATUS__CRTC_H_SYNC_A_MASK 0x00040000L +#define CRTC_STATUS__CRTC_H_SYNC_A__SHIFT 0x00000012 +#define CRTC_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x00000002L +#define CRTC_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x00000001 +#define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x00000020L +#define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x00000005 +#define CRTC_STATUS__CRTC_V_BLANK_MASK 0x00000001L +#define CRTC_STATUS__CRTC_V_BLANK__SHIFT 0x00000000 +#define CRTC_STATUS__CRTC_V_START_LINE_MASK 0x00000010L +#define CRTC_STATUS__CRTC_V_START_LINE__SHIFT 0x00000004 +#define CRTC_STATUS__CRTC_V_SYNC_A_MASK 0x00000004L +#define CRTC_STATUS__CRTC_V_SYNC_A__SHIFT 0x00000002 +#define CRTC_STATUS__CRTC_V_UPDATE_MASK 0x00000008L +#define CRTC_STATUS__CRTC_V_UPDATE__SHIFT 0x00000003 +#define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0x00ffffffL +#define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x00000000 +#define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x1fffffffL +#define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x00000000 +#define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x1fff0000L +#define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x00000010 +#define CRTC_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x00001fffL +#define CRTC_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x00000000 +#define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x1fffffffL +#define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x00000000 +#define CRTC_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x01000000L +#define CRTC_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x00000018 +#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00001fffL +#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x00000000 +#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L +#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0x0000000f +#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x00010000L +#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x00000010 +#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L +#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x00000000 +#define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x00000001L +#define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x00000000 +#define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L +#define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x00000018 +#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x00000100L +#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x00000008 +#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x00010000L +#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x00000010 +#define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA_MASK 0xffffffffL +#define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0x0000ffffL +#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x00000000 +#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x003f0000L +#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x00000010 +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xff000000L +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x00000018 +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x00010000L +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x00000010 +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x00000001L +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x00000000 +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x00000700L +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x00000008 +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0x0000f000L +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0x0000000c +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0x0000000fL +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x00000000 +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0x000000f0L +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x00000004 +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xffff0000L +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x00000010 +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0x00000f00L +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x00000008 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000L +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x0000001f +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1f000000L +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x00000018 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x00000010 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x00000014 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x00000200L +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x00000009 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x00000800L +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0x0000000b +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0x000000e0L +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x00000005 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x00000400L +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0x0000000a +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000100L +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x00000008 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x0000000c +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x0000001fL +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x00000000 +#define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x00000001L +#define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x00000000 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000L +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x0000001f +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1f000000L +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x00000018 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x00000010 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x00000014 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x00000200L +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x00000009 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x00000800L +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0x0000000b +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0x000000e0L +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x00000005 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x00000400L +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0x0000000a +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000100L +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x00000008 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x0000000c +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x0000001fL +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x00000000 +#define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x00000001L +#define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x00000000 +#define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x00000001L +#define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x00000000 +#define CRTC_VBI_END__CRTC_VBI_H_END_MASK 0x1fff0000L +#define CRTC_VBI_END__CRTC_VBI_H_END__SHIFT 0x00000010 +#define CRTC_VBI_END__CRTC_VBI_V_END_MASK 0x00001fffL +#define CRTC_VBI_END__CRTC_VBI_V_END__SHIFT 0x00000000 +#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x1fff0000L +#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x00000010 +#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x00001fffL +#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x00000000 +#define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L +#define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x00000010 +#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L +#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x00000008 +#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L +#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x00000000 +#define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x00000001L +#define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x00000000 +#define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x00000001L +#define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x00000000 +#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x1fff0000L +#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x00000010 +#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x00001fffL +#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x00000000 +#define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x00000001L +#define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x00000000 +#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x1fff0000L +#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x00000010 +#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x00001fffL +#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x00000000 +#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L +#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x00000004 +#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x00000001L +#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x00000000 +#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x00000100L +#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x00000008 +#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x00001000L +#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0x0000000c +#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xffff0000L +#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x00000010 +#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x00000010L +#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x00000004 +#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x00000001L +#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x00000000 +#define CRTC_V_TOTAL__CRTC_V_TOTAL_MASK 0x00001fffL +#define CRTC_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x00000000 +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x00000008 +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x00000004 +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0x0000000c +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x00000000 +#define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x00010000L +#define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x00000010 +#define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x00001fffL +#define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x00000000 +#define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x00001fffL +#define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x00000000 +#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x00000100L +#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x00000008 +#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x00000001L +#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x00000000 +#define CUR_COLOR1__CUR_COLOR1_BLUE_MASK 0x000000ffL +#define CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT 0x00000000 +#define CUR_COLOR1__CUR_COLOR1_GREEN_MASK 0x0000ff00L +#define CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT 0x00000008 +#define CUR_COLOR1__CUR_COLOR1_RED_MASK 0x00ff0000L +#define CUR_COLOR1__CUR_COLOR1_RED__SHIFT 0x00000010 +#define CUR_COLOR2__CUR_COLOR2_BLUE_MASK 0x000000ffL +#define CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT 0x00000000 +#define CUR_COLOR2__CUR_COLOR2_GREEN_MASK 0x0000ff00L +#define CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT 0x00000008 +#define CUR_COLOR2__CUR_COLOR2_RED_MASK 0x00ff0000L +#define CUR_COLOR2__CUR_COLOR2_RED__SHIFT 0x00000010 +#define CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK 0x00000010L +#define CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT 0x00000004 +#define CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00010000L +#define CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x00000010 +#define CUR_CONTROL__CURSOR_EN_MASK 0x00000001L +#define CUR_CONTROL__CURSOR_EN__SHIFT 0x00000000 +#define CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK 0x00100000L +#define CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT 0x00000014 +#define CUR_CONTROL__CURSOR_MODE_MASK 0x00000300L +#define CUR_CONTROL__CURSOR_MODE__SHIFT 0x00000008 +#define CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK 0x07000000L +#define CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT 0x00000018 +#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x003f0000L +#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x00000010 +#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x0000003fL +#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x00000000 +#define CUR_POSITION__CURSOR_X_POSITION_MASK 0x3fff0000L +#define CUR_POSITION__CURSOR_X_POSITION__SHIFT 0x00000010 +#define CUR_POSITION__CURSOR_Y_POSITION_MASK 0x00003fffL +#define CUR_POSITION__CURSOR_Y_POSITION__SHIFT 0x00000000 +#define CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK 0x00000001L +#define CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT 0x00000000 +#define CUR_SIZE__CURSOR_HEIGHT_MASK 0x0000003fL +#define CUR_SIZE__CURSOR_HEIGHT__SHIFT 0x00000000 +#define CUR_SIZE__CURSOR_WIDTH_MASK 0x003f0000L +#define CUR_SIZE__CURSOR_WIDTH__SHIFT 0x00000010 +#define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xffffffffL +#define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x00000000 +#define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x000000ffL +#define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x00000000 +#define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L +#define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT 0x00000018 +#define CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK 0x00010000L +#define CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT 0x00000010 +#define CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK 0x00000001L +#define CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT 0x00000000 +#define CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK 0x00000002L +#define CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT 0x00000001 +#define D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK 0x00000001L +#define D1VGA_CONTROL__D1VGA_MODE_ENABLE__SHIFT 0x00000000 +#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT 0x00000010 +#define D1VGA_CONTROL__D1VGA_ROTATE_MASK 0x03000000L +#define D1VGA_CONTROL__D1VGA_ROTATE__SHIFT 0x00000018 +#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT__SHIFT 0x00000009 +#define D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK 0x00000100L +#define D1VGA_CONTROL__D1VGA_TIMING_SELECT__SHIFT 0x00000008 +#define D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK 0x00000001L +#define D2VGA_CONTROL__D2VGA_MODE_ENABLE__SHIFT 0x00000000 +#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT 0x00000010 +#define D2VGA_CONTROL__D2VGA_ROTATE_MASK 0x03000000L +#define D2VGA_CONTROL__D2VGA_ROTATE__SHIFT 0x00000018 +#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT__SHIFT 0x00000009 +#define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK 0x00000100L +#define D2VGA_CONTROL__D2VGA_TIMING_SELECT__SHIFT 0x00000008 +#define D3VGA_CONTROL__D3VGA_MODE_ENABLE_MASK 0x00000001L +#define D3VGA_CONTROL__D3VGA_MODE_ENABLE__SHIFT 0x00000000 +#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN__SHIFT 0x00000010 +#define D3VGA_CONTROL__D3VGA_ROTATE_MASK 0x03000000L +#define D3VGA_CONTROL__D3VGA_ROTATE__SHIFT 0x00000018 +#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT__SHIFT 0x00000009 +#define D3VGA_CONTROL__D3VGA_TIMING_SELECT_MASK 0x00000100L +#define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT 0x00000008 +#define D4VGA_CONTROL__D4VGA_MODE_ENABLE_MASK 0x00000001L +#define D4VGA_CONTROL__D4VGA_MODE_ENABLE__SHIFT 0x00000000 +#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN__SHIFT 0x00000010 +#define D4VGA_CONTROL__D4VGA_ROTATE_MASK 0x03000000L +#define D4VGA_CONTROL__D4VGA_ROTATE__SHIFT 0x00000018 +#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT__SHIFT 0x00000009 +#define D4VGA_CONTROL__D4VGA_TIMING_SELECT_MASK 0x00000100L +#define D4VGA_CONTROL__D4VGA_TIMING_SELECT__SHIFT 0x00000008 +#define D5VGA_CONTROL__D5VGA_MODE_ENABLE_MASK 0x00000001L +#define D5VGA_CONTROL__D5VGA_MODE_ENABLE__SHIFT 0x00000000 +#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN__SHIFT 0x00000010 +#define D5VGA_CONTROL__D5VGA_ROTATE_MASK 0x03000000L +#define D5VGA_CONTROL__D5VGA_ROTATE__SHIFT 0x00000018 +#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT__SHIFT 0x00000009 +#define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK 0x00000100L +#define D5VGA_CONTROL__D5VGA_TIMING_SELECT__SHIFT 0x00000008 +#define D6VGA_CONTROL__D6VGA_MODE_ENABLE_MASK 0x00000001L +#define D6VGA_CONTROL__D6VGA_MODE_ENABLE__SHIFT 0x00000000 +#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN__SHIFT 0x00000010 +#define D6VGA_CONTROL__D6VGA_ROTATE_MASK 0x03000000L +#define D6VGA_CONTROL__D6VGA_ROTATE__SHIFT 0x00000018 +#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT__SHIFT 0x00000009 +#define D6VGA_CONTROL__D6VGA_TIMING_SELECT_MASK 0x00000100L +#define D6VGA_CONTROL__D6VGA_TIMING_SELECT__SHIFT 0x00000008 +#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER_MASK 0x000000ffL +#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER__SHIFT 0x00000000 +#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE_MASK 0x00000100L +#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE__SHIFT 0x00000008 +#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY_MASK 0x000000ffL +#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY__SHIFT 0x00000000 +#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY_MASK 0x0000ff00L +#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY__SHIFT 0x00000008 +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK_MASK 0x00070000L +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK__SHIFT 0x00000010 +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER_MASK 0x0000ff00L +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER__SHIFT 0x00000008 +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE_MASK 0x00000003L +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE__SHIFT 0x00000000 +#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK_MASK 0x00000001L +#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK__SHIFT 0x00000000 +#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE_MASK 0x00010000L +#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE__SHIFT 0x00000010 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE_MASK 0x03000000L +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE__SHIFT 0x00000018 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT_MASK 0x00000010L +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT__SHIFT 0x00000004 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE_MASK 0x00030000L +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE__SHIFT 0x00000010 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE_MASK 0x00000300L +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE__SHIFT 0x00000008 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS_MASK 0x00000001L +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS__SHIFT 0x00000000 +#define DAC_CLK_ENABLE__DACA_CLK_ENABLE_MASK 0x00000001L +#define DAC_CLK_ENABLE__DACA_CLK_ENABLE__SHIFT 0x00000000 +#define DAC_CLK_ENABLE__DACB_CLK_ENABLE_MASK 0x00000010L +#define DAC_CLK_ENABLE__DACB_CLK_ENABLE__SHIFT 0x00000004 +#define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE_MASK 0x00040000L +#define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE__SHIFT 0x00000012 +#define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN_MASK 0x00000001L +#define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN__SHIFT 0x00000000 +#define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN_MASK 0x00000100L +#define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN__SHIFT 0x00000008 +#define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE_MASK 0x00020000L +#define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE__SHIFT 0x00000011 +#define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE_MASK 0x00010000L +#define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE__SHIFT 0x00000010 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE_MASK 0x00000002L +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE__SHIFT 0x00000001 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN_MASK 0x00000004L +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN__SHIFT 0x00000002 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_MASK 0x00000001L +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED_MASK 0x00000008L +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED__SHIFT 0x00000003 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT__SHIFT 0x00000000 +#define DAC_CONTROL__DAC_DFORCE_EN_MASK 0x00000001L +#define DAC_CONTROL__DAC_DFORCE_EN__SHIFT 0x00000000 +#define DAC_CONTROL__DAC_TV_ENABLE_MASK 0x00000100L +#define DAC_CONTROL__DAC_TV_ENABLE__SHIFT 0x00000008 +#define DAC_CONTROL__DAC_ZSCALE_SHIFT_MASK 0x00010000L +#define DAC_CONTROL__DAC_ZSCALE_SHIFT__SHIFT 0x00000010 +#define DAC_CRC_CONTROL__DAC_CRC_FIELD_MASK 0x00000001L +#define DAC_CRC_CONTROL__DAC_CRC_FIELD__SHIFT 0x00000000 +#define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKb_MASK 0x00000100L +#define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKb__SHIFT 0x00000008 +#define DAC_CRC_EN__DAC_CRC_CONT_EN_MASK 0x00010000L +#define DAC_CRC_EN__DAC_CRC_CONT_EN__SHIFT 0x00000010 +#define DAC_CRC_EN__DAC_CRC_EN_MASK 0x00000001L +#define DAC_CRC_EN__DAC_CRC_EN__SHIFT 0x00000000 +#define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL_MASK 0x0000003fL +#define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL__SHIFT 0x00000000 +#define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK_MASK 0x0000003fL +#define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK__SHIFT 0x00000000 +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE_MASK 0x000003ffL +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE__SHIFT 0x00000000 +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN_MASK 0x000ffc00L +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN__SHIFT 0x0000000a +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED_MASK 0x3ff00000L +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED__SHIFT 0x00000014 +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK_MASK 0x000003ffL +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK__SHIFT 0x00000000 +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK_MASK 0x000ffc00L +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK__SHIFT 0x0000000a +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK_MASK 0x3ff00000L +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK__SHIFT 0x00000014 +#define DAC_DATA__DAC_DATA_MASK 0x0000003fL +#define DAC_DATA__DAC_DATA__SHIFT 0x00000000 +#define DAC_DFT_CONFIG__DAC_DFT_CONFIG_MASK 0xffffffffL +#define DAC_DFT_CONFIG__DAC_DFT_CONFIG__SHIFT 0x00000000 +#define DAC_ENABLE__DAC_ENABLE_MASK 0x00000001L +#define DAC_ENABLE__DAC_ENABLE__SHIFT 0x00000000 +#define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE_MASK 0x00000002L +#define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE__SHIFT 0x00000001 +#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK_MASK 0x00000020L +#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK__SHIFT 0x00000005 +#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_MASK 0x00000010L +#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR__SHIFT 0x00000004 +#define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW_MASK 0x0000000cL +#define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW__SHIFT 0x00000002 +#define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM_MASK 0x00000100L +#define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM__SHIFT 0x00000008 +#define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000fc00L +#define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x0000000a +#define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED_MASK 0x20000000L +#define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED__SHIFT 0x0000001d +#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x0000001e +#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x0000001f +#define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL_MASK 0x000f0000L +#define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL__SHIFT 0x00000010 +#define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL_MASK 0x03c00000L +#define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL__SHIFT 0x00000016 +#define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL_MASK 0x000000fcL +#define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL__SHIFT 0x00000002 +#define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x00000001 +#define DAC_FORCE_DATA__DAC_FORCE_DATA_MASK 0x000003ffL +#define DAC_FORCE_DATA__DAC_FORCE_DATA__SHIFT 0x00000000 +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN_MASK 0x00000001L +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN__SHIFT 0x00000000 +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKb_ONLY_MASK 0x01000000L +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKb_ONLY__SHIFT 0x00000018 +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL_MASK 0x00000700L +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL__SHIFT 0x00000008 +#define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffffL +#define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED__SHIFT 0x00000000 +#define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffffL +#define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED__SHIFT 0x00000000 +#define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffffL +#define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED__SHIFT 0x00000000 +#define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffffL +#define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED__SHIFT 0x00000000 +#define DAC_MASK__DAC_MASK_MASK 0x000000ffL +#define DAC_MASK__DAC_MASK__SHIFT 0x00000000 +#define DAC_POWERDOWN__DAC_POWERDOWN_BLUE_MASK 0x00000100L +#define DAC_POWERDOWN__DAC_POWERDOWN_BLUE__SHIFT 0x00000008 +#define DAC_POWERDOWN__DAC_POWERDOWN_GREEN_MASK 0x00010000L +#define DAC_POWERDOWN__DAC_POWERDOWN_GREEN__SHIFT 0x00000010 +#define DAC_POWERDOWN__DAC_POWERDOWN_MASK 0x00000001L +#define DAC_POWERDOWN__DAC_POWERDOWN_RED_MASK 0x01000000L +#define DAC_POWERDOWN__DAC_POWERDOWN_RED__SHIFT 0x00000018 +#define DAC_POWERDOWN__DAC_POWERDOWN__SHIFT 0x00000000 +#define DAC_PWR_CNTL__DAC_BG_MODE_MASK 0x00000003L +#define DAC_PWR_CNTL__DAC_BG_MODE__SHIFT 0x00000000 +#define DAC_PWR_CNTL__DAC_PWRCNTL_MASK 0x00030000L +#define DAC_PWR_CNTL__DAC_PWRCNTL__SHIFT 0x00000010 +#define DAC_R_INDEX__DAC_R_INDEX_MASK 0x000000ffL +#define DAC_R_INDEX__DAC_R_INDEX__SHIFT 0x00000000 +#define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT_MASK 0x00000007L +#define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT__SHIFT 0x00000000 +#define DAC_SOURCE_SELECT__DAC_TV_SELECT_MASK 0x00000008L +#define DAC_SOURCE_SELECT__DAC_TV_SELECT__SHIFT 0x00000003 +#define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT_MASK 0x00000007L +#define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT__SHIFT 0x00000000 +#define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE_MASK 0x00000001L +#define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE__SHIFT 0x00000000 +#define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE_MASK 0x00010000L +#define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE__SHIFT 0x00000010 +#define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE_MASK 0x00000100L +#define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE__SHIFT 0x00000008 +#define DAC_W_INDEX__DAC_W_INDEX_MASK 0x000000ffL +#define DAC_W_INDEX__DAC_W_INDEX__SHIFT 0x00000000 +#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x00000100L +#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x00000008 +#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x00000001L +#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x00000000 +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000L +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x0000001f +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x07ff0000L +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x00000010 +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x00007fffL +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x00000000 +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000L +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x0000001f +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x07ff0000L +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x00000010 +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x00007fffL +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x00000000 +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000L +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x0000001f +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x07ff0000L +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x00000010 +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x00007fffL +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x00000000 +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000L +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x0000001f +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x07ff0000L +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x00000010 +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x00007fffL +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x00000000 +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000L +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x0000001f +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x07ff0000L +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x00000010 +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x00007fffL +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x00000000 +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000L +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x0000001f +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x000003ffL +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x00000000 +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x03ff0000L +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x00000010 +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000L +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x0000001e +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000L +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x0000001c +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000L +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x0000001f +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000L +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x0000001d +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x000003ffL +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x00000000 +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x03ff0000L +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x00000010 +#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000L +#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x0000001f +#define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE_MASK 0x80000000L +#define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE__SHIFT 0x0000001f +#define DC_ABM1_CNTL__ABM1_EN_MASK 0x00000001L +#define DC_ABM1_CNTL__ABM1_EN__SHIFT 0x00000000 +#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT_MASK 0x00000700L +#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT__SHIFT 0x00000008 +#define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT_MASK 0x00010000L +#define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT__SHIFT 0x00000010 +#define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT_MASK 0x00000001L +#define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT__SHIFT 0x00000000 +#define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT_MASK 0x00000100L +#define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT__SHIFT 0x00000008 +#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xffffffffL +#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x00000000 +#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xffffffffL +#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x00000000 +#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xffffffffL +#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x00000000 +#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xffffffffL +#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x00000000 +#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xffffffffL +#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x00000000 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x00000004L +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x00000002 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000L +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x0000001f +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x00000400L +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0x0000000a +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x00000001L +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x00000000 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x00010000L +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x00000010 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x00000100L +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x00000008 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x00000002L +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x00000001 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x01000000L +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x00000018 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x00000200L +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x00000009 +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x00800000L +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x00000017 +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x07000000L +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x00000018 +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000L +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x0000001c +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000L +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x0000001e +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x00030000L +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x00000010 +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x00001000L +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0x0000000c +#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000L +#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x0000001d +#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x0000001f +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x00000003L +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x00000000 +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x00000100L +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x00000008 +#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x00100000L +#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x00000014 +#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x00000000 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00ff0000L +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x00000010 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x0000001f +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x00000001 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x00000000 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000ff00L +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x00000008 +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x0000001f +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0x0000000fL +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x00000000 +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0x00000f00L +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x00000008 +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0x000f0000L +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x00000010 +#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x03ff0000L +#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x00000010 +#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x000003ffL +#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x00000000 +#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0x00ffffffL +#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x00000000 +#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x03ff0000L +#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x00000010 +#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x000003ffL +#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x00000000 +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x0000001f +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x03ff0000L +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x00000010 +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x000003ffL +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x00000000 +#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0x00ffffffL +#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x00000000 +#define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN_MASK 0x00ffffffL +#define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN__SHIFT 0x00000000 +#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0x00ffffffL +#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x00000000 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x0000001f +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00ff0000L +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x00000010 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x00000001 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x00000000 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000ff00L +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x00000008 +#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xffffffffL +#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x00000000 +#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE_MASK 0x3ff00000L +#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE__SHIFT 0x00000014 +#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE_MASK 0x000ffc00L +#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE__SHIFT 0x0000000a +#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE_MASK 0x000003ffL +#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE__SHIFT 0x00000000 +#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK 0xffffffffL +#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT 0x00000000 +#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK 0xffffffffL +#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT 0x00000000 +#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK 0xffffffffL +#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT 0x00000000 +#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK 0xffffffffL +#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT 0x00000000 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK 0x00000007L +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT 0x00000000 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK 0x00000010L +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT 0x00000004 +#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK 0xffffffffL +#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT 0x00000000 +#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK 0x00000010L +#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT 0x00000004 +#define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE_MASK 0x00000020L +#define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE__SHIFT 0x00000005 +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK 0x00000001L +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT 0x00000000 +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_RAMP_DIV_ID_MASK 0x07000000L +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_RAMP_DIV_ID__SHIFT 0x00000018 +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK 0x00000002L +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT 0x00000001 +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_RAMP_DISABLE_MASK 0x00100000L +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_RAMP_DISABLE__SHIFT 0x00000014 +#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK 0x00000040L +#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT 0x00000006 +#define DCCG_GATE_DISABLE_CNTL__PCLK_TV_GATE_DISABLE_MASK 0x00010000L +#define DCCG_GATE_DISABLE_CNTL__PCLK_TV_GATE_DISABLE__SHIFT 0x00000010 +#define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE_MASK 0x00000004L +#define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE__SHIFT 0x00000002 +#define DCCG_GATE_DISABLE_CNTL__SCLK_RAMP_DIV_ID_MASK 0x70000000L +#define DCCG_GATE_DISABLE_CNTL__SCLK_RAMP_DIV_ID__SHIFT 0x0000001c +#define DCCG_GATE_DISABLE_CNTL__SYMCLKA_GATE_DISABLE_MASK 0x00000100L +#define DCCG_GATE_DISABLE_CNTL__SYMCLKA_GATE_DISABLE__SHIFT 0x00000008 +#define DCCG_GATE_DISABLE_CNTL__SYMCLKB_GATE_DISABLE_MASK 0x00000200L +#define DCCG_GATE_DISABLE_CNTL__SYMCLKB_GATE_DISABLE__SHIFT 0x00000009 +#define DCCG_GATE_DISABLE_CNTL__SYMCLKC_GATE_DISABLE_MASK 0x00000400L +#define DCCG_GATE_DISABLE_CNTL__SYMCLKC_GATE_DISABLE__SHIFT 0x0000000a +#define DCCG_GATE_DISABLE_CNTL__SYMCLKD_GATE_DISABLE_MASK 0x00000800L +#define DCCG_GATE_DISABLE_CNTL__SYMCLKD_GATE_DISABLE__SHIFT 0x0000000b +#define DCCG_GATE_DISABLE_CNTL__SYMCLKE_GATE_DISABLE_MASK 0x00001000L +#define DCCG_GATE_DISABLE_CNTL__SYMCLKE_GATE_DISABLE__SHIFT 0x0000000c +#define DCCG_GATE_DISABLE_CNTL__SYMCLKF_GATE_DISABLE_MASK 0x00002000L +#define DCCG_GATE_DISABLE_CNTL__SYMCLKF_GATE_DISABLE__SHIFT 0x0000000d +#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK 0x00000001L +#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT 0x00000000 +#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK 0xffffffffL +#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT 0x00000000 +#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK 0xffffffffL +#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT 0x00000000 +#define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL_MASK 0x00000700L +#define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL__SHIFT 0x00000008 +#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE_MASK 0x00000001L +#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE__SHIFT 0x00000000 +#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE_MASK 0x00000002L +#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE__SHIFT 0x00000001 +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC_MASK 0x00000080L +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC__SHIFT 0x00000007 +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC_MASK 0x00000040L +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC__SHIFT 0x00000006 +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK 0x00000010L +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE__SHIFT 0x00000004 +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE_MASK 0x00000004L +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE__SHIFT 0x00000002 +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK2_ENABLE_MASK 0x00000008L +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK2_ENABLE__SHIFT 0x00000003 +#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN_MASK 0x00000020L +#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN__SHIFT 0x00000005 +#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK 0x00000001L +#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT 0x00000000 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV_MASK 0x00010000L +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV__SHIFT 0x00000010 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL_MASK 0x000000ffL +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL__SHIFT 0x00000000 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV_MASK 0x01000000L +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV__SHIFT 0x00000018 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL_MASK 0x0000ff00L +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL__SHIFT 0x00000008 +#define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA_MASK 0xffffffffL +#define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define DCCG_TEST_DEBUG_INDEX__DCCG_DBG_SEL_MASK 0x00001000L +#define DCCG_TEST_DEBUG_INDEX__DCCG_DBG_SEL__SHIFT 0x0000000c +#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define DCCG_VPCLK_CNTL__AZ_LIGHT_SLEEP_DIS_MASK 0x00000004L +#define DCCG_VPCLK_CNTL__AZ_LIGHT_SLEEP_DIS__SHIFT 0x00000002 +#define DCCG_VPCLK_CNTL__AZ_MEM_SHUTDOWN_DIS_MASK 0x04000000L +#define DCCG_VPCLK_CNTL__AZ_MEM_SHUTDOWN_DIS__SHIFT 0x0000001a +#define DCCG_VPCLK_CNTL__DCCG_VPCLK_POL_MASK 0x00000001L +#define DCCG_VPCLK_CNTL__DCCG_VPCLK_POL__SHIFT 0x00000000 +#define DCCG_VPCLK_CNTL__DMCU_LIGHT_SLEEP_DIS_MASK 0x00000008L +#define DCCG_VPCLK_CNTL__DMCU_LIGHT_SLEEP_DIS__SHIFT 0x00000003 +#define DCCG_VPCLK_CNTL__DMCU_MEM_SHUTDOWN_DIS_MASK 0x00010000L +#define DCCG_VPCLK_CNTL__DMCU_MEM_SHUTDOWN_DIS__SHIFT 0x00000010 +#define DCCG_VPCLK_CNTL__DMIF0_LIGHT_SLEEP_DIS_MASK 0x00000100L +#define DCCG_VPCLK_CNTL__DMIF0_LIGHT_SLEEP_DIS__SHIFT 0x00000008 +#define DCCG_VPCLK_CNTL__DMIF0_MEM_SHUTDOWN_DIS_MASK 0x00100000L +#define DCCG_VPCLK_CNTL__DMIF0_MEM_SHUTDOWN_DIS__SHIFT 0x00000014 +#define DCCG_VPCLK_CNTL__DMIF1_LIGHT_SLEEP_DIS_MASK 0x00000200L +#define DCCG_VPCLK_CNTL__DMIF1_LIGHT_SLEEP_DIS__SHIFT 0x00000009 +#define DCCG_VPCLK_CNTL__DMIF1_MEM_SHUTDOWN_DIS_MASK 0x00200000L +#define DCCG_VPCLK_CNTL__DMIF1_MEM_SHUTDOWN_DIS__SHIFT 0x00000015 +#define DCCG_VPCLK_CNTL__DMIF2_LIGHT_SLEEP_DIS_MASK 0x00000400L +#define DCCG_VPCLK_CNTL__DMIF2_LIGHT_SLEEP_DIS__SHIFT 0x0000000a +#define DCCG_VPCLK_CNTL__DMIF2_MEM_SHUTDOWN_DIS_MASK 0x00400000L +#define DCCG_VPCLK_CNTL__DMIF2_MEM_SHUTDOWN_DIS__SHIFT 0x00000016 +#define DCCG_VPCLK_CNTL__DMIF3_LIGHT_SLEEP_DIS_MASK 0x00000800L +#define DCCG_VPCLK_CNTL__DMIF3_LIGHT_SLEEP_DIS__SHIFT 0x0000000b +#define DCCG_VPCLK_CNTL__DMIF3_MEM_SHUTDOWN_DIS_MASK 0x00800000L +#define DCCG_VPCLK_CNTL__DMIF3_MEM_SHUTDOWN_DIS__SHIFT 0x00000017 +#define DCCG_VPCLK_CNTL__DMIF4_LIGHT_SLEEP_DIS_MASK 0x00001000L +#define DCCG_VPCLK_CNTL__DMIF4_LIGHT_SLEEP_DIS__SHIFT 0x0000000c +#define DCCG_VPCLK_CNTL__DMIF4_MEM_SHUTDOWN_DIS_MASK 0x01000000L +#define DCCG_VPCLK_CNTL__DMIF4_MEM_SHUTDOWN_DIS__SHIFT 0x00000018 +#define DCCG_VPCLK_CNTL__DMIF5_LIGHT_SLEEP_DIS_MASK 0x00002000L +#define DCCG_VPCLK_CNTL__DMIF5_LIGHT_SLEEP_DIS__SHIFT 0x0000000d +#define DCCG_VPCLK_CNTL__DMIF5_MEM_SHUTDOWN_DIS_MASK 0x02000000L +#define DCCG_VPCLK_CNTL__DMIF5_MEM_SHUTDOWN_DIS__SHIFT 0x00000019 +#define DCCG_VPCLK_CNTL__DMIF_XLR_LIGHT_SLEEP_MODE_FORCE_MASK 0x00000020L +#define DCCG_VPCLK_CNTL__DMIF_XLR_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x00000005 +#define DCCG_VPCLK_CNTL__DMIF_XLR_MEM_SHUTDOWN_MODE_FORCE_MASK 0x00040000L +#define DCCG_VPCLK_CNTL__DMIF_XLR_MEM_SHUTDOWN_MODE_FORCE__SHIFT 0x00000012 +#define DCCG_VPCLK_CNTL__FBC_LIGHT_SLEEP_DIS_MASK 0x00004000L +#define DCCG_VPCLK_CNTL__FBC_LIGHT_SLEEP_DIS__SHIFT 0x0000000e +#define DCCG_VPCLK_CNTL__FBC_MEM_SHUTDOWN_DIS_MASK 0x00080000L +#define DCCG_VPCLK_CNTL__FBC_MEM_SHUTDOWN_DIS__SHIFT 0x00000013 +#define DCCG_VPCLK_CNTL__MCIF_LIGHT_SLEEP_MODE_FORCE_MASK 0x00000010L +#define DCCG_VPCLK_CNTL__MCIF_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x00000004 +#define DCCG_VPCLK_CNTL__MCIF_MEM_SHUTDOWN_MODE_FORCE_MASK 0x00020000L +#define DCCG_VPCLK_CNTL__MCIF_MEM_SHUTDOWN_MODE_FORCE__SHIFT 0x00000011 +#define DCCG_VPCLK_CNTL__VGA_LIGHT_SLEEP_MODE_FORCE_MASK 0x00000002L +#define DCCG_VPCLK_CNTL__VGA_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x00000001 +#define DCCG_VPCLK_CNTL__VIP_LIGHT_SLEEP_DIS_MASK 0x00008000L +#define DCCG_VPCLK_CNTL__VIP_LIGHT_SLEEP_DIS__SHIFT 0x0000000f +#define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL_MASK 0xffffffffL +#define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL__SHIFT 0x00000000 +#define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL_MASK 0xffffffffL +#define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL__SHIFT 0x00000000 +#define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL_MASK 0xffffffffL +#define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL__SHIFT 0x00000000 +#define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL_MASK 0xffffffffL +#define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL__SHIFT 0x00000000 +#define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL_MASK 0x0000001fL +#define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL__SHIFT 0x00000000 +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_EN_MASK 0x00000020L +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_EN__SHIFT 0x00000005 +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_PIN_SEL_MASK 0x00000040L +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_PIN_SEL__SHIFT 0x00000006 +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_SEL_MASK 0x00300000L +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_SEL__SHIFT 0x00000014 +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA_EN_MASK 0x00000080L +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA_EN__SHIFT 0x00000007 +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA_MASK 0x000fff00L +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA__SHIFT 0x00000008 +#define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA_MASK 0xffffffffL +#define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA__SHIFT 0x00000000 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN_MASK 0x00001000L +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN__SHIFT 0x0000000c +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL_MASK 0x0000000fL +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL__SHIFT 0x00000000 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL_MASK 0x000001f0L +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL__SHIFT 0x00000004 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN_MASK 0x10000000L +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN__SHIFT 0x0000001c +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL_MASK 0x000f0000L +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL__SHIFT 0x00000010 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL_MASK 0x01f00000L +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL__SHIFT 0x00000014 +#define DC_DMCU_SCRATCH__DMCU_SCRATCH_MASK 0xffffffffL +#define DC_DMCU_SCRATCH__DMCU_SCRATCH__SHIFT 0x00000000 +#define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN_MASK 0x00200000L +#define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN__SHIFT 0x00000015 +#define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN_MASK 0x00100000L +#define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN__SHIFT 0x00000014 +#define DC_DVODATA_CONFIG__VIP_MUX_EN_MASK 0x00080000L +#define DC_DVODATA_CONFIG__VIP_MUX_EN__SHIFT 0x00000013 +#define DCFE0_SOFT_RESET__CRTC0_SOFT_RESET_MASK 0x00000010L +#define DCFE0_SOFT_RESET__CRTC0_SOFT_RESET__SHIFT 0x00000004 +#define DCFE0_SOFT_RESET__DCP0_PIXPIPE_SOFT_RESET_MASK 0x00000001L +#define DCFE0_SOFT_RESET__DCP0_PIXPIPE_SOFT_RESET__SHIFT 0x00000000 +#define DCFE0_SOFT_RESET__DCP0_REQ_SOFT_RESET_MASK 0x00000002L +#define DCFE0_SOFT_RESET__DCP0_REQ_SOFT_RESET__SHIFT 0x00000001 +#define DCFE0_SOFT_RESET__SCL0_ALU_SOFT_RESET_MASK 0x00000004L +#define DCFE0_SOFT_RESET__SCL0_ALU_SOFT_RESET__SHIFT 0x00000002 +#define DCFE0_SOFT_RESET__SCL0_SOFT_RESET_MASK 0x00000008L +#define DCFE0_SOFT_RESET__SCL0_SOFT_RESET__SHIFT 0x00000003 +#define DCFE1_SOFT_RESET__CRTC1_SOFT_RESET_MASK 0x00000010L +#define DCFE1_SOFT_RESET__CRTC1_SOFT_RESET__SHIFT 0x00000004 +#define DCFE1_SOFT_RESET__DCP1_PIXPIPE_SOFT_RESET_MASK 0x00000001L +#define DCFE1_SOFT_RESET__DCP1_PIXPIPE_SOFT_RESET__SHIFT 0x00000000 +#define DCFE1_SOFT_RESET__DCP1_REQ_SOFT_RESET_MASK 0x00000002L +#define DCFE1_SOFT_RESET__DCP1_REQ_SOFT_RESET__SHIFT 0x00000001 +#define DCFE1_SOFT_RESET__SCL1_ALU_SOFT_RESET_MASK 0x00000004L +#define DCFE1_SOFT_RESET__SCL1_ALU_SOFT_RESET__SHIFT 0x00000002 +#define DCFE1_SOFT_RESET__SCL1_SOFT_RESET_MASK 0x00000008L +#define DCFE1_SOFT_RESET__SCL1_SOFT_RESET__SHIFT 0x00000003 +#define DCFE2_SOFT_RESET__CRTC2_SOFT_RESET_MASK 0x00000010L +#define DCFE2_SOFT_RESET__CRTC2_SOFT_RESET__SHIFT 0x00000004 +#define DCFE2_SOFT_RESET__DCP2_PIXPIPE_SOFT_RESET_MASK 0x00000001L +#define DCFE2_SOFT_RESET__DCP2_PIXPIPE_SOFT_RESET__SHIFT 0x00000000 +#define DCFE2_SOFT_RESET__DCP2_REQ_SOFT_RESET_MASK 0x00000002L +#define DCFE2_SOFT_RESET__DCP2_REQ_SOFT_RESET__SHIFT 0x00000001 +#define DCFE2_SOFT_RESET__SCL2_ALU_SOFT_RESET_MASK 0x00000004L +#define DCFE2_SOFT_RESET__SCL2_ALU_SOFT_RESET__SHIFT 0x00000002 +#define DCFE2_SOFT_RESET__SCL2_SOFT_RESET_MASK 0x00000008L +#define DCFE2_SOFT_RESET__SCL2_SOFT_RESET__SHIFT 0x00000003 +#define DCFE3_SOFT_RESET__CRTC3_SOFT_RESET_MASK 0x00000010L +#define DCFE3_SOFT_RESET__CRTC3_SOFT_RESET__SHIFT 0x00000004 +#define DCFE3_SOFT_RESET__DCP3_PIXPIPE_SOFT_RESET_MASK 0x00000001L +#define DCFE3_SOFT_RESET__DCP3_PIXPIPE_SOFT_RESET__SHIFT 0x00000000 +#define DCFE3_SOFT_RESET__DCP3_REQ_SOFT_RESET_MASK 0x00000002L +#define DCFE3_SOFT_RESET__DCP3_REQ_SOFT_RESET__SHIFT 0x00000001 +#define DCFE3_SOFT_RESET__SCL3_ALU_SOFT_RESET_MASK 0x00000004L +#define DCFE3_SOFT_RESET__SCL3_ALU_SOFT_RESET__SHIFT 0x00000002 +#define DCFE3_SOFT_RESET__SCL3_SOFT_RESET_MASK 0x00000008L +#define DCFE3_SOFT_RESET__SCL3_SOFT_RESET__SHIFT 0x00000003 +#define DCFE4_SOFT_RESET__CRTC4_SOFT_RESET_MASK 0x00000010L +#define DCFE4_SOFT_RESET__CRTC4_SOFT_RESET__SHIFT 0x00000004 +#define DCFE4_SOFT_RESET__DCP4_PIXPIPE_SOFT_RESET_MASK 0x00000001L +#define DCFE4_SOFT_RESET__DCP4_PIXPIPE_SOFT_RESET__SHIFT 0x00000000 +#define DCFE4_SOFT_RESET__DCP4_REQ_SOFT_RESET_MASK 0x00000002L +#define DCFE4_SOFT_RESET__DCP4_REQ_SOFT_RESET__SHIFT 0x00000001 +#define DCFE4_SOFT_RESET__SCL4_ALU_SOFT_RESET_MASK 0x00000004L +#define DCFE4_SOFT_RESET__SCL4_ALU_SOFT_RESET__SHIFT 0x00000002 +#define DCFE4_SOFT_RESET__SCL4_SOFT_RESET_MASK 0x00000008L +#define DCFE4_SOFT_RESET__SCL4_SOFT_RESET__SHIFT 0x00000003 +#define DCFE5_SOFT_RESET__CRTC5_SOFT_RESET_MASK 0x00000010L +#define DCFE5_SOFT_RESET__CRTC5_SOFT_RESET__SHIFT 0x00000004 +#define DCFE5_SOFT_RESET__DCP5_PIXPIPE_SOFT_RESET_MASK 0x00000001L +#define DCFE5_SOFT_RESET__DCP5_PIXPIPE_SOFT_RESET__SHIFT 0x00000000 +#define DCFE5_SOFT_RESET__DCP5_REQ_SOFT_RESET_MASK 0x00000002L +#define DCFE5_SOFT_RESET__DCP5_REQ_SOFT_RESET__SHIFT 0x00000001 +#define DCFE5_SOFT_RESET__SCL5_ALU_SOFT_RESET_MASK 0x00000004L +#define DCFE5_SOFT_RESET__SCL5_ALU_SOFT_RESET__SHIFT 0x00000002 +#define DCFE5_SOFT_RESET__SCL5_SOFT_RESET_MASK 0x00000008L +#define DCFE5_SOFT_RESET__SCL5_SOFT_RESET__SHIFT 0x00000003 +#define DCFE_DBG_SEL__DCFE_DBG_SEL_MASK 0x0000000fL +#define DCFE_DBG_SEL__DCFE_DBG_SEL__SHIFT 0x00000000 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_LIGHT_SLEEP_DIS__SHIFT 0x00000000 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_MEM_PWR_STATE_MASK 0x00000300L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_MEM_PWR_STATE__SHIFT 0x00000008 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_LIGHT_SLEEP_DIS_MASK 0x00000004L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_LIGHT_SLEEP_DIS__SHIFT 0x00000002 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_MEM_PWR_STATE_MASK 0x00003000L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_MEM_PWR_STATE__SHIFT 0x0000000c +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB1_MEM_SHUTDOWN_DIS_MASK 0x20000000L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB1_MEM_SHUTDOWN_DIS__SHIFT 0x0000001d +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB2_MEM_SHUTDOWN_DIS_MASK 0x40000000L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB2_MEM_SHUTDOWN_DIS__SHIFT 0x0000001e +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_LIGHT_SLEEP_DIS_MASK 0x00000010L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_LIGHT_SLEEP_DIS__SHIFT 0x00000004 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_0_MASK 0x00030000L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_0__SHIFT 0x00000010 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_1_MASK 0x00c00000L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_1__SHIFT 0x00000016 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_2_MASK 0x03000000L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_2__SHIFT 0x00000018 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_LIGHT_SLEEP_DIS_MASK 0x00000008L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_LIGHT_SLEEP_DIS__SHIFT 0x00000003 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_MEM_PWR_STATE_MASK 0x0000c000L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_MEM_PWR_STATE__SHIFT 0x0000000e +#define DCFE_MEM_LIGHT_SLEEP_CNTL__PIPE_MEM_SHUTDOWN_DIS_MASK 0x10000000L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__PIPE_MEM_SHUTDOWN_DIS__SHIFT 0x0000001c +#define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_LIGHT_SLEEP_DIS_MASK 0x00000040L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_LIGHT_SLEEP_DIS__SHIFT 0x00000006 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_MEM_PWR_STATE_MASK 0x00300000L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_MEM_PWR_STATE__SHIFT 0x00000014 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_LIGHT_SLEEP_DIS_MASK 0x00000020L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_LIGHT_SLEEP_DIS__SHIFT 0x00000005 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_MEM_PWR_STATE_MASK 0x000c0000L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_MEM_PWR_STATE__SHIFT 0x00000012 +#define DC_GENERICA__GENERICA_EN_MASK 0x00000001L +#define DC_GENERICA__GENERICA_EN__SHIFT 0x00000000 +#define DC_GENERICA__GENERICA_SEL_MASK 0x00000f00L +#define DC_GENERICA__GENERICA_SEL__SHIFT 0x00000008 +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x07000000L +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x00000018 +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK 0x00070000L +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x00000010 +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x00700000L +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x00000014 +#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK 0x00007000L +#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT 0x0000000c +#define DC_GENERICB__GENERICB_EN_MASK 0x00000001L +#define DC_GENERICB__GENERICB_EN__SHIFT 0x00000000 +#define DC_GENERICB__GENERICB_SEL_MASK 0x00000f00L +#define DC_GENERICB__GENERICB_SEL__SHIFT 0x00000008 +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x07000000L +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x00000018 +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK 0x00070000L +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x00000010 +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x00700000L +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x00000014 +#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK 0x00007000L +#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT 0x0000000c +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT 0x00000000 +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK 0x00000100L +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT 0x00000008 +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT 0x00000000 +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK 0x00000100L +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT 0x00000008 +#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT 0x00000016 +#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK 0x00100000L +#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT 0x00000014 +#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK 0x00010000L +#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT 0x00000010 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT 0x00000000 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT 0x00000004 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT 0x00000006 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK 0x0f000000L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT 0x00000018 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT 0x00000008 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT 0x0000000c +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT 0x0000000e +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK 0xf0000000L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT 0x0000001c +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT 0x00000000 +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK 0x00000100L +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT 0x00000008 +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT 0x00000000 +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK 0x00000100L +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT 0x00000008 +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT 0x00000000 +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK 0x00000100L +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT 0x00000008 +#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT 0x00000016 +#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK 0x00100000L +#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT 0x00000014 +#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK 0x00010000L +#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT 0x00000010 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT 0x00000000 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT 0x00000004 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT 0x00000006 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK 0x0f000000L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT 0x00000018 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT 0x00000008 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT 0x0000000c +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT 0x0000000e +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK 0xf0000000L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT 0x0000001c +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT 0x00000000 +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK 0x00000100L +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT 0x00000008 +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT 0x00000000 +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK 0x00000100L +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT 0x00000008 +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT 0x00000000 +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK 0x00000100L +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT 0x00000008 +#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT 0x00000016 +#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK 0x00100000L +#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT 0x00000014 +#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK 0x00010000L +#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT 0x00000010 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT 0x00000000 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT 0x00000004 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT 0x00000006 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK 0x0f000000L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT 0x00000018 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT 0x00000008 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT 0x0000000c +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT 0x0000000e +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK 0xf0000000L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT 0x0000001c +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT 0x00000000 +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK 0x00000100L +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT 0x00000008 +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT 0x00000000 +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK 0x00000100L +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT 0x00000008 +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT 0x00000000 +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK 0x00000100L +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT 0x00000008 +#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT 0x00000016 +#define DC_GPIO_DDC4_MASK__AUX4_POL_MASK 0x00100000L +#define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT 0x00000014 +#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK 0x00010000L +#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT 0x00000010 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT 0x00000000 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT 0x00000004 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT 0x00000006 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK 0x0f000000L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT 0x00000018 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT 0x00000008 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT 0x0000000c +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT 0x0000000e +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK 0xf0000000L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT 0x0000001c +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT 0x00000000 +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK 0x00000100L +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT 0x00000008 +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT 0x00000000 +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK 0x00000100L +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT 0x00000008 +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT 0x00000000 +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK 0x00000100L +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT 0x00000008 +#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT 0x00000016 +#define DC_GPIO_DDC5_MASK__AUX5_POL_MASK 0x00100000L +#define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT 0x00000014 +#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK 0x00010000L +#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 0x00000010 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT 0x00000000 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT 0x00000004 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT 0x00000006 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK 0x0f000000L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT 0x00000018 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT 0x00000008 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT 0x0000000c +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT 0x0000000e +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK 0xf0000000L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT 0x0000001c +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT 0x00000000 +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK 0x00000100L +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT 0x00000008 +#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A__SHIFT 0x00000000 +#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK 0x00000100L +#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A__SHIFT 0x00000008 +#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN__SHIFT 0x00000000 +#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN_MASK 0x00000100L +#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN__SHIFT 0x00000008 +#define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN__SHIFT 0x00000016 +#define DC_GPIO_DDC6_MASK__AUX6_POL_MASK 0x00100000L +#define DC_GPIO_DDC6_MASK__AUX6_POL__SHIFT 0x00000014 +#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE_MASK 0x00010000L +#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE__SHIFT 0x00000010 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK__SHIFT 0x00000000 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN__SHIFT 0x00000004 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV__SHIFT 0x00000006 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR_MASK 0x0f000000L +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR__SHIFT 0x00000018 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK__SHIFT 0x00000008 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN__SHIFT 0x0000000c +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV__SHIFT 0x0000000e +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR_MASK 0xf0000000L +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR__SHIFT 0x0000001c +#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y__SHIFT 0x00000000 +#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y_MASK 0x00000100L +#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y__SHIFT 0x00000008 +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK 0x00000001L +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT 0x00000000 +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK 0x00000100L +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT 0x00000008 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK 0x00000001L +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT 0x00000000 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK 0x00000100L +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT 0x00000008 +#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT 0x00000016 +#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK 0x00010000L +#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT 0x00000010 +#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK 0x00100000L +#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT 0x00000014 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT 0x00000000 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT 0x00000006 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK 0x0f000000L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT 0x00000018 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT 0x00000008 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT 0x0000000c +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT 0x0000000e +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK 0xf0000000L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT 0x0000001c +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK 0x00000001L +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT 0x00000000 +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK 0x00000100L +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT 0x00000008 +#define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_MASK 0x00010000L +#define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL__SHIFT 0x00000010 +#define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG_MASK 0x00000300L +#define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG__SHIFT 0x00000008 +#define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG_MASK 0x00000001L +#define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG__SHIFT 0x00000000 +#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A_MASK 0x10000000L +#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A__SHIFT 0x0000001c +#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A_MASK 0x07000000L +#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A__SHIFT 0x00000018 +#define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A_MASK 0x00ffffffL +#define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A__SHIFT 0x00000000 +#define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A_MASK 0xc0000000L +#define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A__SHIFT 0x0000001e +#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN_MASK 0x10000000L +#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN__SHIFT 0x0000001c +#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN_MASK 0x07000000L +#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN__SHIFT 0x00000018 +#define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN_MASK 0x00ffffffL +#define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN__SHIFT 0x00000000 +#define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN_MASK 0xc0000000L +#define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN__SHIFT 0x0000001e +#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK_MASK 0x10000000L +#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK__SHIFT 0x0000001c +#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK_MASK 0x07000000L +#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK__SHIFT 0x00000018 +#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK_MASK 0x00ffffffL +#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK__SHIFT 0x00000000 +#define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK_MASK 0xc0000000L +#define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK__SHIFT 0x0000001e +#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y_MASK 0x10000000L +#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y__SHIFT 0x0000001c +#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y_MASK 0x07000000L +#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y__SHIFT 0x00000018 +#define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y_MASK 0x00ffffffL +#define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y__SHIFT 0x00000000 +#define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y_MASK 0xc0000000L +#define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y__SHIFT 0x0000001e +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK 0x00000001L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT 0x00000000 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK 0x00000100L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT 0x00000008 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK 0x00010000L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT 0x00000010 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK 0x00100000L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT 0x00000014 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK 0x00200000L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT 0x00000015 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK 0x00400000L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT 0x00000016 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK 0x00800000L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT 0x00000017 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK 0x00000001L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT 0x00000000 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK 0x00000100L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT 0x00000008 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK 0x00010000L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT 0x00000010 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK 0x00100000L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT 0x00000014 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK 0x00200000L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT 0x00000015 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK 0x00400000L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT 0x00000016 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK 0x00800000L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT 0x00000017 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK 0x00000001L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT 0x00000000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK 0x00000002L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT 0x00000001 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK 0x00000004L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT 0x00000002 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK 0x00000010L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT 0x00000004 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK 0x00000020L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT 0x00000005 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK 0x00000040L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT 0x00000006 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK 0x00000100L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT 0x00000008 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK 0x00000200L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT 0x00000009 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK 0x00000400L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT 0x0000000a +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK 0x00001000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT 0x0000000c +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK 0x00002000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT 0x0000000d +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK 0x00004000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT 0x0000000e +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK 0x00010000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT 0x00000010 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK 0x00020000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT 0x00000011 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK 0x00040000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT 0x00000012 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK 0x00100000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT 0x00000014 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK 0x00200000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT 0x00000015 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK 0x00400000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT 0x00000016 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK 0x01000000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT 0x00000018 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK 0x02000000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT 0x00000019 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK 0x04000000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT 0x0000001a +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK 0x00000001L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT 0x00000000 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK 0x00000100L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT 0x00000008 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK 0x00010000L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT 0x00000010 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK 0x00100000L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT 0x00000014 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK 0x00200000L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT 0x00000015 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK 0x00400000L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT 0x00000016 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK 0x00800000L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT 0x00000017 +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK 0x00000001L +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT 0x00000000 +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK 0x00000100L +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT 0x00000008 +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK 0x00010000L +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT 0x00000010 +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK 0x01000000L +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT 0x00000018 +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK 0x00000001L +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT 0x00000000 +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK 0x00000100L +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT 0x00000008 +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK 0x00010000L +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT 0x00000010 +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK 0x01000000L +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT 0x00000018 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK 0x00000001L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT 0x00000000 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK 0x00000002L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT 0x00000001 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK 0x00000008L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT 0x00000003 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK 0x00000004L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT 0x00000002 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK 0x00000100L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT 0x00000008 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK 0x00000200L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT 0x00000009 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK 0x00000800L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT 0x0000000b +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK 0x00000400L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT 0x0000000a +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK 0x00010000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT 0x00000010 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK 0x00020000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT 0x00000011 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK 0x00080000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT 0x00000013 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK 0x00040000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT 0x00000012 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK 0x01000000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT 0x00000018 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK 0x02000000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT 0x00000019 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK 0x08000000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT 0x0000001b +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK 0x04000000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT 0x0000001a +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK 0x00000001L +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT 0x00000000 +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK 0x00000100L +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT 0x00000008 +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK 0x00010000L +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT 0x00000010 +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK 0x01000000L +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT 0x00000018 +#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK 0x00000001L +#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT 0x00000000 +#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK 0x00000100L +#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT 0x00000008 +#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK 0x00010000L +#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT 0x00000010 +#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK 0x01000000L +#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT 0x00000018 +#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK 0x04000000L +#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT 0x0000001a +#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK 0x10000000L +#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT 0x0000001c +#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK 0x00000001L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT 0x00000000 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK 0x00000100L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT 0x00000008 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK 0x00010000L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT 0x00000010 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK 0x01000000L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT 0x00000018 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK 0x04000000L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT 0x0000001a +#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK 0x10000000L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT 0x0000001c +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK 0x00000001L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT 0x00000000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK 0x00000010L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT 0x00000004 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK 0x00000040L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT 0x00000006 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK 0x00000100L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT 0x00000008 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK 0x00000200L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT 0x00000009 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK 0x00000400L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT 0x0000000a +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK 0x00010000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT 0x00000010 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK 0x00020000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT 0x00000011 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK 0x00040000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT 0x00000012 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK 0x00100000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT 0x00000014 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK 0x00200000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT 0x00000015 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK 0x00400000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT 0x00000016 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK 0x01000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT 0x00000018 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK 0x02000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT 0x00000019 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK 0x04000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT 0x0000001a +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK 0x10000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT 0x0000001c +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK 0x20000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT 0x0000001d +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK 0x40000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT 0x0000001e +#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK 0x00000001L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT 0x00000000 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK 0x00000100L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT 0x00000008 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK 0x00010000L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT 0x00000010 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK 0x01000000L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT 0x00000018 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK 0x04000000L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT 0x0000001a +#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK 0x10000000L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT 0x0000001c +#define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A_MASK 0x00000001L +#define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A__SHIFT 0x00000000 +#define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A_MASK 0x00000002L +#define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A__SHIFT 0x00000001 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN_MASK 0x00000001L +#define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN__SHIFT 0x00000000 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN_MASK 0x00000002L +#define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN__SHIFT 0x00000001 +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_MASK_MASK 0x00000001L +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_MASK__SHIFT 0x00000000 +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_PD_DIS_MASK 0x00000002L +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_PD_DIS__SHIFT 0x00000001 +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_RECV_MASK 0x00000004L +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_RECV__SHIFT 0x00000002 +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_MASK_MASK 0x00000010L +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_MASK__SHIFT 0x00000004 +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_PD_DIS_MASK 0x00000020L +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_PD_DIS__SHIFT 0x00000005 +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_RECV_MASK 0x00000040L +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_RECV__SHIFT 0x00000006 +#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN_MASK 0x0000000fL +#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN__SHIFT 0x00000000 +#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP_MASK 0x000000f0L +#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP__SHIFT 0x00000004 +#define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y_MASK 0x00000001L +#define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y__SHIFT 0x00000000 +#define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y_MASK 0x00000002L +#define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y__SHIFT 0x00000001 +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK 0x0000000fL +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT 0x00000000 +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK 0x000000f0L +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT 0x00000004 +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK 0x0f000000L +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT 0x00000018 +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK 0xf0000000L +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT 0x0000001c +#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN_MASK 0x000f0000L +#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN__SHIFT 0x00000010 +#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP_MASK 0x00f00000L +#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP__SHIFT 0x00000014 +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK 0x0000000fL +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT 0x00000000 +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK 0x000000f0L +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT 0x00000004 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A_MASK 0x00000001L +#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A__SHIFT 0x00000000 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A_MASK 0x00000100L +#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A__SHIFT 0x00000008 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A_MASK 0x00010000L +#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A__SHIFT 0x00000010 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK 0x00000001L +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT 0x00000000 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK 0x00000100L +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT 0x00000008 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN_MASK 0x00010000L +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN__SHIFT 0x00000010 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x00000002L +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT 0x00000001 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK 0x00000001L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT 0x00000000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK 0x00000010L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT 0x00000004 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK 0x00000040L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT 0x00000006 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK 0x00000100L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT 0x00000008 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK 0x00001000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT 0x0000000c +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK 0x00004000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT 0x0000000e +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK_MASK 0x00010000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK__SHIFT 0x00000010 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS_MASK 0x00100000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS__SHIFT 0x00000014 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV_MASK 0x00400000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV__SHIFT 0x00000016 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y_MASK 0x00000001L +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y__SHIFT 0x00000000 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y_MASK 0x00000100L +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y__SHIFT 0x00000008 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y_MASK 0x00010000L +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y__SHIFT 0x00000010 +#define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK 0x00000001L +#define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A__SHIFT 0x00000000 +#define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK 0x00000100L +#define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A__SHIFT 0x00000008 +#define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN_MASK 0x00000001L +#define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN__SHIFT 0x00000000 +#define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN_MASK 0x00000100L +#define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN__SHIFT 0x00000008 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK_MASK 0x07000000L +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK__SHIFT 0x00000018 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK_MASK 0x00000001L +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK__SHIFT 0x00000000 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS_MASK 0x00000010L +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS__SHIFT 0x00000004 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV_MASK 0x00000040L +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV__SHIFT 0x00000006 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK_MASK 0x70000000L +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK__SHIFT 0x0000001c +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK_MASK 0x00000100L +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK__SHIFT 0x00000008 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS_MASK 0x00001000L +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS__SHIFT 0x0000000c +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV_MASK 0x00004000L +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV__SHIFT 0x0000000e +#define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y_MASK 0x00000001L +#define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y__SHIFT 0x00000000 +#define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y_MASK 0x00000100L +#define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y__SHIFT 0x00000008 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK 0x0000003fL +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT 0x00000000 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK 0x00000700L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT 0x00000008 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK 0x00003800L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT 0x0000000b +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK 0x0001c000L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT 0x0000000e +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK 0x000e0000L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT 0x00000011 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK 0x00700000L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT 0x00000014 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK 0x03800000L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT 0x00000017 +#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK 0xffffffffL +#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT 0x00000000 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP__SHIFT 0x00000000 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP__SHIFT 0x00000004 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP__SHIFT 0x00000008 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP__SHIFT 0x0000000c +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP__SHIFT 0x00000010 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP_MASK 0x00700000L +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP__SHIFT 0x00000014 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT 0x00000000 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT 0x00000004 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT 0x00000008 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT 0x0000000c +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT 0x00000010 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK 0x00700000L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT 0x00000014 +#define DC_HPD1_CONTROL__DC_HPD1_CONNECTION_TIMER_MASK 0x00001fffL +#define DC_HPD1_CONTROL__DC_HPD1_CONNECTION_TIMER__SHIFT 0x00000000 +#define DC_HPD1_CONTROL__DC_HPD1_EN_MASK 0x10000000L +#define DC_HPD1_CONTROL__DC_HPD1_EN__SHIFT 0x0000001c +#define DC_HPD1_CONTROL__DC_HPD1_RX_INT_TIMER_MASK 0x03ff0000L +#define DC_HPD1_CONTROL__DC_HPD1_RX_INT_TIMER__SHIFT 0x00000010 +#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_DELAY_MASK 0x000000ffL +#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_DELAY__SHIFT 0x00000000 +#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_EN__SHIFT 0x00000018 +#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_DELAY_MASK 0x000ff000L +#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_DELAY__SHIFT 0x0000000c +#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_EN__SHIFT 0x0000001c +#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK 0x00000001L +#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK__SHIFT 0x00000000 +#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK 0x00010000L +#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN__SHIFT 0x00000010 +#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK 0x00000100L +#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY__SHIFT 0x00000008 +#define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK 0x00100000L +#define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK__SHIFT 0x00000014 +#define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK 0x01000000L +#define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN__SHIFT 0x00000018 +#define DC_HPD1_INT_STATUS__DC_HPD1_INT_STATUS_MASK 0x00000001L +#define DC_HPD1_INT_STATUS__DC_HPD1_INT_STATUS__SHIFT 0x00000000 +#define DC_HPD1_INT_STATUS__DC_HPD1_RX_INT_STATUS_MASK 0x00000100L +#define DC_HPD1_INT_STATUS__DC_HPD1_RX_INT_STATUS__SHIFT 0x00000008 +#define DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED_MASK 0x00000010L +#define DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED__SHIFT 0x00000004 +#define DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK 0x00000002L +#define DC_HPD1_INT_STATUS__DC_HPD1_SENSE__SHIFT 0x00000001 +#define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000ff000L +#define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0x0000000c +#define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000L +#define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x00000018 +#define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_CONNECT_INT_DELAY_MASK 0x000000ffL +#define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_CONNECT_INT_DELAY__SHIFT 0x00000000 +#define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_DISCONNECT_INT_DELAY_MASK 0x0ff00000L +#define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_DISCONNECT_INT_DELAY__SHIFT 0x00000014 +#define DC_HPD2_CONTROL__DC_HPD2_CONNECTION_TIMER_MASK 0x00001fffL +#define DC_HPD2_CONTROL__DC_HPD2_CONNECTION_TIMER__SHIFT 0x00000000 +#define DC_HPD2_CONTROL__DC_HPD2_EN_MASK 0x10000000L +#define DC_HPD2_CONTROL__DC_HPD2_EN__SHIFT 0x0000001c +#define DC_HPD2_CONTROL__DC_HPD2_RX_INT_TIMER_MASK 0x03ff0000L +#define DC_HPD2_CONTROL__DC_HPD2_RX_INT_TIMER__SHIFT 0x00000010 +#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_DELAY_MASK 0x000000ffL +#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_DELAY__SHIFT 0x00000000 +#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_EN__SHIFT 0x00000018 +#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_DELAY_MASK 0x000ff000L +#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_DELAY__SHIFT 0x0000000c +#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_EN__SHIFT 0x0000001c +#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_ACK_MASK 0x00000001L +#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_ACK__SHIFT 0x00000000 +#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_EN_MASK 0x00010000L +#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_EN__SHIFT 0x00000010 +#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK 0x00000100L +#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY__SHIFT 0x00000008 +#define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_ACK_MASK 0x00100000L +#define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_ACK__SHIFT 0x00000014 +#define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_EN_MASK 0x01000000L +#define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_EN__SHIFT 0x00000018 +#define DC_HPD2_INT_STATUS__DC_HPD2_INT_STATUS_MASK 0x00000001L +#define DC_HPD2_INT_STATUS__DC_HPD2_INT_STATUS__SHIFT 0x00000000 +#define DC_HPD2_INT_STATUS__DC_HPD2_RX_INT_STATUS_MASK 0x00000100L +#define DC_HPD2_INT_STATUS__DC_HPD2_RX_INT_STATUS__SHIFT 0x00000008 +#define DC_HPD2_INT_STATUS__DC_HPD2_SENSE_DELAYED_MASK 0x00000010L +#define DC_HPD2_INT_STATUS__DC_HPD2_SENSE_DELAYED__SHIFT 0x00000004 +#define DC_HPD2_INT_STATUS__DC_HPD2_SENSE_MASK 0x00000002L +#define DC_HPD2_INT_STATUS__DC_HPD2_SENSE__SHIFT 0x00000001 +#define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000ff000L +#define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0x0000000c +#define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000L +#define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x00000018 +#define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_CONNECT_INT_DELAY_MASK 0x000000ffL +#define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_CONNECT_INT_DELAY__SHIFT 0x00000000 +#define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_DISCONNECT_INT_DELAY_MASK 0x0ff00000L +#define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_DISCONNECT_INT_DELAY__SHIFT 0x00000014 +#define DC_HPD3_CONTROL__DC_HPD3_CONNECTION_TIMER_MASK 0x00001fffL +#define DC_HPD3_CONTROL__DC_HPD3_CONNECTION_TIMER__SHIFT 0x00000000 +#define DC_HPD3_CONTROL__DC_HPD3_EN_MASK 0x10000000L +#define DC_HPD3_CONTROL__DC_HPD3_EN__SHIFT 0x0000001c +#define DC_HPD3_CONTROL__DC_HPD3_RX_INT_TIMER_MASK 0x03ff0000L +#define DC_HPD3_CONTROL__DC_HPD3_RX_INT_TIMER__SHIFT 0x00000010 +#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_DELAY_MASK 0x000000ffL +#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_DELAY__SHIFT 0x00000000 +#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_EN__SHIFT 0x00000018 +#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_DELAY_MASK 0x000ff000L +#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_DELAY__SHIFT 0x0000000c +#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_EN__SHIFT 0x0000001c +#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_ACK_MASK 0x00000001L +#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_ACK__SHIFT 0x00000000 +#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_EN_MASK 0x00010000L +#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_EN__SHIFT 0x00000010 +#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK 0x00000100L +#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY__SHIFT 0x00000008 +#define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_ACK_MASK 0x00100000L +#define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_ACK__SHIFT 0x00000014 +#define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_EN_MASK 0x01000000L +#define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_EN__SHIFT 0x00000018 +#define DC_HPD3_INT_STATUS__DC_HPD3_INT_STATUS_MASK 0x00000001L +#define DC_HPD3_INT_STATUS__DC_HPD3_INT_STATUS__SHIFT 0x00000000 +#define DC_HPD3_INT_STATUS__DC_HPD3_RX_INT_STATUS_MASK 0x00000100L +#define DC_HPD3_INT_STATUS__DC_HPD3_RX_INT_STATUS__SHIFT 0x00000008 +#define DC_HPD3_INT_STATUS__DC_HPD3_SENSE_DELAYED_MASK 0x00000010L +#define DC_HPD3_INT_STATUS__DC_HPD3_SENSE_DELAYED__SHIFT 0x00000004 +#define DC_HPD3_INT_STATUS__DC_HPD3_SENSE_MASK 0x00000002L +#define DC_HPD3_INT_STATUS__DC_HPD3_SENSE__SHIFT 0x00000001 +#define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000ff000L +#define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0x0000000c +#define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000L +#define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x00000018 +#define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_CONNECT_INT_DELAY_MASK 0x000000ffL +#define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_CONNECT_INT_DELAY__SHIFT 0x00000000 +#define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_DISCONNECT_INT_DELAY_MASK 0x0ff00000L +#define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_DISCONNECT_INT_DELAY__SHIFT 0x00000014 +#define DC_HPD4_CONTROL__DC_HPD4_CONNECTION_TIMER_MASK 0x00001fffL +#define DC_HPD4_CONTROL__DC_HPD4_CONNECTION_TIMER__SHIFT 0x00000000 +#define DC_HPD4_CONTROL__DC_HPD4_EN_MASK 0x10000000L +#define DC_HPD4_CONTROL__DC_HPD4_EN__SHIFT 0x0000001c +#define DC_HPD4_CONTROL__DC_HPD4_RX_INT_TIMER_MASK 0x03ff0000L +#define DC_HPD4_CONTROL__DC_HPD4_RX_INT_TIMER__SHIFT 0x00000010 +#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_DELAY_MASK 0x000000ffL +#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_DELAY__SHIFT 0x00000000 +#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_EN__SHIFT 0x00000018 +#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_DELAY_MASK 0x000ff000L +#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_DELAY__SHIFT 0x0000000c +#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_EN__SHIFT 0x0000001c +#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_ACK_MASK 0x00000001L +#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_ACK__SHIFT 0x00000000 +#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_EN_MASK 0x00010000L +#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_EN__SHIFT 0x00000010 +#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK 0x00000100L +#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY__SHIFT 0x00000008 +#define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_ACK_MASK 0x00100000L +#define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_ACK__SHIFT 0x00000014 +#define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_EN_MASK 0x01000000L +#define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_EN__SHIFT 0x00000018 +#define DC_HPD4_INT_STATUS__DC_HPD4_INT_STATUS_MASK 0x00000001L +#define DC_HPD4_INT_STATUS__DC_HPD4_INT_STATUS__SHIFT 0x00000000 +#define DC_HPD4_INT_STATUS__DC_HPD4_RX_INT_STATUS_MASK 0x00000100L +#define DC_HPD4_INT_STATUS__DC_HPD4_RX_INT_STATUS__SHIFT 0x00000008 +#define DC_HPD4_INT_STATUS__DC_HPD4_SENSE_DELAYED_MASK 0x00000010L +#define DC_HPD4_INT_STATUS__DC_HPD4_SENSE_DELAYED__SHIFT 0x00000004 +#define DC_HPD4_INT_STATUS__DC_HPD4_SENSE_MASK 0x00000002L +#define DC_HPD4_INT_STATUS__DC_HPD4_SENSE__SHIFT 0x00000001 +#define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000ff000L +#define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0x0000000c +#define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000L +#define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x00000018 +#define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_CONNECT_INT_DELAY_MASK 0x000000ffL +#define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_CONNECT_INT_DELAY__SHIFT 0x00000000 +#define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_DISCONNECT_INT_DELAY_MASK 0x0ff00000L +#define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_DISCONNECT_INT_DELAY__SHIFT 0x00000014 +#define DC_HPD5_CONTROL__DC_HPD5_CONNECTION_TIMER_MASK 0x00001fffL +#define DC_HPD5_CONTROL__DC_HPD5_CONNECTION_TIMER__SHIFT 0x00000000 +#define DC_HPD5_CONTROL__DC_HPD5_EN_MASK 0x10000000L +#define DC_HPD5_CONTROL__DC_HPD5_EN__SHIFT 0x0000001c +#define DC_HPD5_CONTROL__DC_HPD5_RX_INT_TIMER_MASK 0x03ff0000L +#define DC_HPD5_CONTROL__DC_HPD5_RX_INT_TIMER__SHIFT 0x00000010 +#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_DELAY_MASK 0x000000ffL +#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_DELAY__SHIFT 0x00000000 +#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_EN__SHIFT 0x00000018 +#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_DELAY_MASK 0x000ff000L +#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_DELAY__SHIFT 0x0000000c +#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_EN__SHIFT 0x0000001c +#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_ACK_MASK 0x00000001L +#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_ACK__SHIFT 0x00000000 +#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_EN_MASK 0x00010000L +#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_EN__SHIFT 0x00000010 +#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK 0x00000100L +#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY__SHIFT 0x00000008 +#define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_ACK_MASK 0x00100000L +#define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_ACK__SHIFT 0x00000014 +#define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_EN_MASK 0x01000000L +#define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_EN__SHIFT 0x00000018 +#define DC_HPD5_INT_STATUS__DC_HPD5_INT_STATUS_MASK 0x00000001L +#define DC_HPD5_INT_STATUS__DC_HPD5_INT_STATUS__SHIFT 0x00000000 +#define DC_HPD5_INT_STATUS__DC_HPD5_RX_INT_STATUS_MASK 0x00000100L +#define DC_HPD5_INT_STATUS__DC_HPD5_RX_INT_STATUS__SHIFT 0x00000008 +#define DC_HPD5_INT_STATUS__DC_HPD5_SENSE_DELAYED_MASK 0x00000010L +#define DC_HPD5_INT_STATUS__DC_HPD5_SENSE_DELAYED__SHIFT 0x00000004 +#define DC_HPD5_INT_STATUS__DC_HPD5_SENSE_MASK 0x00000002L +#define DC_HPD5_INT_STATUS__DC_HPD5_SENSE__SHIFT 0x00000001 +#define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000ff000L +#define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0x0000000c +#define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000L +#define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x00000018 +#define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_CONNECT_INT_DELAY_MASK 0x000000ffL +#define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_CONNECT_INT_DELAY__SHIFT 0x00000000 +#define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_DISCONNECT_INT_DELAY_MASK 0x0ff00000L +#define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_DISCONNECT_INT_DELAY__SHIFT 0x00000014 +#define DC_HPD6_CONTROL__DC_HPD6_CONNECTION_TIMER_MASK 0x00001fffL +#define DC_HPD6_CONTROL__DC_HPD6_CONNECTION_TIMER__SHIFT 0x00000000 +#define DC_HPD6_CONTROL__DC_HPD6_EN_MASK 0x10000000L +#define DC_HPD6_CONTROL__DC_HPD6_EN__SHIFT 0x0000001c +#define DC_HPD6_CONTROL__DC_HPD6_RX_INT_TIMER_MASK 0x03ff0000L +#define DC_HPD6_CONTROL__DC_HPD6_RX_INT_TIMER__SHIFT 0x00000010 +#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_DELAY_MASK 0x000000ffL +#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_DELAY__SHIFT 0x00000000 +#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_EN__SHIFT 0x00000018 +#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_DELAY_MASK 0x000ff000L +#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_DELAY__SHIFT 0x0000000c +#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_EN__SHIFT 0x0000001c +#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_ACK_MASK 0x00000001L +#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_ACK__SHIFT 0x00000000 +#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_EN_MASK 0x00010000L +#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_EN__SHIFT 0x00000010 +#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK 0x00000100L +#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY__SHIFT 0x00000008 +#define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_ACK_MASK 0x00100000L +#define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_ACK__SHIFT 0x00000014 +#define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_EN_MASK 0x01000000L +#define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_EN__SHIFT 0x00000018 +#define DC_HPD6_INT_STATUS__DC_HPD6_INT_STATUS_MASK 0x00000001L +#define DC_HPD6_INT_STATUS__DC_HPD6_INT_STATUS__SHIFT 0x00000000 +#define DC_HPD6_INT_STATUS__DC_HPD6_RX_INT_STATUS_MASK 0x00000100L +#define DC_HPD6_INT_STATUS__DC_HPD6_RX_INT_STATUS__SHIFT 0x00000008 +#define DC_HPD6_INT_STATUS__DC_HPD6_SENSE_DELAYED_MASK 0x00000010L +#define DC_HPD6_INT_STATUS__DC_HPD6_SENSE_DELAYED__SHIFT 0x00000004 +#define DC_HPD6_INT_STATUS__DC_HPD6_SENSE_MASK 0x00000002L +#define DC_HPD6_INT_STATUS__DC_HPD6_SENSE__SHIFT 0x00000001 +#define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000ff000L +#define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0x0000000c +#define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000L +#define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x00000018 +#define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_CONNECT_INT_DELAY_MASK 0x000000ffL +#define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_CONNECT_INT_DELAY__SHIFT 0x00000000 +#define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_DISCONNECT_INT_DELAY_MASK 0x0ff00000L +#define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_DISCONNECT_INT_DELAY__SHIFT 0x00000014 +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK 0x00000100L +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT 0x00000008 +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK 0x00001000L +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT 0x0000000c +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK 0x02000000L +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT 0x00000019 +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK 0x01000000L +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT 0x00000018 +#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK 0x00000010L +#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT 0x00000004 +#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK 0x0000000cL +#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT 0x00000002 +#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK 0x00200000L +#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT 0x00000015 +#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK 0x00000003L +#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT 0x00000000 +#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK 0x00100000L +#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT 0x00000014 +#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL_MASK 0x80000000L +#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL__SHIFT 0x0000001f +#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK 0x00000700L +#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT 0x00000008 +#define DC_I2C_CONTROL__DC_I2C_GO_MASK 0x00000001L +#define DC_I2C_CONTROL__DC_I2C_GO__SHIFT 0x00000000 +#define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK 0x00000004L +#define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT 0x00000002 +#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK 0x00000002L +#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT 0x00000001 +#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK 0x00000008L +#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT 0x00000003 +#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK 0x00300000L +#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT 0x00000014 +#define DC_I2C_DATA__DC_I2C_DATA_MASK 0x0000ff00L +#define DC_I2C_DATA__DC_I2C_DATA_RW_MASK 0x00000001L +#define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT 0x00000000 +#define DC_I2C_DATA__DC_I2C_DATA__SHIFT 0x00000008 +#define DC_I2C_DATA__DC_I2C_INDEX_MASK 0x00ff0000L +#define DC_I2C_DATA__DC_I2C_INDEX__SHIFT 0x00000010 +#define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK 0x80000000L +#define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT 0x0000001f +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK 0x70000000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT 0x0000001c +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT 0x00000014 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT 0x00000003 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT 0x00000010 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT 0x00000000 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT 0x00000011 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT 0x00000007 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT 0x00000000 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT 0x00000001 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT 0x00000004 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT 0x00000005 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT 0x00000006 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK 0x0000ff00L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT 0x00000008 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK 0xff000000L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT 0x00000018 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK 0xffff0000L +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT 0x00000010 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT 0x00000000 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK 0x70000000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT 0x0000001c +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT 0x00000014 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT 0x00000003 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT 0x00000010 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT 0x00000000 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT 0x00000011 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT 0x00000007 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT 0x00000000 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT 0x00000001 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT 0x00000004 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT 0x00000005 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT 0x00000006 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK 0x0000ff00L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT 0x00000008 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK 0xff000000L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT 0x00000018 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK 0xffff0000L +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT 0x00000010 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT 0x00000000 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK 0x70000000L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT 0x0000001c +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT 0x00000014 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT 0x00000003 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT 0x00000010 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT 0x00000000 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT 0x00000011 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT 0x00000007 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT 0x00000000 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT 0x00000001 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT 0x00000004 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT 0x00000005 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT 0x00000006 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK 0x0000ff00L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT 0x00000008 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK 0xff000000L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT 0x00000018 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK 0xffff0000L +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT 0x00000010 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT 0x00000000 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK 0x70000000L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT 0x0000001c +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT 0x00000014 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT 0x00000003 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT 0x00000010 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT 0x00000000 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT 0x00000011 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT 0x00000007 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT 0x00000000 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT 0x00000001 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT 0x00000004 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT 0x00000005 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT 0x00000006 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK 0x0000ff00L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT 0x00000008 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK 0xff000000L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT 0x00000018 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK 0xffff0000L +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT 0x00000010 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT 0x00000000 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK 0x70000000L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT 0x0000001c +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT 0x00000014 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT 0x00000003 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT 0x00000010 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT 0x00000000 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT 0x00000011 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT 0x00000007 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT 0x00000000 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT 0x00000001 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT 0x00000004 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT 0x00000005 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT 0x00000006 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK 0x0000ff00L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT 0x00000008 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK 0xff000000L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT 0x00000018 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK 0xffff0000L +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT 0x00000010 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT 0x00000000 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE_MASK 0x70000000L +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE__SHIFT 0x0000001c +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS__SHIFT 0x00000014 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE__SHIFT 0x00000003 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ__SHIFT 0x00000010 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS__SHIFT 0x00000000 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG__SHIFT 0x00000011 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN__SHIFT 0x00000007 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN__SHIFT 0x00000000 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL__SHIFT 0x00000001 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE__SHIFT 0x00000004 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE__SHIFT 0x00000005 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE__SHIFT 0x00000006 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY_MASK 0x0000ff00L +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY__SHIFT 0x00000008 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT_MASK 0xff000000L +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT__SHIFT 0x00000018 +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE_MASK 0xffff0000L +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE__SHIFT 0x00000010 +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD__SHIFT 0x00000000 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE_MASK 0x70000000L +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE__SHIFT 0x0000001c +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS__SHIFT 0x00000014 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE__SHIFT 0x00000003 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ__SHIFT 0x00000010 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS__SHIFT 0x00000000 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG_MASK 0x00020000L +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG__SHIFT 0x00000011 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN__SHIFT 0x00000007 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN__SHIFT 0x00000000 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL__SHIFT 0x00000001 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE__SHIFT 0x00000004 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE__SHIFT 0x00000005 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE_MASK 0x00000040L +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE__SHIFT 0x00000006 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY_MASK 0x0000ff00L +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY__SHIFT 0x00000008 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT_MASK 0xff000000L +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT__SHIFT 0x00000018 +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE_MASK 0xffff0000L +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE__SHIFT 0x00000010 +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD__SHIFT 0x00000000 +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK 0x00f00000L +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT 0x00000014 +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK 0x10000000L +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT 0x0000001c +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK 0x0000ffffL +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT 0x00000000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK 0x00000020L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT 0x00000005 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK 0x00000010L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT 0x00000004 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK 0x00000040L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT 0x00000006 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK 0x00000200L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT 0x00000009 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK 0x00000100L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT 0x00000008 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK 0x00000400L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT 0x0000000a +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK 0x00002000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT 0x0000000d +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK 0x00001000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT 0x0000000c +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK 0x00004000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT 0x0000000e +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK 0x00020000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT 0x00000011 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK 0x00010000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT 0x00000010 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK 0x00040000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT 0x00000012 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK 0x00200000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT 0x00000015 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK 0x00100000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT 0x00000014 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK 0x00400000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT 0x00000016 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK 0x02000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT 0x00000019 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK 0x01000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT 0x00000018 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK 0x04000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT 0x0000001a +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK 0x10000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT 0x0000001c +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK 0x08000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT 0x0000001b +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK 0x20000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT 0x0000001d +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK 0x00000002L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT 0x00000001 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK 0x00000001L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT 0x00000000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK 0x00000004L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT 0x00000002 +#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK 0x00000010L +#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT 0x00000004 +#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK 0x00000080L +#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT 0x00000007 +#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK 0x00000004L +#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT 0x00000002 +#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK 0x00000040L +#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT 0x00000006 +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK 0x00001000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT 0x0000000c +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK 0x00002000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT 0x0000000d +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK 0x00004000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT 0x0000000e +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK 0x00008000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT 0x0000000f +#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK 0x00040000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT 0x00000012 +#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK 0x00000003L +#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT 0x00000000 +#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK 0x00000100L +#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT 0x00000008 +#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK 0x00000020L +#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT 0x00000005 +#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK 0x00ff0000L +#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT 0x00000010 +#define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK 0x00000001L +#define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT 0x00000000 +#define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK 0x00001000L +#define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT 0x0000000c +#define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK 0x00002000L +#define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT 0x0000000d +#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK 0x00000100L +#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT 0x00000008 +#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK 0x00ff0000L +#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT 0x00000010 +#define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK 0x00000001L +#define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT 0x00000000 +#define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK 0x00001000L +#define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT 0x0000000c +#define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK 0x00002000L +#define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT 0x0000000d +#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK 0x00000100L +#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT 0x00000008 +#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK 0x00ff0000L +#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT 0x00000010 +#define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK 0x00000001L +#define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT 0x00000000 +#define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK 0x00001000L +#define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT 0x0000000c +#define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK 0x00002000L +#define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT 0x0000000d +#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK 0x00000100L +#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT 0x00000008 +#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK 0x00ff0000L +#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT 0x00000010 +#define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK 0x00000001L +#define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT 0x00000000 +#define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK 0x00001000L +#define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT 0x0000000c +#define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK 0x00002000L +#define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT 0x0000000d +#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK 0x00000100L +#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT 0x00000008 +#define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL_MASK 0xf8000000L +#define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL__SHIFT 0x0000001b +#define DCI_CLK_CNTL__DCI_TEST_CLK_SEL_MASK 0x0000001fL +#define DCI_CLK_CNTL__DCI_TEST_CLK_SEL__SHIFT 0x00000000 +#define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS_MASK 0x00008000L +#define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS__SHIFT 0x0000000f +#define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS_MASK 0x00010000L +#define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS__SHIFT 0x00000010 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS_MASK 0x00020000L +#define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS__SHIFT 0x00000011 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS_MASK 0x00040000L +#define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS__SHIFT 0x00000012 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS_MASK 0x00080000L +#define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS__SHIFT 0x00000013 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS_MASK 0x00100000L +#define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS__SHIFT 0x00000014 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS_MASK 0x00200000L +#define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS__SHIFT 0x00000015 +#define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS_MASK 0x00000200L +#define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS__SHIFT 0x00000009 +#define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK 0x00000800L +#define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS__SHIFT 0x0000000b +#define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS_MASK 0x00002000L +#define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS__SHIFT 0x0000000d +#define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS_MASK 0x00000040L +#define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS__SHIFT 0x00000006 +#define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS_MASK 0x00000020L +#define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS__SHIFT 0x00000005 +#define DCI_CLK_CNTL__DISPCLK_R_DMCU_GATE_DIS_MASK 0x00004000L +#define DCI_CLK_CNTL__DISPCLK_R_DMCU_GATE_DIS__SHIFT 0x0000000e +#define DCI_CLK_CNTL__DISPCLK_R_VGA_GATE_DIS_MASK 0x00000400L +#define DCI_CLK_CNTL__DISPCLK_R_VGA_GATE_DIS__SHIFT 0x0000000a +#define DCI_CLK_CNTL__DISPCLK_R_VIP_GATE_DIS_MASK 0x00001000L +#define DCI_CLK_CNTL__DISPCLK_R_VIP_GATE_DIS__SHIFT 0x0000000c +#define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS_MASK 0x00400000L +#define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS__SHIFT 0x00000016 +#define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS_MASK 0x00800000L +#define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS__SHIFT 0x00000017 +#define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS_MASK 0x00000100L +#define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT 0x00000008 +#define DCI_DEBUG_CONFIG__DCI_DBG_SEL_MASK 0x0000000fL +#define DCI_DEBUG_CONFIG__DCI_DBG_SEL__SHIFT 0x00000000 +#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x00000000 +#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_PWR_STATE_MASK 0x00003000L +#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_PWR_STATE__SHIFT 0x0000000c +#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x00000040L +#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x00000006 +#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_LIGHT_SLEEP_DIS_MASK 0x00000002L +#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x00000001 +#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_PWR_STATE_MASK 0x0000c000L +#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_PWR_STATE__SHIFT 0x0000000e +#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x00000080L +#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x00000007 +#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_LIGHT_SLEEP_DIS_MASK 0x00000004L +#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x00000002 +#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_PWR_STATE_MASK 0x00030000L +#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_PWR_STATE__SHIFT 0x00000010 +#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x00000100L +#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x00000008 +#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_LIGHT_SLEEP_DIS_MASK 0x00000008L +#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x00000003 +#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_PWR_STATE_MASK 0x000c0000L +#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_PWR_STATE__SHIFT 0x00000012 +#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x00000200L +#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x00000009 +#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_LIGHT_SLEEP_DIS_MASK 0x00000010L +#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x00000004 +#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_PWR_STATE_MASK 0x00300000L +#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_PWR_STATE__SHIFT 0x00000014 +#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x00000400L +#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x0000000a +#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_LIGHT_SLEEP_DIS_MASK 0x00000020L +#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x00000005 +#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_PWR_STATE_MASK 0x00c00000L +#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_PWR_STATE__SHIFT 0x00000016 +#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x00000800L +#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x0000000b +#define DCI_MEM_PWR_STATE2__DMCU_ERAM1_PWR_STATE_MASK 0x00000003L +#define DCI_MEM_PWR_STATE2__DMCU_ERAM1_PWR_STATE__SHIFT 0x00000000 +#define DCI_MEM_PWR_STATE2__DMCU_ERAM2_PWR_STATE_MASK 0x0000000cL +#define DCI_MEM_PWR_STATE2__DMCU_ERAM2_PWR_STATE__SHIFT 0x00000002 +#define DCI_MEM_PWR_STATE2__DMCU_ERAM3_PWR_STATE_MASK 0x00000030L +#define DCI_MEM_PWR_STATE2__DMCU_ERAM3_PWR_STATE__SHIFT 0x00000004 +#define DCI_MEM_PWR_STATE__AZ_MEM_PWR_STATE_MASK 0x00c00000L +#define DCI_MEM_PWR_STATE__AZ_MEM_PWR_STATE__SHIFT 0x00000016 +#define DCI_MEM_PWR_STATE__DMCU_IRAM_PWR_STATE_MASK 0x30000000L +#define DCI_MEM_PWR_STATE__DMCU_IRAM_PWR_STATE__SHIFT 0x0000001c +#define DCI_MEM_PWR_STATE__DMCU_MEM_PWR_STATE_MASK 0x00000003L +#define DCI_MEM_PWR_STATE__DMCU_MEM_PWR_STATE__SHIFT 0x00000000 +#define DCI_MEM_PWR_STATE__DMIF0_MEM_PWR_STATE_MASK 0x0000000cL +#define DCI_MEM_PWR_STATE__DMIF0_MEM_PWR_STATE__SHIFT 0x00000002 +#define DCI_MEM_PWR_STATE__DMIF1_MEM_PWR_STATE_MASK 0x00000030L +#define DCI_MEM_PWR_STATE__DMIF1_MEM_PWR_STATE__SHIFT 0x00000004 +#define DCI_MEM_PWR_STATE__DMIF2_MEM_PWR_STATE_MASK 0x000000c0L +#define DCI_MEM_PWR_STATE__DMIF2_MEM_PWR_STATE__SHIFT 0x00000006 +#define DCI_MEM_PWR_STATE__DMIF3_MEM_PWR_STATE_MASK 0x00000300L +#define DCI_MEM_PWR_STATE__DMIF3_MEM_PWR_STATE__SHIFT 0x00000008 +#define DCI_MEM_PWR_STATE__DMIF4_MEM_PWR_STATE_MASK 0x00000c00L +#define DCI_MEM_PWR_STATE__DMIF4_MEM_PWR_STATE__SHIFT 0x0000000a +#define DCI_MEM_PWR_STATE__DMIF5_MEM_PWR_STATE_MASK 0x00003000L +#define DCI_MEM_PWR_STATE__DMIF5_MEM_PWR_STATE__SHIFT 0x0000000c +#define DCI_MEM_PWR_STATE__DMIF_XLR_MEM1_PWR_STATE_MASK 0x0c000000L +#define DCI_MEM_PWR_STATE__DMIF_XLR_MEM1_PWR_STATE__SHIFT 0x0000001a +#define DCI_MEM_PWR_STATE__DMIF_XLR_MEM_PWR_STATE_MASK 0x03000000L +#define DCI_MEM_PWR_STATE__DMIF_XLR_MEM_PWR_STATE__SHIFT 0x00000018 +#define DCI_MEM_PWR_STATE__FBC_MEM_PWR_STATE_MASK 0x00030000L +#define DCI_MEM_PWR_STATE__FBC_MEM_PWR_STATE__SHIFT 0x00000010 +#define DCI_MEM_PWR_STATE__MCIF_MEM_PWR_STATE_MASK 0x000c0000L +#define DCI_MEM_PWR_STATE__MCIF_MEM_PWR_STATE__SHIFT 0x00000012 +#define DCI_MEM_PWR_STATE__VGA_MEM_PWR_STATE_MASK 0x0000c000L +#define DCI_MEM_PWR_STATE__VGA_MEM_PWR_STATE__SHIFT 0x0000000e +#define DCI_MEM_PWR_STATE__VIP_MEM_PWR_STATE_MASK 0x00300000L +#define DCI_MEM_PWR_STATE__VIP_MEM_PWR_STATE__SHIFT 0x00000014 +#define DCIO_DEBUG10__DCIO_DIGC_DEBUG_MASK 0xffffffffL +#define DCIO_DEBUG10__DCIO_DIGC_DEBUG__SHIFT 0x00000000 +#define DCIO_DEBUG11__DCIO_DIGD_DEBUG_MASK 0xffffffffL +#define DCIO_DEBUG11__DCIO_DIGD_DEBUG__SHIFT 0x00000000 +#define DCIO_DEBUG12__DCIO_DIGE_DEBUG_MASK 0xffffffffL +#define DCIO_DEBUG12__DCIO_DIGE_DEBUG__SHIFT 0x00000000 +#define DCIO_DEBUG13__DCIO_DIGF_DEBUG_MASK 0xffffffffL +#define DCIO_DEBUG13__DCIO_DIGF_DEBUG__SHIFT 0x00000000 +#define DCIO_DEBUG1__DOUT_DCIO_DVO_CLK_TRISTATE_MASK 0x00040000L +#define DCIO_DEBUG1__DOUT_DCIO_DVO_CLK_TRISTATE__SHIFT 0x00000012 +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_MASK 0x00008000L +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_PREMUX_MASK 0x00004000L +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_PREMUX__SHIFT 0x0000000e +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_REG_MASK 0x00002000L +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_REG__SHIFT 0x0000000d +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0__SHIFT 0x0000000f +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_MASK 0x00100000L +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_PREMUX_MASK 0x00080000L +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_PREMUX__SHIFT 0x00000013 +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_REG_MASK 0x00010000L +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_REG__SHIFT 0x00000010 +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN__SHIFT 0x00000014 +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MASK_REG_MASK 0x00400000L +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MASK_REG__SHIFT 0x00000016 +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MUX_MASK 0x00200000L +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MUX__SHIFT 0x00000015 +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0_MASK 0x08000000L +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0_PREMUX_MASK 0x04000000L +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0_PREMUX__SHIFT 0x0000001a +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0__SHIFT 0x0000001b +#define DCIO_DEBUG1__DOUT_DCIO_DVO_ENABLE_MASK 0x00800000L +#define DCIO_DEBUG1__DOUT_DCIO_DVO_ENABLE__SHIFT 0x00000017 +#define DCIO_DEBUG1__DOUT_DCIO_DVO_HSYNC_TRISTATE_MASK 0x00020000L +#define DCIO_DEBUG1__DOUT_DCIO_DVO_HSYNC_TRISTATE__SHIFT 0x00000011 +#define DCIO_DEBUG1__DOUT_DCIO_DVO_RATE_SEL_MASK 0x02000000L +#define DCIO_DEBUG1__DOUT_DCIO_DVO_RATE_SEL__SHIFT 0x00000019 +#define DCIO_DEBUG1__DOUT_DCIO_DVO_VSYNC_TRISTATE_MASK 0x01000000L +#define DCIO_DEBUG1__DOUT_DCIO_DVO_VSYNC_TRISTATE__SHIFT 0x00000018 +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCLK_C_MASK 0x00001000L +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCLK_C__SHIFT 0x0000000c +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0_MASK 0x000000c0L +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0_REG_MASK 0x00000003L +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0_REG__SHIFT 0x00000000 +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0__SHIFT 0x00000006 +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN_MASK 0x00000c00L +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN_REG_MASK 0x00000030L +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN_REG__SHIFT 0x00000004 +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN__SHIFT 0x0000000a +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_MASK_REG_MASK 0x0000000cL +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_MASK_REG__SHIFT 0x00000002 +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_SEL0_MASK 0x00000300L +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_SEL0__SHIFT 0x00000008 +#define DCIO_DEBUG2__DCIO_DEBUG2_MASK 0xffffffffL +#define DCIO_DEBUG2__DCIO_DEBUG2__SHIFT 0x00000000 +#define DCIO_DEBUG3__DCIO_DEBUG3_MASK 0xffffffffL +#define DCIO_DEBUG3__DCIO_DEBUG3__SHIFT 0x00000000 +#define DCIO_DEBUG4__DCIO_DEBUG4_MASK 0xffffffffL +#define DCIO_DEBUG4__DCIO_DEBUG4__SHIFT 0x00000000 +#define DCIO_DEBUG5__DCIO_DEBUG5_MASK 0xffffffffL +#define DCIO_DEBUG5__DCIO_DEBUG5__SHIFT 0x00000000 +#define DCIO_DEBUG6__DCIO_DEBUG6_MASK 0xffffffffL +#define DCIO_DEBUG6__DCIO_DEBUG6__SHIFT 0x00000000 +#define DCIO_DEBUG7__DCIO_DEBUG7_MASK 0xffffffffL +#define DCIO_DEBUG7__DCIO_DEBUG7__SHIFT 0x00000000 +#define DCIO_DEBUG8__DCIO_DEBUG8_MASK 0xffffffffL +#define DCIO_DEBUG8__DCIO_DEBUG8__SHIFT 0x00000000 +#define DCIO_DEBUG9__DCIO_DEBUG9_MASK 0xffffffffL +#define DCIO_DEBUG9__DCIO_DEBUG9__SHIFT 0x00000000 +#define DCIO_DEBUGA__DCIO_DEBUGA_MASK 0xffffffffL +#define DCIO_DEBUGA__DCIO_DEBUGA__SHIFT 0x00000000 +#define DCIO_DEBUGB__DCIO_DEBUGB_MASK 0xffffffffL +#define DCIO_DEBUGB__DCIO_DEBUGB__SHIFT 0x00000000 +#define DCIO_DEBUGC__DCIO_DEBUGC_MASK 0xffffffffL +#define DCIO_DEBUGC__DCIO_DEBUGC__SHIFT 0x00000000 +#define DCIO_DEBUG__DCIO_DEBUG_MASK 0xffffffffL +#define DCIO_DEBUG__DCIO_DEBUG__SHIFT 0x00000000 +#define DCIO_DEBUGD__DCIO_DEBUGD_MASK 0xffffffffL +#define DCIO_DEBUGD__DCIO_DEBUGD__SHIFT 0x00000000 +#define DCIO_DEBUGE__DCIO_DIGA_DEBUG_MASK 0xffffffffL +#define DCIO_DEBUGE__DCIO_DIGA_DEBUG__SHIFT 0x00000000 +#define DCIO_DEBUGF__DCIO_DIGB_DEBUG_MASK 0xffffffffL +#define DCIO_DEBUGF__DCIO_DIGB_DEBUG__SHIFT 0x00000000 +#define DCIO_DEBUG_ID__DCIO_DEBUG_ID_MASK 0xffffffffL +#define DCIO_DEBUG_ID__DCIO_DEBUG_ID__SHIFT 0x00000000 +#define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL_MASK 0x00070000L +#define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL__SHIFT 0x00000010 +#define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL_MASK 0x00000700L +#define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL__SHIFT 0x00000008 +#define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL_MASK 0x00000007L +#define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL__SHIFT 0x00000000 +#define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL_MASK 0x00070000L +#define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL__SHIFT 0x00000010 +#define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL_MASK 0x00000700L +#define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL__SHIFT 0x00000008 +#define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL_MASK 0x00000007L +#define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL__SHIFT 0x00000000 +#define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL_MASK 0x00070000L +#define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL__SHIFT 0x00000010 +#define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL_MASK 0x00000700L +#define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL__SHIFT 0x00000008 +#define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL_MASK 0x00000007L +#define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL__SHIFT 0x00000000 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL_MASK 0x00000030L +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL__SHIFT 0x00000004 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK 0x00000300L +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT 0x00000008 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL_MASK 0x00000003L +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL__SHIFT 0x00000000 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL_MASK 0x00300000L +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL__SHIFT 0x00000014 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK 0x03000000L +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT 0x00000018 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL_MASK 0x00030000L +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL__SHIFT 0x00000010 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL_MASK 0x00000030L +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL__SHIFT 0x00000004 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK 0x00000300L +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT 0x00000008 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL_MASK 0x00000003L +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL__SHIFT 0x00000000 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL_MASK 0x00300000L +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL__SHIFT 0x00000014 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK 0x03000000L +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT 0x00000018 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL_MASK 0x00030000L +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL__SHIFT 0x00000010 +#define DCIO_IMPCAL_CNTL_AB__CALR_CNTL_OVERRIDE_MASK 0x0000000fL +#define DCIO_IMPCAL_CNTL_AB__CALR_CNTL_OVERRIDE__SHIFT 0x00000000 +#define DCIO_IMPCAL_CNTL_AB__IMPCAL_ARB_STATE_MASK 0x00007000L +#define DCIO_IMPCAL_CNTL_AB__IMPCAL_ARB_STATE__SHIFT 0x0000000c +#define DCIO_IMPCAL_CNTL_AB__IMPCAL_SOFT_RESET_MASK 0x00000020L +#define DCIO_IMPCAL_CNTL_AB__IMPCAL_SOFT_RESET__SHIFT 0x00000005 +#define DCIO_IMPCAL_CNTL_AB__IMPCAL_STATUS_MASK 0x00000300L +#define DCIO_IMPCAL_CNTL_AB__IMPCAL_STATUS__SHIFT 0x00000008 +#define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE_MASK 0x0000000fL +#define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE__SHIFT 0x00000000 +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE_MASK 0x00007000L +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE__SHIFT 0x0000000c +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET_MASK 0x00000020L +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET__SHIFT 0x00000005 +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS_MASK 0x00000300L +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS__SHIFT 0x00000008 +#define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE_MASK 0x0000000fL +#define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE__SHIFT 0x00000000 +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE_MASK 0x00007000L +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE__SHIFT 0x0000000c +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET_MASK 0x00000020L +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET__SHIFT 0x00000005 +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS_MASK 0x00000300L +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS__SHIFT 0x00000008 +#define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA_MASK 0xffffffffL +#define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define DCI_SOFT_RESET__DMIF0_SOFT_RESET_MASK 0x00000010L +#define DCI_SOFT_RESET__DMIF0_SOFT_RESET__SHIFT 0x00000004 +#define DCI_SOFT_RESET__DMIF1_SOFT_RESET_MASK 0x00000020L +#define DCI_SOFT_RESET__DMIF1_SOFT_RESET__SHIFT 0x00000005 +#define DCI_SOFT_RESET__DMIF2_SOFT_RESET_MASK 0x00000040L +#define DCI_SOFT_RESET__DMIF2_SOFT_RESET__SHIFT 0x00000006 +#define DCI_SOFT_RESET__DMIF3_SOFT_RESET_MASK 0x00000080L +#define DCI_SOFT_RESET__DMIF3_SOFT_RESET__SHIFT 0x00000007 +#define DCI_SOFT_RESET__DMIF4_SOFT_RESET_MASK 0x00000100L +#define DCI_SOFT_RESET__DMIF4_SOFT_RESET__SHIFT 0x00000008 +#define DCI_SOFT_RESET__DMIF5_SOFT_RESET_MASK 0x00000200L +#define DCI_SOFT_RESET__DMIF5_SOFT_RESET__SHIFT 0x00000009 +#define DCI_SOFT_RESET__DMIFARB_SOFT_RESET_MASK 0x00001000L +#define DCI_SOFT_RESET__DMIFARB_SOFT_RESET__SHIFT 0x0000000c +#define DCI_SOFT_RESET__FBC_SOFT_RESET_MASK 0x00000008L +#define DCI_SOFT_RESET__FBC_SOFT_RESET__SHIFT 0x00000003 +#define DCI_SOFT_RESET__MCIF_SOFT_RESET_MASK 0x00000004L +#define DCI_SOFT_RESET__MCIF_SOFT_RESET__SHIFT 0x00000002 +#define DCI_SOFT_RESET__VGA_SOFT_RESET_MASK 0x00000001L +#define DCI_SOFT_RESET__VGA_SOFT_RESET__SHIFT 0x00000000 +#define DCI_SOFT_RESET__VIP_SOFT_RESET_MASK 0x00000002L +#define DCI_SOFT_RESET__VIP_SOFT_RESET__SHIFT 0x00000001 +#define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA_MASK 0xffffffffL +#define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK 0x000003ffL +#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT 0x00000000 +#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK 0x000ffc00L +#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT 0x0000000a +#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK 0x3ff00000L +#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT 0x00000014 +#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK 0x00000002L +#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT 0x00000001 +#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK 0x00000001L +#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT 0x00000000 +#define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK 0x0000ffffL +#define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT 0x00000000 +#define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK 0x0000ffffL +#define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT 0x00000000 +#define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK 0x0000ffffL +#define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT 0x00000000 +#define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK 0x00000020L +#define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT 0x00000005 +#define DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK 0x000000c0L +#define DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT 0x00000006 +#define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK 0x00000010L +#define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT 0x00000004 +#define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK 0x00002000L +#define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT 0x0000000d +#define DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK 0x0000c000L +#define DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT 0x0000000e +#define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK 0x00001000L +#define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT 0x0000000c +#define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK 0x00200000L +#define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT 0x00000015 +#define DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK 0x00c00000L +#define DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT 0x00000016 +#define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK 0x00100000L +#define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT 0x00000014 +#define DC_LUT_CONTROL__DC_LUT_INC_B_MASK 0x0000000fL +#define DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT 0x00000000 +#define DC_LUT_CONTROL__DC_LUT_INC_G_MASK 0x00000f00L +#define DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT 0x00000008 +#define DC_LUT_CONTROL__DC_LUT_INC_R_MASK 0x000f0000L +#define DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT 0x00000010 +#define DC_LUT_PWL_DATA__DC_LUT_BASE_MASK 0x0000ffffL +#define DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT 0x00000000 +#define DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK 0xffff0000L +#define DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT 0x00000010 +#define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK 0x000000ffL +#define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT 0x00000000 +#define DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK 0x00000001L +#define DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT 0x00000000 +#define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK 0x0000ffffL +#define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT 0x00000000 +#define DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK 0x00000001L +#define DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT 0x00000000 +#define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK 0x0000ffffL +#define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT 0x00000000 +#define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK 0x0000ffffL +#define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT 0x00000000 +#define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK 0x0000ffffL +#define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT 0x00000000 +#define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT 0x00000000 +#define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS_MASK 0x80000000L +#define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS__SHIFT 0x0000001f +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP_MASK 0x10000000L +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP__SHIFT 0x0000001c +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE_MASK 0x00001000L +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__SHIFT 0x0000000c +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO_MASK 0x00010000L +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__SHIFT 0x00000010 +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL_MASK 0x00000100L +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL__SHIFT 0x00000008 +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS_MASK 0x00100000L +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS__SHIFT 0x00000014 +#define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE_MASK 0x00000003L +#define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE__SHIFT 0x00000000 +#define DCO_CLK_CNTL__DCO_TEST_CLK_SEL_MASK 0x0000001fL +#define DCO_CLK_CNTL__DCO_TEST_CLK_SEL__SHIFT 0x00000000 +#define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS_MASK 0x00000040L +#define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS__SHIFT 0x00000006 +#define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS_MASK 0x00000100L +#define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS__SHIFT 0x00000008 +#define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS_MASK 0x00000200L +#define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS__SHIFT 0x00000009 +#define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS_MASK 0x01000000L +#define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS__SHIFT 0x00000018 +#define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS_MASK 0x02000000L +#define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS__SHIFT 0x00000019 +#define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS_MASK 0x04000000L +#define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS__SHIFT 0x0000001a +#define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS_MASK 0x08000000L +#define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS__SHIFT 0x0000001b +#define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS_MASK 0x10000000L +#define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS__SHIFT 0x0000001c +#define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS_MASK 0x20000000L +#define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS__SHIFT 0x0000001d +#define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS_MASK 0x00000080L +#define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS__SHIFT 0x00000007 +#define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS_MASK 0x00010000L +#define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS__SHIFT 0x00000010 +#define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS_MASK 0x00020000L +#define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS__SHIFT 0x00000011 +#define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS_MASK 0x00040000L +#define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS__SHIFT 0x00000012 +#define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS_MASK 0x00080000L +#define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS__SHIFT 0x00000013 +#define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS_MASK 0x00100000L +#define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS__SHIFT 0x00000014 +#define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS_MASK 0x00200000L +#define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS__SHIFT 0x00000015 +#define DCO_CLK_CNTL__DISPCLK_R_ABM_GATE_DIS_MASK 0x00001000L +#define DCO_CLK_CNTL__DISPCLK_R_ABM_GATE_DIS__SHIFT 0x0000000c +#define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS_MASK 0x00000020L +#define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS__SHIFT 0x00000005 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_ABM_RAMP_DIS_MASK 0x00000040L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_ABM_RAMP_DIS__SHIFT 0x00000006 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACA_RAMP_DIS_MASK 0x00000100L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACA_RAMP_DIS__SHIFT 0x00000008 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACB_RAMP_DIS_MASK 0x00000200L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACB_RAMP_DIS__SHIFT 0x00000009 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGA_RAMP_DIS_MASK 0x01000000L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGA_RAMP_DIS__SHIFT 0x00000018 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGB_RAMP_DIS_MASK 0x02000000L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGB_RAMP_DIS__SHIFT 0x00000019 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGC_RAMP_DIS_MASK 0x04000000L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGC_RAMP_DIS__SHIFT 0x0000001a +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGD_RAMP_DIS_MASK 0x08000000L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGD_RAMP_DIS__SHIFT 0x0000001b +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGE_RAMP_DIS_MASK 0x10000000L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGE_RAMP_DIS__SHIFT 0x0000001c +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGF_RAMP_DIS_MASK 0x20000000L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGF_RAMP_DIS__SHIFT 0x0000001d +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DVO_RAMP_DIS_MASK 0x00000080L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DVO_RAMP_DIS__SHIFT 0x00000007 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT0_RAMP_DIS_MASK 0x00010000L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT0_RAMP_DIS__SHIFT 0x00000010 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT1_RAMP_DIS_MASK 0x00020000L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT1_RAMP_DIS__SHIFT 0x00000011 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT2_RAMP_DIS_MASK 0x00040000L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT2_RAMP_DIS__SHIFT 0x00000012 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT3_RAMP_DIS_MASK 0x00080000L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT3_RAMP_DIS__SHIFT 0x00000013 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT4_RAMP_DIS_MASK 0x00100000L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT4_RAMP_DIS__SHIFT 0x00000014 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT5_RAMP_DIS_MASK 0x00200000L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT5_RAMP_DIS__SHIFT 0x00000015 +#define DCO_CLK_RAMP_CNTL__DISPCLK_R_ABM_RAMP_DIS_MASK 0x00001000L +#define DCO_CLK_RAMP_CNTL__DISPCLK_R_ABM_RAMP_DIS__SHIFT 0x0000000c +#define DCO_CLK_RAMP_CNTL__DISPCLK_R_DCO_RAMP_DIS_MASK 0x00000020L +#define DCO_CLK_RAMP_CNTL__DISPCLK_R_DCO_RAMP_DIS__SHIFT 0x00000005 +#define DCO_LIGHT_SLEEP_DIS__DPA_LIGHT_SLEEP_DIS_MASK 0x00000008L +#define DCO_LIGHT_SLEEP_DIS__DPA_LIGHT_SLEEP_DIS__SHIFT 0x00000003 +#define DCO_LIGHT_SLEEP_DIS__DPA_MEM_SHUTDOWN_DIS_MASK 0x00020000L +#define DCO_LIGHT_SLEEP_DIS__DPA_MEM_SHUTDOWN_DIS__SHIFT 0x00000011 +#define DCO_LIGHT_SLEEP_DIS__DPB_LIGHT_SLEEP_DIS_MASK 0x00000010L +#define DCO_LIGHT_SLEEP_DIS__DPB_LIGHT_SLEEP_DIS__SHIFT 0x00000004 +#define DCO_LIGHT_SLEEP_DIS__DPB_MEM_SHUTDOWN_DIS_MASK 0x00040000L +#define DCO_LIGHT_SLEEP_DIS__DPB_MEM_SHUTDOWN_DIS__SHIFT 0x00000012 +#define DCO_LIGHT_SLEEP_DIS__DPC_LIGHT_SLEEP_DIS_MASK 0x00000020L +#define DCO_LIGHT_SLEEP_DIS__DPC_LIGHT_SLEEP_DIS__SHIFT 0x00000005 +#define DCO_LIGHT_SLEEP_DIS__DPC_MEM_SHUTDOWN_DIS_MASK 0x00080000L +#define DCO_LIGHT_SLEEP_DIS__DPC_MEM_SHUTDOWN_DIS__SHIFT 0x00000013 +#define DCO_LIGHT_SLEEP_DIS__DPD_LIGHT_SLEEP_DIS_MASK 0x00000040L +#define DCO_LIGHT_SLEEP_DIS__DPD_LIGHT_SLEEP_DIS__SHIFT 0x00000006 +#define DCO_LIGHT_SLEEP_DIS__DPD_MEM_SHUTDOWN_DIS_MASK 0x00100000L +#define DCO_LIGHT_SLEEP_DIS__DPD_MEM_SHUTDOWN_DIS__SHIFT 0x00000014 +#define DCO_LIGHT_SLEEP_DIS__DPE_LIGHT_SLEEP_DIS_MASK 0x00000080L +#define DCO_LIGHT_SLEEP_DIS__DPE_LIGHT_SLEEP_DIS__SHIFT 0x00000007 +#define DCO_LIGHT_SLEEP_DIS__DPE_MEM_SHUTDOWN_DIS_MASK 0x00200000L +#define DCO_LIGHT_SLEEP_DIS__DPE_MEM_SHUTDOWN_DIS__SHIFT 0x00000015 +#define DCO_LIGHT_SLEEP_DIS__DPF_LIGHT_SLEEP_DIS_MASK 0x00000100L +#define DCO_LIGHT_SLEEP_DIS__DPF_LIGHT_SLEEP_DIS__SHIFT 0x00000008 +#define DCO_LIGHT_SLEEP_DIS__DPF_MEM_SHUTDOWN_DIS_MASK 0x00400000L +#define DCO_LIGHT_SLEEP_DIS__DPF_MEM_SHUTDOWN_DIS__SHIFT 0x00000016 +#define DCO_LIGHT_SLEEP_DIS__HDMI0_LIGHT_SLEEP_DIS_MASK 0x00000200L +#define DCO_LIGHT_SLEEP_DIS__HDMI0_LIGHT_SLEEP_DIS__SHIFT 0x00000009 +#define DCO_LIGHT_SLEEP_DIS__HDMI1_LIGHT_SLEEP_DIS_MASK 0x00000400L +#define DCO_LIGHT_SLEEP_DIS__HDMI1_LIGHT_SLEEP_DIS__SHIFT 0x0000000a +#define DCO_LIGHT_SLEEP_DIS__HDMI2_LIGHT_SLEEP_DIS_MASK 0x00000800L +#define DCO_LIGHT_SLEEP_DIS__HDMI2_LIGHT_SLEEP_DIS__SHIFT 0x0000000b +#define DCO_LIGHT_SLEEP_DIS__HDMI3_LIGHT_SLEEP_DIS_MASK 0x00001000L +#define DCO_LIGHT_SLEEP_DIS__HDMI3_LIGHT_SLEEP_DIS__SHIFT 0x0000000c +#define DCO_LIGHT_SLEEP_DIS__HDMI4_LIGHT_SLEEP_DIS_MASK 0x00002000L +#define DCO_LIGHT_SLEEP_DIS__HDMI4_LIGHT_SLEEP_DIS__SHIFT 0x0000000d +#define DCO_LIGHT_SLEEP_DIS__HDMI5_LIGHT_SLEEP_DIS_MASK 0x00004000L +#define DCO_LIGHT_SLEEP_DIS__HDMI5_LIGHT_SLEEP_DIS__SHIFT 0x0000000e +#define DCO_LIGHT_SLEEP_DIS__I2C_LIGHT_SLEEP_FORCE_MASK 0x00000002L +#define DCO_LIGHT_SLEEP_DIS__I2C_LIGHT_SLEEP_FORCE__SHIFT 0x00000001 +#define DCO_LIGHT_SLEEP_DIS__MVP_LIGHT_SLEEP_DIS_MASK 0x00000004L +#define DCO_LIGHT_SLEEP_DIS__MVP_LIGHT_SLEEP_DIS__SHIFT 0x00000002 +#define DCO_LIGHT_SLEEP_DIS__MVP_MEM_SHUTDOWN_DIS_MASK 0x00010000L +#define DCO_LIGHT_SLEEP_DIS__MVP_MEM_SHUTDOWN_DIS__SHIFT 0x00000010 +#define DCO_LIGHT_SLEEP_DIS__TVOUT_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define DCO_LIGHT_SLEEP_DIS__TVOUT_LIGHT_SLEEP_DIS__SHIFT 0x00000000 +#define DCO_MEM_POWER_STATE__DPA_MEM_PWR_STATE_MASK 0x000000c0L +#define DCO_MEM_POWER_STATE__DPA_MEM_PWR_STATE__SHIFT 0x00000006 +#define DCO_MEM_POWER_STATE__DPB_MEM_PWR_STATE_MASK 0x00000300L +#define DCO_MEM_POWER_STATE__DPB_MEM_PWR_STATE__SHIFT 0x00000008 +#define DCO_MEM_POWER_STATE__DPC_MEM_PWR_STATE_MASK 0x00000c00L +#define DCO_MEM_POWER_STATE__DPC_MEM_PWR_STATE__SHIFT 0x0000000a +#define DCO_MEM_POWER_STATE__DPD_MEM_PWR_STATE_MASK 0x00003000L +#define DCO_MEM_POWER_STATE__DPD_MEM_PWR_STATE__SHIFT 0x0000000c +#define DCO_MEM_POWER_STATE__DPE_MEM_PWR_STATE_MASK 0x0000c000L +#define DCO_MEM_POWER_STATE__DPE_MEM_PWR_STATE__SHIFT 0x0000000e +#define DCO_MEM_POWER_STATE__DPF_MEM_PWR_STATE_MASK 0x00030000L +#define DCO_MEM_POWER_STATE__DPF_MEM_PWR_STATE__SHIFT 0x00000010 +#define DCO_MEM_POWER_STATE__HDMI0_MEM_PWR_STATE_MASK 0x000c0000L +#define DCO_MEM_POWER_STATE__HDMI0_MEM_PWR_STATE__SHIFT 0x00000012 +#define DCO_MEM_POWER_STATE__HDMI1_MEM_PWR_STATE_MASK 0x00300000L +#define DCO_MEM_POWER_STATE__HDMI1_MEM_PWR_STATE__SHIFT 0x00000014 +#define DCO_MEM_POWER_STATE__HDMI2_MEM_PWR_STATE_MASK 0x00c00000L +#define DCO_MEM_POWER_STATE__HDMI2_MEM_PWR_STATE__SHIFT 0x00000016 +#define DCO_MEM_POWER_STATE__HDMI3_MEM_PWR_STATE_MASK 0x03000000L +#define DCO_MEM_POWER_STATE__HDMI3_MEM_PWR_STATE__SHIFT 0x00000018 +#define DCO_MEM_POWER_STATE__HDMI4_MEM_PWR_STATE_MASK 0x0c000000L +#define DCO_MEM_POWER_STATE__HDMI4_MEM_PWR_STATE__SHIFT 0x0000001a +#define DCO_MEM_POWER_STATE__HDMI5_MEM_PWR_STATE_MASK 0x30000000L +#define DCO_MEM_POWER_STATE__HDMI5_MEM_PWR_STATE__SHIFT 0x0000001c +#define DCO_MEM_POWER_STATE__I2C_MEM_PWR_STATE_MASK 0x0000000cL +#define DCO_MEM_POWER_STATE__I2C_MEM_PWR_STATE__SHIFT 0x00000002 +#define DCO_MEM_POWER_STATE__MVP_MEM_PWR_STATE_MASK 0x00000030L +#define DCO_MEM_POWER_STATE__MVP_MEM_PWR_STATE__SHIFT 0x00000004 +#define DCO_MEM_POWER_STATE__TVOUT_MEM_PWR_STATE_MASK 0x00000003L +#define DCO_MEM_POWER_STATE__TVOUT_MEM_PWR_STATE__SHIFT 0x00000000 +#define DCO_SOFT_RESET__ABM_SOFT_RESET_MASK 0x02000000L +#define DCO_SOFT_RESET__ABM_SOFT_RESET__SHIFT 0x00000019 +#define DCO_SOFT_RESET__DACA_CFG_IF_SOFT_RESET_MASK 0x20000000L +#define DCO_SOFT_RESET__DACA_CFG_IF_SOFT_RESET__SHIFT 0x0000001d +#define DCO_SOFT_RESET__DACA_SOFT_RESET_MASK 0x00000001L +#define DCO_SOFT_RESET__DACA_SOFT_RESET__SHIFT 0x00000000 +#define DCO_SOFT_RESET__DACB_SOFT_RESET_MASK 0x00000002L +#define DCO_SOFT_RESET__DACB_SOFT_RESET__SHIFT 0x00000001 +#define DCO_SOFT_RESET__DVO_ENABLE_RST_MASK 0x00000008L +#define DCO_SOFT_RESET__DVO_ENABLE_RST__SHIFT 0x00000003 +#define DCO_SOFT_RESET__DVO_SOFT_RESET_MASK 0x08000000L +#define DCO_SOFT_RESET__DVO_SOFT_RESET__SHIFT 0x0000001b +#define DCO_SOFT_RESET__FMT0_SOFT_RESET_MASK 0x00010000L +#define DCO_SOFT_RESET__FMT0_SOFT_RESET__SHIFT 0x00000010 +#define DCO_SOFT_RESET__FMT1_SOFT_RESET_MASK 0x00020000L +#define DCO_SOFT_RESET__FMT1_SOFT_RESET__SHIFT 0x00000011 +#define DCO_SOFT_RESET__FMT2_SOFT_RESET_MASK 0x00040000L +#define DCO_SOFT_RESET__FMT2_SOFT_RESET__SHIFT 0x00000012 +#define DCO_SOFT_RESET__FMT3_SOFT_RESET_MASK 0x00080000L +#define DCO_SOFT_RESET__FMT3_SOFT_RESET__SHIFT 0x00000013 +#define DCO_SOFT_RESET__FMT4_SOFT_RESET_MASK 0x00100000L +#define DCO_SOFT_RESET__FMT4_SOFT_RESET__SHIFT 0x00000014 +#define DCO_SOFT_RESET__FMT5_SOFT_RESET_MASK 0x00200000L +#define DCO_SOFT_RESET__FMT5_SOFT_RESET__SHIFT 0x00000015 +#define DCO_SOFT_RESET__MVP_SOFT_RESET_MASK 0x01000000L +#define DCO_SOFT_RESET__MVP_SOFT_RESET__SHIFT 0x00000018 +#define DCO_SOFT_RESET__SOFT_RESET_DVO_MASK 0x00000004L +#define DCO_SOFT_RESET__SOFT_RESET_DVO__SHIFT 0x00000002 +#define DCO_SOFT_RESET__SRBM_SOFT_RESET_ENABLE_MASK 0x10000000L +#define DCO_SOFT_RESET__SRBM_SOFT_RESET_ENABLE__SHIFT 0x0000001c +#define DCO_SOFT_RESET__TVOUT_SOFT_RESET_MASK 0x04000000L +#define DCO_SOFT_RESET__TVOUT_SOFT_RESET__SHIFT 0x0000001a +#define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL_MASK 0x0000000fL +#define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL__SHIFT 0x00000000 +#define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS_MASK 0x00000030L +#define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS__SHIFT 0x00000004 +#define DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK 0x00000001L +#define DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT 0x00000000 +#define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK 0x00000300L +#define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT 0x00000008 +#define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK 0x0000001cL +#define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT 0x00000002 +#define DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK 0xffffffffL +#define DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT 0x00000000 +#define DCP_CRC_LAST__DCP_CRC_LAST_MASK 0xffffffffL +#define DCP_CRC_LAST__DCP_CRC_LAST__SHIFT 0x00000000 +#define DCP_CRC_MASK__DCP_CRC_MASK_MASK 0xffffffffL +#define DCP_CRC_MASK__DCP_CRC_MASK__SHIFT 0x00000000 +#define DCP_DEBUG2__DCP_DEBUG2_MASK 0xffffffffL +#define DCP_DEBUG2__DCP_DEBUG2__SHIFT 0x00000000 +#define DCP_DEBUG__DCP_DEBUG_MASK 0xffffffffL +#define DCP_DEBUG__DCP_DEBUG__SHIFT 0x00000000 +#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK 0x0003ffffL +#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT 0x00000000 +#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK 0x07f00000L +#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT 0x00000014 +#define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG_MASK 0xffff0000L +#define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG__SHIFT 0x00000010 +#define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS_MASK 0x00000004L +#define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS__SHIFT 0x00000002 +#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY_MASK 0x00000001L +#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY__SHIFT 0x00000000 +#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE_MASK 0x00000002L +#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE__SHIFT 0x00000001 +#define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG_MASK 0xffffffffL +#define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG__SHIFT 0x00000000 +#define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG_MASK 0xffffffffL +#define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG__SHIFT 0x00000000 +#define DCP_GSL_CONTROL__DCP_GSL0_EN_MASK 0x00000001L +#define DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT 0x00000000 +#define DCP_GSL_CONTROL__DCP_GSL1_EN_MASK 0x00000002L +#define DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT 0x00000001 +#define DCP_GSL_CONTROL__DCP_GSL2_EN_MASK 0x00000004L +#define DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT 0x00000002 +#define DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK 0x08000000L +#define DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT 0x0000001b +#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK 0xf0000000L +#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT 0x0000001c +#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK 0x0000f000L +#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT 0x0000000c +#define DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK 0x00010000L +#define DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT 0x00000010 +#define DCP_GSL_CONTROL__DCP_GSL_MODE_MASK 0x00000300L +#define DCP_GSL_CONTROL__DCP_GSL_MODE__SHIFT 0x00000008 +#define DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK 0x03000000L +#define DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT 0x00000018 +#define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA_MASK 0xffffffffL +#define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK 0x0000c000L +#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT 0x0000000e +#define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS_MASK 0x00000400L +#define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS__SHIFT 0x0000000a +#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK 0x00010000L +#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT 0x00000010 +#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK 0x00002000L +#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT 0x0000000d +#define DC_PINSTRAPS__DC_PINSTRAPS_VIP_DEVICE_MASK 0x00000800L +#define DC_PINSTRAPS__DC_PINSTRAPS_VIP_DEVICE__SHIFT 0x0000000b +#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK 0x0000000fL +#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT 0x00000000 +#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK 0x000000f0L +#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT 0x00000004 +#define DCP_RANDOM_SEEDS__DCP_RAND_B_SEED_MASK 0x00ff0000L +#define DCP_RANDOM_SEEDS__DCP_RAND_B_SEED__SHIFT 0x00000010 +#define DCP_RANDOM_SEEDS__DCP_RAND_G_SEED_MASK 0x0000ff00L +#define DCP_RANDOM_SEEDS__DCP_RAND_G_SEED__SHIFT 0x00000008 +#define DCP_RANDOM_SEEDS__DCP_RAND_R_SEED_MASK 0x000000ffL +#define DCP_RANDOM_SEEDS__DCP_RAND_R_SEED__SHIFT 0x00000000 +#define DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK 0x00000100L +#define DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT 0x00000008 +#define DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK 0x00000400L +#define DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT 0x0000000a +#define DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK 0x00000200L +#define DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT 0x00000009 +#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK 0x00000040L +#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT 0x00000006 +#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK 0x00000001L +#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT 0x00000000 +#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK 0x00000030L +#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT 0x00000004 +#define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA_MASK 0xffffffffL +#define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_DELAY_MASK 0x00000007L +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_DELAY__SHIFT 0x00000000 +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_TIMEOUT_DIS_MASK 0x00000008L +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_TIMEOUT_DIS__SHIFT 0x00000003 +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_DELAY_MASK 0x00000070L +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_DELAY__SHIFT 0x00000004 +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_TIMEOUT_DIS_MASK 0x00000080L +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_TIMEOUT_DIS__SHIFT 0x00000007 +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_DELAY_MASK 0x00000700L +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_DELAY__SHIFT 0x00000008 +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_TIMEOUT_DIS_MASK 0x00000800L +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_TIMEOUT_DIS__SHIFT 0x0000000b +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_DELAY_MASK 0x00007000L +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_DELAY__SHIFT 0x0000000c +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_TIMEOUT_DIS_MASK 0x00008000L +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_TIMEOUT_DIS__SHIFT 0x0000000f +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_DELAY_MASK 0x00070000L +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_DELAY__SHIFT 0x00000010 +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_TIMEOUT_DIS_MASK 0x00080000L +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_TIMEOUT_DIS__SHIFT 0x00000013 +#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_DELAY_MASK 0x00000007L +#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_DELAY__SHIFT 0x00000000 +#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_TIMEOUT_DIS_MASK 0x00000008L +#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_TIMEOUT_DIS__SHIFT 0x00000003 +#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_DELAY_MASK 0x00000070L +#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_DELAY__SHIFT 0x00000004 +#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_TIMEOUT_DIS_MASK 0x00000080L +#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_TIMEOUT_DIS__SHIFT 0x00000007 +#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK 0x00000300L +#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 0x00000008 +#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK 0x00000003L +#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x00000000 +#define DC_XDMA_INTERFACE_CNTL__DC_FLIP_PENDING_TO_DCP_MASK 0x00400000L +#define DC_XDMA_INTERFACE_CNTL__DC_FLIP_PENDING_TO_DCP__SHIFT 0x00000016 +#define DC_XDMA_INTERFACE_CNTL__DC_XDMA_FLIP_PENDING_MASK 0x00010000L +#define DC_XDMA_INTERFACE_CNTL__DC_XDMA_FLIP_PENDING__SHIFT 0x00000010 +#define DC_XDMA_INTERFACE_CNTL__XDMA_M_FLIP_PENDING_TO_DCP_MASK 0x00100000L +#define DC_XDMA_INTERFACE_CNTL__XDMA_M_FLIP_PENDING_TO_DCP__SHIFT 0x00000014 +#define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_ENABLE_MASK 0x0000003fL +#define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_ENABLE__SHIFT 0x00000000 +#define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_SEL_MASK 0x00000700L +#define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_SEL__SHIFT 0x00000008 +#define DC_XDMA_INTERFACE_CNTL__XDMA_S_FLIP_PENDING_TO_DCP_MASK 0x00200000L +#define DC_XDMA_INTERFACE_CNTL__XDMA_S_FLIP_PENDING_TO_DCP__SHIFT 0x00000015 +#define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK 0x00003000L +#define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT 0x0000000c +#define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK 0x00000003L +#define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT 0x00000000 +#define DEGAMMA_CONTROL__OVL_DEGAMMA_MODE_MASK 0x00000030L +#define DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT 0x00000004 +#define DENORM_CONTROL__DENORM_MODE_MASK 0x00000007L +#define DENORM_CONTROL__DENORM_MODE__SHIFT 0x00000000 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x00080000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x00000013 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK 0x00018000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT 0x0000000f +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK 0x00020000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT 0x00000011 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK 0x00040000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT 0x00000012 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x00007f00L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x00000008 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x0000007fL +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x00000000 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE_MASK 0x00100000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE__SHIFT 0x00000014 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG_MASK 0x00200000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG__SHIFT 0x00000015 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG_MASK 0x00400000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG__SHIFT 0x00000016 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER_MASK 0x7f000000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER__SHIFT 0x00000018 +#define DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00003f00L +#define DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x00000008 +#define DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L +#define DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x0000001c +#define DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L +#define DIG_BE_CNTL__DIG_MODE__SHIFT 0x00000010 +#define DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L +#define DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x00000000 +#define DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L +#define DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x00000008 +#define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003ffL +#define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x00000000 +#define DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT_MASK 0x00000001L +#define DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT__SHIFT 0x00000000 +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK_MASK 0x00000100L +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK__SHIFT 0x00000008 +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK 0x00000010L +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK_MASK 0x00001000L +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK__SHIFT 0x0000000c +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT__SHIFT 0x00000004 +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_MASK 0x00000001L +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED__SHIFT 0x00000000 +#define DIG_FE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00010000L +#define DIG_FE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x00000010 +#define DIG_FE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00100000L +#define DIG_FE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x00000014 +#define DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L +#define DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x00000000 +#define DIG_FE_CNTL__DIG_START_MASK 0x00000400L +#define DIG_FE_CNTL__DIG_START__SHIFT 0x0000000a +#define DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L +#define DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x00000008 +#define DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L +#define DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x00000004 +#define DIG_FE_CNTL__DIG_SWAP_MASK 0x00040000L +#define DIG_FE_CNTL__DIG_SWAP__SHIFT 0x00000012 +#define DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L +#define DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x00000018 +#define DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000fc00L +#define DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x0000000a +#define DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L +#define DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x0000001d +#define DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L +#define DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x00000008 +#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x0000001e +#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x0000001f +#define DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L +#define DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x00000000 +#define DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001f0000L +#define DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x00000010 +#define DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03c00000L +#define DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x00000016 +#define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000fcL +#define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x00000002 +#define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x00000001 +#define DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L +#define DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x00000008 +#define DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L +#define DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x00000000 +#define DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L +#define DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x00000001 +#define DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L +#define DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x00000002 +#define DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L +#define DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x00000003 +#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L +#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x00000008 +#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L +#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x00000000 +#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L +#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x00000004 +#define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3fffffffL +#define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x00000000 +#define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00ffffffL +#define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x00000000 +#define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L +#define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x00000018 +#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET_MASK 0x00000002L +#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET__SHIFT 0x00000001 +#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET_MASK 0x00000001L +#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET__SHIFT 0x00000000 +#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET_MASK 0x00000020L +#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET__SHIFT 0x00000005 +#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET_MASK 0x00000010L +#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET__SHIFT 0x00000004 +#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET_MASK 0x00000200L +#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET__SHIFT 0x00000009 +#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET_MASK 0x00000100L +#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET__SHIFT 0x00000008 +#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET_MASK 0x00002000L +#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET__SHIFT 0x0000000d +#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET_MASK 0x00001000L +#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET__SHIFT 0x0000000c +#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET_MASK 0x00020000L +#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET__SHIFT 0x00000011 +#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET_MASK 0x00010000L +#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET__SHIFT 0x00000010 +#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET_MASK 0x00200000L +#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET__SHIFT 0x00000015 +#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET_MASK 0x00100000L +#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET__SHIFT 0x00000014 +#define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L +#define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x00000001 +#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L +#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x00000004 +#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L +#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x00000005 +#define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03ff0000L +#define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x00000010 +#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L +#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x00000006 +#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L +#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x00000000 +#define DIG_TEST_PATTERN__LVDS_EYE_PATTERN_MASK 0x00000100L +#define DIG_TEST_PATTERN__LVDS_EYE_PATTERN__SHIFT 0x00000008 +#define DIG_TEST_PATTERN__LVDS_TEST_CLOCK_DATA_MASK 0x00000004L +#define DIG_TEST_PATTERN__LVDS_TEST_CLOCK_DATA__SHIFT 0x00000002 +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK 0x00000ff0L +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT 0x00000004 +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK 0x0000000fL +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT 0x00000000 +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK 0x40000000L +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT 0x0000001e +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK 0x10000000L +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT 0x0000001c +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK 0x20000000L +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT 0x0000001d +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK 0x80000000L +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT 0x0000001f +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK 0x00100000L +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT 0x00000014 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK 0x0e000000L +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT 0x00000019 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK 0x00003fffL +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT 0x00000000 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK 0x000f0000L +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT 0x00000010 +#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT__SHIFT 0x0000001e +#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT__SHIFT 0x0000001c +#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT__SHIFT 0x0000001d +#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT 0x00000014 +#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT 0x00000013 +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT 0x00000014 +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT 0x00000013 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x00000006 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x00000005 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x0000000a +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT__SHIFT 0x00000004 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT__SHIFT 0x00000007 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT__SHIFT 0x00000008 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT__SHIFT 0x00000009 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT 0x00000011 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT 0x00000012 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x0000000f +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x00000010 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK 0x80000000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT 0x0000001f +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT__SHIFT 0x00000003 +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT__SHIFT 0x00000002 +#define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT__SHIFT 0x00000000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT 0x00000014 +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT 0x00000013 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x00000006 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x00000005 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x0000000a +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT__SHIFT 0x00000004 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT__SHIFT 0x00000007 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT__SHIFT 0x00000008 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT__SHIFT 0x00000009 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT 0x00000011 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT 0x00000012 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x0000000f +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x00000010 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK 0x80000000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT 0x0000001f +#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT__SHIFT 0x00000003 +#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT__SHIFT 0x00000002 +#define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT__SHIFT 0x00000000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT 0x00000014 +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT 0x00000013 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x00000006 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x00000005 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x0000000a +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT__SHIFT 0x00000004 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT__SHIFT 0x00000007 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT__SHIFT 0x00000008 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT__SHIFT 0x00000009 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT 0x00000011 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT 0x00000012 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x0000000f +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x00000010 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK 0x80000000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT 0x0000001f +#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT__SHIFT 0x00000003 +#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT__SHIFT 0x00000002 +#define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT__SHIFT 0x00000000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT 0x00000014 +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT 0x00000013 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x00000006 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x00000005 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x0000000a +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT__SHIFT 0x00000004 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT__SHIFT 0x00000007 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT__SHIFT 0x00000008 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT__SHIFT 0x00000009 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT 0x00000011 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT 0x00000012 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x0000000f +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x00000010 +#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT__SHIFT 0x00000003 +#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT__SHIFT 0x00000002 +#define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT__SHIFT 0x00000000 +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT 0x00000014 +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT 0x00000013 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x00000006 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x00000005 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x0000000a +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT__SHIFT 0x00000004 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT__SHIFT 0x00000007 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT__SHIFT 0x00000008 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT__SHIFT 0x00000009 +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT 0x00000011 +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT 0x00000012 +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x0000000f +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x00000010 +#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK 0x80000000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT 0x0000001f +#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_TIMER_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_TIMER_INTERRUPT__SHIFT 0x00000018 +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT__SHIFT 0x00000003 +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT__SHIFT 0x00000002 +#define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT__SHIFT 0x00000000 +#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x00000006 +#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x00000005 +#define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x0000000a +#define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT__SHIFT 0x00000004 +#define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT__SHIFT 0x00000007 +#define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT__SHIFT 0x00000008 +#define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT__SHIFT 0x00000009 +#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT__SHIFT 0x00000016 +#define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT__SHIFT 0x00000017 +#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT 0x00000011 +#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT 0x00000012 +#define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT__SHIFT 0x00000019 +#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT 0x00000018 +#define DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT__SHIFT 0x00000015 +#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x0000000f +#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x00000010 +#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK 0x80000000L +#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT 0x0000001f +#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT__SHIFT 0x0000001b +#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT__SHIFT 0x0000001a +#define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT__SHIFT 0x00000003 +#define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT__SHIFT 0x00000002 +#define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT__SHIFT 0x00000000 +#define DISPOUT_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL_MASK 0x00000007L +#define DISPOUT_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL__SHIFT 0x00000000 +#define DISPOUT_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL_MASK 0x00070000L +#define DISPOUT_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL__SHIFT 0x00000010 +#define DISPPLL_BG_CNTL__DISPPLL_BG_ADJ_MASK 0x000000f0L +#define DISPPLL_BG_CNTL__DISPPLL_BG_ADJ__SHIFT 0x00000004 +#define DISPPLL_BG_CNTL__DISPPLL_BG_PDN_MASK 0x00000001L +#define DISPPLL_BG_CNTL__DISPPLL_BG_PDN__SHIFT 0x00000000 +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x01ffffffL +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x00000000 +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x02000000L +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x00000019 +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK 0x40000000L +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_MSK_MASK 0x08000000L +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_MSK__SHIFT 0x0000001b +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x04000000L +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x0000001a +#define DISP_TIMER_CONTROL__DISP_TIMER_INT__SHIFT 0x0000001e +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000L +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x0000001d +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000L +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x0000001c +#define DMCU_CTRL__DISABLE_IRQ_TO_UC_MASK 0x00000004L +#define DMCU_CTRL__DISABLE_IRQ_TO_UC__SHIFT 0x00000002 +#define DMCU_CTRL__DISABLE_XIRQ_TO_UC_MASK 0x00000008L +#define DMCU_CTRL__DISABLE_XIRQ_TO_UC__SHIFT 0x00000003 +#define DMCU_CTRL__DMCU_ENABLE_MASK 0x00000010L +#define DMCU_CTRL__DMCU_ENABLE__SHIFT 0x00000004 +#define DMCU_CTRL__IGNORE_PWRMGT_MASK 0x00000002L +#define DMCU_CTRL__IGNORE_PWRMGT__SHIFT 0x00000001 +#define DMCU_CTRL__RESET_UC_MASK 0x00000001L +#define DMCU_CTRL__RESET_UC__SHIFT 0x00000000 +#define DMCU_CTRL__UC_REG_RD_TIMEOUT_MASK 0xffc00000L +#define DMCU_CTRL__UC_REG_RD_TIMEOUT__SHIFT 0x00000016 +#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR_MASK 0x0000ffffL +#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR__SHIFT 0x00000000 +#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE_MASK 0x000f0000L +#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE__SHIFT 0x00000010 +#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE_MASK 0x00100000L +#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE__SHIFT 0x00000014 +#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA_MASK 0xffffffffL +#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA__SHIFT 0x00000000 +#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK 0x0000ffffL +#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR__SHIFT 0x00000000 +#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE_MASK 0x000f0000L +#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE__SHIFT 0x00000010 +#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE_MASK 0x00100000L +#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE__SHIFT 0x00000014 +#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA_MASK 0xffffffffL +#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA__SHIFT 0x00000000 +#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC_MASK 0x00000001L +#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC__SHIFT 0x00000000 +#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST_MASK 0x00800000L +#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST__SHIFT 0x00000017 +#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE_MASK 0x007f0000L +#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE__SHIFT 0x00000010 +#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS_MASK 0x0000000cL +#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS__SHIFT 0x00000002 +#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS_MASK 0x00000003L +#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS__SHIFT 0x00000000 +#define DMCU_FW_CS_HI__FW_CHECKSUM_HI_MASK 0xffffffffL +#define DMCU_FW_CS_HI__FW_CHECKSUM_HI__SHIFT 0x00000000 +#define DMCU_FW_CS_LO__FW_CHECKSUM_LO_MASK 0xffffffffL +#define DMCU_FW_CS_LO__FW_CHECKSUM_LO__SHIFT 0x00000000 +#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB_MASK 0x000000ffL +#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB__SHIFT 0x00000000 +#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB_MASK 0x0000ff00L +#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB__SHIFT 0x00000008 +#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB_MASK 0x000000ffL +#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB__SHIFT 0x00000000 +#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB_MASK 0x0000ff00L +#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB__SHIFT 0x00000008 +#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB_MASK 0x000000ffL +#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB__SHIFT 0x00000000 +#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB_MASK 0x0000ff00L +#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB__SHIFT 0x00000008 +#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT_MASK 0x00ff0000L +#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT__SHIFT 0x00000010 +#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT_MASK 0x000000ffL +#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT__SHIFT 0x00000000 +#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT_MASK 0x0000ff00L +#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT__SHIFT 0x00000008 +#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR_MASK 0x00000004L +#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR__SHIFT 0x00000002 +#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK 0x00000004L +#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED__SHIFT 0x00000002 +#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR_MASK 0x00000001L +#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR__SHIFT 0x00000000 +#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED_MASK 0x00000001L +#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED__SHIFT 0x00000000 +#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR_MASK 0x00000002L +#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR__SHIFT 0x00000001 +#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED_MASK 0x00000002L +#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED__SHIFT 0x00000001 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR_MASK 0x00040000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR__SHIFT 0x00000012 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED_MASK 0x00040000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED__SHIFT 0x00000012 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR_MASK 0x00001000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR__SHIFT 0x0000000c +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED_MASK 0x00001000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED__SHIFT 0x0000000c +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR_MASK 0x00080000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR__SHIFT 0x00000013 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED_MASK 0x00080000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED__SHIFT 0x00000013 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR_MASK 0x00002000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR__SHIFT 0x0000000d +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED_MASK 0x00002000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED__SHIFT 0x0000000d +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR_MASK 0x00100000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR__SHIFT 0x00000014 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED_MASK 0x00100000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED__SHIFT 0x00000014 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR_MASK 0x00004000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR__SHIFT 0x0000000e +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED_MASK 0x00004000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED__SHIFT 0x0000000e +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR_MASK 0x00200000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR__SHIFT 0x00000015 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED_MASK 0x00200000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED__SHIFT 0x00000015 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR_MASK 0x00008000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR__SHIFT 0x0000000f +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED_MASK 0x00008000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED__SHIFT 0x0000000f +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR_MASK 0x00400000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR__SHIFT 0x00000016 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED_MASK 0x00400000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED__SHIFT 0x00000016 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR_MASK 0x00010000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR__SHIFT 0x00000010 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED_MASK 0x00010000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED__SHIFT 0x00000010 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR_MASK 0x00800000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR__SHIFT 0x00000017 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED_MASK 0x00800000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED__SHIFT 0x00000017 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR_MASK 0x00020000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR__SHIFT 0x00000011 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED_MASK 0x00020000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED__SHIFT 0x00000011 +#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR_MASK 0x00000100L +#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR__SHIFT 0x00000008 +#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED_MASK 0x00000100L +#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED__SHIFT 0x00000008 +#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK 0x00000008L +#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED__SHIFT 0x00000003 +#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED_MASK 0x00000200L +#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED__SHIFT 0x00000009 +#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR_MASK 0x00000400L +#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR__SHIFT 0x0000000a +#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED_MASK 0x00000400L +#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED__SHIFT 0x0000000a +#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR_MASK 0x00000800L +#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR__SHIFT 0x0000000b +#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED_MASK 0x00000800L +#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED__SHIFT 0x0000000b +#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK 0x01000000L +#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR__SHIFT 0x00000018 +#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK 0x01000000L +#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED__SHIFT 0x00000018 +#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR_MASK 0x02000000L +#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR__SHIFT 0x00000019 +#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED_MASK 0x02000000L +#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED__SHIFT 0x00000019 +#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK 0x04000000L +#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR__SHIFT 0x0000001a +#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK 0x04000000L +#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED__SHIFT 0x0000001a +#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR_MASK 0x08000000L +#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT 0x0000001b +#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED_MASK 0x08000000L +#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED__SHIFT 0x0000001b +#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR_MASK 0x10000000L +#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR__SHIFT 0x0000001c +#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK 0x10000000L +#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED__SHIFT 0x0000001c +#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR_MASK 0x20000000L +#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR__SHIFT 0x0000001d +#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED_MASK 0x20000000L +#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED__SHIFT 0x0000001d +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK_MASK 0x00000004L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK__SHIFT 0x00000002 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK_MASK 0x00000001L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK__SHIFT 0x00000000 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK_MASK 0x00000002L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK__SHIFT 0x00000001 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_MASK_MASK 0x00040000L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_MASK__SHIFT 0x00000012 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_MASK_MASK 0x00001000L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_MASK__SHIFT 0x0000000c +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_MASK_MASK 0x00080000L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_MASK__SHIFT 0x00000013 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_MASK_MASK 0x00002000L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_MASK__SHIFT 0x0000000d +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_MASK_MASK 0x00100000L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_MASK__SHIFT 0x00000014 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_MASK_MASK 0x00004000L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_MASK__SHIFT 0x0000000e +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_MASK_MASK 0x00200000L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_MASK__SHIFT 0x00000015 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_MASK_MASK 0x00008000L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_MASK__SHIFT 0x0000000f +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_MASK_MASK 0x00400000L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_MASK__SHIFT 0x00000016 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_MASK_MASK 0x00010000L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_MASK__SHIFT 0x00000010 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_MASK_MASK 0x00800000L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_MASK__SHIFT 0x00000017 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_MASK_MASK 0x00020000L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_MASK__SHIFT 0x00000011 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK_MASK 0x00000200L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK__SHIFT 0x00000009 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK_MASK 0x00000400L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK__SHIFT 0x0000000a +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK_MASK 0x00000800L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK__SHIFT 0x0000000b +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN_MASK 0x00000004L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN__SHIFT 0x00000002 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN_MASK 0x00000001L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN__SHIFT 0x00000000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN_MASK 0x00000002L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN__SHIFT 0x00000001 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN_MASK 0x00040000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x00000012 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN_MASK 0x00001000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN__SHIFT 0x0000000c +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN_MASK 0x00080000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x00000013 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN_MASK 0x00002000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN__SHIFT 0x0000000d +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN_MASK 0x00100000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x00000014 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN_MASK 0x00004000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN__SHIFT 0x0000000e +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN_MASK 0x00200000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x00000015 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN_MASK 0x00008000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN__SHIFT 0x0000000f +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN_MASK 0x00400000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x00000016 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN_MASK 0x00010000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN__SHIFT 0x00000010 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN_MASK 0x00800000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x00000017 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN_MASK 0x00020000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN__SHIFT 0x00000011 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN_MASK 0x00000100L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN__SHIFT 0x00000008 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN_MASK 0x00000008L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN__SHIFT 0x00000003 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN_MASK 0x01000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN__SHIFT 0x00000018 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN_MASK 0x02000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN__SHIFT 0x00000019 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN_MASK 0x04000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN__SHIFT 0x0000001a +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN_MASK 0x08000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN__SHIFT 0x0000001b +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN_MASK 0x10000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN__SHIFT 0x0000001c +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN_MASK 0x20000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN__SHIFT 0x0000001d +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000004L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x00000002 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL_MASK 0x00000001L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x00000000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL_MASK 0x00000002L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x00000001 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00040000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x00000012 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00001000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0000000c +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00080000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x00000013 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00002000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0000000d +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00100000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x00000014 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00004000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0000000e +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00200000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x00000015 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00008000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0000000f +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00400000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x00000016 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00010000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x00000010 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00800000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x00000017 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00020000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x00000011 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK 0x00000100L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL__SHIFT 0x00000008 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL_MASK 0x00000008L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL__SHIFT 0x00000003 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL_MASK 0x01000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL__SHIFT 0x00000018 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL_MASK 0x02000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL__SHIFT 0x00000019 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL_MASK 0x04000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL__SHIFT 0x0000001a +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL_MASK 0x08000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL__SHIFT 0x0000001b +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL_MASK 0x10000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL__SHIFT 0x0000001c +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL_MASK 0x20000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL__SHIFT 0x0000001d +#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR_MASK 0x000003ffL +#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR__SHIFT 0x00000000 +#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA_MASK 0x000000ffL +#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA__SHIFT 0x00000000 +#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR_MASK 0x000003ffL +#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR__SHIFT 0x00000000 +#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA_MASK 0x000000ffL +#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA__SHIFT 0x00000000 +#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB_MASK 0x000000ffL +#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB__SHIFT 0x00000000 +#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB_MASK 0x0000ff00L +#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB__SHIFT 0x00000008 +#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN_MASK 0x00000010L +#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN__SHIFT 0x00000004 +#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC_MASK 0x00000002L +#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC__SHIFT 0x00000001 +#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC_MASK 0x00000001L +#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC__SHIFT 0x00000000 +#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK 0x00000020L +#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT 0x00000005 +#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK 0x00000008L +#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC__SHIFT 0x00000003 +#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK 0x00000004L +#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC__SHIFT 0x00000002 +#define DMCU_RAM_ACCESS_CTRL__UC_RST_RELEASE_DELAY_CNT_MASK 0x0000ff00L +#define DMCU_RAM_ACCESS_CTRL__UC_RST_RELEASE_DELAY_CNT__SHIFT 0x00000008 +#define DMCU_STATUS__UC_IN_RESET_MASK 0x00000001L +#define DMCU_STATUS__UC_IN_RESET__SHIFT 0x00000000 +#define DMCU_STATUS__UC_IN_STOP_MODE_MASK 0x00000004L +#define DMCU_STATUS__UC_IN_STOP_MODE__SHIFT 0x00000002 +#define DMCU_STATUS__UC_IN_WAIT_MODE_MASK 0x00000002L +#define DMCU_STATUS__UC_IN_WAIT_MODE__SHIFT 0x00000001 +#define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA_MASK 0xffffffffL +#define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY_MASK 0x00000700L +#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY__SHIFT 0x00000008 +#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY_MASK 0x00000007L +#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY__SHIFT 0x00000000 +#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN_MASK 0x00010000L +#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN__SHIFT 0x00000010 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP_MASK 0x00000008L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP__SHIFT 0x00000003 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN_MASK 0x00000001L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN__SHIFT 0x00000000 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE_MASK 0x00004000L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE__SHIFT 0x0000000e +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW_MASK 0x00008000L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW__SHIFT 0x0000000f +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT_MASK 0x00000200L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT__SHIFT 0x00000009 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT_MASK 0x00000004L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT__SHIFT 0x00000002 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1_MASK 0x00002000L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1__SHIFT 0x0000000d +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2_MASK 0x00001000L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2__SHIFT 0x0000000c +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3_MASK 0x00000800L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3__SHIFT 0x0000000b +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5_MASK 0x00000400L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5__SHIFT 0x0000000a +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1_MASK 0x00000080L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1__SHIFT 0x00000007 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2_MASK 0x00000040L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2__SHIFT 0x00000006 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3_MASK 0x00000020L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3__SHIFT 0x00000005 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4_MASK 0x00000010L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4__SHIFT 0x00000004 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW_MASK 0x00000100L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW__SHIFT 0x00000008 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN_MASK 0x00000002L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN__SHIFT 0x00000001 +#define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE_MASK 0x00000070L +#define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004 +#define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE_MASK 0x30000000L +#define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE__SHIFT 0x0000001c +#define DMIF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define DMIF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008 +#define DMIF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L +#define DMIF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e +#define DMIF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define DMIF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000 +#define DMIF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L +#define DMIF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c +#define DMIF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L +#define DMIF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004 +#define DMIF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L +#define DMIF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c +#define DMIF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L +#define DMIF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010 +#define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD_MASK 0x0000ffffL +#define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD__SHIFT 0x00000000 +#define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT_MASK 0xffff0000L +#define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT__SHIFT 0x00000010 +#define DMIF_CONTROL__DMIF_BUFF_SIZE_MASK 0x00000003L +#define DMIF_CONTROL__DMIF_BUFF_SIZE__SHIFT 0x00000000 +#define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN_MASK 0x60000000L +#define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN__SHIFT 0x0000001d +#define DMIF_CONTROL__DMIF_DELAY_ARBITRATION_MASK 0x1f000000L +#define DMIF_CONTROL__DMIF_DELAY_ARBITRATION__SHIFT 0x00000018 +#define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT_MASK 0x00000010L +#define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT__SHIFT 0x00000004 +#define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE_MASK 0x0000f000L +#define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE__SHIFT 0x0000000c +#define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK_MASK 0x00000004L +#define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK__SHIFT 0x00000002 +#define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS_MASK 0x003f0000L +#define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS__SHIFT 0x00000010 +#define DMIF_CONTROL__DMIF_REQ_BURST_SIZE_MASK 0x00000700L +#define DMIF_CONTROL__DMIF_REQ_BURST_SIZE__SHIFT 0x00000008 +#define DMIF_DEBUG02_CORE0__DB_DATA_MASK 0x0000ffffL +#define DMIF_DEBUG02_CORE0__DB_DATA__SHIFT 0x00000000 +#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN_MASK 0x00010000L +#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN__SHIFT 0x00000010 +#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER_MASK 0x0ffe0000L +#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER__SHIFT 0x00000011 +#define DMIF_DEBUG02_CORE1__DB_DATA_MASK 0x0000ffffL +#define DMIF_DEBUG02_CORE1__DB_DATA__SHIFT 0x00000000 +#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN_MASK 0x00010000L +#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN__SHIFT 0x00000010 +#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER_MASK 0x0ffe0000L +#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER__SHIFT 0x00000011 +#define DMIF_HW_DEBUG__DMIF_HW_DEBUG_MASK 0xffffffffL +#define DMIF_HW_DEBUG__DMIF_HW_DEBUG__SHIFT 0x00000000 +#define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS_MASK 0x00000100L +#define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS__SHIFT 0x00000008 +#define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS_MASK 0x00000200L +#define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS__SHIFT 0x00000009 +#define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS_MASK 0x00000001L +#define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS__SHIFT 0x00000000 +#define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS_MASK 0x00000002L +#define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS__SHIFT 0x00000001 +#define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS_MASK 0x00000004L +#define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS__SHIFT 0x00000002 +#define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS_MASK 0x00000008L +#define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS__SHIFT 0x00000003 +#define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS_MASK 0x00000010L +#define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS__SHIFT 0x00000004 +#define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS_MASK 0x00000020L +#define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS__SHIFT 0x00000005 +#define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE_MASK 0x00003f00L +#define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE__SHIFT 0x00000008 +#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x00010000L +#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x00000010 +#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT_MASK 0x00700000L +#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT__SHIFT 0x00000014 +#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x00020000L +#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x00000011 +#define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE_MASK 0x0000003fL +#define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE__SHIFT 0x00000000 +#define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT_MASK 0x07000000L +#define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT__SHIFT 0x00000018 +#define DMIF_STATUS__DMIF_UNDERFLOW_MASK 0x10000000L +#define DMIF_STATUS__DMIF_UNDERFLOW__SHIFT 0x0000001c +#define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA_MASK 0xffffffffL +#define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define DOUT_DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT_MASK 0x00000070L +#define DOUT_DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT__SHIFT 0x00000004 +#define DOUT_DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT_MASK 0x00000007L +#define DOUT_DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT__SHIFT 0x00000000 +#define DOUT_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK 0x00000100L +#define DOUT_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT 0x00000008 +#define DOUT_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK 0x00000001L +#define DOUT_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT 0x00000000 +#define DOUT_SCRATCH0__DOUT_SCRATCH0_MASK 0xffffffffL +#define DOUT_SCRATCH0__DOUT_SCRATCH0__SHIFT 0x00000000 +#define DOUT_SCRATCH1__DOUT_SCRATCH1_MASK 0xffffffffL +#define DOUT_SCRATCH1__DOUT_SCRATCH1__SHIFT 0x00000000 +#define DOUT_SCRATCH2__DOUT_SCRATCH2_MASK 0xffffffffL +#define DOUT_SCRATCH2__DOUT_SCRATCH2__SHIFT 0x00000000 +#define DOUT_SCRATCH3__DOUT_SCRATCH3_MASK 0xffffffffL +#define DOUT_SCRATCH3__DOUT_SCRATCH3__SHIFT 0x00000000 +#define DOUT_SCRATCH4__DOUT_SCRATCH4_MASK 0xffffffffL +#define DOUT_SCRATCH4__DOUT_SCRATCH4__SHIFT 0x00000000 +#define DOUT_SCRATCH5__DOUT_SCRATCH5_MASK 0xffffffffL +#define DOUT_SCRATCH5__DOUT_SCRATCH5__SHIFT 0x00000000 +#define DOUT_SCRATCH6__DOUT_SCRATCH6_MASK 0xffffffffL +#define DOUT_SCRATCH6__DOUT_SCRATCH6__SHIFT 0x00000000 +#define DOUT_SCRATCH7__DOUT_SCRATCH7_MASK 0xffffffffL +#define DOUT_SCRATCH7__DOUT_SCRATCH7__SHIFT 0x00000000 +#define DOUT_TEST_DEBUG_DATA__DOUT_TEST_DEBUG_DATA_MASK 0xffffffffL +#define DOUT_TEST_DEBUG_DATA__DOUT_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define DP_AUX1_DEBUG_A__DP_AUX1_DEBUG_A_MASK 0xffffffffL +#define DP_AUX1_DEBUG_A__DP_AUX1_DEBUG_A__SHIFT 0x00000000 +#define DP_AUX1_DEBUG_B__DP_AUX1_DEBUG_B_MASK 0xffffffffL +#define DP_AUX1_DEBUG_B__DP_AUX1_DEBUG_B__SHIFT 0x00000000 +#define DP_AUX1_DEBUG_C__DP_AUX1_DEBUG_C_MASK 0xffffffffL +#define DP_AUX1_DEBUG_C__DP_AUX1_DEBUG_C__SHIFT 0x00000000 +#define DP_AUX1_DEBUG_D__DP_AUX1_DEBUG_D_MASK 0xffffffffL +#define DP_AUX1_DEBUG_D__DP_AUX1_DEBUG_D__SHIFT 0x00000000 +#define DP_AUX1_DEBUG_E__DP_AUX1_DEBUG_E_MASK 0xffffffffL +#define DP_AUX1_DEBUG_E__DP_AUX1_DEBUG_E__SHIFT 0x00000000 +#define DP_AUX1_DEBUG_F__DP_AUX1_DEBUG_F_MASK 0xffffffffL +#define DP_AUX1_DEBUG_F__DP_AUX1_DEBUG_F__SHIFT 0x00000000 +#define DP_AUX1_DEBUG_G__DP_AUX1_DEBUG_G_MASK 0xffffffffL +#define DP_AUX1_DEBUG_G__DP_AUX1_DEBUG_G__SHIFT 0x00000000 +#define DP_AUX1_DEBUG_H__DP_AUX1_DEBUG_H_MASK 0xffffffffL +#define DP_AUX1_DEBUG_H__DP_AUX1_DEBUG_H__SHIFT 0x00000000 +#define DP_AUX1_DEBUG_I__DP_AUX1_DEBUG_I_MASK 0xffffffffL +#define DP_AUX1_DEBUG_I__DP_AUX1_DEBUG_I__SHIFT 0x00000000 +#define DP_AUX2_DEBUG_A__DP_AUX2_DEBUG_A_MASK 0xffffffffL +#define DP_AUX2_DEBUG_A__DP_AUX2_DEBUG_A__SHIFT 0x00000000 +#define DP_AUX2_DEBUG_B__DP_AUX2_DEBUG_B_MASK 0xffffffffL +#define DP_AUX2_DEBUG_B__DP_AUX2_DEBUG_B__SHIFT 0x00000000 +#define DP_AUX2_DEBUG_C__DP_AUX2_DEBUG_C_MASK 0xffffffffL +#define DP_AUX2_DEBUG_C__DP_AUX2_DEBUG_C__SHIFT 0x00000000 +#define DP_AUX2_DEBUG_D__DP_AUX2_DEBUG_D_MASK 0xffffffffL +#define DP_AUX2_DEBUG_D__DP_AUX2_DEBUG_D__SHIFT 0x00000000 +#define DP_AUX2_DEBUG_E__DP_AUX2_DEBUG_E_MASK 0xffffffffL +#define DP_AUX2_DEBUG_E__DP_AUX2_DEBUG_E__SHIFT 0x00000000 +#define DP_AUX2_DEBUG_F__DP_AUX2_DEBUG_F_MASK 0xffffffffL +#define DP_AUX2_DEBUG_F__DP_AUX2_DEBUG_F__SHIFT 0x00000000 +#define DP_AUX2_DEBUG_G__DP_AUX2_DEBUG_G_MASK 0xffffffffL +#define DP_AUX2_DEBUG_G__DP_AUX2_DEBUG_G__SHIFT 0x00000000 +#define DP_AUX2_DEBUG_H__DP_AUX2_DEBUG_H_MASK 0xffffffffL +#define DP_AUX2_DEBUG_H__DP_AUX2_DEBUG_H__SHIFT 0x00000000 +#define DP_AUX2_DEBUG_I__DP_AUX2_DEBUG_I_MASK 0xffffffffL +#define DP_AUX2_DEBUG_I__DP_AUX2_DEBUG_I__SHIFT 0x00000000 +#define DP_AUX3_DEBUG_A__DP_AUX3_DEBUG_A_MASK 0xffffffffL +#define DP_AUX3_DEBUG_A__DP_AUX3_DEBUG_A__SHIFT 0x00000000 +#define DP_AUX3_DEBUG_B__DP_AUX3_DEBUG_B_MASK 0xffffffffL +#define DP_AUX3_DEBUG_B__DP_AUX3_DEBUG_B__SHIFT 0x00000000 +#define DP_AUX3_DEBUG_C__DP_AUX3_DEBUG_C_MASK 0xffffffffL +#define DP_AUX3_DEBUG_C__DP_AUX3_DEBUG_C__SHIFT 0x00000000 +#define DP_AUX3_DEBUG_D__DP_AUX3_DEBUG_D_MASK 0xffffffffL +#define DP_AUX3_DEBUG_D__DP_AUX3_DEBUG_D__SHIFT 0x00000000 +#define DP_AUX3_DEBUG_E__DP_AUX3_DEBUG_E_MASK 0xffffffffL +#define DP_AUX3_DEBUG_E__DP_AUX3_DEBUG_E__SHIFT 0x00000000 +#define DP_AUX3_DEBUG_F__DP_AUX3_DEBUG_F_MASK 0xffffffffL +#define DP_AUX3_DEBUG_F__DP_AUX3_DEBUG_F__SHIFT 0x00000000 +#define DP_AUX3_DEBUG_G__DP_AUX3_DEBUG_G_MASK 0xffffffffL +#define DP_AUX3_DEBUG_G__DP_AUX3_DEBUG_G__SHIFT 0x00000000 +#define DP_AUX3_DEBUG_H__DP_AUX3_DEBUG_H_MASK 0xffffffffL +#define DP_AUX3_DEBUG_H__DP_AUX3_DEBUG_H__SHIFT 0x00000000 +#define DP_AUX3_DEBUG_I__DP_AUX3_DEBUG_I_MASK 0xffffffffL +#define DP_AUX3_DEBUG_I__DP_AUX3_DEBUG_I__SHIFT 0x00000000 +#define DP_AUX4_DEBUG_A__DP_AUX4_DEBUG_A_MASK 0xffffffffL +#define DP_AUX4_DEBUG_A__DP_AUX4_DEBUG_A__SHIFT 0x00000000 +#define DP_AUX4_DEBUG_B__DP_AUX4_DEBUG_B_MASK 0xffffffffL +#define DP_AUX4_DEBUG_B__DP_AUX4_DEBUG_B__SHIFT 0x00000000 +#define DP_AUX4_DEBUG_C__DP_AUX4_DEBUG_C_MASK 0xffffffffL +#define DP_AUX4_DEBUG_C__DP_AUX4_DEBUG_C__SHIFT 0x00000000 +#define DP_AUX4_DEBUG_D__DP_AUX4_DEBUG_D_MASK 0xffffffffL +#define DP_AUX4_DEBUG_D__DP_AUX4_DEBUG_D__SHIFT 0x00000000 +#define DP_AUX4_DEBUG_E__DP_AUX4_DEBUG_E_MASK 0xffffffffL +#define DP_AUX4_DEBUG_E__DP_AUX4_DEBUG_E__SHIFT 0x00000000 +#define DP_AUX4_DEBUG_F__DP_AUX4_DEBUG_F_MASK 0xffffffffL +#define DP_AUX4_DEBUG_F__DP_AUX4_DEBUG_F__SHIFT 0x00000000 +#define DP_AUX4_DEBUG_G__DP_AUX4_DEBUG_G_MASK 0xffffffffL +#define DP_AUX4_DEBUG_G__DP_AUX4_DEBUG_G__SHIFT 0x00000000 +#define DP_AUX4_DEBUG_H__DP_AUX4_DEBUG_H_MASK 0xffffffffL +#define DP_AUX4_DEBUG_H__DP_AUX4_DEBUG_H__SHIFT 0x00000000 +#define DP_AUX4_DEBUG_I__DP_AUX4_DEBUG_I_MASK 0xffffffffL +#define DP_AUX4_DEBUG_I__DP_AUX4_DEBUG_I__SHIFT 0x00000000 +#define DP_AUX5_DEBUG_A__DP_AUX5_DEBUG_A_MASK 0xffffffffL +#define DP_AUX5_DEBUG_A__DP_AUX5_DEBUG_A__SHIFT 0x00000000 +#define DP_AUX5_DEBUG_B__DP_AUX5_DEBUG_B_MASK 0xffffffffL +#define DP_AUX5_DEBUG_B__DP_AUX5_DEBUG_B__SHIFT 0x00000000 +#define DP_AUX5_DEBUG_C__DP_AUX5_DEBUG_C_MASK 0xffffffffL +#define DP_AUX5_DEBUG_C__DP_AUX5_DEBUG_C__SHIFT 0x00000000 +#define DP_AUX5_DEBUG_D__DP_AUX5_DEBUG_D_MASK 0xffffffffL +#define DP_AUX5_DEBUG_D__DP_AUX5_DEBUG_D__SHIFT 0x00000000 +#define DP_AUX5_DEBUG_E__DP_AUX5_DEBUG_E_MASK 0xffffffffL +#define DP_AUX5_DEBUG_E__DP_AUX5_DEBUG_E__SHIFT 0x00000000 +#define DP_AUX5_DEBUG_F__DP_AUX5_DEBUG_F_MASK 0xffffffffL +#define DP_AUX5_DEBUG_F__DP_AUX5_DEBUG_F__SHIFT 0x00000000 +#define DP_AUX5_DEBUG_G__DP_AUX5_DEBUG_G_MASK 0xffffffffL +#define DP_AUX5_DEBUG_G__DP_AUX5_DEBUG_G__SHIFT 0x00000000 +#define DP_AUX5_DEBUG_H__DP_AUX5_DEBUG_H_MASK 0xffffffffL +#define DP_AUX5_DEBUG_H__DP_AUX5_DEBUG_H__SHIFT 0x00000000 +#define DP_AUX5_DEBUG_I__DP_AUX5_DEBUG_I_MASK 0xffffffffL +#define DP_AUX5_DEBUG_I__DP_AUX5_DEBUG_I__SHIFT 0x00000000 +#define DP_AUX6_DEBUG_A__DP_AUX6_DEBUG_A_MASK 0xffffffffL +#define DP_AUX6_DEBUG_A__DP_AUX6_DEBUG_A__SHIFT 0x00000000 +#define DP_AUX6_DEBUG_B__DP_AUX6_DEBUG_B_MASK 0xffffffffL +#define DP_AUX6_DEBUG_B__DP_AUX6_DEBUG_B__SHIFT 0x00000000 +#define DP_AUX6_DEBUG_C__DP_AUX6_DEBUG_C_MASK 0xffffffffL +#define DP_AUX6_DEBUG_C__DP_AUX6_DEBUG_C__SHIFT 0x00000000 +#define DP_AUX6_DEBUG_D__DP_AUX6_DEBUG_D_MASK 0xffffffffL +#define DP_AUX6_DEBUG_D__DP_AUX6_DEBUG_D__SHIFT 0x00000000 +#define DP_AUX6_DEBUG_E__DP_AUX6_DEBUG_E_MASK 0xffffffffL +#define DP_AUX6_DEBUG_E__DP_AUX6_DEBUG_E__SHIFT 0x00000000 +#define DP_AUX6_DEBUG_F__DP_AUX6_DEBUG_F_MASK 0xffffffffL +#define DP_AUX6_DEBUG_F__DP_AUX6_DEBUG_F__SHIFT 0x00000000 +#define DP_AUX6_DEBUG_G__DP_AUX6_DEBUG_G_MASK 0xffffffffL +#define DP_AUX6_DEBUG_G__DP_AUX6_DEBUG_G__SHIFT 0x00000000 +#define DP_AUX6_DEBUG_H__DP_AUX6_DEBUG_H_MASK 0xffffffffL +#define DP_AUX6_DEBUG_H__DP_AUX6_DEBUG_H__SHIFT 0x00000000 +#define DP_AUX6_DEBUG_I__DP_AUX6_DEBUG_I_MASK 0xffffffffL +#define DP_AUX6_DEBUG_I__DP_AUX6_DEBUG_I__SHIFT 0x00000000 +#define DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L +#define DP_CONFIG__DP_UDI_LANES__SHIFT 0x00000000 +#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L +#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x00000018 +#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L +#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x00000010 +#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L +#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x00000008 +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x00000000 +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x00000001 +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x00000002 +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x00000003 +#define DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L +#define DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x00000010 +#define DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L +#define DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x00000018 +#define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L +#define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x00000000 +#define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00ff0000L +#define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x00000010 +#define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L +#define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x00000004 +#define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L +#define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x00000004 +#define DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L +#define DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x00000000 +#define DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L +#define DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x00000008 +#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003fL +#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x00000000 +#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003f00L +#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x00000008 +#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L +#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x00000010 +#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L +#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x00000008 +#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L +#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x00000000 +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000ff00L +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x00000008 +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00ff0000L +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x00000010 +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xff000000L +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x00000018 +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000ffL +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x00000000 +#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000fff00L +#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x00000008 +#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xfff00000L +#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x00000014 +#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L +#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x00000002 +#define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L +#define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x00000000 +#define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L +#define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x00000001 +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0x0000000c +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x00000008 +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x00000004 +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x00000000 +#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L +#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x00000000 +#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7fffff00L +#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x00000008 +#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L +#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x00000004 +#define DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003ffL +#define DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x00000000 +#define DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000ffc00L +#define DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0x0000000a +#define DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3ff00000L +#define DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x00000014 +#define DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003ffL +#define DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x00000000 +#define DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000ffc00L +#define DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0x0000000a +#define DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3ff00000L +#define DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x00000014 +#define DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003ffL +#define DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x00000000 +#define DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000ffc00L +#define DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0x0000000a +#define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L +#define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x00000000 +#define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK 0xffffffffL +#define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT 0x00000000 +#define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK 0xffffffffL +#define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT 0x00000000 +#define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK 0xffffffffL +#define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT 0x00000000 +#define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK 0xffffffffL +#define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT 0x00000000 +#define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK 0xffffffffL +#define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT 0x00000000 +#define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK 0xffffffffL +#define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT 0x00000000 +#define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK 0xffffffffL +#define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT 0x00000000 +#define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK 0xffffffffL +#define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT 0x00000000 +#define DP_DTO4_MODULO__DP_DTO4_MODULO_MASK 0xffffffffL +#define DP_DTO4_MODULO__DP_DTO4_MODULO__SHIFT 0x00000000 +#define DP_DTO4_PHASE__DP_DTO4_PHASE_MASK 0xffffffffL +#define DP_DTO4_PHASE__DP_DTO4_PHASE__SHIFT 0x00000000 +#define DP_DTO5_MODULO__DP_DTO5_MODULO_MASK 0xffffffffL +#define DP_DTO5_MODULO__DP_DTO5_MODULO__SHIFT 0x00000000 +#define DP_DTO5_PHASE__DP_DTO5_PHASE_MASK 0xffffffffL +#define DP_DTO5_PHASE__DP_DTO5_PHASE__SHIFT 0x00000000 +#define DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xffff0000L +#define DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x00000010 +#define DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0x0000ffffL +#define DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x00000000 +#define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0x0000ffffL +#define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x00000000 +#define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xffff0000L +#define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x00000010 +#define DPG_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x00000001L +#define DPG_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x00000000 +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE_MASK 0x00000010L +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE__SHIFT 0x00000004 +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON_MASK 0x00000100L +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON__SHIFT 0x00000008 +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK 0xffff0000L +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK_MASK 0x00003000L +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK__SHIFT 0x0000000c +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK__SHIFT 0x00000010 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x00000400L +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0x0000000a +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK 0x00000001L +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT 0x00000000 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000200L +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x00000009 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x00000100L +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x00000008 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000010L +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x00000004 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xffff0000L +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x00000010 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x00000001L +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT 0x00000000 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x00000010L +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x00000004 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x00000080L +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x00000007 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x00000020L +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x00000005 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x00000040L +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x00000006 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x00000800L +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0x0000000b +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x00000400L +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0x0000000a +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK 0x00000200L +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT 0x00000009 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK 0x00000100L +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x00000008 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x00000001L +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x00000000 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xffff0000L +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x00000010 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x00000010L +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x00000004 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x00000080L +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x00000007 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x00000020L +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x00000005 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x00000040L +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x00000006 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x00000800L +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0x0000000b +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x00000400L +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0x0000000a +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK 0x00000200L +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT 0x00000009 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK 0x00000100L +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT 0x00000008 +#define DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xffff0000L +#define DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x00000010 +#define DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0x0000ffffL +#define DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x00000000 +#define DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA_MASK 0xffffffffL +#define DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L +#define DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x00000000 +#define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L +#define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x00000011 +#define DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L +#define DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x00000008 +#define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L +#define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x00000004 +#define DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003ffffL +#define DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x00000000 +#define DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L +#define DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x00000018 +#define DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L +#define DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x0000001c +#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK 0x00000100L +#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT 0x00000008 +#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK 0x000000ffL +#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT 0x00000000 +#define DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000f8L +#define DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x00000003 +#define DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000ff00L +#define DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x00000008 +#define DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00ff0000L +#define DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x00000010 +#define DP_MSA_MISC__DP_MSA_MISC4_MASK 0xff000000L +#define DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x00000018 +#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK 0x00000001L +#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT 0x00000000 +#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK 0x0001fff0L +#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT 0x00000004 +#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK 0x1fff0000L +#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT 0x00000010 +#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK 0x00001fffL +#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT 0x00000000 +#define DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003ffL +#define DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x00000000 +#define DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L +#define DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x00000010 +#define DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L +#define DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x00000000 +#define DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L +#define DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x00000004 +#define DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L +#define DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x00000008 +#define DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xfc000000L +#define DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x0000001a +#define DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03ffffffL +#define DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x00000000 +#define DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L +#define DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x00000000 +#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003f00L +#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x00000008 +#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3f000000L +#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x00000018 +#define DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L +#define DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x00000000 +#define DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L +#define DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x00000010 +#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003f00L +#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x00000008 +#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3f000000L +#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x00000018 +#define DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L +#define DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x00000000 +#define DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L +#define DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x00000010 +#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003f00L +#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x00000008 +#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3f000000L +#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x00000018 +#define DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L +#define DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x00000000 +#define DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L +#define DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x00000010 +#define DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L +#define DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x00000008 +#define DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L +#define DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x00000000 +#define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L +#define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x00000018 +#define DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK 0x00000100L +#define DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT 0x00000008 +#define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000003L +#define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x00000000 +#define DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK 0x00010000L +#define DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT 0x00000010 +#define DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00ffffffL +#define DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x00000000 +#define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00ffffffL +#define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x00000000 +#define DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00ffffffL +#define DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x00000000 +#define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00ffffffL +#define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x00000000 +#define DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L +#define DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x00000000 +#define DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L +#define DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x00000010 +#define DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L +#define DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0x0000000c +#define DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L +#define DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x00000004 +#define DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L +#define DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x00000008 +#define DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK 0x01000000L +#define DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT 0x00000018 +#define DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L +#define DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x00000014 +#define DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L +#define DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x00000015 +#define DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L +#define DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x00000016 +#define DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L +#define DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x00000017 +#define DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L +#define DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x0000001c +#define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L +#define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x00000000 +#define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000fffL +#define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x00000000 +#define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xffff0000L +#define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x00000010 +#define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xffff0000L +#define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x00000010 +#define DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000ffffL +#define DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x00000000 +#define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003fffL +#define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x00000000 +#define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xffff0000L +#define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x00000010 +#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L +#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x0000001c +#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L +#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x0000001d +#define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L +#define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x00000018 +#define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L +#define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x00000014 +#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L +#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x00000010 +#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000eL +#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x00000001 +#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L +#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x00000004 +#define DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003f00L +#define DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x00000008 +#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L +#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x00000000 +#define DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L +#define DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x00000000 +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x00000006 +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x00000004 +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x00000005 +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x00000007 +#define DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L +#define DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0x0000000c +#define DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L +#define DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x00000008 +#define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA_MASK 0xffffffffL +#define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L +#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x00000001 +#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L +#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x00000000 +#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L +#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x00000002 +#define DP_VID_M__DP_VID_M_MASK 0x00ffffffL +#define DP_VID_M__DP_VID_M__SHIFT 0x00000000 +#define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000fffL +#define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x00000000 +#define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK 0x00010000L +#define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT 0x00000010 +#define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L +#define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x00000018 +#define DP_VID_N__DP_VID_N_MASK 0x00ffffffL +#define DP_VID_N__DP_VID_N__SHIFT 0x00000000 +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x00000014 +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x00000008 +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x00000000 +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x00000010 +#define DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L +#define DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x00000008 +#define DP_VID_TIMING__DP_VID_N_DIV_MASK 0xff000000L +#define DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x00000018 +#define DP_VID_TIMING__DP_VID_TIMING_MODE_MASK 0x00000001L +#define DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT 0x00000000 +#define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN_MASK 0x00020000L +#define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN__SHIFT 0x00000011 +#define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL_MASK 0x00001f00L +#define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL__SHIFT 0x00000008 +#define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN_MASK 0x00010000L +#define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN__SHIFT 0x00000010 +#define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL_MASK 0x00000007L +#define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL__SHIFT 0x00000000 +#define DVOACLKC_CNTL__DVOACLKC_IN_PHASE_MASK 0x00040000L +#define DVOACLKC_CNTL__DVOACLKC_IN_PHASE__SHIFT 0x00000012 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN_MASK 0x00020000L +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN__SHIFT 0x00000011 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL_MASK 0x00001f00L +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL__SHIFT 0x00000008 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN_MASK 0x00010000L +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN__SHIFT 0x00000010 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL_MASK 0x00000007L +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL__SHIFT 0x00000000 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE_MASK 0x00040000L +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE__SHIFT 0x00000012 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_MASK 0x00100000L +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE__SHIFT 0x00000014 +#define DVOACLKC_MVP_CNTL__MVP_CLK_A_SRC_SEL_MASK 0x03000000L +#define DVOACLKC_MVP_CNTL__MVP_CLK_A_SRC_SEL__SHIFT 0x00000018 +#define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL_MASK 0x30000000L +#define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL__SHIFT 0x0000001c +#define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN_MASK 0x00020000L +#define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN__SHIFT 0x00000011 +#define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL_MASK 0x00001f00L +#define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL__SHIFT 0x00000008 +#define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN_MASK 0x00010000L +#define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN__SHIFT 0x00000010 +#define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL_MASK 0x00000007L +#define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL__SHIFT 0x00000000 +#define DVOACLKD_CNTL__DVOACLKD_IN_PHASE_MASK 0x00040000L +#define DVOACLKD_CNTL__DVOACLKD_IN_PHASE__SHIFT 0x00000012 +#define DVO_CLK_ENABLE__DVO_CLK_ENABLE_MASK 0x00000001L +#define DVO_CLK_ENABLE__DVO_CLK_ENABLE__SHIFT 0x00000000 +#define DVO_CONTROL__DVO_COLOR_FORMAT_MASK 0x03000000L +#define DVO_CONTROL__DVO_COLOR_FORMAT__SHIFT 0x00000018 +#define DVO_CONTROL__DVO_CTL3_MASK 0x80000000L +#define DVO_CONTROL__DVO_CTL3__SHIFT 0x0000001f +#define DVO_CONTROL__DVO_DUAL_CHANNEL_EN_MASK 0x00000100L +#define DVO_CONTROL__DVO_DUAL_CHANNEL_EN__SHIFT 0x00000008 +#define DVO_CONTROL__DVO_INVERT_DVOCLK_MASK 0x00040000L +#define DVO_CONTROL__DVO_INVERT_DVOCLK__SHIFT 0x00000012 +#define DVO_CONTROL__DVO_RATE_SELECT_MASK 0x00000001L +#define DVO_CONTROL__DVO_RATE_SELECT__SHIFT 0x00000000 +#define DVO_CONTROL__DVO_RESET_FIFO_MASK 0x00010000L +#define DVO_CONTROL__DVO_RESET_FIFO__SHIFT 0x00000010 +#define DVO_CONTROL__DVO_SDRCLK_SEL_MASK 0x00000002L +#define DVO_CONTROL__DVO_SDRCLK_SEL__SHIFT 0x00000001 +#define DVO_CONTROL__DVO_SYNC_PHASE_MASK 0x00020000L +#define DVO_CONTROL__DVO_SYNC_PHASE__SHIFT 0x00000011 +#define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK_MASK 0x07ffffffL +#define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK__SHIFT 0x00000000 +#define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT_MASK 0x07ffffffL +#define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT__SHIFT 0x00000000 +#define DVO_CRC_EN__DVO_CRC2_EN_MASK 0x00010000L +#define DVO_CRC_EN__DVO_CRC2_EN__SHIFT 0x00000010 +#define DVO_ENABLE__DVO_ENABLE_MASK 0x00000001L +#define DVO_ENABLE__DVO_ENABLE__SHIFT 0x00000000 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000fc00L +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x0000000a +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED_MASK 0x20000000L +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED__SHIFT 0x0000001d +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK_MASK 0x00000100L +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK__SHIFT 0x00000008 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x0000001e +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x0000001f +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR_MASK 0x00000001L +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR__SHIFT 0x00000000 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL_MASK 0x000f0000L +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL__SHIFT 0x00000010 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL_MASK 0x03c00000L +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL__SHIFT 0x00000016 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL_MASK 0x000000fcL +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL__SHIFT 0x00000002 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x00000001 +#define DVO_OUTPUT__DVO_CLOCK_MODE_MASK 0x00000100L +#define DVO_OUTPUT__DVO_CLOCK_MODE__SHIFT 0x00000008 +#define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE_MASK 0x00000003L +#define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE__SHIFT 0x00000000 +#define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST_MASK 0xffffffffL +#define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST__SHIFT 0x00000000 +#define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT_MASK 0x00000007L +#define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT__SHIFT 0x00000000 +#define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT_MASK 0x00070000L +#define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT__SHIFT 0x00000010 +#define DVO_STRENGTH_CONTROL__DVOCLK_SN_MASK 0x0000f000L +#define DVO_STRENGTH_CONTROL__DVOCLK_SN__SHIFT 0x0000000c +#define DVO_STRENGTH_CONTROL__DVOCLK_SP_MASK 0x00000f00L +#define DVO_STRENGTH_CONTROL__DVOCLK_SP__SHIFT 0x00000008 +#define DVO_STRENGTH_CONTROL__DVO_LSB_VMODE_MASK 0x10000000L +#define DVO_STRENGTH_CONTROL__DVO_LSB_VMODE__SHIFT 0x0000001c +#define DVO_STRENGTH_CONTROL__DVO_MSB_VMODE_MASK 0x20000000L +#define DVO_STRENGTH_CONTROL__DVO_MSB_VMODE__SHIFT 0x0000001d +#define DVO_STRENGTH_CONTROL__DVO_SN_MASK 0x000000f0L +#define DVO_STRENGTH_CONTROL__DVO_SN__SHIFT 0x00000004 +#define DVO_STRENGTH_CONTROL__DVO_SP_MASK 0x0000000fL +#define DVO_STRENGTH_CONTROL__DVO_SP__SHIFT 0x00000000 +#define DVO_VREF_CONTROL__DVO_VREFCAL_MASK 0x000000f0L +#define DVO_VREF_CONTROL__DVO_VREFCAL__SHIFT 0x00000004 +#define DVO_VREF_CONTROL__DVO_VREFPON_MASK 0x00000001L +#define DVO_VREF_CONTROL__DVO_VREFPON__SHIFT 0x00000000 +#define DVO_VREF_CONTROL__DVO_VREFSEL_MASK 0x00000002L +#define DVO_VREF_CONTROL__DVO_VREFSEL__SHIFT 0x00000001 +#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x0fff0000L +#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x00000010 +#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00000fffL +#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x00000000 +#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00000fffL +#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x00000000 +#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x0fff0000L +#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x00000010 +#define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK_MASK 0x000f0000L +#define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK__SHIFT 0x00000010 +#define FBC_CNTL__FBC_COHERENCY_MODE_MASK 0x00030000L +#define FBC_CNTL__FBC_COHERENCY_MODE__SHIFT 0x00000010 +#define FBC_CNTL__FBC_EN_MASK 0x80000000L +#define FBC_CNTL__FBC_EN__SHIFT 0x0000001f +#define FBC_CNTL__FBC_GRPH_COMP_EN_MASK 0x00000001L +#define FBC_CNTL__FBC_GRPH_COMP_EN__SHIFT 0x00000000 +#define FBC_CNTL__FBC_SOFT_COMPRESS_EN_MASK 0x02000000L +#define FBC_CNTL__FBC_SOFT_COMPRESS_EN__SHIFT 0x00000019 +#define FBC_CNTL__FBC_SRC_SEL_MASK 0x0000000eL +#define FBC_CNTL__FBC_SRC_SEL__SHIFT 0x00000001 +#define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN_MASK 0x00010000L +#define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN__SHIFT 0x00000010 +#define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN_MASK 0x00020000L +#define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN__SHIFT 0x00000011 +#define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN_MASK 0x00040000L +#define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN__SHIFT 0x00000012 +#define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN_MASK 0x00080000L +#define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN__SHIFT 0x00000013 +#define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN_MASK 0x00100000L +#define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN__SHIFT 0x00000014 +#define FBC_COMP_CNTL__FBC_MIN_COMPRESSION_MASK 0x0000000fL +#define FBC_COMP_CNTL__FBC_MIN_COMPRESSION__SHIFT 0x00000000 +#define FBC_COMP_MODE__FBC_DPCM4_RGB_EN_MASK 0x00000100L +#define FBC_COMP_MODE__FBC_DPCM4_RGB_EN__SHIFT 0x00000008 +#define FBC_COMP_MODE__FBC_DPCM4_YUV_EN_MASK 0x00000400L +#define FBC_COMP_MODE__FBC_DPCM4_YUV_EN__SHIFT 0x0000000a +#define FBC_COMP_MODE__FBC_DPCM8_RGB_EN_MASK 0x00000200L +#define FBC_COMP_MODE__FBC_DPCM8_RGB_EN__SHIFT 0x00000009 +#define FBC_COMP_MODE__FBC_DPCM8_YUV_EN_MASK 0x00000800L +#define FBC_COMP_MODE__FBC_DPCM8_YUV_EN__SHIFT 0x0000000b +#define FBC_COMP_MODE__FBC_IND_EN_MASK 0x00010000L +#define FBC_COMP_MODE__FBC_IND_EN__SHIFT 0x00000010 +#define FBC_COMP_MODE__FBC_RLE_EN_MASK 0x00000001L +#define FBC_COMP_MODE__FBC_RLE_EN__SHIFT 0x00000000 +#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0_MASK 0x000003ffL +#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0__SHIFT 0x00000000 +#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1_MASK 0x03ff0000L +#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1__SHIFT 0x00000010 +#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2_MASK 0x000003ffL +#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2__SHIFT 0x00000000 +#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3_MASK 0x03ff0000L +#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3__SHIFT 0x00000010 +#define FBC_DEBUG0__FBC_COMP_WAKE_DIS_MASK 0x00010000L +#define FBC_DEBUG0__FBC_COMP_WAKE_DIS__SHIFT 0x00000010 +#define FBC_DEBUG0__FBC_DEBUG0_MASK 0x00fe0000L +#define FBC_DEBUG0__FBC_DEBUG0__SHIFT 0x00000011 +#define FBC_DEBUG0__FBC_DEBUG_MUX_MASK 0xff000000L +#define FBC_DEBUG0__FBC_DEBUG_MUX__SHIFT 0x00000018 +#define FBC_DEBUG0__FBC_PERF_MUX0_MASK 0x000000ffL +#define FBC_DEBUG0__FBC_PERF_MUX0__SHIFT 0x00000000 +#define FBC_DEBUG0__FBC_PERF_MUX1_MASK 0x0000ff00L +#define FBC_DEBUG0__FBC_PERF_MUX1__SHIFT 0x00000008 +#define FBC_DEBUG1__FBC_DEBUG1_MASK 0xffffffffL +#define FBC_DEBUG1__FBC_DEBUG1__SHIFT 0x00000000 +#define FBC_DEBUG2__FBC_DEBUG2_MASK 0xffffffffL +#define FBC_DEBUG2__FBC_DEBUG2__SHIFT 0x00000000 +#define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE_MASK 0x00000800L +#define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x0000000b +#define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS_MASK 0x000000f0L +#define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS__SHIFT 0x00000004 +#define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL_MASK 0x00000300L +#define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL__SHIFT 0x00000008 +#define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE_MASK 0x00000400L +#define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x0000000a +#define FBC_DEBUG_COMP__FBC_COMP_RSIZE_MASK 0x00000008L +#define FBC_DEBUG_COMP__FBC_COMP_RSIZE__SHIFT 0x00000003 +#define FBC_DEBUG_COMP__FBC_COMP_SWAP_MASK 0x00000003L +#define FBC_DEBUG_COMP__FBC_COMP_SWAP__SHIFT 0x00000000 +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR_MASK 0x000003ffL +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR__SHIFT 0x00000000 +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN_MASK 0x80000000L +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN__SHIFT 0x0000001f +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_RD_DATA_MASK 0x00020000L +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_RD_DATA__SHIFT 0x00000011 +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_WR_DATA_MASK 0x00010000L +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_WR_DATA__SHIFT 0x00000010 +#define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA_MASK 0xffffffffL +#define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA__SHIFT 0x00000000 +#define FBC_DEBUG_CSR_RDATA_HI__FBC_DEBUG_CSR_RDATA_HI_MASK 0x000000ffL +#define FBC_DEBUG_CSR_RDATA_HI__FBC_DEBUG_CSR_RDATA_HI__SHIFT 0x00000000 +#define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA_MASK 0xffffffffL +#define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA__SHIFT 0x00000000 +#define FBC_DEBUG_CSR_WDATA_HI__FBC_DEBUG_CSR_WDATA_HI_MASK 0x000000ffL +#define FBC_DEBUG_CSR_WDATA_HI__FBC_DEBUG_CSR_WDATA_HI__SHIFT 0x00000000 +#define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK_MASK 0xffffffffL +#define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK__SHIFT 0x00000000 +#define FBC_IDLE_MASK__FBC_IDLE_MASK_MASK 0xffffffffL +#define FBC_IDLE_MASK__FBC_IDLE_MASK__SHIFT 0x00000000 +#define FBC_IND_LUT0__FBC_IND_LUT0_MASK 0x00ffffffL +#define FBC_IND_LUT0__FBC_IND_LUT0__SHIFT 0x00000000 +#define FBC_IND_LUT10__FBC_IND_LUT10_MASK 0x00ffffffL +#define FBC_IND_LUT10__FBC_IND_LUT10__SHIFT 0x00000000 +#define FBC_IND_LUT11__FBC_IND_LUT11_MASK 0x00ffffffL +#define FBC_IND_LUT11__FBC_IND_LUT11__SHIFT 0x00000000 +#define FBC_IND_LUT12__FBC_IND_LUT12_MASK 0x00ffffffL +#define FBC_IND_LUT12__FBC_IND_LUT12__SHIFT 0x00000000 +#define FBC_IND_LUT13__FBC_IND_LUT13_MASK 0x00ffffffL +#define FBC_IND_LUT13__FBC_IND_LUT13__SHIFT 0x00000000 +#define FBC_IND_LUT14__FBC_IND_LUT14_MASK 0x00ffffffL +#define FBC_IND_LUT14__FBC_IND_LUT14__SHIFT 0x00000000 +#define FBC_IND_LUT15__FBC_IND_LUT15_MASK 0x00ffffffL +#define FBC_IND_LUT15__FBC_IND_LUT15__SHIFT 0x00000000 +#define FBC_IND_LUT1__FBC_IND_LUT1_MASK 0x00ffffffL +#define FBC_IND_LUT1__FBC_IND_LUT1__SHIFT 0x00000000 +#define FBC_IND_LUT2__FBC_IND_LUT2_MASK 0x00ffffffL +#define FBC_IND_LUT2__FBC_IND_LUT2__SHIFT 0x00000000 +#define FBC_IND_LUT3__FBC_IND_LUT3_MASK 0x00ffffffL +#define FBC_IND_LUT3__FBC_IND_LUT3__SHIFT 0x00000000 +#define FBC_IND_LUT4__FBC_IND_LUT4_MASK 0x00ffffffL +#define FBC_IND_LUT4__FBC_IND_LUT4__SHIFT 0x00000000 +#define FBC_IND_LUT5__FBC_IND_LUT5_MASK 0x00ffffffL +#define FBC_IND_LUT5__FBC_IND_LUT5__SHIFT 0x00000000 +#define FBC_IND_LUT6__FBC_IND_LUT6_MASK 0x00ffffffL +#define FBC_IND_LUT6__FBC_IND_LUT6__SHIFT 0x00000000 +#define FBC_IND_LUT7__FBC_IND_LUT7_MASK 0x00ffffffL +#define FBC_IND_LUT7__FBC_IND_LUT7__SHIFT 0x00000000 +#define FBC_IND_LUT8__FBC_IND_LUT8_MASK 0x00ffffffL +#define FBC_IND_LUT8__FBC_IND_LUT8__SHIFT 0x00000000 +#define FBC_IND_LUT9__FBC_IND_LUT9_MASK 0x00ffffffL +#define FBC_IND_LUT9__FBC_IND_LUT9__SHIFT 0x00000000 +#define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR_MASK 0x00010000L +#define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR__SHIFT 0x00000010 +#define FBC_MISC__FBC_DECOMPRESS_ERROR_MASK 0x00000003L +#define FBC_MISC__FBC_DECOMPRESS_ERROR__SHIFT 0x00000000 +#define FBC_MISC__FBC_DIVIDE_X_MASK 0x00000300L +#define FBC_MISC__FBC_DIVIDE_X__SHIFT 0x00000008 +#define FBC_MISC__FBC_DIVIDE_Y_MASK 0x00000400L +#define FBC_MISC__FBC_DIVIDE_Y__SHIFT 0x0000000a +#define FBC_MISC__FBC_ERROR_PIXEL_MASK 0x000000f0L +#define FBC_MISC__FBC_ERROR_PIXEL__SHIFT 0x00000004 +#define FBC_MISC__FBC_INVALIDATE_ON_ERROR_MASK 0x00000008L +#define FBC_MISC__FBC_INVALIDATE_ON_ERROR__SHIFT 0x00000003 +#define FBC_MISC__FBC_RESET_AT_DISABLE_MASK 0x00200000L +#define FBC_MISC__FBC_RESET_AT_DISABLE__SHIFT 0x00000015 +#define FBC_MISC__FBC_RESET_AT_ENABLE_MASK 0x00100000L +#define FBC_MISC__FBC_RESET_AT_ENABLE__SHIFT 0x00000014 +#define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY_MASK 0x00001000L +#define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY__SHIFT 0x0000000c +#define FBC_MISC__FBC_RSM_WRITE_VALUE_MASK 0x00000800L +#define FBC_MISC__FBC_RSM_WRITE_VALUE__SHIFT 0x0000000b +#define FBC_MISC__FBC_SLOW_REQ_INTERVAL_MASK 0xf0000000L +#define FBC_MISC__FBC_SLOW_REQ_INTERVAL__SHIFT 0x0000001c +#define FBC_MISC__FBC_STOP_ON_ERROR_MASK 0x00000004L +#define FBC_MISC__FBC_STOP_ON_ERROR__SHIFT 0x00000002 +#define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY_MASK 0x00001f00L +#define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY__SHIFT 0x00000008 +#define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY_MASK 0x0000001fL +#define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY__SHIFT 0x00000000 +#define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY_MASK 0x00000080L +#define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY__SHIFT 0x00000007 +#define FBC_STATUS__FBC_ENABLE_STATUS_MASK 0x00000001L +#define FBC_STATUS__FBC_ENABLE_STATUS__SHIFT 0x00000000 +#define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA_MASK 0xffffffffL +#define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0c000000L +#define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x0000001a +#define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L +#define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x0000001c +#define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xc0000000L +#define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x0000001e +#define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L +#define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0x0000000d +#define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L +#define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0x0000000f +#define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L +#define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0x0000000e +#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001000L +#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0x0000000c +#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L +#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x00000008 +#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L +#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x00000009 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00100000L +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x00000014 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x00000010 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x00000015 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x00000019 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x00000018 +#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000010L +#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x00000004 +#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L +#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x00000000 +#define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L +#define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x00000010 +#define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L +#define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x00000000 +#define FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00010000L +#define FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x00000010 +#define FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L +#define FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x00000000 +#define FMT_CONTROL__FMT_STEREOSYNC_OVR_POL_MASK 0x00000010L +#define FMT_CONTROL__FMT_STEREOSYNC_OVR_POL__SHIFT 0x00000004 +#define FMT_CRC_CNTL__FMT_CRC_CONT_EN_MASK 0x00000010L +#define FMT_CRC_CNTL__FMT_CRC_CONT_EN__SHIFT 0x00000004 +#define FMT_CRC_CNTL__FMT_CRC_EN_MASK 0x00000001L +#define FMT_CRC_CNTL__FMT_CRC_EN__SHIFT 0x00000000 +#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE_MASK 0x00100000L +#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE__SHIFT 0x00000014 +#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT_MASK 0x01000000L +#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT__SHIFT 0x00000018 +#define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE_MASK 0x00003000L +#define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE__SHIFT 0x0000000c +#define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKb_MASK 0x00000100L +#define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKb__SHIFT 0x00000008 +#define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L +#define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x00000010 +#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE_MASK 0x0000ffffL +#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE__SHIFT 0x00000000 +#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL_MASK 0xffff0000L +#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL__SHIFT 0x00000010 +#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK_MASK 0x0000ffffL +#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK__SHIFT 0x00000000 +#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK_MASK 0xffff0000L +#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK__SHIFT 0x00000010 +#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN_MASK 0xffff0000L +#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN__SHIFT 0x00000010 +#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED_MASK 0x0000ffffL +#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED__SHIFT 0x00000000 +#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK_MASK 0xffff0000L +#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK__SHIFT 0x00000010 +#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK_MASK 0x0000ffffL +#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK__SHIFT 0x00000000 +#define FMT_DEBUG0__FMT_DEBUG0_MASK 0xffffffffL +#define FMT_DEBUG0__FMT_DEBUG0__SHIFT 0x00000000 +#define FMT_DEBUG1__FMT_DEBUG1_MASK 0xffffffffL +#define FMT_DEBUG1__FMT_DEBUG1__SHIFT 0x00000000 +#define FMT_DEBUG2__FMT_DEBUG2_MASK 0xffffffffL +#define FMT_DEBUG2__FMT_DEBUG2__SHIFT 0x00000000 +#define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT_MASK 0x00000003L +#define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT__SHIFT 0x00000000 +#define FMT_DEBUG_ID__FMT_DEBUG_ID_MASK 0xffffffffL +#define FMT_DEBUG_ID__FMT_DEBUG_ID__SHIFT 0x00000000 +#define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000ffL +#define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x00000000 +#define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000ffL +#define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x00000000 +#define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000ffL +#define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x00000000 +#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L +#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x00000000 +#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L +#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x00000004 +#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA0_MASK 0x0000ffffL +#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA0__SHIFT 0x00000000 +#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA1_MASK 0xffff0000L +#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA1__SHIFT 0x00000010 +#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA2_MASK 0x0000ffffL +#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA2__SHIFT 0x00000000 +#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA3_MASK 0xffff0000L +#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA3__SHIFT 0x00000010 +#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_EN_MASK 0x00000001L +#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_EN__SHIFT 0x00000000 +#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_ON_BLANKb_ONLY_MASK 0x00010000L +#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_ON_BLANKb_ONLY__SHIFT 0x00000010 +#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_COLOR_MASK 0x00000700L +#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_COLOR__SHIFT 0x00000008 +#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_SLOT_MASK 0x0000f000L +#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_SLOT__SHIFT 0x0000000c +#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0_MASK 0x00000010L +#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0__SHIFT 0x00000004 +#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT_MASK 0x00000001L +#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT__SHIFT 0x00000000 +#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX_MASK 0xffffffffL +#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SHIFT 0x00000000 +#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX_MASK 0xffffffffL +#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SHIFT 0x00000000 +#define FMT_TEST_DEBUG_DATA__FMT_TEST_DEBUG_DATA_MASK 0xffffffffL +#define FMT_TEST_DEBUG_DATA__FMT_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK 0x0000ffffL +#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT 0x00000000 +#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK 0xffff0000L +#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT 0x00000010 +#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK 0x0000ffffL +#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT 0x00000000 +#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK 0xffff0000L +#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT 0x00000010 +#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK 0x0000ffffL +#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT 0x00000000 +#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK 0xffff0000L +#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT 0x00000010 +#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK 0x0000ffffL +#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT 0x00000000 +#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK 0xffff0000L +#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT 0x00000010 +#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK 0x0000ffffL +#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT 0x00000000 +#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK 0xffff0000L +#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT 0x00000010 +#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK 0x0000ffffL +#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT 0x00000000 +#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK 0xffff0000L +#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT 0x00000010 +#define GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK 0x00000003L +#define GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT 0x00000000 +#define GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE_MASK 0x00000030L +#define GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT 0x00000004 +#define GENENB__BLK_IO_BASE_MASK 0x000000ffL +#define GENENB__BLK_IO_BASE__SHIFT 0x00000000 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL_MASK 0x80000000L +#define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL__SHIFT 0x0000001f +#define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE_MASK 0x00000008L +#define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE__SHIFT 0x00000003 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_GO_MASK 0x00000001L +#define GENERIC_I2C_CONTROL__GENERIC_I2C_GO__SHIFT 0x00000000 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET_MASK 0x00000004L +#define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET__SHIFT 0x00000002 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET_MASK 0x00000002L +#define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET__SHIFT 0x00000001 +#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_MASK 0x0000ff00L +#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW_MASK 0x00000001L +#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW__SHIFT 0x00000000 +#define GENERIC_I2C_DATA__GENERIC_I2C_DATA__SHIFT 0x00000008 +#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_MASK 0x000f0000L +#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX__SHIFT 0x00000010 +#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE_MASK 0x80000000L +#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE__SHIFT 0x0000001f +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK_MASK 0x00000002L +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK__SHIFT 0x00000001 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT_MASK 0x00000001L +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT__SHIFT 0x00000000 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK_MASK 0x00000004L +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK__SHIFT 0x00000002 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN_MASK 0x00000004L +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN__SHIFT 0x00000002 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT_MASK 0x00000002L +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT__SHIFT 0x00000001 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT_MASK 0x00000001L +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT__SHIFT 0x00000000 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN_MASK 0x00000040L +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN__SHIFT 0x00000006 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT_MASK 0x00000020L +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT__SHIFT 0x00000005 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT_MASK 0x00000010L +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT__SHIFT 0x00000004 +#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL_MASK 0x0000007fL +#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL__SHIFT 0x00000000 +#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL_MASK 0x00007f00L +#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL__SHIFT 0x00000008 +#define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN_MASK 0x00000080L +#define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN__SHIFT 0x00000007 +#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN_MASK 0x00000001L +#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN__SHIFT 0x00000000 +#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL_MASK 0x00000002L +#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL__SHIFT 0x00000001 +#define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY_MASK 0x0000ff00L +#define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY__SHIFT 0x00000008 +#define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT_MASK 0xff000000L +#define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT__SHIFT 0x00000018 +#define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 +#define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE_MASK 0xffff0000L +#define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE__SHIFT 0x00000010 +#define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD_MASK 0x00000003L +#define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD__SHIFT 0x00000000 +#define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED_MASK 0x00000020L +#define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED__SHIFT 0x00000005 +#define GENERIC_I2C_STATUS__GENERIC_I2C_DONE_MASK 0x00000010L +#define GENERIC_I2C_STATUS__GENERIC_I2C_DONE__SHIFT 0x00000004 +#define GENERIC_I2C_STATUS__GENERIC_I2C_NACK_MASK 0x00000400L +#define GENERIC_I2C_STATUS__GENERIC_I2C_NACK__SHIFT 0x0000000a +#define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS_MASK 0x0000000fL +#define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS__SHIFT 0x00000000 +#define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK_MASK 0x00000200L +#define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK__SHIFT 0x00000009 +#define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT_MASK 0x00000040L +#define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT__SHIFT 0x00000006 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ_MASK 0x00000200L +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ__SHIFT 0x00000009 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT_MASK 0x000f0000L +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT__SHIFT 0x00000010 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW_MASK 0x00000001L +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW__SHIFT 0x00000000 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START_MASK 0x00001000L +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START__SHIFT 0x0000000c +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_MASK 0x00002000L +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK_MASK 0x00000100L +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK__SHIFT 0x00000008 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP__SHIFT 0x0000000d +#define GENFC_RD__VSYNC_SEL_R_MASK 0x00000008L +#define GENFC_RD__VSYNC_SEL_R__SHIFT 0x00000003 +#define GENFC_WT__VSYNC_SEL_W_MASK 0x00000008L +#define GENFC_WT__VSYNC_SEL_W__SHIFT 0x00000003 +#define GENMO_RD__GENMO_MONO_ADDRESS_B_MASK 0x00000001L +#define GENMO_RD__GENMO_MONO_ADDRESS_B__SHIFT 0x00000000 +#define GENMO_RD__ODD_EVEN_MD_PGSEL_MASK 0x00000020L +#define GENMO_RD__ODD_EVEN_MD_PGSEL__SHIFT 0x00000005 +#define GENMO_RD__VGA_CKSEL_MASK 0x0000000cL +#define GENMO_RD__VGA_CKSEL__SHIFT 0x00000002 +#define GENMO_RD__VGA_HSYNC_POL_MASK 0x00000040L +#define GENMO_RD__VGA_HSYNC_POL__SHIFT 0x00000006 +#define GENMO_RD__VGA_RAM_EN_MASK 0x00000002L +#define GENMO_RD__VGA_RAM_EN__SHIFT 0x00000001 +#define GENMO_RD__VGA_VSYNC_POL_MASK 0x00000080L +#define GENMO_RD__VGA_VSYNC_POL__SHIFT 0x00000007 +#define GENMO_WT__GENMO_MONO_ADDRESS_B_MASK 0x00000001L +#define GENMO_WT__GENMO_MONO_ADDRESS_B__SHIFT 0x00000000 +#define GENMO_WT__ODD_EVEN_MD_PGSEL_MASK 0x00000020L +#define GENMO_WT__ODD_EVEN_MD_PGSEL__SHIFT 0x00000005 +#define GENMO_WT__VGA_CKSEL_MASK 0x0000000cL +#define GENMO_WT__VGA_CKSEL__SHIFT 0x00000002 +#define GENMO_WT__VGA_HSYNC_POL_MASK 0x00000040L +#define GENMO_WT__VGA_HSYNC_POL__SHIFT 0x00000006 +#define GENMO_WT__VGA_RAM_EN_MASK 0x00000002L +#define GENMO_WT__VGA_RAM_EN__SHIFT 0x00000001 +#define GENMO_WT__VGA_VSYNC_POL_MASK 0x00000080L +#define GENMO_WT__VGA_VSYNC_POL__SHIFT 0x00000007 +#define GENS0__CRT_INTR_MASK 0x00000080L +#define GENS0__CRT_INTR__SHIFT 0x00000007 +#define GENS0__SENSE_SWITCH_MASK 0x00000010L +#define GENS0__SENSE_SWITCH__SHIFT 0x00000004 +#define GENS1__NO_DISPLAY_MASK 0x00000001L +#define GENS1__NO_DISPLAY__SHIFT 0x00000000 +#define GENS1__PIXEL_READ_BACK_MASK 0x00000030L +#define GENS1__PIXEL_READ_BACK__SHIFT 0x00000004 +#define GENS1__VGA_VSTATUS_MASK 0x00000008L +#define GENS1__VGA_VSTATUS__SHIFT 0x00000003 +#define GRA00__GRPH_SET_RESET0_MASK 0x00000001L +#define GRA00__GRPH_SET_RESET0__SHIFT 0x00000000 +#define GRA00__GRPH_SET_RESET1_MASK 0x00000002L +#define GRA00__GRPH_SET_RESET1__SHIFT 0x00000001 +#define GRA00__GRPH_SET_RESET2_MASK 0x00000004L +#define GRA00__GRPH_SET_RESET2__SHIFT 0x00000002 +#define GRA00__GRPH_SET_RESET3_MASK 0x00000008L +#define GRA00__GRPH_SET_RESET3__SHIFT 0x00000003 +#define GRA01__GRPH_SET_RESET_ENA0_MASK 0x00000001L +#define GRA01__GRPH_SET_RESET_ENA0__SHIFT 0x00000000 +#define GRA01__GRPH_SET_RESET_ENA1_MASK 0x00000002L +#define GRA01__GRPH_SET_RESET_ENA1__SHIFT 0x00000001 +#define GRA01__GRPH_SET_RESET_ENA2_MASK 0x00000004L +#define GRA01__GRPH_SET_RESET_ENA2__SHIFT 0x00000002 +#define GRA01__GRPH_SET_RESET_ENA3_MASK 0x00000008L +#define GRA01__GRPH_SET_RESET_ENA3__SHIFT 0x00000003 +#define GRA02__GRPH_CCOMP_MASK 0x0000000fL +#define GRA02__GRPH_CCOMP__SHIFT 0x00000000 +#define GRA03__GRPH_FN_SEL_MASK 0x00000018L +#define GRA03__GRPH_FN_SEL__SHIFT 0x00000003 +#define GRA03__GRPH_ROTATE_MASK 0x00000007L +#define GRA03__GRPH_ROTATE__SHIFT 0x00000000 +#define GRA04__GRPH_RMAP_MASK 0x00000003L +#define GRA04__GRPH_RMAP__SHIFT 0x00000000 +#define GRA05__CGA_ODDEVEN_MASK 0x00000010L +#define GRA05__CGA_ODDEVEN__SHIFT 0x00000004 +#define GRA05__GRPH_OES_MASK 0x00000020L +#define GRA05__GRPH_OES__SHIFT 0x00000005 +#define GRA05__GRPH_PACK_MASK 0x00000040L +#define GRA05__GRPH_PACK__SHIFT 0x00000006 +#define GRA05__GRPH_READ1_MASK 0x00000008L +#define GRA05__GRPH_READ1__SHIFT 0x00000003 +#define GRA05__GRPH_WRITE_MODE_MASK 0x00000003L +#define GRA05__GRPH_WRITE_MODE__SHIFT 0x00000000 +#define GRA06__GRPH_ADRSEL_MASK 0x0000000cL +#define GRA06__GRPH_ADRSEL__SHIFT 0x00000002 +#define GRA06__GRPH_GRAPHICS_MASK 0x00000001L +#define GRA06__GRPH_GRAPHICS__SHIFT 0x00000000 +#define GRA06__GRPH_ODDEVEN_MASK 0x00000002L +#define GRA06__GRPH_ODDEVEN__SHIFT 0x00000001 +#define GRA07__GRPH_XCARE0_MASK 0x00000001L +#define GRA07__GRPH_XCARE0__SHIFT 0x00000000 +#define GRA07__GRPH_XCARE1_MASK 0x00000002L +#define GRA07__GRPH_XCARE1__SHIFT 0x00000001 +#define GRA07__GRPH_XCARE2_MASK 0x00000004L +#define GRA07__GRPH_XCARE2__SHIFT 0x00000002 +#define GRA07__GRPH_XCARE3_MASK 0x00000008L +#define GRA07__GRPH_XCARE3__SHIFT 0x00000003 +#define GRA08__GRPH_BMSK_MASK 0x000000ffL +#define GRA08__GRPH_BMSK__SHIFT 0x00000000 +#define GRPH8_DATA__GRPH_DATA_MASK 0x000000ffL +#define GRPH8_DATA__GRPH_DATA__SHIFT 0x00000000 +#define GRPH8_IDX__GRPH_IDX_MASK 0x0000000fL +#define GRPH8_IDX__GRPH_IDX__SHIFT 0x00000000 +#define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK 0x0001ffc0L +#define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT 0x00000006 +#define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK 0xffffff00L +#define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT 0x00000008 +#define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK 0x000000ffL +#define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT 0x00000000 +#define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x00010000L +#define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x00000010 +#define GRPH_CONTROL__GRPH_ARRAY_MODE_MASK 0x00f00000L +#define GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT 0x00000014 +#define GRPH_CONTROL__GRPH_BANK_HEIGHT_MASK 0x00001800L +#define GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT 0x0000000b +#define GRPH_CONTROL__GRPH_BANK_WIDTH_MASK 0x000000c0L +#define GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT 0x00000006 +#define GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000L +#define GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x0000001f +#define GRPH_CONTROL__GRPH_DEPTH_MASK 0x00000003L +#define GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x00000000 +#define GRPH_CONTROL__GRPH_FORMAT_MASK 0x00000700L +#define GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x00000008 +#define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_MASK 0x000c0000L +#define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT 0x00000012 +#define GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0x0000000cL +#define GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0x00000002 +#define GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK 0x1f000000L +#define GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT 0x00000018 +#define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x00020000L +#define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x00000011 +#define GRPH_CONTROL__GRPH_TILE_SPLIT_MASK 0x0000e000L +#define GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT 0x0000000d +#define GRPH_CONTROL__GRPH_Z_MASK 0x00000030L +#define GRPH_CONTROL__GRPH_Z__SHIFT 0x00000004 +#define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK 0x00000700L +#define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT 0x00000008 +#define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK 0x00000001L +#define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT 0x00000000 +#define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK 0x00000070L +#define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT 0x00000004 +#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK 0x00000200L +#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT 0x00000009 +#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK 0x00000100L +#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT 0x00000008 +#define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK 0x0000000fL +#define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT 0x00000000 +#define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK 0x000000f0L +#define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x00000004 +#define GRPH_ENABLE__GRPH_ENABLE_MASK 0x00000001L +#define GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x00000000 +#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK 0x00000001L +#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT 0x00000000 +#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x00000001L +#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x00000000 +#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x00000100L +#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x00000008 +#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x00000100L +#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x00000008 +#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x00000001L +#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x00000000 +#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x00010000L +#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x00000010 +#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK 0x00000100L +#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT 0x00000008 +#define GRPH_PITCH__GRPH_PITCH_MASK 0x00007fffL +#define GRPH_PITCH__GRPH_PITCH__SHIFT 0x00000000 +#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK 0x00000001L +#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT 0x00000000 +#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK 0xffffff00L +#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT 0x00000008 +#define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x000000ffL +#define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x00000000 +#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK 0x00000001L +#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT 0x00000000 +#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK 0xffffff00L +#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT 0x00000008 +#define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x000000ffL +#define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x00000000 +#define GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x00010000L +#define GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x00000010 +#define GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x00020000L +#define GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x00000011 +#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x00000001L +#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x00000000 +#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x00000300L +#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x00000008 +#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000L +#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x0000001c +#define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK 0x000000ffL +#define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x00000000 +#define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK 0xffffff00L +#define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT 0x00000008 +#define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK 0x00003fffL +#define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT 0x00000000 +#define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK 0x00003fffL +#define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT 0x00000000 +#define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK 0x00000c00L +#define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT 0x0000000a +#define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x00000300L +#define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x00000008 +#define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x00000003L +#define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x00000000 +#define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0x000000c0L +#define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x00000006 +#define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x00000030L +#define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x00000004 +#define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L +#define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x00000018 +#define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x00000001L +#define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x00000000 +#define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x00000002L +#define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x00000001 +#define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000L +#define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x0000001c +#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x00000004L +#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x00000002 +#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x00000008L +#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x00000003 +#define GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE_MASK 0x00000100L +#define GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE__SHIFT 0x00000008 +#define GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x00010000L +#define GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x00000010 +#define GRPH_X_END__GRPH_X_END_MASK 0x00007fffL +#define GRPH_X_END__GRPH_X_END__SHIFT 0x00000000 +#define GRPH_X_START__GRPH_X_START_MASK 0x00003fffL +#define GRPH_X_START__GRPH_X_START__SHIFT 0x00000000 +#define GRPH_Y_END__GRPH_Y_END_MASK 0x00007fffL +#define GRPH_Y_END__GRPH_Y_END__SHIFT 0x00000000 +#define GRPH_Y_START__GRPH_Y_START_MASK 0x00003fffL +#define GRPH_Y_START__GRPH_Y_START__SHIFT 0x00000000 +#define HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xfffff000L +#define HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0x0000000c +#define HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000fffffL +#define HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x00000000 +#define HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xfffff000L +#define HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0x0000000c +#define HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000fffffL +#define HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x00000000 +#define HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xfffff000L +#define HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0x0000000c +#define HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000fffffL +#define HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x00000000 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x0000001f +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0x0000000c +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x00000001 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x00000010 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x00000004 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x00000000 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x00000008 +#define HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xfffff000L +#define HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0x0000000c +#define HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000fffffL +#define HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x00000000 +#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L +#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x00000004 +#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001f0000L +#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x00000010 +#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x00000100L +#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x00000008 +#define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L +#define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x0000001c +#define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L +#define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x00000018 +#define HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L +#define HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x00000008 +#define HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L +#define HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x00000009 +#define HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L +#define HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x00000000 +#define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L +#define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x00000004 +#define HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L +#define HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x00000004 +#define HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x00000002 +#define HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L +#define HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x00000000 +#define HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000f00L +#define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L +#define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0x0000000c +#define HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x00000008 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x00000001 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x003f0000L +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x00000010 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x00000000 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x00000005 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3f000000L +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x00000018 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x00000004 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x00000002L +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x00000001 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x003f0000L +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x00000010 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x00000001L +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x00000000 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x00000020L +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x00000005 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3f000000L +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x00000018 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x00000010L +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x00000004 +#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L +#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x00000005 +#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L +#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x00000004 +#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK 0x00000002L +#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT 0x00000001 +#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x00000001L +#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT 0x00000000 +#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L +#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x00000009 +#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L +#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x00000008 +#define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003f00L +#define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x00000008 +#define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK 0x0000003fL +#define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT 0x00000000 +#define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003f0000L +#define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x00000010 +#define HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L +#define HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x00000000 +#define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L +#define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x00000010 +#define HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L +#define HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x0000001b +#define HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L +#define HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x00000014 +#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L +#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x00000005 +#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L +#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x00000004 +#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L +#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x00000009 +#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003f0000L +#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x00000010 +#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L +#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x00000008 +#define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L +#define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x00000000 +#define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C_MASK 0xffffffffL +#define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT 0x00000000 +#define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E_MASK 0xffffffffL +#define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E__SHIFT 0x00000000 +#define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F_MASK 0xffffffffL +#define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F__SHIFT 0x00000000 +#define INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK 0x0000ffffL +#define INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT 0x00000000 +#define INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK 0xffff0000L +#define INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT 0x00000010 +#define INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK 0x0000ffffL +#define INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT 0x00000000 +#define INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK 0xffff0000L +#define INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT 0x00000010 +#define INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK 0x0000ffffL +#define INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT 0x00000000 +#define INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK 0xffff0000L +#define INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT 0x00000010 +#define INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK 0x0000ffffL +#define INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT 0x00000000 +#define INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK 0xffff0000L +#define INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT 0x00000010 +#define INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK 0x0000ffffL +#define INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT 0x00000000 +#define INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK 0xffff0000L +#define INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT 0x00000010 +#define INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK 0x0000ffffL +#define INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT 0x00000000 +#define INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK 0xffff0000L +#define INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT 0x00000010 +#define INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK 0x00000003L +#define INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT 0x00000000 +#define INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE_MASK 0x00000030L +#define INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT 0x00000004 +#define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK 0x00000003L +#define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT 0x00000000 +#define INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE_MASK 0x00000030L +#define INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT 0x00000004 +#define KEY_CONTROL__GRPH_OVL_HALF_BLEND_MASK 0x10000000L +#define KEY_CONTROL__GRPH_OVL_HALF_BLEND__SHIFT 0x0000001c +#define KEY_CONTROL__KEY_MODE_MASK 0x00000006L +#define KEY_CONTROL__KEY_MODE__SHIFT 0x00000001 +#define KEY_CONTROL__KEY_SELECT_MASK 0x00000001L +#define KEY_CONTROL__KEY_SELECT__SHIFT 0x00000000 +#define KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK 0xffff0000L +#define KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT 0x00000010 +#define KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK 0x0000ffffL +#define KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT 0x00000000 +#define KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK 0xffff0000L +#define KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT 0x00000010 +#define KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK 0x0000ffffL +#define KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT 0x00000000 +#define KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK 0xffff0000L +#define KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT 0x00000010 +#define KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK 0x0000ffffL +#define KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT 0x00000000 +#define KEY_RANGE_RED__KEY_RED_HIGH_MASK 0xffff0000L +#define KEY_RANGE_RED__KEY_RED_HIGH__SHIFT 0x00000010 +#define KEY_RANGE_RED__KEY_RED_LOW_MASK 0x0000ffffL +#define KEY_RANGE_RED__KEY_RED_LOW__SHIFT 0x00000000 +#define LB_DEBUG2__LB_DEBUG2_MASK 0xffffffffL +#define LB_DEBUG2__LB_DEBUG2__SHIFT 0x00000000 +#define LB_DEBUG__LB_DEBUG_MASK 0xffffffffL +#define LB_DEBUG__LB_DEBUG__SHIFT 0x00000000 +#define LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x00000001L +#define LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x00000000 +#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x00000010L +#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x00000004 +#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x00000003L +#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x00000000 +#define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA_MASK 0xffffffffL +#define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define LIGHT_SLEEP_CNTL__LIGHT_SLEEP_DIS_MASK 0x00000001L +#define LIGHT_SLEEP_CNTL__LIGHT_SLEEP_DIS__SHIFT 0x00000000 +#define LIGHT_SLEEP_CNTL__MEM_SHUTDOWN_DIS_MASK 0x00000100L +#define LIGHT_SLEEP_CNTL__MEM_SHUTDOWN_DIS__SHIFT 0x00000008 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE_MASK 0x00000001L +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE__SHIFT 0x00000000 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE_MASK 0x00000018L +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE__SHIFT 0x00000003 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS_MASK 0x00000700L +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS__SHIFT 0x00000008 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES_MASK 0x000000e0L +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES__SHIFT 0x00000005 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE_MASK 0x00000800L +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE__SHIFT 0x0000000b +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE_MASK 0x00007000L +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE__SHIFT 0x0000000c +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN_MASK 0x0fff0000L +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN__SHIFT 0x00000010 +#define LVDS_DATA_CNTL__LVDS_24BIT_ENABLE_MASK 0x00000001L +#define LVDS_DATA_CNTL__LVDS_24BIT_ENABLE__SHIFT 0x00000000 +#define LVDS_DATA_CNTL__LVDS_24BIT_FORMAT_MASK 0x00000010L +#define LVDS_DATA_CNTL__LVDS_24BIT_FORMAT__SHIFT 0x00000004 +#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_DE_MASK 0x00000100L +#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_DE__SHIFT 0x00000008 +#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_HS_MASK 0x00000400L +#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_HS__SHIFT 0x0000000a +#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_VS_MASK 0x00000200L +#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_VS__SHIFT 0x00000009 +#define LVDS_DATA_CNTL__LVDS_2ND_LINK_CNTL_BITS_MASK 0x00007000L +#define LVDS_DATA_CNTL__LVDS_2ND_LINK_CNTL_BITS__SHIFT 0x0000000c +#define LVDS_DATA_CNTL__LVDS_DTMG_POL_MASK 0x00040000L +#define LVDS_DATA_CNTL__LVDS_DTMG_POL__SHIFT 0x00000012 +#define LVDS_DATA_CNTL__LVDS_FP_POL_MASK 0x00010000L +#define LVDS_DATA_CNTL__LVDS_FP_POL__SHIFT 0x00000010 +#define LVDS_DATA_CNTL__LVDS_LP_POL_MASK 0x00020000L +#define LVDS_DATA_CNTL__LVDS_LP_POL__SHIFT 0x00000011 +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_MASK 0x01000000L +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD_MASK 0x02000000L +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT 0x00000019 +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL_MASK 0x04000000L +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL__SHIFT 0x0000001a +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT 0x00000018 +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_MASK 0x00010000L +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD_MASK 0x00020000L +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x00000011 +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL_MASK 0x00040000L +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT 0x00000012 +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT 0x00000010 +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN_MASK 0x00000002L +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN__SHIFT 0x00000001 +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN_MASK 0x00000001L +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN__SHIFT 0x00000000 +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE_MASK 0x00000010L +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE__SHIFT 0x00000004 +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK 0x00000100L +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD_MASK 0x00000200L +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD__SHIFT 0x00000009 +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK 0x00000400L +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT 0x0000000a +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT 0x00000008 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1_MASK 0x00ff0000L +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1__SHIFT 0x00000010 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2_MASK 0xff000000L +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2__SHIFT 0x00000018 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1_MASK 0x000000ffL +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1__SHIFT 0x00000000 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2_MASK 0x0000ff00L +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2__SHIFT 0x00000008 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3_MASK 0x00ff0000L +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3__SHIFT 0x00000010 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH_MASK 0x000000ffL +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH__SHIFT 0x00000000 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3_MASK 0x0000ff00L +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3__SHIFT 0x00000008 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN_MASK 0x01000000L +#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN__SHIFT 0x00000018 +#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK 0xffff0000L +#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT 0x00000010 +#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV_MASK 0x00000fffL +#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV__SHIFT 0x00000000 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON_MASK 0x00000008L +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON__SHIFT 0x00000003 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK 0x00000002L +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON__SHIFT 0x00000001 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE_MASK 0x00000010L +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE__SHIFT 0x00000004 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE_MASK 0x00000f00L +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT 0x00000008 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN_MASK 0x00000004L +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN__SHIFT 0x00000002 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R_MASK 0x00000001L +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R__SHIFT 0x00000000 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0_MASK 0x000000ffL +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0__SHIFT 0x00000000 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1_MASK 0x0000ff00L +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1__SHIFT 0x00000008 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2_MASK 0x00ff0000L +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT 0x00000010 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3_MASK 0xff000000L +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT 0x00000018 +#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x00000001L +#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT 0x00000000 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0_MASK 0x000000ffL +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0__SHIFT 0x00000000 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1_MASK 0x0000ff00L +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1__SHIFT 0x00000008 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2_MASK 0x00ff0000L +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2__SHIFT 0x00000010 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3_MASK 0xff000000L +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3__SHIFT 0x00000018 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0_MASK 0x000000ffL +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0__SHIFT 0x00000000 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1_MASK 0x0000ff00L +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1__SHIFT 0x00000008 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2_MASK 0x00ff0000L +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2__SHIFT 0x00000010 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3_MASK 0xff000000L +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3__SHIFT 0x00000018 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0_MASK 0x000000ffL +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0__SHIFT 0x00000000 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1_MASK 0x0000ff00L +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1__SHIFT 0x00000008 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2_MASK 0x00ff0000L +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2__SHIFT 0x00000010 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3_MASK 0xff000000L +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3__SHIFT 0x00000018 +#define MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x00000100L +#define MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x00000008 +#define MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x00000001L +#define MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x00000000 +#define MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00030000L +#define MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x00000010 +#define MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x00000007L +#define MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x00000000 +#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR_MASK 0x00000010L +#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR__SHIFT 0x00000004 +#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED_MASK 0x00000001L +#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED__SHIFT 0x00000000 +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR_MASK 0x00100000L +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR__SHIFT 0x00000014 +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED_MASK 0x00010000L +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED__SHIFT 0x00000010 +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR_MASK 0x10000000L +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR__SHIFT 0x0000001c +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED_MASK 0x01000000L +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED__SHIFT 0x00000018 +#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR_MASK 0x00001000L +#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR__SHIFT 0x0000000c +#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED_MASK 0x00000100L +#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED__SHIFT 0x00000008 +#define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE_MASK 0x00000010L +#define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE__SHIFT 0x00000004 +#define MCIF_CONTROL__LOW_READ_URG_LEVEL_MASK 0x00ff0000L +#define MCIF_CONTROL__LOW_READ_URG_LEVEL__SHIFT 0x00000010 +#define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY_MASK 0x3f000000L +#define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY__SHIFT 0x00000018 +#define MCIF_CONTROL__MCIF_BUFF_SIZE_MASK 0x00000003L +#define MCIF_CONTROL__MCIF_BUFF_SIZE__SHIFT 0x00000000 +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x40000000L +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x0000001e +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x80000000L +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x0000001f +#define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL_MASK 0x0000f000L +#define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL__SHIFT 0x0000000c +#define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE_MASK 0x00000100L +#define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE__SHIFT 0x00000008 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS_MASK 0x00000001L +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS__SHIFT 0x00000000 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_MASK 0x00000030L +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE__SHIFT 0x00000004 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE_MASK 0x00070000L +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE__SHIFT 0x00000010 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE_MASK 0x00007f00L +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE__SHIFT 0x00000008 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE_MASK 0x00180000L +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE__SHIFT 0x00000013 +#define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA_MASK 0xffffffffL +#define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define MCIF_VMID__MCIF_WR_VMID_MASK 0x0000000fL +#define MCIF_VMID__MCIF_WR_VMID__SHIFT 0x00000000 +#define MCIF_VMID__VIP_WR_VMID_MASK 0x000000f0L +#define MCIF_VMID__VIP_WR_VMID__SHIFT 0x00000004 +#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT_MASK 0x000000ffL +#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT__SHIFT 0x00000000 +#define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT_MASK 0x0000ff00L +#define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT__SHIFT 0x00000008 +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x00100000L +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x00000014 +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK 0x0000007fL +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT 0x00000000 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK 0x00020000L +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT 0x00000011 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK 0x00007f00L +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 0x00000008 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK 0x00010000L +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT 0x00000010 +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x00100000L +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x00000014 +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK 0x0001ffffL +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT 0x00000000 +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES_MASK 0x0000000fL +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES__SHIFT 0x00000000 +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK_MASK 0x00001000L +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK__SHIFT 0x0000000c +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG_MASK 0x00000100L +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG__SHIFT 0x00000008 +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_MASK 0x00000010L +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET__SHIFT 0x00000004 +#define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE_MASK 0x00000003L +#define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE__SHIFT 0x00000000 +#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B_MASK 0x3ff00000L +#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B__SHIFT 0x00000014 +#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G_MASK 0x000ffc00L +#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G__SHIFT 0x0000000a +#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R_MASK 0x000003ffL +#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R__SHIFT 0x00000000 +#define MVP_CONTROL1__MVP_30BPP_EN_MASK 0x10000000L +#define MVP_CONTROL1__MVP_30BPP_EN__SHIFT 0x0000001c +#define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE_MASK 0x00000400L +#define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE__SHIFT 0x0000000a +#define MVP_CONTROL1__MVP_CHANNEL_CONTROL_MASK 0x00010000L +#define MVP_CONTROL1__MVP_CHANNEL_CONTROL__SHIFT 0x00000010 +#define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND_MASK 0x01000000L +#define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND__SHIFT 0x00000018 +#define MVP_CONTROL1__MVP_EN_MASK 0x00000001L +#define MVP_CONTROL1__MVP_EN__SHIFT 0x00000000 +#define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION_MASK 0x00300000L +#define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION__SHIFT 0x00000014 +#define MVP_CONTROL1__MVP_MIXER_MODE_MASK 0x00000070L +#define MVP_CONTROL1__MVP_MIXER_MODE__SHIFT 0x00000004 +#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK_MASK 0x00000200L +#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK__SHIFT 0x00000009 +#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_MASK 0x00000100L +#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL__SHIFT 0x00000008 +#define MVP_CONTROL1__MVP_RATE_CONTROL_MASK 0x00001000L +#define MVP_CONTROL1__MVP_RATE_CONTROL__SHIFT 0x0000000c +#define MVP_CONTROL1__MVP_TERMINATION_CNTL_A_MASK 0x40000000L +#define MVP_CONTROL1__MVP_TERMINATION_CNTL_A__SHIFT 0x0000001e +#define MVP_CONTROL1__MVP_TERMINATION_CNTL_B_MASK 0x80000000L +#define MVP_CONTROL1__MVP_TERMINATION_CNTL_B__SHIFT 0x0000001f +#define MVP_CONTROL2__MVP_DVOCNTL_MUX_MASK 0x00010000L +#define MVP_CONTROL2__MVP_DVOCNTL_MUX__SHIFT 0x00000010 +#define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN_MASK 0x00100000L +#define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN__SHIFT 0x00000014 +#define MVP_CONTROL2__MVP_MUXA_CLK_SEL_MASK 0x00000100L +#define MVP_CONTROL2__MVP_MUXA_CLK_SEL__SHIFT 0x00000008 +#define MVP_CONTROL2__MVP_MUXB_CLK_SEL_MASK 0x00001000L +#define MVP_CONTROL2__MVP_MUXB_CLK_SEL__SHIFT 0x0000000c +#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL_MASK 0x00000001L +#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL__SHIFT 0x00000000 +#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL_MASK 0x00000010L +#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL__SHIFT 0x00000004 +#define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR_MASK 0x10000000L +#define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR__SHIFT 0x0000001c +#define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN_MASK 0x01000000L +#define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN__SHIFT 0x00000018 +#define MVP_CONTROL3__MVP_DDR_SC_AB_SEL_MASK 0x00000010L +#define MVP_CONTROL3__MVP_DDR_SC_AB_SEL__SHIFT 0x00000004 +#define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE_MASK 0x00000100L +#define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE__SHIFT 0x00000008 +#define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN_MASK 0x00100000L +#define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN__SHIFT 0x00000014 +#define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP_MASK 0x10000000L +#define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP__SHIFT 0x0000001c +#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE_MASK 0x00001000L +#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE__SHIFT 0x0000000c +#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO_MASK 0x00010000L +#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO__SHIFT 0x00000010 +#define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES_MASK 0x00000001L +#define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES__SHIFT 0x00000000 +#define MVP_CONTROL3__MVP_SWAP_48BIT_EN_MASK 0x01000000L +#define MVP_CONTROL3__MVP_SWAP_48BIT_EN__SHIFT 0x00000018 +#define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK_MASK 0x000000ffL +#define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK__SHIFT 0x00000000 +#define MVP_CRC_CNTL__MVP_CRC_CONT_EN_MASK 0x20000000L +#define MVP_CRC_CNTL__MVP_CRC_CONT_EN__SHIFT 0x0000001d +#define MVP_CRC_CNTL__MVP_CRC_EN_MASK 0x10000000L +#define MVP_CRC_CNTL__MVP_CRC_EN__SHIFT 0x0000001c +#define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK_MASK 0x0000ff00L +#define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK__SHIFT 0x00000008 +#define MVP_CRC_CNTL__MVP_CRC_RED_MASK_MASK 0x00ff0000L +#define MVP_CRC_CNTL__MVP_CRC_RED_MASK__SHIFT 0x00000010 +#define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL_MASK 0x40000000L +#define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL__SHIFT 0x0000001e +#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT_MASK 0x0000ffffL +#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT__SHIFT 0x00000000 +#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT_MASK 0xffff0000L +#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT__SHIFT 0x00000010 +#define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT_MASK 0x0000ffffL +#define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT__SHIFT 0x00000000 +#define MVP_DEBUG_05__IDE0_MVP_GPU_CHAIN_LOCATION_MASK 0x00000006L +#define MVP_DEBUG_05__IDE0_MVP_GPU_CHAIN_LOCATION__SHIFT 0x00000001 +#define MVP_DEBUG_09__IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION_MASK 0x00000006L +#define MVP_DEBUG_09__IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION__SHIFT 0x00000001 +#define MVP_DEBUG_12__IDEC_MVP_DATA_A_H_MASK 0x00000001L +#define MVP_DEBUG_12__IDEC_MVP_DATA_A_H__SHIFT 0x00000000 +#define MVP_DEBUG_12__IDEC_MVP_DATA_A_MASK 0x01fffffeL +#define MVP_DEBUG_12__IDEC_MVP_DATA_A__SHIFT 0x00000001 +#define MVP_DEBUG_13__IDED_MVP_DATA_B_H_MASK 0x00000001L +#define MVP_DEBUG_13__IDED_MVP_DATA_B_H__SHIFT 0x00000000 +#define MVP_DEBUG_13__IDED_MVP_DATA_B_MASK 0x01fffffeL +#define MVP_DEBUG_13__IDED_MVP_DATA_B__SHIFT 0x00000001 +#define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B_MASK 0x04000000L +#define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B__SHIFT 0x0000001a +#define MVP_DEBUG_13__IDED_START_READ_B_MASK 0x02000000L +#define MVP_DEBUG_13__IDED_START_READ_B__SHIFT 0x00000019 +#define MVP_DEBUG_13__IDED_WRITE_ADD_B_MASK 0x38000000L +#define MVP_DEBUG_13__IDED_WRITE_ADD_B__SHIFT 0x0000001b +#define MVP_DEBUG_14__IDEE_CRC_PHASE_MASK 0x00100000L +#define MVP_DEBUG_14__IDEE_CRC_PHASE__SHIFT 0x00000014 +#define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A_MASK 0x00080000L +#define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A__SHIFT 0x00000013 +#define MVP_DEBUG_14__IDEE_READ_ADD_MASK 0x00000007L +#define MVP_DEBUG_14__IDEE_READ_ADD__SHIFT 0x00000000 +#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B_MASK 0x00020000L +#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B__SHIFT 0x00000011 +#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_MASK 0x00010000L +#define MVP_DEBUG_14__IDEE_READ_FIFO_DE__SHIFT 0x00000010 +#define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE_MASK 0x00040000L +#define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE__SHIFT 0x00000012 +#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B_MASK 0x00008000L +#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B__SHIFT 0x0000000f +#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_MASK 0x00004000L +#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE__SHIFT 0x0000000e +#define MVP_DEBUG_14__IDEE_START_INCR_WR_A_MASK 0x00000800L +#define MVP_DEBUG_14__IDEE_START_INCR_WR_A__SHIFT 0x0000000b +#define MVP_DEBUG_14__IDEE_START_INCR_WR_B_MASK 0x00001000L +#define MVP_DEBUG_14__IDEE_START_INCR_WR_B__SHIFT 0x0000000c +#define MVP_DEBUG_14__IDEE_START_READ_B_MASK 0x00000400L +#define MVP_DEBUG_14__IDEE_START_READ_B__SHIFT 0x0000000a +#define MVP_DEBUG_14__IDEE_START_READ_MASK 0x00000200L +#define MVP_DEBUG_14__IDEE_START_READ__SHIFT 0x00000009 +#define MVP_DEBUG_14__IDEE_WRITE2FIFO_MASK 0x00002000L +#define MVP_DEBUG_14__IDEE_WRITE2FIFO__SHIFT 0x0000000d +#define MVP_DEBUG_14__IDEE_WRITE_ADD_A_MASK 0x00000038L +#define MVP_DEBUG_14__IDEE_WRITE_ADD_A__SHIFT 0x00000003 +#define MVP_DEBUG_14__IDEE_WRITE_ADD_B_MASK 0x000001c0L +#define MVP_DEBUG_14__IDEE_WRITE_ADD_B__SHIFT 0x00000006 +#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA_MASK 0xfffffff0L +#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA__SHIFT 0x00000004 +#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN_MASK 0x00000001L +#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN__SHIFT 0x00000000 +#define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT_MASK 0x00000008L +#define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT__SHIFT 0x00000003 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL_MASK 0x00000004L +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL__SHIFT 0x00000002 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL_MASK 0x00000002L +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL__SHIFT 0x00000001 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES_MASK 0x00000ff0L +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES__SHIFT 0x00000004 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW_MASK 0x00001000L +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW__SHIFT 0x0000000c +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ_MASK 0x00000001L +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ__SHIFT 0x00000000 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW_MASK 0x00002000L +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW__SHIFT 0x0000000d +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR_MASK 0x00ff0000L +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR__SHIFT 0x00000010 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR_MASK 0xff000000L +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR__SHIFT 0x00000018 +#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE_MASK 0x00000002L +#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE__SHIFT 0x00000001 +#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA_MASK 0xfffffffcL +#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA__SHIFT 0x00000002 +#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_MASK 0x00000001L +#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ__SHIFT 0x00000000 +#define MVP_DEBUG__MVP_DEBUG_BITS_MASK 0xffffff00L +#define MVP_DEBUG__MVP_DEBUG_BITS__SHIFT 0x00000008 +#define MVP_DEBUG__MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP_MASK 0x00000020L +#define MVP_DEBUG__MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP__SHIFT 0x00000005 +#define MVP_DEBUG__MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP_MASK 0x00000010L +#define MVP_DEBUG__MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP__SHIFT 0x00000004 +#define MVP_DEBUG__MVP_DIS_READ_POINTER_RESET_DELAY_MASK 0x00000080L +#define MVP_DEBUG__MVP_DIS_READ_POINTER_RESET_DELAY__SHIFT 0x00000007 +#define MVP_DEBUG__MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR_MASK 0x00000040L +#define MVP_DEBUG__MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR__SHIFT 0x00000006 +#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN_MASK 0x00000002L +#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN__SHIFT 0x00000001 +#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_SEL_MASK 0x00000008L +#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_SEL__SHIFT 0x00000003 +#define MVP_DEBUG__MVP_SWAP_LOCK_IN_EN_MASK 0x00000001L +#define MVP_DEBUG__MVP_SWAP_LOCK_IN_EN__SHIFT 0x00000000 +#define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL_MASK 0x00000004L +#define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL__SHIFT 0x00000002 +#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT_MASK 0x00ff0000L +#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT__SHIFT 0x00000010 +#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM_MASK 0x0000ff00L +#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM__SHIFT 0x00000008 +#define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM_MASK 0x000000ffL +#define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM__SHIFT 0x00000000 +#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS_MASK 0x80000000L +#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS__SHIFT 0x0000001f +#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK_MASK 0x40000000L +#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK__SHIFT 0x0000001e +#define MVP_FIFO_STATUS__MVP_FIFO_LEVEL_MASK 0x000000ffL +#define MVP_FIFO_STATUS__MVP_FIFO_LEVEL__SHIFT 0x00000000 +#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK_MASK 0x00010000L +#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK__SHIFT 0x00000010 +#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_MASK 0x00000100L +#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED_MASK 0x00001000L +#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED__SHIFT 0x0000000c +#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW__SHIFT 0x00000008 +#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK_MASK 0x10000000L +#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK__SHIFT 0x0000001c +#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_MASK 0x00100000L +#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED_MASK 0x01000000L +#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED__SHIFT 0x00000018 +#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW__SHIFT 0x00000014 +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE_MASK 0x40000000L +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE__SHIFT 0x0000001e +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MASK 0x007fff00L +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE_MASK 0x00000003L +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE__SHIFT 0x00000000 +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT__SHIFT 0x00000008 +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET_MASK 0x3f000000L +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET__SHIFT 0x00000018 +#define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL_MASK 0x00000001L +#define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL__SHIFT 0x00000000 +#define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP_MASK 0xffffff00L +#define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP__SHIFT 0x00000008 +#define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN_MASK 0x00000010L +#define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN__SHIFT 0x00000004 +#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN_MASK 0x80000000L +#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN__SHIFT 0x0000001f +#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT_MASK 0x1fff0000L +#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT__SHIFT 0x00000010 +#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT_MASK 0x00001fffL +#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT__SHIFT 0x00000000 +#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_MASK 0x00001fffL +#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET_MASK 0x80000000L +#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET__SHIFT 0x0000001f +#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT__SHIFT 0x00000000 +#define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED_MASK 0x1fff0000L +#define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED__SHIFT 0x00000010 +#define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED_MASK 0x00001fffL +#define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED__SHIFT 0x00000000 +#define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA_MASK 0xffffffffL +#define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK 0x0000ffffL +#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT 0x00000000 +#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK 0xffff0000L +#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT 0x00000010 +#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK 0x0000ffffL +#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT 0x00000000 +#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK 0xffff0000L +#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT 0x00000010 +#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK 0x0000ffffL +#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT 0x00000000 +#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK 0xffff0000L +#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT 0x00000010 +#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK 0x0000ffffL +#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT 0x00000000 +#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK 0xffff0000L +#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT 0x00000010 +#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK 0x0000ffffL +#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT 0x00000000 +#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK 0xffff0000L +#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT 0x00000010 +#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK 0x0000ffffL +#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT 0x00000000 +#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK 0xffff0000L +#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT 0x00000010 +#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK 0x00000007L +#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT 0x00000000 +#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE_MASK 0x00000070L +#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT 0x00000004 +#define OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK 0x0000000fL +#define OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT 0x00000000 +#define OVL_CONTROL1__OVL_ADDRESS_TRANSLATION_ENABLE_MASK 0x00010000L +#define OVL_CONTROL1__OVL_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x00000010 +#define OVL_CONTROL1__OVL_ARRAY_MODE_MASK 0x00f00000L +#define OVL_CONTROL1__OVL_ARRAY_MODE__SHIFT 0x00000014 +#define OVL_CONTROL1__OVL_BANK_HEIGHT_MASK 0x00001800L +#define OVL_CONTROL1__OVL_BANK_HEIGHT__SHIFT 0x0000000b +#define OVL_CONTROL1__OVL_BANK_WIDTH_MASK 0x000000c0L +#define OVL_CONTROL1__OVL_BANK_WIDTH__SHIFT 0x00000006 +#define OVL_CONTROL1__OVL_COLOR_EXPANSION_MODE_MASK 0x01000000L +#define OVL_CONTROL1__OVL_COLOR_EXPANSION_MODE__SHIFT 0x00000018 +#define OVL_CONTROL1__OVL_DEPTH_MASK 0x00000003L +#define OVL_CONTROL1__OVL_DEPTH__SHIFT 0x00000000 +#define OVL_CONTROL1__OVL_FORMAT_MASK 0x00000700L +#define OVL_CONTROL1__OVL_FORMAT__SHIFT 0x00000008 +#define OVL_CONTROL1__OVL_MACRO_TILE_ASPECT_MASK 0x000c0000L +#define OVL_CONTROL1__OVL_MACRO_TILE_ASPECT__SHIFT 0x00000012 +#define OVL_CONTROL1__OVL_NUM_BANKS_MASK 0x0000000cL +#define OVL_CONTROL1__OVL_NUM_BANKS__SHIFT 0x00000002 +#define OVL_CONTROL1__OVL_PIPE_CONFIG_MASK 0x3e000000L +#define OVL_CONTROL1__OVL_PIPE_CONFIG__SHIFT 0x00000019 +#define OVL_CONTROL1__OVL_PRIVILEGED_ACCESS_ENABLE_MASK 0x00020000L +#define OVL_CONTROL1__OVL_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x00000011 +#define OVL_CONTROL1__OVL_TILE_SPLIT_MASK 0x0000e000L +#define OVL_CONTROL1__OVL_TILE_SPLIT__SHIFT 0x0000000d +#define OVL_CONTROL1__OVL_Z_MASK 0x00000030L +#define OVL_CONTROL1__OVL_Z__SHIFT 0x00000004 +#define OVL_CONTROL2__OVL_HALF_RESOLUTION_ENABLE_MASK 0x00000001L +#define OVL_CONTROL2__OVL_HALF_RESOLUTION_ENABLE__SHIFT 0x00000000 +#define OVL_DFQ_CONTROL__OVL_DFQ_MIN_FREE_ENTRIES_MASK 0x00000700L +#define OVL_DFQ_CONTROL__OVL_DFQ_MIN_FREE_ENTRIES__SHIFT 0x00000008 +#define OVL_DFQ_CONTROL__OVL_DFQ_RESET_MASK 0x00000001L +#define OVL_DFQ_CONTROL__OVL_DFQ_RESET__SHIFT 0x00000000 +#define OVL_DFQ_CONTROL__OVL_DFQ_SIZE_MASK 0x00000070L +#define OVL_DFQ_CONTROL__OVL_DFQ_SIZE__SHIFT 0x00000004 +#define OVL_DFQ_STATUS__OVL_DFQ_NUM_ENTRIES_MASK 0x0000000fL +#define OVL_DFQ_STATUS__OVL_DFQ_NUM_ENTRIES__SHIFT 0x00000000 +#define OVL_DFQ_STATUS__OVL_DFQ_RESET_ACK_MASK 0x00000200L +#define OVL_DFQ_STATUS__OVL_DFQ_RESET_ACK__SHIFT 0x00000009 +#define OVL_DFQ_STATUS__OVL_DFQ_RESET_FLAG_MASK 0x00000100L +#define OVL_DFQ_STATUS__OVL_DFQ_RESET_FLAG__SHIFT 0x00000008 +#define OVL_DFQ_STATUS__OVL_SECONDARY_DFQ_NUM_ENTRIES_MASK 0x000000f0L +#define OVL_DFQ_STATUS__OVL_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x00000004 +#define OVL_ENABLE__OVL_ENABLE_MASK 0x00000001L +#define OVL_ENABLE__OVL_ENABLE__SHIFT 0x00000000 +#define OVL_ENABLE__OVLSCL_EN_MASK 0x00000100L +#define OVL_ENABLE__OVLSCL_EN__SHIFT 0x00000008 +#define OVL_END__OVL_X_END_MASK 0x7fff0000L +#define OVL_END__OVL_X_END__SHIFT 0x00000010 +#define OVL_END__OVL_Y_END_MASK 0x00007fffL +#define OVL_END__OVL_Y_END__SHIFT 0x00000000 +#define OVL_PITCH__OVL_PITCH_MASK 0x00007fffL +#define OVL_PITCH__OVL_PITCH__SHIFT 0x00000000 +#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_BCB_MASK 0x000003ffL +#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_BCB__SHIFT 0x00000000 +#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_GY_MASK 0x000ffc00L +#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_GY__SHIFT 0x0000000a +#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_RCR_MASK 0x3ff00000L +#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_RCR__SHIFT 0x00000014 +#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_EDGE_PIXEL_SEL_MASK 0x80000000L +#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_EDGE_PIXEL_SEL__SHIFT 0x0000001f +#define OVL_SECONDARY_SURFACE_ADDRESS_HIGH__OVL_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x000000ffL +#define OVL_SECONDARY_SURFACE_ADDRESS_HIGH__OVL_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x00000000 +#define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_DFQ_ENABLE_MASK 0x00000001L +#define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_DFQ_ENABLE__SHIFT 0x00000000 +#define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_SURFACE_ADDRESS_MASK 0xffffff00L +#define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_SURFACE_ADDRESS__SHIFT 0x00000008 +#define OVL_START__OVL_X_START_MASK 0x3fff0000L +#define OVL_START__OVL_X_START__SHIFT 0x00000010 +#define OVL_START__OVL_Y_START_MASK 0x00003fffL +#define OVL_START__OVL_Y_START__SHIFT 0x00000000 +#define OVL_STEREOSYNC_FLIP__OVL_PRIMARY_SURFACE_PENDING_MASK 0x00010000L +#define OVL_STEREOSYNC_FLIP__OVL_PRIMARY_SURFACE_PENDING__SHIFT 0x00000010 +#define OVL_STEREOSYNC_FLIP__OVL_SECONDARY_SURFACE_PENDING_MASK 0x00020000L +#define OVL_STEREOSYNC_FLIP__OVL_SECONDARY_SURFACE_PENDING__SHIFT 0x00000011 +#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_EN_MASK 0x00000001L +#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_EN__SHIFT 0x00000000 +#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_MODE_MASK 0x00000300L +#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_MODE__SHIFT 0x00000008 +#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000L +#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_SELECT_DISABLE__SHIFT 0x0000001c +#define OVL_SURFACE_ADDRESS_HIGH_INUSE__OVL_SURFACE_ADDRESS_HIGH_INUSE_MASK 0x000000ffL +#define OVL_SURFACE_ADDRESS_HIGH_INUSE__OVL_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x00000000 +#define OVL_SURFACE_ADDRESS_HIGH__OVL_SURFACE_ADDRESS_HIGH_MASK 0x000000ffL +#define OVL_SURFACE_ADDRESS_HIGH__OVL_SURFACE_ADDRESS_HIGH__SHIFT 0x00000000 +#define OVL_SURFACE_ADDRESS_INUSE__OVL_SURFACE_ADDRESS_INUSE_MASK 0xffffff00L +#define OVL_SURFACE_ADDRESS_INUSE__OVL_SURFACE_ADDRESS_INUSE__SHIFT 0x00000008 +#define OVL_SURFACE_ADDRESS__OVL_DFQ_ENABLE_MASK 0x00000001L +#define OVL_SURFACE_ADDRESS__OVL_DFQ_ENABLE__SHIFT 0x00000000 +#define OVL_SURFACE_ADDRESS__OVL_SURFACE_ADDRESS_MASK 0xffffff00L +#define OVL_SURFACE_ADDRESS__OVL_SURFACE_ADDRESS__SHIFT 0x00000008 +#define OVL_SURFACE_OFFSET_X__OVL_SURFACE_OFFSET_X_MASK 0x00003fffL +#define OVL_SURFACE_OFFSET_X__OVL_SURFACE_OFFSET_X__SHIFT 0x00000000 +#define OVL_SURFACE_OFFSET_Y__OVL_SURFACE_OFFSET_Y_MASK 0x00003fffL +#define OVL_SURFACE_OFFSET_Y__OVL_SURFACE_OFFSET_Y__SHIFT 0x00000000 +#define OVL_SWAP_CNTL__OVL_ALPHA_CROSSBAR_MASK 0x00000c00L +#define OVL_SWAP_CNTL__OVL_ALPHA_CROSSBAR__SHIFT 0x0000000a +#define OVL_SWAP_CNTL__OVL_BLUE_CROSSBAR_MASK 0x00000300L +#define OVL_SWAP_CNTL__OVL_BLUE_CROSSBAR__SHIFT 0x00000008 +#define OVL_SWAP_CNTL__OVL_ENDIAN_SWAP_MASK 0x00000003L +#define OVL_SWAP_CNTL__OVL_ENDIAN_SWAP__SHIFT 0x00000000 +#define OVL_SWAP_CNTL__OVL_GREEN_CROSSBAR_MASK 0x000000c0L +#define OVL_SWAP_CNTL__OVL_GREEN_CROSSBAR__SHIFT 0x00000006 +#define OVL_SWAP_CNTL__OVL_RED_CROSSBAR_MASK 0x00000030L +#define OVL_SWAP_CNTL__OVL_RED_CROSSBAR__SHIFT 0x00000004 +#define OVL_UPDATE__OVL_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L +#define OVL_UPDATE__OVL_DISABLE_MULTIPLE_UPDATE__SHIFT 0x00000018 +#define OVL_UPDATE__OVL_UPDATE_LOCK_MASK 0x00010000L +#define OVL_UPDATE__OVL_UPDATE_LOCK__SHIFT 0x00000010 +#define OVL_UPDATE__OVL_UPDATE_PENDING_MASK 0x00000001L +#define OVL_UPDATE__OVL_UPDATE_PENDING__SHIFT 0x00000000 +#define OVL_UPDATE__OVL_UPDATE_TAKEN_MASK 0x00000002L +#define OVL_UPDATE__OVL_UPDATE_TAKEN__SHIFT 0x00000001 +#define PHY_AUX_CNTL__AUX_PAD_RXSEL_MASK 0x00010000L +#define PHY_AUX_CNTL__AUX_PAD_RXSEL__SHIFT 0x00000010 +#define PHY_AUX_CNTL__AUX_PAD_SLEWN_MASK 0x00001000L +#define PHY_AUX_CNTL__AUX_PAD_SLEWN__SHIFT 0x0000000c +#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK 0x00004000L +#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT 0x0000000e +#define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000ffffL +#define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x00000000 +#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L +#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x00000000 +#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L +#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x00000004 +#define PIPE0_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003ffL +#define PIPE0_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x00000000 +#define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x00000001L +#define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x00000000 +#define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x00000001L +#define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x00000000 +#define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000L +#define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x0000001c +#define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS_MASK 0xc0000000L +#define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS__SHIFT 0x0000001e +#define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0x00ffffffL +#define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x00000000 +#define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE_MASK 0x20000000L +#define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE__SHIFT 0x0000001d +#define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000ffffL +#define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x00000000 +#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L +#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x00000000 +#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L +#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x00000004 +#define PIPE1_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003ffL +#define PIPE1_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x00000000 +#define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON_MASK 0x00000001L +#define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON__SHIFT 0x00000000 +#define PIPE1_PG_ENABLE__PIPE1_POWER_GATE_MASK 0x00000001L +#define PIPE1_PG_ENABLE__PIPE1_POWER_GATE__SHIFT 0x00000000 +#define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE_MASK 0x10000000L +#define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE__SHIFT 0x0000001c +#define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS_MASK 0xc0000000L +#define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS__SHIFT 0x0000001e +#define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA_MASK 0x00ffffffL +#define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA__SHIFT 0x00000000 +#define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE_MASK 0x20000000L +#define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE__SHIFT 0x0000001d +#define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000ffffL +#define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x00000000 +#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L +#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x00000000 +#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L +#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x00000004 +#define PIPE2_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003ffL +#define PIPE2_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x00000000 +#define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON_MASK 0x00000001L +#define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON__SHIFT 0x00000000 +#define PIPE2_PG_ENABLE__PIPE2_POWER_GATE_MASK 0x00000001L +#define PIPE2_PG_ENABLE__PIPE2_POWER_GATE__SHIFT 0x00000000 +#define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE_MASK 0x10000000L +#define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE__SHIFT 0x0000001c +#define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS_MASK 0xc0000000L +#define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS__SHIFT 0x0000001e +#define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA_MASK 0x00ffffffL +#define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA__SHIFT 0x00000000 +#define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE_MASK 0x20000000L +#define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE__SHIFT 0x0000001d +#define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000ffffL +#define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x00000000 +#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L +#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x00000000 +#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L +#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x00000004 +#define PIPE3_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003ffL +#define PIPE3_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x00000000 +#define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON_MASK 0x00000001L +#define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON__SHIFT 0x00000000 +#define PIPE3_PG_ENABLE__PIPE3_POWER_GATE_MASK 0x00000001L +#define PIPE3_PG_ENABLE__PIPE3_POWER_GATE__SHIFT 0x00000000 +#define PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE_MASK 0x10000000L +#define PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE__SHIFT 0x0000001c +#define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS_MASK 0xc0000000L +#define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS__SHIFT 0x0000001e +#define PIPE3_PG_STATUS__PIPE3_PGFSM_READ_DATA_MASK 0x00ffffffL +#define PIPE3_PG_STATUS__PIPE3_PGFSM_READ_DATA__SHIFT 0x00000000 +#define PIPE3_PG_STATUS__PIPE3_REQUESTED_PWR_STATE_MASK 0x20000000L +#define PIPE3_PG_STATUS__PIPE3_REQUESTED_PWR_STATE__SHIFT 0x0000001d +#define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000ffffL +#define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x00000000 +#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L +#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x00000000 +#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L +#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x00000004 +#define PIPE4_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003ffL +#define PIPE4_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x00000000 +#define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON_MASK 0x00000001L +#define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON__SHIFT 0x00000000 +#define PIPE4_PG_ENABLE__PIPE4_POWER_GATE_MASK 0x00000001L +#define PIPE4_PG_ENABLE__PIPE4_POWER_GATE__SHIFT 0x00000000 +#define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE_MASK 0x10000000L +#define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE__SHIFT 0x0000001c +#define PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS_MASK 0xc0000000L +#define PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS__SHIFT 0x0000001e +#define PIPE4_PG_STATUS__PIPE4_PGFSM_READ_DATA_MASK 0x00ffffffL +#define PIPE4_PG_STATUS__PIPE4_PGFSM_READ_DATA__SHIFT 0x00000000 +#define PIPE4_PG_STATUS__PIPE4_REQUESTED_PWR_STATE_MASK 0x20000000L +#define PIPE4_PG_STATUS__PIPE4_REQUESTED_PWR_STATE__SHIFT 0x0000001d +#define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000ffffL +#define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x00000000 +#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L +#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x00000000 +#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L +#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x00000004 +#define PIPE5_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003ffL +#define PIPE5_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x00000000 +#define PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON_MASK 0x00000001L +#define PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON__SHIFT 0x00000000 +#define PIPE5_PG_ENABLE__PIPE5_POWER_GATE_MASK 0x00000001L +#define PIPE5_PG_ENABLE__PIPE5_POWER_GATE__SHIFT 0x00000000 +#define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE_MASK 0x10000000L +#define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE__SHIFT 0x0000001c +#define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS_MASK 0xc0000000L +#define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS__SHIFT 0x0000001e +#define PIPE5_PG_STATUS__PIPE5_PGFSM_READ_DATA_MASK 0x00ffffffL +#define PIPE5_PG_STATUS__PIPE5_PGFSM_READ_DATA__SHIFT 0x00000000 +#define PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE_MASK 0x20000000L +#define PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE__SHIFT 0x0000001d +#define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0_MASK 0x00000030L +#define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0__SHIFT 0x00000004 +#define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE_MASK 0x00000001L +#define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE__SHIFT 0x00000000 +#define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1_MASK 0x00000030L +#define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1__SHIFT 0x00000004 +#define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE_MASK 0x00000001L +#define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE__SHIFT 0x00000000 +#define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2_MASK 0x00000030L +#define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2__SHIFT 0x00000004 +#define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE_MASK 0x00000001L +#define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE__SHIFT 0x00000000 +#define PLL_ANALOG__PLL_CAL_MODE_MASK 0x0000001fL +#define PLL_ANALOG__PLL_CAL_MODE__SHIFT 0x00000000 +#define PLL_ANALOG__PLL_CP_MASK 0x00000f00L +#define PLL_ANALOG__PLL_CP__SHIFT 0x00000008 +#define PLL_ANALOG__PLL_IBIAS_MASK 0xff000000L +#define PLL_ANALOG__PLL_IBIAS__SHIFT 0x00000018 +#define PLL_ANALOG__PLL_LF_MODE_MASK 0x001ff000L +#define PLL_ANALOG__PLL_LF_MODE__SHIFT 0x0000000c +#define PLL_ANALOG__PLL_PFD_PULSE_SEL_MASK 0x00000060L +#define PLL_ANALOG__PLL_PFD_PULSE_SEL__SHIFT 0x00000005 +#define PLL_CNTL__PLL_ANTIGLITCH_RESETB_MASK 0x00000080L +#define PLL_CNTL__PLL_ANTIGLITCH_RESETB__SHIFT 0x00000007 +#define PLL_CNTL__PLL_ANTI_GLITCH_RESET_MASK 0x00002000L +#define PLL_CNTL__PLL_ANTI_GLITCH_RESET__SHIFT 0x0000000d +#define PLL_CNTL__PLL_BYPASS_CAL_MASK 0x00000004L +#define PLL_CNTL__PLL_BYPASS_CAL__SHIFT 0x00000002 +#define PLL_CNTL__PLL_CAL_BYPASS_REFDIV_MASK 0x00000400L +#define PLL_CNTL__PLL_CAL_BYPASS_REFDIV__SHIFT 0x0000000a +#define PLL_CNTL__PLL_CALIB_DONE_MASK 0x00100000L +#define PLL_CNTL__PLL_CALIB_DONE__SHIFT 0x00000014 +#define PLL_CNTL__PLL_CALREF_MASK 0x00000300L +#define PLL_CNTL__PLL_CALREF__SHIFT 0x00000008 +#define PLL_CNTL__PLL_DIG_SPARE_MASK 0xfc000000L +#define PLL_CNTL__PLL_DIG_SPARE__SHIFT 0x0000001a +#define PLL_CNTL__PLL_LOCKED_MASK 0x00200000L +#define PLL_CNTL__PLL_LOCKED__SHIFT 0x00000015 +#define PLL_CNTL__PLL_LOCK_FREQ_SEL_MASK 0x00080000L +#define PLL_CNTL__PLL_LOCK_FREQ_SEL__SHIFT 0x00000013 +#define PLL_CNTL__PLL_PCIE_REFCLK_SEL_MASK 0x00000040L +#define PLL_CNTL__PLL_PCIE_REFCLK_SEL__SHIFT 0x00000006 +#define PLL_CNTL__PLL_POST_DIV_SRC_MASK 0x00000008L +#define PLL_CNTL__PLL_POST_DIV_SRC__SHIFT 0x00000003 +#define PLL_CNTL__PLL_POWER_DOWN_MASK 0x00000002L +#define PLL_CNTL__PLL_POWER_DOWN__SHIFT 0x00000001 +#define PLL_CNTL__PLL_REFCLK_SEL_MASK 0x00001800L +#define PLL_CNTL__PLL_REFCLK_SEL__SHIFT 0x0000000b +#define PLL_CNTL__PLL_REF_DIV_SRC_MASK 0x00070000L +#define PLL_CNTL__PLL_REF_DIV_SRC__SHIFT 0x00000010 +#define PLL_CNTL__PLL_RESET_MASK 0x00000001L +#define PLL_CNTL__PLL_RESET__SHIFT 0x00000000 +#define PLL_CNTL__PLL_TIMING_MODE_STATUS_MASK 0x03000000L +#define PLL_CNTL__PLL_TIMING_MODE_STATUS__SHIFT 0x00000018 +#define PLL_CNTL__PLL_VCOREF_MASK 0x00000030L +#define PLL_CNTL__PLL_VCOREF__SHIFT 0x00000004 +#define PLL_DEBUG_CNTL__PLL_DEBUG_CLK_SEL_MASK 0x00000f00L +#define PLL_DEBUG_CNTL__PLL_DEBUG_CLK_SEL__SHIFT 0x00000008 +#define PLL_DEBUG_CNTL__PLL_DEBUG_MUXOUT_SEL_MASK 0x000000f0L +#define PLL_DEBUG_CNTL__PLL_DEBUG_MUXOUT_SEL__SHIFT 0x00000004 +#define PLL_DEBUG_CNTL__PLL_DEBUG_SIGNALS_ENABLE_MASK 0x00000001L +#define PLL_DEBUG_CNTL__PLL_DEBUG_SIGNALS_ENABLE__SHIFT 0x00000000 +#define PLL_DISPCLK_CURRENT_DTO_PHASE__PLL_DISPCLK_CURRENT_DTO_PHASE_MASK 0x000001ffL +#define PLL_DISPCLK_CURRENT_DTO_PHASE__PLL_DISPCLK_CURRENT_DTO_PHASE__SHIFT 0x00000000 +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_COMPL_DELAY_MASK 0xff000000L +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_COMPL_DELAY__SHIFT 0x00000018 +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_DIS_MASK 0x00010000L +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_DIS__SHIFT 0x00000010 +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_PHASE_MASK 0x000001ffL +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_PHASE__SHIFT 0x00000000 +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_ACK_MASK 0x00400000L +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_ACK__SHIFT 0x00000016 +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_MODE_MASK 0x00060000L +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_MODE__SHIFT 0x00000011 +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_PENDING_MASK 0x00100000L +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_PENDING__SHIFT 0x00000014 +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_REQ_MASK 0x00200000L +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_REQ__SHIFT 0x00000015 +#define PLL_DS_CNTL__PLL_DS_FRAC_MASK 0x0000ffffL +#define PLL_DS_CNTL__PLL_DS_FRAC__SHIFT 0x00000000 +#define PLL_DS_CNTL__PLL_DS_MODE_MASK 0x00040000L +#define PLL_DS_CNTL__PLL_DS_MODE__SHIFT 0x00000012 +#define PLL_DS_CNTL__PLL_DS_ORDER_MASK 0x00030000L +#define PLL_DS_CNTL__PLL_DS_ORDER__SHIFT 0x00000010 +#define PLL_DS_CNTL__PLL_DS_PRBS_EN_MASK 0x00080000L +#define PLL_DS_CNTL__PLL_DS_PRBS_EN__SHIFT 0x00000013 +#define PLL_FB_DIV__PLL_FB_DIV_FRACTION_CNTL_MASK 0x00000030L +#define PLL_FB_DIV__PLL_FB_DIV_FRACTION_CNTL__SHIFT 0x00000004 +#define PLL_FB_DIV__PLL_FB_DIV_FRACTION_MASK 0x0000000fL +#define PLL_FB_DIV__PLL_FB_DIV_FRACTION__SHIFT 0x00000000 +#define PLL_FB_DIV__PLL_FB_DIV_MASK 0x0fff0000L +#define PLL_FB_DIV__PLL_FB_DIV__SHIFT 0x00000010 +#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_MASK 0x000f0000L +#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_RESET_MASK 0x00000100L +#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_RESET__SHIFT 0x00000008 +#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_SELECT_MASK 0x00001000L +#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_SELECT__SHIFT 0x0000000c +#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV__SHIFT 0x00000010 +#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_DIFF_EN_MASK 0x00000002L +#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_DIFF_EN__SHIFT 0x00000001 +#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_EN_MASK 0x00000001L +#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_EN__SHIFT 0x00000000 +#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_DIFF_EN_MASK 0x00000008L +#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_DIFF_EN__SHIFT 0x00000003 +#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_EN_MASK 0x00000004L +#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_EN__SHIFT 0x00000002 +#define PLL_IDCLK_CNTL__PLL_UNIPHY_IDCLK_DIFF_EN_MASK 0x00000010L +#define PLL_IDCLK_CNTL__PLL_UNIPHY_IDCLK_DIFF_EN__SHIFT 0x00000004 +#define PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK_MASK 0x00000080L +#define PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK__SHIFT 0x00000007 +#define PLL_POST_DIV__PLL_POST_DIV1P5_DPREFCLK_MASK 0x00008000L +#define PLL_POST_DIV__PLL_POST_DIV1P5_DPREFCLK__SHIFT 0x0000000f +#define PLL_POST_DIV__PLL_POST_DIV_DVOCLK_MASK 0x00007f00L +#define PLL_POST_DIV__PLL_POST_DIV_DVOCLK__SHIFT 0x00000008 +#define PLL_POST_DIV__PLL_POST_DIV_IDCLK_MASK 0x007f0000L +#define PLL_POST_DIV__PLL_POST_DIV_IDCLK__SHIFT 0x00000010 +#define PLL_POST_DIV__PLL_POST_DIV_PIXCLK_MASK 0x0000007fL +#define PLL_POST_DIV__PLL_POST_DIV_PIXCLK__SHIFT 0x00000000 +#define PLL_REF_DIV__PLL_CALIBRATION_REF_DIV_MASK 0x0000f000L +#define PLL_REF_DIV__PLL_CALIBRATION_REF_DIV__SHIFT 0x0000000c +#define PLL_REF_DIV__PLL_REF_DIV_MASK 0x000003ffL +#define PLL_REF_DIV__PLL_REF_DIV__SHIFT 0x00000000 +#define PLL_SS_AMOUNT_DSFRAC__PLL_SS_AMOUNT_DSFRAC_MASK 0x0000ffffL +#define PLL_SS_AMOUNT_DSFRAC__PLL_SS_AMOUNT_DSFRAC__SHIFT 0x00000000 +#define PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV_MASK 0x000000ffL +#define PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV__SHIFT 0x00000000 +#define PLL_SS_CNTL__PLL_SS_AMOUNT_NFRAC_SLIP_MASK 0x00000f00L +#define PLL_SS_CNTL__PLL_SS_AMOUNT_NFRAC_SLIP__SHIFT 0x00000008 +#define PLL_SS_CNTL__PLL_SS_EN_MASK 0x00001000L +#define PLL_SS_CNTL__PLL_SS_EN__SHIFT 0x0000000c +#define PLL_SS_CNTL__PLL_SS_MODE_MASK 0x00002000L +#define PLL_SS_CNTL__PLL_SS_MODE__SHIFT 0x0000000d +#define PLL_SS_CNTL__PLL_SS_STEP_SIZE_DSFRAC_MASK 0xffff0000L +#define PLL_SS_CNTL__PLL_SS_STEP_SIZE_DSFRAC__SHIFT 0x00000010 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_COUNT_MASK 0x00000070L +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_COUNT__SHIFT 0x00000004 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DETECT_ENABLE_MASK 0x00000001L +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DETECT_ENABLE__SHIFT 0x00000000 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_RES100_SELECT_MASK 0x00000002L +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_RES100_SELECT__SHIFT 0x00000001 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_CLEAR_MASK 0x00000008L +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_CLEAR__SHIFT 0x00000003 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_STATUS_MASK 0x00000004L +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_STATUS__SHIFT 0x00000002 +#define PLL_UPDATE_CNTL__PLL_AUTO_RESET_DISABLE_MASK 0x00010000L +#define PLL_UPDATE_CNTL__PLL_AUTO_RESET_DISABLE__SHIFT 0x00000010 +#define PLL_UPDATE_CNTL__PLL_UPDATE_PENDING_MASK 0x00000001L +#define PLL_UPDATE_CNTL__PLL_UPDATE_PENDING__SHIFT 0x00000000 +#define PLL_UPDATE_CNTL__PLL_UPDATE_POINT_MASK 0x00000100L +#define PLL_UPDATE_CNTL__PLL_UPDATE_POINT__SHIFT 0x00000008 +#define PLL_UPDATE_LOCK__PLL_UPDATE_LOCK_MASK 0x00000001L +#define PLL_UPDATE_LOCK__PLL_UPDATE_LOCK__SHIFT 0x00000000 +#define PLL_VREG_CNTL__PLL_VREF_SEL_MASK 0x04000000L +#define PLL_VREG_CNTL__PLL_VREF_SEL__SHIFT 0x0000001a +#define PLL_VREG_CNTL__PLL_VREG_BIAS_MASK 0xf0000000L +#define PLL_VREG_CNTL__PLL_VREG_BIAS__SHIFT 0x0000001c +#define PLL_VREG_CNTL__PLL_VREG_CNTL_MASK 0x000fffffL +#define PLL_VREG_CNTL__PLL_VREG_CNTL__SHIFT 0x00000000 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK 0x00000008L +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT 0x00000003 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK 0x00000010L +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT 0x00000004 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK 0x00000004L +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT 0x00000002 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK 0x00000002L +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT 0x00000001 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK 0x00000001L +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT 0x00000000 +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK 0x00000010L +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS__SHIFT 0x00000004 +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CB_SIGN_MASK 0x00000002L +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CB_SIGN__SHIFT 0x00000001 +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CR_SIGN_MASK 0x00000008L +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CR_SIGN__SHIFT 0x00000003 +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_SELECT_MASK 0x00000001L +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_SELECT__SHIFT 0x00000000 +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_Y_SIGN_MASK 0x00000004L +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_Y_SIGN__SHIFT 0x00000002 +#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK 0x0000ffffL +#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT 0x00000000 +#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK 0xffff0000L +#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT 0x00000010 +#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK 0x0000ffffL +#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT 0x00000000 +#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK 0xffff0000L +#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT 0x00000010 +#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK 0x0000ffffL +#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT 0x00000000 +#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK 0xffff0000L +#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT 0x00000010 +#define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_BIAS_CB_MASK 0x0000ffffL +#define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_BIAS_CB__SHIFT 0x00000000 +#define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_SCALE_CB_MASK 0xffff0000L +#define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_SCALE_CB__SHIFT 0x00000010 +#define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_BIAS_CR_MASK 0x0000ffffL +#define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_BIAS_CR__SHIFT 0x00000000 +#define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_SCALE_CR_MASK 0xffff0000L +#define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_SCALE_CR__SHIFT 0x00000010 +#define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_BIAS_Y_MASK 0x0000ffffL +#define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_BIAS_Y__SHIFT 0x00000000 +#define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_SCALE_Y_MASK 0xffff0000L +#define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_SCALE_Y__SHIFT 0x00000010 +#define REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK 0x0000ffffL +#define REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT 0x00000000 +#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK 0xffff0000L +#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT 0x00000010 +#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK 0x0000ffffL +#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x00000000 +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x0003ffffL +#define REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x00000000 +#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK 0x0003ffffL +#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x07f00000L +#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x00000014 +#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT 0x00000000 +#define REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK 0x0000ffffL +#define REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT 0x00000000 +#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK 0xffff0000L +#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT 0x00000010 +#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK 0x0000ffffL +#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x00000000 +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x0003ffffL +#define REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x00000000 +#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK 0x0003ffffL +#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x07f00000L +#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x00000014 +#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT 0x00000000 +#define REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK 0x00000007L +#define REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT 0x00000000 +#define REGAMMA_CONTROL__OVL_REGAMMA_MODE_MASK 0x00000070L +#define REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT 0x00000004 +#define REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK 0x0007ffffL +#define REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT 0x00000000 +#define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK 0x000001ffL +#define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT 0x00000000 +#define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x00000000 +#define SCL_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x00000001L +#define SCL_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x00000000 +#define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE_MASK 0x00000003L +#define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE__SHIFT 0x00000000 +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK_MASK 0x00000100L +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK__SHIFT 0x00000008 +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG_MASK 0x00000001L +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG__SHIFT 0x00000000 +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS_MASK 0x00010000L +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x00000010 +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK_MASK 0x00001000L +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK__SHIFT 0x0000000c +#define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x00030000L +#define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x00000010 +#define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0x00000f00L +#define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x00000008 +#define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0x0000000fL +#define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x00000000 +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0x0000000f +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x00003fffL +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x00000000 +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x0000001f +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3fff0000L +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x00000010 +#define SCL_DEBUG2__SCL_DEBUG2_MASK 0xffffffffL +#define SCL_DEBUG2__SCL_DEBUG2__SHIFT 0x00000000 +#define SCL_DEBUG__SCL_DEBUG_MASK 0xffffffffL +#define SCL_DEBUG__SCL_DEBUG__SHIFT 0x00000000 +#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN_MASK 0x00000010L +#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN__SHIFT 0x00000004 +#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR_MASK 0x00000007L +#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR__SHIFT 0x00000000 +#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN_MASK 0x00001000L +#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN__SHIFT 0x0000000c +#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR_MASK 0x00000700L +#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR__SHIFT 0x00000008 +#define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST_MASK 0x00000001L +#define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST__SHIFT 0x00000000 +#define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03ffffffL +#define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x00000000 +#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY_MASK 0x00000ff0L +#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY__SHIFT 0x00000004 +#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY_MASK 0x0000000fL +#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY__SHIFT 0x00000000 +#define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000f00L +#define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x00000008 +#define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000fL +#define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x00000000 +#define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0x0fffff80L +#define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x00000007 +#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x00000010L +#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x00000004 +#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x00000001L +#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x00000000 +#define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x001fffffL +#define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x00000000 +#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x00003fffL +#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x00000000 +#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3fff0000L +#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x00000010 +#define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x00000001L +#define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x00000000 +#define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA_MASK 0xffffffffL +#define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define SCL_UPDATE__SCL_UPDATE_LOCK_MASK 0x00010000L +#define SCL_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x00000010 +#define SCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L +#define SCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x00000000 +#define SCL_UPDATE__SCL_UPDATE_TAKEN_MASK 0x00000100L +#define SCL_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x00000008 +#define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST_MASK 0x00000001L +#define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST__SHIFT 0x00000000 +#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x0000ffffL +#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x00000000 +#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x00070000L +#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x00000010 +#define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x0000ffffL +#define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x00000000 +#define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x00070000L +#define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x00000010 +#define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03ffffffL +#define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x00000000 +#define SEQ00__SEQ_RST0B_MASK 0x00000001L +#define SEQ00__SEQ_RST0B__SHIFT 0x00000000 +#define SEQ00__SEQ_RST1B_MASK 0x00000002L +#define SEQ00__SEQ_RST1B__SHIFT 0x00000001 +#define SEQ01__SEQ_DOT8_MASK 0x00000001L +#define SEQ01__SEQ_DOT8__SHIFT 0x00000000 +#define SEQ01__SEQ_MAXBW_MASK 0x00000020L +#define SEQ01__SEQ_MAXBW__SHIFT 0x00000005 +#define SEQ01__SEQ_PCLKBY2_MASK 0x00000008L +#define SEQ01__SEQ_PCLKBY2__SHIFT 0x00000003 +#define SEQ01__SEQ_SHIFT2_MASK 0x00000004L +#define SEQ01__SEQ_SHIFT2__SHIFT 0x00000002 +#define SEQ01__SEQ_SHIFT4_MASK 0x00000010L +#define SEQ01__SEQ_SHIFT4__SHIFT 0x00000004 +#define SEQ02__SEQ_MAP0_EN_MASK 0x00000001L +#define SEQ02__SEQ_MAP0_EN__SHIFT 0x00000000 +#define SEQ02__SEQ_MAP1_EN_MASK 0x00000002L +#define SEQ02__SEQ_MAP1_EN__SHIFT 0x00000001 +#define SEQ02__SEQ_MAP2_EN_MASK 0x00000004L +#define SEQ02__SEQ_MAP2_EN__SHIFT 0x00000002 +#define SEQ02__SEQ_MAP3_EN_MASK 0x00000008L +#define SEQ02__SEQ_MAP3_EN__SHIFT 0x00000003 +#define SEQ03__SEQ_FONT_A0_MASK 0x00000020L +#define SEQ03__SEQ_FONT_A0__SHIFT 0x00000005 +#define SEQ03__SEQ_FONT_A1_MASK 0x00000004L +#define SEQ03__SEQ_FONT_A1__SHIFT 0x00000002 +#define SEQ03__SEQ_FONT_A2_MASK 0x00000008L +#define SEQ03__SEQ_FONT_A2__SHIFT 0x00000003 +#define SEQ03__SEQ_FONT_B0_MASK 0x00000010L +#define SEQ03__SEQ_FONT_B0__SHIFT 0x00000004 +#define SEQ03__SEQ_FONT_B1_MASK 0x00000001L +#define SEQ03__SEQ_FONT_B1__SHIFT 0x00000000 +#define SEQ03__SEQ_FONT_B2_MASK 0x00000002L +#define SEQ03__SEQ_FONT_B2__SHIFT 0x00000001 +#define SEQ04__SEQ_256K_MASK 0x00000002L +#define SEQ04__SEQ_256K__SHIFT 0x00000001 +#define SEQ04__SEQ_CHAIN_MASK 0x00000008L +#define SEQ04__SEQ_CHAIN__SHIFT 0x00000003 +#define SEQ04__SEQ_ODDEVEN_MASK 0x00000004L +#define SEQ04__SEQ_ODDEVEN__SHIFT 0x00000002 +#define SEQ8_DATA__SEQ_DATA_MASK 0x000000ffL +#define SEQ8_DATA__SEQ_DATA__SHIFT 0x00000000 +#define SEQ8_IDX__SEQ_IDX_MASK 0x00000007L +#define SEQ8_IDX__SEQ_IDX__SHIFT 0x00000000 +#define SINK_DESCRIPTION0__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION0__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION10__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION10__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION11__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION11__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION12__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION12__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION13__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION13__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION14__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION14__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION15__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION15__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION16__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION16__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION17__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION17__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION1__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION1__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION2__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION2__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION3__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION3__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION4__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION4__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION5__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION5__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION6__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION6__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION7__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION7__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION8__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION8__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION9__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION9__DESCRIPTION__SHIFT 0x00000000 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0_MASK 0x000000ffL +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0__SHIFT 0x00000000 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1_MASK 0x0000ff00L +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1__SHIFT 0x00000008 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2_MASK 0x00ff0000L +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2__SHIFT 0x00000010 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3_MASK 0xff000000L +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3__SHIFT 0x00000018 +#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS_MASK 0x00000100L +#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS__SHIFT 0x00000008 +#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT_MASK 0x00000001L +#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT__SHIFT 0x00000000 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0_MASK 0x000000ffL +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0__SHIFT 0x00000000 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1_MASK 0x0000ff00L +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1__SHIFT 0x00000008 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2_MASK 0x00ff0000L +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2__SHIFT 0x00000010 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3_MASK 0xff000000L +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3__SHIFT 0x00000018 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0_MASK 0x000000ffL +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0__SHIFT 0x00000000 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1_MASK 0x0000ff00L +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1__SHIFT 0x00000008 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2_MASK 0x00ff0000L +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2__SHIFT 0x00000010 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3_MASK 0xff000000L +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3__SHIFT 0x00000018 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0_MASK 0x000000ffL +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0__SHIFT 0x00000000 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1_MASK 0x0000ff00L +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1__SHIFT 0x00000008 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2_MASK 0x00ff0000L +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2__SHIFT 0x00000010 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3_MASK 0xff000000L +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3__SHIFT 0x00000018 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT 0x00000000 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN__SHIFT 0x00000004 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC_MASK 0x00000700L +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC__SHIFT 0x00000008 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT 0x00000000 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN__SHIFT 0x00000004 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC_MASK 0x00000700L +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC__SHIFT 0x00000008 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT 0x00000000 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN__SHIFT 0x00000004 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC_MASK 0x00000700L +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC__SHIFT 0x00000008 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT 0x00000000 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN__SHIFT 0x00000004 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC_MASK 0x00000700L +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC__SHIFT 0x00000008 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT 0x00000000 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN__SHIFT 0x00000004 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC_MASK 0x00000700L +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC__SHIFT 0x00000008 +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE__SHIFT 0x00000000 +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN__SHIFT 0x00000004 +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC_MASK 0x00000700L +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC__SHIFT 0x00000008 +#define TMDS_CNTL__TMDS_COLOR_FORMAT_MASK 0x00000300L +#define TMDS_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x00000008 +#define TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK 0x00000010L +#define TMDS_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x00000004 +#define TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L +#define TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x00000000 +#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L +#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x00000008 +#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L +#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x00000000 +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x00000000 +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x00000001 +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x00000002 +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x00000003 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L +#define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x0000001f +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x00000004 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x00000007 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x00000008 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000fL +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x00000000 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0x0000000b +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0x0000000c +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0x0000000a +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x00000014 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x00000017 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x00000018 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000f0000L +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x00000010 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x0000001b +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x0000001c +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x0000001a +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x00000004 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x00000007 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x00000008 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000fL +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x00000000 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0x0000000b +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0x0000000c +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0x0000000a +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x00000014 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x00000017 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x00000018 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000f0000L +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x00000010 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x0000001b +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x0000001c +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x0000001a +#define TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L +#define TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x00000000 +#define TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L +#define TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x00000008 +#define TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L +#define TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x00000010 +#define TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L +#define TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x00000018 +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x00000000 +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x00000018 +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x00000008 +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000f0000L +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x00000010 +#define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L +#define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x00000004 +#define TMDS_DEBUG__TMDS_DEBUG_DE_EN_MASK 0x02000000L +#define TMDS_DEBUG__TMDS_DEBUG_DE_EN__SHIFT 0x00000019 +#define TMDS_DEBUG__TMDS_DEBUG_DE_MASK 0x01000000L +#define TMDS_DEBUG__TMDS_DEBUG_DE__SHIFT 0x00000018 +#define TMDS_DEBUG__TMDS_DEBUG_EN_MASK 0x00000001L +#define TMDS_DEBUG__TMDS_DEBUG_EN__SHIFT 0x00000000 +#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN_MASK 0x00000200L +#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN__SHIFT 0x00000009 +#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_MASK 0x00000100L +#define TMDS_DEBUG__TMDS_DEBUG_HSYNC__SHIFT 0x00000008 +#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN_MASK 0x00020000L +#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN__SHIFT 0x00000011 +#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_MASK 0x00010000L +#define TMDS_DEBUG__TMDS_DEBUG_VSYNC__SHIFT 0x00000010 +#define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L +#define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x00000000 +#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003ffL +#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x00000000 +#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03ff0000L +#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x00000010 +#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003ffL +#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x00000000 +#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03ff0000L +#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x00000010 +#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_STATIC_TEST_PATTERN_MASK 0x000003ffL +#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_STATIC_TEST_PATTERN__SHIFT 0x00000000 +#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_EN_MASK 0x00010000L +#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_EN__SHIFT 0x00000010 +#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_SEL_MASK 0x000e0000L +#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_SEL__SHIFT 0x00000011 +#define UNIPHYAB_TPG_SEED__UNIPHYAB_TPG_SEED_MASK 0x007fffffL +#define UNIPHYAB_TPG_SEED__UNIPHYAB_TPG_SEED__SHIFT 0x00000000 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_ERROR_MASK 0x001f0000L +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_ERROR__SHIFT 0x00000010 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_RESET_MASK 0x00000002L +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_RESET__SHIFT 0x00000001 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_PRESETB_MASK 0x01000000L +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_PRESETB__SHIFT 0x00000018 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_RX_BIAS_MASK 0x00000f00L +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_RX_BIAS__SHIFT 0x00000008 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_TEST_RX_EN_MASK 0x00000001L +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_TEST_RX_EN__SHIFT 0x00000000 +#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_STATIC_TEST_PATTERN_MASK 0x000003ffL +#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_STATIC_TEST_PATTERN__SHIFT 0x00000000 +#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_EN_MASK 0x00010000L +#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_EN__SHIFT 0x00000010 +#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_SEL_MASK 0x000e0000L +#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_SEL__SHIFT 0x00000011 +#define UNIPHYCD_TPG_SEED__UNIPHYCD_TPG_SEED_MASK 0x007fffffL +#define UNIPHYCD_TPG_SEED__UNIPHYCD_TPG_SEED__SHIFT 0x00000000 +#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x00000000 +#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x00000008 +#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x00000010 +#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x00000018 +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_ERROR_MASK 0x00000040L +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_ERROR__SHIFT 0x00000006 +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_LEVEL_MASK 0x00000030L +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_LEVEL__SHIFT 0x00000004 +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYNSEL_MASK 0x00000001L +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYNSEL__SHIFT 0x00000000 +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DUAL_LINK_PHASE_MASK 0x00010000L +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DUAL_LINK_PHASE__SHIFT 0x00000010 +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_LINK_ENABLE_MASK 0x00001000L +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_LINK_ENABLE__SHIFT 0x0000000c +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_SOURCE_SELECT_MASK 0x00000100L +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_SOURCE_SELECT__SHIFT 0x00000008 +#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_STATIC_TEST_PATTERN_MASK 0x000003ffL +#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_STATIC_TEST_PATTERN__SHIFT 0x00000000 +#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_EN_MASK 0x00010000L +#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_EN__SHIFT 0x00000010 +#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_SEL_MASK 0x000e0000L +#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_SEL__SHIFT 0x00000011 +#define UNIPHYEF_TPG_SEED__UNIPHYEF_TPG_SEED_MASK 0x007fffffL +#define UNIPHYEF_TPG_SEED__UNIPHYEF_TPG_SEED__SHIFT 0x00000000 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK_MASK 0x00000400L +#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK__SHIFT 0x0000000a +#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_MASK 0x00000200L +#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA__SHIFT 0x00000009 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA_MASK 0x00000100L +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA__SHIFT 0x00000008 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA_MASK 0x00000001L +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA__SHIFT 0x00000000 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA_MASK 0x10000000L +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA__SHIFT 0x0000001c +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA_MASK 0x0f000000L +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA__SHIFT 0x00000018 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA_MASK 0x40000000L +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA__SHIFT 0x0000001e +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA_MASK 0x00f00000L +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA__SHIFT 0x00000014 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA_MASK 0x000f0000L +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA__SHIFT 0x00000010 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK_MASK 0x00000400L +#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK__SHIFT 0x0000000a +#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_MASK 0x00000200L +#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB__SHIFT 0x00000009 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB_MASK 0x00000100L +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB__SHIFT 0x00000008 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB_MASK 0x00000001L +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB__SHIFT 0x00000000 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB_MASK 0x10000000L +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB__SHIFT 0x0000001c +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB_MASK 0x0f000000L +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB__SHIFT 0x00000018 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB_MASK 0x40000000L +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB__SHIFT 0x0000001e +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB_MASK 0x00f00000L +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB__SHIFT 0x00000014 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB_MASK 0x000f0000L +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB__SHIFT 0x00000010 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK_MASK 0x00000400L +#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK__SHIFT 0x0000000a +#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_MASK 0x00000200L +#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC__SHIFT 0x00000009 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC_MASK 0x00000100L +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC__SHIFT 0x00000008 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC_MASK 0x00000001L +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC__SHIFT 0x00000000 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC_MASK 0x10000000L +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC__SHIFT 0x0000001c +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC_MASK 0x0f000000L +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC__SHIFT 0x00000018 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC_MASK 0x40000000L +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC__SHIFT 0x0000001e +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC_MASK 0x00f00000L +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC__SHIFT 0x00000014 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC_MASK 0x000f0000L +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC__SHIFT 0x00000010 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK_MASK 0x00000400L +#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK__SHIFT 0x0000000a +#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_MASK 0x00000200L +#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD__SHIFT 0x00000009 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD_MASK 0x00000100L +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD__SHIFT 0x00000008 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD_MASK 0x00000001L +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD__SHIFT 0x00000000 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD_MASK 0x10000000L +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD__SHIFT 0x0000001c +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD_MASK 0x0f000000L +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD__SHIFT 0x00000018 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD_MASK 0x40000000L +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD__SHIFT 0x0000001e +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD_MASK 0x00f00000L +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD__SHIFT 0x00000014 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD_MASK 0x000f0000L +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD__SHIFT 0x00000010 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK_MASK 0x00000400L +#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK__SHIFT 0x0000000a +#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_MASK 0x00000200L +#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE__SHIFT 0x00000009 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE_MASK 0x00000100L +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE__SHIFT 0x00000008 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE_MASK 0x00000001L +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE__SHIFT 0x00000000 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE_MASK 0x10000000L +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE__SHIFT 0x0000001c +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE_MASK 0x0f000000L +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE__SHIFT 0x00000018 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE_MASK 0x40000000L +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE__SHIFT 0x0000001e +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE_MASK 0x00f00000L +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE__SHIFT 0x00000014 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE_MASK 0x000f0000L +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE__SHIFT 0x00000010 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK_MASK 0x00000400L +#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK__SHIFT 0x0000000a +#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_MASK 0x00000200L +#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF__SHIFT 0x00000009 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF_MASK 0x00000100L +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF__SHIFT 0x00000008 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF_MASK 0x00000001L +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF__SHIFT 0x00000000 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF_MASK 0x10000000L +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF__SHIFT 0x0000001c +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF_MASK 0x0f000000L +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF__SHIFT 0x00000018 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF_MASK 0x40000000L +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF__SHIFT 0x0000001e +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF_MASK 0x00f00000L +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF__SHIFT 0x00000014 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF_MASK 0x000f0000L +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF__SHIFT 0x00000010 +#define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD_MASK 0xffffffffL +#define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD__SHIFT 0x00000000 +#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA_MASK 0x00007fffL +#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA__SHIFT 0x00000000 +#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB_MASK 0x7fff0000L +#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB__SHIFT 0x00000010 +#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC_MASK 0x00007fffL +#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC__SHIFT 0x00000000 +#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD_MASK 0x7fff0000L +#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD__SHIFT 0x00000010 +#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE_MASK 0x00007fffL +#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE__SHIFT 0x00000000 +#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF_MASK 0x7fff0000L +#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF__SHIFT 0x00000010 +#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L +#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0x0000000c +#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L +#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0x0000000d +#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L +#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0x0000000e +#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L +#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0x0000000f +#define UNIPHY_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L +#define UNIPHY_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x00000014 +#define UNIPHY_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x00030000L +#define UNIPHY_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x00000010 +#define UNIPHY_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L +#define UNIPHY_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x00000008 +#define UNIPHY_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L +#define UNIPHY_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x00000000 +#define UNIPHY_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L +#define UNIPHY_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x00000004 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_BW_CNTL_MASK 0x00ff0000L +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_BW_CNTL__SHIFT 0x00000010 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLK_EN_MASK 0x00000008L +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLK_EN__SHIFT 0x00000003 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLKPH_EN_MASK 0x000000f0L +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLKPH_EN__SHIFT 0x00000004 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_ENABLE_MASK 0x00000001L +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_ENABLE__SHIFT 0x00000000 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_EXT_RESET_EN_MASK 0x00000004L +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_EXT_RESET_EN__SHIFT 0x00000002 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_LF_CNTL_MASK 0x00007f00L +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_LF_CNTL__SHIFT 0x00000008 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_RESET_MASK 0x00000002L +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_RESET__SHIFT 0x00000001 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_EN_MASK 0x02000000L +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_EN__SHIFT 0x00000019 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_SRC_MASK 0x01000000L +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_SRC__SHIFT 0x00000018 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_VCTL_ADC_EN_MASK 0x04000000L +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_VCTL_ADC_EN__SHIFT 0x0000001a +#define UNIPHY_PLL_CONTROL1__UNIPHY_VCO_MODE_MASK 0x30000000L +#define UNIPHY_PLL_CONTROL1__UNIPHY_VCO_MODE__SHIFT 0x0000001c +#define UNIPHY_PLL_CONTROL2__UNIPHY_CLKINV_MASK 0x00002000L +#define UNIPHY_PLL_CONTROL2__UNIPHY_CLKINV__SHIFT 0x0000000d +#define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL_MASK 0x0000000cL +#define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL__SHIFT 0x00000002 +#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_EN_MASK 0x00001000L +#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_EN__SHIFT 0x0000000c +#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_SEL_MASK 0x00000010L +#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_SEL__SHIFT 0x00000004 +#define UNIPHY_PLL_CONTROL2__UNIPHY_IPCIE_REFCLK_SEL_MASK 0x00000020L +#define UNIPHY_PLL_CONTROL2__UNIPHY_IPCIE_REFCLK_SEL__SHIFT 0x00000005 +#define UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL_MASK 0x00000040L +#define UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL__SHIFT 0x00000006 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PCIEREF_CLK_EN_MASK 0x00000800L +#define UNIPHY_PLL_CONTROL2__UNIPHY_PCIEREF_CLK_EN__SHIFT 0x0000000b +#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIVFRAC_SEL_MASK 0x00100000L +#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIVFRAC_SEL__SHIFT 0x00000014 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIV_SEL_MASK 0xe0000000L +#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIV_SEL__SHIFT 0x0000001d +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_DISPCLK_MODE_MASK 0x00000003L +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_DISPCLK_MODE__SHIFT 0x00000000 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFCLK_SRC_MASK 0x00000700L +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFCLK_SRC__SHIFT 0x00000008 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFDIV_MASK 0x1f000000L +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFDIV__SHIFT 0x00000018 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS_MASK 0x00080000L +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS__SHIFT 0x00000013 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_VTOI_BIAS_CNTL_MASK 0x00010000L +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_VTOI_BIAS_CNTL__SHIFT 0x00000010 +#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_FRACTION_MASK 0x0000fffcL +#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_FRACTION__SHIFT 0x00000002 +#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_MASK 0x0fff0000L +#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV__SHIFT 0x00000010 +#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_DSMOD_EN_MASK 0x00001000L +#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_DSMOD_EN__SHIFT 0x0000000c +#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_EN_MASK 0x00002000L +#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_EN__SHIFT 0x0000000d +#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_STEP_NUM_MASK 0x00000fffL +#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_STEP_NUM__SHIFT 0x00000000 +#define UNIPHY_PLL_SS_STEP_SIZE__UNIPHY_PLL_SS_STEP_SIZE_MASK 0x03ffffffL +#define UNIPHY_PLL_SS_STEP_SIZE__UNIPHY_PLL_SS_STEP_SIZE__SHIFT 0x00000000 +#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ0P45_MASK 0x000f0000L +#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ0P45__SHIFT 0x00000010 +#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P00_MASK 0x00000f00L +#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P00__SHIFT 0x00000008 +#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P25_MASK 0x0000f000L +#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P25__SHIFT 0x0000000c +#define UNIPHY_POWER_CONTROL__UNIPHY_BGPDN_MASK 0x00000001L +#define UNIPHY_POWER_CONTROL__UNIPHY_BGPDN__SHIFT 0x00000000 +#define UNIPHY_POWER_CONTROL__UNIPHY_BIASREF_SEL_MASK 0x00000004L +#define UNIPHY_POWER_CONTROL__UNIPHY_BIASREF_SEL__SHIFT 0x00000002 +#define UNIPHY_POWER_CONTROL__UNIPHY_RST_LOGIC_MASK 0x00000002L +#define UNIPHY_POWER_CONTROL__UNIPHY_RST_LOGIC__SHIFT 0x00000001 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR_MASK 0x01f00000L +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR__SHIFT 0x00000014 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_RESET_MASK 0x00008000L +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_RESET__SHIFT 0x0000000f +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_SEL_MASK 0x00010000L +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_SEL__SHIFT 0x00000010 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_INTRESET_MASK 0x20000000L +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_INTRESET__SHIFT 0x0000001d +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_FREQ_LOCK_MASK 0x10000000L +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_FREQ_LOCK__SHIFT 0x0000001c +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_ADC_MASK 0x0e000000L +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_ADC__SHIFT 0x00000019 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL_MASK 0x0000001fL +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL__SHIFT 0x00000000 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_VCTL_EN_MASK 0x00020000L +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_VCTL_EN__SHIFT 0x00000011 +#define UNIPHY_SOFT_RESET__DSYNCA_SOFT_RESET_MASK 0x00000001L +#define UNIPHY_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT 0x00000000 +#define UNIPHY_SOFT_RESET__DSYNCB_SOFT_RESET_MASK 0x00000002L +#define UNIPHY_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT 0x00000001 +#define UNIPHY_SOFT_RESET__DSYNCC_SOFT_RESET_MASK 0x00000004L +#define UNIPHY_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT 0x00000002 +#define UNIPHY_SOFT_RESET__DSYNCD_SOFT_RESET_MASK 0x00000008L +#define UNIPHY_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT 0x00000003 +#define UNIPHY_SOFT_RESET__DSYNCE_SOFT_RESET_MASK 0x00000010L +#define UNIPHY_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT 0x00000004 +#define UNIPHY_SOFT_RESET__DSYNCF_SOFT_RESET_MASK 0x00000020L +#define UNIPHY_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT 0x00000005 +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR0_MASK 0x00000007L +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR0__SHIFT 0x00000000 +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR1_MASK 0x00000070L +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR1__SHIFT 0x00000004 +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR2_MASK 0x00000700L +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR2__SHIFT 0x00000008 +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR3_MASK 0x00007000L +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR3__SHIFT 0x0000000c +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR4_MASK 0x00070000L +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR4__SHIFT 0x00000010 +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS0_MASK 0x00300000L +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS0__SHIFT 0x00000014 +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS1_MASK 0x00c00000L +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS1__SHIFT 0x00000016 +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS2_MASK 0x03000000L +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS2__SHIFT 0x00000018 +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS3_MASK 0x0c000000L +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS3__SHIFT 0x0000001a +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS4_MASK 0x30000000L +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS4__SHIFT 0x0000001c +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH0_PC_MASK 0x00000003L +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH0_PC__SHIFT 0x00000000 +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH1_PC_MASK 0x00000030L +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH1_PC__SHIFT 0x00000004 +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH2_PC_MASK 0x00000300L +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH2_PC__SHIFT 0x00000008 +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH3_PC_MASK 0x00003000L +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH3_PC__SHIFT 0x0000000c +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH4_PC_MASK 0x00030000L +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH4_PC__SHIFT 0x00000010 +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH_SEL_MASK 0x00100000L +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH_SEL__SHIFT 0x00000014 +#define UNIPHY_TX_CONTROL2__UNIPHY_RT0_CPSEL_MASK 0x00600000L +#define UNIPHY_TX_CONTROL2__UNIPHY_RT0_CPSEL__SHIFT 0x00000015 +#define UNIPHY_TX_CONTROL2__UNIPHY_RT1_CPSEL_MASK 0x01800000L +#define UNIPHY_TX_CONTROL2__UNIPHY_RT1_CPSEL__SHIFT 0x00000017 +#define UNIPHY_TX_CONTROL2__UNIPHY_RT2_CPSEL_MASK 0x06000000L +#define UNIPHY_TX_CONTROL2__UNIPHY_RT2_CPSEL__SHIFT 0x00000019 +#define UNIPHY_TX_CONTROL2__UNIPHY_RT3_CPSEL_MASK 0x18000000L +#define UNIPHY_TX_CONTROL2__UNIPHY_RT3_CPSEL__SHIFT 0x0000001b +#define UNIPHY_TX_CONTROL2__UNIPHY_RT4_CPSEL_MASK 0x60000000L +#define UNIPHY_TX_CONTROL2__UNIPHY_RT4_CPSEL__SHIFT 0x0000001d +#define UNIPHY_TX_CONTROL3__UNIPHY_LVDS_PULLDWN_MASK 0x80000000L +#define UNIPHY_TX_CONTROL3__UNIPHY_LVDS_PULLDWN__SHIFT 0x0000001f +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL0_MASK 0x00100000L +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL0__SHIFT 0x00000014 +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL1_MASK 0x00200000L +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL1__SHIFT 0x00000015 +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL2_MASK 0x00400000L +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL2__SHIFT 0x00000016 +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL3_MASK 0x00800000L +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL3__SHIFT 0x00000017 +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_CLK_MASK 0x000000f0L +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_CLK__SHIFT 0x00000004 +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_DAT_MASK 0x00000f00L +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_DAT__SHIFT 0x00000008 +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_CLK_MASK 0x00000003L +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_CLK__SHIFT 0x00000000 +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_DAT_MASK 0x0000000cL +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_DAT__SHIFT 0x00000002 +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_CLK_MASK 0x00007000L +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_CLK__SHIFT 0x0000000c +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_DAT_MASK 0x00070000L +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_DAT__SHIFT 0x00000010 +#define UNIPHY_TX_CONTROL3__UNIPHY_TX_VS_ADJ_MASK 0x1f000000L +#define UNIPHY_TX_CONTROL3__UNIPHY_TX_VS_ADJ__SHIFT 0x00000018 +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_CLK_MASK 0x0000001fL +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_CLK__SHIFT 0x00000000 +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_DAT_MASK 0x000003e0L +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_DAT__SHIFT 0x00000005 +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_CLK_MASK 0x07000000L +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_CLK__SHIFT 0x00000018 +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_DAT_MASK 0x70000000L +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_DAT__SHIFT 0x0000001c +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK_MASK 0x0001f000L +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK__SHIFT 0x0000000c +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT_MASK 0x003e0000L +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT__SHIFT 0x00000011 +#define VGA25_PPLL_ANALOG__VGA25_CAL_MODE_MASK 0x0000001fL +#define VGA25_PPLL_ANALOG__VGA25_CAL_MODE__SHIFT 0x00000000 +#define VGA25_PPLL_ANALOG__VGA25_PPLL_CP_MASK 0x00000f00L +#define VGA25_PPLL_ANALOG__VGA25_PPLL_CP__SHIFT 0x00000008 +#define VGA25_PPLL_ANALOG__VGA25_PPLL_IBIAS_MASK 0xff000000L +#define VGA25_PPLL_ANALOG__VGA25_PPLL_IBIAS__SHIFT 0x00000018 +#define VGA25_PPLL_ANALOG__VGA25_PPLL_LF_MODE_MASK 0x001ff000L +#define VGA25_PPLL_ANALOG__VGA25_PPLL_LF_MODE__SHIFT 0x0000000c +#define VGA25_PPLL_ANALOG__VGA25_PPLL_PFD_PULSE_SEL_MASK 0x00000060L +#define VGA25_PPLL_ANALOG__VGA25_PPLL_PFD_PULSE_SEL__SHIFT 0x00000005 +#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x00000030L +#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x00000004 +#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_MASK 0x0000000fL +#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION__SHIFT 0x00000000 +#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_MASK 0x07ff0000L +#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV__SHIFT 0x00000010 +#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_DVOCLK_MASK 0x00007f00L +#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_DVOCLK__SHIFT 0x00000008 +#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_IDCLK_MASK 0x007f0000L +#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_IDCLK__SHIFT 0x00000010 +#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK_MASK 0x0000007fL +#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK__SHIFT 0x00000000 +#define VGA25_PPLL_REF_DIV__VGA25_PPLL_REF_DIV_MASK 0x000003ffL +#define VGA25_PPLL_REF_DIV__VGA25_PPLL_REF_DIV__SHIFT 0x00000000 +#define VGA28_PPLL_ANALOG__VGA28_CAL_MODE_MASK 0x0000001fL +#define VGA28_PPLL_ANALOG__VGA28_CAL_MODE__SHIFT 0x00000000 +#define VGA28_PPLL_ANALOG__VGA28_PPLL_CP_MASK 0x00000f00L +#define VGA28_PPLL_ANALOG__VGA28_PPLL_CP__SHIFT 0x00000008 +#define VGA28_PPLL_ANALOG__VGA28_PPLL_IBIAS_MASK 0xff000000L +#define VGA28_PPLL_ANALOG__VGA28_PPLL_IBIAS__SHIFT 0x00000018 +#define VGA28_PPLL_ANALOG__VGA28_PPLL_LF_MODE_MASK 0x001ff000L +#define VGA28_PPLL_ANALOG__VGA28_PPLL_LF_MODE__SHIFT 0x0000000c +#define VGA28_PPLL_ANALOG__VGA28_PPLL_PFD_PULSE_SEL_MASK 0x00000060L +#define VGA28_PPLL_ANALOG__VGA28_PPLL_PFD_PULSE_SEL__SHIFT 0x00000005 +#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x00000030L +#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x00000004 +#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_MASK 0x0000000fL +#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION__SHIFT 0x00000000 +#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_MASK 0x07ff0000L +#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV__SHIFT 0x00000010 +#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_DVOCLK_MASK 0x00007f00L +#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_DVOCLK__SHIFT 0x00000008 +#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_IDCLK_MASK 0x007f0000L +#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_IDCLK__SHIFT 0x00000010 +#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_PIXCLK_MASK 0x0000007fL +#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_PIXCLK__SHIFT 0x00000000 +#define VGA28_PPLL_REF_DIV__VGA28_PPLL_REF_DIV_MASK 0x000003ffL +#define VGA28_PPLL_REF_DIV__VGA28_PPLL_REF_DIV__SHIFT 0x00000000 +#define VGA41_PPLL_ANALOG__VGA41_CAL_MODE_MASK 0x0000001fL +#define VGA41_PPLL_ANALOG__VGA41_CAL_MODE__SHIFT 0x00000000 +#define VGA41_PPLL_ANALOG__VGA41_PPLL_CP_MASK 0x00000f00L +#define VGA41_PPLL_ANALOG__VGA41_PPLL_CP__SHIFT 0x00000008 +#define VGA41_PPLL_ANALOG__VGA41_PPLL_IBIAS_MASK 0xff000000L +#define VGA41_PPLL_ANALOG__VGA41_PPLL_IBIAS__SHIFT 0x00000018 +#define VGA41_PPLL_ANALOG__VGA41_PPLL_LF_MODE_MASK 0x001ff000L +#define VGA41_PPLL_ANALOG__VGA41_PPLL_LF_MODE__SHIFT 0x0000000c +#define VGA41_PPLL_ANALOG__VGA41_PPLL_PFD_PULSE_SEL_MASK 0x00000060L +#define VGA41_PPLL_ANALOG__VGA41_PPLL_PFD_PULSE_SEL__SHIFT 0x00000005 +#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x00000030L +#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x00000004 +#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_MASK 0x0000000fL +#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION__SHIFT 0x00000000 +#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_MASK 0x07ff0000L +#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV__SHIFT 0x00000010 +#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_DVOCLK_MASK 0x00007f00L +#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_DVOCLK__SHIFT 0x00000008 +#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_IDCLK_MASK 0x007f0000L +#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_IDCLK__SHIFT 0x00000010 +#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_PIXCLK_MASK 0x0000007fL +#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_PIXCLK__SHIFT 0x00000000 +#define VGA41_PPLL_REF_DIV__VGA41_PPLL_REF_DIV_MASK 0x000003ffL +#define VGA41_PPLL_REF_DIV__VGA41_PPLL_REF_DIV__SHIFT 0x00000000 +#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY_MASK 0x00100000L +#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT 0x00000014 +#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT_MASK 0x3f000000L +#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT__SHIFT 0x00000018 +#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE_MASK 0x00010000L +#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT 0x00000010 +#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE_MASK 0x00000100L +#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE__SHIFT 0x00000008 +#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS_MASK 0x00000001L +#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS__SHIFT 0x00000000 +#define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C_MASK 0xffffffffL +#define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT 0x00000000 +#define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA_MASK 0xffffffffL +#define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA__SHIFT 0x00000000 +#define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX_MASK 0x000000ffL +#define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX__SHIFT 0x00000000 +#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR_MASK 0x01ffffffL +#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR__SHIFT 0x00000000 +#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR_MASK 0x01ffffffL +#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR__SHIFT 0x00000000 +#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK 0x00000010L +#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE__SHIFT 0x00000004 +#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN_MASK 0x00000001L +#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN__SHIFT 0x00000000 +#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE_MASK 0x00000100L +#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE__SHIFT 0x00000008 +#define VGA_HDP_CONTROL__VGA_SOFT_RESET_MASK 0x00010000L +#define VGA_HDP_CONTROL__VGA_SOFT_RESET__SHIFT 0x00000010 +#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK 0x01000000L +#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT 0x00000018 +#define VGA_HW_DEBUG__VGA_HW_DEBUG_MASK 0xffffffffL +#define VGA_HW_DEBUG__VGA_HW_DEBUG__SHIFT 0x00000000 +#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK_MASK 0x00010000L +#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT 0x00000010 +#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK_MASK 0x00000001L +#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK__SHIFT 0x00000000 +#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK_MASK 0x01000000L +#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK__SHIFT 0x00000018 +#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK 0x00000100L +#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK__SHIFT 0x00000008 +#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS_MASK 0x00000004L +#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT 0x00000002 +#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS_MASK 0x00000001L +#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS__SHIFT 0x00000000 +#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS_MASK 0x00000008L +#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS__SHIFT 0x00000003 +#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK 0x00000002L +#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS__SHIFT 0x00000001 +#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT_MASK 0x00000003L +#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT__SHIFT 0x00000000 +#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE_MASK 0x20000000L +#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE__SHIFT 0x0000001d +#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT_MASK 0x80000000L +#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT__SHIFT 0x0000001f +#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT_MASK 0x03000000L +#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT__SHIFT 0x00000018 +#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT_MASK 0x00030000L +#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT__SHIFT 0x00000010 +#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT_MASK 0x04000000L +#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT__SHIFT 0x0000001a +#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT_MASK 0x00000300L +#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT__SHIFT 0x00000008 +#define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE_MASK 0x08000000L +#define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE__SHIFT 0x0000001b +#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT_MASK 0x00000018L +#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT__SHIFT 0x00000003 +#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION_MASK 0x000000e0L +#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION__SHIFT 0x00000005 +#define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE_MASK 0x10000000L +#define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE__SHIFT 0x0000001c +#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH_MASK 0x000000ffL +#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH__SHIFT 0x00000000 +#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS_MASK 0xffffffffL +#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS__SHIFT 0x00000000 +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x000003ffL +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x00000000 +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x03ff0000L +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x00000010 +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x000003ffL +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x00000000 +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x03ff0000L +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x00000010 +#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING_MASK 0x00000100L +#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING__SHIFT 0x00000008 +#define VGA_MODE_CONTROL__VGA_ATI_LINEAR_MASK 0x00000001L +#define VGA_MODE_CONTROL__VGA_ATI_LINEAR__SHIFT 0x00000000 +#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE_MASK 0x00000030L +#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE__SHIFT 0x00000004 +#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN_MASK 0x00010000L +#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT 0x00000010 +#define VGA_RENDER_CONTROL__VGA_BLINK_MODE_MASK 0x00000060L +#define VGA_RENDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x00000005 +#define VGA_RENDER_CONTROL__VGA_BLINK_RATE_MASK 0x0000001fL +#define VGA_RENDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x00000000 +#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT_MASK 0x00000080L +#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT__SHIFT 0x00000007 +#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE_MASK 0x00000100L +#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE__SHIFT 0x00000008 +#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT_MASK 0x01000000L +#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT__SHIFT 0x00000018 +#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL_MASK 0x02000000L +#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL__SHIFT 0x00000019 +#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK 0x00030000L +#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL__SHIFT 0x00000010 +#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000001L +#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x00000000 +#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000100L +#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x00000008 +#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000002L +#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x00000001 +#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000200L +#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x00000009 +#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000004L +#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x00000002 +#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000400L +#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x0000000a +#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000008L +#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x00000003 +#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000800L +#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x0000000b +#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000010L +#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x00000004 +#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00001000L +#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x0000000c +#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000020L +#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x00000005 +#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00002000L +#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x0000000d +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE_MASK 0x00010000L +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT 0x00000010 +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT_MASK 0x00fc0000L +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT__SHIFT 0x00000012 +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT_MASK 0x00020000L +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT__SHIFT 0x00000011 +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A_MASK 0x00000007L +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A__SHIFT 0x00000000 +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B_MASK 0x00000700L +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B__SHIFT 0x00000008 +#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR_MASK 0x00010000L +#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR__SHIFT 0x00000010 +#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR_MASK 0x00000001L +#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR__SHIFT 0x00000000 +#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR_MASK 0x01000000L +#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR__SHIFT 0x00000018 +#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR_MASK 0x00000100L +#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR__SHIFT 0x00000008 +#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS_MASK 0x00000004L +#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT 0x00000002 +#define VGA_STATUS__VGA_MEM_ACCESS_STATUS_MASK 0x00000001L +#define VGA_STATUS__VGA_MEM_ACCESS_STATUS__SHIFT 0x00000000 +#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS_MASK 0x00000008L +#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS__SHIFT 0x00000003 +#define VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK 0x00000002L +#define VGA_STATUS__VGA_REG_ACCESS_STATUS__SHIFT 0x00000001 +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT_MASK 0x00000300L +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT__SHIFT 0x00000008 +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT_MASK 0x00000003L +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT__SHIFT 0x00000000 +#define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK 0x00000001L +#define VGA_TEST_CONTROL__VGA_TEST_ENABLE__SHIFT 0x00000000 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT_MASK 0x01000000L +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT__SHIFT 0x00000018 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE_MASK 0x00010000L +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE__SHIFT 0x00000010 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START_MASK 0x00000100L +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START__SHIFT 0x00000008 +#define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA_MASK 0xffffffffL +#define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x00003fffL +#define VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x00000000 +#define VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x3fff0000L +#define VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x00000010 +#define VIEWPORT_START__VIEWPORT_X_START_MASK 0x3fff0000L +#define VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x00000010 +#define VIEWPORT_START__VIEWPORT_Y_START_MASK 0x00003fffL +#define VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x00000000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_GATE_DIS_MASK 0x00008000L +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_GATE_DIS__SHIFT 0x0000000f +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MSTAT_GATE_DIS_MASK 0x00080000L +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MSTAT_GATE_DIS__SHIFT 0x00000013 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SDYN_GATE_DIS_MASK 0x00040000L +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SDYN_GATE_DIS__SHIFT 0x00000012 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SSTAT_GATE_DIS_MASK 0x00100000L +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SSTAT_GATE_DIS__SHIFT 0x00000014 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_REG_GATE_DIS_MASK 0x00010000L +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_REG_GATE_DIS__SHIFT 0x00000010 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_OFF_DELAY_MASK 0x00000ff0L +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_OFF_DELAY__SHIFT 0x00000004 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_ON_DELAY_MASK 0x0000000fL +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_ON_DELAY__SHIFT 0x00000000 +#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_CLEAR_MASK 0x00000100L +#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_CLEAR__SHIFT 0x00000008 +#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_STATUS_MASK 0x0000000fL +#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_STATUS__SHIFT 0x00000000 +#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_ACK_MASK 0x00000400L +#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_ACK__SHIFT 0x0000000a +#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_MASK_MASK 0x00000200L +#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_MASK__SHIFT 0x00000009 +#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_STAT_MASK 0x00000100L +#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_STAT__SHIFT 0x00000008 +#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_ACK_MASK 0x00004000L +#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_ACK__SHIFT 0x0000000e +#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_MASK_MASK 0x00002000L +#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_MASK__SHIFT 0x0000000d +#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_STAT_MASK 0x00001000L +#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_STAT__SHIFT 0x0000000c +#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_ACK_MASK 0x00040000L +#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_ACK__SHIFT 0x00000012 +#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_MASK_MASK 0x00020000L +#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_MASK__SHIFT 0x00000011 +#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_STAT_MASK 0x00010000L +#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_STAT__SHIFT 0x00000010 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_ARRAY_MODE_MASK 0x0000000fL +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_ARRAY_MODE__SHIFT 0x00000000 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_HEIGHT_MASK 0x00000c00L +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_HEIGHT__SHIFT 0x0000000a +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_WIDTH_MASK 0x00000300L +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_WIDTH__SHIFT 0x00000008 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_MACRO_TILE_ASPECT_MASK 0x00003000L +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_MACRO_TILE_ASPECT__SHIFT 0x0000000c +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_NUM_BANKS_MASK 0x00300000L +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_NUM_BANKS__SHIFT 0x00000014 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_TILE_SPLIT_MASK 0x00000070L +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_TILE_SPLIT__SHIFT 0x00000004 +#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_MICRO_TILE_MODE_MASK 0x00c00000L +#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_MICRO_TILE_MODE__SHIFT 0x00000016 +#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_CONFIG_MASK 0xf8000000L +#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_CONFIG__SHIFT 0x0000001b +#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_INTERLEAVE_SIZE_MASK 0x00000007L +#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_INTERLEAVE_SIZE__SHIFT 0x00000000 +#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_PRIV_MASK 0x00010000L +#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_PRIV__SHIFT 0x00000010 +#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_SWAP_MASK 0x00000300L +#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_SWAP__SHIFT 0x00000008 +#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_VMID_MASK 0x0000f000L +#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_VMID__SHIFT 0x0000000c +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_DIS__SHIFT 0x00000000 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_MODE_FORCE_MASK 0x00010000L +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x00000010 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_POWER_STATE_MASK 0xc0000000L +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_POWER_STATE__SHIFT 0x0000001e +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_DIS_MASK 0x00000100L +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_DIS__SHIFT 0x00000008 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_MODE_FORCE_MASK 0x01000000L +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_MODE_FORCE__SHIFT 0x00000018 +#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_URGENT_LEVEL_MASK 0x00000f00L +#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_URGENT_LEVEL__SHIFT 0x00000008 +#define XDMA_MSTR_CNTL__XDMA_MSTR_DEBUG_MODE_MASK 0x00040000L +#define XDMA_MSTR_CNTL__XDMA_MSTR_DEBUG_MODE__SHIFT 0x00000012 +#define XDMA_MSTR_CNTL__XDMA_MSTR_ENABLE_MASK 0x00010000L +#define XDMA_MSTR_CNTL__XDMA_MSTR_ENABLE__SHIFT 0x00000010 +#define XDMA_MSTR_CNTL__XDMA_MSTR_MEM_READY_MASK 0x00000200L +#define XDMA_MSTR_CNTL__XDMA_MSTR_MEM_READY__SHIFT 0x00000009 +#define XDMA_MSTR_CNTL__XDMA_MSTR_SOFT_RESET_MASK 0x00100000L +#define XDMA_MSTR_CNTL__XDMA_MSTR_SOFT_RESET__SHIFT 0x00000014 +#define XDMA_MSTR_HEIGHT__XDMA_MSTR_ACTIVE_HEIGHT_MASK 0x00003fffL +#define XDMA_MSTR_HEIGHT__XDMA_MSTR_ACTIVE_HEIGHT__SHIFT 0x00000000 +#define XDMA_MSTR_HEIGHT__XDMA_MSTR_FRAME_HEIGHT_MASK 0x3fff0000L +#define XDMA_MSTR_HEIGHT__XDMA_MSTR_FRAME_HEIGHT__SHIFT 0x00000010 +#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH_MASK 0x000000ffL +#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__SHIFT 0x00000000 +#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_MASK 0xffffffffL +#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__SHIFT 0x00000000 +#define XDMA_MSTR_LOCAL_SURFACE_PITCH__XDMA_MSTR_LOCAL_SURFACE_PITCH_MASK 0x00003fffL +#define XDMA_MSTR_LOCAL_SURFACE_PITCH__XDMA_MSTR_LOCAL_SURFACE_PITCH__SHIFT 0x00000000 +#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_PRIV_MASK 0x00010000L +#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_PRIV__SHIFT 0x00000010 +#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_SWAP_MASK 0x00000300L +#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_SWAP__SHIFT 0x00000008 +#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_VMID_MASK 0x0000f000L +#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_VMID__SHIFT 0x0000000c +#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_CLR_MASK 0x00010000L +#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_CLR__SHIFT 0x00000010 +#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_MASK 0x00003000L +#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK__SHIFT 0x0000000c +#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_TAG_MASK 0x000003ffL +#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_TAG__SHIFT 0x00000000 +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_CLIENT_STALL_MASK 0x00000001L +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_CLIENT_STALL__SHIFT 0x00000000 +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_STALL_DELAY_MASK 0x0000f000L +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_STALL_DELAY__SHIFT 0x0000000c +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LEVEL_MASK 0x00000f00L +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LEVEL__SHIFT 0x00000008 +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LIMIT_MASK 0x000000f0L +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LIMIT__SHIFT 0x00000004 +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_TIMER_MASK 0xffff0000L +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_TIMER__SHIFT 0x00000010 +#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_CLR_MASK 0x00010000L +#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_CLR__SHIFT 0x00000010 +#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_MASK 0x00003000L +#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK__SHIFT 0x0000000c +#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_TAG_MASK 0x000003ffL +#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_TAG__SHIFT 0x00000000 +#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_PREFETCH_MASK 0x3fff0000L +#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_PREFETCH__SHIFT 0x00000010 +#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_SIZE_MASK 0x00003fffL +#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_SIZE__SHIFT 0x00000000 +#define XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH_MASK 0x000000ffL +#define XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__SHIFT 0x00000000 +#define XDMA_MSTR_REMOTE_GPU_ADDRESS__XDMA_MSTR_REMOTE_GPU_ADDRESS_MASK 0xffffffffL +#define XDMA_MSTR_REMOTE_GPU_ADDRESS__XDMA_MSTR_REMOTE_GPU_ADDRESS__SHIFT 0x00000000 +#define XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH_MASK 0x000000ffL +#define XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__SHIFT 0x00000000 +#define XDMA_MSTR_REMOTE_SURFACE_BASE__XDMA_MSTR_REMOTE_SURFACE_BASE_MASK 0xffffffffL +#define XDMA_MSTR_REMOTE_SURFACE_BASE__XDMA_MSTR_REMOTE_SURFACE_BASE__SHIFT 0x00000000 +#define XDMA_MSTR_STATUS__XDMA_MSTR_VCOUNT_CURRENT_MASK 0x00003fffL +#define XDMA_MSTR_STATUS__XDMA_MSTR_VCOUNT_CURRENT__SHIFT 0x00000000 +#define XDMA_MSTR_STATUS__XDMA_MSTR_WRITE_LINE_CURRENT_MASK 0x3fff0000L +#define XDMA_MSTR_STATUS__XDMA_MSTR_WRITE_LINE_CURRENT__SHIFT 0x00000010 +#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_DELAY_MASK 0x00000007L +#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_DELAY__SHIFT 0x00000000 +#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_TIMEOUT_DIS_MASK 0x00000008L +#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_TIMEOUT_DIS__SHIFT 0x00000003 +#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_TIMEOUT_DELAY_MASK 0xffff8000L +#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_TIMEOUT_DELAY__SHIFT 0x0000000f +#define XDMA_SLV_CNTL__XDMA_SLV_ACTIVE_MASK 0x00000100L +#define XDMA_SLV_CNTL__XDMA_SLV_ACTIVE__SHIFT 0x00000008 +#define XDMA_SLV_CNTL__XDMA_SLV_ENABLE_MASK 0x00010000L +#define XDMA_SLV_CNTL__XDMA_SLV_ENABLE__SHIFT 0x00000010 +#define XDMA_SLV_CNTL__XDMA_SLV_MEM_READY_MASK 0x00000200L +#define XDMA_SLV_CNTL__XDMA_SLV_MEM_READY__SHIFT 0x00000009 +#define XDMA_SLV_CNTL__XDMA_SLV_READ_LAT_TEST_EN_MASK 0x00080000L +#define XDMA_SLV_CNTL__XDMA_SLV_READ_LAT_TEST_EN__SHIFT 0x00000013 +#define XDMA_SLV_CNTL__XDMA_SLV_SOFT_RESET_MASK 0x00100000L +#define XDMA_SLV_CNTL__XDMA_SLV_SOFT_RESET__SHIFT 0x00000014 +#define XDMA_SLV_FLIP_PENDING__XDMA_SLV_FLIP_PENDING_MASK 0x00000001L +#define XDMA_SLV_FLIP_PENDING__XDMA_SLV_FLIP_PENDING__SHIFT 0x00000000 +#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_PRIV_MASK 0x00010000L +#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_PRIV__SHIFT 0x00000010 +#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_SWAP_MASK 0x00000300L +#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_SWAP__SHIFT 0x00000008 +#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_VMID_MASK 0x0000f000L +#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_VMID__SHIFT 0x0000000c +#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_CLR_MASK 0x80000000L +#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_CLR__SHIFT 0x0000001f +#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_MASK 0x00030000L +#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK__SHIFT 0x00000010 +#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_TAG_MASK 0x0000ffffL +#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_TAG__SHIFT 0x00000000 +#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_CLR_MASK 0x00010000L +#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_CLR__SHIFT 0x00000010 +#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_MASK 0x00003000L +#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK__SHIFT 0x0000000c +#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_TAG_MASK 0x000003ffL +#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_TAG__SHIFT 0x00000000 +#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_ACC_MASK 0x000fffffL +#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_ACC__SHIFT 0x00000000 +#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_COUNT_MASK 0xfff00000L +#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_COUNT__SHIFT 0x00000014 +#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MAX_MASK 0xffff0000L +#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MAX__SHIFT 0x00000010 +#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MIN_MASK 0x0000ffffL +#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MIN__SHIFT 0x00000000 +#define XDMA_SLV_READ_LATENCY_TIMER__XDMA_SLV_READ_LATENCY_TIMER_MASK 0x0000ffffL +#define XDMA_SLV_READ_LATENCY_TIMER__XDMA_SLV_READ_LATENCY_TIMER__SHIFT 0x00000000 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_CLIENT_STALL_MASK 0x00000001L +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_CLIENT_STALL__SHIFT 0x00000000 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_STALL_DELAY_MASK 0x0000f000L +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_STALL_DELAY__SHIFT 0x0000000c +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LEVEL_MASK 0x00000f00L +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LEVEL__SHIFT 0x00000008 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LIMIT_MASK 0x000000f0L +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LIMIT__SHIFT 0x00000004 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_TIMER_MASK 0xffff0000L +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_TIMER__SHIFT 0x00000010 +#define XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH_MASK 0x000000ffL +#define XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__SHIFT 0x00000000 +#define XDMA_SLV_REMOTE_GPU_ADDRESS__XDMA_SLV_REMOTE_GPU_ADDRESS_MASK 0xffffffffL +#define XDMA_SLV_REMOTE_GPU_ADDRESS__XDMA_SLV_REMOTE_GPU_ADDRESS__SHIFT 0x00000000 +#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_PITCH_MASK 0x00003fffL +#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_PITCH__SHIFT 0x00000000 +#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_WIDTH_MASK 0x3fff0000L +#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_WIDTH__SHIFT 0x00000010 +#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_PERIOD_MASK 0xffff0000L +#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_PERIOD__SHIFT 0x00000010 +#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_SIZE_MASK 0x000001ffL +#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_SIZE__SHIFT 0x00000000 +#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_DELAY_MASK 0x0000f000L +#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_DELAY__SHIFT 0x0000000c +#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_MASK 0x00000001L +#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL__SHIFT 0x00000000 +#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_URGENT_LEVEL_MASK 0x00000f00L +#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_URGENT_LEVEL__SHIFT 0x00000008 +#define XDMA_TEST_DEBUG_DATA__XDMA_TEST_DEBUG_DATA_MASK 0xffffffffL +#define XDMA_TEST_DEBUG_DATA__XDMA_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h new file mode 100644 index 000000000000..c75aee25619e --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h @@ -0,0 +1,1784 @@ +/* + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef GFX_6_0_D_H +#define GFX_6_0_D_H + +#define ixCLIPPER_DEBUG_REG00 0x0000 +#define ixCLIPPER_DEBUG_REG01 0x0001 +#define ixCLIPPER_DEBUG_REG02 0x0002 +#define ixCLIPPER_DEBUG_REG03 0x0003 +#define ixCLIPPER_DEBUG_REG04 0x0004 +#define ixCLIPPER_DEBUG_REG05 0x0005 +#define ixCLIPPER_DEBUG_REG06 0x0006 +#define ixCLIPPER_DEBUG_REG07 0x0007 +#define ixCLIPPER_DEBUG_REG08 0x0008 +#define ixCLIPPER_DEBUG_REG09 0x0009 +#define ixCLIPPER_DEBUG_REG10 0x000A +#define ixCLIPPER_DEBUG_REG11 0x000B +#define ixCLIPPER_DEBUG_REG12 0x000C +#define ixCLIPPER_DEBUG_REG13 0x000D +#define ixCLIPPER_DEBUG_REG14 0x000E +#define ixCLIPPER_DEBUG_REG15 0x000F +#define ixCLIPPER_DEBUG_REG16 0x0010 +#define ixCLIPPER_DEBUG_REG17 0x0011 +#define ixCLIPPER_DEBUG_REG18 0x0012 +#define ixCLIPPER_DEBUG_REG19 0x0013 +#define ixGDS_DEBUG_REG0 0x0000 +#define ixGDS_DEBUG_REG1 0x0001 +#define ixGDS_DEBUG_REG2 0x0002 +#define ixGDS_DEBUG_REG3 0x0003 +#define ixGDS_DEBUG_REG4 0x0004 +#define ixGDS_DEBUG_REG5 0x0005 +#define ixGDS_DEBUG_REG6 0x0006 +#define ixIA_DEBUG_REG0 0x0000 +#define ixIA_DEBUG_REG1 0x0001 +#define ixIA_DEBUG_REG2 0x0002 +#define ixIA_DEBUG_REG3 0x0003 +#define ixIA_DEBUG_REG4 0x0004 +#define ixIA_DEBUG_REG5 0x0005 +#define ixIA_DEBUG_REG6 0x0006 +#define ixIA_DEBUG_REG7 0x0007 +#define ixIA_DEBUG_REG8 0x0008 +#define ixIA_DEBUG_REG9 0x0009 +#define ixPA_SC_DEBUG_REG0 0x0000 +#define ixPA_SC_DEBUG_REG1 0x0001 +#define ixSETUP_DEBUG_REG0 0x0018 +#define ixSETUP_DEBUG_REG1 0x0019 +#define ixSETUP_DEBUG_REG2 0x001A +#define ixSETUP_DEBUG_REG3 0x001B +#define ixSETUP_DEBUG_REG4 0x001C +#define ixSETUP_DEBUG_REG5 0x001D +#define ixSQ_DEBUG_CTRL_LOCAL 0x0009 +#define ixSQ_DEBUG_STS_LOCAL 0x0008 +#define ixSQ_INTERRUPT_WORD_AUTO 0x20C0 +#define ixSQ_INTERRUPT_WORD_CMN 0x20C0 +#define ixSQ_INTERRUPT_WORD_WAVE 0x20C0 +#define ixSQ_WAVE_EXEC_HI 0x027F +#define ixSQ_WAVE_EXEC_LO 0x027E +#define ixSQ_WAVE_GPR_ALLOC 0x0015 +#define ixSQ_WAVE_HW_ID 0x0014 +#define ixSQ_WAVE_IB_DBG0 0x001C +#define ixSQ_WAVE_IB_STS 0x0017 +#define ixSQ_WAVE_INST_DW0 0x001A +#define ixSQ_WAVE_INST_DW1 0x001B +#define ixSQ_WAVE_LDS_ALLOC 0x0016 +#define ixSQ_WAVE_M0 0x027C +#define ixSQ_WAVE_MODE 0x0011 +#define ixSQ_WAVE_PC_HI 0x0019 +#define ixSQ_WAVE_PC_LO 0x0018 +#define ixSQ_WAVE_STATUS 0x0012 +#define ixSQ_WAVE_TBA_HI 0x026D +#define ixSQ_WAVE_TBA_LO 0x026C +#define ixSQ_WAVE_TMA_HI 0x026F +#define ixSQ_WAVE_TMA_LO 0x026E +#define ixSQ_WAVE_TRAPSTS 0x0013 +#define ixSQ_WAVE_TTMP0 0x0270 +#define ixSQ_WAVE_TTMP10 0x027A +#define ixSQ_WAVE_TTMP1 0x0271 +#define ixSQ_WAVE_TTMP11 0x027B +#define ixSQ_WAVE_TTMP2 0x0272 +#define ixSQ_WAVE_TTMP3 0x0273 +#define ixSQ_WAVE_TTMP4 0x0274 +#define ixSQ_WAVE_TTMP5 0x0275 +#define ixSQ_WAVE_TTMP6 0x0276 +#define ixSQ_WAVE_TTMP7 0x0277 +#define ixSQ_WAVE_TTMP8 0x0278 +#define ixSQ_WAVE_TTMP9 0x0279 +#define ixSXIFCCG_DEBUG_REG0 0x0014 +#define ixSXIFCCG_DEBUG_REG1 0x0015 +#define ixSXIFCCG_DEBUG_REG2 0x0016 +#define ixSXIFCCG_DEBUG_REG3 0x0017 +#define ixVGT_DEBUG_REG0 0x0000 +#define ixVGT_DEBUG_REG10 0x000A +#define ixVGT_DEBUG_REG1 0x0001 +#define ixVGT_DEBUG_REG11 0x000B +#define ixVGT_DEBUG_REG12 0x000C +#define ixVGT_DEBUG_REG13 0x000D +#define ixVGT_DEBUG_REG14 0x000E +#define ixVGT_DEBUG_REG15 0x000F +#define ixVGT_DEBUG_REG16 0x0010 +#define ixVGT_DEBUG_REG17 0x0011 +#define ixVGT_DEBUG_REG18 0x0012 +#define ixVGT_DEBUG_REG19 0x0013 +#define ixVGT_DEBUG_REG20 0x0014 +#define ixVGT_DEBUG_REG2 0x0002 +#define ixVGT_DEBUG_REG21 0x0015 +#define ixVGT_DEBUG_REG22 0x0016 +#define ixVGT_DEBUG_REG23 0x0017 +#define ixVGT_DEBUG_REG24 0x0018 +#define ixVGT_DEBUG_REG25 0x0019 +#define ixVGT_DEBUG_REG26 0x001A +#define ixVGT_DEBUG_REG27 0x001B +#define ixVGT_DEBUG_REG28 0x001C +#define ixVGT_DEBUG_REG29 0x001D +#define ixVGT_DEBUG_REG30 0x001E +#define ixVGT_DEBUG_REG3 0x0003 +#define ixVGT_DEBUG_REG31 0x001F +#define ixVGT_DEBUG_REG32 0x0020 +#define ixVGT_DEBUG_REG33 0x0021 +#define ixVGT_DEBUG_REG34 0x0022 +#define ixVGT_DEBUG_REG35 0x0023 +#define ixVGT_DEBUG_REG36 0x0024 +#define ixVGT_DEBUG_REG4 0x0004 +#define ixVGT_DEBUG_REG5 0x0005 +#define ixVGT_DEBUG_REG6 0x0006 +#define ixVGT_DEBUG_REG7 0x0007 +#define ixVGT_DEBUG_REG8 0x0008 +#define ixVGT_DEBUG_REG9 0x0009 +#define mmBCI_DEBUG_READ 0x24E3 +#define mmCB_BLEND0_CONTROL 0xA1E0 +#define mmCB_BLEND1_CONTROL 0xA1E1 +#define mmCB_BLEND2_CONTROL 0xA1E2 +#define mmCB_BLEND3_CONTROL 0xA1E3 +#define mmCB_BLEND4_CONTROL 0xA1E4 +#define mmCB_BLEND5_CONTROL 0xA1E5 +#define mmCB_BLEND6_CONTROL 0xA1E6 +#define mmCB_BLEND7_CONTROL 0xA1E7 +#define mmCB_BLEND_ALPHA 0xA108 +#define mmCB_BLEND_BLUE 0xA107 +#define mmCB_BLEND_GREEN 0xA106 +#define mmCB_BLEND_RED 0xA105 +#define mmCB_CGTT_SCLK_CTRL 0x2698 +#define mmCB_COLOR0_ATTRIB 0xA31D +#define mmCB_COLOR0_BASE 0xA318 +#define mmCB_COLOR0_CLEAR_WORD0 0xA323 +#define mmCB_COLOR0_CLEAR_WORD1 0xA324 +#define mmCB_COLOR0_CMASK 0xA31F +#define mmCB_COLOR0_CMASK_SLICE 0xA320 +#define mmCB_COLOR0_FMASK 0xA321 +#define mmCB_COLOR0_FMASK_SLICE 0xA322 +#define mmCB_COLOR0_INFO 0xA31C +#define mmCB_COLOR0_PITCH 0xA319 +#define mmCB_COLOR0_SLICE 0xA31A +#define mmCB_COLOR0_VIEW 0xA31B +#define mmCB_COLOR1_ATTRIB 0xA32C +#define mmCB_COLOR1_BASE 0xA327 +#define mmCB_COLOR1_CLEAR_WORD0 0xA332 +#define mmCB_COLOR1_CLEAR_WORD1 0xA333 +#define mmCB_COLOR1_CMASK 0xA32E +#define mmCB_COLOR1_CMASK_SLICE 0xA32F +#define mmCB_COLOR1_FMASK 0xA330 +#define mmCB_COLOR1_FMASK_SLICE 0xA331 +#define mmCB_COLOR1_INFO 0xA32B +#define mmCB_COLOR1_PITCH 0xA328 +#define mmCB_COLOR1_SLICE 0xA329 +#define mmCB_COLOR1_VIEW 0xA32A +#define mmCB_COLOR2_ATTRIB 0xA33B +#define mmCB_COLOR2_BASE 0xA336 +#define mmCB_COLOR2_CLEAR_WORD0 0xA341 +#define mmCB_COLOR2_CLEAR_WORD1 0xA342 +#define mmCB_COLOR2_CMASK 0xA33D +#define mmCB_COLOR2_CMASK_SLICE 0xA33E +#define mmCB_COLOR2_FMASK 0xA33F +#define mmCB_COLOR2_FMASK_SLICE 0xA340 +#define mmCB_COLOR2_INFO 0xA33A +#define mmCB_COLOR2_PITCH 0xA337 +#define mmCB_COLOR2_SLICE 0xA338 +#define mmCB_COLOR2_VIEW 0xA339 +#define mmCB_COLOR3_ATTRIB 0xA34A +#define mmCB_COLOR3_BASE 0xA345 +#define mmCB_COLOR3_CLEAR_WORD0 0xA350 +#define mmCB_COLOR3_CLEAR_WORD1 0xA351 +#define mmCB_COLOR3_CMASK 0xA34C +#define mmCB_COLOR3_CMASK_SLICE 0xA34D +#define mmCB_COLOR3_FMASK 0xA34E +#define mmCB_COLOR3_FMASK_SLICE 0xA34F +#define mmCB_COLOR3_INFO 0xA349 +#define mmCB_COLOR3_PITCH 0xA346 +#define mmCB_COLOR3_SLICE 0xA347 +#define mmCB_COLOR3_VIEW 0xA348 +#define mmCB_COLOR4_ATTRIB 0xA359 +#define mmCB_COLOR4_BASE 0xA354 +#define mmCB_COLOR4_CLEAR_WORD0 0xA35F +#define mmCB_COLOR4_CLEAR_WORD1 0xA360 +#define mmCB_COLOR4_CMASK 0xA35B +#define mmCB_COLOR4_CMASK_SLICE 0xA35C +#define mmCB_COLOR4_FMASK 0xA35D +#define mmCB_COLOR4_FMASK_SLICE 0xA35E +#define mmCB_COLOR4_INFO 0xA358 +#define mmCB_COLOR4_PITCH 0xA355 +#define mmCB_COLOR4_SLICE 0xA356 +#define mmCB_COLOR4_VIEW 0xA357 +#define mmCB_COLOR5_ATTRIB 0xA368 +#define mmCB_COLOR5_BASE 0xA363 +#define mmCB_COLOR5_CLEAR_WORD0 0xA36E +#define mmCB_COLOR5_CLEAR_WORD1 0xA36F +#define mmCB_COLOR5_CMASK 0xA36A +#define mmCB_COLOR5_CMASK_SLICE 0xA36B +#define mmCB_COLOR5_FMASK 0xA36C +#define mmCB_COLOR5_FMASK_SLICE 0xA36D +#define mmCB_COLOR5_INFO 0xA367 +#define mmCB_COLOR5_PITCH 0xA364 +#define mmCB_COLOR5_SLICE 0xA365 +#define mmCB_COLOR5_VIEW 0xA366 +#define mmCB_COLOR6_ATTRIB 0xA377 +#define mmCB_COLOR6_BASE 0xA372 +#define mmCB_COLOR6_CLEAR_WORD0 0xA37D +#define mmCB_COLOR6_CLEAR_WORD1 0xA37E +#define mmCB_COLOR6_CMASK 0xA379 +#define mmCB_COLOR6_CMASK_SLICE 0xA37A +#define mmCB_COLOR6_FMASK 0xA37B +#define mmCB_COLOR6_FMASK_SLICE 0xA37C +#define mmCB_COLOR6_INFO 0xA376 +#define mmCB_COLOR6_PITCH 0xA373 +#define mmCB_COLOR6_SLICE 0xA374 +#define mmCB_COLOR6_VIEW 0xA375 +#define mmCB_COLOR7_ATTRIB 0xA386 +#define mmCB_COLOR7_BASE 0xA381 +#define mmCB_COLOR7_CLEAR_WORD0 0xA38C +#define mmCB_COLOR7_CLEAR_WORD1 0xA38D +#define mmCB_COLOR7_CMASK 0xA388 +#define mmCB_COLOR7_CMASK_SLICE 0xA389 +#define mmCB_COLOR7_FMASK 0xA38A +#define mmCB_COLOR7_FMASK_SLICE 0xA38B +#define mmCB_COLOR7_INFO 0xA385 +#define mmCB_COLOR7_PITCH 0xA382 +#define mmCB_COLOR7_SLICE 0xA383 +#define mmCB_COLOR7_VIEW 0xA384 +#define mmCB_COLOR_CONTROL 0xA202 +#define mmCB_DEBUG_BUS_10 0x26A2 +#define mmCB_DEBUG_BUS_1 0x2699 +#define mmCB_DEBUG_BUS_11 0x26A3 +#define mmCB_DEBUG_BUS_12 0x26A4 +#define mmCB_DEBUG_BUS_13 0x26A5 +#define mmCB_DEBUG_BUS_14 0x26A6 +#define mmCB_DEBUG_BUS_15 0x26A7 +#define mmCB_DEBUG_BUS_16 0x26A8 +#define mmCB_DEBUG_BUS_17 0x26A9 +#define mmCB_DEBUG_BUS_18 0x26AA +#define mmCB_DEBUG_BUS_2 0x269A +#define mmCB_DEBUG_BUS_3 0x269B +#define mmCB_DEBUG_BUS_4 0x269C +#define mmCB_DEBUG_BUS_5 0x269D +#define mmCB_DEBUG_BUS_6 0x269E +#define mmCB_DEBUG_BUS_7 0x269F +#define mmCB_DEBUG_BUS_8 0x26A0 +#define mmCB_DEBUG_BUS_9 0x26A1 +#define mmCB_HW_CONTROL 0x2684 +#define mmCB_HW_CONTROL_1 0x2685 +#define mmCB_HW_CONTROL_2 0x2686 +#define mmCB_PERFCOUNTER0_HI 0x2691 +#define mmCB_PERFCOUNTER0_LO 0x2690 +#define mmCB_PERFCOUNTER0_SELECT1 0x2689 +#define mmCB_PERFCOUNTER1_HI 0x2693 +#define mmCB_PERFCOUNTER1_LO 0x2692 +#define mmCB_PERFCOUNTER2_HI 0x2695 +#define mmCB_PERFCOUNTER2_LO 0x2694 +#define mmCB_PERFCOUNTER3_HI 0x2697 +#define mmCB_PERFCOUNTER3_LO 0x2696 +#define mmCB_SHADER_MASK 0xA08F +#define mmCB_TARGET_MASK 0xA08E +#define mmCC_GC_SHADER_ARRAY_CONFIG 0x226F +#define mmCC_RB_BACKEND_DISABLE 0x263D +#define mmCC_RB_DAISY_CHAIN 0x2641 +#define mmCC_RB_REDUNDANCY 0x263C +#define mmCC_SQC_BANK_DISABLE 0x2307 +#define mmCGTS_RD_CTRL_REG 0x2455 +#define mmCGTS_RD_REG 0x2456 +#define mmCGTS_SM_CTRL_REG 0x2454 +#define mmCGTS_TCC_DISABLE 0x2452 +#define mmCGTS_USER_TCC_DISABLE 0x2453 +#define mmCGTT_BCI_CLK_CTRL 0x24A9 +#define mmCGTT_CP_CLK_CTRL 0x3059 +#define mmCGTT_GDS_CLK_CTRL 0x25DD +#define mmCGTT_IA_CLK_CTRL 0x2261 +#define mmCGTT_PA_CLK_CTRL 0x2286 +#define mmCGTT_PC_CLK_CTRL 0x24A8 +#define mmCGTT_RLC_CLK_CTRL 0x30E0 +#define mmCGTT_SC_CLK_CTRL 0x22CA +#define mmCGTT_SPI_CLK_CTRL 0x2451 +#define mmCGTT_SQ_CLK_CTRL 0x2362 +#define mmCGTT_SQG_CLK_CTRL 0x2363 +#define mmCGTT_SX_CLK_CTRL0 0x240C +#define mmCGTT_SX_CLK_CTRL1 0x240D +#define mmCGTT_SX_CLK_CTRL2 0x240E +#define mmCGTT_SX_CLK_CTRL3 0x240F +#define mmCGTT_SX_CLK_CTRL4 0x2410 +#define mmCGTT_TCI_CLK_CTRL 0x2B60 +#define mmCGTT_TCP_CLK_CTRL 0x2B15 +#define mmCGTT_VGT_CLK_CTRL 0x225F +#define mmCOHER_DEST_BASE_0 0xA092 +#define mmCOHER_DEST_BASE_1 0xA093 +#define mmCOHER_DEST_BASE_2 0xA07E +#define mmCOHER_DEST_BASE_3 0xA07F +#define mmCOMPUTE_DIM_X 0x2E01 +#define mmCOMPUTE_DIM_Y 0x2E02 +#define mmCOMPUTE_DIM_Z 0x2E03 +#define mmCOMPUTE_DISPATCH_INITIATOR 0x2E00 +#define mmCOMPUTE_NUM_THREAD_X 0x2E07 +#define mmCOMPUTE_NUM_THREAD_Y 0x2E08 +#define mmCOMPUTE_NUM_THREAD_Z 0x2E09 +#define mmCOMPUTE_PGM_HI 0x2E0D +#define mmCOMPUTE_PGM_LO 0x2E0C +#define mmCOMPUTE_PGM_RSRC1 0x2E12 +#define mmCOMPUTE_PGM_RSRC2 0x2E13 +#define mmCOMPUTE_RESOURCE_LIMITS 0x2E15 +#define mmCOMPUTE_START_X 0x2E04 +#define mmCOMPUTE_START_Y 0x2E05 +#define mmCOMPUTE_START_Z 0x2E06 +#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0 0x2E16 +#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1 0x2E17 +#define mmCOMPUTE_TBA_HI 0x2E0F +#define mmCOMPUTE_TBA_LO 0x2E0E +#define mmCOMPUTE_TMA_HI 0x2E11 +#define mmCOMPUTE_TMA_LO 0x2E10 +#define mmCOMPUTE_TMPRING_SIZE 0x2E18 +#define mmCOMPUTE_USER_DATA_0 0x2E40 +#define mmCOMPUTE_USER_DATA_10 0x2E4A +#define mmCOMPUTE_USER_DATA_1 0x2E41 +#define mmCOMPUTE_USER_DATA_11 0x2E4B +#define mmCOMPUTE_USER_DATA_12 0x2E4C +#define mmCOMPUTE_USER_DATA_13 0x2E4D +#define mmCOMPUTE_USER_DATA_14 0x2E4E +#define mmCOMPUTE_USER_DATA_15 0x2E4F +#define mmCOMPUTE_USER_DATA_2 0x2E42 +#define mmCOMPUTE_USER_DATA_3 0x2E43 +#define mmCOMPUTE_USER_DATA_4 0x2E44 +#define mmCOMPUTE_USER_DATA_5 0x2E45 +#define mmCOMPUTE_USER_DATA_6 0x2E46 +#define mmCOMPUTE_USER_DATA_7 0x2E47 +#define mmCOMPUTE_USER_DATA_8 0x2E48 +#define mmCOMPUTE_USER_DATA_9 0x2E49 +#define mmCOMPUTE_VMID 0x2E14 +#define mmCP_APPEND_ADDR_HI 0x2159 +#define mmCP_APPEND_ADDR_LO 0x2158 +#define mmCP_APPEND_DATA 0x215A +#define mmCP_APPEND_LAST_CS_FENCE 0x215B +#define mmCP_APPEND_LAST_PS_FENCE 0x215C +#define mmCP_ATOMIC_PREOP_HI 0x215E +#define mmCP_ATOMIC_PREOP_LO 0x215D +#define mmCP_BUSY_STAT 0x219F +#define mmCP_CE_HEADER_DUMP 0x21A4 +#define mmCP_CE_IB1_BASE_HI 0x21C7 +#define mmCP_CE_IB1_BASE_LO 0x21C6 +#define mmCP_CE_IB1_BUFSZ 0x21C8 +#define mmCP_CE_IB2_BASE_HI 0x21CA +#define mmCP_CE_IB2_BASE_LO 0x21C9 +#define mmCP_CE_IB2_BUFSZ 0x21CB +#define mmCP_CE_INIT_BASE_HI 0x21C4 +#define mmCP_CE_INIT_BASE_LO 0x21C3 +#define mmCP_CE_INIT_BUFSZ 0x21C5 +#define mmCP_CEQ1_AVAIL 0x21E6 +#define mmCP_CEQ2_AVAIL 0x21E7 +#define mmCP_CE_ROQ_IB1_STAT 0x21E9 +#define mmCP_CE_ROQ_IB2_STAT 0x21EA +#define mmCP_CE_ROQ_RB_STAT 0x21E8 +#define mmCP_CE_UCODE_ADDR 0x305A +#define mmCP_CE_UCODE_DATA 0x305B +#define mmCP_CMD_DATA 0x21DF +#define mmCP_CMD_INDEX 0x21DE +#define mmCP_CNTX_STAT 0x21B8 +#define mmCP_COHER_BASE 0x217E +#define mmCP_COHER_CNTL 0x217C +#define mmCP_COHER_SIZE 0x217D +#define mmCP_COHER_START_DELAY 0x217B +#define mmCP_COHER_STATUS 0x217F +#define mmCP_CSF_CNTL 0x21B5 +#define mmCP_CSF_STAT 0x21B4 +#define mmCP_DMA_CNTL 0x218A +#define mmCP_DMA_ME_COMMAND 0x2184 +#define mmCP_DMA_ME_DST_ADDR 0x2182 +#define mmCP_DMA_ME_DST_ADDR_HI 0x2183 +#define mmCP_DMA_ME_SRC_ADDR 0x2180 +#define mmCP_DMA_ME_SRC_ADDR_HI 0x2181 +#define mmCP_DMA_PFP_COMMAND 0x2189 +#define mmCP_DMA_PFP_DST_ADDR 0x2187 +#define mmCP_DMA_PFP_DST_ADDR_HI 0x2188 +#define mmCP_DMA_PFP_SRC_ADDR 0x2185 +#define mmCP_DMA_PFP_SRC_ADDR_HI 0x2186 +#define mmCP_DMA_READ_TAGS 0x218B +#define mmCP_ECC_FIRSTOCCURRENCE 0x307A +#define mmCP_ECC_FIRSTOCCURRENCE_RING0 0x307B +#define mmCP_ECC_FIRSTOCCURRENCE_RING1 0x307C +#define mmCP_ECC_FIRSTOCCURRENCE_RING2 0x307D +#define mmCP_EOP_DONE_ADDR_HI 0x2101 +#define mmCP_EOP_DONE_ADDR_LO 0x2100 +#define mmCP_EOP_DONE_DATA_HI 0x2103 +#define mmCP_EOP_DONE_DATA_LO 0x2102 +#define mmCP_EOP_LAST_FENCE_HI 0x2105 +#define mmCP_EOP_LAST_FENCE_LO 0x2104 +#define mmCP_GDS_ATOMIC0_PREOP_HI 0x2160 +#define mmCP_GDS_ATOMIC0_PREOP_LO 0x215F +#define mmCP_GDS_ATOMIC1_PREOP_HI 0x2162 +#define mmCP_GDS_ATOMIC1_PREOP_LO 0x2161 +#define mmCP_GRBM_FREE_COUNT 0x21A3 +#define mmCP_IB1_BASE_HI 0x21CD +#define mmCP_IB1_BASE_LO 0x21CC +#define mmCP_IB1_BUFSZ 0x21CE +#define mmCP_IB1_OFFSET 0x2192 +#define mmCP_IB1_PREAMBLE_BEGIN 0x2194 +#define mmCP_IB1_PREAMBLE_END 0x2195 +#define mmCP_IB2_BASE_HI 0x21D0 +#define mmCP_IB2_BASE_LO 0x21CF +#define mmCP_IB2_BUFSZ 0x21D1 +#define mmCP_IB2_OFFSET 0x2193 +#define mmCP_IB2_PREAMBLE_BEGIN 0x2196 +#define mmCP_IB2_PREAMBLE_END 0x2197 +#define mmCP_INT_CNTL 0x3049 +#define mmCP_INT_CNTL_RING0 0x306A +#define mmCP_INT_CNTL_RING1 0x306B +#define mmCP_INT_CNTL_RING2 0x306C +#define mmCP_INT_STAT_DEBUG 0x21F7 +#define mmCP_INT_STATUS 0x304A +#define mmCP_INT_STATUS_RING0 0x306D +#define mmCP_INT_STATUS_RING1 0x306E +#define mmCP_INT_STATUS_RING2 0x306F +#define mmCP_MC_PACK_DELAY_CNT 0x21A7 +#define mmCP_ME_CNTL 0x21B6 +#define mmCP_ME_HEADER_DUMP 0x21A1 +#define mmCP_ME_MC_RADDR_HI 0x216E +#define mmCP_ME_MC_RADDR_LO 0x216D +#define mmCP_ME_MC_WADDR_HI 0x216A +#define mmCP_ME_MC_WADDR_LO 0x2169 +#define mmCP_ME_MC_WDATA_HI 0x216C +#define mmCP_ME_MC_WDATA_LO 0x216B +#define mmCP_MEM_SLP_CNTL 0x3079 +#define mmCP_ME_PREEMPTION 0x21B9 +#define mmCP_MEQ_AVAIL 0x21DD +#define mmCP_MEQ_STAT 0x21E5 +#define mmCP_MEQ_THRESHOLDS 0x21D9 +#define mmCP_ME_RAM_DATA 0x3058 +#define mmCP_ME_RAM_RADDR 0x3056 +#define mmCP_ME_RAM_WADDR 0x3057 +#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI 0x210B +#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO 0x210A +#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI 0x210F +#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO 0x210E +#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI 0x2113 +#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO 0x2112 +#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI 0x2117 +#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO 0x2116 +#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI 0x2109 +#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO 0x2108 +#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI 0x210D +#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO 0x210C +#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI 0x2111 +#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO 0x2110 +#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI 0x2115 +#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO 0x2114 +#define mmCP_PA_CINVOC_COUNT_HI 0x2129 +#define mmCP_PA_CINVOC_COUNT_LO 0x2128 +#define mmCP_PA_CPRIM_COUNT_HI 0x212B +#define mmCP_PA_CPRIM_COUNT_LO 0x212A +#define mmCP_PERFMON_CNTL 0x21FF +#define mmCP_PERFMON_CNTX_CNTL 0xA0D8 +#define mmCP_PFP_HEADER_DUMP 0x21A2 +#define mmCP_PFP_IB_CONTROL 0x218D +#define mmCP_PFP_LOAD_CONTROL 0x218E +#define mmCP_PFP_UCODE_ADDR 0x3054 +#define mmCP_PFP_UCODE_DATA 0x3055 +#define mmCP_PIPE_STATS_ADDR_HI 0x2119 +#define mmCP_PIPE_STATS_ADDR_LO 0x2118 +#define mmCP_PWR_CNTL 0x3078 +#define mmCP_QUEUE_THRESHOLDS 0x21D8 +#define mmCP_RB0_BASE 0x3040 +#define mmCP_RB0_CNTL 0x3041 +#define mmCP_RB0_RPTR 0x21C0 +#define mmCP_RB0_RPTR_ADDR 0x3043 +#define mmCP_RB0_RPTR_ADDR_HI 0x3044 +#define mmCP_RB0_WPTR 0x3045 +#define mmCP_RB1_BASE 0x3060 +#define mmCP_RB1_CNTL 0x3061 +#define mmCP_RB1_RPTR 0x21BF +#define mmCP_RB1_RPTR_ADDR 0x3062 +#define mmCP_RB1_RPTR_ADDR_HI 0x3063 +#define mmCP_RB1_WPTR 0x3064 +#define mmCP_RB2_BASE 0x3065 +#define mmCP_RB2_CNTL 0x3066 +#define mmCP_RB2_RPTR 0x21BE +#define mmCP_RB2_RPTR_ADDR 0x3067 +#define mmCP_RB2_RPTR_ADDR_HI 0x3068 +#define mmCP_RB2_WPTR 0x3069 +#define mmCP_RB_BASE 0x3040 +#define mmCP_RB_CNTL 0x3041 +#define mmCP_RB_OFFSET 0x2191 +#define mmCP_RB_RPTR 0x21C0 +#define mmCP_RB_RPTR_ADDR 0x3043 +#define mmCP_RB_RPTR_ADDR_HI 0x3044 +#define mmCP_RB_RPTR_WR 0x3042 +#define mmCP_RB_VMID 0x3051 +#define mmCP_RB_WPTR 0x3045 +#define mmCP_RB_WPTR_DELAY 0x21C1 +#define mmCP_RB_WPTR_POLL_ADDR_HI 0x3047 +#define mmCP_RB_WPTR_POLL_ADDR_LO 0x3046 +#define mmCP_RB_WPTR_POLL_CNTL 0x21C2 +#define mmCP_RING0_PRIORITY 0x304D +#define mmCP_RING1_PRIORITY 0x304E +#define mmCP_RING2_PRIORITY 0x304F +#define mmCP_RINGID 0xA0D9 +#define mmCP_RING_PRIORITY_CNTS 0x304C +#define mmCP_ROQ1_THRESHOLDS 0x21D5 +#define mmCP_ROQ2_AVAIL 0x21DC +#define mmCP_ROQ2_THRESHOLDS 0x21D6 +#define mmCP_ROQ_AVAIL 0x21DA +#define mmCP_ROQ_IB1_STAT 0x21E1 +#define mmCP_ROQ_IB2_STAT 0x21E2 +#define mmCP_ROQ_RB_STAT 0x21E0 +#define mmCP_SC_PSINVOC_COUNT0_HI 0x212D +#define mmCP_SC_PSINVOC_COUNT0_LO 0x212C +#define mmCP_SC_PSINVOC_COUNT1_HI 0x212F +#define mmCP_SC_PSINVOC_COUNT1_LO 0x212E +#define mmCP_SCRATCH_DATA 0x2190 +#define mmCP_SCRATCH_INDEX 0x218F +#define mmCP_SEM_INCOMPLETE_TIMER_CNTL 0x2172 +#define mmCP_SEM_WAIT_TIMER 0x216F +#define mmCP_SIG_SEM_ADDR_HI 0x2171 +#define mmCP_SIG_SEM_ADDR_LO 0x2170 +#define mmCP_STALLED_STAT1 0x219D +#define mmCP_STALLED_STAT2 0x219E +#define mmCP_STALLED_STAT3 0x219C +#define mmCP_STAT 0x21A0 +#define mmCP_ST_BASE_HI 0x21D3 +#define mmCP_ST_BASE_LO 0x21D2 +#define mmCP_ST_BUFSZ 0x21D4 +#define mmCP_STQ_AVAIL 0x21DB +#define mmCP_STQ_STAT 0x21E3 +#define mmCP_STQ_THRESHOLDS 0x21D7 +#define mmCP_STREAM_OUT_ADDR_HI 0x2107 +#define mmCP_STREAM_OUT_ADDR_LO 0x2106 +#define mmCP_STRMOUT_CNTL 0x213F +#define mmCP_VGT_CSINVOC_COUNT_HI 0x2131 +#define mmCP_VGT_CSINVOC_COUNT_LO 0x2130 +#define mmCP_VGT_DSINVOC_COUNT_HI 0x2127 +#define mmCP_VGT_DSINVOC_COUNT_LO 0x2126 +#define mmCP_VGT_GSINVOC_COUNT_HI 0x2123 +#define mmCP_VGT_GSINVOC_COUNT_LO 0x2122 +#define mmCP_VGT_GSPRIM_COUNT_HI 0x211F +#define mmCP_VGT_GSPRIM_COUNT_LO 0x211E +#define mmCP_VGT_HSINVOC_COUNT_HI 0x2125 +#define mmCP_VGT_HSINVOC_COUNT_LO 0x2124 +#define mmCP_VGT_IAPRIM_COUNT_HI 0x211D +#define mmCP_VGT_IAPRIM_COUNT_LO 0x211C +#define mmCP_VGT_IAVERT_COUNT_HI 0x211B +#define mmCP_VGT_IAVERT_COUNT_LO 0x211A +#define mmCP_VGT_VSINVOC_COUNT_HI 0x2121 +#define mmCP_VGT_VSINVOC_COUNT_LO 0x2120 +#define mmCP_VMID 0xA0DA +#define mmCP_WAIT_REG_MEM_TIMEOUT 0x2174 +#define mmCP_WAIT_SEM_ADDR_HI 0x2176 +#define mmCP_WAIT_SEM_ADDR_LO 0x2175 +#define mmCS_COPY_STATE 0xA1F3 +#define mmDB_ALPHA_TO_MASK 0xA2DC +#define mmDB_CGTT_CLK_CTRL_0 0x261A +#define mmDB_COUNT_CONTROL 0xA001 +#define mmDB_CREDIT_LIMIT 0x2614 +#define mmDB_DEBUG 0x260C +#define mmDB_DEBUG2 0x260D +#define mmDB_DEBUG3 0x260E +#define mmDB_DEBUG4 0x260F +#define mmDB_DEPTH_BOUNDS_MAX 0xA009 +#define mmDB_DEPTH_BOUNDS_MIN 0xA008 +#define mmDB_DEPTH_CLEAR 0xA00B +#define mmDB_DEPTH_CONTROL 0xA200 +#define mmDB_DEPTH_INFO 0xA00F +#define mmDB_DEPTH_SIZE 0xA016 +#define mmDB_DEPTH_SLICE 0xA017 +#define mmDB_DEPTH_VIEW 0xA002 +#define mmDB_EQAA 0xA201 +#define mmDB_FIFO_DEPTH1 0x2618 +#define mmDB_FIFO_DEPTH2 0x2619 +#define mmDB_FREE_CACHELINES 0x2617 +#define mmDB_HTILE_DATA_BASE 0xA005 +#define mmDB_HTILE_SURFACE 0xA2AF +#define mmDB_PERFCOUNTER0_HI 0x2602 +#define mmDB_PERFCOUNTER0_LO 0x2601 +#define mmDB_PERFCOUNTER0_SELECT 0x2600 +#define mmDB_PERFCOUNTER1_HI 0x2605 +#define mmDB_PERFCOUNTER1_LO 0x2604 +#define mmDB_PERFCOUNTER1_SELECT 0x2603 +#define mmDB_PERFCOUNTER2_HI 0x2608 +#define mmDB_PERFCOUNTER2_LO 0x2607 +#define mmDB_PERFCOUNTER2_SELECT 0x2606 +#define mmDB_PERFCOUNTER3_HI 0x260B +#define mmDB_PERFCOUNTER3_LO 0x260A +#define mmDB_PERFCOUNTER3_SELECT 0x2609 +#define mmDB_PRELOAD_CONTROL 0xA2B2 +#define mmDB_READ_DEBUG_0 0x2620 +#define mmDB_READ_DEBUG_1 0x2621 +#define mmDB_READ_DEBUG_2 0x2622 +#define mmDB_READ_DEBUG_3 0x2623 +#define mmDB_READ_DEBUG_4 0x2624 +#define mmDB_READ_DEBUG_5 0x2625 +#define mmDB_READ_DEBUG_6 0x2626 +#define mmDB_READ_DEBUG_7 0x2627 +#define mmDB_READ_DEBUG_8 0x2628 +#define mmDB_READ_DEBUG_9 0x2629 +#define mmDB_READ_DEBUG_A 0x262A +#define mmDB_READ_DEBUG_B 0x262B +#define mmDB_READ_DEBUG_C 0x262C +#define mmDB_READ_DEBUG_D 0x262D +#define mmDB_READ_DEBUG_E 0x262E +#define mmDB_READ_DEBUG_F 0x262F +#define mmDB_RENDER_CONTROL 0xA000 +#define mmDB_RENDER_OVERRIDE 0xA003 +#define mmDB_RENDER_OVERRIDE2 0xA004 +#define mmDB_SHADER_CONTROL 0xA203 +#define mmDB_SRESULTS_COMPARE_STATE0 0xA2B0 +#define mmDB_SRESULTS_COMPARE_STATE1 0xA2B1 +#define mmDB_STENCIL_CLEAR 0xA00A +#define mmDB_STENCIL_CONTROL 0xA10B +#define mmDB_STENCIL_INFO 0xA011 +#define mmDB_STENCIL_READ_BASE 0xA013 +#define mmDB_STENCILREFMASK 0xA10C +#define mmDB_STENCILREFMASK_BF 0xA10D +#define mmDB_STENCIL_WRITE_BASE 0xA015 +#define mmDB_SUBTILE_CONTROL 0x2616 +#define mmDB_WATERMARKS 0x2615 +#define mmDB_Z_INFO 0xA010 +#define mmDB_ZPASS_COUNT_HI 0x261D +#define mmDB_ZPASS_COUNT_LOW 0x261C +#define mmDB_Z_READ_BASE 0xA012 +#define mmDB_Z_WRITE_BASE 0xA014 +#define mmDEBUG_DATA 0x203D +#define mmDEBUG_INDEX 0x203C +#define mmGB_ADDR_CONFIG 0x263E +#define mmGB_BACKEND_MAP 0x263F +#define mmGB_EDC_MODE 0x307E +#define mmGB_GPU_ID 0x2640 +#define mmGB_TILE_MODE0 0x2644 +#define mmGB_TILE_MODE10 0x264E +#define mmGB_TILE_MODE1 0x2645 +#define mmGB_TILE_MODE11 0x264F +#define mmGB_TILE_MODE12 0x2650 +#define mmGB_TILE_MODE13 0x2651 +#define mmGB_TILE_MODE14 0x2652 +#define mmGB_TILE_MODE15 0x2653 +#define mmGB_TILE_MODE16 0x2654 +#define mmGB_TILE_MODE17 0x2655 +#define mmGB_TILE_MODE18 0x2656 +#define mmGB_TILE_MODE19 0x2657 +#define mmGB_TILE_MODE20 0x2658 +#define mmGB_TILE_MODE2 0x2646 +#define mmGB_TILE_MODE21 0x2659 +#define mmGB_TILE_MODE22 0x265A +#define mmGB_TILE_MODE23 0x265B +#define mmGB_TILE_MODE24 0x265C +#define mmGB_TILE_MODE25 0x265D +#define mmGB_TILE_MODE26 0x265E +#define mmGB_TILE_MODE27 0x265F +#define mmGB_TILE_MODE28 0x2660 +#define mmGB_TILE_MODE29 0x2661 +#define mmGB_TILE_MODE30 0x2662 +#define mmGB_TILE_MODE3 0x2647 +#define mmGB_TILE_MODE31 0x2663 +#define mmGB_TILE_MODE4 0x2648 +#define mmGB_TILE_MODE5 0x2649 +#define mmGB_TILE_MODE6 0x264A +#define mmGB_TILE_MODE7 0x264B +#define mmGB_TILE_MODE8 0x264C +#define mmGB_TILE_MODE9 0x264D +#define mmGC_PRIV_MODE 0x3048 +#define mmGC_USER_RB_BACKEND_DISABLE 0x26DF +#define mmGC_USER_SHADER_ARRAY_CONFIG 0x2270 +#define mmGDS_ATOM_BASE 0x25CE +#define mmGDS_ATOM_CNTL 0x25CC +#define mmGDS_ATOM_COMPLETE 0x25CD +#define mmGDS_ATOM_DST 0x25D2 +#define mmGDS_ATOM_OFFSET0 0x25D0 +#define mmGDS_ATOM_OFFSET1 0x25D1 +#define mmGDS_ATOM_OP 0x25D3 +#define mmGDS_ATOM_READ0 0x25D8 +#define mmGDS_ATOM_READ0_U 0x25D9 +#define mmGDS_ATOM_READ1 0x25DA +#define mmGDS_ATOM_READ1_U 0x25DB +#define mmGDS_ATOM_SIZE 0x25CF +#define mmGDS_ATOM_SRC0 0x25D4 +#define mmGDS_ATOM_SRC0_U 0x25D5 +#define mmGDS_ATOM_SRC1 0x25D6 +#define mmGDS_ATOM_SRC1_U 0x25D7 +#define mmGDS_CNTL_STATUS 0x25C1 +#define mmGDS_CONFIG 0x25C0 +#define mmGDS_DEBUG_CNTL 0x25DE +#define mmGDS_DEBUG_DATA 0x25DF +#define mmGDS_ENHANCE 0x25DC +#define mmGDS_GRBM_SECDED_CNT 0x25E3 +#define mmGDS_GWS_RESOURCE 0x25E1 +#define mmGDS_GWS_RESOURCE_CNTL 0x25E0 +#define mmGDS_OA_DED 0x25E4 +#define mmGDS_PERFCOUNTER0_HI 0x25E7 +#define mmGDS_PERFCOUNTER0_LO 0x25E6 +#define mmGDS_PERFCOUNTER0_SELECT 0x25E5 +#define mmGDS_PERFCOUNTER1_HI 0x25EA +#define mmGDS_PERFCOUNTER1_LO 0x25E9 +#define mmGDS_PERFCOUNTER1_SELECT 0x25E8 +#define mmGDS_PERFCOUNTER2_HI 0x25ED +#define mmGDS_PERFCOUNTER2_LO 0x25EC +#define mmGDS_PERFCOUNTER2_SELECT 0x25EB +#define mmGDS_PERFCOUNTER3_HI 0x25F0 +#define mmGDS_PERFCOUNTER3_LO 0x25EF +#define mmGDS_PERFCOUNTER3_SELECT 0x25EE +#define mmGDS_RD_ADDR 0x25C2 +#define mmGDS_RD_BURST_ADDR 0x25C4 +#define mmGDS_RD_BURST_COUNT 0x25C5 +#define mmGDS_RD_BURST_DATA 0x25C6 +#define mmGDS_RD_DATA 0x25C3 +#define mmGDS_SECDED_CNT 0x25E2 +#define mmGDS_WR_ADDR 0x25C7 +#define mmGDS_WR_BURST_ADDR 0x25C9 +#define mmGDS_WR_BURST_DATA 0x25CA +#define mmGDS_WR_DATA 0x25C8 +#define mmGDS_WRITE_COMPLETE 0x25CB +#define mmGFX_COPY_STATE 0xA1F4 +#define mmGRBM_CAM_DATA 0x3001 +#define mmGRBM_CAM_INDEX 0x3000 +#define mmGRBM_CNTL 0x2000 +#define mmGRBM_DEBUG 0x2014 +#define mmGRBM_DEBUG_CNTL 0x2009 +#define mmGRBM_DEBUG_DATA 0x200A +#define mmGRBM_DEBUG_SNAPSHOT 0x2015 +#define mmGRBM_GFX_CLKEN_CNTL 0x200C +#define mmGRBM_GFX_INDEX 0x200B +#define mmGRBM_INT_CNTL 0x2018 +#define mmGRBM_NOWHERE 0x203F +#define mmGRBM_PERFCOUNTER0_HI 0x201F +#define mmGRBM_PERFCOUNTER0_LO 0x201E +#define mmGRBM_PERFCOUNTER0_SELECT 0x201C +#define mmGRBM_PERFCOUNTER1_HI 0x2021 +#define mmGRBM_PERFCOUNTER1_LO 0x2020 +#define mmGRBM_PERFCOUNTER1_SELECT 0x201D +#define mmGRBM_PWR_CNTL 0x2003 +#define mmGRBM_READ_ERROR 0x2016 +#define mmGRBM_SCRATCH_REG0 0x2040 +#define mmGRBM_SCRATCH_REG1 0x2041 +#define mmGRBM_SCRATCH_REG2 0x2042 +#define mmGRBM_SCRATCH_REG3 0x2043 +#define mmGRBM_SCRATCH_REG4 0x2044 +#define mmGRBM_SCRATCH_REG5 0x2045 +#define mmGRBM_SCRATCH_REG6 0x2046 +#define mmGRBM_SCRATCH_REG7 0x2047 +#define mmGRBM_SE0_PERFCOUNTER_HI 0x202B +#define mmGRBM_SE0_PERFCOUNTER_LO 0x202A +#define mmGRBM_SE0_PERFCOUNTER_SELECT 0x2026 +#define mmGRBM_SE1_PERFCOUNTER_HI 0x202D +#define mmGRBM_SE1_PERFCOUNTER_LO 0x202C +#define mmGRBM_SE1_PERFCOUNTER_SELECT 0x2027 +#define mmGRBM_SKEW_CNTL 0x2001 +#define mmGRBM_SOFT_RESET 0x2008 +#define mmGRBM_STATUS 0x2004 +#define mmGRBM_STATUS2 0x2002 +#define mmGRBM_STATUS_SE0 0x2005 +#define mmGRBM_STATUS_SE1 0x2006 +#define mmGRBM_WAIT_IDLE_CLOCKS 0x200D +#define mmIA_CNTL_STATUS 0x2237 +#define mmIA_DEBUG_CNTL 0x223A +#define mmIA_DEBUG_DATA 0x223B +#define mmIA_ENHANCE 0xA29C +#define mmIA_MULTI_VGT_PARAM 0xA2AA +#define mmIA_PERFCOUNTER0_HI 0x2225 +#define mmIA_PERFCOUNTER0_LO 0x2224 +#define mmIA_PERFCOUNTER0_SELECT 0x2220 +#define mmIA_PERFCOUNTER1_HI 0x2227 +#define mmIA_PERFCOUNTER1_LO 0x2226 +#define mmIA_PERFCOUNTER1_SELECT 0x2221 +#define mmIA_PERFCOUNTER2_HI 0x2229 +#define mmIA_PERFCOUNTER2_LO 0x2228 +#define mmIA_PERFCOUNTER2_SELECT 0x2222 +#define mmIA_PERFCOUNTER3_HI 0x222B +#define mmIA_PERFCOUNTER3_LO 0x222A +#define mmIA_PERFCOUNTER3_SELECT 0x2223 +#define mmIA_VMID_OVERRIDE 0x2260 +#define mmPA_CL_CLIP_CNTL 0xA204 +#define mmPA_CL_CNTL_STATUS 0x2284 +#define mmPA_CL_ENHANCE 0x2285 +#define mmPA_CL_GB_HORZ_CLIP_ADJ 0xA2FC +#define mmPA_CL_GB_HORZ_DISC_ADJ 0xA2FD +#define mmPA_CL_GB_VERT_CLIP_ADJ 0xA2FA +#define mmPA_CL_GB_VERT_DISC_ADJ 0xA2FB +#define mmPA_CL_NANINF_CNTL 0xA208 +#define mmPA_CL_POINT_CULL_RAD 0xA1F8 +#define mmPA_CL_POINT_SIZE 0xA1F7 +#define mmPA_CL_POINT_X_RAD 0xA1F5 +#define mmPA_CL_POINT_Y_RAD 0xA1F6 +#define mmPA_CL_UCP_0_W 0xA172 +#define mmPA_CL_UCP_0_X 0xA16F +#define mmPA_CL_UCP_0_Y 0xA170 +#define mmPA_CL_UCP_0_Z 0xA171 +#define mmPA_CL_UCP_1_W 0xA176 +#define mmPA_CL_UCP_1_X 0xA173 +#define mmPA_CL_UCP_1_Y 0xA174 +#define mmPA_CL_UCP_1_Z 0xA175 +#define mmPA_CL_UCP_2_W 0xA17A +#define mmPA_CL_UCP_2_X 0xA177 +#define mmPA_CL_UCP_2_Y 0xA178 +#define mmPA_CL_UCP_2_Z 0xA179 +#define mmPA_CL_UCP_3_W 0xA17E +#define mmPA_CL_UCP_3_X 0xA17B +#define mmPA_CL_UCP_3_Y 0xA17C +#define mmPA_CL_UCP_3_Z 0xA17D +#define mmPA_CL_UCP_4_W 0xA182 +#define mmPA_CL_UCP_4_X 0xA17F +#define mmPA_CL_UCP_4_Y 0xA180 +#define mmPA_CL_UCP_4_Z 0xA181 +#define mmPA_CL_UCP_5_W 0xA186 +#define mmPA_CL_UCP_5_X 0xA183 +#define mmPA_CL_UCP_5_Y 0xA184 +#define mmPA_CL_UCP_5_Z 0xA185 +#define mmPA_CL_VPORT_XOFFSET 0xA110 +#define mmPA_CL_VPORT_XOFFSET_10 0xA14C +#define mmPA_CL_VPORT_XOFFSET_1 0xA116 +#define mmPA_CL_VPORT_XOFFSET_11 0xA152 +#define mmPA_CL_VPORT_XOFFSET_12 0xA158 +#define mmPA_CL_VPORT_XOFFSET_13 0xA15E +#define mmPA_CL_VPORT_XOFFSET_14 0xA164 +#define mmPA_CL_VPORT_XOFFSET_15 0xA16A +#define mmPA_CL_VPORT_XOFFSET_2 0xA11C +#define mmPA_CL_VPORT_XOFFSET_3 0xA122 +#define mmPA_CL_VPORT_XOFFSET_4 0xA128 +#define mmPA_CL_VPORT_XOFFSET_5 0xA12E +#define mmPA_CL_VPORT_XOFFSET_6 0xA134 +#define mmPA_CL_VPORT_XOFFSET_7 0xA13A +#define mmPA_CL_VPORT_XOFFSET_8 0xA140 +#define mmPA_CL_VPORT_XOFFSET_9 0xA146 +#define mmPA_CL_VPORT_XSCALE 0xA10F +#define mmPA_CL_VPORT_XSCALE_10 0xA14B +#define mmPA_CL_VPORT_XSCALE_1 0xA115 +#define mmPA_CL_VPORT_XSCALE_11 0xA151 +#define mmPA_CL_VPORT_XSCALE_12 0xA157 +#define mmPA_CL_VPORT_XSCALE_13 0xA15D +#define mmPA_CL_VPORT_XSCALE_14 0xA163 +#define mmPA_CL_VPORT_XSCALE_15 0xA169 +#define mmPA_CL_VPORT_XSCALE_2 0xA11B +#define mmPA_CL_VPORT_XSCALE_3 0xA121 +#define mmPA_CL_VPORT_XSCALE_4 0xA127 +#define mmPA_CL_VPORT_XSCALE_5 0xA12D +#define mmPA_CL_VPORT_XSCALE_6 0xA133 +#define mmPA_CL_VPORT_XSCALE_7 0xA139 +#define mmPA_CL_VPORT_XSCALE_8 0xA13F +#define mmPA_CL_VPORT_XSCALE_9 0xA145 +#define mmPA_CL_VPORT_YOFFSET 0xA112 +#define mmPA_CL_VPORT_YOFFSET_10 0xA14E +#define mmPA_CL_VPORT_YOFFSET_1 0xA118 +#define mmPA_CL_VPORT_YOFFSET_11 0xA154 +#define mmPA_CL_VPORT_YOFFSET_12 0xA15A +#define mmPA_CL_VPORT_YOFFSET_13 0xA160 +#define mmPA_CL_VPORT_YOFFSET_14 0xA166 +#define mmPA_CL_VPORT_YOFFSET_15 0xA16C +#define mmPA_CL_VPORT_YOFFSET_2 0xA11E +#define mmPA_CL_VPORT_YOFFSET_3 0xA124 +#define mmPA_CL_VPORT_YOFFSET_4 0xA12A +#define mmPA_CL_VPORT_YOFFSET_5 0xA130 +#define mmPA_CL_VPORT_YOFFSET_6 0xA136 +#define mmPA_CL_VPORT_YOFFSET_7 0xA13C +#define mmPA_CL_VPORT_YOFFSET_8 0xA142 +#define mmPA_CL_VPORT_YOFFSET_9 0xA148 +#define mmPA_CL_VPORT_YSCALE 0xA111 +#define mmPA_CL_VPORT_YSCALE_10 0xA14D +#define mmPA_CL_VPORT_YSCALE_1 0xA117 +#define mmPA_CL_VPORT_YSCALE_11 0xA153 +#define mmPA_CL_VPORT_YSCALE_12 0xA159 +#define mmPA_CL_VPORT_YSCALE_13 0xA15F +#define mmPA_CL_VPORT_YSCALE_14 0xA165 +#define mmPA_CL_VPORT_YSCALE_15 0xA16B +#define mmPA_CL_VPORT_YSCALE_2 0xA11D +#define mmPA_CL_VPORT_YSCALE_3 0xA123 +#define mmPA_CL_VPORT_YSCALE_4 0xA129 +#define mmPA_CL_VPORT_YSCALE_5 0xA12F +#define mmPA_CL_VPORT_YSCALE_6 0xA135 +#define mmPA_CL_VPORT_YSCALE_7 0xA13B +#define mmPA_CL_VPORT_YSCALE_8 0xA141 +#define mmPA_CL_VPORT_YSCALE_9 0xA147 +#define mmPA_CL_VPORT_ZOFFSET 0xA114 +#define mmPA_CL_VPORT_ZOFFSET_10 0xA150 +#define mmPA_CL_VPORT_ZOFFSET_1 0xA11A +#define mmPA_CL_VPORT_ZOFFSET_11 0xA156 +#define mmPA_CL_VPORT_ZOFFSET_12 0xA15C +#define mmPA_CL_VPORT_ZOFFSET_13 0xA162 +#define mmPA_CL_VPORT_ZOFFSET_14 0xA168 +#define mmPA_CL_VPORT_ZOFFSET_15 0xA16E +#define mmPA_CL_VPORT_ZOFFSET_2 0xA120 +#define mmPA_CL_VPORT_ZOFFSET_3 0xA126 +#define mmPA_CL_VPORT_ZOFFSET_4 0xA12C +#define mmPA_CL_VPORT_ZOFFSET_5 0xA132 +#define mmPA_CL_VPORT_ZOFFSET_6 0xA138 +#define mmPA_CL_VPORT_ZOFFSET_7 0xA13E +#define mmPA_CL_VPORT_ZOFFSET_8 0xA144 +#define mmPA_CL_VPORT_ZOFFSET_9 0xA14A +#define mmPA_CL_VPORT_ZSCALE 0xA113 +#define mmPA_CL_VPORT_ZSCALE_10 0xA14F +#define mmPA_CL_VPORT_ZSCALE_1 0xA119 +#define mmPA_CL_VPORT_ZSCALE_11 0xA155 +#define mmPA_CL_VPORT_ZSCALE_12 0xA15B +#define mmPA_CL_VPORT_ZSCALE_13 0xA161 +#define mmPA_CL_VPORT_ZSCALE_14 0xA167 +#define mmPA_CL_VPORT_ZSCALE_15 0xA16D +#define mmPA_CL_VPORT_ZSCALE_2 0xA11F +#define mmPA_CL_VPORT_ZSCALE_3 0xA125 +#define mmPA_CL_VPORT_ZSCALE_4 0xA12B +#define mmPA_CL_VPORT_ZSCALE_5 0xA131 +#define mmPA_CL_VPORT_ZSCALE_6 0xA137 +#define mmPA_CL_VPORT_ZSCALE_7 0xA13D +#define mmPA_CL_VPORT_ZSCALE_8 0xA143 +#define mmPA_CL_VPORT_ZSCALE_9 0xA149 +#define mmPA_CL_VS_OUT_CNTL 0xA207 +#define mmPA_CL_VTE_CNTL 0xA206 +#define mmPA_SC_AA_CONFIG 0xA2F8 +#define mmPA_SC_AA_MASK_X0Y0_X1Y0 0xA30E +#define mmPA_SC_AA_MASK_X0Y1_X1Y1 0xA30F +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0xA2FE +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0xA2FF +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0xA300 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0xA301 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0xA306 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0xA307 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0xA308 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0xA309 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0xA302 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0xA303 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0xA304 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0xA305 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0xA30A +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0xA30B +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0xA30C +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0xA30D +#define mmPA_SC_CENTROID_PRIORITY_0 0xA2F5 +#define mmPA_SC_CENTROID_PRIORITY_1 0xA2F6 +#define mmPA_SC_CLIPRECT_0_BR 0xA085 +#define mmPA_SC_CLIPRECT_0_TL 0xA084 +#define mmPA_SC_CLIPRECT_1_BR 0xA087 +#define mmPA_SC_CLIPRECT_1_TL 0xA086 +#define mmPA_SC_CLIPRECT_2_BR 0xA089 +#define mmPA_SC_CLIPRECT_2_TL 0xA088 +#define mmPA_SC_CLIPRECT_3_BR 0xA08B +#define mmPA_SC_CLIPRECT_3_TL 0xA08A +#define mmPA_SC_CLIPRECT_RULE 0xA083 +#define mmPA_SC_DEBUG_CNTL 0x22F6 +#define mmPA_SC_DEBUG_DATA 0x22F7 +#define mmPA_SC_EDGERULE 0xA08C +#define mmPA_SC_ENHANCE 0x22FC +#define mmPA_SC_FIFO_DEPTH_CNTL 0x2295 +#define mmPA_SC_FIFO_SIZE 0x22F3 +#define mmPA_SC_FORCE_EOV_MAX_CNTS 0x22C9 +#define mmPA_SC_GENERIC_SCISSOR_BR 0xA091 +#define mmPA_SC_GENERIC_SCISSOR_TL 0xA090 +#define mmPA_SC_IF_FIFO_SIZE 0x22F5 +#define mmPA_SC_LINE_CNTL 0xA2F7 +#define mmPA_SC_LINE_STIPPLE 0xA283 +#define mmPA_SC_LINE_STIPPLE_STATE 0x22C4 +#define mmPA_SC_MODE_CNTL_0 0xA292 +#define mmPA_SC_MODE_CNTL_1 0xA293 +#define mmPA_SC_PERFCOUNTER0_HI 0x22A9 +#define mmPA_SC_PERFCOUNTER0_LO 0x22A8 +#define mmPA_SC_PERFCOUNTER0_SELECT 0x22A0 +#define mmPA_SC_PERFCOUNTER1_HI 0x22AB +#define mmPA_SC_PERFCOUNTER1_LO 0x22AA +#define mmPA_SC_PERFCOUNTER1_SELECT 0x22A1 +#define mmPA_SC_PERFCOUNTER2_HI 0x22AD +#define mmPA_SC_PERFCOUNTER2_LO 0x22AC +#define mmPA_SC_PERFCOUNTER2_SELECT 0x22A2 +#define mmPA_SC_PERFCOUNTER3_HI 0x22AF +#define mmPA_SC_PERFCOUNTER3_LO 0x22AE +#define mmPA_SC_PERFCOUNTER3_SELECT 0x22A3 +#define mmPA_SC_PERFCOUNTER4_HI 0x22B1 +#define mmPA_SC_PERFCOUNTER4_LO 0x22B0 +#define mmPA_SC_PERFCOUNTER4_SELECT 0x22A4 +#define mmPA_SC_PERFCOUNTER5_HI 0x22B3 +#define mmPA_SC_PERFCOUNTER5_LO 0x22B2 +#define mmPA_SC_PERFCOUNTER5_SELECT 0x22A5 +#define mmPA_SC_PERFCOUNTER6_HI 0x22B5 +#define mmPA_SC_PERFCOUNTER6_LO 0x22B4 +#define mmPA_SC_PERFCOUNTER6_SELECT 0x22A6 +#define mmPA_SC_PERFCOUNTER7_HI 0x22B7 +#define mmPA_SC_PERFCOUNTER7_LO 0x22B6 +#define mmPA_SC_PERFCOUNTER7_SELECT 0x22A7 +#define mmPA_SC_RASTER_CONFIG 0xA0D4 +#define mmPA_SC_SCREEN_SCISSOR_BR 0xA00D +#define mmPA_SC_SCREEN_SCISSOR_TL 0xA00C +#define mmPA_SC_VPORT_SCISSOR_0_BR 0xA095 +#define mmPA_SC_VPORT_SCISSOR_0_TL 0xA094 +#define mmPA_SC_VPORT_SCISSOR_10_BR 0xA0A9 +#define mmPA_SC_VPORT_SCISSOR_10_TL 0xA0A8 +#define mmPA_SC_VPORT_SCISSOR_11_BR 0xA0AB +#define mmPA_SC_VPORT_SCISSOR_11_TL 0xA0AA +#define mmPA_SC_VPORT_SCISSOR_12_BR 0xA0AD +#define mmPA_SC_VPORT_SCISSOR_12_TL 0xA0AC +#define mmPA_SC_VPORT_SCISSOR_13_BR 0xA0AF +#define mmPA_SC_VPORT_SCISSOR_13_TL 0xA0AE +#define mmPA_SC_VPORT_SCISSOR_14_BR 0xA0B1 +#define mmPA_SC_VPORT_SCISSOR_14_TL 0xA0B0 +#define mmPA_SC_VPORT_SCISSOR_15_BR 0xA0B3 +#define mmPA_SC_VPORT_SCISSOR_15_TL 0xA0B2 +#define mmPA_SC_VPORT_SCISSOR_1_BR 0xA097 +#define mmPA_SC_VPORT_SCISSOR_1_TL 0xA096 +#define mmPA_SC_VPORT_SCISSOR_2_BR 0xA099 +#define mmPA_SC_VPORT_SCISSOR_2_TL 0xA098 +#define mmPA_SC_VPORT_SCISSOR_3_BR 0xA09B +#define mmPA_SC_VPORT_SCISSOR_3_TL 0xA09A +#define mmPA_SC_VPORT_SCISSOR_4_BR 0xA09D +#define mmPA_SC_VPORT_SCISSOR_4_TL 0xA09C +#define mmPA_SC_VPORT_SCISSOR_5_BR 0xA09F +#define mmPA_SC_VPORT_SCISSOR_5_TL 0xA09E +#define mmPA_SC_VPORT_SCISSOR_6_BR 0xA0A1 +#define mmPA_SC_VPORT_SCISSOR_6_TL 0xA0A0 +#define mmPA_SC_VPORT_SCISSOR_7_BR 0xA0A3 +#define mmPA_SC_VPORT_SCISSOR_7_TL 0xA0A2 +#define mmPA_SC_VPORT_SCISSOR_8_BR 0xA0A5 +#define mmPA_SC_VPORT_SCISSOR_8_TL 0xA0A4 +#define mmPA_SC_VPORT_SCISSOR_9_BR 0xA0A7 +#define mmPA_SC_VPORT_SCISSOR_9_TL 0xA0A6 +#define mmPA_SC_VPORT_ZMAX_0 0xA0B5 +#define mmPA_SC_VPORT_ZMAX_10 0xA0C9 +#define mmPA_SC_VPORT_ZMAX_1 0xA0B7 +#define mmPA_SC_VPORT_ZMAX_11 0xA0CB +#define mmPA_SC_VPORT_ZMAX_12 0xA0CD +#define mmPA_SC_VPORT_ZMAX_13 0xA0CF +#define mmPA_SC_VPORT_ZMAX_14 0xA0D1 +#define mmPA_SC_VPORT_ZMAX_15 0xA0D3 +#define mmPA_SC_VPORT_ZMAX_2 0xA0B9 +#define mmPA_SC_VPORT_ZMAX_3 0xA0BB +#define mmPA_SC_VPORT_ZMAX_4 0xA0BD +#define mmPA_SC_VPORT_ZMAX_5 0xA0BF +#define mmPA_SC_VPORT_ZMAX_6 0xA0C1 +#define mmPA_SC_VPORT_ZMAX_7 0xA0C3 +#define mmPA_SC_VPORT_ZMAX_8 0xA0C5 +#define mmPA_SC_VPORT_ZMAX_9 0xA0C7 +#define mmPA_SC_VPORT_ZMIN_0 0xA0B4 +#define mmPA_SC_VPORT_ZMIN_10 0xA0C8 +#define mmPA_SC_VPORT_ZMIN_1 0xA0B6 +#define mmPA_SC_VPORT_ZMIN_11 0xA0CA +#define mmPA_SC_VPORT_ZMIN_12 0xA0CC +#define mmPA_SC_VPORT_ZMIN_13 0xA0CE +#define mmPA_SC_VPORT_ZMIN_14 0xA0D0 +#define mmPA_SC_VPORT_ZMIN_15 0xA0D2 +#define mmPA_SC_VPORT_ZMIN_2 0xA0B8 +#define mmPA_SC_VPORT_ZMIN_3 0xA0BA +#define mmPA_SC_VPORT_ZMIN_4 0xA0BC +#define mmPA_SC_VPORT_ZMIN_5 0xA0BE +#define mmPA_SC_VPORT_ZMIN_6 0xA0C0 +#define mmPA_SC_VPORT_ZMIN_7 0xA0C2 +#define mmPA_SC_VPORT_ZMIN_8 0xA0C4 +#define mmPA_SC_VPORT_ZMIN_9 0xA0C6 +#define mmPA_SC_WINDOW_OFFSET 0xA080 +#define mmPA_SC_WINDOW_SCISSOR_BR 0xA082 +#define mmPA_SC_WINDOW_SCISSOR_TL 0xA081 +#define mmPA_SU_CNTL_STATUS 0x2294 +#define mmPA_SU_DEBUG_CNTL 0x2280 +#define mmPA_SU_DEBUG_DATA 0x2281 +#define mmPA_SU_HARDWARE_SCREEN_OFFSET 0xA08D +#define mmPA_SU_LINE_CNTL 0xA282 +#define mmPA_SU_LINE_STIPPLE_CNTL 0xA209 +#define mmPA_SU_LINE_STIPPLE_SCALE 0xA20A +#define mmPA_SU_LINE_STIPPLE_VALUE 0x2298 +#define mmPA_SU_PERFCOUNTER0_HI 0x228D +#define mmPA_SU_PERFCOUNTER0_LO 0x228C +#define mmPA_SU_PERFCOUNTER0_SELECT 0x2288 +#define mmPA_SU_PERFCOUNTER1_HI 0x228F +#define mmPA_SU_PERFCOUNTER1_LO 0x228E +#define mmPA_SU_PERFCOUNTER1_SELECT 0x2289 +#define mmPA_SU_PERFCOUNTER2_HI 0x2291 +#define mmPA_SU_PERFCOUNTER2_LO 0x2290 +#define mmPA_SU_PERFCOUNTER2_SELECT 0x228A +#define mmPA_SU_PERFCOUNTER3_HI 0x2293 +#define mmPA_SU_PERFCOUNTER3_LO 0x2292 +#define mmPA_SU_PERFCOUNTER3_SELECT 0x228B +#define mmPA_SU_POINT_MINMAX 0xA281 +#define mmPA_SU_POINT_SIZE 0xA280 +#define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0xA2E3 +#define mmPA_SU_POLY_OFFSET_BACK_SCALE 0xA2E2 +#define mmPA_SU_POLY_OFFSET_CLAMP 0xA2DF +#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL 0xA2DE +#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0xA2E1 +#define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0xA2E0 +#define mmPA_SU_PRIM_FILTER_CNTL 0xA20B +#define mmPA_SU_SC_MODE_CNTL 0xA205 +#define mmPA_SU_VTX_CNTL 0xA2F9 +#define mmRAS_BCI_SIGNATURE0 0x339E +#define mmRAS_BCI_SIGNATURE1 0x339F +#define mmRAS_CB_SIGNATURE0 0x339D +#define mmRAS_DB_SIGNATURE0 0x338B +#define mmRAS_IA_SIGNATURE0 0x3397 +#define mmRAS_IA_SIGNATURE1 0x3398 +#define mmRAS_PA_SIGNATURE0 0x338C +#define mmRAS_SC_SIGNATURE0 0x338F +#define mmRAS_SC_SIGNATURE1 0x3390 +#define mmRAS_SC_SIGNATURE2 0x3391 +#define mmRAS_SC_SIGNATURE3 0x3392 +#define mmRAS_SC_SIGNATURE4 0x3393 +#define mmRAS_SC_SIGNATURE5 0x3394 +#define mmRAS_SC_SIGNATURE6 0x3395 +#define mmRAS_SC_SIGNATURE7 0x3396 +#define mmRAS_SIGNATURE_CONTROL 0x3380 +#define mmRAS_SIGNATURE_MASK 0x3381 +#define mmRAS_SPI_SIGNATURE0 0x3399 +#define mmRAS_SPI_SIGNATURE1 0x339A +#define mmRAS_SQ_SIGNATURE0 0x338E +#define mmRAS_SX_SIGNATURE0 0x3382 +#define mmRAS_SX_SIGNATURE1 0x3383 +#define mmRAS_SX_SIGNATURE2 0x3384 +#define mmRAS_SX_SIGNATURE3 0x3385 +#define mmRAS_TA_SIGNATURE0 0x339B +#define mmRAS_TD_SIGNATURE0 0x339C +#define mmRAS_VGT_SIGNATURE0 0x338D +#define mmRLC_AUTO_PG_CTRL 0x310D +#define mmRLC_CAPTURE_GPU_CLOCK_COUNT 0x30D0 +#define mmRLC_CGCG_CGLS_CTRL 0x3101 +#define mmRLC_CGCG_RAMP_CTRL 0x3102 +#define mmRLC_CGTT_MGCG_OVERRIDE 0x3100 +#define mmRLC_CNTL 0x30C0 +#define mmRLC_CU_STATUS 0x3106 +#define mmRLC_DEBUG 0x30CA +#define mmRLC_DEBUG_SELECT 0x30C9 +#define mmRLC_DRIVER_CPDMA_STATUS 0x30C7 +#define mmRLC_DYN_PG_REQUEST 0x3104 +#define mmRLC_DYN_PG_STATUS 0x3103 +#define mmRLC_GPU_CLOCK_32 0x30D5 +#define mmRLC_GPU_CLOCK_32_RES_SEL 0x30D4 +#define mmRLC_GPU_CLOCK_COUNT_LSB 0x30CE +#define mmRLC_GPU_CLOCK_COUNT_MSB 0x30CF +#define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK 0x3108 +#define mmRLC_LB_CNTL 0x30C3 +#define mmRLC_LB_CNTR_INIT 0x30C6 +#define mmRLC_LB_CNTR_MAX 0x30C5 +#define mmRLC_LB_INIT_CU_MASK 0x3107 +#define mmRLC_LB_PARAMS 0x3109 +#define mmRLC_LOAD_BALANCE_CNTR 0x30F6 +#define mmRLC_MAX_PG_CU 0x310C +#define mmRLC_MC_CNTL 0x30D1 +#define mmRLC_MEM_SLP_CNTL 0x30D8 +#define mmRLC_PERFCOUNTER0_HI 0x30DC +#define mmRLC_PERFCOUNTER0_LO 0x30DB +#define mmRLC_PERFCOUNTER0_SELECT 0x30DA +#define mmRLC_PERFCOUNTER1_HI 0x30DF +#define mmRLC_PERFCOUNTER1_LO 0x30DE +#define mmRLC_PERFCOUNTER1_SELECT 0x30DD +#define mmRLC_PERFMON_CNTL 0x30D9 +#define mmRLC_PG_ALWAYS_ON_CU_MASK 0x310B +#define mmRLC_PG_CNTL 0x30D7 +#define mmRLC_SAVE_AND_RESTORE_BASE 0x30C4 +#define mmRLC_SERDES_RD_DATA_0 0x3112 +#define mmRLC_SERDES_RD_DATA_1 0x3113 +#define mmRLC_SERDES_RD_DATA_2 0x3114 +#define mmRLC_SERDES_RD_MASTER_INDEX 0x3111 +#define mmRLC_SERDES_WR_CTRL 0x3117 +#define mmRLC_SERDES_WR_DATA 0x3118 +#define mmRLC_SMU_GRBM_REG_SAVE_CTRL 0x310E +#define mmRLC_SMU_PG_CTRL 0x310F +#define mmRLC_SMU_PG_WAKE_UP_CTRL 0x3110 +#define mmRLC_SOFT_RESET_GPU 0x30D6 +#define mmRLC_STAT 0x30D3 +#define mmRLC_THREAD1_DELAY 0x310A +#define mmRLC_UCODE_CNTL 0x30D2 +#define mmSCRATCH_ADDR 0x2151 +#define mmSCRATCH_REG0 0x2140 +#define mmSCRATCH_REG1 0x2141 +#define mmSCRATCH_REG2 0x2142 +#define mmSCRATCH_REG3 0x2143 +#define mmSCRATCH_REG4 0x2144 +#define mmSCRATCH_REG5 0x2145 +#define mmSCRATCH_REG6 0x2146 +#define mmSCRATCH_REG7 0x2147 +#define mmSCRATCH_UMSK 0x2150 +#define mmSPI_ARB_CYCLES_0 0x243D +#define mmSPI_ARB_CYCLES_1 0x243E +#define mmSPI_ARB_PRIORITY 0x243C +#define mmSPI_BARYC_CNTL 0xA1B8 +#define mmSPI_CONFIG_CNTL 0x2440 +#define mmSPI_CONFIG_CNTL_1 0x244F +#define mmSPI_DEBUG_BUSY 0x2450 +#define mmSPI_DEBUG_CNTL 0x2441 +#define mmSPI_DEBUG_READ 0x2442 +#define mmSPI_GDS_CREDITS 0x24D8 +#define mmSPI_INTERP_CONTROL_0 0xA1B5 +#define mmSPI_LB_CTR_CTRL 0x24D4 +#define mmSPI_LB_CU_MASK 0x24D5 +#define mmSPI_LB_DATA_REG 0x24D6 +#define mmSPI_PERFCOUNTER0_HI 0x2447 +#define mmSPI_PERFCOUNTER0_LO 0x2448 +#define mmSPI_PERFCOUNTER0_SELECT 0x2443 +#define mmSPI_PERFCOUNTER1_HI 0x2449 +#define mmSPI_PERFCOUNTER1_LO 0x244A +#define mmSPI_PERFCOUNTER1_SELECT 0x2444 +#define mmSPI_PERFCOUNTER2_HI 0x244B +#define mmSPI_PERFCOUNTER2_LO 0x244C +#define mmSPI_PERFCOUNTER2_SELECT 0x2445 +#define mmSPI_PERFCOUNTER3_HI 0x244D +#define mmSPI_PERFCOUNTER3_LO 0x244E +#define mmSPI_PERFCOUNTER3_SELECT 0x2446 +#define mmSPI_PERFCOUNTER_BINS 0x243F +#define mmSPI_PG_ENABLE_STATIC_CU_MASK 0x24D7 +#define mmSPI_PS_IN_CONTROL 0xA1B6 +#define mmSPI_PS_INPUT_ADDR 0xA1B4 +#define mmSPI_PS_INPUT_CNTL_0 0xA191 +#define mmSPI_PS_INPUT_CNTL_10 0xA19B +#define mmSPI_PS_INPUT_CNTL_1 0xA192 +#define mmSPI_PS_INPUT_CNTL_11 0xA19C +#define mmSPI_PS_INPUT_CNTL_12 0xA19D +#define mmSPI_PS_INPUT_CNTL_13 0xA19E +#define mmSPI_PS_INPUT_CNTL_14 0xA19F +#define mmSPI_PS_INPUT_CNTL_15 0xA1A0 +#define mmSPI_PS_INPUT_CNTL_16 0xA1A1 +#define mmSPI_PS_INPUT_CNTL_17 0xA1A2 +#define mmSPI_PS_INPUT_CNTL_18 0xA1A3 +#define mmSPI_PS_INPUT_CNTL_19 0xA1A4 +#define mmSPI_PS_INPUT_CNTL_20 0xA1A5 +#define mmSPI_PS_INPUT_CNTL_2 0xA193 +#define mmSPI_PS_INPUT_CNTL_21 0xA1A6 +#define mmSPI_PS_INPUT_CNTL_22 0xA1A7 +#define mmSPI_PS_INPUT_CNTL_23 0xA1A8 +#define mmSPI_PS_INPUT_CNTL_24 0xA1A9 +#define mmSPI_PS_INPUT_CNTL_25 0xA1AA +#define mmSPI_PS_INPUT_CNTL_26 0xA1AB +#define mmSPI_PS_INPUT_CNTL_27 0xA1AC +#define mmSPI_PS_INPUT_CNTL_28 0xA1AD +#define mmSPI_PS_INPUT_CNTL_29 0xA1AE +#define mmSPI_PS_INPUT_CNTL_30 0xA1AF +#define mmSPI_PS_INPUT_CNTL_3 0xA194 +#define mmSPI_PS_INPUT_CNTL_31 0xA1B0 +#define mmSPI_PS_INPUT_CNTL_4 0xA195 +#define mmSPI_PS_INPUT_CNTL_5 0xA196 +#define mmSPI_PS_INPUT_CNTL_6 0xA197 +#define mmSPI_PS_INPUT_CNTL_7 0xA198 +#define mmSPI_PS_INPUT_CNTL_8 0xA199 +#define mmSPI_PS_INPUT_CNTL_9 0xA19A +#define mmSPI_PS_INPUT_ENA 0xA1B3 +#define mmSPI_PS_MAX_WAVE_ID 0x243B +#define mmSPI_SHADER_COL_FORMAT 0xA1C5 +#define mmSPI_SHADER_PGM_HI_ES 0x2CC9 +#define mmSPI_SHADER_PGM_HI_GS 0x2C89 +#define mmSPI_SHADER_PGM_HI_HS 0x2D09 +#define mmSPI_SHADER_PGM_HI_LS 0x2D49 +#define mmSPI_SHADER_PGM_HI_PS 0x2C09 +#define mmSPI_SHADER_PGM_HI_VS 0x2C49 +#define mmSPI_SHADER_PGM_LO_ES 0x2CC8 +#define mmSPI_SHADER_PGM_LO_GS 0x2C88 +#define mmSPI_SHADER_PGM_LO_HS 0x2D08 +#define mmSPI_SHADER_PGM_LO_LS 0x2D48 +#define mmSPI_SHADER_PGM_LO_PS 0x2C08 +#define mmSPI_SHADER_PGM_LO_VS 0x2C48 +#define mmSPI_SHADER_PGM_RSRC1_ES 0x2CCA +#define mmSPI_SHADER_PGM_RSRC1_GS 0x2C8A +#define mmSPI_SHADER_PGM_RSRC1_HS 0x2D0A +#define mmSPI_SHADER_PGM_RSRC1_LS 0x2D4A +#define mmSPI_SHADER_PGM_RSRC1_PS 0x2C0A +#define mmSPI_SHADER_PGM_RSRC1_VS 0x2C4A +#define mmSPI_SHADER_PGM_RSRC2_ES 0x2CCB +#define mmSPI_SHADER_PGM_RSRC2_GS 0x2C8B +#define mmSPI_SHADER_PGM_RSRC2_HS 0x2D0B +#define mmSPI_SHADER_PGM_RSRC2_LS 0x2D4B +#define mmSPI_SHADER_PGM_RSRC2_PS 0x2C0B +#define mmSPI_SHADER_PGM_RSRC2_VS 0x2C4B +#define mmSPI_SHADER_POS_FORMAT 0xA1C3 +#define mmSPI_SHADER_TBA_HI_ES 0x2CC1 +#define mmSPI_SHADER_TBA_HI_GS 0x2C81 +#define mmSPI_SHADER_TBA_HI_HS 0x2D01 +#define mmSPI_SHADER_TBA_HI_LS 0x2D41 +#define mmSPI_SHADER_TBA_HI_PS 0x2C01 +#define mmSPI_SHADER_TBA_HI_VS 0x2C41 +#define mmSPI_SHADER_TBA_LO_ES 0x2CC0 +#define mmSPI_SHADER_TBA_LO_GS 0x2C80 +#define mmSPI_SHADER_TBA_LO_HS 0x2D00 +#define mmSPI_SHADER_TBA_LO_LS 0x2D40 +#define mmSPI_SHADER_TBA_LO_PS 0x2C00 +#define mmSPI_SHADER_TBA_LO_VS 0x2C40 +#define mmSPI_SHADER_TMA_HI_ES 0x2CC3 +#define mmSPI_SHADER_TMA_HI_GS 0x2C83 +#define mmSPI_SHADER_TMA_HI_HS 0x2D03 +#define mmSPI_SHADER_TMA_HI_LS 0x2D43 +#define mmSPI_SHADER_TMA_HI_PS 0x2C03 +#define mmSPI_SHADER_TMA_HI_VS 0x2C43 +#define mmSPI_SHADER_TMA_LO_ES 0x2CC2 +#define mmSPI_SHADER_TMA_LO_GS 0x2C82 +#define mmSPI_SHADER_TMA_LO_HS 0x2D02 +#define mmSPI_SHADER_TMA_LO_LS 0x2D42 +#define mmSPI_SHADER_TMA_LO_PS 0x2C02 +#define mmSPI_SHADER_TMA_LO_VS 0x2C42 +#define mmSPI_SHADER_USER_DATA_ES_0 0x2CCC +#define mmSPI_SHADER_USER_DATA_ES_10 0x2CD6 +#define mmSPI_SHADER_USER_DATA_ES_1 0x2CCD +#define mmSPI_SHADER_USER_DATA_ES_11 0x2CD7 +#define mmSPI_SHADER_USER_DATA_ES_12 0x2CD8 +#define mmSPI_SHADER_USER_DATA_ES_13 0x2CD9 +#define mmSPI_SHADER_USER_DATA_ES_14 0x2CDA +#define mmSPI_SHADER_USER_DATA_ES_15 0x2CDB +#define mmSPI_SHADER_USER_DATA_ES_2 0x2CCE +#define mmSPI_SHADER_USER_DATA_ES_3 0x2CCF +#define mmSPI_SHADER_USER_DATA_ES_4 0x2CD0 +#define mmSPI_SHADER_USER_DATA_ES_5 0x2CD1 +#define mmSPI_SHADER_USER_DATA_ES_6 0x2CD2 +#define mmSPI_SHADER_USER_DATA_ES_7 0x2CD3 +#define mmSPI_SHADER_USER_DATA_ES_8 0x2CD4 +#define mmSPI_SHADER_USER_DATA_ES_9 0x2CD5 +#define mmSPI_SHADER_USER_DATA_GS_0 0x2C8C +#define mmSPI_SHADER_USER_DATA_GS_10 0x2C96 +#define mmSPI_SHADER_USER_DATA_GS_1 0x2C8D +#define mmSPI_SHADER_USER_DATA_GS_11 0x2C97 +#define mmSPI_SHADER_USER_DATA_GS_12 0x2C98 +#define mmSPI_SHADER_USER_DATA_GS_13 0x2C99 +#define mmSPI_SHADER_USER_DATA_GS_14 0x2C9A +#define mmSPI_SHADER_USER_DATA_GS_15 0x2C9B +#define mmSPI_SHADER_USER_DATA_GS_2 0x2C8E +#define mmSPI_SHADER_USER_DATA_GS_3 0x2C8F +#define mmSPI_SHADER_USER_DATA_GS_4 0x2C90 +#define mmSPI_SHADER_USER_DATA_GS_5 0x2C91 +#define mmSPI_SHADER_USER_DATA_GS_6 0x2C92 +#define mmSPI_SHADER_USER_DATA_GS_7 0x2C93 +#define mmSPI_SHADER_USER_DATA_GS_8 0x2C94 +#define mmSPI_SHADER_USER_DATA_GS_9 0x2C95 +#define mmSPI_SHADER_USER_DATA_HS_0 0x2D0C +#define mmSPI_SHADER_USER_DATA_HS_10 0x2D16 +#define mmSPI_SHADER_USER_DATA_HS_1 0x2D0D +#define mmSPI_SHADER_USER_DATA_HS_11 0x2D17 +#define mmSPI_SHADER_USER_DATA_HS_12 0x2D18 +#define mmSPI_SHADER_USER_DATA_HS_13 0x2D19 +#define mmSPI_SHADER_USER_DATA_HS_14 0x2D1A +#define mmSPI_SHADER_USER_DATA_HS_15 0x2D1B +#define mmSPI_SHADER_USER_DATA_HS_2 0x2D0E +#define mmSPI_SHADER_USER_DATA_HS_3 0x2D0F +#define mmSPI_SHADER_USER_DATA_HS_4 0x2D10 +#define mmSPI_SHADER_USER_DATA_HS_5 0x2D11 +#define mmSPI_SHADER_USER_DATA_HS_6 0x2D12 +#define mmSPI_SHADER_USER_DATA_HS_7 0x2D13 +#define mmSPI_SHADER_USER_DATA_HS_8 0x2D14 +#define mmSPI_SHADER_USER_DATA_HS_9 0x2D15 +#define mmSPI_SHADER_USER_DATA_LS_0 0x2D4C +#define mmSPI_SHADER_USER_DATA_LS_10 0x2D56 +#define mmSPI_SHADER_USER_DATA_LS_1 0x2D4D +#define mmSPI_SHADER_USER_DATA_LS_11 0x2D57 +#define mmSPI_SHADER_USER_DATA_LS_12 0x2D58 +#define mmSPI_SHADER_USER_DATA_LS_13 0x2D59 +#define mmSPI_SHADER_USER_DATA_LS_14 0x2D5A +#define mmSPI_SHADER_USER_DATA_LS_15 0x2D5B +#define mmSPI_SHADER_USER_DATA_LS_2 0x2D4E +#define mmSPI_SHADER_USER_DATA_LS_3 0x2D4F +#define mmSPI_SHADER_USER_DATA_LS_4 0x2D50 +#define mmSPI_SHADER_USER_DATA_LS_5 0x2D51 +#define mmSPI_SHADER_USER_DATA_LS_6 0x2D52 +#define mmSPI_SHADER_USER_DATA_LS_7 0x2D53 +#define mmSPI_SHADER_USER_DATA_LS_8 0x2D54 +#define mmSPI_SHADER_USER_DATA_LS_9 0x2D55 +#define mmSPI_SHADER_USER_DATA_PS_0 0x2C0C +#define mmSPI_SHADER_USER_DATA_PS_10 0x2C16 +#define mmSPI_SHADER_USER_DATA_PS_1 0x2C0D +#define mmSPI_SHADER_USER_DATA_PS_11 0x2C17 +#define mmSPI_SHADER_USER_DATA_PS_12 0x2C18 +#define mmSPI_SHADER_USER_DATA_PS_13 0x2C19 +#define mmSPI_SHADER_USER_DATA_PS_14 0x2C1A +#define mmSPI_SHADER_USER_DATA_PS_15 0x2C1B +#define mmSPI_SHADER_USER_DATA_PS_2 0x2C0E +#define mmSPI_SHADER_USER_DATA_PS_3 0x2C0F +#define mmSPI_SHADER_USER_DATA_PS_4 0x2C10 +#define mmSPI_SHADER_USER_DATA_PS_5 0x2C11 +#define mmSPI_SHADER_USER_DATA_PS_6 0x2C12 +#define mmSPI_SHADER_USER_DATA_PS_7 0x2C13 +#define mmSPI_SHADER_USER_DATA_PS_8 0x2C14 +#define mmSPI_SHADER_USER_DATA_PS_9 0x2C15 +#define mmSPI_SHADER_USER_DATA_VS_0 0x2C4C +#define mmSPI_SHADER_USER_DATA_VS_10 0x2C56 +#define mmSPI_SHADER_USER_DATA_VS_1 0x2C4D +#define mmSPI_SHADER_USER_DATA_VS_11 0x2C57 +#define mmSPI_SHADER_USER_DATA_VS_12 0x2C58 +#define mmSPI_SHADER_USER_DATA_VS_13 0x2C59 +#define mmSPI_SHADER_USER_DATA_VS_14 0x2C5A +#define mmSPI_SHADER_USER_DATA_VS_15 0x2C5B +#define mmSPI_SHADER_USER_DATA_VS_2 0x2C4E +#define mmSPI_SHADER_USER_DATA_VS_3 0x2C4F +#define mmSPI_SHADER_USER_DATA_VS_4 0x2C50 +#define mmSPI_SHADER_USER_DATA_VS_5 0x2C51 +#define mmSPI_SHADER_USER_DATA_VS_6 0x2C52 +#define mmSPI_SHADER_USER_DATA_VS_7 0x2C53 +#define mmSPI_SHADER_USER_DATA_VS_8 0x2C54 +#define mmSPI_SHADER_USER_DATA_VS_9 0x2C55 +#define mmSPI_SHADER_Z_FORMAT 0xA1C4 +#define mmSPI_SLAVE_DEBUG_BUSY 0x24D3 +#define mmSPI_SX_EXPORT_BUFFER_SIZES 0x24D9 +#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES 0x24DA +#define mmSPI_TMPRING_SIZE 0xA1BA +#define mmSPI_VS_OUT_CONFIG 0xA1B1 +#define mmSQ_ALU_CLK_CTRL 0x2360 +#define mmSQ_BUF_RSRC_WORD0 0x23C0 +#define mmSQ_BUF_RSRC_WORD1 0x23C1 +#define mmSQ_BUF_RSRC_WORD2 0x23C2 +#define mmSQ_BUF_RSRC_WORD3 0x23C3 +#define mmSQC_CACHES 0x2302 +#define mmSQC_CONFIG 0x2301 +#define mmSQ_CONFIG 0x2300 +#define mmSQC_SECDED_CNT 0x23A0 +#define mmSQ_DEBUG_STS_GLOBAL 0x2309 +#define mmSQ_DED_CNT 0x23A2 +#define mmSQ_DED_INFO 0x23A3 +#define mmSQ_DS_0 0x237F +#define mmSQ_DS_1 0x237F +#define mmSQ_EXP_0 0x237F +#define mmSQ_EXP_1 0x237F +#define mmSQ_FIFO_SIZES 0x2305 +#define mmSQ_IMG_RSRC_WORD0 0x23C4 +#define mmSQ_IMG_RSRC_WORD1 0x23C5 +#define mmSQ_IMG_RSRC_WORD2 0x23C6 +#define mmSQ_IMG_RSRC_WORD3 0x23C7 +#define mmSQ_IMG_RSRC_WORD4 0x23C8 +#define mmSQ_IMG_RSRC_WORD5 0x23C9 +#define mmSQ_IMG_RSRC_WORD6 0x23CA +#define mmSQ_IMG_RSRC_WORD7 0x23CB +#define mmSQ_IMG_SAMP_WORD0 0x23CC +#define mmSQ_IMG_SAMP_WORD1 0x23CD +#define mmSQ_IMG_SAMP_WORD2 0x23CE +#define mmSQ_IMG_SAMP_WORD3 0x23CF +#define mmSQ_IND_CMD 0x237A +#define mmSQ_IND_DATA 0x2379 +#define mmSQ_IND_INDEX 0x2378 +#define mmSQ_INST 0x237F +#define mmSQ_LB_CTR_CTRL 0x2398 +#define mmSQ_LB_DATA_ALU_CYCLES 0x2399 +#define mmSQ_LB_DATA_ALU_STALLS 0x239B +#define mmSQ_LB_DATA_TEX_CYCLES 0x239A +#define mmSQ_LB_DATA_TEX_STALLS 0x239C +#define mmSQ_MIMG_0 0x237F +#define mmSQ_MIMG_1 0x237F +#define mmSQ_MTBUF_0 0x237F +#define mmSQ_MTBUF_1 0x237F +#define mmSQ_MUBUF_0 0x237F +#define mmSQ_MUBUF_1 0x237F +#define mmSQ_PERFCOUNTER0_HI 0x2321 +#define mmSQ_PERFCOUNTER0_LO 0x2320 +#define mmSQ_PERFCOUNTER0_SELECT 0x2340 +#define mmSQ_PERFCOUNTER10_HI 0x2335 +#define mmSQ_PERFCOUNTER10_LO 0x2334 +#define mmSQ_PERFCOUNTER10_SELECT 0x234A +#define mmSQ_PERFCOUNTER11_HI 0x2337 +#define mmSQ_PERFCOUNTER11_LO 0x2336 +#define mmSQ_PERFCOUNTER11_SELECT 0x234B +#define mmSQ_PERFCOUNTER12_HI 0x2339 +#define mmSQ_PERFCOUNTER12_LO 0x2338 +#define mmSQ_PERFCOUNTER12_SELECT 0x234C +#define mmSQ_PERFCOUNTER13_HI 0x233B +#define mmSQ_PERFCOUNTER13_LO 0x233A +#define mmSQ_PERFCOUNTER13_SELECT 0x234D +#define mmSQ_PERFCOUNTER14_HI 0x233D +#define mmSQ_PERFCOUNTER14_LO 0x233C +#define mmSQ_PERFCOUNTER14_SELECT 0x234E +#define mmSQ_PERFCOUNTER15_HI 0x233F +#define mmSQ_PERFCOUNTER15_LO 0x233E +#define mmSQ_PERFCOUNTER15_SELECT 0x234F +#define mmSQ_PERFCOUNTER1_HI 0x2323 +#define mmSQ_PERFCOUNTER1_LO 0x2322 +#define mmSQ_PERFCOUNTER1_SELECT 0x2341 +#define mmSQ_PERFCOUNTER2_HI 0x2325 +#define mmSQ_PERFCOUNTER2_LO 0x2324 +#define mmSQ_PERFCOUNTER2_SELECT 0x2342 +#define mmSQ_PERFCOUNTER3_HI 0x2327 +#define mmSQ_PERFCOUNTER3_LO 0x2326 +#define mmSQ_PERFCOUNTER3_SELECT 0x2343 +#define mmSQ_PERFCOUNTER4_HI 0x2329 +#define mmSQ_PERFCOUNTER4_LO 0x2328 +#define mmSQ_PERFCOUNTER4_SELECT 0x2344 +#define mmSQ_PERFCOUNTER5_HI 0x232B +#define mmSQ_PERFCOUNTER5_LO 0x232A +#define mmSQ_PERFCOUNTER5_SELECT 0x2345 +#define mmSQ_PERFCOUNTER6_HI 0x232D +#define mmSQ_PERFCOUNTER6_LO 0x232C +#define mmSQ_PERFCOUNTER6_SELECT 0x2346 +#define mmSQ_PERFCOUNTER7_HI 0x232F +#define mmSQ_PERFCOUNTER7_LO 0x232E +#define mmSQ_PERFCOUNTER7_SELECT 0x2347 +#define mmSQ_PERFCOUNTER8_HI 0x2331 +#define mmSQ_PERFCOUNTER8_LO 0x2330 +#define mmSQ_PERFCOUNTER8_SELECT 0x2348 +#define mmSQ_PERFCOUNTER9_HI 0x2333 +#define mmSQ_PERFCOUNTER9_LO 0x2332 +#define mmSQ_PERFCOUNTER9_SELECT 0x2349 +#define mmSQ_PERFCOUNTER_CTRL 0x2306 +#define mmSQ_POWER_THROTTLE 0x2396 +#define mmSQ_POWER_THROTTLE2 0x2397 +#define mmSQ_RANDOM_WAVE_PRI 0x2303 +#define mmSQ_REG_CREDITS 0x2304 +#define mmSQ_SEC_CNT 0x23A1 +#define mmSQ_SMRD 0x237F +#define mmSQ_SOP1 0x237F +#define mmSQ_SOP2 0x237F +#define mmSQ_SOPC 0x237F +#define mmSQ_SOPK 0x237F +#define mmSQ_SOPP 0x237F +#define mmSQ_TEX_CLK_CTRL 0x2361 +#define mmSQ_THREAD_TRACE_BASE 0x2380 +#define mmSQ_THREAD_TRACE_CNTR 0x2390 +#define mmSQ_THREAD_TRACE_CTRL 0x238F +#define mmSQ_THREAD_TRACE_HIWATER 0x2392 +#define mmSQ_THREAD_TRACE_MASK 0x2382 +#define mmSQ_THREAD_TRACE_MODE 0x238E +#define mmSQ_THREAD_TRACE_PERF_MASK 0x2384 +#define mmSQ_THREAD_TRACE_SIZE 0x2381 +#define mmSQ_THREAD_TRACE_STATUS 0x238D +#define mmSQ_THREAD_TRACE_TOKEN_MASK 0x2383 +#define mmSQ_THREAD_TRACE_USERDATA_0 0x2388 +#define mmSQ_THREAD_TRACE_USERDATA_1 0x2389 +#define mmSQ_THREAD_TRACE_USERDATA_2 0x238A +#define mmSQ_THREAD_TRACE_USERDATA_3 0x238B +#define mmSQ_THREAD_TRACE_WORD_CMN 0x23B0 +#define mmSQ_THREAD_TRACE_WORD_EVENT 0x23B0 +#define mmSQ_THREAD_TRACE_WORD_INST 0x23B0 +#define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 0x23B0 +#define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 0x23B1 +#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 0x23B0 +#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 0x23B1 +#define mmSQ_THREAD_TRACE_WORD_ISSUE 0x23B0 +#define mmSQ_THREAD_TRACE_WORD_MISC 0x23B0 +#define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2 0x23B0 +#define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2 0x23B1 +#define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2 0x23B0 +#define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2 0x23B0 +#define mmSQ_THREAD_TRACE_WORD_TIME 0x23B0 +#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 0x23B0 +#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 0x23B1 +#define mmSQ_THREAD_TRACE_WORD_WAVE 0x23B0 +#define mmSQ_THREAD_TRACE_WORD_WAVE_START 0x23B0 +#define mmSQ_THREAD_TRACE_WPTR 0x238C +#define mmSQ_TIME_HI 0x237C +#define mmSQ_TIME_LO 0x237D +#define mmSQ_VINTRP 0x237F +#define mmSQ_VOP1 0x237F +#define mmSQ_VOP2 0x237F +#define mmSQ_VOP3_0 0x237F +#define mmSQ_VOP3_0_SDST_ENC 0x237F +#define mmSQ_VOP3_1 0x237F +#define mmSQ_VOPC 0x237F +#define mmSX_DEBUG_1 0x2418 +#define mmSX_DEBUG_BUSY 0x2414 +#define mmSX_DEBUG_BUSY_2 0x2415 +#define mmSX_DEBUG_BUSY_3 0x2416 +#define mmSX_DEBUG_BUSY_4 0x2417 +#define mmSX_PERFCOUNTER0_HI 0x2421 +#define mmSX_PERFCOUNTER0_LO 0x2420 +#define mmSX_PERFCOUNTER0_SELECT 0x241C +#define mmSX_PERFCOUNTER1_HI 0x2423 +#define mmSX_PERFCOUNTER1_LO 0x2422 +#define mmSX_PERFCOUNTER1_SELECT 0x241D +#define mmSX_PERFCOUNTER2_HI 0x2425 +#define mmSX_PERFCOUNTER2_LO 0x2424 +#define mmSX_PERFCOUNTER2_SELECT 0x241E +#define mmSX_PERFCOUNTER3_HI 0x2427 +#define mmSX_PERFCOUNTER3_LO 0x2426 +#define mmSX_PERFCOUNTER3_SELECT 0x241F +#define mmTA_BC_BASE_ADDR 0xA020 +#define mmTA_CGTT_CTRL 0x2544 +#define mmTA_CNTL 0x2541 +#define mmTA_CNTL_AUX 0x2542 +#define mmTA_CS_BC_BASE_ADDR 0x2543 +#define mmTA_DEBUG_DATA 0x254D +#define mmTA_DEBUG_INDEX 0x254C +#define mmTA_PERFCOUNTER0_HI 0x2556 +#define mmTA_PERFCOUNTER0_LO 0x2555 +#define mmTA_PERFCOUNTER0_SELECT 0x2554 +#define mmTA_PERFCOUNTER1_HI 0x2562 +#define mmTA_PERFCOUNTER1_LO 0x2561 +#define mmTA_PERFCOUNTER1_SELECT 0x2560 +#define mmTA_SCRATCH 0x2564 +#define mmTA_STATUS 0x2548 +#define mmTCA_CGTT_SCLK_CTRL 0x2BC1 +#define mmTCA_CTRL 0x2BC0 +#define mmTCA_PERFCOUNTER0_HI 0x2BD2 +#define mmTCA_PERFCOUNTER0_LO 0x2BD1 +#define mmTCA_PERFCOUNTER0_SELECT 0x2BD0 +#define mmTCA_PERFCOUNTER1_HI 0x2BD5 +#define mmTCA_PERFCOUNTER1_LO 0x2BD4 +#define mmTCA_PERFCOUNTER1_SELECT 0x2BD3 +#define mmTCA_PERFCOUNTER2_HI 0x2BD8 +#define mmTCA_PERFCOUNTER2_LO 0x2BD7 +#define mmTCA_PERFCOUNTER2_SELECT 0x2BD6 +#define mmTCA_PERFCOUNTER3_HI 0x2BDB +#define mmTCA_PERFCOUNTER3_LO 0x2BDA +#define mmTCA_PERFCOUNTER3_SELECT 0x2BD9 +#define mmTCC_CGTT_SCLK_CTRL 0x2B81 +#define mmTCC_CTRL 0x2B80 +#define mmTCC_EDC_COUNTER 0x2B82 +#define mmTCC_PERFCOUNTER0_HI 0x2B92 +#define mmTCC_PERFCOUNTER0_LO 0x2B91 +#define mmTCC_PERFCOUNTER0_SELECT 0x2B90 +#define mmTCC_PERFCOUNTER1_HI 0x2B95 +#define mmTCC_PERFCOUNTER1_LO 0x2B94 +#define mmTCC_PERFCOUNTER1_SELECT 0x2B93 +#define mmTCC_PERFCOUNTER2_HI 0x2B98 +#define mmTCC_PERFCOUNTER2_LO 0x2B97 +#define mmTCC_PERFCOUNTER2_SELECT 0x2B96 +#define mmTCC_PERFCOUNTER3_HI 0x2B9B +#define mmTCC_PERFCOUNTER3_LO 0x2B9A +#define mmTCC_PERFCOUNTER3_SELECT 0x2B99 +#define mmTCI_CNTL_1 0x2B62 +#define mmTCI_CNTL_2 0x2B63 +#define mmTCI_STATUS 0x2B61 +#define mmTCP_ADDR_CONFIG 0x2B05 +#define mmTCP_BUFFER_ADDR_HASH_CNTL 0x2B16 +#define mmTCP_CHAN_STEER_HI 0x2B04 +#define mmTCP_CHAN_STEER_LO 0x2B03 +#define mmTCP_CNTL 0x2B02 +#define mmTCP_CREDIT 0x2B06 +#define mmTCP_EDC_COUNTER 0x2B17 +#define mmTCP_INVALIDATE 0x2B00 +#define mmTCP_PERFCOUNTER0_HI 0x2B0A +#define mmTCP_PERFCOUNTER0_LO 0x2B0B +#define mmTCP_PERFCOUNTER0_SELECT 0x2B09 +#define mmTCP_PERFCOUNTER1_HI 0x2B0D +#define mmTCP_PERFCOUNTER1_LO 0x2B0E +#define mmTCP_PERFCOUNTER1_SELECT 0x2B0C +#define mmTCP_PERFCOUNTER2_HI 0x2B10 +#define mmTCP_PERFCOUNTER2_LO 0x2B11 +#define mmTCP_PERFCOUNTER2_SELECT 0x2B0F +#define mmTCP_PERFCOUNTER3_HI 0x2B13 +#define mmTCP_PERFCOUNTER3_LO 0x2B14 +#define mmTCP_PERFCOUNTER3_SELECT 0x2B12 +#define mmTCP_STATUS 0x2B01 +#define mmTD_CGTT_CTRL 0x2527 +#define mmTD_CNTL 0x2525 +#define mmTD_DEBUG_DATA 0x2529 +#define mmTD_DEBUG_INDEX 0x2528 +#define mmTD_PERFCOUNTER0_HI 0x252E +#define mmTD_PERFCOUNTER0_LO 0x252D +#define mmTD_PERFCOUNTER0_SELECT 0x252C +#define mmTD_SCRATCH 0x2530 +#define mmTD_STATUS 0x2526 +#define mmUSER_SQC_BANK_DISABLE 0x2308 +#define mmVGT_CACHE_INVALIDATION 0x2231 +#define mmVGT_CNTL_STATUS 0x223C +#define mmVGT_DEBUG_CNTL 0x2238 +#define mmVGT_DEBUG_DATA 0x2239 +#define mmVGT_DMA_BASE 0xA1FA +#define mmVGT_DMA_BASE_HI 0xA1F9 +#define mmVGT_DMA_DATA_FIFO_DEPTH 0x222D +#define mmVGT_DMA_INDEX_TYPE 0xA29F +#define mmVGT_DMA_MAX_SIZE 0xA29E +#define mmVGT_DMA_NUM_INSTANCES 0xA2A2 +#define mmVGT_DMA_REQ_FIFO_DEPTH 0x222E +#define mmVGT_DMA_SIZE 0xA29D +#define mmVGT_DRAW_INIT_FIFO_DEPTH 0x222F +#define mmVGT_DRAW_INITIATOR 0xA1FC +#define mmVGT_ENHANCE 0xA294 +#define mmVGT_ESGS_RING_ITEMSIZE 0xA2AB +#define mmVGT_ESGS_RING_SIZE 0x2232 +#define mmVGT_ES_PER_GS 0xA296 +#define mmVGT_EVENT_ADDRESS_REG 0xA1FE +#define mmVGT_EVENT_INITIATOR 0xA2A4 +#define mmVGT_FIFO_DEPTHS 0x2234 +#define mmVGT_GROUP_DECR 0xA28B +#define mmVGT_GROUP_FIRST_DECR 0xA28A +#define mmVGT_GROUP_PRIM_TYPE 0xA289 +#define mmVGT_GROUP_VECT_0_CNTL 0xA28C +#define mmVGT_GROUP_VECT_0_FMT_CNTL 0xA28E +#define mmVGT_GROUP_VECT_1_CNTL 0xA28D +#define mmVGT_GROUP_VECT_1_FMT_CNTL 0xA28F +#define mmVGT_GS_INSTANCE_CNT 0xA2E4 +#define mmVGT_GS_MAX_VERT_OUT 0xA2CE +#define mmVGT_GS_MODE 0xA290 +#define mmVGT_GS_OUT_PRIM_TYPE 0xA29B +#define mmVGT_GS_PER_ES 0xA295 +#define mmVGT_GS_PER_VS 0xA297 +#define mmVGT_GS_VERTEX_REUSE 0x2235 +#define mmVGT_GS_VERT_ITEMSIZE 0xA2D7 +#define mmVGT_GS_VERT_ITEMSIZE_1 0xA2D8 +#define mmVGT_GS_VERT_ITEMSIZE_2 0xA2D9 +#define mmVGT_GS_VERT_ITEMSIZE_3 0xA2DA +#define mmVGT_GSVS_RING_ITEMSIZE 0xA2AC +#define mmVGT_GSVS_RING_OFFSET_1 0xA298 +#define mmVGT_GSVS_RING_OFFSET_2 0xA299 +#define mmVGT_GSVS_RING_OFFSET_3 0xA29A +#define mmVGT_GSVS_RING_SIZE 0x2233 +#define mmVGT_HOS_CNTL 0xA285 +#define mmVGT_HOS_MAX_TESS_LEVEL 0xA286 +#define mmVGT_HOS_MIN_TESS_LEVEL 0xA287 +#define mmVGT_HOS_REUSE_DEPTH 0xA288 +#define mmVGT_HS_OFFCHIP_PARAM 0x226C +#define mmVGT_IMMED_DATA 0xA1FD +#define mmVGT_INDEX_TYPE 0x2257 +#define mmVGT_INDX_OFFSET 0xA102 +#define mmVGT_INSTANCE_STEP_RATE_0 0xA2A8 +#define mmVGT_INSTANCE_STEP_RATE_1 0xA2A9 +#define mmVGT_LAST_COPY_STATE 0x2230 +#define mmVGT_LS_HS_CONFIG 0xA2D6 +#define mmVGT_MAX_VTX_INDX 0xA100 +#define mmVGT_MC_LAT_CNTL 0x2236 +#define mmVGT_MIN_VTX_INDX 0xA101 +#define mmVGT_MULTI_PRIM_IB_RESET_EN 0xA2A5 +#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0xA103 +#define mmVGT_NUM_INDICES 0x225C +#define mmVGT_NUM_INSTANCES 0x225D +#define mmVGT_OUT_DEALLOC_CNTL 0xA317 +#define mmVGT_OUTPUT_PATH_CNTL 0xA284 +#define mmVGT_PERFCOUNTER0_HI 0x224D +#define mmVGT_PERFCOUNTER0_LO 0x224C +#define mmVGT_PERFCOUNTER0_SELECT 0x2248 +#define mmVGT_PERFCOUNTER1_HI 0x224F +#define mmVGT_PERFCOUNTER1_LO 0x224E +#define mmVGT_PERFCOUNTER1_SELECT 0x2249 +#define mmVGT_PERFCOUNTER2_HI 0x2251 +#define mmVGT_PERFCOUNTER2_LO 0x2250 +#define mmVGT_PERFCOUNTER2_SELECT 0x224A +#define mmVGT_PERFCOUNTER3_HI 0x2253 +#define mmVGT_PERFCOUNTER3_LO 0x2252 +#define mmVGT_PERFCOUNTER3_SELECT 0x224B +#define mmVGT_PERFCOUNTER_SEID_MASK 0x2247 +#define mmVGT_PRIMITIVEID_EN 0xA2A1 +#define mmVGT_PRIMITIVEID_RESET 0xA2A3 +#define mmVGT_PRIMITIVE_TYPE 0x2256 +#define mmVGT_REUSE_OFF 0xA2AD +#define mmVGT_SHADER_STAGES_EN 0xA2D5 +#define mmVGT_STRMOUT_BUFFER_CONFIG 0xA2E6 +#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0 0x2258 +#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1 0x2259 +#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2 0x225A +#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3 0x225B +#define mmVGT_STRMOUT_BUFFER_OFFSET_0 0xA2B7 +#define mmVGT_STRMOUT_BUFFER_OFFSET_1 0xA2BB +#define mmVGT_STRMOUT_BUFFER_OFFSET_2 0xA2BF +#define mmVGT_STRMOUT_BUFFER_OFFSET_3 0xA2C3 +#define mmVGT_STRMOUT_BUFFER_SIZE_0 0xA2B4 +#define mmVGT_STRMOUT_BUFFER_SIZE_1 0xA2B8 +#define mmVGT_STRMOUT_BUFFER_SIZE_2 0xA2BC +#define mmVGT_STRMOUT_BUFFER_SIZE_3 0xA2C0 +#define mmVGT_STRMOUT_CONFIG 0xA2E5 +#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0xA2CB +#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET 0xA2CA +#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0xA2CC +#define mmVGT_STRMOUT_VTX_STRIDE_0 0xA2B5 +#define mmVGT_STRMOUT_VTX_STRIDE_1 0xA2B9 +#define mmVGT_STRMOUT_VTX_STRIDE_2 0xA2BD +#define mmVGT_STRMOUT_VTX_STRIDE_3 0xA2C1 +#define mmVGT_SYS_CONFIG 0x2263 +#define mmVGT_TF_MEMORY_BASE 0x226E +#define mmVGT_TF_PARAM 0xA2DB +#define mmVGT_TF_RING_SIZE 0x2262 +#define mmVGT_VERTEX_REUSE_BLOCK_CNTL 0xA316 +#define mmVGT_VTX_CNT_EN 0xA2AE +#define mmVGT_VTX_VECT_EJECT_REG 0x222C + +/* manually added from old sid.h */ +#define mmCB_PERFCOUNTER0_SELECT0 0x2688 +#define mmCB_PERFCOUNTER1_SELECT0 0x268A +#define mmCB_PERFCOUNTER1_SELECT1 0x268B +#define mmCB_PERFCOUNTER2_SELECT0 0x268C +#define mmCB_PERFCOUNTER2_SELECT1 0x268D +#define mmCB_PERFCOUNTER3_SELECT0 0x268E +#define mmCB_PERFCOUNTER3_SELECT1 0x268F +#define mmCP_COHER_CNTL2 0x217A +#define mmCP_DEBUG 0x307F +#define mmRLC_SERDES_MASTER_BUSY_0 0x3119 +#define mmRLC_SERDES_MASTER_BUSY_1 0x311A +#define mmRLC_RL_BASE 0x30C1 +#define mmRLC_RL_SIZE 0x30C2 +#define mmRLC_UCODE_ADDR 0x30CB +#define mmRLC_UCODE_DATA 0x30CC +#define mmRLC_GCPM_GENERAL_3 0x311E +#define mmRLC_SERDES_WR_MASTER_MASK_0 0x3115 +#define mmRLC_SERDES_WR_MASTER_MASK_1 0x3116 +#define mmRLC_TTOP_D 0x3105 +#define mmRLC_CLEAR_STATE_RESTORE_BASE 0x30C8 +#define mmRLC_PG_AO_CU_MASK 0x310B +#define mmSPI_STATIC_THREAD_MGMT_3 0x243A + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h new file mode 100644 index 000000000000..b5e634749665 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h @@ -0,0 +1,12821 @@ +/* + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef GFX_6_0_SH_MASK_H +#define GFX_6_0_SH_MASK_H + +#define BCI_DEBUG_READ__DATA_MASK 0x00ffffffL +#define BCI_DEBUG_READ__DATA__SHIFT 0x00000000 +#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L +#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 +#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L +#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 +#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L +#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 +#define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L +#define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 +#define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L +#define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 +#define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL +#define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 +#define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000L +#define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f +#define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x0000001e +#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d +#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L +#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 +#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L +#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 +#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L +#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 +#define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L +#define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 +#define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L +#define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 +#define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL +#define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 +#define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000L +#define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f +#define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x0000001e +#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d +#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L +#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 +#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L +#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 +#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L +#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 +#define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L +#define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 +#define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L +#define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 +#define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL +#define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 +#define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000L +#define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f +#define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x0000001e +#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d +#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L +#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 +#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L +#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 +#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L +#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 +#define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L +#define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 +#define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L +#define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 +#define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL +#define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 +#define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000L +#define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f +#define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x0000001e +#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d +#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L +#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 +#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L +#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 +#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L +#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 +#define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L +#define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 +#define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L +#define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 +#define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL +#define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 +#define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000L +#define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f +#define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x0000001e +#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d +#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L +#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 +#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L +#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 +#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L +#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 +#define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L +#define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 +#define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L +#define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 +#define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL +#define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 +#define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000L +#define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f +#define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x0000001e +#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d +#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L +#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 +#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L +#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 +#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L +#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 +#define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L +#define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 +#define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L +#define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 +#define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL +#define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 +#define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000L +#define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f +#define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x0000001e +#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d +#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L +#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 +#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L +#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 +#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L +#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 +#define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L +#define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 +#define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L +#define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 +#define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL +#define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 +#define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000L +#define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f +#define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x0000001e +#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d +#define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffffL +#define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x00000000 +#define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffffL +#define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x00000000 +#define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffffL +#define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x00000000 +#define CB_BLEND_RED__BLEND_RED_MASK 0xffffffffL +#define CB_BLEND_RED__BLEND_RED__SHIFT 0x00000000 +#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L +#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 +#define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000fL +#define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x00000000 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 +#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L +#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a +#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L +#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005 +#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L +#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011 +#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L +#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f +#define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x00007000L +#define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c +#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL +#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000 +#define CB_COLOR0_BASE__BASE_256B_MASK 0xffffffffL +#define CB_COLOR0_BASE__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL +#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000 +#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL +#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000 +#define CB_COLOR0_CMASK__BASE_256B_MASK 0xffffffffL +#define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR0_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL +#define CB_COLOR0_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR0_FMASK__BASE_256B_MASK 0xffffffffL +#define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR0_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL +#define CB_COLOR0_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x00000010 +#define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0x0000000f +#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017 +#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014 +#define CB_COLOR0_INFO__CMASK_IS_LINEAR_MASK 0x00080000L +#define CB_COLOR0_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013 +#define CB_COLOR0_INFO__COMPRESSION_MASK 0x00004000L +#define CB_COLOR0_INFO__COMPRESSION__SHIFT 0x0000000e +#define CB_COLOR0_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0x0000000b +#define CB_COLOR0_INFO__ENDIAN_MASK 0x00000003L +#define CB_COLOR0_INFO__ENDIAN__SHIFT 0x00000000 +#define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x00002000L +#define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0x0000000d +#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L +#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a +#define CB_COLOR0_INFO__FORMAT_MASK 0x0000007cL +#define CB_COLOR0_INFO__FORMAT__SHIFT 0x00000002 +#define CB_COLOR0_INFO__LINEAR_GENERAL_MASK 0x00000080L +#define CB_COLOR0_INFO__LINEAR_GENERAL__SHIFT 0x00000007 +#define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x00000008 +#define CB_COLOR0_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x00000012 +#define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x00000011 +#define CB_COLOR0_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L +#define CB_COLOR0_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014 +#define CB_COLOR0_PITCH__TILE_MAX_MASK 0x000007ffL +#define CB_COLOR0_PITCH__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR0_SLICE__TILE_MAX_MASK 0x003fffffL +#define CB_COLOR0_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR0_VIEW__SLICE_MAX_MASK 0x00ffe000L +#define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0x0000000d +#define CB_COLOR0_VIEW__SLICE_START_MASK 0x000007ffL +#define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x00000000 +#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L +#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a +#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L +#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005 +#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L +#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011 +#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L +#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f +#define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x00007000L +#define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c +#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL +#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000 +#define CB_COLOR1_BASE__BASE_256B_MASK 0xffffffffL +#define CB_COLOR1_BASE__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL +#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000 +#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL +#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000 +#define CB_COLOR1_CMASK__BASE_256B_MASK 0xffffffffL +#define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR1_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL +#define CB_COLOR1_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR1_FMASK__BASE_256B_MASK 0xffffffffL +#define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR1_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL +#define CB_COLOR1_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x00000010 +#define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0x0000000f +#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017 +#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014 +#define CB_COLOR1_INFO__CMASK_IS_LINEAR_MASK 0x00080000L +#define CB_COLOR1_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013 +#define CB_COLOR1_INFO__COMPRESSION_MASK 0x00004000L +#define CB_COLOR1_INFO__COMPRESSION__SHIFT 0x0000000e +#define CB_COLOR1_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0x0000000b +#define CB_COLOR1_INFO__ENDIAN_MASK 0x00000003L +#define CB_COLOR1_INFO__ENDIAN__SHIFT 0x00000000 +#define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x00002000L +#define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0x0000000d +#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L +#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a +#define CB_COLOR1_INFO__FORMAT_MASK 0x0000007cL +#define CB_COLOR1_INFO__FORMAT__SHIFT 0x00000002 +#define CB_COLOR1_INFO__LINEAR_GENERAL_MASK 0x00000080L +#define CB_COLOR1_INFO__LINEAR_GENERAL__SHIFT 0x00000007 +#define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x00000008 +#define CB_COLOR1_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x00000012 +#define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x00000011 +#define CB_COLOR1_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L +#define CB_COLOR1_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014 +#define CB_COLOR1_PITCH__TILE_MAX_MASK 0x000007ffL +#define CB_COLOR1_PITCH__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR1_SLICE__TILE_MAX_MASK 0x003fffffL +#define CB_COLOR1_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR1_VIEW__SLICE_MAX_MASK 0x00ffe000L +#define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0x0000000d +#define CB_COLOR1_VIEW__SLICE_START_MASK 0x000007ffL +#define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x00000000 +#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L +#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a +#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L +#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005 +#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L +#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011 +#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L +#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f +#define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x00007000L +#define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c +#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL +#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000 +#define CB_COLOR2_BASE__BASE_256B_MASK 0xffffffffL +#define CB_COLOR2_BASE__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL +#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000 +#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL +#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000 +#define CB_COLOR2_CMASK__BASE_256B_MASK 0xffffffffL +#define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR2_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL +#define CB_COLOR2_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR2_FMASK__BASE_256B_MASK 0xffffffffL +#define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR2_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL +#define CB_COLOR2_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x00000010 +#define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0x0000000f +#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017 +#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014 +#define CB_COLOR2_INFO__CMASK_IS_LINEAR_MASK 0x00080000L +#define CB_COLOR2_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013 +#define CB_COLOR2_INFO__COMPRESSION_MASK 0x00004000L +#define CB_COLOR2_INFO__COMPRESSION__SHIFT 0x0000000e +#define CB_COLOR2_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0x0000000b +#define CB_COLOR2_INFO__ENDIAN_MASK 0x00000003L +#define CB_COLOR2_INFO__ENDIAN__SHIFT 0x00000000 +#define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x00002000L +#define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0x0000000d +#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L +#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a +#define CB_COLOR2_INFO__FORMAT_MASK 0x0000007cL +#define CB_COLOR2_INFO__FORMAT__SHIFT 0x00000002 +#define CB_COLOR2_INFO__LINEAR_GENERAL_MASK 0x00000080L +#define CB_COLOR2_INFO__LINEAR_GENERAL__SHIFT 0x00000007 +#define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x00000008 +#define CB_COLOR2_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x00000012 +#define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x00000011 +#define CB_COLOR2_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L +#define CB_COLOR2_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014 +#define CB_COLOR2_PITCH__TILE_MAX_MASK 0x000007ffL +#define CB_COLOR2_PITCH__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR2_SLICE__TILE_MAX_MASK 0x003fffffL +#define CB_COLOR2_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR2_VIEW__SLICE_MAX_MASK 0x00ffe000L +#define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0x0000000d +#define CB_COLOR2_VIEW__SLICE_START_MASK 0x000007ffL +#define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x00000000 +#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L +#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a +#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L +#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005 +#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L +#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011 +#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L +#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f +#define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x00007000L +#define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c +#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL +#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000 +#define CB_COLOR3_BASE__BASE_256B_MASK 0xffffffffL +#define CB_COLOR3_BASE__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL +#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000 +#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL +#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000 +#define CB_COLOR3_CMASK__BASE_256B_MASK 0xffffffffL +#define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR3_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL +#define CB_COLOR3_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR3_FMASK__BASE_256B_MASK 0xffffffffL +#define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR3_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL +#define CB_COLOR3_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x00000010 +#define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0x0000000f +#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017 +#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014 +#define CB_COLOR3_INFO__CMASK_IS_LINEAR_MASK 0x00080000L +#define CB_COLOR3_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013 +#define CB_COLOR3_INFO__COMPRESSION_MASK 0x00004000L +#define CB_COLOR3_INFO__COMPRESSION__SHIFT 0x0000000e +#define CB_COLOR3_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0x0000000b +#define CB_COLOR3_INFO__ENDIAN_MASK 0x00000003L +#define CB_COLOR3_INFO__ENDIAN__SHIFT 0x00000000 +#define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x00002000L +#define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0x0000000d +#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L +#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a +#define CB_COLOR3_INFO__FORMAT_MASK 0x0000007cL +#define CB_COLOR3_INFO__FORMAT__SHIFT 0x00000002 +#define CB_COLOR3_INFO__LINEAR_GENERAL_MASK 0x00000080L +#define CB_COLOR3_INFO__LINEAR_GENERAL__SHIFT 0x00000007 +#define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x00000008 +#define CB_COLOR3_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x00000012 +#define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x00000011 +#define CB_COLOR3_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L +#define CB_COLOR3_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014 +#define CB_COLOR3_PITCH__TILE_MAX_MASK 0x000007ffL +#define CB_COLOR3_PITCH__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR3_SLICE__TILE_MAX_MASK 0x003fffffL +#define CB_COLOR3_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR3_VIEW__SLICE_MAX_MASK 0x00ffe000L +#define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0x0000000d +#define CB_COLOR3_VIEW__SLICE_START_MASK 0x000007ffL +#define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x00000000 +#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L +#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a +#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L +#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005 +#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L +#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011 +#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L +#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f +#define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x00007000L +#define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c +#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL +#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000 +#define CB_COLOR4_BASE__BASE_256B_MASK 0xffffffffL +#define CB_COLOR4_BASE__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL +#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000 +#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL +#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000 +#define CB_COLOR4_CMASK__BASE_256B_MASK 0xffffffffL +#define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR4_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL +#define CB_COLOR4_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR4_FMASK__BASE_256B_MASK 0xffffffffL +#define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR4_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL +#define CB_COLOR4_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x00000010 +#define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0x0000000f +#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017 +#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014 +#define CB_COLOR4_INFO__CMASK_IS_LINEAR_MASK 0x00080000L +#define CB_COLOR4_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013 +#define CB_COLOR4_INFO__COMPRESSION_MASK 0x00004000L +#define CB_COLOR4_INFO__COMPRESSION__SHIFT 0x0000000e +#define CB_COLOR4_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0x0000000b +#define CB_COLOR4_INFO__ENDIAN_MASK 0x00000003L +#define CB_COLOR4_INFO__ENDIAN__SHIFT 0x00000000 +#define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x00002000L +#define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0x0000000d +#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L +#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a +#define CB_COLOR4_INFO__FORMAT_MASK 0x0000007cL +#define CB_COLOR4_INFO__FORMAT__SHIFT 0x00000002 +#define CB_COLOR4_INFO__LINEAR_GENERAL_MASK 0x00000080L +#define CB_COLOR4_INFO__LINEAR_GENERAL__SHIFT 0x00000007 +#define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x00000008 +#define CB_COLOR4_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x00000012 +#define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x00000011 +#define CB_COLOR4_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L +#define CB_COLOR4_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014 +#define CB_COLOR4_PITCH__TILE_MAX_MASK 0x000007ffL +#define CB_COLOR4_PITCH__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR4_SLICE__TILE_MAX_MASK 0x003fffffL +#define CB_COLOR4_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR4_VIEW__SLICE_MAX_MASK 0x00ffe000L +#define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0x0000000d +#define CB_COLOR4_VIEW__SLICE_START_MASK 0x000007ffL +#define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x00000000 +#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L +#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a +#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L +#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005 +#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L +#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011 +#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L +#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f +#define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x00007000L +#define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c +#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL +#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000 +#define CB_COLOR5_BASE__BASE_256B_MASK 0xffffffffL +#define CB_COLOR5_BASE__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL +#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000 +#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL +#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000 +#define CB_COLOR5_CMASK__BASE_256B_MASK 0xffffffffL +#define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR5_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL +#define CB_COLOR5_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR5_FMASK__BASE_256B_MASK 0xffffffffL +#define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR5_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL +#define CB_COLOR5_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x00000010 +#define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0x0000000f +#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017 +#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014 +#define CB_COLOR5_INFO__CMASK_IS_LINEAR_MASK 0x00080000L +#define CB_COLOR5_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013 +#define CB_COLOR5_INFO__COMPRESSION_MASK 0x00004000L +#define CB_COLOR5_INFO__COMPRESSION__SHIFT 0x0000000e +#define CB_COLOR5_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0x0000000b +#define CB_COLOR5_INFO__ENDIAN_MASK 0x00000003L +#define CB_COLOR5_INFO__ENDIAN__SHIFT 0x00000000 +#define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x00002000L +#define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0x0000000d +#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L +#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a +#define CB_COLOR5_INFO__FORMAT_MASK 0x0000007cL +#define CB_COLOR5_INFO__FORMAT__SHIFT 0x00000002 +#define CB_COLOR5_INFO__LINEAR_GENERAL_MASK 0x00000080L +#define CB_COLOR5_INFO__LINEAR_GENERAL__SHIFT 0x00000007 +#define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x00000008 +#define CB_COLOR5_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x00000012 +#define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x00000011 +#define CB_COLOR5_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L +#define CB_COLOR5_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014 +#define CB_COLOR5_PITCH__TILE_MAX_MASK 0x000007ffL +#define CB_COLOR5_PITCH__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR5_SLICE__TILE_MAX_MASK 0x003fffffL +#define CB_COLOR5_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR5_VIEW__SLICE_MAX_MASK 0x00ffe000L +#define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0x0000000d +#define CB_COLOR5_VIEW__SLICE_START_MASK 0x000007ffL +#define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x00000000 +#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L +#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a +#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L +#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005 +#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L +#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011 +#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L +#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f +#define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x00007000L +#define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c +#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL +#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000 +#define CB_COLOR6_BASE__BASE_256B_MASK 0xffffffffL +#define CB_COLOR6_BASE__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL +#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000 +#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL +#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000 +#define CB_COLOR6_CMASK__BASE_256B_MASK 0xffffffffL +#define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR6_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL +#define CB_COLOR6_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR6_FMASK__BASE_256B_MASK 0xffffffffL +#define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR6_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL +#define CB_COLOR6_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x00000010 +#define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0x0000000f +#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017 +#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014 +#define CB_COLOR6_INFO__CMASK_IS_LINEAR_MASK 0x00080000L +#define CB_COLOR6_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013 +#define CB_COLOR6_INFO__COMPRESSION_MASK 0x00004000L +#define CB_COLOR6_INFO__COMPRESSION__SHIFT 0x0000000e +#define CB_COLOR6_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0x0000000b +#define CB_COLOR6_INFO__ENDIAN_MASK 0x00000003L +#define CB_COLOR6_INFO__ENDIAN__SHIFT 0x00000000 +#define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x00002000L +#define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0x0000000d +#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L +#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a +#define CB_COLOR6_INFO__FORMAT_MASK 0x0000007cL +#define CB_COLOR6_INFO__FORMAT__SHIFT 0x00000002 +#define CB_COLOR6_INFO__LINEAR_GENERAL_MASK 0x00000080L +#define CB_COLOR6_INFO__LINEAR_GENERAL__SHIFT 0x00000007 +#define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x00000008 +#define CB_COLOR6_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x00000012 +#define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x00000011 +#define CB_COLOR6_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L +#define CB_COLOR6_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014 +#define CB_COLOR6_PITCH__TILE_MAX_MASK 0x000007ffL +#define CB_COLOR6_PITCH__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR6_SLICE__TILE_MAX_MASK 0x003fffffL +#define CB_COLOR6_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR6_VIEW__SLICE_MAX_MASK 0x00ffe000L +#define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0x0000000d +#define CB_COLOR6_VIEW__SLICE_START_MASK 0x000007ffL +#define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x00000000 +#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L +#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a +#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L +#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005 +#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L +#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011 +#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L +#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f +#define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x00007000L +#define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c +#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL +#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000 +#define CB_COLOR7_BASE__BASE_256B_MASK 0xffffffffL +#define CB_COLOR7_BASE__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL +#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000 +#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL +#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000 +#define CB_COLOR7_CMASK__BASE_256B_MASK 0xffffffffL +#define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR7_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL +#define CB_COLOR7_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR7_FMASK__BASE_256B_MASK 0xffffffffL +#define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR7_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL +#define CB_COLOR7_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x00000010 +#define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0x0000000f +#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017 +#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014 +#define CB_COLOR7_INFO__CMASK_IS_LINEAR_MASK 0x00080000L +#define CB_COLOR7_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013 +#define CB_COLOR7_INFO__COMPRESSION_MASK 0x00004000L +#define CB_COLOR7_INFO__COMPRESSION__SHIFT 0x0000000e +#define CB_COLOR7_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0x0000000b +#define CB_COLOR7_INFO__ENDIAN_MASK 0x00000003L +#define CB_COLOR7_INFO__ENDIAN__SHIFT 0x00000000 +#define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x00002000L +#define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0x0000000d +#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L +#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a +#define CB_COLOR7_INFO__FORMAT_MASK 0x0000007cL +#define CB_COLOR7_INFO__FORMAT__SHIFT 0x00000002 +#define CB_COLOR7_INFO__LINEAR_GENERAL_MASK 0x00000080L +#define CB_COLOR7_INFO__LINEAR_GENERAL__SHIFT 0x00000007 +#define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x00000008 +#define CB_COLOR7_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x00000012 +#define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x00000011 +#define CB_COLOR7_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L +#define CB_COLOR7_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014 +#define CB_COLOR7_PITCH__TILE_MAX_MASK 0x000007ffL +#define CB_COLOR7_PITCH__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR7_SLICE__TILE_MAX_MASK 0x003fffffL +#define CB_COLOR7_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR7_VIEW__SLICE_MAX_MASK 0x00ffe000L +#define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0x0000000d +#define CB_COLOR7_VIEW__SLICE_START_MASK 0x000007ffL +#define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x00000000 +#define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x00000008L +#define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x00000003 +#define CB_COLOR_CONTROL__MODE_MASK 0x00000070L +#define CB_COLOR_CONTROL__MODE__SHIFT 0x00000004 +#define CB_COLOR_CONTROL__ROP3_MASK 0x00ff0000L +#define CB_COLOR_CONTROL__ROP3__SHIFT 0x00000010 +#define CB_DEBUG_BUS_13__AC_BUSY_MASK 0x00000008L +#define CB_DEBUG_BUS_13__AC_BUSY__SHIFT 0x00000003 +#define CB_DEBUG_BUS_13__CACHE_CTRL_BUSY_MASK 0x00000020L +#define CB_DEBUG_BUS_13__CACHE_CTRL_BUSY__SHIFT 0x00000005 +#define CB_DEBUG_BUS_13__CRW_BUSY_MASK 0x00000010L +#define CB_DEBUG_BUS_13__CRW_BUSY__SHIFT 0x00000004 +#define CB_DEBUG_BUS_13__EVICT_PENDING_MASK 0x00000200L +#define CB_DEBUG_BUS_13__EVICT_PENDING__SHIFT 0x00000009 +#define CB_DEBUG_BUS_13__FC_RD_PENDING_MASK 0x00000100L +#define CB_DEBUG_BUS_13__FC_RD_PENDING__SHIFT 0x00000008 +#define CB_DEBUG_BUS_13__FC_WR_PENDING_MASK 0x00000080L +#define CB_DEBUG_BUS_13__FC_WR_PENDING__SHIFT 0x00000007 +#define CB_DEBUG_BUS_13__LAST_RD_ARB_WINNER_MASK 0x00000400L +#define CB_DEBUG_BUS_13__LAST_RD_ARB_WINNER__SHIFT 0x0000000a +#define CB_DEBUG_BUS_13__MC_WR_PENDING_MASK 0x00000040L +#define CB_DEBUG_BUS_13__MC_WR_PENDING__SHIFT 0x00000006 +#define CB_DEBUG_BUS_13__MU_BUSY_MASK 0x00000002L +#define CB_DEBUG_BUS_13__MU_BUSY__SHIFT 0x00000001 +#define CB_DEBUG_BUS_13__MU_STATE_MASK 0x0007f800L +#define CB_DEBUG_BUS_13__MU_STATE__SHIFT 0x0000000b +#define CB_DEBUG_BUS_13__TILE_INTFC_BUSY_MASK 0x00000001L +#define CB_DEBUG_BUS_13__TILE_INTFC_BUSY__SHIFT 0x00000000 +#define CB_DEBUG_BUS_13__TQ_BUSY_MASK 0x00000004L +#define CB_DEBUG_BUS_13__TQ_BUSY__SHIFT 0x00000002 +#define CB_DEBUG_BUS_14__ADDR_BUSY_MASK 0x00000010L +#define CB_DEBUG_BUS_14__ADDR_BUSY__SHIFT 0x00000004 +#define CB_DEBUG_BUS_14__CACHE_CTL_BUSY_MASK 0x00000008L +#define CB_DEBUG_BUS_14__CACHE_CTL_BUSY__SHIFT 0x00000003 +#define CB_DEBUG_BUS_14__CLEAR_BUSY_MASK 0x00000100L +#define CB_DEBUG_BUS_14__CLEAR_BUSY__SHIFT 0x00000008 +#define CB_DEBUG_BUS_14__FOP_BUSY_MASK 0x00000002L +#define CB_DEBUG_BUS_14__FOP_BUSY__SHIFT 0x00000001 +#define CB_DEBUG_BUS_14__LAT_BUSY_MASK 0x00000004L +#define CB_DEBUG_BUS_14__LAT_BUSY__SHIFT 0x00000002 +#define CB_DEBUG_BUS_14__MERGE_BUSY_MASK 0x00000020L +#define CB_DEBUG_BUS_14__MERGE_BUSY__SHIFT 0x00000005 +#define CB_DEBUG_BUS_14__QUAD_BUSY_MASK 0x00000040L +#define CB_DEBUG_BUS_14__QUAD_BUSY__SHIFT 0x00000006 +#define CB_DEBUG_BUS_14__TILE_BUSY_MASK 0x00000080L +#define CB_DEBUG_BUS_14__TILE_BUSY__SHIFT 0x00000007 +#define CB_DEBUG_BUS_14__TILE_RETIREMENT_BUSY_MASK 0x00000001L +#define CB_DEBUG_BUS_14__TILE_RETIREMENT_BUSY__SHIFT 0x00000000 +#define CB_DEBUG_BUS_15__CS_BUSY_MASK 0x00000010L +#define CB_DEBUG_BUS_15__CS_BUSY__SHIFT 0x00000004 +#define CB_DEBUG_BUS_15__DS_BUSY_MASK 0x00000040L +#define CB_DEBUG_BUS_15__DS_BUSY__SHIFT 0x00000006 +#define CB_DEBUG_BUS_15__IB_BUSY_MASK 0x00000100L +#define CB_DEBUG_BUS_15__IB_BUSY__SHIFT 0x00000008 +#define CB_DEBUG_BUS_15__RB_BUSY_MASK 0x00000020L +#define CB_DEBUG_BUS_15__RB_BUSY__SHIFT 0x00000005 +#define CB_DEBUG_BUS_15__SF_BUSY_MASK 0x00000008L +#define CB_DEBUG_BUS_15__SF_BUSY__SHIFT 0x00000003 +#define CB_DEBUG_BUS_15__SURF_SYNC_START_MASK 0x00000004L +#define CB_DEBUG_BUS_15__SURF_SYNC_START__SHIFT 0x00000002 +#define CB_DEBUG_BUS_15__SURF_SYNC_STATE_MASK 0x00000003L +#define CB_DEBUG_BUS_15__SURF_SYNC_STATE__SHIFT 0x00000000 +#define CB_DEBUG_BUS_15__TB_BUSY_MASK 0x00000080L +#define CB_DEBUG_BUS_15__TB_BUSY__SHIFT 0x00000007 +#define CB_DEBUG_BUS_16__CC_WRREQ_FIFO_EMPTY_MASK 0x00100000L +#define CB_DEBUG_BUS_16__CC_WRREQ_FIFO_EMPTY__SHIFT 0x00000014 +#define CB_DEBUG_BUS_16__CM_WRREQ_FIFO_EMPTY_MASK 0x00400000L +#define CB_DEBUG_BUS_16__CM_WRREQ_FIFO_EMPTY__SHIFT 0x00000016 +#define CB_DEBUG_BUS_16__FC_WRREQ_FIFO_EMPTY_MASK 0x00200000L +#define CB_DEBUG_BUS_16__FC_WRREQ_FIFO_EMPTY__SHIFT 0x00000015 +#define CB_DEBUG_BUS_16__LAST_RD_GRANT_VEC_MASK 0x000003c0L +#define CB_DEBUG_BUS_16__LAST_RD_GRANT_VEC__SHIFT 0x00000006 +#define CB_DEBUG_BUS_16__LAST_WR_GRANT_VEC_MASK 0x000f0000L +#define CB_DEBUG_BUS_16__LAST_WR_GRANT_VEC__SHIFT 0x00000010 +#define CB_DEBUG_BUS_16__MC_RDREQ_CREDITS_MASK 0x0000003fL +#define CB_DEBUG_BUS_16__MC_RDREQ_CREDITS__SHIFT 0x00000000 +#define CB_DEBUG_BUS_16__MC_WRREQ_CREDITS_MASK 0x0000fc00L +#define CB_DEBUG_BUS_16__MC_WRREQ_CREDITS__SHIFT 0x0000000a +#define CB_DEBUG_BUS_17__BB_BUSY_MASK 0x00000008L +#define CB_DEBUG_BUS_17__BB_BUSY__SHIFT 0x00000003 +#define CB_DEBUG_BUS_17__CC_BUSY_MASK 0x00000004L +#define CB_DEBUG_BUS_17__CC_BUSY__SHIFT 0x00000002 +#define CB_DEBUG_BUS_17__CM_BUSY_MASK 0x00000001L +#define CB_DEBUG_BUS_17__CM_BUSY__SHIFT 0x00000000 +#define CB_DEBUG_BUS_17__CORE_SCLK_VLD_MASK 0x00000020L +#define CB_DEBUG_BUS_17__CORE_SCLK_VLD__SHIFT 0x00000005 +#define CB_DEBUG_BUS_17__FC_BUSY_MASK 0x00000002L +#define CB_DEBUG_BUS_17__FC_BUSY__SHIFT 0x00000001 +#define CB_DEBUG_BUS_17__MA_BUSY_MASK 0x00000010L +#define CB_DEBUG_BUS_17__MA_BUSY__SHIFT 0x00000004 +#define CB_DEBUG_BUS_17__REG_SCLK0_VLD_MASK 0x00000080L +#define CB_DEBUG_BUS_17__REG_SCLK0_VLD__SHIFT 0x00000007 +#define CB_DEBUG_BUS_17__REG_SCLK1_VLD_MASK 0x00000040L +#define CB_DEBUG_BUS_17__REG_SCLK1_VLD__SHIFT 0x00000006 +#define CB_DEBUG_BUS_18__NOT_USED_MASK 0x00ffffffL +#define CB_DEBUG_BUS_18__NOT_USED__SHIFT 0x00000000 +#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x0001f800L +#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0x0000000b +#define CB_HW_CONTROL_1__CHICKEN_BITS_MASK 0xfc000000L +#define CB_HW_CONTROL_1__CHICKEN_BITS__SHIFT 0x0000001a +#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x0000001fL +#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x00000000 +#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x03fe0000L +#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x00000011 +#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x000007e0L +#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x00000005 +#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0x000000ffL +#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x00000000 +#define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xff800000L +#define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x00000017 +#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x007f8000L +#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0x0000000f +#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x00007f00L +#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x00000008 +#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x00000001L +#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x00000000 +#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x00010000L +#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x00000010 +#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK 0x0000f000L +#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT 0x0000000c +#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK 0x0000000fL +#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT 0x00000000 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x02000000L +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x00000019 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x04000000L +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x0000001a +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x01000000L +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x00000018 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x00200000L +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x00000015 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x08000000L +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x0000001b +#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000L +#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x0000001e +#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x00400000L +#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x00000016 +#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x00040000L +#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x00000012 +#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000L +#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x0000001f +#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x00800000L +#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x00000017 +#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK 0x000003c0L +#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT 0x00000006 +#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x00100000L +#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x00000014 +#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x00080000L +#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x00000013 +#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000L +#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x0000001d +#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000L +#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x0000001c +#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000L +#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x0000001c +#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0f000000L +#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x00000018 +#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000001ffL +#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 +#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0007fc00L +#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a +#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0x0000000fL +#define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x00000000 +#define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0x000000f0L +#define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x00000004 +#define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0x00000f00L +#define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x00000008 +#define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0x0000f000L +#define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0x0000000c +#define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0x000f0000L +#define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x00000010 +#define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0x00f00000L +#define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x00000014 +#define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0x0f000000L +#define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x00000018 +#define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xf0000000L +#define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x0000001c +#define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0x0000000fL +#define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x00000000 +#define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0x000000f0L +#define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x00000004 +#define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0x00000f00L +#define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x00000008 +#define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0x0000f000L +#define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0x0000000c +#define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0x000f0000L +#define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x00000010 +#define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0x00f00000L +#define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x00000014 +#define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0x0f000000L +#define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x00000018 +#define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xf0000000L +#define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x0000001c +#define CC_GC_SHADER_ARRAY_CONFIG__DPFP_RATE_MASK 0x00000006L +#define CC_GC_SHADER_ARRAY_CONFIG__DPFP_RATE__SHIFT 0x00000001 +#define CC_GC_SHADER_ARRAY_CONFIG__HALF_LDS_MASK 0x00000010L +#define CC_GC_SHADER_ARRAY_CONFIG__HALF_LDS__SHIFT 0x00000004 +#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xffff0000L +#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x00000010 +#define CC_GC_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L +#define CC_GC_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x00000003 +#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00ff0000L +#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x00000010 +#define CC_RB_DAISY_CHAIN__RB_0_MASK 0x0000000fL +#define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x00000000 +#define CC_RB_DAISY_CHAIN__RB_1_MASK 0x000000f0L +#define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x00000004 +#define CC_RB_DAISY_CHAIN__RB_2_MASK 0x00000f00L +#define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x00000008 +#define CC_RB_DAISY_CHAIN__RB_3_MASK 0x0000f000L +#define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0x0000000c +#define CC_RB_DAISY_CHAIN__RB_4_MASK 0x000f0000L +#define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x00000010 +#define CC_RB_DAISY_CHAIN__RB_5_MASK 0x00f00000L +#define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x00000014 +#define CC_RB_DAISY_CHAIN__RB_6_MASK 0x0f000000L +#define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x00000018 +#define CC_RB_DAISY_CHAIN__RB_7_MASK 0xf0000000L +#define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x0000001c +#define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L +#define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0x0000000c +#define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L +#define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x00000014 +#define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000f00L +#define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x00000008 +#define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0x000f0000L +#define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x00000010 +#define CC_SQC_BANK_DISABLE__SQC0_BANK_DISABLE_MASK 0x000f0000L +#define CC_SQC_BANK_DISABLE__SQC0_BANK_DISABLE__SHIFT 0x00000010 +#define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE_MASK 0x00f00000L +#define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT 0x00000014 +#define CC_SQC_BANK_DISABLE__SQC2_BANK_DISABLE_MASK 0x0f000000L +#define CC_SQC_BANK_DISABLE__SQC2_BANK_DISABLE__SHIFT 0x00000018 +#define CC_SQC_BANK_DISABLE__SQC3_BANK_DISABLE_MASK 0xf0000000L +#define CC_SQC_BANK_DISABLE__SQC3_BANK_DISABLE__SHIFT 0x0000001c +#define CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK 0x00001f00L +#define CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT 0x00000008 +#define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK 0x0000001fL +#define CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT 0x00000000 +#define CGTS_RD_REG__READ_DATA_MASK 0x00003fffL +#define CGTS_RD_REG__READ_DATA__SHIFT 0x00000000 +#define CGTS_SM_CTRL_REG__BASE_MODE_MASK 0x00010000L +#define CGTS_SM_CTRL_REG__BASE_MODE__SHIFT 0x00000010 +#define CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK 0x00400000L +#define CGTS_SM_CTRL_REG__LS_OVERRIDE__SHIFT 0x00000016 +#define CGTS_SM_CTRL_REG__MGCG_ENABLED_MASK 0x00001000L +#define CGTS_SM_CTRL_REG__MGCG_ENABLED__SHIFT 0x0000000c +#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY_MASK 0x00000ff0L +#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT 0x00000004 +#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK 0x00800000L +#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN__SHIFT 0x00000017 +#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK 0xff000000L +#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT 0x00000018 +#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY_MASK 0x0000000fL +#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT 0x00000000 +#define CGTS_SM_CTRL_REG__OVERRIDE_MASK 0x00200000L +#define CGTS_SM_CTRL_REG__OVERRIDE__SHIFT 0x00000015 +#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK 0x00100000L +#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x00000014 +#define CGTS_SM_CTRL_REG__SM_MODE_MASK 0x000e0000L +#define CGTS_SM_CTRL_REG__SM_MODE__SHIFT 0x00000011 +#define CGTS_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000L +#define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT 0x00000010 +#define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000L +#define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT 0x00000010 +#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L +#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x0000001e +#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L +#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x0000001d +#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L +#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x0000001c +#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L +#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x0000001b +#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK 0x04000000L +#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT 0x0000001a +#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK 0x02000000L +#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT 0x00000019 +#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK 0x01000000L +#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT 0x00000018 +#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L +#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 +#define CGTT_BCI_CLK_CTRL__ON_DELAY_MASK 0x0000000fL +#define CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 +#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f +#define CGTT_BCI_CLK_CTRL__RESERVED_MASK 0x00fff000L +#define CGTT_BCI_CLK_CTRL__RESERVED__SHIFT 0x0000000c +#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L +#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 +#define CGTT_CP_CLK_CTRL__ON_DELAY_MASK 0x0000000fL +#define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x0000001e +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x0000001f +#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L +#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 +#define CGTT_GDS_CLK_CTRL__ON_DELAY_MASK 0x0000000fL +#define CGTT_GDS_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 +#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK 0x20000000L +#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x0000001d +#define CGTT_IA_CLK_CTRL__DBG_ENABLE_MASK 0x04000000L +#define CGTT_IA_CLK_CTRL__DBG_ENABLE__SHIFT 0x0000001a +#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L +#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 +#define CGTT_IA_CLK_CTRL__ON_DELAY_MASK 0x0000000fL +#define CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 +#define CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK 0x02000000L +#define CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT 0x00000019 +#define CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +#define CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 +#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x40000000L +#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x0000001e +#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L +#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 +#define CGTT_PA_CLK_CTRL__ON_DELAY_MASK 0x0000000fL +#define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 +#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK 0x80000000L +#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT 0x0000001f +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 +#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x20000000L +#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x0000001d +#define CGTT_PC_CLK_CTRL__BACK_CLK_ON_OVERRIDE_MASK 0x02000000L +#define CGTT_PC_CLK_CTRL__BACK_CLK_ON_OVERRIDE__SHIFT 0x00000019 +#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L +#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x0000001e +#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L +#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x0000001d +#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L +#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x0000001c +#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L +#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x0000001b +#define CGTT_PC_CLK_CTRL__FRONT_CLK_ON_OVERRIDE_MASK 0x04000000L +#define CGTT_PC_CLK_CTRL__FRONT_CLK_ON_OVERRIDE__SHIFT 0x0000001a +#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0x00fc0000L +#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x00000012 +#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x01000000L +#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x00000018 +#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L +#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 +#define CGTT_PC_CLK_CTRL__ON_DELAY_MASK 0x0000000fL +#define CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 +#define CGTT_PC_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +#define CGTT_PC_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f +#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L +#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 +#define CGTT_RLC_CLK_CTRL__ON_DELAY_MASK 0x0000000fL +#define CGTT_RLC_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 +#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L +#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x0000001e +#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L +#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x0000001f +#define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L +#define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 +#define CGTT_SC_CLK_CTRL__ON_DELAY_MASK 0x0000000fL +#define CGTT_SC_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 +#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE_MASK 0x04000000L +#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE__SHIFT 0x0000001a +#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000L +#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x0000001e +#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000L +#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x0000001d +#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000L +#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x0000001c +#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE_MASK 0x08000000L +#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x0000001b +#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0x00fc0000L +#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x00000012 +#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x01000000L +#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x00000018 +#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L +#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 +#define CGTT_SPI_CLK_CTRL__ON_DELAY_MASK 0x0000000fL +#define CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 +#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f +#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L +#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x0000001e +#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L +#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 +#define CGTT_SQ_CLK_CTRL__ON_DELAY_MASK 0x0000000fL +#define CGTT_SQ_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 +#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f +#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L +#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x0000001e +#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L +#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 +#define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK 0x0000000fL +#define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 +#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f +#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000ff0L +#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x00000004 +#define CGTT_SX_CLK_CTRL0__ON_DELAY_MASK 0x0000000fL +#define CGTT_SX_CLK_CTRL0__ON_DELAY__SHIFT 0x00000000 +#define CGTT_SX_CLK_CTRL0__RESERVED_MASK 0x00fff000L +#define CGTT_SX_CLK_CTRL0__RESERVED__SHIFT 0x0000000c +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x0000001f +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x0000001e +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x0000001d +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x0000001c +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x0000001b +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x0000001a +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x00000019 +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x00000018 +#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000ff0L +#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x00000004 +#define CGTT_SX_CLK_CTRL1__ON_DELAY_MASK 0x0000000fL +#define CGTT_SX_CLK_CTRL1__ON_DELAY__SHIFT 0x00000000 +#define CGTT_SX_CLK_CTRL1__RESERVED_MASK 0x00fff000L +#define CGTT_SX_CLK_CTRL1__RESERVED__SHIFT 0x0000000c +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0_MASK 0x80000000L +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0__SHIFT 0x0000001f +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1_MASK 0x40000000L +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT 0x0000001e +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x0000001d +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT 0x0000001c +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT 0x0000001b +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT 0x0000001a +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT 0x00000019 +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE7__SHIFT 0x00000018 +#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS_MASK 0x00000ff0L +#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x00000004 +#define CGTT_SX_CLK_CTRL2__ON_DELAY_MASK 0x0000000fL +#define CGTT_SX_CLK_CTRL2__ON_DELAY__SHIFT 0x00000000 +#define CGTT_SX_CLK_CTRL2__RESERVED_MASK 0x00fff000L +#define CGTT_SX_CLK_CTRL2__RESERVED__SHIFT 0x0000000c +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0_MASK 0x80000000L +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0__SHIFT 0x0000001f +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000L +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x0000001e +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x0000001d +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x0000001c +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x0000001b +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT 0x0000001a +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT 0x00000019 +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE7__SHIFT 0x00000018 +#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS_MASK 0x00000ff0L +#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x00000004 +#define CGTT_SX_CLK_CTRL3__ON_DELAY_MASK 0x0000000fL +#define CGTT_SX_CLK_CTRL3__ON_DELAY__SHIFT 0x00000000 +#define CGTT_SX_CLK_CTRL3__RESERVED_MASK 0x00fff000L +#define CGTT_SX_CLK_CTRL3__RESERVED__SHIFT 0x0000000c +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0_MASK 0x80000000L +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0__SHIFT 0x0000001f +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000L +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x0000001e +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x0000001d +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x0000001c +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x0000001b +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x0000001a +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x00000019 +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE7__SHIFT 0x00000018 +#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS_MASK 0x00000ff0L +#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS__SHIFT 0x00000004 +#define CGTT_SX_CLK_CTRL4__ON_DELAY_MASK 0x0000000fL +#define CGTT_SX_CLK_CTRL4__ON_DELAY__SHIFT 0x00000000 +#define CGTT_SX_CLK_CTRL4__RESERVED_MASK 0x00fff000L +#define CGTT_SX_CLK_CTRL4__RESERVED__SHIFT 0x0000000c +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0_MASK 0x80000000L +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0__SHIFT 0x0000001f +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1_MASK 0x40000000L +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1__SHIFT 0x0000001e +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2__SHIFT 0x0000001d +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3__SHIFT 0x0000001c +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4__SHIFT 0x0000001b +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5__SHIFT 0x0000001a +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6__SHIFT 0x00000019 +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE7__SHIFT 0x00000018 +#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L +#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 +#define CGTT_TCI_CLK_CTRL__ON_DELAY_MASK 0x0000000fL +#define CGTT_TCI_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 +#define CGTT_TCP_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L +#define CGTT_TCP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 +#define CGTT_TCP_CLK_CTRL__ON_DELAY_MASK 0x0000000fL +#define CGTT_TCP_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 +#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L +#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x0000001e +#define CGTT_VGT_CLK_CTRL__DBG_ENABLE_MASK 0x04000000L +#define CGTT_VGT_CLK_CTRL__DBG_ENABLE__SHIFT 0x0000001a +#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE_MASK 0x20000000L +#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE__SHIFT 0x0000001d +#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L +#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 +#define CGTT_VGT_CLK_CTRL__ON_DELAY_MASK 0x0000000fL +#define CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 +#define CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK 0x02000000L +#define CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT 0x00000019 +#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f +#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c +#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b +#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 +#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO_MASK 0x000000ffL +#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty_MASK 0x08000000L +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty__SHIFT 0x0000001b +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full_MASK 0x10000000L +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full__SHIFT 0x0000001c +#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty_MASK 0x00200000L +#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG00__clipcode_fifo_full_MASK 0x00400000L +#define CLIPPER_DEBUG_REG00__clipcode_fifo_full__SHIFT 0x00000016 +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write_MASK 0x00000100L +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full_MASK 0x00001000L +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full__SHIFT 0x0000000c +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write_MASK 0x00000800L +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty_MASK 0x00008000L +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty__SHIFT 0x0000000f +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full_MASK 0x00010000L +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full__SHIFT 0x00000010 +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write_MASK 0x20000000L +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write__SHIFT 0x0000001d +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty_MASK 0x00002000L +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty__SHIFT 0x0000000d +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full_MASK 0x00004000L +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full__SHIFT 0x0000000e +#define CLIPPER_DEBUG_REG00__su_clip_baryc_free_MASK 0x00000600L +#define CLIPPER_DEBUG_REG00__su_clip_baryc_free__SHIFT 0x00000009 +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty_MASK 0x00020000L +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty__SHIFT 0x00000011 +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full_MASK 0x00040000L +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write_MASK 0x80000000L +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write__SHIFT 0x0000001f +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty_MASK 0x00080000L +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full_MASK 0x00100000L +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty_MASK 0x00800000L +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty__SHIFT 0x00000017 +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full_MASK 0x01000000L +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full__SHIFT 0x00000018 +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty_MASK 0x02000000L +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty__SHIFT 0x00000019 +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full_MASK 0x04000000L +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full__SHIFT 0x0000001a +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write_MASK 0x40000000L +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write__SHIFT 0x0000001e +#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO_MASK 0x000000ffL +#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG01__clip_extra_bc_valid_MASK 0x00000700L +#define CLIPPER_DEBUG_REG01__clip_extra_bc_valid__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write_MASK 0x10000000L +#define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write__SHIFT 0x0000001c +#define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write_MASK 0x20000000L +#define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write__SHIFT 0x0000001d +#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot_MASK 0x000e0000L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot__SHIFT 0x00000011 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive_MASK 0x00100000L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate_MASK 0x0001c000L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate__SHIFT 0x0000000e +#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid_MASK 0x00003800L +#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread_MASK 0x40000000L +#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread__SHIFT 0x0000001e +#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty_MASK 0x80000000L +#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty__SHIFT 0x0000001f +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid_MASK 0x01000000L +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid__SHIFT 0x00000018 +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx_MASK 0x0c000000L +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx__SHIFT 0x0000001a +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill_MASK 0x02000000L +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill__SHIFT 0x00000019 +#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0_MASK 0x00800000L +#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0__SHIFT 0x00000017 +#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1_MASK 0x00400000L +#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1__SHIFT 0x00000016 +#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2_MASK 0x00200000L +#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG02__clip_extra_bc_valid_MASK 0x00000007L +#define CLIPPER_DEBUG_REG02__clip_extra_bc_valid__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full_MASK 0x04000000L +#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full__SHIFT 0x0000001a +#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write_MASK 0x10000000L +#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write__SHIFT 0x0000001c +#define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords_MASK 0x00100000L +#define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill_MASK 0x00200000L +#define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full_MASK 0x08000000L +#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full__SHIFT 0x0000001b +#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write_MASK 0x20000000L +#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write__SHIFT 0x0000001d +#define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim_MASK 0x01000000L +#define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim__SHIFT 0x00000018 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx_MASK 0x000000c0L +#define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet_MASK 0x00400000L +#define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet__SHIFT 0x00000016 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread_MASK 0x40000000L +#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread__SHIFT 0x0000001e +#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty_MASK 0x80000000L +#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty__SHIFT 0x0000001f +#define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot_MASK 0x00800000L +#define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot__SHIFT 0x00000017 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive_MASK 0x02000000L +#define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive__SHIFT 0x00000019 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0_MASK 0x000f0000L +#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0__SHIFT 0x00000010 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1_MASK 0x0000f000L +#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1__SHIFT 0x0000000c +#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2_MASK 0x00000f00L +#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG02__clip_vert_vte_valid_MASK 0x00000038L +#define CLIPPER_DEBUG_REG02__clip_vert_vte_valid__SHIFT 0x00000003 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or_MASK 0x00003fffL +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive_MASK 0x00800000L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x00000017 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot_MASK 0x07000000L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot__SHIFT 0x00000018 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet_MASK 0x10000000L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet__SHIFT 0x0000001c +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id_MASK 0x000fc000L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id__SHIFT 0x0000000e +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_MASK 0x20000000L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event__SHIFT 0x0000001d +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x08000000L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT 0x0000001b +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x0000001e +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx_MASK 0x00700000L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event_MASK 0x20000000L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x0000001d +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x0000001e +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0_MASK 0x000007feL +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0__SHIFT 0x00000001 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000017 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x007e0000L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000011 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x0001f800L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or_MASK 0x00003fffL +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive_MASK 0x00800000L +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x00000017 +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot_MASK 0x07000000L +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot__SHIFT 0x00000018 +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet_MASK 0x10000000L +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet__SHIFT 0x0000001c +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id_MASK 0x000fc000L +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id__SHIFT 0x0000000e +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_MASK 0x20000000L +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event__SHIFT 0x0000001d +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot_MASK 0x08000000L +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot__SHIFT 0x0000001b +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000L +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x0000001e +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000L +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x0000001f +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx_MASK 0x00700000L +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event_MASK 0x20000000L +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event__SHIFT 0x0000001d +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000L +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x0000001e +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0_MASK 0x000007feL +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0__SHIFT 0x00000001 +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000L +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x0000001f +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000L +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000017 +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1_MASK 0x007e0000L +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000011 +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2_MASK 0x0001f800L +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or_MASK 0x00003fffL +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive_MASK 0x00800000L +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x00000017 +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot_MASK 0x07000000L +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot__SHIFT 0x00000018 +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet_MASK 0x10000000L +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet__SHIFT 0x0000001c +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id_MASK 0x000fc000L +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id__SHIFT 0x0000000e +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_MASK 0x20000000L +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event__SHIFT 0x0000001d +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot_MASK 0x08000000L +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot__SHIFT 0x0000001b +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000L +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x0000001e +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000L +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x0000001f +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx_MASK 0x00700000L +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event_MASK 0x20000000L +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event__SHIFT 0x0000001d +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000L +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x0000001e +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0_MASK 0x000007feL +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0__SHIFT 0x00000001 +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000L +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x0000001f +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000L +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000017 +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1_MASK 0x007e0000L +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000011 +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2_MASK 0x0001f800L +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or_MASK 0x00003fffL +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive_MASK 0x00800000L +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x00000017 +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot_MASK 0x07000000L +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot__SHIFT 0x00000018 +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet_MASK 0x10000000L +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet__SHIFT 0x0000001c +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id_MASK 0x000fc000L +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id__SHIFT 0x0000000e +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_MASK 0x20000000L +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event__SHIFT 0x0000001d +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot_MASK 0x08000000L +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot__SHIFT 0x0000001b +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000L +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x0000001e +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000L +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x0000001f +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx_MASK 0x00700000L +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event_MASK 0x20000000L +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event__SHIFT 0x0000001d +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000L +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x0000001e +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0_MASK 0x000007feL +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0__SHIFT 0x00000001 +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000L +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x0000001f +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000L +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000017 +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1_MASK 0x007e0000L +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000011 +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2_MASK 0x0001f800L +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive_MASK 0x00000080L +#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00f00000L +#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event_MASK 0x00000008L +#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event__SHIFT 0x00000003 +#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid_MASK 0x08000000L +#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid__SHIFT 0x0000001b +#define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x80000000L +#define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x0000001f +#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive_MASK 0x00000040L +#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt_MASK 0x000f0000L +#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000010 +#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event_MASK 0x00000004L +#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event__SHIFT 0x00000002 +#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid_MASK 0x04000000L +#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid__SHIFT 0x0000001a +#define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x40000000L +#define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x0000001e +#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive_MASK 0x00000020L +#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive__SHIFT 0x00000005 +#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt_MASK 0x0000f000L +#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x0000000c +#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event_MASK 0x00000002L +#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event__SHIFT 0x00000001 +#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid_MASK 0x02000000L +#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid__SHIFT 0x00000019 +#define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x20000000L +#define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x0000001d +#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive_MASK 0x00000010L +#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00000f00L +#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event_MASK 0x00000001L +#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid_MASK 0x01000000L +#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid__SHIFT 0x00000018 +#define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x10000000L +#define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x0000001c +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO_MASK 0x000000ffL +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts_MASK 0x0003e000L +#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts__SHIFT 0x0000000d +#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip_MASK 0x00001f00L +#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load_MASK 0x00c00000L +#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load__SHIFT 0x00000016 +#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out_MASK 0x000c0000L +#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert_MASK 0x00300000L +#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive_MASK 0x40000000L +#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x0000001e +#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000L +#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f +#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive_MASK 0x10000000L +#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x0000001c +#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid_MASK 0x20000000L +#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x0000001d +#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive_MASK 0x04000000L +#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x0000001a +#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid_MASK 0x08000000L +#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x0000001b +#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive_MASK 0x01000000L +#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x00000018 +#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid_MASK 0x02000000L +#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x00000019 +#define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty_MASK 0x00010000L +#define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty__SHIFT 0x00000010 +#define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx_MASK 0x00003000L +#define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx__SHIFT 0x0000000c +#define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty_MASK 0x00008000L +#define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty__SHIFT 0x0000000f +#define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt_MASK 0x001e0000L +#define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt__SHIFT 0x00000011 +#define CLIPPER_DEBUG_REG13__clprim_clip_primitive_MASK 0x00000020L +#define CLIPPER_DEBUG_REG13__clprim_clip_primitive__SHIFT 0x00000005 +#define CLIPPER_DEBUG_REG13__clprim_cull_primitive_MASK 0x00000040L +#define CLIPPER_DEBUG_REG13__clprim_cull_primitive__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx_MASK 0x00000007L +#define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread_MASK 0x40000000L +#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread__SHIFT 0x0000001e +#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents_MASK 0x1f000000L +#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents__SHIFT 0x00000018 +#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full_MASK 0x20000000L +#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full__SHIFT 0x0000001d +#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write_MASK 0x80000000L +#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write__SHIFT 0x0000001f +#define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait_MASK 0x00800000L +#define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait__SHIFT 0x00000017 +#define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices_MASK 0x00600000L +#define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG13__point_clip_candidate_MASK 0x00000008L +#define CLIPPER_DEBUG_REG13__point_clip_candidate__SHIFT 0x00000003 +#define CLIPPER_DEBUG_REG13__prim_back_valid_MASK 0x00000080L +#define CLIPPER_DEBUG_REG13__prim_back_valid__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG13__prim_nan_kill_MASK 0x00000010L +#define CLIPPER_DEBUG_REG13__prim_nan_kill__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid_MASK 0x00000f00L +#define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty_MASK 0x00004000L +#define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty__SHIFT 0x0000000e +#define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot_MASK 0x00e00000L +#define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet_MASK 0x00080000L +#define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG14__clprim_in_back_event_id_MASK 0x3f000000L +#define CLIPPER_DEBUG_REG14__clprim_in_back_event_id__SHIFT 0x00000018 +#define CLIPPER_DEBUG_REG14__clprim_in_back_event_MASK 0x40000000L +#define CLIPPER_DEBUG_REG14__clprim_in_back_event__SHIFT 0x0000001e +#define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot_MASK 0x00100000L +#define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0_MASK 0x0003f000L +#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0__SHIFT 0x0000000c +#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1_MASK 0x00000fc0L +#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2_MASK 0x0000003fL +#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive_MASK 0x00040000L +#define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG14__prim_back_valid_MASK 0x80000000L +#define CLIPPER_DEBUG_REG14__prim_back_valid__SHIFT 0x0000001f +#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x7c000000L +#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT 0x0000001a +#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x03e00000L +#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x001f0000L +#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2__SHIFT 0x00000010 +#define CLIPPER_DEBUG_REG15__primic_to_clprim_valid_MASK 0x80000000L +#define CLIPPER_DEBUG_REG15__primic_to_clprim_valid__SHIFT 0x0000001f +#define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb_MASK 0x0000ffffL +#define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x08000000L +#define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x0000001b +#define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full_MASK 0x10000000L +#define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full__SHIFT 0x0000001c +#define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt_MASK 0x00001f00L +#define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid_MASK 0x80000000L +#define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f +#define CLIPPER_DEBUG_REG16__sm0_current_state_MASK 0x07f00000L +#define CLIPPER_DEBUG_REG16__sm0_current_state__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq_MASK 0x20000000L +#define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq__SHIFT 0x0000001d +#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0_MASK 0x00080000L +#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1_MASK 0x00040000L +#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0_MASK 0x40000000L +#define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0__SHIFT 0x0000001e +#define CLIPPER_DEBUG_REG16__sm0_prim_end_state_MASK 0x0000007fL +#define CLIPPER_DEBUG_REG16__sm0_prim_end_state__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG16__sm0_ps_expand_MASK 0x00000080L +#define CLIPPER_DEBUG_REG16__sm0_ps_expand__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt_MASK 0x0003e000L +#define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt__SHIFT 0x0000000d +#define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x08000000L +#define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x0000001b +#define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full_MASK 0x10000000L +#define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full__SHIFT 0x0000001c +#define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt_MASK 0x00001f00L +#define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid_MASK 0x80000000L +#define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid__SHIFT 0x0000001f +#define CLIPPER_DEBUG_REG17__sm1_current_state_MASK 0x07f00000L +#define CLIPPER_DEBUG_REG17__sm1_current_state__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq_MASK 0x20000000L +#define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq__SHIFT 0x0000001d +#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0_MASK 0x00080000L +#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1_MASK 0x00040000L +#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0_MASK 0x40000000L +#define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0__SHIFT 0x0000001e +#define CLIPPER_DEBUG_REG17__sm1_prim_end_state_MASK 0x0000007fL +#define CLIPPER_DEBUG_REG17__sm1_prim_end_state__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG17__sm1_ps_expand_MASK 0x00000080L +#define CLIPPER_DEBUG_REG17__sm1_ps_expand__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt_MASK 0x0003e000L +#define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt__SHIFT 0x0000000d +#define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x08000000L +#define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x0000001b +#define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full_MASK 0x10000000L +#define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full__SHIFT 0x0000001c +#define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt_MASK 0x00001f00L +#define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid_MASK 0x80000000L +#define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid__SHIFT 0x0000001f +#define CLIPPER_DEBUG_REG18__sm2_current_state_MASK 0x07f00000L +#define CLIPPER_DEBUG_REG18__sm2_current_state__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq_MASK 0x20000000L +#define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq__SHIFT 0x0000001d +#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0_MASK 0x00080000L +#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1_MASK 0x00040000L +#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0_MASK 0x40000000L +#define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0__SHIFT 0x0000001e +#define CLIPPER_DEBUG_REG18__sm2_prim_end_state_MASK 0x0000007fL +#define CLIPPER_DEBUG_REG18__sm2_prim_end_state__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG18__sm2_ps_expand_MASK 0x00000080L +#define CLIPPER_DEBUG_REG18__sm2_ps_expand__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt_MASK 0x0003e000L +#define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt__SHIFT 0x0000000d +#define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x08000000L +#define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x0000001b +#define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full_MASK 0x10000000L +#define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full__SHIFT 0x0000001c +#define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt_MASK 0x00001f00L +#define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid_MASK 0x80000000L +#define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid__SHIFT 0x0000001f +#define CLIPPER_DEBUG_REG19__sm3_current_state_MASK 0x07f00000L +#define CLIPPER_DEBUG_REG19__sm3_current_state__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq_MASK 0x20000000L +#define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq__SHIFT 0x0000001d +#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0_MASK 0x00080000L +#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1_MASK 0x00040000L +#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0_MASK 0x40000000L +#define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0__SHIFT 0x0000001e +#define CLIPPER_DEBUG_REG19__sm3_prim_end_state_MASK 0x0000007fL +#define CLIPPER_DEBUG_REG19__sm3_prim_end_state__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG19__sm3_ps_expand_MASK 0x00000080L +#define CLIPPER_DEBUG_REG19__sm3_ps_expand__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt_MASK 0x0003e000L +#define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt__SHIFT 0x0000000d +#define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xffffffffL +#define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x00000000 +#define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xffffffffL +#define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x00000000 +#define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xffffffffL +#define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x00000000 +#define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xffffffffL +#define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x00000000 +#define COMPUTE_DIM_X__SIZE_MASK 0xffffffffL +#define COMPUTE_DIM_X__SIZE__SHIFT 0x00000000 +#define COMPUTE_DIM_Y__SIZE_MASK 0xffffffffL +#define COMPUTE_DIM_Y__SIZE__SHIFT 0x00000000 +#define COMPUTE_DIM_Z__SIZE_MASK 0xffffffffL +#define COMPUTE_DIM_Z__SIZE__SHIFT 0x00000000 +#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x00000001L +#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x00000000 +#define COMPUTE_DISPATCH_INITIATOR__DATA_ATC_MASK 0x00001000L +#define COMPUTE_DISPATCH_INITIATOR__DATA_ATC__SHIFT 0x0000000c +#define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL_MASK 0x00000380L +#define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL__SHIFT 0x00000007 +#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x00000004L +#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x00000002 +#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x00000008L +#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x00000003 +#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x00000010L +#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x00000004 +#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x00000040L +#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x00000006 +#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x00000002L +#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x00000001 +#define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x00004000L +#define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0x0000000e +#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK 0x00000400L +#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0x0000000a +#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x00000020L +#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x00000005 +#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK 0x00000800L +#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT 0x0000000b +#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0x0000ffffL +#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x00000000 +#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xffff0000L +#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x00000010 +#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0x0000ffffL +#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x00000000 +#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xffff0000L +#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x00000010 +#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0x0000ffffL +#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x00000000 +#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xffff0000L +#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x00000010 +#define COMPUTE_PGM_HI__DATA_MASK 0x000000ffL +#define COMPUTE_PGM_HI__DATA__SHIFT 0x00000000 +#define COMPUTE_PGM_HI__INST_ATC_MASK 0x00000100L +#define COMPUTE_PGM_HI__INST_ATC__SHIFT 0x00000008 +#define COMPUTE_PGM_LO__DATA_MASK 0xffffffffL +#define COMPUTE_PGM_LO__DATA__SHIFT 0x00000000 +#define COMPUTE_PGM_RSRC1__BULKY_MASK 0x01000000L +#define COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x00000018 +#define COMPUTE_PGM_RSRC1__CDBG_USER_MASK 0x02000000L +#define COMPUTE_PGM_RSRC1__CDBG_USER__SHIFT 0x00000019 +#define COMPUTE_PGM_RSRC1__DEBUG_MODE_MASK 0x00400000L +#define COMPUTE_PGM_RSRC1__DEBUG_MODE__SHIFT 0x00000016 +#define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK 0x00200000L +#define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT 0x00000015 +#define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0x000ff000L +#define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0x0000000c +#define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK 0x00800000L +#define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT 0x00000017 +#define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0x00000c00L +#define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0x0000000a +#define COMPUTE_PGM_RSRC1__PRIV_MASK 0x00100000L +#define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x00000014 +#define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x000003c0L +#define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x00000006 +#define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x0000003fL +#define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x00000000 +#define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7f000000L +#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x00006000L +#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0x0000000d +#define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x00000018 +#define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0x00ff8000L +#define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0x0000000f +#define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x00000001L +#define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x00000000 +#define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x00000080L +#define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x00000007 +#define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x00000100L +#define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x00000008 +#define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x00000200L +#define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x00000009 +#define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x00000400L +#define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0x0000000a +#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x00001800L +#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0x0000000b +#define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK 0x00000040L +#define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT 0x00000006 +#define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x0000003eL +#define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x00000001 +#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x07000000L +#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x00000018 +#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x00800000L +#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x00000017 +#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x003f0000L +#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x00000010 +#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x00400000L +#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x00000016 +#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0x0000f000L +#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0x0000000c +#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x0000003fL +#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x00000000 +#define COMPUTE_START_X__START_MASK 0xffffffffL +#define COMPUTE_START_X__START__SHIFT 0x00000000 +#define COMPUTE_START_Y__START_MASK 0xffffffffL +#define COMPUTE_START_Y__START__SHIFT 0x00000000 +#define COMPUTE_START_Z__START_MASK 0xffffffffL +#define COMPUTE_START_Z__START__SHIFT 0x00000000 +#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN_MASK 0x0000ffffL +#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN__SHIFT 0x00000000 +#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN_MASK 0xffff0000L +#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN__SHIFT 0x00000010 +#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN_MASK 0x0000ffffL +#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN__SHIFT 0x00000000 +#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN_MASK 0xffff0000L +#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN__SHIFT 0x00000010 +#define COMPUTE_TBA_HI__DATA_MASK 0x000000ffL +#define COMPUTE_TBA_HI__DATA__SHIFT 0x00000000 +#define COMPUTE_TBA_LO__DATA_MASK 0xffffffffL +#define COMPUTE_TBA_LO__DATA__SHIFT 0x00000000 +#define COMPUTE_TMA_HI__DATA_MASK 0x000000ffL +#define COMPUTE_TMA_HI__DATA__SHIFT 0x00000000 +#define COMPUTE_TMA_LO__DATA_MASK 0xffffffffL +#define COMPUTE_TMA_LO__DATA__SHIFT 0x00000000 +#define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x01fff000L +#define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0x0000000c +#define COMPUTE_TMPRING_SIZE__WAVES_MASK 0x00000fffL +#define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x00000000 +#define COMPUTE_USER_DATA_0__DATA_MASK 0xffffffffL +#define COMPUTE_USER_DATA_0__DATA__SHIFT 0x00000000 +#define COMPUTE_USER_DATA_10__DATA_MASK 0xffffffffL +#define COMPUTE_USER_DATA_10__DATA__SHIFT 0x00000000 +#define COMPUTE_USER_DATA_11__DATA_MASK 0xffffffffL +#define COMPUTE_USER_DATA_11__DATA__SHIFT 0x00000000 +#define COMPUTE_USER_DATA_12__DATA_MASK 0xffffffffL +#define COMPUTE_USER_DATA_12__DATA__SHIFT 0x00000000 +#define COMPUTE_USER_DATA_13__DATA_MASK 0xffffffffL +#define COMPUTE_USER_DATA_13__DATA__SHIFT 0x00000000 +#define COMPUTE_USER_DATA_14__DATA_MASK 0xffffffffL +#define COMPUTE_USER_DATA_14__DATA__SHIFT 0x00000000 +#define COMPUTE_USER_DATA_15__DATA_MASK 0xffffffffL +#define COMPUTE_USER_DATA_15__DATA__SHIFT 0x00000000 +#define COMPUTE_USER_DATA_1__DATA_MASK 0xffffffffL +#define COMPUTE_USER_DATA_1__DATA__SHIFT 0x00000000 +#define COMPUTE_USER_DATA_2__DATA_MASK 0xffffffffL +#define COMPUTE_USER_DATA_2__DATA__SHIFT 0x00000000 +#define COMPUTE_USER_DATA_3__DATA_MASK 0xffffffffL +#define COMPUTE_USER_DATA_3__DATA__SHIFT 0x00000000 +#define COMPUTE_USER_DATA_4__DATA_MASK 0xffffffffL +#define COMPUTE_USER_DATA_4__DATA__SHIFT 0x00000000 +#define COMPUTE_USER_DATA_5__DATA_MASK 0xffffffffL +#define COMPUTE_USER_DATA_5__DATA__SHIFT 0x00000000 +#define COMPUTE_USER_DATA_6__DATA_MASK 0xffffffffL +#define COMPUTE_USER_DATA_6__DATA__SHIFT 0x00000000 +#define COMPUTE_USER_DATA_7__DATA_MASK 0xffffffffL +#define COMPUTE_USER_DATA_7__DATA__SHIFT 0x00000000 +#define COMPUTE_USER_DATA_8__DATA_MASK 0xffffffffL +#define COMPUTE_USER_DATA_8__DATA__SHIFT 0x00000000 +#define COMPUTE_USER_DATA_9__DATA_MASK 0xffffffffL +#define COMPUTE_USER_DATA_9__DATA__SHIFT 0x00000000 +#define COMPUTE_VMID__DATA_MASK 0x0000000fL +#define COMPUTE_VMID__DATA__SHIFT 0x00000000 +#define CP_APPEND_ADDR_HI__COMMAND_MASK 0xe0000000L +#define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x0000001d +#define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x00030000L +#define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x00000010 +#define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0x000000ffL +#define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x00000000 +#define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xfffffffcL +#define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x00000002 +#define CP_APPEND_DATA__DATA_MASK 0xffffffffL +#define CP_APPEND_DATA__DATA__SHIFT 0x00000000 +#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE_MASK 0xffffffffL +#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE__SHIFT 0x00000000 +#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE_MASK 0xffffffffL +#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE__SHIFT 0x00000000 +#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffffL +#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x00000000 +#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffffL +#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x00000000 +#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x00400000L +#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x00000016 +#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x00000040L +#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x00000006 +#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x00040000L +#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x00000012 +#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x00008000L +#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0x0000000f +#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x00020000L +#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x00000011 +#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x00000100L +#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x00000008 +#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x00000080L +#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x00000007 +#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x00100000L +#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x00000014 +#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x00200000L +#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x00000015 +#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x00000400L +#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0x0000000a +#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x00000200L +#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x00000009 +#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L +#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x00000000 +#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x00001000L +#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0x0000000c +#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x00002000L +#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0x0000000d +#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x00004000L +#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0x0000000e +#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x00080000L +#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x00000013 +#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK 0xffffffffL +#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT 0x00000000 +#define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK 0x000000ffL +#define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x00000000 +#define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffcL +#define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x00000002 +#define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000fffffL +#define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x00000000 +#define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK 0x000000ffL +#define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x00000000 +#define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffcL +#define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x00000002 +#define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000fffffL +#define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x00000000 +#define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK 0x000000ffL +#define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT 0x00000000 +#define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK 0xffffffe0L +#define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT 0x00000005 +#define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK 0x00000fffL +#define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT 0x00000000 +#define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x07ff0000L +#define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x00000010 +#define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x000007ffL +#define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x00000000 +#define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x000007ffL +#define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x00000000 +#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x000003ffL +#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x00000000 +#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x03ff0000L +#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x00000010 +#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x000003ffL +#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x00000000 +#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x03ff0000L +#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x00000010 +#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x000003ffL +#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x00000000 +#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x03ff0000L +#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x00000010 +#define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0x00000fffL +#define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x00000000 +#define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xffffffffL +#define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x00000000 +#define CP_CMD_DATA__CMD_DATA_MASK 0xffffffffL +#define CP_CMD_DATA__CMD_DATA__SHIFT 0x00000000 +#define CP_CMD_INDEX__CMD_INDEX_MASK 0x000007ffL +#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x00000000 +#define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x00003000L +#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0x0000000c +#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x00030000L +#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x00000010 +#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0x0ff00000L +#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x00000014 +#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0x000000ffL +#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x00000000 +#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000L +#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x0000001c +#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x00000700L +#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x00000008 +#define CP_COHER_BASE__COHER_BASE_256B_MASK 0xffffffffL +#define CP_COHER_BASE__COHER_BASE_256B__SHIFT 0x00000000 +#define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0x000000ffL +#define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x00000000 +#define CP_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x00000040L +#define CP_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x00000006 +#define CP_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x00000080L +#define CP_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x00000007 +#define CP_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x00000100L +#define CP_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x00000008 +#define CP_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x00000200L +#define CP_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x00000009 +#define CP_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x00000400L +#define CP_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0x0000000a +#define CP_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x00000800L +#define CP_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0x0000000b +#define CP_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x00001000L +#define CP_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0x0000000c +#define CP_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x00002000L +#define CP_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0x0000000d +#define CP_COHER_CNTL__CB_ACTION_ENA_MASK 0x02000000L +#define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT 0x00000019 +#define CP_COHER_CNTL__DB_ACTION_ENA_MASK 0x04000000L +#define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT 0x0000001a +#define CP_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x00004000L +#define CP_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0x0000000e +#define CP_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x00000001L +#define CP_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x00000000 +#define CP_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x00000002L +#define CP_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x00000001 +#define CP_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x00080000L +#define CP_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x00000013 +#define CP_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x00200000L +#define CP_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x00000015 +#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK 0x20000000L +#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x0000001d +#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK 0x08000000L +#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT 0x0000001b +#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK 0x10000000L +#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT 0x0000001c +#define CP_COHER_CNTL__TC_ACTION_ENA_MASK 0x00800000L +#define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT 0x00000017 +#define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK 0x00400000L +#define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT 0x00000016 +#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK 0x00008000L +#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT 0x0000000f +#define CP_COHER_CNTL__TC_VOL_ACTION_ENA_MASK 0x00010000L +#define CP_COHER_CNTL__TC_VOL_ACTION_ENA__SHIFT 0x00000010 +#define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK 0x00040000L +#define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x00000012 +#define CP_COHER_SIZE__COHER_SIZE_256B_MASK 0xffffffffL +#define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x00000000 +#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0x000000ffL +#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x00000000 +#define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK 0x0000003fL +#define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT 0x00000000 +#define CP_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0x000000ffL +#define CP_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x00000000 +#define CP_COHER_STATUS__MEID_MASK 0x03000000L +#define CP_COHER_STATUS__MEID__SHIFT 0x00000018 +#define CP_COHER_STATUS__PHASE1_STATUS_MASK 0x40000000L +#define CP_COHER_STATUS__PHASE1_STATUS__SHIFT 0x0000001e +#define CP_COHER_STATUS__STATUS_MASK 0x80000000L +#define CP_COHER_STATUS__STATUS__SHIFT 0x0000001f +#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH_MASK 0x0000000fL +#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH__SHIFT 0x00000000 +#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x00003f00L +#define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x00000008 +#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED_MASK 0x0000000fL +#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED__SHIFT 0x00000000 +#define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0x000f0000L +#define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x00000010 +#define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x00000030L +#define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x00000004 +#define CP_DMA_CNTL__PIO_COUNT_MASK 0xc0000000L +#define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x0000001e +#define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000L +#define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x0000001c +#define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000L +#define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x0000001d +#define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x001fffffL +#define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x00000000 +#define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000L +#define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x0000001d +#define CP_DMA_ME_COMMAND__DAS_MASK 0x08000000L +#define CP_DMA_ME_COMMAND__DAS__SHIFT 0x0000001b +#define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x00200000L +#define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x00000015 +#define CP_DMA_ME_COMMAND__DST_SWAP_MASK 0x03000000L +#define CP_DMA_ME_COMMAND__DST_SWAP__SHIFT 0x00000018 +#define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000L +#define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x0000001e +#define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000L +#define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x0000001c +#define CP_DMA_ME_COMMAND__SAS_MASK 0x04000000L +#define CP_DMA_ME_COMMAND__SAS__SHIFT 0x0000001a +#define CP_DMA_ME_COMMAND__SRC_SWAP_MASK 0x00c00000L +#define CP_DMA_ME_COMMAND__SRC_SWAP__SHIFT 0x00000016 +#define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xffffffffL +#define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x00000000 +#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0x000000ffL +#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x00000000 +#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x000000ffL +#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x00000000 +#define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xffffffffL +#define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x00000000 +#define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x001fffffL +#define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x00000000 +#define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000L +#define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x0000001d +#define CP_DMA_PFP_COMMAND__DAS_MASK 0x08000000L +#define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x0000001b +#define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x00200000L +#define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x00000015 +#define CP_DMA_PFP_COMMAND__DST_SWAP_MASK 0x03000000L +#define CP_DMA_PFP_COMMAND__DST_SWAP__SHIFT 0x00000018 +#define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000L +#define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x0000001e +#define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000L +#define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x0000001c +#define CP_DMA_PFP_COMMAND__SAS_MASK 0x04000000L +#define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x0000001a +#define CP_DMA_PFP_COMMAND__SRC_SWAP_MASK 0x00c00000L +#define CP_DMA_PFP_COMMAND__SRC_SWAP__SHIFT 0x00000016 +#define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xffffffffL +#define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x00000000 +#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0x000000ffL +#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x00000000 +#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x000000ffL +#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x00000000 +#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xffffffffL +#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x00000000 +#define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x03ffffffL +#define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x00000000 +#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000L +#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x0000001c +#define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x00000003L +#define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x00000000 +#define CP_ECC_FIRSTOCCURRENCE__REQUEST_CLIENT_MASK 0x000000f0L +#define CP_ECC_FIRSTOCCURRENCE__REQUEST_CLIENT__SHIFT 0x00000004 +#define CP_ECC_FIRSTOCCURRENCE_RING0__INTERFACE_MASK 0x00000003L +#define CP_ECC_FIRSTOCCURRENCE_RING0__INTERFACE__SHIFT 0x00000000 +#define CP_ECC_FIRSTOCCURRENCE_RING0__REQUEST_CLIENT_MASK 0x000000f0L +#define CP_ECC_FIRSTOCCURRENCE_RING0__REQUEST_CLIENT__SHIFT 0x00000004 +#define CP_ECC_FIRSTOCCURRENCE_RING0__RING_ID_MASK 0x00003c00L +#define CP_ECC_FIRSTOCCURRENCE_RING0__RING_ID__SHIFT 0x0000000a +#define CP_ECC_FIRSTOCCURRENCE_RING0__VMID_MASK 0x000f0000L +#define CP_ECC_FIRSTOCCURRENCE_RING0__VMID__SHIFT 0x00000010 +#define CP_ECC_FIRSTOCCURRENCE_RING1__INTERFACE_MASK 0x00000003L +#define CP_ECC_FIRSTOCCURRENCE_RING1__INTERFACE__SHIFT 0x00000000 +#define CP_ECC_FIRSTOCCURRENCE_RING1__REQUEST_CLIENT_MASK 0x000000f0L +#define CP_ECC_FIRSTOCCURRENCE_RING1__REQUEST_CLIENT__SHIFT 0x00000004 +#define CP_ECC_FIRSTOCCURRENCE_RING1__RING_ID_MASK 0x00003c00L +#define CP_ECC_FIRSTOCCURRENCE_RING1__RING_ID__SHIFT 0x0000000a +#define CP_ECC_FIRSTOCCURRENCE_RING1__VMID_MASK 0x000f0000L +#define CP_ECC_FIRSTOCCURRENCE_RING1__VMID__SHIFT 0x00000010 +#define CP_ECC_FIRSTOCCURRENCE_RING2__INTERFACE_MASK 0x00000003L +#define CP_ECC_FIRSTOCCURRENCE_RING2__INTERFACE__SHIFT 0x00000000 +#define CP_ECC_FIRSTOCCURRENCE_RING2__REQUEST_CLIENT_MASK 0x000000f0L +#define CP_ECC_FIRSTOCCURRENCE_RING2__REQUEST_CLIENT__SHIFT 0x00000004 +#define CP_ECC_FIRSTOCCURRENCE_RING2__RING_ID_MASK 0x00003c00L +#define CP_ECC_FIRSTOCCURRENCE_RING2__RING_ID__SHIFT 0x0000000a +#define CP_ECC_FIRSTOCCURRENCE_RING2__VMID_MASK 0x000f0000L +#define CP_ECC_FIRSTOCCURRENCE_RING2__VMID__SHIFT 0x00000010 +#define CP_ECC_FIRSTOCCURRENCE__RING_ID_MASK 0x00003c00L +#define CP_ECC_FIRSTOCCURRENCE__RING_ID__SHIFT 0x0000000a +#define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0x000f0000L +#define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x00000010 +#define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0x0000ffffL +#define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x00000000 +#define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xfffffffcL +#define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x00000002 +#define CP_EOP_DONE_ADDR_LO__ADDR_SWAP_MASK 0x00000003L +#define CP_EOP_DONE_ADDR_LO__ADDR_SWAP__SHIFT 0x00000000 +#define CP_EOP_DONE_DATA_CNTL__CNTX_ID_MASK 0x0000ffffL +#define CP_EOP_DONE_DATA_CNTL__CNTX_ID__SHIFT 0x00000000 +#define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xe0000000L +#define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x0000001d +#define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x00030000L +#define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x00000010 +#define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x07000000L +#define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x00000018 +#define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xffffffffL +#define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x00000000 +#define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xffffffffL +#define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x00000000 +#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xffffffffL +#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x00000000 +#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xffffffffL +#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x00000000 +#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffffL +#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x00000000 +#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffffL +#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x00000000 +#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffffL +#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x00000000 +#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffffL +#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x00000000 +#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x00003f00L +#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x00000008 +#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003fL +#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x003f0000L +#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x00000010 +#define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x00000000 +#define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0x000000ffL +#define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x00000000 +#define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffcL +#define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x00000002 +#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000fffffL +#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x00000000 +#define CP_IB1_OFFSET__IB1_OFFSET_MASK 0x000fffffL +#define CP_IB1_OFFSET__IB1_OFFSET__SHIFT 0x00000000 +#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK 0x000fffffL +#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT 0x00000000 +#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK 0x000fffffL +#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT 0x00000000 +#define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0x000000ffL +#define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x00000000 +#define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffcL +#define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x00000002 +#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000fffffL +#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x00000000 +#define CP_IB2_OFFSET__IB2_OFFSET_MASK 0x000fffffL +#define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x00000000 +#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0x000fffffL +#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x00000000 +#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0x000fffffL +#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x00000000 +#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L +#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x00000013 +#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L +#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x00000014 +#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0x0000000e +#define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +#define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x0000001f +#define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x0000001e +#define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x0000001d +#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x00000018 +#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L +#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x00000016 +#define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x00000017 +#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x0000001b +#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L +#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x00000013 +#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L +#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x00000014 +#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0x0000000e +#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000L +#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x0000001f +#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x0000001e +#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x0000001d +#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x00000018 +#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L +#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x00000016 +#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x00000017 +#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x0000001b +#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x0000001a +#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x00000011 +#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L +#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x00000013 +#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L +#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x00000014 +#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0x0000000e +#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000L +#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x0000001f +#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x0000001e +#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x0000001d +#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x00000018 +#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L +#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x00000016 +#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x00000017 +#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x0000001b +#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x0000001a +#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x00000011 +#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L +#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x00000013 +#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L +#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x00000014 +#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0x0000000e +#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK 0x80000000L +#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT 0x0000001f +#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT 0x0000001e +#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x0000001d +#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x00000018 +#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L +#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x00000016 +#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x00000017 +#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x0000001b +#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x0000001a +#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x00000011 +#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x0000001a +#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x00000011 +#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED_MASK 0x00080000L +#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED__SHIFT 0x00000013 +#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED_MASK 0x00100000L +#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED__SHIFT 0x00000014 +#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x00004000L +#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0x0000000e +#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000L +#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x0000001f +#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000L +#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x0000001e +#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000L +#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x0000001d +#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x01000000L +#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x00000018 +#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x00400000L +#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x00000016 +#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L +#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x00000017 +#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x08000000L +#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x0000001b +#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x04000000L +#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x0000001a +#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x00020000L +#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x00000011 +#define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x00080000L +#define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x00000013 +#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x00100000L +#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x00000014 +#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L +#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0x0000000e +#define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000L +#define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x0000001f +#define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000L +#define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x0000001e +#define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000L +#define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x0000001d +#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x01000000L +#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x00000018 +#define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x00400000L +#define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x00000016 +#define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x00800000L +#define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x00000017 +#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L +#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x0000001b +#define CP_INT_STATUS_RING0__CNTX_BUSY_INT_STAT_MASK 0x00080000L +#define CP_INT_STATUS_RING0__CNTX_BUSY_INT_STAT__SHIFT 0x00000013 +#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x00100000L +#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x00000014 +#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L +#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0x0000000e +#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000L +#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x0000001f +#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000L +#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x0000001e +#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000L +#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x0000001d +#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x01000000L +#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x00000018 +#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x00400000L +#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x00000016 +#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x00800000L +#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x00000017 +#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L +#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x0000001b +#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x04000000L +#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x0000001a +#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L +#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x00000011 +#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x00080000L +#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x00000013 +#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x00100000L +#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x00000014 +#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L +#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0x0000000e +#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000L +#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x0000001f +#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000L +#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x0000001e +#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000L +#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x0000001d +#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x01000000L +#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x00000018 +#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x00400000L +#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x00000016 +#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x00800000L +#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x00000017 +#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L +#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x0000001b +#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x04000000L +#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x0000001a +#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L +#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x00000011 +#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x00080000L +#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x00000013 +#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x00100000L +#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x00000014 +#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L +#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0x0000000e +#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK 0x80000000L +#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT 0x0000001f +#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000L +#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT 0x0000001e +#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK 0x20000000L +#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x0000001d +#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x01000000L +#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x00000018 +#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x00400000L +#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x00000016 +#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x00800000L +#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x00000017 +#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L +#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x0000001b +#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x04000000L +#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x0000001a +#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L +#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x00000011 +#define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x04000000L +#define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x0000001a +#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L +#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x00000011 +#define CP_MC_PACK_DELAY_CNT__PACK_DELAY_CNT_MASK 0x0000001fL +#define CP_MC_PACK_DELAY_CNT__PACK_DELAY_CNT__SHIFT 0x00000000 +#define CP_ME_CNTL__CE_HALT_MASK 0x01000000L +#define CP_ME_CNTL__CE_HALT__SHIFT 0x00000018 +#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x00000010L +#define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x00000004 +#define CP_ME_CNTL__CE_STEP_MASK 0x02000000L +#define CP_ME_CNTL__CE_STEP__SHIFT 0x00000019 +#define CP_ME_CNTL__ME_HALT_MASK 0x10000000L +#define CP_ME_CNTL__ME_HALT__SHIFT 0x0000001c +#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x00000100L +#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x00000008 +#define CP_ME_CNTL__ME_STEP_MASK 0x20000000L +#define CP_ME_CNTL__ME_STEP__SHIFT 0x0000001d +#define CP_ME_CNTL__PFP_HALT_MASK 0x04000000L +#define CP_ME_CNTL__PFP_HALT__SHIFT 0x0000001a +#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x00000040L +#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x00000006 +#define CP_ME_CNTL__PFP_STEP_MASK 0x08000000L +#define CP_ME_CNTL__PFP_STEP__SHIFT 0x0000001b +#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xffffffffL +#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x00000000 +#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0x000000ffL +#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x00000000 +#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xfffffffcL +#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x00000002 +#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP_MASK 0x00000003L +#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP__SHIFT 0x00000000 +#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0x000000ffL +#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x00000000 +#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xfffffffcL +#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x00000002 +#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP_MASK 0x00000003L +#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP__SHIFT 0x00000000 +#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xffffffffL +#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x00000000 +#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xffffffffL +#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x00000000 +#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x00000002L +#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x00000001 +#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x00000001L +#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x00000000 +#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0x00ff0000L +#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x00000010 +#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0x0000ff00L +#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x00000008 +#define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000L +#define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x00000018 +#define CP_MEM_SLP_CNTL__RESERVED_MASK 0x000000fcL +#define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x00000002 +#define CP_ME_PREEMPTION__ME_CNTXSW_PREEMPTION_MASK 0x00000001L +#define CP_ME_PREEMPTION__ME_CNTXSW_PREEMPTION__SHIFT 0x00000000 +#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x000003ffL +#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x00000000 +#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x000003ffL +#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x00000000 +#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x03ff0000L +#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x00000010 +#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0x000000ffL +#define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x00000000 +#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0x0000ff00L +#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x00000008 +#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xffffffffL +#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x00000000 +#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x00000fffL +#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x00000000 +#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x00000fffL +#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x00000000 +#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK 0xffffffffL +#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT 0x00000000 +#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK 0xffffffffL +#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT 0x00000000 +#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK 0xffffffffL +#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT 0x00000000 +#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK 0xffffffffL +#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT 0x00000000 +#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK 0xffffffffL +#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT 0x00000000 +#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK 0xffffffffL +#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT 0x00000000 +#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK 0xffffffffL +#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT 0x00000000 +#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK 0xffffffffL +#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT 0x00000000 +#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK 0xffffffffL +#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT 0x00000000 +#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xffffffffL +#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT 0x00000000 +#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK 0xffffffffL +#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT 0x00000000 +#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK 0xffffffffL +#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT 0x00000000 +#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK 0xffffffffL +#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT 0x00000000 +#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK 0xffffffffL +#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT 0x00000000 +#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK 0xffffffffL +#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT 0x00000000 +#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK 0xffffffffL +#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT 0x00000000 +#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xffffffffL +#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x00000000 +#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xffffffffL +#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x00000000 +#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xffffffffL +#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x00000000 +#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xffffffffL +#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x00000000 +#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L +#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x00000008 +#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L +#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0x0000000a +#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000fL +#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x00000000 +#define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0x000000f0L +#define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x00000004 +#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000L +#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x0000001f +#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xffffffffL +#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x00000000 +#define CP_PFP_IB_CONTROL__IB_EN_MASK 0x00000001L +#define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x00000000 +#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x00000002L +#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x00000001 +#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x00000001L +#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x00000000 +#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x01000000L +#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x00000018 +#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x00010000L +#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x00000010 +#define CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN_MASK 0x00008000L +#define CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN__SHIFT 0x0000000f +#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x00000fffL +#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x00000000 +#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xffffffffL +#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x00000000 +#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0xffffffffL +#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x00000000 +#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xfffffffcL +#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x00000002 +#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_SWAP_MASK 0x00000003L +#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_SWAP__SHIFT 0x00000000 +#define CP_PWR_CNTL__GFX_CLK_HALT_MASK 0x00000001L +#define CP_PWR_CNTL__GFX_CLK_HALT__SHIFT 0x00000000 +#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x0000003fL +#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x00000000 +#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x00003f00L +#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x00000008 +#define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0x000000ffL +#define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x00000000 +#define CP_RB0_BASE__RB_BASE_MASK 0xffffffffL +#define CP_RB0_BASE__RB_BASE__SHIFT 0x00000000 +#define CP_RB0_CNTL__BUF_SWAP_MASK 0x00030000L +#define CP_RB0_CNTL__BUF_SWAP__SHIFT 0x00000010 +#define CP_RB0_CNTL__CACHE_POLICY_MASK 0x03000000L +#define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x00000018 +#define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x00300000L +#define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x00000014 +#define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0x00c00000L +#define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x00000016 +#define CP_RB0_CNTL__RB_BLKSZ_MASK 0x00003f00L +#define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x00000008 +#define CP_RB0_CNTL__RB_BUFSZ_MASK 0x0000003fL +#define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x00000000 +#define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x08000000L +#define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x0000001b +#define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L +#define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x0000001f +#define CP_RB0_CNTL__RB_VOLATILE_MASK 0x04000000L +#define CP_RB0_CNTL__RB_VOLATILE__SHIFT 0x0000001a +#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x000000ffL +#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x00000000 +#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffcL +#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000002 +#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x00000003L +#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x00000000 +#define CP_RB0_RPTR__RB_RPTR_MASK 0x000fffffL +#define CP_RB0_RPTR__RB_RPTR__SHIFT 0x00000000 +#define CP_RB0_WPTR__RB_WPTR_MASK 0x000fffffL +#define CP_RB0_WPTR__RB_WPTR__SHIFT 0x00000000 +#define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0x000000ffL +#define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x00000000 +#define CP_RB1_BASE__RB_BASE_MASK 0xffffffffL +#define CP_RB1_BASE__RB_BASE__SHIFT 0x00000000 +#define CP_RB1_CNTL__CACHE_POLICY_MASK 0x03000000L +#define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x00000018 +#define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x00300000L +#define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x00000014 +#define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0x00c00000L +#define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x00000016 +#define CP_RB1_CNTL__RB_BLKSZ_MASK 0x00003f00L +#define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x00000008 +#define CP_RB1_CNTL__RB_BUFSZ_MASK 0x0000003fL +#define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x00000000 +#define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x08000000L +#define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x0000001b +#define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L +#define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x0000001f +#define CP_RB1_CNTL__RB_VOLATILE_MASK 0x04000000L +#define CP_RB1_CNTL__RB_VOLATILE__SHIFT 0x0000001a +#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x000000ffL +#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x00000000 +#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffcL +#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000002 +#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x00000003L +#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x00000000 +#define CP_RB1_RPTR__RB_RPTR_MASK 0x000fffffL +#define CP_RB1_RPTR__RB_RPTR__SHIFT 0x00000000 +#define CP_RB1_WPTR__RB_WPTR_MASK 0x000fffffL +#define CP_RB1_WPTR__RB_WPTR__SHIFT 0x00000000 +#define CP_RB2_BASE__RB_BASE_MASK 0xffffffffL +#define CP_RB2_BASE__RB_BASE__SHIFT 0x00000000 +#define CP_RB2_CNTL__CACHE_POLICY_MASK 0x03000000L +#define CP_RB2_CNTL__CACHE_POLICY__SHIFT 0x00000018 +#define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x00300000L +#define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x00000014 +#define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0x00c00000L +#define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x00000016 +#define CP_RB2_CNTL__RB_BLKSZ_MASK 0x00003f00L +#define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x00000008 +#define CP_RB2_CNTL__RB_BUFSZ_MASK 0x0000003fL +#define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x00000000 +#define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x08000000L +#define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x0000001b +#define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L +#define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x0000001f +#define CP_RB2_CNTL__RB_VOLATILE_MASK 0x04000000L +#define CP_RB2_CNTL__RB_VOLATILE__SHIFT 0x0000001a +#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x000000ffL +#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x00000000 +#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffcL +#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000002 +#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x00000003L +#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x00000000 +#define CP_RB2_RPTR__RB_RPTR_MASK 0x000fffffL +#define CP_RB2_RPTR__RB_RPTR__SHIFT 0x00000000 +#define CP_RB2_WPTR__RB_WPTR_MASK 0x000fffffL +#define CP_RB2_WPTR__RB_WPTR__SHIFT 0x00000000 +#define CP_RB_BASE__RB_BASE_MASK 0xffffffffL +#define CP_RB_BASE__RB_BASE__SHIFT 0x00000000 +#define CP_RB_CNTL__BUF_SWAP_MASK 0x00030000L +#define CP_RB_CNTL__BUF_SWAP__SHIFT 0x00000010 +#define CP_RB_CNTL__CACHE_POLICY_MASK 0x03000000L +#define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x00000018 +#define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x00300000L +#define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x00000014 +#define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0x00c00000L +#define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x00000016 +#define CP_RB_CNTL__RB_BLKSZ_MASK 0x00003f00L +#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x00000008 +#define CP_RB_CNTL__RB_BUFSZ_MASK 0x0000003fL +#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x00000000 +#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x08000000L +#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x0000001b +#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L +#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x0000001f +#define CP_RB_CNTL__RB_VOLATILE_MASK 0x04000000L +#define CP_RB_CNTL__RB_VOLATILE__SHIFT 0x0000001a +#define CP_RB_OFFSET__RB_OFFSET_MASK 0x000fffffL +#define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x00000000 +#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x000000ffL +#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x00000000 +#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffcL +#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000002 +#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x00000003L +#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x00000000 +#define CP_RB_RPTR__RB_RPTR_MASK 0x000fffffL +#define CP_RB_RPTR__RB_RPTR__SHIFT 0x00000000 +#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0x000fffffL +#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x00000000 +#define CP_RB_VMID__RB0_VMID_MASK 0x0000000fL +#define CP_RB_VMID__RB0_VMID__SHIFT 0x00000000 +#define CP_RB_VMID__RB1_VMID_MASK 0x00000f00L +#define CP_RB_VMID__RB1_VMID__SHIFT 0x00000008 +#define CP_RB_VMID__RB2_VMID_MASK 0x000f0000L +#define CP_RB_VMID__RB2_VMID__SHIFT 0x00000010 +#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xf0000000L +#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x0000001c +#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0x0fffffffL +#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x00000000 +#define CP_RB_WPTR_POLL_ADDR_HI__OBSOLETE_MASK 0x000000ffL +#define CP_RB_WPTR_POLL_ADDR_HI__OBSOLETE__SHIFT 0x00000000 +#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK 0x000000ffL +#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT 0x00000000 +#define CP_RB_WPTR_POLL_ADDR_LO__OBSOLETE_MASK 0xfffffffcL +#define CP_RB_WPTR_POLL_ADDR_LO__OBSOLETE__SHIFT 0x00000002 +#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK 0xfffffffcL +#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT 0x00000002 +#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000L +#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x00000010 +#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0x0000ffffL +#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x00000000 +#define CP_RB_WPTR__RB_WPTR_MASK 0x000fffffL +#define CP_RB_WPTR__RB_WPTR__SHIFT 0x00000000 +#define CP_RING0_PRIORITY__PRIORITY_MASK 0x00000003L +#define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x00000000 +#define CP_RING1_PRIORITY__PRIORITY_MASK 0x00000003L +#define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x00000000 +#define CP_RING2_PRIORITY__PRIORITY_MASK 0x00000003L +#define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x00000000 +#define CP_RINGID__RINGID_MASK 0x00000003L +#define CP_RINGID__RINGID__SHIFT 0x00000000 +#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000ffL +#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x00000000 +#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000ff00L +#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x00000008 +#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00ff0000L +#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x00000010 +#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000L +#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x00000018 +#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0x00ff0000L +#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x00000010 +#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0xff000000L +#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x00000018 +#define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0x000000ffL +#define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x00000000 +#define CP_ROQ1_THRESHOLDS__RB2_START_MASK 0x0000ff00L +#define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x00000008 +#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x000007ffL +#define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x00000000 +#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0x0000ff00L +#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x00000008 +#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0x00ff0000L +#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0x00000010 +#define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK 0x000000ffL +#define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT 0x00000000 +#define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK 0xff000000L +#define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT 0x00000018 +#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x07ff0000L +#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x00000010 +#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x000007ffL +#define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x00000000 +#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x000003ffL +#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x00000000 +#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x03ff0000L +#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x00000010 +#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x000003ffL +#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x00000000 +#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x03ff0000L +#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x00000010 +#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x000003ffL +#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x00000000 +#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x03ff0000L +#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x00000010 +#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xffffffffL +#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x00000000 +#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xffffffffL +#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x00000000 +#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xffffffffL +#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x00000000 +#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xffffffffL +#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x00000000 +#define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffffL +#define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x00000000 +#define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000000ffL +#define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x00000000 +#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xffffffffL +#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x00000000 +#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x000000ffL +#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x00000000 +#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L +#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x00000018 +#define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000L +#define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x0000001d +#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L +#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x00000014 +#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L +#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x00000010 +#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8L +#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x00000003 +#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x00000003L +#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x00000000 +#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x00000400L +#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0x0000000a +#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x00000800L +#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0x0000000b +#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00002000L +#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x0000000d +#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x00001000L +#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x0000000c +#define CP_STALLED_STAT1__ME_WAITING_ON_MC_READ_DATA_MASK 0x00004000L +#define CP_STALLED_STAT1__ME_WAITING_ON_MC_READ_DATA__SHIFT 0x0000000e +#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x00008000L +#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0x0000000f +#define CP_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE_MASK 0x00010000L +#define CP_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE__SHIFT 0x00000010 +#define CP_STALLED_STAT1__MIU_WAITING_ON_WRREQ_FREE_MASK 0x00020000L +#define CP_STALLED_STAT1__MIU_WAITING_ON_WRREQ_FREE__SHIFT 0x00000011 +#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x00000001L +#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x00000000 +#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x00000010L +#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x00000004 +#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x00000004L +#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x00000002 +#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x10000000L +#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x0000001c +#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000L +#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x0000001c +#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x08000000L +#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x0000001b +#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x04000000L +#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x0000001a +#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x00800000L +#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x00000017 +#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x01000000L +#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x00000018 +#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x02000000L +#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x00000019 +#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000L +#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x0000001c +#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x02000000L +#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x00000019 +#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x04000000L +#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x0000001a +#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000L +#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x0000001d +#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x08000000L +#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x0000001b +#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x00200000L +#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x00000015 +#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x00400000L +#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x00000016 +#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x00000800L +#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0x0000000b +#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00010000L +#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x00000010 +#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x00001000L +#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0x0000000c +#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x00002000L +#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0x0000000d +#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x00004000L +#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0x0000000e +#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x00040000L +#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x00000012 +#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x00008000L +#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0x0000000f +#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x00000400L +#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0x0000000a +#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x00000200L +#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x00000009 +#define CP_STALLED_STAT2__PFP_MIU_READ_PENDING_MASK 0x00000040L +#define CP_STALLED_STAT2__PFP_MIU_READ_PENDING__SHIFT 0x00000006 +#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x00000020L +#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x00000005 +#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00100000L +#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x00000014 +#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x00080000L +#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x00000013 +#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L +#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x00000000 +#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x00000002L +#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x00000001 +#define CP_STALLED_STAT2__PFP_TO_MIU_WRITE_NOT_RDY_TO_RCV_MASK 0x00000080L +#define CP_STALLED_STAT2__PFP_TO_MIU_WRITE_NOT_RDY_TO_RCV__SHIFT 0x00000007 +#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x00000004L +#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x00000002 +#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x00000010L +#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x00000004 +#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x00000100L +#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x00000008 +#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x01000000L +#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x00000018 +#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00020000L +#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x00000011 +#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x00800000L +#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x00000017 +#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000L +#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x0000001f +#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000L +#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x0000001e +#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L +#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x00000000 +#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x00000040L +#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x00000006 +#define CP_STALLED_STAT3__CE_TO_MIU_WRITE_NOT_RDY_TO_RCV_MASK 0x00000100L +#define CP_STALLED_STAT3__CE_TO_MIU_WRITE_NOT_RDY_TO_RCV__SHIFT 0x00000008 +#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x00000010L +#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x00000004 +#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x00000002L +#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x00000001 +#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x00000008L +#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x00000003 +#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x00000020L +#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x00000005 +#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x00000080L +#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x00000007 +#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x00000400L +#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0x0000000a +#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x00000800L +#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0x0000000b +#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x00000004L +#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x00000002 +#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x00001000L +#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0x0000000c +#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x00002000L +#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0x0000000d +#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x00004000L +#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0x0000000e +#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x00008000L +#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0x0000000f +#define CP_STAT__CE_BUSY_MASK 0x04000000L +#define CP_STAT__CE_BUSY__SHIFT 0x0000001a +#define CP_STAT__CP_BUSY_MASK 0x80000000L +#define CP_STAT__CP_BUSY__SHIFT 0x0000001f +#define CP_STAT__CPC_CPG_BUSY_MASK 0x02000000L +#define CP_STAT__CPC_CPG_BUSY__SHIFT 0x00000019 +#define CP_STAT__DC_BUSY_MASK 0x00002000L +#define CP_STAT__DC_BUSY__SHIFT 0x0000000d +#define CP_STAT__DMA_BUSY_MASK 0x00400000L +#define CP_STAT__DMA_BUSY__SHIFT 0x00000016 +#define CP_STAT__INTERRUPT_BUSY_MASK 0x00100000L +#define CP_STAT__INTERRUPT_BUSY__SHIFT 0x00000014 +#define CP_STAT__ME_BUSY_MASK 0x00020000L +#define CP_STAT__ME_BUSY__SHIFT 0x00000011 +#define CP_STAT__MEQ_BUSY_MASK 0x00010000L +#define CP_STAT__MEQ_BUSY__SHIFT 0x00000010 +#define CP_STAT__MIU_RDREQ_BUSY_MASK 0x00000080L +#define CP_STAT__MIU_RDREQ_BUSY__SHIFT 0x00000007 +#define CP_STAT__MIU_WRREQ_BUSY_MASK 0x00000100L +#define CP_STAT__MIU_WRREQ_BUSY__SHIFT 0x00000008 +#define CP_STAT__PFP_BUSY_MASK 0x00008000L +#define CP_STAT__PFP_BUSY__SHIFT 0x0000000f +#define CP_STAT__QUERY_BUSY_MASK 0x00040000L +#define CP_STAT__QUERY_BUSY__SHIFT 0x00000012 +#define CP_STAT__RCIU_BUSY_MASK 0x00800000L +#define CP_STAT__RCIU_BUSY__SHIFT 0x00000017 +#define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000L +#define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x0000001d +#define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000L +#define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x0000001e +#define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000L +#define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x0000001c +#define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x00000400L +#define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0x0000000a +#define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x00000800L +#define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0x0000000b +#define CP_STAT__ROQ_RING_BUSY_MASK 0x00000200L +#define CP_STAT__ROQ_RING_BUSY__SHIFT 0x00000009 +#define CP_STAT__ROQ_STATE_BUSY_MASK 0x00001000L +#define CP_STAT__ROQ_STATE_BUSY__SHIFT 0x0000000c +#define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x01000000L +#define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x00000018 +#define CP_STAT__SEMAPHORE_BUSY_MASK 0x00080000L +#define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x00000013 +#define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x00200000L +#define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x00000015 +#define CP_STAT__TCIU_BUSY_MASK 0x08000000L +#define CP_STAT__TCIU_BUSY__SHIFT 0x0000001b +#define CP_ST_BASE_HI__ST_BASE_HI_MASK 0x000000ffL +#define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x00000000 +#define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xfffffffcL +#define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x00000002 +#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0x000fffffL +#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x00000000 +#define CP_STQ_AVAIL__STQ_CNT_MASK 0x000001ffL +#define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x00000000 +#define CP_STQ_STAT__STQ_RPTR_MASK 0x000003ffL +#define CP_STQ_STAT__STQ_RPTR__SHIFT 0x00000000 +#define CP_STQ_THRESHOLDS__STQ0_START_MASK 0x000000ffL +#define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x00000000 +#define CP_STQ_THRESHOLDS__STQ1_START_MASK 0x0000ff00L +#define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x00000008 +#define CP_STQ_THRESHOLDS__STQ2_START_MASK 0x00ff0000L +#define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x00000010 +#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK 0xffffffffL +#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT 0x00000000 +#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK 0xfffffffcL +#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT 0x00000002 +#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_SWAP_MASK 0x00000003L +#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_SWAP__SHIFT 0x00000000 +#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK 0x00000001L +#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT 0x00000000 +#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xffffffffL +#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x00000000 +#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xffffffffL +#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x00000000 +#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xffffffffL +#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x00000000 +#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xffffffffL +#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x00000000 +#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xffffffffL +#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x00000000 +#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xffffffffL +#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x00000000 +#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xffffffffL +#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x00000000 +#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xffffffffL +#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x00000000 +#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xffffffffL +#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x00000000 +#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xffffffffL +#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x00000000 +#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xffffffffL +#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x00000000 +#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xffffffffL +#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x00000000 +#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xffffffffL +#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x00000000 +#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xffffffffL +#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x00000000 +#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xffffffffL +#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x00000000 +#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xffffffffL +#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x00000000 +#define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0x0000ffffL +#define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x00000000 +#define CP_VMID_PREEMPT__PREEMPT_STATUS_MASK 0xffff0000L +#define CP_VMID_PREEMPT__PREEMPT_STATUS__SHIFT 0x00000010 +#define CP_VMID_RESET__RESET_REQUEST_MASK 0x0000ffffL +#define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x00000000 +#define CP_VMID_RESET__RESET_STATUS_MASK 0xffff0000L +#define CP_VMID_RESET__RESET_STATUS__SHIFT 0x00000010 +#define CP_VMID__VMID_MASK 0x0000000fL +#define CP_VMID__VMID__SHIFT 0x00000000 +#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xffffffffL +#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x00000000 +#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x000000ffL +#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x00000000 +#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L +#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x00000018 +#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000L +#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x0000001d +#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L +#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x00000014 +#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L +#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x00000010 +#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8L +#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x00000003 +#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x00000003L +#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x00000000 +#define CS_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L +#define CS_COPY_STATE__SRC_STATE_ID__SHIFT 0x00000000 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x00000001L +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x00000000 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x00000300L +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x00000008 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0x00000c00L +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0x0000000a +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x00003000L +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0x0000000c +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0x0000c000L +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0x0000000e +#define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x00010000L +#define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x00000010 +#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK 0x00000ff0L +#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT 0x00000004 +#define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK 0x0000000fL +#define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT 0x00000000 +#define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0x00fff000L +#define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0x0000000c +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x80000000L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x0000001f +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x40000000L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x0000001e +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x20000000L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x0000001d +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x10000000L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x0000001c +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x08000000L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x0000001b +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x04000000L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x0000001a +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x02000000L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x00000019 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK 0x01000000L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT 0x00000018 +#define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0x00f00000L +#define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x00000014 +#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x00000002L +#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x00000001 +#define DB_COUNT_CONTROL__SAMPLE_RATE_MASK 0x00000070L +#define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT 0x00000004 +#define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0x000f0000L +#define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x00000010 +#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x0f000000L +#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x00000018 +#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xf0000000L +#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x0000001c +#define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0x0000f000L +#define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0x0000000c +#define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0x00000f00L +#define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x00000008 +#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK 0x00000001L +#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT 0x00000000 +#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x00001c00L +#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0x0000000a +#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK 0x7f000000L +#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT 0x00000018 +#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x000003e0L +#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x00000005 +#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x0000001fL +#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x00000000 +#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x00000001L +#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x00000000 +#define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x00003e00L +#define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x00000009 +#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x00040000L +#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x00000012 +#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES_MASK 0x00010000L +#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES__SHIFT 0x00000010 +#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x00020000L +#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x00000011 +#define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ_MASK 0x00000100L +#define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ__SHIFT 0x00000008 +#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_MASK 0x00000020L +#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ_MASK 0x00000080L +#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ__SHIFT 0x00000007 +#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL__SHIFT 0x00000005 +#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000L +#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x0000001d +#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x00080000L +#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x00000013 +#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x80000000L +#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x0000001f +#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x00000004L +#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x00000002 +#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x00000002L +#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x00000001 +#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK 0x00004000L +#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT 0x0000000e +#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000L +#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x0000001f +#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x00000010L +#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x00000004 +#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x00000008L +#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x00000003 +#define DB_DEBUG2__ENABLE_PREZL_CB_STALL_MASK 0x00000040L +#define DB_DEBUG2__ENABLE_PREZL_CB_STALL__SHIFT 0x00000006 +#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000L +#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x0000001c +#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK 0x00008000L +#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT 0x0000000f +#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK 0x00020000L +#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT 0x00000011 +#define DB_DEBUG3__DB_EXTRA_DEBUG3_MASK 0xfc000000L +#define DB_DEBUG3__DB_EXTRA_DEBUG3__SHIFT 0x0000001a +#define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK 0x02000000L +#define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT 0x00000019 +#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK 0x01000000L +#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT 0x00000018 +#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x00000010L +#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x00000004 +#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x00200000L +#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x00000015 +#define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x00004000L +#define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0x0000000e +#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x00010000L +#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0x00000010 +#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x00008000L +#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0x0000000f +#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK 0x00080000L +#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT 0x00000013 +#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK 0x00002000L +#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT 0x0000000d +#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x08000000L +#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x0000001b +#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x00800000L +#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x00000017 +#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x00000800L +#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0x0000000b +#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK 0x00000400L +#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT 0x0000000a +#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK 0x00000080L +#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT 0x00000007 +#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x00100000L +#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT 0x00000014 +#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x00000008L +#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x00000003 +#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x00000100L +#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x00000008 +#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK 0x20000000L +#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT 0x0000001d +#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK 0x10000000L +#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT 0x0000001c +#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x04000000L +#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x0000001a +#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK 0x00001000L +#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT 0x0000000c +#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x00400000L +#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x00000016 +#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK 0x00800000L +#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT 0x00000017 +#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x00000020L +#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x00000005 +#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x00000040L +#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x00000006 +#define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x00000004L +#define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x00000002 +#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x00040000L +#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x00000012 +#define DB_DEBUG4__DB_EXTRA_DEBUG4_MASK 0xffffffc0L +#define DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT 0x00000006 +#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x00000020L +#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x00000005 +#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x00000002L +#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x00000001 +#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x00000001L +#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x00000000 +#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x00000004L +#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x00000002 +#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x00000002L +#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x00000001 +#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x00008000L +#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0x0000000f +#define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x00004000L +#define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0x0000000e +#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x00000040L +#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x00000006 +#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x00180000L +#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x00000013 +#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0x00000c00L +#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0x0000000a +#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x00003000L +#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0x0000000c +#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x00000300L +#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x00000008 +#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x00000080L +#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x00000007 +#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x00010000L +#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x00000010 +#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x00000001L +#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x00000000 +#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0x0f000000L +#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x00000018 +#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x00040000L +#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x00000012 +#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000L +#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x0000001e +#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000L +#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x0000001f +#define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x00020000L +#define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x00000011 +#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x00800000L +#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x00000017 +#define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x00000008L +#define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x00000003 +#define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x00000004L +#define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x00000002 +#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000L +#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x0000001d +#define DB_DEBUG__FORCE_Z_MODE_MASK 0x00000030L +#define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x00000004 +#define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x00200000L +#define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x00000015 +#define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000L +#define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x0000001c +#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x00400000L +#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x00000016 +#define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xffffffffL +#define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x00000000 +#define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xffffffffL +#define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x00000000 +#define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xffffffffL +#define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x00000000 +#define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x00000080L +#define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x00000007 +#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x00000008L +#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x00000003 +#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK 0x80000000L +#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT 0x0000001f +#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK 0x40000000L +#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT 0x0000001e +#define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x00000001L +#define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x00000000 +#define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x00700000L +#define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x00000014 +#define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x00000700L +#define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x00000008 +#define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x00000002L +#define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x00000001 +#define DB_DEPTH_CONTROL__ZFUNC_MASK 0x00000070L +#define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x00000004 +#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x00000004L +#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x00000002 +#define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK_MASK 0x0000000fL +#define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK__SHIFT 0x00000000 +#define DB_DEPTH_INFO__ARRAY_MODE_MASK 0x000000f0L +#define DB_DEPTH_INFO__ARRAY_MODE__SHIFT 0x00000004 +#define DB_DEPTH_INFO__BANK_HEIGHT_MASK 0x00018000L +#define DB_DEPTH_INFO__BANK_HEIGHT__SHIFT 0x0000000f +#define DB_DEPTH_INFO__BANK_WIDTH_MASK 0x00006000L +#define DB_DEPTH_INFO__BANK_WIDTH__SHIFT 0x0000000d +#define DB_DEPTH_INFO__MACRO_TILE_ASPECT_MASK 0x00060000L +#define DB_DEPTH_INFO__MACRO_TILE_ASPECT__SHIFT 0x00000011 +#define DB_DEPTH_INFO__NUM_BANKS_MASK 0x00180000L +#define DB_DEPTH_INFO__NUM_BANKS__SHIFT 0x00000013 +#define DB_DEPTH_INFO__PIPE_CONFIG_MASK 0x00001f00L +#define DB_DEPTH_INFO__PIPE_CONFIG__SHIFT 0x00000008 +#define DB_DEPTH_SIZE__HEIGHT_TILE_MAX_MASK 0x003ff800L +#define DB_DEPTH_SIZE__HEIGHT_TILE_MAX__SHIFT 0x0000000b +#define DB_DEPTH_SIZE__PITCH_TILE_MAX_MASK 0x000007ffL +#define DB_DEPTH_SIZE__PITCH_TILE_MAX__SHIFT 0x00000000 +#define DB_DEPTH_SLICE__SLICE_TILE_MAX_MASK 0x003fffffL +#define DB_DEPTH_SLICE__SLICE_TILE_MAX__SHIFT 0x00000000 +#define DB_DEPTH_VIEW__SLICE_MAX_MASK 0x00ffe000L +#define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0x0000000d +#define DB_DEPTH_VIEW__SLICE_START_MASK 0x000007ffL +#define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x00000000 +#define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK 0x02000000L +#define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT 0x00000019 +#define DB_DEPTH_VIEW__Z_READ_ONLY_MASK 0x01000000L +#define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT 0x00000018 +#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK 0x00200000L +#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT 0x00000015 +#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x00007000L +#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0x0000000c +#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x08000000L +#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x0000001b +#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x00010000L +#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x00000010 +#define DB_EQAA__INCOHERENT_EQAA_READS_MASK 0x00020000L +#define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT 0x00000011 +#define DB_EQAA__INTERPOLATE_COMP_Z_MASK 0x00040000L +#define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT 0x00000012 +#define DB_EQAA__INTERPOLATE_SRC_Z_MASK 0x00080000L +#define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT 0x00000013 +#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x00000700L +#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x00000008 +#define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK 0x00000007L +#define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT 0x00000000 +#define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x07000000L +#define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x00000018 +#define DB_EQAA__PS_ITER_SAMPLES_MASK 0x00000070L +#define DB_EQAA__PS_ITER_SAMPLES__SHIFT 0x00000004 +#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x00100000L +#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x00000014 +#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK 0x1fe00000L +#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x00000015 +#define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0x0000fc00L +#define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0x0000000a +#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH_MASK 0x0000001fL +#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH__SHIFT 0x00000000 +#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH_MASK 0x000003e0L +#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH__SHIFT 0x00000005 +#define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0x001f0000L +#define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x00000010 +#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0x000000ffL +#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x00000000 +#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x00007f00L +#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x00000008 +#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x01ff8000L +#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0x0000000f +#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xfe000000L +#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x00000019 +#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x0000007fL +#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x00000000 +#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0x01e00000L +#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x00000015 +#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x00003f80L +#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x00000007 +#define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x001fc000L +#define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0x0000000e +#define DB_FREE_CACHELINES__QUAD_READ_REQS_MASK 0xfe000000L +#define DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT 0x00000019 +#define DB_HTILE_DATA_BASE__BASE_256B_MASK 0xffffffffL +#define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x00000000 +#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x00010000L +#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x00000010 +#define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x00000002L +#define DB_HTILE_SURFACE__FULL_CACHE__SHIFT 0x00000001 +#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK 0x00000004L +#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT 0x00000002 +#define DB_HTILE_SURFACE__LINEAR_MASK 0x00000001L +#define DB_HTILE_SURFACE__LINEAR__SHIFT 0x00000000 +#define DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK 0x0000fc00L +#define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT 0x0000000a +#define DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK 0x000003f0L +#define DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT 0x00000004 +#define DB_HTILE_SURFACE__PRELOAD_MASK 0x00000008L +#define DB_HTILE_SURFACE__PRELOAD__SHIFT 0x00000003 +#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000L +#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x0000001c +#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0f000000L +#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x00000018 +#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003ffL +#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 +#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L +#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a +#define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L +#define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0f000000L +#define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x00000018 +#define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L +#define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c +#define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000ffc00L +#define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a +#define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL +#define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 +#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000L +#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x0000001c +#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0f000000L +#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x00000018 +#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003ffL +#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x00000000 +#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000ffc00L +#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0x0000000a +#define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L +#define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0f000000L +#define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x00000018 +#define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L +#define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c +#define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000ffc00L +#define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0x0000000a +#define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL +#define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 +#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00f00000L +#define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0f000000L +#define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x00000018 +#define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000L +#define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x0000001c +#define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000ffc00L +#define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0x0000000a +#define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL +#define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 +#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00f00000L +#define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0f000000L +#define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x00000018 +#define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000L +#define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x0000001c +#define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000ffc00L +#define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0x0000000a +#define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL +#define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 +#define DB_PRELOAD_CONTROL__MAX_X_MASK 0x00ff0000L +#define DB_PRELOAD_CONTROL__MAX_X__SHIFT 0x00000010 +#define DB_PRELOAD_CONTROL__MAX_Y_MASK 0xff000000L +#define DB_PRELOAD_CONTROL__MAX_Y__SHIFT 0x00000018 +#define DB_PRELOAD_CONTROL__START_X_MASK 0x000000ffL +#define DB_PRELOAD_CONTROL__START_X__SHIFT 0x00000000 +#define DB_PRELOAD_CONTROL__START_Y_MASK 0x0000ff00L +#define DB_PRELOAD_CONTROL__START_Y__SHIFT 0x00000008 +#define DB_READ_DEBUG_0__BUSY_DATA0_MASK 0xffffffffL +#define DB_READ_DEBUG_0__BUSY_DATA0__SHIFT 0x00000000 +#define DB_READ_DEBUG_1__BUSY_DATA1_MASK 0xffffffffL +#define DB_READ_DEBUG_1__BUSY_DATA1__SHIFT 0x00000000 +#define DB_READ_DEBUG_2__BUSY_DATA2_MASK 0xffffffffL +#define DB_READ_DEBUG_2__BUSY_DATA2__SHIFT 0x00000000 +#define DB_READ_DEBUG_3__DEBUG_DATA_MASK 0xffffffffL +#define DB_READ_DEBUG_3__DEBUG_DATA__SHIFT 0x00000000 +#define DB_READ_DEBUG_4__DEBUG_DATA_MASK 0xffffffffL +#define DB_READ_DEBUG_4__DEBUG_DATA__SHIFT 0x00000000 +#define DB_READ_DEBUG_5__DEBUG_DATA_MASK 0xffffffffL +#define DB_READ_DEBUG_5__DEBUG_DATA__SHIFT 0x00000000 +#define DB_READ_DEBUG_6__DEBUG_DATA_MASK 0xffffffffL +#define DB_READ_DEBUG_6__DEBUG_DATA__SHIFT 0x00000000 +#define DB_READ_DEBUG_7__DEBUG_DATA_MASK 0xffffffffL +#define DB_READ_DEBUG_7__DEBUG_DATA__SHIFT 0x00000000 +#define DB_READ_DEBUG_8__DEBUG_DATA_MASK 0xffffffffL +#define DB_READ_DEBUG_8__DEBUG_DATA__SHIFT 0x00000000 +#define DB_READ_DEBUG_9__DEBUG_DATA_MASK 0xffffffffL +#define DB_READ_DEBUG_9__DEBUG_DATA__SHIFT 0x00000000 +#define DB_READ_DEBUG_A__DEBUG_DATA_MASK 0xffffffffL +#define DB_READ_DEBUG_A__DEBUG_DATA__SHIFT 0x00000000 +#define DB_READ_DEBUG_B__DEBUG_DATA_MASK 0xffffffffL +#define DB_READ_DEBUG_B__DEBUG_DATA__SHIFT 0x00000000 +#define DB_READ_DEBUG_C__DEBUG_DATA_MASK 0xffffffffL +#define DB_READ_DEBUG_C__DEBUG_DATA__SHIFT 0x00000000 +#define DB_READ_DEBUG_D__DEBUG_DATA_MASK 0xffffffffL +#define DB_READ_DEBUG_D__DEBUG_DATA__SHIFT 0x00000000 +#define DB_READ_DEBUG_E__DEBUG_DATA_MASK 0xffffffffL +#define DB_READ_DEBUG_E__DEBUG_DATA__SHIFT 0x00000000 +#define DB_READ_DEBUG_F__DEBUG_DATA_MASK 0xffffffffL +#define DB_READ_DEBUG_F__DEBUG_DATA__SHIFT 0x00000000 +#define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x00000080L +#define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x00000007 +#define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0x00000f00L +#define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x00000008 +#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x00000001L +#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x00000000 +#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x00000040L +#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x00000006 +#define DB_RENDER_CONTROL__DEPTH_COPY_MASK 0x00000004L +#define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT 0x00000002 +#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK 0x00000010L +#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT 0x00000004 +#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x00000002L +#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x00000001 +#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x00000020L +#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x00000005 +#define DB_RENDER_CONTROL__STENCIL_COPY_MASK 0x00000008L +#define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT 0x00000003 +#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x00000100L +#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x00000008 +#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x00000400L +#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0x0000000a +#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x00000080L +#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x00000007 +#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x00800000L +#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x00000017 +#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK 0x00000200L +#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT 0x00000009 +#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK 0x00000040L +#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT 0x00000006 +#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK 0x00000020L +#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT 0x00000005 +#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK 0x001c0000L +#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT 0x00000012 +#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK 0x00038000L +#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT 0x0000000f +#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK 0x00007000L +#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT 0x0000000c +#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x00000003L +#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x00000000 +#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x0000001cL +#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x00000002 +#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK 0x00400000L +#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT 0x00000016 +#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x00200000L +#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x00000015 +#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK 0x00000800L +#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT 0x0000000b +#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK 0x00040000L +#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT 0x00000012 +#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x04000000L +#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x0000001a +#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK 0x00010000L +#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT 0x00000010 +#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x00000100L +#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x00000008 +#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x00000080L +#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x00000007 +#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x00000400L +#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0x0000000a +#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x00006000L +#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0x0000000d +#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0x0000000cL +#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x00000002 +#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x00000030L +#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x00000004 +#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x00000003L +#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x00000000 +#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK 0x00008000L +#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT 0x0000000f +#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x00000040L +#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x00000006 +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000L +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x0000001c +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x00001000L +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0x0000000c +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000L +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x0000001e +#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x08000000L +#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x0000001b +#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x00180000L +#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x00000013 +#define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x00000800L +#define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0x0000000b +#define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000L +#define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x0000001d +#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK 0x00020000L +#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT 0x00000011 +#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x03e00000L +#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x00000015 +#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x00000200L +#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x00000009 +#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000L +#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x0000001f +#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x00000800L +#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0x0000000b +#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x00006000L +#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0x0000000d +#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x00000080L +#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x00000007 +#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x00001000L +#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0x0000000c +#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x00000200L +#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x00000009 +#define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x00000400L +#define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0x0000000a +#define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x00000040L +#define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x00000006 +#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x00000100L +#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x00000008 +#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x00000004L +#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x00000002 +#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x00000002L +#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x00000001 +#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x00000001L +#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x00000000 +#define DB_SHADER_CONTROL__Z_ORDER_MASK 0x00000030L +#define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x00000004 +#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x00000007L +#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x00000000 +#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0x000ff000L +#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0x0000000c +#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0x00000ff0L +#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x00000004 +#define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK 0x01000000L +#define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT 0x00000018 +#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x00000007L +#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x00000000 +#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0x000ff000L +#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0x0000000c +#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0x00000ff0L +#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x00000004 +#define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK 0x01000000L +#define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT 0x00000018 +#define DB_STENCIL_CLEAR__CLEAR_MASK 0x000000ffL +#define DB_STENCIL_CLEAR__CLEAR__SHIFT 0x00000000 +#define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0x0000f000L +#define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0x0000000c +#define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0x0000000fL +#define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x00000000 +#define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0x00f00000L +#define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x00000014 +#define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0x00000f00L +#define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x00000008 +#define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0x000f0000L +#define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x00000010 +#define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0x000000f0L +#define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x00000004 +#define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L +#define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT 0x0000001b +#define DB_STENCIL_INFO__FORMAT_MASK 0x00000001L +#define DB_STENCIL_INFO__FORMAT__SHIFT 0x00000000 +#define DB_STENCIL_INFO__TILE_MODE_INDEX_MASK 0x00700000L +#define DB_STENCIL_INFO__TILE_MODE_INDEX__SHIFT 0x00000014 +#define DB_STENCIL_INFO__TILE_SPLIT_MASK 0x0000e000L +#define DB_STENCIL_INFO__TILE_SPLIT__SHIFT 0x0000000d +#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000L +#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x0000001d +#define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xffffffffL +#define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x00000000 +#define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0x0000ff00L +#define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x00000008 +#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK 0xff000000L +#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT 0x00000018 +#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK 0x000000ffL +#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT 0x00000000 +#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0x00ff0000L +#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x00000010 +#define DB_STENCILREFMASK__STENCILMASK_MASK 0x0000ff00L +#define DB_STENCILREFMASK__STENCILMASK__SHIFT 0x00000008 +#define DB_STENCILREFMASK__STENCILOPVAL_MASK 0xff000000L +#define DB_STENCILREFMASK__STENCILOPVAL__SHIFT 0x00000018 +#define DB_STENCILREFMASK__STENCILTESTVAL_MASK 0x000000ffL +#define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT 0x00000000 +#define DB_STENCILREFMASK__STENCILWRITEMASK_MASK 0x00ff0000L +#define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x00000010 +#define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xffffffffL +#define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x00000000 +#define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x00030000L +#define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x00000010 +#define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0x000c0000L +#define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x00000012 +#define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x00000003L +#define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x00000000 +#define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0x0000000cL +#define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x00000002 +#define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x00000030L +#define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x00000004 +#define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0x000000c0L +#define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x00000006 +#define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x00000300L +#define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x00000008 +#define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0x00000c00L +#define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0x0000000a +#define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x00003000L +#define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0x0000000c +#define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0x0000c000L +#define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0x0000000e +#define DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK 0x40000000L +#define DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT 0x0000001e +#define DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK 0x80000000L +#define DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT 0x0000001f +#define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0x07f00000L +#define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x00000014 +#define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x000007e0L +#define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x00000005 +#define DB_WATERMARKS__DEPTH_FREE_MASK 0x0000001fL +#define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x00000000 +#define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0x000f8000L +#define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0x0000000f +#define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE_MASK 0x08000000L +#define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE__SHIFT 0x0000001b +#define DB_WATERMARKS__FORCE_SUMMARIZE_MASK 0x00007800L +#define DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT 0x0000000b +#define DB_WATERMARKS__LATE_Z_PANIC_DISABLE_MASK 0x10000000L +#define DB_WATERMARKS__LATE_Z_PANIC_DISABLE__SHIFT 0x0000001c +#define DB_WATERMARKS__RE_Z_PANIC_DISABLE_MASK 0x20000000L +#define DB_WATERMARKS__RE_Z_PANIC_DISABLE__SHIFT 0x0000001d +#define DB_Z_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L +#define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT 0x0000001b +#define DB_Z_INFO__FORMAT_MASK 0x00000003L +#define DB_Z_INFO__FORMAT__SHIFT 0x00000000 +#define DB_Z_INFO__NUM_SAMPLES_MASK 0x0000000cL +#define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x00000002 +#define DB_Z_INFO__READ_SIZE_MASK 0x10000000L +#define DB_Z_INFO__READ_SIZE__SHIFT 0x0000001c +#define DB_Z_INFO__TILE_MODE_INDEX_MASK 0x00700000L +#define DB_Z_INFO__TILE_MODE_INDEX__SHIFT 0x00000014 +#define DB_Z_INFO__TILE_SPLIT_MASK 0x0000e000L +#define DB_Z_INFO__TILE_SPLIT__SHIFT 0x0000000d +#define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000L +#define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x0000001d +#define DB_Z_INFO__ZRANGE_PRECISION_MASK 0x80000000L +#define DB_Z_INFO__ZRANGE_PRECISION__SHIFT 0x0000001f +#define DB_ZPASS_COUNT_HI__COUNT_HI_MASK 0x7fffffffL +#define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT 0x00000000 +#define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK 0xffffffffL +#define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT 0x00000000 +#define DB_Z_READ_BASE__BASE_256B_MASK 0xffffffffL +#define DB_Z_READ_BASE__BASE_256B__SHIFT 0x00000000 +#define DB_Z_WRITE_BASE__BASE_256B_MASK 0xffffffffL +#define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x00000000 +#define DEBUG_DATA__DEBUG_DATA_MASK 0xffffffffL +#define DEBUG_DATA__DEBUG_DATA__SHIFT 0x00000000 +#define DEBUG_INDEX__DEBUG_INDEX_MASK 0x0003ffffL +#define DEBUG_INDEX__DEBUG_INDEX__SHIFT 0x00000000 +#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008 +#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L +#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x00000018 +#define GB_ADDR_CONFIG__NUM_GPUS_MASK 0x00700000L +#define GB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x00000014 +#define GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L +#define GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e +#define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000 +#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L +#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c +#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L +#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004 +#define GB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L +#define GB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c +#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L +#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010 +#define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xffffffffL +#define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x00000000 +#define GB_EDC_MODE__BYPASS_MASK 0x80000000L +#define GB_EDC_MODE__BYPASS__SHIFT 0x0000001f +#define GB_EDC_MODE__DED_MODE_MASK 0x00300000L +#define GB_EDC_MODE__DED_MODE__SHIFT 0x00000014 +#define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x00010000L +#define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0x00000010 +#define GB_EDC_MODE__PROP_FED_MASK 0x20000000L +#define GB_EDC_MODE__PROP_FED__SHIFT 0x0000001d +#define GB_GPU_ID__GPU_ID_MASK 0x0000000fL +#define GB_GPU_ID__GPU_ID__SHIFT 0x00000000 +#define GB_TILE_MODE0__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE0__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE0__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE0__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE0__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE0__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE0__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE10__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE10__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE10__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE10__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE10__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE10__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE10__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE11__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE11__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE11__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE11__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE11__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE11__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE11__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE12__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE12__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE12__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE12__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE12__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE12__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE12__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE13__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE13__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE13__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE13__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE13__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE13__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE13__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE14__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE14__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE14__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE14__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE14__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE14__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE14__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE15__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE15__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE15__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE15__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE15__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE15__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE15__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE16__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE16__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE16__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE16__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE16__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE16__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE16__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE17__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE17__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE17__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE17__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE17__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE17__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE17__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE18__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE18__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE18__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE18__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE18__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE18__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE18__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE19__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE19__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE19__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE19__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE19__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE19__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE19__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE1__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE1__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE1__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE1__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE1__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE1__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE1__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE20__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE20__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE20__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE20__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE20__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE20__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE20__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE21__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE21__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE21__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE21__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE21__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE21__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE21__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE22__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE22__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE22__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE22__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE22__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE22__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE22__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE23__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE23__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE23__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE23__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE23__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE23__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE23__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE24__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE24__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE24__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE24__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE24__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE24__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE24__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE25__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE25__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE25__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE25__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE25__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE25__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE25__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE26__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE26__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE26__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE26__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE26__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE26__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE26__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE27__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE27__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE27__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE27__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE27__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE27__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE27__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE28__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE28__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE28__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE28__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE28__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE28__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE28__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE29__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE29__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE29__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE29__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE29__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE29__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE29__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE2__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE2__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE2__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE2__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE2__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE2__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE2__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE30__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE30__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE30__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE30__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE30__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE30__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE30__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE31__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE31__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE31__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE31__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE31__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE31__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE31__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE3__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE3__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE3__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE3__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE3__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE3__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE3__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE4__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE4__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE4__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE4__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE4__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE4__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE4__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE5__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE5__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE5__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE5__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE5__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE5__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE5__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE6__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE6__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE6__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE6__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE6__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE6__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE6__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE7__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE7__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE7__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE7__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE7__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE7__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE7__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE8__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE8__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE8__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE8__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE8__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE8__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE8__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE9__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE9__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE9__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE9__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE9__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE9__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE9__TILE_SPLIT__SHIFT 0x0000000b +#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00ff0000L +#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x00000010 +#define GC_USER_SHADER_ARRAY_CONFIG__DPFP_RATE_MASK 0x00000006L +#define GC_USER_SHADER_ARRAY_CONFIG__DPFP_RATE__SHIFT 0x00000001 +#define GC_USER_SHADER_ARRAY_CONFIG__HALF_LDS_MASK 0x00000010L +#define GC_USER_SHADER_ARRAY_CONFIG__HALF_LDS__SHIFT 0x00000004 +#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xffff0000L +#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x00000010 +#define GC_USER_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L +#define GC_USER_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x00000003 +#define GDS_ATOM_BASE__BASE_MASK 0x0000ffffL +#define GDS_ATOM_BASE__BASE__SHIFT 0x00000000 +#define GDS_ATOM_BASE__UNUSED_MASK 0xffff0000L +#define GDS_ATOM_BASE__UNUSED__SHIFT 0x00000010 +#define GDS_ATOM_CNTL__AINC_MASK 0x0000003fL +#define GDS_ATOM_CNTL__AINC__SHIFT 0x00000000 +#define GDS_ATOM_CNTL__DMODE_MASK 0x00000100L +#define GDS_ATOM_CNTL__DMODE__SHIFT 0x00000008 +#define GDS_ATOM_CNTL__UNUSED1_MASK 0x000000c0L +#define GDS_ATOM_CNTL__UNUSED1__SHIFT 0x00000006 +#define GDS_ATOM_CNTL__UNUSED2_MASK 0xfffffe00L +#define GDS_ATOM_CNTL__UNUSED2__SHIFT 0x00000009 +#define GDS_ATOM_COMPLETE__COMPLETE_MASK 0x00000001L +#define GDS_ATOM_COMPLETE__COMPLETE__SHIFT 0x00000000 +#define GDS_ATOM_COMPLETE__UNUSED_MASK 0xfffffffeL +#define GDS_ATOM_COMPLETE__UNUSED__SHIFT 0x00000001 +#define GDS_ATOM_DST__DST_MASK 0xffffffffL +#define GDS_ATOM_DST__DST__SHIFT 0x00000000 +#define GDS_ATOM_OFFSET0__OFFSET0_MASK 0x000000ffL +#define GDS_ATOM_OFFSET0__OFFSET0__SHIFT 0x00000000 +#define GDS_ATOM_OFFSET0__UNUSED_MASK 0xffffff00L +#define GDS_ATOM_OFFSET0__UNUSED__SHIFT 0x00000008 +#define GDS_ATOM_OFFSET1__OFFSET1_MASK 0x000000ffL +#define GDS_ATOM_OFFSET1__OFFSET1__SHIFT 0x00000000 +#define GDS_ATOM_OFFSET1__UNUSED_MASK 0xffffff00L +#define GDS_ATOM_OFFSET1__UNUSED__SHIFT 0x00000008 +#define GDS_ATOM_OP__OP_MASK 0x000000ffL +#define GDS_ATOM_OP__OP__SHIFT 0x00000000 +#define GDS_ATOM_OP__UNUSED_MASK 0xffffff00L +#define GDS_ATOM_OP__UNUSED__SHIFT 0x00000008 +#define GDS_ATOM_READ0__DATA_MASK 0xffffffffL +#define GDS_ATOM_READ0__DATA__SHIFT 0x00000000 +#define GDS_ATOM_READ0_U__DATA_MASK 0xffffffffL +#define GDS_ATOM_READ0_U__DATA__SHIFT 0x00000000 +#define GDS_ATOM_READ1__DATA_MASK 0xffffffffL +#define GDS_ATOM_READ1__DATA__SHIFT 0x00000000 +#define GDS_ATOM_READ1_U__DATA_MASK 0xffffffffL +#define GDS_ATOM_READ1_U__DATA__SHIFT 0x00000000 +#define GDS_ATOM_SIZE__SIZE_MASK 0x0000ffffL +#define GDS_ATOM_SIZE__SIZE__SHIFT 0x00000000 +#define GDS_ATOM_SIZE__UNUSED_MASK 0xffff0000L +#define GDS_ATOM_SIZE__UNUSED__SHIFT 0x00000010 +#define GDS_ATOM_SRC0__DATA_MASK 0xffffffffL +#define GDS_ATOM_SRC0__DATA__SHIFT 0x00000000 +#define GDS_ATOM_SRC0_U__DATA_MASK 0xffffffffL +#define GDS_ATOM_SRC0_U__DATA__SHIFT 0x00000000 +#define GDS_ATOM_SRC1__DATA_MASK 0xffffffffL +#define GDS_ATOM_SRC1__DATA__SHIFT 0x00000000 +#define GDS_ATOM_SRC1_U__DATA_MASK 0xffffffffL +#define GDS_ATOM_SRC1_U__DATA__SHIFT 0x00000000 +#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK 0x00000010L +#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT 0x00000004 +#define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK 0x00000008L +#define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT 0x00000003 +#define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK 0x00000040L +#define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT 0x00000006 +#define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK 0x00000020L +#define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x00000005 +#define GDS_CNTL_STATUS__GDS_BUSY_MASK 0x00000001L +#define GDS_CNTL_STATUS__GDS_BUSY__SHIFT 0x00000000 +#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK 0x00000002L +#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT 0x00000001 +#define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK 0x00000004L +#define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT 0x00000002 +#define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x00000006L +#define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT 0x00000001 +#define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK 0x00000018L +#define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x00000003 +#define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK 0x00000060L +#define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x00000005 +#define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x00000180L +#define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT 0x00000007 +#define GDS_DEBUG_CNTL__GDS_DEBUG_INDX_MASK 0x0000001fL +#define GDS_DEBUG_CNTL__GDS_DEBUG_INDX__SHIFT 0x00000000 +#define GDS_DEBUG_CNTL__UNUSED_MASK 0xffffffe0L +#define GDS_DEBUG_CNTL__UNUSED__SHIFT 0x00000005 +#define GDS_DEBUG_DATA__DATA_MASK 0xffffffffL +#define GDS_DEBUG_DATA__DATA__SHIFT 0x00000000 +#define GDS_DEBUG_REG0__buff_write_MASK 0x00020000L +#define GDS_DEBUG_REG0__buff_write__SHIFT 0x00000011 +#define GDS_DEBUG_REG0__cstate_MASK 0x0001e000L +#define GDS_DEBUG_REG0__cstate__SHIFT 0x0000000d +#define GDS_DEBUG_REG0__flush_request_MASK 0x00040000L +#define GDS_DEBUG_REG0__flush_request__SHIFT 0x00000012 +#define GDS_DEBUG_REG0__last_pixel_ptr_MASK 0x00001000L +#define GDS_DEBUG_REG0__last_pixel_ptr__SHIFT 0x0000000c +#define GDS_DEBUG_REG0__spare1_MASK 0x00000001L +#define GDS_DEBUG_REG0__spare1__SHIFT 0x00000000 +#define GDS_DEBUG_REG0__spare_MASK 0xff000000L +#define GDS_DEBUG_REG0__spare__SHIFT 0x00000018 +#define GDS_DEBUG_REG0__wbuf_fifo_empty_MASK 0x00100000L +#define GDS_DEBUG_REG0__wbuf_fifo_empty__SHIFT 0x00000014 +#define GDS_DEBUG_REG0__wbuf_fifo_full_MASK 0x00200000L +#define GDS_DEBUG_REG0__wbuf_fifo_full__SHIFT 0x00000015 +#define GDS_DEBUG_REG0__wr_buffer_wr_complete_MASK 0x00080000L +#define GDS_DEBUG_REG0__wr_buffer_wr_complete__SHIFT 0x00000013 +#define GDS_DEBUG_REG0__write_buff_valid_MASK 0x00000040L +#define GDS_DEBUG_REG0__write_buff_valid__SHIFT 0x00000006 +#define GDS_DEBUG_REG0__wr_pixel_nxt_ptr_MASK 0x00000f80L +#define GDS_DEBUG_REG0__wr_pixel_nxt_ptr__SHIFT 0x00000007 +#define GDS_DEBUG_REG1__addr_fifo_empty_MASK 0x00200000L +#define GDS_DEBUG_REG1__addr_fifo_empty__SHIFT 0x00000015 +#define GDS_DEBUG_REG1__addr_fifo_full_MASK 0x00100000L +#define GDS_DEBUG_REG1__addr_fifo_full__SHIFT 0x00000014 +#define GDS_DEBUG_REG1__awaiting_data_MASK 0x00080000L +#define GDS_DEBUG_REG1__awaiting_data__SHIFT 0x00000013 +#define GDS_DEBUG_REG1__buffer_invalid_MASK 0x00800000L +#define GDS_DEBUG_REG1__buffer_invalid__SHIFT 0x00000017 +#define GDS_DEBUG_REG1__buffer_loaded_MASK 0x00400000L +#define GDS_DEBUG_REG1__buffer_loaded__SHIFT 0x00000016 +#define GDS_DEBUG_REG1__data_ready_MASK 0x00040000L +#define GDS_DEBUG_REG1__data_ready__SHIFT 0x00000012 +#define GDS_DEBUG_REG1__pixel_addr_MASK 0x0001fffcL +#define GDS_DEBUG_REG1__pixel_addr__SHIFT 0x00000002 +#define GDS_DEBUG_REG1__pixel_vld_MASK 0x00020000L +#define GDS_DEBUG_REG1__pixel_vld__SHIFT 0x00000011 +#define GDS_DEBUG_REG1__spare_MASK 0xff000000L +#define GDS_DEBUG_REG1__spare__SHIFT 0x00000018 +#define GDS_DEBUG_REG1__tag_hit_MASK 0x00000001L +#define GDS_DEBUG_REG1__tag_hit__SHIFT 0x00000000 +#define GDS_DEBUG_REG1__tag_miss_MASK 0x00000002L +#define GDS_DEBUG_REG1__tag_miss__SHIFT 0x00000001 +#define GDS_DEBUG_REG2__app_sel_MASK 0x000000f0L +#define GDS_DEBUG_REG2__app_sel__SHIFT 0x00000004 +#define GDS_DEBUG_REG2__cmd_write_MASK 0x00000008L +#define GDS_DEBUG_REG2__cmd_write__SHIFT 0x00000003 +#define GDS_DEBUG_REG2__ds_credit_avail_MASK 0x00000002L +#define GDS_DEBUG_REG2__ds_credit_avail__SHIFT 0x00000001 +#define GDS_DEBUG_REG2__ds_full_MASK 0x00000001L +#define GDS_DEBUG_REG2__ds_full__SHIFT 0x00000000 +#define GDS_DEBUG_REG2__ord_idx_free_MASK 0x00000004L +#define GDS_DEBUG_REG2__ord_idx_free__SHIFT 0x00000002 +#define GDS_DEBUG_REG2__req_MASK 0x007fff00L +#define GDS_DEBUG_REG2__req__SHIFT 0x00000008 +#define GDS_DEBUG_REG2__spare_MASK 0xff000000L +#define GDS_DEBUG_REG2__spare__SHIFT 0x00000018 +#define GDS_DEBUG_REG3__pipe0_busy_num_MASK 0x00007800L +#define GDS_DEBUG_REG3__pipe0_busy_num__SHIFT 0x0000000b +#define GDS_DEBUG_REG3__pipe_num_busy_MASK 0x000007ffL +#define GDS_DEBUG_REG3__pipe_num_busy__SHIFT 0x00000000 +#define GDS_DEBUG_REG3__spare_MASK 0xff000000L +#define GDS_DEBUG_REG3__spare__SHIFT 0x00000018 +#define GDS_DEBUG_REG4__cmd_write_MASK 0x00020000L +#define GDS_DEBUG_REG4__cmd_write__SHIFT 0x00000011 +#define GDS_DEBUG_REG4__credit_cnt_gt0_MASK 0x00010000L +#define GDS_DEBUG_REG4__credit_cnt_gt0__SHIFT 0x00000010 +#define GDS_DEBUG_REG4__cur_reso_barrier_MASK 0x00002000L +#define GDS_DEBUG_REG4__cur_reso_barrier__SHIFT 0x0000000d +#define GDS_DEBUG_REG4__cur_reso_cnt_gt0_MASK 0x00008000L +#define GDS_DEBUG_REG4__cur_reso_cnt_gt0__SHIFT 0x0000000f +#define GDS_DEBUG_REG4__cur_reso_fed_MASK 0x00001000L +#define GDS_DEBUG_REG4__cur_reso_fed__SHIFT 0x0000000c +#define GDS_DEBUG_REG4__cur_reso_flag_MASK 0x00004000L +#define GDS_DEBUG_REG4__cur_reso_flag__SHIFT 0x0000000e +#define GDS_DEBUG_REG4__cur_reso_head_dirty_MASK 0x00000400L +#define GDS_DEBUG_REG4__cur_reso_head_dirty__SHIFT 0x0000000a +#define GDS_DEBUG_REG4__cur_reso_head_flag_MASK 0x00000800L +#define GDS_DEBUG_REG4__cur_reso_head_flag__SHIFT 0x0000000b +#define GDS_DEBUG_REG4__cur_reso_head_valid_MASK 0x00000200L +#define GDS_DEBUG_REG4__cur_reso_head_valid__SHIFT 0x00000009 +#define GDS_DEBUG_REG4__cur_reso_MASK 0x000001f8L +#define GDS_DEBUG_REG4__cur_reso__SHIFT 0x00000003 +#define GDS_DEBUG_REG4__grbm_gws_reso_rd_MASK 0x00080000L +#define GDS_DEBUG_REG4__grbm_gws_reso_rd__SHIFT 0x00000013 +#define GDS_DEBUG_REG4__grbm_gws_reso_wr_MASK 0x00040000L +#define GDS_DEBUG_REG4__grbm_gws_reso_wr__SHIFT 0x00000012 +#define GDS_DEBUG_REG4__gws_bulkfree_MASK 0x00200000L +#define GDS_DEBUG_REG4__gws_bulkfree__SHIFT 0x00000015 +#define GDS_DEBUG_REG4__gws_busy_MASK 0x00000001L +#define GDS_DEBUG_REG4__gws_busy__SHIFT 0x00000000 +#define GDS_DEBUG_REG4__gws_out_stall_MASK 0x00000004L +#define GDS_DEBUG_REG4__gws_out_stall__SHIFT 0x00000002 +#define GDS_DEBUG_REG4__gws_req_MASK 0x00000002L +#define GDS_DEBUG_REG4__gws_req__SHIFT 0x00000001 +#define GDS_DEBUG_REG4__ram_gws_re_MASK 0x00400000L +#define GDS_DEBUG_REG4__ram_gws_re__SHIFT 0x00000016 +#define GDS_DEBUG_REG4__ram_gws_we_MASK 0x00800000L +#define GDS_DEBUG_REG4__ram_gws_we__SHIFT 0x00000017 +#define GDS_DEBUG_REG4__ram_read_busy_MASK 0x00100000L +#define GDS_DEBUG_REG4__ram_read_busy__SHIFT 0x00000014 +#define GDS_DEBUG_REG4__spare_MASK 0xff000000L +#define GDS_DEBUG_REG4__spare__SHIFT 0x00000018 +#define GDS_DEBUG_REG5__alloc_opco_error_MASK 0x00000004L +#define GDS_DEBUG_REG5__alloc_opco_error__SHIFT 0x00000002 +#define GDS_DEBUG_REG5__dealloc_opco_error_MASK 0x00000008L +#define GDS_DEBUG_REG5__dealloc_opco_error__SHIFT 0x00000003 +#define GDS_DEBUG_REG5__dec_error_MASK 0x00000002L +#define GDS_DEBUG_REG5__dec_error__SHIFT 0x00000001 +#define GDS_DEBUG_REG5__error_ds_address_MASK 0x003fff00L +#define GDS_DEBUG_REG5__error_ds_address__SHIFT 0x00000008 +#define GDS_DEBUG_REG5__spare1_MASK 0xffc00000L +#define GDS_DEBUG_REG5__spare1__SHIFT 0x00000016 +#define GDS_DEBUG_REG5__spare_MASK 0xff000000L +#define GDS_DEBUG_REG5__spare__SHIFT 0x00000018 +#define GDS_DEBUG_REG5__wrap_opco_error_MASK 0x00000010L +#define GDS_DEBUG_REG5__wrap_opco_error__SHIFT 0x00000004 +#define GDS_DEBUG_REG5__write_dis_MASK 0x00000001L +#define GDS_DEBUG_REG5__write_dis__SHIFT 0x00000000 +#define GDS_DEBUG_REG6__counters_busy_MASK 0x001fffe0L +#define GDS_DEBUG_REG6__counters_busy__SHIFT 0x00000005 +#define GDS_DEBUG_REG6__counters_enabled_MASK 0x0000001eL +#define GDS_DEBUG_REG6__counters_enabled__SHIFT 0x00000001 +#define GDS_DEBUG_REG6__oa_busy_MASK 0x00000001L +#define GDS_DEBUG_REG6__oa_busy__SHIFT 0x00000000 +#define GDS_DEBUG_REG6__spare_MASK 0xff000000L +#define GDS_DEBUG_REG6__spare__SHIFT 0x00000018 +#define GDS_ENHANCE__AUTO_INC_INDEX_MASK 0x00010000L +#define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT 0x00000010 +#define GDS_ENHANCE__MISC_MASK 0x0000ffffL +#define GDS_ENHANCE__MISC__SHIFT 0x00000000 +#define GDS_ENHANCE__UNUSED_MASK 0xffff0000L +#define GDS_ENHANCE__UNUSED__SHIFT 0x00000010 +#define GDS_GRBM_SECDED_CNT__DED_MASK 0xffff0000L +#define GDS_GRBM_SECDED_CNT__DED__SHIFT 0x00000010 +#define GDS_GRBM_SECDED_CNT__SEC_MASK 0x0000ffffL +#define GDS_GRBM_SECDED_CNT__SEC__SHIFT 0x00000000 +#define GDS_GWS_RESOURCE_CNTL__INDEX_MASK 0x0000003fL +#define GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT 0x00000000 +#define GDS_GWS_RESOURCE_CNTL__UNUSED_MASK 0xffffffc0L +#define GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT 0x00000006 +#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK 0x0000ffffL +#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT 0x00000000 +#define GDS_GWS_RESOURCE_CNT__UNUSED_MASK 0xffff0000L +#define GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT 0x00000010 +#define GDS_GWS_RESOURCE__COUNTER_MASK 0x00001ffeL +#define GDS_GWS_RESOURCE__COUNTER__SHIFT 0x00000001 +#define GDS_GWS_RESOURCE__DED_MASK 0x00004000L +#define GDS_GWS_RESOURCE__DED__SHIFT 0x0000000e +#define GDS_GWS_RESOURCE__FLAG_MASK 0x00000001L +#define GDS_GWS_RESOURCE__FLAG__SHIFT 0x00000000 +#define GDS_GWS_RESOURCE__HEAD_FLAG_MASK 0x10000000L +#define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT 0x0000001c +#define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK 0x07ff0000L +#define GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT 0x00000010 +#define GDS_GWS_RESOURCE__HEAD_VALID_MASK 0x08000000L +#define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT 0x0000001b +#define GDS_GWS_RESOURCE__RELEASE_ALL_MASK 0x00008000L +#define GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT 0x0000000f +#define GDS_GWS_RESOURCE_RESET__RESET_MASK 0x00000001L +#define GDS_GWS_RESOURCE_RESET__RESET__SHIFT 0x00000000 +#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK 0x0000ff00L +#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT 0x00000008 +#define GDS_GWS_RESOURCE__TYPE_MASK 0x00002000L +#define GDS_GWS_RESOURCE__TYPE__SHIFT 0x0000000d +#define GDS_GWS_RESOURCE__UNUSED1_MASK 0xe0000000L +#define GDS_GWS_RESOURCE__UNUSED1__SHIFT 0x0000001d +#define GDS_OA_DED__ME0_CS_DED_MASK 0x00000004L +#define GDS_OA_DED__ME0_CS_DED__SHIFT 0x00000002 +#define GDS_OA_DED__ME0_GFXHP3D_PIX_DED_MASK 0x00000001L +#define GDS_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT 0x00000000 +#define GDS_OA_DED__ME0_GFXHP3D_VTX_DED_MASK 0x00000002L +#define GDS_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT 0x00000001 +#define GDS_OA_DED__ME1_PIPE0_DED_MASK 0x00000010L +#define GDS_OA_DED__ME1_PIPE0_DED__SHIFT 0x00000004 +#define GDS_OA_DED__ME1_PIPE1_DED_MASK 0x00000020L +#define GDS_OA_DED__ME1_PIPE1_DED__SHIFT 0x00000005 +#define GDS_OA_DED__ME1_PIPE2_DED_MASK 0x00000040L +#define GDS_OA_DED__ME1_PIPE2_DED__SHIFT 0x00000006 +#define GDS_OA_DED__ME1_PIPE3_DED_MASK 0x00000080L +#define GDS_OA_DED__ME1_PIPE3_DED__SHIFT 0x00000007 +#define GDS_OA_DED__ME2_PIPE0_DED_MASK 0x00000100L +#define GDS_OA_DED__ME2_PIPE0_DED__SHIFT 0x00000008 +#define GDS_OA_DED__ME2_PIPE1_DED_MASK 0x00000200L +#define GDS_OA_DED__ME2_PIPE1_DED__SHIFT 0x00000009 +#define GDS_OA_DED__ME2_PIPE2_DED_MASK 0x00000400L +#define GDS_OA_DED__ME2_PIPE2_DED__SHIFT 0x0000000a +#define GDS_OA_DED__ME2_PIPE3_DED_MASK 0x00000800L +#define GDS_OA_DED__ME2_PIPE3_DED__SHIFT 0x0000000b +#define GDS_OA_DED__UNUSED0_MASK 0x00000008L +#define GDS_OA_DED__UNUSED0__SHIFT 0x00000003 +#define GDS_OA_DED__UNUSED1_MASK 0xfffff000L +#define GDS_OA_DED__UNUSED1__SHIFT 0x0000000c +#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x000003ffL +#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x00000000 +#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0x000ffc00L +#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0x0000000a +#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L +#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0x000ffc00L +#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0x0000000a +#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL +#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 +#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L +#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0x000ffc00L +#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0x0000000a +#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL +#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 +#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00f00000L +#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0x000ffc00L +#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0x0000000a +#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL +#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 +#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00f00000L +#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0x000ffc00L +#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0x0000000a +#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL +#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 +#define GDS_RD_ADDR__READ_ADDR_MASK 0xffffffffL +#define GDS_RD_ADDR__READ_ADDR__SHIFT 0x00000000 +#define GDS_RD_BURST_ADDR__BURST_ADDR_MASK 0xffffffffL +#define GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT 0x00000000 +#define GDS_RD_BURST_COUNT__BURST_COUNT_MASK 0xffffffffL +#define GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT 0x00000000 +#define GDS_RD_BURST_DATA__BURST_DATA_MASK 0xffffffffL +#define GDS_RD_BURST_DATA__BURST_DATA__SHIFT 0x00000000 +#define GDS_RD_DATA__READ_DATA_MASK 0xffffffffL +#define GDS_RD_DATA__READ_DATA__SHIFT 0x00000000 +#define GDS_SECDED_CNT__DED_MASK 0xffff0000L +#define GDS_SECDED_CNT__DED__SHIFT 0x00000010 +#define GDS_SECDED_CNT__SEC_MASK 0x0000ffffL +#define GDS_SECDED_CNT__SEC__SHIFT 0x00000000 +#define GDS_WR_ADDR__WRITE_ADDR_MASK 0xffffffffL +#define GDS_WR_ADDR__WRITE_ADDR__SHIFT 0x00000000 +#define GDS_WR_BURST_ADDR__WRITE_ADDR_MASK 0xffffffffL +#define GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT 0x00000000 +#define GDS_WR_BURST_DATA__WRITE_DATA_MASK 0xffffffffL +#define GDS_WR_BURST_DATA__WRITE_DATA__SHIFT 0x00000000 +#define GDS_WR_DATA__WRITE_DATA_MASK 0xffffffffL +#define GDS_WR_DATA__WRITE_DATA__SHIFT 0x00000000 +#define GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK 0xffffffffL +#define GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT 0x00000000 +#define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L +#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x00000000 +#define GRBM_CAM_DATA__CAM_ADDR_MASK 0x0000ffffL +#define GRBM_CAM_DATA__CAM_ADDR__SHIFT 0x00000000 +#define GRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000L +#define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x00000010 +#define GRBM_CAM_INDEX__CAM_INDEX_MASK 0x00000007L +#define GRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x00000000 +#define GRBM_CNTL__READ_TIMEOUT_MASK 0x000000ffL +#define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x00000000 +#define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX_MASK 0x0000003fL +#define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX__SHIFT 0x00000000 +#define GRBM_DEBUG_DATA__DATA_MASK 0xffffffffL +#define GRBM_DEBUG_DATA__DATA__SHIFT 0x00000000 +#define GRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x00000040L +#define GRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x00000006 +#define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE_MASK 0x00001000L +#define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x0000000c +#define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE_MASK 0x00000f00L +#define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE__SHIFT 0x00000008 +#define GRBM_DEBUG__IGNORE_FAO_MASK 0x00000020L +#define GRBM_DEBUG__IGNORE_FAO__SHIFT 0x00000005 +#define GRBM_DEBUG__IGNORE_RDY_MASK 0x00000002L +#define GRBM_DEBUG__IGNORE_RDY__SHIFT 0x00000001 +#define GRBM_DEBUG_SNAPSHOT__CPF_RDY_MASK 0x00000001L +#define GRBM_DEBUG_SNAPSHOT__CPF_RDY__SHIFT 0x00000000 +#define GRBM_DEBUG_SNAPSHOT__CPG_RDY_MASK 0x00000002L +#define GRBM_DEBUG_SNAPSHOT__CPG_RDY__SHIFT 0x00000001 +#define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x00000080L +#define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x00000007 +#define GRBM_DEBUG_SNAPSHOT__GDS_RDY_MASK 0x00000200L +#define GRBM_DEBUG_SNAPSHOT__GDS_RDY__SHIFT 0x00000009 +#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0_MASK 0x00000040L +#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0__SHIFT 0x00000006 +#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1_MASK 0x00004000L +#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1__SHIFT 0x0000000e +#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0_MASK 0x00000080L +#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0__SHIFT 0x00000007 +#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1_MASK 0x00008000L +#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1__SHIFT 0x0000000f +#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0_MASK 0x00000100L +#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0__SHIFT 0x00000008 +#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1_MASK 0x00010000L +#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1__SHIFT 0x00000010 +#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0_MASK 0x00000200L +#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0__SHIFT 0x00000009 +#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1_MASK 0x00020000L +#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1__SHIFT 0x00000011 +#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0_MASK 0x00000400L +#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0__SHIFT 0x0000000a +#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1_MASK 0x00040000L +#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1__SHIFT 0x00000012 +#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0_MASK 0x00000800L +#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0__SHIFT 0x0000000b +#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1_MASK 0x00080000L +#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1__SHIFT 0x00000013 +#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0_MASK 0x00001000L +#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0__SHIFT 0x0000000c +#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1_MASK 0x00100000L +#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1__SHIFT 0x00000014 +#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0_MASK 0x00002000L +#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0__SHIFT 0x0000000d +#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1_MASK 0x00200000L +#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1__SHIFT 0x00000015 +#define GRBM_DEBUG_SNAPSHOT__SRBM_RDY_MASK 0x00000002L +#define GRBM_DEBUG_SNAPSHOT__SRBM_RDY__SHIFT 0x00000001 +#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY_MASK 0x00000008L +#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY__SHIFT 0x00000003 +#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY_MASK 0x00000010L +#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY__SHIFT 0x00000004 +#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001f00L +#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x00000008 +#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000fL +#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x00000000 +#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L +#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x0000001e +#define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0x000000ffL +#define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x00000000 +#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000L +#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x0000001f +#define GRBM_GFX_INDEX__SE_INDEX_MASK 0x00ff0000L +#define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x00000010 +#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK 0x20000000L +#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT 0x0000001d +#define GRBM_GFX_INDEX__SH_INDEX_MASK 0x0000ff00L +#define GRBM_GFX_INDEX__SH_INDEX__SHIFT 0x00000008 +#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x00080000L +#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x00000013 +#define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x00000001L +#define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x00000000 +#define GRBM_NOWHERE__DATA_MASK 0xffffffffL +#define GRBM_NOWHERE__DATA__SHIFT 0x00000000 +#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L +#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x00000019 +#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000015 +#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000b +#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L +#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x00000016 +#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000014 +#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000a +#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L +#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x00000018 +#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L +#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x00000013 +#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x00800000L +#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x00000017 +#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L +#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x00000012 +#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x0000003fL +#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 +#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L +#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x0000001a +#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L +#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x00000011 +#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L +#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x00000010 +#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L +#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000e +#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000d +#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L +#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x0000001b +#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00001000L +#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000c +#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000L +#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x0000001c +#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L +#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x00000019 +#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000015 +#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000b +#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L +#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x00000016 +#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000014 +#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000a +#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L +#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x00000018 +#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L +#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x00000013 +#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x00800000L +#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x00000017 +#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L +#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x00000012 +#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x0000003fL +#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 +#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L +#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x0000001a +#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L +#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x00000011 +#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L +#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x00000010 +#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L +#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000e +#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000d +#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L +#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x0000001b +#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00001000L +#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000c +#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000L +#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x0000001c +#define GRBM_PWR_CNTL__REQ_TYPE_MASK 0x0000000fL +#define GRBM_PWR_CNTL__REQ_TYPE__SHIFT 0x00000000 +#define GRBM_PWR_CNTL__RSP_TYPE_MASK 0x000000f0L +#define GRBM_PWR_CNTL__RSP_TYPE__SHIFT 0x00000004 +#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x00080000L +#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x00000013 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x00100000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x00000014 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x00200000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x00000015 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x00400000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x00000016 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x00800000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x00000017 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x01000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x00000018 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x02000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x00000019 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x04000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x0000001a +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x08000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x0000001b +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x0000001c +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x0000001d +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x0000001e +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x0000001f +#define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x00040000L +#define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x00000012 +#define GRBM_READ_ERROR2__READ_REQUESTER_SRBM_MASK 0x00020000L +#define GRBM_READ_ERROR2__READ_REQUESTER_SRBM__SHIFT 0x00000011 +#define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x0003fffcL +#define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x00000002 +#define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000L +#define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x0000001f +#define GRBM_READ_ERROR__READ_MEID_MASK 0x00c00000L +#define GRBM_READ_ERROR__READ_MEID__SHIFT 0x00000016 +#define GRBM_READ_ERROR__READ_PIPEID_MASK 0x00300000L +#define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x00000014 +#define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffffL +#define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x00000000 +#define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffffL +#define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x00000000 +#define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffffL +#define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x00000000 +#define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffffL +#define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x00000000 +#define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffffL +#define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x00000000 +#define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffffL +#define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x00000000 +#define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffffL +#define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x00000000 +#define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffffL +#define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x00000000 +#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x00000015 +#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L +#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000012 +#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000b +#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L +#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000011 +#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000a +#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x00000014 +#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003fL +#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x00000000 +#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L +#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x00000010 +#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L +#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000f +#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000d +#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L +#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000c +#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L +#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x00000013 +#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x00000015 +#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L +#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000012 +#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000b +#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L +#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000011 +#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000a +#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x00000014 +#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003fL +#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x00000000 +#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L +#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x00000010 +#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L +#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000f +#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000d +#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L +#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000c +#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L +#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x00000013 +#define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0x00000fc0L +#define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x00000006 +#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x0000003fL +#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x00000000 +#define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x00040000L +#define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x00000012 +#define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x00020000L +#define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x00000011 +#define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x00080000L +#define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x00000013 +#define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x00000001L +#define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x00000000 +#define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x00010000L +#define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x00000010 +#define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x00000004L +#define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x00000002 +#define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000L +#define GRBM_STATUS2__CPC_BUSY__SHIFT 0x0000001d +#define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000L +#define GRBM_STATUS2__CPF_BUSY__SHIFT 0x0000001c +#define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000L +#define GRBM_STATUS2__CPG_BUSY__SHIFT 0x0000001e +#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x00000010L +#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x00000004 +#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000fL +#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x00000000 +#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x00000020L +#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x00000005 +#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x00000040L +#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x00000006 +#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x00000080L +#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x00000007 +#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x00000100L +#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x00000008 +#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x00000200L +#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x00000009 +#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x00000400L +#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0x0000000a +#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x00000800L +#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0x0000000b +#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x00001000L +#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0x0000000c +#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x00002000L +#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0x0000000d +#define GRBM_STATUS2__RLC_BUSY_MASK 0x00000100L +#define GRBM_STATUS2__RLC_BUSY__SHIFT 0x00000008 +#define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x00000001L +#define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0x00000000 +#define GRBM_STATUS2__TC_BUSY_MASK 0x00000200L +#define GRBM_STATUS2__TC_BUSY__SHIFT 0x00000009 +#define GRBM_STATUS__BCI_BUSY_MASK 0x00800000L +#define GRBM_STATUS__BCI_BUSY__SHIFT 0x00000017 +#define GRBM_STATUS__CB_BUSY_MASK 0x40000000L +#define GRBM_STATUS__CB_BUSY__SHIFT 0x0000001e +#define GRBM_STATUS__CB_CLEAN_MASK 0x00002000L +#define GRBM_STATUS__CB_CLEAN__SHIFT 0x0000000d +#define GRBM_STATUS__CP_BUSY_MASK 0x20000000L +#define GRBM_STATUS__CP_BUSY__SHIFT 0x0000001d +#define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000L +#define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x0000001c +#define GRBM_STATUS__DB_BUSY_MASK 0x04000000L +#define GRBM_STATUS__DB_BUSY__SHIFT 0x0000001a +#define GRBM_STATUS__DB_CLEAN_MASK 0x00001000L +#define GRBM_STATUS__DB_CLEAN__SHIFT 0x0000000c +#define GRBM_STATUS__GDS_BUSY_MASK 0x00008000L +#define GRBM_STATUS__GDS_BUSY__SHIFT 0x0000000f +#define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x00000200L +#define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x00000009 +#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000L +#define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x0000001f +#define GRBM_STATUS__IA_BUSY_MASK 0x00080000L +#define GRBM_STATUS__IA_BUSY_NO_DMA_MASK 0x00040000L +#define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT 0x00000012 +#define GRBM_STATUS__IA_BUSY__SHIFT 0x00000013 +#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x00000080L +#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x00000007 +#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000fL +#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x00000000 +#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x00000100L +#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x00000008 +#define GRBM_STATUS__PA_BUSY_MASK 0x02000000L +#define GRBM_STATUS__PA_BUSY__SHIFT 0x00000019 +#define GRBM_STATUS__SC_BUSY_MASK 0x01000000L +#define GRBM_STATUS__SC_BUSY__SHIFT 0x00000018 +#define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x00400000L +#define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x00000016 +#define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000L +#define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x0000001f +#define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x00000004L +#define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x00000002 +#define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000L +#define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x0000001e +#define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x00000002L +#define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x00000001 +#define GRBM_STATUS_SE0__PA_BUSY_MASK 0x01000000L +#define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x00000018 +#define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000L +#define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x0000001d +#define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x08000000L +#define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x0000001b +#define GRBM_STATUS_SE0__SX_BUSY_MASK 0x04000000L +#define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x0000001a +#define GRBM_STATUS_SE0__TA_BUSY_MASK 0x02000000L +#define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x00000019 +#define GRBM_STATUS_SE0__VGT_BUSY_MASK 0x00800000L +#define GRBM_STATUS_SE0__VGT_BUSY__SHIFT 0x00000017 +#define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x00400000L +#define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x00000016 +#define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000L +#define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x0000001f +#define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x00000004L +#define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x00000002 +#define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000L +#define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x0000001e +#define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x00000002L +#define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x00000001 +#define GRBM_STATUS_SE1__PA_BUSY_MASK 0x01000000L +#define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x00000018 +#define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000L +#define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x0000001d +#define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x08000000L +#define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x0000001b +#define GRBM_STATUS_SE1__SX_BUSY_MASK 0x04000000L +#define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x0000001a +#define GRBM_STATUS_SE1__TA_BUSY_MASK 0x02000000L +#define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x00000019 +#define GRBM_STATUS_SE1__VGT_BUSY_MASK 0x00800000L +#define GRBM_STATUS_SE1__VGT_BUSY__SHIFT 0x00000017 +#define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x00400000L +#define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x00000016 +#define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000L +#define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x0000001f +#define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x00000004L +#define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x00000002 +#define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000L +#define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x0000001e +#define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x00000002L +#define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x00000001 +#define GRBM_STATUS_SE2__PA_BUSY_MASK 0x01000000L +#define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x00000018 +#define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000L +#define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x0000001d +#define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x08000000L +#define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x0000001b +#define GRBM_STATUS_SE2__SX_BUSY_MASK 0x04000000L +#define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x0000001a +#define GRBM_STATUS_SE2__TA_BUSY_MASK 0x02000000L +#define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x00000019 +#define GRBM_STATUS_SE2__VGT_BUSY_MASK 0x00800000L +#define GRBM_STATUS_SE2__VGT_BUSY__SHIFT 0x00000017 +#define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x00400000L +#define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x00000016 +#define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000L +#define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x0000001f +#define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x00000004L +#define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x00000002 +#define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000L +#define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x0000001e +#define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x00000002L +#define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x00000001 +#define GRBM_STATUS_SE3__PA_BUSY_MASK 0x01000000L +#define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x00000018 +#define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000L +#define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x0000001d +#define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x08000000L +#define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x0000001b +#define GRBM_STATUS_SE3__SX_BUSY_MASK 0x04000000L +#define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x0000001a +#define GRBM_STATUS_SE3__TA_BUSY_MASK 0x02000000L +#define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x00000019 +#define GRBM_STATUS_SE3__VGT_BUSY_MASK 0x00800000L +#define GRBM_STATUS_SE3__VGT_BUSY__SHIFT 0x00000017 +#define GRBM_STATUS__SPI_BUSY_MASK 0x00400000L +#define GRBM_STATUS__SPI_BUSY__SHIFT 0x00000016 +#define GRBM_STATUS__SRBM_RQ_PENDING_MASK 0x00000020L +#define GRBM_STATUS__SRBM_RQ_PENDING__SHIFT 0x00000005 +#define GRBM_STATUS__SX_BUSY_MASK 0x00100000L +#define GRBM_STATUS__SX_BUSY__SHIFT 0x00000014 +#define GRBM_STATUS__TA_BUSY_MASK 0x00004000L +#define GRBM_STATUS__TA_BUSY__SHIFT 0x0000000e +#define GRBM_STATUS__VGT_BUSY_MASK 0x00020000L +#define GRBM_STATUS__VGT_BUSY__SHIFT 0x00000011 +#define GRBM_STATUS__WD_BUSY_MASK 0x00200000L +#define GRBM_STATUS__WD_BUSY_NO_DMA_MASK 0x00010000L +#define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT 0x00000010 +#define GRBM_STATUS__WD_BUSY__SHIFT 0x00000015 +#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0x000000ffL +#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x00000000 +#define IA_CNTL_STATUS__IA_ADC_BUSY_MASK 0x00000010L +#define IA_CNTL_STATUS__IA_ADC_BUSY__SHIFT 0x00000004 +#define IA_CNTL_STATUS__IA_BUSY_MASK 0x00000001L +#define IA_CNTL_STATUS__IA_BUSY__SHIFT 0x00000000 +#define IA_CNTL_STATUS__IA_DMA_BUSY_MASK 0x00000002L +#define IA_CNTL_STATUS__IA_DMA_BUSY__SHIFT 0x00000001 +#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY_MASK 0x00000004L +#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY__SHIFT 0x00000002 +#define IA_CNTL_STATUS__IA_GRP_BUSY_MASK 0x00000008L +#define IA_CNTL_STATUS__IA_GRP_BUSY__SHIFT 0x00000003 +#define IA_DEBUG_CNTL__IA_DEBUG_INDX_MASK 0x0000003fL +#define IA_DEBUG_CNTL__IA_DEBUG_INDX__SHIFT 0x00000000 +#define IA_DEBUG_CNTL__IA_DEBUG_SEL_BUS_B_MASK 0x00000040L +#define IA_DEBUG_CNTL__IA_DEBUG_SEL_BUS_B__SHIFT 0x00000006 +#define IA_DEBUG_DATA__DATA_MASK 0xffffffffL +#define IA_DEBUG_DATA__DATA__SHIFT 0x00000000 +#define IA_DEBUG_REG0__core_clk_busy_MASK 0x04000000L +#define IA_DEBUG_REG0__core_clk_busy__SHIFT 0x0000001a +#define IA_DEBUG_REG0__dma_busy_MASK 0x00000040L +#define IA_DEBUG_REG0__dma_busy__SHIFT 0x00000006 +#define IA_DEBUG_REG0__dma_grp_hp_valid_MASK 0x00001000L +#define IA_DEBUG_REG0__dma_grp_hp_valid__SHIFT 0x0000000c +#define IA_DEBUG_REG0__dma_grp_valid_MASK 0x00000400L +#define IA_DEBUG_REG0__dma_grp_valid__SHIFT 0x0000000a +#define IA_DEBUG_REG0__dma_req_busy_MASK 0x00000020L +#define IA_DEBUG_REG0__dma_req_busy__SHIFT 0x00000005 +#define IA_DEBUG_REG0__grp_busy_MASK 0x00000100L +#define IA_DEBUG_REG0__grp_busy__SHIFT 0x00000008 +#define IA_DEBUG_REG0__grp_dma_hp_read_MASK 0x00002000L +#define IA_DEBUG_REG0__grp_dma_hp_read__SHIFT 0x0000000d +#define IA_DEBUG_REG0__grp_dma_read_MASK 0x00000800L +#define IA_DEBUG_REG0__grp_dma_read__SHIFT 0x0000000b +#define IA_DEBUG_REG0__ia_busy_extended_MASK 0x00000001L +#define IA_DEBUG_REG0__ia_busy_extended__SHIFT 0x00000000 +#define IA_DEBUG_REG0__ia_busy_MASK 0x00000004L +#define IA_DEBUG_REG0__ia_busy__SHIFT 0x00000002 +#define IA_DEBUG_REG0__ia_nodma_busy_extended_MASK 0x00000002L +#define IA_DEBUG_REG0__ia_nodma_busy_extended__SHIFT 0x00000001 +#define IA_DEBUG_REG0__ia_nodma_busy_MASK 0x00000008L +#define IA_DEBUG_REG0__ia_nodma_busy__SHIFT 0x00000003 +#define IA_DEBUG_REG0__mc_xl8r_busy_MASK 0x00000080L +#define IA_DEBUG_REG0__mc_xl8r_busy__SHIFT 0x00000007 +#define IA_DEBUG_REG0__reg_clk_busy_MASK 0x01000000L +#define IA_DEBUG_REG0__reg_clk_busy__SHIFT 0x00000018 +#define IA_DEBUG_REG0__sclk_core_vld_MASK 0x20000000L +#define IA_DEBUG_REG0__sclk_core_vld__SHIFT 0x0000001d +#define IA_DEBUG_REG0__sclk_reg_vld_MASK 0x10000000L +#define IA_DEBUG_REG0__sclk_reg_vld__SHIFT 0x0000001c +#define IA_DEBUG_REG0__SPARE0_MASK 0x00000010L +#define IA_DEBUG_REG0__SPARE0__SHIFT 0x00000004 +#define IA_DEBUG_REG0__SPARE1_MASK 0x00000200L +#define IA_DEBUG_REG0__SPARE1__SHIFT 0x00000009 +#define IA_DEBUG_REG0__SPARE2_MASK 0x00ffc000L +#define IA_DEBUG_REG0__SPARE2__SHIFT 0x0000000e +#define IA_DEBUG_REG0__SPARE3_MASK 0x00100000L +#define IA_DEBUG_REG0__SPARE3__SHIFT 0x00000014 +#define IA_DEBUG_REG0__SPARE4_MASK 0x08000000L +#define IA_DEBUG_REG0__SPARE4__SHIFT 0x0000001b +#define IA_DEBUG_REG0__SPARE5_MASK 0x40000000L +#define IA_DEBUG_REG0__SPARE5__SHIFT 0x0000001e +#define IA_DEBUG_REG0__SPARE6_MASK 0x80000000L +#define IA_DEBUG_REG0__SPARE6__SHIFT 0x0000001f +#define IA_DEBUG_REG1__current_data_valid_MASK 0x10000000L +#define IA_DEBUG_REG1__current_data_valid__SHIFT 0x0000001c +#define IA_DEBUG_REG1__discard_1st_chunk_MASK 0x00000100L +#define IA_DEBUG_REG1__discard_1st_chunk__SHIFT 0x00000008 +#define IA_DEBUG_REG1__discard_2nd_chunk_MASK 0x00000200L +#define IA_DEBUG_REG1__discard_2nd_chunk__SHIFT 0x00000009 +#define IA_DEBUG_REG1__dma_buf_type_q_MASK 0x00000060L +#define IA_DEBUG_REG1__dma_buf_type_q__SHIFT 0x00000005 +#define IA_DEBUG_REG1__dma_data_fifo_empty_q_MASK 0x00004000L +#define IA_DEBUG_REG1__dma_data_fifo_empty_q__SHIFT 0x0000000e +#define IA_DEBUG_REG1__dma_data_fifo_full_MASK 0x00008000L +#define IA_DEBUG_REG1__dma_data_fifo_full__SHIFT 0x0000000f +#define IA_DEBUG_REG1__dma_grp_valid_MASK 0x04000000L +#define IA_DEBUG_REG1__dma_grp_valid__SHIFT 0x0000001a +#define IA_DEBUG_REG1__dma_input_fifo_empty_MASK 0x00000001L +#define IA_DEBUG_REG1__dma_input_fifo_empty__SHIFT 0x00000000 +#define IA_DEBUG_REG1__dma_input_fifo_full_MASK 0x00000002L +#define IA_DEBUG_REG1__dma_input_fifo_full__SHIFT 0x00000001 +#define IA_DEBUG_REG1__dma_mask_fifo_empty_MASK 0x00002000L +#define IA_DEBUG_REG1__dma_mask_fifo_empty__SHIFT 0x0000000d +#define IA_DEBUG_REG1__dma_mask_fifo_we_MASK 0x40000000L +#define IA_DEBUG_REG1__dma_mask_fifo_we__SHIFT 0x0000001e +#define IA_DEBUG_REG1__dma_rdreq_dr_q_MASK 0x00000008L +#define IA_DEBUG_REG1__dma_rdreq_dr_q__SHIFT 0x00000003 +#define IA_DEBUG_REG1__dma_req_fifo_empty_MASK 0x00010000L +#define IA_DEBUG_REG1__dma_req_fifo_empty__SHIFT 0x00000010 +#define IA_DEBUG_REG1__dma_req_fifo_full_MASK 0x00020000L +#define IA_DEBUG_REG1__dma_req_fifo_full__SHIFT 0x00000011 +#define IA_DEBUG_REG1__dma_req_path_q_MASK 0x00000080L +#define IA_DEBUG_REG1__dma_req_path_q__SHIFT 0x00000007 +#define IA_DEBUG_REG1__dma_ret_data_we_q_MASK 0x80000000L +#define IA_DEBUG_REG1__dma_ret_data_we_q__SHIFT 0x0000001f +#define IA_DEBUG_REG1__dma_skid_fifo_empty_MASK 0x01000000L +#define IA_DEBUG_REG1__dma_skid_fifo_empty__SHIFT 0x00000018 +#define IA_DEBUG_REG1__dma_skid_fifo_full_MASK 0x02000000L +#define IA_DEBUG_REG1__dma_skid_fifo_full__SHIFT 0x00000019 +#define IA_DEBUG_REG1__dma_tc_ret_sel_q_MASK 0x00000800L +#define IA_DEBUG_REG1__dma_tc_ret_sel_q__SHIFT 0x0000000b +#define IA_DEBUG_REG1__dma_zero_indices_q_MASK 0x00000010L +#define IA_DEBUG_REG1__dma_zero_indices_q__SHIFT 0x00000004 +#define IA_DEBUG_REG1__grp_dma_read_MASK 0x08000000L +#define IA_DEBUG_REG1__grp_dma_read__SHIFT 0x0000001b +#define IA_DEBUG_REG1__last_rdreq_in_dma_op_MASK 0x00001000L +#define IA_DEBUG_REG1__last_rdreq_in_dma_op__SHIFT 0x0000000c +#define IA_DEBUG_REG1__out_of_range_r2_q_MASK 0x20000000L +#define IA_DEBUG_REG1__out_of_range_r2_q__SHIFT 0x0000001d +#define IA_DEBUG_REG1__second_tc_ret_data_q_MASK 0x00000400L +#define IA_DEBUG_REG1__second_tc_ret_data_q__SHIFT 0x0000000a +#define IA_DEBUG_REG1__stage2_dr_MASK 0x00040000L +#define IA_DEBUG_REG1__stage2_dr__SHIFT 0x00000012 +#define IA_DEBUG_REG1__stage2_rtr_MASK 0x00080000L +#define IA_DEBUG_REG1__stage2_rtr__SHIFT 0x00000013 +#define IA_DEBUG_REG1__stage3_dr_MASK 0x00100000L +#define IA_DEBUG_REG1__stage3_dr__SHIFT 0x00000014 +#define IA_DEBUG_REG1__stage3_rtr_MASK 0x00200000L +#define IA_DEBUG_REG1__stage3_rtr__SHIFT 0x00000015 +#define IA_DEBUG_REG1__stage4_dr_MASK 0x00400000L +#define IA_DEBUG_REG1__stage4_dr__SHIFT 0x00000016 +#define IA_DEBUG_REG1__stage4_rtr_MASK 0x00800000L +#define IA_DEBUG_REG1__stage4_rtr__SHIFT 0x00000017 +#define IA_DEBUG_REG1__start_new_packet_MASK 0x00000004L +#define IA_DEBUG_REG1__start_new_packet__SHIFT 0x00000002 +#define IA_DEBUG_REG2__hp_current_data_valid_MASK 0x10000000L +#define IA_DEBUG_REG2__hp_current_data_valid__SHIFT 0x0000001c +#define IA_DEBUG_REG2__hp_discard_1st_chunk_MASK 0x00000100L +#define IA_DEBUG_REG2__hp_discard_1st_chunk__SHIFT 0x00000008 +#define IA_DEBUG_REG2__hp_discard_2nd_chunk_MASK 0x00000200L +#define IA_DEBUG_REG2__hp_discard_2nd_chunk__SHIFT 0x00000009 +#define IA_DEBUG_REG2__hp_dma_buf_type_q_MASK 0x00000060L +#define IA_DEBUG_REG2__hp_dma_buf_type_q__SHIFT 0x00000005 +#define IA_DEBUG_REG2__hp_dma_data_fifo_empty_q_MASK 0x00004000L +#define IA_DEBUG_REG2__hp_dma_data_fifo_empty_q__SHIFT 0x0000000e +#define IA_DEBUG_REG2__hp_dma_data_fifo_full_MASK 0x00008000L +#define IA_DEBUG_REG2__hp_dma_data_fifo_full__SHIFT 0x0000000f +#define IA_DEBUG_REG2__hp_dma_grp_valid_MASK 0x04000000L +#define IA_DEBUG_REG2__hp_dma_grp_valid__SHIFT 0x0000001a +#define IA_DEBUG_REG2__hp_dma_input_fifo_empty_MASK 0x00000001L +#define IA_DEBUG_REG2__hp_dma_input_fifo_empty__SHIFT 0x00000000 +#define IA_DEBUG_REG2__hp_dma_input_fifo_full_MASK 0x00000002L +#define IA_DEBUG_REG2__hp_dma_input_fifo_full__SHIFT 0x00000001 +#define IA_DEBUG_REG2__hp_dma_mask_fifo_empty_MASK 0x00002000L +#define IA_DEBUG_REG2__hp_dma_mask_fifo_empty__SHIFT 0x0000000d +#define IA_DEBUG_REG2__hp_dma_mask_fifo_we_MASK 0x40000000L +#define IA_DEBUG_REG2__hp_dma_mask_fifo_we__SHIFT 0x0000001e +#define IA_DEBUG_REG2__hp_dma_rdreq_dr_q_MASK 0x00000008L +#define IA_DEBUG_REG2__hp_dma_rdreq_dr_q__SHIFT 0x00000003 +#define IA_DEBUG_REG2__hp_dma_req_fifo_empty_MASK 0x00010000L +#define IA_DEBUG_REG2__hp_dma_req_fifo_empty__SHIFT 0x00000010 +#define IA_DEBUG_REG2__hp_dma_req_fifo_full_MASK 0x00020000L +#define IA_DEBUG_REG2__hp_dma_req_fifo_full__SHIFT 0x00000011 +#define IA_DEBUG_REG2__hp_dma_req_path_q_MASK 0x00000080L +#define IA_DEBUG_REG2__hp_dma_req_path_q__SHIFT 0x00000007 +#define IA_DEBUG_REG2__hp_dma_ret_data_we_q_MASK 0x80000000L +#define IA_DEBUG_REG2__hp_dma_ret_data_we_q__SHIFT 0x0000001f +#define IA_DEBUG_REG2__hp_dma_skid_fifo_empty_MASK 0x01000000L +#define IA_DEBUG_REG2__hp_dma_skid_fifo_empty__SHIFT 0x00000018 +#define IA_DEBUG_REG2__hp_dma_skid_fifo_full_MASK 0x02000000L +#define IA_DEBUG_REG2__hp_dma_skid_fifo_full__SHIFT 0x00000019 +#define IA_DEBUG_REG2__hp_dma_tc_ret_sel_q_MASK 0x00000800L +#define IA_DEBUG_REG2__hp_dma_tc_ret_sel_q__SHIFT 0x0000000b +#define IA_DEBUG_REG2__hp_dma_zero_indices_q_MASK 0x00000010L +#define IA_DEBUG_REG2__hp_dma_zero_indices_q__SHIFT 0x00000004 +#define IA_DEBUG_REG2__hp_grp_dma_read_MASK 0x08000000L +#define IA_DEBUG_REG2__hp_grp_dma_read__SHIFT 0x0000001b +#define IA_DEBUG_REG2__hp_last_rdreq_in_dma_op_MASK 0x00001000L +#define IA_DEBUG_REG2__hp_last_rdreq_in_dma_op__SHIFT 0x0000000c +#define IA_DEBUG_REG2__hp_out_of_range_r2_q_MASK 0x20000000L +#define IA_DEBUG_REG2__hp_out_of_range_r2_q__SHIFT 0x0000001d +#define IA_DEBUG_REG2__hp_second_tc_ret_data_q_MASK 0x00000400L +#define IA_DEBUG_REG2__hp_second_tc_ret_data_q__SHIFT 0x0000000a +#define IA_DEBUG_REG2__hp_stage2_dr_MASK 0x00040000L +#define IA_DEBUG_REG2__hp_stage2_dr__SHIFT 0x00000012 +#define IA_DEBUG_REG2__hp_stage2_rtr_MASK 0x00080000L +#define IA_DEBUG_REG2__hp_stage2_rtr__SHIFT 0x00000013 +#define IA_DEBUG_REG2__hp_stage3_dr_MASK 0x00100000L +#define IA_DEBUG_REG2__hp_stage3_dr__SHIFT 0x00000014 +#define IA_DEBUG_REG2__hp_stage3_rtr_MASK 0x00200000L +#define IA_DEBUG_REG2__hp_stage3_rtr__SHIFT 0x00000015 +#define IA_DEBUG_REG2__hp_stage4_dr_MASK 0x00400000L +#define IA_DEBUG_REG2__hp_stage4_dr__SHIFT 0x00000016 +#define IA_DEBUG_REG2__hp_stage4_rtr_MASK 0x00800000L +#define IA_DEBUG_REG2__hp_stage4_rtr__SHIFT 0x00000017 +#define IA_DEBUG_REG2__hp_start_new_packet_MASK 0x00000004L +#define IA_DEBUG_REG2__hp_start_new_packet__SHIFT 0x00000002 +#define IA_DEBUG_REG3__discard_1st_chunk_MASK 0x04000000L +#define IA_DEBUG_REG3__discard_1st_chunk__SHIFT 0x0000001a +#define IA_DEBUG_REG3__discard_2nd_chunk_MASK 0x08000000L +#define IA_DEBUG_REG3__discard_2nd_chunk__SHIFT 0x0000001b +#define IA_DEBUG_REG3__dma_pipe0_rdreq_eop_out_MASK 0x00000008L +#define IA_DEBUG_REG3__dma_pipe0_rdreq_eop_out__SHIFT 0x00000003 +#define IA_DEBUG_REG3__dma_pipe0_rdreq_null_out_MASK 0x00000004L +#define IA_DEBUG_REG3__dma_pipe0_rdreq_null_out__SHIFT 0x00000002 +#define IA_DEBUG_REG3__dma_pipe0_rdreq_read_MASK 0x00000002L +#define IA_DEBUG_REG3__dma_pipe0_rdreq_read__SHIFT 0x00000001 +#define IA_DEBUG_REG3__dma_pipe0_rdreq_use_tc_out_MASK 0x00000010L +#define IA_DEBUG_REG3__dma_pipe0_rdreq_use_tc_out__SHIFT 0x00000004 +#define IA_DEBUG_REG3__dma_pipe0_rdreq_valid_MASK 0x00000001L +#define IA_DEBUG_REG3__dma_pipe0_rdreq_valid__SHIFT 0x00000000 +#define IA_DEBUG_REG3__dma_pipe1_rdreq_eop_out_MASK 0x00000800L +#define IA_DEBUG_REG3__dma_pipe1_rdreq_eop_out__SHIFT 0x0000000b +#define IA_DEBUG_REG3__dma_pipe1_rdreq_null_out_MASK 0x00000400L +#define IA_DEBUG_REG3__dma_pipe1_rdreq_null_out__SHIFT 0x0000000a +#define IA_DEBUG_REG3__dma_pipe1_rdreq_read_MASK 0x00000200L +#define IA_DEBUG_REG3__dma_pipe1_rdreq_read__SHIFT 0x00000009 +#define IA_DEBUG_REG3__dma_pipe1_rdreq_use_tc_out_MASK 0x00001000L +#define IA_DEBUG_REG3__dma_pipe1_rdreq_use_tc_out__SHIFT 0x0000000c +#define IA_DEBUG_REG3__dma_pipe1_rdreq_valid_MASK 0x00000100L +#define IA_DEBUG_REG3__dma_pipe1_rdreq_valid__SHIFT 0x00000008 +#define IA_DEBUG_REG3__dma_rdreq_send_out_MASK 0x00008000L +#define IA_DEBUG_REG3__dma_rdreq_send_out__SHIFT 0x0000000f +#define IA_DEBUG_REG3__grp_dma_draw_is_pipe0_MASK 0x00000020L +#define IA_DEBUG_REG3__grp_dma_draw_is_pipe0__SHIFT 0x00000005 +#define IA_DEBUG_REG3__ia_mc_rdreq_rtr_q_MASK 0x00002000L +#define IA_DEBUG_REG3__ia_mc_rdreq_rtr_q__SHIFT 0x0000000d +#define IA_DEBUG_REG3__ia_tc_rdreq_rtr_q_MASK 0x00040000L +#define IA_DEBUG_REG3__ia_tc_rdreq_rtr_q__SHIFT 0x00000012 +#define IA_DEBUG_REG3__IA_TC_rdreq_send_out_MASK 0x20000000L +#define IA_DEBUG_REG3__IA_TC_rdreq_send_out__SHIFT 0x0000001d +#define IA_DEBUG_REG3__last_tc_req_p1_MASK 0x10000000L +#define IA_DEBUG_REG3__last_tc_req_p1__SHIFT 0x0000001c +#define IA_DEBUG_REG3__mc_out_rtr_MASK 0x00004000L +#define IA_DEBUG_REG3__mc_out_rtr__SHIFT 0x0000000e +#define IA_DEBUG_REG3__must_service_pipe0_req_MASK 0x00000040L +#define IA_DEBUG_REG3__must_service_pipe0_req__SHIFT 0x00000006 +#define IA_DEBUG_REG3__pair0_valid_p1_MASK 0x00100000L +#define IA_DEBUG_REG3__pair0_valid_p1__SHIFT 0x00000014 +#define IA_DEBUG_REG3__pair1_valid_p1_MASK 0x00200000L +#define IA_DEBUG_REG3__pair1_valid_p1__SHIFT 0x00000015 +#define IA_DEBUG_REG3__pair2_valid_p1_MASK 0x00400000L +#define IA_DEBUG_REG3__pair2_valid_p1__SHIFT 0x00000016 +#define IA_DEBUG_REG3__pair3_valid_p1_MASK 0x00800000L +#define IA_DEBUG_REG3__pair3_valid_p1__SHIFT 0x00000017 +#define IA_DEBUG_REG3__pipe0_dr_MASK 0x00010000L +#define IA_DEBUG_REG3__pipe0_dr__SHIFT 0x00000010 +#define IA_DEBUG_REG3__pipe0_rtr_MASK 0x00020000L +#define IA_DEBUG_REG3__pipe0_rtr__SHIFT 0x00000011 +#define IA_DEBUG_REG3__send_pipe1_req_MASK 0x00000080L +#define IA_DEBUG_REG3__send_pipe1_req__SHIFT 0x00000007 +#define IA_DEBUG_REG3__TAP_IA_rdret_vld_in_MASK 0x80000000L +#define IA_DEBUG_REG3__TAP_IA_rdret_vld_in__SHIFT 0x0000001f +#define IA_DEBUG_REG3__TC_IA_rdret_valid_in_MASK 0x40000000L +#define IA_DEBUG_REG3__TC_IA_rdret_valid_in__SHIFT 0x0000001e +#define IA_DEBUG_REG3__tc_out_rtr_MASK 0x00080000L +#define IA_DEBUG_REG3__tc_out_rtr__SHIFT 0x00000013 +#define IA_DEBUG_REG3__tc_req_count_q_MASK 0x03000000L +#define IA_DEBUG_REG3__tc_req_count_q__SHIFT 0x00000018 +#define IA_DEBUG_REG4__current_shift_is_vect1_q_MASK 0x80000000L +#define IA_DEBUG_REG4__current_shift_is_vect1_q__SHIFT 0x0000001f +#define IA_DEBUG_REG4__di_event_flag_p1_q_MASK 0x00100000L +#define IA_DEBUG_REG4__di_event_flag_p1_q__SHIFT 0x00000014 +#define IA_DEBUG_REG4__di_first_group_of_draw_q_MASK 0x20000000L +#define IA_DEBUG_REG4__di_first_group_of_draw_q__SHIFT 0x0000001d +#define IA_DEBUG_REG4__di_major_mode_p1_q_MASK 0x00010000L +#define IA_DEBUG_REG4__di_major_mode_p1_q__SHIFT 0x00000010 +#define IA_DEBUG_REG4__di_source_select_p1_q_MASK 0x0c000000L +#define IA_DEBUG_REG4__di_source_select_p1_q__SHIFT 0x0000001a +#define IA_DEBUG_REG4__di_state_sel_p1_q_MASK 0x00e00000L +#define IA_DEBUG_REG4__di_state_sel_p1_q__SHIFT 0x00000015 +#define IA_DEBUG_REG4__draw_opaq_active_q_MASK 0x02000000L +#define IA_DEBUG_REG4__draw_opaq_active_q__SHIFT 0x00000019 +#define IA_DEBUG_REG4__draw_opaq_en_p1_q_MASK 0x01000000L +#define IA_DEBUG_REG4__draw_opaq_en_p1_q__SHIFT 0x00000018 +#define IA_DEBUG_REG4__grp_se0_fifo_empty_MASK 0x00000040L +#define IA_DEBUG_REG4__grp_se0_fifo_empty__SHIFT 0x00000006 +#define IA_DEBUG_REG4__grp_se0_fifo_full_MASK 0x00000080L +#define IA_DEBUG_REG4__grp_se0_fifo_full__SHIFT 0x00000007 +#define IA_DEBUG_REG4__gs_mode_p1_q_MASK 0x000e0000L +#define IA_DEBUG_REG4__gs_mode_p1_q__SHIFT 0x00000011 +#define IA_DEBUG_REG4__ia_se1vgt_prim_rtr_q_MASK 0x00008000L +#define IA_DEBUG_REG4__ia_se1vgt_prim_rtr_q__SHIFT 0x0000000f +#define IA_DEBUG_REG4__ia_vgt_prim_rtr_q_MASK 0x00004000L +#define IA_DEBUG_REG4__ia_vgt_prim_rtr_q__SHIFT 0x0000000e +#define IA_DEBUG_REG4__last_shift_of_draw_MASK 0x40000000L +#define IA_DEBUG_REG4__last_shift_of_draw__SHIFT 0x0000001e +#define IA_DEBUG_REG4__pipe0_dr_MASK 0x00000001L +#define IA_DEBUG_REG4__pipe0_dr__SHIFT 0x00000000 +#define IA_DEBUG_REG4__pipe0_rtr_MASK 0x00000100L +#define IA_DEBUG_REG4__pipe0_rtr__SHIFT 0x00000008 +#define IA_DEBUG_REG4__pipe1_dr_MASK 0x00000002L +#define IA_DEBUG_REG4__pipe1_dr__SHIFT 0x00000001 +#define IA_DEBUG_REG4__pipe1_rtr_MASK 0x00000200L +#define IA_DEBUG_REG4__pipe1_rtr__SHIFT 0x00000009 +#define IA_DEBUG_REG4__pipe2_dr_MASK 0x00000004L +#define IA_DEBUG_REG4__pipe2_dr__SHIFT 0x00000002 +#define IA_DEBUG_REG4__pipe2_rtr_MASK 0x00000400L +#define IA_DEBUG_REG4__pipe2_rtr__SHIFT 0x0000000a +#define IA_DEBUG_REG4__pipe3_dr_MASK 0x00000008L +#define IA_DEBUG_REG4__pipe3_dr__SHIFT 0x00000003 +#define IA_DEBUG_REG4__pipe3_rtr_MASK 0x00000800L +#define IA_DEBUG_REG4__pipe3_rtr__SHIFT 0x0000000b +#define IA_DEBUG_REG4__pipe4_dr_MASK 0x00000010L +#define IA_DEBUG_REG4__pipe4_dr__SHIFT 0x00000004 +#define IA_DEBUG_REG4__pipe4_rtr_MASK 0x00001000L +#define IA_DEBUG_REG4__pipe4_rtr__SHIFT 0x0000000c +#define IA_DEBUG_REG4__pipe5_dr_MASK 0x00000020L +#define IA_DEBUG_REG4__pipe5_dr__SHIFT 0x00000005 +#define IA_DEBUG_REG4__pipe5_rtr_MASK 0x00002000L +#define IA_DEBUG_REG4__pipe5_rtr__SHIFT 0x0000000d +#define IA_DEBUG_REG4__ready_to_read_di_MASK 0x10000000L +#define IA_DEBUG_REG4__ready_to_read_di__SHIFT 0x0000001c +#define IA_DEBUG_REG5__di_index_counter_q_15_0_MASK 0x0000ffffL +#define IA_DEBUG_REG5__di_index_counter_q_15_0__SHIFT 0x00000000 +#define IA_DEBUG_REG5__draw_input_fifo_empty_MASK 0x80000000L +#define IA_DEBUG_REG5__draw_input_fifo_empty__SHIFT 0x0000001f +#define IA_DEBUG_REG5__draw_input_fifo_full_MASK 0x40000000L +#define IA_DEBUG_REG5__draw_input_fifo_full__SHIFT 0x0000001e +#define IA_DEBUG_REG5__instanceid_13_0_MASK 0x3fff0000L +#define IA_DEBUG_REG5__instanceid_13_0__SHIFT 0x00000010 +#define IA_DEBUG_REG6__after_group_partial_MASK 0x00400000L +#define IA_DEBUG_REG6__after_group_partial__SHIFT 0x00000016 +#define IA_DEBUG_REG6__current_shift_q_MASK 0x0000000fL +#define IA_DEBUG_REG6__current_shift_q__SHIFT 0x00000000 +#define IA_DEBUG_REG6__current_stride_pre_MASK 0x000000f0L +#define IA_DEBUG_REG6__current_stride_pre__SHIFT 0x00000004 +#define IA_DEBUG_REG6__current_stride_q_MASK 0x00001f00L +#define IA_DEBUG_REG6__current_stride_q__SHIFT 0x00000008 +#define IA_DEBUG_REG6__curr_prim_partial_MASK 0x00008000L +#define IA_DEBUG_REG6__curr_prim_partial__SHIFT 0x0000000f +#define IA_DEBUG_REG6__extract_group_MASK 0x00800000L +#define IA_DEBUG_REG6__extract_group__SHIFT 0x00000017 +#define IA_DEBUG_REG6__first_group_partial_MASK 0x00002000L +#define IA_DEBUG_REG6__first_group_partial__SHIFT 0x0000000d +#define IA_DEBUG_REG6__grp_shift_debug_data_MASK 0xff000000L +#define IA_DEBUG_REG6__grp_shift_debug_data__SHIFT 0x00000018 +#define IA_DEBUG_REG6__next_group_partial_MASK 0x00200000L +#define IA_DEBUG_REG6__next_group_partial__SHIFT 0x00000015 +#define IA_DEBUG_REG6__next_stride_q_MASK 0x001f0000L +#define IA_DEBUG_REG6__next_stride_q__SHIFT 0x00000010 +#define IA_DEBUG_REG6__second_group_partial_MASK 0x00004000L +#define IA_DEBUG_REG6__second_group_partial__SHIFT 0x0000000e +#define IA_DEBUG_REG7__indx_shift_is_one_p2_q_MASK 0x02000000L +#define IA_DEBUG_REG7__indx_shift_is_one_p2_q__SHIFT 0x00000019 +#define IA_DEBUG_REG7__indx_shift_is_two_p2_q_MASK 0x04000000L +#define IA_DEBUG_REG7__indx_shift_is_two_p2_q__SHIFT 0x0000001a +#define IA_DEBUG_REG7__indx_stride_is_four_p2_q_MASK 0x08000000L +#define IA_DEBUG_REG7__indx_stride_is_four_p2_q__SHIFT 0x0000001b +#define IA_DEBUG_REG7__last_group_of_draw_p2_q_MASK 0x00800000L +#define IA_DEBUG_REG7__last_group_of_draw_p2_q__SHIFT 0x00000017 +#define IA_DEBUG_REG7__num_indx_in_group_p2_q_MASK 0x00700000L +#define IA_DEBUG_REG7__num_indx_in_group_p2_q__SHIFT 0x00000014 +#define IA_DEBUG_REG7__reset_indx_state_q_MASK 0x0000000fL +#define IA_DEBUG_REG7__reset_indx_state_q__SHIFT 0x00000000 +#define IA_DEBUG_REG7__shift_event_flag_p2_q_MASK 0x01000000L +#define IA_DEBUG_REG7__shift_event_flag_p2_q__SHIFT 0x00000018 +#define IA_DEBUG_REG7__shift_prim0_partial_p3_q_MASK 0x80000000L +#define IA_DEBUG_REG7__shift_prim0_partial_p3_q__SHIFT 0x0000001f +#define IA_DEBUG_REG7__shift_prim0_reset_p3_q_MASK 0x40000000L +#define IA_DEBUG_REG7__shift_prim0_reset_p3_q__SHIFT 0x0000001e +#define IA_DEBUG_REG7__shift_prim1_partial_p3_q_MASK 0x20000000L +#define IA_DEBUG_REG7__shift_prim1_partial_p3_q__SHIFT 0x0000001d +#define IA_DEBUG_REG7__shift_prim1_reset_p3_q_MASK 0x10000000L +#define IA_DEBUG_REG7__shift_prim1_reset_p3_q__SHIFT 0x0000001c +#define IA_DEBUG_REG7__shift_vect0_reset_match_p2_q_MASK 0x0000f000L +#define IA_DEBUG_REG7__shift_vect0_reset_match_p2_q__SHIFT 0x0000000c +#define IA_DEBUG_REG7__shift_vect1_reset_match_p2_q_MASK 0x000f0000L +#define IA_DEBUG_REG7__shift_vect1_reset_match_p2_q__SHIFT 0x00000010 +#define IA_DEBUG_REG7__shift_vect1_valid_p2_q_MASK 0x00000f00L +#define IA_DEBUG_REG7__shift_vect1_valid_p2_q__SHIFT 0x00000008 +#define IA_DEBUG_REG7__shift_vect_valid_p2_q_MASK 0x000000f0L +#define IA_DEBUG_REG7__shift_vect_valid_p2_q__SHIFT 0x00000004 +#define IA_DEBUG_REG8__di_prim_type_p1_q_MASK 0x0000001fL +#define IA_DEBUG_REG8__di_prim_type_p1_q__SHIFT 0x00000000 +#define IA_DEBUG_REG8__grp_components_valid_MASK 0xf0000000L +#define IA_DEBUG_REG8__grp_components_valid__SHIFT 0x0000001c +#define IA_DEBUG_REG8__grp_continued_MASK 0x00000800L +#define IA_DEBUG_REG8__grp_continued__SHIFT 0x0000000b +#define IA_DEBUG_REG8__grp_eopg_MASK 0x04000000L +#define IA_DEBUG_REG8__grp_eopg__SHIFT 0x0000001a +#define IA_DEBUG_REG8__grp_eop_MASK 0x02000000L +#define IA_DEBUG_REG8__grp_eop__SHIFT 0x00000019 +#define IA_DEBUG_REG8__grp_event_flag_MASK 0x08000000L +#define IA_DEBUG_REG8__grp_event_flag__SHIFT 0x0000001b +#define IA_DEBUG_REG8__grp_null_primitive_MASK 0x01000000L +#define IA_DEBUG_REG8__grp_null_primitive__SHIFT 0x00000018 +#define IA_DEBUG_REG8__grp_output_path_MASK 0x00e00000L +#define IA_DEBUG_REG8__grp_output_path__SHIFT 0x00000015 +#define IA_DEBUG_REG8__grp_state_sel_MASK 0x00007000L +#define IA_DEBUG_REG8__grp_state_sel__SHIFT 0x0000000c +#define IA_DEBUG_REG8__grp_sub_prim_type_MASK 0x001f8000L +#define IA_DEBUG_REG8__grp_sub_prim_type__SHIFT 0x0000000f +#define IA_DEBUG_REG8__last_group_of_inst_p5_q_MASK 0x00000100L +#define IA_DEBUG_REG8__last_group_of_inst_p5_q__SHIFT 0x00000008 +#define IA_DEBUG_REG8__shift_prim0_null_flag_p5_q_MASK 0x00000400L +#define IA_DEBUG_REG8__shift_prim0_null_flag_p5_q__SHIFT 0x0000000a +#define IA_DEBUG_REG8__shift_prim1_null_flag_p5_q_MASK 0x00000200L +#define IA_DEBUG_REG8__shift_prim1_null_flag_p5_q__SHIFT 0x00000009 +#define IA_DEBUG_REG8__shift_vect_end_of_packet_p5_q_MASK 0x00000080L +#define IA_DEBUG_REG8__shift_vect_end_of_packet_p5_q__SHIFT 0x00000007 +#define IA_DEBUG_REG8__two_cycle_xfer_p1_q_MASK 0x00000020L +#define IA_DEBUG_REG8__two_cycle_xfer_p1_q__SHIFT 0x00000005 +#define IA_DEBUG_REG8__two_prim_input_p1_q_MASK 0x00000040L +#define IA_DEBUG_REG8__two_prim_input_p1_q__SHIFT 0x00000006 +#define IA_DEBUG_REG9__eopg_between_prims_p6_MASK 0x00000400L +#define IA_DEBUG_REG9__eopg_between_prims_p6__SHIFT 0x0000000a +#define IA_DEBUG_REG9__eopg_on_last_prim_p6_MASK 0x00000200L +#define IA_DEBUG_REG9__eopg_on_last_prim_p6__SHIFT 0x00000009 +#define IA_DEBUG_REG9__gfx_se_switch_p6_MASK 0x00000002L +#define IA_DEBUG_REG9__gfx_se_switch_p6__SHIFT 0x00000001 +#define IA_DEBUG_REG9__grp_se1_fifo_empty_MASK 0x00040000L +#define IA_DEBUG_REG9__grp_se1_fifo_empty__SHIFT 0x00000012 +#define IA_DEBUG_REG9__grp_se1_fifo_full_MASK 0x00080000L +#define IA_DEBUG_REG9__grp_se1_fifo_full__SHIFT 0x00000013 +#define IA_DEBUG_REG9__null_eoi_xfer_prim0_p6_MASK 0x00000008L +#define IA_DEBUG_REG9__null_eoi_xfer_prim0_p6__SHIFT 0x00000003 +#define IA_DEBUG_REG9__null_eoi_xfer_prim1_p6_MASK 0x00000004L +#define IA_DEBUG_REG9__null_eoi_xfer_prim1_p6__SHIFT 0x00000002 +#define IA_DEBUG_REG9__prim0_eoi_p6_MASK 0x00000020L +#define IA_DEBUG_REG9__prim0_eoi_p6__SHIFT 0x00000005 +#define IA_DEBUG_REG9__prim0_valid_eopg_p6_MASK 0x00000080L +#define IA_DEBUG_REG9__prim0_valid_eopg_p6__SHIFT 0x00000007 +#define IA_DEBUG_REG9__prim1_eoi_p6_MASK 0x00000010L +#define IA_DEBUG_REG9__prim1_eoi_p6__SHIFT 0x00000004 +#define IA_DEBUG_REG9__prim1_to_other_se_p6_MASK 0x00000100L +#define IA_DEBUG_REG9__prim1_to_other_se_p6__SHIFT 0x00000008 +#define IA_DEBUG_REG9__prim1_valid_eopg_p6_MASK 0x00000040L +#define IA_DEBUG_REG9__prim1_valid_eopg_p6__SHIFT 0x00000006 +#define IA_DEBUG_REG9__prim1_xfer_p6_MASK 0x00020000L +#define IA_DEBUG_REG9__prim1_xfer_p6__SHIFT 0x00000011 +#define IA_DEBUG_REG9__prim_count_eq_group_size_p6_MASK 0x00000800L +#define IA_DEBUG_REG9__prim_count_eq_group_size_p6__SHIFT 0x0000000b +#define IA_DEBUG_REG9__prim_counter_q_MASK 0xfffc0000L +#define IA_DEBUG_REG9__prim_counter_q__SHIFT 0x00000012 +#define IA_DEBUG_REG9__prim_count_gt_group_size_p6_MASK 0x00001000L +#define IA_DEBUG_REG9__prim_count_gt_group_size_p6__SHIFT 0x0000000c +#define IA_DEBUG_REG9__send_to_se1_p6_MASK 0x00000001L +#define IA_DEBUG_REG9__send_to_se1_p6__SHIFT 0x00000000 +#define IA_DEBUG_REG9__shift_vect_end_of_packet_p5_q_MASK 0x00010000L +#define IA_DEBUG_REG9__shift_vect_end_of_packet_p5_q__SHIFT 0x00000010 +#define IA_DEBUG_REG9__SPARE0_MASK 0x00004000L +#define IA_DEBUG_REG9__SPARE0__SHIFT 0x0000000e +#define IA_DEBUG_REG9__SPARE1_MASK 0x00008000L +#define IA_DEBUG_REG9__SPARE1__SHIFT 0x0000000f +#define IA_DEBUG_REG9__two_prim_output_p5_q_MASK 0x00002000L +#define IA_DEBUG_REG9__two_prim_output_p5_q__SHIFT 0x0000000d +#define IA_ENHANCE__MISC_MASK 0xffffffffL +#define IA_ENHANCE__MISC__SHIFT 0x00000000 +#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK 0x00040000L +#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT 0x00000012 +#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK 0x00010000L +#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT 0x00000010 +#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK 0x0000ffffL +#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT 0x00000000 +#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK 0x00080000L +#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT 0x00000013 +#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK 0x00020000L +#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT 0x00000011 +#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK 0x00100000L +#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT 0x00000014 +#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000L +#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x0000001c +#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0f000000L +#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x00000018 +#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003ffL +#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 +#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L +#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a +#define IA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L +#define IA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define IA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0f000000L +#define IA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x00000018 +#define IA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L +#define IA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c +#define IA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000ffc00L +#define IA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a +#define IA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL +#define IA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 +#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define IA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L +#define IA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c +#define IA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL +#define IA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 +#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define IA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000L +#define IA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x0000001c +#define IA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL +#define IA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 +#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define IA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000L +#define IA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x0000001c +#define IA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL +#define IA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 +#define IA_VMID_OVERRIDE__ENABLE_MASK 0x00000001L +#define IA_VMID_OVERRIDE__ENABLE__SHIFT 0x00000000 +#define IA_VMID_OVERRIDE__VMID_MASK 0x0000001eL +#define IA_VMID_OVERRIDE__VMID__SHIFT 0x00000001 +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000L +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x00000012 +#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x00010000L +#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x00000010 +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x00100000L +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x00000014 +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x00080000L +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x00000013 +#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK 0x01000000L +#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT 0x00000018 +#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK 0x00400000L +#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT 0x00000016 +#define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0x0000c000L +#define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT 0x0000000e +#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK 0x00002000L +#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT 0x0000000d +#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x00020000L +#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT 0x00000011 +#define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x00000001L +#define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x00000000 +#define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK 0x00000002L +#define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x00000001 +#define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x00000004L +#define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT 0x00000002 +#define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x00000008L +#define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x00000003 +#define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x00000010L +#define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x00000004 +#define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x00000020L +#define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x00000005 +#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK 0x02000000L +#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT 0x00000019 +#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x00200000L +#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x00000015 +#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK 0x08000000L +#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT 0x0000001b +#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK 0x04000000L +#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT 0x0000001a +#define PA_CL_CNTL_STATUS__CL_BUSY_MASK 0x80000000L +#define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT 0x0000001f +#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x00000008L +#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x00000003 +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x00000001L +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x00000000 +#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000L +#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x0000001f +#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000L +#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x0000001e +#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000L +#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x0000001d +#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000L +#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x0000001c +#define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x00000006L +#define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x00000001 +#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x00000010L +#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x00000004 +#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK 0x00000020L +#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT 0x00000005 +#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK 0x00004000L +#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT 0x0000000e +#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK 0x00002000L +#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT 0x0000000d +#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK 0x00001000L +#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT 0x0000000c +#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK 0x00000200L +#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT 0x00000009 +#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK 0x00000100L +#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT 0x00000008 +#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK 0x00000800L +#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT 0x0000000b +#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK 0x00000400L +#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0x0000000a +#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK 0x00000008L +#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT 0x00000003 +#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK 0x00100000L +#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT 0x00000014 +#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK 0x00000004L +#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x00000002 +#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK 0x00000040L +#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT 0x00000006 +#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK 0x00000080L +#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT 0x00000007 +#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK 0x00000001L +#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x00000000 +#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK 0x00000010L +#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT 0x00000004 +#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK 0x00000002L +#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x00000001 +#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK 0x00000020L +#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT 0x00000005 +#define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_POINT_SIZE__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_0_X__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_0_Y__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_0_Z__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_1_W__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_1_Y__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_2_X__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_2_Y__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_2_Z__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_3_X__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_3_Y__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_3_Z__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_4_W__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_4_X__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_4_Y__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_4_Z__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_5_W__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_5_Y__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_5_Z__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x00000000 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK 0x00000001L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT 0x00000000 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK 0x00000002L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT 0x00000001 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK 0x00000004L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT 0x00000002 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK 0x00000008L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT 0x00000003 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK 0x00000010L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT 0x00000004 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK 0x00000020L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT 0x00000005 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK 0x00000040L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT 0x00000006 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK 0x00000080L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT 0x00000007 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK 0x00000100L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT 0x00000008 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK 0x00000200L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT 0x00000009 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK 0x00000400L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0x0000000a +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK 0x00000800L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT 0x0000000b +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK 0x00001000L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT 0x0000000c +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK 0x00002000L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT 0x0000000d +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK 0x00004000L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT 0x0000000e +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK 0x00008000L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT 0x0000000f +#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK 0x00020000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT 0x00000011 +#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK 0x02000000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT 0x00000019 +#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK 0x00100000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT 0x00000014 +#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK 0x00010000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT 0x00000010 +#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK 0x00040000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT 0x00000012 +#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK 0x00080000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT 0x00000013 +#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK 0x00400000L +#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT 0x00000016 +#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK 0x00800000L +#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT 0x00000017 +#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK 0x01000000L +#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT 0x00000018 +#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK 0x00200000L +#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT 0x00000015 +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x00000800L +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0x0000000b +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x00000002L +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x00000001 +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x00000001L +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x00000000 +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x00000008L +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x00000003 +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x00000004L +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x00000002 +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x00000020L +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x00000005 +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x00000010L +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x00000004 +#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x00000400L +#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0x0000000a +#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100L +#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x00000008 +#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200L +#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x00000009 +#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK 0x00000010L +#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT 0x00000004 +#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK 0x03000000L +#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT 0x00000018 +#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x0001e000L +#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0x0000000d +#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK 0x00700000L +#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT 0x00000014 +#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x00000007L +#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x00000000 +#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK 0x0000ffffL +#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT 0x00000000 +#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK 0xffff0000L +#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT 0x00000010 +#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK 0x0000ffffL +#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT 0x00000000 +#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK 0xffff0000L +#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT 0x00000010 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK 0x0000000fL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT 0x00000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK 0x000000f0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT 0x00000004 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK 0x00000f00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT 0x00000008 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK 0x0000f000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT 0x0000000c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK 0x000f0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT 0x00000010 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK 0x00f00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT 0x00000014 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK 0x0f000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT 0x00000018 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK 0xf0000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT 0x0000001c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK 0x0000000fL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT 0x00000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK 0x000000f0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT 0x00000004 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK 0x00000f00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT 0x00000008 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK 0x0000f000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT 0x0000000c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK 0x000f0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT 0x00000010 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK 0x00f00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT 0x00000014 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK 0x0f000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT 0x00000018 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK 0xf0000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT 0x0000001c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK 0x000f0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT 0x00000010 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK 0x00f00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT 0x00000014 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK 0x0f000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT 0x00000018 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK 0xf0000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT 0x0000001c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK 0x0000000fL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT 0x00000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK 0x000000f0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT 0x00000004 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK 0x00000f00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT 0x00000008 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK 0x0000f000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT 0x0000000c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK 0x0000000fL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT 0x00000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK 0x000000f0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT 0x00000004 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK 0x00000f00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT 0x00000008 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK 0x0000f000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT 0x0000000c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK 0x000f0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT 0x00000010 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK 0x00f00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT 0x00000014 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK 0x0f000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT 0x00000018 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK 0xf0000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT 0x0000001c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK 0x0000000fL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT 0x00000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK 0x000000f0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT 0x00000004 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK 0x00000f00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT 0x00000008 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK 0x0000f000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT 0x0000000c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK 0x000f0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT 0x00000010 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK 0x00f00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT 0x00000014 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK 0x0f000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT 0x00000018 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK 0xf0000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT 0x0000001c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK 0x0000000fL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT 0x00000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK 0x000000f0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT 0x00000004 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK 0x00000f00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT 0x00000008 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK 0x0000f000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT 0x0000000c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK 0x000f0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT 0x00000010 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK 0x00f00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT 0x00000014 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK 0x0f000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT 0x00000018 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK 0xf0000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT 0x0000001c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK 0x000f0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT 0x00000010 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK 0x00f00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT 0x00000014 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK 0x0f000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT 0x00000018 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK 0xf0000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT 0x0000001c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK 0x0000000fL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT 0x00000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK 0x000000f0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT 0x00000004 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK 0x00000f00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT 0x00000008 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK 0x0000f000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT 0x0000000c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK 0x0000000fL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT 0x00000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK 0x000000f0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT 0x00000004 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK 0x00000f00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT 0x00000008 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK 0x0000f000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT 0x0000000c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK 0x000f0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT 0x00000010 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK 0x00f00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT 0x00000014 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK 0x0f000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT 0x00000018 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK 0xf0000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT 0x0000001c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK 0x0000000fL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT 0x00000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK 0x000000f0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT 0x00000004 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK 0x00000f00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT 0x00000008 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK 0x0000f000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT 0x0000000c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK 0x000f0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT 0x00000010 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK 0x00f00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT 0x00000014 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK 0x0f000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT 0x00000018 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK 0xf0000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT 0x0000001c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK 0x0000000fL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT 0x00000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK 0x000000f0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT 0x00000004 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK 0x00000f00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT 0x00000008 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK 0x0000f000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT 0x0000000c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK 0x000f0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT 0x00000010 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK 0x00f00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT 0x00000014 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK 0x0f000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT 0x00000018 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK 0xf0000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT 0x0000001c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK 0x000f0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT 0x00000010 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK 0x00f00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT 0x00000014 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK 0x0f000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT 0x00000018 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK 0xf0000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT 0x0000001c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK 0x0000000fL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT 0x00000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK 0x000000f0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT 0x00000004 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK 0x00000f00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT 0x00000008 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK 0x0000f000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT 0x0000000c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK 0x0000000fL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT 0x00000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK 0x000000f0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT 0x00000004 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK 0x00000f00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT 0x00000008 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK 0x0000f000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT 0x0000000c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK 0x000f0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT 0x00000010 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK 0x00f00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT 0x00000014 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK 0x0f000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT 0x00000018 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK 0xf0000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT 0x0000001c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK 0x0000000fL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT 0x00000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK 0x000000f0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT 0x00000004 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK 0x00000f00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT 0x00000008 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK 0x0000f000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT 0x0000000c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK 0x000f0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT 0x00000010 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK 0x00f00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT 0x00000014 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK 0x0f000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT 0x00000018 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK 0xf0000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT 0x0000001c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK 0x0000000fL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT 0x00000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK 0x000000f0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT 0x00000004 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK 0x00000f00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT 0x00000008 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK 0x0000f000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT 0x0000000c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK 0x000f0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT 0x00000010 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK 0x00f00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT 0x00000014 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK 0x0f000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT 0x00000018 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK 0xf0000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT 0x0000001c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK 0x000f0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT 0x00000010 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK 0x00f00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT 0x00000014 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK 0x0f000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT 0x00000018 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK 0xf0000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT 0x0000001c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK 0x0000000fL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT 0x00000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK 0x000000f0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT 0x00000004 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK 0x00000f00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT 0x00000008 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK 0x0000f000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT 0x0000000c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK 0x0000000fL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT 0x00000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK 0x000000f0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT 0x00000004 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK 0x00000f00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT 0x00000008 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK 0x0000f000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT 0x0000000c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK 0x000f0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT 0x00000010 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK 0x00f00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT 0x00000014 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK 0x0f000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT 0x00000018 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK 0xf0000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT 0x0000001c +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK 0x0000000fL +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT 0x00000000 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK 0x000000f0L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT 0x00000004 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK 0x00000f00L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT 0x00000008 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK 0x0000f000L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT 0x0000000c +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK 0x000f0000L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT 0x00000010 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK 0x00f00000L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT 0x00000014 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK 0x0f000000L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT 0x00000018 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK 0xf0000000L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT 0x0000001c +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK 0x00000f00L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT 0x00000008 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK 0x0000f000L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT 0x0000000c +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK 0x000f0000L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT 0x00000010 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK 0x00f00000L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT 0x00000014 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK 0x0f000000L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT 0x00000018 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK 0xf0000000L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT 0x0000001c +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK 0x0000000fL +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT 0x00000000 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK 0x000000f0L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT 0x00000004 +#define PA_SC_CLIPRECT_0_BR__BR_X_MASK 0x00007fffL +#define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_CLIPRECT_0_BR__BR_Y_MASK 0x7fff0000L +#define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT 0x00000010 +#define PA_SC_CLIPRECT_0_TL__TL_X_MASK 0x00007fffL +#define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_CLIPRECT_0_TL__TL_Y_MASK 0x7fff0000L +#define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_CLIPRECT_1_BR__BR_X_MASK 0x00007fffL +#define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_CLIPRECT_1_BR__BR_Y_MASK 0x7fff0000L +#define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT 0x00000010 +#define PA_SC_CLIPRECT_1_TL__TL_X_MASK 0x00007fffL +#define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_CLIPRECT_1_TL__TL_Y_MASK 0x7fff0000L +#define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_CLIPRECT_2_BR__BR_X_MASK 0x00007fffL +#define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_CLIPRECT_2_BR__BR_Y_MASK 0x7fff0000L +#define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT 0x00000010 +#define PA_SC_CLIPRECT_2_TL__TL_X_MASK 0x00007fffL +#define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_CLIPRECT_2_TL__TL_Y_MASK 0x7fff0000L +#define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_CLIPRECT_3_BR__BR_X_MASK 0x00007fffL +#define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_CLIPRECT_3_BR__BR_Y_MASK 0x7fff0000L +#define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT 0x00000010 +#define PA_SC_CLIPRECT_3_TL__TL_X_MASK 0x00007fffL +#define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_CLIPRECT_3_TL__TL_Y_MASK 0x7fff0000L +#define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK 0x0000ffffL +#define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT 0x00000000 +#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX_MASK 0x0000003fL +#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX__SHIFT 0x00000000 +#define PA_SC_DEBUG_DATA__DATA_MASK 0xffffffffL +#define PA_SC_DEBUG_DATA__DATA__SHIFT 0x00000000 +#define PA_SC_DEBUG_REG0__REG0_FIELD0_MASK 0x00000003L +#define PA_SC_DEBUG_REG0__REG0_FIELD0__SHIFT 0x00000000 +#define PA_SC_DEBUG_REG0__REG0_FIELD1_MASK 0x0000000cL +#define PA_SC_DEBUG_REG0__REG0_FIELD1__SHIFT 0x00000002 +#define PA_SC_DEBUG_REG1__REG1_FIELD0_MASK 0x00000003L +#define PA_SC_DEBUG_REG1__REG1_FIELD0__SHIFT 0x00000000 +#define PA_SC_DEBUG_REG1__REG1_FIELD1_MASK 0x0000000cL +#define PA_SC_DEBUG_REG1__REG1_FIELD1__SHIFT 0x00000002 +#define PA_SC_EDGERULE__ER_LINE_BT_MASK 0xf0000000L +#define PA_SC_EDGERULE__ER_LINE_BT__SHIFT 0x0000001c +#define PA_SC_EDGERULE__ER_LINE_LR_MASK 0x0003f000L +#define PA_SC_EDGERULE__ER_LINE_LR__SHIFT 0x0000000c +#define PA_SC_EDGERULE__ER_LINE_RL_MASK 0x00fc0000L +#define PA_SC_EDGERULE__ER_LINE_RL__SHIFT 0x00000012 +#define PA_SC_EDGERULE__ER_LINE_TB_MASK 0x0f000000L +#define PA_SC_EDGERULE__ER_LINE_TB__SHIFT 0x00000018 +#define PA_SC_EDGERULE__ER_POINT_MASK 0x000000f0L +#define PA_SC_EDGERULE__ER_POINT__SHIFT 0x00000004 +#define PA_SC_EDGERULE__ER_RECT_MASK 0x00000f00L +#define PA_SC_EDGERULE__ER_RECT__SHIFT 0x00000008 +#define PA_SC_EDGERULE__ER_TRI_MASK 0x0000000fL +#define PA_SC_EDGERULE__ER_TRI__SHIFT 0x00000000 +#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x00000004L +#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x00000002 +#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x00000200L +#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x00000009 +#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x00004000L +#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0x0000000e +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x00200000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x00000015 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x00800000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x00000017 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x00040000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x00000012 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x00010000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0x00000010 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x00400000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x00000016 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x00080000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x00000013 +#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x00002000L +#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0x0000000d +#define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE_MASK 0x000000c0L +#define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE__SHIFT 0x00000006 +#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x00000002L +#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x00000001 +#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x00000020L +#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x00000005 +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x00000400L +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0x0000000a +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x00000800L +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0x0000000b +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x00001000L +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0x0000000c +#define PA_SC_ENHANCE__ECO_SPARE0_MASK 0x80000000L +#define PA_SC_ENHANCE__ECO_SPARE0__SHIFT 0x0000001f +#define PA_SC_ENHANCE__ECO_SPARE1_MASK 0x40000000L +#define PA_SC_ENHANCE__ECO_SPARE1__SHIFT 0x0000001e +#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x00000008L +#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x00000003 +#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x00000010L +#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x00000004 +#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x00008000L +#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0x0000000f +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x01000000L +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x00000018 +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x00020000L +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0x00000011 +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x00100000L +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x00000014 +#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x00000001L +#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x00000000 +#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x00000100L +#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x00000008 +#define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x000000ffL +#define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x00000000 +#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x00007fc0L +#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x00000006 +#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xff800000L +#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x00000017 +#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x0000003fL +#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x00000000 +#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x001f8000L +#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0x0000000f +#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0x0000ffffL +#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x00000000 +#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xffff0000L +#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x00000010 +#define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK 0x00007fffL +#define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK 0x7fff0000L +#define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT 0x00000010 +#define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK 0x00007fffL +#define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK 0x7fff0000L +#define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f +#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0x00fc0000L +#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x00000012 +#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0x00000fc0L +#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x00000006 +#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x0000003fL +#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x00000000 +#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x0003f000L +#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0x0000000c +#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK 0x00001000L +#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT 0x0000000c +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x00000200L +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x00000009 +#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x00000400L +#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0x0000000a +#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK 0x00000800L +#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT 0x0000000b +#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000L +#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x0000001d +#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0x0000ffffL +#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x00000000 +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000L +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x0000001c +#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0x00ff0000L +#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x00000010 +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0x0000ff00L +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x00000008 +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0x0000000fL +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x00000000 +#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK 0x00000004L +#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT 0x00000002 +#define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK 0x00000001L +#define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT 0x00000000 +#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK 0x00000008L +#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT 0x00000003 +#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK 0x00000002L +#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT 0x00000001 +#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK 0x02000000L +#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT 0x00000019 +#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x04000000L +#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT 0x0000001a +#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK 0x00080000L +#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT 0x00000013 +#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK 0x00f00000L +#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT 0x00000014 +#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK 0x00008000L +#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT 0x0000000f +#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK 0x00004000L +#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT 0x0000000e +#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK 0x01000000L +#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT 0x00000018 +#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK 0x00040000L +#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT 0x00000012 +#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK 0x00020000L +#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT 0x00000011 +#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK 0x08000000L +#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT 0x0000001b +#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK 0x70000000L +#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT 0x0000001c +#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK 0x00010000L +#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT 0x00000010 +#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK 0x00000080L +#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT 0x00000007 +#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK 0x00000200L +#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT 0x00000009 +#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK 0x00000400L +#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0x0000000a +#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK 0x00000100L +#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT 0x00000008 +#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK 0x00000004L +#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT 0x00000002 +#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK 0x00000002L +#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT 0x00000001 +#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK 0x00000008L +#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT 0x00000003 +#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK 0x00000070L +#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT 0x00000004 +#define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK 0x00000001L +#define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT 0x00000000 +#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK 0x00000800L +#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT 0x0000000b +#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK 0x00001000L +#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT 0x0000000c +#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK 0x00002000L +#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT 0x0000000d +#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003ffL +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a +#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L +#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000ffc00L +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001ffL +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001ffL +#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001ffL +#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001ffL +#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000001ffL +#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000001ffL +#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000001ffL +#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000001ffL +#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x00000000 +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK 0x00000003L +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT 0x00000000 +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK 0x0000000cL +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT 0x00000002 +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK 0x00000030L +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT 0x00000004 +#define PA_SC_RASTER_CONFIG__PKR_MAP_MASK 0x00000300L +#define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT 0x00000008 +#define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK 0x0000c000L +#define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT 0x0000000e +#define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK 0x00000c00L +#define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0x0000000a +#define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK 0x00003000L +#define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT 0x0000000c +#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK 0x00000003L +#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT 0x00000000 +#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK 0x0000000cL +#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT 0x00000002 +#define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK 0x00000030L +#define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT 0x00000004 +#define PA_SC_RASTER_CONFIG__RB_XSEL_MASK 0x00000040L +#define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT 0x00000006 +#define PA_SC_RASTER_CONFIG__RB_YSEL_MASK 0x00000080L +#define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT 0x00000007 +#define PA_SC_RASTER_CONFIG__SC_MAP_MASK 0x00030000L +#define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT 0x00000010 +#define PA_SC_RASTER_CONFIG__SC_XSEL_MASK 0x000c0000L +#define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT 0x00000012 +#define PA_SC_RASTER_CONFIG__SC_YSEL_MASK 0x00300000L +#define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT 0x00000014 +#define PA_SC_RASTER_CONFIG__SE_MAP_MASK 0x03000000L +#define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT 0x00000018 +#define PA_SC_RASTER_CONFIG__SE_XSEL_MASK 0x0c000000L +#define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT 0x0000001a +#define PA_SC_RASTER_CONFIG__SE_YSEL_MASK 0x30000000L +#define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT 0x0000001c +#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0x0000ffffL +#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0xffff0000L +#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x00000010 +#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0x0000ffffL +#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0xffff0000L +#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f +#define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f +#define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f +#define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f +#define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f +#define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f +#define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f +#define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f +#define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f +#define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f +#define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f +#define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f +#define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f +#define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f +#define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f +#define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f +#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK 0xffffffffL +#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK 0xffffffffL +#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK 0xffffffffL +#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK 0xffffffffL +#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK 0xffffffffL +#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK 0xffffffffL +#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK 0xffffffffL +#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK 0xffffffffL +#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK 0xffffffffL +#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK 0xffffffffL +#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK 0xffffffffL +#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK 0xffffffffL +#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK 0xffffffffL +#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK 0xffffffffL +#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK 0xffffffffL +#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK 0xffffffffL +#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK 0xffffffffL +#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK 0xffffffffL +#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK 0xffffffffL +#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK 0xffffffffL +#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK 0xffffffffL +#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK 0xffffffffL +#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK 0xffffffffL +#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK 0xffffffffL +#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK 0xffffffffL +#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK 0xffffffffL +#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK 0xffffffffL +#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK 0xffffffffL +#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK 0xffffffffL +#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK 0xffffffffL +#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK 0xffffffffL +#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK 0xffffffffL +#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT 0x00000000 +#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0x0000ffffL +#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x00000000 +#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0xffff0000L +#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x00000010 +#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x00007fffL +#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x7fff0000L +#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x00000010 +#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x00007fffL +#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x7fff0000L +#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f +#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000L +#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x0000001f +#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX_MASK 0x0000001fL +#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX__SHIFT 0x00000000 +#define PA_SU_DEBUG_DATA__DATA_MASK 0xffffffffL +#define PA_SU_DEBUG_DATA__DATA__SHIFT 0x00000000 +#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK 0x000001ffL +#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT 0x00000000 +#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK 0x01ff0000L +#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT 0x00000010 +#define PA_SU_LINE_CNTL__WIDTH_MASK 0x0000ffffL +#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x00000000 +#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK 0x00000010L +#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT 0x00000004 +#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK 0x00000004L +#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT 0x00000002 +#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK 0x00000008L +#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT 0x00000003 +#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK 0x00000003L +#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT 0x00000000 +#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK 0xffffffffL +#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT 0x00000000 +#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK 0x00ffffffL +#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT 0x00000000 +#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000ffffL +#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003ffL +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a +#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L +#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000ffc00L +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 +#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000ffffL +#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003ffL +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x00000000 +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000ffc00L +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0x0000000a +#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L +#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000ffc00L +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0x0000000a +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 +#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0x0000ffffL +#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00f00000L +#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL +#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 +#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0x0000ffffL +#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00f00000L +#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL +#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 +#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xffff0000L +#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x00000010 +#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0x0000ffffL +#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x00000000 +#define PA_SU_POINT_SIZE__HEIGHT_MASK 0x0000ffffL +#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x00000000 +#define PA_SU_POINT_SIZE__WIDTH_MASK 0xffff0000L +#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x00000010 +#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xffffffffL +#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x00000000 +#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xffffffffL +#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x00000000 +#define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK 0xffffffffL +#define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT 0x00000000 +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK 0x00000100L +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT 0x00000008 +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK 0x000000ffL +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT 0x00000000 +#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xffffffffL +#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x00000000 +#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xffffffffL +#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x00000000 +#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK 0x00000020L +#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT 0x00000005 +#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000002L +#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x00000001 +#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK 0x00000040L +#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT 0x00000006 +#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000004L +#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x00000002 +#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK 0x0000ff00L +#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT 0x00000008 +#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK 0x00000080L +#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT 0x00000007 +#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000008L +#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x00000003 +#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK 0x00000010L +#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT 0x00000004 +#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000001L +#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x00000000 +#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK 0x40000000L +#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT 0x0000001e +#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK 0x80000000L +#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT 0x0000001f +#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x00000002L +#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x00000001 +#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x00000001L +#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x00000000 +#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x00000004L +#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x00000002 +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x00200000L +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x00000015 +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x00100000L +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x00000014 +#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x00000700L +#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x00000008 +#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0x000000e0L +#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x00000005 +#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x00000018L +#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x00000003 +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x00001000L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0x0000000c +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0x0000000b +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x00002000L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0x0000000d +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x00080000L +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x00000013 +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000L +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x00000010 +#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x00000001L +#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x00000000 +#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x00000038L +#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x00000003 +#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x00000006L +#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x00000001 +#define RAS_BCI_SIGNATURE0__SIGNATURE_MASK 0xffffffffL +#define RAS_BCI_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 +#define RAS_BCI_SIGNATURE1__SIGNATURE_MASK 0xffffffffL +#define RAS_BCI_SIGNATURE1__SIGNATURE__SHIFT 0x00000000 +#define RAS_CB_SIGNATURE0__SIGNATURE_MASK 0xffffffffL +#define RAS_CB_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 +#define RAS_DB_SIGNATURE0__SIGNATURE_MASK 0xffffffffL +#define RAS_DB_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 +#define RAS_IA_SIGNATURE0__SIGNATURE_MASK 0xffffffffL +#define RAS_IA_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 +#define RAS_IA_SIGNATURE1__SIGNATURE_MASK 0xffffffffL +#define RAS_IA_SIGNATURE1__SIGNATURE__SHIFT 0x00000000 +#define RAS_PA_SIGNATURE0__SIGNATURE_MASK 0xffffffffL +#define RAS_PA_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 +#define RAS_SC_SIGNATURE0__SIGNATURE_MASK 0xffffffffL +#define RAS_SC_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 +#define RAS_SC_SIGNATURE1__SIGNATURE_MASK 0xffffffffL +#define RAS_SC_SIGNATURE1__SIGNATURE__SHIFT 0x00000000 +#define RAS_SC_SIGNATURE2__SIGNATURE_MASK 0xffffffffL +#define RAS_SC_SIGNATURE2__SIGNATURE__SHIFT 0x00000000 +#define RAS_SC_SIGNATURE3__SIGNATURE_MASK 0xffffffffL +#define RAS_SC_SIGNATURE3__SIGNATURE__SHIFT 0x00000000 +#define RAS_SC_SIGNATURE4__SIGNATURE_MASK 0xffffffffL +#define RAS_SC_SIGNATURE4__SIGNATURE__SHIFT 0x00000000 +#define RAS_SC_SIGNATURE5__SIGNATURE_MASK 0xffffffffL +#define RAS_SC_SIGNATURE5__SIGNATURE__SHIFT 0x00000000 +#define RAS_SC_SIGNATURE6__SIGNATURE_MASK 0xffffffffL +#define RAS_SC_SIGNATURE6__SIGNATURE__SHIFT 0x00000000 +#define RAS_SC_SIGNATURE7__SIGNATURE_MASK 0xffffffffL +#define RAS_SC_SIGNATURE7__SIGNATURE__SHIFT 0x00000000 +#define RAS_SIGNATURE_CONTROL__ENABLE_MASK 0x00000001L +#define RAS_SIGNATURE_CONTROL__ENABLE__SHIFT 0x00000000 +#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK_MASK 0xffffffffL +#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK__SHIFT 0x00000000 +#define RAS_SPI_SIGNATURE0__SIGNATURE_MASK 0xffffffffL +#define RAS_SPI_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 +#define RAS_SPI_SIGNATURE1__SIGNATURE_MASK 0xffffffffL +#define RAS_SPI_SIGNATURE1__SIGNATURE__SHIFT 0x00000000 +#define RAS_SQ_SIGNATURE0__SIGNATURE_MASK 0xffffffffL +#define RAS_SQ_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 +#define RAS_SX_SIGNATURE0__SIGNATURE_MASK 0xffffffffL +#define RAS_SX_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 +#define RAS_SX_SIGNATURE1__SIGNATURE_MASK 0xffffffffL +#define RAS_SX_SIGNATURE1__SIGNATURE__SHIFT 0x00000000 +#define RAS_SX_SIGNATURE2__SIGNATURE_MASK 0xffffffffL +#define RAS_SX_SIGNATURE2__SIGNATURE__SHIFT 0x00000000 +#define RAS_SX_SIGNATURE3__SIGNATURE_MASK 0xffffffffL +#define RAS_SX_SIGNATURE3__SIGNATURE__SHIFT 0x00000000 +#define RAS_TA_SIGNATURE0__SIGNATURE_MASK 0xffffffffL +#define RAS_TA_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 +#define RAS_TD_SIGNATURE0__SIGNATURE_MASK 0xffffffffL +#define RAS_TD_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 +#define RAS_VGT_SIGNATURE0__SIGNATURE_MASK 0xffffffffL +#define RAS_VGT_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 +#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK 0x00000002L +#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT 0x00000001 +#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x00000001L +#define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT 0x00000000 +#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x00000004L +#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT 0x00000002 +#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK 0x0007fff8L +#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT 0x00000003 +#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xfff80000L +#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT 0x00000013 +#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK 0x00000001L +#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT 0x00000000 +#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK 0xfffffffeL +#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT 0x00000001 +#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK 0x08000000L +#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT 0x0000001b +#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x00000001L +#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x00000000 +#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x0000ff00L +#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x00000008 +#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000L +#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT 0x0000001c +#define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x00000002L +#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x00000001 +#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK 0x000000fcL +#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x00000002 +#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK 0x60000000L +#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x0000001d +#define RLC_CGCG_CGLS_CTRL__SPARE_MASK 0x80000000L +#define RLC_CGCG_CGLS_CTRL__SPARE__SHIFT 0x0000001f +#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK 0x0000000fL +#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT 0x00000000 +#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK 0x000000f0L +#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT 0x00000004 +#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK 0x0fff0000L +#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT 0x00000010 +#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK 0xf0000000L +#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT 0x0000001c +#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK 0x00000f00L +#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT 0x00000008 +#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK 0x0000f000L +#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT 0x0000000c +#define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE_MASK 0xffffffffL +#define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE__SHIFT 0x00000000 +#define RLC_CNTL__FORCE_RETRY_MASK 0x00000002L +#define RLC_CNTL__FORCE_RETRY__SHIFT 0x00000001 +#define RLC_CNTL__READ_CACHE_DISABLE_MASK 0x00000004L +#define RLC_CNTL__READ_CACHE_DISABLE__SHIFT 0x00000002 +#define RLC_CNTL__RESERVED_MASK 0xffffff00L +#define RLC_CNTL__RESERVED__SHIFT 0x00000008 +#define RLC_CNTL__RLC_ENABLE_F32_MASK 0x00000001L +#define RLC_CNTL__RLC_ENABLE_F32__SHIFT 0x00000000 +#define RLC_CNTL__RLC_STEP_F32_MASK 0x00000008L +#define RLC_CNTL__RLC_STEP_F32__SHIFT 0x00000003 +#define RLC_CNTL__SOFT_RESET_DEBUG_MODE_MASK 0x00000010L +#define RLC_CNTL__SOFT_RESET_DEBUG_MODE__SHIFT 0x00000004 +#define RLC_CU_STATUS__WORK_PENDING_MASK 0xffffffffL +#define RLC_CU_STATUS__WORK_PENDING__SHIFT 0x00000000 +#define RLC_DEBUG__DATA_MASK 0xffffffffL +#define RLC_DEBUG__DATA__SHIFT 0x00000000 +#define RLC_DEBUG_SELECT__RESERVED_MASK 0xffff8000L +#define RLC_DEBUG_SELECT__RESERVED__SHIFT 0x0000000f +#define RLC_DEBUG_SELECT__SELECT_MASK 0x000000ffL +#define RLC_DEBUG_SELECT__SELECT__SHIFT 0x00000000 +#define RLC_DRIVER_CPDMA_STATUS__DRIVER_ACK_MASK 0x00000010L +#define RLC_DRIVER_CPDMA_STATUS__DRIVER_ACK__SHIFT 0x00000004 +#define RLC_DRIVER_CPDMA_STATUS__DRIVER_REQUEST_MASK 0x00000001L +#define RLC_DRIVER_CPDMA_STATUS__DRIVER_REQUEST__SHIFT 0x00000000 +#define RLC_DRIVER_CPDMA_STATUS__RESERVED1_MASK 0x0000000eL +#define RLC_DRIVER_CPDMA_STATUS__RESERVED1__SHIFT 0x00000001 +#define RLC_DRIVER_CPDMA_STATUS__RESERVED_MASK 0xffffffe0L +#define RLC_DRIVER_CPDMA_STATUS__RESERVED__SHIFT 0x00000005 +#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK_MASK 0xffffffffL +#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK__SHIFT 0x00000000 +#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xffffffffL +#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x00000000 +#define RLC_GPM_SCRATCH_ADDR__ADDR_MASK 0x000001ffL +#define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT 0x00000000 +#define RLC_GPM_SCRATCH_ADDR__RESERVED_MASK 0xfffffe00L +#define RLC_GPM_SCRATCH_ADDR__RESERVED__SHIFT 0x00000009 +#define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK 0xffffffffL +#define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT 0x00000000 +#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK 0xffffffc0L +#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT 0x00000006 +#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x0000003fL +#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x00000000 +#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK 0xffffffffL +#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT 0x00000000 +#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK 0xffffffffL +#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT 0x00000000 +#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK_MASK 0xffffffffL +#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK__SHIFT 0x00000000 +#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK 0x00000ff0L +#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT 0x00000004 +#define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK 0x00000002L +#define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT 0x00000001 +#define RLC_LB_CNTL__LB_CNT_REG_INC_MASK 0x00000008L +#define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT 0x00000003 +#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK 0x00000004L +#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT 0x00000002 +#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK 0x00000001L +#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT 0x00000000 +#define RLC_LB_CNTL__RESERVED_MASK 0xfffffff0L +#define RLC_LB_CNTL__RESERVED__SHIFT 0x00000004 +#define RLC_LB_CNTR_INIT__LB_CNTR_INIT_MASK 0xffffffffL +#define RLC_LB_CNTR_INIT__LB_CNTR_INIT__SHIFT 0x00000000 +#define RLC_LB_CNTR_MAX__LB_CNTR_MAX_MASK 0xffffffffL +#define RLC_LB_CNTR_MAX__LB_CNTR_MAX__SHIFT 0x00000000 +#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK_MASK 0xffffffffL +#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK__SHIFT 0x00000000 +#define RLC_LB_PARAMS__FIFO_SAMPLES_MASK 0x000000feL +#define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT 0x00000001 +#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK 0xffff0000L +#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT 0x00000010 +#define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK 0x0000ff00L +#define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT 0x00000008 +#define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK 0x00000001L +#define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT 0x00000000 +#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR_MASK 0xffffffffL +#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR__SHIFT 0x00000000 +#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK 0x000000ffL +#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT 0x00000000 +#define RLC_MAX_PG_CU__SPARE_MASK 0xffffff00L +#define RLC_MAX_PG_CU__SPARE__SHIFT 0x00000008 +#define RLC_MC_CNTL__RDNFO_STALL_MASK 0x10000000L +#define RLC_MC_CNTL__RDNFO_STALL__SHIFT 0x0000001c +#define RLC_MC_CNTL__RDNFO_URG_MASK 0x00f00000L +#define RLC_MC_CNTL__RDNFO_URG__SHIFT 0x00000014 +#define RLC_MC_CNTL__RDREQ_PRIV_MASK 0x08000000L +#define RLC_MC_CNTL__RDREQ_PRIV__SHIFT 0x0000001b +#define RLC_MC_CNTL__RDREQ_SWAP_MASK 0x03000000L +#define RLC_MC_CNTL__RDREQ_SWAP__SHIFT 0x00000018 +#define RLC_MC_CNTL__RDREQ_TRAN_MASK 0x04000000L +#define RLC_MC_CNTL__RDREQ_TRAN__SHIFT 0x0000001a +#define RLC_MC_CNTL__RESERVED_B_MASK 0x000fe000L +#define RLC_MC_CNTL__RESERVED_B__SHIFT 0x0000000d +#define RLC_MC_CNTL__RESERVED_MASK 0xe0000000L +#define RLC_MC_CNTL__RESERVED__SHIFT 0x0000001d +#define RLC_MC_CNTL__WRNFO_STALL_MASK 0x00000010L +#define RLC_MC_CNTL__WRNFO_STALL__SHIFT 0x00000004 +#define RLC_MC_CNTL__WRNFO_URG_MASK 0x000001e0L +#define RLC_MC_CNTL__WRNFO_URG__SHIFT 0x00000005 +#define RLC_MC_CNTL__WRREQ_DW_IMASK_MASK 0x00001e00L +#define RLC_MC_CNTL__WRREQ_DW_IMASK__SHIFT 0x00000009 +#define RLC_MC_CNTL__WRREQ_PRIV_MASK 0x00000008L +#define RLC_MC_CNTL__WRREQ_PRIV__SHIFT 0x00000003 +#define RLC_MC_CNTL__WRREQ_SWAP_MASK 0x00000003L +#define RLC_MC_CNTL__WRREQ_SWAP__SHIFT 0x00000000 +#define RLC_MC_CNTL__WRREQ_TRAN_MASK 0x00000004L +#define RLC_MC_CNTL__WRREQ_TRAN__SHIFT 0x00000002 +#define RLC_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000L +#define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x00000018 +#define RLC_MEM_SLP_CNTL__RESERVED_MASK 0x000000fcL +#define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x00000002 +#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x00000002L +#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT 0x00000001 +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x00000001L +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT 0x00000000 +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK 0x00ff0000L +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT 0x00000010 +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK 0x0000ff00L +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT 0x00000008 +#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL +#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 +#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL +#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 +#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L +#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0x0000000a +#define RLC_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000007L +#define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x00000000 +#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK_MASK 0xffffffffL +#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK__SHIFT 0x00000000 +#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK 0x00010000L +#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT 0x00000010 +#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x00000004L +#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE__SHIFT 0x00000002 +#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x00000001L +#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT 0x00000000 +#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x00000002L +#define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT 0x00000001 +#define RLC_PG_CNTL__PG_ERROR_STATUS_MASK 0xff000000L +#define RLC_PG_CNTL__PG_ERROR_STATUS__SHIFT 0x00000018 +#define RLC_PG_CNTL__RESERVED1_MASK 0x00f80000L +#define RLC_PG_CNTL__RESERVED1__SHIFT 0x00000013 +#define RLC_PG_CNTL__RESERVED_MASK 0xfffffff0L +#define RLC_PG_CNTL__RESERVED__SHIFT 0x00000004 +#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x00040000L +#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT 0x00000012 +#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x00020000L +#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT 0x00000011 +#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK 0x00000008L +#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE__SHIFT 0x00000003 +#define RLC_SAVE_AND_RESTORE_BASE__BASE_MASK 0xffffffffL +#define RLC_SAVE_AND_RESTORE_BASE__BASE__SHIFT 0x00000000 +#define RLC_SERDES_RD_DATA_0__DATA_MASK 0xffffffffL +#define RLC_SERDES_RD_DATA_0__DATA__SHIFT 0x00000000 +#define RLC_SERDES_RD_DATA_1__DATA_MASK 0xffffffffL +#define RLC_SERDES_RD_DATA_1__DATA__SHIFT 0x00000000 +#define RLC_SERDES_RD_DATA_2__DATA_MASK 0xffffffffL +#define RLC_SERDES_RD_DATA_2__DATA__SHIFT 0x00000000 +#define RLC_SERDES_RD_MASTER_INDEX__CU_ID_MASK 0x0000000fL +#define RLC_SERDES_RD_MASTER_INDEX__CU_ID__SHIFT 0x00000000 +#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID_MASK 0x0000c000L +#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID__SHIFT 0x0000000e +#define RLC_SERDES_RD_MASTER_INDEX__NON_SE_MASK 0x00003800L +#define RLC_SERDES_RD_MASTER_INDEX__NON_SE__SHIFT 0x0000000b +#define RLC_SERDES_RD_MASTER_INDEX__SE_ID_MASK 0x000001c0L +#define RLC_SERDES_RD_MASTER_INDEX__SE_ID__SHIFT 0x00000006 +#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID_MASK 0x00000200L +#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID__SHIFT 0x00000009 +#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_MASK 0x00000400L +#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU__SHIFT 0x0000000a +#define RLC_SERDES_RD_MASTER_INDEX__SH_ID_MASK 0x00000030L +#define RLC_SERDES_RD_MASTER_INDEX__SH_ID__SHIFT 0x00000004 +#define RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK 0xffffc000L +#define RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT 0x0000000e +#define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK 0x000000ffL +#define RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT 0x00000000 +#define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK 0x00100000L +#define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0__SHIFT 0x00000014 +#define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_1_MASK 0x00200000L +#define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_1__SHIFT 0x00000015 +#define RLC_SERDES_WR_CTRL__CGLS_DISABLE_MASK 0x00020000L +#define RLC_SERDES_WR_CTRL__CGLS_DISABLE__SHIFT 0x00000011 +#define RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK 0x00010000L +#define RLC_SERDES_WR_CTRL__CGLS_ENABLE__SHIFT 0x00000010 +#define RLC_SERDES_WR_CTRL__CGLS_OFF_MASK 0x00080000L +#define RLC_SERDES_WR_CTRL__CGLS_OFF__SHIFT 0x00000013 +#define RLC_SERDES_WR_CTRL__CGLS_ON_MASK 0x00040000L +#define RLC_SERDES_WR_CTRL__CGLS_ON__SHIFT 0x00000012 +#define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK 0x00400000L +#define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0__SHIFT 0x00000016 +#define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK 0x00800000L +#define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1__SHIFT 0x00000017 +#define RLC_SERDES_WR_CTRL__P1_SELECT_MASK 0x00000400L +#define RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT 0x0000000a +#define RLC_SERDES_WR_CTRL__P2_SELECT_MASK 0x00000800L +#define RLC_SERDES_WR_CTRL__P2_SELECT__SHIFT 0x0000000b +#define RLC_SERDES_WR_CTRL__POWER_DOWN_MASK 0x00000100L +#define RLC_SERDES_WR_CTRL__POWER_DOWN__SHIFT 0x00000008 +#define RLC_SERDES_WR_CTRL__POWER_UP_MASK 0x00000200L +#define RLC_SERDES_WR_CTRL__POWER_UP__SHIFT 0x00000009 +#define RLC_SERDES_WR_CTRL__READ_COMMAND_MASK 0x00002000L +#define RLC_SERDES_WR_CTRL__READ_COMMAND__SHIFT 0x0000000d +#define RLC_SERDES_WR_CTRL__REG_ADDR_MASK 0xf0000000L +#define RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT 0x0000001c +#define RLC_SERDES_WR_CTRL__RESERVED_1_MASK 0x0000c000L +#define RLC_SERDES_WR_CTRL__RESERVED_1__SHIFT 0x0000000e +#define RLC_SERDES_WR_CTRL__RESERVED_2_MASK 0x0f000000L +#define RLC_SERDES_WR_CTRL__RESERVED_2__SHIFT 0x00000018 +#define RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK 0x00001000L +#define RLC_SERDES_WR_CTRL__WRITE_COMMAND__SHIFT 0x0000000c +#define RLC_SERDES_WR_DATA__DATA_MASK 0xffffffffL +#define RLC_SERDES_WR_DATA__DATA__SHIFT 0x00000000 +#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK 0xfffffffeL +#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT 0x00000001 +#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK 0x00000001L +#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT 0x00000000 +#define RLC_SMU_PG_CTRL__SPARE_MASK 0xfffffffeL +#define RLC_SMU_PG_CTRL__SPARE__SHIFT 0x00000001 +#define RLC_SMU_PG_CTRL__START_PG_MASK 0x00000001L +#define RLC_SMU_PG_CTRL__START_PG__SHIFT 0x00000000 +#define RLC_SMU_PG_WAKE_UP_CTRL__SPARE_MASK 0xfffffffeL +#define RLC_SMU_PG_WAKE_UP_CTRL__SPARE__SHIFT 0x00000001 +#define RLC_SMU_PG_WAKE_UP_CTRL__START_PG_WAKE_UP_MASK 0x00000001L +#define RLC_SMU_PG_WAKE_UP_CTRL__START_PG_WAKE_UP__SHIFT 0x00000000 +#define RLC_SOFT_RESET_GPU__RESERVED_MASK 0xfffffffeL +#define RLC_SOFT_RESET_GPU__RESERVED__SHIFT 0x00000001 +#define RLC_SOFT_RESET_GPU__SOFT_RESET_GPU_MASK 0x00000001L +#define RLC_SOFT_RESET_GPU__SOFT_RESET_GPU__SHIFT 0x00000000 +#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xffffffffL +#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x00000000 +#define RLC_STAT__RESERVED_MASK 0xfffffff0L +#define RLC_STAT__RESERVED__SHIFT 0x00000004 +#define RLC_STAT__RLC_BUSY_MASK 0x00000001L +#define RLC_STAT__RLC_BUSY__SHIFT 0x00000000 +#define RLC_STAT__RLC_GPM_BUSY_MASK 0x00000002L +#define RLC_STAT__RLC_GPM_BUSY__SHIFT 0x00000001 +#define RLC_STAT__RLC_SPM_BUSY_MASK 0x00000004L +#define RLC_STAT__RLC_SPM_BUSY__SHIFT 0x00000002 +#define RLC_THREAD1_DELAY__CU_IDEL_DELAY_MASK 0x000000ffL +#define RLC_THREAD1_DELAY__CU_IDEL_DELAY__SHIFT 0x00000000 +#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY_MASK 0x0000ff00L +#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT 0x00000008 +#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY_MASK 0x00ff0000L +#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT 0x00000010 +#define RLC_THREAD1_DELAY__SPARE_MASK 0xff000000L +#define RLC_THREAD1_DELAY__SPARE__SHIFT 0x00000018 +#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK 0xffffffffL +#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT 0x00000000 +#define SCRATCH_ADDR__OBSOLETE_ADDR_MASK 0xffffffffL +#define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT 0x00000000 +#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffffL +#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x00000000 +#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffffL +#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x00000000 +#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffffL +#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x00000000 +#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffffL +#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x00000000 +#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffffL +#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x00000000 +#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffffL +#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x00000000 +#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffffL +#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x00000000 +#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffffL +#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x00000000 +#define SCRATCH_UMSK__OBSOLETE_SWAP_MASK 0x00030000L +#define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT 0x00000010 +#define SCRATCH_UMSK__OBSOLETE_UMSK_MASK 0x000000ffL +#define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT 0x00000000 +#define SETUP_DEBUG_REG0__cl_dyn_sclk_vld_MASK 0x80000000L +#define SETUP_DEBUG_REG0__cl_dyn_sclk_vld__SHIFT 0x0000001f +#define SETUP_DEBUG_REG0__event_gated_MASK 0x10000000L +#define SETUP_DEBUG_REG0__event_gated__SHIFT 0x0000001c +#define SETUP_DEBUG_REG0__event_id_gated_MASK 0x0fc00000L +#define SETUP_DEBUG_REG0__event_id_gated__SHIFT 0x00000016 +#define SETUP_DEBUG_REG0__geom_busy_MASK 0x00200000L +#define SETUP_DEBUG_REG0__geom_busy__SHIFT 0x00000015 +#define SETUP_DEBUG_REG0__geom_enable_MASK 0x00008000L +#define SETUP_DEBUG_REG0__geom_enable__SHIFT 0x0000000f +#define SETUP_DEBUG_REG0__ge_stallb_MASK 0x00004000L +#define SETUP_DEBUG_REG0__ge_stallb__SHIFT 0x0000000e +#define SETUP_DEBUG_REG0__pfifo_busy_MASK 0x00080000L +#define SETUP_DEBUG_REG0__pfifo_busy__SHIFT 0x00000013 +#define SETUP_DEBUG_REG0__pmode_prim_gated_MASK 0x20000000L +#define SETUP_DEBUG_REG0__pmode_prim_gated__SHIFT 0x0000001d +#define SETUP_DEBUG_REG0__pmode_state_MASK 0x00003f00L +#define SETUP_DEBUG_REG0__pmode_state__SHIFT 0x00000008 +#define SETUP_DEBUG_REG0__su_baryc_cntl_state_MASK 0x00000003L +#define SETUP_DEBUG_REG0__su_baryc_cntl_state__SHIFT 0x00000000 +#define SETUP_DEBUG_REG0__su_clip_baryc_free_MASK 0x00030000L +#define SETUP_DEBUG_REG0__su_clip_baryc_free__SHIFT 0x00000010 +#define SETUP_DEBUG_REG0__su_clip_rtr_MASK 0x00040000L +#define SETUP_DEBUG_REG0__su_clip_rtr__SHIFT 0x00000012 +#define SETUP_DEBUG_REG0__su_cntl_busy_MASK 0x00100000L +#define SETUP_DEBUG_REG0__su_cntl_busy__SHIFT 0x00000014 +#define SETUP_DEBUG_REG0__su_cntl_state_MASK 0x0000003cL +#define SETUP_DEBUG_REG0__su_cntl_state__SHIFT 0x00000002 +#define SETUP_DEBUG_REG0__su_dyn_sclk_vld_MASK 0x40000000L +#define SETUP_DEBUG_REG0__su_dyn_sclk_vld__SHIFT 0x0000001e +#define SETUP_DEBUG_REG1__x_sort0_gated_23_8_MASK 0xffff0000L +#define SETUP_DEBUG_REG1__x_sort0_gated_23_8__SHIFT 0x00000010 +#define SETUP_DEBUG_REG1__y_sort0_gated_23_8_MASK 0x0000ffffL +#define SETUP_DEBUG_REG1__y_sort0_gated_23_8__SHIFT 0x00000000 +#define SETUP_DEBUG_REG2__x_sort1_gated_23_8_MASK 0xffff0000L +#define SETUP_DEBUG_REG2__x_sort1_gated_23_8__SHIFT 0x00000010 +#define SETUP_DEBUG_REG2__y_sort1_gated_23_8_MASK 0x0000ffffL +#define SETUP_DEBUG_REG2__y_sort1_gated_23_8__SHIFT 0x00000000 +#define SETUP_DEBUG_REG3__x_sort2_gated_23_8_MASK 0xffff0000L +#define SETUP_DEBUG_REG3__x_sort2_gated_23_8__SHIFT 0x00000010 +#define SETUP_DEBUG_REG3__y_sort2_gated_23_8_MASK 0x0000ffffL +#define SETUP_DEBUG_REG3__y_sort2_gated_23_8__SHIFT 0x00000000 +#define SETUP_DEBUG_REG4__attr_indx_sort0_gated_MASK 0x00003fffL +#define SETUP_DEBUG_REG4__attr_indx_sort0_gated__SHIFT 0x00000000 +#define SETUP_DEBUG_REG4__backfacing_gated_MASK 0x00008000L +#define SETUP_DEBUG_REG4__backfacing_gated__SHIFT 0x0000000f +#define SETUP_DEBUG_REG4__clipped_gated_MASK 0x00080000L +#define SETUP_DEBUG_REG4__clipped_gated__SHIFT 0x00000013 +#define SETUP_DEBUG_REG4__dealloc_slot_gated_MASK 0x00700000L +#define SETUP_DEBUG_REG4__dealloc_slot_gated__SHIFT 0x00000014 +#define SETUP_DEBUG_REG4__diamond_rule_gated_MASK 0x03000000L +#define SETUP_DEBUG_REG4__diamond_rule_gated__SHIFT 0x00000018 +#define SETUP_DEBUG_REG4__eop_gated_MASK 0x80000000L +#define SETUP_DEBUG_REG4__eop_gated__SHIFT 0x0000001f +#define SETUP_DEBUG_REG4__fpov_gated_MASK 0x60000000L +#define SETUP_DEBUG_REG4__fpov_gated__SHIFT 0x0000001d +#define SETUP_DEBUG_REG4__null_prim_gated_MASK 0x00004000L +#define SETUP_DEBUG_REG4__null_prim_gated__SHIFT 0x0000000e +#define SETUP_DEBUG_REG4__st_indx_gated_MASK 0x00070000L +#define SETUP_DEBUG_REG4__st_indx_gated__SHIFT 0x00000010 +#define SETUP_DEBUG_REG4__type_gated_MASK 0x1c000000L +#define SETUP_DEBUG_REG4__type_gated__SHIFT 0x0000001a +#define SETUP_DEBUG_REG4__xmajor_gated_MASK 0x00800000L +#define SETUP_DEBUG_REG4__xmajor_gated__SHIFT 0x00000017 +#define SETUP_DEBUG_REG5__attr_indx_sort1_gated_MASK 0x0fffc000L +#define SETUP_DEBUG_REG5__attr_indx_sort1_gated__SHIFT 0x0000000e +#define SETUP_DEBUG_REG5__attr_indx_sort2_gated_MASK 0x00003fffL +#define SETUP_DEBUG_REG5__attr_indx_sort2_gated__SHIFT 0x00000000 +#define SETUP_DEBUG_REG5__pa_reg_sclk_vld_MASK 0x80000000L +#define SETUP_DEBUG_REG5__pa_reg_sclk_vld__SHIFT 0x0000001f +#define SETUP_DEBUG_REG5__provoking_vtx_gated_MASK 0x30000000L +#define SETUP_DEBUG_REG5__provoking_vtx_gated__SHIFT 0x0000001c +#define SETUP_DEBUG_REG5__valid_prim_gated_MASK 0x40000000L +#define SETUP_DEBUG_REG5__valid_prim_gated__SHIFT 0x0000001e +#define SPI_ARB_CYCLES_0__TS0_DURATION_MASK 0x0000ffffL +#define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT 0x00000000 +#define SPI_ARB_CYCLES_0__TS1_DURATION_MASK 0xffff0000L +#define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT 0x00000010 +#define SPI_ARB_CYCLES_1__TS2_DURATION_MASK 0x0000ffffL +#define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT 0x00000000 +#define SPI_ARB_CYCLES_1__TS3_DURATION_MASK 0xffff0000L +#define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT 0x00000010 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK 0x00000007L +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT 0x00000000 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK 0x00000038L +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT 0x00000003 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK 0x000001c0L +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT 0x00000006 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK 0x00000e00L +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT 0x00000009 +#define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK 0x00003000L +#define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT 0x0000000c +#define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK 0x0000c000L +#define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT 0x0000000e +#define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK 0x00030000L +#define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT 0x00000010 +#define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK 0x000c0000L +#define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT 0x00000012 +#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK 0x01000000L +#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT 0x00000018 +#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK 0x00000100L +#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT 0x00000008 +#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK 0x00001000L +#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT 0x0000000c +#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK 0x00000001L +#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT 0x00000000 +#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK 0x00000010L +#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT 0x00000004 +#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK 0x00030000L +#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT 0x00000010 +#define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK 0x00100000L +#define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT 0x00000014 +#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK 0x00000100L +#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT 0x00000008 +#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x00000010L +#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT 0x00000004 +#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK 0x00003c00L +#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0x0000000a +#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK 0x00000200L +#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT 0x00000009 +#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x00000040L +#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT 0x00000006 +#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE_MASK 0xffff0000L +#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE__SHIFT 0x00000010 +#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK 0x00000080L +#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT 0x00000007 +#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK 0x0000000fL +#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT 0x00000000 +#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK 0x02000000L +#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT 0x00000019 +#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK 0x01000000L +#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT 0x00000018 +#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK 0x00e00000L +#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT 0x00000015 +#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK 0x001fffffL +#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT 0x00000000 +#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET_MASK 0x04000000L +#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET__SHIFT 0x0000001a +#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK 0x08000000L +#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT 0x0000001b +#define SPI_DEBUG_BUSY__CS0_BUSY_MASK 0x00000080L +#define SPI_DEBUG_BUSY__CS0_BUSY__SHIFT 0x00000007 +#define SPI_DEBUG_BUSY__CS1_BUSY_MASK 0x00000100L +#define SPI_DEBUG_BUSY__CS1_BUSY__SHIFT 0x00000008 +#define SPI_DEBUG_BUSY__CS2_BUSY_MASK 0x00000200L +#define SPI_DEBUG_BUSY__CS2_BUSY__SHIFT 0x00000009 +#define SPI_DEBUG_BUSY__CS3_BUSY_MASK 0x00000800L +#define SPI_DEBUG_BUSY__CS3_BUSY__SHIFT 0x0000000b +#define SPI_DEBUG_BUSY__CS4_BUSY_MASK 0x00001000L +#define SPI_DEBUG_BUSY__CS4_BUSY__SHIFT 0x0000000c +#define SPI_DEBUG_BUSY__CS5_BUSY_MASK 0x00002000L +#define SPI_DEBUG_BUSY__CS5_BUSY__SHIFT 0x0000000d +#define SPI_DEBUG_BUSY__CS6_BUSY_MASK 0x00004000L +#define SPI_DEBUG_BUSY__CS6_BUSY__SHIFT 0x0000000e +#define SPI_DEBUG_BUSY__CS7_BUSY_MASK 0x00008000L +#define SPI_DEBUG_BUSY__CS7_BUSY__SHIFT 0x0000000f +#define SPI_DEBUG_BUSY__CSG_BUSY_MASK 0x00000080L +#define SPI_DEBUG_BUSY__CSG_BUSY__SHIFT 0x00000007 +#define SPI_DEBUG_BUSY__ES_BUSY_MASK 0x00000004L +#define SPI_DEBUG_BUSY__ES_BUSY__SHIFT 0x00000002 +#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY_MASK 0x00008000L +#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY__SHIFT 0x0000000f +#define SPI_DEBUG_BUSY__GRBM_BUSY_MASK 0x00010000L +#define SPI_DEBUG_BUSY__GRBM_BUSY__SHIFT 0x00000010 +#define SPI_DEBUG_BUSY__GS_BUSY_MASK 0x00000008L +#define SPI_DEBUG_BUSY__GS_BUSY__SHIFT 0x00000003 +#define SPI_DEBUG_BUSY__HS_BUSY_MASK 0x00000002L +#define SPI_DEBUG_BUSY__HS_BUSY__SHIFT 0x00000001 +#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY_MASK 0x00000400L +#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY__SHIFT 0x0000000a +#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY_MASK 0x00000800L +#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY__SHIFT 0x0000000b +#define SPI_DEBUG_BUSY__LS_BUSY_MASK 0x00000001L +#define SPI_DEBUG_BUSY__LS_BUSY__SHIFT 0x00000000 +#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY_MASK 0x00100000L +#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY__SHIFT 0x00000014 +#define SPI_DEBUG_BUSY__PS0_BUSY_MASK 0x00000020L +#define SPI_DEBUG_BUSY__PS0_BUSY__SHIFT 0x00000005 +#define SPI_DEBUG_BUSY__PS1_BUSY_MASK 0x00000040L +#define SPI_DEBUG_BUSY__PS1_BUSY__SHIFT 0x00000006 +#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY_MASK 0x00001000L +#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY__SHIFT 0x0000000c +#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY_MASK 0x00002000L +#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY__SHIFT 0x0000000d +#define SPI_DEBUG_BUSY__SPIS_BUSY_MASK 0x00020000L +#define SPI_DEBUG_BUSY__SPIS_BUSY__SHIFT 0x00000011 +#define SPI_DEBUG_BUSY__VS_BUSY_MASK 0x00000010L +#define SPI_DEBUG_BUSY__VS_BUSY__SHIFT 0x00000004 +#define SPI_DEBUG_CNTL__DEBUG_GRBM_OVERRIDE_MASK 0x00000001L +#define SPI_DEBUG_CNTL__DEBUG_GRBM_OVERRIDE__SHIFT 0x00000000 +#define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL_MASK 0x000003e0L +#define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL__SHIFT 0x00000005 +#define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL_MASK 0x0e000000L +#define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL__SHIFT 0x00000019 +#define SPI_DEBUG_CNTL__DEBUG_REG_EN_MASK 0x80000000L +#define SPI_DEBUG_CNTL__DEBUG_REG_EN__SHIFT 0x0000001f +#define SPI_DEBUG_CNTL__DEBUG_SH_SEL_MASK 0x00010000L +#define SPI_DEBUG_CNTL__DEBUG_SH_SEL__SHIFT 0x00000010 +#define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL_MASK 0x0000fc00L +#define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL__SHIFT 0x0000000a +#define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL_MASK 0x0000001eL +#define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL__SHIFT 0x00000001 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0_MASK 0x00020000L +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0__SHIFT 0x00000011 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1_MASK 0x00040000L +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1__SHIFT 0x00000012 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_2_MASK 0x00080000L +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_2__SHIFT 0x00000013 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3_MASK 0x00100000L +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3__SHIFT 0x00000014 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_4_MASK 0x00200000L +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_4__SHIFT 0x00000015 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_5_MASK 0x00400000L +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_5__SHIFT 0x00000016 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_6_MASK 0x00800000L +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_6__SHIFT 0x00000017 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_7_MASK 0x01000000L +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_7__SHIFT 0x00000018 +#define SPI_DEBUG_READ__DATA_MASK 0x00ffffffL +#define SPI_DEBUG_READ__DATA__SHIFT 0x00000000 +#define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK 0x0000ff00L +#define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT 0x00000008 +#define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK 0x000000ffL +#define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT 0x00000000 +#define SPI_GDS_CREDITS__UNUSED_MASK 0xffff0000L +#define SPI_GDS_CREDITS__UNUSED__SHIFT 0x00000010 +#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK 0x00000001L +#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x00000000 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK 0x00000002L +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT 0x00000001 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK 0x00003800L +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT 0x0000000b +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK 0x0000001cL +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT 0x00000002 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK 0x000000e0L +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT 0x00000005 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK 0x00000700L +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT 0x00000008 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK 0x00004000L +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT 0x0000000e +#define SPI_LB_CTR_CTRL__LOAD_MASK 0x00000001L +#define SPI_LB_CTR_CTRL__LOAD__SHIFT 0x00000000 +#define SPI_LB_CU_MASK__CU_MASK_MASK 0x0000ffffL +#define SPI_LB_CU_MASK__CU_MASK__SHIFT 0x00000000 +#define SPI_LB_DATA_REG__CNT_DATA_MASK 0xffffffffL +#define SPI_LB_DATA_REG__CNT_DATA__SHIFT 0x00000000 +#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003ffL +#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 +#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L +#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a +#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L +#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000ffc00L +#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a +#define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL +#define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 +#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003ffL +#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x00000000 +#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000ffc00L +#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0x0000000a +#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L +#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000ffc00L +#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0x0000000a +#define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL +#define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 +#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003ffL +#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x00000000 +#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000ffc00L +#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0x0000000a +#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00f00000L +#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000ffc00L +#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0x0000000a +#define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL +#define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 +#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003ffL +#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x00000000 +#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000ffc00L +#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0x0000000a +#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00f00000L +#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000ffc00L +#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0x0000000a +#define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL +#define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 +#define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0x000000f0L +#define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT 0x00000004 +#define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK 0x0000000fL +#define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT 0x00000000 +#define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0x0000f000L +#define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT 0x0000000c +#define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK 0x00000f00L +#define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT 0x00000008 +#define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK 0x00f00000L +#define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT 0x00000014 +#define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK 0x000f0000L +#define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT 0x00000010 +#define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK 0xf0000000L +#define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT 0x0000001c +#define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0x0f000000L +#define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT 0x00000018 +#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK_MASK 0x0000ffffL +#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK__SHIFT 0x00000000 +#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK 0x00004000L +#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT 0x0000000e +#define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x0000003fL +#define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x00000000 +#define SPI_PS_IN_CONTROL__PARAM_GEN_MASK 0x00000040L +#define SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT 0x00000006 +#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK 0x00002000L +#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT 0x0000000d +#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK 0x00001000L +#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT 0x0000000c +#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK 0x00000020L +#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT 0x00000005 +#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK 0x00000040L +#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT 0x00000006 +#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK 0x00000010L +#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT 0x00000004 +#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L +#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT 0x00000007 +#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK 0x00000002L +#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT 0x00000001 +#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK 0x00000004L +#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT 0x00000002 +#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK 0x00000008L +#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT 0x00000003 +#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK 0x00000001L +#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT 0x00000000 +#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK 0x00008000L +#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT 0x0000000f +#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK 0x00000800L +#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT 0x0000000b +#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK 0x00000100L +#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT 0x00000008 +#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK 0x00000200L +#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT 0x00000009 +#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK 0x00000400L +#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0x0000000a +#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK 0x00004000L +#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT 0x0000000e +#define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK 0x0001e000L +#define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT 0x0000000d +#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_0__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_0__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_0__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT 0x00000011 +#define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK 0x0001e000L +#define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT 0x0000000d +#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_10__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_10__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_10__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT 0x00000011 +#define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK 0x0001e000L +#define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT 0x0000000d +#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_11__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_11__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_11__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT 0x00000011 +#define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK 0x0001e000L +#define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT 0x0000000d +#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_12__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_12__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_12__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT 0x00000011 +#define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK 0x0001e000L +#define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT 0x0000000d +#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_13__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_13__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_13__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT 0x00000011 +#define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK 0x0001e000L +#define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT 0x0000000d +#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_14__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_14__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_14__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT 0x00000011 +#define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK 0x0001e000L +#define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT 0x0000000d +#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_15__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_15__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_15__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT 0x00000011 +#define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK 0x0001e000L +#define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT 0x0000000d +#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_16__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_16__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_16__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT 0x00000011 +#define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK 0x0001e000L +#define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT 0x0000000d +#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_17__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_17__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_17__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT 0x00000011 +#define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK 0x0001e000L +#define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT 0x0000000d +#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_18__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_18__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_18__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT 0x00000011 +#define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK 0x0001e000L +#define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT 0x0000000d +#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_19__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_19__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_19__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT 0x00000011 +#define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x0001e000L +#define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT 0x0000000d +#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_1__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_1__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_1__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT 0x00000011 +#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_20__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_20__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_20__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_21__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_21__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_21__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_22__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_22__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_22__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_23__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_23__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_23__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_24__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_24__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_24__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_25__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_25__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_25__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_26__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_26__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_26__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_27__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_27__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_27__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_28__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_28__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_28__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_29__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_29__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_29__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK 0x0001e000L +#define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT 0x0000000d +#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_2__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_2__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_2__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT 0x00000011 +#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_30__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_30__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_30__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_31__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_31__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_31__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK 0x0001e000L +#define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT 0x0000000d +#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_3__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_3__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_3__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT 0x00000011 +#define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK 0x0001e000L +#define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT 0x0000000d +#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_4__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_4__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_4__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT 0x00000011 +#define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK 0x0001e000L +#define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT 0x0000000d +#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_5__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_5__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_5__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT 0x00000011 +#define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK 0x0001e000L +#define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT 0x0000000d +#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_6__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_6__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_6__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT 0x00000011 +#define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK 0x0001e000L +#define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT 0x0000000d +#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_7__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_7__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_7__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT 0x00000011 +#define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK 0x0001e000L +#define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT 0x0000000d +#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_8__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_8__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_8__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT 0x00000011 +#define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK 0x0001e000L +#define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT 0x0000000d +#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_9__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_9__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_9__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT 0x00000011 +#define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK 0x00002000L +#define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT 0x0000000d +#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK 0x00001000L +#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT 0x0000000c +#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK 0x00000020L +#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT 0x00000005 +#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK 0x00000040L +#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT 0x00000006 +#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK 0x00000010L +#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT 0x00000004 +#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L +#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT 0x00000007 +#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK 0x00000002L +#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT 0x00000001 +#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK 0x00000004L +#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT 0x00000002 +#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK 0x00000008L +#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT 0x00000003 +#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK 0x00000001L +#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT 0x00000000 +#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK 0x00008000L +#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT 0x0000000f +#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK 0x00000800L +#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT 0x0000000b +#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK 0x00000100L +#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT 0x00000008 +#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK 0x00000200L +#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT 0x00000009 +#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK 0x00000400L +#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0x0000000a +#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK 0x00004000L +#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT 0x0000000e +#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000fffL +#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x00000000 +#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK 0x0000000fL +#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT 0x00000000 +#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK 0x000000f0L +#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT 0x00000004 +#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK 0x00000f00L +#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT 0x00000008 +#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK 0x0000f000L +#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT 0x0000000c +#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK 0x000f0000L +#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT 0x00000010 +#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK 0x00f00000L +#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT 0x00000014 +#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK 0x0f000000L +#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT 0x00000018 +#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK 0xf0000000L +#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT 0x0000001c +#define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK 0x000000ffL +#define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK 0x000000ffL +#define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK 0x000000ffL +#define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK 0x000000ffL +#define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK 0x000000ffL +#define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_PGM_HI_VS__MEM_BASE_MASK 0x000000ffL +#define SPI_SHADER_PGM_HI_VS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK 0xffffffffL +#define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK 0xffffffffL +#define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK 0xffffffffL +#define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK 0xffffffffL +#define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK 0xffffffffL +#define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_PGM_LO_VS__MEM_BASE_MASK 0xffffffffL +#define SPI_SHADER_PGM_LO_VS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_PGM_RSRC1_ES__CACHE_CTL_MASK 0x38000000L +#define SPI_SHADER_PGM_RSRC1_ES__CACHE_CTL__SHIFT 0x0000001b +#define SPI_SHADER_PGM_RSRC1_ES__CDBG_USER_MASK 0x40000000L +#define SPI_SHADER_PGM_RSRC1_ES__CDBG_USER__SHIFT 0x0000001e +#define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE_MASK 0x04000000L +#define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE__SHIFT 0x0000001a +#define SPI_SHADER_PGM_RSRC1_ES__DEBUG_MODE_MASK 0x00400000L +#define SPI_SHADER_PGM_RSRC1_ES__DEBUG_MODE__SHIFT 0x00000016 +#define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP_MASK 0x00200000L +#define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP__SHIFT 0x00000015 +#define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE_MASK 0x000ff000L +#define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE__SHIFT 0x0000000c +#define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE_MASK 0x00800000L +#define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE__SHIFT 0x00000017 +#define SPI_SHADER_PGM_RSRC1_ES__PRIORITY_MASK 0x00000c00L +#define SPI_SHADER_PGM_RSRC1_ES__PRIORITY__SHIFT 0x0000000a +#define SPI_SHADER_PGM_RSRC1_ES__PRIV_MASK 0x00100000L +#define SPI_SHADER_PGM_RSRC1_ES__PRIV__SHIFT 0x00000014 +#define SPI_SHADER_PGM_RSRC1_ES__SGPRS_MASK 0x000003c0L +#define SPI_SHADER_PGM_RSRC1_ES__SGPRS__SHIFT 0x00000006 +#define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT_MASK 0x03000000L +#define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT__SHIFT 0x00000018 +#define SPI_SHADER_PGM_RSRC1_ES__VGPRS_MASK 0x0000003fL +#define SPI_SHADER_PGM_RSRC1_ES__VGPRS__SHIFT 0x00000000 +#define SPI_SHADER_PGM_RSRC1_GS__CACHE_CTL_MASK 0x0e000000L +#define SPI_SHADER_PGM_RSRC1_GS__CACHE_CTL__SHIFT 0x00000019 +#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER_MASK 0x10000000L +#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER__SHIFT 0x0000001c +#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK 0x01000000L +#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT 0x00000018 +#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE_MASK 0x00400000L +#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE__SHIFT 0x00000016 +#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK 0x00200000L +#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT 0x00000015 +#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK 0x000ff000L +#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT 0x0000000c +#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK 0x00800000L +#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT 0x00000017 +#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK 0x00000c00L +#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT 0x0000000a +#define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK 0x00100000L +#define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT 0x00000014 +#define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK 0x000003c0L +#define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT 0x00000006 +#define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK 0x0000003fL +#define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT 0x00000000 +#define SPI_SHADER_PGM_RSRC1_HS__CACHE_CTL_MASK 0x07000000L +#define SPI_SHADER_PGM_RSRC1_HS__CACHE_CTL__SHIFT 0x00000018 +#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER_MASK 0x08000000L +#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER__SHIFT 0x0000001b +#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE_MASK 0x00400000L +#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE__SHIFT 0x00000016 +#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK 0x00200000L +#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT 0x00000015 +#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK 0x000ff000L +#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT 0x0000000c +#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK 0x00800000L +#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT 0x00000017 +#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK 0x00000c00L +#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT 0x0000000a +#define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK 0x00100000L +#define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT 0x00000014 +#define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK 0x000003c0L +#define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT 0x00000006 +#define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK 0x0000003fL +#define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT 0x00000000 +#define SPI_SHADER_PGM_RSRC1_LS__CACHE_CTL_MASK 0x1c000000L +#define SPI_SHADER_PGM_RSRC1_LS__CACHE_CTL__SHIFT 0x0000001a +#define SPI_SHADER_PGM_RSRC1_LS__CDBG_USER_MASK 0x20000000L +#define SPI_SHADER_PGM_RSRC1_LS__CDBG_USER__SHIFT 0x0000001d +#define SPI_SHADER_PGM_RSRC1_LS__DEBUG_MODE_MASK 0x00400000L +#define SPI_SHADER_PGM_RSRC1_LS__DEBUG_MODE__SHIFT 0x00000016 +#define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP_MASK 0x00200000L +#define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP__SHIFT 0x00000015 +#define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE_MASK 0x000ff000L +#define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE__SHIFT 0x0000000c +#define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE_MASK 0x00800000L +#define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE__SHIFT 0x00000017 +#define SPI_SHADER_PGM_RSRC1_LS__PRIORITY_MASK 0x00000c00L +#define SPI_SHADER_PGM_RSRC1_LS__PRIORITY__SHIFT 0x0000000a +#define SPI_SHADER_PGM_RSRC1_LS__PRIV_MASK 0x00100000L +#define SPI_SHADER_PGM_RSRC1_LS__PRIV__SHIFT 0x00000014 +#define SPI_SHADER_PGM_RSRC1_LS__SGPRS_MASK 0x000003c0L +#define SPI_SHADER_PGM_RSRC1_LS__SGPRS__SHIFT 0x00000006 +#define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT_MASK 0x03000000L +#define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT__SHIFT 0x00000018 +#define SPI_SHADER_PGM_RSRC1_LS__VGPRS_MASK 0x0000003fL +#define SPI_SHADER_PGM_RSRC1_LS__VGPRS__SHIFT 0x00000000 +#define SPI_SHADER_PGM_RSRC1_PS__CACHE_CTL_MASK 0x0e000000L +#define SPI_SHADER_PGM_RSRC1_PS__CACHE_CTL__SHIFT 0x00000019 +#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER_MASK 0x10000000L +#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER__SHIFT 0x0000001c +#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK 0x01000000L +#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT 0x00000018 +#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE_MASK 0x00400000L +#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE__SHIFT 0x00000016 +#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK 0x00200000L +#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT 0x00000015 +#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK 0x000ff000L +#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT 0x0000000c +#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK 0x00800000L +#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT 0x00000017 +#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK 0x00000c00L +#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT 0x0000000a +#define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK 0x00100000L +#define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT 0x00000014 +#define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK 0x000003c0L +#define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT 0x00000006 +#define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK 0x0000003fL +#define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT 0x00000000 +#define SPI_SHADER_PGM_RSRC1_VS__CACHE_CTL_MASK 0x38000000L +#define SPI_SHADER_PGM_RSRC1_VS__CACHE_CTL__SHIFT 0x0000001b +#define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER_MASK 0x40000000L +#define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER__SHIFT 0x0000001e +#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE_MASK 0x04000000L +#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE__SHIFT 0x0000001a +#define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE_MASK 0x00400000L +#define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE__SHIFT 0x00000016 +#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP_MASK 0x00200000L +#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP__SHIFT 0x00000015 +#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE_MASK 0x000ff000L +#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE__SHIFT 0x0000000c +#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE_MASK 0x00800000L +#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE__SHIFT 0x00000017 +#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY_MASK 0x00000c00L +#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT 0x0000000a +#define SPI_SHADER_PGM_RSRC1_VS__PRIV_MASK 0x00100000L +#define SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT 0x00000014 +#define SPI_SHADER_PGM_RSRC1_VS__SGPRS_MASK 0x000003c0L +#define SPI_SHADER_PGM_RSRC1_VS__SGPRS__SHIFT 0x00000006 +#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT_MASK 0x03000000L +#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT__SHIFT 0x00000018 +#define SPI_SHADER_PGM_RSRC1_VS__VGPRS_MASK 0x0000003fL +#define SPI_SHADER_PGM_RSRC1_VS__VGPRS__SHIFT 0x00000000 +#define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN_MASK 0x00007f00L +#define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN__SHIFT 0x00000008 +#define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN_MASK 0x0001ff00L +#define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN__SHIFT 0x00000008 +#define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE_MASK 0x1ff00000L +#define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE__SHIFT 0x00000014 +#define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN_MASK 0x00000080L +#define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN__SHIFT 0x00000007 +#define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN__SHIFT 0x00000000 +#define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT_MASK 0x00000040L +#define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT__SHIFT 0x00000006 +#define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR_MASK 0x0000003eL +#define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR__SHIFT 0x00000001 +#define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE_MASK 0x1ff00000L +#define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE__SHIFT 0x00000014 +#define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN_MASK 0x00000080L +#define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN__SHIFT 0x00000007 +#define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN__SHIFT 0x00000000 +#define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT_MASK 0x00000040L +#define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT__SHIFT 0x00000006 +#define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR_MASK 0x0000003eL +#define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR__SHIFT 0x00000001 +#define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN_MASK 0x0001ff00L +#define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN__SHIFT 0x00000008 +#define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE_MASK 0x1ff00000L +#define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE__SHIFT 0x00000014 +#define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN_MASK 0x00000080L +#define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN__SHIFT 0x00000007 +#define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN__SHIFT 0x00000000 +#define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT_MASK 0x00000040L +#define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT__SHIFT 0x00000006 +#define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR_MASK 0x0000003eL +#define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR__SHIFT 0x00000001 +#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK 0x00003f80L +#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT 0x00000007 +#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT 0x00000000 +#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK 0x00000040L +#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT 0x00000006 +#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK 0x0000003eL +#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT 0x00000001 +#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK 0x0000fe00L +#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT 0x00000009 +#define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN_MASK 0x00000080L +#define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN__SHIFT 0x00000007 +#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT 0x00000000 +#define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN_MASK 0x00000100L +#define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN__SHIFT 0x00000008 +#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK 0x00000040L +#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT 0x00000006 +#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK 0x0000003eL +#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT 0x00000001 +#define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN_MASK 0x01ff0000L +#define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN__SHIFT 0x00000010 +#define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE_MASK 0x0000ff80L +#define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE__SHIFT 0x00000007 +#define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN__SHIFT 0x00000000 +#define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT_MASK 0x00000040L +#define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT__SHIFT 0x00000006 +#define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR_MASK 0x0000003eL +#define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR__SHIFT 0x00000001 +#define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN_MASK 0x007f0000L +#define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN__SHIFT 0x00000010 +#define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN_MASK 0x01ff0000L +#define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN__SHIFT 0x00000010 +#define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE_MASK 0x0000ff80L +#define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE__SHIFT 0x00000007 +#define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN__SHIFT 0x00000000 +#define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT_MASK 0x00000040L +#define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT__SHIFT 0x00000006 +#define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR_MASK 0x0000003eL +#define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR__SHIFT 0x00000001 +#define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE_MASK 0x0000ff80L +#define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE__SHIFT 0x00000007 +#define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN__SHIFT 0x00000000 +#define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT_MASK 0x00000040L +#define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT__SHIFT 0x00000006 +#define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR_MASK 0x0000003eL +#define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR__SHIFT 0x00000001 +#define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN_MASK 0x01ff0000L +#define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN__SHIFT 0x00000010 +#define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE_MASK 0x0000ff80L +#define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE__SHIFT 0x00000007 +#define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN__SHIFT 0x00000000 +#define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT_MASK 0x00000040L +#define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT__SHIFT 0x00000006 +#define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR_MASK 0x0000003eL +#define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR__SHIFT 0x00000001 +#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK 0x007f0000L +#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT 0x00000010 +#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK 0x0000ff00L +#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT 0x00000008 +#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT 0x00000000 +#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK 0x00000040L +#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT 0x00000006 +#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK 0x0000003eL +#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT 0x00000001 +#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK 0x00000080L +#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT 0x00000007 +#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK 0x000fe000L +#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN__SHIFT 0x0000000d +#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN_MASK 0x00000080L +#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN__SHIFT 0x00000007 +#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN__SHIFT 0x00000000 +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN_MASK 0x00000100L +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN__SHIFT 0x00000008 +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN_MASK 0x00000200L +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN__SHIFT 0x00000009 +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN_MASK 0x00000400L +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT 0x0000000a +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN_MASK 0x00000800L +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN__SHIFT 0x0000000b +#define SPI_SHADER_PGM_RSRC2_VS__SO_EN_MASK 0x00001000L +#define SPI_SHADER_PGM_RSRC2_VS__SO_EN__SHIFT 0x0000000c +#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT_MASK 0x00000040L +#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT__SHIFT 0x00000006 +#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MASK 0x0000003eL +#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR__SHIFT 0x00000001 +#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK 0x0000000fL +#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT 0x00000000 +#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK 0x000000f0L +#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT 0x00000004 +#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK 0x00000f00L +#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT 0x00000008 +#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK 0x0000f000L +#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT 0x0000000c +#define SPI_SHADER_TBA_HI_ES__MEM_BASE_MASK 0x000000ffL +#define SPI_SHADER_TBA_HI_ES__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_TBA_HI_GS__MEM_BASE_MASK 0x000000ffL +#define SPI_SHADER_TBA_HI_GS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_TBA_HI_HS__MEM_BASE_MASK 0x000000ffL +#define SPI_SHADER_TBA_HI_HS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_TBA_HI_LS__MEM_BASE_MASK 0x000000ffL +#define SPI_SHADER_TBA_HI_LS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_TBA_HI_PS__MEM_BASE_MASK 0x000000ffL +#define SPI_SHADER_TBA_HI_PS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_TBA_HI_VS__MEM_BASE_MASK 0x000000ffL +#define SPI_SHADER_TBA_HI_VS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_TBA_LO_ES__MEM_BASE_MASK 0xffffffffL +#define SPI_SHADER_TBA_LO_ES__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_TBA_LO_GS__MEM_BASE_MASK 0xffffffffL +#define SPI_SHADER_TBA_LO_GS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_TBA_LO_HS__MEM_BASE_MASK 0xffffffffL +#define SPI_SHADER_TBA_LO_HS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_TBA_LO_LS__MEM_BASE_MASK 0xffffffffL +#define SPI_SHADER_TBA_LO_LS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_TBA_LO_PS__MEM_BASE_MASK 0xffffffffL +#define SPI_SHADER_TBA_LO_PS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_TBA_LO_VS__MEM_BASE_MASK 0xffffffffL +#define SPI_SHADER_TBA_LO_VS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_TMA_HI_ES__MEM_BASE_MASK 0x000000ffL +#define SPI_SHADER_TMA_HI_ES__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_TMA_HI_GS__MEM_BASE_MASK 0x000000ffL +#define SPI_SHADER_TMA_HI_GS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_TMA_HI_HS__MEM_BASE_MASK 0x000000ffL +#define SPI_SHADER_TMA_HI_HS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_TMA_HI_LS__MEM_BASE_MASK 0x000000ffL +#define SPI_SHADER_TMA_HI_LS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_TMA_HI_PS__MEM_BASE_MASK 0x000000ffL +#define SPI_SHADER_TMA_HI_PS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_TMA_HI_VS__MEM_BASE_MASK 0x000000ffL +#define SPI_SHADER_TMA_HI_VS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_TMA_LO_ES__MEM_BASE_MASK 0xffffffffL +#define SPI_SHADER_TMA_LO_ES__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_TMA_LO_GS__MEM_BASE_MASK 0xffffffffL +#define SPI_SHADER_TMA_LO_GS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_TMA_LO_HS__MEM_BASE_MASK 0xffffffffL +#define SPI_SHADER_TMA_LO_HS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_TMA_LO_LS__MEM_BASE_MASK 0xffffffffL +#define SPI_SHADER_TMA_LO_LS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_TMA_LO_PS__MEM_BASE_MASK 0xffffffffL +#define SPI_SHADER_TMA_LO_PS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_TMA_LO_VS__MEM_BASE_MASK 0xffffffffL +#define SPI_SHADER_TMA_LO_VS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_ES_0__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_ES_0__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_ES_10__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_ES_10__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_ES_11__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_ES_11__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_ES_12__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_ES_12__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_ES_13__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_ES_13__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_ES_14__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_ES_14__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_ES_15__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_ES_15__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_ES_1__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_ES_1__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_ES_2__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_ES_2__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_ES_3__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_ES_3__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_ES_4__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_ES_4__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_ES_5__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_ES_5__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_ES_6__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_ES_6__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_ES_7__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_ES_7__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_ES_8__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_ES_8__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_ES_9__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_ES_9__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_GS_0__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_GS_0__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_GS_10__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_GS_10__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_GS_11__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_GS_11__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_GS_12__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_GS_12__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_GS_13__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_GS_13__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_GS_14__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_GS_14__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_GS_15__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_GS_15__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_GS_1__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_GS_1__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_GS_2__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_GS_2__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_GS_3__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_GS_3__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_GS_4__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_GS_4__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_GS_5__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_GS_5__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_GS_6__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_GS_6__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_GS_7__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_GS_7__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_GS_8__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_GS_8__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_GS_9__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_GS_9__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_HS_0__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_HS_0__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_HS_10__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_HS_10__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_HS_11__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_HS_11__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_HS_12__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_HS_12__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_HS_13__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_HS_13__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_HS_14__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_HS_14__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_HS_15__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_HS_15__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_HS_1__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_HS_1__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_HS_2__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_HS_2__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_HS_3__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_HS_3__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_HS_4__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_HS_4__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_HS_5__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_HS_5__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_HS_6__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_HS_6__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_HS_7__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_HS_7__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_HS_8__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_HS_8__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_HS_9__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_HS_9__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_LS_0__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_LS_0__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_LS_10__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_LS_10__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_LS_11__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_LS_11__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_LS_12__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_LS_12__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_LS_13__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_LS_13__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_LS_14__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_LS_14__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_LS_15__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_LS_15__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_LS_1__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_LS_1__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_LS_2__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_LS_2__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_LS_3__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_LS_3__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_LS_4__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_LS_4__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_LS_5__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_LS_5__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_LS_6__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_LS_6__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_LS_7__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_LS_7__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_LS_8__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_LS_8__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_LS_9__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_LS_9__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_PS_0__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_PS_10__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_PS_11__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_PS_12__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_PS_13__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_PS_14__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_PS_15__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_PS_1__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_PS_2__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_PS_3__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_PS_4__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_PS_5__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_PS_6__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_PS_7__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_PS_8__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_PS_9__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_VS_0__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_VS_0__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_VS_10__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_VS_10__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_VS_11__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_VS_11__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_VS_12__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_VS_12__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_VS_13__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_VS_13__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_VS_14__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_VS_14__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_VS_15__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_VS_15__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_VS_1__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_VS_1__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_VS_2__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_VS_2__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_VS_3__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_VS_3__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_VS_4__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_VS_4__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_VS_5__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_VS_5__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_VS_6__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_VS_6__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_VS_7__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_VS_7__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_VS_8__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_VS_8__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_VS_9__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_VS_9__DATA__SHIFT 0x00000000 +#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK 0x0000000fL +#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT 0x00000000 +#define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY_MASK 0x00000004L +#define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY__SHIFT 0x00000002 +#define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY_MASK 0x00200000L +#define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY__SHIFT 0x00000015 +#define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY_MASK 0x00000008L +#define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY__SHIFT 0x00000003 +#define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY_MASK 0x00000002L +#define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY__SHIFT 0x00000001 +#define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY_MASK 0x00000001L +#define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY__SHIFT 0x00000000 +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY_MASK 0x00000200L +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY__SHIFT 0x00000009 +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY_MASK 0x00000400L +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY__SHIFT 0x0000000a +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC02_BUSY_MASK 0x00000800L +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC02_BUSY__SHIFT 0x0000000b +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC03_BUSY_MASK 0x00001000L +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC03_BUSY__SHIFT 0x0000000c +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC10_BUSY_MASK 0x00002000L +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC10_BUSY__SHIFT 0x0000000d +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC11_BUSY_MASK 0x00004000L +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC11_BUSY__SHIFT 0x0000000e +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC12_BUSY_MASK 0x00008000L +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC12_BUSY__SHIFT 0x0000000f +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC13_BUSY_MASK 0x00010000L +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC13_BUSY__SHIFT 0x00000010 +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY_MASK 0x00000020L +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY__SHIFT 0x00000005 +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY_MASK 0x00000040L +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY__SHIFT 0x00000006 +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC10_BUSY_MASK 0x00000080L +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC10_BUSY__SHIFT 0x00000007 +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC11_BUSY_MASK 0x00000100L +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC11_BUSY__SHIFT 0x00000008 +#define SPI_SLAVE_DEBUG_BUSY__VS_VTX_BUSY_MASK 0x00000010L +#define SPI_SLAVE_DEBUG_BUSY__VS_VTX_BUSY__SHIFT 0x00000004 +#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER0_BUSY_MASK 0x00020000L +#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER0_BUSY__SHIFT 0x00000011 +#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER1_BUSY_MASK 0x00040000L +#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER1_BUSY__SHIFT 0x00000012 +#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC0_BUSY_MASK 0x00080000L +#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC0_BUSY__SHIFT 0x00000013 +#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC1_BUSY_MASK 0x00100000L +#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC1_BUSY__SHIFT 0x00000014 +#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK 0x0000ffffL +#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT 0x00000000 +#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK 0xffff0000L +#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT 0x00000010 +#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK 0x0000ffffL +#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT 0x00000000 +#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK 0xffff0000L +#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT 0x00000010 +#define SPI_TMPRING_SIZE__WAVESIZE_MASK 0x01fff000L +#define SPI_TMPRING_SIZE__WAVESIZE__SHIFT 0x0000000c +#define SPI_TMPRING_SIZE__WAVES_MASK 0x00000fffL +#define SPI_TMPRING_SIZE__WAVES__SHIFT 0x00000000 +#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK 0x0000003eL +#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT 0x00000001 +#define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK 0x00000040L +#define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT 0x00000006 +#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000ffffL +#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x00000000 +#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000L +#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x00000010 +#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS_MASK 0xffffffffL +#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x00000000 +#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x0000ffffL +#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x00000000 +#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE_MASK 0x40000000L +#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE__SHIFT 0x0000001e +#define SQ_BUF_RSRC_WORD1__STRIDE_MASK 0x3fff0000L +#define SQ_BUF_RSRC_WORD1__STRIDE__SHIFT 0x00000010 +#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE_MASK 0x80000000L +#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE__SHIFT 0x0000001f +#define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 0xffffffffL +#define SQ_BUF_RSRC_WORD2__NUM_RECORDS__SHIFT 0x00000000 +#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE_MASK 0x00800000L +#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE__SHIFT 0x00000017 +#define SQ_BUF_RSRC_WORD3__ATC_MASK 0x01000000L +#define SQ_BUF_RSRC_WORD3__ATC__SHIFT 0x00000018 +#define SQ_BUF_RSRC_WORD3__DATA_FORMAT_MASK 0x00078000L +#define SQ_BUF_RSRC_WORD3__DATA_FORMAT__SHIFT 0x0000000f +#define SQ_BUF_RSRC_WORD3__DST_SEL_W_MASK 0x00000e00L +#define SQ_BUF_RSRC_WORD3__DST_SEL_W__SHIFT 0x00000009 +#define SQ_BUF_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L +#define SQ_BUF_RSRC_WORD3__DST_SEL_X__SHIFT 0x00000000 +#define SQ_BUF_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L +#define SQ_BUF_RSRC_WORD3__DST_SEL_Y__SHIFT 0x00000003 +#define SQ_BUF_RSRC_WORD3__DST_SEL_Z_MASK 0x000001c0L +#define SQ_BUF_RSRC_WORD3__DST_SEL_Z__SHIFT 0x00000006 +#define SQ_BUF_RSRC_WORD3__ELEMENT_SIZE_MASK 0x00180000L +#define SQ_BUF_RSRC_WORD3__ELEMENT_SIZE__SHIFT 0x00000013 +#define SQ_BUF_RSRC_WORD3__HASH_ENABLE_MASK 0x02000000L +#define SQ_BUF_RSRC_WORD3__HASH_ENABLE__SHIFT 0x00000019 +#define SQ_BUF_RSRC_WORD3__HEAP_MASK 0x04000000L +#define SQ_BUF_RSRC_WORD3__HEAP__SHIFT 0x0000001a +#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE_MASK 0x00600000L +#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE__SHIFT 0x00000015 +#define SQ_BUF_RSRC_WORD3__MTYPE_MASK 0x38000000L +#define SQ_BUF_RSRC_WORD3__MTYPE__SHIFT 0x0000001b +#define SQ_BUF_RSRC_WORD3__NUM_FORMAT_MASK 0x00007000L +#define SQ_BUF_RSRC_WORD3__NUM_FORMAT__SHIFT 0x0000000c +#define SQ_BUF_RSRC_WORD3__TYPE_MASK 0xc0000000L +#define SQ_BUF_RSRC_WORD3__TYPE__SHIFT 0x0000001e +#define SQC_CACHES__DATA_INVALIDATE_MASK 0x00000002L +#define SQC_CACHES__DATA_INVALIDATE__SHIFT 0x00000001 +#define SQC_CACHES__INST_INVALIDATE_MASK 0x00000001L +#define SQC_CACHES__INST_INVALIDATE__SHIFT 0x00000000 +#define SQC_CACHES__INVALIDATE_VOLATILE_MASK 0x00000004L +#define SQC_CACHES__INVALIDATE_VOLATILE__SHIFT 0x00000002 +#define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0x0000000cL +#define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x00000002 +#define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x00000080L +#define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x00000007 +#define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x00000100L +#define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x00000008 +#define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x00000040L +#define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x00000006 +#define SQC_CONFIG__IDENTITY_HASH_BANK_MASK 0x00000200L +#define SQC_CONFIG__IDENTITY_HASH_BANK__SHIFT 0x00000009 +#define SQC_CONFIG__IDENTITY_HASH_SET_MASK 0x00000400L +#define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT 0x0000000a +#define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x00000003L +#define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x00000000 +#define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x00000030L +#define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x00000004 +#define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK 0x00000800L +#define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT 0x0000000b +#define SQ_CONFIG__DEBUG_EN_MASK 0x00000100L +#define SQ_CONFIG__DEBUG_EN__SHIFT 0x00000008 +#define SQ_CONFIG__DISABLE_IB_DEP_CHECK_MASK 0x00000400L +#define SQ_CONFIG__DISABLE_IB_DEP_CHECK__SHIFT 0x0000000a +#define SQ_CONFIG__DISABLE_SCA_BYPASS_MASK 0x00000200L +#define SQ_CONFIG__DISABLE_SCA_BYPASS__SHIFT 0x00000009 +#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE_MASK 0x00008000L +#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE__SHIFT 0x0000000f +#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE_MASK 0x00002000L +#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE__SHIFT 0x0000000d +#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE_MASK 0x00004000L +#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE__SHIFT 0x0000000e +#define SQ_CONFIG__EARLY_TA_DONE_DISABLE_MASK 0x00001000L +#define SQ_CONFIG__EARLY_TA_DONE_DISABLE__SHIFT 0x0000000c +#define SQ_CONFIG__ENABLE_SOFT_CLAUSE_MASK 0x00000800L +#define SQ_CONFIG__ENABLE_SOFT_CLAUSE__SHIFT 0x0000000b +#define SQ_CONFIG__UNUSED_MASK 0x000000ffL +#define SQ_CONFIG__UNUSED__SHIFT 0x00000000 +#define SQC_SECDED_CNT__DATA_DED_MASK 0xff000000L +#define SQC_SECDED_CNT__DATA_DED__SHIFT 0x00000018 +#define SQC_SECDED_CNT__DATA_SEC_MASK 0x00ff0000L +#define SQC_SECDED_CNT__DATA_SEC__SHIFT 0x00000010 +#define SQC_SECDED_CNT__INST_DED_MASK 0x0000ff00L +#define SQC_SECDED_CNT__INST_DED__SHIFT 0x00000008 +#define SQC_SECDED_CNT__INST_SEC_MASK 0x000000ffL +#define SQC_SECDED_CNT__INST_SEC__SHIFT 0x00000000 +#define SQ_DEBUG_CTRL_LOCAL__UNUSED_MASK 0x000000ffL +#define SQ_DEBUG_CTRL_LOCAL__UNUSED__SHIFT 0x00000000 +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0x000000ffL +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x00000000 +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK 0x0000ff00L +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT 0x00000008 +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST_MASK 0xff000000L +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST__SHIFT 0x00000018 +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED_MASK 0x00ff0000L +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED__SHIFT 0x00000010 +#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD_MASK 0x0000000fL +#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD__SHIFT 0x00000000 +#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG_MASK 0x000000f0L +#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG__SHIFT 0x00000004 +#define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x00000001L +#define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x00000000 +#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK 0x00000002L +#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT 0x00000001 +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0_MASK 0x0000fff0L +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0__SHIFT 0x00000004 +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1_MASK 0x0fff0000L +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1__SHIFT 0x00000010 +#define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x00000001L +#define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x00000000 +#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK 0x000003f0L +#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT 0x00000004 +#define SQ_DED_CNT__LDS_DED_MASK 0x0000003fL +#define SQ_DED_CNT__LDS_DED__SHIFT 0x00000000 +#define SQ_DED_CNT__SGPR_DED_MASK 0x00001f00L +#define SQ_DED_CNT__SGPR_DED__SHIFT 0x00000008 +#define SQ_DED_CNT__VGPR_DED_MASK 0x01ff0000L +#define SQ_DED_CNT__VGPR_DED__SHIFT 0x00000010 +#define SQ_DED_INFO__SIMD_ID_MASK 0x00000030L +#define SQ_DED_INFO__SIMD_ID__SHIFT 0x00000004 +#define SQ_DED_INFO__SOURCE_MASK 0x000001c0L +#define SQ_DED_INFO__SOURCE__SHIFT 0x00000006 +#define SQ_DED_INFO__VM_ID_MASK 0x00001e00L +#define SQ_DED_INFO__VM_ID__SHIFT 0x00000009 +#define SQ_DED_INFO__WAVE_ID_MASK 0x0000000fL +#define SQ_DED_INFO__WAVE_ID__SHIFT 0x00000000 +#define SQ_DS_0__ENCODING_MASK 0xfc000000L +#define SQ_DS_0__ENCODING__SHIFT 0x0000001a +#define SQ_DS_0__GDS_MASK 0x00020000L +#define SQ_DS_0__GDS__SHIFT 0x00000011 +#define SQ_DS_0__OFFSET0_MASK 0x000000ffL +#define SQ_DS_0__OFFSET0__SHIFT 0x00000000 +#define SQ_DS_0__OFFSET1_MASK 0x0000ff00L +#define SQ_DS_0__OFFSET1__SHIFT 0x00000008 +#define SQ_DS_0__OP_MASK 0x03fc0000L +#define SQ_DS_0__OP__SHIFT 0x00000012 +#define SQ_DS_1__ADDR_MASK 0x000000ffL +#define SQ_DS_1__ADDR__SHIFT 0x00000000 +#define SQ_DS_1__DATA0_MASK 0x0000ff00L +#define SQ_DS_1__DATA0__SHIFT 0x00000008 +#define SQ_DS_1__DATA1_MASK 0x00ff0000L +#define SQ_DS_1__DATA1__SHIFT 0x00000010 +#define SQ_DS_1__VDST_MASK 0xff000000L +#define SQ_DS_1__VDST__SHIFT 0x00000018 +#define SQ_EXP_0__COMPR_MASK 0x00000400L +#define SQ_EXP_0__COMPR__SHIFT 0x0000000a +#define SQ_EXP_0__DONE_MASK 0x00000800L +#define SQ_EXP_0__DONE__SHIFT 0x0000000b +#define SQ_EXP_0__ENCODING_MASK 0xfc000000L +#define SQ_EXP_0__ENCODING__SHIFT 0x0000001a +#define SQ_EXP_0__EN_MASK 0x0000000fL +#define SQ_EXP_0__EN__SHIFT 0x00000000 +#define SQ_EXP_0__TGT_MASK 0x000003f0L +#define SQ_EXP_0__TGT__SHIFT 0x00000004 +#define SQ_EXP_0__VM_MASK 0x00001000L +#define SQ_EXP_0__VM__SHIFT 0x0000000c +#define SQ_EXP_1__VSRC0_MASK 0x000000ffL +#define SQ_EXP_1__VSRC0__SHIFT 0x00000000 +#define SQ_EXP_1__VSRC1_MASK 0x0000ff00L +#define SQ_EXP_1__VSRC1__SHIFT 0x00000008 +#define SQ_EXP_1__VSRC2_MASK 0x00ff0000L +#define SQ_EXP_1__VSRC2__SHIFT 0x00000010 +#define SQ_EXP_1__VSRC3_MASK 0xff000000L +#define SQ_EXP_1__VSRC3__SHIFT 0x00000018 +#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE_MASK 0x00030000L +#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE__SHIFT 0x00000010 +#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0x0000000fL +#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x00000000 +#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0x00000f00L +#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x00000008 +#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0x000c0000L +#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x00000012 +#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS_MASK 0xffffffffL +#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x00000000 +#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x000000ffL +#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x00000000 +#define SQ_IMG_RSRC_WORD1__DATA_FORMAT_MASK 0x03f00000L +#define SQ_IMG_RSRC_WORD1__DATA_FORMAT__SHIFT 0x00000014 +#define SQ_IMG_RSRC_WORD1__MIN_LOD_MASK 0x000fff00L +#define SQ_IMG_RSRC_WORD1__MIN_LOD__SHIFT 0x00000008 +#define SQ_IMG_RSRC_WORD1__MTYPE_MASK 0xc0000000L +#define SQ_IMG_RSRC_WORD1__MTYPE__SHIFT 0x0000001e +#define SQ_IMG_RSRC_WORD1__NUM_FORMAT_MASK 0x3c000000L +#define SQ_IMG_RSRC_WORD1__NUM_FORMAT__SHIFT 0x0000001a +#define SQ_IMG_RSRC_WORD2__HEIGHT_MASK 0x0fffc000L +#define SQ_IMG_RSRC_WORD2__HEIGHT__SHIFT 0x0000000e +#define SQ_IMG_RSRC_WORD2__INTERLACED_MASK 0x80000000L +#define SQ_IMG_RSRC_WORD2__INTERLACED__SHIFT 0x0000001f +#define SQ_IMG_RSRC_WORD2__PERF_MOD_MASK 0x70000000L +#define SQ_IMG_RSRC_WORD2__PERF_MOD__SHIFT 0x0000001c +#define SQ_IMG_RSRC_WORD2__WIDTH_MASK 0x00003fffL +#define SQ_IMG_RSRC_WORD2__WIDTH__SHIFT 0x00000000 +#define SQ_IMG_RSRC_WORD3__ATC_MASK 0x08000000L +#define SQ_IMG_RSRC_WORD3__ATC__SHIFT 0x0000001b +#define SQ_IMG_RSRC_WORD3__BASE_LEVEL_MASK 0x0000f000L +#define SQ_IMG_RSRC_WORD3__BASE_LEVEL__SHIFT 0x0000000c +#define SQ_IMG_RSRC_WORD3__DST_SEL_W_MASK 0x00000e00L +#define SQ_IMG_RSRC_WORD3__DST_SEL_W__SHIFT 0x00000009 +#define SQ_IMG_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L +#define SQ_IMG_RSRC_WORD3__DST_SEL_X__SHIFT 0x00000000 +#define SQ_IMG_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L +#define SQ_IMG_RSRC_WORD3__DST_SEL_Y__SHIFT 0x00000003 +#define SQ_IMG_RSRC_WORD3__DST_SEL_Z_MASK 0x000001c0L +#define SQ_IMG_RSRC_WORD3__DST_SEL_Z__SHIFT 0x00000006 +#define SQ_IMG_RSRC_WORD3__LAST_LEVEL_MASK 0x000f0000L +#define SQ_IMG_RSRC_WORD3__LAST_LEVEL__SHIFT 0x00000010 +#define SQ_IMG_RSRC_WORD3__MTYPE_MASK 0x04000000L +#define SQ_IMG_RSRC_WORD3__MTYPE__SHIFT 0x0000001a +#define SQ_IMG_RSRC_WORD3__POW2_PAD_MASK 0x02000000L +#define SQ_IMG_RSRC_WORD3__POW2_PAD__SHIFT 0x00000019 +#define SQ_IMG_RSRC_WORD3__TILING_INDEX_MASK 0x01f00000L +#define SQ_IMG_RSRC_WORD3__TILING_INDEX__SHIFT 0x00000014 +#define SQ_IMG_RSRC_WORD3__TYPE_MASK 0xf0000000L +#define SQ_IMG_RSRC_WORD3__TYPE__SHIFT 0x0000001c +#define SQ_IMG_RSRC_WORD4__DEPTH_MASK 0x00001fffL +#define SQ_IMG_RSRC_WORD4__DEPTH__SHIFT 0x00000000 +#define SQ_IMG_RSRC_WORD4__PITCH_MASK 0x07ffe000L +#define SQ_IMG_RSRC_WORD4__PITCH__SHIFT 0x0000000d +#define SQ_IMG_RSRC_WORD5__BASE_ARRAY_MASK 0x00001fffL +#define SQ_IMG_RSRC_WORD5__BASE_ARRAY__SHIFT 0x00000000 +#define SQ_IMG_RSRC_WORD5__LAST_ARRAY_MASK 0x03ffe000L +#define SQ_IMG_RSRC_WORD5__LAST_ARRAY__SHIFT 0x0000000d +#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID_MASK 0x000ff000L +#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID__SHIFT 0x0000000c +#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN_MASK 0x00100000L +#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN__SHIFT 0x00000014 +#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN_MASK 0x00000fffL +#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN__SHIFT 0x00000000 +#define SQ_IMG_RSRC_WORD6__UNUNSED_MASK 0xffe00000L +#define SQ_IMG_RSRC_WORD6__UNUNSED__SHIFT 0x00000015 +#define SQ_IMG_RSRC_WORD7__UNUNSED_MASK 0xffffffffL +#define SQ_IMG_RSRC_WORD7__UNUNSED__SHIFT 0x00000000 +#define SQ_IMG_SAMP_WORD0__ANISO_BIAS_MASK 0x07e00000L +#define SQ_IMG_SAMP_WORD0__ANISO_BIAS__SHIFT 0x00000015 +#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD_MASK 0x00070000L +#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD__SHIFT 0x00000010 +#define SQ_IMG_SAMP_WORD0__CLAMP_X_MASK 0x00000007L +#define SQ_IMG_SAMP_WORD0__CLAMP_X__SHIFT 0x00000000 +#define SQ_IMG_SAMP_WORD0__CLAMP_Y_MASK 0x00000038L +#define SQ_IMG_SAMP_WORD0__CLAMP_Y__SHIFT 0x00000003 +#define SQ_IMG_SAMP_WORD0__CLAMP_Z_MASK 0x000001c0L +#define SQ_IMG_SAMP_WORD0__CLAMP_Z__SHIFT 0x00000006 +#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC_MASK 0x00007000L +#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC__SHIFT 0x0000000c +#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP_MASK 0x10000000L +#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP__SHIFT 0x0000001c +#define SQ_IMG_SAMP_WORD0__FILTER_MODE_MASK 0x60000000L +#define SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT 0x0000001d +#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA_MASK 0x00100000L +#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA__SHIFT 0x00000014 +#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED_MASK 0x00008000L +#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED__SHIFT 0x0000000f +#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO_MASK 0x00000e00L +#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO__SHIFT 0x00000009 +#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC_MASK 0x00080000L +#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC__SHIFT 0x00000013 +#define SQ_IMG_SAMP_WORD0__TRUNC_COORD_MASK 0x08000000L +#define SQ_IMG_SAMP_WORD0__TRUNC_COORD__SHIFT 0x0000001b +#define SQ_IMG_SAMP_WORD1__MAX_LOD_MASK 0x00fff000L +#define SQ_IMG_SAMP_WORD1__MAX_LOD__SHIFT 0x0000000c +#define SQ_IMG_SAMP_WORD1__MIN_LOD_MASK 0x00000fffL +#define SQ_IMG_SAMP_WORD1__MIN_LOD__SHIFT 0x00000000 +#define SQ_IMG_SAMP_WORD1__PERF_MIP_MASK 0x0f000000L +#define SQ_IMG_SAMP_WORD1__PERF_MIP__SHIFT 0x00000018 +#define SQ_IMG_SAMP_WORD1__PERF_Z_MASK 0xf0000000L +#define SQ_IMG_SAMP_WORD1__PERF_Z__SHIFT 0x0000001c +#define SQ_IMG_SAMP_WORD2__DISABLE_LSB_CEIL_MASK 0x20000000L +#define SQ_IMG_SAMP_WORD2__DISABLE_LSB_CEIL__SHIFT 0x0000001d +#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX_MASK 0x40000000L +#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX__SHIFT 0x0000001e +#define SQ_IMG_SAMP_WORD2__LOD_BIAS_MASK 0x00003fffL +#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC_MASK 0x000fc000L +#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC__SHIFT 0x0000000e +#define SQ_IMG_SAMP_WORD2__LOD_BIAS__SHIFT 0x00000000 +#define SQ_IMG_SAMP_WORD2__MIP_FILTER_MASK 0x0c000000L +#define SQ_IMG_SAMP_WORD2__MIP_FILTER__SHIFT 0x0000001a +#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP_MASK 0x10000000L +#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP__SHIFT 0x0000001c +#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER_MASK 0x00300000L +#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER__SHIFT 0x00000014 +#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER_MASK 0x00c00000L +#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER__SHIFT 0x00000016 +#define SQ_IMG_SAMP_WORD2__Z_FILTER_MASK 0x03000000L +#define SQ_IMG_SAMP_WORD2__Z_FILTER__SHIFT 0x00000018 +#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR_MASK 0x00000fffL +#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR__SHIFT 0x00000000 +#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE_MASK 0xc0000000L +#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE__SHIFT 0x0000001e +#define SQ_IND_DATA__DATA_MASK 0xffffffffL +#define SQ_IND_DATA__DATA__SHIFT 0x00000000 +#define SQ_IND_INDEX__AUTO_INCR_MASK 0x00001000L +#define SQ_IND_INDEX__AUTO_INCR__SHIFT 0x0000000c +#define SQ_IND_INDEX__FORCE_READ_MASK 0x00002000L +#define SQ_IND_INDEX__FORCE_READ__SHIFT 0x0000000d +#define SQ_IND_INDEX__INDEX_MASK 0xffff0000L +#define SQ_IND_INDEX__INDEX__SHIFT 0x00000010 +#define SQ_IND_INDEX__READ_TIMEOUT_MASK 0x00004000L +#define SQ_IND_INDEX__READ_TIMEOUT__SHIFT 0x0000000e +#define SQ_IND_INDEX__SIMD_ID_MASK 0x00000030L +#define SQ_IND_INDEX__SIMD_ID__SHIFT 0x00000004 +#define SQ_IND_INDEX__THREAD_ID_MASK 0x00000fc0L +#define SQ_IND_INDEX__THREAD_ID__SHIFT 0x00000006 +#define SQ_IND_INDEX__UNINDEXED_MASK 0x00008000L +#define SQ_IND_INDEX__UNINDEXED__SHIFT 0x0000000f +#define SQ_IND_INDEX__WAVE_ID_MASK 0x0000000fL +#define SQ_IND_INDEX__WAVE_ID__SHIFT 0x00000000 +#define SQ_INST__ENCODING_MASK 0xffffffffL +#define SQ_INST__ENCODING__SHIFT 0x00000000 +#define SQ_INTERRUPT_WORD_AUTO__CMD_TIMESTAMP_MASK 0x00000010L +#define SQ_INTERRUPT_WORD_AUTO__CMD_TIMESTAMP__SHIFT 0x00000004 +#define SQ_INTERRUPT_WORD_AUTO__ENCODING_MASK 0x0c000000L +#define SQ_INTERRUPT_WORD_AUTO__ENCODING__SHIFT 0x0000001a +#define SQ_INTERRUPT_WORD_AUTO__HOST_CMD_OVERFLOW_MASK 0x00000020L +#define SQ_INTERRUPT_WORD_AUTO__HOST_CMD_OVERFLOW__SHIFT 0x00000005 +#define SQ_INTERRUPT_WORD_AUTO__HOST_REG_OVERFLOW_MASK 0x00000040L +#define SQ_INTERRUPT_WORD_AUTO__HOST_REG_OVERFLOW__SHIFT 0x00000006 +#define SQ_INTERRUPT_WORD_AUTO__IMMED_OVERFLOW_MASK 0x00000080L +#define SQ_INTERRUPT_WORD_AUTO__IMMED_OVERFLOW__SHIFT 0x00000007 +#define SQ_INTERRUPT_WORD_AUTO__REG_TIMESTAMP_MASK 0x00000008L +#define SQ_INTERRUPT_WORD_AUTO__REG_TIMESTAMP__SHIFT 0x00000003 +#define SQ_INTERRUPT_WORD_AUTO__SE_ID_MASK 0x02000000L +#define SQ_INTERRUPT_WORD_AUTO__SE_ID__SHIFT 0x00000019 +#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF_FULL_MASK 0x00000004L +#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF_FULL__SHIFT 0x00000002 +#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_MASK 0x00000001L +#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE__SHIFT 0x00000000 +#define SQ_INTERRUPT_WORD_AUTO__WLT_MASK 0x00000002L +#define SQ_INTERRUPT_WORD_AUTO__WLT__SHIFT 0x00000001 +#define SQ_INTERRUPT_WORD_CMN__ENCODING_MASK 0x0c000000L +#define SQ_INTERRUPT_WORD_CMN__ENCODING__SHIFT 0x0000001a +#define SQ_INTERRUPT_WORD_CMN__SE_ID_MASK 0x02000000L +#define SQ_INTERRUPT_WORD_CMN__SE_ID__SHIFT 0x00000019 +#define SQ_INTERRUPT_WORD_WAVE__CU_ID_MASK 0x00f00000L +#define SQ_INTERRUPT_WORD_WAVE__CU_ID__SHIFT 0x00000014 +#define SQ_INTERRUPT_WORD_WAVE__DATA_MASK 0x000000ffL +#define SQ_INTERRUPT_WORD_WAVE__DATA__SHIFT 0x00000000 +#define SQ_INTERRUPT_WORD_WAVE__ENCODING_MASK 0x0c000000L +#define SQ_INTERRUPT_WORD_WAVE__ENCODING__SHIFT 0x0000001a +#define SQ_INTERRUPT_WORD_WAVE__PRIV_MASK 0x00000200L +#define SQ_INTERRUPT_WORD_WAVE__PRIV__SHIFT 0x00000009 +#define SQ_INTERRUPT_WORD_WAVE__SE_ID_MASK 0x02000000L +#define SQ_INTERRUPT_WORD_WAVE__SE_ID__SHIFT 0x00000019 +#define SQ_INTERRUPT_WORD_WAVE__SH_ID_MASK 0x01000000L +#define SQ_INTERRUPT_WORD_WAVE__SH_ID__SHIFT 0x00000018 +#define SQ_INTERRUPT_WORD_WAVE__SIMD_ID_MASK 0x000c0000L +#define SQ_INTERRUPT_WORD_WAVE__SIMD_ID__SHIFT 0x00000012 +#define SQ_INTERRUPT_WORD_WAVE__VM_ID_MASK 0x00003c00L +#define SQ_INTERRUPT_WORD_WAVE__VM_ID__SHIFT 0x0000000a +#define SQ_INTERRUPT_WORD_WAVE__WAVE_ID_MASK 0x0003c000L +#define SQ_INTERRUPT_WORD_WAVE__WAVE_ID__SHIFT 0x0000000e +#define SQ_LB_CTR_CTRL__CLEAR_MASK 0x00000004L +#define SQ_LB_CTR_CTRL__CLEAR__SHIFT 0x00000002 +#define SQ_LB_CTR_CTRL__LOAD_MASK 0x00000002L +#define SQ_LB_CTR_CTRL__LOAD__SHIFT 0x00000001 +#define SQ_LB_CTR_CTRL__START_MASK 0x00000001L +#define SQ_LB_CTR_CTRL__START__SHIFT 0x00000000 +#define SQ_LB_DATA_ALU_CYCLES__DATA_MASK 0xffffffffL +#define SQ_LB_DATA_ALU_CYCLES__DATA__SHIFT 0x00000000 +#define SQ_LB_DATA_ALU_STALLS__DATA_MASK 0xffffffffL +#define SQ_LB_DATA_ALU_STALLS__DATA__SHIFT 0x00000000 +#define SQ_LB_DATA_TEX_CYCLES__DATA_MASK 0xffffffffL +#define SQ_LB_DATA_TEX_CYCLES__DATA__SHIFT 0x00000000 +#define SQ_LB_DATA_TEX_STALLS__DATA_MASK 0xffffffffL +#define SQ_LB_DATA_TEX_STALLS__DATA__SHIFT 0x00000000 +#define SQ_MIMG_0__DA_MASK 0x00004000L +#define SQ_MIMG_0__DA__SHIFT 0x0000000e +#define SQ_MIMG_0__DMASK_MASK 0x00000f00L +#define SQ_MIMG_0__DMASK__SHIFT 0x00000008 +#define SQ_MIMG_0__ENCODING_MASK 0xfc000000L +#define SQ_MIMG_0__ENCODING__SHIFT 0x0000001a +#define SQ_MIMG_0__GLC_MASK 0x00002000L +#define SQ_MIMG_0__GLC__SHIFT 0x0000000d +#define SQ_MIMG_0__LWE_MASK 0x00020000L +#define SQ_MIMG_0__LWE__SHIFT 0x00000011 +#define SQ_MIMG_0__OP_MASK 0x01fc0000L +#define SQ_MIMG_0__OP__SHIFT 0x00000012 +#define SQ_MIMG_0__R128_MASK 0x00008000L +#define SQ_MIMG_0__R128__SHIFT 0x0000000f +#define SQ_MIMG_0__SLC_MASK 0x02000000L +#define SQ_MIMG_0__SLC__SHIFT 0x00000019 +#define SQ_MIMG_0__TFE_MASK 0x00010000L +#define SQ_MIMG_0__TFE__SHIFT 0x00000010 +#define SQ_MIMG_0__UNORM_MASK 0x00001000L +#define SQ_MIMG_0__UNORM__SHIFT 0x0000000c +#define SQ_MIMG_1__SRSRC_MASK 0x001f0000L +#define SQ_MIMG_1__SRSRC__SHIFT 0x00000010 +#define SQ_MIMG_1__SSAMP_MASK 0x03e00000L +#define SQ_MIMG_1__SSAMP__SHIFT 0x00000015 +#define SQ_MIMG_1__VADDR_MASK 0x000000ffL +#define SQ_MIMG_1__VADDR__SHIFT 0x00000000 +#define SQ_MIMG_1__VDATA_MASK 0x0000ff00L +#define SQ_MIMG_1__VDATA__SHIFT 0x00000008 +#define SQ_MTBUF_0__ADDR64_MASK 0x00008000L +#define SQ_MTBUF_0__ADDR64__SHIFT 0x0000000f +#define SQ_MTBUF_0__DFMT_MASK 0x00780000L +#define SQ_MTBUF_0__DFMT__SHIFT 0x00000013 +#define SQ_MTBUF_0__ENCODING_MASK 0xfc000000L +#define SQ_MTBUF_0__ENCODING__SHIFT 0x0000001a +#define SQ_MTBUF_0__GLC_MASK 0x00004000L +#define SQ_MTBUF_0__GLC__SHIFT 0x0000000e +#define SQ_MTBUF_0__IDXEN_MASK 0x00002000L +#define SQ_MTBUF_0__IDXEN__SHIFT 0x0000000d +#define SQ_MTBUF_0__NFMT_MASK 0x03800000L +#define SQ_MTBUF_0__NFMT__SHIFT 0x00000017 +#define SQ_MTBUF_0__OFFEN_MASK 0x00001000L +#define SQ_MTBUF_0__OFFEN__SHIFT 0x0000000c +#define SQ_MTBUF_0__OFFSET_MASK 0x00000fffL +#define SQ_MTBUF_0__OFFSET__SHIFT 0x00000000 +#define SQ_MTBUF_0__OP_MASK 0x00070000L +#define SQ_MTBUF_0__OP__SHIFT 0x00000010 +#define SQ_MTBUF_1__SLC_MASK 0x00400000L +#define SQ_MTBUF_1__SLC__SHIFT 0x00000016 +#define SQ_MTBUF_1__SOFFSET_MASK 0xff000000L +#define SQ_MTBUF_1__SOFFSET__SHIFT 0x00000018 +#define SQ_MTBUF_1__SRSRC_MASK 0x001f0000L +#define SQ_MTBUF_1__SRSRC__SHIFT 0x00000010 +#define SQ_MTBUF_1__TFE_MASK 0x00800000L +#define SQ_MTBUF_1__TFE__SHIFT 0x00000017 +#define SQ_MTBUF_1__VADDR_MASK 0x000000ffL +#define SQ_MTBUF_1__VADDR__SHIFT 0x00000000 +#define SQ_MTBUF_1__VDATA_MASK 0x0000ff00L +#define SQ_MTBUF_1__VDATA__SHIFT 0x00000008 +#define SQ_MUBUF_0__ADDR64_MASK 0x00008000L +#define SQ_MUBUF_0__ADDR64__SHIFT 0x0000000f +#define SQ_MUBUF_0__ENCODING_MASK 0xfc000000L +#define SQ_MUBUF_0__ENCODING__SHIFT 0x0000001a +#define SQ_MUBUF_0__GLC_MASK 0x00004000L +#define SQ_MUBUF_0__GLC__SHIFT 0x0000000e +#define SQ_MUBUF_0__IDXEN_MASK 0x00002000L +#define SQ_MUBUF_0__IDXEN__SHIFT 0x0000000d +#define SQ_MUBUF_0__LDS_MASK 0x00010000L +#define SQ_MUBUF_0__LDS__SHIFT 0x00000010 +#define SQ_MUBUF_0__OFFEN_MASK 0x00001000L +#define SQ_MUBUF_0__OFFEN__SHIFT 0x0000000c +#define SQ_MUBUF_0__OFFSET_MASK 0x00000fffL +#define SQ_MUBUF_0__OFFSET__SHIFT 0x00000000 +#define SQ_MUBUF_0__OP_MASK 0x01fc0000L +#define SQ_MUBUF_0__OP__SHIFT 0x00000012 +#define SQ_MUBUF_1__SLC_MASK 0x00400000L +#define SQ_MUBUF_1__SLC__SHIFT 0x00000016 +#define SQ_MUBUF_1__SOFFSET_MASK 0xff000000L +#define SQ_MUBUF_1__SOFFSET__SHIFT 0x00000018 +#define SQ_MUBUF_1__SRSRC_MASK 0x001f0000L +#define SQ_MUBUF_1__SRSRC__SHIFT 0x00000010 +#define SQ_MUBUF_1__TFE_MASK 0x00800000L +#define SQ_MUBUF_1__TFE__SHIFT 0x00000017 +#define SQ_MUBUF_1__VADDR_MASK 0x000000ffL +#define SQ_MUBUF_1__VADDR__SHIFT 0x00000000 +#define SQ_MUBUF_1__VDATA_MASK 0x0000ff00L +#define SQ_MUBUF_1__VDATA__SHIFT 0x00000008 +#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L +#define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c +#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001ffL +#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 +#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK_MASK 0x0f000000L +#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK__SHIFT 0x00000018 +#define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00f00000L +#define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x00000014 +#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK_MASK 0x0000f000L +#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c +#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L +#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 +#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK 0xf0000000L +#define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT 0x0000001c +#define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK 0x000001ffL +#define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT 0x00000000 +#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK_MASK 0x0f000000L +#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK__SHIFT 0x00000018 +#define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK 0x00f00000L +#define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT 0x00000014 +#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK_MASK 0x0000f000L +#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c +#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L +#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 +#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK 0xf0000000L +#define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT 0x0000001c +#define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK 0x000001ffL +#define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT 0x00000000 +#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK_MASK 0x0f000000L +#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK__SHIFT 0x00000018 +#define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK 0x00f00000L +#define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT 0x00000014 +#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK_MASK 0x0000f000L +#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c +#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L +#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 +#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK 0xf0000000L +#define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT 0x0000001c +#define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK 0x000001ffL +#define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT 0x00000000 +#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK_MASK 0x0f000000L +#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK__SHIFT 0x00000018 +#define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK 0x00f00000L +#define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT 0x00000014 +#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK_MASK 0x0000f000L +#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c +#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L +#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 +#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK 0xf0000000L +#define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT 0x0000001c +#define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK 0x000001ffL +#define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT 0x00000000 +#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK_MASK 0x0f000000L +#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK__SHIFT 0x00000018 +#define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK 0x00f00000L +#define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT 0x00000014 +#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK_MASK 0x0000f000L +#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c +#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L +#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 +#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK 0xf0000000L +#define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT 0x0000001c +#define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK 0x000001ffL +#define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT 0x00000000 +#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK_MASK 0x0f000000L +#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK__SHIFT 0x00000018 +#define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK 0x00f00000L +#define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT 0x00000014 +#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK_MASK 0x0000f000L +#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c +#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L +#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 +#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK 0xf0000000L +#define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT 0x0000001c +#define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK 0x000001ffL +#define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT 0x00000000 +#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK_MASK 0x0f000000L +#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK__SHIFT 0x00000018 +#define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK 0x00f00000L +#define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT 0x00000014 +#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK_MASK 0x0000f000L +#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c +#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L +#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 +#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L +#define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c +#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001ffL +#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 +#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK_MASK 0x0f000000L +#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK__SHIFT 0x00000018 +#define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00f00000L +#define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x00000014 +#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK_MASK 0x0000f000L +#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c +#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L +#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 +#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000L +#define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x0000001c +#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001ffL +#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 +#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK_MASK 0x0f000000L +#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK__SHIFT 0x00000018 +#define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0x00f00000L +#define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x00000014 +#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK_MASK 0x0000f000L +#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c +#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L +#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 +#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000L +#define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x0000001c +#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001ffL +#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 +#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK_MASK 0x0f000000L +#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK__SHIFT 0x00000018 +#define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0x00f00000L +#define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x00000014 +#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK_MASK 0x0000f000L +#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c +#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L +#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 +#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xf0000000L +#define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x0000001c +#define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000001ffL +#define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x00000000 +#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK_MASK 0x0f000000L +#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK__SHIFT 0x00000018 +#define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0x00f00000L +#define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x00000014 +#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK_MASK 0x0000f000L +#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c +#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L +#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 +#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xf0000000L +#define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x0000001c +#define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000001ffL +#define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x00000000 +#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK_MASK 0x0f000000L +#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK__SHIFT 0x00000018 +#define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0x00f00000L +#define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x00000014 +#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK_MASK 0x0000f000L +#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c +#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L +#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 +#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xf0000000L +#define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x0000001c +#define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000001ffL +#define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x00000000 +#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK_MASK 0x0f000000L +#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK__SHIFT 0x00000018 +#define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK 0x00f00000L +#define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT 0x00000014 +#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK_MASK 0x0000f000L +#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c +#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L +#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 +#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xf0000000L +#define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x0000001c +#define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000001ffL +#define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x00000000 +#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK_MASK 0x0f000000L +#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK__SHIFT 0x00000018 +#define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK 0x00f00000L +#define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT 0x00000014 +#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK_MASK 0x0000f000L +#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c +#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L +#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 +#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK 0xf0000000L +#define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT 0x0000001c +#define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK 0x000001ffL +#define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT 0x00000000 +#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK_MASK 0x0f000000L +#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK__SHIFT 0x00000018 +#define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK 0x00f00000L +#define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT 0x00000014 +#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK_MASK 0x0000f000L +#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c +#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L +#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 +#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK 0xf0000000L +#define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT 0x0000001c +#define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK 0x000001ffL +#define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT 0x00000000 +#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK_MASK 0x0f000000L +#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK__SHIFT 0x00000018 +#define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK 0x00f00000L +#define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT 0x00000014 +#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK_MASK 0x0000f000L +#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c +#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L +#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 +#define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK 0x00000001L +#define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT 0x00000000 +#define SQ_PERFCOUNTER_CTRL__CNTR_RATE_MASK 0x00001f00L +#define SQ_PERFCOUNTER_CTRL__CNTR_RATE__SHIFT 0x00000008 +#define SQ_PERFCOUNTER_CTRL__CS_EN_MASK 0x00000040L +#define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT 0x00000006 +#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH_MASK 0x00002000L +#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH__SHIFT 0x0000000d +#define SQ_PERFCOUNTER_CTRL__ES_EN_MASK 0x00000008L +#define SQ_PERFCOUNTER_CTRL__ES_EN__SHIFT 0x00000003 +#define SQ_PERFCOUNTER_CTRL__GS_EN_MASK 0x00000004L +#define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT 0x00000002 +#define SQ_PERFCOUNTER_CTRL__HS_EN_MASK 0x00000010L +#define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT 0x00000004 +#define SQ_PERFCOUNTER_CTRL__LS_EN_MASK 0x00000020L +#define SQ_PERFCOUNTER_CTRL__LS_EN__SHIFT 0x00000005 +#define SQ_PERFCOUNTER_CTRL__PS_EN_MASK 0x00000001L +#define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT 0x00000000 +#define SQ_PERFCOUNTER_CTRL__VS_EN_MASK 0x00000002L +#define SQ_PERFCOUNTER_CTRL__VS_EN__SHIFT 0x00000001 +#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L +#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x0000001b +#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK 0x00003fffL +#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT 0x00000000 +#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03ff0000L +#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x00000010 +#define SQ_POWER_THROTTLE2__USE_REF_CLOCK_MASK 0x80000000L +#define SQ_POWER_THROTTLE2__USE_REF_CLOCK__SHIFT 0x0000001f +#define SQ_POWER_THROTTLE__MAX_POWER_MASK 0x3fff0000L +#define SQ_POWER_THROTTLE__MAX_POWER__SHIFT 0x00000010 +#define SQ_POWER_THROTTLE__MIN_POWER_MASK 0x00003fffL +#define SQ_POWER_THROTTLE__MIN_POWER__SHIFT 0x00000000 +#define SQ_POWER_THROTTLE__PHASE_OFFSET_MASK 0xc0000000L +#define SQ_POWER_THROTTLE__PHASE_OFFSET__SHIFT 0x0000001e +#define SQ_RANDOM_WAVE_PRI__RET_MASK 0x0000007fL +#define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x00000000 +#define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x001ffc00L +#define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0x0000000a +#define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x00000380L +#define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x00000007 +#define SQ_REG_CREDITS__CMD_CREDITS_MASK 0x00000f00L +#define SQ_REG_CREDITS__CMD_CREDITS__SHIFT 0x00000008 +#define SQ_REG_CREDITS__CMD_OVERFLOW_MASK 0x80000000L +#define SQ_REG_CREDITS__CMD_OVERFLOW__SHIFT 0x0000001f +#define SQ_REG_CREDITS__IMMED_OVERFLOW_MASK 0x40000000L +#define SQ_REG_CREDITS__IMMED_OVERFLOW__SHIFT 0x0000001e +#define SQ_REG_CREDITS__REG_BUSY_MASK 0x10000000L +#define SQ_REG_CREDITS__REG_BUSY__SHIFT 0x0000001c +#define SQ_REG_CREDITS__SRBM_CREDITS_MASK 0x0000003fL +#define SQ_REG_CREDITS__SRBM_CREDITS__SHIFT 0x00000000 +#define SQ_REG_CREDITS__SRBM_OVERFLOW_MASK 0x20000000L +#define SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT 0x0000001d +#define SQ_SEC_CNT__LDS_SEC_MASK 0x0000003fL +#define SQ_SEC_CNT__LDS_SEC__SHIFT 0x00000000 +#define SQ_SEC_CNT__SGPR_SEC_MASK 0x00001f00L +#define SQ_SEC_CNT__SGPR_SEC__SHIFT 0x00000008 +#define SQ_SEC_CNT__VGPR_SEC_MASK 0x01ff0000L +#define SQ_SEC_CNT__VGPR_SEC__SHIFT 0x00000010 +#define SQ_SMRD__ENCODING_MASK 0xf8000000L +#define SQ_SMRD__ENCODING__SHIFT 0x0000001b +#define SQ_SMRD__IMM_MASK 0x00000100L +#define SQ_SMRD__IMM__SHIFT 0x00000008 +#define SQ_SMRD__OFFSET_MASK 0x000000ffL +#define SQ_SMRD__OFFSET__SHIFT 0x00000000 +#define SQ_SMRD__OP_MASK 0x07c00000L +#define SQ_SMRD__OP__SHIFT 0x00000016 +#define SQ_SMRD__SBASE_MASK 0x00007e00L +#define SQ_SMRD__SBASE__SHIFT 0x00000009 +#define SQ_SMRD__SDST_MASK 0x003f8000L +#define SQ_SMRD__SDST__SHIFT 0x0000000f +#define SQ_SOP1__ENCODING_MASK 0xff800000L +#define SQ_SOP1__ENCODING__SHIFT 0x00000017 +#define SQ_SOP1__OP_MASK 0x0000ff00L +#define SQ_SOP1__OP__SHIFT 0x00000008 +#define SQ_SOP1__SDST_MASK 0x007f0000L +#define SQ_SOP1__SDST__SHIFT 0x00000010 +#define SQ_SOP1__SSRC0_MASK 0x000000ffL +#define SQ_SOP1__SSRC0__SHIFT 0x00000000 +#define SQ_SOP2__ENCODING_MASK 0xc0000000L +#define SQ_SOP2__ENCODING__SHIFT 0x0000001e +#define SQ_SOP2__OP_MASK 0x3f800000L +#define SQ_SOP2__OP__SHIFT 0x00000017 +#define SQ_SOP2__SDST_MASK 0x007f0000L +#define SQ_SOP2__SDST__SHIFT 0x00000010 +#define SQ_SOP2__SSRC0_MASK 0x000000ffL +#define SQ_SOP2__SSRC0__SHIFT 0x00000000 +#define SQ_SOP2__SSRC1_MASK 0x0000ff00L +#define SQ_SOP2__SSRC1__SHIFT 0x00000008 +#define SQ_SOPC__ENCODING_MASK 0xff800000L +#define SQ_SOPC__ENCODING__SHIFT 0x00000017 +#define SQ_SOPC__OP_MASK 0x007f0000L +#define SQ_SOPC__OP__SHIFT 0x00000010 +#define SQ_SOPC__SSRC0_MASK 0x000000ffL +#define SQ_SOPC__SSRC0__SHIFT 0x00000000 +#define SQ_SOPC__SSRC1_MASK 0x0000ff00L +#define SQ_SOPC__SSRC1__SHIFT 0x00000008 +#define SQ_SOPK__ENCODING_MASK 0xf0000000L +#define SQ_SOPK__ENCODING__SHIFT 0x0000001c +#define SQ_SOPK__OP_MASK 0x0f800000L +#define SQ_SOPK__OP__SHIFT 0x00000017 +#define SQ_SOPK__SDST_MASK 0x007f0000L +#define SQ_SOPK__SDST__SHIFT 0x00000010 +#define SQ_SOPK__SIMM16_MASK 0x0000ffffL +#define SQ_SOPK__SIMM16__SHIFT 0x00000000 +#define SQ_SOPP__ENCODING_MASK 0xff800000L +#define SQ_SOPP__ENCODING__SHIFT 0x00000017 +#define SQ_SOPP__OP_MASK 0x007f0000L +#define SQ_SOPP__OP__SHIFT 0x00000010 +#define SQ_SOPP__SIMM16_MASK 0x0000ffffL +#define SQ_SOPP__SIMM16__SHIFT 0x00000000 +#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000ffffL +#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x00000000 +#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000L +#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x00000010 +#define SQ_THREAD_TRACE_BASE2__ADDR_HI_MASK 0x0000000fL +#define SQ_THREAD_TRACE_BASE2__ADDR_HI__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_BASE2__ATC_MASK 0x00000010L +#define SQ_THREAD_TRACE_BASE2__ATC__SHIFT 0x00000004 +#define SQ_THREAD_TRACE_BASE__ADDR_MASK 0xffffffffL +#define SQ_THREAD_TRACE_BASE__ADDR__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_CNTR__CNTR_MASK 0xffffffffL +#define SQ_THREAD_TRACE_CNTR__CNTR__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER_MASK 0x80000000L +#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER__SHIFT 0x0000001f +#define SQ_THREAD_TRACE_HIWATER__HIWATER_MASK 0x00000007L +#define SQ_THREAD_TRACE_HIWATER__HIWATER__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_MASK__CU_SEL_MASK 0x0000001fL +#define SQ_THREAD_TRACE_MASK__CU_SEL__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_MASK__RANDOM_SEED_MASK 0xffff0000L +#define SQ_THREAD_TRACE_MASK__RANDOM_SEED__SHIFT 0x00000010 +#define SQ_THREAD_TRACE_MASK__REG_STALL_EN_MASK 0x00000080L +#define SQ_THREAD_TRACE_MASK__REG_STALL_EN__SHIFT 0x00000007 +#define SQ_THREAD_TRACE_MASK__SH_SEL_MASK 0x00000020L +#define SQ_THREAD_TRACE_MASK__SH_SEL__SHIFT 0x00000005 +#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN_MASK 0x00004000L +#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN__SHIFT 0x0000000e +#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN_MASK 0x00008000L +#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN__SHIFT 0x0000000f +#define SQ_THREAD_TRACE_MASK__VM_ID_MASK_MASK 0x00003000L +#define SQ_THREAD_TRACE_MASK__VM_ID_MASK__SHIFT 0x0000000c +#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN_MASK 0x02000000L +#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN__SHIFT 0x00000019 +#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE_MASK 0x01800000L +#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE__SHIFT 0x00000017 +#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN_MASK 0x40000000L +#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN__SHIFT 0x0000001e +#define SQ_THREAD_TRACE_MODE__ISSUE_MASK_MASK 0x18000000L +#define SQ_THREAD_TRACE_MODE__ISSUE_MASK__SHIFT 0x0000001b +#define SQ_THREAD_TRACE_MODE__MASK_CS_MASK 0x001c0000L +#define SQ_THREAD_TRACE_MODE__MASK_CS__SHIFT 0x00000012 +#define SQ_THREAD_TRACE_MODE__MASK_ES_MASK 0x00000e00L +#define SQ_THREAD_TRACE_MODE__MASK_ES__SHIFT 0x00000009 +#define SQ_THREAD_TRACE_MODE__MASK_GS_MASK 0x000001c0L +#define SQ_THREAD_TRACE_MODE__MASK_GS__SHIFT 0x00000006 +#define SQ_THREAD_TRACE_MODE__MASK_HS_MASK 0x00007000L +#define SQ_THREAD_TRACE_MODE__MASK_HS__SHIFT 0x0000000c +#define SQ_THREAD_TRACE_MODE__MASK_LS_MASK 0x00038000L +#define SQ_THREAD_TRACE_MODE__MASK_LS__SHIFT 0x0000000f +#define SQ_THREAD_TRACE_MODE__MASK_PS_MASK 0x00000007L +#define SQ_THREAD_TRACE_MODE__MASK_PS__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_MODE__MASK_VS_MASK 0x00000038L +#define SQ_THREAD_TRACE_MODE__MASK_VS__SHIFT 0x00000003 +#define SQ_THREAD_TRACE_MODE__MODE_MASK 0x00600000L +#define SQ_THREAD_TRACE_MODE__MODE__SHIFT 0x00000015 +#define SQ_THREAD_TRACE_MODE__PRIV_MASK 0x04000000L +#define SQ_THREAD_TRACE_MODE__PRIV__SHIFT 0x0000001a +#define SQ_THREAD_TRACE_MODE__TEST_MODE_MASK 0x20000000L +#define SQ_THREAD_TRACE_MODE__TEST_MODE__SHIFT 0x0000001d +#define SQ_THREAD_TRACE_MODE__WRAP_MASK 0x80000000L +#define SQ_THREAD_TRACE_MODE__WRAP__SHIFT 0x0000001f +#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK_MASK 0x0000ffffL +#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK_MASK 0xffff0000L +#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK__SHIFT 0x00000010 +#define SQ_THREAD_TRACE_SIZE__SIZE_MASK 0x003fffffL +#define SQ_THREAD_TRACE_SIZE__SIZE__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_STATUS__BUSY_MASK 0x40000000L +#define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT 0x0000001e +#define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK 0x00070000L +#define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT 0x00000010 +#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK 0x00000007L +#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_STATUS__FULL_MASK 0x80000000L +#define SQ_THREAD_TRACE_STATUS__FULL__SHIFT 0x0000001f +#define SQ_THREAD_TRACE_STATUS__NEW_BUF_MASK 0x20000000L +#define SQ_THREAD_TRACE_STATUS__NEW_BUF__SHIFT 0x0000001d +#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK_MASK 0x0000ffffL +#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL_MASK 0x01000000L +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL__SHIFT 0x00000018 +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK_MASK 0x00ff0000L +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK__SHIFT 0x00000010 +#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK_MASK 0x0000ffffL +#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK 0xffffffffL +#define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK 0xffffffffL +#define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK 0xffffffffL +#define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK 0xffffffffL +#define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA_MASK 0x00000010L +#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA__SHIFT 0x00000004 +#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE_MASK 0x0000000fL +#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE_MASK 0x0000fc00L +#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT 0x0000000a +#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID_MASK 0x00000020L +#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID__SHIFT 0x00000005 +#define SQ_THREAD_TRACE_WORD_EVENT__STAGE_MASK 0x000001c0L +#define SQ_THREAD_TRACE_WORD_EVENT__STAGE__SHIFT 0x00000006 +#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA_MASK 0x00000010L +#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA__SHIFT 0x00000004 +#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE_MASK 0x0000000fL +#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE_MASK 0x0000f000L +#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE__SHIFT 0x0000000c +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO_MASK 0xffff0000L +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO__SHIFT 0x00000010 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID_MASK 0x00000600L +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID__SHIFT 0x00000009 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA_MASK 0x00000010L +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA__SHIFT 0x00000004 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE_MASK 0x0000000fL +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID_MASK 0x000001e0L +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID__SHIFT 0x00000005 +#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI_MASK 0x00ffffffL +#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID_MASK 0x00000600L +#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID__SHIFT 0x00000009 +#define SQ_THREAD_TRACE_WORD_INST__SIZE_MASK 0x00000800L +#define SQ_THREAD_TRACE_WORD_INST__SIZE__SHIFT 0x0000000b +#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA_MASK 0x00000010L +#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA__SHIFT 0x00000004 +#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE_MASK 0x0000000fL +#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID_MASK 0x000003c0L +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID__SHIFT 0x00000006 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO_MASK 0xffff0000L +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO__SHIFT 0x00000010 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID_MASK 0x00000020L +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID__SHIFT 0x00000005 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID_MASK 0x0000c000L +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID__SHIFT 0x0000000e +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA_MASK 0x00000010L +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA__SHIFT 0x00000004 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE_MASK 0x0000000fL +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID_MASK 0x00003c00L +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT 0x0000000a +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI_MASK 0x0000ffffL +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID_MASK 0x000001e0L +#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID__SHIFT 0x00000005 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST0_MASK 0x00000300L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST0__SHIFT 0x00000008 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST1_MASK 0x00000c00L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT 0x0000000a +#define SQ_THREAD_TRACE_WORD_ISSUE__INST2_MASK 0x00003000L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST2__SHIFT 0x0000000c +#define SQ_THREAD_TRACE_WORD_ISSUE__INST3_MASK 0x0000c000L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST3__SHIFT 0x0000000e +#define SQ_THREAD_TRACE_WORD_ISSUE__INST4_MASK 0x00030000L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST4__SHIFT 0x00000010 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST5_MASK 0x000c0000L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST5__SHIFT 0x00000012 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST6_MASK 0x00300000L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST6__SHIFT 0x00000014 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST7_MASK 0x00c00000L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST7__SHIFT 0x00000016 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST8_MASK 0x03000000L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST8__SHIFT 0x00000018 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST9_MASK 0x0c000000L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST9__SHIFT 0x0000001a +#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID_MASK 0x00000060L +#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID__SHIFT 0x00000005 +#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA_MASK 0x00000010L +#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA__SHIFT 0x00000004 +#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE_MASK 0x0000000fL +#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE_MASK 0x000000c0L +#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE__SHIFT 0x00000006 +#define SQ_THREAD_TRACE_WORD_MISC__SH_ID_MASK 0x00000020L +#define SQ_THREAD_TRACE_WORD_MISC__SH_ID__SHIFT 0x00000005 +#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA_MASK 0x00000010L +#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA__SHIFT 0x00000004 +#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE_MASK 0x0000000fL +#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0_MASK 0x01fff000L +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0__SHIFT 0x0000000c +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO_MASK 0xfe000000L +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO__SHIFT 0x00000019 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK_MASK 0x00000c00L +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT 0x0000000a +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID_MASK 0x000003c0L +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID__SHIFT 0x00000006 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID_MASK 0x00000020L +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID__SHIFT 0x00000005 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA_MASK 0x00000010L +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA__SHIFT 0x00000004 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE_MASK 0x0000000fL +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI_MASK 0x0000003fL +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2_MASK 0x0007ffc0L +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2__SHIFT 0x00000006 +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3_MASK 0xfff80000L +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3__SHIFT 0x00000013 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID_MASK 0x00000180L +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID__SHIFT 0x00000007 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID_MASK 0x00000060L +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID__SHIFT 0x00000005 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR_MASK 0xffff0000L +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR__SHIFT 0x00000010 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV_MASK 0x00000200L +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV__SHIFT 0x00000009 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP_MASK 0x00008000L +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP__SHIFT 0x0000000f +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV_MASK 0x00004000L +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV__SHIFT 0x0000000e +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE_MASK 0x00001c00L +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT 0x0000000a +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA_MASK 0x00000010L +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA__SHIFT 0x00000004 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE_MASK 0x0000000fL +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA_MASK 0xffffffffL +#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO_MASK 0xffff0000L +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO__SHIFT 0x00000010 +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE_MASK 0x0000000fL +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI_MASK 0xffffffffL +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID_MASK 0x000003c0L +#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID__SHIFT 0x00000006 +#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID_MASK 0x00000020L +#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID__SHIFT 0x00000005 +#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID_MASK 0x0000c000L +#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID__SHIFT 0x0000000e +#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT_MASK 0x1fc00000L +#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT__SHIFT 0x00000016 +#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID_MASK 0x000003c0L +#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID__SHIFT 0x00000006 +#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER_MASK 0x001f0000L +#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER__SHIFT 0x00000010 +#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID_MASK 0x00000020L +#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID__SHIFT 0x00000005 +#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID_MASK 0x0000c000L +#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID__SHIFT 0x0000000e +#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID_MASK 0xe0000000L +#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT 0x0000001d +#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA_MASK 0x00000010L +#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA__SHIFT 0x00000004 +#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE_MASK 0x0000000fL +#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED_MASK 0x00200000L +#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED__SHIFT 0x00000015 +#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID_MASK 0x00003c00L +#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT 0x0000000a +#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA_MASK 0x00000010L +#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA__SHIFT 0x00000004 +#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE_MASK 0x0000000fL +#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID_MASK 0x00003c00L +#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT 0x0000000a +#define SQ_THREAD_TRACE_WPTR__READ_OFFSET_MASK 0xc0000000L +#define SQ_THREAD_TRACE_WPTR__READ_OFFSET__SHIFT 0x0000001e +#define SQ_THREAD_TRACE_WPTR__WPTR_MASK 0x3fffffffL +#define SQ_THREAD_TRACE_WPTR__WPTR__SHIFT 0x00000000 +#define SQ_TIME_HI__TIME_MASK 0xffffffffL +#define SQ_TIME_HI__TIME__SHIFT 0x00000000 +#define SQ_TIME_LO__TIME_MASK 0xffffffffL +#define SQ_TIME_LO__TIME__SHIFT 0x00000000 +#define SQ_VINTRP__ATTRCHAN_MASK 0x00000300L +#define SQ_VINTRP__ATTRCHAN__SHIFT 0x00000008 +#define SQ_VINTRP__ATTR_MASK 0x0000fc00L +#define SQ_VINTRP__ATTR__SHIFT 0x0000000a +#define SQ_VINTRP__ENCODING_MASK 0xfc000000L +#define SQ_VINTRP__ENCODING__SHIFT 0x0000001a +#define SQ_VINTRP__OP_MASK 0x00030000L +#define SQ_VINTRP__OP__SHIFT 0x00000010 +#define SQ_VINTRP__VDST_MASK 0x03fc0000L +#define SQ_VINTRP__VDST__SHIFT 0x00000012 +#define SQ_VINTRP__VSRC_MASK 0x000000ffL +#define SQ_VINTRP__VSRC__SHIFT 0x00000000 +#define SQ_VOP1__ENCODING_MASK 0xfe000000L +#define SQ_VOP1__ENCODING__SHIFT 0x00000019 +#define SQ_VOP1__OP_MASK 0x0001fe00L +#define SQ_VOP1__OP__SHIFT 0x00000009 +#define SQ_VOP1__SRC0_MASK 0x000001ffL +#define SQ_VOP1__SRC0__SHIFT 0x00000000 +#define SQ_VOP1__VDST_MASK 0x01fe0000L +#define SQ_VOP1__VDST__SHIFT 0x00000011 +#define SQ_VOP2__ENCODING_MASK 0x80000000L +#define SQ_VOP2__ENCODING__SHIFT 0x0000001f +#define SQ_VOP2__OP_MASK 0x7e000000L +#define SQ_VOP2__OP__SHIFT 0x00000019 +#define SQ_VOP2__SRC0_MASK 0x000001ffL +#define SQ_VOP2__SRC0__SHIFT 0x00000000 +#define SQ_VOP2__VDST_MASK 0x01fe0000L +#define SQ_VOP2__VDST__SHIFT 0x00000011 +#define SQ_VOP2__VSRC1_MASK 0x0001fe00L +#define SQ_VOP2__VSRC1__SHIFT 0x00000009 +#define SQ_VOP3_0__ABS_MASK 0x00000700L +#define SQ_VOP3_0__ABS__SHIFT 0x00000008 +#define SQ_VOP3_0__CLAMP_MASK 0x00000800L +#define SQ_VOP3_0__CLAMP__SHIFT 0x0000000b +#define SQ_VOP3_0__ENCODING_MASK 0xfc000000L +#define SQ_VOP3_0__ENCODING__SHIFT 0x0000001a +#define SQ_VOP3_0__OP_MASK 0x03fe0000L +#define SQ_VOP3_0__OP__SHIFT 0x00000011 +#define SQ_VOP3_0_SDST_ENC__ENCODING_MASK 0xfc000000L +#define SQ_VOP3_0_SDST_ENC__ENCODING__SHIFT 0x0000001a +#define SQ_VOP3_0_SDST_ENC__OP_MASK 0x03fe0000L +#define SQ_VOP3_0_SDST_ENC__OP__SHIFT 0x00000011 +#define SQ_VOP3_0_SDST_ENC__SDST_MASK 0x00007f00L +#define SQ_VOP3_0_SDST_ENC__SDST__SHIFT 0x00000008 +#define SQ_VOP3_0_SDST_ENC__VDST_MASK 0x000000ffL +#define SQ_VOP3_0_SDST_ENC__VDST__SHIFT 0x00000000 +#define SQ_VOP3_0__VDST_MASK 0x000000ffL +#define SQ_VOP3_0__VDST__SHIFT 0x00000000 +#define SQ_VOP3_1__NEG_MASK 0xe0000000L +#define SQ_VOP3_1__NEG__SHIFT 0x0000001d +#define SQ_VOP3_1__OMOD_MASK 0x18000000L +#define SQ_VOP3_1__OMOD__SHIFT 0x0000001b +#define SQ_VOP3_1__SRC0_MASK 0x000001ffL +#define SQ_VOP3_1__SRC0__SHIFT 0x00000000 +#define SQ_VOP3_1__SRC1_MASK 0x0003fe00L +#define SQ_VOP3_1__SRC1__SHIFT 0x00000009 +#define SQ_VOP3_1__SRC2_MASK 0x07fc0000L +#define SQ_VOP3_1__SRC2__SHIFT 0x00000012 +#define SQ_VOPC__ENCODING_MASK 0xfe000000L +#define SQ_VOPC__ENCODING__SHIFT 0x00000019 +#define SQ_VOPC__OP_MASK 0x01fe0000L +#define SQ_VOPC__OP__SHIFT 0x00000011 +#define SQ_VOPC__SRC0_MASK 0x000001ffL +#define SQ_VOPC__SRC0__SHIFT 0x00000000 +#define SQ_VOPC__VSRC1_MASK 0x0001fe00L +#define SQ_VOPC__VSRC1__SHIFT 0x00000009 +#define SQ_WAVE_EXEC_HI__EXEC_HI_MASK 0xffffffffL +#define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT 0x00000000 +#define SQ_WAVE_EXEC_LO__EXEC_LO_MASK 0xffffffffL +#define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT 0x00000000 +#define SQ_WAVE_GPR_ALLOC__SGPR_BASE_MASK 0x003f0000L +#define SQ_WAVE_GPR_ALLOC__SGPR_BASE__SHIFT 0x00000010 +#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE_MASK 0x0f000000L +#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE__SHIFT 0x00000018 +#define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK 0x0000003fL +#define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT 0x00000000 +#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK 0x00003f00L +#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT 0x00000008 +#define SQ_WAVE_HW_ID__CU_ID_MASK 0x00000f00L +#define SQ_WAVE_HW_ID__CU_ID__SHIFT 0x00000008 +#define SQ_WAVE_HW_ID__ME_ID_MASK 0xc0000000L +#define SQ_WAVE_HW_ID__ME_ID__SHIFT 0x0000001e +#define SQ_WAVE_HW_ID__PIPE_ID_MASK 0x000000c0L +#define SQ_WAVE_HW_ID__PIPE_ID__SHIFT 0x00000006 +#define SQ_WAVE_HW_ID__QUEUE_ID_MASK 0x07000000L +#define SQ_WAVE_HW_ID__QUEUE_ID__SHIFT 0x00000018 +#define SQ_WAVE_HW_ID__SE_ID_MASK 0x00002000L +#define SQ_WAVE_HW_ID__SE_ID__SHIFT 0x0000000d +#define SQ_WAVE_HW_ID__SH_ID_MASK 0x00001000L +#define SQ_WAVE_HW_ID__SH_ID__SHIFT 0x0000000c +#define SQ_WAVE_HW_ID__SIMD_ID_MASK 0x00000030L +#define SQ_WAVE_HW_ID__SIMD_ID__SHIFT 0x00000004 +#define SQ_WAVE_HW_ID__STATE_ID_MASK 0x38000000L +#define SQ_WAVE_HW_ID__STATE_ID__SHIFT 0x0000001b +#define SQ_WAVE_HW_ID__TG_ID_MASK 0x000f0000L +#define SQ_WAVE_HW_ID__TG_ID__SHIFT 0x00000010 +#define SQ_WAVE_HW_ID__VM_ID_MASK 0x00f00000L +#define SQ_WAVE_HW_ID__VM_ID__SHIFT 0x00000014 +#define SQ_WAVE_HW_ID__WAVE_ID_MASK 0x0000000fL +#define SQ_WAVE_HW_ID__WAVE_ID__SHIFT 0x00000000 +#define SQ_WAVE_IB_DBG0__ECC_ST_MASK 0x00c00000L +#define SQ_WAVE_IB_DBG0__ECC_ST__SHIFT 0x00000016 +#define SQ_WAVE_IB_DBG0__HYB_CNT_MASK 0x06000000L +#define SQ_WAVE_IB_DBG0__HYB_CNT__SHIFT 0x00000019 +#define SQ_WAVE_IB_DBG0__IBUF_RPTR_MASK 0x00000300L +#define SQ_WAVE_IB_DBG0__IBUF_RPTR__SHIFT 0x00000008 +#define SQ_WAVE_IB_DBG0__IBUF_ST_MASK 0x00000007L +#define SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT 0x00000000 +#define SQ_WAVE_IB_DBG0__IBUF_WPTR_MASK 0x00000c00L +#define SQ_WAVE_IB_DBG0__IBUF_WPTR__SHIFT 0x0000000a +#define SQ_WAVE_IB_DBG0__INST_STR_ST_MASK 0x00070000L +#define SQ_WAVE_IB_DBG0__INST_STR_ST__SHIFT 0x00000010 +#define SQ_WAVE_IB_DBG0__IS_HYB_MASK 0x01000000L +#define SQ_WAVE_IB_DBG0__IS_HYB__SHIFT 0x00000018 +#define SQ_WAVE_IB_DBG0__KILL_MASK 0x08000000L +#define SQ_WAVE_IB_DBG0__KILL__SHIFT 0x0000001b +#define SQ_WAVE_IB_DBG0__MISC_CNT_MASK 0x00380000L +#define SQ_WAVE_IB_DBG0__MISC_CNT__SHIFT 0x00000013 +#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH_MASK 0x10000000L +#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH__SHIFT 0x0000001c +#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW_MASK 0x00000010L +#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW__SHIFT 0x00000004 +#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_MASK 0x000000e0L +#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT__SHIFT 0x00000005 +#define SQ_WAVE_IB_DBG0__PC_INVALID_MASK 0x00000008L +#define SQ_WAVE_IB_DBG0__PC_INVALID__SHIFT 0x00000003 +#define SQ_WAVE_IB_STS__EXP_CNT_MASK 0x00000070L +#define SQ_WAVE_IB_STS__EXP_CNT__SHIFT 0x00000004 +#define SQ_WAVE_IB_STS__LGKM_CNT_MASK 0x00001f00L +#define SQ_WAVE_IB_STS__LGKM_CNT__SHIFT 0x00000008 +#define SQ_WAVE_IB_STS__VALU_CNT_MASK 0x0000e000L +#define SQ_WAVE_IB_STS__VALU_CNT__SHIFT 0x0000000d +#define SQ_WAVE_IB_STS__VM_CNT_MASK 0x0000000fL +#define SQ_WAVE_IB_STS__VM_CNT__SHIFT 0x00000000 +#define SQ_WAVE_INST_DW0__INST_DW0_MASK 0xffffffffL +#define SQ_WAVE_INST_DW0__INST_DW0__SHIFT 0x00000000 +#define SQ_WAVE_INST_DW1__INST_DW1_MASK 0xffffffffL +#define SQ_WAVE_INST_DW1__INST_DW1__SHIFT 0x00000000 +#define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK 0x000000ffL +#define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT 0x00000000 +#define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK 0x001ff000L +#define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT 0x0000000c +#define SQ_WAVE_M0__M0_MASK 0xffffffffL +#define SQ_WAVE_M0__M0__SHIFT 0x00000000 +#define SQ_WAVE_MODE__CSP_MASK 0xe0000000L +#define SQ_WAVE_MODE__CSP__SHIFT 0x0000001d +#define SQ_WAVE_MODE__DEBUG_EN_MASK 0x00000800L +#define SQ_WAVE_MODE__DEBUG_EN__SHIFT 0x0000000b +#define SQ_WAVE_MODE__DX10_CLAMP_MASK 0x00000100L +#define SQ_WAVE_MODE__DX10_CLAMP__SHIFT 0x00000008 +#define SQ_WAVE_MODE__EXCP_EN_MASK 0x0007f000L +#define SQ_WAVE_MODE__EXCP_EN__SHIFT 0x0000000c +#define SQ_WAVE_MODE__FP_DENORM_MASK 0x000000f0L +#define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x00000004 +#define SQ_WAVE_MODE__FP_ROUND_MASK 0x0000000fL +#define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x00000000 +#define SQ_WAVE_MODE__IEEE_MASK 0x00000200L +#define SQ_WAVE_MODE__IEEE__SHIFT 0x00000009 +#define SQ_WAVE_MODE__LOD_CLAMPED_MASK 0x00000400L +#define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT 0x0000000a +#define SQ_WAVE_MODE__VSKIP_MASK 0x10000000L +#define SQ_WAVE_MODE__VSKIP__SHIFT 0x0000001c +#define SQ_WAVE_PC_HI__PC_HI_MASK 0x000000ffL +#define SQ_WAVE_PC_HI__PC_HI__SHIFT 0x00000000 +#define SQ_WAVE_PC_LO__PC_LO_MASK 0xffffffffL +#define SQ_WAVE_PC_LO__PC_LO__SHIFT 0x00000000 +#define SQ_WAVE_STATUS__COND_DBG_SYS_MASK 0x00200000L +#define SQ_WAVE_STATUS__COND_DBG_SYS__SHIFT 0x00000015 +#define SQ_WAVE_STATUS__COND_DBG_USER_MASK 0x00100000L +#define SQ_WAVE_STATUS__COND_DBG_USER__SHIFT 0x00000014 +#define SQ_WAVE_STATUS__DATA_ATC_MASK 0x00400000L +#define SQ_WAVE_STATUS__DATA_ATC__SHIFT 0x00000016 +#define SQ_WAVE_STATUS__DISPATCH_CACHE_CTRL_MASK 0x07000000L +#define SQ_WAVE_STATUS__DISPATCH_CACHE_CTRL__SHIFT 0x00000018 +#define SQ_WAVE_STATUS__ECC_ERR_MASK 0x00020000L +#define SQ_WAVE_STATUS__ECC_ERR__SHIFT 0x00000011 +#define SQ_WAVE_STATUS__EXECZ_MASK 0x00000200L +#define SQ_WAVE_STATUS__EXECZ__SHIFT 0x00000009 +#define SQ_WAVE_STATUS__EXPORT_RDY_MASK 0x00000100L +#define SQ_WAVE_STATUS__EXPORT_RDY__SHIFT 0x00000008 +#define SQ_WAVE_STATUS__HALT_MASK 0x00002000L +#define SQ_WAVE_STATUS__HALT__SHIFT 0x0000000d +#define SQ_WAVE_STATUS__IN_BARRIER_MASK 0x00001000L +#define SQ_WAVE_STATUS__IN_BARRIER__SHIFT 0x0000000c +#define SQ_WAVE_STATUS__INST_ATC_MASK 0x00800000L +#define SQ_WAVE_STATUS__INST_ATC__SHIFT 0x00000017 +#define SQ_WAVE_STATUS__IN_TG_MASK 0x00000800L +#define SQ_WAVE_STATUS__IN_TG__SHIFT 0x0000000b +#define SQ_WAVE_STATUS__MUST_EXPORT_MASK 0x08000000L +#define SQ_WAVE_STATUS__MUST_EXPORT__SHIFT 0x0000001b +#define SQ_WAVE_STATUS__PERF_EN_MASK 0x00080000L +#define SQ_WAVE_STATUS__PERF_EN__SHIFT 0x00000013 +#define SQ_WAVE_STATUS__PRIV_MASK 0x00000020L +#define SQ_WAVE_STATUS__PRIV__SHIFT 0x00000005 +#define SQ_WAVE_STATUS__SCC_MASK 0x00000001L +#define SQ_WAVE_STATUS__SCC__SHIFT 0x00000000 +#define SQ_WAVE_STATUS__SKIP_EXPORT_MASK 0x00040000L +#define SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT 0x00000012 +#define SQ_WAVE_STATUS__SPI_PRIO_MASK 0x00000006L +#define SQ_WAVE_STATUS__SPI_PRIO__SHIFT 0x00000001 +#define SQ_WAVE_STATUS__TRAP_EN_MASK 0x00000040L +#define SQ_WAVE_STATUS__TRAP_EN__SHIFT 0x00000006 +#define SQ_WAVE_STATUS__TRAP_MASK 0x00004000L +#define SQ_WAVE_STATUS__TRAP__SHIFT 0x0000000e +#define SQ_WAVE_STATUS__TTRACE_CU_EN_MASK 0x00008000L +#define SQ_WAVE_STATUS__TTRACE_CU_EN__SHIFT 0x0000000f +#define SQ_WAVE_STATUS__TTRACE_EN_MASK 0x00000080L +#define SQ_WAVE_STATUS__TTRACE_EN__SHIFT 0x00000007 +#define SQ_WAVE_STATUS__VALID_MASK 0x00010000L +#define SQ_WAVE_STATUS__VALID__SHIFT 0x00000010 +#define SQ_WAVE_STATUS__VCCZ_MASK 0x00000400L +#define SQ_WAVE_STATUS__VCCZ__SHIFT 0x0000000a +#define SQ_WAVE_STATUS__WAVE_PRIO_MASK 0x00000018L +#define SQ_WAVE_STATUS__WAVE_PRIO__SHIFT 0x00000003 +#define SQ_WAVE_TBA_HI__ADDR_HI_MASK 0x000000ffL +#define SQ_WAVE_TBA_HI__ADDR_HI__SHIFT 0x00000000 +#define SQ_WAVE_TBA_LO__ADDR_LO_MASK 0xffffffffL +#define SQ_WAVE_TBA_LO__ADDR_LO__SHIFT 0x00000000 +#define SQ_WAVE_TMA_HI__ADDR_HI_MASK 0x000000ffL +#define SQ_WAVE_TMA_HI__ADDR_HI__SHIFT 0x00000000 +#define SQ_WAVE_TMA_LO__ADDR_LO_MASK 0xffffffffL +#define SQ_WAVE_TMA_LO__ADDR_LO__SHIFT 0x00000000 +#define SQ_WAVE_TRAPSTS__DP_RATE_MASK 0xe0000000L +#define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT 0x0000001d +#define SQ_WAVE_TRAPSTS__EXCP_CYCLE_MASK 0x003f0000L +#define SQ_WAVE_TRAPSTS__EXCP_CYCLE__SHIFT 0x00000010 +#define SQ_WAVE_TRAPSTS__EXCP_MASK 0x0000007fL +#define SQ_WAVE_TRAPSTS__EXCP__SHIFT 0x00000000 +#define SQ_WAVE_TTMP0__DATA_MASK 0xffffffffL +#define SQ_WAVE_TTMP0__DATA__SHIFT 0x00000000 +#define SQ_WAVE_TTMP10__DATA_MASK 0xffffffffL +#define SQ_WAVE_TTMP10__DATA__SHIFT 0x00000000 +#define SQ_WAVE_TTMP11__DATA_MASK 0xffffffffL +#define SQ_WAVE_TTMP11__DATA__SHIFT 0x00000000 +#define SQ_WAVE_TTMP1__DATA_MASK 0xffffffffL +#define SQ_WAVE_TTMP1__DATA__SHIFT 0x00000000 +#define SQ_WAVE_TTMP2__DATA_MASK 0xffffffffL +#define SQ_WAVE_TTMP2__DATA__SHIFT 0x00000000 +#define SQ_WAVE_TTMP3__DATA_MASK 0xffffffffL +#define SQ_WAVE_TTMP3__DATA__SHIFT 0x00000000 +#define SQ_WAVE_TTMP4__DATA_MASK 0xffffffffL +#define SQ_WAVE_TTMP4__DATA__SHIFT 0x00000000 +#define SQ_WAVE_TTMP5__DATA_MASK 0xffffffffL +#define SQ_WAVE_TTMP5__DATA__SHIFT 0x00000000 +#define SQ_WAVE_TTMP6__DATA_MASK 0xffffffffL +#define SQ_WAVE_TTMP6__DATA__SHIFT 0x00000000 +#define SQ_WAVE_TTMP7__DATA_MASK 0xffffffffL +#define SQ_WAVE_TTMP7__DATA__SHIFT 0x00000000 +#define SQ_WAVE_TTMP8__DATA_MASK 0xffffffffL +#define SQ_WAVE_TTMP8__DATA__SHIFT 0x00000000 +#define SQ_WAVE_TTMP9__DATA_MASK 0xffffffffL +#define SQ_WAVE_TTMP9__DATA__SHIFT 0x00000000 +#define SX_DEBUG_1__DEBUG_DATA_MASK 0xffffff80L +#define SX_DEBUG_1__DEBUG_DATA__SHIFT 0x00000007 +#define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK 0x0000007fL +#define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT 0x00000000 +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY_MASK 0x80000000L +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY__SHIFT 0x0000001f +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY_MASK 0x40000000L +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY__SHIFT 0x0000001e +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY_MASK 0x20000000L +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY__SHIFT 0x0000001d +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY_MASK 0x10000000L +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY__SHIFT 0x0000001c +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY_MASK 0x08000000L +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY__SHIFT 0x0000001b +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY_MASK 0x04000000L +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY__SHIFT 0x0000001a +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY_MASK 0x02000000L +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY__SHIFT 0x00000019 +#define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY_MASK 0x00800000L +#define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY__SHIFT 0x00000017 +#define SX_DEBUG_BUSY_2__COL_DBIF0_READ_VALID_MASK 0x01000000L +#define SX_DEBUG_BUSY_2__COL_DBIF0_READ_VALID__SHIFT 0x00000018 +#define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY_MASK 0x00400000L +#define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY__SHIFT 0x00000016 +#define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY_MASK 0x00100000L +#define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY__SHIFT 0x00000014 +#define SX_DEBUG_BUSY_2__COL_DBIF1_READ_VALID_MASK 0x00200000L +#define SX_DEBUG_BUSY_2__COL_DBIF1_READ_VALID__SHIFT 0x00000015 +#define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY_MASK 0x00080000L +#define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY__SHIFT 0x00000013 +#define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY_MASK 0x00020000L +#define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY__SHIFT 0x00000011 +#define SX_DEBUG_BUSY_2__COL_DBIF2_READ_VALID_MASK 0x00040000L +#define SX_DEBUG_BUSY_2__COL_DBIF2_READ_VALID__SHIFT 0x00000012 +#define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY_MASK 0x00010000L +#define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY__SHIFT 0x00000010 +#define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY_MASK 0x00004000L +#define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY__SHIFT 0x0000000e +#define SX_DEBUG_BUSY_2__COL_DBIF3_READ_VALID_MASK 0x00008000L +#define SX_DEBUG_BUSY_2__COL_DBIF3_READ_VALID__SHIFT 0x0000000f +#define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY_MASK 0x00002000L +#define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY__SHIFT 0x0000000d +#define SX_DEBUG_BUSY_2__COL_REQ0_BUSY_MASK 0x00001000L +#define SX_DEBUG_BUSY_2__COL_REQ0_BUSY__SHIFT 0x0000000c +#define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0_MASK 0x00000400L +#define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0__SHIFT 0x0000000a +#define SX_DEBUG_BUSY_2__COL_REQ0_IDLE_MASK 0x00000800L +#define SX_DEBUG_BUSY_2__COL_REQ0_IDLE__SHIFT 0x0000000b +#define SX_DEBUG_BUSY_2__COL_REQ1_BUSY_MASK 0x00000200L +#define SX_DEBUG_BUSY_2__COL_REQ1_BUSY__SHIFT 0x00000009 +#define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0_MASK 0x00000080L +#define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0__SHIFT 0x00000007 +#define SX_DEBUG_BUSY_2__COL_REQ1_IDLE_MASK 0x00000100L +#define SX_DEBUG_BUSY_2__COL_REQ1_IDLE__SHIFT 0x00000008 +#define SX_DEBUG_BUSY_2__COL_REQ2_BUSY_MASK 0x00000040L +#define SX_DEBUG_BUSY_2__COL_REQ2_BUSY__SHIFT 0x00000006 +#define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0_MASK 0x00000010L +#define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0__SHIFT 0x00000004 +#define SX_DEBUG_BUSY_2__COL_REQ2_IDLE_MASK 0x00000020L +#define SX_DEBUG_BUSY_2__COL_REQ2_IDLE__SHIFT 0x00000005 +#define SX_DEBUG_BUSY_2__COL_REQ3_BUSY_MASK 0x00000008L +#define SX_DEBUG_BUSY_2__COL_REQ3_BUSY__SHIFT 0x00000003 +#define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0_MASK 0x00000002L +#define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0__SHIFT 0x00000001 +#define SX_DEBUG_BUSY_2__COL_REQ3_IDLE_MASK 0x00000004L +#define SX_DEBUG_BUSY_2__COL_REQ3_IDLE__SHIFT 0x00000002 +#define SX_DEBUG_BUSY_2__COL_SCBD_BUSY_MASK 0x00000001L +#define SX_DEBUG_BUSY_2__COL_SCBD_BUSY__SHIFT 0x00000000 +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY_MASK 0x80000000L +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY__SHIFT 0x0000001f +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY_MASK 0x40000000L +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY__SHIFT 0x0000001e +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY_MASK 0x20000000L +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY__SHIFT 0x0000001d +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY_MASK 0x10000000L +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY__SHIFT 0x0000001c +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY_MASK 0x08000000L +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY__SHIFT 0x0000001b +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY_MASK 0x04000000L +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY__SHIFT 0x0000001a +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY_MASK 0x02000000L +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY__SHIFT 0x00000019 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY_MASK 0x01000000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY__SHIFT 0x00000018 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY_MASK 0x00800000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY__SHIFT 0x00000017 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY_MASK 0x00400000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY__SHIFT 0x00000016 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY_MASK 0x00200000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY__SHIFT 0x00000015 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY_MASK 0x00100000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY__SHIFT 0x00000014 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY_MASK 0x00080000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY__SHIFT 0x00000013 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY_MASK 0x00040000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY__SHIFT 0x00000012 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY_MASK 0x00020000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY__SHIFT 0x00000011 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY_MASK 0x00010000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY__SHIFT 0x00000010 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY_MASK 0x00008000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY__SHIFT 0x0000000f +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY_MASK 0x00004000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY__SHIFT 0x0000000e +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY_MASK 0x00002000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY__SHIFT 0x0000000d +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY_MASK 0x00001000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY__SHIFT 0x0000000c +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY_MASK 0x00000800L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY__SHIFT 0x0000000b +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY_MASK 0x00000400L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY__SHIFT 0x0000000a +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY_MASK 0x00000200L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY__SHIFT 0x00000009 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY_MASK 0x00000100L +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY__SHIFT 0x00000008 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY_MASK 0x00000080L +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY__SHIFT 0x00000007 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY_MASK 0x00000040L +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY__SHIFT 0x00000006 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY_MASK 0x00000020L +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY__SHIFT 0x00000005 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY_MASK 0x00000010L +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY__SHIFT 0x00000004 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY_MASK 0x00000008L +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY__SHIFT 0x00000003 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY_MASK 0x00000004L +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY__SHIFT 0x00000002 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY_MASK 0x00000002L +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY__SHIFT 0x00000001 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY_MASK 0x00000001L +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY__SHIFT 0x00000000 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY_MASK 0x01000000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY__SHIFT 0x00000018 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY_MASK 0x00800000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY__SHIFT 0x00000017 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY_MASK 0x00400000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY__SHIFT 0x00000016 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY_MASK 0x00200000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY__SHIFT 0x00000015 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY_MASK 0x00100000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY__SHIFT 0x00000014 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY_MASK 0x00080000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY__SHIFT 0x00000013 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY_MASK 0x00040000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY__SHIFT 0x00000012 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY_MASK 0x00020000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY__SHIFT 0x00000011 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY_MASK 0x00010000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY__SHIFT 0x00000010 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY_MASK 0x00008000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY__SHIFT 0x0000000f +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY_MASK 0x00004000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY__SHIFT 0x0000000e +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY_MASK 0x00002000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY__SHIFT 0x0000000d +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY_MASK 0x00001000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY__SHIFT 0x0000000c +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY_MASK 0x00000800L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY__SHIFT 0x0000000b +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY_MASK 0x00000400L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY__SHIFT 0x0000000a +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY_MASK 0x00000200L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY__SHIFT 0x00000009 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY_MASK 0x00000100L +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY__SHIFT 0x00000008 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY_MASK 0x00000080L +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY__SHIFT 0x00000007 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY_MASK 0x00000040L +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY__SHIFT 0x00000006 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY_MASK 0x00000020L +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY__SHIFT 0x00000005 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY_MASK 0x00000010L +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY__SHIFT 0x00000004 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY_MASK 0x00000008L +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY__SHIFT 0x00000003 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY_MASK 0x00000004L +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY__SHIFT 0x00000002 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY_MASK 0x00000002L +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY__SHIFT 0x00000001 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY_MASK 0x00000001L +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY__SHIFT 0x00000000 +#define SX_DEBUG_BUSY_4__RESERVED_MASK 0xfe000000L +#define SX_DEBUG_BUSY_4__RESERVED__SHIFT 0x00000019 +#define SX_DEBUG_BUSY__ADDR_BUSYORVAL_MASK 0x80000000L +#define SX_DEBUG_BUSY__ADDR_BUSYORVAL__SHIFT 0x0000001f +#define SX_DEBUG_BUSY__CMD_BUSYORVAL_MASK 0x40000000L +#define SX_DEBUG_BUSY__CMD_BUSYORVAL__SHIFT 0x0000001e +#define SX_DEBUG_BUSY__PA_SX_BUSY_MASK 0x00000004L +#define SX_DEBUG_BUSY__PA_SX_BUSY__SHIFT 0x00000002 +#define SX_DEBUG_BUSY__PCCMD_VALID_MASK 0x08000000L +#define SX_DEBUG_BUSY__PCCMD_VALID__SHIFT 0x0000001b +#define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY_MASK 0x00080000L +#define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY__SHIFT 0x00000013 +#define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY_MASK 0x00040000L +#define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY__SHIFT 0x00000012 +#define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY_MASK 0x00020000L +#define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY__SHIFT 0x00000011 +#define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY_MASK 0x00010000L +#define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY__SHIFT 0x00000010 +#define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY_MASK 0x00008000L +#define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY__SHIFT 0x0000000f +#define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY_MASK 0x00004000L +#define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY__SHIFT 0x0000000e +#define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY_MASK 0x00002000L +#define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY__SHIFT 0x0000000d +#define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY_MASK 0x00001000L +#define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY__SHIFT 0x0000000c +#define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY_MASK 0x00000800L +#define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY__SHIFT 0x0000000b +#define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY_MASK 0x00000400L +#define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY__SHIFT 0x0000000a +#define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY_MASK 0x00000200L +#define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY__SHIFT 0x00000009 +#define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY_MASK 0x00000100L +#define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY__SHIFT 0x00000008 +#define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY_MASK 0x00000080L +#define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY__SHIFT 0x00000007 +#define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY_MASK 0x00000040L +#define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY__SHIFT 0x00000006 +#define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY_MASK 0x00000020L +#define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY__SHIFT 0x00000005 +#define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY_MASK 0x00000010L +#define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY__SHIFT 0x00000004 +#define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS_MASK 0x00000001L +#define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS__SHIFT 0x00000000 +#define SX_DEBUG_BUSY__POS_INMUX_VALID_MASK 0x00100000L +#define SX_DEBUG_BUSY__POS_INMUX_VALID__SHIFT 0x00000014 +#define SX_DEBUG_BUSY__POS_REQUESTER_BUSY_MASK 0x00000002L +#define SX_DEBUG_BUSY__POS_REQUESTER_BUSY__SHIFT 0x00000001 +#define SX_DEBUG_BUSY__POS_SCBD_BUSY_MASK 0x00000008L +#define SX_DEBUG_BUSY__POS_SCBD_BUSY__SHIFT 0x00000003 +#define SX_DEBUG_BUSY__VDATA0_VALID_MASK 0x20000000L +#define SX_DEBUG_BUSY__VDATA0_VALID__SHIFT 0x0000001d +#define SX_DEBUG_BUSY__VDATA1_VALID_MASK 0x10000000L +#define SX_DEBUG_BUSY__VDATA1_VALID__SHIFT 0x0000001c +#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1_MASK 0x04000000L +#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1__SHIFT 0x0000001a +#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2_MASK 0x02000000L +#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2__SHIFT 0x00000019 +#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3_MASK 0x01000000L +#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3__SHIFT 0x00000018 +#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1_MASK 0x00800000L +#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1__SHIFT 0x00000017 +#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2_MASK 0x00400000L +#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2__SHIFT 0x00000016 +#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3_MASK 0x00200000L +#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3__SHIFT 0x00000015 +#define SXIFCCG_DEBUG_REG0__point_address_MASK 0x000001c0L +#define SXIFCCG_DEBUG_REG0__point_address__SHIFT 0x00000006 +#define SXIFCCG_DEBUG_REG0__position_address_MASK 0x0000003fL +#define SXIFCCG_DEBUG_REG0__position_address__SHIFT 0x00000000 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance_MASK 0x80000000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance__SHIFT 0x0000001f +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc_MASK 0x40000000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc__SHIFT 0x0000001e +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel_MASK 0x0c000000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel__SHIFT 0x0000001a +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci_MASK 0x03ff0000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci__SHIFT 0x00000010 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask_MASK 0x0000f000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask__SHIFT 0x0000000c +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id_MASK 0x30000000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id__SHIFT 0x0000001c +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx_MASK 0x00000e00L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx__SHIFT 0x00000009 +#define SXIFCCG_DEBUG_REG1__aux_sel_MASK 0x00300000L +#define SXIFCCG_DEBUG_REG1__aux_sel__SHIFT 0x00000014 +#define SXIFCCG_DEBUG_REG1__available_positions_MASK 0x0000007fL +#define SXIFCCG_DEBUG_REG1__available_positions__SHIFT 0x00000000 +#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0_MASK 0xf0000000L +#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0__SHIFT 0x0000001c +#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1_MASK 0x0f000000L +#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1__SHIFT 0x00000018 +#define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp_MASK 0x000f0000L +#define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp__SHIFT 0x00000010 +#define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena_MASK 0x00008000L +#define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena__SHIFT 0x0000000f +#define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents_MASK 0x00007c00L +#define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents__SHIFT 0x0000000a +#define SXIFCCG_DEBUG_REG1__sx_receive_indx_MASK 0x00000380L +#define SXIFCCG_DEBUG_REG1__sx_receive_indx__SHIFT 0x00000007 +#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0_MASK 0x00800000L +#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0__SHIFT 0x00000017 +#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1_MASK 0x00400000L +#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1__SHIFT 0x00000016 +#define SXIFCCG_DEBUG_REG2__param_cache_base_MASK 0x0000007fL +#define SXIFCCG_DEBUG_REG2__param_cache_base__SHIFT 0x00000000 +#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded_MASK 0x00008000L +#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded__SHIFT 0x0000000f +#define SXIFCCG_DEBUG_REG2__req_active_verts_MASK 0x007f0000L +#define SXIFCCG_DEBUG_REG2__req_active_verts__SHIFT 0x00000010 +#define SXIFCCG_DEBUG_REG2__sx_aux_MASK 0x00000180L +#define SXIFCCG_DEBUG_REG2__sx_aux__SHIFT 0x00000007 +#define SXIFCCG_DEBUG_REG2__sx_request_indx_MASK 0x00007e00L +#define SXIFCCG_DEBUG_REG2__sx_request_indx__SHIFT 0x00000009 +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts_MASK 0xfc000000L +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts__SHIFT 0x0000001a +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx_MASK 0x03800000L +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx__SHIFT 0x00000017 +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO_MASK 0x000000ffL +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO__SHIFT 0x00000000 +#define SXIFCCG_DEBUG_REG3__available_positions_MASK 0x001fc000L +#define SXIFCCG_DEBUG_REG3__available_positions__SHIFT 0x0000000e +#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full_MASK 0x20000000L +#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full__SHIFT 0x0000001d +#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write_MASK 0x80000000L +#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write__SHIFT 0x0000001f +#define SXIFCCG_DEBUG_REG3__current_state_MASK 0x00600000L +#define SXIFCCG_DEBUG_REG3__current_state__SHIFT 0x00000015 +#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena_MASK 0x00002000L +#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena__SHIFT 0x0000000d +#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena_MASK 0x00001000L +#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena__SHIFT 0x0000000c +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty_MASK 0x02000000L +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty__SHIFT 0x00000019 +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full_MASK 0x04000000L +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full__SHIFT 0x0000001a +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write_MASK 0x40000000L +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write__SHIFT 0x0000001e +#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty_MASK 0x00800000L +#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty__SHIFT 0x00000017 +#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable_MASK 0x00000f00L +#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable__SHIFT 0x00000008 +#define SXIFCCG_DEBUG_REG3__vertex_fifo_full_MASK 0x01000000L +#define SXIFCCG_DEBUG_REG3__vertex_fifo_full__SHIFT 0x00000018 +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty_MASK 0x08000000L +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty__SHIFT 0x0000001b +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full_MASK 0x10000000L +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full__SHIFT 0x0000001c +#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x000003ffL +#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x00000000 +#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0x000ffc00L +#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0x0000000a +#define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L +#define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0x000ffc00L +#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0x0000000a +#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL +#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 +#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2_MASK 0x000003ffL +#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x00000000 +#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3_MASK 0x000ffc00L +#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0x0000000a +#define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L +#define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0x000ffc00L +#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0x0000000a +#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL +#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 +#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00f00000L +#define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0x000ffc00L +#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0x0000000a +#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL +#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 +#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00f00000L +#define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0x000ffc00L +#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0x0000000a +#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL +#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 +#define TA_BC_BASE_ADDR__ADDRESS_MASK 0xffffffffL +#define TA_BC_BASE_ADDR__ADDRESS__SHIFT 0x00000000 +#define TA_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000ffL +#define TA_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x00000000 +#define TA_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L +#define TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 +#define TA_CGTT_CTRL__ON_DELAY_MASK 0x0000000fL +#define TA_CGTT_CTRL__ON_DELAY__SHIFT 0x00000000 +#define TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f +#define TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e +#define TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d +#define TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c +#define TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b +#define TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a +#define TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 +#define TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 +#define TA_CNTL__ALIGNER_CREDIT_MASK 0x001f0000L +#define TA_CNTL__ALIGNER_CREDIT__SHIFT 0x00000010 +#define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK 0x00010000L +#define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT 0x00000010 +#define TA_CNTL__TC_DATA_CREDIT_MASK 0x0000e000L +#define TA_CNTL__TC_DATA_CREDIT__SHIFT 0x0000000d +#define TA_CNTL__TD_FIFO_CREDIT_MASK 0xffc00000L +#define TA_CNTL__TD_FIFO_CREDIT__SHIFT 0x00000016 +#define TA_CS_BC_BASE_ADDR__ADDRESS_MASK 0xffffffffL +#define TA_CS_BC_BASE_ADDR__ADDRESS__SHIFT 0x00000000 +#define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000ffL +#define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x00000000 +#define TA_DEBUG_DATA__DATA_MASK 0xffffffffL +#define TA_DEBUG_DATA__DATA__SHIFT 0x00000000 +#define TA_DEBUG_INDEX__INDEX_MASK 0x0000001fL +#define TA_DEBUG_INDEX__INDEX__SHIFT 0x00000000 +#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000L +#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x0000001c +#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0f000000L +#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x00000018 +#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000000ffL +#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 +#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0003fc00L +#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a +#define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L +#define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0f000000L +#define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x00000018 +#define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L +#define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c +#define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0003fc00L +#define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a +#define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL +#define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 +#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L +#define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define TA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0f000000L +#define TA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x00000018 +#define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L +#define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c +#define TA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x0003fc00L +#define TA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0x0000000a +#define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL +#define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 +#define TA_SCRATCH__SCRATCH_MASK 0xffffffffL +#define TA_SCRATCH__SCRATCH__SHIFT 0x00000000 +#define TA_STATUS__AL_BUSY_MASK 0x40000000L +#define TA_STATUS__AL_BUSY__SHIFT 0x0000001e +#define TA_STATUS__BUSY_MASK 0x80000000L +#define TA_STATUS__BUSY__SHIFT 0x0000001f +#define TA_STATUS__FA_BUSY_MASK 0x20000000L +#define TA_STATUS__FA_BUSY__SHIFT 0x0000001d +#define TA_STATUS__FA_LFIFO_EMPTYB_MASK 0x00200000L +#define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT 0x00000015 +#define TA_STATUS__FA_PFIFO_EMPTYB_MASK 0x00100000L +#define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x00000014 +#define TA_STATUS__FA_SFIFO_EMPTYB_MASK 0x00400000L +#define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT 0x00000016 +#define TA_STATUS__FG_BUSY_MASK 0x02000000L +#define TA_STATUS__FG_BUSY__SHIFT 0x00000019 +#define TA_STATUS__FG_LFIFO_EMPTYB_MASK 0x00002000L +#define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0x0000000d +#define TA_STATUS__FG_PFIFO_EMPTYB_MASK 0x00001000L +#define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0x0000000c +#define TA_STATUS__FG_SFIFO_EMPTYB_MASK 0x00004000L +#define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT 0x0000000e +#define TA_STATUS__FL_BUSY_MASK 0x08000000L +#define TA_STATUS__FL_BUSY__SHIFT 0x0000001b +#define TA_STATUS__FL_LFIFO_EMPTYB_MASK 0x00020000L +#define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT 0x00000011 +#define TA_STATUS__FL_PFIFO_EMPTYB_MASK 0x00010000L +#define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT 0x00000010 +#define TA_STATUS__FL_SFIFO_EMPTYB_MASK 0x00040000L +#define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT 0x00000012 +#define TA_STATUS__IN_BUSY_MASK 0x01000000L +#define TA_STATUS__IN_BUSY__SHIFT 0x00000018 +#define TA_STATUS__LA_BUSY_MASK 0x04000000L +#define TA_STATUS__LA_BUSY__SHIFT 0x0000001a +#define TA_STATUS__TA_BUSY_MASK 0x10000000L +#define TA_STATUS__TA_BUSY__SHIFT 0x0000001c +#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L +#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 +#define TCA_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000fL +#define TCA_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x00000000 +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 +#define TCA_CTRL__HOLE_TIMEOUT_MASK 0x0000000fL +#define TCA_CTRL__HOLE_TIMEOUT__SHIFT 0x00000000 +#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0f000000L +#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x00000018 +#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000L +#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x0000001c +#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003ffL +#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 +#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L +#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a +#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L +#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0f000000L +#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x00000018 +#define TCA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L +#define TCA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c +#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000ffc00L +#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a +#define TCA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL +#define TCA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 +#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0f000000L +#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x00000018 +#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf0000000L +#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x0000001c +#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003ffL +#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x00000000 +#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000ffc00L +#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0x0000000a +#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L +#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0f000000L +#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x00000018 +#define TCA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L +#define TCA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c +#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000ffc00L +#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0x0000000a +#define TCA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL +#define TCA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 +#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00f00000L +#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define TCA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000L +#define TCA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x0000001c +#define TCA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL +#define TCA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 +#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00f00000L +#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define TCA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000L +#define TCA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x0000001c +#define TCA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL +#define TCA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 +#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L +#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 +#define TCC_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000fL +#define TCC_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x00000000 +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 +#define TCC_CTRL__CACHE_SIZE_MASK 0x00000003L +#define TCC_CTRL__CACHE_SIZE__SHIFT 0x00000000 +#define TCC_CTRL__LATENCY_FIFO_SIZE_MASK 0x000f0000L +#define TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x00000010 +#define TCC_CTRL__RATE_MASK 0x0000000cL +#define TCC_CTRL__RATE__SHIFT 0x00000002 +#define TCC_CTRL__SRC_FIFO_SIZE_MASK 0x0000f000L +#define TCC_CTRL__SRC_FIFO_SIZE__SHIFT 0x0000000c +#define TCC_CTRL__WB_OR_INV_ALL_VMIDS_MASK 0x00100000L +#define TCC_CTRL__WB_OR_INV_ALL_VMIDS__SHIFT 0x00000014 +#define TCC_CTRL__WRITEBACK_MARGIN_MASK 0x000000f0L +#define TCC_CTRL__WRITEBACK_MARGIN__SHIFT 0x00000004 +#define TCC_EDC_COUNTER__DED_COUNT_MASK 0x000f0000L +#define TCC_EDC_COUNTER__DED_COUNT__SHIFT 0x00000010 +#define TCC_EDC_COUNTER__SEC_COUNT_MASK 0x0000000fL +#define TCC_EDC_COUNTER__SEC_COUNT__SHIFT 0x00000000 +#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0f000000L +#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x00000018 +#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000L +#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x0000001c +#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003ffL +#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 +#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L +#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a +#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L +#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0f000000L +#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x00000018 +#define TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L +#define TCC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c +#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000ffc00L +#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a +#define TCC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL +#define TCC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 +#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0f000000L +#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x00000018 +#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf0000000L +#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x0000001c +#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003ffL +#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x00000000 +#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000ffc00L +#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0x0000000a +#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L +#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0f000000L +#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x00000018 +#define TCC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L +#define TCC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c +#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000ffc00L +#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0x0000000a +#define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL +#define TCC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 +#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00f00000L +#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define TCC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000L +#define TCC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x0000001c +#define TCC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL +#define TCC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 +#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00f00000L +#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define TCC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000L +#define TCC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x0000001c +#define TCC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL +#define TCC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 +#define TCI_CNTL_1__REQ_FIFO_DEPTH_MASK 0x00ff0000L +#define TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT 0x00000010 +#define TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK 0x0000ffffL +#define TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT 0x00000000 +#define TCI_CNTL_1__WDATA_RAM_DEPTH_MASK 0xff000000L +#define TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT 0x00000018 +#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK 0x00000001L +#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT 0x00000000 +#define TCI_CNTL_2__TCA_MAX_CREDIT_MASK 0x000001feL +#define TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT 0x00000001 +#define TCI_STATUS__TCI_BUSY_MASK 0x00000001L +#define TCI_STATUS__TCI_BUSY__SHIFT 0x00000000 +#define TCP_ADDR_CONFIG__COLHI_WIDTH_MASK 0x000001c0L +#define TCP_ADDR_CONFIG__COLHI_WIDTH__SHIFT 0x00000006 +#define TCP_ADDR_CONFIG__NUM_BANKS_MASK 0x00000030L +#define TCP_ADDR_CONFIG__NUM_BANKS__SHIFT 0x00000004 +#define TCP_ADDR_CONFIG__NUM_TCC_BANKS_MASK 0x0000000fL +#define TCP_ADDR_CONFIG__NUM_TCC_BANKS__SHIFT 0x00000000 +#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI_MASK 0x00000200L +#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI__SHIFT 0x00000009 +#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS_MASK 0x00000700L +#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS__SHIFT 0x00000008 +#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT_MASK 0x07000000L +#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT__SHIFT 0x00000018 +#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS_MASK 0x00000007L +#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS__SHIFT 0x00000000 +#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT_MASK 0x00070000L +#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT__SHIFT 0x00000010 +#define TCP_CHAN_STEER_HI__CHAN8_MASK 0x0000000fL +#define TCP_CHAN_STEER_HI__CHAN8__SHIFT 0x00000000 +#define TCP_CHAN_STEER_HI__CHAN9_MASK 0x000000f0L +#define TCP_CHAN_STEER_HI__CHAN9__SHIFT 0x00000004 +#define TCP_CHAN_STEER_HI__CHANA_MASK 0x00000f00L +#define TCP_CHAN_STEER_HI__CHANA__SHIFT 0x00000008 +#define TCP_CHAN_STEER_HI__CHANB_MASK 0x0000f000L +#define TCP_CHAN_STEER_HI__CHANB__SHIFT 0x0000000c +#define TCP_CHAN_STEER_HI__CHANC_MASK 0x000f0000L +#define TCP_CHAN_STEER_HI__CHANC__SHIFT 0x00000010 +#define TCP_CHAN_STEER_HI__CHAND_MASK 0x00f00000L +#define TCP_CHAN_STEER_HI__CHAND__SHIFT 0x00000014 +#define TCP_CHAN_STEER_HI__CHANE_MASK 0x0f000000L +#define TCP_CHAN_STEER_HI__CHANE__SHIFT 0x00000018 +#define TCP_CHAN_STEER_HI__CHANF_MASK 0xf0000000L +#define TCP_CHAN_STEER_HI__CHANF__SHIFT 0x0000001c +#define TCP_CHAN_STEER_LO__CHAN0_MASK 0x0000000fL +#define TCP_CHAN_STEER_LO__CHAN0__SHIFT 0x00000000 +#define TCP_CHAN_STEER_LO__CHAN1_MASK 0x000000f0L +#define TCP_CHAN_STEER_LO__CHAN1__SHIFT 0x00000004 +#define TCP_CHAN_STEER_LO__CHAN2_MASK 0x00000f00L +#define TCP_CHAN_STEER_LO__CHAN2__SHIFT 0x00000008 +#define TCP_CHAN_STEER_LO__CHAN3_MASK 0x0000f000L +#define TCP_CHAN_STEER_LO__CHAN3__SHIFT 0x0000000c +#define TCP_CHAN_STEER_LO__CHAN4_MASK 0x000f0000L +#define TCP_CHAN_STEER_LO__CHAN4__SHIFT 0x00000010 +#define TCP_CHAN_STEER_LO__CHAN5_MASK 0x00f00000L +#define TCP_CHAN_STEER_LO__CHAN5__SHIFT 0x00000014 +#define TCP_CHAN_STEER_LO__CHAN6_MASK 0x0f000000L +#define TCP_CHAN_STEER_LO__CHAN6__SHIFT 0x00000018 +#define TCP_CHAN_STEER_LO__CHAN7_MASK 0xf0000000L +#define TCP_CHAN_STEER_LO__CHAN7__SHIFT 0x0000001c +#define TCP_CNTL__DISABLE_Z_MAP_MASK 0x10000000L +#define TCP_CNTL__DISABLE_Z_MAP__SHIFT 0x0000001c +#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE_MASK 0x00000020L +#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE__SHIFT 0x00000005 +#define TCP_CNTL__FLAT_BUF_HASH_ENABLE_MASK 0x00000010L +#define TCP_CNTL__FLAT_BUF_HASH_ENABLE__SHIFT 0x00000004 +#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT_MASK 0x0fc00000L +#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT__SHIFT 0x00000016 +#define TCP_CNTL__FORCE_EOW_TOTAL_CNT_MASK 0x001f8000L +#define TCP_CNTL__FORCE_EOW_TOTAL_CNT__SHIFT 0x0000000f +#define TCP_CNTL__FORCE_HIT_MASK 0x00000001L +#define TCP_CNTL__FORCE_HIT__SHIFT 0x00000000 +#define TCP_CNTL__FORCE_MISS_MASK 0x00000002L +#define TCP_CNTL__FORCE_MISS__SHIFT 0x00000001 +#define TCP_CNTL__INV_ALL_VMIDS_MASK 0x20000000L +#define TCP_CNTL__INV_ALL_VMIDS__SHIFT 0x0000001d +#define TCP_CNTL__L1_SIZE_MASK 0x0000000cL +#define TCP_CNTL__L1_SIZE__SHIFT 0x00000002 +#define TCP_CREDIT__LFIFO_CREDIT_MASK 0x000003ffL +#define TCP_CREDIT__LFIFO_CREDIT__SHIFT 0x00000000 +#define TCP_CREDIT__REQ_FIFO_CREDIT_MASK 0x007f0000L +#define TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT 0x00000010 +#define TCP_CREDIT__TD_CREDIT_MASK 0xe0000000L +#define TCP_CREDIT__TD_CREDIT__SHIFT 0x0000001d +#define TCP_EDC_COUNTER__DED_COUNT_MASK 0x000f0000L +#define TCP_EDC_COUNTER__DED_COUNT__SHIFT 0x00000010 +#define TCP_EDC_COUNTER__SEC_COUNT_MASK 0x0000000fL +#define TCP_EDC_COUNTER__SEC_COUNT__SHIFT 0x00000000 +#define TCP_INVALIDATE__START_MASK 0x00000001L +#define TCP_INVALIDATE__START__SHIFT 0x00000000 +#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000L +#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x0000001c +#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0f000000L +#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x00000018 +#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003ffL +#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 +#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L +#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a +#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L +#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0f000000L +#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x00000018 +#define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L +#define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c +#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000ffc00L +#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a +#define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL +#define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 +#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000L +#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x0000001c +#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0f000000L +#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x00000018 +#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003ffL +#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x00000000 +#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000ffc00L +#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0x0000000a +#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L +#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0f000000L +#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x00000018 +#define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L +#define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c +#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000ffc00L +#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0x0000000a +#define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL +#define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 +#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00f00000L +#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000L +#define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x0000001c +#define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL +#define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 +#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00f00000L +#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000L +#define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x0000001c +#define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL +#define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 +#define TCP_STATUS__TCP_BUSY_MASK 0x00000001L +#define TCP_STATUS__TCP_BUSY__SHIFT 0x00000000 +#define TD_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L +#define TD_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 +#define TD_CGTT_CTRL__ON_DELAY_MASK 0x0000000fL +#define TD_CGTT_CTRL__ON_DELAY__SHIFT 0x00000000 +#define TD_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +#define TD_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f +#define TD_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define TD_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e +#define TD_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d +#define TD_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define TD_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c +#define TD_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define TD_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b +#define TD_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define TD_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a +#define TD_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define TD_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 +#define TD_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define TD_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 +#define TD_CNTL__DISABLE_POWER_THROTTLE_MASK 0x00100000L +#define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT 0x00000014 +#define TD_CNTL__EXTEND_LDS_STALL_MASK 0x00000600L +#define TD_CNTL__EXTEND_LDS_STALL__SHIFT 0x00000009 +#define TD_CNTL__GATHER4_DX9_MODE_MASK 0x00080000L +#define TD_CNTL__GATHER4_DX9_MODE__SHIFT 0x00000013 +#define TD_CNTL__GATHER4_FLOAT_MODE_MASK 0x00010000L +#define TD_CNTL__GATHER4_FLOAT_MODE__SHIFT 0x00000010 +#define TD_CNTL__LD_FLOAT_MODE_MASK 0x00040000L +#define TD_CNTL__LD_FLOAT_MODE__SHIFT 0x00000012 +#define TD_CNTL__LDS_STALL_PHASE_ADJUST_MASK 0x00001800L +#define TD_CNTL__LDS_STALL_PHASE_ADJUST__SHIFT 0x0000000b +#define TD_CNTL__PAD_STALL_EN_MASK 0x00000100L +#define TD_CNTL__PAD_STALL_EN__SHIFT 0x00000008 +#define TD_CNTL__PRECISION_COMPATIBILITY_MASK 0x00008000L +#define TD_CNTL__PRECISION_COMPATIBILITY__SHIFT 0x0000000f +#define TD_CNTL__SYNC_PHASE_SH_MASK 0x00000003L +#define TD_CNTL__SYNC_PHASE_SH__SHIFT 0x00000000 +#define TD_CNTL__SYNC_PHASE_VC_SMX_MASK 0x00000030L +#define TD_CNTL__SYNC_PHASE_VC_SMX__SHIFT 0x00000004 +#define TD_DEBUG_DATA__DATA_MASK 0x00ffffffL +#define TD_DEBUG_DATA__DATA__SHIFT 0x00000000 +#define TD_DEBUG_INDEX__INDEX_MASK 0x0000001fL +#define TD_DEBUG_INDEX__INDEX__SHIFT 0x00000000 +#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000L +#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x0000001c +#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0f000000L +#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x00000018 +#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000000ffL +#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 +#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0003fc00L +#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a +#define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L +#define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0f000000L +#define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x00000018 +#define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L +#define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c +#define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0003fc00L +#define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a +#define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL +#define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 +#define TD_SCRATCH__SCRATCH_MASK 0xffffffffL +#define TD_SCRATCH__SCRATCH__SHIFT 0x00000000 +#define TD_STATUS__BUSY_MASK 0x80000000L +#define TD_STATUS__BUSY__SHIFT 0x0000001f +#define USER_SQC_BANK_DISABLE__SQC0_BANK_DISABLE_MASK 0x000f0000L +#define USER_SQC_BANK_DISABLE__SQC0_BANK_DISABLE__SHIFT 0x00000010 +#define USER_SQC_BANK_DISABLE__SQC1_BANK_DISABLE_MASK 0x00f00000L +#define USER_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT 0x00000014 +#define USER_SQC_BANK_DISABLE__SQC2_BANK_DISABLE_MASK 0x0f000000L +#define USER_SQC_BANK_DISABLE__SQC2_BANK_DISABLE__SHIFT 0x00000018 +#define USER_SQC_BANK_DISABLE__SQC3_BANK_DISABLE_MASK 0xf0000000L +#define USER_SQC_BANK_DISABLE__SQC3_BANK_DISABLE__SHIFT 0x0000001c +#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK 0x000000c0L +#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT 0x00000006 +#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK 0x00000003L +#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT 0x00000000 +#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK 0x00000800L +#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT 0x0000000b +#define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK 0x001f0000L +#define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT 0x00000010 +#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK 0x00001000L +#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT 0x0000000c +#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK 0x00002000L +#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT 0x0000000d +#define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK 0x00000200L +#define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT 0x00000009 +#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK 0x00000020L +#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT 0x00000005 +#define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x00000001L +#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x00000000 +#define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK 0x00000080L +#define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT 0x00000007 +#define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK 0x00000100L +#define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT 0x00000008 +#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x00000004L +#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x00000002 +#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x00000002L +#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x00000001 +#define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK 0x00000040L +#define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT 0x00000006 +#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x00000008L +#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x00000003 +#define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK 0x00000200L +#define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT 0x00000009 +#define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK 0x00000010L +#define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT 0x00000004 +#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x00000020L +#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x00000005 +#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX_MASK 0x0000003fL +#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX__SHIFT 0x00000000 +#define VGT_DEBUG_CNTL__VGT_DEBUG_SEL_BUS_B_MASK 0x00000040L +#define VGT_DEBUG_CNTL__VGT_DEBUG_SEL_BUS_B__SHIFT 0x00000006 +#define VGT_DEBUG_DATA__DATA_MASK 0xffffffffL +#define VGT_DEBUG_DATA__DATA__SHIFT 0x00000000 +#define VGT_DEBUG_REG0__cm_busy_MASK 0x00008000L +#define VGT_DEBUG_REG0__cm_busy__SHIFT 0x0000000f +#define VGT_DEBUG_REG0__combined_out_busy_MASK 0x00200000L +#define VGT_DEBUG_REG0__combined_out_busy__SHIFT 0x00000015 +#define VGT_DEBUG_REG0__core_clk_busy_MASK 0x04000000L +#define VGT_DEBUG_REG0__core_clk_busy__SHIFT 0x0000001a +#define VGT_DEBUG_REG0__frmt_busy_MASK 0x00020000L +#define VGT_DEBUG_REG0__frmt_busy__SHIFT 0x00000011 +#define VGT_DEBUG_REG0__gog_busy_MASK 0x00010000L +#define VGT_DEBUG_REG0__gog_busy__SHIFT 0x00000010 +#define VGT_DEBUG_REG0__gs_busy_MASK 0x00001000L +#define VGT_DEBUG_REG0__gs_busy__SHIFT 0x0000000c +#define VGT_DEBUG_REG0__gs_clk_busy_MASK 0x08000000L +#define VGT_DEBUG_REG0__gs_clk_busy__SHIFT 0x0000001b +#define VGT_DEBUG_REG0__pa_interfaces_busy_MASK 0x00800000L +#define VGT_DEBUG_REG0__pa_interfaces_busy__SHIFT 0x00000017 +#define VGT_DEBUG_REG0__pi_busy_MASK 0x00000100L +#define VGT_DEBUG_REG0__pi_busy__SHIFT 0x00000008 +#define VGT_DEBUG_REG0__pt_pi_busy_MASK 0x00000400L +#define VGT_DEBUG_REG0__pt_pi_busy__SHIFT 0x0000000a +#define VGT_DEBUG_REG0__rcm_busy_MASK 0x00002000L +#define VGT_DEBUG_REG0__rcm_busy__SHIFT 0x0000000d +#define VGT_DEBUG_REG0__reg_clk_busy_MASK 0x01000000L +#define VGT_DEBUG_REG0__reg_clk_busy__SHIFT 0x00000018 +#define VGT_DEBUG_REG0__sclk_core_vld_MASK 0x20000000L +#define VGT_DEBUG_REG0__sclk_core_vld__SHIFT 0x0000001d +#define VGT_DEBUG_REG0__sclk_gs_vld_MASK 0x40000000L +#define VGT_DEBUG_REG0__sclk_gs_vld__SHIFT 0x0000001e +#define VGT_DEBUG_REG0__SPARE0_MASK 0x80000000L +#define VGT_DEBUG_REG0__SPARE0__SHIFT 0x0000001f +#define VGT_DEBUG_REG0__SPARE10_MASK 0x00040000L +#define VGT_DEBUG_REG0__SPARE10__SHIFT 0x00000012 +#define VGT_DEBUG_REG0__SPARE1_MASK 0x10000000L +#define VGT_DEBUG_REG0__SPARE1__SHIFT 0x0000001c +#define VGT_DEBUG_REG0__SPARE2_MASK 0x02000000L +#define VGT_DEBUG_REG0__SPARE2__SHIFT 0x00000019 +#define VGT_DEBUG_REG0__SPARE3_MASK 0x00100000L +#define VGT_DEBUG_REG0__SPARE3__SHIFT 0x00000014 +#define VGT_DEBUG_REG0__SPARE4_MASK 0x00000080L +#define VGT_DEBUG_REG0__SPARE4__SHIFT 0x00000007 +#define VGT_DEBUG_REG0__SPARE5_MASK 0x00000040L +#define VGT_DEBUG_REG0__SPARE5__SHIFT 0x00000006 +#define VGT_DEBUG_REG0__SPARE6_MASK 0x00000020L +#define VGT_DEBUG_REG0__SPARE6__SHIFT 0x00000005 +#define VGT_DEBUG_REG0__SPARE7_MASK 0x00000010L +#define VGT_DEBUG_REG0__SPARE7__SHIFT 0x00000004 +#define VGT_DEBUG_REG0__SPARE8_MASK 0x00000008L +#define VGT_DEBUG_REG0__SPARE8__SHIFT 0x00000003 +#define VGT_DEBUG_REG0__SPARE9_MASK 0x00000002L +#define VGT_DEBUG_REG0__SPARE9__SHIFT 0x00000001 +#define VGT_DEBUG_REG0__spi_vs_interfaces_busy_MASK 0x00400000L +#define VGT_DEBUG_REG0__spi_vs_interfaces_busy__SHIFT 0x00000016 +#define VGT_DEBUG_REG0__te11_pi_busy_MASK 0x00080000L +#define VGT_DEBUG_REG0__te11_pi_busy__SHIFT 0x00000013 +#define VGT_DEBUG_REG0__te_pi_busy_MASK 0x00000800L +#define VGT_DEBUG_REG0__te_pi_busy__SHIFT 0x0000000b +#define VGT_DEBUG_REG0__tm_busy_MASK 0x00004000L +#define VGT_DEBUG_REG0__tm_busy__SHIFT 0x0000000e +#define VGT_DEBUG_REG0__vgt_busy_extended_MASK 0x00000001L +#define VGT_DEBUG_REG0__vgt_busy_extended__SHIFT 0x00000000 +#define VGT_DEBUG_REG0__vgt_busy_MASK 0x00000004L +#define VGT_DEBUG_REG0__vgt_busy__SHIFT 0x00000002 +#define VGT_DEBUG_REG0__vr_pi_busy_MASK 0x00000200L +#define VGT_DEBUG_REG0__vr_pi_busy__SHIFT 0x00000009 +#define VGT_DEBUG_REG10__eopg_r2_q_MASK 0x00000020L +#define VGT_DEBUG_REG10__eopg_r2_q__SHIFT 0x00000005 +#define VGT_DEBUG_REG10__eotg_r2_q_MASK 0x00000040L +#define VGT_DEBUG_REG10__eotg_r2_q__SHIFT 0x00000006 +#define VGT_DEBUG_REG10__es_rb_space_avail_r2_q_8_0_MASK 0xff800000L +#define VGT_DEBUG_REG10__es_rb_space_avail_r2_q_8_0__SHIFT 0x00000017 +#define VGT_DEBUG_REG10__gs_rb_space_avail_r3_q_9_0_MASK 0x007fe000L +#define VGT_DEBUG_REG10__gs_rb_space_avail_r3_q_9_0__SHIFT 0x0000000d +#define VGT_DEBUG_REG10__index_buffer_depth_r1_q_MASK 0x0000001fL +#define VGT_DEBUG_REG10__index_buffer_depth_r1_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG10__onchip_gs_en_r0_q_MASK 0x00000180L +#define VGT_DEBUG_REG10__onchip_gs_en_r0_q__SHIFT 0x00000007 +#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_q_MASK 0x00001000L +#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_qq_MASK 0x00000800L +#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_qq__SHIFT 0x0000000b +#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG10__SPARE2_MASK 0x00000600L +#define VGT_DEBUG_REG10__SPARE2__SHIFT 0x00000009 +#define VGT_DEBUG_REG11__counters_available_r0_MASK 0x00001000L +#define VGT_DEBUG_REG11__counters_available_r0__SHIFT 0x0000000c +#define VGT_DEBUG_REG11__counters_avail_r0_MASK 0x00000800L +#define VGT_DEBUG_REG11__counters_avail_r0__SHIFT 0x0000000b +#define VGT_DEBUG_REG11__counters_busy_r0_MASK 0x00000400L +#define VGT_DEBUG_REG11__counters_busy_r0__SHIFT 0x0000000a +#define VGT_DEBUG_REG11__es_r0_rtr_MASK 0x00100000L +#define VGT_DEBUG_REG11__es_r0_rtr__SHIFT 0x00000014 +#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_busy_MASK 0x00000008L +#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_busy__SHIFT 0x00000003 +#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_full_MASK 0x08000000L +#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_full__SHIFT 0x0000001b +#define VGT_DEBUG_REG11__es_rb_roll_over_r3_MASK 0x00000200L +#define VGT_DEBUG_REG11__es_rb_roll_over_r3__SHIFT 0x00000009 +#define VGT_DEBUG_REG11__es_tbl_empty_MASK 0x40000000L +#define VGT_DEBUG_REG11__es_tbl_empty__SHIFT 0x0000001e +#define VGT_DEBUG_REG11__gog_tm_vs_event_rtr_MASK 0x00200000L +#define VGT_DEBUG_REG11__gog_tm_vs_event_rtr__SHIFT 0x00000015 +#define VGT_DEBUG_REG11__gs_issue_rtr_MASK 0x00010000L +#define VGT_DEBUG_REG11__gs_issue_rtr__SHIFT 0x00000010 +#define VGT_DEBUG_REG11__gs_r0_rtr_MASK 0x00080000L +#define VGT_DEBUG_REG11__gs_r0_rtr__SHIFT 0x00000013 +#define VGT_DEBUG_REG11__hold_eswave_MASK 0x00000100L +#define VGT_DEBUG_REG11__hold_eswave__SHIFT 0x00000008 +#define VGT_DEBUG_REG11__no_active_states_r0_MASK 0x80000000L +#define VGT_DEBUG_REG11__no_active_states_r0__SHIFT 0x0000001f +#define VGT_DEBUG_REG11__send_event_q_MASK 0x20000000L +#define VGT_DEBUG_REG11__send_event_q__SHIFT 0x0000001d +#define VGT_DEBUG_REG11__SPARE0_MASK 0x00040000L +#define VGT_DEBUG_REG11__SPARE0__SHIFT 0x00000012 +#define VGT_DEBUG_REG11__SPARE1_MASK 0x00000020L +#define VGT_DEBUG_REG11__SPARE1__SHIFT 0x00000005 +#define VGT_DEBUG_REG11__spi_esthread_fifo_busy_MASK 0x00000080L +#define VGT_DEBUG_REG11__spi_esthread_fifo_busy__SHIFT 0x00000007 +#define VGT_DEBUG_REG11__spi_gsthread_fifo_busy_MASK 0x00000040L +#define VGT_DEBUG_REG11__spi_gsthread_fifo_busy__SHIFT 0x00000006 +#define VGT_DEBUG_REG11__tm_busy_q_MASK 0x00000001L +#define VGT_DEBUG_REG11__tm_busy_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG11__tm_noif_busy_q_MASK 0x00000002L +#define VGT_DEBUG_REG11__tm_noif_busy_q__SHIFT 0x00000001 +#define VGT_DEBUG_REG11__tm_out_busy_q_MASK 0x00000004L +#define VGT_DEBUG_REG11__tm_out_busy_q__SHIFT 0x00000002 +#define VGT_DEBUG_REG11__tm_pt_event_rtr_MASK 0x00020000L +#define VGT_DEBUG_REG11__tm_pt_event_rtr__SHIFT 0x00000011 +#define VGT_DEBUG_REG11__tm_rcm_es_tbl_rtr_MASK 0x01000000L +#define VGT_DEBUG_REG11__tm_rcm_es_tbl_rtr__SHIFT 0x00000018 +#define VGT_DEBUG_REG11__tm_rcm_gs_event_rtr_MASK 0x00400000L +#define VGT_DEBUG_REG11__tm_rcm_gs_event_rtr__SHIFT 0x00000016 +#define VGT_DEBUG_REG11__tm_rcm_gs_tbl_rtr_MASK 0x00800000L +#define VGT_DEBUG_REG11__tm_rcm_gs_tbl_rtr__SHIFT 0x00000017 +#define VGT_DEBUG_REG11__VGT_SPI_esthread_rtr_q_MASK 0x00008000L +#define VGT_DEBUG_REG11__VGT_SPI_esthread_rtr_q__SHIFT 0x0000000f +#define VGT_DEBUG_REG11__VGT_SPI_gsthread_rtr_q_MASK 0x00004000L +#define VGT_DEBUG_REG11__VGT_SPI_gsthread_rtr_q__SHIFT 0x0000000e +#define VGT_DEBUG_REG11__vs_dealloc_tbl_busy_MASK 0x00000010L +#define VGT_DEBUG_REG11__vs_dealloc_tbl_busy__SHIFT 0x00000004 +#define VGT_DEBUG_REG11__vs_dealloc_tbl_full_MASK 0x10000000L +#define VGT_DEBUG_REG11__vs_dealloc_tbl_full__SHIFT 0x0000001c +#define VGT_DEBUG_REG11__vs_event_fifo_empty_MASK 0x02000000L +#define VGT_DEBUG_REG11__vs_event_fifo_empty__SHIFT 0x00000019 +#define VGT_DEBUG_REG11__vs_event_fifo_full_MASK 0x04000000L +#define VGT_DEBUG_REG11__vs_event_fifo_full__SHIFT 0x0000001a +#define VGT_DEBUG_REG11__vs_event_fifo_rtr_MASK 0x00002000L +#define VGT_DEBUG_REG11__vs_event_fifo_rtr__SHIFT 0x0000000d +#define VGT_DEBUG_REG12__gs_state0_r0_q_MASK 0x00000007L +#define VGT_DEBUG_REG12__gs_state0_r0_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG12__gs_state1_r0_q_MASK 0x00000038L +#define VGT_DEBUG_REG12__gs_state1_r0_q__SHIFT 0x00000003 +#define VGT_DEBUG_REG12__gs_state2_r0_q_MASK 0x000001c0L +#define VGT_DEBUG_REG12__gs_state2_r0_q__SHIFT 0x00000006 +#define VGT_DEBUG_REG12__gs_state3_r0_q_MASK 0x00000e00L +#define VGT_DEBUG_REG12__gs_state3_r0_q__SHIFT 0x00000009 +#define VGT_DEBUG_REG12__gs_state4_r0_q_MASK 0x00007000L +#define VGT_DEBUG_REG12__gs_state4_r0_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG12__gs_state5_r0_q_MASK 0x00038000L +#define VGT_DEBUG_REG12__gs_state5_r0_q__SHIFT 0x0000000f +#define VGT_DEBUG_REG12__gs_state6_r0_q_MASK 0x001c0000L +#define VGT_DEBUG_REG12__gs_state6_r0_q__SHIFT 0x00000012 +#define VGT_DEBUG_REG12__gs_state7_r0_q_MASK 0x00e00000L +#define VGT_DEBUG_REG12__gs_state7_r0_q__SHIFT 0x00000015 +#define VGT_DEBUG_REG12__gs_state8_r0_q_MASK 0x07000000L +#define VGT_DEBUG_REG12__gs_state8_r0_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG12__gs_state9_r0_q_MASK 0x38000000L +#define VGT_DEBUG_REG12__gs_state9_r0_q__SHIFT 0x0000001b +#define VGT_DEBUG_REG12__hold_eswave_eop_MASK 0x40000000L +#define VGT_DEBUG_REG12__hold_eswave_eop__SHIFT 0x0000001e +#define VGT_DEBUG_REG12__SPARE0_MASK 0x80000000L +#define VGT_DEBUG_REG12__SPARE0__SHIFT 0x0000001f +#define VGT_DEBUG_REG13__active_cm_sm_r0_q_MASK 0xf8000000L +#define VGT_DEBUG_REG13__active_cm_sm_r0_q__SHIFT 0x0000001b +#define VGT_DEBUG_REG13__es_tbl_full_MASK 0x01000000L +#define VGT_DEBUG_REG13__es_tbl_full__SHIFT 0x00000018 +#define VGT_DEBUG_REG13__gsfetch_done_cnt_q_not_0_MASK 0x00800000L +#define VGT_DEBUG_REG13__gsfetch_done_cnt_q_not_0__SHIFT 0x00000017 +#define VGT_DEBUG_REG13__gsfetch_done_fifo_cnt_q_not_0_MASK 0x00400000L +#define VGT_DEBUG_REG13__gsfetch_done_fifo_cnt_q_not_0__SHIFT 0x00000016 +#define VGT_DEBUG_REG13__gs_state10_r0_q_MASK 0x00000007L +#define VGT_DEBUG_REG13__gs_state10_r0_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG13__gs_state11_r0_q_MASK 0x00000038L +#define VGT_DEBUG_REG13__gs_state11_r0_q__SHIFT 0x00000003 +#define VGT_DEBUG_REG13__gs_state12_r0_q_MASK 0x000001c0L +#define VGT_DEBUG_REG13__gs_state12_r0_q__SHIFT 0x00000006 +#define VGT_DEBUG_REG13__gs_state13_r0_q_MASK 0x00000e00L +#define VGT_DEBUG_REG13__gs_state13_r0_q__SHIFT 0x00000009 +#define VGT_DEBUG_REG13__gs_state14_r0_q_MASK 0x00007000L +#define VGT_DEBUG_REG13__gs_state14_r0_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG13__gs_state15_r0_q_MASK 0x00038000L +#define VGT_DEBUG_REG13__gs_state15_r0_q__SHIFT 0x0000000f +#define VGT_DEBUG_REG13__gs_tbl_wrptr_r0_q_3_0_MASK 0x003c0000L +#define VGT_DEBUG_REG13__gs_tbl_wrptr_r0_q_3_0__SHIFT 0x00000012 +#define VGT_DEBUG_REG13__SPARE0_MASK 0x04000000L +#define VGT_DEBUG_REG13__SPARE0__SHIFT 0x0000001a +#define VGT_DEBUG_REG13__SPARE1_MASK 0x02000000L +#define VGT_DEBUG_REG13__SPARE1__SHIFT 0x00000019 +#define VGT_DEBUG_REG14__es_flush_cnt_busy_q_MASK 0x00000400L +#define VGT_DEBUG_REG14__es_flush_cnt_busy_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG14__gsfetch_done_fifo_full_MASK 0x00000010L +#define VGT_DEBUG_REG14__gsfetch_done_fifo_full__SHIFT 0x00000004 +#define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0_MASK 0x20000000L +#define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0__SHIFT 0x0000001d +#define VGT_DEBUG_REG14__gs_rb_space_avail_r0_MASK 0x00000020L +#define VGT_DEBUG_REG14__gs_rb_space_avail_r0__SHIFT 0x00000005 +#define VGT_DEBUG_REG14__gs_tbl_full_r0_MASK 0x00000800L +#define VGT_DEBUG_REG14__gs_tbl_full_r0__SHIFT 0x0000000b +#define VGT_DEBUG_REG14__se1spi_esthread_fifo_busy_MASK 0x08000000L +#define VGT_DEBUG_REG14__se1spi_esthread_fifo_busy__SHIFT 0x0000001b +#define VGT_DEBUG_REG14__se1spi_gsthread_fifo_busy_MASK 0x00200000L +#define VGT_DEBUG_REG14__se1spi_gsthread_fifo_busy__SHIFT 0x00000015 +#define VGT_DEBUG_REG14__smx1_es_done_cnt_r0_q_not_0_MASK 0x04000000L +#define VGT_DEBUG_REG14__smx1_es_done_cnt_r0_q_not_0__SHIFT 0x0000001a +#define VGT_DEBUG_REG14__smx_es_done_cnt_r0_q_not_0_MASK 0x00000040L +#define VGT_DEBUG_REG14__smx_es_done_cnt_r0_q_not_0__SHIFT 0x00000006 +#define VGT_DEBUG_REG14__SPARE0_MASK 0x40000000L +#define VGT_DEBUG_REG14__SPARE0__SHIFT 0x0000001e +#define VGT_DEBUG_REG14__SPARE1_MASK 0x10000000L +#define VGT_DEBUG_REG14__SPARE1__SHIFT 0x0000001c +#define VGT_DEBUG_REG14__SPARE2_MASK 0x001ff000L +#define VGT_DEBUG_REG14__SPARE2__SHIFT 0x0000000c +#define VGT_DEBUG_REG14__SPARE3_MASK 0x0000000fL +#define VGT_DEBUG_REG14__SPARE3__SHIFT 0x00000000 +#define VGT_DEBUG_REG14__SPARE8_MASK 0x00000180L +#define VGT_DEBUG_REG14__SPARE8__SHIFT 0x00000007 +#define VGT_DEBUG_REG14__SPARE_MASK 0x01c00000L +#define VGT_DEBUG_REG14__SPARE__SHIFT 0x00000016 +#define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q_MASK 0x80000000L +#define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q__SHIFT 0x0000001f +#define VGT_DEBUG_REG14__VGT_SE1SPI_gsthread_rtr_q_MASK 0x02000000L +#define VGT_DEBUG_REG14__VGT_SE1SPI_gsthread_rtr_q__SHIFT 0x00000019 +#define VGT_DEBUG_REG14__vs_done_cnt_q_not_0_MASK 0x00000200L +#define VGT_DEBUG_REG14__vs_done_cnt_q_not_0__SHIFT 0x00000009 +#define VGT_DEBUG_REG15__active_sm_q_MASK 0x000003e0L +#define VGT_DEBUG_REG15__active_sm_q__SHIFT 0x00000005 +#define VGT_DEBUG_REG15__cm_busy_q_MASK 0x00000001L +#define VGT_DEBUG_REG15__cm_busy_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG15__cntr_tbl_wrptr_q_MASK 0x000f8000L +#define VGT_DEBUG_REG15__cntr_tbl_wrptr_q__SHIFT 0x0000000f +#define VGT_DEBUG_REG15__counters_busy_q_MASK 0x00000002L +#define VGT_DEBUG_REG15__counters_busy_q__SHIFT 0x00000001 +#define VGT_DEBUG_REG15__counters_full_MASK 0x00000010L +#define VGT_DEBUG_REG15__counters_full__SHIFT 0x00000004 +#define VGT_DEBUG_REG15__entry_rdptr_q_MASK 0x00007c00L +#define VGT_DEBUG_REG15__entry_rdptr_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG15__gs_done_array_q_not_0_MASK 0x10000000L +#define VGT_DEBUG_REG15__gs_done_array_q_not_0__SHIFT 0x0000001c +#define VGT_DEBUG_REG15__output_fifo_empty_MASK 0x00000004L +#define VGT_DEBUG_REG15__output_fifo_empty__SHIFT 0x00000002 +#define VGT_DEBUG_REG15__output_fifo_full_MASK 0x00000008L +#define VGT_DEBUG_REG15__output_fifo_full__SHIFT 0x00000003 +#define VGT_DEBUG_REG15__SPARE25_MASK 0x03f00000L +#define VGT_DEBUG_REG15__SPARE25__SHIFT 0x00000014 +#define VGT_DEBUG_REG15__SPARE31_MASK 0xe0000000L +#define VGT_DEBUG_REG15__SPARE31__SHIFT 0x0000001d +#define VGT_DEBUG_REG15__st_cut_mode_q_MASK 0x0c000000L +#define VGT_DEBUG_REG15__st_cut_mode_q__SHIFT 0x0000001a +#define VGT_DEBUG_REG16__gog_busy_MASK 0x00000001L +#define VGT_DEBUG_REG16__gog_busy__SHIFT 0x00000000 +#define VGT_DEBUG_REG16__gog_out_prim_state_sel_MASK 0x0e000000L +#define VGT_DEBUG_REG16__gog_out_prim_state_sel__SHIFT 0x00000019 +#define VGT_DEBUG_REG16__gog_state_q_MASK 0x0000000eL +#define VGT_DEBUG_REG16__gog_state_q__SHIFT 0x00000001 +#define VGT_DEBUG_REG16__gog_tm_vs_event_rtr_MASK 0x00000800L +#define VGT_DEBUG_REG16__gog_tm_vs_event_rtr__SHIFT 0x0000000b +#define VGT_DEBUG_REG16__indx_valid_r0_q_MASK 0x00080000L +#define VGT_DEBUG_REG16__indx_valid_r0_q__SHIFT 0x00000013 +#define VGT_DEBUG_REG16__indx_valid_r1_q_MASK 0x00020000L +#define VGT_DEBUG_REG16__indx_valid_r1_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG16__indx_valid_r2_q_MASK 0x00002000L +#define VGT_DEBUG_REG16__indx_valid_r2_q__SHIFT 0x0000000d +#define VGT_DEBUG_REG16__multiple_streams_en_r1_q_MASK 0x10000000L +#define VGT_DEBUG_REG16__multiple_streams_en_r1_q__SHIFT 0x0000001c +#define VGT_DEBUG_REG16__new_vs_thread_r2_MASK 0x80000000L +#define VGT_DEBUG_REG16__new_vs_thread_r2__SHIFT 0x0000001f +#define VGT_DEBUG_REG16__num_gs_r2_q_not_0_MASK 0x40000000L +#define VGT_DEBUG_REG16__num_gs_r2_q_not_0__SHIFT 0x0000001e +#define VGT_DEBUG_REG16__prim_valid_r0_q_MASK 0x00100000L +#define VGT_DEBUG_REG16__prim_valid_r0_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG16__prim_valid_r1_q_MASK 0x00010000L +#define VGT_DEBUG_REG16__prim_valid_r1_q__SHIFT 0x00000010 +#define VGT_DEBUG_REG16__prim_valid_r2_q_MASK 0x00004000L +#define VGT_DEBUG_REG16__prim_valid_r2_q__SHIFT 0x0000000e +#define VGT_DEBUG_REG16__r0_rtr_MASK 0x00000010L +#define VGT_DEBUG_REG16__r0_rtr__SHIFT 0x00000004 +#define VGT_DEBUG_REG16__r1_rtr_MASK 0x00000020L +#define VGT_DEBUG_REG16__r1_rtr__SHIFT 0x00000005 +#define VGT_DEBUG_REG16__r1_upstream_rtr_MASK 0x00000040L +#define VGT_DEBUG_REG16__r1_upstream_rtr__SHIFT 0x00000006 +#define VGT_DEBUG_REG16__r2_indx_rtr_MASK 0x00000200L +#define VGT_DEBUG_REG16__r2_indx_rtr__SHIFT 0x00000009 +#define VGT_DEBUG_REG16__r2_prim_rtr_MASK 0x00000100L +#define VGT_DEBUG_REG16__r2_prim_rtr__SHIFT 0x00000008 +#define VGT_DEBUG_REG16__r2_rtr_MASK 0x00000400L +#define VGT_DEBUG_REG16__r2_rtr__SHIFT 0x0000000a +#define VGT_DEBUG_REG16__r2_vs_tbl_rtr_MASK 0x00000080L +#define VGT_DEBUG_REG16__r2_vs_tbl_rtr__SHIFT 0x00000007 +#define VGT_DEBUG_REG16__r3_force_vs_tbl_we_rtr_MASK 0x00001000L +#define VGT_DEBUG_REG16__r3_force_vs_tbl_we_rtr__SHIFT 0x0000000c +#define VGT_DEBUG_REG16__send_event_q_MASK 0x00400000L +#define VGT_DEBUG_REG16__send_event_q__SHIFT 0x00000016 +#define VGT_DEBUG_REG16__SPARE24_MASK 0x01800000L +#define VGT_DEBUG_REG16__SPARE24__SHIFT 0x00000017 +#define VGT_DEBUG_REG16__valid_r0_q_MASK 0x00200000L +#define VGT_DEBUG_REG16__valid_r0_q__SHIFT 0x00000015 +#define VGT_DEBUG_REG16__valid_r1_q_MASK 0x00040000L +#define VGT_DEBUG_REG16__valid_r1_q__SHIFT 0x00000012 +#define VGT_DEBUG_REG16__valid_r2_q_MASK 0x00008000L +#define VGT_DEBUG_REG16__valid_r2_q__SHIFT 0x0000000f +#define VGT_DEBUG_REG16__vert_seen_since_sopg_r2_q_MASK 0x01000000L +#define VGT_DEBUG_REG16__vert_seen_since_sopg_r2_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0_MASK 0x20000000L +#define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0__SHIFT 0x0000001d +#define VGT_DEBUG_REG17__gog_out_indx_13_0_MASK 0xfffc0000L +#define VGT_DEBUG_REG17__gog_out_indx_13_0__SHIFT 0x00000012 +#define VGT_DEBUG_REG17__gog_out_prim_rel_indx0_5_0_MASK 0x0003f000L +#define VGT_DEBUG_REG17__gog_out_prim_rel_indx0_5_0__SHIFT 0x0000000c +#define VGT_DEBUG_REG17__gog_out_prim_rel_indx1_5_0_MASK 0x00000fc0L +#define VGT_DEBUG_REG17__gog_out_prim_rel_indx1_5_0__SHIFT 0x00000006 +#define VGT_DEBUG_REG17__gog_out_prim_rel_indx2_5_0_MASK 0x0000003fL +#define VGT_DEBUG_REG17__gog_out_prim_rel_indx2_5_0__SHIFT 0x00000000 +#define VGT_DEBUG_REG18__components_valid_r0_q_MASK 0xe0000000L +#define VGT_DEBUG_REG18__components_valid_r0_q__SHIFT 0x0000001d +#define VGT_DEBUG_REG18__eject_vtx_vect_r1_d_MASK 0x00800000L +#define VGT_DEBUG_REG18__eject_vtx_vect_r1_d__SHIFT 0x00000017 +#define VGT_DEBUG_REG18__eop_r0_q_MASK 0x00400000L +#define VGT_DEBUG_REG18__eop_r0_q__SHIFT 0x00000016 +#define VGT_DEBUG_REG18__grp_vr_valid_MASK 0x00000001L +#define VGT_DEBUG_REG18__grp_vr_valid__SHIFT 0x00000000 +#define VGT_DEBUG_REG18__gs_scenario_a_r0_q_MASK 0x08000000L +#define VGT_DEBUG_REG18__gs_scenario_a_r0_q__SHIFT 0x0000001b +#define VGT_DEBUG_REG18__gs_scenario_b_r0_q_MASK 0x10000000L +#define VGT_DEBUG_REG18__gs_scenario_b_r0_q__SHIFT 0x0000001c +#define VGT_DEBUG_REG18__indices_to_send_q_MASK 0x00000700L +#define VGT_DEBUG_REG18__indices_to_send_q__SHIFT 0x00000008 +#define VGT_DEBUG_REG18__indx0_hit_d_MASK 0x00040000L +#define VGT_DEBUG_REG18__indx0_hit_d__SHIFT 0x00000012 +#define VGT_DEBUG_REG18__indx0_new_d_MASK 0x00002000L +#define VGT_DEBUG_REG18__indx0_new_d__SHIFT 0x0000000d +#define VGT_DEBUG_REG18__indx1_hit_d_MASK 0x00020000L +#define VGT_DEBUG_REG18__indx1_hit_d__SHIFT 0x00000011 +#define VGT_DEBUG_REG18__indx1_new_d_MASK 0x00004000L +#define VGT_DEBUG_REG18__indx1_new_d__SHIFT 0x0000000e +#define VGT_DEBUG_REG18__indx2_hit_d_MASK 0x00010000L +#define VGT_DEBUG_REG18__indx2_hit_d__SHIFT 0x00000010 +#define VGT_DEBUG_REG18__indx2_new_d_MASK 0x00008000L +#define VGT_DEBUG_REG18__indx2_new_d__SHIFT 0x0000000f +#define VGT_DEBUG_REG18__last_group_of_instance_r0_q_MASK 0x00100000L +#define VGT_DEBUG_REG18__last_group_of_instance_r0_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG18__last_indx_of_prim_MASK 0x00001000L +#define VGT_DEBUG_REG18__last_indx_of_prim__SHIFT 0x0000000c +#define VGT_DEBUG_REG18__null_primitive_r0_q_MASK 0x00200000L +#define VGT_DEBUG_REG18__null_primitive_r0_q__SHIFT 0x00000015 +#define VGT_DEBUG_REG18__out_vr_indx_read_MASK 0x00000040L +#define VGT_DEBUG_REG18__out_vr_indx_read__SHIFT 0x00000006 +#define VGT_DEBUG_REG18__out_vr_prim_read_MASK 0x00000080L +#define VGT_DEBUG_REG18__out_vr_prim_read__SHIFT 0x00000007 +#define VGT_DEBUG_REG18__pipe0_dr_MASK 0x00000002L +#define VGT_DEBUG_REG18__pipe0_dr__SHIFT 0x00000001 +#define VGT_DEBUG_REG18__pipe0_rtr_MASK 0x00000010L +#define VGT_DEBUG_REG18__pipe0_rtr__SHIFT 0x00000004 +#define VGT_DEBUG_REG18__pipe1_dr_MASK 0x00000004L +#define VGT_DEBUG_REG18__pipe1_dr__SHIFT 0x00000002 +#define VGT_DEBUG_REG18__pipe1_rtr_MASK 0x00000020L +#define VGT_DEBUG_REG18__pipe1_rtr__SHIFT 0x00000005 +#define VGT_DEBUG_REG18__st_vertex_reuse_off_r0_q_MASK 0x00080000L +#define VGT_DEBUG_REG18__st_vertex_reuse_off_r0_q__SHIFT 0x00000013 +#define VGT_DEBUG_REG18__sub_prim_type_r0_q_MASK 0x07000000L +#define VGT_DEBUG_REG18__sub_prim_type_r0_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG18__valid_indices_MASK 0x00000800L +#define VGT_DEBUG_REG18__valid_indices__SHIFT 0x0000000b +#define VGT_DEBUG_REG18__vr_grp_read_MASK 0x00000008L +#define VGT_DEBUG_REG18__vr_grp_read__SHIFT 0x00000003 +#define VGT_DEBUG_REG19__buffered_prim_eject_vtx_vect_MASK 0x00080000L +#define VGT_DEBUG_REG19__buffered_prim_eject_vtx_vect__SHIFT 0x00000013 +#define VGT_DEBUG_REG19__buffered_prim_eop_MASK 0x00040000L +#define VGT_DEBUG_REG19__buffered_prim_eop__SHIFT 0x00000012 +#define VGT_DEBUG_REG19__buffered_prim_event_MASK 0x00010000L +#define VGT_DEBUG_REG19__buffered_prim_event__SHIFT 0x00000010 +#define VGT_DEBUG_REG19__buffered_prim_null_primitive_MASK 0x00020000L +#define VGT_DEBUG_REG19__buffered_prim_null_primitive__SHIFT 0x00000011 +#define VGT_DEBUG_REG19__buffered_prim_type_event_MASK 0x03f00000L +#define VGT_DEBUG_REG19__buffered_prim_type_event__SHIFT 0x00000014 +#define VGT_DEBUG_REG19__filter_event_MASK 0x80000000L +#define VGT_DEBUG_REG19__filter_event__SHIFT 0x0000001f +#define VGT_DEBUG_REG19__hold_prim_MASK 0x00000800L +#define VGT_DEBUG_REG19__hold_prim__SHIFT 0x0000000b +#define VGT_DEBUG_REG19__new_packet_q_MASK 0x00008000L +#define VGT_DEBUG_REG19__new_packet_q__SHIFT 0x0000000f +#define VGT_DEBUG_REG19__null_terminate_vtx_vector_MASK 0x40000000L +#define VGT_DEBUG_REG19__null_terminate_vtx_vector__SHIFT 0x0000001e +#define VGT_DEBUG_REG19__num_new_unique_rel_indx_MASK 0x30000000L +#define VGT_DEBUG_REG19__num_new_unique_rel_indx__SHIFT 0x0000001c +#define VGT_DEBUG_REG19__pa_clipp_fifo_busy_q_MASK 0x00000020L +#define VGT_DEBUG_REG19__pa_clipp_fifo_busy_q__SHIFT 0x00000005 +#define VGT_DEBUG_REG19__pa_clips_fifo_busy_q_MASK 0x00000010L +#define VGT_DEBUG_REG19__pa_clips_fifo_busy_q__SHIFT 0x00000004 +#define VGT_DEBUG_REG19__pa_clipv_fifo_busy_q_MASK 0x00000400L +#define VGT_DEBUG_REG19__pa_clipv_fifo_busy_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG19__prim_buffer_empty_MASK 0x00000004L +#define VGT_DEBUG_REG19__prim_buffer_empty__SHIFT 0x00000002 +#define VGT_DEBUG_REG19__prim_buffer_full_MASK 0x00000008L +#define VGT_DEBUG_REG19__prim_buffer_full__SHIFT 0x00000003 +#define VGT_DEBUG_REG19__separate_out_busy_q_MASK 0x00000001L +#define VGT_DEBUG_REG19__separate_out_busy_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG19__separate_out_indx_busy_q_MASK 0x00000002L +#define VGT_DEBUG_REG19__separate_out_indx_busy_q__SHIFT 0x00000001 +#define VGT_DEBUG_REG19__spi_vsthread_fifo_busy_q_MASK 0x00000100L +#define VGT_DEBUG_REG19__spi_vsthread_fifo_busy_q__SHIFT 0x00000008 +#define VGT_DEBUG_REG19__spi_vsvert_fifo_busy_q_MASK 0x00000200L +#define VGT_DEBUG_REG19__spi_vsvert_fifo_busy_q__SHIFT 0x00000009 +#define VGT_DEBUG_REG19__VGT_PA_clipp_rtr_q_MASK 0x00000080L +#define VGT_DEBUG_REG19__VGT_PA_clipp_rtr_q__SHIFT 0x00000007 +#define VGT_DEBUG_REG19__VGT_PA_clips_rtr_q_MASK 0x00000040L +#define VGT_DEBUG_REG19__VGT_PA_clips_rtr_q__SHIFT 0x00000006 +#define VGT_DEBUG_REG19__VGT_PA_clipv_rtr_q_MASK 0x00004000L +#define VGT_DEBUG_REG19__VGT_PA_clipv_rtr_q__SHIFT 0x0000000e +#define VGT_DEBUG_REG19__VGT_SE1SPI_vsvert_rtr_q_MASK 0x08000000L +#define VGT_DEBUG_REG19__VGT_SE1SPI_vsvert_rtr_q__SHIFT 0x0000001b +#define VGT_DEBUG_REG19__VGT_SE1SPI_vswave_rtr_q_MASK 0x04000000L +#define VGT_DEBUG_REG19__VGT_SE1SPI_vswave_rtr_q__SHIFT 0x0000001a +#define VGT_DEBUG_REG19__VGT_SPI_vsthread_rtr_q_MASK 0x00001000L +#define VGT_DEBUG_REG19__VGT_SPI_vsthread_rtr_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG19__VGT_SPI_vsvert_rtr_q_MASK 0x00002000L +#define VGT_DEBUG_REG19__VGT_SPI_vsvert_rtr_q__SHIFT 0x0000000d +#define VGT_DEBUG_REG1__gog_out_indx_valid_MASK 0x10000000L +#define VGT_DEBUG_REG1__gog_out_indx_valid__SHIFT 0x0000001c +#define VGT_DEBUG_REG1__gog_out_prim_valid_MASK 0x40000000L +#define VGT_DEBUG_REG1__gog_out_prim_valid__SHIFT 0x0000001e +#define VGT_DEBUG_REG1__gs_pi_read_MASK 0x08000000L +#define VGT_DEBUG_REG1__gs_pi_read__SHIFT 0x0000001b +#define VGT_DEBUG_REG1__out_indx_read_MASK 0x20000000L +#define VGT_DEBUG_REG1__out_indx_read__SHIFT 0x0000001d +#define VGT_DEBUG_REG1__out_prim_read_MASK 0x80000000L +#define VGT_DEBUG_REG1__out_prim_read__SHIFT 0x0000001f +#define VGT_DEBUG_REG1__pi_gs_valid_MASK 0x04000000L +#define VGT_DEBUG_REG1__pi_gs_valid__SHIFT 0x0000001a +#define VGT_DEBUG_REG1__pi_pt_valid_MASK 0x00001000L +#define VGT_DEBUG_REG1__pi_pt_valid__SHIFT 0x0000000c +#define VGT_DEBUG_REG1__pi_te_valid_MASK 0x00004000L +#define VGT_DEBUG_REG1__pi_te_valid__SHIFT 0x0000000e +#define VGT_DEBUG_REG1__pi_vr_valid_MASK 0x00000400L +#define VGT_DEBUG_REG1__pi_vr_valid__SHIFT 0x0000000a +#define VGT_DEBUG_REG1__pt_out_indx_valid_MASK 0x00100000L +#define VGT_DEBUG_REG1__pt_out_indx_valid__SHIFT 0x00000014 +#define VGT_DEBUG_REG1__pt_out_prim_valid_MASK 0x00400000L +#define VGT_DEBUG_REG1__pt_out_prim_valid__SHIFT 0x00000016 +#define VGT_DEBUG_REG1__pt_pi_read_MASK 0x00002000L +#define VGT_DEBUG_REG1__pt_pi_read__SHIFT 0x0000000d +#define VGT_DEBUG_REG1__SPARE0_MASK 0x00000200L +#define VGT_DEBUG_REG1__SPARE0__SHIFT 0x00000009 +#define VGT_DEBUG_REG1__SPARE10_MASK 0x00200000L +#define VGT_DEBUG_REG1__SPARE10__SHIFT 0x00000015 +#define VGT_DEBUG_REG1__SPARE11_MASK 0x00080000L +#define VGT_DEBUG_REG1__SPARE11__SHIFT 0x00000013 +#define VGT_DEBUG_REG1__SPARE12_MASK 0x00020000L +#define VGT_DEBUG_REG1__SPARE12__SHIFT 0x00000011 +#define VGT_DEBUG_REG1__SPARE1_MASK 0x00000100L +#define VGT_DEBUG_REG1__SPARE1__SHIFT 0x00000008 +#define VGT_DEBUG_REG1__SPARE23_MASK 0x00800000L +#define VGT_DEBUG_REG1__SPARE23__SHIFT 0x00000017 +#define VGT_DEBUG_REG1__SPARE25_MASK 0x02000000L +#define VGT_DEBUG_REG1__SPARE25__SHIFT 0x00000019 +#define VGT_DEBUG_REG1__SPARE2_MASK 0x00000080L +#define VGT_DEBUG_REG1__SPARE2__SHIFT 0x00000007 +#define VGT_DEBUG_REG1__SPARE3_MASK 0x00000040L +#define VGT_DEBUG_REG1__SPARE3__SHIFT 0x00000006 +#define VGT_DEBUG_REG1__SPARE4_MASK 0x00000020L +#define VGT_DEBUG_REG1__SPARE4__SHIFT 0x00000005 +#define VGT_DEBUG_REG1__SPARE5_MASK 0x00000010L +#define VGT_DEBUG_REG1__SPARE5__SHIFT 0x00000004 +#define VGT_DEBUG_REG1__SPARE6_MASK 0x00000008L +#define VGT_DEBUG_REG1__SPARE6__SHIFT 0x00000003 +#define VGT_DEBUG_REG1__SPARE7_MASK 0x00000004L +#define VGT_DEBUG_REG1__SPARE7__SHIFT 0x00000002 +#define VGT_DEBUG_REG1__SPARE8_MASK 0x00000002L +#define VGT_DEBUG_REG1__SPARE8__SHIFT 0x00000001 +#define VGT_DEBUG_REG1__SPARE9_MASK 0x00000001L +#define VGT_DEBUG_REG1__SPARE9__SHIFT 0x00000000 +#define VGT_DEBUG_REG1__te_grp_read_MASK 0x00008000L +#define VGT_DEBUG_REG1__te_grp_read__SHIFT 0x0000000f +#define VGT_DEBUG_REG1__te_out_data_valid_MASK 0x01000000L +#define VGT_DEBUG_REG1__te_out_data_valid__SHIFT 0x00000018 +#define VGT_DEBUG_REG1__vr_out_indx_valid_MASK 0x00010000L +#define VGT_DEBUG_REG1__vr_out_indx_valid__SHIFT 0x00000010 +#define VGT_DEBUG_REG1__vr_out_prim_valid_MASK 0x00040000L +#define VGT_DEBUG_REG1__vr_out_prim_valid__SHIFT 0x00000012 +#define VGT_DEBUG_REG1__vr_pi_read_MASK 0x00000800L +#define VGT_DEBUG_REG1__vr_pi_read__SHIFT 0x0000000b +#define VGT_DEBUG_REG20__alloc_counter_q_MASK 0x003c0000L +#define VGT_DEBUG_REG20__alloc_counter_q__SHIFT 0x00000012 +#define VGT_DEBUG_REG20__curr_dealloc_distance_q_MASK 0x1fc00000L +#define VGT_DEBUG_REG20__curr_dealloc_distance_q__SHIFT 0x00000016 +#define VGT_DEBUG_REG20__curr_slot_in_vtx_vect_q_not_0_MASK 0x40000000L +#define VGT_DEBUG_REG20__curr_slot_in_vtx_vect_q_not_0__SHIFT 0x0000001e +#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexcount_not_0_MASK 0x00010000L +#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexcount_not_0__SHIFT 0x00000010 +#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexindex_MASK 0x0000ffffL +#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexindex__SHIFT 0x00000000 +#define VGT_DEBUG_REG20__int_vtx_counter_q_not_0_MASK 0x80000000L +#define VGT_DEBUG_REG20__int_vtx_counter_q_not_0__SHIFT 0x0000001f +#define VGT_DEBUG_REG20__new_allocate_q_MASK 0x20000000L +#define VGT_DEBUG_REG20__new_allocate_q__SHIFT 0x0000001d +#define VGT_DEBUG_REG20__SPARE17_MASK 0x00020000L +#define VGT_DEBUG_REG20__SPARE17__SHIFT 0x00000011 +#define VGT_DEBUG_REG21__buff_full_p1_MASK 0x01000000L +#define VGT_DEBUG_REG21__buff_full_p1__SHIFT 0x00000018 +#define VGT_DEBUG_REG21__eopg_p0_q_MASK 0x40000000L +#define VGT_DEBUG_REG21__eopg_p0_q__SHIFT 0x0000001e +#define VGT_DEBUG_REG21__eotg_r2_q_MASK 0x04000000L +#define VGT_DEBUG_REG21__eotg_r2_q__SHIFT 0x0000001a +#define VGT_DEBUG_REG21__full_state_p1_q_MASK 0x00008000L +#define VGT_DEBUG_REG21__full_state_p1_q__SHIFT 0x0000000f +#define VGT_DEBUG_REG21__indx_count_q_not_0_MASK 0x00002000L +#define VGT_DEBUG_REG21__indx_count_q_not_0__SHIFT 0x0000000d +#define VGT_DEBUG_REG21__indx_side_fifo_empty_MASK 0x00000002L +#define VGT_DEBUG_REG21__indx_side_fifo_empty__SHIFT 0x00000001 +#define VGT_DEBUG_REG21__indx_side_fifo_full_MASK 0x00000080L +#define VGT_DEBUG_REG21__indx_side_fifo_full__SHIFT 0x00000007 +#define VGT_DEBUG_REG21__indx_side_indx_valid_MASK 0x00010000L +#define VGT_DEBUG_REG21__indx_side_indx_valid__SHIFT 0x00000010 +#define VGT_DEBUG_REG21__interfaces_rtr_MASK 0x00001000L +#define VGT_DEBUG_REG21__interfaces_rtr__SHIFT 0x0000000c +#define VGT_DEBUG_REG21__is_event_p0_q_MASK 0x00100000L +#define VGT_DEBUG_REG21__is_event_p0_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG21__lshs_dealloc_p1_MASK 0x00200000L +#define VGT_DEBUG_REG21__lshs_dealloc_p1__SHIFT 0x00000015 +#define VGT_DEBUG_REG21__null_r2_q_MASK 0x08000000L +#define VGT_DEBUG_REG21__null_r2_q__SHIFT 0x0000001b +#define VGT_DEBUG_REG21__out_indx_fifo_empty_MASK 0x00000001L +#define VGT_DEBUG_REG21__out_indx_fifo_empty__SHIFT 0x00000000 +#define VGT_DEBUG_REG21__out_indx_fifo_full_MASK 0x00000040L +#define VGT_DEBUG_REG21__out_indx_fifo_full__SHIFT 0x00000006 +#define VGT_DEBUG_REG21__p0_dr_MASK 0x10000000L +#define VGT_DEBUG_REG21__p0_dr__SHIFT 0x0000001c +#define VGT_DEBUG_REG21__p0_nobp_MASK 0x80000000L +#define VGT_DEBUG_REG21__p0_nobp__SHIFT 0x0000001f +#define VGT_DEBUG_REG21__p0_rtr_MASK 0x20000000L +#define VGT_DEBUG_REG21__p0_rtr__SHIFT 0x0000001d +#define VGT_DEBUG_REG21__pipe0_dr_MASK 0x00000004L +#define VGT_DEBUG_REG21__pipe0_dr__SHIFT 0x00000002 +#define VGT_DEBUG_REG21__pipe0_rtr_MASK 0x00000100L +#define VGT_DEBUG_REG21__pipe0_rtr__SHIFT 0x00000008 +#define VGT_DEBUG_REG21__pipe1_dr_MASK 0x00000008L +#define VGT_DEBUG_REG21__pipe1_dr__SHIFT 0x00000003 +#define VGT_DEBUG_REG21__pipe1_rtr_MASK 0x00000200L +#define VGT_DEBUG_REG21__pipe1_rtr__SHIFT 0x00000009 +#define VGT_DEBUG_REG21__pipe2_dr_MASK 0x00000010L +#define VGT_DEBUG_REG21__pipe2_dr__SHIFT 0x00000004 +#define VGT_DEBUG_REG21__pipe2_rtr_MASK 0x00000400L +#define VGT_DEBUG_REG21__pipe2_rtr__SHIFT 0x0000000a +#define VGT_DEBUG_REG21__stateid_p0_q_MASK 0x000e0000L +#define VGT_DEBUG_REG21__stateid_p0_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG21__stream_id_r2_q_MASK 0x00400000L +#define VGT_DEBUG_REG21__stream_id_r2_q__SHIFT 0x00000016 +#define VGT_DEBUG_REG21__strmout_valid_p1_MASK 0x02000000L +#define VGT_DEBUG_REG21__strmout_valid_p1__SHIFT 0x00000019 +#define VGT_DEBUG_REG21__vsthread_buff_empty_MASK 0x00000020L +#define VGT_DEBUG_REG21__vsthread_buff_empty__SHIFT 0x00000005 +#define VGT_DEBUG_REG21__vsthread_buff_full_MASK 0x00000800L +#define VGT_DEBUG_REG21__vsthread_buff_full__SHIFT 0x0000000b +#define VGT_DEBUG_REG21__vtx_vect_counter_q_not_0_MASK 0x00800000L +#define VGT_DEBUG_REG21__vtx_vect_counter_q_not_0__SHIFT 0x00000017 +#define VGT_DEBUG_REG21__wait_for_external_eopg_q_MASK 0x00004000L +#define VGT_DEBUG_REG21__wait_for_external_eopg_q__SHIFT 0x0000000e +#define VGT_DEBUG_REG22__cm_state16_MASK 0x00000003L +#define VGT_DEBUG_REG22__cm_state16__SHIFT 0x00000000 +#define VGT_DEBUG_REG22__cm_state17_MASK 0x0000000cL +#define VGT_DEBUG_REG22__cm_state17__SHIFT 0x00000002 +#define VGT_DEBUG_REG22__cm_state18_MASK 0x00000030L +#define VGT_DEBUG_REG22__cm_state18__SHIFT 0x00000004 +#define VGT_DEBUG_REG22__cm_state19_MASK 0x000000c0L +#define VGT_DEBUG_REG22__cm_state19__SHIFT 0x00000006 +#define VGT_DEBUG_REG22__cm_state20_MASK 0x00000300L +#define VGT_DEBUG_REG22__cm_state20__SHIFT 0x00000008 +#define VGT_DEBUG_REG22__cm_state21_MASK 0x00000c00L +#define VGT_DEBUG_REG22__cm_state21__SHIFT 0x0000000a +#define VGT_DEBUG_REG22__cm_state22_MASK 0x00003000L +#define VGT_DEBUG_REG22__cm_state22__SHIFT 0x0000000c +#define VGT_DEBUG_REG22__cm_state23_MASK 0x0000c000L +#define VGT_DEBUG_REG22__cm_state23__SHIFT 0x0000000e +#define VGT_DEBUG_REG22__cm_state24_MASK 0x00030000L +#define VGT_DEBUG_REG22__cm_state24__SHIFT 0x00000010 +#define VGT_DEBUG_REG22__cm_state25_MASK 0x000c0000L +#define VGT_DEBUG_REG22__cm_state25__SHIFT 0x00000012 +#define VGT_DEBUG_REG22__cm_state26_MASK 0x00300000L +#define VGT_DEBUG_REG22__cm_state26__SHIFT 0x00000014 +#define VGT_DEBUG_REG22__cm_state27_MASK 0x00c00000L +#define VGT_DEBUG_REG22__cm_state27__SHIFT 0x00000016 +#define VGT_DEBUG_REG22__cm_state28_MASK 0x03000000L +#define VGT_DEBUG_REG22__cm_state28__SHIFT 0x00000018 +#define VGT_DEBUG_REG22__cm_state29_MASK 0x0c000000L +#define VGT_DEBUG_REG22__cm_state29__SHIFT 0x0000001a +#define VGT_DEBUG_REG22__cm_state30_MASK 0x30000000L +#define VGT_DEBUG_REG22__cm_state30__SHIFT 0x0000001c +#define VGT_DEBUG_REG22__cm_state31_MASK 0xc0000000L +#define VGT_DEBUG_REG22__cm_state31__SHIFT 0x0000001e +#define VGT_DEBUG_REG23__frmt_busy_MASK 0x00000001L +#define VGT_DEBUG_REG23__frmt_busy__SHIFT 0x00000000 +#define VGT_DEBUG_REG23__new_verts_r2_q_MASK 0x00018000L +#define VGT_DEBUG_REG23__new_verts_r2_q__SHIFT 0x0000000f +#define VGT_DEBUG_REG23__prim_dr_r2_q_MASK 0x00001000L +#define VGT_DEBUG_REG23__prim_dr_r2_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG23__prim_fifo_empty_MASK 0x00000200L +#define VGT_DEBUG_REG23__prim_fifo_empty__SHIFT 0x00000009 +#define VGT_DEBUG_REG23__prim_fifo_full_MASK 0x00000400L +#define VGT_DEBUG_REG23__prim_fifo_full__SHIFT 0x0000000a +#define VGT_DEBUG_REG23__prim_r2_rtr_MASK 0x00000010L +#define VGT_DEBUG_REG23__prim_r2_rtr__SHIFT 0x00000004 +#define VGT_DEBUG_REG23__prim_r3_rtr_MASK 0x00000008L +#define VGT_DEBUG_REG23__prim_r3_rtr__SHIFT 0x00000003 +#define VGT_DEBUG_REG23__prim_state_sel_r2_q_MASK 0x00e00000L +#define VGT_DEBUG_REG23__prim_state_sel_r2_q__SHIFT 0x00000015 +#define VGT_DEBUG_REG23__rcm_frmt_prim_rtr_MASK 0x00000004L +#define VGT_DEBUG_REG23__rcm_frmt_prim_rtr__SHIFT 0x00000002 +#define VGT_DEBUG_REG23__rcm_frmt_vert_rtr_MASK 0x00000002L +#define VGT_DEBUG_REG23__rcm_frmt_vert_rtr__SHIFT 0x00000001 +#define VGT_DEBUG_REG23__SPARE_MASK 0xff000000L +#define VGT_DEBUG_REG23__SPARE__SHIFT 0x00000018 +#define VGT_DEBUG_REG23__vert_dr_r0_q_MASK 0x00004000L +#define VGT_DEBUG_REG23__vert_dr_r0_q__SHIFT 0x0000000e +#define VGT_DEBUG_REG23__vert_dr_r1_q_MASK 0x00002000L +#define VGT_DEBUG_REG23__vert_dr_r1_q__SHIFT 0x0000000d +#define VGT_DEBUG_REG23__vert_dr_r2_q_MASK 0x00000800L +#define VGT_DEBUG_REG23__vert_dr_r2_q__SHIFT 0x0000000b +#define VGT_DEBUG_REG23__vert_r0_rtr_MASK 0x00000100L +#define VGT_DEBUG_REG23__vert_r0_rtr__SHIFT 0x00000008 +#define VGT_DEBUG_REG23__vert_r1_rtr_MASK 0x00000080L +#define VGT_DEBUG_REG23__vert_r1_rtr__SHIFT 0x00000007 +#define VGT_DEBUG_REG23__vert_r2_rtr_MASK 0x00000040L +#define VGT_DEBUG_REG23__vert_r2_rtr__SHIFT 0x00000006 +#define VGT_DEBUG_REG23__vert_r3_rtr_MASK 0x00000020L +#define VGT_DEBUG_REG23__vert_r3_rtr__SHIFT 0x00000005 +#define VGT_DEBUG_REG23__verts_sent_r2_q_MASK 0x001e0000L +#define VGT_DEBUG_REG23__verts_sent_r2_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG24__avail_es_rb_space_r0_q_23_0_MASK 0x00ffffffL +#define VGT_DEBUG_REG24__avail_es_rb_space_r0_q_23_0__SHIFT 0x00000000 +#define VGT_DEBUG_REG24__dependent_st_cut_mode_q_MASK 0x03000000L +#define VGT_DEBUG_REG24__dependent_st_cut_mode_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG24__SPARE31_MASK 0xfc000000L +#define VGT_DEBUG_REG24__SPARE31__SHIFT 0x0000001a +#define VGT_DEBUG_REG25__active_sm_r0_q_MASK 0x3c000000L +#define VGT_DEBUG_REG25__active_sm_r0_q__SHIFT 0x0000001a +#define VGT_DEBUG_REG25__add_gs_rb_space_r0_q_MASK 0x80000000L +#define VGT_DEBUG_REG25__add_gs_rb_space_r0_q__SHIFT 0x0000001f +#define VGT_DEBUG_REG25__add_gs_rb_space_r1_q_MASK 0x40000000L +#define VGT_DEBUG_REG25__add_gs_rb_space_r1_q__SHIFT 0x0000001e +#define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0_MASK 0x03ffffffL +#define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0__SHIFT 0x00000000 +#define VGT_DEBUG_REG26__cm_state0_MASK 0x00000003L +#define VGT_DEBUG_REG26__cm_state0__SHIFT 0x00000000 +#define VGT_DEBUG_REG26__cm_state10_MASK 0x00300000L +#define VGT_DEBUG_REG26__cm_state10__SHIFT 0x00000014 +#define VGT_DEBUG_REG26__cm_state11_MASK 0x00c00000L +#define VGT_DEBUG_REG26__cm_state11__SHIFT 0x00000016 +#define VGT_DEBUG_REG26__cm_state12_MASK 0x03000000L +#define VGT_DEBUG_REG26__cm_state12__SHIFT 0x00000018 +#define VGT_DEBUG_REG26__cm_state13_MASK 0x0c000000L +#define VGT_DEBUG_REG26__cm_state13__SHIFT 0x0000001a +#define VGT_DEBUG_REG26__cm_state14_MASK 0x30000000L +#define VGT_DEBUG_REG26__cm_state14__SHIFT 0x0000001c +#define VGT_DEBUG_REG26__cm_state15_MASK 0xc0000000L +#define VGT_DEBUG_REG26__cm_state15__SHIFT 0x0000001e +#define VGT_DEBUG_REG26__cm_state1_MASK 0x0000000cL +#define VGT_DEBUG_REG26__cm_state1__SHIFT 0x00000002 +#define VGT_DEBUG_REG26__cm_state2_MASK 0x00000030L +#define VGT_DEBUG_REG26__cm_state2__SHIFT 0x00000004 +#define VGT_DEBUG_REG26__cm_state3_MASK 0x000000c0L +#define VGT_DEBUG_REG26__cm_state3__SHIFT 0x00000006 +#define VGT_DEBUG_REG26__cm_state4_MASK 0x00000300L +#define VGT_DEBUG_REG26__cm_state4__SHIFT 0x00000008 +#define VGT_DEBUG_REG26__cm_state5_MASK 0x00000c00L +#define VGT_DEBUG_REG26__cm_state5__SHIFT 0x0000000a +#define VGT_DEBUG_REG26__cm_state6_MASK 0x00003000L +#define VGT_DEBUG_REG26__cm_state6__SHIFT 0x0000000c +#define VGT_DEBUG_REG26__cm_state7_MASK 0x0000c000L +#define VGT_DEBUG_REG26__cm_state7__SHIFT 0x0000000e +#define VGT_DEBUG_REG26__cm_state8_MASK 0x00030000L +#define VGT_DEBUG_REG26__cm_state8__SHIFT 0x00000010 +#define VGT_DEBUG_REG26__cm_state9_MASK 0x000c0000L +#define VGT_DEBUG_REG26__cm_state9__SHIFT 0x00000012 +#define VGT_DEBUG_REG27__eop_p1_q_MASK 0x00000800L +#define VGT_DEBUG_REG27__eop_p1_q__SHIFT 0x0000000b +#define VGT_DEBUG_REG27__event_flag_p1_q_MASK 0x00000400L +#define VGT_DEBUG_REG27__event_flag_p1_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG27__first_vsprim_of_gsprim_p0_q_MASK 0x00080000L +#define VGT_DEBUG_REG27__first_vsprim_of_gsprim_p0_q__SHIFT 0x00000013 +#define VGT_DEBUG_REG27__gsc0_dr_MASK 0x00000002L +#define VGT_DEBUG_REG27__gsc0_dr__SHIFT 0x00000001 +#define VGT_DEBUG_REG27__gsc0_rtr_MASK 0x00000020L +#define VGT_DEBUG_REG27__gsc0_rtr__SHIFT 0x00000005 +#define VGT_DEBUG_REG27__gsc_2cycle_output_MASK 0x00010000L +#define VGT_DEBUG_REG27__gsc_2cycle_output__SHIFT 0x00000010 +#define VGT_DEBUG_REG27__gsc_2nd_cycle_p0_q_MASK 0x00020000L +#define VGT_DEBUG_REG27__gsc_2nd_cycle_p0_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG27__gsc_eop_p0_q_MASK 0x00008000L +#define VGT_DEBUG_REG27__gsc_eop_p0_q__SHIFT 0x0000000f +#define VGT_DEBUG_REG27__gsc_indx_count_p0_q_MASK 0x7ff00000L +#define VGT_DEBUG_REG27__gsc_indx_count_p0_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG27__gsc_null_primitive_p0_q_MASK 0x00004000L +#define VGT_DEBUG_REG27__gsc_null_primitive_p0_q__SHIFT 0x0000000e +#define VGT_DEBUG_REG27__gs_out_prim_type_p0_q_MASK 0x00003000L +#define VGT_DEBUG_REG27__gs_out_prim_type_p0_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG27__indices_to_send_p0_q_MASK 0x00000300L +#define VGT_DEBUG_REG27__indices_to_send_p0_q__SHIFT 0x00000008 +#define VGT_DEBUG_REG27__last_indx_of_prim_p1_q_MASK 0x00000080L +#define VGT_DEBUG_REG27__last_indx_of_prim_p1_q__SHIFT 0x00000007 +#define VGT_DEBUG_REG27__last_indx_of_vsprim_MASK 0x00040000L +#define VGT_DEBUG_REG27__last_indx_of_vsprim__SHIFT 0x00000012 +#define VGT_DEBUG_REG27__last_vsprim_of_gsprim_MASK 0x80000000L +#define VGT_DEBUG_REG27__last_vsprim_of_gsprim__SHIFT 0x0000001f +#define VGT_DEBUG_REG27__pipe0_dr_MASK 0x00000001L +#define VGT_DEBUG_REG27__pipe0_dr__SHIFT 0x00000000 +#define VGT_DEBUG_REG27__pipe0_rtr_MASK 0x00000010L +#define VGT_DEBUG_REG27__pipe0_rtr__SHIFT 0x00000004 +#define VGT_DEBUG_REG27__pipe1_dr_MASK 0x00000004L +#define VGT_DEBUG_REG27__pipe1_dr__SHIFT 0x00000002 +#define VGT_DEBUG_REG27__pipe1_rtr_MASK 0x00000040L +#define VGT_DEBUG_REG27__pipe1_rtr__SHIFT 0x00000006 +#define VGT_DEBUG_REG27__tm_pt_event_rtr_MASK 0x00000008L +#define VGT_DEBUG_REG27__tm_pt_event_rtr__SHIFT 0x00000003 +#define VGT_DEBUG_REG28__advance_inner_point_p1_MASK 0x00800000L +#define VGT_DEBUG_REG28__advance_inner_point_p1__SHIFT 0x00000017 +#define VGT_DEBUG_REG28__advance_outer_point_p1_MASK 0x00400000L +#define VGT_DEBUG_REG28__advance_outer_point_p1__SHIFT 0x00000016 +#define VGT_DEBUG_REG28__con_state_q_MASK 0x0000000fL +#define VGT_DEBUG_REG28__con_state_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG28__first_ring_of_patch_p0_q_MASK 0x00010000L +#define VGT_DEBUG_REG28__first_ring_of_patch_p0_q__SHIFT 0x00000010 +#define VGT_DEBUG_REG28__last_edge_of_outer_ring_p0_q_MASK 0x00040000L +#define VGT_DEBUG_REG28__last_edge_of_outer_ring_p0_q__SHIFT 0x00000012 +#define VGT_DEBUG_REG28__last_point_of_inner_ring_p1_MASK 0x00100000L +#define VGT_DEBUG_REG28__last_point_of_inner_ring_p1__SHIFT 0x00000014 +#define VGT_DEBUG_REG28__last_point_of_outer_ring_p1_MASK 0x00080000L +#define VGT_DEBUG_REG28__last_point_of_outer_ring_p1__SHIFT 0x00000013 +#define VGT_DEBUG_REG28__last_ring_of_patch_p0_q_MASK 0x00020000L +#define VGT_DEBUG_REG28__last_ring_of_patch_p0_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG28__next_ring_is_rect_p0_q_MASK 0x01000000L +#define VGT_DEBUG_REG28__next_ring_is_rect_p0_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG28__outer_edge_tf_eq_one_p0_q_MASK 0x00200000L +#define VGT_DEBUG_REG28__outer_edge_tf_eq_one_p0_q__SHIFT 0x00000015 +#define VGT_DEBUG_REG28__outer_parity_p0_q_MASK 0x00004000L +#define VGT_DEBUG_REG28__outer_parity_p0_q__SHIFT 0x0000000e +#define VGT_DEBUG_REG28__parallel_parity_p0_q_MASK 0x00008000L +#define VGT_DEBUG_REG28__parallel_parity_p0_q__SHIFT 0x0000000f +#define VGT_DEBUG_REG28__pipe0_edge_dr_MASK 0x00000200L +#define VGT_DEBUG_REG28__pipe0_edge_dr__SHIFT 0x00000009 +#define VGT_DEBUG_REG28__pipe0_edge_rtr_MASK 0x00001000L +#define VGT_DEBUG_REG28__pipe0_edge_rtr__SHIFT 0x0000000c +#define VGT_DEBUG_REG28__pipe0_patch_dr_MASK 0x00000100L +#define VGT_DEBUG_REG28__pipe0_patch_dr__SHIFT 0x00000008 +#define VGT_DEBUG_REG28__pipe0_patch_rtr_MASK 0x00000800L +#define VGT_DEBUG_REG28__pipe0_patch_rtr__SHIFT 0x0000000b +#define VGT_DEBUG_REG28__pipe1_dr_MASK 0x00000400L +#define VGT_DEBUG_REG28__pipe1_dr__SHIFT 0x0000000a +#define VGT_DEBUG_REG28__pipe1_edge_rtr_MASK 0x40000000L +#define VGT_DEBUG_REG28__pipe1_edge_rtr__SHIFT 0x0000001e +#define VGT_DEBUG_REG28__pipe1_inner1_rtr_MASK 0x08000000L +#define VGT_DEBUG_REG28__pipe1_inner1_rtr__SHIFT 0x0000001b +#define VGT_DEBUG_REG28__pipe1_inner2_rtr_MASK 0x10000000L +#define VGT_DEBUG_REG28__pipe1_inner2_rtr__SHIFT 0x0000001c +#define VGT_DEBUG_REG28__pipe1_outer1_rtr_MASK 0x02000000L +#define VGT_DEBUG_REG28__pipe1_outer1_rtr__SHIFT 0x00000019 +#define VGT_DEBUG_REG28__pipe1_outer2_rtr_MASK 0x04000000L +#define VGT_DEBUG_REG28__pipe1_outer2_rtr__SHIFT 0x0000001a +#define VGT_DEBUG_REG28__pipe1_patch_rtr_MASK 0x20000000L +#define VGT_DEBUG_REG28__pipe1_patch_rtr__SHIFT 0x0000001d +#define VGT_DEBUG_REG28__pipe1_rtr_MASK 0x00002000L +#define VGT_DEBUG_REG28__pipe1_rtr__SHIFT 0x0000000d +#define VGT_DEBUG_REG28__process_tri_1st_2nd_half_p0_q_MASK 0x00000040L +#define VGT_DEBUG_REG28__process_tri_1st_2nd_half_p0_q__SHIFT 0x00000006 +#define VGT_DEBUG_REG28__process_tri_center_poly_p0_q_MASK 0x00000080L +#define VGT_DEBUG_REG28__process_tri_center_poly_p0_q__SHIFT 0x00000007 +#define VGT_DEBUG_REG28__process_tri_middle_p0_q_MASK 0x00000020L +#define VGT_DEBUG_REG28__process_tri_middle_p0_q__SHIFT 0x00000005 +#define VGT_DEBUG_REG28__second_cycle_q_MASK 0x00000010L +#define VGT_DEBUG_REG28__second_cycle_q__SHIFT 0x00000004 +#define VGT_DEBUG_REG28__use_stored_inner_q_ring2_MASK 0x80000000L +#define VGT_DEBUG_REG28__use_stored_inner_q_ring2__SHIFT 0x0000001f +#define VGT_DEBUG_REG29__advance_inner_point_p1_MASK 0x00800000L +#define VGT_DEBUG_REG29__advance_inner_point_p1__SHIFT 0x00000017 +#define VGT_DEBUG_REG29__advance_outer_point_p1_MASK 0x00400000L +#define VGT_DEBUG_REG29__advance_outer_point_p1__SHIFT 0x00000016 +#define VGT_DEBUG_REG29__con_state_q_MASK 0x0000000fL +#define VGT_DEBUG_REG29__con_state_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG29__first_ring_of_patch_p0_q_MASK 0x00010000L +#define VGT_DEBUG_REG29__first_ring_of_patch_p0_q__SHIFT 0x00000010 +#define VGT_DEBUG_REG29__last_edge_of_outer_ring_p0_q_MASK 0x00040000L +#define VGT_DEBUG_REG29__last_edge_of_outer_ring_p0_q__SHIFT 0x00000012 +#define VGT_DEBUG_REG29__last_point_of_inner_ring_p1_MASK 0x00100000L +#define VGT_DEBUG_REG29__last_point_of_inner_ring_p1__SHIFT 0x00000014 +#define VGT_DEBUG_REG29__last_point_of_outer_ring_p1_MASK 0x00080000L +#define VGT_DEBUG_REG29__last_point_of_outer_ring_p1__SHIFT 0x00000013 +#define VGT_DEBUG_REG29__last_ring_of_patch_p0_q_MASK 0x00020000L +#define VGT_DEBUG_REG29__last_ring_of_patch_p0_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG29__next_ring_is_rect_p0_q_MASK 0x01000000L +#define VGT_DEBUG_REG29__next_ring_is_rect_p0_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG29__outer_edge_tf_eq_one_p0_q_MASK 0x00200000L +#define VGT_DEBUG_REG29__outer_edge_tf_eq_one_p0_q__SHIFT 0x00000015 +#define VGT_DEBUG_REG29__outer_parity_p0_q_MASK 0x00004000L +#define VGT_DEBUG_REG29__outer_parity_p0_q__SHIFT 0x0000000e +#define VGT_DEBUG_REG29__parallel_parity_p0_q_MASK 0x00008000L +#define VGT_DEBUG_REG29__parallel_parity_p0_q__SHIFT 0x0000000f +#define VGT_DEBUG_REG29__pipe0_edge_dr_MASK 0x00000200L +#define VGT_DEBUG_REG29__pipe0_edge_dr__SHIFT 0x00000009 +#define VGT_DEBUG_REG29__pipe0_edge_rtr_MASK 0x00001000L +#define VGT_DEBUG_REG29__pipe0_edge_rtr__SHIFT 0x0000000c +#define VGT_DEBUG_REG29__pipe0_patch_dr_MASK 0x00000100L +#define VGT_DEBUG_REG29__pipe0_patch_dr__SHIFT 0x00000008 +#define VGT_DEBUG_REG29__pipe0_patch_rtr_MASK 0x00000800L +#define VGT_DEBUG_REG29__pipe0_patch_rtr__SHIFT 0x0000000b +#define VGT_DEBUG_REG29__pipe1_dr_MASK 0x00000400L +#define VGT_DEBUG_REG29__pipe1_dr__SHIFT 0x0000000a +#define VGT_DEBUG_REG29__pipe1_edge_rtr_MASK 0x40000000L +#define VGT_DEBUG_REG29__pipe1_edge_rtr__SHIFT 0x0000001e +#define VGT_DEBUG_REG29__pipe1_inner1_rtr_MASK 0x08000000L +#define VGT_DEBUG_REG29__pipe1_inner1_rtr__SHIFT 0x0000001b +#define VGT_DEBUG_REG29__pipe1_inner2_rtr_MASK 0x10000000L +#define VGT_DEBUG_REG29__pipe1_inner2_rtr__SHIFT 0x0000001c +#define VGT_DEBUG_REG29__pipe1_outer1_rtr_MASK 0x02000000L +#define VGT_DEBUG_REG29__pipe1_outer1_rtr__SHIFT 0x00000019 +#define VGT_DEBUG_REG29__pipe1_outer2_rtr_MASK 0x04000000L +#define VGT_DEBUG_REG29__pipe1_outer2_rtr__SHIFT 0x0000001a +#define VGT_DEBUG_REG29__pipe1_patch_rtr_MASK 0x20000000L +#define VGT_DEBUG_REG29__pipe1_patch_rtr__SHIFT 0x0000001d +#define VGT_DEBUG_REG29__pipe1_rtr_MASK 0x00002000L +#define VGT_DEBUG_REG29__pipe1_rtr__SHIFT 0x0000000d +#define VGT_DEBUG_REG29__process_tri_1st_2nd_half_p0_q_MASK 0x00000040L +#define VGT_DEBUG_REG29__process_tri_1st_2nd_half_p0_q__SHIFT 0x00000006 +#define VGT_DEBUG_REG29__process_tri_center_poly_p0_q_MASK 0x00000080L +#define VGT_DEBUG_REG29__process_tri_center_poly_p0_q__SHIFT 0x00000007 +#define VGT_DEBUG_REG29__process_tri_middle_p0_q_MASK 0x00000020L +#define VGT_DEBUG_REG29__process_tri_middle_p0_q__SHIFT 0x00000005 +#define VGT_DEBUG_REG29__second_cycle_q_MASK 0x00000010L +#define VGT_DEBUG_REG29__second_cycle_q__SHIFT 0x00000004 +#define VGT_DEBUG_REG29__use_stored_inner_q_ring3_MASK 0x80000000L +#define VGT_DEBUG_REG29__use_stored_inner_q_ring3__SHIFT 0x0000001f +#define VGT_DEBUG_REG2__grpModBusy_MASK 0x00000080L +#define VGT_DEBUG_REG2__grpModBusy__SHIFT 0x00000007 +#define VGT_DEBUG_REG2__hs_grp_busy_MASK 0x00000001L +#define VGT_DEBUG_REG2__hs_grp_busy__SHIFT 0x00000000 +#define VGT_DEBUG_REG2__hsInputFifoEmpty_MASK 0x00001000L +#define VGT_DEBUG_REG2__hsInputFifoEmpty__SHIFT 0x0000000c +#define VGT_DEBUG_REG2__hsInputFifoFull_MASK 0x00040000L +#define VGT_DEBUG_REG2__hsInputFifoFull__SHIFT 0x00000012 +#define VGT_DEBUG_REG2__hs_noif_busy_MASK 0x00000002L +#define VGT_DEBUG_REG2__hs_noif_busy__SHIFT 0x00000001 +#define VGT_DEBUG_REG2__hs_te11_tess_input_rts_MASK 0x00000040L +#define VGT_DEBUG_REG2__hs_te11_tess_input_rts__SHIFT 0x00000006 +#define VGT_DEBUG_REG2__hsTifFifoEmpty_MASK 0x00002000L +#define VGT_DEBUG_REG2__hsTifFifoEmpty__SHIFT 0x0000000d +#define VGT_DEBUG_REG2__hsTifFifoFull_MASK 0x00080000L +#define VGT_DEBUG_REG2__hsTifFifoFull__SHIFT 0x00000013 +#define VGT_DEBUG_REG2__hsVertFifoEmpty_MASK 0x00000400L +#define VGT_DEBUG_REG2__hsVertFifoEmpty__SHIFT 0x0000000a +#define VGT_DEBUG_REG2__hsVertFifoFull_MASK 0x00010000L +#define VGT_DEBUG_REG2__hsVertFifoFull__SHIFT 0x00000010 +#define VGT_DEBUG_REG2__hsWaveFifoEmpty_MASK 0x00000800L +#define VGT_DEBUG_REG2__hsWaveFifoEmpty__SHIFT 0x0000000b +#define VGT_DEBUG_REG2__hsWaveFifoFull_MASK 0x00020000L +#define VGT_DEBUG_REG2__hsWaveFifoFull__SHIFT 0x00000011 +#define VGT_DEBUG_REG2__lsFwaveFlag_MASK 0x08000000L +#define VGT_DEBUG_REG2__lsFwaveFlag__SHIFT 0x0000001b +#define VGT_DEBUG_REG2__ls_sh_id_MASK 0x04000000L +#define VGT_DEBUG_REG2__ls_sh_id__SHIFT 0x0000001a +#define VGT_DEBUG_REG2__lsVertFifoEmpty_MASK 0x00000100L +#define VGT_DEBUG_REG2__lsVertFifoEmpty__SHIFT 0x00000008 +#define VGT_DEBUG_REG2__lsVertFifoFull_MASK 0x00004000L +#define VGT_DEBUG_REG2__lsVertFifoFull__SHIFT 0x0000000e +#define VGT_DEBUG_REG2__lsVertIfBusy_0_MASK 0x00000008L +#define VGT_DEBUG_REG2__lsVertIfBusy_0__SHIFT 0x00000003 +#define VGT_DEBUG_REG2__lsWaveFifoEmpty_MASK 0x00000200L +#define VGT_DEBUG_REG2__lsWaveFifoEmpty__SHIFT 0x00000009 +#define VGT_DEBUG_REG2__lsWaveFifoFull_MASK 0x00008000L +#define VGT_DEBUG_REG2__lsWaveFifoFull__SHIFT 0x0000000f +#define VGT_DEBUG_REG2__lsWaveIfBusy_0_MASK 0x00000020L +#define VGT_DEBUG_REG2__lsWaveIfBusy_0__SHIFT 0x00000005 +#define VGT_DEBUG_REG2__lsWaveSendFlush_MASK 0x10000000L +#define VGT_DEBUG_REG2__lsWaveSendFlush__SHIFT 0x0000001c +#define VGT_DEBUG_REG2__p0_dr_MASK 0x00400000L +#define VGT_DEBUG_REG2__p0_dr__SHIFT 0x00000016 +#define VGT_DEBUG_REG2__p0_rtr_MASK 0x00100000L +#define VGT_DEBUG_REG2__p0_rtr__SHIFT 0x00000014 +#define VGT_DEBUG_REG2__p0_rts_MASK 0x01000000L +#define VGT_DEBUG_REG2__p0_rts__SHIFT 0x00000018 +#define VGT_DEBUG_REG2__p1_dr_MASK 0x00800000L +#define VGT_DEBUG_REG2__p1_dr__SHIFT 0x00000017 +#define VGT_DEBUG_REG2__p1_rtr_MASK 0x00200000L +#define VGT_DEBUG_REG2__p1_rtr__SHIFT 0x00000015 +#define VGT_DEBUG_REG2__p1_rts_MASK 0x02000000L +#define VGT_DEBUG_REG2__p1_rts__SHIFT 0x00000019 +#define VGT_DEBUG_REG2__SPARE_MASK 0xffffffffL +#define VGT_DEBUG_REG2__SPARE__SHIFT 0x00000000 +#define VGT_DEBUG_REG2__te11_hs_tess_input_rtr_MASK 0x00000010L +#define VGT_DEBUG_REG2__te11_hs_tess_input_rtr__SHIFT 0x00000004 +#define VGT_DEBUG_REG2__tfmmIsBusy_MASK 0x00000004L +#define VGT_DEBUG_REG2__tfmmIsBusy__SHIFT 0x00000002 +#define VGT_DEBUG_REG30__dynamic_hs_p0_q_MASK 0x01000000L +#define VGT_DEBUG_REG30__dynamic_hs_p0_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG30__event_or_null_p0_q_MASK 0x00000008L +#define VGT_DEBUG_REG30__event_or_null_p0_q__SHIFT 0x00000003 +#define VGT_DEBUG_REG30__first_data_chunk_invalid_p0_q_MASK 0x08000000L +#define VGT_DEBUG_REG30__first_data_chunk_invalid_p0_q__SHIFT 0x0000001b +#define VGT_DEBUG_REG30__first_data_ret_of_req_p0_q_MASK 0x04000000L +#define VGT_DEBUG_REG30__first_data_ret_of_req_p0_q__SHIFT 0x0000001a +#define VGT_DEBUG_REG30__first_fetch_of_tg_p0_q_MASK 0x02000000L +#define VGT_DEBUG_REG30__first_fetch_of_tg_p0_q__SHIFT 0x00000019 +#define VGT_DEBUG_REG30__last_tf_of_tg_MASK 0x00080000L +#define VGT_DEBUG_REG30__last_tf_of_tg__SHIFT 0x00000013 +#define VGT_DEBUG_REG30__pipe0_dr_MASK 0x00000001L +#define VGT_DEBUG_REG30__pipe0_dr__SHIFT 0x00000000 +#define VGT_DEBUG_REG30__pipe0_rtr_MASK 0x00000010L +#define VGT_DEBUG_REG30__pipe0_rtr__SHIFT 0x00000004 +#define VGT_DEBUG_REG30__pipe0_tf_dr_MASK 0x00000002L +#define VGT_DEBUG_REG30__pipe0_tf_dr__SHIFT 0x00000001 +#define VGT_DEBUG_REG30__pipe1_rtr_MASK 0x00000020L +#define VGT_DEBUG_REG30__pipe1_rtr__SHIFT 0x00000005 +#define VGT_DEBUG_REG30__pipe1_tf_rtr_MASK 0x00000040L +#define VGT_DEBUG_REG30__pipe1_tf_rtr__SHIFT 0x00000006 +#define VGT_DEBUG_REG30__pipe2_dr_MASK 0x00000004L +#define VGT_DEBUG_REG30__pipe2_dr__SHIFT 0x00000002 +#define VGT_DEBUG_REG30__pipe2_rtr_MASK 0x00000080L +#define VGT_DEBUG_REG30__pipe2_rtr__SHIFT 0x00000007 +#define VGT_DEBUG_REG30__pipe4_dr_MASK 0x40000000L +#define VGT_DEBUG_REG30__pipe4_dr__SHIFT 0x0000001e +#define VGT_DEBUG_REG30__pipe4_rtr_MASK 0x80000000L +#define VGT_DEBUG_REG30__pipe4_rtr__SHIFT 0x0000001f +#define VGT_DEBUG_REG30__tf_fetch_state_q_MASK 0x00070000L +#define VGT_DEBUG_REG30__tf_fetch_state_q__SHIFT 0x00000010 +#define VGT_DEBUG_REG30__tf_pointer_p0_q_MASK 0x00f00000L +#define VGT_DEBUG_REG30__tf_pointer_p0_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG30__tf_xfer_count_p2_q_MASK 0x30000000L +#define VGT_DEBUG_REG30__tf_xfer_count_p2_q__SHIFT 0x0000001c +#define VGT_DEBUG_REG30__ttp_patch_fifo_empty_MASK 0x00000200L +#define VGT_DEBUG_REG30__ttp_patch_fifo_empty__SHIFT 0x00000009 +#define VGT_DEBUG_REG30__ttp_patch_fifo_full_MASK 0x00000100L +#define VGT_DEBUG_REG30__ttp_patch_fifo_full__SHIFT 0x00000008 +#define VGT_DEBUG_REG30__ttp_tf0_fifo_empty_MASK 0x00000400L +#define VGT_DEBUG_REG30__ttp_tf0_fifo_empty__SHIFT 0x0000000a +#define VGT_DEBUG_REG30__ttp_tf1_fifo_empty_MASK 0x00000800L +#define VGT_DEBUG_REG30__ttp_tf1_fifo_empty__SHIFT 0x0000000b +#define VGT_DEBUG_REG30__ttp_tf2_fifo_empty_MASK 0x00001000L +#define VGT_DEBUG_REG30__ttp_tf2_fifo_empty__SHIFT 0x0000000c +#define VGT_DEBUG_REG30__ttp_tf3_fifo_empty_MASK 0x00002000L +#define VGT_DEBUG_REG30__ttp_tf3_fifo_empty__SHIFT 0x0000000d +#define VGT_DEBUG_REG30__ttp_tf4_fifo_empty_MASK 0x00004000L +#define VGT_DEBUG_REG30__ttp_tf4_fifo_empty__SHIFT 0x0000000e +#define VGT_DEBUG_REG30__ttp_tf5_fifo_empty_MASK 0x00008000L +#define VGT_DEBUG_REG30__ttp_tf5_fifo_empty__SHIFT 0x0000000f +#define VGT_DEBUG_REG31__inner_ring_done_q_MASK 0x80000000L +#define VGT_DEBUG_REG31__inner_ring_done_q__SHIFT 0x0000001f +#define VGT_DEBUG_REG31__outer_ring_done_q_MASK 0x40000000L +#define VGT_DEBUG_REG31__outer_ring_done_q__SHIFT 0x0000001e +#define VGT_DEBUG_REG31__pg_con_inner_point1_rts_MASK 0x00400000L +#define VGT_DEBUG_REG31__pg_con_inner_point1_rts__SHIFT 0x00000016 +#define VGT_DEBUG_REG31__pg_con_inner_point2_rts_MASK 0x00800000L +#define VGT_DEBUG_REG31__pg_con_inner_point2_rts__SHIFT 0x00000017 +#define VGT_DEBUG_REG31__pg_con_outer_point1_rts_MASK 0x00100000L +#define VGT_DEBUG_REG31__pg_con_outer_point1_rts__SHIFT 0x00000014 +#define VGT_DEBUG_REG31__pg_con_outer_point2_rts_MASK 0x00200000L +#define VGT_DEBUG_REG31__pg_con_outer_point2_rts__SHIFT 0x00000015 +#define VGT_DEBUG_REG31__pg_edge_fifo_empty_MASK 0x02000000L +#define VGT_DEBUG_REG31__pg_edge_fifo_empty__SHIFT 0x00000019 +#define VGT_DEBUG_REG31__pg_edge_fifo_full_MASK 0x10000000L +#define VGT_DEBUG_REG31__pg_edge_fifo_full__SHIFT 0x0000001c +#define VGT_DEBUG_REG31__pg_inner3_perp_fifo_empty_MASK 0x04000000L +#define VGT_DEBUG_REG31__pg_inner3_perp_fifo_empty__SHIFT 0x0000001a +#define VGT_DEBUG_REG31__pg_inner_perp_fifo_full_MASK 0x20000000L +#define VGT_DEBUG_REG31__pg_inner_perp_fifo_full__SHIFT 0x0000001d +#define VGT_DEBUG_REG31__pg_patch_fifo_empty_MASK 0x01000000L +#define VGT_DEBUG_REG31__pg_patch_fifo_empty__SHIFT 0x00000018 +#define VGT_DEBUG_REG31__pg_patch_fifo_full_MASK 0x08000000L +#define VGT_DEBUG_REG31__pg_patch_fifo_full__SHIFT 0x0000001b +#define VGT_DEBUG_REG31__pipe0_dr_MASK 0x00000001L +#define VGT_DEBUG_REG31__pipe0_dr__SHIFT 0x00000000 +#define VGT_DEBUG_REG31__pipe0_rtr_MASK 0x00000002L +#define VGT_DEBUG_REG31__pipe0_rtr__SHIFT 0x00000001 +#define VGT_DEBUG_REG31__pipe1_inner_dr_MASK 0x00000008L +#define VGT_DEBUG_REG31__pipe1_inner_dr__SHIFT 0x00000003 +#define VGT_DEBUG_REG31__pipe1_outer_dr_MASK 0x00000004L +#define VGT_DEBUG_REG31__pipe1_outer_dr__SHIFT 0x00000002 +#define VGT_DEBUG_REG31__pipe2_inner_dr_MASK 0x00000020L +#define VGT_DEBUG_REG31__pipe2_inner_dr__SHIFT 0x00000005 +#define VGT_DEBUG_REG31__pipe2_inner_rtr_MASK 0x00002000L +#define VGT_DEBUG_REG31__pipe2_inner_rtr__SHIFT 0x0000000d +#define VGT_DEBUG_REG31__pipe2_outer_dr_MASK 0x00000010L +#define VGT_DEBUG_REG31__pipe2_outer_dr__SHIFT 0x00000004 +#define VGT_DEBUG_REG31__pipe2_outer_rtr_MASK 0x00001000L +#define VGT_DEBUG_REG31__pipe2_outer_rtr__SHIFT 0x0000000c +#define VGT_DEBUG_REG31__pipe3_inner_dr_MASK 0x00000080L +#define VGT_DEBUG_REG31__pipe3_inner_dr__SHIFT 0x00000007 +#define VGT_DEBUG_REG31__pipe3_inner_rtr_MASK 0x00008000L +#define VGT_DEBUG_REG31__pipe3_inner_rtr__SHIFT 0x0000000f +#define VGT_DEBUG_REG31__pipe3_outer_dr_MASK 0x00000040L +#define VGT_DEBUG_REG31__pipe3_outer_dr__SHIFT 0x00000006 +#define VGT_DEBUG_REG31__pipe3_outer_rtr_MASK 0x00004000L +#define VGT_DEBUG_REG31__pipe3_outer_rtr__SHIFT 0x0000000e +#define VGT_DEBUG_REG31__pipe4_inner_dr_MASK 0x00000200L +#define VGT_DEBUG_REG31__pipe4_inner_dr__SHIFT 0x00000009 +#define VGT_DEBUG_REG31__pipe4_inner_rtr_MASK 0x00020000L +#define VGT_DEBUG_REG31__pipe4_inner_rtr__SHIFT 0x00000011 +#define VGT_DEBUG_REG31__pipe4_outer_dr_MASK 0x00000100L +#define VGT_DEBUG_REG31__pipe4_outer_dr__SHIFT 0x00000008 +#define VGT_DEBUG_REG31__pipe4_outer_rtr_MASK 0x00010000L +#define VGT_DEBUG_REG31__pipe4_outer_rtr__SHIFT 0x00000010 +#define VGT_DEBUG_REG31__pipe5_inner_dr_MASK 0x00000800L +#define VGT_DEBUG_REG31__pipe5_inner_dr__SHIFT 0x0000000b +#define VGT_DEBUG_REG31__pipe5_inner_rtr_MASK 0x00080000L +#define VGT_DEBUG_REG31__pipe5_inner_rtr__SHIFT 0x00000013 +#define VGT_DEBUG_REG31__pipe5_outer_dr_MASK 0x00000400L +#define VGT_DEBUG_REG31__pipe5_outer_dr__SHIFT 0x0000000a +#define VGT_DEBUG_REG31__pipe5_outer_rtr_MASK 0x00040000L +#define VGT_DEBUG_REG31__pipe5_outer_rtr__SHIFT 0x00000012 +#define VGT_DEBUG_REG32__event_flag_p5_q_MASK 0x00000100L +#define VGT_DEBUG_REG32__event_flag_p5_q__SHIFT 0x00000008 +#define VGT_DEBUG_REG32__event_null_special_p0_q_MASK 0x00000080L +#define VGT_DEBUG_REG32__event_null_special_p0_q__SHIFT 0x00000007 +#define VGT_DEBUG_REG32__fifos_rtr_MASK 0x08000000L +#define VGT_DEBUG_REG32__fifos_rtr__SHIFT 0x0000001b +#define VGT_DEBUG_REG32__first_point_of_edge_p5_q_MASK 0x00000400L +#define VGT_DEBUG_REG32__first_point_of_edge_p5_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG32__first_point_of_patch_p5_q_MASK 0x00000200L +#define VGT_DEBUG_REG32__first_point_of_patch_p5_q__SHIFT 0x00000009 +#define VGT_DEBUG_REG32__first_ring_of_patch_MASK 0x00000001L +#define VGT_DEBUG_REG32__first_ring_of_patch__SHIFT 0x00000000 +#define VGT_DEBUG_REG32__inner2_fifos_rtr_MASK 0x01000000L +#define VGT_DEBUG_REG32__inner2_fifos_rtr__SHIFT 0x00000018 +#define VGT_DEBUG_REG32__inner_fifos_rtr_MASK 0x02000000L +#define VGT_DEBUG_REG32__inner_fifos_rtr__SHIFT 0x00000019 +#define VGT_DEBUG_REG32__last_edge_of_inner_ring_MASK 0x00000010L +#define VGT_DEBUG_REG32__last_edge_of_inner_ring__SHIFT 0x00000004 +#define VGT_DEBUG_REG32__last_edge_of_outer_ring_MASK 0x00000004L +#define VGT_DEBUG_REG32__last_edge_of_outer_ring__SHIFT 0x00000002 +#define VGT_DEBUG_REG32__last_patch_of_tg_p0_q_MASK 0x00000040L +#define VGT_DEBUG_REG32__last_patch_of_tg_p0_q__SHIFT 0x00000006 +#define VGT_DEBUG_REG32__last_patch_of_tg_p5_q_MASK 0x00000800L +#define VGT_DEBUG_REG32__last_patch_of_tg_p5_q__SHIFT 0x0000000b +#define VGT_DEBUG_REG32__last_point_of_inner_edge_MASK 0x00000020L +#define VGT_DEBUG_REG32__last_point_of_inner_edge__SHIFT 0x00000005 +#define VGT_DEBUG_REG32__last_point_of_outer_edge_MASK 0x00000008L +#define VGT_DEBUG_REG32__last_point_of_outer_edge__SHIFT 0x00000003 +#define VGT_DEBUG_REG32__last_ring_of_patch_MASK 0x00000002L +#define VGT_DEBUG_REG32__last_ring_of_patch__SHIFT 0x00000001 +#define VGT_DEBUG_REG32__outer_fifos_rtr_MASK 0x04000000L +#define VGT_DEBUG_REG32__outer_fifos_rtr__SHIFT 0x0000001a +#define VGT_DEBUG_REG32__pg_edge_fifo2_full_MASK 0x00020000L +#define VGT_DEBUG_REG32__pg_edge_fifo2_full__SHIFT 0x00000011 +#define VGT_DEBUG_REG32__pg_edge_fifo3_full_MASK 0x00010000L +#define VGT_DEBUG_REG32__pg_edge_fifo3_full__SHIFT 0x00000010 +#define VGT_DEBUG_REG32__pg_inner2_point_fifo_full_MASK 0x00100000L +#define VGT_DEBUG_REG32__pg_inner2_point_fifo_full__SHIFT 0x00000014 +#define VGT_DEBUG_REG32__pg_inner3_point_fifo_full_MASK 0x00040000L +#define VGT_DEBUG_REG32__pg_inner3_point_fifo_full__SHIFT 0x00000012 +#define VGT_DEBUG_REG32__pg_inner_point_fifo_full_MASK 0x00400000L +#define VGT_DEBUG_REG32__pg_inner_point_fifo_full__SHIFT 0x00000016 +#define VGT_DEBUG_REG32__pg_outer2_point_fifo_full_MASK 0x00200000L +#define VGT_DEBUG_REG32__pg_outer2_point_fifo_full__SHIFT 0x00000015 +#define VGT_DEBUG_REG32__pg_outer3_point_fifo_full_MASK 0x00080000L +#define VGT_DEBUG_REG32__pg_outer3_point_fifo_full__SHIFT 0x00000013 +#define VGT_DEBUG_REG32__pg_outer_point_fifo_full_MASK 0x00800000L +#define VGT_DEBUG_REG32__pg_outer_point_fifo_full__SHIFT 0x00000017 +#define VGT_DEBUG_REG32__pipe5_inner2_rtr_MASK 0x00008000L +#define VGT_DEBUG_REG32__pipe5_inner2_rtr__SHIFT 0x0000000f +#define VGT_DEBUG_REG32__pipe5_inner3_rtr_MASK 0x00004000L +#define VGT_DEBUG_REG32__pipe5_inner3_rtr__SHIFT 0x0000000e +#define VGT_DEBUG_REG32__SPARE_MASK 0x80000000L +#define VGT_DEBUG_REG32__SPARE__SHIFT 0x0000001f +#define VGT_DEBUG_REG32__tess_topology_p5_q_MASK 0x00003000L +#define VGT_DEBUG_REG32__tess_topology_p5_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG33__con_prim_fifo_empty_MASK 0x00040000L +#define VGT_DEBUG_REG33__con_prim_fifo_empty__SHIFT 0x00000012 +#define VGT_DEBUG_REG33__con_prim_fifo_full_MASK 0x00010000L +#define VGT_DEBUG_REG33__con_prim_fifo_full__SHIFT 0x00000010 +#define VGT_DEBUG_REG33__con_ring1_busy_MASK 0x80000000L +#define VGT_DEBUG_REG33__con_ring1_busy__SHIFT 0x0000001f +#define VGT_DEBUG_REG33__con_ring2_busy_MASK 0x40000000L +#define VGT_DEBUG_REG33__con_ring2_busy__SHIFT 0x0000001e +#define VGT_DEBUG_REG33__con_ring3_busy_MASK 0x20000000L +#define VGT_DEBUG_REG33__con_ring3_busy__SHIFT 0x0000001d +#define VGT_DEBUG_REG33__con_vert_fifo_empty_MASK 0x00080000L +#define VGT_DEBUG_REG33__con_vert_fifo_empty__SHIFT 0x00000013 +#define VGT_DEBUG_REG33__con_vert_fifo_full_MASK 0x00020000L +#define VGT_DEBUG_REG33__con_vert_fifo_full__SHIFT 0x00000011 +#define VGT_DEBUG_REG33__first_prim_of_patch_q_MASK 0x00008000L +#define VGT_DEBUG_REG33__first_prim_of_patch_q__SHIFT 0x0000000f +#define VGT_DEBUG_REG33__last_patch_of_tg_p0_q_MASK 0x00100000L +#define VGT_DEBUG_REG33__last_patch_of_tg_p0_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG33__pipe0_patch_dr_MASK 0x00000001L +#define VGT_DEBUG_REG33__pipe0_patch_dr__SHIFT 0x00000000 +#define VGT_DEBUG_REG33__pipe0_patch_rtr_MASK 0x00000010L +#define VGT_DEBUG_REG33__pipe0_patch_rtr__SHIFT 0x00000004 +#define VGT_DEBUG_REG33__pipe1_dr_MASK 0x00000004L +#define VGT_DEBUG_REG33__pipe1_dr__SHIFT 0x00000002 +#define VGT_DEBUG_REG33__pipe1_patch_rtr_MASK 0x00001000L +#define VGT_DEBUG_REG33__pipe1_patch_rtr__SHIFT 0x0000000c +#define VGT_DEBUG_REG33__pipe2_dr_MASK 0x00000008L +#define VGT_DEBUG_REG33__pipe2_dr__SHIFT 0x00000003 +#define VGT_DEBUG_REG33__pipe2_rtr_MASK 0x00000080L +#define VGT_DEBUG_REG33__pipe2_rtr__SHIFT 0x00000007 +#define VGT_DEBUG_REG33__pipe3_dr_MASK 0x00000100L +#define VGT_DEBUG_REG33__pipe3_dr__SHIFT 0x00000008 +#define VGT_DEBUG_REG33__pipe3_rtr_MASK 0x00000200L +#define VGT_DEBUG_REG33__pipe3_rtr__SHIFT 0x00000009 +#define VGT_DEBUG_REG33__ring1_in_sync_q_MASK 0x00000800L +#define VGT_DEBUG_REG33__ring1_in_sync_q__SHIFT 0x0000000b +#define VGT_DEBUG_REG33__ring1_pipe1_dr_MASK 0x00000040L +#define VGT_DEBUG_REG33__ring1_pipe1_dr__SHIFT 0x00000006 +#define VGT_DEBUG_REG33__ring1_valid_p2_MASK 0x00800000L +#define VGT_DEBUG_REG33__ring1_valid_p2__SHIFT 0x00000017 +#define VGT_DEBUG_REG33__ring2_in_sync_q_MASK 0x00000400L +#define VGT_DEBUG_REG33__ring2_in_sync_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG33__ring2_pipe1_dr_MASK 0x00000020L +#define VGT_DEBUG_REG33__ring2_pipe1_dr__SHIFT 0x00000005 +#define VGT_DEBUG_REG33__ring2_valid_p2_MASK 0x00400000L +#define VGT_DEBUG_REG33__ring2_valid_p2__SHIFT 0x00000016 +#define VGT_DEBUG_REG33__ring3_in_sync_q_MASK 0x00002000L +#define VGT_DEBUG_REG33__ring3_in_sync_q__SHIFT 0x0000000d +#define VGT_DEBUG_REG33__ring3_pipe1_dr_MASK 0x00000002L +#define VGT_DEBUG_REG33__ring3_pipe1_dr__SHIFT 0x00000001 +#define VGT_DEBUG_REG33__ring3_valid_p2_MASK 0x00200000L +#define VGT_DEBUG_REG33__ring3_valid_p2__SHIFT 0x00000015 +#define VGT_DEBUG_REG33__te11_out_vert_gs_en_MASK 0x10000000L +#define VGT_DEBUG_REG33__te11_out_vert_gs_en__SHIFT 0x0000001c +#define VGT_DEBUG_REG33__tess_topology_p0_q_MASK 0x0c000000L +#define VGT_DEBUG_REG33__tess_topology_p0_q__SHIFT 0x0000001a +#define VGT_DEBUG_REG33__tess_type_p0_q_MASK 0x03000000L +#define VGT_DEBUG_REG33__tess_type_p0_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG33__tm_te11_event_rtr_MASK 0x00004000L +#define VGT_DEBUG_REG33__tm_te11_event_rtr__SHIFT 0x0000000e +#define VGT_DEBUG_REG34__advance_inner_point_p1_MASK 0x00800000L +#define VGT_DEBUG_REG34__advance_inner_point_p1__SHIFT 0x00000017 +#define VGT_DEBUG_REG34__advance_outer_point_p1_MASK 0x00400000L +#define VGT_DEBUG_REG34__advance_outer_point_p1__SHIFT 0x00000016 +#define VGT_DEBUG_REG34__con_state_q_MASK 0x0000000fL +#define VGT_DEBUG_REG34__con_state_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG34__first_ring_of_patch_p0_q_MASK 0x00010000L +#define VGT_DEBUG_REG34__first_ring_of_patch_p0_q__SHIFT 0x00000010 +#define VGT_DEBUG_REG34__last_edge_of_outer_ring_p0_q_MASK 0x00040000L +#define VGT_DEBUG_REG34__last_edge_of_outer_ring_p0_q__SHIFT 0x00000012 +#define VGT_DEBUG_REG34__last_point_of_inner_ring_p1_MASK 0x00100000L +#define VGT_DEBUG_REG34__last_point_of_inner_ring_p1__SHIFT 0x00000014 +#define VGT_DEBUG_REG34__last_point_of_outer_ring_p1_MASK 0x00080000L +#define VGT_DEBUG_REG34__last_point_of_outer_ring_p1__SHIFT 0x00000013 +#define VGT_DEBUG_REG34__last_ring_of_patch_p0_q_MASK 0x00020000L +#define VGT_DEBUG_REG34__last_ring_of_patch_p0_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG34__next_ring_is_rect_p0_q_MASK 0x01000000L +#define VGT_DEBUG_REG34__next_ring_is_rect_p0_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q_MASK 0x00200000L +#define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q__SHIFT 0x00000015 +#define VGT_DEBUG_REG34__outer_parity_p0_q_MASK 0x00004000L +#define VGT_DEBUG_REG34__outer_parity_p0_q__SHIFT 0x0000000e +#define VGT_DEBUG_REG34__parallel_parity_p0_q_MASK 0x00008000L +#define VGT_DEBUG_REG34__parallel_parity_p0_q__SHIFT 0x0000000f +#define VGT_DEBUG_REG34__pipe0_edge_dr_MASK 0x00000200L +#define VGT_DEBUG_REG34__pipe0_edge_dr__SHIFT 0x00000009 +#define VGT_DEBUG_REG34__pipe0_edge_rtr_MASK 0x00001000L +#define VGT_DEBUG_REG34__pipe0_edge_rtr__SHIFT 0x0000000c +#define VGT_DEBUG_REG34__pipe0_patch_dr_MASK 0x00000100L +#define VGT_DEBUG_REG34__pipe0_patch_dr__SHIFT 0x00000008 +#define VGT_DEBUG_REG34__pipe0_patch_rtr_MASK 0x00000800L +#define VGT_DEBUG_REG34__pipe0_patch_rtr__SHIFT 0x0000000b +#define VGT_DEBUG_REG34__pipe1_dr_MASK 0x00000400L +#define VGT_DEBUG_REG34__pipe1_dr__SHIFT 0x0000000a +#define VGT_DEBUG_REG34__pipe1_edge_rtr_MASK 0x40000000L +#define VGT_DEBUG_REG34__pipe1_edge_rtr__SHIFT 0x0000001e +#define VGT_DEBUG_REG34__pipe1_inner1_rtr_MASK 0x08000000L +#define VGT_DEBUG_REG34__pipe1_inner1_rtr__SHIFT 0x0000001b +#define VGT_DEBUG_REG34__pipe1_inner2_rtr_MASK 0x10000000L +#define VGT_DEBUG_REG34__pipe1_inner2_rtr__SHIFT 0x0000001c +#define VGT_DEBUG_REG34__pipe1_outer1_rtr_MASK 0x02000000L +#define VGT_DEBUG_REG34__pipe1_outer1_rtr__SHIFT 0x00000019 +#define VGT_DEBUG_REG34__pipe1_outer2_rtr_MASK 0x04000000L +#define VGT_DEBUG_REG34__pipe1_outer2_rtr__SHIFT 0x0000001a +#define VGT_DEBUG_REG34__pipe1_patch_rtr_MASK 0x20000000L +#define VGT_DEBUG_REG34__pipe1_patch_rtr__SHIFT 0x0000001d +#define VGT_DEBUG_REG34__pipe1_rtr_MASK 0x00002000L +#define VGT_DEBUG_REG34__pipe1_rtr__SHIFT 0x0000000d +#define VGT_DEBUG_REG34__process_tri_1st_2nd_half_p0_q_MASK 0x00000040L +#define VGT_DEBUG_REG34__process_tri_1st_2nd_half_p0_q__SHIFT 0x00000006 +#define VGT_DEBUG_REG34__process_tri_center_poly_p0_q_MASK 0x00000080L +#define VGT_DEBUG_REG34__process_tri_center_poly_p0_q__SHIFT 0x00000007 +#define VGT_DEBUG_REG34__process_tri_middle_p0_q_MASK 0x00000020L +#define VGT_DEBUG_REG34__process_tri_middle_p0_q__SHIFT 0x00000005 +#define VGT_DEBUG_REG34__second_cycle_q_MASK 0x00000010L +#define VGT_DEBUG_REG34__second_cycle_q__SHIFT 0x00000004 +#define VGT_DEBUG_REG34__use_stored_inner_q_ring1_MASK 0x80000000L +#define VGT_DEBUG_REG34__use_stored_inner_q_ring1__SHIFT 0x0000001f +#define VGT_DEBUG_REG35__event_flag_p1_q_MASK 0x00040000L +#define VGT_DEBUG_REG35__event_flag_p1_q__SHIFT 0x00000012 +#define VGT_DEBUG_REG35__first_req_of_tg_p1_q_MASK 0x10000000L +#define VGT_DEBUG_REG35__first_req_of_tg_p1_q__SHIFT 0x0000001c +#define VGT_DEBUG_REG35__last_req_of_tg_p2_MASK 0x00000800L +#define VGT_DEBUG_REG35__last_req_of_tg_p2__SHIFT 0x0000000b +#define VGT_DEBUG_REG35__null_flag_p1_q_MASK 0x00080000L +#define VGT_DEBUG_REG35__null_flag_p1_q__SHIFT 0x00000013 +#define VGT_DEBUG_REG35__pipe0_dr_MASK 0x00000001L +#define VGT_DEBUG_REG35__pipe0_dr__SHIFT 0x00000000 +#define VGT_DEBUG_REG35__pipe0_rtr_MASK 0x00000004L +#define VGT_DEBUG_REG35__pipe0_rtr__SHIFT 0x00000002 +#define VGT_DEBUG_REG35__pipe1_dr_MASK 0x00000002L +#define VGT_DEBUG_REG35__pipe1_dr__SHIFT 0x00000001 +#define VGT_DEBUG_REG35__pipe1_rtr_MASK 0x00000008L +#define VGT_DEBUG_REG35__pipe1_rtr__SHIFT 0x00000003 +#define VGT_DEBUG_REG35__second_tf_ret_data_q_MASK 0x08000000L +#define VGT_DEBUG_REG35__second_tf_ret_data_q__SHIFT 0x0000001b +#define VGT_DEBUG_REG35__spi_vgt_hs_done_cnt_q_MASK 0x0003f000L +#define VGT_DEBUG_REG35__spi_vgt_hs_done_cnt_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG35__TC_VGT_rdret_data_in_MASK 0x80000000L +#define VGT_DEBUG_REG35__TC_VGT_rdret_data_in__SHIFT 0x0000001f +#define VGT_DEBUG_REG35__tf_data_fifo_busy_q_MASK 0x00000040L +#define VGT_DEBUG_REG35__tf_data_fifo_busy_q__SHIFT 0x00000006 +#define VGT_DEBUG_REG35__tf_data_fifo_cnt_q_MASK 0x07f00000L +#define VGT_DEBUG_REG35__tf_data_fifo_cnt_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG35__tf_data_fifo_rtr_q_MASK 0x00000080L +#define VGT_DEBUG_REG35__tf_data_fifo_rtr_q__SHIFT 0x00000007 +#define VGT_DEBUG_REG35__tfreq_tg_fifo_empty_MASK 0x00000010L +#define VGT_DEBUG_REG35__tfreq_tg_fifo_empty__SHIFT 0x00000004 +#define VGT_DEBUG_REG35__tfreq_tg_fifo_full_MASK 0x00000020L +#define VGT_DEBUG_REG35__tfreq_tg_fifo_full__SHIFT 0x00000005 +#define VGT_DEBUG_REG35__tf_skid_fifo_empty_MASK 0x00000100L +#define VGT_DEBUG_REG35__tf_skid_fifo_empty__SHIFT 0x00000008 +#define VGT_DEBUG_REG35__tf_skid_fifo_full_MASK 0x00000200L +#define VGT_DEBUG_REG35__tf_skid_fifo_full__SHIFT 0x00000009 +#define VGT_DEBUG_REG35__VGT_TC_rdnfo_stall_out_MASK 0x40000000L +#define VGT_DEBUG_REG35__VGT_TC_rdnfo_stall_out__SHIFT 0x0000001e +#define VGT_DEBUG_REG35__vgt_tc_rdreq_rtr_q_MASK 0x00000400L +#define VGT_DEBUG_REG35__vgt_tc_rdreq_rtr_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG35__VGT_TC_rdreq_send_out_MASK 0x20000000L +#define VGT_DEBUG_REG35__VGT_TC_rdreq_send_out__SHIFT 0x0000001d +#define VGT_DEBUG_REG3__hsWaveRelInd_MASK 0xfc000000L +#define VGT_DEBUG_REG3__hsWaveRelInd__SHIFT 0x0000001a +#define VGT_DEBUG_REG3__lsPatchCnt_MASK 0x03fc0000L +#define VGT_DEBUG_REG3__lsPatchCnt__SHIFT 0x00000012 +#define VGT_DEBUG_REG3__lsTgRelInd_MASK 0x00000fffL +#define VGT_DEBUG_REG3__lsTgRelInd__SHIFT 0x00000000 +#define VGT_DEBUG_REG3__lsWaveRelInd_MASK 0x0003f000L +#define VGT_DEBUG_REG3__lsWaveRelInd__SHIFT 0x0000000c +#define VGT_DEBUG_REG4__hsCpCnt_MASK 0x1f000000L +#define VGT_DEBUG_REG4__hsCpCnt__SHIFT 0x00000018 +#define VGT_DEBUG_REG4__hsFwaveFlag_MASK 0x40000000L +#define VGT_DEBUG_REG4__hsFwaveFlag__SHIFT 0x0000001e +#define VGT_DEBUG_REG4__hsPatchCnt_MASK 0x000000ffL +#define VGT_DEBUG_REG4__hsPatchCnt__SHIFT 0x00000000 +#define VGT_DEBUG_REG4__hsPrimId_15_0_MASK 0x00ffff00L +#define VGT_DEBUG_REG4__hsPrimId_15_0__SHIFT 0x00000008 +#define VGT_DEBUG_REG4__hsWaveSendFlush_MASK 0x20000000L +#define VGT_DEBUG_REG4__hsWaveSendFlush__SHIFT 0x0000001d +#define VGT_DEBUG_REG4__SPARE_MASK 0xffffffffL +#define VGT_DEBUG_REG4__SPARE__SHIFT 0x00000000 +#define VGT_DEBUG_REG5__hsVertCreditCnt_0_MASK 0x0000f800L +#define VGT_DEBUG_REG5__hsVertCreditCnt_0__SHIFT 0x0000000b +#define VGT_DEBUG_REG5__hsWaveCreditCnt_0_MASK 0x000000f8L +#define VGT_DEBUG_REG5__hsWaveCreditCnt_0__SHIFT 0x00000003 +#define VGT_DEBUG_REG5__lsVertCreditCnt_0_MASK 0xf8000000L +#define VGT_DEBUG_REG5__lsVertCreditCnt_0__SHIFT 0x0000001b +#define VGT_DEBUG_REG5__lsWaveCreditCnt_0_MASK 0x00f80000L +#define VGT_DEBUG_REG5__lsWaveCreditCnt_0__SHIFT 0x00000013 +#define VGT_DEBUG_REG5__SPARE1_MASK 0x07000000L +#define VGT_DEBUG_REG5__SPARE1__SHIFT 0x00000018 +#define VGT_DEBUG_REG5__SPARE2_MASK 0x00070000L +#define VGT_DEBUG_REG5__SPARE2__SHIFT 0x00000010 +#define VGT_DEBUG_REG5__SPARE3_MASK 0x00000700L +#define VGT_DEBUG_REG5__SPARE3__SHIFT 0x00000008 +#define VGT_DEBUG_REG5__SPARE4_MASK 0x00000007L +#define VGT_DEBUG_REG5__SPARE4__SHIFT 0x00000000 +#define VGT_DEBUG_REG6__debug_BASE_MASK 0x0000ffffL +#define VGT_DEBUG_REG6__debug_BASE__SHIFT 0x00000000 +#define VGT_DEBUG_REG6__debug_SIZE_MASK 0xffff0000L +#define VGT_DEBUG_REG6__debug_SIZE__SHIFT 0x00000010 +#define VGT_DEBUG_REG7__debug_tfmmFifoEmpty_MASK 0x00000001L +#define VGT_DEBUG_REG7__debug_tfmmFifoEmpty__SHIFT 0x00000000 +#define VGT_DEBUG_REG7__debug_tfmmFifoFull_MASK 0x00000002L +#define VGT_DEBUG_REG7__debug_tfmmFifoFull__SHIFT 0x00000001 +#define VGT_DEBUG_REG7__hs_pipe0_dr_MASK 0x00000004L +#define VGT_DEBUG_REG7__hs_pipe0_dr__SHIFT 0x00000002 +#define VGT_DEBUG_REG7__hs_pipe0_rtr_MASK 0x00000008L +#define VGT_DEBUG_REG7__hs_pipe0_rtr__SHIFT 0x00000003 +#define VGT_DEBUG_REG7__hs_pipe1_rtr_MASK 0x00000010L +#define VGT_DEBUG_REG7__hs_pipe1_rtr__SHIFT 0x00000004 +#define VGT_DEBUG_REG7__SPARE_MASK 0x0000ffe0L +#define VGT_DEBUG_REG7__SPARE__SHIFT 0x00000005 +#define VGT_DEBUG_REG7__TF_addr_MASK 0xffff0000L +#define VGT_DEBUG_REG7__TF_addr__SHIFT 0x00000010 +#define VGT_DEBUG_REG8__es_gs_rtr_MASK 0x00004000L +#define VGT_DEBUG_REG8__es_gs_rtr__SHIFT 0x0000000e +#define VGT_DEBUG_REG8__gs_event_fifo_empty_MASK 0x02000000L +#define VGT_DEBUG_REG8__gs_event_fifo_empty__SHIFT 0x00000019 +#define VGT_DEBUG_REG8__gs_event_fifo_rtr_MASK 0x00008000L +#define VGT_DEBUG_REG8__gs_event_fifo_rtr__SHIFT 0x0000000f +#define VGT_DEBUG_REG8__gsprim_buff_empty_q_MASK 0x04000000L +#define VGT_DEBUG_REG8__gsprim_buff_empty_q__SHIFT 0x0000001a +#define VGT_DEBUG_REG8__gsprim_buff_full_q_MASK 0x08000000L +#define VGT_DEBUG_REG8__gsprim_buff_full_q__SHIFT 0x0000001b +#define VGT_DEBUG_REG8__gs_tbl_r3_rtr_MASK 0x00020000L +#define VGT_DEBUG_REG8__gs_tbl_r3_rtr__SHIFT 0x00000011 +#define VGT_DEBUG_REG8__gs_tbl_valid_r3_q_MASK 0x00000020L +#define VGT_DEBUG_REG8__gs_tbl_valid_r3_q__SHIFT 0x00000005 +#define VGT_DEBUG_REG8__hold_for_es_flush_MASK 0x01000000L +#define VGT_DEBUG_REG8__hold_for_es_flush__SHIFT 0x00000018 +#define VGT_DEBUG_REG8__prim_skid_fifo_empty_MASK 0x00040000L +#define VGT_DEBUG_REG8__prim_skid_fifo_empty__SHIFT 0x00000012 +#define VGT_DEBUG_REG8__r0_rtr_MASK 0x00000400L +#define VGT_DEBUG_REG8__r0_rtr__SHIFT 0x0000000a +#define VGT_DEBUG_REG8__r1_inst_rtr_MASK 0x00000004L +#define VGT_DEBUG_REG8__r1_inst_rtr__SHIFT 0x00000002 +#define VGT_DEBUG_REG8__r1_rtr_MASK 0x00000800L +#define VGT_DEBUG_REG8__r1_rtr__SHIFT 0x0000000b +#define VGT_DEBUG_REG8__r2_indx_rtr_MASK 0x00001000L +#define VGT_DEBUG_REG8__r2_indx_rtr__SHIFT 0x0000000c +#define VGT_DEBUG_REG8__r2_no_bp_rtr_MASK 0x00800000L +#define VGT_DEBUG_REG8__r2_no_bp_rtr__SHIFT 0x00000017 +#define VGT_DEBUG_REG8__r2_rtr_MASK 0x00002000L +#define VGT_DEBUG_REG8__r2_rtr__SHIFT 0x0000000d +#define VGT_DEBUG_REG8__rcm_busy_q_MASK 0x00000001L +#define VGT_DEBUG_REG8__rcm_busy_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG8__rcm_noif_busy_q_MASK 0x00000002L +#define VGT_DEBUG_REG8__rcm_noif_busy_q__SHIFT 0x00000001 +#define VGT_DEBUG_REG8__spi_esvert_fifo_busy_q_MASK 0x00000010L +#define VGT_DEBUG_REG8__spi_esvert_fifo_busy_q__SHIFT 0x00000004 +#define VGT_DEBUG_REG8__spi_gsprim_fifo_busy_q_MASK 0x00000008L +#define VGT_DEBUG_REG8__spi_gsprim_fifo_busy_q__SHIFT 0x00000003 +#define VGT_DEBUG_REG8__te_prim_fifo_empty_MASK 0x10000000L +#define VGT_DEBUG_REG8__te_prim_fifo_empty__SHIFT 0x0000001c +#define VGT_DEBUG_REG8__te_prim_fifo_full_MASK 0x20000000L +#define VGT_DEBUG_REG8__te_prim_fifo_full__SHIFT 0x0000001d +#define VGT_DEBUG_REG8__te_vert_fifo_empty_MASK 0x40000000L +#define VGT_DEBUG_REG8__te_vert_fifo_empty__SHIFT 0x0000001e +#define VGT_DEBUG_REG8__te_vert_fifo_full_MASK 0x80000000L +#define VGT_DEBUG_REG8__te_vert_fifo_full__SHIFT 0x0000001f +#define VGT_DEBUG_REG8__tm_rcm_es_tbl_rtr_MASK 0x00200000L +#define VGT_DEBUG_REG8__tm_rcm_es_tbl_rtr__SHIFT 0x00000015 +#define VGT_DEBUG_REG8__tm_rcm_gs_event_rtr_MASK 0x00010000L +#define VGT_DEBUG_REG8__tm_rcm_gs_event_rtr__SHIFT 0x00000010 +#define VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr_MASK 0x00100000L +#define VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr__SHIFT 0x00000014 +#define VGT_DEBUG_REG8__valid_r0_q_MASK 0x00000040L +#define VGT_DEBUG_REG8__valid_r0_q__SHIFT 0x00000006 +#define VGT_DEBUG_REG8__valid_r1_q_MASK 0x00000080L +#define VGT_DEBUG_REG8__valid_r1_q__SHIFT 0x00000007 +#define VGT_DEBUG_REG8__valid_r2_MASK 0x00000100L +#define VGT_DEBUG_REG8__valid_r2_q_MASK 0x00000200L +#define VGT_DEBUG_REG8__valid_r2_q__SHIFT 0x00000009 +#define VGT_DEBUG_REG8__valid_r2__SHIFT 0x00000008 +#define VGT_DEBUG_REG8__VGT_SPI_esvert_rtr_q_MASK 0x00400000L +#define VGT_DEBUG_REG8__VGT_SPI_esvert_rtr_q__SHIFT 0x00000016 +#define VGT_DEBUG_REG8__VGT_SPI_gsprim_rtr_q_MASK 0x00080000L +#define VGT_DEBUG_REG8__VGT_SPI_gsprim_rtr_q__SHIFT 0x00000013 +#define VGT_DEBUG_REG9__eop_indx_r3_MASK 0x00000010L +#define VGT_DEBUG_REG9__eop_indx_r3__SHIFT 0x00000004 +#define VGT_DEBUG_REG9__eop_prim_r3_MASK 0x00000020L +#define VGT_DEBUG_REG9__eop_prim_r3__SHIFT 0x00000005 +#define VGT_DEBUG_REG9__es_eov_r3_MASK 0x00000040L +#define VGT_DEBUG_REG9__es_eov_r3__SHIFT 0x00000006 +#define VGT_DEBUG_REG9__es_per_gs_vert_cnt_r3_q_not_0_MASK 0x02000000L +#define VGT_DEBUG_REG9__es_per_gs_vert_cnt_r3_q_not_0__SHIFT 0x00000019 +#define VGT_DEBUG_REG9__es_tbl_state_r3_q_0_MASK 0x00000080L +#define VGT_DEBUG_REG9__es_tbl_state_r3_q_0__SHIFT 0x00000007 +#define VGT_DEBUG_REG9__gs_eov_r3_MASK 0x00000008L +#define VGT_DEBUG_REG9__gs_eov_r3__SHIFT 0x00000003 +#define VGT_DEBUG_REG9__gs_instancing_state_q_MASK 0x01000000L +#define VGT_DEBUG_REG9__gs_instancing_state_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG9__gs_pending_state_r3_q_MASK 0x00400000L +#define VGT_DEBUG_REG9__gs_pending_state_r3_q__SHIFT 0x00000016 +#define VGT_DEBUG_REG9__gs_prim_per_es_ctr_r3_q_not_0_MASK 0x04000000L +#define VGT_DEBUG_REG9__gs_prim_per_es_ctr_r3_q_not_0__SHIFT 0x0000001a +#define VGT_DEBUG_REG9__gs_tbl_eop_r3_q_MASK 0x00040000L +#define VGT_DEBUG_REG9__gs_tbl_eop_r3_q__SHIFT 0x00000012 +#define VGT_DEBUG_REG9__gs_tbl_num_es_per_gs_r3_q_not_0_MASK 0x00000400L +#define VGT_DEBUG_REG9__gs_tbl_num_es_per_gs_r3_q_not_0__SHIFT 0x0000000a +#define VGT_DEBUG_REG9__gs_tbl_prim_cnt_r3_q_MASK 0x0003f800L +#define VGT_DEBUG_REG9__gs_tbl_prim_cnt_r3_q__SHIFT 0x0000000b +#define VGT_DEBUG_REG9__gs_tbl_state_r3_q_MASK 0x00380000L +#define VGT_DEBUG_REG9__gs_tbl_state_r3_q__SHIFT 0x00000013 +#define VGT_DEBUG_REG9__indices_to_send_r2_q_MASK 0x00000003L +#define VGT_DEBUG_REG9__indices_to_send_r2_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG9__invalidate_rb_roll_over_q_MASK 0x00800000L +#define VGT_DEBUG_REG9__invalidate_rb_roll_over_q__SHIFT 0x00000017 +#define VGT_DEBUG_REG9__off_chip_hs_r2_q_MASK 0x80000000L +#define VGT_DEBUG_REG9__off_chip_hs_r2_q__SHIFT 0x0000001f +#define VGT_DEBUG_REG9__pending_es_flush_r3_MASK 0x00000200L +#define VGT_DEBUG_REG9__pending_es_flush_r3__SHIFT 0x00000009 +#define VGT_DEBUG_REG9__pending_es_send_r3_q_MASK 0x00000100L +#define VGT_DEBUG_REG9__pending_es_send_r3_q__SHIFT 0x00000008 +#define VGT_DEBUG_REG9__pre_r0_rtr_MASK 0x08000000L +#define VGT_DEBUG_REG9__pre_r0_rtr__SHIFT 0x0000001b +#define VGT_DEBUG_REG9__SPARE0_MASK 0x40000000L +#define VGT_DEBUG_REG9__SPARE0__SHIFT 0x0000001e +#define VGT_DEBUG_REG9__valid_indices_r3_MASK 0x00000004L +#define VGT_DEBUG_REG9__valid_indices_r3__SHIFT 0x00000002 +#define VGT_DEBUG_REG9__valid_pre_r0_q_MASK 0x20000000L +#define VGT_DEBUG_REG9__valid_pre_r0_q__SHIFT 0x0000001d +#define VGT_DEBUG_REG9__valid_r3_q_MASK 0x10000000L +#define VGT_DEBUG_REG9__valid_r3_q__SHIFT 0x0000001c +#define VGT_DMA_BASE__BASE_ADDR_MASK 0xffffffffL +#define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x00000000 +#define VGT_DMA_BASE_HI__BASE_ADDR_MASK 0x000000ffL +#define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT 0x00000000 +#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x000001ffL +#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x00000000 +#define VGT_DMA_INDEX_TYPE__ATC_MASK 0x00000100L +#define VGT_DMA_INDEX_TYPE__ATC__SHIFT 0x00000008 +#define VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK 0x00000030L +#define VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT 0x00000004 +#define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L +#define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT 0x00000000 +#define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK 0x00000200L +#define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT 0x00000009 +#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK 0x000000c0L +#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT 0x00000006 +#define VGT_DMA_INDEX_TYPE__REQ_PATH_MASK 0x00000400L +#define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT 0x0000000a +#define VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK 0x0000000cL +#define VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT 0x00000002 +#define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK 0xffffffffL +#define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT 0x00000000 +#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK 0xffffffffL +#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x00000000 +#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x0000003fL +#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x00000000 +#define VGT_DMA_SIZE__NUM_INDICES_MASK 0xffffffffL +#define VGT_DMA_SIZE__NUM_INDICES__SHIFT 0x00000000 +#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x0000003fL +#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x00000000 +#define VGT_DRAW_INITIATOR__MAJOR_MODE_MASK 0x0000000cL +#define VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT 0x00000002 +#define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x00000020L +#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x00000005 +#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x00000003L +#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x00000000 +#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK 0x00000010L +#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT 0x00000004 +#define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK 0x00000040L +#define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT 0x00000006 +#define VGT_ENHANCE__MISC_MASK 0xffffffffL +#define VGT_ENHANCE__MISC__SHIFT 0x00000000 +#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007fffL +#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x00000000 +#define VGT_ESGS_RING_SIZE__MEM_SIZE_MASK 0xffffffffL +#define VGT_ESGS_RING_SIZE__MEM_SIZE__SHIFT 0x00000000 +#define VGT_ES_PER_GS__ES_PER_GS_MASK 0x000007ffL +#define VGT_ES_PER_GS__ES_PER_GS__SHIFT 0x00000000 +#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK 0x0fffffffL +#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT 0x00000000 +#define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK 0x07fc0000L +#define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0x00000012 +#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003fL +#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x00000000 +#define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x08000000L +#define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x0000001b +#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK 0x003fff00L +#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT 0x00000008 +#define VGT_FIFO_DEPTHS__RESERVED_0_MASK 0x00000080L +#define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT 0x00000007 +#define VGT_FIFO_DEPTHS__RESERVED_1_MASK 0xffc00000L +#define VGT_FIFO_DEPTHS__RESERVED_1__SHIFT 0x00000016 +#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK 0x0000007fL +#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT 0x00000000 +#define VGT_GROUP_DECR__DECR_MASK 0x0000000fL +#define VGT_GROUP_DECR__DECR__SHIFT 0x00000000 +#define VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK 0x0000000fL +#define VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT 0x00000000 +#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK 0x00070000L +#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT 0x00000010 +#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK 0x0000001fL +#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT 0x00000000 +#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK 0x00004000L +#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT 0x0000000e +#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK 0x00008000L +#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT 0x0000000f +#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK 0x00000008L +#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT 0x00000003 +#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK 0x00000001L +#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT 0x00000000 +#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK 0x00000002L +#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT 0x00000001 +#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK 0x00000004L +#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT 0x00000002 +#define VGT_GROUP_VECT_0_CNTL__SHIFT_MASK 0x00ff0000L +#define VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT 0x00000010 +#define VGT_GROUP_VECT_0_CNTL__STRIDE_MASK 0x0000ff00L +#define VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT 0x00000008 +#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK 0x0f000000L +#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT 0x00000018 +#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK 0xf0000000L +#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT 0x0000001c +#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK 0x0000000fL +#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT 0x00000000 +#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK 0x000000f0L +#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT 0x00000004 +#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK 0x00000f00L +#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT 0x00000008 +#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK 0x0000f000L +#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT 0x0000000c +#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK 0x000f0000L +#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT 0x00000010 +#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK 0x00f00000L +#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT 0x00000014 +#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK 0x00000008L +#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT 0x00000003 +#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK 0x00000001L +#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT 0x00000000 +#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK 0x00000002L +#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT 0x00000001 +#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK 0x00000004L +#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT 0x00000002 +#define VGT_GROUP_VECT_1_CNTL__SHIFT_MASK 0x00ff0000L +#define VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT 0x00000010 +#define VGT_GROUP_VECT_1_CNTL__STRIDE_MASK 0x0000ff00L +#define VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT 0x00000008 +#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK 0x0f000000L +#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT 0x00000018 +#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK 0xf0000000L +#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT 0x0000001c +#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK 0x0000000fL +#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT 0x00000000 +#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK 0x000000f0L +#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT 0x00000004 +#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK 0x00000f00L +#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT 0x00000008 +#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK 0x0000f000L +#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT 0x0000000c +#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK 0x000f0000L +#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT 0x00000010 +#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK 0x00f00000L +#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT 0x00000014 +#define VGT_GS_INSTANCE_CNT__CNT_MASK 0x000001fcL +#define VGT_GS_INSTANCE_CNT__CNT__SHIFT 0x00000002 +#define VGT_GS_INSTANCE_CNT__ENABLE_MASK 0x00000001L +#define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT 0x00000000 +#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK 0x000007ffL +#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT 0x00000000 +#define VGT_GS_MODE__COMPUTE_MODE_MASK 0x00004000L +#define VGT_GS_MODE__COMPUTE_MODE__SHIFT 0x0000000e +#define VGT_GS_MODE__CUT_MODE_MASK 0x00000030L +#define VGT_GS_MODE__CUT_MODE__SHIFT 0x00000004 +#define VGT_GS_MODE__ELEMENT_INFO_EN_MASK 0x00010000L +#define VGT_GS_MODE__ELEMENT_INFO_EN__SHIFT 0x00000010 +#define VGT_GS_MODE__ES_PASSTHRU_MASK 0x00002000L +#define VGT_GS_MODE__ES_PASSTHRU__SHIFT 0x0000000d +#define VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK 0x00080000L +#define VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT 0x00000013 +#define VGT_GS_MODE__FAST_COMPUTE_MODE_MASK 0x00008000L +#define VGT_GS_MODE__FAST_COMPUTE_MODE__SHIFT 0x0000000f +#define VGT_GS_MODE__GS_C_PACK_EN_MASK 0x00000800L +#define VGT_GS_MODE__GS_C_PACK_EN__SHIFT 0x0000000b +#define VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK 0x00100000L +#define VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT 0x00000014 +#define VGT_GS_MODE__MODE_MASK 0x00000007L +#define VGT_GS_MODE__MODE__SHIFT 0x00000000 +#define VGT_GS_MODE__ONCHIP_MASK 0x00600000L +#define VGT_GS_MODE__ONCHIP__SHIFT 0x00000015 +#define VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK 0x00020000L +#define VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT 0x00000011 +#define VGT_GS_MODE__RESERVED_0_MASK 0x00000008L +#define VGT_GS_MODE__RESERVED_0__SHIFT 0x00000003 +#define VGT_GS_MODE__RESERVED_1_MASK 0x000007c0L +#define VGT_GS_MODE__RESERVED_1__SHIFT 0x00000006 +#define VGT_GS_MODE__RESERVED_2_MASK 0x00001000L +#define VGT_GS_MODE__RESERVED_2__SHIFT 0x0000000c +#define VGT_GS_MODE__SUPPRESS_CUTS_MASK 0x00040000L +#define VGT_GS_MODE__SUPPRESS_CUTS__SHIFT 0x00000012 +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK 0x00003f00L +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT 0x00000008 +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK 0x003f0000L +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT 0x00000010 +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK 0x0fc00000L +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT 0x00000016 +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK 0x0000003fL +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT 0x00000000 +#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK 0x80000000L +#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT 0x0000001f +#define VGT_GS_PER_ES__GS_PER_ES_MASK 0x000007ffL +#define VGT_GS_PER_ES__GS_PER_ES__SHIFT 0x00000000 +#define VGT_GS_PER_VS__GS_PER_VS_MASK 0x0000000fL +#define VGT_GS_PER_VS__GS_PER_VS__SHIFT 0x00000000 +#define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK 0x0000001fL +#define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT 0x00000000 +#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK 0x00007fffL +#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT 0x00000000 +#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK 0x00007fffL +#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT 0x00000000 +#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK 0x00007fffL +#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT 0x00000000 +#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK 0x00007fffL +#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT 0x00000000 +#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007fffL +#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x00000000 +#define VGT_GSVS_RING_OFFSET_1__OFFSET_MASK 0x00007fffL +#define VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT 0x00000000 +#define VGT_GSVS_RING_OFFSET_2__OFFSET_MASK 0x00007fffL +#define VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT 0x00000000 +#define VGT_GSVS_RING_OFFSET_3__OFFSET_MASK 0x00007fffL +#define VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT 0x00000000 +#define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xffffffffL +#define VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT 0x00000000 +#define VGT_HOS_CNTL__TESS_MODE_MASK 0x00000003L +#define VGT_HOS_CNTL__TESS_MODE__SHIFT 0x00000000 +#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK 0xffffffffL +#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT 0x00000000 +#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK 0xffffffffL +#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT 0x00000000 +#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK 0x000000ffL +#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT 0x00000000 +#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK 0x0000007fL +#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT 0x00000000 +#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK 0x00000600L +#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT 0x00000009 +#define VGT_IMMED_DATA__DATA_MASK 0xffffffffL +#define VGT_IMMED_DATA__DATA__SHIFT 0x00000000 +#define VGT_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L +#define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT 0x00000000 +#define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0xffffffffL +#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x00000000 +#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK 0xffffffffL +#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT 0x00000000 +#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK 0xffffffffL +#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT 0x00000000 +#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x00070000L +#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x00000010 +#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L +#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x00000000 +#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003f00L +#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x00000008 +#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK 0x000fc000L +#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT 0x0000000e +#define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK 0x000000ffL +#define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT 0x00000000 +#define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0xffffffffL +#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x00000000 +#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x00000003L +#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x00000000 +#define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0xffffffffL +#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x00000000 +#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK 0x00000001L +#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT 0x00000000 +#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xffffffffL +#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x00000000 +#define VGT_NUM_INDICES__NUM_INDICES_MASK 0xffffffffL +#define VGT_NUM_INDICES__NUM_INDICES__SHIFT 0x00000000 +#define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK 0xffffffffL +#define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x00000000 +#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x0000007fL +#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x00000000 +#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK 0x00000007L +#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT 0x00000000 +#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000L +#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x0000001c +#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0f000000L +#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x00000018 +#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003ffL +#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 +#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L +#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a +#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L +#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0f000000L +#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x00000018 +#define VGT_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L +#define VGT_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000ffc00L +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 +#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000L +#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x0000001c +#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0f000000L +#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x00000018 +#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003ffL +#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x00000000 +#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000ffc00L +#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0x0000000a +#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L +#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0f000000L +#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x00000018 +#define VGT_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L +#define VGT_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000ffc00L +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0x0000000a +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 +#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define VGT_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000L +#define VGT_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x0000001c +#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL +#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 +#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define VGT_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000L +#define VGT_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x0000001c +#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL +#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 +#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK_MASK 0x000000ffL +#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK__SHIFT 0x00000000 +#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK 0x00000002L +#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT 0x00000001 +#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK 0x00000001L +#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT 0x00000000 +#define VGT_PRIMITIVEID_RESET__VALUE_MASK 0xffffffffL +#define VGT_PRIMITIVEID_RESET__VALUE__SHIFT 0x00000000 +#define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003fL +#define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x00000000 +#define VGT_REUSE_OFF__REUSE_OFF_MASK 0x00000001L +#define VGT_REUSE_OFF__REUSE_OFF__SHIFT 0x00000000 +#define VGT_SHADER_STAGES_EN__DYNAMIC_HS_MASK 0x00000100L +#define VGT_SHADER_STAGES_EN__DYNAMIC_HS__SHIFT 0x00000008 +#define VGT_SHADER_STAGES_EN__ES_EN_MASK 0x00000018L +#define VGT_SHADER_STAGES_EN__ES_EN__SHIFT 0x00000003 +#define VGT_SHADER_STAGES_EN__GS_EN_MASK 0x00000020L +#define VGT_SHADER_STAGES_EN__GS_EN__SHIFT 0x00000005 +#define VGT_SHADER_STAGES_EN__HS_EN_MASK 0x00000004L +#define VGT_SHADER_STAGES_EN__HS_EN__SHIFT 0x00000002 +#define VGT_SHADER_STAGES_EN__LS_EN_MASK 0x00000003L +#define VGT_SHADER_STAGES_EN__LS_EN__SHIFT 0x00000000 +#define VGT_SHADER_STAGES_EN__VS_EN_MASK 0x000000c0L +#define VGT_SHADER_STAGES_EN__VS_EN__SHIFT 0x00000006 +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK 0x0000000fL +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT 0x00000000 +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK 0x000000f0L +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT 0x00000004 +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK 0x00000f00L +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT 0x00000008 +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK 0x0000f000L +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT 0x0000000c +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK 0xffffffffL +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT 0x00000000 +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK 0xffffffffL +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT 0x00000000 +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK 0xffffffffL +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT 0x00000000 +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK 0xffffffffL +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT 0x00000000 +#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK 0xffffffffL +#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT 0x00000000 +#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK 0xffffffffL +#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT 0x00000000 +#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK 0xffffffffL +#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT 0x00000000 +#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK 0xffffffffL +#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT 0x00000000 +#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK 0xffffffffL +#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT 0x00000000 +#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK 0xffffffffL +#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT 0x00000000 +#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK 0xffffffffL +#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT 0x00000000 +#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK 0xffffffffL +#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT 0x00000000 +#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK 0x00000070L +#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK 0x00000f00L +#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT 0x00000008 +#define VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT 0x00000004 +#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK 0x00000001L +#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT 0x00000000 +#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK 0x00000002L +#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT 0x00000001 +#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK 0x00000004L +#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT 0x00000002 +#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK 0x00000008L +#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT 0x00000003 +#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK 0x80000000L +#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT 0x0000001f +#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK 0xffffffffL +#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT 0x00000000 +#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK 0xffffffffL +#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT 0x00000000 +#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK 0x000001ffL +#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT 0x00000000 +#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK 0x000003ffL +#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT 0x00000000 +#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK 0x000003ffL +#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT 0x00000000 +#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK 0x000003ffL +#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT 0x00000000 +#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK 0x000003ffL +#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT 0x00000000 +#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK 0x00000080L +#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT 0x00000007 +#define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK 0x00000001L +#define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT 0x00000000 +#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK 0x0000007eL +#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT 0x00000001 +#define VGT_TF_MEMORY_BASE__BASE_MASK 0xffffffffL +#define VGT_TF_MEMORY_BASE__BASE__SHIFT 0x00000000 +#define VGT_TF_PARAM__DEPRECATED_MASK 0x00000200L +#define VGT_TF_PARAM__DEPRECATED__SHIFT 0x00000009 +#define VGT_TF_PARAM__DISABLE_DONUTS_MASK 0x00004000L +#define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT 0x0000000e +#define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD_MASK 0x00003c00L +#define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD__SHIFT 0x0000000a +#define VGT_TF_PARAM__PARTITIONING_MASK 0x0000001cL +#define VGT_TF_PARAM__PARTITIONING__SHIFT 0x00000002 +#define VGT_TF_PARAM__RDREQ_POLICY_MASK 0x00018000L +#define VGT_TF_PARAM__RDREQ_POLICY__SHIFT 0x0000000f +#define VGT_TF_PARAM__RESERVED_REDUC_AXIS_MASK 0x00000100L +#define VGT_TF_PARAM__RESERVED_REDUC_AXIS__SHIFT 0x00000008 +#define VGT_TF_PARAM__TOPOLOGY_MASK 0x000000e0L +#define VGT_TF_PARAM__TOPOLOGY__SHIFT 0x00000005 +#define VGT_TF_PARAM__TYPE_MASK 0x00000003L +#define VGT_TF_PARAM__TYPE__SHIFT 0x00000000 +#define VGT_TF_RING_SIZE__SIZE_MASK 0x0000ffffL +#define VGT_TF_RING_SIZE__SIZE__SHIFT 0x00000000 +#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0x000000ffL +#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x00000000 +#define VGT_VTX_CNT_EN__VTX_CNT_EN_MASK 0x00000001L +#define VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT 0x00000000 +#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x000003ffL +#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x00000000 +#define WD_DEBUG_DATA__DATA_MASK 0xffffffffL +#define WD_DEBUG_DATA__DATA__SHIFT 0x00000000 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_d.h new file mode 100644 index 000000000000..dc4e5b93801d --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_d.h @@ -0,0 +1,1274 @@ +/* + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef GMC_6_0_D_H +#define GMC_6_0_D_H + +#define ixMC_IO_DEBUG_ACMD_CLKSEL_D0 0x00CE +#define ixMC_IO_DEBUG_ACMD_CLKSEL_D1 0x00DE +#define ixMC_IO_DEBUG_ACMD_MISC_D0 0x00AE +#define ixMC_IO_DEBUG_ACMD_MISC_D1 0x00BE +#define ixMC_IO_DEBUG_ACMD_OFSCAL_D0 0x00EE +#define ixMC_IO_DEBUG_ACMD_OFSCAL_D1 0x00FE +#define ixMC_IO_DEBUG_ACMD_RXPHASE_D0 0x010E +#define ixMC_IO_DEBUG_ACMD_RXPHASE_D1 0x011E +#define ixMC_IO_DEBUG_ACMD_TXBST_PD_D0 0x018E +#define ixMC_IO_DEBUG_ACMD_TXBST_PD_D1 0x019E +#define ixMC_IO_DEBUG_ACMD_TXBST_PU_D0 0x01AE +#define ixMC_IO_DEBUG_ACMD_TXBST_PU_D1 0x01BE +#define ixMC_IO_DEBUG_ACMD_TXPHASE_D0 0x012E +#define ixMC_IO_DEBUG_ACMD_TXPHASE_D1 0x013E +#define ixMC_IO_DEBUG_ACMD_TXSLF_D0 0x016E +#define ixMC_IO_DEBUG_ACMD_TXSLF_D1 0x017E +#define ixMC_IO_DEBUG_ADDRH_CLKSEL_D0 0x00CD +#define ixMC_IO_DEBUG_ADDRH_CLKSEL_D1 0x00DD +#define ixMC_IO_DEBUG_ADDRH_MISC_D0 0x00AD +#define ixMC_IO_DEBUG_ADDRH_MISC_D1 0x00BD +#define ixMC_IO_DEBUG_ADDRH_RXPHASE_D0 0x010D +#define ixMC_IO_DEBUG_ADDRH_RXPHASE_D1 0x011D +#define ixMC_IO_DEBUG_ADDRH_TXBST_PD_D0 0x018D +#define ixMC_IO_DEBUG_ADDRH_TXBST_PD_D1 0x019D +#define ixMC_IO_DEBUG_ADDRH_TXBST_PU_D0 0x01AD +#define ixMC_IO_DEBUG_ADDRH_TXBST_PU_D1 0x01BD +#define ixMC_IO_DEBUG_ADDRH_TXPHASE_D0 0x012D +#define ixMC_IO_DEBUG_ADDRH_TXPHASE_D1 0x013D +#define ixMC_IO_DEBUG_ADDRH_TXSLF_D0 0x016D +#define ixMC_IO_DEBUG_ADDRH_TXSLF_D1 0x017D +#define ixMC_IO_DEBUG_ADDRL_CLKSEL_D0 0x00CC +#define ixMC_IO_DEBUG_ADDRL_CLKSEL_D1 0x00DC +#define ixMC_IO_DEBUG_ADDRL_MISC_D0 0x00AC +#define ixMC_IO_DEBUG_ADDRL_MISC_D1 0x00BC +#define ixMC_IO_DEBUG_ADDRL_RXPHASE_D0 0x010C +#define ixMC_IO_DEBUG_ADDRL_RXPHASE_D1 0x011C +#define ixMC_IO_DEBUG_ADDRL_TXBST_PD_D0 0x018C +#define ixMC_IO_DEBUG_ADDRL_TXBST_PD_D1 0x019C +#define ixMC_IO_DEBUG_ADDRL_TXBST_PU_D0 0x01AC +#define ixMC_IO_DEBUG_ADDRL_TXBST_PU_D1 0x01BC +#define ixMC_IO_DEBUG_ADDRL_TXPHASE_D0 0x012C +#define ixMC_IO_DEBUG_ADDRL_TXPHASE_D1 0x013C +#define ixMC_IO_DEBUG_ADDRL_TXSLF_D0 0x016C +#define ixMC_IO_DEBUG_ADDRL_TXSLF_D1 0x017C +#define ixMC_IO_DEBUG_CK_CLKSEL_D0 0x00CB +#define ixMC_IO_DEBUG_CK_CLKSEL_D1 0x00DB +#define ixMC_IO_DEBUG_CK_MISC_D0 0x00AB +#define ixMC_IO_DEBUG_CK_MISC_D1 0x00BB +#define ixMC_IO_DEBUG_CK_RXPHASE_D0 0x010B +#define ixMC_IO_DEBUG_CK_RXPHASE_D1 0x011B +#define ixMC_IO_DEBUG_CK_TXBST_PD_D0 0x018B +#define ixMC_IO_DEBUG_CK_TXBST_PD_D1 0x019B +#define ixMC_IO_DEBUG_CK_TXBST_PU_D0 0x01AB +#define ixMC_IO_DEBUG_CK_TXBST_PU_D1 0x01BB +#define ixMC_IO_DEBUG_CK_TXPHASE_D0 0x012B +#define ixMC_IO_DEBUG_CK_TXPHASE_D1 0x013B +#define ixMC_IO_DEBUG_CK_TXSLF_D0 0x016B +#define ixMC_IO_DEBUG_CK_TXSLF_D1 0x017B +#define ixMC_IO_DEBUG_CMD_CLKSEL_D0 0x00CF +#define ixMC_IO_DEBUG_CMD_CLKSEL_D1 0x00DF +#define ixMC_IO_DEBUG_CMD_MISC_D0 0x00AF +#define ixMC_IO_DEBUG_CMD_MISC_D1 0x00BF +#define ixMC_IO_DEBUG_CMD_OFSCAL_D0 0x00EF +#define ixMC_IO_DEBUG_CMD_OFSCAL_D1 0x00FF +#define ixMC_IO_DEBUG_CMD_RX_EQ_D0 0x01CF +#define ixMC_IO_DEBUG_CMD_RX_EQ_D1 0x01DF +#define ixMC_IO_DEBUG_CMD_RXPHASE_D0 0x010F +#define ixMC_IO_DEBUG_CMD_RXPHASE_D1 0x011F +#define ixMC_IO_DEBUG_CMD_TXBST_PD_D0 0x018F +#define ixMC_IO_DEBUG_CMD_TXBST_PD_D1 0x019F +#define ixMC_IO_DEBUG_CMD_TXBST_PU_D0 0x01AF +#define ixMC_IO_DEBUG_CMD_TXBST_PU_D1 0x01BF +#define ixMC_IO_DEBUG_CMD_TXPHASE_D0 0x012F +#define ixMC_IO_DEBUG_CMD_TXPHASE_D1 0x013F +#define ixMC_IO_DEBUG_CMD_TXSLF_D0 0x016F +#define ixMC_IO_DEBUG_CMD_TXSLF_D1 0x017F +#define ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D0 0x014F +#define ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D1 0x015F +#define ixMC_IO_DEBUG_DBI_CLKSEL_D0 0x00C8 +#define ixMC_IO_DEBUG_DBI_CLKSEL_D1 0x00D8 +#define ixMC_IO_DEBUG_DBI_MISC_D0 0x00A8 +#define ixMC_IO_DEBUG_DBI_MISC_D1 0x00B8 +#define ixMC_IO_DEBUG_DBI_OFSCAL_D0 0x00E8 +#define ixMC_IO_DEBUG_DBI_OFSCAL_D1 0x00F8 +#define ixMC_IO_DEBUG_DBI_RX_EQ_D0 0x01C8 +#define ixMC_IO_DEBUG_DBI_RX_EQ_D1 0x01D8 +#define ixMC_IO_DEBUG_DBI_RXPHASE_D0 0x0108 +#define ixMC_IO_DEBUG_DBI_RXPHASE_D1 0x0118 +#define ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D0 0x0148 +#define ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D1 0x0158 +#define ixMC_IO_DEBUG_DBI_TXBST_PD_D0 0x0188 +#define ixMC_IO_DEBUG_DBI_TXBST_PD_D1 0x0198 +#define ixMC_IO_DEBUG_DBI_TXBST_PU_D0 0x01A8 +#define ixMC_IO_DEBUG_DBI_TXBST_PU_D1 0x01B8 +#define ixMC_IO_DEBUG_DBI_TXPHASE_D0 0x0128 +#define ixMC_IO_DEBUG_DBI_TXPHASE_D1 0x0138 +#define ixMC_IO_DEBUG_DBI_TXSLF_D0 0x0168 +#define ixMC_IO_DEBUG_DBI_TXSLF_D1 0x0178 +#define ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D0 0x01CD +#define ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D1 0x01DD +#define ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D0 0x01CB +#define ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D1 0x01DB +#define ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D0 0x01CE +#define ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D1 0x01DE +#define ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D0 0x01CC +#define ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D1 0x01DC +#define ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D0 0x014B +#define ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D1 0x015B +#define ixMC_IO_DEBUG_DQB0H_CLKSEL_D0 0x00C1 +#define ixMC_IO_DEBUG_DQB0H_CLKSEL_D1 0x00D1 +#define ixMC_IO_DEBUG_DQB0H_MISC_D0 0x00A1 +#define ixMC_IO_DEBUG_DQB0H_MISC_D1 0x00B1 +#define ixMC_IO_DEBUG_DQB0H_OFSCAL_D0 0x00E1 +#define ixMC_IO_DEBUG_DQB0H_OFSCAL_D1 0x00F1 +#define ixMC_IO_DEBUG_DQB0H_RX_EQ_D0 0x01C1 +#define ixMC_IO_DEBUG_DQB0H_RX_EQ_D1 0x01D1 +#define ixMC_IO_DEBUG_DQB0H_RXPHASE_D0 0x0101 +#define ixMC_IO_DEBUG_DQB0H_RXPHASE_D1 0x0111 +#define ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0 0x0141 +#define ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1 0x0151 +#define ixMC_IO_DEBUG_DQB0H_TXBST_PD_D0 0x0181 +#define ixMC_IO_DEBUG_DQB0H_TXBST_PD_D1 0x0191 +#define ixMC_IO_DEBUG_DQB0H_TXBST_PU_D0 0x01A1 +#define ixMC_IO_DEBUG_DQB0H_TXBST_PU_D1 0x01B1 +#define ixMC_IO_DEBUG_DQB0H_TXPHASE_D0 0x0121 +#define ixMC_IO_DEBUG_DQB0H_TXPHASE_D1 0x0131 +#define ixMC_IO_DEBUG_DQB0H_TXSLF_D0 0x0161 +#define ixMC_IO_DEBUG_DQB0H_TXSLF_D1 0x0171 +#define ixMC_IO_DEBUG_DQB0L_CLKSEL_D0 0x00C0 +#define ixMC_IO_DEBUG_DQB0L_CLKSEL_D1 0x00D0 +#define ixMC_IO_DEBUG_DQB0L_MISC_D0 0x00A0 +#define ixMC_IO_DEBUG_DQB0L_MISC_D1 0x00B0 +#define ixMC_IO_DEBUG_DQB0L_OFSCAL_D0 0x00E0 +#define ixMC_IO_DEBUG_DQB0L_OFSCAL_D1 0x00F0 +#define ixMC_IO_DEBUG_DQB0L_RX_EQ_D0 0x01C0 +#define ixMC_IO_DEBUG_DQB0L_RX_EQ_D1 0x01D0 +#define ixMC_IO_DEBUG_DQB0L_RXPHASE_D0 0x0100 +#define ixMC_IO_DEBUG_DQB0L_RXPHASE_D1 0x0110 +#define ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0 0x0140 +#define ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1 0x0150 +#define ixMC_IO_DEBUG_DQB0L_TXBST_PD_D0 0x0180 +#define ixMC_IO_DEBUG_DQB0L_TXBST_PD_D1 0x0190 +#define ixMC_IO_DEBUG_DQB0L_TXBST_PU_D0 0x01A0 +#define ixMC_IO_DEBUG_DQB0L_TXBST_PU_D1 0x01B0 +#define ixMC_IO_DEBUG_DQB0L_TXPHASE_D0 0x0120 +#define ixMC_IO_DEBUG_DQB0L_TXPHASE_D1 0x0130 +#define ixMC_IO_DEBUG_DQB0L_TXSLF_D0 0x0160 +#define ixMC_IO_DEBUG_DQB0L_TXSLF_D1 0x0170 +#define ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D0 0x014C +#define ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D1 0x015C +#define ixMC_IO_DEBUG_DQB1H_CLKSEL_D0 0x00C3 +#define ixMC_IO_DEBUG_DQB1H_CLKSEL_D1 0x00D3 +#define ixMC_IO_DEBUG_DQB1H_MISC_D0 0x00A3 +#define ixMC_IO_DEBUG_DQB1H_MISC_D1 0x00B3 +#define ixMC_IO_DEBUG_DQB1H_OFSCAL_D0 0x00E3 +#define ixMC_IO_DEBUG_DQB1H_OFSCAL_D1 0x00F3 +#define ixMC_IO_DEBUG_DQB1H_RX_EQ_D0 0x01C3 +#define ixMC_IO_DEBUG_DQB1H_RX_EQ_D1 0x01D3 +#define ixMC_IO_DEBUG_DQB1H_RXPHASE_D0 0x0103 +#define ixMC_IO_DEBUG_DQB1H_RXPHASE_D1 0x0113 +#define ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0 0x0143 +#define ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1 0x0153 +#define ixMC_IO_DEBUG_DQB1H_TXBST_PD_D0 0x0183 +#define ixMC_IO_DEBUG_DQB1H_TXBST_PD_D1 0x0193 +#define ixMC_IO_DEBUG_DQB1H_TXBST_PU_D0 0x01A3 +#define ixMC_IO_DEBUG_DQB1H_TXBST_PU_D1 0x01B3 +#define ixMC_IO_DEBUG_DQB1H_TXPHASE_D0 0x0123 +#define ixMC_IO_DEBUG_DQB1H_TXPHASE_D1 0x0133 +#define ixMC_IO_DEBUG_DQB1H_TXSLF_D0 0x0163 +#define ixMC_IO_DEBUG_DQB1H_TXSLF_D1 0x0173 +#define ixMC_IO_DEBUG_DQB1L_CLKSEL_D0 0x00C2 +#define ixMC_IO_DEBUG_DQB1L_CLKSEL_D1 0x00D2 +#define ixMC_IO_DEBUG_DQB1L_MISC_D0 0x00A2 +#define ixMC_IO_DEBUG_DQB1L_MISC_D1 0x00B2 +#define ixMC_IO_DEBUG_DQB1L_OFSCAL_D0 0x00E2 +#define ixMC_IO_DEBUG_DQB1L_OFSCAL_D1 0x00F2 +#define ixMC_IO_DEBUG_DQB1L_RX_EQ_D0 0x01C2 +#define ixMC_IO_DEBUG_DQB1L_RX_EQ_D1 0x01D2 +#define ixMC_IO_DEBUG_DQB1L_RXPHASE_D0 0x0102 +#define ixMC_IO_DEBUG_DQB1L_RXPHASE_D1 0x0112 +#define ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0 0x0142 +#define ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1 0x0152 +#define ixMC_IO_DEBUG_DQB1L_TXBST_PD_D0 0x0182 +#define ixMC_IO_DEBUG_DQB1L_TXBST_PD_D1 0x0192 +#define ixMC_IO_DEBUG_DQB1L_TXBST_PU_D0 0x01A2 +#define ixMC_IO_DEBUG_DQB1L_TXBST_PU_D1 0x01B2 +#define ixMC_IO_DEBUG_DQB1L_TXPHASE_D0 0x0122 +#define ixMC_IO_DEBUG_DQB1L_TXPHASE_D1 0x0132 +#define ixMC_IO_DEBUG_DQB1L_TXSLF_D0 0x0162 +#define ixMC_IO_DEBUG_DQB1L_TXSLF_D1 0x0172 +#define ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D0 0x014D +#define ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D1 0x015D +#define ixMC_IO_DEBUG_DQB2H_CLKSEL_D0 0x00C5 +#define ixMC_IO_DEBUG_DQB2H_CLKSEL_D1 0x00D5 +#define ixMC_IO_DEBUG_DQB2H_MISC_D0 0x00A5 +#define ixMC_IO_DEBUG_DQB2H_MISC_D1 0x00B5 +#define ixMC_IO_DEBUG_DQB2H_OFSCAL_D0 0x00E5 +#define ixMC_IO_DEBUG_DQB2H_OFSCAL_D1 0x00F5 +#define ixMC_IO_DEBUG_DQB2H_RX_EQ_D0 0x01C5 +#define ixMC_IO_DEBUG_DQB2H_RX_EQ_D1 0x01D5 +#define ixMC_IO_DEBUG_DQB2H_RXPHASE_D0 0x0105 +#define ixMC_IO_DEBUG_DQB2H_RXPHASE_D1 0x0115 +#define ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0 0x0145 +#define ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1 0x0155 +#define ixMC_IO_DEBUG_DQB2H_TXBST_PD_D0 0x0185 +#define ixMC_IO_DEBUG_DQB2H_TXBST_PD_D1 0x0195 +#define ixMC_IO_DEBUG_DQB2H_TXBST_PU_D0 0x01A5 +#define ixMC_IO_DEBUG_DQB2H_TXBST_PU_D1 0x01B5 +#define ixMC_IO_DEBUG_DQB2H_TXPHASE_D0 0x0125 +#define ixMC_IO_DEBUG_DQB2H_TXPHASE_D1 0x0135 +#define ixMC_IO_DEBUG_DQB2H_TXSLF_D0 0x0165 +#define ixMC_IO_DEBUG_DQB2H_TXSLF_D1 0x0175 +#define ixMC_IO_DEBUG_DQB2L_CLKSEL_D0 0x00C4 +#define ixMC_IO_DEBUG_DQB2L_CLKSEL_D1 0x00D4 +#define ixMC_IO_DEBUG_DQB2L_MISC_D0 0x00A4 +#define ixMC_IO_DEBUG_DQB2L_MISC_D1 0x00B4 +#define ixMC_IO_DEBUG_DQB2L_OFSCAL_D0 0x00E4 +#define ixMC_IO_DEBUG_DQB2L_OFSCAL_D1 0x00F4 +#define ixMC_IO_DEBUG_DQB2L_RX_EQ_D0 0x01C4 +#define ixMC_IO_DEBUG_DQB2L_RX_EQ_D1 0x01D4 +#define ixMC_IO_DEBUG_DQB2L_RXPHASE_D0 0x0104 +#define ixMC_IO_DEBUG_DQB2L_RXPHASE_D1 0x0114 +#define ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0 0x0144 +#define ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1 0x0154 +#define ixMC_IO_DEBUG_DQB2L_TXBST_PD_D0 0x0184 +#define ixMC_IO_DEBUG_DQB2L_TXBST_PD_D1 0x0194 +#define ixMC_IO_DEBUG_DQB2L_TXBST_PU_D0 0x01A4 +#define ixMC_IO_DEBUG_DQB2L_TXBST_PU_D1 0x01B4 +#define ixMC_IO_DEBUG_DQB2L_TXPHASE_D0 0x0124 +#define ixMC_IO_DEBUG_DQB2L_TXPHASE_D1 0x0134 +#define ixMC_IO_DEBUG_DQB2L_TXSLF_D0 0x0164 +#define ixMC_IO_DEBUG_DQB2L_TXSLF_D1 0x0174 +#define ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D0 0x014E +#define ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D1 0x015E +#define ixMC_IO_DEBUG_DQB3H_CLKSEL_D0 0x00C7 +#define ixMC_IO_DEBUG_DQB3H_CLKSEL_D1 0x00D7 +#define ixMC_IO_DEBUG_DQB3H_MISC_D0 0x00A7 +#define ixMC_IO_DEBUG_DQB3H_MISC_D1 0x00B7 +#define ixMC_IO_DEBUG_DQB3H_OFSCAL_D0 0x00E7 +#define ixMC_IO_DEBUG_DQB3H_OFSCAL_D1 0x00F7 +#define ixMC_IO_DEBUG_DQB3H_RX_EQ_D0 0x01C7 +#define ixMC_IO_DEBUG_DQB3H_RX_EQ_D1 0x01D7 +#define ixMC_IO_DEBUG_DQB3H_RXPHASE_D0 0x0107 +#define ixMC_IO_DEBUG_DQB3H_RXPHASE_D1 0x0117 +#define ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0 0x0147 +#define ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1 0x0157 +#define ixMC_IO_DEBUG_DQB3H_TXBST_PD_D0 0x0187 +#define ixMC_IO_DEBUG_DQB3H_TXBST_PD_D1 0x0197 +#define ixMC_IO_DEBUG_DQB3H_TXBST_PU_D0 0x01A7 +#define ixMC_IO_DEBUG_DQB3H_TXBST_PU_D1 0x01B7 +#define ixMC_IO_DEBUG_DQB3H_TXPHASE_D0 0x0127 +#define ixMC_IO_DEBUG_DQB3H_TXPHASE_D1 0x0137 +#define ixMC_IO_DEBUG_DQB3H_TXSLF_D0 0x0167 +#define ixMC_IO_DEBUG_DQB3H_TXSLF_D1 0x0177 +#define ixMC_IO_DEBUG_DQB3L_CLKSEL_D0 0x00C6 +#define ixMC_IO_DEBUG_DQB3L_CLKSEL_D1 0x00D6 +#define ixMC_IO_DEBUG_DQB3L_MISC_D0 0x00A6 +#define ixMC_IO_DEBUG_DQB3L_MISC_D1 0x00B6 +#define ixMC_IO_DEBUG_DQB3L_OFSCAL_D0 0x00E6 +#define ixMC_IO_DEBUG_DQB3L_OFSCAL_D1 0x00F6 +#define ixMC_IO_DEBUG_DQB3L_RX_EQ_D0 0x01C6 +#define ixMC_IO_DEBUG_DQB3L_RX_EQ_D1 0x01D6 +#define ixMC_IO_DEBUG_DQB3L_RXPHASE_D0 0x0106 +#define ixMC_IO_DEBUG_DQB3L_RXPHASE_D1 0x0116 +#define ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0 0x0146 +#define ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1 0x0156 +#define ixMC_IO_DEBUG_DQB3L_TXBST_PD_D0 0x0186 +#define ixMC_IO_DEBUG_DQB3L_TXBST_PD_D1 0x0196 +#define ixMC_IO_DEBUG_DQB3L_TXBST_PU_D0 0x01A6 +#define ixMC_IO_DEBUG_DQB3L_TXBST_PU_D1 0x01B6 +#define ixMC_IO_DEBUG_DQB3L_TXPHASE_D0 0x0126 +#define ixMC_IO_DEBUG_DQB3L_TXPHASE_D1 0x0136 +#define ixMC_IO_DEBUG_DQB3L_TXSLF_D0 0x0166 +#define ixMC_IO_DEBUG_DQB3L_TXSLF_D1 0x0176 +#define ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D0 0x00ED +#define ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D1 0x00FD +#define ixMC_IO_DEBUG_EDC_CLKSEL_D0 0x00C9 +#define ixMC_IO_DEBUG_EDC_CLKSEL_D1 0x00D9 +#define ixMC_IO_DEBUG_EDC_MISC_D0 0x00A9 +#define ixMC_IO_DEBUG_EDC_MISC_D1 0x00B9 +#define ixMC_IO_DEBUG_EDC_OFSCAL_D0 0x00E9 +#define ixMC_IO_DEBUG_EDC_OFSCAL_D1 0x00F9 +#define ixMC_IO_DEBUG_EDC_RX_DYN_PM_D0 0x00EC +#define ixMC_IO_DEBUG_EDC_RX_DYN_PM_D1 0x00FC +#define ixMC_IO_DEBUG_EDC_RX_EQ_D0 0x01C9 +#define ixMC_IO_DEBUG_EDC_RX_EQ_D1 0x01D9 +#define ixMC_IO_DEBUG_EDC_RX_EQ_PM_D0 0x00EB +#define ixMC_IO_DEBUG_EDC_RX_EQ_PM_D1 0x00FB +#define ixMC_IO_DEBUG_EDC_RXPHASE_D0 0x0109 +#define ixMC_IO_DEBUG_EDC_RXPHASE_D1 0x0119 +#define ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D0 0x0149 +#define ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D1 0x0159 +#define ixMC_IO_DEBUG_EDC_TXBST_PD_D0 0x0189 +#define ixMC_IO_DEBUG_EDC_TXBST_PD_D1 0x0199 +#define ixMC_IO_DEBUG_EDC_TXBST_PU_D0 0x01A9 +#define ixMC_IO_DEBUG_EDC_TXBST_PU_D1 0x01B9 +#define ixMC_IO_DEBUG_EDC_TXPHASE_D0 0x0129 +#define ixMC_IO_DEBUG_EDC_TXPHASE_D1 0x0139 +#define ixMC_IO_DEBUG_EDC_TXSLF_D0 0x0169 +#define ixMC_IO_DEBUG_EDC_TXSLF_D1 0x0179 +#define ixMC_IO_DEBUG_UP_0 0x0000 +#define ixMC_IO_DEBUG_UP_100 0x0064 +#define ixMC_IO_DEBUG_UP_10 0x000A +#define ixMC_IO_DEBUG_UP_101 0x0065 +#define ixMC_IO_DEBUG_UP_102 0x0066 +#define ixMC_IO_DEBUG_UP_103 0x0067 +#define ixMC_IO_DEBUG_UP_104 0x0068 +#define ixMC_IO_DEBUG_UP_105 0x0069 +#define ixMC_IO_DEBUG_UP_106 0x006A +#define ixMC_IO_DEBUG_UP_107 0x006B +#define ixMC_IO_DEBUG_UP_108 0x006C +#define ixMC_IO_DEBUG_UP_109 0x006D +#define ixMC_IO_DEBUG_UP_1 0x0001 +#define ixMC_IO_DEBUG_UP_110 0x006E +#define ixMC_IO_DEBUG_UP_11 0x000B +#define ixMC_IO_DEBUG_UP_111 0x006F +#define ixMC_IO_DEBUG_UP_112 0x0070 +#define ixMC_IO_DEBUG_UP_113 0x0071 +#define ixMC_IO_DEBUG_UP_114 0x0072 +#define ixMC_IO_DEBUG_UP_115 0x0073 +#define ixMC_IO_DEBUG_UP_116 0x0074 +#define ixMC_IO_DEBUG_UP_117 0x0075 +#define ixMC_IO_DEBUG_UP_118 0x0076 +#define ixMC_IO_DEBUG_UP_119 0x0077 +#define ixMC_IO_DEBUG_UP_120 0x0078 +#define ixMC_IO_DEBUG_UP_12 0x000C +#define ixMC_IO_DEBUG_UP_121 0x0079 +#define ixMC_IO_DEBUG_UP_122 0x007A +#define ixMC_IO_DEBUG_UP_123 0x007B +#define ixMC_IO_DEBUG_UP_124 0x007C +#define ixMC_IO_DEBUG_UP_125 0x007D +#define ixMC_IO_DEBUG_UP_126 0x007E +#define ixMC_IO_DEBUG_UP_127 0x007F +#define ixMC_IO_DEBUG_UP_128 0x0080 +#define ixMC_IO_DEBUG_UP_129 0x0081 +#define ixMC_IO_DEBUG_UP_130 0x0082 +#define ixMC_IO_DEBUG_UP_13 0x000D +#define ixMC_IO_DEBUG_UP_131 0x0083 +#define ixMC_IO_DEBUG_UP_132 0x0084 +#define ixMC_IO_DEBUG_UP_133 0x0085 +#define ixMC_IO_DEBUG_UP_134 0x0086 +#define ixMC_IO_DEBUG_UP_135 0x0087 +#define ixMC_IO_DEBUG_UP_136 0x0088 +#define ixMC_IO_DEBUG_UP_137 0x0089 +#define ixMC_IO_DEBUG_UP_138 0x008A +#define ixMC_IO_DEBUG_UP_139 0x008B +#define ixMC_IO_DEBUG_UP_140 0x008C +#define ixMC_IO_DEBUG_UP_14 0x000E +#define ixMC_IO_DEBUG_UP_141 0x008D +#define ixMC_IO_DEBUG_UP_142 0x008E +#define ixMC_IO_DEBUG_UP_143 0x008F +#define ixMC_IO_DEBUG_UP_144 0x0090 +#define ixMC_IO_DEBUG_UP_145 0x0091 +#define ixMC_IO_DEBUG_UP_146 0x0092 +#define ixMC_IO_DEBUG_UP_147 0x0093 +#define ixMC_IO_DEBUG_UP_148 0x0094 +#define ixMC_IO_DEBUG_UP_149 0x0095 +#define ixMC_IO_DEBUG_UP_150 0x0096 +#define ixMC_IO_DEBUG_UP_15 0x000F +#define ixMC_IO_DEBUG_UP_151 0x0097 +#define ixMC_IO_DEBUG_UP_152 0x0098 +#define ixMC_IO_DEBUG_UP_153 0x0099 +#define ixMC_IO_DEBUG_UP_154 0x009A +#define ixMC_IO_DEBUG_UP_155 0x009B +#define ixMC_IO_DEBUG_UP_156 0x009C +#define ixMC_IO_DEBUG_UP_157 0x009D +#define ixMC_IO_DEBUG_UP_158 0x009E +#define ixMC_IO_DEBUG_UP_159 0x009F +#define ixMC_IO_DEBUG_UP_16 0x0010 +#define ixMC_IO_DEBUG_UP_17 0x0011 +#define ixMC_IO_DEBUG_UP_18 0x0012 +#define ixMC_IO_DEBUG_UP_19 0x0013 +#define ixMC_IO_DEBUG_UP_20 0x0014 +#define ixMC_IO_DEBUG_UP_2 0x0002 +#define ixMC_IO_DEBUG_UP_21 0x0015 +#define ixMC_IO_DEBUG_UP_22 0x0016 +#define ixMC_IO_DEBUG_UP_23 0x0017 +#define ixMC_IO_DEBUG_UP_24 0x0018 +#define ixMC_IO_DEBUG_UP_25 0x0019 +#define ixMC_IO_DEBUG_UP_26 0x001A +#define ixMC_IO_DEBUG_UP_27 0x001B +#define ixMC_IO_DEBUG_UP_28 0x001C +#define ixMC_IO_DEBUG_UP_29 0x001D +#define ixMC_IO_DEBUG_UP_30 0x001E +#define ixMC_IO_DEBUG_UP_3 0x0003 +#define ixMC_IO_DEBUG_UP_31 0x001F +#define ixMC_IO_DEBUG_UP_32 0x0020 +#define ixMC_IO_DEBUG_UP_33 0x0021 +#define ixMC_IO_DEBUG_UP_34 0x0022 +#define ixMC_IO_DEBUG_UP_35 0x0023 +#define ixMC_IO_DEBUG_UP_36 0x0024 +#define ixMC_IO_DEBUG_UP_37 0x0025 +#define ixMC_IO_DEBUG_UP_38 0x0026 +#define ixMC_IO_DEBUG_UP_39 0x0027 +#define ixMC_IO_DEBUG_UP_40 0x0028 +#define ixMC_IO_DEBUG_UP_4 0x0004 +#define ixMC_IO_DEBUG_UP_41 0x0029 +#define ixMC_IO_DEBUG_UP_42 0x002A +#define ixMC_IO_DEBUG_UP_43 0x002B +#define ixMC_IO_DEBUG_UP_44 0x002C +#define ixMC_IO_DEBUG_UP_45 0x002D +#define ixMC_IO_DEBUG_UP_46 0x002E +#define ixMC_IO_DEBUG_UP_47 0x002F +#define ixMC_IO_DEBUG_UP_48 0x0030 +#define ixMC_IO_DEBUG_UP_49 0x0031 +#define ixMC_IO_DEBUG_UP_50 0x0032 +#define ixMC_IO_DEBUG_UP_5 0x0005 +#define ixMC_IO_DEBUG_UP_51 0x0033 +#define ixMC_IO_DEBUG_UP_52 0x0034 +#define ixMC_IO_DEBUG_UP_53 0x0035 +#define ixMC_IO_DEBUG_UP_54 0x0036 +#define ixMC_IO_DEBUG_UP_55 0x0037 +#define ixMC_IO_DEBUG_UP_56 0x0038 +#define ixMC_IO_DEBUG_UP_57 0x0039 +#define ixMC_IO_DEBUG_UP_58 0x003A +#define ixMC_IO_DEBUG_UP_59 0x003B +#define ixMC_IO_DEBUG_UP_60 0x003C +#define ixMC_IO_DEBUG_UP_6 0x0006 +#define ixMC_IO_DEBUG_UP_61 0x003D +#define ixMC_IO_DEBUG_UP_62 0x003E +#define ixMC_IO_DEBUG_UP_63 0x003F +#define ixMC_IO_DEBUG_UP_64 0x0040 +#define ixMC_IO_DEBUG_UP_65 0x0041 +#define ixMC_IO_DEBUG_UP_66 0x0042 +#define ixMC_IO_DEBUG_UP_67 0x0043 +#define ixMC_IO_DEBUG_UP_68 0x0044 +#define ixMC_IO_DEBUG_UP_69 0x0045 +#define ixMC_IO_DEBUG_UP_70 0x0046 +#define ixMC_IO_DEBUG_UP_7 0x0007 +#define ixMC_IO_DEBUG_UP_71 0x0047 +#define ixMC_IO_DEBUG_UP_72 0x0048 +#define ixMC_IO_DEBUG_UP_73 0x0049 +#define ixMC_IO_DEBUG_UP_74 0x004A +#define ixMC_IO_DEBUG_UP_75 0x004B +#define ixMC_IO_DEBUG_UP_76 0x004C +#define ixMC_IO_DEBUG_UP_77 0x004D +#define ixMC_IO_DEBUG_UP_78 0x004E +#define ixMC_IO_DEBUG_UP_79 0x004F +#define ixMC_IO_DEBUG_UP_80 0x0050 +#define ixMC_IO_DEBUG_UP_8 0x0008 +#define ixMC_IO_DEBUG_UP_81 0x0051 +#define ixMC_IO_DEBUG_UP_82 0x0052 +#define ixMC_IO_DEBUG_UP_83 0x0053 +#define ixMC_IO_DEBUG_UP_84 0x0054 +#define ixMC_IO_DEBUG_UP_85 0x0055 +#define ixMC_IO_DEBUG_UP_86 0x0056 +#define ixMC_IO_DEBUG_UP_87 0x0057 +#define ixMC_IO_DEBUG_UP_88 0x0058 +#define ixMC_IO_DEBUG_UP_89 0x0059 +#define ixMC_IO_DEBUG_UP_90 0x005A +#define ixMC_IO_DEBUG_UP_9 0x0009 +#define ixMC_IO_DEBUG_UP_91 0x005B +#define ixMC_IO_DEBUG_UP_92 0x005C +#define ixMC_IO_DEBUG_UP_93 0x005D +#define ixMC_IO_DEBUG_UP_94 0x005E +#define ixMC_IO_DEBUG_UP_95 0x005F +#define ixMC_IO_DEBUG_UP_96 0x0060 +#define ixMC_IO_DEBUG_UP_97 0x0061 +#define ixMC_IO_DEBUG_UP_98 0x0062 +#define ixMC_IO_DEBUG_UP_99 0x0063 +#define ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D0 0x01EA +#define ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D1 0x01FA +#define ixMC_IO_DEBUG_WCDR_CLKSEL_D0 0x01E1 +#define ixMC_IO_DEBUG_WCDR_CLKSEL_D1 0x01F1 +#define ixMC_IO_DEBUG_WCDR_MISC_D0 0x01E0 +#define ixMC_IO_DEBUG_WCDR_MISC_D1 0x01F0 +#define ixMC_IO_DEBUG_WCDR_OFSCAL_D0 0x01E2 +#define ixMC_IO_DEBUG_WCDR_OFSCAL_D1 0x01F2 +#define ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D0 0x01EC +#define ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D1 0x01FC +#define ixMC_IO_DEBUG_WCDR_RX_EQ_D0 0x01E9 +#define ixMC_IO_DEBUG_WCDR_RX_EQ_D1 0x01F9 +#define ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D0 0x01EB +#define ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D1 0x01FB +#define ixMC_IO_DEBUG_WCDR_RXPHASE_D0 0x01E3 +#define ixMC_IO_DEBUG_WCDR_RXPHASE_D1 0x01F3 +#define ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D0 0x01E5 +#define ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D1 0x01F5 +#define ixMC_IO_DEBUG_WCDR_TXBST_PD_D0 0x01E7 +#define ixMC_IO_DEBUG_WCDR_TXBST_PD_D1 0x01F7 +#define ixMC_IO_DEBUG_WCDR_TXBST_PU_D0 0x01E8 +#define ixMC_IO_DEBUG_WCDR_TXBST_PU_D1 0x01F8 +#define ixMC_IO_DEBUG_WCDR_TXPHASE_D0 0x01E4 +#define ixMC_IO_DEBUG_WCDR_TXPHASE_D1 0x01F4 +#define ixMC_IO_DEBUG_WCDR_TXSLF_D0 0x01E6 +#define ixMC_IO_DEBUG_WCDR_TXSLF_D1 0x01F6 +#define ixMC_IO_DEBUG_WCK_CLKSEL_D0 0x00CA +#define ixMC_IO_DEBUG_WCK_CLKSEL_D1 0x00DA +#define ixMC_IO_DEBUG_WCK_MISC_D0 0x00AA +#define ixMC_IO_DEBUG_WCK_MISC_D1 0x00BA +#define ixMC_IO_DEBUG_WCK_OFSCAL_D0 0x00EA +#define ixMC_IO_DEBUG_WCK_OFSCAL_D1 0x00FA +#define ixMC_IO_DEBUG_WCK_RX_EQ_D0 0x01CA +#define ixMC_IO_DEBUG_WCK_RX_EQ_D1 0x01DA +#define ixMC_IO_DEBUG_WCK_RXPHASE_D0 0x010A +#define ixMC_IO_DEBUG_WCK_RXPHASE_D1 0x011A +#define ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D0 0x014A +#define ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D1 0x015A +#define ixMC_IO_DEBUG_WCK_TXBST_PD_D0 0x018A +#define ixMC_IO_DEBUG_WCK_TXBST_PD_D1 0x019A +#define ixMC_IO_DEBUG_WCK_TXBST_PU_D0 0x01AA +#define ixMC_IO_DEBUG_WCK_TXBST_PU_D1 0x01BA +#define ixMC_IO_DEBUG_WCK_TXPHASE_D0 0x012A +#define ixMC_IO_DEBUG_WCK_TXPHASE_D1 0x013A +#define ixMC_IO_DEBUG_WCK_TXSLF_D0 0x016A +#define ixMC_IO_DEBUG_WCK_TXSLF_D1 0x017A +#define ixMC_TSM_DEBUG_BCNT0 0x0003 +#define ixMC_TSM_DEBUG_BCNT10 0x000D +#define ixMC_TSM_DEBUG_BCNT1 0x0004 +#define ixMC_TSM_DEBUG_BCNT2 0x0005 +#define ixMC_TSM_DEBUG_BCNT3 0x0006 +#define ixMC_TSM_DEBUG_BCNT4 0x0007 +#define ixMC_TSM_DEBUG_BCNT5 0x0008 +#define ixMC_TSM_DEBUG_BCNT6 0x0009 +#define ixMC_TSM_DEBUG_BCNT7 0x000A +#define ixMC_TSM_DEBUG_BCNT8 0x000B +#define ixMC_TSM_DEBUG_BCNT9 0x000C +#define ixMC_TSM_DEBUG_BKPT 0x0013 +#define ixMC_TSM_DEBUG_FLAG 0x0001 +#define ixMC_TSM_DEBUG_GCNT 0x0000 +#define ixMC_TSM_DEBUG_MISC 0x0002 +#define ixMC_TSM_DEBUG_ST01 0x0010 +#define ixMC_TSM_DEBUG_ST23 0x0011 +#define ixMC_TSM_DEBUG_ST45 0x0012 +#define mmATC_ATS_CNTL 0x0CC9 +#define mmATC_ATS_DEBUG 0x0CCA +#define mmATC_ATS_DEFAULT_PAGE_CNTL 0x0CD1 +#define mmATC_ATS_DEFAULT_PAGE_LOW 0x0CD0 +#define mmATC_ATS_FAULT_CNTL 0x0CCD +#define mmATC_ATS_FAULT_DEBUG 0x0CCB +#define mmATC_ATS_FAULT_STATUS_ADDR 0x0CCF +#define mmATC_ATS_FAULT_STATUS_INFO 0x0CCE +#define mmATC_ATS_STATUS 0x0CCC +#define mmATC_L1_ADDRESS_OFFSET 0x0CDD +#define mmATC_L1_CNTL 0x0CDC +#define mmATC_L1RD_DEBUG_TLB 0x0CDE +#define mmATC_L1RD_STATUS 0x0CE0 +#define mmATC_L1WR_DEBUG_TLB 0x0CDF +#define mmATC_L1WR_STATUS 0x0CE1 +#define mmATC_L2_CNTL 0x0CD5 +#define mmATC_L2_DEBUG 0x0CD7 +#define mmATC_MISC_CG 0x0CD4 +#define mmATC_VM_APERTURE0_CNTL 0x0CC4 +#define mmATC_VM_APERTURE0_CNTL2 0x0CC6 +#define mmATC_VM_APERTURE0_HIGH_ADDR 0x0CC2 +#define mmATC_VM_APERTURE0_LOW_ADDR 0x0CC0 +#define mmATC_VM_APERTURE1_CNTL 0x0CC5 +#define mmATC_VM_APERTURE1_CNTL2 0x0CC7 +#define mmATC_VM_APERTURE1_HIGH_ADDR 0x0CC3 +#define mmATC_VM_APERTURE1_LOW_ADDR 0x0CC1 +#define mmATC_VMID0_PASID_MAPPING 0x0CE7 +#define mmATC_VMID10_PASID_MAPPING 0x0CF1 +#define mmATC_VMID11_PASID_MAPPING 0x0CF2 +#define mmATC_VMID12_PASID_MAPPING 0x0CF3 +#define mmATC_VMID13_PASID_MAPPING 0x0CF4 +#define mmATC_VMID14_PASID_MAPPING 0x0CF5 +#define mmATC_VMID15_PASID_MAPPING 0x0CF6 +#define mmATC_VMID1_PASID_MAPPING 0x0CE8 +#define mmATC_VMID2_PASID_MAPPING 0x0CE9 +#define mmATC_VMID3_PASID_MAPPING 0x0CEA +#define mmATC_VMID4_PASID_MAPPING 0x0CEB +#define mmATC_VMID5_PASID_MAPPING 0x0CEC +#define mmATC_VMID6_PASID_MAPPING 0x0CED +#define mmATC_VMID7_PASID_MAPPING 0x0CEE +#define mmATC_VMID8_PASID_MAPPING 0x0CEF +#define mmATC_VMID9_PASID_MAPPING 0x0CF0 +#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS 0x0CE6 +#define mmCC_MC_MAX_CHANNEL 0x096E +#define mmDLL_CNTL 0x0AE9 +#define mmGMCON_DEBUG 0x0D5F +#define mmGMCON_MISC 0x0D43 +#define mmGMCON_MISC2 0x0D44 +#define mmGMCON_MISC3 0x0D51 +#define mmGMCON_PERF_MON_CNTL0 0x0D4A +#define mmGMCON_PERF_MON_CNTL1 0x0D4B +#define mmGMCON_PERF_MON_RSLT0 0x0D4C +#define mmGMCON_PERF_MON_RSLT1 0x0D4D +#define mmGMCON_PGFSM_CONFIG 0x0D4E +#define mmGMCON_PGFSM_READ 0x0D50 +#define mmGMCON_PGFSM_WRITE 0x0D4F +#define mmGMCON_RENG_EXECUTE 0x0D42 +#define mmGMCON_RENG_RAM_DATA 0x0D41 +#define mmGMCON_RENG_RAM_INDEX 0x0D40 +#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0 0x0D48 +#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1 0x0D49 +#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE0 0x0D45 +#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE1 0x0D46 +#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE2 0x0D47 +#define mmMC_ARB_ADDR_HASH 0x09DC +#define mmMC_ARB_AGE_RD 0x09E9 +#define mmMC_ARB_AGE_WR 0x09EA +#define mmMC_ARB_BANKMAP 0x09D7 +#define mmMC_ARB_BURST_TIME 0x0A02 +#define mmMC_ARB_CAC_CNTL 0x09D4 +#define mmMC_ARB_CG 0x09FA +#define mmMC_ARB_DRAM_TIMING 0x09DD +#define mmMC_ARB_DRAM_TIMING_1 0x09FC +#define mmMC_ARB_DRAM_TIMING2 0x09DE +#define mmMC_ARB_DRAM_TIMING2_1 0x09FF +#define mmMC_ARB_FED_CNTL 0x09C1 +#define mmMC_ARB_GDEC_RD_CNTL 0x09EE +#define mmMC_ARB_GDEC_WR_CNTL 0x09EF +#define mmMC_ARB_GECC2 0x09C9 +#define mmMC_ARB_GECC2_CLI 0x09CA +#define mmMC_ARB_GECC2_DEBUG 0x09C4 +#define mmMC_ARB_GECC2_DEBUG2 0x09C5 +#define mmMC_ARB_GECC2_MISC 0x09C3 +#define mmMC_ARB_GECC2_STATUS 0x09C2 +#define mmMC_ARB_LAZY0_RD 0x09E5 +#define mmMC_ARB_LAZY0_WR 0x09E6 +#define mmMC_ARB_LAZY1_RD 0x09E7 +#define mmMC_ARB_LAZY1_WR 0x09E8 +#define mmMC_ARB_LM_RD 0x09F0 +#define mmMC_ARB_LM_WR 0x09F1 +#define mmMC_ARB_MINCLKS 0x09DA +#define mmMC_ARB_MISC 0x09D6 +#define mmMC_ARB_MISC2 0x09D5 +#define mmMC_ARB_PM_CNTL 0x09ED +#define mmMC_ARB_POP 0x09D9 +#define mmMC_ARB_RAMCFG 0x09D8 +#define mmMC_ARB_REMREQ 0x09F2 +#define mmMC_ARB_REPLAY 0x09F3 +#define mmMC_ARB_RET_CREDITS_RD 0x09F4 +#define mmMC_ARB_RET_CREDITS_WR 0x09F5 +#define mmMC_ARB_RFSH_CNTL 0x09EB +#define mmMC_ARB_RFSH_RATE 0x09EC +#define mmMC_ARB_RTT_CNTL0 0x09D0 +#define mmMC_ARB_RTT_CNTL1 0x09D1 +#define mmMC_ARB_RTT_CNTL2 0x09D2 +#define mmMC_ARB_RTT_DATA 0x09CF +#define mmMC_ARB_RTT_DEBUG 0x09D3 +#define mmMC_ARB_SQM_CNTL 0x09DB +#define mmMC_ARB_TM_CNTL_RD 0x09E3 +#define mmMC_ARB_TM_CNTL_WR 0x09E4 +#define mmMC_ARB_WCDR 0x09FB +#define mmMC_ARB_WCDR_2 0x09CE +#define mmMC_ARB_WTM_CNTL_RD 0x09DF +#define mmMC_ARB_WTM_CNTL_WR 0x09E0 +#define mmMC_ARB_WTM_GRPWT_RD 0x09E1 +#define mmMC_ARB_WTM_GRPWT_WR 0x09E2 +#define mmMC_BIST_AUTO_CNTL 0x0A06 +#define mmMC_BIST_CMD_CNTL 0x0A8E +#define mmMC_BIST_CMP_CNTL 0x0A8D +#define mmMC_BIST_CMP_CNTL_2 0x0AB6 +#define mmMC_BIST_CNTL 0x0A05 +#define mmMC_BIST_DATA_MASK 0x0A12 +#define mmMC_BIST_DATA_WORD0 0x0A0A +#define mmMC_BIST_DATA_WORD1 0x0A0B +#define mmMC_BIST_DATA_WORD2 0x0A0C +#define mmMC_BIST_DATA_WORD3 0x0A0D +#define mmMC_BIST_DATA_WORD4 0x0A0E +#define mmMC_BIST_DATA_WORD5 0x0A0F +#define mmMC_BIST_DATA_WORD6 0x0A10 +#define mmMC_BIST_DATA_WORD7 0x0A11 +#define mmMC_BIST_DIR_CNTL 0x0A07 +#define mmMC_BIST_EADDR 0x0A09 +#define mmMC_BIST_MISMATCH_ADDR 0x0A13 +#define mmMC_BIST_RDATA_EDC 0x0A1D +#define mmMC_BIST_RDATA_MASK 0x0A1C +#define mmMC_BIST_RDATA_WORD0 0x0A14 +#define mmMC_BIST_RDATA_WORD1 0x0A15 +#define mmMC_BIST_RDATA_WORD2 0x0A16 +#define mmMC_BIST_RDATA_WORD3 0x0A17 +#define mmMC_BIST_RDATA_WORD4 0x0A18 +#define mmMC_BIST_RDATA_WORD5 0x0A19 +#define mmMC_BIST_RDATA_WORD6 0x0A1A +#define mmMC_BIST_RDATA_WORD7 0x0A1B +#define mmMC_BIST_SADDR 0x0A08 +#define mmMC_CG_CONFIG 0x096F +#define mmMC_CG_CONFIG_MCD 0x0829 +#define mmMC_CG_DATAPORT 0x0A21 +#define mmMC_CITF_CNTL 0x0970 +#define mmMC_CITF_CREDITS_ARB_RD 0x0972 +#define mmMC_CITF_CREDITS_ARB_WR 0x0973 +#define mmMC_CITF_CREDITS_VM 0x0971 +#define mmMC_CITF_CREDITS_XBAR 0x0989 +#define mmMC_CITF_DAGB_CNTL 0x0974 +#define mmMC_CITF_DAGB_DLY 0x0977 +#define mmMC_CITF_INT_CREDITS 0x0975 +#define mmMC_CITF_INT_CREDITS_WR 0x097D +#define mmMC_CITF_MISC_RD_CG 0x0992 +#define mmMC_CITF_MISC_VM_CG 0x0994 +#define mmMC_CITF_MISC_WR_CG 0x0993 +#define mmMC_CITF_PERF_MON_CNTL2 0x098E +#define mmMC_CITF_PERF_MON_RSLT2 0x0991 +#define mmMC_CITF_REMREQ 0x097A +#define mmMC_CITF_RET_MODE 0x0976 +#define mmMC_CITF_WTM_RD_CNTL 0x097F +#define mmMC_CITF_WTM_WR_CNTL 0x0980 +#define mmMC_CITF_XTRA_ENABLE 0x096D +#define mmMC_CONFIG 0x0800 +#define mmMC_CONFIG_MCD 0x0828 +#define mmMC_HUB_MISC_DBG 0x0831 +#define mmMC_HUB_MISC_FRAMING 0x0834 +#define mmMC_HUB_MISC_HUB_CG 0x082E +#define mmMC_HUB_MISC_IDLE_STATUS 0x0847 +#define mmMC_HUB_MISC_OVERRIDE 0x0833 +#define mmMC_HUB_MISC_POWER 0x082D +#define mmMC_HUB_MISC_SIP_CG 0x0830 +#define mmMC_HUB_MISC_STATUS 0x0832 +#define mmMC_HUB_MISC_VM_CG 0x082F +#define mmMC_HUB_RDREQ_CNTL 0x083B +#define mmMC_HUB_RDREQ_CREDITS 0x0844 +#define mmMC_HUB_RDREQ_CREDITS2 0x0845 +#define mmMC_HUB_RDREQ_DMIF 0x0863 +#define mmMC_HUB_RDREQ_DMIF_LIMIT 0x0848 +#define mmMC_HUB_RDREQ_GBL0 0x0856 +#define mmMC_HUB_RDREQ_GBL1 0x0857 +#define mmMC_HUB_RDREQ_HDP 0x085B +#define mmMC_HUB_RDREQ_MCDW 0x0851 +#define mmMC_HUB_RDREQ_MCDX 0x0852 +#define mmMC_HUB_RDREQ_MCDY 0x0853 +#define mmMC_HUB_RDREQ_MCDZ 0x0854 +#define mmMC_HUB_RDREQ_MCIF 0x0864 +#define mmMC_HUB_RDREQ_RLC 0x085D +#define mmMC_HUB_RDREQ_SEM 0x085E +#define mmMC_HUB_RDREQ_SIP 0x0855 +#define mmMC_HUB_RDREQ_SMU 0x0858 +#define mmMC_HUB_RDREQ_STATUS 0x0839 +#define mmMC_HUB_RDREQ_UMC 0x0860 +#define mmMC_HUB_RDREQ_UVD 0x0861 +#define mmMC_HUB_RDREQ_VCE 0x085F +#define mmMC_HUB_RDREQ_VCEU 0x0866 +#define mmMC_HUB_RDREQ_VMC 0x0865 +#define mmMC_HUB_RDREQ_WTM_CNTL 0x083D +#define mmMC_HUB_RDREQ_XDMAM 0x0882 +#define mmMC_HUB_SHARED_DAGB_DLY 0x0846 +#define mmMC_HUB_WDP_BP 0x0837 +#define mmMC_HUB_WDP_CNTL 0x0835 +#define mmMC_HUB_WDP_CREDITS 0x083F +#define mmMC_HUB_WDP_ERR 0x0836 +#define mmMC_HUB_WDP_GBL0 0x0841 +#define mmMC_HUB_WDP_GBL1 0x0842 +#define mmMC_HUB_WDP_HDP 0x0879 +#define mmMC_HUB_WDP_IH 0x0872 +#define mmMC_HUB_WDP_MCDW 0x0867 +#define mmMC_HUB_WDP_MCDX 0x0868 +#define mmMC_HUB_WDP_MCDY 0x0869 +#define mmMC_HUB_WDP_MCDZ 0x086A +#define mmMC_HUB_WDP_MCIF 0x086F +#define mmMC_HUB_WDP_MGPU 0x0843 +#define mmMC_HUB_WDP_MGPU2 0x0840 +#define mmMC_HUB_WDP_RLC 0x0873 +#define mmMC_HUB_WDP_SEM 0x0874 +#define mmMC_HUB_WDP_SH0 0x086E +#define mmMC_HUB_WDP_SH1 0x0876 +#define mmMC_HUB_WDP_SIP 0x086B +#define mmMC_HUB_WDP_SMU 0x0875 +#define mmMC_HUB_WDP_STATUS 0x0838 +#define mmMC_HUB_WDP_UMC 0x0877 +#define mmMC_HUB_WDP_UVD 0x0878 +#define mmMC_HUB_WDP_VCE 0x0870 +#define mmMC_HUB_WDP_VCEU 0x087F +#define mmMC_HUB_WDP_WTM_CNTL 0x083E +#define mmMC_HUB_WDP_XDMA 0x0881 +#define mmMC_HUB_WDP_XDMAM 0x0880 +#define mmMC_HUB_WDP_XDP 0x0871 +#define mmMC_HUB_WRRET_CNTL 0x083C +#define mmMC_HUB_WRRET_MCDW 0x087B +#define mmMC_HUB_WRRET_MCDX 0x087C +#define mmMC_HUB_WRRET_MCDY 0x087D +#define mmMC_HUB_WRRET_MCDZ 0x087E +#define mmMC_HUB_WRRET_STATUS 0x083A +#define mmMC_IMP_CNTL 0x0A36 +#define mmMC_IMP_DEBUG 0x0A37 +#define mmMC_IMP_DQ_STATUS 0x0ABC +#define mmMC_IMP_STATUS 0x0A38 +#define mmMC_IO_APHY_STR_CNTL_D0 0x0A97 +#define mmMC_IO_APHY_STR_CNTL_D1 0x0A98 +#define mmMC_IO_CDRCNTL1_D0 0x0ADD +#define mmMC_IO_CDRCNTL1_D1 0x0ADE +#define mmMC_IO_CDRCNTL2_D0 0x0AE4 +#define mmMC_IO_CDRCNTL2_D1 0x0AE5 +#define mmMC_IO_CDRCNTL_D0 0x0A55 +#define mmMC_IO_CDRCNTL_D1 0x0A56 +#define mmMC_IO_DPHY_STR_CNTL_D0 0x0A4E +#define mmMC_IO_DPHY_STR_CNTL_D1 0x0A54 +#define mmMC_IO_PAD_CNTL 0x0A73 +#define mmMC_IO_PAD_CNTL_D0 0x0A74 +#define mmMC_IO_PAD_CNTL_D1 0x0A75 +#define mmMC_IO_RXCNTL1_DPHY0_D0 0x0ADF +#define mmMC_IO_RXCNTL1_DPHY0_D1 0x0AE1 +#define mmMC_IO_RXCNTL1_DPHY1_D0 0x0AE0 +#define mmMC_IO_RXCNTL1_DPHY1_D1 0x0AE2 +#define mmMC_IO_RXCNTL_DPHY0_D0 0x0A4C +#define mmMC_IO_RXCNTL_DPHY0_D1 0x0A52 +#define mmMC_IO_RXCNTL_DPHY1_D0 0x0A4D +#define mmMC_IO_RXCNTL_DPHY1_D1 0x0A53 +#define mmMC_IO_TXCNTL_APHY_D0 0x0A4B +#define mmMC_IO_TXCNTL_APHY_D1 0x0A51 +#define mmMC_IO_TXCNTL_DPHY0_D0 0x0A49 +#define mmMC_IO_TXCNTL_DPHY0_D1 0x0A4F +#define mmMC_IO_TXCNTL_DPHY1_D0 0x0A4A +#define mmMC_IO_TXCNTL_DPHY1_D1 0x0A50 +#define mmMCLK_PWRMGT_CNTL 0x0AE8 +#define mmMC_MEM_POWER_LS 0x082A +#define mmMC_NPL_STATUS 0x0A76 +#define mmMC_PHY_TIMING_2 0x0ACE +#define mmMC_PHY_TIMING_D0 0x0ACC +#define mmMC_PHY_TIMING_D1 0x0ACD +#define mmMC_PMG_AUTO_CFG 0x0A35 +#define mmMC_PMG_AUTO_CMD 0x0A34 +#define mmMC_PMG_CFG 0x0A84 +#define mmMC_PMG_CMD_EMRS 0x0A83 +#define mmMC_PMG_CMD_MRS 0x0AAB +#define mmMC_PMG_CMD_MRS1 0x0AD1 +#define mmMC_PMG_CMD_MRS2 0x0AD7 +#define mmMC_RD_CB 0x0981 +#define mmMC_RD_DB 0x0982 +#define mmMC_RD_GRP_EXT 0x0978 +#define mmMC_RD_GRP_GFX 0x0803 +#define mmMC_RD_GRP_LCL 0x098A +#define mmMC_RD_GRP_OTH 0x0807 +#define mmMC_RD_GRP_SYS 0x0805 +#define mmMC_RD_HUB 0x0985 +#define mmMC_RD_TC0 0x0983 +#define mmMC_RD_TC1 0x0984 +#define mmMC_RPB_ARB_CNTL 0x0951 +#define mmMC_RPB_BIF_CNTL 0x0952 +#define mmMC_RPB_CID_QUEUE_EX 0x095A +#define mmMC_RPB_CID_QUEUE_EX_DATA 0x095B +#define mmMC_RPB_CID_QUEUE_RD 0x0957 +#define mmMC_RPB_CID_QUEUE_WR 0x0956 +#define mmMC_RPB_CONF 0x094D +#define mmMC_RPB_DBG1 0x094F +#define mmMC_RPB_EFF_CNTL 0x0950 +#define mmMC_RPB_IF_CONF 0x094E +#define mmMC_RPB_PERF_COUNTER_CNTL 0x0958 +#define mmMC_RPB_PERF_COUNTER_STATUS 0x0959 +#define mmMC_RPB_RD_SWITCH_CNTL 0x0955 +#define mmMC_RPB_WR_COMBINE_CNTL 0x0954 +#define mmMC_RPB_WR_SWITCH_CNTL 0x0953 +#define mmMC_SEQ_BIT_REMAP_B0_D0 0x0AA3 +#define mmMC_SEQ_BIT_REMAP_B0_D1 0x0AA7 +#define mmMC_SEQ_BIT_REMAP_B1_D0 0x0AA4 +#define mmMC_SEQ_BIT_REMAP_B1_D1 0x0AA8 +#define mmMC_SEQ_BIT_REMAP_B2_D0 0x0AA5 +#define mmMC_SEQ_BIT_REMAP_B2_D1 0x0AA9 +#define mmMC_SEQ_BIT_REMAP_B3_D0 0x0AA6 +#define mmMC_SEQ_BIT_REMAP_B3_D1 0x0AAA +#define mmMC_SEQ_BYTE_REMAP_D0 0x0A93 +#define mmMC_SEQ_BYTE_REMAP_D1 0x0A94 +#define mmMC_SEQ_CAS_TIMING 0x0A29 +#define mmMC_SEQ_CAS_TIMING_LP 0x0A9C +#define mmMC_SEQ_CG 0x0A9A +#define mmMC_SEQ_CMD 0x0A31 +#define mmMC_SEQ_CNTL 0x0A25 +#define mmMC_SEQ_CNTL_2 0x0AD4 +#define mmMC_SEQ_DRAM 0x0A26 +#define mmMC_SEQ_DRAM_2 0x0A27 +#define mmMC_SEQ_DRAM_ERROR_INSERTION 0x0ACB +#define mmMC_SEQ_FIFO_CTL 0x0A57 +#define mmMC_SEQ_IO_DEBUG_DATA 0x0A92 +#define mmMC_SEQ_IO_DEBUG_INDEX 0x0A91 +#define mmMC_SEQ_IO_RDBI 0x0AB4 +#define mmMC_SEQ_IO_REDC 0x0AB5 +#define mmMC_SEQ_IO_RESERVE_D0 0x0AB7 +#define mmMC_SEQ_IO_RESERVE_D1 0x0AB8 +#define mmMC_SEQ_IO_RWORD0 0x0AAC +#define mmMC_SEQ_IO_RWORD1 0x0AAD +#define mmMC_SEQ_IO_RWORD2 0x0AAE +#define mmMC_SEQ_IO_RWORD3 0x0AAF +#define mmMC_SEQ_IO_RWORD4 0x0AB0 +#define mmMC_SEQ_IO_RWORD5 0x0AB1 +#define mmMC_SEQ_IO_RWORD6 0x0AB2 +#define mmMC_SEQ_IO_RWORD7 0x0AB3 +#define mmMC_SEQ_MISC0 0x0A80 +#define mmMC_SEQ_MISC1 0x0A81 +#define mmMC_SEQ_MISC3 0x0A8B +#define mmMC_SEQ_MISC4 0x0A8C +#define mmMC_SEQ_MISC5 0x0A95 +#define mmMC_SEQ_MISC6 0x0A96 +#define mmMC_SEQ_MISC7 0x0A99 +#define mmMC_SEQ_MISC8 0x0A5F +#define mmMC_SEQ_MISC9 0x0AE7 +#define mmMC_SEQ_MISC_TIMING 0x0A2A +#define mmMC_SEQ_MISC_TIMING2 0x0A2B +#define mmMC_SEQ_MISC_TIMING2_LP 0x0A9E +#define mmMC_SEQ_MISC_TIMING_LP 0x0A9D +#define mmMC_SEQ_MPLL_OVERRIDE 0x0A22 +#define mmMC_SEQ_PERF_CNTL 0x0A77 +#define mmMC_SEQ_PERF_CNTL_1 0x0AFD +#define mmMC_SEQ_PERF_SEQ_CNT_A_I0 0x0A79 +#define mmMC_SEQ_PERF_SEQ_CNT_A_I1 0x0A7A +#define mmMC_SEQ_PERF_SEQ_CNT_B_I0 0x0A7B +#define mmMC_SEQ_PERF_SEQ_CNT_B_I1 0x0A7C +#define mmMC_SEQ_PERF_SEQ_CNT_C_I0 0x0AD9 +#define mmMC_SEQ_PERF_SEQ_CNT_C_I1 0x0ADA +#define mmMC_SEQ_PERF_SEQ_CNT_D_I0 0x0ADB +#define mmMC_SEQ_PERF_SEQ_CNT_D_I1 0x0ADC +#define mmMC_SEQ_PERF_SEQ_CTL 0x0A78 +#define mmMC_SEQ_PMG_CMD_EMRS_LP 0x0AA1 +#define mmMC_SEQ_PMG_CMD_MRS1_LP 0x0AD2 +#define mmMC_SEQ_PMG_CMD_MRS2_LP 0x0AD8 +#define mmMC_SEQ_PMG_CMD_MRS_LP 0x0AA2 +#define mmMC_SEQ_PMG_PG_HWCNTL 0x0AB9 +#define mmMC_SEQ_PMG_PG_SWCNTL_0 0x0ABA +#define mmMC_SEQ_PMG_PG_SWCNTL_1 0x0ABB +#define mmMC_SEQ_PMG_TIMING 0x0A2C +#define mmMC_SEQ_PMG_TIMING_LP 0x0AD3 +#define mmMC_SEQ_RAS_TIMING 0x0A28 +#define mmMC_SEQ_RAS_TIMING_LP 0x0A9B +#define mmMC_SEQ_RD_CTL_D0 0x0A2D +#define mmMC_SEQ_RD_CTL_D0_LP 0x0AC7 +#define mmMC_SEQ_RD_CTL_D1 0x0A2E +#define mmMC_SEQ_RD_CTL_D1_LP 0x0AC8 +#define mmMC_SEQ_RESERVE_0_S 0x0A1E +#define mmMC_SEQ_RESERVE_1_S 0x0A1F +#define mmMC_SEQ_RESERVE_M 0x0A82 +#define mmMC_SEQ_RXFRAMING_BYTE0_D0 0x0A67 +#define mmMC_SEQ_RXFRAMING_BYTE0_D1 0x0A6D +#define mmMC_SEQ_RXFRAMING_BYTE1_D0 0x0A68 +#define mmMC_SEQ_RXFRAMING_BYTE1_D1 0x0A6E +#define mmMC_SEQ_RXFRAMING_BYTE2_D0 0x0A69 +#define mmMC_SEQ_RXFRAMING_BYTE2_D1 0x0A6F +#define mmMC_SEQ_RXFRAMING_BYTE3_D0 0x0A6A +#define mmMC_SEQ_RXFRAMING_BYTE3_D1 0x0A70 +#define mmMC_SEQ_RXFRAMING_DBI_D0 0x0A6B +#define mmMC_SEQ_RXFRAMING_DBI_D1 0x0A71 +#define mmMC_SEQ_RXFRAMING_EDC_D0 0x0A6C +#define mmMC_SEQ_RXFRAMING_EDC_D1 0x0A72 +#define mmMC_SEQ_STATUS_M 0x0A7D +#define mmMC_SEQ_STATUS_S 0x0A20 +#define mmMC_SEQ_SUP_CNTL 0x0A32 +#define mmMC_SEQ_SUP_DEC_STAT 0x0A88 +#define mmMC_SEQ_SUP_GP0_STAT 0x0A8F +#define mmMC_SEQ_SUP_GP1_STAT 0x0A90 +#define mmMC_SEQ_SUP_GP2_STAT 0x0A85 +#define mmMC_SEQ_SUP_GP3_STAT 0x0A86 +#define mmMC_SEQ_SUP_IR_STAT 0x0A87 +#define mmMC_SEQ_SUP_PGM 0x0A33 +#define mmMC_SEQ_SUP_PGM_STAT 0x0A89 +#define mmMC_SEQ_SUP_R_PGM 0x0A8A +#define mmMC_SEQ_TCG_CNTL 0x0ABD +#define mmMC_SEQ_TIMER_RD 0x0ACA +#define mmMC_SEQ_TIMER_WR 0x0AC9 +#define mmMC_SEQ_TRAIN_CAPTURE 0x0A3E +#define mmMC_SEQ_TRAIN_EDC_THRESHOLD 0x0A3B +#define mmMC_SEQ_TRAIN_EDC_THRESHOLD2 0x0AFE +#define mmMC_SEQ_TRAIN_EDC_THRESHOLD3 0x0AFF +#define mmMC_SEQ_TRAIN_TIMING 0x0A40 +#define mmMC_SEQ_TRAIN_WAKEUP_CLEAR 0x0A3F +#define mmMC_SEQ_TRAIN_WAKEUP_CNTL 0x0A3A +#define mmMC_SEQ_TRAIN_WAKEUP_EDGE 0x0A3C +#define mmMC_SEQ_TRAIN_WAKEUP_MASK 0x0A3D +#define mmMC_SEQ_TSM_BCNT 0x0AC2 +#define mmMC_SEQ_TSM_CTRL 0x0ABE +#define mmMC_SEQ_TSM_DBI 0x0AC6 +#define mmMC_SEQ_TSM_DEBUG_DATA 0x0AD0 +#define mmMC_SEQ_TSM_DEBUG_INDEX 0x0ACF +#define mmMC_SEQ_TSM_EDC 0x0AC5 +#define mmMC_SEQ_TSM_FLAG 0x0AC3 +#define mmMC_SEQ_TSM_GCNT 0x0ABF +#define mmMC_SEQ_TSM_MISC 0x0AE6 +#define mmMC_SEQ_TSM_NCNT 0x0AC1 +#define mmMC_SEQ_TSM_OCNT 0x0AC0 +#define mmMC_SEQ_TSM_UPDATE 0x0AC4 +#define mmMC_SEQ_TSM_WCDR 0x0AE3 +#define mmMC_SEQ_TXFRAMING_BYTE0_D0 0x0A58 +#define mmMC_SEQ_TXFRAMING_BYTE0_D1 0x0A60 +#define mmMC_SEQ_TXFRAMING_BYTE1_D0 0x0A59 +#define mmMC_SEQ_TXFRAMING_BYTE1_D1 0x0A61 +#define mmMC_SEQ_TXFRAMING_BYTE2_D0 0x0A5A +#define mmMC_SEQ_TXFRAMING_BYTE2_D1 0x0A62 +#define mmMC_SEQ_TXFRAMING_BYTE3_D0 0x0A5B +#define mmMC_SEQ_TXFRAMING_BYTE3_D1 0x0A63 +#define mmMC_SEQ_TXFRAMING_DBI_D0 0x0A5C +#define mmMC_SEQ_TXFRAMING_DBI_D1 0x0A64 +#define mmMC_SEQ_TXFRAMING_EDC_D0 0x0A5D +#define mmMC_SEQ_TXFRAMING_EDC_D1 0x0A65 +#define mmMC_SEQ_TXFRAMING_FCK_D0 0x0A5E +#define mmMC_SEQ_TXFRAMING_FCK_D1 0x0A66 +#define mmMC_SEQ_VENDOR_ID_I0 0x0A7E +#define mmMC_SEQ_VENDOR_ID_I1 0x0A7F +#define mmMC_SEQ_WCDR_CTRL 0x0A39 +#define mmMC_SEQ_WR_CTL_2 0x0AD5 +#define mmMC_SEQ_WR_CTL_2_LP 0x0AD6 +#define mmMC_SEQ_WR_CTL_D0 0x0A2F +#define mmMC_SEQ_WR_CTL_D0_LP 0x0A9F +#define mmMC_SEQ_WR_CTL_D1 0x0A30 +#define mmMC_SEQ_WR_CTL_D1_LP 0x0AA0 +#define mmMC_SHARED_BLACKOUT_CNTL 0x082B +#define mmMC_SHARED_CHMAP 0x0801 +#define mmMC_SHARED_CHREMAP 0x0802 +#define mmMC_TRAIN_EDCCDR_R_D0 0x0A41 +#define mmMC_TRAIN_EDCCDR_R_D1 0x0A42 +#define mmMC_TRAIN_EDC_STATUS_D0 0x0A45 +#define mmMC_TRAIN_EDC_STATUS_D1 0x0A48 +#define mmMC_TRAIN_PRBSERR_0_D0 0x0A43 +#define mmMC_TRAIN_PRBSERR_0_D1 0x0A46 +#define mmMC_TRAIN_PRBSERR_1_D0 0x0A44 +#define mmMC_TRAIN_PRBSERR_1_D1 0x0A47 +#define mmMC_TRAIN_PRBSERR_2_D0 0x0AFB +#define mmMC_TRAIN_PRBSERR_2_D1 0x0AFC +#define mmMC_VM_AGP_BASE 0x080C +#define mmMC_VM_AGP_BOT 0x080B +#define mmMC_VM_AGP_TOP 0x080A +#define mmMC_VM_DC_WRITE_CNTL 0x0810 +#define mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR 0x0815 +#define mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR 0x0811 +#define mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR 0x0816 +#define mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR 0x0812 +#define mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR 0x0817 +#define mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR 0x0813 +#define mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR 0x0818 +#define mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR 0x0814 +#define mmMC_VM_FB_LOCATION 0x0809 +#define mmMC_VM_FB_OFFSET 0x081A +#define mmMC_VM_MB_L1_TLB0_DEBUG 0x0891 +#define mmMC_VM_MB_L1_TLB0_STATUS 0x0895 +#define mmMC_VM_MB_L1_TLB1_STATUS 0x0896 +#define mmMC_VM_MB_L1_TLB2_DEBUG 0x0893 +#define mmMC_VM_MB_L1_TLB2_STATUS 0x0897 +#define mmMC_VM_MB_L1_TLB3_DEBUG 0x08A5 +#define mmMC_VM_MB_L1_TLB3_STATUS 0x08A6 +#define mmMC_VM_MB_L2ARBITER_L2_CREDITS 0x08A1 +#define mmMC_VM_MD_L1_TLB0_DEBUG 0x0998 +#define mmMC_VM_MD_L1_TLB0_STATUS 0x099B +#define mmMC_VM_MD_L1_TLB1_DEBUG 0x0999 +#define mmMC_VM_MD_L1_TLB1_STATUS 0x099C +#define mmMC_VM_MD_L1_TLB2_DEBUG 0x099A +#define mmMC_VM_MD_L1_TLB2_STATUS 0x099D +#define mmMC_VM_MD_L1_TLB3_DEBUG 0x09A7 +#define mmMC_VM_MD_L1_TLB3_STATUS 0x09A8 +#define mmMC_VM_MD_L2ARBITER_L2_CREDITS 0x09A4 +#define mmMC_VM_MX_L1_TLB_CNTL 0x0819 +#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x080F +#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x080E +#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x080D +#define mmMC_WR_CB 0x0986 +#define mmMC_WR_DB 0x0987 +#define mmMC_WR_GRP_EXT 0x0979 +#define mmMC_WR_GRP_GFX 0x0804 +#define mmMC_WR_GRP_LCL 0x098B +#define mmMC_WR_GRP_OTH 0x0808 +#define mmMC_WR_GRP_SYS 0x0806 +#define mmMC_WR_HUB 0x0988 +#define mmMC_WR_TC0 0x097B +#define mmMC_WR_TC1 0x097C +#define mmMC_XBAR_ADDR_DEC 0x0C80 +#define mmMC_XBAR_ARB 0x0C8D +#define mmMC_XBAR_ARB_MAX_BURST 0x0C8E +#define mmMC_XBAR_CHTRIREMAP 0x0C8B +#define mmMC_XBAR_PERF_MON_CNTL0 0x0C8F +#define mmMC_XBAR_PERF_MON_CNTL1 0x0C90 +#define mmMC_XBAR_PERF_MON_CNTL2 0x0C91 +#define mmMC_XBAR_PERF_MON_MAX_THSH 0x0C96 +#define mmMC_XBAR_PERF_MON_RSLT0 0x0C92 +#define mmMC_XBAR_PERF_MON_RSLT1 0x0C93 +#define mmMC_XBAR_PERF_MON_RSLT2 0x0C94 +#define mmMC_XBAR_PERF_MON_RSLT3 0x0C95 +#define mmMC_XBAR_RDREQ_CREDIT 0x0C83 +#define mmMC_XBAR_RDREQ_PRI_CREDIT 0x0C84 +#define mmMC_XBAR_RDRET_CREDIT1 0x0C87 +#define mmMC_XBAR_RDRET_CREDIT2 0x0C88 +#define mmMC_XBAR_RDRET_PRI_CREDIT1 0x0C89 +#define mmMC_XBAR_RDRET_PRI_CREDIT2 0x0C8A +#define mmMC_XBAR_REMOTE 0x0C81 +#define mmMC_XBAR_SPARE0 0x0C97 +#define mmMC_XBAR_SPARE1 0x0C98 +#define mmMC_XBAR_TWOCHAN 0x0C8C +#define mmMC_XBAR_WRREQ_CREDIT 0x0C82 +#define mmMC_XBAR_WRRET_CREDIT1 0x0C85 +#define mmMC_XBAR_WRRET_CREDIT2 0x0C86 +#define mmMC_XPB_CLG_CFG0 0x08E9 +#define mmMC_XPB_CLG_CFG10 0x08F3 +#define mmMC_XPB_CLG_CFG1 0x08EA +#define mmMC_XPB_CLG_CFG11 0x08F4 +#define mmMC_XPB_CLG_CFG12 0x08F5 +#define mmMC_XPB_CLG_CFG13 0x08F6 +#define mmMC_XPB_CLG_CFG14 0x08F7 +#define mmMC_XPB_CLG_CFG15 0x08F8 +#define mmMC_XPB_CLG_CFG16 0x08F9 +#define mmMC_XPB_CLG_CFG17 0x08FA +#define mmMC_XPB_CLG_CFG18 0x08FB +#define mmMC_XPB_CLG_CFG19 0x08FC +#define mmMC_XPB_CLG_CFG20 0x0928 +#define mmMC_XPB_CLG_CFG2 0x08EB +#define mmMC_XPB_CLG_CFG21 0x0929 +#define mmMC_XPB_CLG_CFG22 0x092A +#define mmMC_XPB_CLG_CFG23 0x092B +#define mmMC_XPB_CLG_CFG24 0x092C +#define mmMC_XPB_CLG_CFG25 0x092D +#define mmMC_XPB_CLG_CFG26 0x092E +#define mmMC_XPB_CLG_CFG27 0x092F +#define mmMC_XPB_CLG_CFG28 0x0930 +#define mmMC_XPB_CLG_CFG29 0x0931 +#define mmMC_XPB_CLG_CFG30 0x0932 +#define mmMC_XPB_CLG_CFG3 0x08EC +#define mmMC_XPB_CLG_CFG31 0x0933 +#define mmMC_XPB_CLG_CFG32 0x0936 +#define mmMC_XPB_CLG_CFG33 0x0937 +#define mmMC_XPB_CLG_CFG34 0x0938 +#define mmMC_XPB_CLG_CFG35 0x0939 +#define mmMC_XPB_CLG_CFG36 0x093A +#define mmMC_XPB_CLG_CFG4 0x08ED +#define mmMC_XPB_CLG_CFG5 0x08EE +#define mmMC_XPB_CLG_CFG6 0x08EF +#define mmMC_XPB_CLG_CFG7 0x08F0 +#define mmMC_XPB_CLG_CFG8 0x08F1 +#define mmMC_XPB_CLG_CFG9 0x08F2 +#define mmMC_XPB_CLG_EXTRA 0x08FD +#define mmMC_XPB_CLG_EXTRA_RD 0x0935 +#define mmMC_XPB_CLK_GAT 0x091E +#define mmMC_XPB_INTF_CFG 0x091F +#define mmMC_XPB_INTF_CFG2 0x0934 +#define mmMC_XPB_INTF_STS 0x0920 +#define mmMC_XPB_LB_ADDR 0x08FE +#define mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB 0x0923 +#define mmMC_XPB_MISC_CFG 0x0927 +#define mmMC_XPB_P2P_BAR0 0x0904 +#define mmMC_XPB_P2P_BAR1 0x0905 +#define mmMC_XPB_P2P_BAR2 0x0906 +#define mmMC_XPB_P2P_BAR3 0x0907 +#define mmMC_XPB_P2P_BAR4 0x0908 +#define mmMC_XPB_P2P_BAR5 0x0909 +#define mmMC_XPB_P2P_BAR6 0x090A +#define mmMC_XPB_P2P_BAR7 0x090B +#define mmMC_XPB_P2P_BAR_CFG 0x0903 +#define mmMC_XPB_P2P_BAR_DEBUG 0x090D +#define mmMC_XPB_P2P_BAR_DELTA_ABOVE 0x090E +#define mmMC_XPB_P2P_BAR_DELTA_BELOW 0x090F +#define mmMC_XPB_P2P_BAR_SETUP 0x090C +#define mmMC_XPB_PEER_SYS_BAR0 0x0910 +#define mmMC_XPB_PEER_SYS_BAR1 0x0911 +#define mmMC_XPB_PEER_SYS_BAR2 0x0912 +#define mmMC_XPB_PEER_SYS_BAR3 0x0913 +#define mmMC_XPB_PEER_SYS_BAR4 0x0914 +#define mmMC_XPB_PEER_SYS_BAR5 0x0915 +#define mmMC_XPB_PEER_SYS_BAR6 0x0916 +#define mmMC_XPB_PEER_SYS_BAR7 0x0917 +#define mmMC_XPB_PEER_SYS_BAR8 0x0918 +#define mmMC_XPB_PEER_SYS_BAR9 0x0919 +#define mmMC_XPB_PERF_KNOBS 0x0924 +#define mmMC_XPB_PIPE_STS 0x0921 +#define mmMC_XPB_RTR_DEST_MAP0 0x08DB +#define mmMC_XPB_RTR_DEST_MAP1 0x08DC +#define mmMC_XPB_RTR_DEST_MAP2 0x08DD +#define mmMC_XPB_RTR_DEST_MAP3 0x08DE +#define mmMC_XPB_RTR_DEST_MAP4 0x08DF +#define mmMC_XPB_RTR_DEST_MAP5 0x08E0 +#define mmMC_XPB_RTR_DEST_MAP6 0x08E1 +#define mmMC_XPB_RTR_DEST_MAP7 0x08E2 +#define mmMC_XPB_RTR_DEST_MAP8 0x08E3 +#define mmMC_XPB_RTR_DEST_MAP9 0x08E4 +#define mmMC_XPB_RTR_SRC_APRTR0 0x08CD +#define mmMC_XPB_RTR_SRC_APRTR1 0x08CE +#define mmMC_XPB_RTR_SRC_APRTR2 0x08CF +#define mmMC_XPB_RTR_SRC_APRTR3 0x08D0 +#define mmMC_XPB_RTR_SRC_APRTR4 0x08D1 +#define mmMC_XPB_RTR_SRC_APRTR5 0x08D2 +#define mmMC_XPB_RTR_SRC_APRTR6 0x08D3 +#define mmMC_XPB_RTR_SRC_APRTR7 0x08D4 +#define mmMC_XPB_RTR_SRC_APRTR8 0x08D5 +#define mmMC_XPB_RTR_SRC_APRTR9 0x08D6 +#define mmMC_XPB_STICKY 0x0925 +#define mmMC_XPB_STICKY_W1C 0x0926 +#define mmMC_XPB_SUB_CTRL 0x0922 +#define mmMC_XPB_UNC_THRESH_HST 0x08FF +#define mmMC_XPB_UNC_THRESH_SID 0x0900 +#define mmMC_XPB_WCB_CFG 0x0902 +#define mmMC_XPB_WCB_STS 0x0901 +#define mmMC_XPB_XDMA_PEER_SYS_BAR0 0x091A +#define mmMC_XPB_XDMA_PEER_SYS_BAR1 0x091B +#define mmMC_XPB_XDMA_PEER_SYS_BAR2 0x091C +#define mmMC_XPB_XDMA_PEER_SYS_BAR3 0x091D +#define mmMC_XPB_XDMA_RTR_DEST_MAP0 0x08E5 +#define mmMC_XPB_XDMA_RTR_DEST_MAP1 0x08E6 +#define mmMC_XPB_XDMA_RTR_DEST_MAP2 0x08E7 +#define mmMC_XPB_XDMA_RTR_DEST_MAP3 0x08E8 +#define mmMC_XPB_XDMA_RTR_SRC_APRTR0 0x08D7 +#define mmMC_XPB_XDMA_RTR_SRC_APRTR1 0x08D8 +#define mmMC_XPB_XDMA_RTR_SRC_APRTR2 0x08D9 +#define mmMC_XPB_XDMA_RTR_SRC_APRTR3 0x08DA +#define mmMPLL_AD_FUNC_CNTL 0x0AF0 +#define mmMPLL_AD_STATUS 0x0AF6 +#define mmMPLL_CNTL_MODE 0x0AEC +#define mmMPLL_CONTROL 0x0AF5 +#define mmMPLL_DQ_0_0_STATUS 0x0AF7 +#define mmMPLL_DQ_0_1_STATUS 0x0AF8 +#define mmMPLL_DQ_1_0_STATUS 0x0AF9 +#define mmMPLL_DQ_1_1_STATUS 0x0AFA +#define mmMPLL_DQ_FUNC_CNTL 0x0AF1 +#define mmMPLL_FUNC_CNTL 0x0AED +#define mmMPLL_FUNC_CNTL_1 0x0AEE +#define mmMPLL_FUNC_CNTL_2 0x0AEF +#define mmMPLL_SEQ_UCODE_1 0x0AEA +#define mmMPLL_SEQ_UCODE_2 0x0AEB +#define mmMPLL_SS1 0x0AF3 +#define mmMPLL_SS2 0x0AF4 +#define mmMPLL_TIME 0x0AF2 +#define mmVM_CONTEXT0_CNTL 0x0504 +#define mmVM_CONTEXT0_CNTL2 0x050C +#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x054F +#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR 0x055F +#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR 0x0557 +#define mmVM_CONTEXT0_PROTECTION_FAULT_ADDR 0x053E +#define mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x0546 +#define mmVM_CONTEXT0_PROTECTION_FAULT_STATUS 0x0536 +#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x0510 +#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x0511 +#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x0512 +#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x0513 +#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x0514 +#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x0515 +#define mmVM_CONTEXT1_CNTL 0x0505 +#define mmVM_CONTEXT1_CNTL2 0x050D +#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x0550 +#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR 0x0560 +#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR 0x0558 +#define mmVM_CONTEXT1_PROTECTION_FAULT_ADDR 0x053F +#define mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x0547 +#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS 0x0537 +#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x0551 +#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x0552 +#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x0553 +#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x0554 +#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x0555 +#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x0556 +#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x050E +#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x050F +#define mmVM_CONTEXTS_DISABLE 0x0535 +#define mmVM_DEBUG 0x056F +#define mmVM_DUMMY_PAGE_FAULT_ADDR 0x0507 +#define mmVM_DUMMY_PAGE_FAULT_CNTL 0x0506 +#define mmVM_FAULT_CLIENT_ID 0x054E +#define mmVM_INVALIDATE_REQUEST 0x051E +#define mmVM_INVALIDATE_RESPONSE 0x051F +#define mmVM_L2_BANK_SELECT_MASKA 0x0572 +#define mmVM_L2_BANK_SELECT_MASKB 0x0573 +#define mmVM_L2_CG 0x0570 +#define mmVM_L2_CNTL 0x0500 +#define mmVM_L2_CNTL2 0x0501 +#define mmVM_L2_CNTL3 0x0502 +#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR 0x0576 +#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR 0x0575 +#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET 0x0577 +#define mmVM_L2_STATUS 0x0503 +#define mmVM_PRT_APERTURE0_HIGH_ADDR 0x0530 +#define mmVM_PRT_APERTURE0_LOW_ADDR 0x052C +#define mmVM_PRT_APERTURE1_HIGH_ADDR 0x0531 +#define mmVM_PRT_APERTURE1_LOW_ADDR 0x052D +#define mmVM_PRT_APERTURE2_HIGH_ADDR 0x0532 +#define mmVM_PRT_APERTURE2_LOW_ADDR 0x052E +#define mmVM_PRT_APERTURE3_HIGH_ADDR 0x0533 +#define mmVM_PRT_APERTURE3_LOW_ADDR 0x052F +#define mmVM_PRT_CNTL 0x0534 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h new file mode 100644 index 000000000000..0f6c6c8d089b --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h @@ -0,0 +1,11895 @@ +/* + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef GMC_6_0_SH_MASK_H +#define GMC_6_0_SH_MASK_H + +#define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x00003f00L +#define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x00000008 +#define ATC_ATS_CNTL__DEBUG_ECO_MASK 0x000f0000L +#define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x00000010 +#define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L +#define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x00000000 +#define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L +#define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x00000002 +#define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L +#define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x00000001 +#define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS_MASK 0x00000004L +#define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS__SHIFT 0x00000002 +#define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE_MASK 0x00004000L +#define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE__SHIFT 0x0000000e +#define ATC_ATS_DEBUG__EXE_BIT_MASK 0x00000080L +#define ATC_ATS_DEBUG__EXE_BIT__SHIFT 0x00000007 +#define ATC_ATS_DEBUG__IDENT_RETURN_MASK 0x00000002L +#define ATC_ATS_DEBUG__IDENT_RETURN__SHIFT 0x00000001 +#define ATC_ATS_DEBUG__IGNORE_FED_MASK 0x00008000L +#define ATC_ATS_DEBUG__IGNORE_FED__SHIFT 0x0000000f +#define ATC_ATS_DEBUG__INVALIDATE_ALL_MASK 0x00000001L +#define ATC_ATS_DEBUG__INVALIDATE_ALL__SHIFT 0x00000000 +#define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED_MASK 0x00010000L +#define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED__SHIFT 0x00000010 +#define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR_MASK 0x00003c00L +#define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR__SHIFT 0x0000000a +#define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS_MASK 0x00000100L +#define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS__SHIFT 0x00000008 +#define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING_MASK 0x00000020L +#define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING__SHIFT 0x00000005 +#define ATC_ATS_DEBUG__PRIV_BIT_MASK 0x00000040L +#define ATC_ATS_DEBUG__PRIV_BIT__SHIFT 0x00000006 +#define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE_MASK 0x00000200L +#define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE__SHIFT 0x00000009 +#define ATC_ATS_DEFAULT_PAGE_CNTL__DEFAULT_PAGE_HIGH_MASK 0x0000003cL +#define ATC_ATS_DEFAULT_PAGE_CNTL__DEFAULT_PAGE_HIGH__SHIFT 0x00000002 +#define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE_MASK 0x00000001L +#define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE__SHIFT 0x00000000 +#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE_MASK 0xffffffffL +#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE__SHIFT 0x00000000 +#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE_MASK 0x03f00000L +#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE__SHIFT 0x00000014 +#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE_MASK 0x0000fc00L +#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0x0000000a +#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG_MASK 0x0000003fL +#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG__SHIFT 0x00000000 +#define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000100L +#define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x00000008 +#define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR_MASK 0x00010000L +#define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR__SHIFT 0x00000010 +#define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH_MASK 0x0000001fL +#define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH__SHIFT 0x00000000 +#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR_MASK 0xffffffffL +#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR__SHIFT 0x00000000 +#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2_MASK 0x00010000L +#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2__SHIFT 0x00000010 +#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO_MASK 0x00008000L +#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO__SHIFT 0x0000000f +#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE_MASK 0x0000003fL +#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE__SHIFT 0x00000000 +#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION_MASK 0x00020000L +#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION__SHIFT 0x00000011 +#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH_MASK 0x0f000000L +#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH__SHIFT 0x00000018 +#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST_MASK 0x00040000L +#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST__SHIFT 0x00000012 +#define ATC_ATS_FAULT_STATUS_INFO__STATUS_MASK 0x00f80000L +#define ATC_ATS_FAULT_STATUS_INFO__STATUS__SHIFT 0x00000013 +#define ATC_ATS_FAULT_STATUS_INFO__VMID_MASK 0x00007c00L +#define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT 0x0000000a +#define ATC_ATS_STATUS__BUSY_MASK 0x00000001L +#define ATC_ATS_STATUS__BUSY__SHIFT 0x00000000 +#define ATC_ATS_STATUS__CRASHED_MASK 0x00000002L +#define ATC_ATS_STATUS__CRASHED__SHIFT 0x00000001 +#define ATC_ATS_STATUS__DEADLOCK_DETECTION_MASK 0x00000004L +#define ATC_ATS_STATUS__DEADLOCK_DETECTION__SHIFT 0x00000002 +#define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS_MASK 0xffffffffL +#define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS__SHIFT 0x00000000 +#define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR_MASK 0x00000003L +#define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR__SHIFT 0x00000000 +#define ATC_L1_CNTL__NEED_ATS_BEHAVIOR_MASK 0x00000004L +#define ATC_L1_CNTL__NEED_ATS_BEHAVIOR__SHIFT 0x00000002 +#define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT_MASK 0x00000010L +#define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT__SHIFT 0x00000004 +#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2_MASK 0x0003f000L +#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0x0000000c +#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB_MASK 0x0ff00000L +#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x00000014 +#define ATC_L1RD_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000L +#define ATC_L1RD_DEBUG_TLB__DEBUG_ECO__SHIFT 0x0000001c +#define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x00000001L +#define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x00000000 +#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0x000000f0L +#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x00000004 +#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x00000700L +#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x00000008 +#define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000L +#define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x0000001e +#define ATC_L1RD_STATUS__BAD_NEED_ATS_MASK 0x00000100L +#define ATC_L1RD_STATUS__BAD_NEED_ATS__SHIFT 0x00000008 +#define ATC_L1RD_STATUS__BUSY_MASK 0x00000001L +#define ATC_L1RD_STATUS__BUSY__SHIFT 0x00000000 +#define ATC_L1RD_STATUS__DEADLOCK_DETECTION_MASK 0x00000002L +#define ATC_L1RD_STATUS__DEADLOCK_DETECTION__SHIFT 0x00000001 +#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2_MASK 0x0003f000L +#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0x0000000c +#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB_MASK 0x0ff00000L +#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x00000014 +#define ATC_L1WR_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000L +#define ATC_L1WR_DEBUG_TLB__DEBUG_ECO__SHIFT 0x0000001c +#define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x00000001L +#define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x00000000 +#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0x000000f0L +#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x00000004 +#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x00000700L +#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x00000008 +#define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000L +#define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x0000001e +#define ATC_L1WR_STATUS__BAD_NEED_ATS_MASK 0x00000100L +#define ATC_L1WR_STATUS__BAD_NEED_ATS__SHIFT 0x00000008 +#define ATC_L1WR_STATUS__BUSY_MASK 0x00000001L +#define ATC_L1WR_STATUS__BUSY__SHIFT 0x00000000 +#define ATC_L1WR_STATUS__DEADLOCK_DETECTION_MASK 0x00000002L +#define ATC_L1WR_STATUS__DEADLOCK_DETECTION__SHIFT 0x00000001 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x00000000 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000400L +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x0000000a +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000030L +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x00000004 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000800L +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x0000000b +#define ATC_L2_DEBUG__CREDITS_L2_ATS_MASK 0x0000003fL +#define ATC_L2_DEBUG__CREDITS_L2_ATS__SHIFT 0x00000000 +#define ATC_MISC_CG__ENABLE_MASK 0x00040000L +#define ATC_MISC_CG__ENABLE__SHIFT 0x00000012 +#define ATC_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L +#define ATC_MISC_CG__MEM_LS_ENABLE__SHIFT 0x00000013 +#define ATC_MISC_CG__OFFDLY_MASK 0x00000fc0L +#define ATC_MISC_CG__OFFDLY__SHIFT 0x00000006 +#define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE_MASK 0x0000ffffL +#define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE__SHIFT 0x00000000 +#define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE_MASK 0x00000003L +#define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE__SHIFT 0x00000000 +#define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0x0fffffffL +#define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x00000000 +#define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0x0fffffffL +#define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x00000000 +#define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE_MASK 0x0000ffffL +#define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE__SHIFT 0x00000000 +#define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE_MASK 0x00000003L +#define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE__SHIFT 0x00000000 +#define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0x0fffffffL +#define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x00000000 +#define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0x0fffffffL +#define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x00000000 +#define ATC_VMID0_PASID_MAPPING__PASID_MASK 0x0000ffffL +#define ATC_VMID0_PASID_MAPPING__PASID__SHIFT 0x00000000 +#define ATC_VMID0_PASID_MAPPING__VALID_MASK 0x80000000L +#define ATC_VMID0_PASID_MAPPING__VALID__SHIFT 0x0000001f +#define ATC_VMID10_PASID_MAPPING__PASID_MASK 0x0000ffffL +#define ATC_VMID10_PASID_MAPPING__PASID__SHIFT 0x00000000 +#define ATC_VMID10_PASID_MAPPING__VALID_MASK 0x80000000L +#define ATC_VMID10_PASID_MAPPING__VALID__SHIFT 0x0000001f +#define ATC_VMID11_PASID_MAPPING__PASID_MASK 0x0000ffffL +#define ATC_VMID11_PASID_MAPPING__PASID__SHIFT 0x00000000 +#define ATC_VMID11_PASID_MAPPING__VALID_MASK 0x80000000L +#define ATC_VMID11_PASID_MAPPING__VALID__SHIFT 0x0000001f +#define ATC_VMID12_PASID_MAPPING__PASID_MASK 0x0000ffffL +#define ATC_VMID12_PASID_MAPPING__PASID__SHIFT 0x00000000 +#define ATC_VMID12_PASID_MAPPING__VALID_MASK 0x80000000L +#define ATC_VMID12_PASID_MAPPING__VALID__SHIFT 0x0000001f +#define ATC_VMID13_PASID_MAPPING__PASID_MASK 0x0000ffffL +#define ATC_VMID13_PASID_MAPPING__PASID__SHIFT 0x00000000 +#define ATC_VMID13_PASID_MAPPING__VALID_MASK 0x80000000L +#define ATC_VMID13_PASID_MAPPING__VALID__SHIFT 0x0000001f +#define ATC_VMID14_PASID_MAPPING__PASID_MASK 0x0000ffffL +#define ATC_VMID14_PASID_MAPPING__PASID__SHIFT 0x00000000 +#define ATC_VMID14_PASID_MAPPING__VALID_MASK 0x80000000L +#define ATC_VMID14_PASID_MAPPING__VALID__SHIFT 0x0000001f +#define ATC_VMID15_PASID_MAPPING__PASID_MASK 0x0000ffffL +#define ATC_VMID15_PASID_MAPPING__PASID__SHIFT 0x00000000 +#define ATC_VMID15_PASID_MAPPING__VALID_MASK 0x80000000L +#define ATC_VMID15_PASID_MAPPING__VALID__SHIFT 0x0000001f +#define ATC_VMID1_PASID_MAPPING__PASID_MASK 0x0000ffffL +#define ATC_VMID1_PASID_MAPPING__PASID__SHIFT 0x00000000 +#define ATC_VMID1_PASID_MAPPING__VALID_MASK 0x80000000L +#define ATC_VMID1_PASID_MAPPING__VALID__SHIFT 0x0000001f +#define ATC_VMID2_PASID_MAPPING__PASID_MASK 0x0000ffffL +#define ATC_VMID2_PASID_MAPPING__PASID__SHIFT 0x00000000 +#define ATC_VMID2_PASID_MAPPING__VALID_MASK 0x80000000L +#define ATC_VMID2_PASID_MAPPING__VALID__SHIFT 0x0000001f +#define ATC_VMID3_PASID_MAPPING__PASID_MASK 0x0000ffffL +#define ATC_VMID3_PASID_MAPPING__PASID__SHIFT 0x00000000 +#define ATC_VMID3_PASID_MAPPING__VALID_MASK 0x80000000L +#define ATC_VMID3_PASID_MAPPING__VALID__SHIFT 0x0000001f +#define ATC_VMID4_PASID_MAPPING__PASID_MASK 0x0000ffffL +#define ATC_VMID4_PASID_MAPPING__PASID__SHIFT 0x00000000 +#define ATC_VMID4_PASID_MAPPING__VALID_MASK 0x80000000L +#define ATC_VMID4_PASID_MAPPING__VALID__SHIFT 0x0000001f +#define ATC_VMID5_PASID_MAPPING__PASID_MASK 0x0000ffffL +#define ATC_VMID5_PASID_MAPPING__PASID__SHIFT 0x00000000 +#define ATC_VMID5_PASID_MAPPING__VALID_MASK 0x80000000L +#define ATC_VMID5_PASID_MAPPING__VALID__SHIFT 0x0000001f +#define ATC_VMID6_PASID_MAPPING__PASID_MASK 0x0000ffffL +#define ATC_VMID6_PASID_MAPPING__PASID__SHIFT 0x00000000 +#define ATC_VMID6_PASID_MAPPING__VALID_MASK 0x80000000L +#define ATC_VMID6_PASID_MAPPING__VALID__SHIFT 0x0000001f +#define ATC_VMID7_PASID_MAPPING__PASID_MASK 0x0000ffffL +#define ATC_VMID7_PASID_MAPPING__PASID__SHIFT 0x00000000 +#define ATC_VMID7_PASID_MAPPING__VALID_MASK 0x80000000L +#define ATC_VMID7_PASID_MAPPING__VALID__SHIFT 0x0000001f +#define ATC_VMID8_PASID_MAPPING__PASID_MASK 0x0000ffffL +#define ATC_VMID8_PASID_MAPPING__PASID__SHIFT 0x00000000 +#define ATC_VMID8_PASID_MAPPING__VALID_MASK 0x80000000L +#define ATC_VMID8_PASID_MAPPING__VALID__SHIFT 0x0000001f +#define ATC_VMID9_PASID_MAPPING__PASID_MASK 0x0000ffffL +#define ATC_VMID9_PASID_MAPPING__PASID__SHIFT 0x00000000 +#define ATC_VMID9_PASID_MAPPING__VALID_MASK 0x80000000L +#define ATC_VMID9_PASID_MAPPING__VALID__SHIFT 0x0000001f +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED_MASK 0x00000001L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED__SHIFT 0x00000000 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED_MASK 0x00000400L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT 0x0000000a +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED_MASK 0x00000800L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED__SHIFT 0x0000000b +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED_MASK 0x00001000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED__SHIFT 0x0000000c +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED_MASK 0x00002000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED__SHIFT 0x0000000d +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED_MASK 0x00004000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED__SHIFT 0x0000000e +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED_MASK 0x00008000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED__SHIFT 0x0000000f +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED_MASK 0x00000002L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED__SHIFT 0x00000001 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED_MASK 0x00000004L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED__SHIFT 0x00000002 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED_MASK 0x00000008L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED__SHIFT 0x00000003 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED_MASK 0x00000010L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED__SHIFT 0x00000004 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED_MASK 0x00000020L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED__SHIFT 0x00000005 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED_MASK 0x00000040L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED__SHIFT 0x00000006 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED_MASK 0x00000080L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED__SHIFT 0x00000007 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED_MASK 0x00000100L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED__SHIFT 0x00000008 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED_MASK 0x00000200L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED__SHIFT 0x00000009 +#define CC_MC_MAX_CHANNEL__NOOFCHAN_MASK 0x0000001eL +#define CC_MC_MAX_CHANNEL__NOOFCHAN__SHIFT 0x00000001 +#define DLL_CNTL__DLL_LOCK_TIME_MASK 0x003ff000L +#define DLL_CNTL__DLL_LOCK_TIME__SHIFT 0x0000000c +#define DLL_CNTL__DLL_RESET_TIME_MASK 0x000003ffL +#define DLL_CNTL__DLL_RESET_TIME__SHIFT 0x00000000 +#define DLL_CNTL__MRDCK0_BYPASS_MASK 0x01000000L +#define DLL_CNTL__MRDCK0_BYPASS__SHIFT 0x00000018 +#define DLL_CNTL__MRDCK1_BYPASS_MASK 0x02000000L +#define DLL_CNTL__MRDCK1_BYPASS__SHIFT 0x00000019 +#define DLL_CNTL__PWR2_MODE_MASK 0x04000000L +#define DLL_CNTL__PWR2_MODE__SHIFT 0x0000001a +#define GMCON_DEBUG__GFX_CLEAR_MASK 0x00000002L +#define GMCON_DEBUG__GFX_CLEAR__SHIFT 0x00000001 +#define GMCON_DEBUG__GFX_STALL_MASK 0x00000001L +#define GMCON_DEBUG__GFX_STALL__SHIFT 0x00000000 +#define GMCON_DEBUG__MISC_FLAGS_MASK 0x3ffffffcL +#define GMCON_DEBUG__MISC_FLAGS__SHIFT 0x00000002 +#define GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE0_MASK 0x00000007L +#define GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE0__SHIFT 0x00000000 +#define GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE1_MASK 0x00000038L +#define GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE1__SHIFT 0x00000003 +#define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD_MASK 0x0000fc00L +#define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD__SHIFT 0x0000000a +#define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE_MASK 0x20000000L +#define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE__SHIFT 0x0000001d +#define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY_MASK 0x10000000L +#define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY__SHIFT 0x0000001c +#define GMCON_MISC2__STCTRL_LPT_TARGET_MASK 0x0fff0000L +#define GMCON_MISC2__STCTRL_LPT_TARGET__SHIFT 0x00000010 +#define GMCON_MISC3__RENG_DISABLE_MCC_MASK 0x0000003fL +#define GMCON_MISC3__RENG_DISABLE_MCC__SHIFT 0x00000000 +#define GMCON_MISC3__RENG_DISABLE_MCD_MASK 0x00000fc0L +#define GMCON_MISC3__RENG_DISABLE_MCD__SHIFT 0x00000006 +#define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00fff000L +#define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x0000000c +#define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE_MASK 0x30000000L +#define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x0000001c +#define GMCON_MISC__CRITICAL_REGS_LOCK_MASK 0x08000000L +#define GMCON_MISC__CRITICAL_REGS_LOCK__SHIFT 0x0000001b +#define GMCON_MISC__RENG_EXECUTE_NOW_MODE_MASK 0x00000400L +#define GMCON_MISC__RENG_EXECUTE_NOW_MODE__SHIFT 0x0000000a +#define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00000800L +#define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x0000000b +#define GMCON_MISC__RENG_SRBM_CREDITS_MCD_MASK 0x0000f000L +#define GMCON_MISC__RENG_SRBM_CREDITS_MCD__SHIFT 0x0000000c +#define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR_MASK 0x02000000L +#define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR__SHIFT 0x00000019 +#define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE_MASK 0x04000000L +#define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE__SHIFT 0x0000001a +#define GMCON_MISC__STCTRL_FORCE_ALLOW_SR_MASK 0x40000000L +#define GMCON_MISC__STCTRL_FORCE_ALLOW_SR__SHIFT 0x0000001e +#define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD_MASK 0x00060000L +#define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD__SHIFT 0x00000011 +#define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP_MASK 0x00400000L +#define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP__SHIFT 0x00000016 +#define GMCON_MISC__STCTRL_IGNORE_PRE_SR_MASK 0x00200000L +#define GMCON_MISC__STCTRL_IGNORE_PRE_SR__SHIFT 0x00000015 +#define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x01000000L +#define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0x00000018 +#define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT_MASK 0x00800000L +#define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT__SHIFT 0x00000017 +#define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD_MASK 0x00180000L +#define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD__SHIFT 0x00000013 +#define GMCON_MISC__STCTRL_STUTTER_EN_MASK 0x00010000L +#define GMCON_MISC__STCTRL_STUTTER_EN__SHIFT 0x00000010 +#define GMCON_PERF_MON_CNTL0__ALLOW_WRAP_MASK 0x10000000L +#define GMCON_PERF_MON_CNTL0__ALLOW_WRAP__SHIFT 0x0000001c +#define GMCON_PERF_MON_CNTL0__START_MODE_MASK 0x03000000L +#define GMCON_PERF_MON_CNTL0__START_MODE__SHIFT 0x00000018 +#define GMCON_PERF_MON_CNTL0__START_THRESH_MASK 0x00000fffL +#define GMCON_PERF_MON_CNTL0__START_THRESH__SHIFT 0x00000000 +#define GMCON_PERF_MON_CNTL0__STOP_MODE_MASK 0x0c000000L +#define GMCON_PERF_MON_CNTL0__STOP_MODE__SHIFT 0x0000001a +#define GMCON_PERF_MON_CNTL0__STOP_THRESH_MASK 0x00fff000L +#define GMCON_PERF_MON_CNTL0__STOP_THRESH__SHIFT 0x0000000c +#define GMCON_PERF_MON_CNTL1__MON0_ID_MASK 0x00fc0000L +#define GMCON_PERF_MON_CNTL1__MON0_ID__SHIFT 0x00000012 +#define GMCON_PERF_MON_CNTL1__MON1_ID_MASK 0x3f000000L +#define GMCON_PERF_MON_CNTL1__MON1_ID__SHIFT 0x00000018 +#define GMCON_PERF_MON_CNTL1__START_TRIG_ID_MASK 0x00000fc0L +#define GMCON_PERF_MON_CNTL1__START_TRIG_ID__SHIFT 0x00000006 +#define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID_MASK 0x0003f000L +#define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID__SHIFT 0x0000000c +#define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID_MASK 0x0000003fL +#define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID__SHIFT 0x00000000 +#define GMCON_PERF_MON_RSLT0__COUNT_MASK 0xffffffffL +#define GMCON_PERF_MON_RSLT0__COUNT__SHIFT 0x00000000 +#define GMCON_PERF_MON_RSLT1__COUNT_MASK 0xffffffffL +#define GMCON_PERF_MON_RSLT1__COUNT__SHIFT 0x00000000 +#define GMCON_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000ffL +#define GMCON_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x00000000 +#define GMCON_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L +#define GMCON_PGFSM_CONFIG__P1_SELECT__SHIFT 0x0000000a +#define GMCON_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L +#define GMCON_PGFSM_CONFIG__P2_SELECT__SHIFT 0x0000000b +#define GMCON_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L +#define GMCON_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x00000008 +#define GMCON_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L +#define GMCON_PGFSM_CONFIG__POWER_UP__SHIFT 0x00000009 +#define GMCON_PGFSM_CONFIG__READ_MASK 0x00002000L +#define GMCON_PGFSM_CONFIG__READ__SHIFT 0x0000000d +#define GMCON_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000L +#define GMCON_PGFSM_CONFIG__REG_ADDR__SHIFT 0x0000001c +#define GMCON_PGFSM_CONFIG__RSRVD_MASK 0x07ffc000L +#define GMCON_PGFSM_CONFIG__RSRVD__SHIFT 0x0000000e +#define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L +#define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x0000001b +#define GMCON_PGFSM_CONFIG__WRITE_MASK 0x00001000L +#define GMCON_PGFSM_CONFIG__WRITE__SHIFT 0x0000000c +#define GMCON_PGFSM_READ__PGFSM_SELECT_MASK 0x0f000000L +#define GMCON_PGFSM_READ__PGFSM_SELECT__SHIFT 0x00000018 +#define GMCON_PGFSM_READ__READ_VALUE_MASK 0x00ffffffL +#define GMCON_PGFSM_READ__READ_VALUE__SHIFT 0x00000000 +#define GMCON_PGFSM_READ__SERDES_MASTER_BUSY_MASK 0x10000000L +#define GMCON_PGFSM_READ__SERDES_MASTER_BUSY__SHIFT 0x0000001c +#define GMCON_PGFSM_WRITE__WRITE_VALUE_MASK 0xffffffffL +#define GMCON_PGFSM_WRITE__WRITE_VALUE__SHIFT 0x00000000 +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR_MASK 0x003ff000L +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR__SHIFT 0x0000000c +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0xffc00000L +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0x00000016 +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000002L +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x00000001 +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000ffcL +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x00000002 +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x00000001L +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x00000000 +#define GMCON_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xffffffffL +#define GMCON_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x00000000 +#define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003ffL +#define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x00000000 +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000ffffL +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x00000000 +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xffff0000L +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x00000010 +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000ffffL +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x00000000 +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xffff0000L +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x00000010 +#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0_MASK 0x0000ffffL +#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0__SHIFT 0x00000000 +#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0_MASK 0xffff0000L +#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0__SHIFT 0x00000010 +#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1_MASK 0x0000ffffL +#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1__SHIFT 0x00000000 +#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1_MASK 0xffff0000L +#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1__SHIFT 0x00000010 +#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2_MASK 0x0000ffffL +#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2__SHIFT 0x00000000 +#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2_MASK 0xffff0000L +#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2__SHIFT 0x00000010 +#define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE_MASK 0x0000000fL +#define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE__SHIFT 0x00000000 +#define MC_ARB_ADDR_HASH__COL_XOR_MASK 0x00000ff0L +#define MC_ARB_ADDR_HASH__COL_XOR__SHIFT 0x00000004 +#define MC_ARB_ADDR_HASH__ROW_XOR_MASK 0x0ffff000L +#define MC_ARB_ADDR_HASH__ROW_XOR__SHIFT 0x0000000c +#define MC_ARB_AGE_RD__DIVIDE_GROUP0_MASK 0x01000000L +#define MC_ARB_AGE_RD__DIVIDE_GROUP0__SHIFT 0x00000018 +#define MC_ARB_AGE_RD__DIVIDE_GROUP1_MASK 0x02000000L +#define MC_ARB_AGE_RD__DIVIDE_GROUP1__SHIFT 0x00000019 +#define MC_ARB_AGE_RD__DIVIDE_GROUP2_MASK 0x04000000L +#define MC_ARB_AGE_RD__DIVIDE_GROUP2__SHIFT 0x0000001a +#define MC_ARB_AGE_RD__DIVIDE_GROUP3_MASK 0x08000000L +#define MC_ARB_AGE_RD__DIVIDE_GROUP3__SHIFT 0x0000001b +#define MC_ARB_AGE_RD__DIVIDE_GROUP4_MASK 0x10000000L +#define MC_ARB_AGE_RD__DIVIDE_GROUP4__SHIFT 0x0000001c +#define MC_ARB_AGE_RD__DIVIDE_GROUP5_MASK 0x20000000L +#define MC_ARB_AGE_RD__DIVIDE_GROUP5__SHIFT 0x0000001d +#define MC_ARB_AGE_RD__DIVIDE_GROUP6_MASK 0x40000000L +#define MC_ARB_AGE_RD__DIVIDE_GROUP6__SHIFT 0x0000001e +#define MC_ARB_AGE_RD__DIVIDE_GROUP7_MASK 0x80000000L +#define MC_ARB_AGE_RD__DIVIDE_GROUP7__SHIFT 0x0000001f +#define MC_ARB_AGE_RD__ENABLE_GROUP0_MASK 0x00010000L +#define MC_ARB_AGE_RD__ENABLE_GROUP0__SHIFT 0x00000010 +#define MC_ARB_AGE_RD__ENABLE_GROUP1_MASK 0x00020000L +#define MC_ARB_AGE_RD__ENABLE_GROUP1__SHIFT 0x00000011 +#define MC_ARB_AGE_RD__ENABLE_GROUP2_MASK 0x00040000L +#define MC_ARB_AGE_RD__ENABLE_GROUP2__SHIFT 0x00000012 +#define MC_ARB_AGE_RD__ENABLE_GROUP3_MASK 0x00080000L +#define MC_ARB_AGE_RD__ENABLE_GROUP3__SHIFT 0x00000013 +#define MC_ARB_AGE_RD__ENABLE_GROUP4_MASK 0x00100000L +#define MC_ARB_AGE_RD__ENABLE_GROUP4__SHIFT 0x00000014 +#define MC_ARB_AGE_RD__ENABLE_GROUP5_MASK 0x00200000L +#define MC_ARB_AGE_RD__ENABLE_GROUP5__SHIFT 0x00000015 +#define MC_ARB_AGE_RD__ENABLE_GROUP6_MASK 0x00400000L +#define MC_ARB_AGE_RD__ENABLE_GROUP6__SHIFT 0x00000016 +#define MC_ARB_AGE_RD__ENABLE_GROUP7_MASK 0x00800000L +#define MC_ARB_AGE_RD__ENABLE_GROUP7__SHIFT 0x00000017 +#define MC_ARB_AGE_RD__RATE_GROUP0_MASK 0x00000003L +#define MC_ARB_AGE_RD__RATE_GROUP0__SHIFT 0x00000000 +#define MC_ARB_AGE_RD__RATE_GROUP1_MASK 0x0000000cL +#define MC_ARB_AGE_RD__RATE_GROUP1__SHIFT 0x00000002 +#define MC_ARB_AGE_RD__RATE_GROUP2_MASK 0x00000030L +#define MC_ARB_AGE_RD__RATE_GROUP2__SHIFT 0x00000004 +#define MC_ARB_AGE_RD__RATE_GROUP3_MASK 0x000000c0L +#define MC_ARB_AGE_RD__RATE_GROUP3__SHIFT 0x00000006 +#define MC_ARB_AGE_RD__RATE_GROUP4_MASK 0x00000300L +#define MC_ARB_AGE_RD__RATE_GROUP4__SHIFT 0x00000008 +#define MC_ARB_AGE_RD__RATE_GROUP5_MASK 0x00000c00L +#define MC_ARB_AGE_RD__RATE_GROUP5__SHIFT 0x0000000a +#define MC_ARB_AGE_RD__RATE_GROUP6_MASK 0x00003000L +#define MC_ARB_AGE_RD__RATE_GROUP6__SHIFT 0x0000000c +#define MC_ARB_AGE_RD__RATE_GROUP7_MASK 0x0000c000L +#define MC_ARB_AGE_RD__RATE_GROUP7__SHIFT 0x0000000e +#define MC_ARB_AGE_WR__DIVIDE_GROUP0_MASK 0x01000000L +#define MC_ARB_AGE_WR__DIVIDE_GROUP0__SHIFT 0x00000018 +#define MC_ARB_AGE_WR__DIVIDE_GROUP1_MASK 0x02000000L +#define MC_ARB_AGE_WR__DIVIDE_GROUP1__SHIFT 0x00000019 +#define MC_ARB_AGE_WR__DIVIDE_GROUP2_MASK 0x04000000L +#define MC_ARB_AGE_WR__DIVIDE_GROUP2__SHIFT 0x0000001a +#define MC_ARB_AGE_WR__DIVIDE_GROUP3_MASK 0x08000000L +#define MC_ARB_AGE_WR__DIVIDE_GROUP3__SHIFT 0x0000001b +#define MC_ARB_AGE_WR__DIVIDE_GROUP4_MASK 0x10000000L +#define MC_ARB_AGE_WR__DIVIDE_GROUP4__SHIFT 0x0000001c +#define MC_ARB_AGE_WR__DIVIDE_GROUP5_MASK 0x20000000L +#define MC_ARB_AGE_WR__DIVIDE_GROUP5__SHIFT 0x0000001d +#define MC_ARB_AGE_WR__DIVIDE_GROUP6_MASK 0x40000000L +#define MC_ARB_AGE_WR__DIVIDE_GROUP6__SHIFT 0x0000001e +#define MC_ARB_AGE_WR__DIVIDE_GROUP7_MASK 0x80000000L +#define MC_ARB_AGE_WR__DIVIDE_GROUP7__SHIFT 0x0000001f +#define MC_ARB_AGE_WR__ENABLE_GROUP0_MASK 0x00010000L +#define MC_ARB_AGE_WR__ENABLE_GROUP0__SHIFT 0x00000010 +#define MC_ARB_AGE_WR__ENABLE_GROUP1_MASK 0x00020000L +#define MC_ARB_AGE_WR__ENABLE_GROUP1__SHIFT 0x00000011 +#define MC_ARB_AGE_WR__ENABLE_GROUP2_MASK 0x00040000L +#define MC_ARB_AGE_WR__ENABLE_GROUP2__SHIFT 0x00000012 +#define MC_ARB_AGE_WR__ENABLE_GROUP3_MASK 0x00080000L +#define MC_ARB_AGE_WR__ENABLE_GROUP3__SHIFT 0x00000013 +#define MC_ARB_AGE_WR__ENABLE_GROUP4_MASK 0x00100000L +#define MC_ARB_AGE_WR__ENABLE_GROUP4__SHIFT 0x00000014 +#define MC_ARB_AGE_WR__ENABLE_GROUP5_MASK 0x00200000L +#define MC_ARB_AGE_WR__ENABLE_GROUP5__SHIFT 0x00000015 +#define MC_ARB_AGE_WR__ENABLE_GROUP6_MASK 0x00400000L +#define MC_ARB_AGE_WR__ENABLE_GROUP6__SHIFT 0x00000016 +#define MC_ARB_AGE_WR__ENABLE_GROUP7_MASK 0x00800000L +#define MC_ARB_AGE_WR__ENABLE_GROUP7__SHIFT 0x00000017 +#define MC_ARB_AGE_WR__RATE_GROUP0_MASK 0x00000003L +#define MC_ARB_AGE_WR__RATE_GROUP0__SHIFT 0x00000000 +#define MC_ARB_AGE_WR__RATE_GROUP1_MASK 0x0000000cL +#define MC_ARB_AGE_WR__RATE_GROUP1__SHIFT 0x00000002 +#define MC_ARB_AGE_WR__RATE_GROUP2_MASK 0x00000030L +#define MC_ARB_AGE_WR__RATE_GROUP2__SHIFT 0x00000004 +#define MC_ARB_AGE_WR__RATE_GROUP3_MASK 0x000000c0L +#define MC_ARB_AGE_WR__RATE_GROUP3__SHIFT 0x00000006 +#define MC_ARB_AGE_WR__RATE_GROUP4_MASK 0x00000300L +#define MC_ARB_AGE_WR__RATE_GROUP4__SHIFT 0x00000008 +#define MC_ARB_AGE_WR__RATE_GROUP5_MASK 0x00000c00L +#define MC_ARB_AGE_WR__RATE_GROUP5__SHIFT 0x0000000a +#define MC_ARB_AGE_WR__RATE_GROUP6_MASK 0x00003000L +#define MC_ARB_AGE_WR__RATE_GROUP6__SHIFT 0x0000000c +#define MC_ARB_AGE_WR__RATE_GROUP7_MASK 0x0000c000L +#define MC_ARB_AGE_WR__RATE_GROUP7__SHIFT 0x0000000e +#define MC_ARB_BANKMAP__BANK0_MASK 0x0000000fL +#define MC_ARB_BANKMAP__BANK0__SHIFT 0x00000000 +#define MC_ARB_BANKMAP__BANK1_MASK 0x000000f0L +#define MC_ARB_BANKMAP__BANK1__SHIFT 0x00000004 +#define MC_ARB_BANKMAP__BANK2_MASK 0x00000f00L +#define MC_ARB_BANKMAP__BANK2__SHIFT 0x00000008 +#define MC_ARB_BANKMAP__BANK3_MASK 0x0000f000L +#define MC_ARB_BANKMAP__BANK3__SHIFT 0x0000000c +#define MC_ARB_BANKMAP__RANK_MASK 0x000f0000L +#define MC_ARB_BANKMAP__RANK__SHIFT 0x00000010 +#define MC_ARB_BURST_TIME__STATE0_MASK 0x0000001fL +#define MC_ARB_BURST_TIME__STATE0__SHIFT 0x00000000 +#define MC_ARB_BURST_TIME__STATE1_MASK 0x000003e0L +#define MC_ARB_BURST_TIME__STATE1__SHIFT 0x00000005 +#define MC_ARB_BURST_TIME__STATE2_MASK 0x00007c00L +#define MC_ARB_BURST_TIME__STATE2__SHIFT 0x0000000a +#define MC_ARB_BURST_TIME__STATE3_MASK 0x000f8000L +#define MC_ARB_BURST_TIME__STATE3__SHIFT 0x0000000f +#define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW_MASK 0x00002000L +#define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW__SHIFT 0x0000000d +#define MC_ARB_CAC_CNTL__ENABLE_MASK 0x00000001L +#define MC_ARB_CAC_CNTL__ENABLE__SHIFT 0x00000000 +#define MC_ARB_CAC_CNTL__READ_WEIGHT_MASK 0x0000007eL +#define MC_ARB_CAC_CNTL__READ_WEIGHT__SHIFT 0x00000001 +#define MC_ARB_CAC_CNTL__WRITE_WEIGHT_MASK 0x00001f80L +#define MC_ARB_CAC_CNTL__WRITE_WEIGHT__SHIFT 0x00000007 +#define MC_ARB_CG__CG_ARB_REQ_MASK 0x000000ffL +#define MC_ARB_CG__CG_ARB_REQ__SHIFT 0x00000000 +#define MC_ARB_CG__CG_ARB_RESP_MASK 0x0000ff00L +#define MC_ARB_CG__CG_ARB_RESP__SHIFT 0x00000008 +#define MC_ARB_DRAM_TIMING_1__ACTRD_MASK 0x000000ffL +#define MC_ARB_DRAM_TIMING_1__ACTRD__SHIFT 0x00000000 +#define MC_ARB_DRAM_TIMING_1__ACTWR_MASK 0x0000ff00L +#define MC_ARB_DRAM_TIMING_1__ACTWR__SHIFT 0x00000008 +#define MC_ARB_DRAM_TIMING_1__RASMACTRD_MASK 0x00ff0000L +#define MC_ARB_DRAM_TIMING_1__RASMACTRD__SHIFT 0x00000010 +#define MC_ARB_DRAM_TIMING_1__RASMACTWR_MASK 0xff000000L +#define MC_ARB_DRAM_TIMING_1__RASMACTWR__SHIFT 0x00000018 +#define MC_ARB_DRAM_TIMING2_1__BUS_TURN_MASK 0x1f000000L +#define MC_ARB_DRAM_TIMING2_1__BUS_TURN__SHIFT 0x00000018 +#define MC_ARB_DRAM_TIMING2_1__RAS2RAS_MASK 0x000000ffL +#define MC_ARB_DRAM_TIMING2_1__RAS2RAS__SHIFT 0x00000000 +#define MC_ARB_DRAM_TIMING2_1__RP_MASK 0x0000ff00L +#define MC_ARB_DRAM_TIMING2_1__RP__SHIFT 0x00000008 +#define MC_ARB_DRAM_TIMING2_1__WRPLUSRP_MASK 0x00ff0000L +#define MC_ARB_DRAM_TIMING2_1__WRPLUSRP__SHIFT 0x00000010 +#define MC_ARB_DRAM_TIMING2__BUS_TURN_MASK 0x1f000000L +#define MC_ARB_DRAM_TIMING2__BUS_TURN__SHIFT 0x00000018 +#define MC_ARB_DRAM_TIMING2__RAS2RAS_MASK 0x000000ffL +#define MC_ARB_DRAM_TIMING2__RAS2RAS__SHIFT 0x00000000 +#define MC_ARB_DRAM_TIMING2__RP_MASK 0x0000ff00L +#define MC_ARB_DRAM_TIMING2__RP__SHIFT 0x00000008 +#define MC_ARB_DRAM_TIMING2__WRPLUSRP_MASK 0x00ff0000L +#define MC_ARB_DRAM_TIMING2__WRPLUSRP__SHIFT 0x00000010 +#define MC_ARB_DRAM_TIMING__ACTRD_MASK 0x000000ffL +#define MC_ARB_DRAM_TIMING__ACTRD__SHIFT 0x00000000 +#define MC_ARB_DRAM_TIMING__ACTWR_MASK 0x0000ff00L +#define MC_ARB_DRAM_TIMING__ACTWR__SHIFT 0x00000008 +#define MC_ARB_DRAM_TIMING__RASMACTRD_MASK 0x00ff0000L +#define MC_ARB_DRAM_TIMING__RASMACTRD__SHIFT 0x00000010 +#define MC_ARB_DRAM_TIMING__RASMACTWR_MASK 0xff000000L +#define MC_ARB_DRAM_TIMING__RASMACTWR__SHIFT 0x00000018 +#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE_MASK 0x00000010L +#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE__SHIFT 0x00000004 +#define MC_ARB_FED_CNTL__MODE_MASK 0x00000003L +#define MC_ARB_FED_CNTL__MODE__SHIFT 0x00000000 +#define MC_ARB_FED_CNTL__WR_ERR_MASK 0x0000000cL +#define MC_ARB_FED_CNTL__WR_ERR__SHIFT 0x00000002 +#define MC_ARB_GDEC_RD_CNTL__PAGEBIT0_MASK 0x0000000fL +#define MC_ARB_GDEC_RD_CNTL__PAGEBIT0__SHIFT 0x00000000 +#define MC_ARB_GDEC_RD_CNTL__PAGEBIT1_MASK 0x000000f0L +#define MC_ARB_GDEC_RD_CNTL__PAGEBIT1__SHIFT 0x00000004 +#define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP_MASK 0x00003c00L +#define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP__SHIFT 0x0000000a +#define MC_ARB_GDEC_RD_CNTL__USE_RANK_MASK 0x00000100L +#define MC_ARB_GDEC_RD_CNTL__USE_RANK__SHIFT 0x00000008 +#define MC_ARB_GDEC_RD_CNTL__USE_RSNO_MASK 0x00000200L +#define MC_ARB_GDEC_RD_CNTL__USE_RSNO__SHIFT 0x00000009 +#define MC_ARB_GDEC_WR_CNTL__PAGEBIT0_MASK 0x0000000fL +#define MC_ARB_GDEC_WR_CNTL__PAGEBIT0__SHIFT 0x00000000 +#define MC_ARB_GDEC_WR_CNTL__PAGEBIT1_MASK 0x000000f0L +#define MC_ARB_GDEC_WR_CNTL__PAGEBIT1__SHIFT 0x00000004 +#define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP_MASK 0x00003c00L +#define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP__SHIFT 0x0000000a +#define MC_ARB_GDEC_WR_CNTL__USE_RANK_MASK 0x00000100L +#define MC_ARB_GDEC_WR_CNTL__USE_RANK__SHIFT 0x00000008 +#define MC_ARB_GDEC_WR_CNTL__USE_RSNO_MASK 0x00000200L +#define MC_ARB_GDEC_WR_CNTL__USE_RSNO__SHIFT 0x00000009 +#define MC_ARB_GECC2_CLI__NO_GECC_CLI0_MASK 0x000000ffL +#define MC_ARB_GECC2_CLI__NO_GECC_CLI0__SHIFT 0x00000000 +#define MC_ARB_GECC2_CLI__NO_GECC_CLI1_MASK 0x0000ff00L +#define MC_ARB_GECC2_CLI__NO_GECC_CLI1__SHIFT 0x00000008 +#define MC_ARB_GECC2_CLI__NO_GECC_CLI2_MASK 0x00ff0000L +#define MC_ARB_GECC2_CLI__NO_GECC_CLI2__SHIFT 0x00000010 +#define MC_ARB_GECC2_CLI__NO_GECC_CLI3_MASK 0xff000000L +#define MC_ARB_GECC2_CLI__NO_GECC_CLI3__SHIFT 0x00000018 +#define MC_ARB_GECC2__CLOSE_BANK_RMW_MASK 0x00004000L +#define MC_ARB_GECC2__CLOSE_BANK_RMW__SHIFT 0x0000000e +#define MC_ARB_GECC2__COLFIFO_WATER_MASK 0x001f8000L +#define MC_ARB_GECC2__COLFIFO_WATER__SHIFT 0x0000000f +#define MC_ARB_GECC2_DEBUG2__ERR0_START_MASK 0x0000ff00L +#define MC_ARB_GECC2_DEBUG2__ERR0_START__SHIFT 0x00000008 +#define MC_ARB_GECC2_DEBUG2__ERR1_START_MASK 0x00ff0000L +#define MC_ARB_GECC2_DEBUG2__ERR1_START__SHIFT 0x00000010 +#define MC_ARB_GECC2_DEBUG2__ERR2_START_MASK 0xff000000L +#define MC_ARB_GECC2_DEBUG2__ERR2_START__SHIFT 0x00000018 +#define MC_ARB_GECC2_DEBUG2__PERIOD_MASK 0x000000ffL +#define MC_ARB_GECC2_DEBUG2__PERIOD__SHIFT 0x00000000 +#define MC_ARB_GECC2_DEBUG__DATA_FIELD_MASK 0x00000018L +#define MC_ARB_GECC2_DEBUG__DATA_FIELD__SHIFT 0x00000003 +#define MC_ARB_GECC2_DEBUG__DIRECTION_MASK 0x00000004L +#define MC_ARB_GECC2_DEBUG__DIRECTION__SHIFT 0x00000002 +#define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS_MASK 0x00000003L +#define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS__SHIFT 0x00000000 +#define MC_ARB_GECC2_DEBUG__SW_INJECTION_MASK 0x00000020L +#define MC_ARB_GECC2_DEBUG__SW_INJECTION__SHIFT 0x00000005 +#define MC_ARB_GECC2__ECC_MODE_MASK 0x00000006L +#define MC_ARB_GECC2__ECC_MODE__SHIFT 0x00000001 +#define MC_ARB_GECC2__ENABLE_MASK 0x00000001L +#define MC_ARB_GECC2__ENABLE__SHIFT 0x00000000 +#define MC_ARB_GECC2__EXOR_BANK_SEL_MASK 0x00000060L +#define MC_ARB_GECC2__EXOR_BANK_SEL__SHIFT 0x00000005 +#define MC_ARB_GECC2_MISC__STREAK_BREAK_MASK 0x0000000fL +#define MC_ARB_GECC2_MISC__STREAK_BREAK__SHIFT 0x00000000 +#define MC_ARB_GECC2__NO_GECC_CLI_MASK 0x00000780L +#define MC_ARB_GECC2__NO_GECC_CLI__SHIFT 0x00000007 +#define MC_ARB_GECC2__PAGE_BIT0_MASK 0x00000018L +#define MC_ARB_GECC2__PAGE_BIT0__SHIFT 0x00000003 +#define MC_ARB_GECC2__READ_ERR_MASK 0x00003800L +#define MC_ARB_GECC2__READ_ERR__SHIFT 0x0000000b +#define MC_ARB_GECC2_STATUS__CORR_CLEAR0_MASK 0x00000100L +#define MC_ARB_GECC2_STATUS__CORR_CLEAR0__SHIFT 0x00000008 +#define MC_ARB_GECC2_STATUS__CORR_CLEAR1_MASK 0x00001000L +#define MC_ARB_GECC2_STATUS__CORR_CLEAR1__SHIFT 0x0000000c +#define MC_ARB_GECC2_STATUS__CORR_STS0_MASK 0x00000001L +#define MC_ARB_GECC2_STATUS__CORR_STS0__SHIFT 0x00000000 +#define MC_ARB_GECC2_STATUS__CORR_STS1_MASK 0x00000010L +#define MC_ARB_GECC2_STATUS__CORR_STS1__SHIFT 0x00000004 +#define MC_ARB_GECC2_STATUS__FED_CLEAR0_MASK 0x00000400L +#define MC_ARB_GECC2_STATUS__FED_CLEAR0__SHIFT 0x0000000a +#define MC_ARB_GECC2_STATUS__FED_CLEAR1_MASK 0x00004000L +#define MC_ARB_GECC2_STATUS__FED_CLEAR1__SHIFT 0x0000000e +#define MC_ARB_GECC2_STATUS__FED_STS0_MASK 0x00000004L +#define MC_ARB_GECC2_STATUS__FED_STS0__SHIFT 0x00000002 +#define MC_ARB_GECC2_STATUS__FED_STS1_MASK 0x00000040L +#define MC_ARB_GECC2_STATUS__FED_STS1__SHIFT 0x00000006 +#define MC_ARB_GECC2_STATUS__RSVD0_MASK 0x00000008L +#define MC_ARB_GECC2_STATUS__RSVD0__SHIFT 0x00000003 +#define MC_ARB_GECC2_STATUS__RSVD1_MASK 0x00000080L +#define MC_ARB_GECC2_STATUS__RSVD1__SHIFT 0x00000007 +#define MC_ARB_GECC2_STATUS__RSVD2_MASK 0x00000800L +#define MC_ARB_GECC2_STATUS__RSVD2__SHIFT 0x0000000b +#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0_MASK 0x00000200L +#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0__SHIFT 0x00000009 +#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1_MASK 0x00002000L +#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1__SHIFT 0x0000000d +#define MC_ARB_GECC2_STATUS__UNCORR_STS0_MASK 0x00000002L +#define MC_ARB_GECC2_STATUS__UNCORR_STS0__SHIFT 0x00000001 +#define MC_ARB_GECC2_STATUS__UNCORR_STS1_MASK 0x00000020L +#define MC_ARB_GECC2_STATUS__UNCORR_STS1__SHIFT 0x00000005 +#define MC_ARB_LAZY0_RD__GROUP0_MASK 0x000000ffL +#define MC_ARB_LAZY0_RD__GROUP0__SHIFT 0x00000000 +#define MC_ARB_LAZY0_RD__GROUP1_MASK 0x0000ff00L +#define MC_ARB_LAZY0_RD__GROUP1__SHIFT 0x00000008 +#define MC_ARB_LAZY0_RD__GROUP2_MASK 0x00ff0000L +#define MC_ARB_LAZY0_RD__GROUP2__SHIFT 0x00000010 +#define MC_ARB_LAZY0_RD__GROUP3_MASK 0xff000000L +#define MC_ARB_LAZY0_RD__GROUP3__SHIFT 0x00000018 +#define MC_ARB_LAZY0_WR__GROUP0_MASK 0x000000ffL +#define MC_ARB_LAZY0_WR__GROUP0__SHIFT 0x00000000 +#define MC_ARB_LAZY0_WR__GROUP1_MASK 0x0000ff00L +#define MC_ARB_LAZY0_WR__GROUP1__SHIFT 0x00000008 +#define MC_ARB_LAZY0_WR__GROUP2_MASK 0x00ff0000L +#define MC_ARB_LAZY0_WR__GROUP2__SHIFT 0x00000010 +#define MC_ARB_LAZY0_WR__GROUP3_MASK 0xff000000L +#define MC_ARB_LAZY0_WR__GROUP3__SHIFT 0x00000018 +#define MC_ARB_LAZY1_RD__GROUP4_MASK 0x000000ffL +#define MC_ARB_LAZY1_RD__GROUP4__SHIFT 0x00000000 +#define MC_ARB_LAZY1_RD__GROUP5_MASK 0x0000ff00L +#define MC_ARB_LAZY1_RD__GROUP5__SHIFT 0x00000008 +#define MC_ARB_LAZY1_RD__GROUP6_MASK 0x00ff0000L +#define MC_ARB_LAZY1_RD__GROUP6__SHIFT 0x00000010 +#define MC_ARB_LAZY1_RD__GROUP7_MASK 0xff000000L +#define MC_ARB_LAZY1_RD__GROUP7__SHIFT 0x00000018 +#define MC_ARB_LAZY1_WR__GROUP4_MASK 0x000000ffL +#define MC_ARB_LAZY1_WR__GROUP4__SHIFT 0x00000000 +#define MC_ARB_LAZY1_WR__GROUP5_MASK 0x0000ff00L +#define MC_ARB_LAZY1_WR__GROUP5__SHIFT 0x00000008 +#define MC_ARB_LAZY1_WR__GROUP6_MASK 0x00ff0000L +#define MC_ARB_LAZY1_WR__GROUP6__SHIFT 0x00000010 +#define MC_ARB_LAZY1_WR__GROUP7_MASK 0xff000000L +#define MC_ARB_LAZY1_WR__GROUP7__SHIFT 0x00000018 +#define MC_ARB_LM_RD__BANKGROUP_CONFIG_MASK 0x00e00000L +#define MC_ARB_LM_RD__BANKGROUP_CONFIG__SHIFT 0x00000015 +#define MC_ARB_LM_RD__ENABLE_TWO_LIST_MASK 0x00040000L +#define MC_ARB_LM_RD__ENABLE_TWO_LIST__SHIFT 0x00000012 +#define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST_MASK 0x00080000L +#define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST__SHIFT 0x00000013 +#define MC_ARB_LM_RD__SKID1_RST_TWOLIST_MASK 0x00100000L +#define MC_ARB_LM_RD__SKID1_RST_TWOLIST__SHIFT 0x00000014 +#define MC_ARB_LM_RD__STREAK_BREAK_MASK 0x00010000L +#define MC_ARB_LM_RD__STREAK_BREAK__SHIFT 0x00000010 +#define MC_ARB_LM_RD__STREAK_LIMIT_MASK 0x000000ffL +#define MC_ARB_LM_RD__STREAK_LIMIT__SHIFT 0x00000000 +#define MC_ARB_LM_RD__STREAK_LIMIT_UBER_MASK 0x0000ff00L +#define MC_ARB_LM_RD__STREAK_LIMIT_UBER__SHIFT 0x00000008 +#define MC_ARB_LM_RD__STREAK_UBER_MASK 0x00020000L +#define MC_ARB_LM_RD__STREAK_UBER__SHIFT 0x00000011 +#define MC_ARB_LM_WR__BANKGROUP_CONFIG_MASK 0x00e00000L +#define MC_ARB_LM_WR__BANKGROUP_CONFIG__SHIFT 0x00000015 +#define MC_ARB_LM_WR__ENABLE_TWO_LIST_MASK 0x00040000L +#define MC_ARB_LM_WR__ENABLE_TWO_LIST__SHIFT 0x00000012 +#define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST_MASK 0x00080000L +#define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST__SHIFT 0x00000013 +#define MC_ARB_LM_WR__SKID1_RST_TWOLIST_MASK 0x00100000L +#define MC_ARB_LM_WR__SKID1_RST_TWOLIST__SHIFT 0x00000014 +#define MC_ARB_LM_WR__STREAK_BREAK_MASK 0x00010000L +#define MC_ARB_LM_WR__STREAK_BREAK__SHIFT 0x00000010 +#define MC_ARB_LM_WR__STREAK_LIMIT_MASK 0x000000ffL +#define MC_ARB_LM_WR__STREAK_LIMIT__SHIFT 0x00000000 +#define MC_ARB_LM_WR__STREAK_LIMIT_UBER_MASK 0x0000ff00L +#define MC_ARB_LM_WR__STREAK_LIMIT_UBER__SHIFT 0x00000008 +#define MC_ARB_LM_WR__STREAK_UBER_MASK 0x00020000L +#define MC_ARB_LM_WR__STREAK_UBER__SHIFT 0x00000011 +#define MC_ARB_MINCLKS__ARB_RW_SWITCH_MASK 0x00010000L +#define MC_ARB_MINCLKS__ARB_RW_SWITCH__SHIFT 0x00000010 +#define MC_ARB_MINCLKS__READ_CLKS_MASK 0x000000ffL +#define MC_ARB_MINCLKS__READ_CLKS__SHIFT 0x00000000 +#define MC_ARB_MINCLKS__WRITE_CLKS_MASK 0x0000ff00L +#define MC_ARB_MINCLKS__WRITE_CLKS__SHIFT 0x00000008 +#define MC_ARB_MISC2__ARB_DEBUG29_MASK 0x20000000L +#define MC_ARB_MISC2__ARB_DEBUG29__SHIFT 0x0000001d +#define MC_ARB_MISC2__GECC_MASK 0x00040000L +#define MC_ARB_MISC2__GECC_RST_MASK 0x00080000L +#define MC_ARB_MISC2__GECC_RST__SHIFT 0x00000013 +#define MC_ARB_MISC2__GECC__SHIFT 0x00000012 +#define MC_ARB_MISC2__GECC_STATUS_MASK 0x00100000L +#define MC_ARB_MISC2__GECC_STATUS__SHIFT 0x00000014 +#define MC_ARB_MISC2__POP_IDLE_REPLAY_MASK 0x00000800L +#define MC_ARB_MISC2__POP_IDLE_REPLAY__SHIFT 0x0000000b +#define MC_ARB_MISC2__RDRET_NO_BP_MASK 0x00002000L +#define MC_ARB_MISC2__RDRET_NO_BP__SHIFT 0x0000000d +#define MC_ARB_MISC2__RDRET_NO_REORDERING_MASK 0x00001000L +#define MC_ARB_MISC2__RDRET_NO_REORDERING__SHIFT 0x0000000c +#define MC_ARB_MISC2__RDRET_SEQ_SKID_MASK 0x0003c000L +#define MC_ARB_MISC2__RDRET_SEQ_SKID__SHIFT 0x0000000e +#define MC_ARB_MISC2__REPLAY_DEBUG_MASK 0x10000000L +#define MC_ARB_MISC2__REPLAY_DEBUG__SHIFT 0x0000001c +#define MC_ARB_MISC2__SEQ_RDY_POP_IDLE_MASK 0x40000000L +#define MC_ARB_MISC2__SEQ_RDY_POP_IDLE__SHIFT 0x0000001e +#define MC_ARB_MISC2__TAGFIFO_THRESHOLD_MASK 0x01e00000L +#define MC_ARB_MISC2__TAGFIFO_THRESHOLD__SHIFT 0x00000015 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4_MASK 0x00000040L +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4__SHIFT 0x00000006 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5_MASK 0x00000080L +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5__SHIFT 0x00000007 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6_MASK 0x00000100L +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6__SHIFT 0x00000008 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7_MASK 0x00000200L +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7__SHIFT 0x00000009 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8_MASK 0x00000400L +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8__SHIFT 0x0000000a +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE_MASK 0x00000020L +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE__SHIFT 0x00000005 +#define MC_ARB_MISC2__TCCDL4_REPLAY_EOB_MASK 0x80000000L +#define MC_ARB_MISC2__TCCDL4_REPLAY_EOB__SHIFT 0x0000001f +#define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT_MASK 0x0e000000L +#define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT__SHIFT 0x00000019 +#define MC_ARB_MISC__CALI_ENABLE_MASK 0x00100000L +#define MC_ARB_MISC__CALI_ENABLE__SHIFT 0x00000014 +#define MC_ARB_MISC__CALI_RATES_MASK 0x00600000L +#define MC_ARB_MISC__CALI_RATES__SHIFT 0x00000015 +#define MC_ARB_MISC__CHAN_COUPLE_MASK 0x000007f8L +#define MC_ARB_MISC__CHAN_COUPLE__SHIFT 0x00000003 +#define MC_ARB_MISC__DISPURG_NOSW2WR_MASK 0x01000000L +#define MC_ARB_MISC__DISPURG_NOSW2WR__SHIFT 0x00000018 +#define MC_ARB_MISC__DISPURG_STALL_MASK 0x02000000L +#define MC_ARB_MISC__DISPURG_STALL__SHIFT 0x00000019 +#define MC_ARB_MISC__DISPURG_THROTTLE_MASK 0x3c000000L +#define MC_ARB_MISC__DISPURG_THROTTLE__SHIFT 0x0000001a +#define MC_ARB_MISC__DISPURGVLD_NOWRT_MASK 0x00800000L +#define MC_ARB_MISC__DISPURGVLD_NOWRT__SHIFT 0x00000017 +#define MC_ARB_MISC__HARSHNESS_MASK 0x0007f800L +#define MC_ARB_MISC__HARSHNESS__SHIFT 0x0000000b +#define MC_ARB_MISC__IDLE_RFSH_MASK 0x00000002L +#define MC_ARB_MISC__IDLE_RFSH__SHIFT 0x00000001 +#define MC_ARB_MISC__SMART_RDWR_SW_MASK 0x00080000L +#define MC_ARB_MISC__SMART_RDWR_SW__SHIFT 0x00000013 +#define MC_ARB_MISC__STICKY_RFSH_MASK 0x00000001L +#define MC_ARB_MISC__STICKY_RFSH__SHIFT 0x00000000 +#define MC_ARB_MISC__STUTTER_RFSH_MASK 0x00000004L +#define MC_ARB_MISC__STUTTER_RFSH__SHIFT 0x00000002 +#define MC_ARB_PM_CNTL__BLKOUT_ON_D1_MASK 0x00000020L +#define MC_ARB_PM_CNTL__BLKOUT_ON_D1__SHIFT 0x00000005 +#define MC_ARB_PM_CNTL__IDLE_CNT_MASK 0x00f00000L +#define MC_ARB_PM_CNTL__IDLE_CNT__SHIFT 0x00000014 +#define MC_ARB_PM_CNTL__IDLE_ON_D1_MASK 0x00000040L +#define MC_ARB_PM_CNTL__IDLE_ON_D1__SHIFT 0x00000006 +#define MC_ARB_PM_CNTL__IDLE_ON_D2_MASK 0x00040000L +#define MC_ARB_PM_CNTL__IDLE_ON_D2__SHIFT 0x00000012 +#define MC_ARB_PM_CNTL__IDLE_ON_D3_MASK 0x00080000L +#define MC_ARB_PM_CNTL__IDLE_ON_D3__SHIFT 0x00000013 +#define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE_MASK 0x00000003L +#define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE__SHIFT 0x00000000 +#define MC_ARB_PM_CNTL__OVRR_CGRFSH_MASK 0x00000004L +#define MC_ARB_PM_CNTL__OVRR_CGRFSH__SHIFT 0x00000002 +#define MC_ARB_PM_CNTL__OVRR_CGSQM_MASK 0x00000008L +#define MC_ARB_PM_CNTL__OVRR_CGSQM__SHIFT 0x00000003 +#define MC_ARB_PM_CNTL__OVRR_PM_MASK 0x00000080L +#define MC_ARB_PM_CNTL__OVRR_PM__SHIFT 0x00000007 +#define MC_ARB_PM_CNTL__OVRR_PM_STATE_MASK 0x00000300L +#define MC_ARB_PM_CNTL__OVRR_PM_STATE__SHIFT 0x00000008 +#define MC_ARB_PM_CNTL__OVRR_RD_MASK 0x00000400L +#define MC_ARB_PM_CNTL__OVRR_RD__SHIFT 0x0000000a +#define MC_ARB_PM_CNTL__OVRR_RD_STATE_MASK 0x00000800L +#define MC_ARB_PM_CNTL__OVRR_RD_STATE__SHIFT 0x0000000b +#define MC_ARB_PM_CNTL__OVRR_RFSH_MASK 0x00004000L +#define MC_ARB_PM_CNTL__OVRR_RFSH__SHIFT 0x0000000e +#define MC_ARB_PM_CNTL__OVRR_RFSH_STATE_MASK 0x00008000L +#define MC_ARB_PM_CNTL__OVRR_RFSH_STATE__SHIFT 0x0000000f +#define MC_ARB_PM_CNTL__OVRR_WR_MASK 0x00001000L +#define MC_ARB_PM_CNTL__OVRR_WR__SHIFT 0x0000000c +#define MC_ARB_PM_CNTL__OVRR_WR_STATE_MASK 0x00002000L +#define MC_ARB_PM_CNTL__OVRR_WR_STATE__SHIFT 0x0000000d +#define MC_ARB_PM_CNTL__SRFSH_ON_D1_MASK 0x00000010L +#define MC_ARB_PM_CNTL__SRFSH_ON_D1__SHIFT 0x00000004 +#define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL_MASK 0x00080000L +#define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL__SHIFT 0x00000013 +#define MC_ARB_POP__ENABLE_ARB_MASK 0x00000001L +#define MC_ARB_POP__ENABLE_ARB__SHIFT 0x00000000 +#define MC_ARB_POP__ENABLE_TWO_PAGE_MASK 0x00040000L +#define MC_ARB_POP__ENABLE_TWO_PAGE__SHIFT 0x00000012 +#define MC_ARB_POP__POP_DEPTH_MASK 0x0000003cL +#define MC_ARB_POP__POP_DEPTH__SHIFT 0x00000002 +#define MC_ARB_POP__QUICK_STOP_MASK 0x00020000L +#define MC_ARB_POP__QUICK_STOP__SHIFT 0x00000011 +#define MC_ARB_POP__SKID_DEPTH_MASK 0x00007000L +#define MC_ARB_POP__SKID_DEPTH__SHIFT 0x0000000c +#define MC_ARB_POP__SPEC_OPEN_MASK 0x00000002L +#define MC_ARB_POP__SPEC_OPEN__SHIFT 0x00000001 +#define MC_ARB_POP__WAIT_AFTER_RFSH_MASK 0x00018000L +#define MC_ARB_POP__WAIT_AFTER_RFSH__SHIFT 0x0000000f +#define MC_ARB_POP__WRDATAINDEX_DEPTH_MASK 0x00000fc0L +#define MC_ARB_POP__WRDATAINDEX_DEPTH__SHIFT 0x00000006 +#define MC_ARB_RAMCFG__CHANSIZE_MASK 0x00000100L +#define MC_ARB_RAMCFG__CHANSIZE__SHIFT 0x00000008 +#define MC_ARB_RAMCFG__NOOFBANK_MASK 0x00000003L +#define MC_ARB_RAMCFG__NOOFBANK__SHIFT 0x00000000 +#define MC_ARB_RAMCFG__NOOFCOLS_MASK 0x000000c0L +#define MC_ARB_RAMCFG__NOOFCOLS__SHIFT 0x00000006 +#define MC_ARB_RAMCFG__NOOFGROUPS_MASK 0x00001000L +#define MC_ARB_RAMCFG__NOOFGROUPS__SHIFT 0x0000000c +#define MC_ARB_RAMCFG__NOOFRANKS_MASK 0x00000004L +#define MC_ARB_RAMCFG__NOOFRANKS__SHIFT 0x00000002 +#define MC_ARB_RAMCFG__NOOFROWS_MASK 0x00000038L +#define MC_ARB_RAMCFG__NOOFROWS__SHIFT 0x00000003 +#define MC_ARB_REMREQ__RD_WATER_MASK 0x000000ffL +#define MC_ARB_REMREQ__RD_WATER__SHIFT 0x00000000 +#define MC_ARB_REMREQ__WR_LAZY_TIMER_MASK 0x00f00000L +#define MC_ARB_REMREQ__WR_LAZY_TIMER__SHIFT 0x00000014 +#define MC_ARB_REMREQ__WR_MAXBURST_SIZE_MASK 0x000f0000L +#define MC_ARB_REMREQ__WR_MAXBURST_SIZE__SHIFT 0x00000010 +#define MC_ARB_REMREQ__WR_WATER_MASK 0x0000ff00L +#define MC_ARB_REMREQ__WR_WATER__SHIFT 0x00000008 +#define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC_MASK 0x00000080L +#define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC__SHIFT 0x00000007 +#define MC_ARB_REPLAY__BOS_WAIT_CYC_MASK 0x00007f00L +#define MC_ARB_REPLAY__BOS_WAIT_CYC__SHIFT 0x00000008 +#define MC_ARB_REPLAY__BREAK_ON_STALL_MASK 0x00000040L +#define MC_ARB_REPLAY__BREAK_ON_STALL__SHIFT 0x00000006 +#define MC_ARB_REPLAY__ENABLE_RD_MASK 0x00000001L +#define MC_ARB_REPLAY__ENABLE_RD__SHIFT 0x00000000 +#define MC_ARB_REPLAY__ENABLE_WR_MASK 0x00000002L +#define MC_ARB_REPLAY__ENABLE_WR__SHIFT 0x00000001 +#define MC_ARB_REPLAY__IGNORE_WR_CDC_MASK 0x00000020L +#define MC_ARB_REPLAY__IGNORE_WR_CDC__SHIFT 0x00000005 +#define MC_ARB_REPLAY__RAW_ENABLE_MASK 0x00000010L +#define MC_ARB_REPLAY__RAW_ENABLE__SHIFT 0x00000004 +#define MC_ARB_REPLAY__WAW_ENABLE_MASK 0x00000008L +#define MC_ARB_REPLAY__WAW_ENABLE__SHIFT 0x00000003 +#define MC_ARB_REPLAY__WRACK_MODE_MASK 0x00000004L +#define MC_ARB_REPLAY__WRACK_MODE__SHIFT 0x00000002 +#define MC_ARB_RET_CREDITS_RD__DISP_MASK 0x00ff0000L +#define MC_ARB_RET_CREDITS_RD__DISP__SHIFT 0x00000010 +#define MC_ARB_RET_CREDITS_RD__HUB_MASK 0x0000ff00L +#define MC_ARB_RET_CREDITS_RD__HUB__SHIFT 0x00000008 +#define MC_ARB_RET_CREDITS_RD__LCL_MASK 0x000000ffL +#define MC_ARB_RET_CREDITS_RD__LCL__SHIFT 0x00000000 +#define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT_MASK 0xff000000L +#define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT__SHIFT 0x00000018 +#define MC_ARB_RET_CREDITS_WR__HUB_MASK 0x0000ff00L +#define MC_ARB_RET_CREDITS_WR__HUB__SHIFT 0x00000008 +#define MC_ARB_RET_CREDITS_WR__LCL_MASK 0x000000ffL +#define MC_ARB_RET_CREDITS_WR__LCL__SHIFT 0x00000000 +#define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT_MASK 0x00ff0000L +#define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT__SHIFT 0x00000010 +#define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID_MASK 0x0f000000L +#define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID__SHIFT 0x00000018 +#define MC_ARB_RFSH_CNTL__ACCUM_MASK 0x00000800L +#define MC_ARB_RFSH_CNTL__ACCUM__SHIFT 0x0000000b +#define MC_ARB_RFSH_CNTL__ENABLE_MASK 0x00000001L +#define MC_ARB_RFSH_CNTL__ENABLE__SHIFT 0x00000000 +#define MC_ARB_RFSH_CNTL__URG0_MASK 0x0000003eL +#define MC_ARB_RFSH_CNTL__URG0__SHIFT 0x00000001 +#define MC_ARB_RFSH_CNTL__URG1_MASK 0x000007c0L +#define MC_ARB_RFSH_CNTL__URG1__SHIFT 0x00000006 +#define MC_ARB_RFSH_RATE__POWERMODE0_MASK 0x000000ffL +#define MC_ARB_RFSH_RATE__POWERMODE0__SHIFT 0x00000000 +#define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH_MASK 0x00000100L +#define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH__SHIFT 0x00000008 +#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD_MASK 0x00000200L +#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD__SHIFT 0x00000009 +#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR_MASK 0x00000400L +#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR__SHIFT 0x0000000a +#define MC_ARB_RTT_CNTL0__DATA_CNTL_MASK 0x01000000L +#define MC_ARB_RTT_CNTL0__DATA_CNTL__SHIFT 0x00000018 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_0_MASK 0x00008000L +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_0__SHIFT 0x0000000f +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_1_MASK 0x00010000L +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_1__SHIFT 0x00000010 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_2_MASK 0x00020000L +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_2__SHIFT 0x00000011 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_3_MASK 0x00040000L +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_3__SHIFT 0x00000012 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_4_MASK 0x00080000L +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_4__SHIFT 0x00000013 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_5_MASK 0x00100000L +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_5__SHIFT 0x00000014 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_6_MASK 0x00200000L +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_6__SHIFT 0x00000015 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_7_MASK 0x00400000L +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_7__SHIFT 0x00000016 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_8_MASK 0x00800000L +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_8__SHIFT 0x00000017 +#define MC_ARB_RTT_CNTL0__ENABLE_MASK 0x00000001L +#define MC_ARB_RTT_CNTL0__ENABLE__SHIFT 0x00000000 +#define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER_MASK 0x00000010L +#define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER__SHIFT 0x00000004 +#define MC_ARB_RTT_CNTL0__HARSH_START_MASK 0x00000020L +#define MC_ARB_RTT_CNTL0__HARSH_START__SHIFT 0x00000005 +#define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT_MASK 0x02000000L +#define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT__SHIFT 0x00000019 +#define MC_ARB_RTT_CNTL0__START_IDLE_MASK 0x00000002L +#define MC_ARB_RTT_CNTL0__START_IDLE__SHIFT 0x00000001 +#define MC_ARB_RTT_CNTL0__START_R2W_MASK 0x0000000cL +#define MC_ARB_RTT_CNTL0__START_R2W_RFSH_MASK 0x00004000L +#define MC_ARB_RTT_CNTL0__START_R2W_RFSH__SHIFT 0x0000000e +#define MC_ARB_RTT_CNTL0__START_R2W__SHIFT 0x00000002 +#define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY_MASK 0x00000040L +#define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY__SHIFT 0x00000006 +#define MC_ARB_RTT_CNTL0__TRAIN_PERIOD_MASK 0x00003800L +#define MC_ARB_RTT_CNTL0__TRAIN_PERIOD__SHIFT 0x0000000b +#define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY_MASK 0x00000080L +#define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY__SHIFT 0x00000007 +#define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD_MASK 0x000fe000L +#define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD__SHIFT 0x0000000d +#define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD_MASK 0x00001fc0L +#define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD__SHIFT 0x00000006 +#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MASK 0x0000001fL +#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX_MASK 0x01f00000L +#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX__SHIFT 0x00000014 +#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN_MASK 0x3e000000L +#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN__SHIFT 0x00000019 +#define MC_ARB_RTT_CNTL1__WINDOW_SIZE__SHIFT 0x00000000 +#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT_MASK 0xc0000000L +#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT__SHIFT 0x0000001e +#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_MASK 0x00000020L +#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE__SHIFT 0x00000005 +#define MC_ARB_RTT_CNTL2__FILTER_CNTL_MASK 0x00002000L +#define MC_ARB_RTT_CNTL2__FILTER_CNTL__SHIFT 0x0000000d +#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE_MASK 0x00001000L +#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE__SHIFT 0x0000000c +#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD_MASK 0x00000fc0L +#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD__SHIFT 0x00000006 +#define MC_ARB_RTT_CNTL2__SAMPLE_CNT_MASK 0x0000003fL +#define MC_ARB_RTT_CNTL2__SAMPLE_CNT__SHIFT 0x00000000 +#define MC_ARB_RTT_DATA__PATTERN_MASK 0x000000ffL +#define MC_ARB_RTT_DATA__PATTERN__SHIFT 0x00000000 +#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0_MASK 0x00000003L +#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0__SHIFT 0x00000000 +#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1_MASK 0x0000000cL +#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1__SHIFT 0x00000002 +#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0_MASK 0x00000ff0L +#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0__SHIFT 0x00000004 +#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1_MASK 0x01fe0000L +#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1__SHIFT 0x00000011 +#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0_MASK 0x0001f000L +#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0__SHIFT 0x0000000c +#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1_MASK 0x3e000000L +#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1__SHIFT 0x00000019 +#define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE_MASK 0x00000100L +#define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE__SHIFT 0x00000008 +#define MC_ARB_SQM_CNTL__MIN_PENAL_MASK 0x000000ffL +#define MC_ARB_SQM_CNTL__MIN_PENAL__SHIFT 0x00000000 +#define MC_ARB_SQM_CNTL__RATIO_DEBUG_MASK 0xff000000L +#define MC_ARB_SQM_CNTL__RATIO_DEBUG__SHIFT 0x00000018 +#define MC_ARB_SQM_CNTL__RATIO_MASK 0x00ff0000L +#define MC_ARB_SQM_CNTL__RATIO__SHIFT 0x00000010 +#define MC_ARB_SQM_CNTL__SQM_RESERVE_MASK 0x0000fe00L +#define MC_ARB_SQM_CNTL__SQM_RESERVE__SHIFT 0x00000009 +#define MC_ARB_TM_CNTL_RD__BANK_SELECT_MASK 0x00000006L +#define MC_ARB_TM_CNTL_RD__BANK_SELECT__SHIFT 0x00000001 +#define MC_ARB_TM_CNTL_RD__GROUPBY_RANK_MASK 0x00000001L +#define MC_ARB_TM_CNTL_RD__GROUPBY_RANK__SHIFT 0x00000000 +#define MC_ARB_TM_CNTL_RD__MATCH_BANK_MASK 0x00000010L +#define MC_ARB_TM_CNTL_RD__MATCH_BANK__SHIFT 0x00000004 +#define MC_ARB_TM_CNTL_RD__MATCH_RANK_MASK 0x00000008L +#define MC_ARB_TM_CNTL_RD__MATCH_RANK__SHIFT 0x00000003 +#define MC_ARB_TM_CNTL_WR__BANK_SELECT_MASK 0x00000006L +#define MC_ARB_TM_CNTL_WR__BANK_SELECT__SHIFT 0x00000001 +#define MC_ARB_TM_CNTL_WR__GROUPBY_RANK_MASK 0x00000001L +#define MC_ARB_TM_CNTL_WR__GROUPBY_RANK__SHIFT 0x00000000 +#define MC_ARB_TM_CNTL_WR__MATCH_BANK_MASK 0x00000010L +#define MC_ARB_TM_CNTL_WR__MATCH_BANK__SHIFT 0x00000004 +#define MC_ARB_TM_CNTL_WR__MATCH_RANK_MASK 0x00000008L +#define MC_ARB_TM_CNTL_WR__MATCH_RANK__SHIFT 0x00000003 +#define MC_ARB_WCDR_2__DEBUG_0_MASK 0x00000200L +#define MC_ARB_WCDR_2__DEBUG_0__SHIFT 0x00000009 +#define MC_ARB_WCDR_2__DEBUG_1_MASK 0x00000400L +#define MC_ARB_WCDR_2__DEBUG_1__SHIFT 0x0000000a +#define MC_ARB_WCDR_2__DEBUG_2_MASK 0x00000800L +#define MC_ARB_WCDR_2__DEBUG_2__SHIFT 0x0000000b +#define MC_ARB_WCDR_2__DEBUG_3_MASK 0x00001000L +#define MC_ARB_WCDR_2__DEBUG_3__SHIFT 0x0000000c +#define MC_ARB_WCDR_2__DEBUG_4_MASK 0x00002000L +#define MC_ARB_WCDR_2__DEBUG_4__SHIFT 0x0000000d +#define MC_ARB_WCDR_2__DEBUG_5_MASK 0x00004000L +#define MC_ARB_WCDR_2__DEBUG_5__SHIFT 0x0000000e +#define MC_ARB_WCDR_2__WPRE_INC_STEP_MASK 0x0000000fL +#define MC_ARB_WCDR_2__WPRE_INC_STEP__SHIFT 0x00000000 +#define MC_ARB_WCDR_2__WPRE_MIN_THRESHOLD_MASK 0x000001f0L +#define MC_ARB_WCDR_2__WPRE_MIN_THRESHOLD__SHIFT 0x00000004 +#define MC_ARB_WCDR__IDLE_BURST_MASK 0x00001f80L +#define MC_ARB_WCDR__IDLE_BURST_MODE_MASK 0x00002000L +#define MC_ARB_WCDR__IDLE_BURST_MODE__SHIFT 0x0000000d +#define MC_ARB_WCDR__IDLE_BURST__SHIFT 0x00000007 +#define MC_ARB_WCDR__IDLE_DEGLITCH_ENABLE_MASK 0x00010000L +#define MC_ARB_WCDR__IDLE_DEGLITCH_ENABLE__SHIFT 0x00000010 +#define MC_ARB_WCDR__IDLE_ENABLE_MASK 0x00000001L +#define MC_ARB_WCDR__IDLE_ENABLE__SHIFT 0x00000000 +#define MC_ARB_WCDR__IDLE_PERIOD_MASK 0x0000007cL +#define MC_ARB_WCDR__IDLE_PERIOD__SHIFT 0x00000002 +#define MC_ARB_WCDR__IDLE_WAKEUP_MASK 0x0000c000L +#define MC_ARB_WCDR__IDLE_WAKEUP__SHIFT 0x0000000e +#define MC_ARB_WCDR__SEQ_IDLE_MASK 0x00000002L +#define MC_ARB_WCDR__SEQ_IDLE__SHIFT 0x00000001 +#define MC_ARB_WCDR__WPRE_ENABLE_MASK 0x00020000L +#define MC_ARB_WCDR__WPRE_ENABLE__SHIFT 0x00000011 +#define MC_ARB_WCDR__WPRE_INC_READ_MASK 0x02000000L +#define MC_ARB_WCDR__WPRE_INC_READ__SHIFT 0x00000019 +#define MC_ARB_WCDR__WPRE_INC_SEQIDLE_MASK 0x08000000L +#define MC_ARB_WCDR__WPRE_INC_SEQIDLE__SHIFT 0x0000001b +#define MC_ARB_WCDR__WPRE_INC_SKIDIDLE_MASK 0x04000000L +#define MC_ARB_WCDR__WPRE_INC_SKIDIDLE__SHIFT 0x0000001a +#define MC_ARB_WCDR__WPRE_MAX_BURST_MASK 0x01c00000L +#define MC_ARB_WCDR__WPRE_MAX_BURST__SHIFT 0x00000016 +#define MC_ARB_WCDR__WPRE_THRESHOLD_MASK 0x003c0000L +#define MC_ARB_WCDR__WPRE_THRESHOLD__SHIFT 0x00000012 +#define MC_ARB_WCDR__WPRE_TWOPAGE_MASK 0x10000000L +#define MC_ARB_WCDR__WPRE_TWOPAGE__SHIFT 0x0000001c +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0_MASK 0x00000008L +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0__SHIFT 0x00000003 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1_MASK 0x00000010L +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1__SHIFT 0x00000004 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2_MASK 0x00000020L +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2__SHIFT 0x00000005 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3_MASK 0x00000040L +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3__SHIFT 0x00000006 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4_MASK 0x00000080L +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4__SHIFT 0x00000007 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5_MASK 0x00000100L +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5__SHIFT 0x00000008 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6_MASK 0x00000200L +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6__SHIFT 0x00000009 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7_MASK 0x00000400L +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7__SHIFT 0x0000000a +#define MC_ARB_WTM_CNTL_RD__HARSH_PRI_MASK 0x00000004L +#define MC_ARB_WTM_CNTL_RD__HARSH_PRI__SHIFT 0x00000002 +#define MC_ARB_WTM_CNTL_RD__WTMODE_MASK 0x00000003L +#define MC_ARB_WTM_CNTL_RD__WTMODE__SHIFT 0x00000000 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0_MASK 0x00000008L +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0__SHIFT 0x00000003 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1_MASK 0x00000010L +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1__SHIFT 0x00000004 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2_MASK 0x00000020L +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2__SHIFT 0x00000005 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3_MASK 0x00000040L +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3__SHIFT 0x00000006 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4_MASK 0x00000080L +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4__SHIFT 0x00000007 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5_MASK 0x00000100L +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5__SHIFT 0x00000008 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6_MASK 0x00000200L +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6__SHIFT 0x00000009 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7_MASK 0x00000400L +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7__SHIFT 0x0000000a +#define MC_ARB_WTM_CNTL_WR__HARSH_PRI_MASK 0x00000004L +#define MC_ARB_WTM_CNTL_WR__HARSH_PRI__SHIFT 0x00000002 +#define MC_ARB_WTM_CNTL_WR__WTMODE_MASK 0x00000003L +#define MC_ARB_WTM_CNTL_WR__WTMODE__SHIFT 0x00000000 +#define MC_ARB_WTM_GRPWT_RD__GRP0_MASK 0x00000003L +#define MC_ARB_WTM_GRPWT_RD__GRP0__SHIFT 0x00000000 +#define MC_ARB_WTM_GRPWT_RD__GRP1_MASK 0x0000000cL +#define MC_ARB_WTM_GRPWT_RD__GRP1__SHIFT 0x00000002 +#define MC_ARB_WTM_GRPWT_RD__GRP2_MASK 0x00000030L +#define MC_ARB_WTM_GRPWT_RD__GRP2__SHIFT 0x00000004 +#define MC_ARB_WTM_GRPWT_RD__GRP3_MASK 0x000000c0L +#define MC_ARB_WTM_GRPWT_RD__GRP3__SHIFT 0x00000006 +#define MC_ARB_WTM_GRPWT_RD__GRP4_MASK 0x00000300L +#define MC_ARB_WTM_GRPWT_RD__GRP4__SHIFT 0x00000008 +#define MC_ARB_WTM_GRPWT_RD__GRP5_MASK 0x00000c00L +#define MC_ARB_WTM_GRPWT_RD__GRP5__SHIFT 0x0000000a +#define MC_ARB_WTM_GRPWT_RD__GRP6_MASK 0x00003000L +#define MC_ARB_WTM_GRPWT_RD__GRP6__SHIFT 0x0000000c +#define MC_ARB_WTM_GRPWT_RD__GRP7_MASK 0x0000c000L +#define MC_ARB_WTM_GRPWT_RD__GRP7__SHIFT 0x0000000e +#define MC_ARB_WTM_GRPWT_RD__GRP_EXT_MASK 0x00ff0000L +#define MC_ARB_WTM_GRPWT_RD__GRP_EXT__SHIFT 0x00000010 +#define MC_ARB_WTM_GRPWT_WR__GRP0_MASK 0x00000003L +#define MC_ARB_WTM_GRPWT_WR__GRP0__SHIFT 0x00000000 +#define MC_ARB_WTM_GRPWT_WR__GRP1_MASK 0x0000000cL +#define MC_ARB_WTM_GRPWT_WR__GRP1__SHIFT 0x00000002 +#define MC_ARB_WTM_GRPWT_WR__GRP2_MASK 0x00000030L +#define MC_ARB_WTM_GRPWT_WR__GRP2__SHIFT 0x00000004 +#define MC_ARB_WTM_GRPWT_WR__GRP3_MASK 0x000000c0L +#define MC_ARB_WTM_GRPWT_WR__GRP3__SHIFT 0x00000006 +#define MC_ARB_WTM_GRPWT_WR__GRP4_MASK 0x00000300L +#define MC_ARB_WTM_GRPWT_WR__GRP4__SHIFT 0x00000008 +#define MC_ARB_WTM_GRPWT_WR__GRP5_MASK 0x00000c00L +#define MC_ARB_WTM_GRPWT_WR__GRP5__SHIFT 0x0000000a +#define MC_ARB_WTM_GRPWT_WR__GRP6_MASK 0x00003000L +#define MC_ARB_WTM_GRPWT_WR__GRP6__SHIFT 0x0000000c +#define MC_ARB_WTM_GRPWT_WR__GRP7_MASK 0x0000c000L +#define MC_ARB_WTM_GRPWT_WR__GRP7__SHIFT 0x0000000e +#define MC_ARB_WTM_GRPWT_WR__GRP_EXT_MASK 0x00ff0000L +#define MC_ARB_WTM_GRPWT_WR__GRP_EXT__SHIFT 0x00000010 +#define MC_BIST_AUTO_CNTL__ADR_GEN_MASK 0x000000f0L +#define MC_BIST_AUTO_CNTL__ADR_GEN__SHIFT 0x00000004 +#define MC_BIST_AUTO_CNTL__ADR_RESET_MASK 0x02000000L +#define MC_BIST_AUTO_CNTL__ADR_RESET__SHIFT 0x00000019 +#define MC_BIST_AUTO_CNTL__LFSR_KEY_MASK 0x00ffff00L +#define MC_BIST_AUTO_CNTL__LFSR_KEY__SHIFT 0x00000008 +#define MC_BIST_AUTO_CNTL__LFSR_RESET_MASK 0x01000000L +#define MC_BIST_AUTO_CNTL__LFSR_RESET__SHIFT 0x00000018 +#define MC_BIST_AUTO_CNTL__MOP_MASK 0x00000003L +#define MC_BIST_AUTO_CNTL__MOP__SHIFT 0x00000000 +#define MC_BIST_CMD_CNTL__CMD_ISSUE_LOOP_MASK 0x00000004L +#define MC_BIST_CMD_CNTL__CMD_ISSUE_LOOP__SHIFT 0x00000002 +#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_MASK 0x00000002L +#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE__SHIFT 0x00000001 +#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_U_MASK 0x00010000L +#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_U__SHIFT 0x00000010 +#define MC_BIST_CMD_CNTL__CMD_ISSUE_RUN_MASK 0x00020000L +#define MC_BIST_CMD_CNTL__CMD_ISSUE_RUN__SHIFT 0x00000011 +#define MC_BIST_CMD_CNTL__DONE_MASK 0x80000000L +#define MC_BIST_CMD_CNTL__DONE__SHIFT 0x0000001f +#define MC_BIST_CMD_CNTL__ENABLE_D0_MASK 0x10000000L +#define MC_BIST_CMD_CNTL__ENABLE_D0__SHIFT 0x0000001c +#define MC_BIST_CMD_CNTL__ENABLE_D1_MASK 0x20000000L +#define MC_BIST_CMD_CNTL__ENABLE_D1__SHIFT 0x0000001d +#define MC_BIST_CMD_CNTL__LOOP_CNT_MAX_MASK 0x0000fff0L +#define MC_BIST_CMD_CNTL__LOOP_CNT_MAX__SHIFT 0x00000004 +#define MC_BIST_CMD_CNTL__LOOP_CNT_RD_MASK 0x0ffc0000L +#define MC_BIST_CMD_CNTL__LOOP_CNT_RD__SHIFT 0x00000012 +#define MC_BIST_CMD_CNTL__LOOP_END_CONDITION_MASK 0x00000008L +#define MC_BIST_CMD_CNTL__LOOP_END_CONDITION__SHIFT 0x00000003 +#define MC_BIST_CMD_CNTL__RESET_MASK 0x00000001L +#define MC_BIST_CMD_CNTL__RESET__SHIFT 0x00000000 +#define MC_BIST_CMD_CNTL__STATUS_CH_MASK 0x40000000L +#define MC_BIST_CMD_CNTL__STATUS_CH__SHIFT 0x0000001e +#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_MASK 0x0000001fL +#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_RST_MASK 0x00000100L +#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_RST__SHIFT 0x00000008 +#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT__SHIFT 0x00000000 +#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_MASK 0x0001f000L +#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_RST_MASK 0x00100000L +#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_RST__SHIFT 0x00000014 +#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT__SHIFT 0x0000000c +#define MC_BIST_CMP_CNTL__CMP_MASK 0x00030000L +#define MC_BIST_CMP_CNTL__CMP_MASK_BIT_MASK 0x00000ff0L +#define MC_BIST_CMP_CNTL__CMP_MASK_BIT__SHIFT 0x00000004 +#define MC_BIST_CMP_CNTL__CMP_MASK_BYTE_MASK 0x0000000fL +#define MC_BIST_CMP_CNTL__CMP_MASK_BYTE__SHIFT 0x00000000 +#define MC_BIST_CMP_CNTL__CMP__SHIFT 0x00000010 +#define MC_BIST_CMP_CNTL__DATA_STORE_MODE_MASK 0x00300000L +#define MC_BIST_CMP_CNTL__DATA_STORE_MODE__SHIFT 0x00000014 +#define MC_BIST_CMP_CNTL__DATA_STORE_SEL_MASK 0x00002000L +#define MC_BIST_CMP_CNTL__DATA_STORE_SEL__SHIFT 0x0000000d +#define MC_BIST_CMP_CNTL__DAT_MODE_MASK 0x00040000L +#define MC_BIST_CMP_CNTL__DAT_MODE__SHIFT 0x00000012 +#define MC_BIST_CMP_CNTL__EDC_STORE_MODE_MASK 0x00080000L +#define MC_BIST_CMP_CNTL__EDC_STORE_MODE__SHIFT 0x00000013 +#define MC_BIST_CMP_CNTL__EDC_STORE_SEL_MASK 0x00004000L +#define MC_BIST_CMP_CNTL__EDC_STORE_SEL__SHIFT 0x0000000e +#define MC_BIST_CMP_CNTL__ENABLE_CMD_FIFO_MASK 0x00008000L +#define MC_BIST_CMP_CNTL__ENABLE_CMD_FIFO__SHIFT 0x0000000f +#define MC_BIST_CMP_CNTL__LOAD_RTEDC_MASK 0x00001000L +#define MC_BIST_CMP_CNTL__LOAD_RTEDC__SHIFT 0x0000000c +#define MC_BIST_CMP_CNTL__MISMATCH_CNT_MASK 0xffc00000L +#define MC_BIST_CMP_CNTL__MISMATCH_CNT__SHIFT 0x00000016 +#define MC_BIST_CNTL__ADR_MODE_MASK 0x00000020L +#define MC_BIST_CNTL__ADR_MODE__SHIFT 0x00000005 +#define MC_BIST_CNTL__DAT_MODE_MASK 0x00000040L +#define MC_BIST_CNTL__DAT_MODE__SHIFT 0x00000006 +#define MC_BIST_CNTL__DONE_MASK 0x40000000L +#define MC_BIST_CNTL__DONE__SHIFT 0x0000001e +#define MC_BIST_CNTL__ENABLE_D0_MASK 0x00001000L +#define MC_BIST_CNTL__ENABLE_D0__SHIFT 0x0000000c +#define MC_BIST_CNTL__ENABLE_D1_MASK 0x00002000L +#define MC_BIST_CNTL__ENABLE_D1__SHIFT 0x0000000d +#define MC_BIST_CNTL__LOAD_RTDATA_CH_MASK 0x00004000L +#define MC_BIST_CNTL__LOAD_RTDATA_CH__SHIFT 0x0000000e +#define MC_BIST_CNTL__LOAD_RTDATA_MASK 0x80000000L +#define MC_BIST_CNTL__LOAD_RTDATA__SHIFT 0x0000001f +#define MC_BIST_CNTL__LOOP_CNT_MASK 0x0fff0000L +#define MC_BIST_CNTL__LOOP_CNT__SHIFT 0x00000010 +#define MC_BIST_CNTL__LOOP_MASK 0x00000c00L +#define MC_BIST_CNTL__LOOP__SHIFT 0x0000000a +#define MC_BIST_CNTL__MOP_MODE_MASK 0x00000010L +#define MC_BIST_CNTL__MOP_MODE__SHIFT 0x00000004 +#define MC_BIST_CNTL__PTR_RST_D0_MASK 0x00000004L +#define MC_BIST_CNTL__PTR_RST_D0__SHIFT 0x00000002 +#define MC_BIST_CNTL__PTR_RST_D1_MASK 0x00000008L +#define MC_BIST_CNTL__PTR_RST_D1__SHIFT 0x00000003 +#define MC_BIST_CNTL__RESET_MASK 0x00000001L +#define MC_BIST_CNTL__RESET__SHIFT 0x00000000 +#define MC_BIST_CNTL__RUN_MASK 0x00000002L +#define MC_BIST_CNTL__RUN__SHIFT 0x00000001 +#define MC_BIST_DATA_MASK__MASK_MASK 0xffffffffL +#define MC_BIST_DATA_MASK__MASK__SHIFT 0x00000000 +#define MC_BIST_DATA_WORD0__DATA_MASK 0xffffffffL +#define MC_BIST_DATA_WORD0__DATA__SHIFT 0x00000000 +#define MC_BIST_DATA_WORD1__DATA_MASK 0xffffffffL +#define MC_BIST_DATA_WORD1__DATA__SHIFT 0x00000000 +#define MC_BIST_DATA_WORD2__DATA_MASK 0xffffffffL +#define MC_BIST_DATA_WORD2__DATA__SHIFT 0x00000000 +#define MC_BIST_DATA_WORD3__DATA_MASK 0xffffffffL +#define MC_BIST_DATA_WORD3__DATA__SHIFT 0x00000000 +#define MC_BIST_DATA_WORD4__DATA_MASK 0xffffffffL +#define MC_BIST_DATA_WORD4__DATA__SHIFT 0x00000000 +#define MC_BIST_DATA_WORD5__DATA_MASK 0xffffffffL +#define MC_BIST_DATA_WORD5__DATA__SHIFT 0x00000000 +#define MC_BIST_DATA_WORD6__DATA_MASK 0xffffffffL +#define MC_BIST_DATA_WORD6__DATA__SHIFT 0x00000000 +#define MC_BIST_DATA_WORD7__DATA_MASK 0xffffffffL +#define MC_BIST_DATA_WORD7__DATA__SHIFT 0x00000000 +#define MC_BIST_DIR_CNTL__CMD_RTR_D0_MASK 0x00000040L +#define MC_BIST_DIR_CNTL__CMD_RTR_D0__SHIFT 0x00000006 +#define MC_BIST_DIR_CNTL__CMD_RTR_D1_MASK 0x00000100L +#define MC_BIST_DIR_CNTL__CMD_RTR_D1__SHIFT 0x00000008 +#define MC_BIST_DIR_CNTL__DATA_LOAD_MASK 0x00000020L +#define MC_BIST_DIR_CNTL__DATA_LOAD__SHIFT 0x00000005 +#define MC_BIST_DIR_CNTL__DAT_RTR_D0_MASK 0x00000080L +#define MC_BIST_DIR_CNTL__DAT_RTR_D0__SHIFT 0x00000007 +#define MC_BIST_DIR_CNTL__DAT_RTR_D1_MASK 0x00000200L +#define MC_BIST_DIR_CNTL__DAT_RTR_D1__SHIFT 0x00000009 +#define MC_BIST_DIR_CNTL__EOB_MASK 0x00000008L +#define MC_BIST_DIR_CNTL__EOB__SHIFT 0x00000003 +#define MC_BIST_DIR_CNTL__MOP3_MASK 0x00000400L +#define MC_BIST_DIR_CNTL__MOP3__SHIFT 0x0000000a +#define MC_BIST_DIR_CNTL__MOP_LOAD_MASK 0x00000010L +#define MC_BIST_DIR_CNTL__MOP_LOAD__SHIFT 0x00000004 +#define MC_BIST_DIR_CNTL__MOP_MASK 0x00000007L +#define MC_BIST_DIR_CNTL__MOP__SHIFT 0x00000000 +#define MC_BIST_EADDR__BANK_MASK 0x0f000000L +#define MC_BIST_EADDR__BANK__SHIFT 0x00000018 +#define MC_BIST_EADDR__COLH_MASK 0x20000000L +#define MC_BIST_EADDR__COLH__SHIFT 0x0000001d +#define MC_BIST_EADDR__COL_MASK 0x000003ffL +#define MC_BIST_EADDR__COL__SHIFT 0x00000000 +#define MC_BIST_EADDR__RANK_MASK 0x10000000L +#define MC_BIST_EADDR__RANK__SHIFT 0x0000001c +#define MC_BIST_EADDR__ROWH_MASK 0xc0000000L +#define MC_BIST_EADDR__ROWH__SHIFT 0x0000001e +#define MC_BIST_EADDR__ROW_MASK 0x00fffc00L +#define MC_BIST_EADDR__ROW__SHIFT 0x0000000a +#define MC_BIST_MISMATCH_ADDR__BANK_MASK 0x0f000000L +#define MC_BIST_MISMATCH_ADDR__BANK__SHIFT 0x00000018 +#define MC_BIST_MISMATCH_ADDR__COLH_MASK 0x20000000L +#define MC_BIST_MISMATCH_ADDR__COLH__SHIFT 0x0000001d +#define MC_BIST_MISMATCH_ADDR__COL_MASK 0x000003ffL +#define MC_BIST_MISMATCH_ADDR__COL__SHIFT 0x00000000 +#define MC_BIST_MISMATCH_ADDR__RANK_MASK 0x10000000L +#define MC_BIST_MISMATCH_ADDR__RANK__SHIFT 0x0000001c +#define MC_BIST_MISMATCH_ADDR__ROWH_MASK 0xc0000000L +#define MC_BIST_MISMATCH_ADDR__ROWH__SHIFT 0x0000001e +#define MC_BIST_MISMATCH_ADDR__ROW_MASK 0x00fffc00L +#define MC_BIST_MISMATCH_ADDR__ROW__SHIFT 0x0000000a +#define MC_BIST_RDATA_EDC__EDC_MASK 0xffffffffL +#define MC_BIST_RDATA_EDC__EDC__SHIFT 0x00000000 +#define MC_BIST_RDATA_MASK__MASK_MASK 0xffffffffL +#define MC_BIST_RDATA_MASK__MASK__SHIFT 0x00000000 +#define MC_BIST_RDATA_WORD0__RDATA_MASK 0xffffffffL +#define MC_BIST_RDATA_WORD0__RDATA__SHIFT 0x00000000 +#define MC_BIST_RDATA_WORD1__RDATA_MASK 0xffffffffL +#define MC_BIST_RDATA_WORD1__RDATA__SHIFT 0x00000000 +#define MC_BIST_RDATA_WORD2__RDATA_MASK 0xffffffffL +#define MC_BIST_RDATA_WORD2__RDATA__SHIFT 0x00000000 +#define MC_BIST_RDATA_WORD3__RDATA_MASK 0xffffffffL +#define MC_BIST_RDATA_WORD3__RDATA__SHIFT 0x00000000 +#define MC_BIST_RDATA_WORD4__RDATA_MASK 0xffffffffL +#define MC_BIST_RDATA_WORD4__RDATA__SHIFT 0x00000000 +#define MC_BIST_RDATA_WORD5__RDATA_MASK 0xffffffffL +#define MC_BIST_RDATA_WORD5__RDATA__SHIFT 0x00000000 +#define MC_BIST_RDATA_WORD6__RDATA_MASK 0xffffffffL +#define MC_BIST_RDATA_WORD6__RDATA__SHIFT 0x00000000 +#define MC_BIST_RDATA_WORD7__RDATA_MASK 0xffffffffL +#define MC_BIST_RDATA_WORD7__RDATA__SHIFT 0x00000000 +#define MC_BIST_SADDR__BANK_MASK 0x0f000000L +#define MC_BIST_SADDR__BANK__SHIFT 0x00000018 +#define MC_BIST_SADDR__COLH_MASK 0x20000000L +#define MC_BIST_SADDR__COLH__SHIFT 0x0000001d +#define MC_BIST_SADDR__COL_MASK 0x000003ffL +#define MC_BIST_SADDR__COL__SHIFT 0x00000000 +#define MC_BIST_SADDR__RANK_MASK 0x10000000L +#define MC_BIST_SADDR__RANK__SHIFT 0x0000001c +#define MC_BIST_SADDR__ROWH_MASK 0xc0000000L +#define MC_BIST_SADDR__ROWH__SHIFT 0x0000001e +#define MC_BIST_SADDR__ROW_MASK 0x00fffc00L +#define MC_BIST_SADDR__ROW__SHIFT 0x0000000a +#define MC_CG_CONFIG__INDEX_MASK 0x003fffc0L +#define MC_CG_CONFIG__INDEX__SHIFT 0x00000006 +#define MC_CG_CONFIG_MCD__INDEX_MASK 0x1fffe000L +#define MC_CG_CONFIG_MCD__INDEX__SHIFT 0x0000000d +#define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x00000001L +#define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x00000000 +#define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x00000002L +#define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x00000001 +#define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x00000004L +#define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x00000002 +#define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x00000008L +#define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x00000003 +#define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x00000010L +#define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x00000004 +#define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x00000020L +#define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x00000005 +#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_MASK 0x00000700L +#define MC_CG_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x00000008 +#define MC_CG_CONFIG__MCDW_WR_ENABLE_MASK 0x00000001L +#define MC_CG_CONFIG__MCDW_WR_ENABLE__SHIFT 0x00000000 +#define MC_CG_CONFIG__MCDX_WR_ENABLE_MASK 0x00000002L +#define MC_CG_CONFIG__MCDX_WR_ENABLE__SHIFT 0x00000001 +#define MC_CG_CONFIG__MCDY_WR_ENABLE_MASK 0x00000004L +#define MC_CG_CONFIG__MCDY_WR_ENABLE__SHIFT 0x00000002 +#define MC_CG_CONFIG__MCDZ_WR_ENABLE_MASK 0x00000008L +#define MC_CG_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x00000003 +#define MC_CG_CONFIG__MC_RD_ENABLE_MASK 0x00000030L +#define MC_CG_CONFIG__MC_RD_ENABLE__SHIFT 0x00000004 +#define MC_CG_DATAPORT__DATA_FIELD_MASK 0xffffffffL +#define MC_CG_DATAPORT__DATA_FIELD__SHIFT 0x00000000 +#define MC_CITF_CNTL__EXEMPTPM_MASK 0x00000008L +#define MC_CITF_CNTL__EXEMPTPM__SHIFT 0x00000003 +#define MC_CITF_CNTL__GFX_IDLE_OVERRIDE_MASK 0x00000030L +#define MC_CITF_CNTL__GFX_IDLE_OVERRIDE__SHIFT 0x00000004 +#define MC_CITF_CNTL__IGNOREPM_MASK 0x00000004L +#define MC_CITF_CNTL__IGNOREPM__SHIFT 0x00000002 +#define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE_MASK 0x00000040L +#define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE__SHIFT 0x00000006 +#define MC_CITF_CREDITS_ARB_RD__HUB_PRI_MASK 0x02000000L +#define MC_CITF_CREDITS_ARB_RD__HUB_PRI__SHIFT 0x00000019 +#define MC_CITF_CREDITS_ARB_RD__LCL_PRI_MASK 0x01000000L +#define MC_CITF_CREDITS_ARB_RD__LCL_PRI__SHIFT 0x00000018 +#define MC_CITF_CREDITS_ARB_RD__READ_HUB_MASK 0x0000ff00L +#define MC_CITF_CREDITS_ARB_RD__READ_HUB__SHIFT 0x00000008 +#define MC_CITF_CREDITS_ARB_RD__READ_LCL_MASK 0x000000ffL +#define MC_CITF_CREDITS_ARB_RD__READ_LCL__SHIFT 0x00000000 +#define MC_CITF_CREDITS_ARB_RD__READ_PRI_MASK 0x00ff0000L +#define MC_CITF_CREDITS_ARB_RD__READ_PRI__SHIFT 0x00000010 +#define MC_CITF_CREDITS_ARB_WR__HUB_PRI_MASK 0x00010000L +#define MC_CITF_CREDITS_ARB_WR__HUB_PRI__SHIFT 0x00000010 +#define MC_CITF_CREDITS_ARB_WR__LCL_PRI_MASK 0x00020000L +#define MC_CITF_CREDITS_ARB_WR__LCL_PRI__SHIFT 0x00000011 +#define MC_CITF_CREDITS_ARB_WR__WRITE_HUB_MASK 0x0000ff00L +#define MC_CITF_CREDITS_ARB_WR__WRITE_HUB__SHIFT 0x00000008 +#define MC_CITF_CREDITS_ARB_WR__WRITE_LCL_MASK 0x000000ffL +#define MC_CITF_CREDITS_ARB_WR__WRITE_LCL__SHIFT 0x00000000 +#define MC_CITF_CREDITS_VM__READ_ALL_MASK 0x0000003fL +#define MC_CITF_CREDITS_VM__READ_ALL__SHIFT 0x00000000 +#define MC_CITF_CREDITS_VM__WRITE_ALL_MASK 0x00000fc0L +#define MC_CITF_CREDITS_VM__WRITE_ALL__SHIFT 0x00000006 +#define MC_CITF_CREDITS_XBAR__READ_LCL_MASK 0x000000ffL +#define MC_CITF_CREDITS_XBAR__READ_LCL__SHIFT 0x00000000 +#define MC_CITF_CREDITS_XBAR__WRITE_LCL_MASK 0x0000ff00L +#define MC_CITF_CREDITS_XBAR__WRITE_LCL__SHIFT 0x00000008 +#define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST_MASK 0x0000001eL +#define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST__SHIFT 0x00000001 +#define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST_MASK 0x000003c0L +#define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST__SHIFT 0x00000006 +#define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT_MASK 0x00000020L +#define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT__SHIFT 0x00000005 +#define MC_CITF_DAGB_CNTL__JUMP_AHEAD_MASK 0x00000001L +#define MC_CITF_DAGB_CNTL__JUMP_AHEAD__SHIFT 0x00000000 +#define MC_CITF_DAGB_DLY__CLI_MASK 0x001f0000L +#define MC_CITF_DAGB_DLY__CLI__SHIFT 0x00000010 +#define MC_CITF_DAGB_DLY__DLY_MASK 0x0000001fL +#define MC_CITF_DAGB_DLY__DLY__SHIFT 0x00000000 +#define MC_CITF_DAGB_DLY__POS_MASK 0x1f000000L +#define MC_CITF_DAGB_DLY__POS__SHIFT 0x00000018 +#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP_MASK 0x00fc0000L +#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP__SHIFT 0x00000012 +#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP_MASK 0x0003f000L +#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP__SHIFT 0x0000000c +#define MC_CITF_INT_CREDITS__CNTR_RD_LCL_MASK 0x3f000000L +#define MC_CITF_INT_CREDITS__CNTR_RD_LCL__SHIFT 0x00000018 +#define MC_CITF_INT_CREDITS__REMRDRET_MASK 0x0000003fL +#define MC_CITF_INT_CREDITS__REMRDRET__SHIFT 0x00000000 +#define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB_MASK 0x0000003fL +#define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB__SHIFT 0x00000000 +#define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL_MASK 0x00000fc0L +#define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL__SHIFT 0x00000006 +#define MC_CITF_MISC_RD_CG__ENABLE_MASK 0x00040000L +#define MC_CITF_MISC_RD_CG__ENABLE__SHIFT 0x00000012 +#define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK 0x00080000L +#define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE__SHIFT 0x00000013 +#define MC_CITF_MISC_RD_CG__OFFDLY_MASK 0x00000fc0L +#define MC_CITF_MISC_RD_CG__OFFDLY__SHIFT 0x00000006 +#define MC_CITF_MISC_RD_CG__ONDLY_MASK 0x0000003fL +#define MC_CITF_MISC_RD_CG__ONDLY__SHIFT 0x00000000 +#define MC_CITF_MISC_RD_CG__RDYDLY_MASK 0x0003f000L +#define MC_CITF_MISC_RD_CG__RDYDLY__SHIFT 0x0000000c +#define MC_CITF_MISC_VM_CG__ENABLE_MASK 0x00040000L +#define MC_CITF_MISC_VM_CG__ENABLE__SHIFT 0x00000012 +#define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x00080000L +#define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x00000013 +#define MC_CITF_MISC_VM_CG__OFFDLY_MASK 0x00000fc0L +#define MC_CITF_MISC_VM_CG__OFFDLY__SHIFT 0x00000006 +#define MC_CITF_MISC_VM_CG__ONDLY_MASK 0x0000003fL +#define MC_CITF_MISC_VM_CG__ONDLY__SHIFT 0x00000000 +#define MC_CITF_MISC_VM_CG__RDYDLY_MASK 0x0003f000L +#define MC_CITF_MISC_VM_CG__RDYDLY__SHIFT 0x0000000c +#define MC_CITF_MISC_WR_CG__ENABLE_MASK 0x00040000L +#define MC_CITF_MISC_WR_CG__ENABLE__SHIFT 0x00000012 +#define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK 0x00080000L +#define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE__SHIFT 0x00000013 +#define MC_CITF_MISC_WR_CG__OFFDLY_MASK 0x00000fc0L +#define MC_CITF_MISC_WR_CG__OFFDLY__SHIFT 0x00000006 +#define MC_CITF_MISC_WR_CG__ONDLY_MASK 0x0000003fL +#define MC_CITF_MISC_WR_CG__ONDLY__SHIFT 0x00000000 +#define MC_CITF_MISC_WR_CG__RDYDLY_MASK 0x0003f000L +#define MC_CITF_MISC_WR_CG__RDYDLY__SHIFT 0x0000000c +#define MC_CITF_PERF_MON_CNTL2__CID_MASK 0x000001ffL +#define MC_CITF_PERF_MON_CNTL2__CID__SHIFT 0x00000000 +#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY_MASK 0x00000040L +#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY__SHIFT 0x00000006 +#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY_MASK 0x00001000L +#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY__SHIFT 0x0000000c +#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY_MASK 0x00000080L +#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY__SHIFT 0x00000007 +#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY_MASK 0x00002000L +#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY__SHIFT 0x0000000d +#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY_MASK 0x00004000L +#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY__SHIFT 0x0000000e +#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY_MASK 0x00000100L +#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY__SHIFT 0x00000008 +#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY_MASK 0x00010000L +#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY__SHIFT 0x00000010 +#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY_MASK 0x00000400L +#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY__SHIFT 0x0000000a +#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY_MASK 0x00020000L +#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY__SHIFT 0x00000011 +#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY_MASK 0x00008000L +#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY__SHIFT 0x0000000f +#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY_MASK 0x00040000L +#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY__SHIFT 0x00000012 +#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY_MASK 0x00000200L +#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY__SHIFT 0x00000009 +#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY_MASK 0x00000800L +#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY__SHIFT 0x0000000b +#define MC_CITF_REMREQ__CREDITS_ENABLE_MASK 0x00004000L +#define MC_CITF_REMREQ__CREDITS_ENABLE__SHIFT 0x0000000e +#define MC_CITF_REMREQ__READ_CREDITS_MASK 0x0000007fL +#define MC_CITF_REMREQ__READ_CREDITS__SHIFT 0x00000000 +#define MC_CITF_REMREQ__WRITE_CREDITS_MASK 0x00003f80L +#define MC_CITF_REMREQ__WRITE_CREDITS__SHIFT 0x00000007 +#define MC_CITF_RET_MODE__INORDER_RD_MASK 0x00000001L +#define MC_CITF_RET_MODE__INORDER_RD__SHIFT 0x00000000 +#define MC_CITF_RET_MODE__INORDER_WR_MASK 0x00000002L +#define MC_CITF_RET_MODE__INORDER_WR__SHIFT 0x00000001 +#define MC_CITF_RET_MODE__LCLPRI_RD_MASK 0x00000010L +#define MC_CITF_RET_MODE__LCLPRI_RD__SHIFT 0x00000004 +#define MC_CITF_RET_MODE__LCLPRI_WR_MASK 0x00000020L +#define MC_CITF_RET_MODE__LCLPRI_WR__SHIFT 0x00000005 +#define MC_CITF_RET_MODE__REMPRI_RD_MASK 0x00000004L +#define MC_CITF_RET_MODE__REMPRI_RD__SHIFT 0x00000002 +#define MC_CITF_RET_MODE__REMPRI_WR_MASK 0x00000008L +#define MC_CITF_RET_MODE__REMPRI_WR__SHIFT 0x00000003 +#define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE_MASK 0x01000000L +#define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE__SHIFT 0x00000018 +#define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT_MASK 0x00000007L +#define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT__SHIFT 0x00000000 +#define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT_MASK 0x00000038L +#define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT__SHIFT 0x00000003 +#define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT_MASK 0x000001c0L +#define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT__SHIFT 0x00000006 +#define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT_MASK 0x00000e00L +#define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT__SHIFT 0x00000009 +#define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT_MASK 0x00007000L +#define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT__SHIFT 0x0000000c +#define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT_MASK 0x00038000L +#define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT__SHIFT 0x0000000f +#define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT_MASK 0x001c0000L +#define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT__SHIFT 0x00000012 +#define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT_MASK 0x00e00000L +#define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT__SHIFT 0x00000015 +#define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE_MASK 0x01000000L +#define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE__SHIFT 0x00000018 +#define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT_MASK 0x00000007L +#define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT__SHIFT 0x00000000 +#define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT_MASK 0x00000038L +#define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT__SHIFT 0x00000003 +#define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT_MASK 0x000001c0L +#define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT__SHIFT 0x00000006 +#define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT_MASK 0x00000e00L +#define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT__SHIFT 0x00000009 +#define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT_MASK 0x00007000L +#define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT__SHIFT 0x0000000c +#define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT_MASK 0x00038000L +#define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT__SHIFT 0x0000000f +#define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT_MASK 0x001c0000L +#define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT__SHIFT 0x00000012 +#define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT_MASK 0x00e00000L +#define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT__SHIFT 0x00000015 +#define MC_CITF_XTRA_ENABLE__ARB_DBG_MASK 0x00000f00L +#define MC_CITF_XTRA_ENABLE__ARB_DBG__SHIFT 0x00000008 +#define MC_CITF_XTRA_ENABLE__CB1_RD_MASK 0x00000001L +#define MC_CITF_XTRA_ENABLE__CB1_RD__SHIFT 0x00000000 +#define MC_CITF_XTRA_ENABLE__CB1_WR_MASK 0x00000002L +#define MC_CITF_XTRA_ENABLE__CB1_WR__SHIFT 0x00000001 +#define MC_CITF_XTRA_ENABLE__DB1_RD_MASK 0x00000004L +#define MC_CITF_XTRA_ENABLE__DB1_RD__SHIFT 0x00000002 +#define MC_CITF_XTRA_ENABLE__DB1_WR_MASK 0x00000008L +#define MC_CITF_XTRA_ENABLE__DB1_WR__SHIFT 0x00000003 +#define MC_CITF_XTRA_ENABLE__TC2_RD_MASK 0x00000010L +#define MC_CITF_XTRA_ENABLE__TC2_RD__SHIFT 0x00000004 +#define MC_CITF_XTRA_ENABLE__TC2_WR_MASK 0x00001000L +#define MC_CITF_XTRA_ENABLE__TC2_WR__SHIFT 0x0000000c +#define MC_CONFIG__MCC_INDEX_MODE_ENABLE_MASK 0x80000000L +#define MC_CONFIG__MCC_INDEX_MODE_ENABLE__SHIFT 0x0000001f +#define MC_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x00000001L +#define MC_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x00000000 +#define MC_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x00000002L +#define MC_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x00000001 +#define MC_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x00000004L +#define MC_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x00000002 +#define MC_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x00000008L +#define MC_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x00000003 +#define MC_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x00000010L +#define MC_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x00000004 +#define MC_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x00000020L +#define MC_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x00000005 +#define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE_MASK 0x80000000L +#define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE__SHIFT 0x0000001f +#define MC_CONFIG_MCD__MC_RD_ENABLE_MASK 0x00000700L +#define MC_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x00000008 +#define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x00000001L +#define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x00000000 +#define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x00000002L +#define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x00000001 +#define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x00000004L +#define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x00000002 +#define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x00000008L +#define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x00000003 +#define MC_CONFIG__MC_RD_ENABLE_MASK 0x00000030L +#define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x00000004 +#define MC_HUB_MISC_DBG__SELECT0_MASK 0x0000000fL +#define MC_HUB_MISC_DBG__SELECT0__SHIFT 0x00000000 +#define MC_HUB_MISC_DBG__SELECT1_MASK 0x000000f0L +#define MC_HUB_MISC_DBG__SELECT1__SHIFT 0x00000004 +#define MC_HUB_MISC_FRAMING__BITS_MASK 0xffffffffL +#define MC_HUB_MISC_FRAMING__BITS__SHIFT 0x00000000 +#define MC_HUB_MISC_HUB_CG__ENABLE_MASK 0x00040000L +#define MC_HUB_MISC_HUB_CG__ENABLE__SHIFT 0x00000012 +#define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK 0x00080000L +#define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE__SHIFT 0x00000013 +#define MC_HUB_MISC_HUB_CG__OFFDLY_MASK 0x00000fc0L +#define MC_HUB_MISC_HUB_CG__OFFDLY__SHIFT 0x00000006 +#define MC_HUB_MISC_HUB_CG__ONDLY_MASK 0x0000003fL +#define MC_HUB_MISC_HUB_CG__ONDLY__SHIFT 0x00000000 +#define MC_HUB_MISC_HUB_CG__RDYDLY_MASK 0x0003f000L +#define MC_HUB_MISC_HUB_CG__RDYDLY__SHIFT 0x0000000c +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_READ_MASK 0x00000001L +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_READ__SHIFT 0x00000000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_WRITE_MASK 0x00000002L +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_WRITE__SHIFT 0x00000001 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ_MASK 0x00000400L +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ__SHIFT 0x0000000a +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE_MASK 0x00000800L +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE__SHIFT 0x0000000b +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ_MASK 0x00000004L +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ__SHIFT 0x00000002 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE_MASK 0x00000008L +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE__SHIFT 0x00000003 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ_MASK 0x00010000L +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ__SHIFT 0x00000010 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE_MASK 0x00020000L +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE__SHIFT 0x00000011 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ_MASK 0x00040000L +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ__SHIFT 0x00000012 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE_MASK 0x00080000L +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE__SHIFT 0x00000013 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ_MASK 0x00000040L +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ__SHIFT 0x00000006 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE_MASK 0x00000080L +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE__SHIFT 0x00000007 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ_MASK 0x00004000L +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ__SHIFT 0x0000000e +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE_MASK 0x00008000L +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE__SHIFT 0x0000000f +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ_MASK 0x00001000L +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ__SHIFT 0x0000000c +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE_MASK 0x00002000L +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE__SHIFT 0x0000000d +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ_MASK 0x01000000L +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ__SHIFT 0x00000018 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE_MASK 0x02000000L +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE__SHIFT 0x00000019 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ_MASK 0x00100000L +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ__SHIFT 0x00000014 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE_MASK 0x00200000L +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE__SHIFT 0x00000015 +#define MC_HUB_MISC_OVERRIDE__IDLE_MASK 0x00000003L +#define MC_HUB_MISC_OVERRIDE__IDLE__SHIFT 0x00000000 +#define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL_MASK 0x00000018L +#define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL__SHIFT 0x00000003 +#define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE_MASK 0x00000004L +#define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE__SHIFT 0x00000002 +#define MC_HUB_MISC_SIP_CG__ENABLE_MASK 0x00040000L +#define MC_HUB_MISC_SIP_CG__ENABLE__SHIFT 0x00000012 +#define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK 0x00080000L +#define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE__SHIFT 0x00000013 +#define MC_HUB_MISC_SIP_CG__OFFDLY_MASK 0x00000fc0L +#define MC_HUB_MISC_SIP_CG__OFFDLY__SHIFT 0x00000006 +#define MC_HUB_MISC_SIP_CG__ONDLY_MASK 0x0000003fL +#define MC_HUB_MISC_SIP_CG__ONDLY__SHIFT 0x00000000 +#define MC_HUB_MISC_SIP_CG__RDYDLY_MASK 0x0003f000L +#define MC_HUB_MISC_SIP_CG__RDYDLY__SHIFT 0x0000000c +#define MC_HUB_MISC_STATUS__GFX_BUSY_MASK 0x00002000L +#define MC_HUB_MISC_STATUS__GFX_BUSY__SHIFT 0x0000000d +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ_MASK 0x00000004L +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ__SHIFT 0x00000002 +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET_MASK 0x00000008L +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET__SHIFT 0x00000003 +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ_MASK 0x00000010L +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ__SHIFT 0x00000004 +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET_MASK 0x00000020L +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET__SHIFT 0x00000005 +#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ_MASK 0x00000100L +#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ__SHIFT 0x00000008 +#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE_MASK 0x00000200L +#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE__SHIFT 0x00000009 +#define MC_HUB_MISC_STATUS__OUTSTANDING_READ_MASK 0x00000001L +#define MC_HUB_MISC_STATUS__OUTSTANDING_READ__SHIFT 0x00000000 +#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ_MASK 0x00000040L +#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ__SHIFT 0x00000006 +#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE_MASK 0x00000080L +#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE__SHIFT 0x00000007 +#define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE_MASK 0x00000002L +#define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE__SHIFT 0x00000001 +#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING_MASK 0x00001000L +#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING__SHIFT 0x0000000c +#define MC_HUB_MISC_STATUS__RPB_BUSY_MASK 0x00000400L +#define MC_HUB_MISC_STATUS__RPB_BUSY__SHIFT 0x0000000a +#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING_MASK 0x00000800L +#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING__SHIFT 0x0000000b +#define MC_HUB_MISC_VM_CG__ENABLE_MASK 0x00040000L +#define MC_HUB_MISC_VM_CG__ENABLE__SHIFT 0x00000012 +#define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x00080000L +#define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x00000013 +#define MC_HUB_MISC_VM_CG__OFFDLY_MASK 0x00000fc0L +#define MC_HUB_MISC_VM_CG__OFFDLY__SHIFT 0x00000006 +#define MC_HUB_MISC_VM_CG__ONDLY_MASK 0x0000003fL +#define MC_HUB_MISC_VM_CG__ONDLY__SHIFT 0x00000000 +#define MC_HUB_MISC_VM_CG__RDYDLY_MASK 0x0003f000L +#define MC_HUB_MISC_VM_CG__RDYDLY__SHIFT 0x0000000c +#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK_MASK 0x00000200L +#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK__SHIFT 0x00000009 +#define MC_HUB_RDREQ_CNTL__DEBUG_REG_MASK 0x0001fc00L +#define MC_HUB_RDREQ_CNTL__DEBUG_REG__SHIFT 0x0000000a +#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x00020000L +#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0x00000011 +#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x00040000L +#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0x00000012 +#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0_MASK 0x00000004L +#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0__SHIFT 0x00000002 +#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1_MASK 0x00000008L +#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1__SHIFT 0x00000003 +#define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE_MASK 0x00000020L +#define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE__SHIFT 0x00000005 +#define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE_MASK 0x00000040L +#define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE__SHIFT 0x00000006 +#define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE_MASK 0x00000080L +#define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE__SHIFT 0x00000007 +#define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE_MASK 0x00000100L +#define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE__SHIFT 0x00000008 +#define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x00000010L +#define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x00000004 +#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE_MASK 0x00080000L +#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE__SHIFT 0x00000013 +#define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT_MASK 0x00000001L +#define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT__SHIFT 0x00000000 +#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI_MASK 0x000000ffL +#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI__SHIFT 0x00000000 +#define MC_HUB_RDREQ_CREDITS__STOR0_MASK 0x00ff0000L +#define MC_HUB_RDREQ_CREDITS__STOR0__SHIFT 0x00000010 +#define MC_HUB_RDREQ_CREDITS__STOR1_MASK 0xff000000L +#define MC_HUB_RDREQ_CREDITS__STOR1__SHIFT 0x00000018 +#define MC_HUB_RDREQ_CREDITS__VM0_MASK 0x000000ffL +#define MC_HUB_RDREQ_CREDITS__VM0__SHIFT 0x00000000 +#define MC_HUB_RDREQ_CREDITS__VM1_MASK 0x0000ff00L +#define MC_HUB_RDREQ_CREDITS__VM1__SHIFT 0x00000008 +#define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_RDREQ_DMIF__ENABLE_MASK 0x00000001L +#define MC_HUB_RDREQ_DMIF__ENABLE__SHIFT 0x00000000 +#define MC_HUB_RDREQ_DMIF__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_RDREQ_DMIF__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 0x00000003L +#define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 0x00000000 +#define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT_MASK 0x0000007cL +#define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT__SHIFT 0x00000002 +#define MC_HUB_RDREQ_DMIF__MAXBURST_MASK 0x00000780L +#define MC_HUB_RDREQ_DMIF__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_RDREQ_DMIF__PRESCALE_MASK 0x00000006L +#define MC_HUB_RDREQ_DMIF__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_RDREQ_DMIF__STALL_MODE_MASK 0x00000030L +#define MC_HUB_RDREQ_DMIF__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_MASK 0x000000ffL +#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD__SHIFT 0x00000000 +#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_MASK 0x000000ffL +#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD__SHIFT 0x00000000 +#define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_RDREQ_HDP__ENABLE_MASK 0x00000001L +#define MC_HUB_RDREQ_HDP__ENABLE__SHIFT 0x00000000 +#define MC_HUB_RDREQ_HDP__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_RDREQ_HDP__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_RDREQ_HDP__MAXBURST_MASK 0x00000780L +#define MC_HUB_RDREQ_HDP__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_RDREQ_HDP__PRESCALE_MASK 0x00000006L +#define MC_HUB_RDREQ_HDP__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_RDREQ_HDP__STALL_MODE_MASK 0x00000030L +#define MC_HUB_RDREQ_HDP__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_RDREQ_MCDW__ASK_CREDITS_MASK 0x0003f800L +#define MC_HUB_RDREQ_MCDW__ASK_CREDITS__SHIFT 0x0000000b +#define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT_MASK 0x00000002L +#define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT__SHIFT 0x00000001 +#define MC_HUB_RDREQ_MCDW__BUS_MASK 0x00000004L +#define MC_HUB_RDREQ_MCDW__BUS__SHIFT 0x00000002 +#define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS_MASK 0x01fc0000L +#define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS__SHIFT 0x00000012 +#define MC_HUB_RDREQ_MCDW__ENABLE_MASK 0x00000001L +#define MC_HUB_RDREQ_MCDW__ENABLE__SHIFT 0x00000000 +#define MC_HUB_RDREQ_MCDW__LAZY_TIMER_MASK 0x00000780L +#define MC_HUB_RDREQ_MCDW__LAZY_TIMER__SHIFT 0x00000007 +#define MC_HUB_RDREQ_MCDW__MAXBURST_MASK 0x00000078L +#define MC_HUB_RDREQ_MCDW__MAXBURST__SHIFT 0x00000003 +#define MC_HUB_RDREQ_MCDW__STALL_THRESHOLD_MASK 0xfe000000L +#define MC_HUB_RDREQ_MCDW__STALL_THRESHOLD__SHIFT 0x00000019 +#define MC_HUB_RDREQ_MCDX__ASK_CREDITS_MASK 0x0003f800L +#define MC_HUB_RDREQ_MCDX__ASK_CREDITS__SHIFT 0x0000000b +#define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT_MASK 0x00000002L +#define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT__SHIFT 0x00000001 +#define MC_HUB_RDREQ_MCDX__BUS_MASK 0x00000004L +#define MC_HUB_RDREQ_MCDX__BUS__SHIFT 0x00000002 +#define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS_MASK 0x01fc0000L +#define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS__SHIFT 0x00000012 +#define MC_HUB_RDREQ_MCDX__ENABLE_MASK 0x00000001L +#define MC_HUB_RDREQ_MCDX__ENABLE__SHIFT 0x00000000 +#define MC_HUB_RDREQ_MCDX__LAZY_TIMER_MASK 0x00000780L +#define MC_HUB_RDREQ_MCDX__LAZY_TIMER__SHIFT 0x00000007 +#define MC_HUB_RDREQ_MCDX__MAXBURST_MASK 0x00000078L +#define MC_HUB_RDREQ_MCDX__MAXBURST__SHIFT 0x00000003 +#define MC_HUB_RDREQ_MCDX__STALL_THRESHOLD_MASK 0xfe000000L +#define MC_HUB_RDREQ_MCDX__STALL_THRESHOLD__SHIFT 0x00000019 +#define MC_HUB_RDREQ_MCDY__ASK_CREDITS_MASK 0x0003f800L +#define MC_HUB_RDREQ_MCDY__ASK_CREDITS__SHIFT 0x0000000b +#define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT_MASK 0x00000002L +#define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT__SHIFT 0x00000001 +#define MC_HUB_RDREQ_MCDY__BUS_MASK 0x00000004L +#define MC_HUB_RDREQ_MCDY__BUS__SHIFT 0x00000002 +#define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS_MASK 0x01fc0000L +#define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS__SHIFT 0x00000012 +#define MC_HUB_RDREQ_MCDY__ENABLE_MASK 0x00000001L +#define MC_HUB_RDREQ_MCDY__ENABLE__SHIFT 0x00000000 +#define MC_HUB_RDREQ_MCDY__LAZY_TIMER_MASK 0x00000780L +#define MC_HUB_RDREQ_MCDY__LAZY_TIMER__SHIFT 0x00000007 +#define MC_HUB_RDREQ_MCDY__MAXBURST_MASK 0x00000078L +#define MC_HUB_RDREQ_MCDY__MAXBURST__SHIFT 0x00000003 +#define MC_HUB_RDREQ_MCDY__STALL_THRESHOLD_MASK 0xfe000000L +#define MC_HUB_RDREQ_MCDY__STALL_THRESHOLD__SHIFT 0x00000019 +#define MC_HUB_RDREQ_MCDZ__ASK_CREDITS_MASK 0x0003f800L +#define MC_HUB_RDREQ_MCDZ__ASK_CREDITS__SHIFT 0x0000000b +#define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT_MASK 0x00000002L +#define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x00000001 +#define MC_HUB_RDREQ_MCDZ__BUS_MASK 0x00000004L +#define MC_HUB_RDREQ_MCDZ__BUS__SHIFT 0x00000002 +#define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS_MASK 0x01fc0000L +#define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS__SHIFT 0x00000012 +#define MC_HUB_RDREQ_MCDZ__ENABLE_MASK 0x00000001L +#define MC_HUB_RDREQ_MCDZ__ENABLE__SHIFT 0x00000000 +#define MC_HUB_RDREQ_MCDZ__LAZY_TIMER_MASK 0x00000780L +#define MC_HUB_RDREQ_MCDZ__LAZY_TIMER__SHIFT 0x00000007 +#define MC_HUB_RDREQ_MCDZ__MAXBURST_MASK 0x00000078L +#define MC_HUB_RDREQ_MCDZ__MAXBURST__SHIFT 0x00000003 +#define MC_HUB_RDREQ_MCDZ__STALL_THRESHOLD_MASK 0xfe000000L +#define MC_HUB_RDREQ_MCDZ__STALL_THRESHOLD__SHIFT 0x00000019 +#define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_RDREQ_MCIF__ENABLE_MASK 0x00000001L +#define MC_HUB_RDREQ_MCIF__ENABLE__SHIFT 0x00000000 +#define MC_HUB_RDREQ_MCIF__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_RDREQ_MCIF__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_RDREQ_MCIF__MAXBURST_MASK 0x00000780L +#define MC_HUB_RDREQ_MCIF__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_RDREQ_MCIF__PRESCALE_MASK 0x00000006L +#define MC_HUB_RDREQ_MCIF__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_RDREQ_MCIF__STALL_MODE_MASK 0x00000030L +#define MC_HUB_RDREQ_MCIF__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_RDREQ_RLC__ENABLE_MASK 0x00000001L +#define MC_HUB_RDREQ_RLC__ENABLE__SHIFT 0x00000000 +#define MC_HUB_RDREQ_RLC__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_RDREQ_RLC__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_RDREQ_RLC__MAXBURST_MASK 0x00000780L +#define MC_HUB_RDREQ_RLC__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_RDREQ_RLC__PRESCALE_MASK 0x00000006L +#define MC_HUB_RDREQ_RLC__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_RDREQ_RLC__STALL_MODE_MASK 0x00000030L +#define MC_HUB_RDREQ_RLC__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_RDREQ_SEM__ENABLE_MASK 0x00000001L +#define MC_HUB_RDREQ_SEM__ENABLE__SHIFT 0x00000000 +#define MC_HUB_RDREQ_SEM__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_RDREQ_SEM__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_RDREQ_SEM__MAXBURST_MASK 0x00000780L +#define MC_HUB_RDREQ_SEM__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_RDREQ_SEM__PRESCALE_MASK 0x00000006L +#define MC_HUB_RDREQ_SEM__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_RDREQ_SEM__STALL_MODE_MASK 0x00000030L +#define MC_HUB_RDREQ_SEM__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_RDREQ_SIP__ASK_CREDITS_MASK 0x0000007fL +#define MC_HUB_RDREQ_SIP__ASK_CREDITS__SHIFT 0x00000000 +#define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS_MASK 0x00007f00L +#define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS__SHIFT 0x00000008 +#define MC_HUB_RDREQ_SIP__DUMMY_MASK 0x00000080L +#define MC_HUB_RDREQ_SIP__DUMMY__SHIFT 0x00000007 +#define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_RDREQ_SMU__ENABLE_MASK 0x00000001L +#define MC_HUB_RDREQ_SMU__ENABLE__SHIFT 0x00000000 +#define MC_HUB_RDREQ_SMU__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_RDREQ_SMU__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_RDREQ_SMU__MAXBURST_MASK 0x00000780L +#define MC_HUB_RDREQ_SMU__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_RDREQ_SMU__PRESCALE_MASK 0x00000006L +#define MC_HUB_RDREQ_SMU__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_RDREQ_SMU__STALL_MODE_MASK 0x00000030L +#define MC_HUB_RDREQ_SMU__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x00000080L +#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0x00000007 +#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL_MASK 0x00000040L +#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL__SHIFT 0x00000006 +#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL_MASK 0x00000020L +#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL__SHIFT 0x00000005 +#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x00000400L +#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0x0000000a +#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL_MASK 0x00000200L +#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL__SHIFT 0x00000009 +#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL_MASK 0x00000100L +#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL__SHIFT 0x00000008 +#define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL_MASK 0x00000002L +#define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL__SHIFT 0x00000001 +#define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL_MASK 0x00000004L +#define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL__SHIFT 0x00000002 +#define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL_MASK 0x00000008L +#define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL__SHIFT 0x00000003 +#define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL_MASK 0x00000010L +#define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL__SHIFT 0x00000004 +#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR_MASK 0x00000800L +#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR__SHIFT 0x0000000b +#define MC_HUB_RDREQ_STATUS__SIP_AVAIL_MASK 0x00000001L +#define MC_HUB_RDREQ_STATUS__SIP_AVAIL__SHIFT 0x00000000 +#define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_RDREQ_UMC__ENABLE_MASK 0x00000001L +#define MC_HUB_RDREQ_UMC__ENABLE__SHIFT 0x00000000 +#define MC_HUB_RDREQ_UMC__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_RDREQ_UMC__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_RDREQ_UMC__MAXBURST_MASK 0x00000780L +#define MC_HUB_RDREQ_UMC__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_RDREQ_UMC__PRESCALE_MASK 0x00000006L +#define MC_HUB_RDREQ_UMC__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_RDREQ_UMC__STALL_MODE_MASK 0x00000030L +#define MC_HUB_RDREQ_UMC__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_RDREQ_UVD__ENABLE_MASK 0x00000001L +#define MC_HUB_RDREQ_UVD__ENABLE__SHIFT 0x00000000 +#define MC_HUB_RDREQ_UVD__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_RDREQ_UVD__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_RDREQ_UVD__MAXBURST_MASK 0x00000780L +#define MC_HUB_RDREQ_UVD__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_RDREQ_UVD__PRESCALE_MASK 0x00000006L +#define MC_HUB_RDREQ_UVD__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_RDREQ_UVD__STALL_MODE_MASK 0x00000030L +#define MC_HUB_RDREQ_UVD__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_RDREQ_UVD__VM_BYPASS_MASK 0x00010000L +#define MC_HUB_RDREQ_UVD__VM_BYPASS__SHIFT 0x00000010 +#define MC_HUB_RDREQ_VCE__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_RDREQ_VCE__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_RDREQ_VCE__ENABLE_MASK 0x00000001L +#define MC_HUB_RDREQ_VCE__ENABLE__SHIFT 0x00000000 +#define MC_HUB_RDREQ_VCE__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_RDREQ_VCE__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_RDREQ_VCE__MAXBURST_MASK 0x00000780L +#define MC_HUB_RDREQ_VCE__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_RDREQ_VCE__PRESCALE_MASK 0x00000006L +#define MC_HUB_RDREQ_VCE__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_RDREQ_VCE__STALL_MODE_MASK 0x00000030L +#define MC_HUB_RDREQ_VCE__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_RDREQ_VCEU__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_RDREQ_VCEU__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_RDREQ_VCEU__ENABLE_MASK 0x00000001L +#define MC_HUB_RDREQ_VCEU__ENABLE__SHIFT 0x00000000 +#define MC_HUB_RDREQ_VCEU__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_RDREQ_VCEU__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_RDREQ_VCEU__MAXBURST_MASK 0x00000780L +#define MC_HUB_RDREQ_VCEU__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_RDREQ_VCEU__PRESCALE_MASK 0x00000006L +#define MC_HUB_RDREQ_VCEU__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_RDREQ_VCEU__STALL_MODE_MASK 0x00000030L +#define MC_HUB_RDREQ_VCEU__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_RDREQ_VMC__ENABLE_MASK 0x00000001L +#define MC_HUB_RDREQ_VMC__ENABLE__SHIFT 0x00000000 +#define MC_HUB_RDREQ_VMC__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_RDREQ_VMC__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_RDREQ_VMC__MAXBURST_MASK 0x00000780L +#define MC_HUB_RDREQ_VMC__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_RDREQ_VMC__PRESCALE_MASK 0x00000006L +#define MC_HUB_RDREQ_VMC__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_RDREQ_VMC__STALL_MODE_MASK 0x00000030L +#define MC_HUB_RDREQ_VMC__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT_MASK 0x00000007L +#define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x00000000 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT_MASK 0x00000038L +#define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x00000003 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT_MASK 0x000001c0L +#define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x00000006 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT_MASK 0x00000e00L +#define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x00000009 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT_MASK 0x00007000L +#define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0x0000000c +#define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT_MASK 0x00038000L +#define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0x0000000f +#define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT_MASK 0x001c0000L +#define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x00000012 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT_MASK 0x00e00000L +#define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x00000015 +#define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_RDREQ_XDMAM__ENABLE_MASK 0x00000001L +#define MC_HUB_RDREQ_XDMAM__ENABLE__SHIFT 0x00000000 +#define MC_HUB_RDREQ_XDMAM__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_RDREQ_XDMAM__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_RDREQ_XDMAM__MAXBURST_MASK 0x00000780L +#define MC_HUB_RDREQ_XDMAM__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_RDREQ_XDMAM__PRESCALE_MASK 0x00000006L +#define MC_HUB_RDREQ_XDMAM__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_RDREQ_XDMAM__STALL_MODE_MASK 0x00000030L +#define MC_HUB_RDREQ_XDMAM__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_SHARED_DAGB_DLY__CLI_MASK 0x001f0000L +#define MC_HUB_SHARED_DAGB_DLY__CLI__SHIFT 0x00000010 +#define MC_HUB_SHARED_DAGB_DLY__DLY_MASK 0x0000003fL +#define MC_HUB_SHARED_DAGB_DLY__DLY__SHIFT 0x00000000 +#define MC_HUB_SHARED_DAGB_DLY__POS_MASK 0x1f000000L +#define MC_HUB_SHARED_DAGB_DLY__POS__SHIFT 0x00000018 +#define MC_HUB_WDP_BP__ENABLE_MASK 0x00000001L +#define MC_HUB_WDP_BP__ENABLE__SHIFT 0x00000000 +#define MC_HUB_WDP_BP__RDRET_MASK 0x0003fffeL +#define MC_HUB_WDP_BP__RDRET__SHIFT 0x00000001 +#define MC_HUB_WDP_BP__WRREQ_MASK 0x3ffc0000L +#define MC_HUB_WDP_BP__WRREQ__SHIFT 0x00000012 +#define MC_HUB_WDP_CNTL__DEBUG_REG_MASK 0x00001fe0L +#define MC_HUB_WDP_CNTL__DEBUG_REG__SHIFT 0x00000005 +#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x00002000L +#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0x0000000d +#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x00004000L +#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0x0000000e +#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL_MASK 0x00008000L +#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL__SHIFT 0x0000000f +#define MC_HUB_WDP_CNTL__DISP_WAIT_EOP_MASK 0x00040000L +#define MC_HUB_WDP_CNTL__DISP_WAIT_EOP__SHIFT 0x00000012 +#define MC_HUB_WDP_CNTL__FAIR_CH_SW_MASK 0x00010000L +#define MC_HUB_WDP_CNTL__FAIR_CH_SW__SHIFT 0x00000010 +#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0_MASK 0x00000002L +#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0__SHIFT 0x00000001 +#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1_MASK 0x00000004L +#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1__SHIFT 0x00000002 +#define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL_MASK 0x00000008L +#define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL__SHIFT 0x00000003 +#define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS_MASK 0x00020000L +#define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS__SHIFT 0x00000011 +#define MC_HUB_WDP_CNTL__MCD_WAIT_EOP_MASK 0x00080000L +#define MC_HUB_WDP_CNTL__MCD_WAIT_EOP__SHIFT 0x00000013 +#define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x00000010L +#define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x00000004 +#define MC_HUB_WDP_CNTL__SIP_WAIT_EOP_MASK 0x00100000L +#define MC_HUB_WDP_CNTL__SIP_WAIT_EOP__SHIFT 0x00000014 +#define MC_HUB_WDP_CREDITS__STOR0_MASK 0x00ff0000L +#define MC_HUB_WDP_CREDITS__STOR0__SHIFT 0x00000010 +#define MC_HUB_WDP_CREDITS__STOR1_MASK 0xff000000L +#define MC_HUB_WDP_CREDITS__STOR1__SHIFT 0x00000018 +#define MC_HUB_WDP_CREDITS__VM0_MASK 0x000000ffL +#define MC_HUB_WDP_CREDITS__VM0__SHIFT 0x00000000 +#define MC_HUB_WDP_CREDITS__VM1_MASK 0x0000ff00L +#define MC_HUB_WDP_CREDITS__VM1__SHIFT 0x00000008 +#define MC_HUB_WDP_ERR__MGPU1_TARG_SYS_MASK 0x00000001L +#define MC_HUB_WDP_ERR__MGPU1_TARG_SYS__SHIFT 0x00000000 +#define MC_HUB_WDP_ERR__MGPU2_TARG_SYS_MASK 0x00000002L +#define MC_HUB_WDP_ERR__MGPU2_TARG_SYS__SHIFT 0x00000001 +#define MC_HUB_WDP_GBL0__LAZY_TIMER_MASK 0x000000f0L +#define MC_HUB_WDP_GBL0__LAZY_TIMER__SHIFT 0x00000004 +#define MC_HUB_WDP_GBL0__MAXBURST_MASK 0x0000000fL +#define MC_HUB_WDP_GBL0__MAXBURST__SHIFT 0x00000000 +#define MC_HUB_WDP_GBL0__STALL_MODE_MASK 0x00010000L +#define MC_HUB_WDP_GBL0__STALL_MODE__SHIFT 0x00000010 +#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_MASK 0x0000ff00L +#define MC_HUB_WDP_GBL0__STALL_THRESHOLD__SHIFT 0x00000008 +#define MC_HUB_WDP_GBL1__LAZY_TIMER_MASK 0x000000f0L +#define MC_HUB_WDP_GBL1__LAZY_TIMER__SHIFT 0x00000004 +#define MC_HUB_WDP_GBL1__MAXBURST_MASK 0x0000000fL +#define MC_HUB_WDP_GBL1__MAXBURST__SHIFT 0x00000000 +#define MC_HUB_WDP_GBL1__STALL_MODE_MASK 0x00010000L +#define MC_HUB_WDP_GBL1__STALL_MODE__SHIFT 0x00000010 +#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_MASK 0x0000ff00L +#define MC_HUB_WDP_GBL1__STALL_THRESHOLD__SHIFT 0x00000008 +#define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_WDP_HDP__ENABLE_MASK 0x00000001L +#define MC_HUB_WDP_HDP__ENABLE__SHIFT 0x00000000 +#define MC_HUB_WDP_HDP__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_WDP_HDP__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_WDP_HDP__MAXBURST_MASK 0x00000780L +#define MC_HUB_WDP_HDP__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_WDP_HDP__PRESCALE_MASK 0x00000006L +#define MC_HUB_WDP_HDP__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_WDP_HDP__STALL_MODE_MASK 0x00000030L +#define MC_HUB_WDP_HDP__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_WDP_HDP__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_WDP_HDP__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_WDP_IH__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_WDP_IH__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_WDP_IH__ENABLE_MASK 0x00000001L +#define MC_HUB_WDP_IH__ENABLE__SHIFT 0x00000000 +#define MC_HUB_WDP_IH__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_WDP_IH__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_WDP_IH__MAXBURST_MASK 0x00000780L +#define MC_HUB_WDP_IH__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_WDP_IH__PRESCALE_MASK 0x00000006L +#define MC_HUB_WDP_IH__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_WDP_IH__STALL_MODE_MASK 0x00000030L +#define MC_HUB_WDP_IH__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_WDP_IH__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_WDP_IH__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_WDP_MCDW__ASK_CREDITS_MASK 0x00001f80L +#define MC_HUB_WDP_MCDW__ASK_CREDITS__SHIFT 0x00000007 +#define MC_HUB_WDP_MCDW__ASK_CREDITS_W_MASK 0x7f000000L +#define MC_HUB_WDP_MCDW__ASK_CREDITS_W__SHIFT 0x00000018 +#define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT_MASK 0x00000002L +#define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT__SHIFT 0x00000001 +#define MC_HUB_WDP_MCDW__ENABLE_MASK 0x00000001L +#define MC_HUB_WDP_MCDW__ENABLE__SHIFT 0x00000000 +#define MC_HUB_WDP_MCDW__LAZY_TIMER_MASK 0x0001e000L +#define MC_HUB_WDP_MCDW__LAZY_TIMER__SHIFT 0x0000000d +#define MC_HUB_WDP_MCDW__MAXBURST_MASK 0x00000078L +#define MC_HUB_WDP_MCDW__MAXBURST__SHIFT 0x00000003 +#define MC_HUB_WDP_MCDW__STALL_MODE_MASK 0x00000004L +#define MC_HUB_WDP_MCDW__STALL_MODE__SHIFT 0x00000002 +#define MC_HUB_WDP_MCDW__STALL_THRESHOLD_MASK 0x00fe0000L +#define MC_HUB_WDP_MCDW__STALL_THRESHOLD__SHIFT 0x00000011 +#define MC_HUB_WDP_MCDX__ASK_CREDITS_MASK 0x00001f80L +#define MC_HUB_WDP_MCDX__ASK_CREDITS__SHIFT 0x00000007 +#define MC_HUB_WDP_MCDX__ASK_CREDITS_W_MASK 0x7f000000L +#define MC_HUB_WDP_MCDX__ASK_CREDITS_W__SHIFT 0x00000018 +#define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT_MASK 0x00000002L +#define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT__SHIFT 0x00000001 +#define MC_HUB_WDP_MCDX__ENABLE_MASK 0x00000001L +#define MC_HUB_WDP_MCDX__ENABLE__SHIFT 0x00000000 +#define MC_HUB_WDP_MCDX__LAZY_TIMER_MASK 0x0001e000L +#define MC_HUB_WDP_MCDX__LAZY_TIMER__SHIFT 0x0000000d +#define MC_HUB_WDP_MCDX__MAXBURST_MASK 0x00000078L +#define MC_HUB_WDP_MCDX__MAXBURST__SHIFT 0x00000003 +#define MC_HUB_WDP_MCDX__STALL_MODE_MASK 0x00000004L +#define MC_HUB_WDP_MCDX__STALL_MODE__SHIFT 0x00000002 +#define MC_HUB_WDP_MCDX__STALL_THRESHOLD_MASK 0x00fe0000L +#define MC_HUB_WDP_MCDX__STALL_THRESHOLD__SHIFT 0x00000011 +#define MC_HUB_WDP_MCDY__ASK_CREDITS_MASK 0x00001f80L +#define MC_HUB_WDP_MCDY__ASK_CREDITS__SHIFT 0x00000007 +#define MC_HUB_WDP_MCDY__ASK_CREDITS_W_MASK 0x7f000000L +#define MC_HUB_WDP_MCDY__ASK_CREDITS_W__SHIFT 0x00000018 +#define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT_MASK 0x00000002L +#define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT__SHIFT 0x00000001 +#define MC_HUB_WDP_MCDY__ENABLE_MASK 0x00000001L +#define MC_HUB_WDP_MCDY__ENABLE__SHIFT 0x00000000 +#define MC_HUB_WDP_MCDY__LAZY_TIMER_MASK 0x0001e000L +#define MC_HUB_WDP_MCDY__LAZY_TIMER__SHIFT 0x0000000d +#define MC_HUB_WDP_MCDY__MAXBURST_MASK 0x00000078L +#define MC_HUB_WDP_MCDY__MAXBURST__SHIFT 0x00000003 +#define MC_HUB_WDP_MCDY__STALL_MODE_MASK 0x00000004L +#define MC_HUB_WDP_MCDY__STALL_MODE__SHIFT 0x00000002 +#define MC_HUB_WDP_MCDY__STALL_THRESHOLD_MASK 0x00fe0000L +#define MC_HUB_WDP_MCDY__STALL_THRESHOLD__SHIFT 0x00000011 +#define MC_HUB_WDP_MCDZ__ASK_CREDITS_MASK 0x00001f80L +#define MC_HUB_WDP_MCDZ__ASK_CREDITS__SHIFT 0x00000007 +#define MC_HUB_WDP_MCDZ__ASK_CREDITS_W_MASK 0x7f000000L +#define MC_HUB_WDP_MCDZ__ASK_CREDITS_W__SHIFT 0x00000018 +#define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT_MASK 0x00000002L +#define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x00000001 +#define MC_HUB_WDP_MCDZ__ENABLE_MASK 0x00000001L +#define MC_HUB_WDP_MCDZ__ENABLE__SHIFT 0x00000000 +#define MC_HUB_WDP_MCDZ__LAZY_TIMER_MASK 0x0001e000L +#define MC_HUB_WDP_MCDZ__LAZY_TIMER__SHIFT 0x0000000d +#define MC_HUB_WDP_MCDZ__MAXBURST_MASK 0x00000078L +#define MC_HUB_WDP_MCDZ__MAXBURST__SHIFT 0x00000003 +#define MC_HUB_WDP_MCDZ__STALL_MODE_MASK 0x00000004L +#define MC_HUB_WDP_MCDZ__STALL_MODE__SHIFT 0x00000002 +#define MC_HUB_WDP_MCDZ__STALL_THRESHOLD_MASK 0x00fe0000L +#define MC_HUB_WDP_MCDZ__STALL_THRESHOLD__SHIFT 0x00000011 +#define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_WDP_MCIF__ENABLE_MASK 0x00000001L +#define MC_HUB_WDP_MCIF__ENABLE__SHIFT 0x00000000 +#define MC_HUB_WDP_MCIF__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_WDP_MCIF__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_WDP_MCIF__MAXBURST_MASK 0x00000780L +#define MC_HUB_WDP_MCIF__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_WDP_MCIF__PRESCALE_MASK 0x00000006L +#define MC_HUB_WDP_MCIF__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_WDP_MCIF__STALL_MODE_MASK 0x00000030L +#define MC_HUB_WDP_MCIF__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_WDP_MCIF__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_WDP_MGPU2__CID2_MASK 0x000000ffL +#define MC_HUB_WDP_MGPU2__CID2__SHIFT 0x00000000 +#define MC_HUB_WDP_MGPU__CID_MASK 0x0000ff00L +#define MC_HUB_WDP_MGPU__CID__SHIFT 0x00000008 +#define MC_HUB_WDP_MGPU__ENABLE_MASK 0x00800000L +#define MC_HUB_WDP_MGPU__ENABLE__SHIFT 0x00000017 +#define MC_HUB_WDP_MGPU__MGPU_PRIORITY_TIME_MASK 0x007f0000L +#define MC_HUB_WDP_MGPU__MGPU_PRIORITY_TIME__SHIFT 0x00000010 +#define MC_HUB_WDP_MGPU__OTH_PRIORITY_TIME_MASK 0x7f000000L +#define MC_HUB_WDP_MGPU__OTH_PRIORITY_TIME__SHIFT 0x00000018 +#define MC_HUB_WDP_MGPU__STOR_MASK 0x000000ffL +#define MC_HUB_WDP_MGPU__STOR__SHIFT 0x00000000 +#define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_WDP_RLC__ENABLE_MASK 0x00000001L +#define MC_HUB_WDP_RLC__ENABLE__SHIFT 0x00000000 +#define MC_HUB_WDP_RLC__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_WDP_RLC__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_WDP_RLC__MAXBURST_MASK 0x00000780L +#define MC_HUB_WDP_RLC__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_WDP_RLC__PRESCALE_MASK 0x00000006L +#define MC_HUB_WDP_RLC__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_WDP_RLC__STALL_MODE_MASK 0x00000030L +#define MC_HUB_WDP_RLC__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_WDP_RLC__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_WDP_RLC__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_WDP_SEM__ENABLE_MASK 0x00000001L +#define MC_HUB_WDP_SEM__ENABLE__SHIFT 0x00000000 +#define MC_HUB_WDP_SEM__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_WDP_SEM__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_WDP_SEM__MAXBURST_MASK 0x00000780L +#define MC_HUB_WDP_SEM__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_WDP_SEM__PRESCALE_MASK 0x00000006L +#define MC_HUB_WDP_SEM__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_WDP_SEM__STALL_MODE_MASK 0x00000030L +#define MC_HUB_WDP_SEM__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_WDP_SEM__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_WDP_SEM__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_WDP_SH0__ENABLE_MASK 0x00000001L +#define MC_HUB_WDP_SH0__ENABLE__SHIFT 0x00000000 +#define MC_HUB_WDP_SH0__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_WDP_SH0__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_WDP_SH0__MAXBURST_MASK 0x00000780L +#define MC_HUB_WDP_SH0__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_WDP_SH0__PRESCALE_MASK 0x00000006L +#define MC_HUB_WDP_SH0__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_WDP_SH0__STALL_MODE_MASK 0x00000030L +#define MC_HUB_WDP_SH0__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_WDP_SH0__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_WDP_SH0__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_WDP_SH1__ENABLE_MASK 0x00000001L +#define MC_HUB_WDP_SH1__ENABLE__SHIFT 0x00000000 +#define MC_HUB_WDP_SH1__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_WDP_SH1__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_WDP_SH1__MAXBURST_MASK 0x00000780L +#define MC_HUB_WDP_SH1__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_WDP_SH1__PRESCALE_MASK 0x00000006L +#define MC_HUB_WDP_SH1__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_WDP_SH1__STALL_MODE_MASK 0x00000030L +#define MC_HUB_WDP_SH1__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_WDP_SH1__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_WDP_SH1__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_WDP_SIP__ASK_CREDITS_MASK 0x000001fcL +#define MC_HUB_WDP_SIP__ASK_CREDITS__SHIFT 0x00000002 +#define MC_HUB_WDP_SIP__STALL_MODE_MASK 0x00000003L +#define MC_HUB_WDP_SIP__STALL_MODE__SHIFT 0x00000000 +#define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_WDP_SMU__ENABLE_MASK 0x00000001L +#define MC_HUB_WDP_SMU__ENABLE__SHIFT 0x00000000 +#define MC_HUB_WDP_SMU__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_WDP_SMU__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_WDP_SMU__MAXBURST_MASK 0x00000780L +#define MC_HUB_WDP_SMU__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_WDP_SMU__PRESCALE_MASK 0x00000006L +#define MC_HUB_WDP_SMU__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_WDP_SMU__STALL_MODE_MASK 0x00000030L +#define MC_HUB_WDP_SMU__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_WDP_SMU__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_WDP_SMU__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x00000080L +#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0x00000007 +#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL_MASK 0x00000040L +#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL__SHIFT 0x00000006 +#define MC_HUB_WDP_STATUS__GBL0_VM_FULL_MASK 0x00000020L +#define MC_HUB_WDP_STATUS__GBL0_VM_FULL__SHIFT 0x00000005 +#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x00000400L +#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0x0000000a +#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL_MASK 0x00000200L +#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL__SHIFT 0x00000009 +#define MC_HUB_WDP_STATUS__GBL1_VM_FULL_MASK 0x00000100L +#define MC_HUB_WDP_STATUS__GBL1_VM_FULL__SHIFT 0x00000008 +#define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL_MASK 0x00000002L +#define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL__SHIFT 0x00000001 +#define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL_MASK 0x00000800L +#define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL__SHIFT 0x0000000b +#define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL_MASK 0x00000004L +#define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL__SHIFT 0x00000002 +#define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL_MASK 0x00001000L +#define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL__SHIFT 0x0000000c +#define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL_MASK 0x00000008L +#define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL__SHIFT 0x00000003 +#define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL_MASK 0x00002000L +#define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL__SHIFT 0x0000000d +#define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL_MASK 0x00000010L +#define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL__SHIFT 0x00000004 +#define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL_MASK 0x00004000L +#define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL__SHIFT 0x0000000e +#define MC_HUB_WDP_STATUS__SIP_AVAIL_MASK 0x00000001L +#define MC_HUB_WDP_STATUS__SIP_AVAIL__SHIFT 0x00000000 +#define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_WDP_UMC__ENABLE_MASK 0x00000001L +#define MC_HUB_WDP_UMC__ENABLE__SHIFT 0x00000000 +#define MC_HUB_WDP_UMC__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_WDP_UMC__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_WDP_UMC__MAXBURST_MASK 0x00000780L +#define MC_HUB_WDP_UMC__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_WDP_UMC__PRESCALE_MASK 0x00000006L +#define MC_HUB_WDP_UMC__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_WDP_UMC__STALL_MODE_MASK 0x00000030L +#define MC_HUB_WDP_UMC__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_WDP_UMC__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_WDP_UMC__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_WDP_UVD__ENABLE_MASK 0x00000001L +#define MC_HUB_WDP_UVD__ENABLE__SHIFT 0x00000000 +#define MC_HUB_WDP_UVD__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_WDP_UVD__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_WDP_UVD__MAXBURST_MASK 0x00000780L +#define MC_HUB_WDP_UVD__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_WDP_UVD__PRESCALE_MASK 0x00000006L +#define MC_HUB_WDP_UVD__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_WDP_UVD__STALL_MODE_MASK 0x00000030L +#define MC_HUB_WDP_UVD__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_WDP_UVD__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_WDP_UVD__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_WDP_UVD__VM_BYPASS_MASK 0x00010000L +#define MC_HUB_WDP_UVD__VM_BYPASS__SHIFT 0x00000010 +#define MC_HUB_WDP_VCE__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_WDP_VCE__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_WDP_VCE__ENABLE_MASK 0x00000001L +#define MC_HUB_WDP_VCE__ENABLE__SHIFT 0x00000000 +#define MC_HUB_WDP_VCE__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_WDP_VCE__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_WDP_VCE__MAXBURST_MASK 0x00000780L +#define MC_HUB_WDP_VCE__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_WDP_VCE__PRESCALE_MASK 0x00000006L +#define MC_HUB_WDP_VCE__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_WDP_VCE__STALL_MODE_MASK 0x00000030L +#define MC_HUB_WDP_VCE__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_WDP_VCE__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_WDP_VCE__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_WDP_VCE__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_WDP_VCE__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_WDP_VCEU__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_WDP_VCEU__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_WDP_VCEU__ENABLE_MASK 0x00000001L +#define MC_HUB_WDP_VCEU__ENABLE__SHIFT 0x00000000 +#define MC_HUB_WDP_VCEU__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_WDP_VCEU__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_WDP_VCEU__MAXBURST_MASK 0x00000780L +#define MC_HUB_WDP_VCEU__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_WDP_VCEU__PRESCALE_MASK 0x00000006L +#define MC_HUB_WDP_VCEU__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_WDP_VCEU__STALL_MODE_MASK 0x00000030L +#define MC_HUB_WDP_VCEU__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_WDP_VCEU__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_WDP_VCEU__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_WDP_VCEU__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_WDP_VCEU__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT_MASK 0x00000007L +#define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x00000000 +#define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT_MASK 0x00000038L +#define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x00000003 +#define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT_MASK 0x000001c0L +#define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x00000006 +#define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT_MASK 0x00000e00L +#define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x00000009 +#define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT_MASK 0x00007000L +#define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0x0000000c +#define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT_MASK 0x00038000L +#define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0x0000000f +#define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT_MASK 0x001c0000L +#define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x00000012 +#define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT_MASK 0x00e00000L +#define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x00000015 +#define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE_MASK 0x00010000L +#define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE__SHIFT 0x00000010 +#define MC_HUB_WDP_XDMA__ENABLE_MASK 0x00000001L +#define MC_HUB_WDP_XDMA__ENABLE__SHIFT 0x00000000 +#define MC_HUB_WDP_XDMA__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_WDP_XDMA__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_WDP_XDMA__MAXBURST_MASK 0x00000780L +#define MC_HUB_WDP_XDMA__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE_MASK 0x00010000L +#define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x00000010 +#define MC_HUB_WDP_XDMAM__ENABLE_MASK 0x00000001L +#define MC_HUB_WDP_XDMAM__ENABLE__SHIFT 0x00000000 +#define MC_HUB_WDP_XDMAM__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_WDP_XDMAM__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_WDP_XDMAM__MAXBURST_MASK 0x00000780L +#define MC_HUB_WDP_XDMAM__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_WDP_XDMAM__PRESCALE_MASK 0x00000006L +#define MC_HUB_WDP_XDMAM__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_WDP_XDMAM__STALL_MODE_MASK 0x00000030L +#define MC_HUB_WDP_XDMAM__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_WDP_XDMA__PRESCALE_MASK 0x00000006L +#define MC_HUB_WDP_XDMA__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_WDP_XDMA__STALL_MODE_MASK 0x00000030L +#define MC_HUB_WDP_XDMA__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_WDP_XDMA__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_WDP_XDP__ENABLE_MASK 0x00000001L +#define MC_HUB_WDP_XDP__ENABLE__SHIFT 0x00000000 +#define MC_HUB_WDP_XDP__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_WDP_XDP__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_WDP_XDP__MAXBURST_MASK 0x00000780L +#define MC_HUB_WDP_XDP__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_WDP_XDP__PRESCALE_MASK 0x00000006L +#define MC_HUB_WDP_XDP__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_WDP_XDP__STALL_MODE_MASK 0x00000030L +#define MC_HUB_WDP_XDP__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_WDP_XDP__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_WDP_XDP__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_WRRET_CNTL__BP_ENABLE_MASK 0x00200000L +#define MC_HUB_WRRET_CNTL__BP_ENABLE__SHIFT 0x00000015 +#define MC_HUB_WRRET_CNTL__BP_MASK 0x001ffffeL +#define MC_HUB_WRRET_CNTL__BP__SHIFT 0x00000001 +#define MC_HUB_WRRET_CNTL__DEBUG_REG_MASK 0x3fc00000L +#define MC_HUB_WRRET_CNTL__DEBUG_REG__SHIFT 0x00000016 +#define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT_MASK 0x40000000L +#define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT__SHIFT 0x0000001e +#define MC_HUB_WRRET_CNTL__FAIR_CH_SW_MASK 0x80000000L +#define MC_HUB_WRRET_CNTL__FAIR_CH_SW__SHIFT 0x0000001f +#define MC_HUB_WRRET_CNTL__JUMPAHEAD_MASK 0x00000001L +#define MC_HUB_WRRET_CNTL__JUMPAHEAD__SHIFT 0x00000000 +#define MC_HUB_WRRET_MCDW__CREDIT_COUNT_MASK 0x000000feL +#define MC_HUB_WRRET_MCDW__CREDIT_COUNT__SHIFT 0x00000001 +#define MC_HUB_WRRET_MCDW__STALL_MODE_MASK 0x00000001L +#define MC_HUB_WRRET_MCDW__STALL_MODE__SHIFT 0x00000000 +#define MC_HUB_WRRET_MCDX__CREDIT_COUNT_MASK 0x000000feL +#define MC_HUB_WRRET_MCDX__CREDIT_COUNT__SHIFT 0x00000001 +#define MC_HUB_WRRET_MCDX__STALL_MODE_MASK 0x00000001L +#define MC_HUB_WRRET_MCDX__STALL_MODE__SHIFT 0x00000000 +#define MC_HUB_WRRET_MCDY__CREDIT_COUNT_MASK 0x000000feL +#define MC_HUB_WRRET_MCDY__CREDIT_COUNT__SHIFT 0x00000001 +#define MC_HUB_WRRET_MCDY__STALL_MODE_MASK 0x00000001L +#define MC_HUB_WRRET_MCDY__STALL_MODE__SHIFT 0x00000000 +#define MC_HUB_WRRET_MCDZ__CREDIT_COUNT_MASK 0x000000feL +#define MC_HUB_WRRET_MCDZ__CREDIT_COUNT__SHIFT 0x00000001 +#define MC_HUB_WRRET_MCDZ__STALL_MODE_MASK 0x00000001L +#define MC_HUB_WRRET_MCDZ__STALL_MODE__SHIFT 0x00000000 +#define MC_HUB_WRRET_STATUS__MCDW_AVAIL_MASK 0x00000001L +#define MC_HUB_WRRET_STATUS__MCDW_AVAIL__SHIFT 0x00000000 +#define MC_HUB_WRRET_STATUS__MCDX_AVAIL_MASK 0x00000002L +#define MC_HUB_WRRET_STATUS__MCDX_AVAIL__SHIFT 0x00000001 +#define MC_HUB_WRRET_STATUS__MCDY_AVAIL_MASK 0x00000004L +#define MC_HUB_WRRET_STATUS__MCDY_AVAIL__SHIFT 0x00000002 +#define MC_HUB_WRRET_STATUS__MCDZ_AVAIL_MASK 0x00000008L +#define MC_HUB_WRRET_STATUS__MCDZ_AVAIL__SHIFT 0x00000003 +#define MC_IMP_CNTL__CAL_PWRON_MASK 0x80000000L +#define MC_IMP_CNTL__CAL_PWRON__SHIFT 0x0000001f +#define MC_IMP_CNTL__CAL_VREF_MASK 0x007f0000L +#define MC_IMP_CNTL__CAL_VREFMODE_MASK 0x00000040L +#define MC_IMP_CNTL__CAL_VREFMODE__SHIFT 0x00000006 +#define MC_IMP_CNTL__CAL_VREF_SEL_MASK 0x00000020L +#define MC_IMP_CNTL__CAL_VREF_SEL__SHIFT 0x00000005 +#define MC_IMP_CNTL__CAL_VREF__SHIFT 0x00000010 +#define MC_IMP_CNTL__CAL_WHEN_IDLE_MASK 0x20000000L +#define MC_IMP_CNTL__CAL_WHEN_IDLE__SHIFT 0x0000001d +#define MC_IMP_CNTL__CAL_WHEN_REFRESH_MASK 0x40000000L +#define MC_IMP_CNTL__CAL_WHEN_REFRESH__SHIFT 0x0000001e +#define MC_IMP_CNTL__CLEAR_TIMEOUT_ERR_MASK 0x00000200L +#define MC_IMP_CNTL__CLEAR_TIMEOUT_ERR__SHIFT 0x00000009 +#define MC_IMP_CNTL__MEM_IO_SAMPLE_CNT_MASK 0x0000e000L +#define MC_IMP_CNTL__MEM_IO_SAMPLE_CNT__SHIFT 0x0000000d +#define MC_IMP_CNTL__MEM_IO_UPDATE_RATE_MASK 0x0000001fL +#define MC_IMP_CNTL__MEM_IO_UPDATE_RATE__SHIFT 0x00000000 +#define MC_IMP_CNTL__TIMEOUT_ERR_MASK 0x00000100L +#define MC_IMP_CNTL__TIMEOUT_ERR__SHIFT 0x00000008 +#define MC_IMP_DEBUG__DEBUG_CAL_DONE_MASK 0x80000000L +#define MC_IMP_DEBUG__DEBUG_CAL_DONE__SHIFT 0x0000001f +#define MC_IMP_DEBUG__DEBUG_CAL_EN_MASK 0x10000000L +#define MC_IMP_DEBUG__DEBUG_CAL_EN__SHIFT 0x0000001c +#define MC_IMP_DEBUG__DEBUG_CAL_INTR_MASK 0x40000000L +#define MC_IMP_DEBUG__DEBUG_CAL_INTR__SHIFT 0x0000001e +#define MC_IMP_DEBUG__DEBUG_CAL_START_MASK 0x20000000L +#define MC_IMP_DEBUG__DEBUG_CAL_START__SHIFT 0x0000001d +#define MC_IMP_DEBUG__PMVCAL_RESERVED_MASK 0x0fff0000L +#define MC_IMP_DEBUG__PMVCAL_RESERVED__SHIFT 0x00000010 +#define MC_IMP_DEBUG__TIMEOUT_CNTR_MASK 0x0000ff00L +#define MC_IMP_DEBUG__TIMEOUT_CNTR__SHIFT 0x00000008 +#define MC_IMP_DEBUG__TSTARTUP_CNTR_MASK 0x000000ffL +#define MC_IMP_DEBUG__TSTARTUP_CNTR__SHIFT 0x00000000 +#define MC_IMP_DQ_STATUS__CH0_DQ_NSTR_MASK 0x0000ff00L +#define MC_IMP_DQ_STATUS__CH0_DQ_NSTR__SHIFT 0x00000008 +#define MC_IMP_DQ_STATUS__CH0_DQ_PSTR_MASK 0x000000ffL +#define MC_IMP_DQ_STATUS__CH0_DQ_PSTR__SHIFT 0x00000000 +#define MC_IMP_DQ_STATUS__CH1_DQ_NSTR_MASK 0xff000000L +#define MC_IMP_DQ_STATUS__CH1_DQ_NSTR__SHIFT 0x00000018 +#define MC_IMP_DQ_STATUS__CH1_DQ_PSTR_MASK 0x00ff0000L +#define MC_IMP_DQ_STATUS__CH1_DQ_PSTR__SHIFT 0x00000010 +#define MC_IMP_STATUS__NSTR_ACCUM_VAL_MASK 0xff000000L +#define MC_IMP_STATUS__NSTR_ACCUM_VAL__SHIFT 0x00000018 +#define MC_IMP_STATUS__NSTR_CAL_MASK 0x00ff0000L +#define MC_IMP_STATUS__NSTR_CAL__SHIFT 0x00000010 +#define MC_IMP_STATUS__PSTR_ACCUM_VAL_MASK 0x0000ff00L +#define MC_IMP_STATUS__PSTR_ACCUM_VAL__SHIFT 0x00000008 +#define MC_IMP_STATUS__PSTR_CAL_MASK 0x000000ffL +#define MC_IMP_STATUS__PSTR_CAL__SHIFT 0x00000000 +#define MC_IO_APHY_STR_CNTL_D0__CAL_SEL_MASK 0x0c000000L +#define MC_IO_APHY_STR_CNTL_D0__CAL_SEL__SHIFT 0x0000001a +#define MC_IO_APHY_STR_CNTL_D0__LOAD_A_STR_MASK 0x10000000L +#define MC_IO_APHY_STR_CNTL_D0__LOAD_A_STR__SHIFT 0x0000001c +#define MC_IO_APHY_STR_CNTL_D0__LOAD_D_RD_STR_MASK 0x20000000L +#define MC_IO_APHY_STR_CNTL_D0__LOAD_D_RD_STR__SHIFT 0x0000001d +#define MC_IO_APHY_STR_CNTL_D0__NSTR_OFF_A_MASK 0x00000fc0L +#define MC_IO_APHY_STR_CNTL_D0__NSTR_OFF_A__SHIFT 0x00000006 +#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_A_MASK 0x0000003fL +#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_A__SHIFT 0x00000000 +#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_D_RD_MASK 0x0003f000L +#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_D_RD__SHIFT 0x0000000c +#define MC_IO_APHY_STR_CNTL_D0__USE_A_CAL_MASK 0x01000000L +#define MC_IO_APHY_STR_CNTL_D0__USE_A_CAL__SHIFT 0x00000018 +#define MC_IO_APHY_STR_CNTL_D0__USE_D_RD_CAL_MASK 0x02000000L +#define MC_IO_APHY_STR_CNTL_D0__USE_D_RD_CAL__SHIFT 0x00000019 +#define MC_IO_APHY_STR_CNTL_D1__CAL_SEL_MASK 0x0c000000L +#define MC_IO_APHY_STR_CNTL_D1__CAL_SEL__SHIFT 0x0000001a +#define MC_IO_APHY_STR_CNTL_D1__LOAD_A_STR_MASK 0x10000000L +#define MC_IO_APHY_STR_CNTL_D1__LOAD_A_STR__SHIFT 0x0000001c +#define MC_IO_APHY_STR_CNTL_D1__LOAD_D_RD_STR_MASK 0x20000000L +#define MC_IO_APHY_STR_CNTL_D1__LOAD_D_RD_STR__SHIFT 0x0000001d +#define MC_IO_APHY_STR_CNTL_D1__NSTR_OFF_A_MASK 0x00000fc0L +#define MC_IO_APHY_STR_CNTL_D1__NSTR_OFF_A__SHIFT 0x00000006 +#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_A_MASK 0x0000003fL +#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_A__SHIFT 0x00000000 +#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_D_RD_MASK 0x0003f000L +#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_D_RD__SHIFT 0x0000000c +#define MC_IO_APHY_STR_CNTL_D1__USE_A_CAL_MASK 0x01000000L +#define MC_IO_APHY_STR_CNTL_D1__USE_A_CAL__SHIFT 0x00000018 +#define MC_IO_APHY_STR_CNTL_D1__USE_D_RD_CAL_MASK 0x02000000L +#define MC_IO_APHY_STR_CNTL_D1__USE_D_RD_CAL__SHIFT 0x00000019 +#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B0_MASK 0x000000ffL +#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B0__SHIFT 0x00000000 +#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B1_MASK 0x0000ff00L +#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B1__SHIFT 0x00000008 +#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B0_MASK 0x00ff0000L +#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B0__SHIFT 0x00000010 +#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B1_MASK 0xff000000L +#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B1__SHIFT 0x00000018 +#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B0_MASK 0x000000ffL +#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B0__SHIFT 0x00000000 +#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B1_MASK 0x0000ff00L +#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B1__SHIFT 0x00000008 +#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B0_MASK 0x00ff0000L +#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B0__SHIFT 0x00000010 +#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B1_MASK 0xff000000L +#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B1__SHIFT 0x00000018 +#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL0_MASK 0x00000001L +#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL0__SHIFT 0x00000000 +#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL1_MASK 0x00000002L +#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL1__SHIFT 0x00000001 +#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR0_MASK 0x00000004L +#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR0__SHIFT 0x00000002 +#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR1_MASK 0x00000008L +#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR1__SHIFT 0x00000003 +#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS0_MASK 0x00000010L +#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS0__SHIFT 0x00000004 +#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS1_MASK 0x00000020L +#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS1__SHIFT 0x00000005 +#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR0_MASK 0x00000040L +#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR0__SHIFT 0x00000006 +#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR1_MASK 0x00000080L +#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR1__SHIFT 0x00000007 +#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL0_MASK 0x00000001L +#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL0__SHIFT 0x00000000 +#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL1_MASK 0x00000002L +#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL1__SHIFT 0x00000001 +#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR0_MASK 0x00000004L +#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR0__SHIFT 0x00000002 +#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR1_MASK 0x00000008L +#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR1__SHIFT 0x00000003 +#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS0_MASK 0x00000010L +#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS0__SHIFT 0x00000004 +#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS1_MASK 0x00000020L +#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS1__SHIFT 0x00000005 +#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR0_MASK 0x00000040L +#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR0__SHIFT 0x00000006 +#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR1_MASK 0x00000080L +#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR1__SHIFT 0x00000007 +#define MC_IO_CDRCNTL_D0__DQRXCDREN_B0_MASK 0x00400000L +#define MC_IO_CDRCNTL_D0__DQRXCDREN_B0__SHIFT 0x00000016 +#define MC_IO_CDRCNTL_D0__DQRXCDREN_B1_MASK 0x00800000L +#define MC_IO_CDRCNTL_D0__DQRXCDREN_B1__SHIFT 0x00000017 +#define MC_IO_CDRCNTL_D0__DQRXSEL_B0_MASK 0x10000000L +#define MC_IO_CDRCNTL_D0__DQRXSEL_B0__SHIFT 0x0000001c +#define MC_IO_CDRCNTL_D0__DQRXSEL_B1_MASK 0x20000000L +#define MC_IO_CDRCNTL_D0__DQRXSEL_B1__SHIFT 0x0000001d +#define MC_IO_CDRCNTL_D0__DQTXCDREN_B0_MASK 0x00100000L +#define MC_IO_CDRCNTL_D0__DQTXCDREN_B0__SHIFT 0x00000014 +#define MC_IO_CDRCNTL_D0__DQTXCDREN_B1_MASK 0x00200000L +#define MC_IO_CDRCNTL_D0__DQTXCDREN_B1__SHIFT 0x00000015 +#define MC_IO_CDRCNTL_D0__DQTXSEL_B0_MASK 0x40000000L +#define MC_IO_CDRCNTL_D0__DQTXSEL_B0__SHIFT 0x0000001e +#define MC_IO_CDRCNTL_D0__DQTXSEL_B1_MASK 0x80000000L +#define MC_IO_CDRCNTL_D0__DQTXSEL_B1__SHIFT 0x0000001f +#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B01_MASK 0x00000400L +#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B01__SHIFT 0x0000000a +#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B23_MASK 0x00000800L +#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B23__SHIFT 0x0000000b +#define MC_IO_CDRCNTL_D0__RXCDREN_B01_MASK 0x00000100L +#define MC_IO_CDRCNTL_D0__RXCDREN_B01__SHIFT 0x00000008 +#define MC_IO_CDRCNTL_D0__RXCDREN_B23_MASK 0x00000200L +#define MC_IO_CDRCNTL_D0__RXCDREN_B23__SHIFT 0x00000009 +#define MC_IO_CDRCNTL_D0__RXPHASE1_B01_MASK 0x0000f000L +#define MC_IO_CDRCNTL_D0__RXPHASE1_B01__SHIFT 0x0000000c +#define MC_IO_CDRCNTL_D0__RXPHASE1_B23_MASK 0x000f0000L +#define MC_IO_CDRCNTL_D0__RXPHASE1_B23__SHIFT 0x00000010 +#define MC_IO_CDRCNTL_D0__RXPHASE_B01_MASK 0x0000000fL +#define MC_IO_CDRCNTL_D0__RXPHASE_B01__SHIFT 0x00000000 +#define MC_IO_CDRCNTL_D0__RXPHASE_B23_MASK 0x000000f0L +#define MC_IO_CDRCNTL_D0__RXPHASE_B23__SHIFT 0x00000004 +#define MC_IO_CDRCNTL_D0__WCDREDC_B0_MASK 0x04000000L +#define MC_IO_CDRCNTL_D0__WCDREDC_B0__SHIFT 0x0000001a +#define MC_IO_CDRCNTL_D0__WCDREDC_B1_MASK 0x08000000L +#define MC_IO_CDRCNTL_D0__WCDREDC_B1__SHIFT 0x0000001b +#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B0_MASK 0x01000000L +#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B0__SHIFT 0x00000018 +#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B1_MASK 0x02000000L +#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B1__SHIFT 0x00000019 +#define MC_IO_CDRCNTL_D1__DQRXCDREN_B0_MASK 0x00400000L +#define MC_IO_CDRCNTL_D1__DQRXCDREN_B0__SHIFT 0x00000016 +#define MC_IO_CDRCNTL_D1__DQRXCDREN_B1_MASK 0x00800000L +#define MC_IO_CDRCNTL_D1__DQRXCDREN_B1__SHIFT 0x00000017 +#define MC_IO_CDRCNTL_D1__DQRXSEL_B0_MASK 0x10000000L +#define MC_IO_CDRCNTL_D1__DQRXSEL_B0__SHIFT 0x0000001c +#define MC_IO_CDRCNTL_D1__DQRXSEL_B1_MASK 0x20000000L +#define MC_IO_CDRCNTL_D1__DQRXSEL_B1__SHIFT 0x0000001d +#define MC_IO_CDRCNTL_D1__DQTXCDREN_B0_MASK 0x00100000L +#define MC_IO_CDRCNTL_D1__DQTXCDREN_B0__SHIFT 0x00000014 +#define MC_IO_CDRCNTL_D1__DQTXCDREN_B1_MASK 0x00200000L +#define MC_IO_CDRCNTL_D1__DQTXCDREN_B1__SHIFT 0x00000015 +#define MC_IO_CDRCNTL_D1__DQTXSEL_B0_MASK 0x40000000L +#define MC_IO_CDRCNTL_D1__DQTXSEL_B0__SHIFT 0x0000001e +#define MC_IO_CDRCNTL_D1__DQTXSEL_B1_MASK 0x80000000L +#define MC_IO_CDRCNTL_D1__DQTXSEL_B1__SHIFT 0x0000001f +#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B01_MASK 0x00000400L +#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B01__SHIFT 0x0000000a +#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B23_MASK 0x00000800L +#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B23__SHIFT 0x0000000b +#define MC_IO_CDRCNTL_D1__RXCDREN_B01_MASK 0x00000100L +#define MC_IO_CDRCNTL_D1__RXCDREN_B01__SHIFT 0x00000008 +#define MC_IO_CDRCNTL_D1__RXCDREN_B23_MASK 0x00000200L +#define MC_IO_CDRCNTL_D1__RXCDREN_B23__SHIFT 0x00000009 +#define MC_IO_CDRCNTL_D1__RXPHASE1_B01_MASK 0x0000f000L +#define MC_IO_CDRCNTL_D1__RXPHASE1_B01__SHIFT 0x0000000c +#define MC_IO_CDRCNTL_D1__RXPHASE1_B23_MASK 0x000f0000L +#define MC_IO_CDRCNTL_D1__RXPHASE1_B23__SHIFT 0x00000010 +#define MC_IO_CDRCNTL_D1__RXPHASE_B01_MASK 0x0000000fL +#define MC_IO_CDRCNTL_D1__RXPHASE_B01__SHIFT 0x00000000 +#define MC_IO_CDRCNTL_D1__RXPHASE_B23_MASK 0x000000f0L +#define MC_IO_CDRCNTL_D1__RXPHASE_B23__SHIFT 0x00000004 +#define MC_IO_CDRCNTL_D1__WCDREDC_B0_MASK 0x04000000L +#define MC_IO_CDRCNTL_D1__WCDREDC_B0__SHIFT 0x0000001a +#define MC_IO_CDRCNTL_D1__WCDREDC_B1_MASK 0x08000000L +#define MC_IO_CDRCNTL_D1__WCDREDC_B1__SHIFT 0x0000001b +#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B0_MASK 0x01000000L +#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B0__SHIFT 0x00000018 +#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B1_MASK 0x02000000L +#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B1__SHIFT 0x00000019 +#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CK_MISC_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CK_MISC_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CK_MISC_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CK_MISC_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CK_MISC_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CK_MISC_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CK_MISC_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CK_MISC_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CK_MISC_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CK_MISC_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CK_MISC_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CK_MISC_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CK_MISC_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CK_MISC_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CK_MISC_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CK_MISC_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CMD_MISC_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CMD_MISC_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CMD_MISC_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CMD_MISC_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CMD_MISC_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CMD_MISC_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CMD_MISC_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CMD_MISC_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CMD_MISC_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CMD_MISC_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CMD_MISC_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CMD_MISC_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CMD_MISC_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CMD_MISC_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CMD_MISC_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CMD_MISC_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DBI_MISC_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DBI_MISC_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DBI_MISC_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DBI_MISC_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DBI_MISC_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DBI_MISC_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DBI_MISC_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DBI_MISC_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DBI_MISC_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DBI_MISC_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DBI_MISC_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DBI_MISC_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DBI_MISC_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DBI_MISC_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DBI_MISC_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DBI_MISC_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_MISC_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_MISC_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_MISC_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_MISC_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_MISC_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_MISC_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_MISC_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_MISC_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_MISC_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_MISC_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_MISC_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_MISC_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_MISC_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_MISC_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_MISC_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_MISC_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_100__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_100__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_100__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_100__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_100__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_100__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_100__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_100__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_101__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_101__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_101__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_101__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_101__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_101__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_101__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_101__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_102__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_102__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_102__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_102__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_102__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_102__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_102__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_102__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_103__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_103__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_103__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_103__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_103__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_103__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_103__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_103__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_104__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_104__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_104__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_104__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_104__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_104__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_104__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_104__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_105__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_105__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_105__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_105__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_105__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_105__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_105__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_105__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_106__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_106__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_106__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_106__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_106__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_106__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_106__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_106__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_107__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_107__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_107__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_107__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_107__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_107__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_107__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_107__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_108__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_108__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_108__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_108__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_108__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_108__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_108__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_108__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_109__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_109__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_109__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_109__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_109__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_109__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_109__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_109__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_10__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_10__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_10__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_10__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_10__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_10__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_10__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_10__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_110__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_110__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_110__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_110__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_110__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_110__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_110__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_110__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_111__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_111__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_111__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_111__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_111__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_111__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_111__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_111__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_112__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_112__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_112__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_112__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_112__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_112__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_112__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_112__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_113__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_113__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_113__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_113__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_113__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_113__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_113__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_113__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_114__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_114__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_114__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_114__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_114__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_114__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_114__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_114__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_115__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_115__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_115__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_115__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_115__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_115__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_115__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_115__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_116__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_116__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_116__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_116__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_116__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_116__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_116__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_116__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_117__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_117__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_117__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_117__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_117__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_117__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_117__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_117__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_118__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_118__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_118__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_118__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_118__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_118__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_118__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_118__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_119__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_119__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_119__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_119__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_119__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_119__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_119__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_119__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_11__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_11__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_11__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_11__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_11__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_11__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_11__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_11__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_120__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_120__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_120__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_120__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_120__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_120__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_120__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_120__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_121__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_121__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_121__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_121__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_121__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_121__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_121__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_121__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_122__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_122__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_122__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_122__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_122__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_122__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_122__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_122__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_123__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_123__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_123__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_123__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_123__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_123__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_123__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_123__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_124__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_124__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_124__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_124__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_124__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_124__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_124__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_124__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_125__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_125__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_125__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_125__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_125__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_125__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_125__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_125__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_126__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_126__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_126__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_126__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_126__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_126__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_126__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_126__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_127__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_127__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_127__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_127__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_127__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_127__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_127__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_127__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_128__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_128__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_128__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_128__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_128__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_128__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_128__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_128__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_129__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_129__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_129__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_129__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_129__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_129__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_129__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_129__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_12__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_12__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_12__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_12__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_12__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_12__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_12__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_12__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_130__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_130__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_130__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_130__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_130__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_130__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_130__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_130__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_131__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_131__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_131__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_131__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_131__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_131__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_131__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_131__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_132__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_132__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_132__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_132__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_132__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_132__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_132__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_132__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_133__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_133__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_133__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_133__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_133__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_133__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_133__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_133__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_134__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_134__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_134__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_134__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_134__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_134__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_134__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_134__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_135__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_135__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_135__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_135__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_135__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_135__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_135__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_135__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_136__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_136__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_136__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_136__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_136__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_136__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_136__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_136__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_137__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_137__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_137__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_137__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_137__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_137__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_137__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_137__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_138__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_138__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_138__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_138__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_138__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_138__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_138__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_138__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_139__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_139__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_139__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_139__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_139__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_139__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_139__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_139__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_13__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_13__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_13__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_13__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_13__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_13__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_13__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_13__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_140__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_140__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_140__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_140__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_140__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_140__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_140__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_140__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_141__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_141__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_141__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_141__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_141__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_141__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_141__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_141__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_142__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_142__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_142__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_142__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_142__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_142__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_142__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_142__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_143__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_143__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_143__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_143__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_143__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_143__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_143__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_143__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_144__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_144__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_144__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_144__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_144__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_144__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_144__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_144__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_145__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_145__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_145__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_145__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_145__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_145__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_145__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_145__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_146__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_146__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_146__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_146__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_146__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_146__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_146__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_146__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_147__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_147__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_147__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_147__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_147__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_147__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_147__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_147__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_148__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_148__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_148__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_148__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_148__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_148__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_148__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_148__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_149__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_149__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_149__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_149__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_149__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_149__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_149__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_149__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_14__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_14__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_14__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_14__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_14__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_14__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_14__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_14__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_150__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_150__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_150__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_150__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_150__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_150__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_150__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_150__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_151__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_151__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_151__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_151__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_151__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_151__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_151__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_151__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_152__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_152__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_152__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_152__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_152__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_152__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_152__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_152__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_153__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_153__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_153__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_153__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_153__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_153__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_153__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_153__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_154__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_154__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_154__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_154__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_154__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_154__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_154__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_154__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_155__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_155__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_155__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_155__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_155__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_155__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_155__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_155__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_156__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_156__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_156__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_156__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_156__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_156__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_156__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_156__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_157__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_157__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_157__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_157__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_157__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_157__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_157__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_157__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_158__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_158__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_158__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_158__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_158__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_158__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_158__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_158__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_159__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_159__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_159__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_159__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_159__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_159__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_159__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_159__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_15__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_15__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_15__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_15__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_15__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_15__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_15__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_15__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_16__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_16__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_16__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_16__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_16__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_16__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_16__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_16__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_17__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_17__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_17__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_17__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_17__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_17__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_17__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_17__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_18__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_18__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_18__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_18__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_18__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_18__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_18__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_18__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_19__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_19__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_19__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_19__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_19__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_19__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_19__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_19__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_20__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_20__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_20__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_20__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_20__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_20__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_20__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_20__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_21__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_21__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_21__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_21__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_21__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_21__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_21__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_21__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_22__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_22__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_22__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_22__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_22__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_22__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_22__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_22__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_23__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_23__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_23__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_23__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_23__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_23__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_23__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_23__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_24__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_24__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_24__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_24__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_24__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_24__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_24__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_24__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_25__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_25__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_25__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_25__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_25__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_25__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_25__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_25__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_26__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_26__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_26__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_26__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_26__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_26__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_26__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_26__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_27__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_27__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_27__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_27__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_27__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_27__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_27__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_27__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_28__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_28__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_28__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_28__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_28__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_28__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_28__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_28__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_29__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_29__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_29__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_29__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_29__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_29__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_29__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_29__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_2__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_2__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_2__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_2__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_2__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_2__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_2__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_2__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_30__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_30__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_30__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_30__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_30__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_30__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_30__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_30__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_31__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_31__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_31__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_31__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_31__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_31__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_31__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_31__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_32__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_32__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_32__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_32__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_32__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_32__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_32__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_32__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_33__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_33__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_33__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_33__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_33__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_33__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_33__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_33__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_34__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_34__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_34__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_34__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_34__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_34__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_34__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_34__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_35__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_35__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_35__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_35__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_35__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_35__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_35__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_35__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_36__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_36__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_36__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_36__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_36__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_36__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_36__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_36__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_37__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_37__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_37__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_37__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_37__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_37__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_37__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_37__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_38__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_38__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_38__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_38__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_38__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_38__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_38__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_38__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_39__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_39__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_39__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_39__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_39__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_39__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_39__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_39__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_3__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_3__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_3__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_3__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_3__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_3__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_3__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_3__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_40__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_40__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_40__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_40__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_40__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_40__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_40__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_40__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_41__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_41__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_41__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_41__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_41__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_41__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_41__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_41__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_42__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_42__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_42__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_42__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_42__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_42__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_42__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_42__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_43__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_43__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_43__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_43__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_43__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_43__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_43__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_43__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_44__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_44__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_44__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_44__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_44__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_44__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_44__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_44__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_45__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_45__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_45__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_45__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_45__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_45__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_45__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_45__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_46__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_46__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_46__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_46__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_46__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_46__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_46__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_46__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_47__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_47__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_47__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_47__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_47__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_47__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_47__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_47__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_48__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_48__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_48__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_48__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_48__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_48__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_48__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_48__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_49__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_49__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_49__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_49__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_49__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_49__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_49__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_49__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_4__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_4__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_4__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_4__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_4__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_4__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_4__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_4__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_50__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_50__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_50__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_50__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_50__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_50__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_50__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_50__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_51__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_51__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_51__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_51__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_51__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_51__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_51__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_51__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_52__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_52__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_52__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_52__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_52__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_52__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_52__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_52__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_53__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_53__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_53__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_53__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_53__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_53__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_53__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_53__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_54__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_54__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_54__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_54__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_54__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_54__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_54__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_54__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_55__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_55__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_55__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_55__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_55__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_55__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_55__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_55__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_56__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_56__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_56__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_56__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_56__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_56__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_56__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_56__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_57__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_57__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_57__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_57__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_57__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_57__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_57__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_57__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_58__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_58__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_58__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_58__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_58__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_58__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_58__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_58__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_59__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_59__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_59__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_59__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_59__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_59__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_59__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_59__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_5__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_5__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_5__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_5__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_5__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_5__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_5__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_5__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_60__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_60__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_60__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_60__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_60__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_60__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_60__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_60__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_61__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_61__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_61__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_61__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_61__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_61__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_61__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_61__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_62__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_62__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_62__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_62__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_62__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_62__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_62__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_62__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_63__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_63__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_63__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_63__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_63__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_63__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_63__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_63__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_64__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_64__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_64__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_64__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_64__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_64__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_64__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_64__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_65__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_65__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_65__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_65__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_65__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_65__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_65__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_65__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_66__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_66__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_66__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_66__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_66__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_66__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_66__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_66__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_67__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_67__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_67__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_67__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_67__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_67__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_67__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_67__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_68__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_68__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_68__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_68__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_68__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_68__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_68__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_68__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_69__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_69__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_69__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_69__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_69__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_69__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_69__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_69__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_6__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_6__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_6__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_6__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_6__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_6__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_6__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_6__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_70__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_70__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_70__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_70__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_70__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_70__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_70__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_70__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_71__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_71__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_71__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_71__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_71__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_71__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_71__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_71__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_72__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_72__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_72__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_72__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_72__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_72__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_72__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_72__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_73__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_73__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_73__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_73__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_73__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_73__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_73__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_73__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_74__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_74__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_74__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_74__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_74__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_74__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_74__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_74__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_75__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_75__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_75__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_75__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_75__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_75__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_75__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_75__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_76__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_76__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_76__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_76__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_76__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_76__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_76__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_76__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_77__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_77__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_77__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_77__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_77__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_77__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_77__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_77__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_78__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_78__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_78__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_78__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_78__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_78__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_78__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_78__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_79__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_79__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_79__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_79__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_79__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_79__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_79__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_79__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_7__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_7__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_7__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_7__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_7__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_7__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_7__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_7__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_80__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_80__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_80__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_80__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_80__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_80__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_80__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_80__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_81__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_81__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_81__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_81__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_81__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_81__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_81__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_81__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_82__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_82__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_82__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_82__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_82__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_82__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_82__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_82__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_83__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_83__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_83__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_83__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_83__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_83__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_83__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_83__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_84__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_84__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_84__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_84__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_84__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_84__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_84__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_84__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_85__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_85__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_85__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_85__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_85__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_85__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_85__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_85__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_86__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_86__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_86__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_86__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_86__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_86__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_86__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_86__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_87__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_87__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_87__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_87__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_87__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_87__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_87__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_87__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_88__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_88__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_88__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_88__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_88__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_88__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_88__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_88__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_89__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_89__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_89__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_89__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_89__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_89__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_89__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_89__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_8__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_8__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_8__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_8__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_8__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_8__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_8__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_8__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_90__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_90__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_90__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_90__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_90__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_90__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_90__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_90__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_91__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_91__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_91__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_91__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_91__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_91__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_91__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_91__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_92__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_92__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_92__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_92__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_92__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_92__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_92__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_92__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_93__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_93__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_93__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_93__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_93__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_93__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_93__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_93__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_94__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_94__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_94__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_94__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_94__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_94__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_94__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_94__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_95__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_95__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_95__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_95__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_95__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_95__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_95__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_95__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_96__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_96__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_96__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_96__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_96__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_96__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_96__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_96__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_97__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_97__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_97__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_97__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_97__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_97__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_97__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_97__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_98__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_98__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_98__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_98__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_98__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_98__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_98__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_98__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_99__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_99__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_99__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_99__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_99__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_99__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_99__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_99__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_9__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_9__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_9__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_9__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_9__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_9__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_9__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_9__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCK_MISC_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCK_MISC_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCK_MISC_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCK_MISC_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCK_MISC_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCK_MISC_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCK_MISC_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCK_MISC_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCK_MISC_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCK_MISC_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCK_MISC_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCK_MISC_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCK_MISC_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCK_MISC_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCK_MISC_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCK_MISC_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DPHY_STR_CNTL_D0__CAL_SEL_MASK 0x0c000000L +#define MC_IO_DPHY_STR_CNTL_D0__CAL_SEL__SHIFT 0x0000001a +#define MC_IO_DPHY_STR_CNTL_D0__LOAD_D_STR_MASK 0x10000000L +#define MC_IO_DPHY_STR_CNTL_D0__LOAD_D_STR__SHIFT 0x0000001c +#define MC_IO_DPHY_STR_CNTL_D0__LOAD_S_STR_MASK 0x20000000L +#define MC_IO_DPHY_STR_CNTL_D0__LOAD_S_STR__SHIFT 0x0000001d +#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_D_MASK 0x00000fc0L +#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_D__SHIFT 0x00000006 +#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_S_MASK 0x00fc0000L +#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_S__SHIFT 0x00000012 +#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_D_MASK 0x0000003fL +#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_D__SHIFT 0x00000000 +#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_S_MASK 0x0003f000L +#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_S__SHIFT 0x0000000c +#define MC_IO_DPHY_STR_CNTL_D0__USE_D_CAL_MASK 0x01000000L +#define MC_IO_DPHY_STR_CNTL_D0__USE_D_CAL__SHIFT 0x00000018 +#define MC_IO_DPHY_STR_CNTL_D0__USE_S_CAL_MASK 0x02000000L +#define MC_IO_DPHY_STR_CNTL_D0__USE_S_CAL__SHIFT 0x00000019 +#define MC_IO_DPHY_STR_CNTL_D1__CAL_SEL_MASK 0x0c000000L +#define MC_IO_DPHY_STR_CNTL_D1__CAL_SEL__SHIFT 0x0000001a +#define MC_IO_DPHY_STR_CNTL_D1__LOAD_D_STR_MASK 0x10000000L +#define MC_IO_DPHY_STR_CNTL_D1__LOAD_D_STR__SHIFT 0x0000001c +#define MC_IO_DPHY_STR_CNTL_D1__LOAD_S_STR_MASK 0x20000000L +#define MC_IO_DPHY_STR_CNTL_D1__LOAD_S_STR__SHIFT 0x0000001d +#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_D_MASK 0x00000fc0L +#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_D__SHIFT 0x00000006 +#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_S_MASK 0x00fc0000L +#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_S__SHIFT 0x00000012 +#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_D_MASK 0x0000003fL +#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_D__SHIFT 0x00000000 +#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_S_MASK 0x0003f000L +#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_S__SHIFT 0x0000000c +#define MC_IO_DPHY_STR_CNTL_D1__USE_D_CAL_MASK 0x01000000L +#define MC_IO_DPHY_STR_CNTL_D1__USE_D_CAL__SHIFT 0x00000018 +#define MC_IO_DPHY_STR_CNTL_D1__USE_S_CAL_MASK 0x02000000L +#define MC_IO_DPHY_STR_CNTL_D1__USE_S_CAL__SHIFT 0x00000019 +#define MC_IO_PAD_CNTL__ATBEN_MASK 0x3f000000L +#define MC_IO_PAD_CNTL__ATBEN__SHIFT 0x00000018 +#define MC_IO_PAD_CNTL__ATBSEL_D0_MASK 0x80000000L +#define MC_IO_PAD_CNTL__ATBSEL_D0__SHIFT 0x0000001f +#define MC_IO_PAD_CNTL__ATBSEL_D1_MASK 0x40000000L +#define MC_IO_PAD_CNTL__ATBSEL_D1__SHIFT 0x0000001e +#define MC_IO_PAD_CNTL__ATBSEL_MASK 0x00f00000L +#define MC_IO_PAD_CNTL__ATBSEL__SHIFT 0x00000014 +#define MC_IO_PAD_CNTL_D0__CK_AUTO_EN_MASK 0x00100000L +#define MC_IO_PAD_CNTL_D0__CK_AUTO_EN__SHIFT 0x00000014 +#define MC_IO_PAD_CNTL_D0__CK_DELAY_N_MASK 0x00c00000L +#define MC_IO_PAD_CNTL_D0__CK_DELAY_N__SHIFT 0x00000016 +#define MC_IO_PAD_CNTL_D0__CK_DELAY_P_MASK 0x03000000L +#define MC_IO_PAD_CNTL_D0__CK_DELAY_P__SHIFT 0x00000018 +#define MC_IO_PAD_CNTL_D0__CK_DELAY_SEL_MASK 0x00200000L +#define MC_IO_PAD_CNTL_D0__CK_DELAY_SEL__SHIFT 0x00000015 +#define MC_IO_PAD_CNTL_D0__DELAY_ADR_SYNC_MASK 0x00000010L +#define MC_IO_PAD_CNTL_D0__DELAY_ADR_SYNC__SHIFT 0x00000004 +#define MC_IO_PAD_CNTL_D0__DELAY_CLK_SYNC_MASK 0x00000004L +#define MC_IO_PAD_CNTL_D0__DELAY_CLK_SYNC__SHIFT 0x00000002 +#define MC_IO_PAD_CNTL_D0__DELAY_CMD_SYNC_MASK 0x00000008L +#define MC_IO_PAD_CNTL_D0__DELAY_CMD_SYNC__SHIFT 0x00000003 +#define MC_IO_PAD_CNTL_D0__DIFF_STR_MASK 0x20000000L +#define MC_IO_PAD_CNTL_D0__DIFF_STR__SHIFT 0x0000001d +#define MC_IO_PAD_CNTL_D0__DISABLE_ADR_MASK 0x00002000L +#define MC_IO_PAD_CNTL_D0__DISABLE_ADR__SHIFT 0x0000000d +#define MC_IO_PAD_CNTL_D0__DISABLE_CMD_MASK 0x00001000L +#define MC_IO_PAD_CNTL_D0__DISABLE_CMD__SHIFT 0x0000000c +#define MC_IO_PAD_CNTL_D0__EN_RD_STR_DLY_MASK 0x00000800L +#define MC_IO_PAD_CNTL_D0__EN_RD_STR_DLY__SHIFT 0x0000000b +#define MC_IO_PAD_CNTL_D0__FORCE_EN_RD_STR_MASK 0x00000400L +#define MC_IO_PAD_CNTL_D0__FORCE_EN_RD_STR__SHIFT 0x0000000a +#define MC_IO_PAD_CNTL_D0__GDDR_PWRON_MASK 0x40000000L +#define MC_IO_PAD_CNTL_D0__GDDR_PWRON__SHIFT 0x0000001e +#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_ADR_MASK 0x00000200L +#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_ADR__SHIFT 0x00000009 +#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CLK_MASK 0x00000080L +#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CLK__SHIFT 0x00000007 +#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CMD_MASK 0x00000100L +#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CMD__SHIFT 0x00000008 +#define MC_IO_PAD_CNTL_D0__TXPWROFF_CKE_MASK 0x08000000L +#define MC_IO_PAD_CNTL_D0__TXPWROFF_CKE__SHIFT 0x0000001b +#define MC_IO_PAD_CNTL_D0__TXPWROFF_CLK_MASK 0x80000000L +#define MC_IO_PAD_CNTL_D0__TXPWROFF_CLK__SHIFT 0x0000001f +#define MC_IO_PAD_CNTL_D0__UNI_STR_MASK 0x10000000L +#define MC_IO_PAD_CNTL_D0__UNI_STR__SHIFT 0x0000001c +#define MC_IO_PAD_CNTL_D0__VREFI_EN_MASK 0x00004000L +#define MC_IO_PAD_CNTL_D0__VREFI_EN__SHIFT 0x0000000e +#define MC_IO_PAD_CNTL_D0__VREFI_SEL_MASK 0x000f8000L +#define MC_IO_PAD_CNTL_D0__VREFI_SEL__SHIFT 0x0000000f +#define MC_IO_PAD_CNTL_D1__CK_AUTO_EN_MASK 0x00100000L +#define MC_IO_PAD_CNTL_D1__CK_AUTO_EN__SHIFT 0x00000014 +#define MC_IO_PAD_CNTL_D1__CK_DELAY_N_MASK 0x00c00000L +#define MC_IO_PAD_CNTL_D1__CK_DELAY_N__SHIFT 0x00000016 +#define MC_IO_PAD_CNTL_D1__CK_DELAY_P_MASK 0x03000000L +#define MC_IO_PAD_CNTL_D1__CK_DELAY_P__SHIFT 0x00000018 +#define MC_IO_PAD_CNTL_D1__CK_DELAY_SEL_MASK 0x00200000L +#define MC_IO_PAD_CNTL_D1__CK_DELAY_SEL__SHIFT 0x00000015 +#define MC_IO_PAD_CNTL_D1__DELAY_ADR_SYNC_MASK 0x00000010L +#define MC_IO_PAD_CNTL_D1__DELAY_ADR_SYNC__SHIFT 0x00000004 +#define MC_IO_PAD_CNTL_D1__DELAY_CLK_SYNC_MASK 0x00000004L +#define MC_IO_PAD_CNTL_D1__DELAY_CLK_SYNC__SHIFT 0x00000002 +#define MC_IO_PAD_CNTL_D1__DELAY_CMD_SYNC_MASK 0x00000008L +#define MC_IO_PAD_CNTL_D1__DELAY_CMD_SYNC__SHIFT 0x00000003 +#define MC_IO_PAD_CNTL_D1__DELAY_DATA_SYNC_MASK 0x00000001L +#define MC_IO_PAD_CNTL_D1__DELAY_DATA_SYNC__SHIFT 0x00000000 +#define MC_IO_PAD_CNTL_D1__DELAY_STR_SYNC_MASK 0x00000002L +#define MC_IO_PAD_CNTL_D1__DELAY_STR_SYNC__SHIFT 0x00000001 +#define MC_IO_PAD_CNTL_D1__DIFF_STR_MASK 0x20000000L +#define MC_IO_PAD_CNTL_D1__DIFF_STR__SHIFT 0x0000001d +#define MC_IO_PAD_CNTL_D1__DISABLE_ADR_MASK 0x00002000L +#define MC_IO_PAD_CNTL_D1__DISABLE_ADR__SHIFT 0x0000000d +#define MC_IO_PAD_CNTL_D1__DISABLE_CMD_MASK 0x00001000L +#define MC_IO_PAD_CNTL_D1__DISABLE_CMD__SHIFT 0x0000000c +#define MC_IO_PAD_CNTL_D1__EN_RD_STR_DLY_MASK 0x00000800L +#define MC_IO_PAD_CNTL_D1__EN_RD_STR_DLY__SHIFT 0x0000000b +#define MC_IO_PAD_CNTL_D1__FORCE_EN_RD_STR_MASK 0x00000400L +#define MC_IO_PAD_CNTL_D1__FORCE_EN_RD_STR__SHIFT 0x0000000a +#define MC_IO_PAD_CNTL_D1__GDDR_PWRON_MASK 0x40000000L +#define MC_IO_PAD_CNTL_D1__GDDR_PWRON__SHIFT 0x0000001e +#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_ADR_MASK 0x00000200L +#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_ADR__SHIFT 0x00000009 +#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CLK_MASK 0x00000080L +#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CLK__SHIFT 0x00000007 +#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CMD_MASK 0x00000100L +#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CMD__SHIFT 0x00000008 +#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_DATA_MASK 0x00000020L +#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_DATA__SHIFT 0x00000005 +#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_STR_MASK 0x00000040L +#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_STR__SHIFT 0x00000006 +#define MC_IO_PAD_CNTL_D1__TXPWROFF_CKE_MASK 0x08000000L +#define MC_IO_PAD_CNTL_D1__TXPWROFF_CKE__SHIFT 0x0000001b +#define MC_IO_PAD_CNTL_D1__TXPWROFF_CLK_MASK 0x80000000L +#define MC_IO_PAD_CNTL_D1__TXPWROFF_CLK__SHIFT 0x0000001f +#define MC_IO_PAD_CNTL_D1__UNI_STR_MASK 0x10000000L +#define MC_IO_PAD_CNTL_D1__UNI_STR__SHIFT 0x0000001c +#define MC_IO_PAD_CNTL_D1__VREFI_EN_MASK 0x00004000L +#define MC_IO_PAD_CNTL_D1__VREFI_EN__SHIFT 0x0000000e +#define MC_IO_PAD_CNTL_D1__VREFI_SEL_MASK 0x000f8000L +#define MC_IO_PAD_CNTL_D1__VREFI_SEL__SHIFT 0x0000000f +#define MC_IO_PAD_CNTL__MEM_IO_IMP_MAX_MASK 0x0000ff00L +#define MC_IO_PAD_CNTL__MEM_IO_IMP_MAX__SHIFT 0x00000008 +#define MC_IO_PAD_CNTL__MEM_IO_IMP_MIN_MASK 0x000000ffL +#define MC_IO_PAD_CNTL__MEM_IO_IMP_MIN__SHIFT 0x00000000 +#define MC_IO_PAD_CNTL__OVL_YCLKON_D0_MASK 0x00040000L +#define MC_IO_PAD_CNTL__OVL_YCLKON_D0__SHIFT 0x00000012 +#define MC_IO_PAD_CNTL__OVL_YCLKON_D1_MASK 0x00080000L +#define MC_IO_PAD_CNTL__OVL_YCLKON_D1__SHIFT 0x00000013 +#define MC_IO_PAD_CNTL__RXPHASE_GRAY_MASK 0x00020000L +#define MC_IO_PAD_CNTL__RXPHASE_GRAY__SHIFT 0x00000011 +#define MC_IO_PAD_CNTL__TXPHASE_GRAY_MASK 0x00010000L +#define MC_IO_PAD_CNTL__TXPHASE_GRAY__SHIFT 0x00000010 +#define MC_IO_RXCNTL1_DPHY0_D0__DLL_RSV_MASK 0xf0000000L +#define MC_IO_RXCNTL1_DPHY0_D0__DLL_RSV__SHIFT 0x0000001c +#define MC_IO_RXCNTL1_DPHY0_D0__PMD_LOOPBACK_MASK 0x0e000000L +#define MC_IO_RXCNTL1_DPHY0_D0__PMD_LOOPBACK__SHIFT 0x00000019 +#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL1_MSB_MASK 0x0000000fL +#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL1_MSB__SHIFT 0x00000000 +#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL2_MSB_MASK 0x000000f0L +#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL2_MSB__SHIFT 0x00000004 +#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL3_MASK 0x0000ff00L +#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL3__SHIFT 0x00000008 +#define MC_IO_RXCNTL1_DPHY0_D0__VREFPDNB_1_MASK 0x00040000L +#define MC_IO_RXCNTL1_DPHY0_D0__VREFPDNB_1__SHIFT 0x00000012 +#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL2_MASK 0x00010000L +#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL2__SHIFT 0x00000010 +#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL3_MASK 0x00020000L +#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL3__SHIFT 0x00000011 +#define MC_IO_RXCNTL1_DPHY0_D1__DLL_RSV_MASK 0xf0000000L +#define MC_IO_RXCNTL1_DPHY0_D1__DLL_RSV__SHIFT 0x0000001c +#define MC_IO_RXCNTL1_DPHY0_D1__PMD_LOOPBACK_MASK 0x0e000000L +#define MC_IO_RXCNTL1_DPHY0_D1__PMD_LOOPBACK__SHIFT 0x00000019 +#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL1_MSB_MASK 0x0000000fL +#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL1_MSB__SHIFT 0x00000000 +#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL2_MSB_MASK 0x000000f0L +#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL2_MSB__SHIFT 0x00000004 +#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL3_MASK 0x0000ff00L +#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL3__SHIFT 0x00000008 +#define MC_IO_RXCNTL1_DPHY0_D1__VREFPDNB_1_MASK 0x00040000L +#define MC_IO_RXCNTL1_DPHY0_D1__VREFPDNB_1__SHIFT 0x00000012 +#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL2_MASK 0x00010000L +#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL2__SHIFT 0x00000010 +#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL3_MASK 0x00020000L +#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL3__SHIFT 0x00000011 +#define MC_IO_RXCNTL1_DPHY1_D0__DLL_RSV_MASK 0xf0000000L +#define MC_IO_RXCNTL1_DPHY1_D0__DLL_RSV__SHIFT 0x0000001c +#define MC_IO_RXCNTL1_DPHY1_D0__PMD_LOOPBACK_MASK 0x0e000000L +#define MC_IO_RXCNTL1_DPHY1_D0__PMD_LOOPBACK__SHIFT 0x00000019 +#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL1_MSB_MASK 0x0000000fL +#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL1_MSB__SHIFT 0x00000000 +#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL2_MSB_MASK 0x000000f0L +#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL2_MSB__SHIFT 0x00000004 +#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL3_MASK 0x0000ff00L +#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL3__SHIFT 0x00000008 +#define MC_IO_RXCNTL1_DPHY1_D0__VREFPDNB_1_MASK 0x00040000L +#define MC_IO_RXCNTL1_DPHY1_D0__VREFPDNB_1__SHIFT 0x00000012 +#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL2_MASK 0x00010000L +#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL2__SHIFT 0x00000010 +#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL3_MASK 0x00020000L +#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL3__SHIFT 0x00000011 +#define MC_IO_RXCNTL1_DPHY1_D1__DLL_RSV_MASK 0xf0000000L +#define MC_IO_RXCNTL1_DPHY1_D1__DLL_RSV__SHIFT 0x0000001c +#define MC_IO_RXCNTL1_DPHY1_D1__PMD_LOOPBACK_MASK 0x0e000000L +#define MC_IO_RXCNTL1_DPHY1_D1__PMD_LOOPBACK__SHIFT 0x00000019 +#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL1_MSB_MASK 0x0000000fL +#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL1_MSB__SHIFT 0x00000000 +#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL2_MSB_MASK 0x000000f0L +#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL2_MSB__SHIFT 0x00000004 +#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL3_MASK 0x0000ff00L +#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL3__SHIFT 0x00000008 +#define MC_IO_RXCNTL1_DPHY1_D1__VREFPDNB_1_MASK 0x00040000L +#define MC_IO_RXCNTL1_DPHY1_D1__VREFPDNB_1__SHIFT 0x00000012 +#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL2_MASK 0x00010000L +#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL2__SHIFT 0x00000010 +#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL3_MASK 0x00020000L +#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL3__SHIFT 0x00000011 +#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B0_MASK 0x00700000L +#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B0__SHIFT 0x00000014 +#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B1_MASK 0x07000000L +#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B1__SHIFT 0x00000018 +#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_M_MASK 0x10000000L +#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_M__SHIFT 0x0000001c +#define MC_IO_RXCNTL_DPHY0_D0__DLL_BW_CTRL_MASK 0xc0000000L +#define MC_IO_RXCNTL_DPHY0_D0__DLL_BW_CTRL__SHIFT 0x0000001e +#define MC_IO_RXCNTL_DPHY0_D0__RCVSEL_MASK 0x00000004L +#define MC_IO_RXCNTL_DPHY0_D0__RCVSEL__SHIFT 0x00000002 +#define MC_IO_RXCNTL_DPHY0_D0__REFCLK_PWRON_MASK 0x20000000L +#define MC_IO_RXCNTL_DPHY0_D0__REFCLK_PWRON__SHIFT 0x0000001d +#define MC_IO_RXCNTL_DPHY0_D0__RXBIASSEL_MASK 0x00000003L +#define MC_IO_RXCNTL_DPHY0_D0__RXBIASSEL__SHIFT 0x00000000 +#define MC_IO_RXCNTL_DPHY0_D0__RXDPWRON_DLY_MASK 0x00000030L +#define MC_IO_RXCNTL_DPHY0_D0__RXDPWRON_DLY__SHIFT 0x00000004 +#define MC_IO_RXCNTL_DPHY0_D0__RXLP_MASK 0x00000080L +#define MC_IO_RXCNTL_DPHY0_D0__RXLP__SHIFT 0x00000007 +#define MC_IO_RXCNTL_DPHY0_D0__RXPDNB_MASK 0x00000040L +#define MC_IO_RXCNTL_DPHY0_D0__RXPDNB__SHIFT 0x00000006 +#define MC_IO_RXCNTL_DPHY0_D0__RX_PEAKSEL_MASK 0x000c0000L +#define MC_IO_RXCNTL_DPHY0_D0__RX_PEAKSEL__SHIFT 0x00000012 +#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL_MASK 0x00000f00L +#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL__SHIFT 0x00000008 +#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL_STR_MASK 0x0000f000L +#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL_STR__SHIFT 0x0000000c +#define MC_IO_RXCNTL_DPHY0_D0__VREFPDNB_MASK 0x00000008L +#define MC_IO_RXCNTL_DPHY0_D0__VREFPDNB__SHIFT 0x00000003 +#define MC_IO_RXCNTL_DPHY0_D0__VREFSEL_MASK 0x00010000L +#define MC_IO_RXCNTL_DPHY0_D0__VREFSEL__SHIFT 0x00000010 +#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B0_MASK 0x00700000L +#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B0__SHIFT 0x00000014 +#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B1_MASK 0x07000000L +#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B1__SHIFT 0x00000018 +#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_M_MASK 0x10000000L +#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_M__SHIFT 0x0000001c +#define MC_IO_RXCNTL_DPHY0_D1__DLL_BW_CTRL_MASK 0xc0000000L +#define MC_IO_RXCNTL_DPHY0_D1__DLL_BW_CTRL__SHIFT 0x0000001e +#define MC_IO_RXCNTL_DPHY0_D1__RCVSEL_MASK 0x00000004L +#define MC_IO_RXCNTL_DPHY0_D1__RCVSEL__SHIFT 0x00000002 +#define MC_IO_RXCNTL_DPHY0_D1__REFCLK_PWRON_MASK 0x20000000L +#define MC_IO_RXCNTL_DPHY0_D1__REFCLK_PWRON__SHIFT 0x0000001d +#define MC_IO_RXCNTL_DPHY0_D1__RXBIASSEL_MASK 0x00000003L +#define MC_IO_RXCNTL_DPHY0_D1__RXBIASSEL__SHIFT 0x00000000 +#define MC_IO_RXCNTL_DPHY0_D1__RXDPWRON_DLY_MASK 0x00000030L +#define MC_IO_RXCNTL_DPHY0_D1__RXDPWRON_DLY__SHIFT 0x00000004 +#define MC_IO_RXCNTL_DPHY0_D1__RXLP_MASK 0x00000080L +#define MC_IO_RXCNTL_DPHY0_D1__RXLP__SHIFT 0x00000007 +#define MC_IO_RXCNTL_DPHY0_D1__RXPDNB_MASK 0x00000040L +#define MC_IO_RXCNTL_DPHY0_D1__RXPDNB__SHIFT 0x00000006 +#define MC_IO_RXCNTL_DPHY0_D1__RX_PEAKSEL_MASK 0x000c0000L +#define MC_IO_RXCNTL_DPHY0_D1__RX_PEAKSEL__SHIFT 0x00000012 +#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL_MASK 0x00000f00L +#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL__SHIFT 0x00000008 +#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL_STR_MASK 0x0000f000L +#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL_STR__SHIFT 0x0000000c +#define MC_IO_RXCNTL_DPHY0_D1__VREFPDNB_MASK 0x00000008L +#define MC_IO_RXCNTL_DPHY0_D1__VREFPDNB__SHIFT 0x00000003 +#define MC_IO_RXCNTL_DPHY0_D1__VREFSEL_MASK 0x00010000L +#define MC_IO_RXCNTL_DPHY0_D1__VREFSEL__SHIFT 0x00000010 +#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B0_MASK 0x00700000L +#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B0__SHIFT 0x00000014 +#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B1_MASK 0x07000000L +#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B1__SHIFT 0x00000018 +#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_M_MASK 0x10000000L +#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_M__SHIFT 0x0000001c +#define MC_IO_RXCNTL_DPHY1_D0__DLL_BW_CTRL_MASK 0xc0000000L +#define MC_IO_RXCNTL_DPHY1_D0__DLL_BW_CTRL__SHIFT 0x0000001e +#define MC_IO_RXCNTL_DPHY1_D0__RCVSEL_MASK 0x00000004L +#define MC_IO_RXCNTL_DPHY1_D0__RCVSEL__SHIFT 0x00000002 +#define MC_IO_RXCNTL_DPHY1_D0__REFCLK_PWRON_MASK 0x20000000L +#define MC_IO_RXCNTL_DPHY1_D0__REFCLK_PWRON__SHIFT 0x0000001d +#define MC_IO_RXCNTL_DPHY1_D0__RXBIASSEL_MASK 0x00000003L +#define MC_IO_RXCNTL_DPHY1_D0__RXBIASSEL__SHIFT 0x00000000 +#define MC_IO_RXCNTL_DPHY1_D0__RXDPWRON_DLY_MASK 0x00000030L +#define MC_IO_RXCNTL_DPHY1_D0__RXDPWRON_DLY__SHIFT 0x00000004 +#define MC_IO_RXCNTL_DPHY1_D0__RXLP_MASK 0x00000080L +#define MC_IO_RXCNTL_DPHY1_D0__RXLP__SHIFT 0x00000007 +#define MC_IO_RXCNTL_DPHY1_D0__RXPDNB_MASK 0x00000040L +#define MC_IO_RXCNTL_DPHY1_D0__RXPDNB__SHIFT 0x00000006 +#define MC_IO_RXCNTL_DPHY1_D0__RX_PEAKSEL_MASK 0x000c0000L +#define MC_IO_RXCNTL_DPHY1_D0__RX_PEAKSEL__SHIFT 0x00000012 +#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL_MASK 0x00000f00L +#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL__SHIFT 0x00000008 +#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL_STR_MASK 0x0000f000L +#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL_STR__SHIFT 0x0000000c +#define MC_IO_RXCNTL_DPHY1_D0__VREFPDNB_MASK 0x00000008L +#define MC_IO_RXCNTL_DPHY1_D0__VREFPDNB__SHIFT 0x00000003 +#define MC_IO_RXCNTL_DPHY1_D0__VREFSEL_MASK 0x00010000L +#define MC_IO_RXCNTL_DPHY1_D0__VREFSEL__SHIFT 0x00000010 +#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B0_MASK 0x00700000L +#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B0__SHIFT 0x00000014 +#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B1_MASK 0x07000000L +#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B1__SHIFT 0x00000018 +#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_M_MASK 0x10000000L +#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_M__SHIFT 0x0000001c +#define MC_IO_RXCNTL_DPHY1_D1__DLL_BW_CTRL_MASK 0xc0000000L +#define MC_IO_RXCNTL_DPHY1_D1__DLL_BW_CTRL__SHIFT 0x0000001e +#define MC_IO_RXCNTL_DPHY1_D1__RCVSEL_MASK 0x00000004L +#define MC_IO_RXCNTL_DPHY1_D1__RCVSEL__SHIFT 0x00000002 +#define MC_IO_RXCNTL_DPHY1_D1__REFCLK_PWRON_MASK 0x20000000L +#define MC_IO_RXCNTL_DPHY1_D1__REFCLK_PWRON__SHIFT 0x0000001d +#define MC_IO_RXCNTL_DPHY1_D1__RXBIASSEL_MASK 0x00000003L +#define MC_IO_RXCNTL_DPHY1_D1__RXBIASSEL__SHIFT 0x00000000 +#define MC_IO_RXCNTL_DPHY1_D1__RXDPWRON_DLY_MASK 0x00000030L +#define MC_IO_RXCNTL_DPHY1_D1__RXDPWRON_DLY__SHIFT 0x00000004 +#define MC_IO_RXCNTL_DPHY1_D1__RXLP_MASK 0x00000080L +#define MC_IO_RXCNTL_DPHY1_D1__RXLP__SHIFT 0x00000007 +#define MC_IO_RXCNTL_DPHY1_D1__RXPDNB_MASK 0x00000040L +#define MC_IO_RXCNTL_DPHY1_D1__RXPDNB__SHIFT 0x00000006 +#define MC_IO_RXCNTL_DPHY1_D1__RX_PEAKSEL_MASK 0x000c0000L +#define MC_IO_RXCNTL_DPHY1_D1__RX_PEAKSEL__SHIFT 0x00000012 +#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL_MASK 0x00000f00L +#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL__SHIFT 0x00000008 +#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL_STR_MASK 0x0000f000L +#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL_STR__SHIFT 0x0000000c +#define MC_IO_RXCNTL_DPHY1_D1__VREFPDNB_MASK 0x00000008L +#define MC_IO_RXCNTL_DPHY1_D1__VREFPDNB__SHIFT 0x00000003 +#define MC_IO_RXCNTL_DPHY1_D1__VREFSEL_MASK 0x00010000L +#define MC_IO_RXCNTL_DPHY1_D1__VREFSEL__SHIFT 0x00000010 +#define MC_IO_TXCNTL_APHY_D0__BIASSEL_MASK 0x00000003L +#define MC_IO_TXCNTL_APHY_D0__BIASSEL__SHIFT 0x00000000 +#define MC_IO_TXCNTL_APHY_D0__CKE_BIT_MASK 0x40000000L +#define MC_IO_TXCNTL_APHY_D0__CKE_BIT__SHIFT 0x0000001e +#define MC_IO_TXCNTL_APHY_D0__CKE_SEL_MASK 0x80000000L +#define MC_IO_TXCNTL_APHY_D0__CKE_SEL__SHIFT 0x0000001f +#define MC_IO_TXCNTL_APHY_D0__DRVDUTY_MASK 0x0000000cL +#define MC_IO_TXCNTL_APHY_D0__DRVDUTY__SHIFT 0x00000002 +#define MC_IO_TXCNTL_APHY_D0__EMPH_MASK 0x00000040L +#define MC_IO_TXCNTL_APHY_D0__EMPH__SHIFT 0x00000006 +#define MC_IO_TXCNTL_APHY_D0__LOWCMEN_MASK 0x00000010L +#define MC_IO_TXCNTL_APHY_D0__LOWCMEN__SHIFT 0x00000004 +#define MC_IO_TXCNTL_APHY_D0__NDRV_MASK 0x00700000L +#define MC_IO_TXCNTL_APHY_D0__NDRV__SHIFT 0x00000014 +#define MC_IO_TXCNTL_APHY_D0__PDRV_MASK 0x000f0000L +#define MC_IO_TXCNTL_APHY_D0__PDRV__SHIFT 0x00000010 +#define MC_IO_TXCNTL_APHY_D0__PMA_LOOPBACK_MASK 0x0000e000L +#define MC_IO_TXCNTL_APHY_D0__PMA_LOOPBACK__SHIFT 0x0000000d +#define MC_IO_TXCNTL_APHY_D0__PTERM_MASK 0x00000f00L +#define MC_IO_TXCNTL_APHY_D0__PTERM__SHIFT 0x00000008 +#define MC_IO_TXCNTL_APHY_D0__QDR_MASK 0x00000020L +#define MC_IO_TXCNTL_APHY_D0__QDR__SHIFT 0x00000005 +#define MC_IO_TXCNTL_APHY_D0__TSTEN_MASK 0x01000000L +#define MC_IO_TXCNTL_APHY_D0__TSTEN__SHIFT 0x00000018 +#define MC_IO_TXCNTL_APHY_D0__TXBPASS_SEL_MASK 0x00001000L +#define MC_IO_TXCNTL_APHY_D0__TXBPASS_SEL__SHIFT 0x0000000c +#define MC_IO_TXCNTL_APHY_D0__TXBYPASS_DATA_MASK 0x38000000L +#define MC_IO_TXCNTL_APHY_D0__TXBYPASS_DATA__SHIFT 0x0000001b +#define MC_IO_TXCNTL_APHY_D0__TXBYPASS_MASK 0x04000000L +#define MC_IO_TXCNTL_APHY_D0__TXBYPASS__SHIFT 0x0000001a +#define MC_IO_TXCNTL_APHY_D0__TXPD_MASK 0x00000080L +#define MC_IO_TXCNTL_APHY_D0__TXPD__SHIFT 0x00000007 +#define MC_IO_TXCNTL_APHY_D0__TXRESET_MASK 0x02000000L +#define MC_IO_TXCNTL_APHY_D0__TXRESET__SHIFT 0x00000019 +#define MC_IO_TXCNTL_APHY_D0__YCLKON_MASK 0x00800000L +#define MC_IO_TXCNTL_APHY_D0__YCLKON__SHIFT 0x00000017 +#define MC_IO_TXCNTL_APHY_D1__BIASSEL_MASK 0x00000003L +#define MC_IO_TXCNTL_APHY_D1__BIASSEL__SHIFT 0x00000000 +#define MC_IO_TXCNTL_APHY_D1__CKE_BIT_MASK 0x40000000L +#define MC_IO_TXCNTL_APHY_D1__CKE_BIT__SHIFT 0x0000001e +#define MC_IO_TXCNTL_APHY_D1__CKE_SEL_MASK 0x80000000L +#define MC_IO_TXCNTL_APHY_D1__CKE_SEL__SHIFT 0x0000001f +#define MC_IO_TXCNTL_APHY_D1__DRVDUTY_MASK 0x0000000cL +#define MC_IO_TXCNTL_APHY_D1__DRVDUTY__SHIFT 0x00000002 +#define MC_IO_TXCNTL_APHY_D1__EMPH_MASK 0x00000040L +#define MC_IO_TXCNTL_APHY_D1__EMPH__SHIFT 0x00000006 +#define MC_IO_TXCNTL_APHY_D1__LOWCMEN_MASK 0x00000010L +#define MC_IO_TXCNTL_APHY_D1__LOWCMEN__SHIFT 0x00000004 +#define MC_IO_TXCNTL_APHY_D1__NDRV_MASK 0x00700000L +#define MC_IO_TXCNTL_APHY_D1__NDRV__SHIFT 0x00000014 +#define MC_IO_TXCNTL_APHY_D1__PDRV_MASK 0x000f0000L +#define MC_IO_TXCNTL_APHY_D1__PDRV__SHIFT 0x00000010 +#define MC_IO_TXCNTL_APHY_D1__PMA_LOOPBACK_MASK 0x0000e000L +#define MC_IO_TXCNTL_APHY_D1__PMA_LOOPBACK__SHIFT 0x0000000d +#define MC_IO_TXCNTL_APHY_D1__PTERM_MASK 0x00000f00L +#define MC_IO_TXCNTL_APHY_D1__PTERM__SHIFT 0x00000008 +#define MC_IO_TXCNTL_APHY_D1__QDR_MASK 0x00000020L +#define MC_IO_TXCNTL_APHY_D1__QDR__SHIFT 0x00000005 +#define MC_IO_TXCNTL_APHY_D1__TSTEN_MASK 0x01000000L +#define MC_IO_TXCNTL_APHY_D1__TSTEN__SHIFT 0x00000018 +#define MC_IO_TXCNTL_APHY_D1__TXBPASS_SEL_MASK 0x00001000L +#define MC_IO_TXCNTL_APHY_D1__TXBPASS_SEL__SHIFT 0x0000000c +#define MC_IO_TXCNTL_APHY_D1__TXBYPASS_DATA_MASK 0x38000000L +#define MC_IO_TXCNTL_APHY_D1__TXBYPASS_DATA__SHIFT 0x0000001b +#define MC_IO_TXCNTL_APHY_D1__TXBYPASS_MASK 0x04000000L +#define MC_IO_TXCNTL_APHY_D1__TXBYPASS__SHIFT 0x0000001a +#define MC_IO_TXCNTL_APHY_D1__TXPD_MASK 0x00000080L +#define MC_IO_TXCNTL_APHY_D1__TXPD__SHIFT 0x00000007 +#define MC_IO_TXCNTL_APHY_D1__TXRESET_MASK 0x02000000L +#define MC_IO_TXCNTL_APHY_D1__TXRESET__SHIFT 0x00000019 +#define MC_IO_TXCNTL_APHY_D1__YCLKON_MASK 0x00800000L +#define MC_IO_TXCNTL_APHY_D1__YCLKON__SHIFT 0x00000017 +#define MC_IO_TXCNTL_DPHY0_D0__BIASSEL_MASK 0x00000003L +#define MC_IO_TXCNTL_DPHY0_D0__BIASSEL__SHIFT 0x00000000 +#define MC_IO_TXCNTL_DPHY0_D0__DRVDUTY_MASK 0x0000000cL +#define MC_IO_TXCNTL_DPHY0_D0__DRVDUTY__SHIFT 0x00000002 +#define MC_IO_TXCNTL_DPHY0_D0__EDCTX_CLKGATE_EN_MASK 0x02000000L +#define MC_IO_TXCNTL_DPHY0_D0__EDCTX_CLKGATE_EN__SHIFT 0x00000019 +#define MC_IO_TXCNTL_DPHY0_D0__EMPH_MASK 0x00000040L +#define MC_IO_TXCNTL_DPHY0_D0__EMPH__SHIFT 0x00000006 +#define MC_IO_TXCNTL_DPHY0_D0__LOWCMEN_MASK 0x00000010L +#define MC_IO_TXCNTL_DPHY0_D0__LOWCMEN__SHIFT 0x00000004 +#define MC_IO_TXCNTL_DPHY0_D0__NDRV_MASK 0x00f00000L +#define MC_IO_TXCNTL_DPHY0_D0__NDRV__SHIFT 0x00000014 +#define MC_IO_TXCNTL_DPHY0_D0__NTERM_MASK 0x0000f000L +#define MC_IO_TXCNTL_DPHY0_D0__NTERM__SHIFT 0x0000000c +#define MC_IO_TXCNTL_DPHY0_D0__PDRV_MASK 0x000f0000L +#define MC_IO_TXCNTL_DPHY0_D0__PDRV__SHIFT 0x00000010 +#define MC_IO_TXCNTL_DPHY0_D0__PLL_LOOPBCK_MASK 0x08000000L +#define MC_IO_TXCNTL_DPHY0_D0__PLL_LOOPBCK__SHIFT 0x0000001b +#define MC_IO_TXCNTL_DPHY0_D0__PTERM_MASK 0x00000f00L +#define MC_IO_TXCNTL_DPHY0_D0__PTERM__SHIFT 0x00000008 +#define MC_IO_TXCNTL_DPHY0_D0__QDR_MASK 0x00000020L +#define MC_IO_TXCNTL_DPHY0_D0__QDR__SHIFT 0x00000005 +#define MC_IO_TXCNTL_DPHY0_D0__TSTEN_MASK 0x01000000L +#define MC_IO_TXCNTL_DPHY0_D0__TSTEN__SHIFT 0x00000018 +#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS_DATA_MASK 0xf0000000L +#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS_DATA__SHIFT 0x0000001c +#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS_MASK 0x04000000L +#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS__SHIFT 0x0000001a +#define MC_IO_TXCNTL_DPHY0_D0__TXPD_MASK 0x00000080L +#define MC_IO_TXCNTL_DPHY0_D0__TXPD__SHIFT 0x00000007 +#define MC_IO_TXCNTL_DPHY0_D1__BIASSEL_MASK 0x00000003L +#define MC_IO_TXCNTL_DPHY0_D1__BIASSEL__SHIFT 0x00000000 +#define MC_IO_TXCNTL_DPHY0_D1__DRVDUTY_MASK 0x0000000cL +#define MC_IO_TXCNTL_DPHY0_D1__DRVDUTY__SHIFT 0x00000002 +#define MC_IO_TXCNTL_DPHY0_D1__EDCTX_CLKGATE_EN_MASK 0x02000000L +#define MC_IO_TXCNTL_DPHY0_D1__EDCTX_CLKGATE_EN__SHIFT 0x00000019 +#define MC_IO_TXCNTL_DPHY0_D1__EMPH_MASK 0x00000040L +#define MC_IO_TXCNTL_DPHY0_D1__EMPH__SHIFT 0x00000006 +#define MC_IO_TXCNTL_DPHY0_D1__LOWCMEN_MASK 0x00000010L +#define MC_IO_TXCNTL_DPHY0_D1__LOWCMEN__SHIFT 0x00000004 +#define MC_IO_TXCNTL_DPHY0_D1__NDRV_MASK 0x00f00000L +#define MC_IO_TXCNTL_DPHY0_D1__NDRV__SHIFT 0x00000014 +#define MC_IO_TXCNTL_DPHY0_D1__NTERM_MASK 0x0000f000L +#define MC_IO_TXCNTL_DPHY0_D1__NTERM__SHIFT 0x0000000c +#define MC_IO_TXCNTL_DPHY0_D1__PDRV_MASK 0x000f0000L +#define MC_IO_TXCNTL_DPHY0_D1__PDRV__SHIFT 0x00000010 +#define MC_IO_TXCNTL_DPHY0_D1__PLL_LOOPBCK_MASK 0x08000000L +#define MC_IO_TXCNTL_DPHY0_D1__PLL_LOOPBCK__SHIFT 0x0000001b +#define MC_IO_TXCNTL_DPHY0_D1__PTERM_MASK 0x00000f00L +#define MC_IO_TXCNTL_DPHY0_D1__PTERM__SHIFT 0x00000008 +#define MC_IO_TXCNTL_DPHY0_D1__QDR_MASK 0x00000020L +#define MC_IO_TXCNTL_DPHY0_D1__QDR__SHIFT 0x00000005 +#define MC_IO_TXCNTL_DPHY0_D1__TSTEN_MASK 0x01000000L +#define MC_IO_TXCNTL_DPHY0_D1__TSTEN__SHIFT 0x00000018 +#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS_DATA_MASK 0xf0000000L +#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS_DATA__SHIFT 0x0000001c +#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS_MASK 0x04000000L +#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS__SHIFT 0x0000001a +#define MC_IO_TXCNTL_DPHY0_D1__TXPD_MASK 0x00000080L +#define MC_IO_TXCNTL_DPHY0_D1__TXPD__SHIFT 0x00000007 +#define MC_IO_TXCNTL_DPHY1_D0__BIASSEL_MASK 0x00000003L +#define MC_IO_TXCNTL_DPHY1_D0__BIASSEL__SHIFT 0x00000000 +#define MC_IO_TXCNTL_DPHY1_D0__DRVDUTY_MASK 0x0000000cL +#define MC_IO_TXCNTL_DPHY1_D0__DRVDUTY__SHIFT 0x00000002 +#define MC_IO_TXCNTL_DPHY1_D0__EDCTX_CLKGATE_EN_MASK 0x02000000L +#define MC_IO_TXCNTL_DPHY1_D0__EDCTX_CLKGATE_EN__SHIFT 0x00000019 +#define MC_IO_TXCNTL_DPHY1_D0__EMPH_MASK 0x00000040L +#define MC_IO_TXCNTL_DPHY1_D0__EMPH__SHIFT 0x00000006 +#define MC_IO_TXCNTL_DPHY1_D0__LOWCMEN_MASK 0x00000010L +#define MC_IO_TXCNTL_DPHY1_D0__LOWCMEN__SHIFT 0x00000004 +#define MC_IO_TXCNTL_DPHY1_D0__NDRV_MASK 0x00f00000L +#define MC_IO_TXCNTL_DPHY1_D0__NDRV__SHIFT 0x00000014 +#define MC_IO_TXCNTL_DPHY1_D0__NTERM_MASK 0x0000f000L +#define MC_IO_TXCNTL_DPHY1_D0__NTERM__SHIFT 0x0000000c +#define MC_IO_TXCNTL_DPHY1_D0__PDRV_MASK 0x000f0000L +#define MC_IO_TXCNTL_DPHY1_D0__PDRV__SHIFT 0x00000010 +#define MC_IO_TXCNTL_DPHY1_D0__PLL_LOOPBCK_MASK 0x08000000L +#define MC_IO_TXCNTL_DPHY1_D0__PLL_LOOPBCK__SHIFT 0x0000001b +#define MC_IO_TXCNTL_DPHY1_D0__PTERM_MASK 0x00000f00L +#define MC_IO_TXCNTL_DPHY1_D0__PTERM__SHIFT 0x00000008 +#define MC_IO_TXCNTL_DPHY1_D0__QDR_MASK 0x00000020L +#define MC_IO_TXCNTL_DPHY1_D0__QDR__SHIFT 0x00000005 +#define MC_IO_TXCNTL_DPHY1_D0__TSTEN_MASK 0x01000000L +#define MC_IO_TXCNTL_DPHY1_D0__TSTEN__SHIFT 0x00000018 +#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS_DATA_MASK 0xf0000000L +#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS_DATA__SHIFT 0x0000001c +#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS_MASK 0x04000000L +#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS__SHIFT 0x0000001a +#define MC_IO_TXCNTL_DPHY1_D0__TXPD_MASK 0x00000080L +#define MC_IO_TXCNTL_DPHY1_D0__TXPD__SHIFT 0x00000007 +#define MC_IO_TXCNTL_DPHY1_D1__BIASSEL_MASK 0x00000003L +#define MC_IO_TXCNTL_DPHY1_D1__BIASSEL__SHIFT 0x00000000 +#define MC_IO_TXCNTL_DPHY1_D1__DRVDUTY_MASK 0x0000000cL +#define MC_IO_TXCNTL_DPHY1_D1__DRVDUTY__SHIFT 0x00000002 +#define MC_IO_TXCNTL_DPHY1_D1__EDCTX_CLKGATE_EN_MASK 0x02000000L +#define MC_IO_TXCNTL_DPHY1_D1__EDCTX_CLKGATE_EN__SHIFT 0x00000019 +#define MC_IO_TXCNTL_DPHY1_D1__EMPH_MASK 0x00000040L +#define MC_IO_TXCNTL_DPHY1_D1__EMPH__SHIFT 0x00000006 +#define MC_IO_TXCNTL_DPHY1_D1__LOWCMEN_MASK 0x00000010L +#define MC_IO_TXCNTL_DPHY1_D1__LOWCMEN__SHIFT 0x00000004 +#define MC_IO_TXCNTL_DPHY1_D1__NDRV_MASK 0x00f00000L +#define MC_IO_TXCNTL_DPHY1_D1__NDRV__SHIFT 0x00000014 +#define MC_IO_TXCNTL_DPHY1_D1__NTERM_MASK 0x0000f000L +#define MC_IO_TXCNTL_DPHY1_D1__NTERM__SHIFT 0x0000000c +#define MC_IO_TXCNTL_DPHY1_D1__PDRV_MASK 0x000f0000L +#define MC_IO_TXCNTL_DPHY1_D1__PDRV__SHIFT 0x00000010 +#define MC_IO_TXCNTL_DPHY1_D1__PLL_LOOPBCK_MASK 0x08000000L +#define MC_IO_TXCNTL_DPHY1_D1__PLL_LOOPBCK__SHIFT 0x0000001b +#define MC_IO_TXCNTL_DPHY1_D1__PTERM_MASK 0x00000f00L +#define MC_IO_TXCNTL_DPHY1_D1__PTERM__SHIFT 0x00000008 +#define MC_IO_TXCNTL_DPHY1_D1__QDR_MASK 0x00000020L +#define MC_IO_TXCNTL_DPHY1_D1__QDR__SHIFT 0x00000005 +#define MC_IO_TXCNTL_DPHY1_D1__TSTEN_MASK 0x01000000L +#define MC_IO_TXCNTL_DPHY1_D1__TSTEN__SHIFT 0x00000018 +#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS_DATA_MASK 0xf0000000L +#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS_DATA__SHIFT 0x0000001c +#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS_MASK 0x04000000L +#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS__SHIFT 0x0000001a +#define MC_IO_TXCNTL_DPHY1_D1__TXPD_MASK 0x00000080L +#define MC_IO_TXCNTL_DPHY1_D1__TXPD__SHIFT 0x00000007 +#define MCLK_PWRMGT_CNTL__DLL_READY_MASK 0x00000040L +#define MCLK_PWRMGT_CNTL__DLL_READY_READ_MASK 0x01000000L +#define MCLK_PWRMGT_CNTL__DLL_READY_READ__SHIFT 0x00000018 +#define MCLK_PWRMGT_CNTL__DLL_READY__SHIFT 0x00000006 +#define MCLK_PWRMGT_CNTL__DLL_SPEED_MASK 0x0000001fL +#define MCLK_PWRMGT_CNTL__DLL_SPEED__SHIFT 0x00000000 +#define MCLK_PWRMGT_CNTL__MC_INT_CNTL_MASK 0x00000080L +#define MCLK_PWRMGT_CNTL__MC_INT_CNTL__SHIFT 0x00000007 +#define MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK 0x00000100L +#define MCLK_PWRMGT_CNTL__MRDCK0_PDNB__SHIFT 0x00000008 +#define MCLK_PWRMGT_CNTL__MRDCK0_RESET_MASK 0x00010000L +#define MCLK_PWRMGT_CNTL__MRDCK0_RESET__SHIFT 0x00000010 +#define MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK 0x00000200L +#define MCLK_PWRMGT_CNTL__MRDCK1_PDNB__SHIFT 0x00000009 +#define MCLK_PWRMGT_CNTL__MRDCK1_RESET_MASK 0x00020000L +#define MCLK_PWRMGT_CNTL__MRDCK1_RESET__SHIFT 0x00000011 +#define MC_MEM_POWER_LS__LS_HOLD_MASK 0x00000fc0L +#define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x00000006 +#define MC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003fL +#define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x00000000 +#define MC_NPL_STATUS__D0_NDELAY_MASK 0x0000000cL +#define MC_NPL_STATUS__D0_NDELAY__SHIFT 0x00000002 +#define MC_NPL_STATUS__D0_NEARLY_MASK 0x00000020L +#define MC_NPL_STATUS__D0_NEARLY__SHIFT 0x00000005 +#define MC_NPL_STATUS__D0_PDELAY_MASK 0x00000003L +#define MC_NPL_STATUS__D0_PDELAY__SHIFT 0x00000000 +#define MC_NPL_STATUS__D0_PEARLY_MASK 0x00000010L +#define MC_NPL_STATUS__D0_PEARLY__SHIFT 0x00000004 +#define MC_NPL_STATUS__D1_NDELAY_MASK 0x00000300L +#define MC_NPL_STATUS__D1_NDELAY__SHIFT 0x00000008 +#define MC_NPL_STATUS__D1_NEARLY_MASK 0x00000800L +#define MC_NPL_STATUS__D1_NEARLY__SHIFT 0x0000000b +#define MC_NPL_STATUS__D1_PDELAY_MASK 0x000000c0L +#define MC_NPL_STATUS__D1_PDELAY__SHIFT 0x00000006 +#define MC_NPL_STATUS__D1_PEARLY_MASK 0x00000400L +#define MC_NPL_STATUS__D1_PEARLY__SHIFT 0x0000000a +#define MC_PHY_TIMING_2__ADR_CLKEN_D0_MASK 0x00040000L +#define MC_PHY_TIMING_2__ADR_CLKEN_D0__SHIFT 0x00000012 +#define MC_PHY_TIMING_2__ADR_CLKEN_D1_MASK 0x00080000L +#define MC_PHY_TIMING_2__ADR_CLKEN_D1__SHIFT 0x00000013 +#define MC_PHY_TIMING_2__IND_LD_CNT_MASK 0x0000007fL +#define MC_PHY_TIMING_2__IND_LD_CNT__SHIFT 0x00000000 +#define MC_PHY_TIMING_2__RXC0_FRC_MASK 0x00001000L +#define MC_PHY_TIMING_2__RXC0_FRC__SHIFT 0x0000000c +#define MC_PHY_TIMING_2__RXC0_INV_MASK 0x00000100L +#define MC_PHY_TIMING_2__RXC0_INV__SHIFT 0x00000008 +#define MC_PHY_TIMING_2__RXC1_FRC_MASK 0x00002000L +#define MC_PHY_TIMING_2__RXC1_FRC__SHIFT 0x0000000d +#define MC_PHY_TIMING_2__RXC1_INV_MASK 0x00000200L +#define MC_PHY_TIMING_2__RXC1_INV__SHIFT 0x00000009 +#define MC_PHY_TIMING_2__TXC0_FRC_MASK 0x00004000L +#define MC_PHY_TIMING_2__TXC0_FRC__SHIFT 0x0000000e +#define MC_PHY_TIMING_2__TXC0_INV_MASK 0x00000400L +#define MC_PHY_TIMING_2__TXC0_INV__SHIFT 0x0000000a +#define MC_PHY_TIMING_2__TXC1_FRC_MASK 0x00008000L +#define MC_PHY_TIMING_2__TXC1_FRC__SHIFT 0x0000000f +#define MC_PHY_TIMING_2__TXC1_INV_MASK 0x00000800L +#define MC_PHY_TIMING_2__TXC1_INV__SHIFT 0x0000000b +#define MC_PHY_TIMING_2__TX_CDREN_D0_MASK 0x00010000L +#define MC_PHY_TIMING_2__TX_CDREN_D0__SHIFT 0x00000010 +#define MC_PHY_TIMING_2__TX_CDREN_D1_MASK 0x00020000L +#define MC_PHY_TIMING_2__TX_CDREN_D1__SHIFT 0x00000011 +#define MC_PHY_TIMING_2__WR_DLY_MASK 0x00f00000L +#define MC_PHY_TIMING_2__WR_DLY__SHIFT 0x00000014 +#define MC_PHY_TIMING_D0__RXC0_DLY_MASK 0x0000000fL +#define MC_PHY_TIMING_D0__RXC0_DLY__SHIFT 0x00000000 +#define MC_PHY_TIMING_D0__RXC0_EXT_MASK 0x000000f0L +#define MC_PHY_TIMING_D0__RXC0_EXT__SHIFT 0x00000004 +#define MC_PHY_TIMING_D0__RXC1_DLY_MASK 0x00000f00L +#define MC_PHY_TIMING_D0__RXC1_DLY__SHIFT 0x00000008 +#define MC_PHY_TIMING_D0__RXC1_EXT_MASK 0x0000f000L +#define MC_PHY_TIMING_D0__RXC1_EXT__SHIFT 0x0000000c +#define MC_PHY_TIMING_D0__TXC0_DLY_MASK 0x00070000L +#define MC_PHY_TIMING_D0__TXC0_DLY__SHIFT 0x00000010 +#define MC_PHY_TIMING_D0__TXC0_EXT_MASK 0x00f00000L +#define MC_PHY_TIMING_D0__TXC0_EXT__SHIFT 0x00000014 +#define MC_PHY_TIMING_D0__TXC1_DLY_MASK 0x07000000L +#define MC_PHY_TIMING_D0__TXC1_DLY__SHIFT 0x00000018 +#define MC_PHY_TIMING_D0__TXC1_EXT_MASK 0xf0000000L +#define MC_PHY_TIMING_D0__TXC1_EXT__SHIFT 0x0000001c +#define MC_PHY_TIMING_D1__RXC0_DLY_MASK 0x0000000fL +#define MC_PHY_TIMING_D1__RXC0_DLY__SHIFT 0x00000000 +#define MC_PHY_TIMING_D1__RXC0_EXT_MASK 0x000000f0L +#define MC_PHY_TIMING_D1__RXC0_EXT__SHIFT 0x00000004 +#define MC_PHY_TIMING_D1__RXC1_DLY_MASK 0x00000f00L +#define MC_PHY_TIMING_D1__RXC1_DLY__SHIFT 0x00000008 +#define MC_PHY_TIMING_D1__RXC1_EXT_MASK 0x0000f000L +#define MC_PHY_TIMING_D1__RXC1_EXT__SHIFT 0x0000000c +#define MC_PHY_TIMING_D1__TXC0_DLY_MASK 0x00070000L +#define MC_PHY_TIMING_D1__TXC0_DLY__SHIFT 0x00000010 +#define MC_PHY_TIMING_D1__TXC0_EXT_MASK 0x00f00000L +#define MC_PHY_TIMING_D1__TXC0_EXT__SHIFT 0x00000014 +#define MC_PHY_TIMING_D1__TXC1_DLY_MASK 0x07000000L +#define MC_PHY_TIMING_D1__TXC1_DLY__SHIFT 0x00000018 +#define MC_PHY_TIMING_D1__TXC1_EXT_MASK 0xf0000000L +#define MC_PHY_TIMING_D1__TXC1_EXT__SHIFT 0x0000001c +#define MC_PMG_AUTO_CFG__DLL_CNT_MASK 0xff000000L +#define MC_PMG_AUTO_CFG__DLL_CNT__SHIFT 0x00000018 +#define MC_PMG_AUTO_CFG__EXIT_ALLOW_STOP_MASK 0x00000800L +#define MC_PMG_AUTO_CFG__EXIT_ALLOW_STOP__SHIFT 0x0000000b +#define MC_PMG_AUTO_CFG__MRS_WAIT_CNT_MASK 0x000f0000L +#define MC_PMG_AUTO_CFG__MRS_WAIT_CNT__SHIFT 0x00000010 +#define MC_PMG_AUTO_CFG__PREA_SRX_MASK 0x00002000L +#define MC_PMG_AUTO_CFG__PREA_SRX__SHIFT 0x0000000d +#define MC_PMG_AUTO_CFG__RFS_SRX_MASK 0x00001000L +#define MC_PMG_AUTO_CFG__RFS_SRX__SHIFT 0x0000000c +#define MC_PMG_AUTO_CFG__RST_MRS_MASK 0x00000002L +#define MC_PMG_AUTO_CFG__RST_MRS__SHIFT 0x00000001 +#define MC_PMG_AUTO_CFG__RXPDNB_MASK 0x00400000L +#define MC_PMG_AUTO_CFG__RXPDNB__SHIFT 0x00000016 +#define MC_PMG_AUTO_CFG__SCDS_MODE_MASK 0x00000400L +#define MC_PMG_AUTO_CFG__SCDS_MODE__SHIFT 0x0000000a +#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_0_MASK 0x00008000L +#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_0__SHIFT 0x0000000f +#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_1_MASK 0x00800000L +#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_1__SHIFT 0x00000017 +#define MC_PMG_AUTO_CFG__SS_ALWAYS_SLF_MASK 0x00000100L +#define MC_PMG_AUTO_CFG__SS_ALWAYS_SLF__SHIFT 0x00000008 +#define MC_PMG_AUTO_CFG__SS_S_SLF_MASK 0x00000200L +#define MC_PMG_AUTO_CFG__SS_S_SLF__SHIFT 0x00000009 +#define MC_PMG_AUTO_CFG__STUTTER_EN_MASK 0x00004000L +#define MC_PMG_AUTO_CFG__STUTTER_EN__SHIFT 0x0000000e +#define MC_PMG_AUTO_CFG__SYC_CLK_MASK 0x00000001L +#define MC_PMG_AUTO_CFG__SYC_CLK__SHIFT 0x00000000 +#define MC_PMG_AUTO_CFG__TRI_MIO_MASK 0x00000004L +#define MC_PMG_AUTO_CFG__TRI_MIO__SHIFT 0x00000002 +#define MC_PMG_AUTO_CFG__WRITE_DURING_DLOCK_MASK 0x00100000L +#define MC_PMG_AUTO_CFG__WRITE_DURING_DLOCK__SHIFT 0x00000014 +#define MC_PMG_AUTO_CFG__XSR_TMR_MASK 0x000000f0L +#define MC_PMG_AUTO_CFG__XSR_TMR__SHIFT 0x00000004 +#define MC_PMG_AUTO_CFG__YCLK_ON_MASK 0x00200000L +#define MC_PMG_AUTO_CFG__YCLK_ON__SHIFT 0x00000015 +#define MC_PMG_AUTO_CMD__ADR_MASK 0x0001ffffL +#define MC_PMG_AUTO_CMD__ADR_MSB0_MASK 0x20000000L +#define MC_PMG_AUTO_CMD__ADR_MSB0__SHIFT 0x0000001d +#define MC_PMG_AUTO_CMD__ADR_MSB1_MASK 0x10000000L +#define MC_PMG_AUTO_CMD__ADR_MSB1__SHIFT 0x0000001c +#define MC_PMG_AUTO_CMD__ADR__SHIFT 0x00000000 +#define MC_PMG_CFG__DPM_WAKE_MASK 0x00000400L +#define MC_PMG_CFG__DPM_WAKE__SHIFT 0x0000000a +#define MC_PMG_CFG__EARLY_ACK_ACPI_MASK 0x00400000L +#define MC_PMG_CFG__EARLY_ACK_ACPI__SHIFT 0x00000016 +#define MC_PMG_CFG__MRS_WAIT_CNT_MASK 0x000f0000L +#define MC_PMG_CFG__MRS_WAIT_CNT__SHIFT 0x00000010 +#define MC_PMG_CFG__PREA_SRX_MASK 0x00002000L +#define MC_PMG_CFG__PREA_SRX__SHIFT 0x0000000d +#define MC_PMG_CFG__RFS_SRX_MASK 0x00001000L +#define MC_PMG_CFG__RFS_SRX__SHIFT 0x0000000c +#define MC_PMG_CFG__RST_EMRS_MASK 0x00000004L +#define MC_PMG_CFG__RST_EMRS__SHIFT 0x00000002 +#define MC_PMG_CFG__RST_MRS1_MASK 0x00000100L +#define MC_PMG_CFG__RST_MRS1__SHIFT 0x00000008 +#define MC_PMG_CFG__RST_MRS2_MASK 0x00000200L +#define MC_PMG_CFG__RST_MRS2__SHIFT 0x00000009 +#define MC_PMG_CFG__RST_MRS_MASK 0x00000002L +#define MC_PMG_CFG__RST_MRS__SHIFT 0x00000001 +#define MC_PMG_CFG__RXPDNB_MASK 0x02000000L +#define MC_PMG_CFG__RXPDNB__SHIFT 0x00000019 +#define MC_PMG_CFG__SYC_CLK_MASK 0x00000001L +#define MC_PMG_CFG__SYC_CLK__SHIFT 0x00000000 +#define MC_PMG_CFG__TRI_MIO_MASK 0x00000008L +#define MC_PMG_CFG__TRI_MIO__SHIFT 0x00000003 +#define MC_PMG_CFG__WRITE_DURING_DLOCK_MASK 0x00100000L +#define MC_PMG_CFG__WRITE_DURING_DLOCK__SHIFT 0x00000014 +#define MC_PMG_CFG__XSR_TMR_MASK 0x000000f0L +#define MC_PMG_CFG__XSR_TMR__SHIFT 0x00000004 +#define MC_PMG_CFG__YCLK_ON_MASK 0x00200000L +#define MC_PMG_CFG__YCLK_ON__SHIFT 0x00000015 +#define MC_PMG_CFG__ZQCL_SEND_MASK 0x0c000000L +#define MC_PMG_CFG__ZQCL_SEND__SHIFT 0x0000001a +#define MC_PMG_CMD_EMRS__ADR_MASK 0x0000ffffL +#define MC_PMG_CMD_EMRS__ADR_MSB0_MASK 0x20000000L +#define MC_PMG_CMD_EMRS__ADR_MSB0__SHIFT 0x0000001d +#define MC_PMG_CMD_EMRS__ADR_MSB1_MASK 0x10000000L +#define MC_PMG_CMD_EMRS__ADR_MSB1__SHIFT 0x0000001c +#define MC_PMG_CMD_EMRS__ADR__SHIFT 0x00000000 +#define MC_PMG_CMD_EMRS__BNK_MSB_MASK 0x00080000L +#define MC_PMG_CMD_EMRS__BNK_MSB__SHIFT 0x00000013 +#define MC_PMG_CMD_EMRS__CSB_MASK 0x00600000L +#define MC_PMG_CMD_EMRS__CSB__SHIFT 0x00000015 +#define MC_PMG_CMD_EMRS__END_MASK 0x00100000L +#define MC_PMG_CMD_EMRS__END__SHIFT 0x00000014 +#define MC_PMG_CMD_EMRS__MOP_MASK 0x00070000L +#define MC_PMG_CMD_EMRS__MOP__SHIFT 0x00000010 +#define MC_PMG_CMD_MRS1__ADR_MASK 0x0000ffffL +#define MC_PMG_CMD_MRS1__ADR_MSB0_MASK 0x20000000L +#define MC_PMG_CMD_MRS1__ADR_MSB0__SHIFT 0x0000001d +#define MC_PMG_CMD_MRS1__ADR_MSB1_MASK 0x10000000L +#define MC_PMG_CMD_MRS1__ADR_MSB1__SHIFT 0x0000001c +#define MC_PMG_CMD_MRS1__ADR__SHIFT 0x00000000 +#define MC_PMG_CMD_MRS1__BNK_MSB_MASK 0x00080000L +#define MC_PMG_CMD_MRS1__BNK_MSB__SHIFT 0x00000013 +#define MC_PMG_CMD_MRS1__CSB_MASK 0x00600000L +#define MC_PMG_CMD_MRS1__CSB__SHIFT 0x00000015 +#define MC_PMG_CMD_MRS1__END_MASK 0x00100000L +#define MC_PMG_CMD_MRS1__END__SHIFT 0x00000014 +#define MC_PMG_CMD_MRS1__MOP_MASK 0x00070000L +#define MC_PMG_CMD_MRS1__MOP__SHIFT 0x00000010 +#define MC_PMG_CMD_MRS2__ADR_MASK 0x0000ffffL +#define MC_PMG_CMD_MRS2__ADR_MSB0_MASK 0x20000000L +#define MC_PMG_CMD_MRS2__ADR_MSB0__SHIFT 0x0000001d +#define MC_PMG_CMD_MRS2__ADR_MSB1_MASK 0x10000000L +#define MC_PMG_CMD_MRS2__ADR_MSB1__SHIFT 0x0000001c +#define MC_PMG_CMD_MRS2__ADR__SHIFT 0x00000000 +#define MC_PMG_CMD_MRS2__BNK_MSB_MASK 0x00080000L +#define MC_PMG_CMD_MRS2__BNK_MSB__SHIFT 0x00000013 +#define MC_PMG_CMD_MRS2__CSB_MASK 0x00600000L +#define MC_PMG_CMD_MRS2__CSB__SHIFT 0x00000015 +#define MC_PMG_CMD_MRS2__END_MASK 0x00100000L +#define MC_PMG_CMD_MRS2__END__SHIFT 0x00000014 +#define MC_PMG_CMD_MRS2__MOP_MASK 0x00070000L +#define MC_PMG_CMD_MRS2__MOP__SHIFT 0x00000010 +#define MC_PMG_CMD_MRS__ADR_MASK 0x0000ffffL +#define MC_PMG_CMD_MRS__ADR_MSB0_MASK 0x20000000L +#define MC_PMG_CMD_MRS__ADR_MSB0__SHIFT 0x0000001d +#define MC_PMG_CMD_MRS__ADR_MSB1_MASK 0x10000000L +#define MC_PMG_CMD_MRS__ADR_MSB1__SHIFT 0x0000001c +#define MC_PMG_CMD_MRS__ADR__SHIFT 0x00000000 +#define MC_PMG_CMD_MRS__BNK_MSB_MASK 0x00080000L +#define MC_PMG_CMD_MRS__BNK_MSB__SHIFT 0x00000013 +#define MC_PMG_CMD_MRS__CSB_MASK 0x00600000L +#define MC_PMG_CMD_MRS__CSB__SHIFT 0x00000015 +#define MC_PMG_CMD_MRS__END_MASK 0x00100000L +#define MC_PMG_CMD_MRS__END__SHIFT 0x00000014 +#define MC_PMG_CMD_MRS__MOP_MASK 0x00070000L +#define MC_PMG_CMD_MRS__MOP__SHIFT 0x00000010 +#define MC_RD_CB__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_RD_CB__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_RD_CB__ENABLE_MASK 0x00000001L +#define MC_RD_CB__ENABLE__SHIFT 0x00000000 +#define MC_RD_CB__LAZY_TIMER_MASK 0x00007800L +#define MC_RD_CB__LAZY_TIMER__SHIFT 0x0000000b +#define MC_RD_CB__MAX_BURST_MASK 0x00000780L +#define MC_RD_CB__MAX_BURST__SHIFT 0x00000007 +#define MC_RD_CB__PRESCALE_MASK 0x00000006L +#define MC_RD_CB__PRESCALE__SHIFT 0x00000001 +#define MC_RD_CB__STALL_MODE_MASK 0x00000030L +#define MC_RD_CB__STALL_MODE__SHIFT 0x00000004 +#define MC_RD_CB__STALL_OVERRIDE_MASK 0x00000040L +#define MC_RD_CB__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_RD_CB__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_RD_CB__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_RD_DB__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_RD_DB__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_RD_DB__ENABLE_MASK 0x00000001L +#define MC_RD_DB__ENABLE__SHIFT 0x00000000 +#define MC_RD_DB__LAZY_TIMER_MASK 0x00007800L +#define MC_RD_DB__LAZY_TIMER__SHIFT 0x0000000b +#define MC_RD_DB__MAX_BURST_MASK 0x00000780L +#define MC_RD_DB__MAX_BURST__SHIFT 0x00000007 +#define MC_RD_DB__PRESCALE_MASK 0x00000006L +#define MC_RD_DB__PRESCALE__SHIFT 0x00000001 +#define MC_RD_DB__STALL_MODE_MASK 0x00000030L +#define MC_RD_DB__STALL_MODE__SHIFT 0x00000004 +#define MC_RD_DB__STALL_OVERRIDE_MASK 0x00000040L +#define MC_RD_DB__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_RD_DB__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_RD_DB__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_RD_GRP_EXT__DBSTEN0_MASK 0x0000000fL +#define MC_RD_GRP_EXT__DBSTEN0__SHIFT 0x00000000 +#define MC_RD_GRP_EXT__TC0_MASK 0x000000f0L +#define MC_RD_GRP_EXT__TC0__SHIFT 0x00000004 +#define MC_RD_GRP_GFX__CP_MASK 0x0000000fL +#define MC_RD_GRP_GFX__CP__SHIFT 0x00000000 +#define MC_RD_GRP_GFX__XDMAM_MASK 0x000f0000L +#define MC_RD_GRP_GFX__XDMAM__SHIFT 0x00000010 +#define MC_RD_GRP_LCL__CB0_MASK 0x0000f000L +#define MC_RD_GRP_LCL__CB0__SHIFT 0x0000000c +#define MC_RD_GRP_LCL__CBCMASK0_MASK 0x000f0000L +#define MC_RD_GRP_LCL__CBCMASK0__SHIFT 0x00000010 +#define MC_RD_GRP_LCL__CBFMASK0_MASK 0x00f00000L +#define MC_RD_GRP_LCL__CBFMASK0__SHIFT 0x00000014 +#define MC_RD_GRP_LCL__DB0_MASK 0x0f000000L +#define MC_RD_GRP_LCL__DB0__SHIFT 0x00000018 +#define MC_RD_GRP_LCL__DBHTILE0_MASK 0xf0000000L +#define MC_RD_GRP_LCL__DBHTILE0__SHIFT 0x0000001c +#define MC_RD_GRP_OTH__HDP_MASK 0x00000f00L +#define MC_RD_GRP_OTH__HDP__SHIFT 0x00000008 +#define MC_RD_GRP_OTH__SEM_MASK 0x0000f000L +#define MC_RD_GRP_OTH__SEM__SHIFT 0x0000000c +#define MC_RD_GRP_OTH__UMC_MASK 0x000f0000L +#define MC_RD_GRP_OTH__UMC__SHIFT 0x00000010 +#define MC_RD_GRP_OTH__UVD_EXT0_MASK 0x0000000fL +#define MC_RD_GRP_OTH__UVD_EXT0__SHIFT 0x00000000 +#define MC_RD_GRP_OTH__UVD_EXT1_MASK 0x0f000000L +#define MC_RD_GRP_OTH__UVD_EXT1__SHIFT 0x00000018 +#define MC_RD_GRP_OTH__UVD_MASK 0x00f00000L +#define MC_RD_GRP_OTH__UVD__SHIFT 0x00000014 +#define MC_RD_GRP_SYS__DMIF_MASK 0x0000f000L +#define MC_RD_GRP_SYS__DMIF__SHIFT 0x0000000c +#define MC_RD_GRP_SYS__MCIF_MASK 0x000f0000L +#define MC_RD_GRP_SYS__MCIF__SHIFT 0x00000010 +#define MC_RD_GRP_SYS__RLC_MASK 0x0000000fL +#define MC_RD_GRP_SYS__RLC__SHIFT 0x00000000 +#define MC_RD_GRP_SYS__SMU_MASK 0x00f00000L +#define MC_RD_GRP_SYS__SMU__SHIFT 0x00000014 +#define MC_RD_GRP_SYS__VCE_MASK 0x0f000000L +#define MC_RD_GRP_SYS__VCE__SHIFT 0x00000018 +#define MC_RD_GRP_SYS__VCEU_MASK 0xf0000000L +#define MC_RD_GRP_SYS__VCEU__SHIFT 0x0000001c +#define MC_RD_GRP_SYS__VMC_MASK 0x000000f0L +#define MC_RD_GRP_SYS__VMC__SHIFT 0x00000004 +#define MC_RD_HUB__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_RD_HUB__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_RD_HUB__ENABLE_MASK 0x00000001L +#define MC_RD_HUB__ENABLE__SHIFT 0x00000000 +#define MC_RD_HUB__LAZY_TIMER_MASK 0x00007800L +#define MC_RD_HUB__LAZY_TIMER__SHIFT 0x0000000b +#define MC_RD_HUB__MAX_BURST_MASK 0x00000780L +#define MC_RD_HUB__MAX_BURST__SHIFT 0x00000007 +#define MC_RD_HUB__PRESCALE_MASK 0x00000006L +#define MC_RD_HUB__PRESCALE__SHIFT 0x00000001 +#define MC_RD_HUB__STALL_MODE_MASK 0x00000030L +#define MC_RD_HUB__STALL_MODE__SHIFT 0x00000004 +#define MC_RD_HUB__STALL_OVERRIDE_MASK 0x00000040L +#define MC_RD_HUB__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_RD_HUB__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_RD_HUB__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_RD_TC0__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_RD_TC0__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_RD_TC0__ENABLE_MASK 0x00000001L +#define MC_RD_TC0__ENABLE__SHIFT 0x00000000 +#define MC_RD_TC0__LAZY_TIMER_MASK 0x00007800L +#define MC_RD_TC0__LAZY_TIMER__SHIFT 0x0000000b +#define MC_RD_TC0__MAX_BURST_MASK 0x00000780L +#define MC_RD_TC0__MAX_BURST__SHIFT 0x00000007 +#define MC_RD_TC0__PRESCALE_MASK 0x00000006L +#define MC_RD_TC0__PRESCALE__SHIFT 0x00000001 +#define MC_RD_TC0__STALL_MODE_MASK 0x00000030L +#define MC_RD_TC0__STALL_MODE__SHIFT 0x00000004 +#define MC_RD_TC0__STALL_OVERRIDE_MASK 0x00000040L +#define MC_RD_TC0__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_RD_TC0__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_RD_TC0__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_RD_TC1__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_RD_TC1__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_RD_TC1__ENABLE_MASK 0x00000001L +#define MC_RD_TC1__ENABLE__SHIFT 0x00000000 +#define MC_RD_TC1__LAZY_TIMER_MASK 0x00007800L +#define MC_RD_TC1__LAZY_TIMER__SHIFT 0x0000000b +#define MC_RD_TC1__MAX_BURST_MASK 0x00000780L +#define MC_RD_TC1__MAX_BURST__SHIFT 0x00000007 +#define MC_RD_TC1__PRESCALE_MASK 0x00000006L +#define MC_RD_TC1__PRESCALE__SHIFT 0x00000001 +#define MC_RD_TC1__STALL_MODE_MASK 0x00000030L +#define MC_RD_TC1__STALL_MODE__SHIFT 0x00000004 +#define MC_RD_TC1__STALL_OVERRIDE_MASK 0x00000040L +#define MC_RD_TC1__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_RD_TC1__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_RD_TC1__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM_MASK 0x00ff0000L +#define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM__SHIFT 0x00000010 +#define MC_RPB_ARB_CNTL__RD_SWITCH_NUM_MASK 0x0000ff00L +#define MC_RPB_ARB_CNTL__RD_SWITCH_NUM__SHIFT 0x00000008 +#define MC_RPB_ARB_CNTL__WR_SWITCH_NUM_MASK 0x000000ffL +#define MC_RPB_ARB_CNTL__WR_SWITCH_NUM__SHIFT 0x00000000 +#define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM_MASK 0x000000ffL +#define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM__SHIFT 0x00000000 +#define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM_MASK 0x0000ff00L +#define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM__SHIFT 0x00000008 +#define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES_MASK 0xffff0000L +#define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES__SHIFT 0x00000010 +#define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES_MASK 0x0000ffffL +#define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES__SHIFT 0x00000000 +#define MC_RPB_CID_QUEUE_EX__OFFSET_MASK 0x0000003eL +#define MC_RPB_CID_QUEUE_EX__OFFSET__SHIFT 0x00000001 +#define MC_RPB_CID_QUEUE_EX__START_MASK 0x00000001L +#define MC_RPB_CID_QUEUE_EX__START__SHIFT 0x00000000 +#define MC_RPB_CID_QUEUE_RD__CLIENT_ID_MASK 0x000000ffL +#define MC_RPB_CID_QUEUE_RD__CLIENT_ID__SHIFT 0x00000000 +#define MC_RPB_CID_QUEUE_RD__READ_QUEUE_MASK 0x00000c00L +#define MC_RPB_CID_QUEUE_RD__READ_QUEUE__SHIFT 0x0000000a +#define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE_MASK 0x00000300L +#define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE__SHIFT 0x00000008 +#define MC_RPB_CID_QUEUE_WR__CLIENT_ID_MASK 0x000000ffL +#define MC_RPB_CID_QUEUE_WR__CLIENT_ID__SHIFT 0x00000000 +#define MC_RPB_CID_QUEUE_WR__READ_QUEUE_MASK 0x00001800L +#define MC_RPB_CID_QUEUE_WR__READ_QUEUE__SHIFT 0x0000000b +#define MC_RPB_CID_QUEUE_WR__UPDATE_MASK 0x00002000L +#define MC_RPB_CID_QUEUE_WR__UPDATE_MODE_MASK 0x00000100L +#define MC_RPB_CID_QUEUE_WR__UPDATE_MODE__SHIFT 0x00000008 +#define MC_RPB_CID_QUEUE_WR__UPDATE__SHIFT 0x0000000d +#define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE_MASK 0x00000600L +#define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE__SHIFT 0x00000009 +#define MC_RPB_CONF__RPB_RD_PCIE_ORDER_MASK 0x00010000L +#define MC_RPB_CONF__RPB_RD_PCIE_ORDER__SHIFT 0x00000010 +#define MC_RPB_CONF__RPB_WR_PCIE_ORDER_MASK 0x00020000L +#define MC_RPB_CONF__RPB_WR_PCIE_ORDER__SHIFT 0x00000011 +#define MC_RPB_CONF__XPB_PCIE_ORDER_MASK 0x00008000L +#define MC_RPB_CONF__XPB_PCIE_ORDER__SHIFT 0x0000000f +#define MC_RPB_DBG1__DEBUG_BITS_MASK 0xfff00000L +#define MC_RPB_DBG1__DEBUG_BITS__SHIFT 0x00000014 +#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B_MASK 0x000fff00L +#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B__SHIFT 0x00000008 +#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_MASK 0x000000ffL +#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD__SHIFT 0x00000000 +#define MC_RPB_EFF_CNTL__RD_LAZY_TIMER_MASK 0x0000ff00L +#define MC_RPB_EFF_CNTL__RD_LAZY_TIMER__SHIFT 0x00000008 +#define MC_RPB_EFF_CNTL__WR_LAZY_TIMER_MASK 0x000000ffL +#define MC_RPB_EFF_CNTL__WR_LAZY_TIMER__SHIFT 0x00000000 +#define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK_MASK 0x0000ff00L +#define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK__SHIFT 0x00000008 +#define MC_RPB_IF_CONF__RPB_BIF_CREDITS_MASK 0x000000ffL +#define MC_RPB_IF_CONF__RPB_BIF_CREDITS__SHIFT 0x00000000 +#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS_MASK 0x00000008L +#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS__SHIFT 0x00000003 +#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER_MASK 0x00000004L +#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER__SHIFT 0x00000002 +#define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS_MASK 0x000001e0L +#define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS__SHIFT 0x00000005 +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0_MASK 0x00003e00L +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0__SHIFT 0x00000009 +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1_MASK 0x0007c000L +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1__SHIFT 0x0000000e +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2_MASK 0x00f80000L +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2__SHIFT 0x00000013 +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3_MASK 0x1f000000L +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3__SHIFT 0x00000018 +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT_MASK 0x00000003L +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT__SHIFT 0x00000000 +#define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION_MASK 0x00000010L +#define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION__SHIFT 0x00000004 +#define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE_MASK 0xffffffffL +#define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE__SHIFT 0x00000000 +#define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0x000000ffL +#define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x00000000 +#define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0x0000ff00L +#define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x00000008 +#define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0x00ff0000L +#define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x00000010 +#define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000L +#define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x00000018 +#define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN_MASK 0x00000080L +#define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN__SHIFT 0x00000007 +#define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE_MASK 0x00000001L +#define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE__SHIFT 0x00000000 +#define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER_MASK 0x00000078L +#define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER__SHIFT 0x00000003 +#define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE_MASK 0x00000006L +#define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE__SHIFT 0x00000001 +#define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0x000000ffL +#define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x00000000 +#define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0x0000ff00L +#define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x00000008 +#define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0x00ff0000L +#define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x00000010 +#define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000L +#define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x00000018 +#define MC_SEQ_BIT_REMAP_B0_D0__BIT0_MASK 0x00000007L +#define MC_SEQ_BIT_REMAP_B0_D0__BIT0__SHIFT 0x00000000 +#define MC_SEQ_BIT_REMAP_B0_D0__BIT1_MASK 0x00000038L +#define MC_SEQ_BIT_REMAP_B0_D0__BIT1__SHIFT 0x00000003 +#define MC_SEQ_BIT_REMAP_B0_D0__BIT2_MASK 0x000001c0L +#define MC_SEQ_BIT_REMAP_B0_D0__BIT2__SHIFT 0x00000006 +#define MC_SEQ_BIT_REMAP_B0_D0__BIT3_MASK 0x00000e00L +#define MC_SEQ_BIT_REMAP_B0_D0__BIT3__SHIFT 0x00000009 +#define MC_SEQ_BIT_REMAP_B0_D0__BIT4_MASK 0x00007000L +#define MC_SEQ_BIT_REMAP_B0_D0__BIT4__SHIFT 0x0000000c +#define MC_SEQ_BIT_REMAP_B0_D0__BIT5_MASK 0x00038000L +#define MC_SEQ_BIT_REMAP_B0_D0__BIT5__SHIFT 0x0000000f +#define MC_SEQ_BIT_REMAP_B0_D0__BIT6_MASK 0x001c0000L +#define MC_SEQ_BIT_REMAP_B0_D0__BIT6__SHIFT 0x00000012 +#define MC_SEQ_BIT_REMAP_B0_D0__BIT7_MASK 0x00e00000L +#define MC_SEQ_BIT_REMAP_B0_D0__BIT7__SHIFT 0x00000015 +#define MC_SEQ_BIT_REMAP_B0_D1__BIT0_MASK 0x00000007L +#define MC_SEQ_BIT_REMAP_B0_D1__BIT0__SHIFT 0x00000000 +#define MC_SEQ_BIT_REMAP_B0_D1__BIT1_MASK 0x00000038L +#define MC_SEQ_BIT_REMAP_B0_D1__BIT1__SHIFT 0x00000003 +#define MC_SEQ_BIT_REMAP_B0_D1__BIT2_MASK 0x000001c0L +#define MC_SEQ_BIT_REMAP_B0_D1__BIT2__SHIFT 0x00000006 +#define MC_SEQ_BIT_REMAP_B0_D1__BIT3_MASK 0x00000e00L +#define MC_SEQ_BIT_REMAP_B0_D1__BIT3__SHIFT 0x00000009 +#define MC_SEQ_BIT_REMAP_B0_D1__BIT4_MASK 0x00007000L +#define MC_SEQ_BIT_REMAP_B0_D1__BIT4__SHIFT 0x0000000c +#define MC_SEQ_BIT_REMAP_B0_D1__BIT5_MASK 0x00038000L +#define MC_SEQ_BIT_REMAP_B0_D1__BIT5__SHIFT 0x0000000f +#define MC_SEQ_BIT_REMAP_B0_D1__BIT6_MASK 0x001c0000L +#define MC_SEQ_BIT_REMAP_B0_D1__BIT6__SHIFT 0x00000012 +#define MC_SEQ_BIT_REMAP_B0_D1__BIT7_MASK 0x00e00000L +#define MC_SEQ_BIT_REMAP_B0_D1__BIT7__SHIFT 0x00000015 +#define MC_SEQ_BIT_REMAP_B1_D0__BIT0_MASK 0x00000007L +#define MC_SEQ_BIT_REMAP_B1_D0__BIT0__SHIFT 0x00000000 +#define MC_SEQ_BIT_REMAP_B1_D0__BIT1_MASK 0x00000038L +#define MC_SEQ_BIT_REMAP_B1_D0__BIT1__SHIFT 0x00000003 +#define MC_SEQ_BIT_REMAP_B1_D0__BIT2_MASK 0x000001c0L +#define MC_SEQ_BIT_REMAP_B1_D0__BIT2__SHIFT 0x00000006 +#define MC_SEQ_BIT_REMAP_B1_D0__BIT3_MASK 0x00000e00L +#define MC_SEQ_BIT_REMAP_B1_D0__BIT3__SHIFT 0x00000009 +#define MC_SEQ_BIT_REMAP_B1_D0__BIT4_MASK 0x00007000L +#define MC_SEQ_BIT_REMAP_B1_D0__BIT4__SHIFT 0x0000000c +#define MC_SEQ_BIT_REMAP_B1_D0__BIT5_MASK 0x00038000L +#define MC_SEQ_BIT_REMAP_B1_D0__BIT5__SHIFT 0x0000000f +#define MC_SEQ_BIT_REMAP_B1_D0__BIT6_MASK 0x001c0000L +#define MC_SEQ_BIT_REMAP_B1_D0__BIT6__SHIFT 0x00000012 +#define MC_SEQ_BIT_REMAP_B1_D0__BIT7_MASK 0x00e00000L +#define MC_SEQ_BIT_REMAP_B1_D0__BIT7__SHIFT 0x00000015 +#define MC_SEQ_BIT_REMAP_B1_D1__BIT0_MASK 0x00000007L +#define MC_SEQ_BIT_REMAP_B1_D1__BIT0__SHIFT 0x00000000 +#define MC_SEQ_BIT_REMAP_B1_D1__BIT1_MASK 0x00000038L +#define MC_SEQ_BIT_REMAP_B1_D1__BIT1__SHIFT 0x00000003 +#define MC_SEQ_BIT_REMAP_B1_D1__BIT2_MASK 0x000001c0L +#define MC_SEQ_BIT_REMAP_B1_D1__BIT2__SHIFT 0x00000006 +#define MC_SEQ_BIT_REMAP_B1_D1__BIT3_MASK 0x00000e00L +#define MC_SEQ_BIT_REMAP_B1_D1__BIT3__SHIFT 0x00000009 +#define MC_SEQ_BIT_REMAP_B1_D1__BIT4_MASK 0x00007000L +#define MC_SEQ_BIT_REMAP_B1_D1__BIT4__SHIFT 0x0000000c +#define MC_SEQ_BIT_REMAP_B1_D1__BIT5_MASK 0x00038000L +#define MC_SEQ_BIT_REMAP_B1_D1__BIT5__SHIFT 0x0000000f +#define MC_SEQ_BIT_REMAP_B1_D1__BIT6_MASK 0x001c0000L +#define MC_SEQ_BIT_REMAP_B1_D1__BIT6__SHIFT 0x00000012 +#define MC_SEQ_BIT_REMAP_B1_D1__BIT7_MASK 0x00e00000L +#define MC_SEQ_BIT_REMAP_B1_D1__BIT7__SHIFT 0x00000015 +#define MC_SEQ_BIT_REMAP_B2_D0__BIT0_MASK 0x00000007L +#define MC_SEQ_BIT_REMAP_B2_D0__BIT0__SHIFT 0x00000000 +#define MC_SEQ_BIT_REMAP_B2_D0__BIT1_MASK 0x00000038L +#define MC_SEQ_BIT_REMAP_B2_D0__BIT1__SHIFT 0x00000003 +#define MC_SEQ_BIT_REMAP_B2_D0__BIT2_MASK 0x000001c0L +#define MC_SEQ_BIT_REMAP_B2_D0__BIT2__SHIFT 0x00000006 +#define MC_SEQ_BIT_REMAP_B2_D0__BIT3_MASK 0x00000e00L +#define MC_SEQ_BIT_REMAP_B2_D0__BIT3__SHIFT 0x00000009 +#define MC_SEQ_BIT_REMAP_B2_D0__BIT4_MASK 0x00007000L +#define MC_SEQ_BIT_REMAP_B2_D0__BIT4__SHIFT 0x0000000c +#define MC_SEQ_BIT_REMAP_B2_D0__BIT5_MASK 0x00038000L +#define MC_SEQ_BIT_REMAP_B2_D0__BIT5__SHIFT 0x0000000f +#define MC_SEQ_BIT_REMAP_B2_D0__BIT6_MASK 0x001c0000L +#define MC_SEQ_BIT_REMAP_B2_D0__BIT6__SHIFT 0x00000012 +#define MC_SEQ_BIT_REMAP_B2_D0__BIT7_MASK 0x00e00000L +#define MC_SEQ_BIT_REMAP_B2_D0__BIT7__SHIFT 0x00000015 +#define MC_SEQ_BIT_REMAP_B2_D1__BIT0_MASK 0x00000007L +#define MC_SEQ_BIT_REMAP_B2_D1__BIT0__SHIFT 0x00000000 +#define MC_SEQ_BIT_REMAP_B2_D1__BIT1_MASK 0x00000038L +#define MC_SEQ_BIT_REMAP_B2_D1__BIT1__SHIFT 0x00000003 +#define MC_SEQ_BIT_REMAP_B2_D1__BIT2_MASK 0x000001c0L +#define MC_SEQ_BIT_REMAP_B2_D1__BIT2__SHIFT 0x00000006 +#define MC_SEQ_BIT_REMAP_B2_D1__BIT3_MASK 0x00000e00L +#define MC_SEQ_BIT_REMAP_B2_D1__BIT3__SHIFT 0x00000009 +#define MC_SEQ_BIT_REMAP_B2_D1__BIT4_MASK 0x00007000L +#define MC_SEQ_BIT_REMAP_B2_D1__BIT4__SHIFT 0x0000000c +#define MC_SEQ_BIT_REMAP_B2_D1__BIT5_MASK 0x00038000L +#define MC_SEQ_BIT_REMAP_B2_D1__BIT5__SHIFT 0x0000000f +#define MC_SEQ_BIT_REMAP_B2_D1__BIT6_MASK 0x001c0000L +#define MC_SEQ_BIT_REMAP_B2_D1__BIT6__SHIFT 0x00000012 +#define MC_SEQ_BIT_REMAP_B2_D1__BIT7_MASK 0x00e00000L +#define MC_SEQ_BIT_REMAP_B2_D1__BIT7__SHIFT 0x00000015 +#define MC_SEQ_BIT_REMAP_B3_D0__BIT0_MASK 0x00000007L +#define MC_SEQ_BIT_REMAP_B3_D0__BIT0__SHIFT 0x00000000 +#define MC_SEQ_BIT_REMAP_B3_D0__BIT1_MASK 0x00000038L +#define MC_SEQ_BIT_REMAP_B3_D0__BIT1__SHIFT 0x00000003 +#define MC_SEQ_BIT_REMAP_B3_D0__BIT2_MASK 0x000001c0L +#define MC_SEQ_BIT_REMAP_B3_D0__BIT2__SHIFT 0x00000006 +#define MC_SEQ_BIT_REMAP_B3_D0__BIT3_MASK 0x00000e00L +#define MC_SEQ_BIT_REMAP_B3_D0__BIT3__SHIFT 0x00000009 +#define MC_SEQ_BIT_REMAP_B3_D0__BIT4_MASK 0x00007000L +#define MC_SEQ_BIT_REMAP_B3_D0__BIT4__SHIFT 0x0000000c +#define MC_SEQ_BIT_REMAP_B3_D0__BIT5_MASK 0x00038000L +#define MC_SEQ_BIT_REMAP_B3_D0__BIT5__SHIFT 0x0000000f +#define MC_SEQ_BIT_REMAP_B3_D0__BIT6_MASK 0x001c0000L +#define MC_SEQ_BIT_REMAP_B3_D0__BIT6__SHIFT 0x00000012 +#define MC_SEQ_BIT_REMAP_B3_D0__BIT7_MASK 0x00e00000L +#define MC_SEQ_BIT_REMAP_B3_D0__BIT7__SHIFT 0x00000015 +#define MC_SEQ_BIT_REMAP_B3_D1__BIT0_MASK 0x00000007L +#define MC_SEQ_BIT_REMAP_B3_D1__BIT0__SHIFT 0x00000000 +#define MC_SEQ_BIT_REMAP_B3_D1__BIT1_MASK 0x00000038L +#define MC_SEQ_BIT_REMAP_B3_D1__BIT1__SHIFT 0x00000003 +#define MC_SEQ_BIT_REMAP_B3_D1__BIT2_MASK 0x000001c0L +#define MC_SEQ_BIT_REMAP_B3_D1__BIT2__SHIFT 0x00000006 +#define MC_SEQ_BIT_REMAP_B3_D1__BIT3_MASK 0x00000e00L +#define MC_SEQ_BIT_REMAP_B3_D1__BIT3__SHIFT 0x00000009 +#define MC_SEQ_BIT_REMAP_B3_D1__BIT4_MASK 0x00007000L +#define MC_SEQ_BIT_REMAP_B3_D1__BIT4__SHIFT 0x0000000c +#define MC_SEQ_BIT_REMAP_B3_D1__BIT5_MASK 0x00038000L +#define MC_SEQ_BIT_REMAP_B3_D1__BIT5__SHIFT 0x0000000f +#define MC_SEQ_BIT_REMAP_B3_D1__BIT6_MASK 0x001c0000L +#define MC_SEQ_BIT_REMAP_B3_D1__BIT6__SHIFT 0x00000012 +#define MC_SEQ_BIT_REMAP_B3_D1__BIT7_MASK 0x00e00000L +#define MC_SEQ_BIT_REMAP_B3_D1__BIT7__SHIFT 0x00000015 +#define MC_SEQ_BYTE_REMAP_D0__BYTE0_MASK 0x00000003L +#define MC_SEQ_BYTE_REMAP_D0__BYTE0__SHIFT 0x00000000 +#define MC_SEQ_BYTE_REMAP_D0__BYTE1_MASK 0x0000000cL +#define MC_SEQ_BYTE_REMAP_D0__BYTE1__SHIFT 0x00000002 +#define MC_SEQ_BYTE_REMAP_D0__BYTE2_MASK 0x00000030L +#define MC_SEQ_BYTE_REMAP_D0__BYTE2__SHIFT 0x00000004 +#define MC_SEQ_BYTE_REMAP_D0__BYTE3_MASK 0x000000c0L +#define MC_SEQ_BYTE_REMAP_D0__BYTE3__SHIFT 0x00000006 +#define MC_SEQ_BYTE_REMAP_D1__BYTE0_MASK 0x00000003L +#define MC_SEQ_BYTE_REMAP_D1__BYTE0__SHIFT 0x00000000 +#define MC_SEQ_BYTE_REMAP_D1__BYTE1_MASK 0x0000000cL +#define MC_SEQ_BYTE_REMAP_D1__BYTE1__SHIFT 0x00000002 +#define MC_SEQ_BYTE_REMAP_D1__BYTE2_MASK 0x00000030L +#define MC_SEQ_BYTE_REMAP_D1__BYTE2__SHIFT 0x00000004 +#define MC_SEQ_BYTE_REMAP_D1__BYTE3_MASK 0x000000c0L +#define MC_SEQ_BYTE_REMAP_D1__BYTE3__SHIFT 0x00000006 +#define MC_SEQ_CAS_TIMING_LP__TCCDL_MASK 0x00000e00L +#define MC_SEQ_CAS_TIMING_LP__TCCDL__SHIFT 0x00000009 +#define MC_SEQ_CAS_TIMING_LP__TCL_MASK 0x1f000000L +#define MC_SEQ_CAS_TIMING_LP__TCL__SHIFT 0x00000018 +#define MC_SEQ_CAS_TIMING_LP__TNOPR_MASK 0x0000000cL +#define MC_SEQ_CAS_TIMING_LP__TNOPR__SHIFT 0x00000002 +#define MC_SEQ_CAS_TIMING_LP__TNOPW_MASK 0x00000003L +#define MC_SEQ_CAS_TIMING_LP__TNOPW__SHIFT 0x00000000 +#define MC_SEQ_CAS_TIMING_LP__TR2R_MASK 0x0000f000L +#define MC_SEQ_CAS_TIMING_LP__TR2R__SHIFT 0x0000000c +#define MC_SEQ_CAS_TIMING_LP__TR2W_MASK 0x000001f0L +#define MC_SEQ_CAS_TIMING_LP__TR2W__SHIFT 0x00000004 +#define MC_SEQ_CAS_TIMING_LP__TW2R_MASK 0x001f0000L +#define MC_SEQ_CAS_TIMING_LP__TW2R__SHIFT 0x00000010 +#define MC_SEQ_CAS_TIMING__TCCDL_MASK 0x00000e00L +#define MC_SEQ_CAS_TIMING__TCCDL__SHIFT 0x00000009 +#define MC_SEQ_CAS_TIMING__TCL_MASK 0x1f000000L +#define MC_SEQ_CAS_TIMING__TCL__SHIFT 0x00000018 +#define MC_SEQ_CAS_TIMING__TNOPR_MASK 0x0000000cL +#define MC_SEQ_CAS_TIMING__TNOPR__SHIFT 0x00000002 +#define MC_SEQ_CAS_TIMING__TNOPW_MASK 0x00000003L +#define MC_SEQ_CAS_TIMING__TNOPW__SHIFT 0x00000000 +#define MC_SEQ_CAS_TIMING__TR2R_MASK 0x0000f000L +#define MC_SEQ_CAS_TIMING__TR2R__SHIFT 0x0000000c +#define MC_SEQ_CAS_TIMING__TR2W_MASK 0x000001f0L +#define MC_SEQ_CAS_TIMING__TR2W__SHIFT 0x00000004 +#define MC_SEQ_CAS_TIMING__TW2R_MASK 0x001f0000L +#define MC_SEQ_CAS_TIMING__TW2R__SHIFT 0x00000010 +#define MC_SEQ_CG__CG_SEQ_REQ_MASK 0x000000ffL +#define MC_SEQ_CG__CG_SEQ_REQ__SHIFT 0x00000000 +#define MC_SEQ_CG__CG_SEQ_RESP_MASK 0x0000ff00L +#define MC_SEQ_CG__CG_SEQ_RESP__SHIFT 0x00000008 +#define MC_SEQ_CG__SEQ_CG_REQ_MASK 0x00ff0000L +#define MC_SEQ_CG__SEQ_CG_REQ__SHIFT 0x00000010 +#define MC_SEQ_CG__SEQ_CG_RESP_MASK 0xff000000L +#define MC_SEQ_CG__SEQ_CG_RESP__SHIFT 0x00000018 +#define MC_SEQ_CMD__ADR_MASK 0x0000ffffL +#define MC_SEQ_CMD__ADR_MSB0_MASK 0x20000000L +#define MC_SEQ_CMD__ADR_MSB0__SHIFT 0x0000001d +#define MC_SEQ_CMD__ADR_MSB1_MASK 0x10000000L +#define MC_SEQ_CMD__ADR_MSB1__SHIFT 0x0000001c +#define MC_SEQ_CMD__ADR__SHIFT 0x00000000 +#define MC_SEQ_CMD__CHAN0_MASK 0x01000000L +#define MC_SEQ_CMD__CHAN0__SHIFT 0x00000018 +#define MC_SEQ_CMD__CHAN1_MASK 0x02000000L +#define MC_SEQ_CMD__CHAN1__SHIFT 0x00000019 +#define MC_SEQ_CMD__CSB_MASK 0x00600000L +#define MC_SEQ_CMD__CSB__SHIFT 0x00000015 +#define MC_SEQ_CMD__END_MASK 0x00100000L +#define MC_SEQ_CMD__END__SHIFT 0x00000014 +#define MC_SEQ_CMD__MOP_MASK 0x000f0000L +#define MC_SEQ_CMD__MOP__SHIFT 0x00000010 +#define MC_SEQ_CNTL_2__ARB_RTDAT_WMK_MSB_MASK 0x00000300L +#define MC_SEQ_CNTL_2__ARB_RTDAT_WMK_MSB__SHIFT 0x00000008 +#define MC_SEQ_CNTL_2__DRST_NSTR_MASK 0x0000fc00L +#define MC_SEQ_CNTL_2__DRST_NSTR__SHIFT 0x0000000a +#define MC_SEQ_CNTL_2__DRST_PSTR_MASK 0x003f0000L +#define MC_SEQ_CNTL_2__DRST_PSTR__SHIFT 0x00000010 +#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D0_MASK 0x0f000000L +#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D0__SHIFT 0x00000018 +#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D1_MASK 0xf0000000L +#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D1__SHIFT 0x0000001c +#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D0_MASK 0x00400000L +#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D0__SHIFT 0x00000016 +#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D1_MASK 0x00800000L +#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D1__SHIFT 0x00000017 +#define MC_SEQ_CNTL__ARB_REQCMD_WMK_MASK 0x00f00000L +#define MC_SEQ_CNTL__ARB_REQCMD_WMK__SHIFT 0x00000014 +#define MC_SEQ_CNTL__ARB_REQDAT_WMK_MASK 0x0f000000L +#define MC_SEQ_CNTL__ARB_REQDAT_WMK__SHIFT 0x00000018 +#define MC_SEQ_CNTL__ARB_RTDAT_WMK_MASK 0xf0000000L +#define MC_SEQ_CNTL__ARB_RTDAT_WMK__SHIFT 0x0000001c +#define MC_SEQ_CNTL__BANKGROUP_ENB_MASK 0x00040000L +#define MC_SEQ_CNTL__BANKGROUP_ENB__SHIFT 0x00000012 +#define MC_SEQ_CNTL__BANKGROUP_SIZE_MASK 0x00020000L +#define MC_SEQ_CNTL__BANKGROUP_SIZE__SHIFT 0x00000011 +#define MC_SEQ_CNTL__CHANNEL_DISABLE_MASK 0x00000300L +#define MC_SEQ_CNTL__CHANNEL_DISABLE__SHIFT 0x00000008 +#define MC_SEQ_CNTL__DAT_INV_MASK 0x00000040L +#define MC_SEQ_CNTL__DAT_INV__SHIFT 0x00000006 +#define MC_SEQ_CNTL__MEM_ADDR_MAP_BANK_MASK 0x0000000cL +#define MC_SEQ_CNTL__MEM_ADDR_MAP_BANK__SHIFT 0x00000002 +#define MC_SEQ_CNTL__MEM_ADDR_MAP_COLS_MASK 0x00000003L +#define MC_SEQ_CNTL__MEM_ADDR_MAP_COLS__SHIFT 0x00000000 +#define MC_SEQ_CNTL__MSK_DF1_MASK 0x00000080L +#define MC_SEQ_CNTL__MSK_DF1__SHIFT 0x00000007 +#define MC_SEQ_CNTL__MSKOFF_DAT_TH_MASK 0x00008000L +#define MC_SEQ_CNTL__MSKOFF_DAT_TH__SHIFT 0x0000000f +#define MC_SEQ_CNTL__MSKOFF_DAT_TL_MASK 0x00004000L +#define MC_SEQ_CNTL__MSKOFF_DAT_TL__SHIFT 0x0000000e +#define MC_SEQ_CNTL__RET_HOLD_EOP_MASK 0x00010000L +#define MC_SEQ_CNTL__RET_HOLD_EOP__SHIFT 0x00000010 +#define MC_SEQ_CNTL__RTR_OVERRIDE_MASK 0x00080000L +#define MC_SEQ_CNTL__RTR_OVERRIDE__SHIFT 0x00000013 +#define MC_SEQ_CNTL__SAFE_MODE_MASK 0x00000030L +#define MC_SEQ_CNTL__SAFE_MODE__SHIFT 0x00000004 +#define MC_SEQ_DRAM_2__ADBI_ACT_MASK 0x04000000L +#define MC_SEQ_DRAM_2__ADBI_ACT__SHIFT 0x0000001a +#define MC_SEQ_DRAM_2__ADBI_DF1_MASK 0x02000000L +#define MC_SEQ_DRAM_2__ADBI_DF1__SHIFT 0x00000019 +#define MC_SEQ_DRAM_2__ADR_DBI_ACM_MASK 0x00000004L +#define MC_SEQ_DRAM_2__ADR_DBI_ACM__SHIFT 0x00000002 +#define MC_SEQ_DRAM_2__ADR_DBI_MASK 0x00000002L +#define MC_SEQ_DRAM_2__ADR_DBI__SHIFT 0x00000001 +#define MC_SEQ_DRAM_2__ADR_DDR_MASK 0x00000001L +#define MC_SEQ_DRAM_2__ADR_DDR__SHIFT 0x00000000 +#define MC_SEQ_DRAM_2__BNK_MRS_MASK 0x00002000L +#define MC_SEQ_DRAM_2__BNK_MRS__SHIFT 0x0000000d +#define MC_SEQ_DRAM_2__CMD_QDR_MASK 0x00000008L +#define MC_SEQ_DRAM_2__CMD_QDR__SHIFT 0x00000003 +#define MC_SEQ_DRAM_2__CS_BY16_MASK 0x80000000L +#define MC_SEQ_DRAM_2__CS_BY16__SHIFT 0x0000001f +#define MC_SEQ_DRAM_2__DAT_QDR_MASK 0x00000010L +#define MC_SEQ_DRAM_2__DAT_QDR__SHIFT 0x00000004 +#define MC_SEQ_DRAM_2__DBI_ACT_MASK 0x10000000L +#define MC_SEQ_DRAM_2__DBI_ACT__SHIFT 0x0000001c +#define MC_SEQ_DRAM_2__DBI_DF1_MASK 0x08000000L +#define MC_SEQ_DRAM_2__DBI_DF1__SHIFT 0x0000001b +#define MC_SEQ_DRAM_2__DBI_EDC_DF1_MASK 0x20000000L +#define MC_SEQ_DRAM_2__DBI_EDC_DF1__SHIFT 0x0000001d +#define MC_SEQ_DRAM_2__DBI_OVR_MASK 0x00004000L +#define MC_SEQ_DRAM_2__DBI_OVR__SHIFT 0x0000000e +#define MC_SEQ_DRAM_2__DLL_EST_MASK 0x00001000L +#define MC_SEQ_DRAM_2__DLL_EST__SHIFT 0x0000000c +#define MC_SEQ_DRAM_2__DQM_EST_MASK 0x00000080L +#define MC_SEQ_DRAM_2__DQM_EST__SHIFT 0x00000007 +#define MC_SEQ_DRAM_2__PCH_BNK_MASK 0x01000000L +#define MC_SEQ_DRAM_2__PCH_BNK__SHIFT 0x00000018 +#define MC_SEQ_DRAM_2__PLL_CLR_MASK 0x00000800L +#define MC_SEQ_DRAM_2__PLL_CLR__SHIFT 0x0000000b +#define MC_SEQ_DRAM_2__PLL_CNT_MASK 0x00ff0000L +#define MC_SEQ_DRAM_2__PLL_CNT__SHIFT 0x00000010 +#define MC_SEQ_DRAM_2__PLL_EST_MASK 0x00000400L +#define MC_SEQ_DRAM_2__PLL_EST__SHIFT 0x0000000a +#define MC_SEQ_DRAM_2__RDAT_EDC_MASK 0x00000040L +#define MC_SEQ_DRAM_2__RDAT_EDC__SHIFT 0x00000006 +#define MC_SEQ_DRAM_2__RD_DQS_MASK 0x00000100L +#define MC_SEQ_DRAM_2__RD_DQS__SHIFT 0x00000008 +#define MC_SEQ_DRAM_2__TESTCHIP_EN_MASK 0x40000000L +#define MC_SEQ_DRAM_2__TESTCHIP_EN__SHIFT 0x0000001e +#define MC_SEQ_DRAM_2__TRI_CLK_MASK 0x00008000L +#define MC_SEQ_DRAM_2__TRI_CLK__SHIFT 0x0000000f +#define MC_SEQ_DRAM_2__WDAT_EDC_MASK 0x00000020L +#define MC_SEQ_DRAM_2__WDAT_EDC__SHIFT 0x00000005 +#define MC_SEQ_DRAM_2__WR_DQS_MASK 0x00000200L +#define MC_SEQ_DRAM_2__WR_DQS__SHIFT 0x00000009 +#define MC_SEQ_DRAM__ADR_2CK_MASK 0x00000001L +#define MC_SEQ_DRAM__ADR_2CK__SHIFT 0x00000000 +#define MC_SEQ_DRAM__ADR_DF1_MASK 0x00000004L +#define MC_SEQ_DRAM__ADR_DF1__SHIFT 0x00000002 +#define MC_SEQ_DRAM__ADR_MUX_MASK 0x00000002L +#define MC_SEQ_DRAM__ADR_MUX__SHIFT 0x00000001 +#define MC_SEQ_DRAM__AP8_MASK 0x00000008L +#define MC_SEQ_DRAM__AP8__SHIFT 0x00000003 +#define MC_SEQ_DRAM__BO4_MASK 0x00004000L +#define MC_SEQ_DRAM__BO4__SHIFT 0x0000000e +#define MC_SEQ_DRAM__CKE_ACT_MASK 0x00002000L +#define MC_SEQ_DRAM__CKE_ACT__SHIFT 0x0000000d +#define MC_SEQ_DRAM__CKE_DYN_MASK 0x00001000L +#define MC_SEQ_DRAM__CKE_DYN__SHIFT 0x0000000c +#define MC_SEQ_DRAM__DAT_DF1_MASK 0x00000010L +#define MC_SEQ_DRAM__DAT_DF1__SHIFT 0x00000004 +#define MC_SEQ_DRAM__DAT_INV_MASK 0x01000000L +#define MC_SEQ_DRAM__DAT_INV__SHIFT 0x00000018 +#define MC_SEQ_DRAM__DLL_CLR_MASK 0x00008000L +#define MC_SEQ_DRAM__DLL_CLR__SHIFT 0x0000000f +#define MC_SEQ_DRAM__DLL_CNT_MASK 0x00ff0000L +#define MC_SEQ_DRAM__DLL_CNT__SHIFT 0x00000010 +#define MC_SEQ_DRAM__DQM_ACT_MASK 0x00000080L +#define MC_SEQ_DRAM__DQM_ACT__SHIFT 0x00000007 +#define MC_SEQ_DRAM__DQM_DF1_MASK 0x00000040L +#define MC_SEQ_DRAM__DQM_DF1__SHIFT 0x00000006 +#define MC_SEQ_DRAM__DQS_DF1_MASK 0x00000020L +#define MC_SEQ_DRAM__DQS_DF1__SHIFT 0x00000005 +#define MC_SEQ_DRAM_ERROR_INSERTION__RX_MASK 0xffff0000L +#define MC_SEQ_DRAM_ERROR_INSERTION__RX__SHIFT 0x00000010 +#define MC_SEQ_DRAM_ERROR_INSERTION__TX_MASK 0x0000ffffL +#define MC_SEQ_DRAM_ERROR_INSERTION__TX__SHIFT 0x00000000 +#define MC_SEQ_DRAM__INV_ACM_MASK 0x02000000L +#define MC_SEQ_DRAM__INV_ACM__SHIFT 0x00000019 +#define MC_SEQ_DRAM__ODT_ACT_MASK 0x08000000L +#define MC_SEQ_DRAM__ODT_ACT__SHIFT 0x0000001b +#define MC_SEQ_DRAM__ODT_ENB_MASK 0x04000000L +#define MC_SEQ_DRAM__ODT_ENB__SHIFT 0x0000001a +#define MC_SEQ_DRAM__RST_CTL_MASK 0x10000000L +#define MC_SEQ_DRAM__RST_CTL__SHIFT 0x0000001c +#define MC_SEQ_DRAM__STB_CNT_MASK 0x00000f00L +#define MC_SEQ_DRAM__STB_CNT__SHIFT 0x00000008 +#define MC_SEQ_DRAM__TRI_CKE_MASK 0x40000000L +#define MC_SEQ_DRAM__TRI_CKE__SHIFT 0x0000001e +#define MC_SEQ_DRAM__TRI_MIO_DYN_MASK 0x20000000L +#define MC_SEQ_DRAM__TRI_MIO_DYN__SHIFT 0x0000001d +#define MC_SEQ_FIFO_CTL__CG_DIS_D0_MASK 0x00000100L +#define MC_SEQ_FIFO_CTL__CG_DIS_D0__SHIFT 0x00000008 +#define MC_SEQ_FIFO_CTL__CG_DIS_D1_MASK 0x00000200L +#define MC_SEQ_FIFO_CTL__CG_DIS_D1__SHIFT 0x00000009 +#define MC_SEQ_FIFO_CTL__R_LD_INIT_MASK 0x00000030L +#define MC_SEQ_FIFO_CTL__R_LD_INIT__SHIFT 0x00000004 +#define MC_SEQ_FIFO_CTL__R_SYC_SEL_MASK 0x000000c0L +#define MC_SEQ_FIFO_CTL__R_SYC_SEL__SHIFT 0x00000006 +#define MC_SEQ_FIFO_CTL__SYC_DLY_MASK 0x00007000L +#define MC_SEQ_FIFO_CTL__SYC_DLY__SHIFT 0x0000000c +#define MC_SEQ_FIFO_CTL__W_ASYC_EXT_MASK 0x00030000L +#define MC_SEQ_FIFO_CTL__W_ASYC_EXT__SHIFT 0x00000010 +#define MC_SEQ_FIFO_CTL__W_DSYC_EXT_MASK 0x000c0000L +#define MC_SEQ_FIFO_CTL__W_DSYC_EXT__SHIFT 0x00000012 +#define MC_SEQ_FIFO_CTL__W_LD_INIT_D0_MASK 0x00000003L +#define MC_SEQ_FIFO_CTL__W_LD_INIT_D0__SHIFT 0x00000000 +#define MC_SEQ_FIFO_CTL__W_LD_INIT_D1_MASK 0x00000c00L +#define MC_SEQ_FIFO_CTL__W_LD_INIT_D1__SHIFT 0x0000000a +#define MC_SEQ_FIFO_CTL__W_SYC_SEL_MASK 0x0000000cL +#define MC_SEQ_FIFO_CTL__W_SYC_SEL__SHIFT 0x00000002 +#define MC_SEQ_IO_DEBUG_DATA__IO_DEBUG_DATA_MASK 0xffffffffL +#define MC_SEQ_IO_DEBUG_DATA__IO_DEBUG_DATA__SHIFT 0x00000000 +#define MC_SEQ_IO_DEBUG_INDEX__IO_DEBUG_INDEX_MASK 0x000001ffL +#define MC_SEQ_IO_DEBUG_INDEX__IO_DEBUG_INDEX__SHIFT 0x00000000 +#define MC_SEQ_IO_RDBI__MASK_MASK 0xffffffffL +#define MC_SEQ_IO_RDBI__MASK__SHIFT 0x00000000 +#define MC_SEQ_IO_REDC__EDC_MASK 0xffffffffL +#define MC_SEQ_IO_REDC__EDC__SHIFT 0x00000000 +#define MC_SEQ_IO_RESERVE_D0__APHY_RSV_MASK 0xff000000L +#define MC_SEQ_IO_RESERVE_D0__APHY_RSV__SHIFT 0x00000018 +#define MC_SEQ_IO_RESERVE_D0__DPHY0_RSV_MASK 0x00000fffL +#define MC_SEQ_IO_RESERVE_D0__DPHY0_RSV__SHIFT 0x00000000 +#define MC_SEQ_IO_RESERVE_D0__DPHY1_RSV_MASK 0x00fff000L +#define MC_SEQ_IO_RESERVE_D0__DPHY1_RSV__SHIFT 0x0000000c +#define MC_SEQ_IO_RESERVE_D1__APHY_RSV_MASK 0xff000000L +#define MC_SEQ_IO_RESERVE_D1__APHY_RSV__SHIFT 0x00000018 +#define MC_SEQ_IO_RESERVE_D1__DPHY0_RSV_MASK 0x00000fffL +#define MC_SEQ_IO_RESERVE_D1__DPHY0_RSV__SHIFT 0x00000000 +#define MC_SEQ_IO_RESERVE_D1__DPHY1_RSV_MASK 0x00fff000L +#define MC_SEQ_IO_RESERVE_D1__DPHY1_RSV__SHIFT 0x0000000c +#define MC_SEQ_IO_RWORD0__RDATA_MASK 0xffffffffL +#define MC_SEQ_IO_RWORD0__RDATA__SHIFT 0x00000000 +#define MC_SEQ_IO_RWORD1__RDATA_MASK 0xffffffffL +#define MC_SEQ_IO_RWORD1__RDATA__SHIFT 0x00000000 +#define MC_SEQ_IO_RWORD2__RDATA_MASK 0xffffffffL +#define MC_SEQ_IO_RWORD2__RDATA__SHIFT 0x00000000 +#define MC_SEQ_IO_RWORD3__RDATA_MASK 0xffffffffL +#define MC_SEQ_IO_RWORD3__RDATA__SHIFT 0x00000000 +#define MC_SEQ_IO_RWORD4__RDATA_MASK 0xffffffffL +#define MC_SEQ_IO_RWORD4__RDATA__SHIFT 0x00000000 +#define MC_SEQ_IO_RWORD5__RDATA_MASK 0xffffffffL +#define MC_SEQ_IO_RWORD5__RDATA__SHIFT 0x00000000 +#define MC_SEQ_IO_RWORD6__RDATA_MASK 0xffffffffL +#define MC_SEQ_IO_RWORD6__RDATA__SHIFT 0x00000000 +#define MC_SEQ_IO_RWORD7__RDATA_MASK 0xffffffffL +#define MC_SEQ_IO_RWORD7__RDATA__SHIFT 0x00000000 +#define MC_SEQ_MISC0__VALUE_MASK 0xffffffffL +#define MC_SEQ_MISC0__VALUE__SHIFT 0x00000000 +#define MC_SEQ_MISC1__VALUE_MASK 0xffffffffL +#define MC_SEQ_MISC1__VALUE__SHIFT 0x00000000 +#define MC_SEQ_MISC3__VALUE_MASK 0xffffffffL +#define MC_SEQ_MISC3__VALUE__SHIFT 0x00000000 +#define MC_SEQ_MISC4__VALUE_MASK 0xffffffffL +#define MC_SEQ_MISC4__VALUE__SHIFT 0x00000000 +#define MC_SEQ_MISC5__VALUE_MASK 0xffffffffL +#define MC_SEQ_MISC5__VALUE__SHIFT 0x00000000 +#define MC_SEQ_MISC6__VALUE_MASK 0xffffffffL +#define MC_SEQ_MISC6__VALUE__SHIFT 0x00000000 +#define MC_SEQ_MISC7__VALUE_MASK 0xffffffffL +#define MC_SEQ_MISC7__VALUE__SHIFT 0x00000000 +#define MC_SEQ_MISC8__VALUE_MASK 0xffffffffL +#define MC_SEQ_MISC8__VALUE__SHIFT 0x00000000 +#define MC_SEQ_MISC9__VALUE_MASK 0xffffffffL +#define MC_SEQ_MISC9__VALUE__SHIFT 0x00000000 +#define MC_SEQ_MISC_TIMING2__FAW_MASK 0x00001f00L +#define MC_SEQ_MISC_TIMING2__FAW__SHIFT 0x00000008 +#define MC_SEQ_MISC_TIMING2_LP__FAW_MASK 0x00001f00L +#define MC_SEQ_MISC_TIMING2_LP__FAW__SHIFT 0x00000008 +#define MC_SEQ_MISC_TIMING2_LP__PA2RDATA_MASK 0x00000007L +#define MC_SEQ_MISC_TIMING2_LP__PA2RDATA__SHIFT 0x00000000 +#define MC_SEQ_MISC_TIMING2_LP__PA2WDATA_MASK 0x00000070L +#define MC_SEQ_MISC_TIMING2_LP__PA2WDATA__SHIFT 0x00000004 +#define MC_SEQ_MISC_TIMING2_LP__TADR_MASK 0x00e00000L +#define MC_SEQ_MISC_TIMING2_LP__TADR__SHIFT 0x00000015 +#define MC_SEQ_MISC_TIMING2_LP__TFCKTR_MASK 0x0f000000L +#define MC_SEQ_MISC_TIMING2_LP__TFCKTR__SHIFT 0x00000018 +#define MC_SEQ_MISC_TIMING2_LP__TREDC_MASK 0x0000e000L +#define MC_SEQ_MISC_TIMING2_LP__TREDC__SHIFT 0x0000000d +#define MC_SEQ_MISC_TIMING2_LP__TWDATATR_MASK 0xf0000000L +#define MC_SEQ_MISC_TIMING2_LP__TWDATATR__SHIFT 0x0000001c +#define MC_SEQ_MISC_TIMING2_LP__TWEDC_MASK 0x001f0000L +#define MC_SEQ_MISC_TIMING2_LP__TWEDC__SHIFT 0x00000010 +#define MC_SEQ_MISC_TIMING2__PA2RDATA_MASK 0x00000007L +#define MC_SEQ_MISC_TIMING2__PA2RDATA__SHIFT 0x00000000 +#define MC_SEQ_MISC_TIMING2__PA2WDATA_MASK 0x00000070L +#define MC_SEQ_MISC_TIMING2__PA2WDATA__SHIFT 0x00000004 +#define MC_SEQ_MISC_TIMING2__T32AW_MASK 0x01e00000L +#define MC_SEQ_MISC_TIMING2__T32AW__SHIFT 0x00000015 +#define MC_SEQ_MISC_TIMING2__TREDC_MASK 0x0000e000L +#define MC_SEQ_MISC_TIMING2__TREDC__SHIFT 0x0000000d +#define MC_SEQ_MISC_TIMING2__TWDATATR_MASK 0xf0000000L +#define MC_SEQ_MISC_TIMING2__TWDATATR__SHIFT 0x0000001c +#define MC_SEQ_MISC_TIMING2__TWEDC_MASK 0x001f0000L +#define MC_SEQ_MISC_TIMING2__TWEDC__SHIFT 0x00000010 +#define MC_SEQ_MISC_TIMING_LP__TRFC_MASK 0x1ff00000L +#define MC_SEQ_MISC_TIMING_LP__TRFC__SHIFT 0x00000014 +#define MC_SEQ_MISC_TIMING_LP__TRP_MASK 0x000f8000L +#define MC_SEQ_MISC_TIMING_LP__TRP_RDA_MASK 0x00003f00L +#define MC_SEQ_MISC_TIMING_LP__TRP_RDA__SHIFT 0x00000008 +#define MC_SEQ_MISC_TIMING_LP__TRP__SHIFT 0x0000000f +#define MC_SEQ_MISC_TIMING_LP__TRP_WRA_MASK 0x0000003fL +#define MC_SEQ_MISC_TIMING_LP__TRP_WRA__SHIFT 0x00000000 +#define MC_SEQ_MISC_TIMING__TRFC_MASK 0x1ff00000L +#define MC_SEQ_MISC_TIMING__TRFC__SHIFT 0x00000014 +#define MC_SEQ_MISC_TIMING__TRP_MASK 0x000f8000L +#define MC_SEQ_MISC_TIMING__TRP_RDA_MASK 0x00003f00L +#define MC_SEQ_MISC_TIMING__TRP_RDA__SHIFT 0x00000008 +#define MC_SEQ_MISC_TIMING__TRP__SHIFT 0x0000000f +#define MC_SEQ_MISC_TIMING__TRP_WRA_MASK 0x0000003fL +#define MC_SEQ_MISC_TIMING__TRP_WRA__SHIFT 0x00000000 +#define MC_SEQ_MPLL_OVERRIDE__AD_PLL_RESET_OVERRIDE_MASK 0x00000001L +#define MC_SEQ_MPLL_OVERRIDE__AD_PLL_RESET_OVERRIDE__SHIFT 0x00000000 +#define MC_SEQ_MPLL_OVERRIDE__ATGM_CLK_SEL_OVERRIDE_MASK 0x00000020L +#define MC_SEQ_MPLL_OVERRIDE__ATGM_CLK_SEL_OVERRIDE__SHIFT 0x00000005 +#define MC_SEQ_MPLL_OVERRIDE__DQ_0_0_PLL_RESET_OVERRIDE_MASK 0x00000002L +#define MC_SEQ_MPLL_OVERRIDE__DQ_0_0_PLL_RESET_OVERRIDE__SHIFT 0x00000001 +#define MC_SEQ_MPLL_OVERRIDE__DQ_0_1_PLL_RESET_OVERRIDE_MASK 0x00000004L +#define MC_SEQ_MPLL_OVERRIDE__DQ_0_1_PLL_RESET_OVERRIDE__SHIFT 0x00000002 +#define MC_SEQ_MPLL_OVERRIDE__DQ_1_0_PLL_RESET_OVERRIDE_MASK 0x00000008L +#define MC_SEQ_MPLL_OVERRIDE__DQ_1_0_PLL_RESET_OVERRIDE__SHIFT 0x00000003 +#define MC_SEQ_MPLL_OVERRIDE__DQ_1_1_PLL_RESET_OVERRIDE_MASK 0x00000010L +#define MC_SEQ_MPLL_OVERRIDE__DQ_1_1_PLL_RESET_OVERRIDE__SHIFT 0x00000004 +#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_EN_OVERRIDE_MASK 0x00000040L +#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_EN_OVERRIDE__SHIFT 0x00000006 +#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_SEL_OVERRIDE_MASK 0x00000080L +#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_SEL_OVERRIDE__SHIFT 0x00000007 +#define MC_SEQ_PERF_CNTL_1__PAUSE_MASK 0x00000001L +#define MC_SEQ_PERF_CNTL_1__PAUSE__SHIFT 0x00000000 +#define MC_SEQ_PERF_CNTL_1__SEL_A_MSB_MASK 0x00000100L +#define MC_SEQ_PERF_CNTL_1__SEL_A_MSB__SHIFT 0x00000008 +#define MC_SEQ_PERF_CNTL_1__SEL_B_MSB_MASK 0x00000200L +#define MC_SEQ_PERF_CNTL_1__SEL_B_MSB__SHIFT 0x00000009 +#define MC_SEQ_PERF_CNTL_1__SEL_CH0_C_MSB_MASK 0x00000400L +#define MC_SEQ_PERF_CNTL_1__SEL_CH0_C_MSB__SHIFT 0x0000000a +#define MC_SEQ_PERF_CNTL_1__SEL_CH0_D_MSB_MASK 0x00000800L +#define MC_SEQ_PERF_CNTL_1__SEL_CH0_D_MSB__SHIFT 0x0000000b +#define MC_SEQ_PERF_CNTL_1__SEL_CH1_A_MSB_MASK 0x00001000L +#define MC_SEQ_PERF_CNTL_1__SEL_CH1_A_MSB__SHIFT 0x0000000c +#define MC_SEQ_PERF_CNTL_1__SEL_CH1_B_MSB_MASK 0x00002000L +#define MC_SEQ_PERF_CNTL_1__SEL_CH1_B_MSB__SHIFT 0x0000000d +#define MC_SEQ_PERF_CNTL_1__SEL_CH1_C_MSB_MASK 0x00004000L +#define MC_SEQ_PERF_CNTL_1__SEL_CH1_C_MSB__SHIFT 0x0000000e +#define MC_SEQ_PERF_CNTL_1__SEL_CH1_D_MSB_MASK 0x00008000L +#define MC_SEQ_PERF_CNTL_1__SEL_CH1_D_MSB__SHIFT 0x0000000f +#define MC_SEQ_PERF_CNTL__CNTL_MASK 0xc0000000L +#define MC_SEQ_PERF_CNTL__CNTL__SHIFT 0x0000001e +#define MC_SEQ_PERF_CNTL__MONITOR_PERIOD_MASK 0x3fffffffL +#define MC_SEQ_PERF_CNTL__MONITOR_PERIOD__SHIFT 0x00000000 +#define MC_SEQ_PERF_SEQ_CNT_A_I0__VALUE_MASK 0xffffffffL +#define MC_SEQ_PERF_SEQ_CNT_A_I0__VALUE__SHIFT 0x00000000 +#define MC_SEQ_PERF_SEQ_CNT_A_I1__VALUE_MASK 0xffffffffL +#define MC_SEQ_PERF_SEQ_CNT_A_I1__VALUE__SHIFT 0x00000000 +#define MC_SEQ_PERF_SEQ_CNT_B_I0__VALUE_MASK 0xffffffffL +#define MC_SEQ_PERF_SEQ_CNT_B_I0__VALUE__SHIFT 0x00000000 +#define MC_SEQ_PERF_SEQ_CNT_B_I1__VALUE_MASK 0xffffffffL +#define MC_SEQ_PERF_SEQ_CNT_B_I1__VALUE__SHIFT 0x00000000 +#define MC_SEQ_PERF_SEQ_CNT_C_I0__VALUE_MASK 0xffffffffL +#define MC_SEQ_PERF_SEQ_CNT_C_I0__VALUE__SHIFT 0x00000000 +#define MC_SEQ_PERF_SEQ_CNT_C_I1__VALUE_MASK 0xffffffffL +#define MC_SEQ_PERF_SEQ_CNT_C_I1__VALUE__SHIFT 0x00000000 +#define MC_SEQ_PERF_SEQ_CNT_D_I0__VALUE_MASK 0xffffffffL +#define MC_SEQ_PERF_SEQ_CNT_D_I0__VALUE__SHIFT 0x00000000 +#define MC_SEQ_PERF_SEQ_CNT_D_I1__VALUE_MASK 0xffffffffL +#define MC_SEQ_PERF_SEQ_CNT_D_I1__VALUE__SHIFT 0x00000000 +#define MC_SEQ_PERF_SEQ_CTL__SEL_A_MASK 0x0000000fL +#define MC_SEQ_PERF_SEQ_CTL__SEL_A__SHIFT 0x00000000 +#define MC_SEQ_PERF_SEQ_CTL__SEL_B_MASK 0x000000f0L +#define MC_SEQ_PERF_SEQ_CTL__SEL_B__SHIFT 0x00000004 +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_C_MASK 0x00000f00L +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_C__SHIFT 0x00000008 +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_D_MASK 0x0000f000L +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_D__SHIFT 0x0000000c +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_A_MASK 0x000f0000L +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_A__SHIFT 0x00000010 +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_B_MASK 0x00f00000L +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_B__SHIFT 0x00000014 +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_C_MASK 0x0f000000L +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_C__SHIFT 0x00000018 +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_D_MASK 0xf0000000L +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_D__SHIFT 0x0000001c +#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MASK 0x0000ffffL +#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB0_MASK 0x20000000L +#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB0__SHIFT 0x0000001d +#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB1_MASK 0x10000000L +#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB1__SHIFT 0x0000001c +#define MC_SEQ_PMG_CMD_EMRS_LP__ADR__SHIFT 0x00000000 +#define MC_SEQ_PMG_CMD_EMRS_LP__BNK_MSB_MASK 0x00080000L +#define MC_SEQ_PMG_CMD_EMRS_LP__BNK_MSB__SHIFT 0x00000013 +#define MC_SEQ_PMG_CMD_EMRS_LP__CSB_MASK 0x00600000L +#define MC_SEQ_PMG_CMD_EMRS_LP__CSB__SHIFT 0x00000015 +#define MC_SEQ_PMG_CMD_EMRS_LP__END_MASK 0x00100000L +#define MC_SEQ_PMG_CMD_EMRS_LP__END__SHIFT 0x00000014 +#define MC_SEQ_PMG_CMD_EMRS_LP__MOP_MASK 0x00070000L +#define MC_SEQ_PMG_CMD_EMRS_LP__MOP__SHIFT 0x00000010 +#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MASK 0x0000ffffL +#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB0_MASK 0x20000000L +#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB0__SHIFT 0x0000001d +#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB1_MASK 0x10000000L +#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB1__SHIFT 0x0000001c +#define MC_SEQ_PMG_CMD_MRS1_LP__ADR__SHIFT 0x00000000 +#define MC_SEQ_PMG_CMD_MRS1_LP__BNK_MSB_MASK 0x00080000L +#define MC_SEQ_PMG_CMD_MRS1_LP__BNK_MSB__SHIFT 0x00000013 +#define MC_SEQ_PMG_CMD_MRS1_LP__CSB_MASK 0x00600000L +#define MC_SEQ_PMG_CMD_MRS1_LP__CSB__SHIFT 0x00000015 +#define MC_SEQ_PMG_CMD_MRS1_LP__END_MASK 0x00100000L +#define MC_SEQ_PMG_CMD_MRS1_LP__END__SHIFT 0x00000014 +#define MC_SEQ_PMG_CMD_MRS1_LP__MOP_MASK 0x00070000L +#define MC_SEQ_PMG_CMD_MRS1_LP__MOP__SHIFT 0x00000010 +#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MASK 0x0000ffffL +#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB0_MASK 0x20000000L +#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB0__SHIFT 0x0000001d +#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB1_MASK 0x10000000L +#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB1__SHIFT 0x0000001c +#define MC_SEQ_PMG_CMD_MRS2_LP__ADR__SHIFT 0x00000000 +#define MC_SEQ_PMG_CMD_MRS2_LP__BNK_MSB_MASK 0x00080000L +#define MC_SEQ_PMG_CMD_MRS2_LP__BNK_MSB__SHIFT 0x00000013 +#define MC_SEQ_PMG_CMD_MRS2_LP__CSB_MASK 0x00600000L +#define MC_SEQ_PMG_CMD_MRS2_LP__CSB__SHIFT 0x00000015 +#define MC_SEQ_PMG_CMD_MRS2_LP__END_MASK 0x00100000L +#define MC_SEQ_PMG_CMD_MRS2_LP__END__SHIFT 0x00000014 +#define MC_SEQ_PMG_CMD_MRS2_LP__MOP_MASK 0x00070000L +#define MC_SEQ_PMG_CMD_MRS2_LP__MOP__SHIFT 0x00000010 +#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MASK 0x0000ffffL +#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB0_MASK 0x20000000L +#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB0__SHIFT 0x0000001d +#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB1_MASK 0x10000000L +#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB1__SHIFT 0x0000001c +#define MC_SEQ_PMG_CMD_MRS_LP__ADR__SHIFT 0x00000000 +#define MC_SEQ_PMG_CMD_MRS_LP__BNK_MSB_MASK 0x00080000L +#define MC_SEQ_PMG_CMD_MRS_LP__BNK_MSB__SHIFT 0x00000013 +#define MC_SEQ_PMG_CMD_MRS_LP__CSB_MASK 0x00600000L +#define MC_SEQ_PMG_CMD_MRS_LP__CSB__SHIFT 0x00000015 +#define MC_SEQ_PMG_CMD_MRS_LP__END_MASK 0x00100000L +#define MC_SEQ_PMG_CMD_MRS_LP__END__SHIFT 0x00000014 +#define MC_SEQ_PMG_CMD_MRS_LP__MOP_MASK 0x00070000L +#define MC_SEQ_PMG_CMD_MRS_LP__MOP__SHIFT 0x00000010 +#define MC_SEQ_PMG_PG_HWCNTL__ACAO_MASK 0x00040000L +#define MC_SEQ_PMG_PG_HWCNTL__ACAO__SHIFT 0x00000012 +#define MC_SEQ_PMG_PG_HWCNTL__AC_DLY_MASK 0x00000300L +#define MC_SEQ_PMG_PG_HWCNTL__AC_DLY__SHIFT 0x00000008 +#define MC_SEQ_PMG_PG_HWCNTL__D_DLY_MASK 0x000000c0L +#define MC_SEQ_PMG_PG_HWCNTL__D_DLY__SHIFT 0x00000006 +#define MC_SEQ_PMG_PG_HWCNTL__G_DLY_MASK 0x00003c00L +#define MC_SEQ_PMG_PG_HWCNTL__G_DLY__SHIFT 0x0000000a +#define MC_SEQ_PMG_PG_HWCNTL__PWRGATE_EN_MASK 0x00000001L +#define MC_SEQ_PMG_PG_HWCNTL__PWRGATE_EN__SHIFT 0x00000000 +#define MC_SEQ_PMG_PG_HWCNTL__RXAO_MASK 0x00020000L +#define MC_SEQ_PMG_PG_HWCNTL__RXAO__SHIFT 0x00000011 +#define MC_SEQ_PMG_PG_HWCNTL__STAGGER_EN_MASK 0x00000002L +#define MC_SEQ_PMG_PG_HWCNTL__STAGGER_EN__SHIFT 0x00000001 +#define MC_SEQ_PMG_PG_HWCNTL__TPGCG_MASK 0x0000003cL +#define MC_SEQ_PMG_PG_HWCNTL__TPGCG__SHIFT 0x00000002 +#define MC_SEQ_PMG_PG_HWCNTL__TXAO_MASK 0x00010000L +#define MC_SEQ_PMG_PG_HWCNTL__TXAO__SHIFT 0x00000010 +#define MC_SEQ_PMG_PG_SWCNTL_0__GMCON_SR_COMMIT_MASK 0x80000000L +#define MC_SEQ_PMG_PG_SWCNTL_0__GMCON_SR_COMMIT__SHIFT 0x0000001f +#define MC_SEQ_PMG_PG_SWCNTL_0__PMA0_AC_ENB_MASK 0x00010000L +#define MC_SEQ_PMG_PG_SWCNTL_0__PMA0_AC_ENB__SHIFT 0x00000010 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_RX_ENB_MASK 0x00000020L +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_RX_ENB__SHIFT 0x00000005 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_TX_ENB_MASK 0x00000002L +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_TX_ENB__SHIFT 0x00000001 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_RX_ENB_MASK 0x00000010L +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_RX_ENB__SHIFT 0x00000004 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_TX_ENB_MASK 0x00000001L +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_TX_ENB__SHIFT 0x00000000 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_RX_ENB_MASK 0x00000040L +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_RX_ENB__SHIFT 0x00000006 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_TX_ENB_MASK 0x00000004L +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_TX_ENB__SHIFT 0x00000002 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_RX_ENB_MASK 0x00000080L +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_RX_ENB__SHIFT 0x00000007 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_TX_ENB_MASK 0x00000008L +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_TX_ENB__SHIFT 0x00000003 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_RX_ENB_MASK 0x00002000L +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_RX_ENB__SHIFT 0x0000000d +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_TX_ENB_MASK 0x00000200L +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_TX_ENB__SHIFT 0x00000009 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_RX_ENB_MASK 0x00001000L +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_RX_ENB__SHIFT 0x0000000c +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_TX_ENB_MASK 0x00000100L +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_TX_ENB__SHIFT 0x00000008 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_RX_ENB_MASK 0x00004000L +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_RX_ENB__SHIFT 0x0000000e +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_TX_ENB_MASK 0x00000400L +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_TX_ENB__SHIFT 0x0000000a +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_RX_ENB_MASK 0x00008000L +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_RX_ENB__SHIFT 0x0000000f +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_TX_ENB_MASK 0x00000800L +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_TX_ENB__SHIFT 0x0000000b +#define MC_SEQ_PMG_PG_SWCNTL_1__GMCON_SR_COMMIT_MASK 0x80000000L +#define MC_SEQ_PMG_PG_SWCNTL_1__GMCON_SR_COMMIT__SHIFT 0x0000001f +#define MC_SEQ_PMG_PG_SWCNTL_1__PMA1_AC_ENB_MASK 0x00010000L +#define MC_SEQ_PMG_PG_SWCNTL_1__PMA1_AC_ENB__SHIFT 0x00000010 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_RX_ENB_MASK 0x00000020L +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_RX_ENB__SHIFT 0x00000005 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_TX_ENB_MASK 0x00000002L +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_TX_ENB__SHIFT 0x00000001 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_RX_ENB_MASK 0x00000010L +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_RX_ENB__SHIFT 0x00000004 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_TX_ENB_MASK 0x00000001L +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_TX_ENB__SHIFT 0x00000000 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_RX_ENB_MASK 0x00000040L +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_RX_ENB__SHIFT 0x00000006 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_TX_ENB_MASK 0x00000004L +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_TX_ENB__SHIFT 0x00000002 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_RX_ENB_MASK 0x00000080L +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_RX_ENB__SHIFT 0x00000007 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_TX_ENB_MASK 0x00000008L +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_TX_ENB__SHIFT 0x00000003 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_RX_ENB_MASK 0x00002000L +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_RX_ENB__SHIFT 0x0000000d +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_TX_ENB_MASK 0x00000200L +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_TX_ENB__SHIFT 0x00000009 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_RX_ENB_MASK 0x00001000L +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_RX_ENB__SHIFT 0x0000000c +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_TX_ENB_MASK 0x00000100L +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_TX_ENB__SHIFT 0x00000008 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_RX_ENB_MASK 0x00004000L +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_RX_ENB__SHIFT 0x0000000e +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_TX_ENB_MASK 0x00000400L +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_TX_ENB__SHIFT 0x0000000a +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_RX_ENB_MASK 0x00008000L +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_RX_ENB__SHIFT 0x0000000f +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_TX_ENB_MASK 0x00000800L +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_TX_ENB__SHIFT 0x0000000b +#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE_MASK 0x001c0000L +#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE__SHIFT 0x00000012 +#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE_SS_MASK 0xff000000L +#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE_SS__SHIFT 0x00000018 +#define MC_SEQ_PMG_TIMING_LP__TCKE_MASK 0x0003f000L +#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE_MASK 0x00000f00L +#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE_MSB_MASK 0x00800000L +#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE_MSB__SHIFT 0x00000017 +#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE__SHIFT 0x00000008 +#define MC_SEQ_PMG_TIMING_LP__TCKE__SHIFT 0x0000000c +#define MC_SEQ_PMG_TIMING_LP__TCKSRE_MASK 0x00000007L +#define MC_SEQ_PMG_TIMING_LP__TCKSRE__SHIFT 0x00000000 +#define MC_SEQ_PMG_TIMING_LP__TCKSRX_MASK 0x00000070L +#define MC_SEQ_PMG_TIMING_LP__TCKSRX__SHIFT 0x00000004 +#define MC_SEQ_PMG_TIMING__SEQ_IDLE_MASK 0x001c0000L +#define MC_SEQ_PMG_TIMING__SEQ_IDLE__SHIFT 0x00000012 +#define MC_SEQ_PMG_TIMING__SEQ_IDLE_SS_MASK 0xff000000L +#define MC_SEQ_PMG_TIMING__SEQ_IDLE_SS__SHIFT 0x00000018 +#define MC_SEQ_PMG_TIMING__TCKE_MASK 0x0003f000L +#define MC_SEQ_PMG_TIMING__TCKE_PULSE_MASK 0x00000f00L +#define MC_SEQ_PMG_TIMING__TCKE_PULSE_MSB_MASK 0x00800000L +#define MC_SEQ_PMG_TIMING__TCKE_PULSE_MSB__SHIFT 0x00000017 +#define MC_SEQ_PMG_TIMING__TCKE_PULSE__SHIFT 0x00000008 +#define MC_SEQ_PMG_TIMING__TCKE__SHIFT 0x0000000c +#define MC_SEQ_PMG_TIMING__TCKSRE_MASK 0x00000007L +#define MC_SEQ_PMG_TIMING__TCKSRE__SHIFT 0x00000000 +#define MC_SEQ_PMG_TIMING__TCKSRX_MASK 0x00000070L +#define MC_SEQ_PMG_TIMING__TCKSRX__SHIFT 0x00000004 +#define MC_SEQ_RAS_TIMING_LP__TRCDRA_MASK 0x000f8000L +#define MC_SEQ_RAS_TIMING_LP__TRCDRA__SHIFT 0x0000000f +#define MC_SEQ_RAS_TIMING_LP__TRCDR_MASK 0x00007c00L +#define MC_SEQ_RAS_TIMING_LP__TRCDR__SHIFT 0x0000000a +#define MC_SEQ_RAS_TIMING_LP__TRCDWA_MASK 0x000003e0L +#define MC_SEQ_RAS_TIMING_LP__TRCDWA__SHIFT 0x00000005 +#define MC_SEQ_RAS_TIMING_LP__TRCDW_MASK 0x0000001fL +#define MC_SEQ_RAS_TIMING_LP__TRCDW__SHIFT 0x00000000 +#define MC_SEQ_RAS_TIMING_LP__TRC_MASK 0x7f000000L +#define MC_SEQ_RAS_TIMING_LP__TRC__SHIFT 0x00000018 +#define MC_SEQ_RAS_TIMING_LP__TRRD_MASK 0x00f00000L +#define MC_SEQ_RAS_TIMING_LP__TRRD__SHIFT 0x00000014 +#define MC_SEQ_RAS_TIMING__TRCDRA_MASK 0x000f8000L +#define MC_SEQ_RAS_TIMING__TRCDRA__SHIFT 0x0000000f +#define MC_SEQ_RAS_TIMING__TRCDR_MASK 0x00007c00L +#define MC_SEQ_RAS_TIMING__TRCDR__SHIFT 0x0000000a +#define MC_SEQ_RAS_TIMING__TRCDWA_MASK 0x000003e0L +#define MC_SEQ_RAS_TIMING__TRCDWA__SHIFT 0x00000005 +#define MC_SEQ_RAS_TIMING__TRCDW_MASK 0x0000001fL +#define MC_SEQ_RAS_TIMING__TRCDW__SHIFT 0x00000000 +#define MC_SEQ_RAS_TIMING__TRC_MASK 0x7f000000L +#define MC_SEQ_RAS_TIMING__TRC__SHIFT 0x00000018 +#define MC_SEQ_RAS_TIMING__TRRD_MASK 0x00f00000L +#define MC_SEQ_RAS_TIMING__TRRD__SHIFT 0x00000014 +#define MC_SEQ_RD_CTL_D0_LP__RBS_DLY_MASK 0x01f00000L +#define MC_SEQ_RD_CTL_D0_LP__RBS_DLY__SHIFT 0x00000014 +#define MC_SEQ_RD_CTL_D0_LP__RBS_WEDC_DLY_MASK 0x3e000000L +#define MC_SEQ_RD_CTL_D0_LP__RBS_WEDC_DLY__SHIFT 0x00000019 +#define MC_SEQ_RD_CTL_D0_LP__RCV_DLY_MASK 0x00000007L +#define MC_SEQ_RD_CTL_D0_LP__RCV_DLY__SHIFT 0x00000000 +#define MC_SEQ_RD_CTL_D0_LP__RCV_EXT_MASK 0x000000f8L +#define MC_SEQ_RD_CTL_D0_LP__RCV_EXT__SHIFT 0x00000003 +#define MC_SEQ_RD_CTL_D0_LP__RST_HLD_MASK 0x0000f000L +#define MC_SEQ_RD_CTL_D0_LP__RST_HLD__SHIFT 0x0000000c +#define MC_SEQ_RD_CTL_D0_LP__RST_SEL_MASK 0x00000300L +#define MC_SEQ_RD_CTL_D0_LP__RST_SEL__SHIFT 0x00000008 +#define MC_SEQ_RD_CTL_D0_LP__RXDPWRON_DLY_MASK 0x00000c00L +#define MC_SEQ_RD_CTL_D0_LP__RXDPWRON_DLY__SHIFT 0x0000000a +#define MC_SEQ_RD_CTL_D0_LP__STR_PRE_MASK 0x00010000L +#define MC_SEQ_RD_CTL_D0_LP__STR_PRE__SHIFT 0x00000010 +#define MC_SEQ_RD_CTL_D0_LP__STR_PST_MASK 0x00020000L +#define MC_SEQ_RD_CTL_D0_LP__STR_PST__SHIFT 0x00000011 +#define MC_SEQ_RD_CTL_D0__RBS_DLY_MASK 0x01f00000L +#define MC_SEQ_RD_CTL_D0__RBS_DLY__SHIFT 0x00000014 +#define MC_SEQ_RD_CTL_D0__RBS_WEDC_DLY_MASK 0x3e000000L +#define MC_SEQ_RD_CTL_D0__RBS_WEDC_DLY__SHIFT 0x00000019 +#define MC_SEQ_RD_CTL_D0__RCV_DLY_MASK 0x00000007L +#define MC_SEQ_RD_CTL_D0__RCV_DLY__SHIFT 0x00000000 +#define MC_SEQ_RD_CTL_D0__RCV_EXT_MASK 0x000000f8L +#define MC_SEQ_RD_CTL_D0__RCV_EXT__SHIFT 0x00000003 +#define MC_SEQ_RD_CTL_D0__RST_HLD_MASK 0x0000f000L +#define MC_SEQ_RD_CTL_D0__RST_HLD__SHIFT 0x0000000c +#define MC_SEQ_RD_CTL_D0__RST_SEL_MASK 0x00000300L +#define MC_SEQ_RD_CTL_D0__RST_SEL__SHIFT 0x00000008 +#define MC_SEQ_RD_CTL_D0__RXDPWRON_DLY_MASK 0x00000c00L +#define MC_SEQ_RD_CTL_D0__RXDPWRON_DLY__SHIFT 0x0000000a +#define MC_SEQ_RD_CTL_D0__STR_PRE_MASK 0x00010000L +#define MC_SEQ_RD_CTL_D0__STR_PRE__SHIFT 0x00000010 +#define MC_SEQ_RD_CTL_D0__STR_PST_MASK 0x00020000L +#define MC_SEQ_RD_CTL_D0__STR_PST__SHIFT 0x00000011 +#define MC_SEQ_RD_CTL_D1_LP__RBS_DLY_MASK 0x01f00000L +#define MC_SEQ_RD_CTL_D1_LP__RBS_DLY__SHIFT 0x00000014 +#define MC_SEQ_RD_CTL_D1_LP__RBS_WEDC_DLY_MASK 0x3e000000L +#define MC_SEQ_RD_CTL_D1_LP__RBS_WEDC_DLY__SHIFT 0x00000019 +#define MC_SEQ_RD_CTL_D1_LP__RCV_DLY_MASK 0x00000007L +#define MC_SEQ_RD_CTL_D1_LP__RCV_DLY__SHIFT 0x00000000 +#define MC_SEQ_RD_CTL_D1_LP__RCV_EXT_MASK 0x000000f8L +#define MC_SEQ_RD_CTL_D1_LP__RCV_EXT__SHIFT 0x00000003 +#define MC_SEQ_RD_CTL_D1_LP__RST_HLD_MASK 0x0000f000L +#define MC_SEQ_RD_CTL_D1_LP__RST_HLD__SHIFT 0x0000000c +#define MC_SEQ_RD_CTL_D1_LP__RST_SEL_MASK 0x00000300L +#define MC_SEQ_RD_CTL_D1_LP__RST_SEL__SHIFT 0x00000008 +#define MC_SEQ_RD_CTL_D1_LP__RXDPWRON_DLY_MASK 0x00000c00L +#define MC_SEQ_RD_CTL_D1_LP__RXDPWRON_DLY__SHIFT 0x0000000a +#define MC_SEQ_RD_CTL_D1_LP__STR_PRE_MASK 0x00010000L +#define MC_SEQ_RD_CTL_D1_LP__STR_PRE__SHIFT 0x00000010 +#define MC_SEQ_RD_CTL_D1_LP__STR_PST_MASK 0x00020000L +#define MC_SEQ_RD_CTL_D1_LP__STR_PST__SHIFT 0x00000011 +#define MC_SEQ_RD_CTL_D1__RBS_DLY_MASK 0x01f00000L +#define MC_SEQ_RD_CTL_D1__RBS_DLY__SHIFT 0x00000014 +#define MC_SEQ_RD_CTL_D1__RBS_WEDC_DLY_MASK 0x3e000000L +#define MC_SEQ_RD_CTL_D1__RBS_WEDC_DLY__SHIFT 0x00000019 +#define MC_SEQ_RD_CTL_D1__RCV_DLY_MASK 0x00000007L +#define MC_SEQ_RD_CTL_D1__RCV_DLY__SHIFT 0x00000000 +#define MC_SEQ_RD_CTL_D1__RCV_EXT_MASK 0x000000f8L +#define MC_SEQ_RD_CTL_D1__RCV_EXT__SHIFT 0x00000003 +#define MC_SEQ_RD_CTL_D1__RST_HLD_MASK 0x0000f000L +#define MC_SEQ_RD_CTL_D1__RST_HLD__SHIFT 0x0000000c +#define MC_SEQ_RD_CTL_D1__RST_SEL_MASK 0x00000300L +#define MC_SEQ_RD_CTL_D1__RST_SEL__SHIFT 0x00000008 +#define MC_SEQ_RD_CTL_D1__RXDPWRON_DLY_MASK 0x00000c00L +#define MC_SEQ_RD_CTL_D1__RXDPWRON_DLY__SHIFT 0x0000000a +#define MC_SEQ_RD_CTL_D1__STR_PRE_MASK 0x00010000L +#define MC_SEQ_RD_CTL_D1__STR_PRE__SHIFT 0x00000010 +#define MC_SEQ_RD_CTL_D1__STR_PST_MASK 0x00020000L +#define MC_SEQ_RD_CTL_D1__STR_PST__SHIFT 0x00000011 +#define MC_SEQ_RESERVE_0_S__SCLK_FIELD_MASK 0xffffffffL +#define MC_SEQ_RESERVE_0_S__SCLK_FIELD__SHIFT 0x00000000 +#define MC_SEQ_RESERVE_1_S__SCLK_FIELD_MASK 0xffffffffL +#define MC_SEQ_RESERVE_1_S__SCLK_FIELD__SHIFT 0x00000000 +#define MC_SEQ_RESERVE_M__MCLK_FIELD_MASK 0xffffffffL +#define MC_SEQ_RESERVE_M__MCLK_FIELD__SHIFT 0x00000000 +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ0_MASK 0x0000000fL +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ0__SHIFT 0x00000000 +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ1_MASK 0x000000f0L +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ1__SHIFT 0x00000004 +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ2_MASK 0x00000f00L +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ2__SHIFT 0x00000008 +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ3_MASK 0x0000f000L +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ3__SHIFT 0x0000000c +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ4_MASK 0x000f0000L +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ4__SHIFT 0x00000010 +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ5_MASK 0x00f00000L +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ5__SHIFT 0x00000014 +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ6_MASK 0x0f000000L +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ6__SHIFT 0x00000018 +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ7_MASK 0xf0000000L +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ7__SHIFT 0x0000001c +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ0_MASK 0x0000000fL +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ0__SHIFT 0x00000000 +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ1_MASK 0x000000f0L +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ1__SHIFT 0x00000004 +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ2_MASK 0x00000f00L +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ2__SHIFT 0x00000008 +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ3_MASK 0x0000f000L +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ3__SHIFT 0x0000000c +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ4_MASK 0x000f0000L +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ4__SHIFT 0x00000010 +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ5_MASK 0x00f00000L +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ5__SHIFT 0x00000014 +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ6_MASK 0x0f000000L +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ6__SHIFT 0x00000018 +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ7_MASK 0xf0000000L +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ7__SHIFT 0x0000001c +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ0_MASK 0x0000000fL +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ0__SHIFT 0x00000000 +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ1_MASK 0x000000f0L +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ1__SHIFT 0x00000004 +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ2_MASK 0x00000f00L +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ2__SHIFT 0x00000008 +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ3_MASK 0x0000f000L +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ3__SHIFT 0x0000000c +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ4_MASK 0x000f0000L +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ4__SHIFT 0x00000010 +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ5_MASK 0x00f00000L +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ5__SHIFT 0x00000014 +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ6_MASK 0x0f000000L +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ6__SHIFT 0x00000018 +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ7_MASK 0xf0000000L +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ7__SHIFT 0x0000001c +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ0_MASK 0x0000000fL +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ0__SHIFT 0x00000000 +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ1_MASK 0x000000f0L +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ1__SHIFT 0x00000004 +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ2_MASK 0x00000f00L +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ2__SHIFT 0x00000008 +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ3_MASK 0x0000f000L +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ3__SHIFT 0x0000000c +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ4_MASK 0x000f0000L +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ4__SHIFT 0x00000010 +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ5_MASK 0x00f00000L +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ5__SHIFT 0x00000014 +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ6_MASK 0x0f000000L +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ6__SHIFT 0x00000018 +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ7_MASK 0xf0000000L +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ7__SHIFT 0x0000001c +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ0_MASK 0x0000000fL +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ0__SHIFT 0x00000000 +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ1_MASK 0x000000f0L +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ1__SHIFT 0x00000004 +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ2_MASK 0x00000f00L +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ2__SHIFT 0x00000008 +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ3_MASK 0x0000f000L +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ3__SHIFT 0x0000000c +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ4_MASK 0x000f0000L +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ4__SHIFT 0x00000010 +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ5_MASK 0x00f00000L +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ5__SHIFT 0x00000014 +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ6_MASK 0x0f000000L +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ6__SHIFT 0x00000018 +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ7_MASK 0xf0000000L +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ7__SHIFT 0x0000001c +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ0_MASK 0x0000000fL +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ0__SHIFT 0x00000000 +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ1_MASK 0x000000f0L +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ1__SHIFT 0x00000004 +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ2_MASK 0x00000f00L +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ2__SHIFT 0x00000008 +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ3_MASK 0x0000f000L +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ3__SHIFT 0x0000000c +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ4_MASK 0x000f0000L +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ4__SHIFT 0x00000010 +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ5_MASK 0x00f00000L +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ5__SHIFT 0x00000014 +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ6_MASK 0x0f000000L +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ6__SHIFT 0x00000018 +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ7_MASK 0xf0000000L +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ7__SHIFT 0x0000001c +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ0_MASK 0x0000000fL +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ0__SHIFT 0x00000000 +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ1_MASK 0x000000f0L +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ1__SHIFT 0x00000004 +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ2_MASK 0x00000f00L +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ2__SHIFT 0x00000008 +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ3_MASK 0x0000f000L +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ3__SHIFT 0x0000000c +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ4_MASK 0x000f0000L +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ4__SHIFT 0x00000010 +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ5_MASK 0x00f00000L +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ5__SHIFT 0x00000014 +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ6_MASK 0x0f000000L +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ6__SHIFT 0x00000018 +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ7_MASK 0xf0000000L +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ7__SHIFT 0x0000001c +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ0_MASK 0x0000000fL +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ0__SHIFT 0x00000000 +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ1_MASK 0x000000f0L +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ1__SHIFT 0x00000004 +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ2_MASK 0x00000f00L +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ2__SHIFT 0x00000008 +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ3_MASK 0x0000f000L +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ3__SHIFT 0x0000000c +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ4_MASK 0x000f0000L +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ4__SHIFT 0x00000010 +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ5_MASK 0x00f00000L +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ5__SHIFT 0x00000014 +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ6_MASK 0x0f000000L +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ6__SHIFT 0x00000018 +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ7_MASK 0xf0000000L +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ7__SHIFT 0x0000001c +#define MC_SEQ_RXFRAMING_DBI_D0__DBI0_MASK 0x0000000fL +#define MC_SEQ_RXFRAMING_DBI_D0__DBI0__SHIFT 0x00000000 +#define MC_SEQ_RXFRAMING_DBI_D0__DBI1_MASK 0x000000f0L +#define MC_SEQ_RXFRAMING_DBI_D0__DBI1__SHIFT 0x00000004 +#define MC_SEQ_RXFRAMING_DBI_D0__DBI2_MASK 0x00000f00L +#define MC_SEQ_RXFRAMING_DBI_D0__DBI2__SHIFT 0x00000008 +#define MC_SEQ_RXFRAMING_DBI_D0__DBI3_MASK 0x0000f000L +#define MC_SEQ_RXFRAMING_DBI_D0__DBI3__SHIFT 0x0000000c +#define MC_SEQ_RXFRAMING_DBI_D1__DBI0_MASK 0x0000000fL +#define MC_SEQ_RXFRAMING_DBI_D1__DBI0__SHIFT 0x00000000 +#define MC_SEQ_RXFRAMING_DBI_D1__DBI1_MASK 0x000000f0L +#define MC_SEQ_RXFRAMING_DBI_D1__DBI1__SHIFT 0x00000004 +#define MC_SEQ_RXFRAMING_DBI_D1__DBI2_MASK 0x00000f00L +#define MC_SEQ_RXFRAMING_DBI_D1__DBI2__SHIFT 0x00000008 +#define MC_SEQ_RXFRAMING_DBI_D1__DBI3_MASK 0x0000f000L +#define MC_SEQ_RXFRAMING_DBI_D1__DBI3__SHIFT 0x0000000c +#define MC_SEQ_RXFRAMING_EDC_D0__EDC0_MASK 0x0000000fL +#define MC_SEQ_RXFRAMING_EDC_D0__EDC0__SHIFT 0x00000000 +#define MC_SEQ_RXFRAMING_EDC_D0__EDC1_MASK 0x000000f0L +#define MC_SEQ_RXFRAMING_EDC_D0__EDC1__SHIFT 0x00000004 +#define MC_SEQ_RXFRAMING_EDC_D0__EDC2_MASK 0x00000f00L +#define MC_SEQ_RXFRAMING_EDC_D0__EDC2__SHIFT 0x00000008 +#define MC_SEQ_RXFRAMING_EDC_D0__EDC3_MASK 0x0000f000L +#define MC_SEQ_RXFRAMING_EDC_D0__EDC3__SHIFT 0x0000000c +#define MC_SEQ_RXFRAMING_EDC_D0__WCDR0_MASK 0x000f0000L +#define MC_SEQ_RXFRAMING_EDC_D0__WCDR0__SHIFT 0x00000010 +#define MC_SEQ_RXFRAMING_EDC_D0__WCDR1_MASK 0x00f00000L +#define MC_SEQ_RXFRAMING_EDC_D0__WCDR1__SHIFT 0x00000014 +#define MC_SEQ_RXFRAMING_EDC_D0__WCDR2_MASK 0x0f000000L +#define MC_SEQ_RXFRAMING_EDC_D0__WCDR2__SHIFT 0x00000018 +#define MC_SEQ_RXFRAMING_EDC_D0__WCDR3_MASK 0xf0000000L +#define MC_SEQ_RXFRAMING_EDC_D0__WCDR3__SHIFT 0x0000001c +#define MC_SEQ_RXFRAMING_EDC_D1__EDC0_MASK 0x0000000fL +#define MC_SEQ_RXFRAMING_EDC_D1__EDC0__SHIFT 0x00000000 +#define MC_SEQ_RXFRAMING_EDC_D1__EDC1_MASK 0x000000f0L +#define MC_SEQ_RXFRAMING_EDC_D1__EDC1__SHIFT 0x00000004 +#define MC_SEQ_RXFRAMING_EDC_D1__EDC2_MASK 0x00000f00L +#define MC_SEQ_RXFRAMING_EDC_D1__EDC2__SHIFT 0x00000008 +#define MC_SEQ_RXFRAMING_EDC_D1__EDC3_MASK 0x0000f000L +#define MC_SEQ_RXFRAMING_EDC_D1__EDC3__SHIFT 0x0000000c +#define MC_SEQ_RXFRAMING_EDC_D1__WCDR0_MASK 0x000f0000L +#define MC_SEQ_RXFRAMING_EDC_D1__WCDR0__SHIFT 0x00000010 +#define MC_SEQ_RXFRAMING_EDC_D1__WCDR1_MASK 0x00f00000L +#define MC_SEQ_RXFRAMING_EDC_D1__WCDR1__SHIFT 0x00000014 +#define MC_SEQ_RXFRAMING_EDC_D1__WCDR2_MASK 0x0f000000L +#define MC_SEQ_RXFRAMING_EDC_D1__WCDR2__SHIFT 0x00000018 +#define MC_SEQ_RXFRAMING_EDC_D1__WCDR3_MASK 0xf0000000L +#define MC_SEQ_RXFRAMING_EDC_D1__WCDR3__SHIFT 0x0000001c +#define MC_SEQ_STATUS_M__CMD_RDY_D0_MASK 0x00000004L +#define MC_SEQ_STATUS_M__CMD_RDY_D0__SHIFT 0x00000002 +#define MC_SEQ_STATUS_M__CMD_RDY_D1_MASK 0x00000008L +#define MC_SEQ_STATUS_M__CMD_RDY_D1__SHIFT 0x00000003 +#define MC_SEQ_STATUS_M__PMG_FSMSTATE_MASK 0x01f00000L +#define MC_SEQ_STATUS_M__PMG_FSMSTATE__SHIFT 0x00000014 +#define MC_SEQ_STATUS_M__PMG_PWRSTATE_MASK 0x00010000L +#define MC_SEQ_STATUS_M__PMG_PWRSTATE__SHIFT 0x00000010 +#define MC_SEQ_STATUS_M__PWRUP_COMPL_D0_MASK 0x00000001L +#define MC_SEQ_STATUS_M__PWRUP_COMPL_D0__SHIFT 0x00000000 +#define MC_SEQ_STATUS_M__PWRUP_COMPL_D1_MASK 0x00000002L +#define MC_SEQ_STATUS_M__PWRUP_COMPL_D1__SHIFT 0x00000001 +#define MC_SEQ_STATUS_M__SEQ0_ARB_CMD_FIFO_EMPTY_MASK 0x00000100L +#define MC_SEQ_STATUS_M__SEQ0_ARB_CMD_FIFO_EMPTY__SHIFT 0x00000008 +#define MC_SEQ_STATUS_M__SEQ0_BUSY_HYS_MASK 0x02000000L +#define MC_SEQ_STATUS_M__SEQ0_BUSY_HYS__SHIFT 0x00000019 +#define MC_SEQ_STATUS_M__SEQ0_BUSY_MASK 0x00004000L +#define MC_SEQ_STATUS_M__SEQ0_BUSY__SHIFT 0x0000000e +#define MC_SEQ_STATUS_M__SEQ0_RS_DATA_FIFO_FULL_MASK 0x00001000L +#define MC_SEQ_STATUS_M__SEQ0_RS_DATA_FIFO_FULL__SHIFT 0x0000000c +#define MC_SEQ_STATUS_M__SEQ1_ARB_CMD_FIFO_EMPTY_MASK 0x00000200L +#define MC_SEQ_STATUS_M__SEQ1_ARB_CMD_FIFO_EMPTY__SHIFT 0x00000009 +#define MC_SEQ_STATUS_M__SEQ1_BUSY_HYS_MASK 0x04000000L +#define MC_SEQ_STATUS_M__SEQ1_BUSY_HYS__SHIFT 0x0000001a +#define MC_SEQ_STATUS_M__SEQ1_BUSY_MASK 0x00008000L +#define MC_SEQ_STATUS_M__SEQ1_BUSY__SHIFT 0x0000000f +#define MC_SEQ_STATUS_M__SEQ1_RS_DATA_FIFO_FULL_MASK 0x00002000L +#define MC_SEQ_STATUS_M__SEQ1_RS_DATA_FIFO_FULL__SHIFT 0x0000000d +#define MC_SEQ_STATUS_M__SLF_D0_MASK 0x00000010L +#define MC_SEQ_STATUS_M__SLF_D0__SHIFT 0x00000004 +#define MC_SEQ_STATUS_M__SLF_D1_MASK 0x00000020L +#define MC_SEQ_STATUS_M__SLF_D1__SHIFT 0x00000005 +#define MC_SEQ_STATUS_M__SS_SLF_D0_MASK 0x00000040L +#define MC_SEQ_STATUS_M__SS_SLF_D0__SHIFT 0x00000006 +#define MC_SEQ_STATUS_M__SS_SLF_D1_MASK 0x00000080L +#define MC_SEQ_STATUS_M__SS_SLF_D1__SHIFT 0x00000007 +#define MC_SEQ_STATUS_S__SEQ0_ARB_CMD_FIFO_FULL_MASK 0x00000010L +#define MC_SEQ_STATUS_S__SEQ0_ARB_CMD_FIFO_FULL__SHIFT 0x00000004 +#define MC_SEQ_STATUS_S__SEQ0_ARB_DATA_FIFO_FULL_MASK 0x00000001L +#define MC_SEQ_STATUS_S__SEQ0_ARB_DATA_FIFO_FULL__SHIFT 0x00000000 +#define MC_SEQ_STATUS_S__SEQ0_RS_DATA_FIFO_EMPTY_MASK 0x00000100L +#define MC_SEQ_STATUS_S__SEQ0_RS_DATA_FIFO_EMPTY__SHIFT 0x00000008 +#define MC_SEQ_STATUS_S__SEQ1_ARB_CMD_FIFO_FULL_MASK 0x00000020L +#define MC_SEQ_STATUS_S__SEQ1_ARB_CMD_FIFO_FULL__SHIFT 0x00000005 +#define MC_SEQ_STATUS_S__SEQ1_ARB_DATA_FIFO_FULL_MASK 0x00000002L +#define MC_SEQ_STATUS_S__SEQ1_ARB_DATA_FIFO_FULL__SHIFT 0x00000001 +#define MC_SEQ_STATUS_S__SEQ1_RS_DATA_FIFO_EMPTY_MASK 0x00000200L +#define MC_SEQ_STATUS_S__SEQ1_RS_DATA_FIFO_EMPTY__SHIFT 0x00000009 +#define MC_SEQ_SUP_CNTL__BKPT_CLEAR_MASK 0x00000080L +#define MC_SEQ_SUP_CNTL__BKPT_CLEAR__SHIFT 0x00000007 +#define MC_SEQ_SUP_CNTL__FAST_WRITE_MASK 0x00000040L +#define MC_SEQ_SUP_CNTL__FAST_WRITE__SHIFT 0x00000006 +#define MC_SEQ_SUP_CNTL__PGM_CHKSUM_MASK 0xff800000L +#define MC_SEQ_SUP_CNTL__PGM_CHKSUM__SHIFT 0x00000017 +#define MC_SEQ_SUP_CNTL__PGM_READ_MASK 0x00000020L +#define MC_SEQ_SUP_CNTL__PGM_READ__SHIFT 0x00000005 +#define MC_SEQ_SUP_CNTL__PGM_WRITE_MASK 0x00000010L +#define MC_SEQ_SUP_CNTL__PGM_WRITE__SHIFT 0x00000004 +#define MC_SEQ_SUP_CNTL__RESET_PC_MASK 0x00000008L +#define MC_SEQ_SUP_CNTL__RESET_PC__SHIFT 0x00000003 +#define MC_SEQ_SUP_CNTL__RUN_MASK 0x00000001L +#define MC_SEQ_SUP_CNTL__RUN__SHIFT 0x00000000 +#define MC_SEQ_SUP_CNTL__SINGLE_STEP_MASK 0x00000002L +#define MC_SEQ_SUP_CNTL__SINGLE_STEP__SHIFT 0x00000001 +#define MC_SEQ_SUP_CNTL__SW_WAKE_MASK 0x00000004L +#define MC_SEQ_SUP_CNTL__SW_WAKE__SHIFT 0x00000002 +#define MC_SEQ_SUP_DEC_STAT__STATUS_MASK 0xffffffffL +#define MC_SEQ_SUP_DEC_STAT__STATUS__SHIFT 0x00000000 +#define MC_SEQ_SUP_GP0_STAT__STATUS_MASK 0xffffffffL +#define MC_SEQ_SUP_GP0_STAT__STATUS__SHIFT 0x00000000 +#define MC_SEQ_SUP_GP1_STAT__STATUS_MASK 0xffffffffL +#define MC_SEQ_SUP_GP1_STAT__STATUS__SHIFT 0x00000000 +#define MC_SEQ_SUP_GP2_STAT__STATUS_MASK 0xffffffffL +#define MC_SEQ_SUP_GP2_STAT__STATUS__SHIFT 0x00000000 +#define MC_SEQ_SUP_GP3_STAT__STATUS_MASK 0xffffffffL +#define MC_SEQ_SUP_GP3_STAT__STATUS__SHIFT 0x00000000 +#define MC_SEQ_SUP_IR_STAT__STATUS_MASK 0xffffffffL +#define MC_SEQ_SUP_IR_STAT__STATUS__SHIFT 0x00000000 +#define MC_SEQ_SUP_PGM__CNTL_MASK 0xffffffffL +#define MC_SEQ_SUP_PGM__CNTL__SHIFT 0x00000000 +#define MC_SEQ_SUP_PGM_STAT__STATUS_MASK 0xffffffffL +#define MC_SEQ_SUP_PGM_STAT__STATUS__SHIFT 0x00000000 +#define MC_SEQ_SUP_R_PGM__PGM_MASK 0xffffffffL +#define MC_SEQ_SUP_R_PGM__PGM__SHIFT 0x00000000 +#define MC_SEQ_TCG_CNTL__AREF_BOTH_MASK 0x04000000L +#define MC_SEQ_TCG_CNTL__AREF_BOTH__SHIFT 0x0000001a +#define MC_SEQ_TCG_CNTL__AREF_LAST_MASK 0x02000000L +#define MC_SEQ_TCG_CNTL__AREF_LAST__SHIFT 0x00000019 +#define MC_SEQ_TCG_CNTL__BURST_NUM_MASK 0x00380000L +#define MC_SEQ_TCG_CNTL__BURST_NUM__SHIFT 0x00000013 +#define MC_SEQ_TCG_CNTL__DATA_CNT_MASK 0x0000f000L +#define MC_SEQ_TCG_CNTL__DATA_CNT__SHIFT 0x0000000c +#define MC_SEQ_TCG_CNTL__DONE_MASK 0x80000000L +#define MC_SEQ_TCG_CNTL__DONE__SHIFT 0x0000001f +#define MC_SEQ_TCG_CNTL__ENABLE_D0_MASK 0x00000002L +#define MC_SEQ_TCG_CNTL__ENABLE_D0__SHIFT 0x00000001 +#define MC_SEQ_TCG_CNTL__ENABLE_D1_MASK 0x00000004L +#define MC_SEQ_TCG_CNTL__ENABLE_D1__SHIFT 0x00000002 +#define MC_SEQ_TCG_CNTL__FRAME_TRAIN_MASK 0x00040000L +#define MC_SEQ_TCG_CNTL__FRAME_TRAIN__SHIFT 0x00000012 +#define MC_SEQ_TCG_CNTL__INFINITE_CMD_MASK 0x00000080L +#define MC_SEQ_TCG_CNTL__INFINITE_CMD__SHIFT 0x00000007 +#define MC_SEQ_TCG_CNTL__ISSUE_AREF_MASK 0x00400000L +#define MC_SEQ_TCG_CNTL__ISSUE_AREF__SHIFT 0x00000016 +#define MC_SEQ_TCG_CNTL__LOAD_FIFO_MASK 0x00010000L +#define MC_SEQ_TCG_CNTL__LOAD_FIFO__SHIFT 0x00000010 +#define MC_SEQ_TCG_CNTL__MOP_MASK 0x00000f00L +#define MC_SEQ_TCG_CNTL__MOP__SHIFT 0x00000008 +#define MC_SEQ_TCG_CNTL__NFIFO_MASK 0x00000070L +#define MC_SEQ_TCG_CNTL__NFIFO__SHIFT 0x00000004 +#define MC_SEQ_TCG_CNTL__RESET_MASK 0x00000001L +#define MC_SEQ_TCG_CNTL__RESET__SHIFT 0x00000000 +#define MC_SEQ_TCG_CNTL__SHORT_LDFF_MASK 0x00020000L +#define MC_SEQ_TCG_CNTL__SHORT_LDFF__SHIFT 0x00000011 +#define MC_SEQ_TCG_CNTL__START_MASK 0x00000008L +#define MC_SEQ_TCG_CNTL__START__SHIFT 0x00000003 +#define MC_SEQ_TCG_CNTL__TXDBI_CNTL_MASK 0x00800000L +#define MC_SEQ_TCG_CNTL__TXDBI_CNTL__SHIFT 0x00000017 +#define MC_SEQ_TCG_CNTL__VPTR_MASK_MASK 0x01000000L +#define MC_SEQ_TCG_CNTL__VPTR_MASK__SHIFT 0x00000018 +#define MC_SEQ_TIMER_RD__COUNTER_MASK 0xffffffffL +#define MC_SEQ_TIMER_RD__COUNTER__SHIFT 0x00000000 +#define MC_SEQ_TIMER_WR__COUNTER_MASK 0xffffffffL +#define MC_SEQ_TIMER_WR__COUNTER__SHIFT 0x00000000 +#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP0_WAKEUP_MASK 0x00040000L +#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP0_WAKEUP__SHIFT 0x00000012 +#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP1_WAKEUP_MASK 0x00080000L +#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP1_WAKEUP__SHIFT 0x00000013 +#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB0_WAKEUP_MASK 0x00200000L +#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB0_WAKEUP__SHIFT 0x00000015 +#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB1_WAKEUP_MASK 0x00400000L +#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB1_WAKEUP__SHIFT 0x00000016 +#define MC_SEQ_TRAIN_CAPTURE__D0_ARF_WAKEUP_MASK 0x00000001L +#define MC_SEQ_TRAIN_CAPTURE__D0_ARF_WAKEUP__SHIFT 0x00000000 +#define MC_SEQ_TRAIN_CAPTURE__D0_CMD_FIFO_READY_WAKEUP_MASK 0x00000100L +#define MC_SEQ_TRAIN_CAPTURE__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x00000008 +#define MC_SEQ_TRAIN_CAPTURE__D0_DATA_FIFO_READY_WAKEUP_MASK 0x00000400L +#define MC_SEQ_TRAIN_CAPTURE__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0x0000000a +#define MC_SEQ_TRAIN_CAPTURE__D0_IDLEH_WAKEUP_MASK 0x01000000L +#define MC_SEQ_TRAIN_CAPTURE__D0_IDLEH_WAKEUP__SHIFT 0x00000018 +#define MC_SEQ_TRAIN_CAPTURE__D0_REDC_WAKEUP_MASK 0x00000004L +#define MC_SEQ_TRAIN_CAPTURE__D0_REDC_WAKEUP__SHIFT 0x00000002 +#define MC_SEQ_TRAIN_CAPTURE__D0_WEDC_WAKEUP_MASK 0x00000010L +#define MC_SEQ_TRAIN_CAPTURE__D0_WEDC_WAKEUP__SHIFT 0x00000004 +#define MC_SEQ_TRAIN_CAPTURE__D1_ARF_WAKEUP_MASK 0x00000002L +#define MC_SEQ_TRAIN_CAPTURE__D1_ARF_WAKEUP__SHIFT 0x00000001 +#define MC_SEQ_TRAIN_CAPTURE__D1_CMD_FIFO_READY_WAKEUP_MASK 0x00000200L +#define MC_SEQ_TRAIN_CAPTURE__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x00000009 +#define MC_SEQ_TRAIN_CAPTURE__D1_DATA_FIFO_READY_WAKEUP_MASK 0x00000800L +#define MC_SEQ_TRAIN_CAPTURE__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0x0000000b +#define MC_SEQ_TRAIN_CAPTURE__D1_IDLEH_WAKEUP_MASK 0x02000000L +#define MC_SEQ_TRAIN_CAPTURE__D1_IDLEH_WAKEUP__SHIFT 0x00000019 +#define MC_SEQ_TRAIN_CAPTURE__D1_REDC_WAKEUP_MASK 0x00000008L +#define MC_SEQ_TRAIN_CAPTURE__D1_REDC_WAKEUP__SHIFT 0x00000003 +#define MC_SEQ_TRAIN_CAPTURE__D1_WEDC_WAKEUP_MASK 0x00000020L +#define MC_SEQ_TRAIN_CAPTURE__D1_WEDC_WAKEUP__SHIFT 0x00000005 +#define MC_SEQ_TRAIN_CAPTURE__DPM_LPT_WAKEUP_MASK 0x00800000L +#define MC_SEQ_TRAIN_CAPTURE__DPM_LPT_WAKEUP__SHIFT 0x00000017 +#define MC_SEQ_TRAIN_CAPTURE__DPM_WAKEUP_MASK 0x00100000L +#define MC_SEQ_TRAIN_CAPTURE__DPM_WAKEUP__SHIFT 0x00000014 +#define MC_SEQ_TRAIN_CAPTURE__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x00000040L +#define MC_SEQ_TRAIN_CAPTURE__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x00000006 +#define MC_SEQ_TRAIN_CAPTURE__PHY_PG_WAKEUP_MASK 0x04000000L +#define MC_SEQ_TRAIN_CAPTURE__PHY_PG_WAKEUP__SHIFT 0x0000001a +#define MC_SEQ_TRAIN_CAPTURE__RESERVE0_WAKEUP_MASK 0x00002000L +#define MC_SEQ_TRAIN_CAPTURE__RESERVE0_WAKEUP__SHIFT 0x0000000d +#define MC_SEQ_TRAIN_CAPTURE__SCLK_SRBM_READY_WAKEUP_MASK 0x00000080L +#define MC_SEQ_TRAIN_CAPTURE__SCLK_SRBM_READY_WAKEUP__SHIFT 0x00000007 +#define MC_SEQ_TRAIN_CAPTURE__SOFTWARE_WAKEUP_WAKEUP_MASK 0x00001000L +#define MC_SEQ_TRAIN_CAPTURE__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0x0000000c +#define MC_SEQ_TRAIN_CAPTURE__TCG_DONE_WAKEUP_MASK 0x00020000L +#define MC_SEQ_TRAIN_CAPTURE__TCG_DONE_WAKEUP__SHIFT 0x00000011 +#define MC_SEQ_TRAIN_CAPTURE__TIMER_DONE_WAKEUP_MASK 0x00008000L +#define MC_SEQ_TRAIN_CAPTURE__TIMER_DONE_WAKEUP__SHIFT 0x0000000f +#define MC_SEQ_TRAIN_CAPTURE__TSM_DONE_WAKEUP_MASK 0x00004000L +#define MC_SEQ_TRAIN_CAPTURE__TSM_DONE_WAKEUP__SHIFT 0x0000000e +#define MC_SEQ_TRAIN_EDC_THRESHOLD2__THRESHOLD_PERIOD_MASK 0xffffffffL +#define MC_SEQ_TRAIN_EDC_THRESHOLD2__THRESHOLD_PERIOD__SHIFT 0x00000000 +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_IN_PROGRESS_MASK 0x00000100L +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_IN_PROGRESS__SHIFT 0x00000008 +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_STATUS_MASK 0x00000001L +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_STATUS__SHIFT 0x00000000 +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_IN_PROGRESS_MASK 0x00000200L +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_IN_PROGRESS__SHIFT 0x00000009 +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_STATUS_MASK 0x00000002L +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_STATUS__SHIFT 0x00000001 +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CLEAR_RETRAIN_STATUS_MASK 0x00000004L +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CLEAR_RETRAIN_STATUS__SHIFT 0x00000002 +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_MONITOR_MASK 0x00000030L +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_MONITOR__SHIFT 0x00000004 +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_VBI_MASK 0x00000008L +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_VBI__SHIFT 0x00000003 +#define MC_SEQ_TRAIN_EDC_THRESHOLD__READ_EDC_THRESHOLD_MASK 0xffff0000L +#define MC_SEQ_TRAIN_EDC_THRESHOLD__READ_EDC_THRESHOLD__SHIFT 0x00000010 +#define MC_SEQ_TRAIN_EDC_THRESHOLD__WRITE_EDC_THRESHOLD_MASK 0x0000ffffL +#define MC_SEQ_TRAIN_EDC_THRESHOLD__WRITE_EDC_THRESHOLD__SHIFT 0x00000000 +#define MC_SEQ_TRAIN_TIMING__TARF2T_MASK 0x000003e0L +#define MC_SEQ_TRAIN_TIMING__TARF2T__SHIFT 0x00000005 +#define MC_SEQ_TRAIN_TIMING__TLD2LD_MASK 0x000f8000L +#define MC_SEQ_TRAIN_TIMING__TLD2LD__SHIFT 0x0000000f +#define MC_SEQ_TRAIN_TIMING__TT2ROW_MASK 0x00007c00L +#define MC_SEQ_TRAIN_TIMING__TT2ROW__SHIFT 0x0000000a +#define MC_SEQ_TRAIN_TIMING__TWT2RT_MASK 0x0000001fL +#define MC_SEQ_TRAIN_TIMING__TWT2RT__SHIFT 0x00000000 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP0_WAKEUP_MASK 0x00040000L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP0_WAKEUP__SHIFT 0x00000012 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP1_WAKEUP_MASK 0x00080000L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP1_WAKEUP__SHIFT 0x00000013 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB0_WAKEUP_MASK 0x00200000L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB0_WAKEUP__SHIFT 0x00000015 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB1_WAKEUP_MASK 0x00400000L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB1_WAKEUP__SHIFT 0x00000016 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__CLEARALL_MASK 0x00010000L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__CLEARALL__SHIFT 0x00000010 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_ARF_WAKEUP_MASK 0x00000001L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_ARF_WAKEUP__SHIFT 0x00000000 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_CMD_FIFO_READY_WAKEUP_MASK 0x00000100L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x00000008 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_DATA_FIFO_READY_WAKEUP_MASK 0x00000400L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0x0000000a +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_IDLEH_WAKEUP_MASK 0x01000000L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_IDLEH_WAKEUP__SHIFT 0x00000018 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_REDC_WAKEUP_MASK 0x00000004L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_REDC_WAKEUP__SHIFT 0x00000002 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_WEDC_WAKEUP_MASK 0x00000010L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_WEDC_WAKEUP__SHIFT 0x00000004 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_ARF_WAKEUP_MASK 0x00000002L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_ARF_WAKEUP__SHIFT 0x00000001 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_CMD_FIFO_READY_WAKEUP_MASK 0x00000200L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x00000009 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_DATA_FIFO_READY_WAKEUP_MASK 0x00000800L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0x0000000b +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_IDLEH_WAKEUP_MASK 0x02000000L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_IDLEH_WAKEUP__SHIFT 0x00000019 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_REDC_WAKEUP_MASK 0x00000008L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_REDC_WAKEUP__SHIFT 0x00000003 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_WEDC_WAKEUP_MASK 0x00000020L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_WEDC_WAKEUP__SHIFT 0x00000005 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_LPT_WAKEUP_MASK 0x00800000L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_LPT_WAKEUP__SHIFT 0x00000017 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_WAKEUP_MASK 0x00100000L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_WAKEUP__SHIFT 0x00000014 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x00000040L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x00000006 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__PHY_PG_WAKEUP_MASK 0x04000000L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__PHY_PG_WAKEUP__SHIFT 0x0000001a +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__RESERVE0_WAKEUP_MASK 0x00002000L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__RESERVE0_WAKEUP__SHIFT 0x0000000d +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SCLK_SRBM_READY_WAKEUP_MASK 0x00000080L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SCLK_SRBM_READY_WAKEUP__SHIFT 0x00000007 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SOFTWARE_WAKEUP_WAKEUP_MASK 0x00001000L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0x0000000c +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TCG_DONE_WAKEUP_MASK 0x00020000L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TCG_DONE_WAKEUP__SHIFT 0x00000011 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TIMER_DONE_WAKEUP_MASK 0x00008000L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TIMER_DONE_WAKEUP__SHIFT 0x0000000f +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TSM_DONE_WAKEUP_MASK 0x00004000L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TSM_DONE_WAKEUP__SHIFT 0x0000000e +#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_ADDR_TRAIN_MASK 0x00000100L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_ADDR_TRAIN__SHIFT 0x00000008 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_READ_TRAIN_MASK 0x00000400L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_READ_TRAIN__SHIFT 0x0000000a +#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WAKEUP_EARLY_MASK 0x00100000L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WAKEUP_EARLY__SHIFT 0x00000014 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WCK_TRAIN_MASK 0x00000200L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WCK_TRAIN__SHIFT 0x00000009 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WRITE_TRAIN_MASK 0x00000800L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WRITE_TRAIN__SHIFT 0x0000000b +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D0_MASK 0x01000000L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D0__SHIFT 0x00000018 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D1_MASK 0x04000000L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D1__SHIFT 0x0000001a +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D0_MASK 0x02000000L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D0__SHIFT 0x00000019 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D1_MASK 0x08000000L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D1__SHIFT 0x0000001b +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_ADDR_TRAIN_MASK 0x00000001L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_ADDR_TRAIN__SHIFT 0x00000000 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_READ_TRAIN_MASK 0x00000004L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_READ_TRAIN__SHIFT 0x00000002 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WCK_TRAIN_MASK 0x00000002L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WCK_TRAIN__SHIFT 0x00000001 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WRITE_TRAIN_MASK 0x00000008L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WRITE_TRAIN__SHIFT 0x00000003 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__DISP_ASTOP_WAKEUP_MASK 0x20000000L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__DISP_ASTOP_WAKEUP__SHIFT 0x0000001d +#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_ADDR_TRAIN_MASK 0x00010000L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_ADDR_TRAIN__SHIFT 0x00000010 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_READ_TRAIN_MASK 0x00040000L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_READ_TRAIN__SHIFT 0x00000012 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WCK_TRAIN_MASK 0x00020000L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WCK_TRAIN__SHIFT 0x00000011 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WRITE_TRAIN_MASK 0x00080000L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WRITE_TRAIN__SHIFT 0x00000013 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_ADDR_TRAIN_MASK 0x00000010L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_ADDR_TRAIN__SHIFT 0x00000004 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_READ_TRAIN_MASK 0x00000040L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_READ_TRAIN__SHIFT 0x00000006 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WCK_TRAIN_MASK 0x00000020L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WCK_TRAIN__SHIFT 0x00000005 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WRITE_TRAIN_MASK 0x00000080L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WRITE_TRAIN__SHIFT 0x00000007 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D0_MASK 0x00200000L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D0__SHIFT 0x00000015 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D1_MASK 0x00400000L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D1__SHIFT 0x00000016 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__SW_WAKEUP_MASK 0x10000000L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__SW_WAKEUP__SHIFT 0x0000001c +#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK 0x40000000L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0__SHIFT 0x0000001e +#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK 0x80000000L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1__SHIFT 0x0000001f +#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_ADDR_TRAIN_MASK 0x00001000L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_ADDR_TRAIN__SHIFT 0x0000000c +#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_READ_TRAIN_MASK 0x00004000L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_READ_TRAIN__SHIFT 0x0000000e +#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WCK_TRAIN_MASK 0x00002000L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WCK_TRAIN__SHIFT 0x0000000d +#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WRITE_TRAIN_MASK 0x00008000L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WRITE_TRAIN__SHIFT 0x0000000f +#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP0_WAKEUP_MASK 0x00040000L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP0_WAKEUP__SHIFT 0x00000012 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP1_WAKEUP_MASK 0x00080000L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP1_WAKEUP__SHIFT 0x00000013 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB0_WAKEUP_MASK 0x00200000L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB0_WAKEUP__SHIFT 0x00000015 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB1_WAKEUP_MASK 0x00400000L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB1_WAKEUP__SHIFT 0x00000016 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_ARF_WAKEUP_MASK 0x00000001L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_ARF_WAKEUP__SHIFT 0x00000000 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_CMD_FIFO_READY_WAKEUP_MASK 0x00000100L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x00000008 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_DATA_FIFO_READY_WAKEUP_MASK 0x00000400L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0x0000000a +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_IDLEH_WAKEUP_MASK 0x01000000L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_IDLEH_WAKEUP__SHIFT 0x00000018 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_REDC_WAKEUP_MASK 0x00000004L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_REDC_WAKEUP__SHIFT 0x00000002 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_WEDC_WAKEUP_MASK 0x00000010L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_WEDC_WAKEUP__SHIFT 0x00000004 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_ARF_WAKEUP_MASK 0x00000002L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_ARF_WAKEUP__SHIFT 0x00000001 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_CMD_FIFO_READY_WAKEUP_MASK 0x00000200L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x00000009 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_DATA_FIFO_READY_WAKEUP_MASK 0x00000800L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0x0000000b +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_IDLEH_WAKEUP_MASK 0x02000000L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_IDLEH_WAKEUP__SHIFT 0x00000019 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_REDC_WAKEUP_MASK 0x00000008L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_REDC_WAKEUP__SHIFT 0x00000003 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_WEDC_WAKEUP_MASK 0x00000020L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_WEDC_WAKEUP__SHIFT 0x00000005 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_LPT_WAKEUP_MASK 0x00800000L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_LPT_WAKEUP__SHIFT 0x00000017 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_WAKEUP_MASK 0x00100000L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_WAKEUP__SHIFT 0x00000014 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x00000040L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x00000006 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__PHY_PG_WAKEUP_MASK 0x04000000L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__PHY_PG_WAKEUP__SHIFT 0x0000001a +#define MC_SEQ_TRAIN_WAKEUP_EDGE__RESERVE0_WAKEUP_MASK 0x00002000L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__RESERVE0_WAKEUP__SHIFT 0x0000000d +#define MC_SEQ_TRAIN_WAKEUP_EDGE__SCLK_SRBM_READY_WAKEUP_MASK 0x00000080L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__SCLK_SRBM_READY_WAKEUP__SHIFT 0x00000007 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__SOFTWARE_WAKEUP_WAKEUP_MASK 0x00001000L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0x0000000c +#define MC_SEQ_TRAIN_WAKEUP_EDGE__TCG_DONE_WAKEUP_MASK 0x00020000L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__TCG_DONE_WAKEUP__SHIFT 0x00000011 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__TIMER_DONE_WAKEUP_MASK 0x00008000L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__TIMER_DONE_WAKEUP__SHIFT 0x0000000f +#define MC_SEQ_TRAIN_WAKEUP_EDGE__TSM_DONE_WAKEUP_MASK 0x00004000L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__TSM_DONE_WAKEUP__SHIFT 0x0000000e +#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP0_WAKEUP_MASK 0x00040000L +#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP0_WAKEUP__SHIFT 0x00000012 +#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP1_WAKEUP_MASK 0x00080000L +#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP1_WAKEUP__SHIFT 0x00000013 +#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB0_WAKEUP_MASK 0x00200000L +#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB0_WAKEUP__SHIFT 0x00000015 +#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB1_WAKEUP_MASK 0x00400000L +#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB1_WAKEUP__SHIFT 0x00000016 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_ARF_WAKEUP_MASK 0x00000001L +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_ARF_WAKEUP__SHIFT 0x00000000 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_CMD_FIFO_READY_WAKEUP_MASK 0x00000100L +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x00000008 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_DATA_FIFO_READY_WAKEUP_MASK 0x00000400L +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0x0000000a +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_IDLEH_WAKEUP_MASK 0x01000000L +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_IDLEH_WAKEUP__SHIFT 0x00000018 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_REDC_WAKEUP_MASK 0x00000004L +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_REDC_WAKEUP__SHIFT 0x00000002 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_WEDC_WAKEUP_MASK 0x00000010L +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_WEDC_WAKEUP__SHIFT 0x00000004 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_ARF_WAKEUP_MASK 0x00000002L +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_ARF_WAKEUP__SHIFT 0x00000001 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_CMD_FIFO_READY_WAKEUP_MASK 0x00000200L +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x00000009 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_DATA_FIFO_READY_WAKEUP_MASK 0x00000800L +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0x0000000b +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_IDLEH_WAKEUP_MASK 0x02000000L +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_IDLEH_WAKEUP__SHIFT 0x00000019 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_REDC_WAKEUP_MASK 0x00000008L +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_REDC_WAKEUP__SHIFT 0x00000003 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_WEDC_WAKEUP_MASK 0x00000020L +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_WEDC_WAKEUP__SHIFT 0x00000005 +#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_LPT_WAKEUP_MASK 0x00800000L +#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_LPT_WAKEUP__SHIFT 0x00000017 +#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_WAKEUP_MASK 0x00100000L +#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_WAKEUP__SHIFT 0x00000014 +#define MC_SEQ_TRAIN_WAKEUP_MASK__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x00000040L +#define MC_SEQ_TRAIN_WAKEUP_MASK__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x00000006 +#define MC_SEQ_TRAIN_WAKEUP_MASK__PHY_PG_WAKEUP_MASK 0x04000000L +#define MC_SEQ_TRAIN_WAKEUP_MASK__PHY_PG_WAKEUP__SHIFT 0x0000001a +#define MC_SEQ_TRAIN_WAKEUP_MASK__RESERVE0_WAKEUP_MASK 0x00002000L +#define MC_SEQ_TRAIN_WAKEUP_MASK__RESERVE0_WAKEUP__SHIFT 0x0000000d +#define MC_SEQ_TRAIN_WAKEUP_MASK__SCLK_SRBM_READY_WAKEUP_MASK 0x00000080L +#define MC_SEQ_TRAIN_WAKEUP_MASK__SCLK_SRBM_READY_WAKEUP__SHIFT 0x00000007 +#define MC_SEQ_TRAIN_WAKEUP_MASK__SOFTWARE_WAKEUP_WAKEUP_MASK 0x00001000L +#define MC_SEQ_TRAIN_WAKEUP_MASK__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0x0000000c +#define MC_SEQ_TRAIN_WAKEUP_MASK__TCG_DONE_WAKEUP_MASK 0x00020000L +#define MC_SEQ_TRAIN_WAKEUP_MASK__TCG_DONE_WAKEUP__SHIFT 0x00000011 +#define MC_SEQ_TRAIN_WAKEUP_MASK__TIMER_DONE_WAKEUP_MASK 0x00008000L +#define MC_SEQ_TRAIN_WAKEUP_MASK__TIMER_DONE_WAKEUP__SHIFT 0x0000000f +#define MC_SEQ_TRAIN_WAKEUP_MASK__TSM_DONE_WAKEUP_MASK 0x00004000L +#define MC_SEQ_TRAIN_WAKEUP_MASK__TSM_DONE_WAKEUP__SHIFT 0x0000000e +#define MC_SEQ_TSM_BCNT__BCNT_TESTS_MASK 0x0000ff00L +#define MC_SEQ_TSM_BCNT__BCNT_TESTS__SHIFT 0x00000008 +#define MC_SEQ_TSM_BCNT__COMP_VALUE_MASK 0x00ff0000L +#define MC_SEQ_TSM_BCNT__COMP_VALUE__SHIFT 0x00000010 +#define MC_SEQ_TSM_BCNT__DONE_TESTS_MASK 0xff000000L +#define MC_SEQ_TSM_BCNT__DONE_TESTS__SHIFT 0x00000018 +#define MC_SEQ_TSM_BCNT__FALSE_ACT_MASK 0x000000f0L +#define MC_SEQ_TSM_BCNT__FALSE_ACT__SHIFT 0x00000004 +#define MC_SEQ_TSM_BCNT__TRUE_ACT_MASK 0x0000000fL +#define MC_SEQ_TSM_BCNT__TRUE_ACT__SHIFT 0x00000000 +#define MC_SEQ_TSM_CTRL__CAPTURE_START_MASK 0x00000002L +#define MC_SEQ_TSM_CTRL__CAPTURE_START__SHIFT 0x00000001 +#define MC_SEQ_TSM_CTRL__DIRECTION_MASK 0x00000020L +#define MC_SEQ_TSM_CTRL__DIRECTION__SHIFT 0x00000005 +#define MC_SEQ_TSM_CTRL__DONE_MASK 0x00000004L +#define MC_SEQ_TSM_CTRL__DONE__SHIFT 0x00000002 +#define MC_SEQ_TSM_CTRL__ERR_MASK 0x00000008L +#define MC_SEQ_TSM_CTRL__ERR__SHIFT 0x00000003 +#define MC_SEQ_TSM_CTRL__INVERT_MASK 0x00000040L +#define MC_SEQ_TSM_CTRL__INVERT__SHIFT 0x00000006 +#define MC_SEQ_TSM_CTRL__MASK_BITS_MASK 0x00000080L +#define MC_SEQ_TSM_CTRL__MASK_BITS__SHIFT 0x00000007 +#define MC_SEQ_TSM_CTRL__POINTER_MASK 0xffff0000L +#define MC_SEQ_TSM_CTRL__POINTER__SHIFT 0x00000010 +#define MC_SEQ_TSM_CTRL__ROT_INV_MASK 0x00000400L +#define MC_SEQ_TSM_CTRL__ROT_INV__SHIFT 0x0000000a +#define MC_SEQ_TSM_CTRL__START_MASK 0x00000001L +#define MC_SEQ_TSM_CTRL__START__SHIFT 0x00000000 +#define MC_SEQ_TSM_CTRL__STEP_MASK 0x00000010L +#define MC_SEQ_TSM_CTRL__STEP__SHIFT 0x00000004 +#define MC_SEQ_TSM_CTRL__UPDATE_LOOP_MASK 0x00000300L +#define MC_SEQ_TSM_CTRL__UPDATE_LOOP__SHIFT 0x00000008 +#define MC_SEQ_TSM_DBI__DBI_MASK 0xffffffffL +#define MC_SEQ_TSM_DBI__DBI__SHIFT 0x00000000 +#define MC_SEQ_TSM_DEBUG_DATA__TSM_DEBUG_DATA_MASK 0xffffffffL +#define MC_SEQ_TSM_DEBUG_DATA__TSM_DEBUG_DATA__SHIFT 0x00000000 +#define MC_SEQ_TSM_DEBUG_INDEX__TSM_DEBUG_INDEX_MASK 0x0000001fL +#define MC_SEQ_TSM_DEBUG_INDEX__TSM_DEBUG_INDEX__SHIFT 0x00000000 +#define MC_SEQ_TSM_EDC__EDC_MASK 0xffffffffL +#define MC_SEQ_TSM_EDC__EDC__SHIFT 0x00000000 +#define MC_SEQ_TSM_FLAG__ERROR_TESTS_MASK 0xff000000L +#define MC_SEQ_TSM_FLAG__ERROR_TESTS__SHIFT 0x00000018 +#define MC_SEQ_TSM_FLAG__FALSE_ACT_MASK 0x000000f0L +#define MC_SEQ_TSM_FLAG__FALSE_ACT__SHIFT 0x00000004 +#define MC_SEQ_TSM_FLAG__FLAG_TESTS_MASK 0x0000ff00L +#define MC_SEQ_TSM_FLAG__FLAG_TESTS__SHIFT 0x00000008 +#define MC_SEQ_TSM_FLAG__NBBL_MASK_MASK 0x000f0000L +#define MC_SEQ_TSM_FLAG__NBBL_MASK__SHIFT 0x00000010 +#define MC_SEQ_TSM_FLAG__TRUE_ACT_MASK 0x0000000fL +#define MC_SEQ_TSM_FLAG__TRUE_ACT__SHIFT 0x00000000 +#define MC_SEQ_TSM_GCNT__COMP_VALUE_MASK 0xffff0000L +#define MC_SEQ_TSM_GCNT__COMP_VALUE__SHIFT 0x00000010 +#define MC_SEQ_TSM_GCNT__FALSE_ACT_MASK 0x000000f0L +#define MC_SEQ_TSM_GCNT__FALSE_ACT__SHIFT 0x00000004 +#define MC_SEQ_TSM_GCNT__TESTS_MASK 0x0000ff00L +#define MC_SEQ_TSM_GCNT__TESTS__SHIFT 0x00000008 +#define MC_SEQ_TSM_GCNT__TRUE_ACT_MASK 0x0000000fL +#define MC_SEQ_TSM_GCNT__TRUE_ACT__SHIFT 0x00000000 +#define MC_SEQ_TSM_MISC__WCDR_MASK_MASK 0x000f0000L +#define MC_SEQ_TSM_MISC__WCDR_MASK__SHIFT 0x00000010 +#define MC_SEQ_TSM_MISC__WCDR_PTR_MASK 0x0000ffffL +#define MC_SEQ_TSM_MISC__WCDR_PTR__SHIFT 0x00000000 +#define MC_SEQ_TSM_NCNT__FALSE_ACT_MASK 0x000000f0L +#define MC_SEQ_TSM_NCNT__FALSE_ACT__SHIFT 0x00000004 +#define MC_SEQ_TSM_NCNT__NIBBLE_SKIP_MASK 0x0f000000L +#define MC_SEQ_TSM_NCNT__NIBBLE_SKIP__SHIFT 0x00000018 +#define MC_SEQ_TSM_NCNT__RANGE_HIGH_MASK 0x00f00000L +#define MC_SEQ_TSM_NCNT__RANGE_HIGH__SHIFT 0x00000014 +#define MC_SEQ_TSM_NCNT__RANGE_LOW_MASK 0x000f0000L +#define MC_SEQ_TSM_NCNT__RANGE_LOW__SHIFT 0x00000010 +#define MC_SEQ_TSM_NCNT__TESTS_MASK 0x0000ff00L +#define MC_SEQ_TSM_NCNT__TESTS__SHIFT 0x00000008 +#define MC_SEQ_TSM_NCNT__TRUE_ACT_MASK 0x0000000fL +#define MC_SEQ_TSM_NCNT__TRUE_ACT__SHIFT 0x00000000 +#define MC_SEQ_TSM_OCNT__CMP_VALUE_MASK 0xffff0000L +#define MC_SEQ_TSM_OCNT__CMP_VALUE__SHIFT 0x00000010 +#define MC_SEQ_TSM_OCNT__FALSE_ACT_MASK 0x000000f0L +#define MC_SEQ_TSM_OCNT__FALSE_ACT__SHIFT 0x00000004 +#define MC_SEQ_TSM_OCNT__TESTS_MASK 0x0000ff00L +#define MC_SEQ_TSM_OCNT__TESTS__SHIFT 0x00000008 +#define MC_SEQ_TSM_OCNT__TRUE_ACT_MASK 0x0000000fL +#define MC_SEQ_TSM_OCNT__TRUE_ACT__SHIFT 0x00000000 +#define MC_SEQ_TSM_UPDATE__AREF_COUNT_MASK 0x00ff0000L +#define MC_SEQ_TSM_UPDATE__AREF_COUNT__SHIFT 0x00000010 +#define MC_SEQ_TSM_UPDATE__CAPTR_TESTS_MASK 0xff000000L +#define MC_SEQ_TSM_UPDATE__CAPTR_TESTS__SHIFT 0x00000018 +#define MC_SEQ_TSM_UPDATE__FALSE_ACT_MASK 0x000000f0L +#define MC_SEQ_TSM_UPDATE__FALSE_ACT__SHIFT 0x00000004 +#define MC_SEQ_TSM_UPDATE__TRUE_ACT_MASK 0x0000000fL +#define MC_SEQ_TSM_UPDATE__TRUE_ACT__SHIFT 0x00000000 +#define MC_SEQ_TSM_UPDATE__UPDT_TESTS_MASK 0x0000ff00L +#define MC_SEQ_TSM_UPDATE__UPDT_TESTS__SHIFT 0x00000008 +#define MC_SEQ_TSM_WCDR__WCDR_MASK 0xffffffffL +#define MC_SEQ_TSM_WCDR__WCDR__SHIFT 0x00000000 +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ0_MASK 0x0000000fL +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ0__SHIFT 0x00000000 +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ1_MASK 0x000000f0L +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ1__SHIFT 0x00000004 +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ2_MASK 0x00000f00L +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ2__SHIFT 0x00000008 +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ3_MASK 0x0000f000L +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ3__SHIFT 0x0000000c +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ4_MASK 0x000f0000L +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ4__SHIFT 0x00000010 +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ5_MASK 0x00f00000L +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ5__SHIFT 0x00000014 +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ6_MASK 0x0f000000L +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ6__SHIFT 0x00000018 +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ7_MASK 0xf0000000L +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ7__SHIFT 0x0000001c +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ0_MASK 0x0000000fL +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ0__SHIFT 0x00000000 +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ1_MASK 0x000000f0L +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ1__SHIFT 0x00000004 +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ2_MASK 0x00000f00L +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ2__SHIFT 0x00000008 +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ3_MASK 0x0000f000L +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ3__SHIFT 0x0000000c +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ4_MASK 0x000f0000L +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ4__SHIFT 0x00000010 +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ5_MASK 0x00f00000L +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ5__SHIFT 0x00000014 +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ6_MASK 0x0f000000L +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ6__SHIFT 0x00000018 +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ7_MASK 0xf0000000L +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ7__SHIFT 0x0000001c +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ0_MASK 0x0000000fL +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ0__SHIFT 0x00000000 +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ1_MASK 0x000000f0L +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ1__SHIFT 0x00000004 +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ2_MASK 0x00000f00L +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ2__SHIFT 0x00000008 +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ3_MASK 0x0000f000L +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ3__SHIFT 0x0000000c +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ4_MASK 0x000f0000L +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ4__SHIFT 0x00000010 +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ5_MASK 0x00f00000L +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ5__SHIFT 0x00000014 +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ6_MASK 0x0f000000L +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ6__SHIFT 0x00000018 +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ7_MASK 0xf0000000L +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ7__SHIFT 0x0000001c +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ0_MASK 0x0000000fL +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ0__SHIFT 0x00000000 +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ1_MASK 0x000000f0L +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ1__SHIFT 0x00000004 +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ2_MASK 0x00000f00L +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ2__SHIFT 0x00000008 +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ3_MASK 0x0000f000L +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ3__SHIFT 0x0000000c +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ4_MASK 0x000f0000L +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ4__SHIFT 0x00000010 +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ5_MASK 0x00f00000L +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ5__SHIFT 0x00000014 +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ6_MASK 0x0f000000L +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ6__SHIFT 0x00000018 +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ7_MASK 0xf0000000L +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ7__SHIFT 0x0000001c +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ0_MASK 0x0000000fL +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ0__SHIFT 0x00000000 +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ1_MASK 0x000000f0L +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ1__SHIFT 0x00000004 +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ2_MASK 0x00000f00L +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ2__SHIFT 0x00000008 +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ3_MASK 0x0000f000L +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ3__SHIFT 0x0000000c +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ4_MASK 0x000f0000L +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ4__SHIFT 0x00000010 +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ5_MASK 0x00f00000L +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ5__SHIFT 0x00000014 +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ6_MASK 0x0f000000L +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ6__SHIFT 0x00000018 +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ7_MASK 0xf0000000L +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ7__SHIFT 0x0000001c +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ0_MASK 0x0000000fL +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ0__SHIFT 0x00000000 +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ1_MASK 0x000000f0L +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ1__SHIFT 0x00000004 +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ2_MASK 0x00000f00L +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ2__SHIFT 0x00000008 +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ3_MASK 0x0000f000L +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ3__SHIFT 0x0000000c +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ4_MASK 0x000f0000L +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ4__SHIFT 0x00000010 +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ5_MASK 0x00f00000L +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ5__SHIFT 0x00000014 +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ6_MASK 0x0f000000L +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ6__SHIFT 0x00000018 +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ7_MASK 0xf0000000L +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ7__SHIFT 0x0000001c +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ0_MASK 0x0000000fL +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ0__SHIFT 0x00000000 +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ1_MASK 0x000000f0L +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ1__SHIFT 0x00000004 +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ2_MASK 0x00000f00L +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ2__SHIFT 0x00000008 +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ3_MASK 0x0000f000L +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ3__SHIFT 0x0000000c +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ4_MASK 0x000f0000L +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ4__SHIFT 0x00000010 +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ5_MASK 0x00f00000L +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ5__SHIFT 0x00000014 +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ6_MASK 0x0f000000L +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ6__SHIFT 0x00000018 +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ7_MASK 0xf0000000L +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ7__SHIFT 0x0000001c +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ0_MASK 0x0000000fL +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ0__SHIFT 0x00000000 +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ1_MASK 0x000000f0L +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ1__SHIFT 0x00000004 +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ2_MASK 0x00000f00L +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ2__SHIFT 0x00000008 +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ3_MASK 0x0000f000L +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ3__SHIFT 0x0000000c +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ4_MASK 0x000f0000L +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ4__SHIFT 0x00000010 +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ5_MASK 0x00f00000L +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ5__SHIFT 0x00000014 +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ6_MASK 0x0f000000L +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ6__SHIFT 0x00000018 +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ7_MASK 0xf0000000L +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ7__SHIFT 0x0000001c +#define MC_SEQ_TXFRAMING_DBI_D0__DBI0_MASK 0x0000000fL +#define MC_SEQ_TXFRAMING_DBI_D0__DBI0__SHIFT 0x00000000 +#define MC_SEQ_TXFRAMING_DBI_D0__DBI1_MASK 0x000000f0L +#define MC_SEQ_TXFRAMING_DBI_D0__DBI1__SHIFT 0x00000004 +#define MC_SEQ_TXFRAMING_DBI_D0__DBI2_MASK 0x00000f00L +#define MC_SEQ_TXFRAMING_DBI_D0__DBI2__SHIFT 0x00000008 +#define MC_SEQ_TXFRAMING_DBI_D0__DBI3_MASK 0x0000f000L +#define MC_SEQ_TXFRAMING_DBI_D0__DBI3__SHIFT 0x0000000c +#define MC_SEQ_TXFRAMING_DBI_D1__DBI0_MASK 0x0000000fL +#define MC_SEQ_TXFRAMING_DBI_D1__DBI0__SHIFT 0x00000000 +#define MC_SEQ_TXFRAMING_DBI_D1__DBI1_MASK 0x000000f0L +#define MC_SEQ_TXFRAMING_DBI_D1__DBI1__SHIFT 0x00000004 +#define MC_SEQ_TXFRAMING_DBI_D1__DBI2_MASK 0x00000f00L +#define MC_SEQ_TXFRAMING_DBI_D1__DBI2__SHIFT 0x00000008 +#define MC_SEQ_TXFRAMING_DBI_D1__DBI3_MASK 0x0000f000L +#define MC_SEQ_TXFRAMING_DBI_D1__DBI3__SHIFT 0x0000000c +#define MC_SEQ_TXFRAMING_EDC_D0__EDC0_MASK 0x0000000fL +#define MC_SEQ_TXFRAMING_EDC_D0__EDC0__SHIFT 0x00000000 +#define MC_SEQ_TXFRAMING_EDC_D0__EDC1_MASK 0x000000f0L +#define MC_SEQ_TXFRAMING_EDC_D0__EDC1__SHIFT 0x00000004 +#define MC_SEQ_TXFRAMING_EDC_D0__EDC2_MASK 0x00000f00L +#define MC_SEQ_TXFRAMING_EDC_D0__EDC2__SHIFT 0x00000008 +#define MC_SEQ_TXFRAMING_EDC_D0__EDC3_MASK 0x0000f000L +#define MC_SEQ_TXFRAMING_EDC_D0__EDC3__SHIFT 0x0000000c +#define MC_SEQ_TXFRAMING_EDC_D0__WCDR0_MASK 0x000f0000L +#define MC_SEQ_TXFRAMING_EDC_D0__WCDR0__SHIFT 0x00000010 +#define MC_SEQ_TXFRAMING_EDC_D0__WCDR1_MASK 0x00f00000L +#define MC_SEQ_TXFRAMING_EDC_D0__WCDR1__SHIFT 0x00000014 +#define MC_SEQ_TXFRAMING_EDC_D0__WCDR2_MASK 0x0f000000L +#define MC_SEQ_TXFRAMING_EDC_D0__WCDR2__SHIFT 0x00000018 +#define MC_SEQ_TXFRAMING_EDC_D0__WCDR3_MASK 0xf0000000L +#define MC_SEQ_TXFRAMING_EDC_D0__WCDR3__SHIFT 0x0000001c +#define MC_SEQ_TXFRAMING_EDC_D1__EDC0_MASK 0x0000000fL +#define MC_SEQ_TXFRAMING_EDC_D1__EDC0__SHIFT 0x00000000 +#define MC_SEQ_TXFRAMING_EDC_D1__EDC1_MASK 0x000000f0L +#define MC_SEQ_TXFRAMING_EDC_D1__EDC1__SHIFT 0x00000004 +#define MC_SEQ_TXFRAMING_EDC_D1__EDC2_MASK 0x00000f00L +#define MC_SEQ_TXFRAMING_EDC_D1__EDC2__SHIFT 0x00000008 +#define MC_SEQ_TXFRAMING_EDC_D1__EDC3_MASK 0x0000f000L +#define MC_SEQ_TXFRAMING_EDC_D1__EDC3__SHIFT 0x0000000c +#define MC_SEQ_TXFRAMING_EDC_D1__WCDR0_MASK 0x000f0000L +#define MC_SEQ_TXFRAMING_EDC_D1__WCDR0__SHIFT 0x00000010 +#define MC_SEQ_TXFRAMING_EDC_D1__WCDR1_MASK 0x00f00000L +#define MC_SEQ_TXFRAMING_EDC_D1__WCDR1__SHIFT 0x00000014 +#define MC_SEQ_TXFRAMING_EDC_D1__WCDR2_MASK 0x0f000000L +#define MC_SEQ_TXFRAMING_EDC_D1__WCDR2__SHIFT 0x00000018 +#define MC_SEQ_TXFRAMING_EDC_D1__WCDR3_MASK 0xf0000000L +#define MC_SEQ_TXFRAMING_EDC_D1__WCDR3__SHIFT 0x0000001c +#define MC_SEQ_TXFRAMING_FCK_D0__FCK0_MASK 0x0000000fL +#define MC_SEQ_TXFRAMING_FCK_D0__FCK0__SHIFT 0x00000000 +#define MC_SEQ_TXFRAMING_FCK_D0__FCK1_MASK 0x000000f0L +#define MC_SEQ_TXFRAMING_FCK_D0__FCK1__SHIFT 0x00000004 +#define MC_SEQ_TXFRAMING_FCK_D0__FCK2_MASK 0x00000f00L +#define MC_SEQ_TXFRAMING_FCK_D0__FCK2__SHIFT 0x00000008 +#define MC_SEQ_TXFRAMING_FCK_D0__FCK3_MASK 0x0000f000L +#define MC_SEQ_TXFRAMING_FCK_D0__FCK3__SHIFT 0x0000000c +#define MC_SEQ_TXFRAMING_FCK_D1__FCK0_MASK 0x0000000fL +#define MC_SEQ_TXFRAMING_FCK_D1__FCK0__SHIFT 0x00000000 +#define MC_SEQ_TXFRAMING_FCK_D1__FCK1_MASK 0x000000f0L +#define MC_SEQ_TXFRAMING_FCK_D1__FCK1__SHIFT 0x00000004 +#define MC_SEQ_TXFRAMING_FCK_D1__FCK2_MASK 0x00000f00L +#define MC_SEQ_TXFRAMING_FCK_D1__FCK2__SHIFT 0x00000008 +#define MC_SEQ_TXFRAMING_FCK_D1__FCK3_MASK 0x0000f000L +#define MC_SEQ_TXFRAMING_FCK_D1__FCK3__SHIFT 0x0000000c +#define MC_SEQ_VENDOR_ID_I0__VALUE_MASK 0xffffffffL +#define MC_SEQ_VENDOR_ID_I0__VALUE__SHIFT 0x00000000 +#define MC_SEQ_VENDOR_ID_I1__VALUE_MASK 0xffffffffL +#define MC_SEQ_VENDOR_ID_I1__VALUE__SHIFT 0x00000000 +#define MC_SEQ_WCDR_CTRL__AREF_EN_MASK 0x00004000L +#define MC_SEQ_WCDR_CTRL__AREF_EN__SHIFT 0x0000000e +#define MC_SEQ_WCDR_CTRL__PRBS_EN_MASK 0x00100000L +#define MC_SEQ_WCDR_CTRL__PRBS_EN__SHIFT 0x00000014 +#define MC_SEQ_WCDR_CTRL__PRBS_RST_MASK 0x00200000L +#define MC_SEQ_WCDR_CTRL__PRBS_RST__SHIFT 0x00000015 +#define MC_SEQ_WCDR_CTRL__PREAMBLE_MASK 0x0f000000L +#define MC_SEQ_WCDR_CTRL__PREAMBLE__SHIFT 0x00000018 +#define MC_SEQ_WCDR_CTRL__PRE_MASK_MASK 0xf0000000L +#define MC_SEQ_WCDR_CTRL__PRE_MASK__SHIFT 0x0000001c +#define MC_SEQ_WCDR_CTRL__RD_EN_MASK 0x00002000L +#define MC_SEQ_WCDR_CTRL__RD_EN__SHIFT 0x0000000d +#define MC_SEQ_WCDR_CTRL__TRAIN_EN_MASK 0x00008000L +#define MC_SEQ_WCDR_CTRL__TRAIN_EN__SHIFT 0x0000000f +#define MC_SEQ_WCDR_CTRL__TWCDRL_MASK 0x000f0000L +#define MC_SEQ_WCDR_CTRL__TWCDRL__SHIFT 0x00000010 +#define MC_SEQ_WCDR_CTRL__WCDR_PRE_MASK 0x000000ffL +#define MC_SEQ_WCDR_CTRL__WCDR_PRE__SHIFT 0x00000000 +#define MC_SEQ_WCDR_CTRL__WCDR_TIM_MASK 0x00000f00L +#define MC_SEQ_WCDR_CTRL__WCDR_TIM__SHIFT 0x00000008 +#define MC_SEQ_WCDR_CTRL__WR_EN_MASK 0x00001000L +#define MC_SEQ_WCDR_CTRL__WR_EN__SHIFT 0x0000000c +#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D0_MASK 0x00000001L +#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D0__SHIFT 0x00000000 +#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D1_MASK 0x00000008L +#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D1__SHIFT 0x00000003 +#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D0_MASK 0x00000002L +#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D0__SHIFT 0x00000001 +#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D1_MASK 0x00000010L +#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D1__SHIFT 0x00000004 +#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D0_MASK 0x00000001L +#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D0__SHIFT 0x00000000 +#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D1_MASK 0x00000008L +#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D1__SHIFT 0x00000003 +#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D0_MASK 0x00000002L +#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D0__SHIFT 0x00000001 +#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D1_MASK 0x00000010L +#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D1__SHIFT 0x00000004 +#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D0_MASK 0x00000004L +#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D0__SHIFT 0x00000002 +#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D1_MASK 0x00000020L +#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D1__SHIFT 0x00000005 +#define MC_SEQ_WR_CTL_2_LP__WCDR_EN_MASK 0x00000040L +#define MC_SEQ_WR_CTL_2_LP__WCDR_EN__SHIFT 0x00000006 +#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D0_MASK 0x00000004L +#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D0__SHIFT 0x00000002 +#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D1_MASK 0x00000020L +#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D1__SHIFT 0x00000005 +#define MC_SEQ_WR_CTL_2__WCDR_EN_MASK 0x00000040L +#define MC_SEQ_WR_CTL_2__WCDR_EN__SHIFT 0x00000006 +#define MC_SEQ_WR_CTL_D0__ADR_2Y_DLY_MASK 0x00000400L +#define MC_SEQ_WR_CTL_D0__ADR_2Y_DLY__SHIFT 0x0000000a +#define MC_SEQ_WR_CTL_D0__ADR_DLY_MASK 0x20000000L +#define MC_SEQ_WR_CTL_D0__ADR_DLY__SHIFT 0x0000001d +#define MC_SEQ_WR_CTL_D0__CMD_2Y_DLY_MASK 0x00000800L +#define MC_SEQ_WR_CTL_D0__CMD_2Y_DLY__SHIFT 0x0000000b +#define MC_SEQ_WR_CTL_D0__CMD_DLY_MASK 0x40000000L +#define MC_SEQ_WR_CTL_D0__CMD_DLY__SHIFT 0x0000001e +#define MC_SEQ_WR_CTL_D0__DAT_2Y_DLY_MASK 0x00000200L +#define MC_SEQ_WR_CTL_D0__DAT_2Y_DLY__SHIFT 0x00000009 +#define MC_SEQ_WR_CTL_D0__DAT_DLY_MASK 0x0000000fL +#define MC_SEQ_WR_CTL_D0__DAT_DLY__SHIFT 0x00000000 +#define MC_SEQ_WR_CTL_D0__DQS_DLY_MASK 0x000000f0L +#define MC_SEQ_WR_CTL_D0__DQS_DLY__SHIFT 0x00000004 +#define MC_SEQ_WR_CTL_D0__DQS_XTR_MASK 0x00000100L +#define MC_SEQ_WR_CTL_D0__DQS_XTR__SHIFT 0x00000008 +#define MC_SEQ_WR_CTL_D0_LP__ADR_2Y_DLY_MASK 0x00000400L +#define MC_SEQ_WR_CTL_D0_LP__ADR_2Y_DLY__SHIFT 0x0000000a +#define MC_SEQ_WR_CTL_D0_LP__ADR_DLY_MASK 0x20000000L +#define MC_SEQ_WR_CTL_D0_LP__ADR_DLY__SHIFT 0x0000001d +#define MC_SEQ_WR_CTL_D0_LP__CMD_2Y_DLY_MASK 0x00000800L +#define MC_SEQ_WR_CTL_D0_LP__CMD_2Y_DLY__SHIFT 0x0000000b +#define MC_SEQ_WR_CTL_D0_LP__CMD_DLY_MASK 0x40000000L +#define MC_SEQ_WR_CTL_D0_LP__CMD_DLY__SHIFT 0x0000001e +#define MC_SEQ_WR_CTL_D0_LP__DAT_2Y_DLY_MASK 0x00000200L +#define MC_SEQ_WR_CTL_D0_LP__DAT_2Y_DLY__SHIFT 0x00000009 +#define MC_SEQ_WR_CTL_D0_LP__DAT_DLY_MASK 0x0000000fL +#define MC_SEQ_WR_CTL_D0_LP__DAT_DLY__SHIFT 0x00000000 +#define MC_SEQ_WR_CTL_D0_LP__DQS_DLY_MASK 0x000000f0L +#define MC_SEQ_WR_CTL_D0_LP__DQS_DLY__SHIFT 0x00000004 +#define MC_SEQ_WR_CTL_D0_LP__DQS_XTR_MASK 0x00000100L +#define MC_SEQ_WR_CTL_D0_LP__DQS_XTR__SHIFT 0x00000008 +#define MC_SEQ_WR_CTL_D0_LP__ODT_DLY_MASK 0x0f000000L +#define MC_SEQ_WR_CTL_D0_LP__ODT_DLY__SHIFT 0x00000018 +#define MC_SEQ_WR_CTL_D0_LP__ODT_EXT_MASK 0x10000000L +#define MC_SEQ_WR_CTL_D0_LP__ODT_EXT__SHIFT 0x0000001c +#define MC_SEQ_WR_CTL_D0_LP__OEN_DLY_MASK 0x0000f000L +#define MC_SEQ_WR_CTL_D0_LP__OEN_DLY__SHIFT 0x0000000c +#define MC_SEQ_WR_CTL_D0_LP__OEN_EXT_MASK 0x000f0000L +#define MC_SEQ_WR_CTL_D0_LP__OEN_EXT__SHIFT 0x00000010 +#define MC_SEQ_WR_CTL_D0_LP__OEN_SEL_MASK 0x00300000L +#define MC_SEQ_WR_CTL_D0_LP__OEN_SEL__SHIFT 0x00000014 +#define MC_SEQ_WR_CTL_D0__ODT_DLY_MASK 0x0f000000L +#define MC_SEQ_WR_CTL_D0__ODT_DLY__SHIFT 0x00000018 +#define MC_SEQ_WR_CTL_D0__ODT_EXT_MASK 0x10000000L +#define MC_SEQ_WR_CTL_D0__ODT_EXT__SHIFT 0x0000001c +#define MC_SEQ_WR_CTL_D0__OEN_DLY_MASK 0x0000f000L +#define MC_SEQ_WR_CTL_D0__OEN_DLY__SHIFT 0x0000000c +#define MC_SEQ_WR_CTL_D0__OEN_EXT_MASK 0x000f0000L +#define MC_SEQ_WR_CTL_D0__OEN_EXT__SHIFT 0x00000010 +#define MC_SEQ_WR_CTL_D0__OEN_SEL_MASK 0x00300000L +#define MC_SEQ_WR_CTL_D0__OEN_SEL__SHIFT 0x00000014 +#define MC_SEQ_WR_CTL_D1__ADR_2Y_DLY_MASK 0x00000400L +#define MC_SEQ_WR_CTL_D1__ADR_2Y_DLY__SHIFT 0x0000000a +#define MC_SEQ_WR_CTL_D1__ADR_DLY_MASK 0x20000000L +#define MC_SEQ_WR_CTL_D1__ADR_DLY__SHIFT 0x0000001d +#define MC_SEQ_WR_CTL_D1__CMD_2Y_DLY_MASK 0x00000800L +#define MC_SEQ_WR_CTL_D1__CMD_2Y_DLY__SHIFT 0x0000000b +#define MC_SEQ_WR_CTL_D1__CMD_DLY_MASK 0x40000000L +#define MC_SEQ_WR_CTL_D1__CMD_DLY__SHIFT 0x0000001e +#define MC_SEQ_WR_CTL_D1__DAT_2Y_DLY_MASK 0x00000200L +#define MC_SEQ_WR_CTL_D1__DAT_2Y_DLY__SHIFT 0x00000009 +#define MC_SEQ_WR_CTL_D1__DAT_DLY_MASK 0x0000000fL +#define MC_SEQ_WR_CTL_D1__DAT_DLY__SHIFT 0x00000000 +#define MC_SEQ_WR_CTL_D1__DQS_DLY_MASK 0x000000f0L +#define MC_SEQ_WR_CTL_D1__DQS_DLY__SHIFT 0x00000004 +#define MC_SEQ_WR_CTL_D1__DQS_XTR_MASK 0x00000100L +#define MC_SEQ_WR_CTL_D1__DQS_XTR__SHIFT 0x00000008 +#define MC_SEQ_WR_CTL_D1_LP__ADR_2Y_DLY_MASK 0x00000400L +#define MC_SEQ_WR_CTL_D1_LP__ADR_2Y_DLY__SHIFT 0x0000000a +#define MC_SEQ_WR_CTL_D1_LP__ADR_DLY_MASK 0x20000000L +#define MC_SEQ_WR_CTL_D1_LP__ADR_DLY__SHIFT 0x0000001d +#define MC_SEQ_WR_CTL_D1_LP__CMD_2Y_DLY_MASK 0x00000800L +#define MC_SEQ_WR_CTL_D1_LP__CMD_2Y_DLY__SHIFT 0x0000000b +#define MC_SEQ_WR_CTL_D1_LP__CMD_DLY_MASK 0x40000000L +#define MC_SEQ_WR_CTL_D1_LP__CMD_DLY__SHIFT 0x0000001e +#define MC_SEQ_WR_CTL_D1_LP__DAT_2Y_DLY_MASK 0x00000200L +#define MC_SEQ_WR_CTL_D1_LP__DAT_2Y_DLY__SHIFT 0x00000009 +#define MC_SEQ_WR_CTL_D1_LP__DAT_DLY_MASK 0x0000000fL +#define MC_SEQ_WR_CTL_D1_LP__DAT_DLY__SHIFT 0x00000000 +#define MC_SEQ_WR_CTL_D1_LP__DQS_DLY_MASK 0x000000f0L +#define MC_SEQ_WR_CTL_D1_LP__DQS_DLY__SHIFT 0x00000004 +#define MC_SEQ_WR_CTL_D1_LP__DQS_XTR_MASK 0x00000100L +#define MC_SEQ_WR_CTL_D1_LP__DQS_XTR__SHIFT 0x00000008 +#define MC_SEQ_WR_CTL_D1_LP__ODT_DLY_MASK 0x0f000000L +#define MC_SEQ_WR_CTL_D1_LP__ODT_DLY__SHIFT 0x00000018 +#define MC_SEQ_WR_CTL_D1_LP__ODT_EXT_MASK 0x10000000L +#define MC_SEQ_WR_CTL_D1_LP__ODT_EXT__SHIFT 0x0000001c +#define MC_SEQ_WR_CTL_D1_LP__OEN_DLY_MASK 0x0000f000L +#define MC_SEQ_WR_CTL_D1_LP__OEN_DLY__SHIFT 0x0000000c +#define MC_SEQ_WR_CTL_D1_LP__OEN_EXT_MASK 0x000f0000L +#define MC_SEQ_WR_CTL_D1_LP__OEN_EXT__SHIFT 0x00000010 +#define MC_SEQ_WR_CTL_D1_LP__OEN_SEL_MASK 0x00300000L +#define MC_SEQ_WR_CTL_D1_LP__OEN_SEL__SHIFT 0x00000014 +#define MC_SEQ_WR_CTL_D1__ODT_DLY_MASK 0x0f000000L +#define MC_SEQ_WR_CTL_D1__ODT_DLY__SHIFT 0x00000018 +#define MC_SEQ_WR_CTL_D1__ODT_EXT_MASK 0x10000000L +#define MC_SEQ_WR_CTL_D1__ODT_EXT__SHIFT 0x0000001c +#define MC_SEQ_WR_CTL_D1__OEN_DLY_MASK 0x0000f000L +#define MC_SEQ_WR_CTL_D1__OEN_DLY__SHIFT 0x0000000c +#define MC_SEQ_WR_CTL_D1__OEN_EXT_MASK 0x000f0000L +#define MC_SEQ_WR_CTL_D1__OEN_EXT__SHIFT 0x00000010 +#define MC_SEQ_WR_CTL_D1__OEN_SEL_MASK 0x00300000L +#define MC_SEQ_WR_CTL_D1__OEN_SEL__SHIFT 0x00000014 +#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE_MASK 0x00000007L +#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE__SHIFT 0x00000000 +#define MC_SHARED_CHMAP__CHAN0_MASK 0x0000000fL +#define MC_SHARED_CHMAP__CHAN0__SHIFT 0x00000000 +#define MC_SHARED_CHMAP__CHAN1_MASK 0x000000f0L +#define MC_SHARED_CHMAP__CHAN1__SHIFT 0x00000004 +#define MC_SHARED_CHMAP__CHAN2_MASK 0x00000f00L +#define MC_SHARED_CHMAP__CHAN2__SHIFT 0x00000008 +#define MC_SHARED_CHMAP__NOOFCHAN_MASK 0x0000f000L +#define MC_SHARED_CHMAP__NOOFCHAN__SHIFT 0x0000000c +#define MC_SHARED_CHREMAP__CHAN0_MASK 0x00000007L +#define MC_SHARED_CHREMAP__CHAN0__SHIFT 0x00000000 +#define MC_SHARED_CHREMAP__CHAN1_MASK 0x00000038L +#define MC_SHARED_CHREMAP__CHAN1__SHIFT 0x00000003 +#define MC_SHARED_CHREMAP__CHAN2_MASK 0x000001c0L +#define MC_SHARED_CHREMAP__CHAN2__SHIFT 0x00000006 +#define MC_SHARED_CHREMAP__CHAN3_MASK 0x00000e00L +#define MC_SHARED_CHREMAP__CHAN3__SHIFT 0x00000009 +#define MC_SHARED_CHREMAP__CHAN4_MASK 0x00007000L +#define MC_SHARED_CHREMAP__CHAN4__SHIFT 0x0000000c +#define MC_SHARED_CHREMAP__CHAN5_MASK 0x00038000L +#define MC_SHARED_CHREMAP__CHAN5__SHIFT 0x0000000f +#define MC_SHARED_CHREMAP__CHAN6_MASK 0x001c0000L +#define MC_SHARED_CHREMAP__CHAN6__SHIFT 0x00000012 +#define MC_SHARED_CHREMAP__CHAN7_MASK 0x00e00000L +#define MC_SHARED_CHREMAP__CHAN7__SHIFT 0x00000015 +#define MC_TRAIN_EDCCDR_R_D0__EDC0_MASK 0x000000ffL +#define MC_TRAIN_EDCCDR_R_D0__EDC0__SHIFT 0x00000000 +#define MC_TRAIN_EDCCDR_R_D0__EDC1_MASK 0x0000ff00L +#define MC_TRAIN_EDCCDR_R_D0__EDC1__SHIFT 0x00000008 +#define MC_TRAIN_EDCCDR_R_D0__EDC2_MASK 0x00ff0000L +#define MC_TRAIN_EDCCDR_R_D0__EDC2__SHIFT 0x00000010 +#define MC_TRAIN_EDCCDR_R_D0__EDC3_MASK 0xff000000L +#define MC_TRAIN_EDCCDR_R_D0__EDC3__SHIFT 0x00000018 +#define MC_TRAIN_EDCCDR_R_D1__EDC0_MASK 0x000000ffL +#define MC_TRAIN_EDCCDR_R_D1__EDC0__SHIFT 0x00000000 +#define MC_TRAIN_EDCCDR_R_D1__EDC1_MASK 0x0000ff00L +#define MC_TRAIN_EDCCDR_R_D1__EDC1__SHIFT 0x00000008 +#define MC_TRAIN_EDCCDR_R_D1__EDC2_MASK 0x00ff0000L +#define MC_TRAIN_EDCCDR_R_D1__EDC2__SHIFT 0x00000010 +#define MC_TRAIN_EDCCDR_R_D1__EDC3_MASK 0xff000000L +#define MC_TRAIN_EDCCDR_R_D1__EDC3__SHIFT 0x00000018 +#define MC_TRAIN_EDC_STATUS_D0__REDC_CNT_MASK 0xffff0000L +#define MC_TRAIN_EDC_STATUS_D0__REDC_CNT__SHIFT 0x00000010 +#define MC_TRAIN_EDC_STATUS_D0__WEDC_CNT_MASK 0x0000ffffL +#define MC_TRAIN_EDC_STATUS_D0__WEDC_CNT__SHIFT 0x00000000 +#define MC_TRAIN_EDC_STATUS_D1__REDC_CNT_MASK 0xffff0000L +#define MC_TRAIN_EDC_STATUS_D1__REDC_CNT__SHIFT 0x00000010 +#define MC_TRAIN_EDC_STATUS_D1__WEDC_CNT_MASK 0x0000ffffL +#define MC_TRAIN_EDC_STATUS_D1__WEDC_CNT__SHIFT 0x00000000 +#define MC_TRAIN_PRBSERR_0_D0__DQ_STATUS_MASK 0xffffffffL +#define MC_TRAIN_PRBSERR_0_D0__DQ_STATUS__SHIFT 0x00000000 +#define MC_TRAIN_PRBSERR_0_D1__DQ_STATUS_MASK 0xffffffffL +#define MC_TRAIN_PRBSERR_0_D1__DQ_STATUS__SHIFT 0x00000000 +#define MC_TRAIN_PRBSERR_1_D0__DBI_STATUS_MASK 0x0000000fL +#define MC_TRAIN_PRBSERR_1_D0__DBI_STATUS__SHIFT 0x00000000 +#define MC_TRAIN_PRBSERR_1_D0__EDC_STATUS_MASK 0x000000f0L +#define MC_TRAIN_PRBSERR_1_D0__EDC_STATUS__SHIFT 0x00000004 +#define MC_TRAIN_PRBSERR_1_D0__PMA_PRBSCLR_MASK 0x10000000L +#define MC_TRAIN_PRBSERR_1_D0__PMA_PRBSCLR__SHIFT 0x0000001c +#define MC_TRAIN_PRBSERR_1_D0__PMD0_PRBSCLR_MASK 0x20000000L +#define MC_TRAIN_PRBSERR_1_D0__PMD0_PRBSCLR__SHIFT 0x0000001d +#define MC_TRAIN_PRBSERR_1_D0__PMD1_PRBSCLR_MASK 0x40000000L +#define MC_TRAIN_PRBSERR_1_D0__PMD1_PRBSCLR__SHIFT 0x0000001e +#define MC_TRAIN_PRBSERR_1_D0__WCDR_STATUS_MASK 0x0000f000L +#define MC_TRAIN_PRBSERR_1_D0__WCDR_STATUS__SHIFT 0x0000000c +#define MC_TRAIN_PRBSERR_1_D0__WCK_STATUS_MASK 0x00000f00L +#define MC_TRAIN_PRBSERR_1_D0__WCK_STATUS__SHIFT 0x00000008 +#define MC_TRAIN_PRBSERR_1_D1__DBI_STATUS_MASK 0x0000000fL +#define MC_TRAIN_PRBSERR_1_D1__DBI_STATUS__SHIFT 0x00000000 +#define MC_TRAIN_PRBSERR_1_D1__EDC_STATUS_MASK 0x000000f0L +#define MC_TRAIN_PRBSERR_1_D1__EDC_STATUS__SHIFT 0x00000004 +#define MC_TRAIN_PRBSERR_1_D1__PMA_PRBSCLR_MASK 0x10000000L +#define MC_TRAIN_PRBSERR_1_D1__PMA_PRBSCLR__SHIFT 0x0000001c +#define MC_TRAIN_PRBSERR_1_D1__PMD0_PRBSCLR_MASK 0x20000000L +#define MC_TRAIN_PRBSERR_1_D1__PMD0_PRBSCLR__SHIFT 0x0000001d +#define MC_TRAIN_PRBSERR_1_D1__PMD1_PRBSCLR_MASK 0x40000000L +#define MC_TRAIN_PRBSERR_1_D1__PMD1_PRBSCLR__SHIFT 0x0000001e +#define MC_TRAIN_PRBSERR_1_D1__WCDR_STATUS_MASK 0x0000f000L +#define MC_TRAIN_PRBSERR_1_D1__WCDR_STATUS__SHIFT 0x0000000c +#define MC_TRAIN_PRBSERR_1_D1__WCK_STATUS_MASK 0x00000f00L +#define MC_TRAIN_PRBSERR_1_D1__WCK_STATUS__SHIFT 0x00000008 +#define MC_TRAIN_PRBSERR_2_D0__ABI_STATUS_MASK 0x10000000L +#define MC_TRAIN_PRBSERR_2_D0__ABI_STATUS__SHIFT 0x0000001c +#define MC_TRAIN_PRBSERR_2_D0__ADDR_STATUS_MASK 0x03ff0000L +#define MC_TRAIN_PRBSERR_2_D0__ADDR_STATUS__SHIFT 0x00000010 +#define MC_TRAIN_PRBSERR_2_D0__CAS_STATUS_MASK 0x00000400L +#define MC_TRAIN_PRBSERR_2_D0__CAS_STATUS__SHIFT 0x0000000a +#define MC_TRAIN_PRBSERR_2_D0__CKB_STATUS_MASK 0x00000002L +#define MC_TRAIN_PRBSERR_2_D0__CKB_STATUS__SHIFT 0x00000001 +#define MC_TRAIN_PRBSERR_2_D0__CKE_STATUS_MASK 0x00000100L +#define MC_TRAIN_PRBSERR_2_D0__CKE_STATUS__SHIFT 0x00000008 +#define MC_TRAIN_PRBSERR_2_D0__CK_STATUS_MASK 0x00000001L +#define MC_TRAIN_PRBSERR_2_D0__CK_STATUS__SHIFT 0x00000000 +#define MC_TRAIN_PRBSERR_2_D0__CS_STATUS_MASK 0x00000030L +#define MC_TRAIN_PRBSERR_2_D0__CS_STATUS__SHIFT 0x00000004 +#define MC_TRAIN_PRBSERR_2_D0__RAS_STATUS_MASK 0x00000200L +#define MC_TRAIN_PRBSERR_2_D0__RAS_STATUS__SHIFT 0x00000009 +#define MC_TRAIN_PRBSERR_2_D0__WE_STATUS_MASK 0x00000800L +#define MC_TRAIN_PRBSERR_2_D0__WE_STATUS__SHIFT 0x0000000b +#define MC_TRAIN_PRBSERR_2_D1__ABI_STATUS_MASK 0x10000000L +#define MC_TRAIN_PRBSERR_2_D1__ABI_STATUS__SHIFT 0x0000001c +#define MC_TRAIN_PRBSERR_2_D1__ADDR_STATUS_MASK 0x03ff0000L +#define MC_TRAIN_PRBSERR_2_D1__ADDR_STATUS__SHIFT 0x00000010 +#define MC_TRAIN_PRBSERR_2_D1__CAS_STATUS_MASK 0x00000400L +#define MC_TRAIN_PRBSERR_2_D1__CAS_STATUS__SHIFT 0x0000000a +#define MC_TRAIN_PRBSERR_2_D1__CKB_STATUS_MASK 0x00000002L +#define MC_TRAIN_PRBSERR_2_D1__CKB_STATUS__SHIFT 0x00000001 +#define MC_TRAIN_PRBSERR_2_D1__CKE_STATUS_MASK 0x00000100L +#define MC_TRAIN_PRBSERR_2_D1__CKE_STATUS__SHIFT 0x00000008 +#define MC_TRAIN_PRBSERR_2_D1__CK_STATUS_MASK 0x00000001L +#define MC_TRAIN_PRBSERR_2_D1__CK_STATUS__SHIFT 0x00000000 +#define MC_TRAIN_PRBSERR_2_D1__CS_STATUS_MASK 0x00000030L +#define MC_TRAIN_PRBSERR_2_D1__CS_STATUS__SHIFT 0x00000004 +#define MC_TRAIN_PRBSERR_2_D1__RAS_STATUS_MASK 0x00000200L +#define MC_TRAIN_PRBSERR_2_D1__RAS_STATUS__SHIFT 0x00000009 +#define MC_TRAIN_PRBSERR_2_D1__WE_STATUS_MASK 0x00000800L +#define MC_TRAIN_PRBSERR_2_D1__WE_STATUS__SHIFT 0x0000000b +#define MC_TSM_DEBUG_BCNT0__BYTE0_MASK 0x000000ffL +#define MC_TSM_DEBUG_BCNT0__BYTE0__SHIFT 0x00000000 +#define MC_TSM_DEBUG_BCNT0__BYTE1_MASK 0x0000ff00L +#define MC_TSM_DEBUG_BCNT0__BYTE1__SHIFT 0x00000008 +#define MC_TSM_DEBUG_BCNT0__BYTE2_MASK 0x00ff0000L +#define MC_TSM_DEBUG_BCNT0__BYTE2__SHIFT 0x00000010 +#define MC_TSM_DEBUG_BCNT0__BYTE3_MASK 0xff000000L +#define MC_TSM_DEBUG_BCNT0__BYTE3__SHIFT 0x00000018 +#define MC_TSM_DEBUG_BCNT10__BYTE0_MASK 0x000000ffL +#define MC_TSM_DEBUG_BCNT10__BYTE0__SHIFT 0x00000000 +#define MC_TSM_DEBUG_BCNT10__BYTE1_MASK 0x0000ff00L +#define MC_TSM_DEBUG_BCNT10__BYTE1__SHIFT 0x00000008 +#define MC_TSM_DEBUG_BCNT10__BYTE2_MASK 0x00ff0000L +#define MC_TSM_DEBUG_BCNT10__BYTE2__SHIFT 0x00000010 +#define MC_TSM_DEBUG_BCNT10__BYTE3_MASK 0xff000000L +#define MC_TSM_DEBUG_BCNT10__BYTE3__SHIFT 0x00000018 +#define MC_TSM_DEBUG_BCNT1__BYTE0_MASK 0x000000ffL +#define MC_TSM_DEBUG_BCNT1__BYTE0__SHIFT 0x00000000 +#define MC_TSM_DEBUG_BCNT1__BYTE1_MASK 0x0000ff00L +#define MC_TSM_DEBUG_BCNT1__BYTE1__SHIFT 0x00000008 +#define MC_TSM_DEBUG_BCNT1__BYTE2_MASK 0x00ff0000L +#define MC_TSM_DEBUG_BCNT1__BYTE2__SHIFT 0x00000010 +#define MC_TSM_DEBUG_BCNT1__BYTE3_MASK 0xff000000L +#define MC_TSM_DEBUG_BCNT1__BYTE3__SHIFT 0x00000018 +#define MC_TSM_DEBUG_BCNT2__BYTE0_MASK 0x000000ffL +#define MC_TSM_DEBUG_BCNT2__BYTE0__SHIFT 0x00000000 +#define MC_TSM_DEBUG_BCNT2__BYTE1_MASK 0x0000ff00L +#define MC_TSM_DEBUG_BCNT2__BYTE1__SHIFT 0x00000008 +#define MC_TSM_DEBUG_BCNT2__BYTE2_MASK 0x00ff0000L +#define MC_TSM_DEBUG_BCNT2__BYTE2__SHIFT 0x00000010 +#define MC_TSM_DEBUG_BCNT2__BYTE3_MASK 0xff000000L +#define MC_TSM_DEBUG_BCNT2__BYTE3__SHIFT 0x00000018 +#define MC_TSM_DEBUG_BCNT3__BYTE0_MASK 0x000000ffL +#define MC_TSM_DEBUG_BCNT3__BYTE0__SHIFT 0x00000000 +#define MC_TSM_DEBUG_BCNT3__BYTE1_MASK 0x0000ff00L +#define MC_TSM_DEBUG_BCNT3__BYTE1__SHIFT 0x00000008 +#define MC_TSM_DEBUG_BCNT3__BYTE2_MASK 0x00ff0000L +#define MC_TSM_DEBUG_BCNT3__BYTE2__SHIFT 0x00000010 +#define MC_TSM_DEBUG_BCNT3__BYTE3_MASK 0xff000000L +#define MC_TSM_DEBUG_BCNT3__BYTE3__SHIFT 0x00000018 +#define MC_TSM_DEBUG_BCNT4__BYTE0_MASK 0x000000ffL +#define MC_TSM_DEBUG_BCNT4__BYTE0__SHIFT 0x00000000 +#define MC_TSM_DEBUG_BCNT4__BYTE1_MASK 0x0000ff00L +#define MC_TSM_DEBUG_BCNT4__BYTE1__SHIFT 0x00000008 +#define MC_TSM_DEBUG_BCNT4__BYTE2_MASK 0x00ff0000L +#define MC_TSM_DEBUG_BCNT4__BYTE2__SHIFT 0x00000010 +#define MC_TSM_DEBUG_BCNT4__BYTE3_MASK 0xff000000L +#define MC_TSM_DEBUG_BCNT4__BYTE3__SHIFT 0x00000018 +#define MC_TSM_DEBUG_BCNT5__BYTE0_MASK 0x000000ffL +#define MC_TSM_DEBUG_BCNT5__BYTE0__SHIFT 0x00000000 +#define MC_TSM_DEBUG_BCNT5__BYTE1_MASK 0x0000ff00L +#define MC_TSM_DEBUG_BCNT5__BYTE1__SHIFT 0x00000008 +#define MC_TSM_DEBUG_BCNT5__BYTE2_MASK 0x00ff0000L +#define MC_TSM_DEBUG_BCNT5__BYTE2__SHIFT 0x00000010 +#define MC_TSM_DEBUG_BCNT5__BYTE3_MASK 0xff000000L +#define MC_TSM_DEBUG_BCNT5__BYTE3__SHIFT 0x00000018 +#define MC_TSM_DEBUG_BCNT6__BYTE0_MASK 0x000000ffL +#define MC_TSM_DEBUG_BCNT6__BYTE0__SHIFT 0x00000000 +#define MC_TSM_DEBUG_BCNT6__BYTE1_MASK 0x0000ff00L +#define MC_TSM_DEBUG_BCNT6__BYTE1__SHIFT 0x00000008 +#define MC_TSM_DEBUG_BCNT6__BYTE2_MASK 0x00ff0000L +#define MC_TSM_DEBUG_BCNT6__BYTE2__SHIFT 0x00000010 +#define MC_TSM_DEBUG_BCNT6__BYTE3_MASK 0xff000000L +#define MC_TSM_DEBUG_BCNT6__BYTE3__SHIFT 0x00000018 +#define MC_TSM_DEBUG_BCNT7__BYTE0_MASK 0x000000ffL +#define MC_TSM_DEBUG_BCNT7__BYTE0__SHIFT 0x00000000 +#define MC_TSM_DEBUG_BCNT7__BYTE1_MASK 0x0000ff00L +#define MC_TSM_DEBUG_BCNT7__BYTE1__SHIFT 0x00000008 +#define MC_TSM_DEBUG_BCNT7__BYTE2_MASK 0x00ff0000L +#define MC_TSM_DEBUG_BCNT7__BYTE2__SHIFT 0x00000010 +#define MC_TSM_DEBUG_BCNT7__BYTE3_MASK 0xff000000L +#define MC_TSM_DEBUG_BCNT7__BYTE3__SHIFT 0x00000018 +#define MC_TSM_DEBUG_BCNT8__BYTE0_MASK 0x000000ffL +#define MC_TSM_DEBUG_BCNT8__BYTE0__SHIFT 0x00000000 +#define MC_TSM_DEBUG_BCNT8__BYTE1_MASK 0x0000ff00L +#define MC_TSM_DEBUG_BCNT8__BYTE1__SHIFT 0x00000008 +#define MC_TSM_DEBUG_BCNT8__BYTE2_MASK 0x00ff0000L +#define MC_TSM_DEBUG_BCNT8__BYTE2__SHIFT 0x00000010 +#define MC_TSM_DEBUG_BCNT8__BYTE3_MASK 0xff000000L +#define MC_TSM_DEBUG_BCNT8__BYTE3__SHIFT 0x00000018 +#define MC_TSM_DEBUG_BCNT9__BYTE0_MASK 0x000000ffL +#define MC_TSM_DEBUG_BCNT9__BYTE0__SHIFT 0x00000000 +#define MC_TSM_DEBUG_BCNT9__BYTE1_MASK 0x0000ff00L +#define MC_TSM_DEBUG_BCNT9__BYTE1__SHIFT 0x00000008 +#define MC_TSM_DEBUG_BCNT9__BYTE2_MASK 0x00ff0000L +#define MC_TSM_DEBUG_BCNT9__BYTE2__SHIFT 0x00000010 +#define MC_TSM_DEBUG_BCNT9__BYTE3_MASK 0xff000000L +#define MC_TSM_DEBUG_BCNT9__BYTE3__SHIFT 0x00000018 +#define MC_TSM_DEBUG_BKPT__DATA_MASK 0xffffffffL +#define MC_TSM_DEBUG_BKPT__DATA__SHIFT 0x00000000 +#define MC_TSM_DEBUG_FLAG__DATA_MASK 0xffffffffL +#define MC_TSM_DEBUG_FLAG__DATA__SHIFT 0x00000000 +#define MC_TSM_DEBUG_GCNT__DATA_MASK 0xffffffffL +#define MC_TSM_DEBUG_GCNT__DATA__SHIFT 0x00000000 +#define MC_TSM_DEBUG_MISC__FLAG_MASK 0x000000ffL +#define MC_TSM_DEBUG_MISC__FLAG__SHIFT 0x00000000 +#define MC_TSM_DEBUG_MISC__NCNT_RD_MASK 0x00000f00L +#define MC_TSM_DEBUG_MISC__NCNT_RD__SHIFT 0x00000008 +#define MC_TSM_DEBUG_MISC__NCNT_WR_MASK 0x0000f000L +#define MC_TSM_DEBUG_MISC__NCNT_WR__SHIFT 0x0000000c +#define MC_TSM_DEBUG_ST01__DATA_MASK 0xffffffffL +#define MC_TSM_DEBUG_ST01__DATA__SHIFT 0x00000000 +#define MC_TSM_DEBUG_ST23__DATA_MASK 0xffffffffL +#define MC_TSM_DEBUG_ST23__DATA__SHIFT 0x00000000 +#define MC_TSM_DEBUG_ST45__DATA_MASK 0xffffffffL +#define MC_TSM_DEBUG_ST45__DATA__SHIFT 0x00000000 +#define MC_VM_AGP_BASE__AGP_BASE_MASK 0x0003ffffL +#define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x00000000 +#define MC_VM_AGP_BOT__AGP_BOT_MASK 0x0003ffffL +#define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x00000000 +#define MC_VM_AGP_TOP__AGP_TOP_MASK 0x0003ffffL +#define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x00000000 +#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL_MASK 0x00000100L +#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL__SHIFT 0x00000008 +#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM_MASK 0x00000200L +#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM__SHIFT 0x00000009 +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE_MASK 0x00000003L +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE__SHIFT 0x00000000 +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE_MASK 0x0000000cL +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE__SHIFT 0x00000002 +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE_MASK 0x00000030L +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE__SHIFT 0x00000004 +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE_MASK 0x000000c0L +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE__SHIFT 0x00000006 +#define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0x0fffffffL +#define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x00000000 +#define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0x0fffffffL +#define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x00000000 +#define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0x0fffffffL +#define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x00000000 +#define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0x0fffffffL +#define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x00000000 +#define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0x0fffffffL +#define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x00000000 +#define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0x0fffffffL +#define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x00000000 +#define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0x0fffffffL +#define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x00000000 +#define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0x0fffffffL +#define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x00000000 +#define MC_VM_FB_LOCATION__FB_BASE_MASK 0x0000ffffL +#define MC_VM_FB_LOCATION__FB_BASE__SHIFT 0x00000000 +#define MC_VM_FB_LOCATION__FB_TOP_MASK 0xffff0000L +#define MC_VM_FB_LOCATION__FB_TOP__SHIFT 0x00000010 +#define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x0003ffffL +#define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x00000000 +#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00007000L +#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0x0000000c +#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0x00000e00L +#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x00000009 +#define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x00000001L +#define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x00000000 +#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x00078000L +#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0x0000000f +#define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x00000100L +#define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x00000008 +#define MC_VM_MB_L1_TLB0_STATUS__BUSY_MASK 0x00000001L +#define MC_VM_MB_L1_TLB0_STATUS__BUSY__SHIFT 0x00000000 +#define MC_VM_MB_L1_TLB1_STATUS__BUSY_MASK 0x00000001L +#define MC_VM_MB_L1_TLB1_STATUS__BUSY__SHIFT 0x00000000 +#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00007000L +#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0x0000000c +#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0x00000e00L +#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x00000009 +#define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x00000001L +#define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x00000000 +#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x00078000L +#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0x0000000f +#define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x00000100L +#define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x00000008 +#define MC_VM_MB_L1_TLB2_STATUS__BUSY_MASK 0x00000001L +#define MC_VM_MB_L1_TLB2_STATUS__BUSY__SHIFT 0x00000000 +#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00007000L +#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0x0000000c +#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0x00000e00L +#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x00000009 +#define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x00000001L +#define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x00000000 +#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x00078000L +#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0x0000000f +#define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x00000100L +#define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x00000008 +#define MC_VM_MB_L1_TLB3_STATUS__BUSY_MASK 0x00000001L +#define MC_VM_MB_L1_TLB3_STATUS__BUSY__SHIFT 0x00000000 +#define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x0000003fL +#define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x00000000 +#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00007000L +#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0x0000000c +#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0x00000e00L +#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x00000009 +#define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x00000001L +#define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x00000000 +#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x00078000L +#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0x0000000f +#define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x00000100L +#define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x00000008 +#define MC_VM_MD_L1_TLB0_STATUS__BUSY_MASK 0x00000001L +#define MC_VM_MD_L1_TLB0_STATUS__BUSY__SHIFT 0x00000000 +#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00007000L +#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0x0000000c +#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0x00000e00L +#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x00000009 +#define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB_MASK 0x00000001L +#define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x00000000 +#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG_MASK 0x00078000L +#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG__SHIFT 0x0000000f +#define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN_MASK 0x00000100L +#define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x00000008 +#define MC_VM_MD_L1_TLB1_STATUS__BUSY_MASK 0x00000001L +#define MC_VM_MD_L1_TLB1_STATUS__BUSY__SHIFT 0x00000000 +#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00007000L +#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0x0000000c +#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0x00000e00L +#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x00000009 +#define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x00000001L +#define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x00000000 +#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x00078000L +#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0x0000000f +#define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x00000100L +#define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x00000008 +#define MC_VM_MD_L1_TLB2_STATUS__BUSY_MASK 0x00000001L +#define MC_VM_MD_L1_TLB2_STATUS__BUSY__SHIFT 0x00000000 +#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00007000L +#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0x0000000c +#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0x00000e00L +#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x00000009 +#define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x00000001L +#define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x00000000 +#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x00078000L +#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0x0000000f +#define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x00000100L +#define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x00000008 +#define MC_VM_MD_L1_TLB3_STATUS__BUSY_MASK 0x00000001L +#define MC_VM_MD_L1_TLB3_STATUS__BUSY__SHIFT 0x00000000 +#define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x0000003fL +#define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x00000000 +#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L +#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x00000007 +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x00000006 +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK 0x00000002L +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING__SHIFT 0x00000001 +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x00000000 +#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x00000003 +#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L +#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x00000005 +#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define MC_WR_CB__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_WR_CB__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_WR_CB__ENABLE_MASK 0x00000001L +#define MC_WR_CB__ENABLE__SHIFT 0x00000000 +#define MC_WR_CB__LAZY_TIMER_MASK 0x00007800L +#define MC_WR_CB__LAZY_TIMER__SHIFT 0x0000000b +#define MC_WR_CB__MAX_BURST_MASK 0x00000780L +#define MC_WR_CB__MAX_BURST__SHIFT 0x00000007 +#define MC_WR_CB__PRESCALE_MASK 0x00000006L +#define MC_WR_CB__PRESCALE__SHIFT 0x00000001 +#define MC_WR_CB__STALL_MODE_MASK 0x00000030L +#define MC_WR_CB__STALL_MODE__SHIFT 0x00000004 +#define MC_WR_CB__STALL_OVERRIDE_MASK 0x00000040L +#define MC_WR_CB__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_WR_CB__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_WR_CB__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_WR_DB__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_WR_DB__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_WR_DB__ENABLE_MASK 0x00000001L +#define MC_WR_DB__ENABLE__SHIFT 0x00000000 +#define MC_WR_DB__LAZY_TIMER_MASK 0x00007800L +#define MC_WR_DB__LAZY_TIMER__SHIFT 0x0000000b +#define MC_WR_DB__MAX_BURST_MASK 0x00000780L +#define MC_WR_DB__MAX_BURST__SHIFT 0x00000007 +#define MC_WR_DB__PRESCALE_MASK 0x00000006L +#define MC_WR_DB__PRESCALE__SHIFT 0x00000001 +#define MC_WR_DB__STALL_MODE_MASK 0x00000030L +#define MC_WR_DB__STALL_MODE__SHIFT 0x00000004 +#define MC_WR_DB__STALL_OVERRIDE_MASK 0x00000040L +#define MC_WR_DB__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_WR_DB__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_WR_DB__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_WR_GRP_EXT__DBSTEN0_MASK 0x0000000fL +#define MC_WR_GRP_EXT__DBSTEN0__SHIFT 0x00000000 +#define MC_WR_GRP_EXT__TC0_MASK 0x000000f0L +#define MC_WR_GRP_EXT__TC0__SHIFT 0x00000004 +#define MC_WR_GRP_GFX__CP_MASK 0x0000000fL +#define MC_WR_GRP_GFX__CP__SHIFT 0x00000000 +#define MC_WR_GRP_GFX__XDMA_MASK 0x0000f000L +#define MC_WR_GRP_GFX__XDMAM_MASK 0x000f0000L +#define MC_WR_GRP_GFX__XDMAM__SHIFT 0x00000010 +#define MC_WR_GRP_GFX__XDMA__SHIFT 0x0000000c +#define MC_WR_GRP_LCL__CB0_MASK 0x0000000fL +#define MC_WR_GRP_LCL__CB0__SHIFT 0x00000000 +#define MC_WR_GRP_LCL__CBCMASK0_MASK 0x000000f0L +#define MC_WR_GRP_LCL__CBCMASK0__SHIFT 0x00000004 +#define MC_WR_GRP_LCL__CBFMASK0_MASK 0x00000f00L +#define MC_WR_GRP_LCL__CBFMASK0__SHIFT 0x00000008 +#define MC_WR_GRP_LCL__CBIMMED0_MASK 0xf0000000L +#define MC_WR_GRP_LCL__CBIMMED0__SHIFT 0x0000001c +#define MC_WR_GRP_LCL__DB0_MASK 0x0000f000L +#define MC_WR_GRP_LCL__DB0__SHIFT 0x0000000c +#define MC_WR_GRP_LCL__DBHTILE0_MASK 0x000f0000L +#define MC_WR_GRP_LCL__DBHTILE0__SHIFT 0x00000010 +#define MC_WR_GRP_LCL__SX0_MASK 0x00f00000L +#define MC_WR_GRP_LCL__SX0__SHIFT 0x00000014 +#define MC_WR_GRP_OTH__HDP_MASK 0x00000f00L +#define MC_WR_GRP_OTH__HDP__SHIFT 0x00000008 +#define MC_WR_GRP_OTH__SEM_MASK 0x0000f000L +#define MC_WR_GRP_OTH__SEM__SHIFT 0x0000000c +#define MC_WR_GRP_OTH__UMC_MASK 0x000f0000L +#define MC_WR_GRP_OTH__UMC__SHIFT 0x00000010 +#define MC_WR_GRP_OTH__UVD_EXT0_MASK 0x0000000fL +#define MC_WR_GRP_OTH__UVD_EXT0__SHIFT 0x00000000 +#define MC_WR_GRP_OTH__UVD_EXT1_MASK 0xf0000000L +#define MC_WR_GRP_OTH__UVD_EXT1__SHIFT 0x0000001c +#define MC_WR_GRP_OTH__UVD_MASK 0x00f00000L +#define MC_WR_GRP_OTH__UVD__SHIFT 0x00000014 +#define MC_WR_GRP_OTH__XDP_MASK 0x0f000000L +#define MC_WR_GRP_OTH__XDP__SHIFT 0x00000018 +#define MC_WR_GRP_SYS__IH_MASK 0x0000000fL +#define MC_WR_GRP_SYS__IH__SHIFT 0x00000000 +#define MC_WR_GRP_SYS__MCIF_MASK 0x000000f0L +#define MC_WR_GRP_SYS__MCIF__SHIFT 0x00000004 +#define MC_WR_GRP_SYS__RLC_MASK 0x00000f00L +#define MC_WR_GRP_SYS__RLC__SHIFT 0x00000008 +#define MC_WR_GRP_SYS__SMU_MASK 0x00f00000L +#define MC_WR_GRP_SYS__SMU__SHIFT 0x00000014 +#define MC_WR_GRP_SYS__VCE_MASK 0x0f000000L +#define MC_WR_GRP_SYS__VCE__SHIFT 0x00000018 +#define MC_WR_GRP_SYS__VCEU_MASK 0xf0000000L +#define MC_WR_GRP_SYS__VCEU__SHIFT 0x0000001c +#define MC_WR_HUB__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_WR_HUB__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_WR_HUB__ENABLE_MASK 0x00000001L +#define MC_WR_HUB__ENABLE__SHIFT 0x00000000 +#define MC_WR_HUB__LAZY_TIMER_MASK 0x00007800L +#define MC_WR_HUB__LAZY_TIMER__SHIFT 0x0000000b +#define MC_WR_HUB__MAX_BURST_MASK 0x00000780L +#define MC_WR_HUB__MAX_BURST__SHIFT 0x00000007 +#define MC_WR_HUB__PRESCALE_MASK 0x00000006L +#define MC_WR_HUB__PRESCALE__SHIFT 0x00000001 +#define MC_WR_HUB__STALL_MODE_MASK 0x00000030L +#define MC_WR_HUB__STALL_MODE__SHIFT 0x00000004 +#define MC_WR_HUB__STALL_OVERRIDE_MASK 0x00000040L +#define MC_WR_HUB__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_WR_HUB__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_WR_HUB__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_WR_TC0__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_WR_TC0__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_WR_TC0__ENABLE_MASK 0x00000001L +#define MC_WR_TC0__ENABLE__SHIFT 0x00000000 +#define MC_WR_TC0__LAZY_TIMER_MASK 0x00007800L +#define MC_WR_TC0__LAZY_TIMER__SHIFT 0x0000000b +#define MC_WR_TC0__MAX_BURST_MASK 0x00000780L +#define MC_WR_TC0__MAX_BURST__SHIFT 0x00000007 +#define MC_WR_TC0__PRESCALE_MASK 0x00000006L +#define MC_WR_TC0__PRESCALE__SHIFT 0x00000001 +#define MC_WR_TC0__STALL_MODE_MASK 0x00000030L +#define MC_WR_TC0__STALL_MODE__SHIFT 0x00000004 +#define MC_WR_TC0__STALL_OVERRIDE_MASK 0x00000040L +#define MC_WR_TC0__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_WR_TC0__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_WR_TC0__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_WR_TC1__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_WR_TC1__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_WR_TC1__ENABLE_MASK 0x00000001L +#define MC_WR_TC1__ENABLE__SHIFT 0x00000000 +#define MC_WR_TC1__LAZY_TIMER_MASK 0x00007800L +#define MC_WR_TC1__LAZY_TIMER__SHIFT 0x0000000b +#define MC_WR_TC1__MAX_BURST_MASK 0x00000780L +#define MC_WR_TC1__MAX_BURST__SHIFT 0x00000007 +#define MC_WR_TC1__PRESCALE_MASK 0x00000006L +#define MC_WR_TC1__PRESCALE__SHIFT 0x00000001 +#define MC_WR_TC1__STALL_MODE_MASK 0x00000030L +#define MC_WR_TC1__STALL_MODE__SHIFT 0x00000004 +#define MC_WR_TC1__STALL_OVERRIDE_MASK 0x00000040L +#define MC_WR_TC1__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_WR_TC1__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_WR_TC1__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_XBAR_ADDR_DEC__GECC_MASK 0x00000002L +#define MC_XBAR_ADDR_DEC__GECC__SHIFT 0x00000001 +#define MC_XBAR_ADDR_DEC__NO_DIV_BY_3_MASK 0x00000001L +#define MC_XBAR_ADDR_DEC__NO_DIV_BY_3__SHIFT 0x00000000 +#define MC_XBAR_ADDR_DEC__RB_SPLIT_COLHI_MASK 0x00000008L +#define MC_XBAR_ADDR_DEC__RB_SPLIT_COLHI__SHIFT 0x00000003 +#define MC_XBAR_ADDR_DEC__RB_SPLIT_MASK 0x00000004L +#define MC_XBAR_ADDR_DEC__RB_SPLIT__SHIFT 0x00000002 +#define MC_XBAR_ARB__BREAK_BURST_CID_CHANGE_MASK 0x00000004L +#define MC_XBAR_ARB__BREAK_BURST_CID_CHANGE__SHIFT 0x00000002 +#define MC_XBAR_ARB__DISABLE_HUB_STALL_HIGHEST_MASK 0x00000002L +#define MC_XBAR_ARB__DISABLE_HUB_STALL_HIGHEST__SHIFT 0x00000001 +#define MC_XBAR_ARB__HUBRD_HIGHEST_MASK 0x00000001L +#define MC_XBAR_ARB__HUBRD_HIGHEST__SHIFT 0x00000000 +#define MC_XBAR_ARB_MAX_BURST__RD_PORT0_MASK 0x0000000fL +#define MC_XBAR_ARB_MAX_BURST__RD_PORT0__SHIFT 0x00000000 +#define MC_XBAR_ARB_MAX_BURST__RD_PORT1_MASK 0x000000f0L +#define MC_XBAR_ARB_MAX_BURST__RD_PORT1__SHIFT 0x00000004 +#define MC_XBAR_ARB_MAX_BURST__RD_PORT2_MASK 0x00000f00L +#define MC_XBAR_ARB_MAX_BURST__RD_PORT2__SHIFT 0x00000008 +#define MC_XBAR_ARB_MAX_BURST__RD_PORT3_MASK 0x0000f000L +#define MC_XBAR_ARB_MAX_BURST__RD_PORT3__SHIFT 0x0000000c +#define MC_XBAR_ARB_MAX_BURST__WR_PORT0_MASK 0x000f0000L +#define MC_XBAR_ARB_MAX_BURST__WR_PORT0__SHIFT 0x00000010 +#define MC_XBAR_ARB_MAX_BURST__WR_PORT1_MASK 0x00f00000L +#define MC_XBAR_ARB_MAX_BURST__WR_PORT1__SHIFT 0x00000014 +#define MC_XBAR_ARB_MAX_BURST__WR_PORT2_MASK 0x0f000000L +#define MC_XBAR_ARB_MAX_BURST__WR_PORT2__SHIFT 0x00000018 +#define MC_XBAR_ARB_MAX_BURST__WR_PORT3_MASK 0xf0000000L +#define MC_XBAR_ARB_MAX_BURST__WR_PORT3__SHIFT 0x0000001c +#define MC_XBAR_CHTRIREMAP__CH0_MASK 0x00000003L +#define MC_XBAR_CHTRIREMAP__CH0__SHIFT 0x00000000 +#define MC_XBAR_CHTRIREMAP__CH1_MASK 0x0000000cL +#define MC_XBAR_CHTRIREMAP__CH1__SHIFT 0x00000002 +#define MC_XBAR_CHTRIREMAP__CH2_MASK 0x00000030L +#define MC_XBAR_CHTRIREMAP__CH2__SHIFT 0x00000004 +#define MC_XBAR_PERF_MON_CNTL0__ALLOW_WRAP_MASK 0x10000000L +#define MC_XBAR_PERF_MON_CNTL0__ALLOW_WRAP__SHIFT 0x0000001c +#define MC_XBAR_PERF_MON_CNTL0__START_MODE_MASK 0x03000000L +#define MC_XBAR_PERF_MON_CNTL0__START_MODE__SHIFT 0x00000018 +#define MC_XBAR_PERF_MON_CNTL0__START_THRESH_MASK 0x00000fffL +#define MC_XBAR_PERF_MON_CNTL0__START_THRESH__SHIFT 0x00000000 +#define MC_XBAR_PERF_MON_CNTL0__STOP_MODE_MASK 0x0c000000L +#define MC_XBAR_PERF_MON_CNTL0__STOP_MODE__SHIFT 0x0000001a +#define MC_XBAR_PERF_MON_CNTL0__STOP_THRESH_MASK 0x00fff000L +#define MC_XBAR_PERF_MON_CNTL0__STOP_THRESH__SHIFT 0x0000000c +#define MC_XBAR_PERF_MON_CNTL1__START_TRIG_ID_MASK 0x0000ff00L +#define MC_XBAR_PERF_MON_CNTL1__START_TRIG_ID__SHIFT 0x00000008 +#define MC_XBAR_PERF_MON_CNTL1__STOP_TRIG_ID_MASK 0x00ff0000L +#define MC_XBAR_PERF_MON_CNTL1__STOP_TRIG_ID__SHIFT 0x00000010 +#define MC_XBAR_PERF_MON_CNTL1__THRESH_CNTR_ID_MASK 0x000000ffL +#define MC_XBAR_PERF_MON_CNTL1__THRESH_CNTR_ID__SHIFT 0x00000000 +#define MC_XBAR_PERF_MON_CNTL2__MON0_ID_MASK 0x000000ffL +#define MC_XBAR_PERF_MON_CNTL2__MON0_ID__SHIFT 0x00000000 +#define MC_XBAR_PERF_MON_CNTL2__MON1_ID_MASK 0x0000ff00L +#define MC_XBAR_PERF_MON_CNTL2__MON1_ID__SHIFT 0x00000008 +#define MC_XBAR_PERF_MON_CNTL2__MON2_ID_MASK 0x00ff0000L +#define MC_XBAR_PERF_MON_CNTL2__MON2_ID__SHIFT 0x00000010 +#define MC_XBAR_PERF_MON_CNTL2__MON3_ID_MASK 0xff000000L +#define MC_XBAR_PERF_MON_CNTL2__MON3_ID__SHIFT 0x00000018 +#define MC_XBAR_PERF_MON_MAX_THSH__MON0_MASK 0x000000ffL +#define MC_XBAR_PERF_MON_MAX_THSH__MON0__SHIFT 0x00000000 +#define MC_XBAR_PERF_MON_MAX_THSH__MON1_MASK 0x0000ff00L +#define MC_XBAR_PERF_MON_MAX_THSH__MON1__SHIFT 0x00000008 +#define MC_XBAR_PERF_MON_MAX_THSH__MON2_MASK 0x00ff0000L +#define MC_XBAR_PERF_MON_MAX_THSH__MON2__SHIFT 0x00000010 +#define MC_XBAR_PERF_MON_MAX_THSH__MON3_MASK 0xff000000L +#define MC_XBAR_PERF_MON_MAX_THSH__MON3__SHIFT 0x00000018 +#define MC_XBAR_PERF_MON_RSLT0__COUNT_MASK 0xffffffffL +#define MC_XBAR_PERF_MON_RSLT0__COUNT__SHIFT 0x00000000 +#define MC_XBAR_PERF_MON_RSLT1__COUNT_MASK 0xffffffffL +#define MC_XBAR_PERF_MON_RSLT1__COUNT__SHIFT 0x00000000 +#define MC_XBAR_PERF_MON_RSLT2__COUNT_MASK 0xffffffffL +#define MC_XBAR_PERF_MON_RSLT2__COUNT__SHIFT 0x00000000 +#define MC_XBAR_PERF_MON_RSLT3__COUNT_MASK 0xffffffffL +#define MC_XBAR_PERF_MON_RSLT3__COUNT__SHIFT 0x00000000 +#define MC_XBAR_RDREQ_CREDIT__OUT0_MASK 0x000000ffL +#define MC_XBAR_RDREQ_CREDIT__OUT0__SHIFT 0x00000000 +#define MC_XBAR_RDREQ_CREDIT__OUT1_MASK 0x0000ff00L +#define MC_XBAR_RDREQ_CREDIT__OUT1__SHIFT 0x00000008 +#define MC_XBAR_RDREQ_CREDIT__OUT2_MASK 0x00ff0000L +#define MC_XBAR_RDREQ_CREDIT__OUT2__SHIFT 0x00000010 +#define MC_XBAR_RDREQ_CREDIT__OUT3_MASK 0xff000000L +#define MC_XBAR_RDREQ_CREDIT__OUT3__SHIFT 0x00000018 +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT0_MASK 0x000000ffL +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT0__SHIFT 0x00000000 +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT1_MASK 0x0000ff00L +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT1__SHIFT 0x00000008 +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT2_MASK 0x00ff0000L +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT2__SHIFT 0x00000010 +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT3_MASK 0xff000000L +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT3__SHIFT 0x00000018 +#define MC_XBAR_RDRET_CREDIT1__OUT0_MASK 0x000000ffL +#define MC_XBAR_RDRET_CREDIT1__OUT0__SHIFT 0x00000000 +#define MC_XBAR_RDRET_CREDIT1__OUT1_MASK 0x0000ff00L +#define MC_XBAR_RDRET_CREDIT1__OUT1__SHIFT 0x00000008 +#define MC_XBAR_RDRET_CREDIT1__OUT2_MASK 0x00ff0000L +#define MC_XBAR_RDRET_CREDIT1__OUT2__SHIFT 0x00000010 +#define MC_XBAR_RDRET_CREDIT1__OUT3_MASK 0xff000000L +#define MC_XBAR_RDRET_CREDIT1__OUT3__SHIFT 0x00000018 +#define MC_XBAR_RDRET_CREDIT2__HUB_LP_RDRET_SKID_MASK 0x00ff0000L +#define MC_XBAR_RDRET_CREDIT2__HUB_LP_RDRET_SKID__SHIFT 0x00000010 +#define MC_XBAR_RDRET_CREDIT2__OUT4_MASK 0x000000ffL +#define MC_XBAR_RDRET_CREDIT2__OUT4__SHIFT 0x00000000 +#define MC_XBAR_RDRET_CREDIT2__OUT5_MASK 0x0000ff00L +#define MC_XBAR_RDRET_CREDIT2__OUT5__SHIFT 0x00000008 +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT0_MASK 0x000000ffL +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT0__SHIFT 0x00000000 +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT1_MASK 0x0000ff00L +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT1__SHIFT 0x00000008 +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT2_MASK 0x00ff0000L +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT2__SHIFT 0x00000010 +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT3_MASK 0xff000000L +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT3__SHIFT 0x00000018 +#define MC_XBAR_RDRET_PRI_CREDIT2__OUT4_MASK 0x000000ffL +#define MC_XBAR_RDRET_PRI_CREDIT2__OUT4__SHIFT 0x00000000 +#define MC_XBAR_RDRET_PRI_CREDIT2__OUT5_MASK 0x0000ff00L +#define MC_XBAR_RDRET_PRI_CREDIT2__OUT5__SHIFT 0x00000008 +#define MC_XBAR_REMOTE__RDREQ_EN_GOQ_MASK 0x00000002L +#define MC_XBAR_REMOTE__RDREQ_EN_GOQ__SHIFT 0x00000001 +#define MC_XBAR_REMOTE__WRREQ_EN_GOQ_MASK 0x00000001L +#define MC_XBAR_REMOTE__WRREQ_EN_GOQ__SHIFT 0x00000000 +#define MC_XBAR_SPARE0__BIT_MASK 0xffffffffL +#define MC_XBAR_SPARE0__BIT__SHIFT 0x00000000 +#define MC_XBAR_SPARE1__BIT_MASK 0xffffffffL +#define MC_XBAR_SPARE1__BIT__SHIFT 0x00000000 +#define MC_XBAR_TWOCHAN__CH0_MASK 0x00000006L +#define MC_XBAR_TWOCHAN__CH0__SHIFT 0x00000001 +#define MC_XBAR_TWOCHAN__CH1_MASK 0x00000018L +#define MC_XBAR_TWOCHAN__CH1__SHIFT 0x00000003 +#define MC_XBAR_TWOCHAN__DISABLE_ONEPORT_MASK 0x00000001L +#define MC_XBAR_TWOCHAN__DISABLE_ONEPORT__SHIFT 0x00000000 +#define MC_XBAR_WRREQ_CREDIT__OUT0_MASK 0x000000ffL +#define MC_XBAR_WRREQ_CREDIT__OUT0__SHIFT 0x00000000 +#define MC_XBAR_WRREQ_CREDIT__OUT1_MASK 0x0000ff00L +#define MC_XBAR_WRREQ_CREDIT__OUT1__SHIFT 0x00000008 +#define MC_XBAR_WRREQ_CREDIT__OUT2_MASK 0x00ff0000L +#define MC_XBAR_WRREQ_CREDIT__OUT2__SHIFT 0x00000010 +#define MC_XBAR_WRREQ_CREDIT__OUT3_MASK 0xff000000L +#define MC_XBAR_WRREQ_CREDIT__OUT3__SHIFT 0x00000018 +#define MC_XBAR_WRRET_CREDIT1__OUT0_MASK 0x000000ffL +#define MC_XBAR_WRRET_CREDIT1__OUT0__SHIFT 0x00000000 +#define MC_XBAR_WRRET_CREDIT1__OUT1_MASK 0x0000ff00L +#define MC_XBAR_WRRET_CREDIT1__OUT1__SHIFT 0x00000008 +#define MC_XBAR_WRRET_CREDIT1__OUT2_MASK 0x00ff0000L +#define MC_XBAR_WRRET_CREDIT1__OUT2__SHIFT 0x00000010 +#define MC_XBAR_WRRET_CREDIT1__OUT3_MASK 0xff000000L +#define MC_XBAR_WRRET_CREDIT1__OUT3__SHIFT 0x00000018 +#define MC_XBAR_WRRET_CREDIT2__OUT4_MASK 0x000000ffL +#define MC_XBAR_WRRET_CREDIT2__OUT4__SHIFT 0x00000000 +#define MC_XBAR_WRRET_CREDIT2__OUT5_MASK 0x0000ff00L +#define MC_XBAR_WRRET_CREDIT2__OUT5__SHIFT 0x00000008 +#define MC_XPB_CLG_CFG0__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG0__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG0__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG0__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG0__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG0__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG0__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG0__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG0__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG10__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG10__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG10__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG10__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG10__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG10__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG10__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG10__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG10__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG10__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG11__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG11__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG11__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG11__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG11__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG11__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG11__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG11__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG11__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG11__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG12__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG12__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG12__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG12__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG12__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG12__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG12__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG12__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG12__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG12__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG13__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG13__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG13__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG13__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG13__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG13__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG13__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG13__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG13__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG13__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG14__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG14__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG14__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG14__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG14__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG14__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG14__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG14__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG14__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG14__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG15__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG15__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG15__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG15__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG15__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG15__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG15__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG15__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG15__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG15__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG16__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG16__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG16__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG16__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG16__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG16__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG16__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG16__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG16__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG16__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG17__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG17__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG17__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG17__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG17__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG17__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG17__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG17__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG17__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG17__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG18__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG18__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG18__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG18__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG18__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG18__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG18__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG18__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG18__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG18__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG19__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG19__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG19__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG19__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG19__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG19__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG19__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG19__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG19__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG19__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG1__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG1__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG1__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG1__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG1__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG1__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG1__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG1__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG1__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG20__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG20__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG20__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG20__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG20__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG20__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG20__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG20__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG20__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG20__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG21__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG21__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG21__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG21__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG21__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG21__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG21__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG21__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG21__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG21__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG22__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG22__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG22__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG22__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG22__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG22__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG22__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG22__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG22__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG22__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG23__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG23__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG23__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG23__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG23__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG23__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG23__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG23__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG23__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG23__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG24__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG24__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG24__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG24__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG24__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG24__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG24__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG24__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG24__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG24__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG25__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG25__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG25__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG25__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG25__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG25__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG25__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG25__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG25__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG25__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG26__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG26__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG26__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG26__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG26__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG26__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG26__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG26__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG26__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG26__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG27__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG27__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG27__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG27__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG27__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG27__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG27__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG27__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG27__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG27__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG28__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG28__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG28__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG28__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG28__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG28__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG28__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG28__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG28__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG28__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG29__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG29__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG29__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG29__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG29__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG29__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG29__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG29__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG29__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG29__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG2__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG2__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG2__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG2__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG2__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG2__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG2__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG2__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG2__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG30__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG30__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG30__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG30__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG30__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG30__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG30__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG30__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG30__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG30__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG31__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG31__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG31__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG31__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG31__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG31__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG31__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG31__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG31__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG31__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG32__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG32__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG32__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG32__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG32__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG32__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG32__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG32__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG32__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG32__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG33__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG33__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG33__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG33__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG33__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG33__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG33__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG33__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG33__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG33__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG34__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG34__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG34__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG34__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG34__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG34__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG34__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG34__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG34__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG34__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG35__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG35__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG35__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG35__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG35__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG35__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG35__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG35__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG35__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG35__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG36__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG36__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG36__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG36__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG36__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG36__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG36__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG36__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG36__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG36__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG3__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG3__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG3__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG3__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG3__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG3__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG3__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG3__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG3__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG4__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG4__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG4__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG4__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG4__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG4__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG4__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG4__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG4__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG5__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG5__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG5__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG5__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG5__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG5__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG5__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG5__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG5__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG6__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG6__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG6__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG6__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG6__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG6__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG6__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG6__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG6__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG7__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG7__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG7__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG7__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG7__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG7__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG7__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG7__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG7__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG8__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG8__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG8__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG8__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG8__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG8__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG8__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG8__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG8__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG8__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG9__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG9__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG9__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG9__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG9__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG9__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG9__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG9__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG9__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG9__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_EXTRA__CMP0_MASK 0x000000ffL +#define MC_XPB_CLG_EXTRA__CMP0__SHIFT 0x00000000 +#define MC_XPB_CLG_EXTRA__CMP1_MASK 0x01fe0000L +#define MC_XPB_CLG_EXTRA__CMP1__SHIFT 0x00000011 +#define MC_XPB_CLG_EXTRA__MSK0_MASK 0x0000ff00L +#define MC_XPB_CLG_EXTRA__MSK0__SHIFT 0x00000008 +#define MC_XPB_CLG_EXTRA_RD__CMP0_MASK 0x000000ffL +#define MC_XPB_CLG_EXTRA_RD__CMP0__SHIFT 0x00000000 +#define MC_XPB_CLG_EXTRA_RD__CMP1_MASK 0x01fe0000L +#define MC_XPB_CLG_EXTRA_RD__CMP1__SHIFT 0x00000011 +#define MC_XPB_CLG_EXTRA_RD__MSK0_MASK 0x0000ff00L +#define MC_XPB_CLG_EXTRA_RD__MSK0__SHIFT 0x00000008 +#define MC_XPB_CLG_EXTRA_RD__VLD0_MASK 0x00010000L +#define MC_XPB_CLG_EXTRA_RD__VLD0__SHIFT 0x00000010 +#define MC_XPB_CLG_EXTRA_RD__VLD1_MASK 0x02000000L +#define MC_XPB_CLG_EXTRA_RD__VLD1__SHIFT 0x00000019 +#define MC_XPB_CLG_EXTRA__VLD0_MASK 0x00010000L +#define MC_XPB_CLG_EXTRA__VLD0__SHIFT 0x00000010 +#define MC_XPB_CLG_EXTRA__VLD1_MASK 0x02000000L +#define MC_XPB_CLG_EXTRA__VLD1__SHIFT 0x00000019 +#define MC_XPB_CLK_GAT__ENABLE_MASK 0x00040000L +#define MC_XPB_CLK_GAT__ENABLE__SHIFT 0x00000012 +#define MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK 0x00080000L +#define MC_XPB_CLK_GAT__MEM_LS_ENABLE__SHIFT 0x00000013 +#define MC_XPB_CLK_GAT__OFFDLY_MASK 0x00000fc0L +#define MC_XPB_CLK_GAT__OFFDLY__SHIFT 0x00000006 +#define MC_XPB_CLK_GAT__ONDLY_MASK 0x0000003fL +#define MC_XPB_CLK_GAT__ONDLY__SHIFT 0x00000000 +#define MC_XPB_CLK_GAT__RDYDLY_MASK 0x0003f000L +#define MC_XPB_CLK_GAT__RDYDLY__SHIFT 0x0000000c +#define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD_MASK 0x000000ffL +#define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD__SHIFT 0x00000000 +#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL_MASK 0x02000000L +#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL__SHIFT 0x00000019 +#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL_MASK 0x04000000L +#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL__SHIFT 0x0000001a +#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL_MASK 0x00800000L +#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL__SHIFT 0x00000017 +#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL_MASK 0x01000000L +#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL__SHIFT 0x00000018 +#define MC_XPB_INTF_CFG__MC_WRRET_ASK_MASK 0x0000ff00L +#define MC_XPB_INTF_CFG__MC_WRRET_ASK__SHIFT 0x00000008 +#define MC_XPB_INTF_CFG__RPB_WRREQ_CRD_MASK 0x000000ffL +#define MC_XPB_INTF_CFG__RPB_WRREQ_CRD__SHIFT 0x00000000 +#define MC_XPB_INTF_CFG__XSP_ORDERING_SEL_MASK 0x40000000L +#define MC_XPB_INTF_CFG__XSP_ORDERING_SEL__SHIFT 0x0000001e +#define MC_XPB_INTF_CFG__XSP_ORDERING_VAL_MASK 0x80000000L +#define MC_XPB_INTF_CFG__XSP_ORDERING_VAL__SHIFT 0x0000001f +#define MC_XPB_INTF_CFG__XSP_REQ_CRD_MASK 0x007f0000L +#define MC_XPB_INTF_CFG__XSP_REQ_CRD__SHIFT 0x00000010 +#define MC_XPB_INTF_CFG__XSP_SNOOP_SEL_MASK 0x18000000L +#define MC_XPB_INTF_CFG__XSP_SNOOP_SEL__SHIFT 0x0000001b +#define MC_XPB_INTF_CFG__XSP_SNOOP_VAL_MASK 0x20000000L +#define MC_XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x0000001d +#define MC_XPB_INTF_STS__CNS_BUF_BUSY_MASK 0x00040000L +#define MC_XPB_INTF_STS__CNS_BUF_BUSY__SHIFT 0x00000012 +#define MC_XPB_INTF_STS__CNS_BUF_FULL_MASK 0x00020000L +#define MC_XPB_INTF_STS__CNS_BUF_FULL__SHIFT 0x00000011 +#define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL_MASK 0x00010000L +#define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL__SHIFT 0x00000010 +#define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL_MASK 0x00008000L +#define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL__SHIFT 0x0000000f +#define MC_XPB_INTF_STS__RPB_RDREQ_CRD_MASK 0x07f80000L +#define MC_XPB_INTF_STS__RPB_RDREQ_CRD__SHIFT 0x00000013 +#define MC_XPB_INTF_STS__RPB_WRREQ_CRD_MASK 0x000000ffL +#define MC_XPB_INTF_STS__RPB_WRREQ_CRD__SHIFT 0x00000000 +#define MC_XPB_INTF_STS__XSP_REQ_CRD_MASK 0x00007f00L +#define MC_XPB_INTF_STS__XSP_REQ_CRD__SHIFT 0x00000008 +#define MC_XPB_LB_ADDR__CMP0_MASK 0x000003ffL +#define MC_XPB_LB_ADDR__CMP0__SHIFT 0x00000000 +#define MC_XPB_LB_ADDR__CMP1_MASK 0x03f00000L +#define MC_XPB_LB_ADDR__CMP1__SHIFT 0x00000014 +#define MC_XPB_LB_ADDR__MASK0_MASK 0x000ffc00L +#define MC_XPB_LB_ADDR__MASK0__SHIFT 0x0000000a +#define MC_XPB_LB_ADDR__MASK1_MASK 0xfc000000L +#define MC_XPB_LB_ADDR__MASK1__SHIFT 0x0000001a +#define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM_MASK 0x0000ffffL +#define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM__SHIFT 0x00000000 +#define MC_XPB_MISC_CFG__FIELDNAME0_MASK 0x000000ffL +#define MC_XPB_MISC_CFG__FIELDNAME0__SHIFT 0x00000000 +#define MC_XPB_MISC_CFG__FIELDNAME1_MASK 0x0000ff00L +#define MC_XPB_MISC_CFG__FIELDNAME1__SHIFT 0x00000008 +#define MC_XPB_MISC_CFG__FIELDNAME2_MASK 0x00ff0000L +#define MC_XPB_MISC_CFG__FIELDNAME2__SHIFT 0x00000010 +#define MC_XPB_MISC_CFG__FIELDNAME3_MASK 0x7f000000L +#define MC_XPB_MISC_CFG__FIELDNAME3__SHIFT 0x00000018 +#define MC_XPB_MISC_CFG__TRIGGERNAME_MASK 0x80000000L +#define MC_XPB_MISC_CFG__TRIGGERNAME__SHIFT 0x0000001f +#define MC_XPB_P2P_BAR0__ADDRESS_MASK 0xffff0000L +#define MC_XPB_P2P_BAR0__ADDRESS__SHIFT 0x00000010 +#define MC_XPB_P2P_BAR0__COMPRESS_DIS_MASK 0x00004000L +#define MC_XPB_P2P_BAR0__COMPRESS_DIS__SHIFT 0x0000000e +#define MC_XPB_P2P_BAR0__HOST_FLUSH_MASK 0x0000000fL +#define MC_XPB_P2P_BAR0__HOST_FLUSH__SHIFT 0x00000000 +#define MC_XPB_P2P_BAR0__MEM_SYS_BAR_MASK 0x00000f00L +#define MC_XPB_P2P_BAR0__MEM_SYS_BAR__SHIFT 0x00000008 +#define MC_XPB_P2P_BAR0__REG_SYS_BAR_MASK 0x000000f0L +#define MC_XPB_P2P_BAR0__REG_SYS_BAR__SHIFT 0x00000004 +#define MC_XPB_P2P_BAR0__RESERVED_MASK 0x00008000L +#define MC_XPB_P2P_BAR0__RESERVED__SHIFT 0x0000000f +#define MC_XPB_P2P_BAR0__SEND_DIS_MASK 0x00002000L +#define MC_XPB_P2P_BAR0__SEND_DIS__SHIFT 0x0000000d +#define MC_XPB_P2P_BAR0__VALID_MASK 0x00001000L +#define MC_XPB_P2P_BAR0__VALID__SHIFT 0x0000000c +#define MC_XPB_P2P_BAR1__ADDRESS_MASK 0xffff0000L +#define MC_XPB_P2P_BAR1__ADDRESS__SHIFT 0x00000010 +#define MC_XPB_P2P_BAR1__COMPRESS_DIS_MASK 0x00004000L +#define MC_XPB_P2P_BAR1__COMPRESS_DIS__SHIFT 0x0000000e +#define MC_XPB_P2P_BAR1__HOST_FLUSH_MASK 0x0000000fL +#define MC_XPB_P2P_BAR1__HOST_FLUSH__SHIFT 0x00000000 +#define MC_XPB_P2P_BAR1__MEM_SYS_BAR_MASK 0x00000f00L +#define MC_XPB_P2P_BAR1__MEM_SYS_BAR__SHIFT 0x00000008 +#define MC_XPB_P2P_BAR1__REG_SYS_BAR_MASK 0x000000f0L +#define MC_XPB_P2P_BAR1__REG_SYS_BAR__SHIFT 0x00000004 +#define MC_XPB_P2P_BAR1__RESERVED_MASK 0x00008000L +#define MC_XPB_P2P_BAR1__RESERVED__SHIFT 0x0000000f +#define MC_XPB_P2P_BAR1__SEND_DIS_MASK 0x00002000L +#define MC_XPB_P2P_BAR1__SEND_DIS__SHIFT 0x0000000d +#define MC_XPB_P2P_BAR1__VALID_MASK 0x00001000L +#define MC_XPB_P2P_BAR1__VALID__SHIFT 0x0000000c +#define MC_XPB_P2P_BAR2__ADDRESS_MASK 0xffff0000L +#define MC_XPB_P2P_BAR2__ADDRESS__SHIFT 0x00000010 +#define MC_XPB_P2P_BAR2__COMPRESS_DIS_MASK 0x00004000L +#define MC_XPB_P2P_BAR2__COMPRESS_DIS__SHIFT 0x0000000e +#define MC_XPB_P2P_BAR2__HOST_FLUSH_MASK 0x0000000fL +#define MC_XPB_P2P_BAR2__HOST_FLUSH__SHIFT 0x00000000 +#define MC_XPB_P2P_BAR2__MEM_SYS_BAR_MASK 0x00000f00L +#define MC_XPB_P2P_BAR2__MEM_SYS_BAR__SHIFT 0x00000008 +#define MC_XPB_P2P_BAR2__REG_SYS_BAR_MASK 0x000000f0L +#define MC_XPB_P2P_BAR2__REG_SYS_BAR__SHIFT 0x00000004 +#define MC_XPB_P2P_BAR2__RESERVED_MASK 0x00008000L +#define MC_XPB_P2P_BAR2__RESERVED__SHIFT 0x0000000f +#define MC_XPB_P2P_BAR2__SEND_DIS_MASK 0x00002000L +#define MC_XPB_P2P_BAR2__SEND_DIS__SHIFT 0x0000000d +#define MC_XPB_P2P_BAR2__VALID_MASK 0x00001000L +#define MC_XPB_P2P_BAR2__VALID__SHIFT 0x0000000c +#define MC_XPB_P2P_BAR3__ADDRESS_MASK 0xffff0000L +#define MC_XPB_P2P_BAR3__ADDRESS__SHIFT 0x00000010 +#define MC_XPB_P2P_BAR3__COMPRESS_DIS_MASK 0x00004000L +#define MC_XPB_P2P_BAR3__COMPRESS_DIS__SHIFT 0x0000000e +#define MC_XPB_P2P_BAR3__HOST_FLUSH_MASK 0x0000000fL +#define MC_XPB_P2P_BAR3__HOST_FLUSH__SHIFT 0x00000000 +#define MC_XPB_P2P_BAR3__MEM_SYS_BAR_MASK 0x00000f00L +#define MC_XPB_P2P_BAR3__MEM_SYS_BAR__SHIFT 0x00000008 +#define MC_XPB_P2P_BAR3__REG_SYS_BAR_MASK 0x000000f0L +#define MC_XPB_P2P_BAR3__REG_SYS_BAR__SHIFT 0x00000004 +#define MC_XPB_P2P_BAR3__RESERVED_MASK 0x00008000L +#define MC_XPB_P2P_BAR3__RESERVED__SHIFT 0x0000000f +#define MC_XPB_P2P_BAR3__SEND_DIS_MASK 0x00002000L +#define MC_XPB_P2P_BAR3__SEND_DIS__SHIFT 0x0000000d +#define MC_XPB_P2P_BAR3__VALID_MASK 0x00001000L +#define MC_XPB_P2P_BAR3__VALID__SHIFT 0x0000000c +#define MC_XPB_P2P_BAR4__ADDRESS_MASK 0xffff0000L +#define MC_XPB_P2P_BAR4__ADDRESS__SHIFT 0x00000010 +#define MC_XPB_P2P_BAR4__COMPRESS_DIS_MASK 0x00004000L +#define MC_XPB_P2P_BAR4__COMPRESS_DIS__SHIFT 0x0000000e +#define MC_XPB_P2P_BAR4__HOST_FLUSH_MASK 0x0000000fL +#define MC_XPB_P2P_BAR4__HOST_FLUSH__SHIFT 0x00000000 +#define MC_XPB_P2P_BAR4__MEM_SYS_BAR_MASK 0x00000f00L +#define MC_XPB_P2P_BAR4__MEM_SYS_BAR__SHIFT 0x00000008 +#define MC_XPB_P2P_BAR4__REG_SYS_BAR_MASK 0x000000f0L +#define MC_XPB_P2P_BAR4__REG_SYS_BAR__SHIFT 0x00000004 +#define MC_XPB_P2P_BAR4__RESERVED_MASK 0x00008000L +#define MC_XPB_P2P_BAR4__RESERVED__SHIFT 0x0000000f +#define MC_XPB_P2P_BAR4__SEND_DIS_MASK 0x00002000L +#define MC_XPB_P2P_BAR4__SEND_DIS__SHIFT 0x0000000d +#define MC_XPB_P2P_BAR4__VALID_MASK 0x00001000L +#define MC_XPB_P2P_BAR4__VALID__SHIFT 0x0000000c +#define MC_XPB_P2P_BAR5__ADDRESS_MASK 0xffff0000L +#define MC_XPB_P2P_BAR5__ADDRESS__SHIFT 0x00000010 +#define MC_XPB_P2P_BAR5__COMPRESS_DIS_MASK 0x00004000L +#define MC_XPB_P2P_BAR5__COMPRESS_DIS__SHIFT 0x0000000e +#define MC_XPB_P2P_BAR5__HOST_FLUSH_MASK 0x0000000fL +#define MC_XPB_P2P_BAR5__HOST_FLUSH__SHIFT 0x00000000 +#define MC_XPB_P2P_BAR5__MEM_SYS_BAR_MASK 0x00000f00L +#define MC_XPB_P2P_BAR5__MEM_SYS_BAR__SHIFT 0x00000008 +#define MC_XPB_P2P_BAR5__REG_SYS_BAR_MASK 0x000000f0L +#define MC_XPB_P2P_BAR5__REG_SYS_BAR__SHIFT 0x00000004 +#define MC_XPB_P2P_BAR5__RESERVED_MASK 0x00008000L +#define MC_XPB_P2P_BAR5__RESERVED__SHIFT 0x0000000f +#define MC_XPB_P2P_BAR5__SEND_DIS_MASK 0x00002000L +#define MC_XPB_P2P_BAR5__SEND_DIS__SHIFT 0x0000000d +#define MC_XPB_P2P_BAR5__VALID_MASK 0x00001000L +#define MC_XPB_P2P_BAR5__VALID__SHIFT 0x0000000c +#define MC_XPB_P2P_BAR6__ADDRESS_MASK 0xffff0000L +#define MC_XPB_P2P_BAR6__ADDRESS__SHIFT 0x00000010 +#define MC_XPB_P2P_BAR6__COMPRESS_DIS_MASK 0x00004000L +#define MC_XPB_P2P_BAR6__COMPRESS_DIS__SHIFT 0x0000000e +#define MC_XPB_P2P_BAR6__HOST_FLUSH_MASK 0x0000000fL +#define MC_XPB_P2P_BAR6__HOST_FLUSH__SHIFT 0x00000000 +#define MC_XPB_P2P_BAR6__MEM_SYS_BAR_MASK 0x00000f00L +#define MC_XPB_P2P_BAR6__MEM_SYS_BAR__SHIFT 0x00000008 +#define MC_XPB_P2P_BAR6__REG_SYS_BAR_MASK 0x000000f0L +#define MC_XPB_P2P_BAR6__REG_SYS_BAR__SHIFT 0x00000004 +#define MC_XPB_P2P_BAR6__RESERVED_MASK 0x00008000L +#define MC_XPB_P2P_BAR6__RESERVED__SHIFT 0x0000000f +#define MC_XPB_P2P_BAR6__SEND_DIS_MASK 0x00002000L +#define MC_XPB_P2P_BAR6__SEND_DIS__SHIFT 0x0000000d +#define MC_XPB_P2P_BAR6__VALID_MASK 0x00001000L +#define MC_XPB_P2P_BAR6__VALID__SHIFT 0x0000000c +#define MC_XPB_P2P_BAR7__ADDRESS_MASK 0xffff0000L +#define MC_XPB_P2P_BAR7__ADDRESS__SHIFT 0x00000010 +#define MC_XPB_P2P_BAR7__COMPRESS_DIS_MASK 0x00004000L +#define MC_XPB_P2P_BAR7__COMPRESS_DIS__SHIFT 0x0000000e +#define MC_XPB_P2P_BAR7__HOST_FLUSH_MASK 0x0000000fL +#define MC_XPB_P2P_BAR7__HOST_FLUSH__SHIFT 0x00000000 +#define MC_XPB_P2P_BAR7__MEM_SYS_BAR_MASK 0x00000f00L +#define MC_XPB_P2P_BAR7__MEM_SYS_BAR__SHIFT 0x00000008 +#define MC_XPB_P2P_BAR7__REG_SYS_BAR_MASK 0x000000f0L +#define MC_XPB_P2P_BAR7__REG_SYS_BAR__SHIFT 0x00000004 +#define MC_XPB_P2P_BAR7__RESERVED_MASK 0x00008000L +#define MC_XPB_P2P_BAR7__RESERVED__SHIFT 0x0000000f +#define MC_XPB_P2P_BAR7__SEND_DIS_MASK 0x00002000L +#define MC_XPB_P2P_BAR7__SEND_DIS__SHIFT 0x0000000d +#define MC_XPB_P2P_BAR7__VALID_MASK 0x00001000L +#define MC_XPB_P2P_BAR7__VALID__SHIFT 0x0000000c +#define MC_XPB_P2P_BAR_CFG__ADDR_SIZE_MASK 0x0000000fL +#define MC_XPB_P2P_BAR_CFG__ADDR_SIZE__SHIFT 0x00000000 +#define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED_MASK 0x00001000L +#define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED__SHIFT 0x0000000c +#define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS_MASK 0x00000100L +#define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS__SHIFT 0x00000008 +#define MC_XPB_P2P_BAR_CFG__RD_EN_MASK 0x00000800L +#define MC_XPB_P2P_BAR_CFG__RD_EN__SHIFT 0x0000000b +#define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR_MASK 0x00000400L +#define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0x0000000a +#define MC_XPB_P2P_BAR_CFG__SEND_BAR_MASK 0x00000030L +#define MC_XPB_P2P_BAR_CFG__SEND_BAR__SHIFT 0x00000004 +#define MC_XPB_P2P_BAR_CFG__SEND_DIS_MASK 0x00000080L +#define MC_XPB_P2P_BAR_CFG__SEND_DIS__SHIFT 0x00000007 +#define MC_XPB_P2P_BAR_CFG__SNOOP_MASK 0x00000040L +#define MC_XPB_P2P_BAR_CFG__SNOOP__SHIFT 0x00000006 +#define MC_XPB_P2P_BAR_CFG__UPDATE_DIS_MASK 0x00000200L +#define MC_XPB_P2P_BAR_CFG__UPDATE_DIS__SHIFT 0x00000009 +#define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH_MASK 0x00000f00L +#define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH__SHIFT 0x00000008 +#define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR_MASK 0x0000f000L +#define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR__SHIFT 0x0000000c +#define MC_XPB_P2P_BAR_DEBUG__SEL_MASK 0x000000ffL +#define MC_XPB_P2P_BAR_DEBUG__SEL__SHIFT 0x00000000 +#define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA_MASK 0x0fffff00L +#define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA__SHIFT 0x00000008 +#define MC_XPB_P2P_BAR_DELTA_ABOVE__EN_MASK 0x000000ffL +#define MC_XPB_P2P_BAR_DELTA_ABOVE__EN__SHIFT 0x00000000 +#define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA_MASK 0x0fffff00L +#define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA__SHIFT 0x00000008 +#define MC_XPB_P2P_BAR_DELTA_BELOW__EN_MASK 0x000000ffL +#define MC_XPB_P2P_BAR_DELTA_BELOW__EN__SHIFT 0x00000000 +#define MC_XPB_P2P_BAR_SETUP__ADDRESS_MASK 0xffff0000L +#define MC_XPB_P2P_BAR_SETUP__ADDRESS__SHIFT 0x00000010 +#define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS_MASK 0x00004000L +#define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS__SHIFT 0x0000000e +#define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR_MASK 0x00000f00L +#define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR__SHIFT 0x00000008 +#define MC_XPB_P2P_BAR_SETUP__RESERVED_MASK 0x00008000L +#define MC_XPB_P2P_BAR_SETUP__RESERVED__SHIFT 0x0000000f +#define MC_XPB_P2P_BAR_SETUP__SEL_MASK 0x000000ffL +#define MC_XPB_P2P_BAR_SETUP__SEL__SHIFT 0x00000000 +#define MC_XPB_P2P_BAR_SETUP__SEND_DIS_MASK 0x00002000L +#define MC_XPB_P2P_BAR_SETUP__SEND_DIS__SHIFT 0x0000000d +#define MC_XPB_P2P_BAR_SETUP__VALID_MASK 0x00001000L +#define MC_XPB_P2P_BAR_SETUP__VALID__SHIFT 0x0000000c +#define MC_XPB_PEER_SYS_BAR0__ADDR_MASK 0x07fffffcL +#define MC_XPB_PEER_SYS_BAR0__ADDR__SHIFT 0x00000002 +#define MC_XPB_PEER_SYS_BAR0__SIDE_OK_MASK 0x00000002L +#define MC_XPB_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x00000001 +#define MC_XPB_PEER_SYS_BAR0__VALID_MASK 0x00000001L +#define MC_XPB_PEER_SYS_BAR0__VALID__SHIFT 0x00000000 +#define MC_XPB_PEER_SYS_BAR1__ADDR_MASK 0x07fffffcL +#define MC_XPB_PEER_SYS_BAR1__ADDR__SHIFT 0x00000002 +#define MC_XPB_PEER_SYS_BAR1__SIDE_OK_MASK 0x00000002L +#define MC_XPB_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x00000001 +#define MC_XPB_PEER_SYS_BAR1__VALID_MASK 0x00000001L +#define MC_XPB_PEER_SYS_BAR1__VALID__SHIFT 0x00000000 +#define MC_XPB_PEER_SYS_BAR2__ADDR_MASK 0x07fffffcL +#define MC_XPB_PEER_SYS_BAR2__ADDR__SHIFT 0x00000002 +#define MC_XPB_PEER_SYS_BAR2__SIDE_OK_MASK 0x00000002L +#define MC_XPB_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x00000001 +#define MC_XPB_PEER_SYS_BAR2__VALID_MASK 0x00000001L +#define MC_XPB_PEER_SYS_BAR2__VALID__SHIFT 0x00000000 +#define MC_XPB_PEER_SYS_BAR3__ADDR_MASK 0x07fffffcL +#define MC_XPB_PEER_SYS_BAR3__ADDR__SHIFT 0x00000002 +#define MC_XPB_PEER_SYS_BAR3__SIDE_OK_MASK 0x00000002L +#define MC_XPB_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x00000001 +#define MC_XPB_PEER_SYS_BAR3__VALID_MASK 0x00000001L +#define MC_XPB_PEER_SYS_BAR3__VALID__SHIFT 0x00000000 +#define MC_XPB_PEER_SYS_BAR4__ADDR_MASK 0x07fffffcL +#define MC_XPB_PEER_SYS_BAR4__ADDR__SHIFT 0x00000002 +#define MC_XPB_PEER_SYS_BAR4__SIDE_OK_MASK 0x00000002L +#define MC_XPB_PEER_SYS_BAR4__SIDE_OK__SHIFT 0x00000001 +#define MC_XPB_PEER_SYS_BAR4__VALID_MASK 0x00000001L +#define MC_XPB_PEER_SYS_BAR4__VALID__SHIFT 0x00000000 +#define MC_XPB_PEER_SYS_BAR5__ADDR_MASK 0x07fffffcL +#define MC_XPB_PEER_SYS_BAR5__ADDR__SHIFT 0x00000002 +#define MC_XPB_PEER_SYS_BAR5__SIDE_OK_MASK 0x00000002L +#define MC_XPB_PEER_SYS_BAR5__SIDE_OK__SHIFT 0x00000001 +#define MC_XPB_PEER_SYS_BAR5__VALID_MASK 0x00000001L +#define MC_XPB_PEER_SYS_BAR5__VALID__SHIFT 0x00000000 +#define MC_XPB_PEER_SYS_BAR6__ADDR_MASK 0x07fffffcL +#define MC_XPB_PEER_SYS_BAR6__ADDR__SHIFT 0x00000002 +#define MC_XPB_PEER_SYS_BAR6__SIDE_OK_MASK 0x00000002L +#define MC_XPB_PEER_SYS_BAR6__SIDE_OK__SHIFT 0x00000001 +#define MC_XPB_PEER_SYS_BAR6__VALID_MASK 0x00000001L +#define MC_XPB_PEER_SYS_BAR6__VALID__SHIFT 0x00000000 +#define MC_XPB_PEER_SYS_BAR7__ADDR_MASK 0x07fffffcL +#define MC_XPB_PEER_SYS_BAR7__ADDR__SHIFT 0x00000002 +#define MC_XPB_PEER_SYS_BAR7__SIDE_OK_MASK 0x00000002L +#define MC_XPB_PEER_SYS_BAR7__SIDE_OK__SHIFT 0x00000001 +#define MC_XPB_PEER_SYS_BAR7__VALID_MASK 0x00000001L +#define MC_XPB_PEER_SYS_BAR7__VALID__SHIFT 0x00000000 +#define MC_XPB_PEER_SYS_BAR8__ADDR_MASK 0x07fffffcL +#define MC_XPB_PEER_SYS_BAR8__ADDR__SHIFT 0x00000002 +#define MC_XPB_PEER_SYS_BAR8__SIDE_OK_MASK 0x00000002L +#define MC_XPB_PEER_SYS_BAR8__SIDE_OK__SHIFT 0x00000001 +#define MC_XPB_PEER_SYS_BAR8__VALID_MASK 0x00000001L +#define MC_XPB_PEER_SYS_BAR8__VALID__SHIFT 0x00000000 +#define MC_XPB_PEER_SYS_BAR9__ADDR_MASK 0x07fffffcL +#define MC_XPB_PEER_SYS_BAR9__ADDR__SHIFT 0x00000002 +#define MC_XPB_PEER_SYS_BAR9__SIDE_OK_MASK 0x00000002L +#define MC_XPB_PEER_SYS_BAR9__SIDE_OK__SHIFT 0x00000001 +#define MC_XPB_PEER_SYS_BAR9__VALID_MASK 0x00000001L +#define MC_XPB_PEER_SYS_BAR9__VALID__SHIFT 0x00000000 +#define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH_MASK 0x0000003fL +#define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH__SHIFT 0x00000000 +#define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH_MASK 0x00000fc0L +#define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH__SHIFT 0x00000006 +#define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH_MASK 0x0003f000L +#define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH__SHIFT 0x0000000c +#define MC_XPB_PIPE_STS__RET_BUF_FULL_MASK 0x00800000L +#define MC_XPB_PIPE_STS__RET_BUF_FULL__SHIFT 0x00000017 +#define MC_XPB_PIPE_STS__WCB_ANY_PBUF_MASK 0x00000001L +#define MC_XPB_PIPE_STS__WCB_ANY_PBUF__SHIFT 0x00000000 +#define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT_MASK 0x000000feL +#define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x00000001 +#define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL_MASK 0x00200000L +#define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL__SHIFT 0x00000015 +#define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL_MASK 0x00008000L +#define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL__SHIFT 0x0000000f +#define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL_MASK 0x00020000L +#define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL__SHIFT 0x00000011 +#define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL_MASK 0x00080000L +#define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL__SHIFT 0x00000013 +#define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT_MASK 0x00007f00L +#define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x00000008 +#define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL_MASK 0x00400000L +#define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL__SHIFT 0x00000016 +#define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL_MASK 0x00010000L +#define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL__SHIFT 0x00000010 +#define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL_MASK 0x00040000L +#define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL__SHIFT 0x00000012 +#define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL_MASK 0x00100000L +#define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL__SHIFT 0x00000014 +#define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS_MASK 0xff000000L +#define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS__SHIFT 0x00000018 +#define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000L +#define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x0000001a +#define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000ffffeL +#define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x00000001 +#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_MASK 0x00f00000L +#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L +#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x00000018 +#define MC_XPB_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x00000014 +#define MC_XPB_RTR_DEST_MAP0__NMR_MASK 0x00000001L +#define MC_XPB_RTR_DEST_MAP0__NMR__SHIFT 0x00000000 +#define MC_XPB_RTR_DEST_MAP0__SIDE_OK_MASK 0x02000000L +#define MC_XPB_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x00000019 +#define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000L +#define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x0000001a +#define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000ffffeL +#define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x00000001 +#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_MASK 0x00f00000L +#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L +#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x00000018 +#define MC_XPB_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x00000014 +#define MC_XPB_RTR_DEST_MAP1__NMR_MASK 0x00000001L +#define MC_XPB_RTR_DEST_MAP1__NMR__SHIFT 0x00000000 +#define MC_XPB_RTR_DEST_MAP1__SIDE_OK_MASK 0x02000000L +#define MC_XPB_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x00000019 +#define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000L +#define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x0000001a +#define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000ffffeL +#define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x00000001 +#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_MASK 0x00f00000L +#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L +#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x00000018 +#define MC_XPB_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x00000014 +#define MC_XPB_RTR_DEST_MAP2__NMR_MASK 0x00000001L +#define MC_XPB_RTR_DEST_MAP2__NMR__SHIFT 0x00000000 +#define MC_XPB_RTR_DEST_MAP2__SIDE_OK_MASK 0x02000000L +#define MC_XPB_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x00000019 +#define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000L +#define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x0000001a +#define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET_MASK 0x000ffffeL +#define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x00000001 +#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_MASK 0x00f00000L +#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x01000000L +#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x00000018 +#define MC_XPB_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x00000014 +#define MC_XPB_RTR_DEST_MAP3__NMR_MASK 0x00000001L +#define MC_XPB_RTR_DEST_MAP3__NMR__SHIFT 0x00000000 +#define MC_XPB_RTR_DEST_MAP3__SIDE_OK_MASK 0x02000000L +#define MC_XPB_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x00000019 +#define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE_MASK 0x7c000000L +#define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE__SHIFT 0x0000001a +#define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET_MASK 0x000ffffeL +#define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET__SHIFT 0x00000001 +#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_MASK 0x00f00000L +#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB_MASK 0x01000000L +#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB__SHIFT 0x00000018 +#define MC_XPB_RTR_DEST_MAP4__DEST_SEL__SHIFT 0x00000014 +#define MC_XPB_RTR_DEST_MAP4__NMR_MASK 0x00000001L +#define MC_XPB_RTR_DEST_MAP4__NMR__SHIFT 0x00000000 +#define MC_XPB_RTR_DEST_MAP4__SIDE_OK_MASK 0x02000000L +#define MC_XPB_RTR_DEST_MAP4__SIDE_OK__SHIFT 0x00000019 +#define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE_MASK 0x7c000000L +#define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE__SHIFT 0x0000001a +#define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET_MASK 0x000ffffeL +#define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET__SHIFT 0x00000001 +#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_MASK 0x00f00000L +#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB_MASK 0x01000000L +#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB__SHIFT 0x00000018 +#define MC_XPB_RTR_DEST_MAP5__DEST_SEL__SHIFT 0x00000014 +#define MC_XPB_RTR_DEST_MAP5__NMR_MASK 0x00000001L +#define MC_XPB_RTR_DEST_MAP5__NMR__SHIFT 0x00000000 +#define MC_XPB_RTR_DEST_MAP5__SIDE_OK_MASK 0x02000000L +#define MC_XPB_RTR_DEST_MAP5__SIDE_OK__SHIFT 0x00000019 +#define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE_MASK 0x7c000000L +#define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE__SHIFT 0x0000001a +#define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET_MASK 0x000ffffeL +#define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET__SHIFT 0x00000001 +#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_MASK 0x00f00000L +#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB_MASK 0x01000000L +#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB__SHIFT 0x00000018 +#define MC_XPB_RTR_DEST_MAP6__DEST_SEL__SHIFT 0x00000014 +#define MC_XPB_RTR_DEST_MAP6__NMR_MASK 0x00000001L +#define MC_XPB_RTR_DEST_MAP6__NMR__SHIFT 0x00000000 +#define MC_XPB_RTR_DEST_MAP6__SIDE_OK_MASK 0x02000000L +#define MC_XPB_RTR_DEST_MAP6__SIDE_OK__SHIFT 0x00000019 +#define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE_MASK 0x7c000000L +#define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE__SHIFT 0x0000001a +#define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET_MASK 0x000ffffeL +#define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET__SHIFT 0x00000001 +#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_MASK 0x00f00000L +#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB_MASK 0x01000000L +#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB__SHIFT 0x00000018 +#define MC_XPB_RTR_DEST_MAP7__DEST_SEL__SHIFT 0x00000014 +#define MC_XPB_RTR_DEST_MAP7__NMR_MASK 0x00000001L +#define MC_XPB_RTR_DEST_MAP7__NMR__SHIFT 0x00000000 +#define MC_XPB_RTR_DEST_MAP7__SIDE_OK_MASK 0x02000000L +#define MC_XPB_RTR_DEST_MAP7__SIDE_OK__SHIFT 0x00000019 +#define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE_MASK 0x7c000000L +#define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE__SHIFT 0x0000001a +#define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET_MASK 0x000ffffeL +#define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET__SHIFT 0x00000001 +#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_MASK 0x00f00000L +#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB_MASK 0x01000000L +#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB__SHIFT 0x00000018 +#define MC_XPB_RTR_DEST_MAP8__DEST_SEL__SHIFT 0x00000014 +#define MC_XPB_RTR_DEST_MAP8__NMR_MASK 0x00000001L +#define MC_XPB_RTR_DEST_MAP8__NMR__SHIFT 0x00000000 +#define MC_XPB_RTR_DEST_MAP8__SIDE_OK_MASK 0x02000000L +#define MC_XPB_RTR_DEST_MAP8__SIDE_OK__SHIFT 0x00000019 +#define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE_MASK 0x7c000000L +#define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE__SHIFT 0x0000001a +#define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET_MASK 0x000ffffeL +#define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET__SHIFT 0x00000001 +#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_MASK 0x00f00000L +#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB_MASK 0x01000000L +#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB__SHIFT 0x00000018 +#define MC_XPB_RTR_DEST_MAP9__DEST_SEL__SHIFT 0x00000014 +#define MC_XPB_RTR_DEST_MAP9__NMR_MASK 0x00000001L +#define MC_XPB_RTR_DEST_MAP9__NMR__SHIFT 0x00000000 +#define MC_XPB_RTR_DEST_MAP9__SIDE_OK_MASK 0x02000000L +#define MC_XPB_RTR_DEST_MAP9__SIDE_OK__SHIFT 0x00000019 +#define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x01ffffffL +#define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x00000000 +#define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x01ffffffL +#define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x00000000 +#define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x01ffffffL +#define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x00000000 +#define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x01ffffffL +#define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x00000000 +#define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR_MASK 0x01ffffffL +#define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR__SHIFT 0x00000000 +#define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR_MASK 0x01ffffffL +#define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR__SHIFT 0x00000000 +#define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR_MASK 0x01ffffffL +#define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR__SHIFT 0x00000000 +#define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR_MASK 0x01ffffffL +#define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR__SHIFT 0x00000000 +#define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR_MASK 0x01ffffffL +#define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR__SHIFT 0x00000000 +#define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR_MASK 0x01ffffffL +#define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR__SHIFT 0x00000000 +#define MC_XPB_STICKY__BITS_MASK 0xffffffffL +#define MC_XPB_STICKY__BITS__SHIFT 0x00000000 +#define MC_XPB_STICKY_W1C__BITS_MASK 0xffffffffL +#define MC_XPB_STICKY_W1C__BITS__SHIFT 0x00000000 +#define MC_XPB_SUB_CTRL__RESET_CGR_MASK 0x00080000L +#define MC_XPB_SUB_CTRL__RESET_CGR__SHIFT 0x00000013 +#define MC_XPB_SUB_CTRL__RESET_CNS_MASK 0x00000400L +#define MC_XPB_SUB_CTRL__RESET_CNS__SHIFT 0x0000000a +#define MC_XPB_SUB_CTRL__RESET_HOP_MASK 0x00010000L +#define MC_XPB_SUB_CTRL__RESET_HOP__SHIFT 0x00000010 +#define MC_XPB_SUB_CTRL__RESET_HST_MASK 0x00008000L +#define MC_XPB_SUB_CTRL__RESET_HST__SHIFT 0x0000000f +#define MC_XPB_SUB_CTRL__RESET_MAP_MASK 0x00002000L +#define MC_XPB_SUB_CTRL__RESET_MAP__SHIFT 0x0000000d +#define MC_XPB_SUB_CTRL__RESET_RET_MASK 0x00001000L +#define MC_XPB_SUB_CTRL__RESET_RET__SHIFT 0x0000000c +#define MC_XPB_SUB_CTRL__RESET_RTR_MASK 0x00000800L +#define MC_XPB_SUB_CTRL__RESET_RTR__SHIFT 0x0000000b +#define MC_XPB_SUB_CTRL__RESET_SID_MASK 0x00020000L +#define MC_XPB_SUB_CTRL__RESET_SID__SHIFT 0x00000011 +#define MC_XPB_SUB_CTRL__RESET_SRB_MASK 0x00040000L +#define MC_XPB_SUB_CTRL__RESET_SRB__SHIFT 0x00000012 +#define MC_XPB_SUB_CTRL__RESET_WCB_MASK 0x00004000L +#define MC_XPB_SUB_CTRL__RESET_WCB__SHIFT 0x0000000e +#define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ_MASK 0x00000002L +#define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ__SHIFT 0x00000001 +#define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ_MASK 0x00000100L +#define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ__SHIFT 0x00000008 +#define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ_MASK 0x00000010L +#define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ__SHIFT 0x00000004 +#define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND_MASK 0x00000040L +#define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND__SHIFT 0x00000006 +#define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ_MASK 0x00000008L +#define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ__SHIFT 0x00000003 +#define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ_MASK 0x00000004L +#define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ__SHIFT 0x00000002 +#define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ_MASK 0x00000080L +#define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ__SHIFT 0x00000007 +#define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ_MASK 0x00000020L +#define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ__SHIFT 0x00000005 +#define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR_MASK 0x00000200L +#define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR__SHIFT 0x00000009 +#define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB_MASK 0x00000001L +#define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB__SHIFT 0x00000000 +#define MC_XPB_UNC_THRESH_HST__CHANGE_PREF_MASK 0x0000003fL +#define MC_XPB_UNC_THRESH_HST__CHANGE_PREF__SHIFT 0x00000000 +#define MC_XPB_UNC_THRESH_HST__STRONG_PREF_MASK 0x00000fc0L +#define MC_XPB_UNC_THRESH_HST__STRONG_PREF__SHIFT 0x00000006 +#define MC_XPB_UNC_THRESH_HST__USE_UNFULL_MASK 0x0003f000L +#define MC_XPB_UNC_THRESH_HST__USE_UNFULL__SHIFT 0x0000000c +#define MC_XPB_UNC_THRESH_SID__CHANGE_PREF_MASK 0x0000003fL +#define MC_XPB_UNC_THRESH_SID__CHANGE_PREF__SHIFT 0x00000000 +#define MC_XPB_UNC_THRESH_SID__STRONG_PREF_MASK 0x00000fc0L +#define MC_XPB_UNC_THRESH_SID__STRONG_PREF__SHIFT 0x00000006 +#define MC_XPB_UNC_THRESH_SID__USE_UNFULL_MASK 0x0003f000L +#define MC_XPB_UNC_THRESH_SID__USE_UNFULL__SHIFT 0x0000000c +#define MC_XPB_WCB_CFG__HST_MAX_MASK 0x00030000L +#define MC_XPB_WCB_CFG__HST_MAX__SHIFT 0x00000010 +#define MC_XPB_WCB_CFG__SID_MAX_MASK 0x000c0000L +#define MC_XPB_WCB_CFG__SID_MAX__SHIFT 0x00000012 +#define MC_XPB_WCB_CFG__TIMEOUT_MASK 0x0000ffffL +#define MC_XPB_WCB_CFG__TIMEOUT__SHIFT 0x00000000 +#define MC_XPB_WCB_STS__PBUF_VLD_MASK 0x0000ffffL +#define MC_XPB_WCB_STS__PBUF_VLD__SHIFT 0x00000000 +#define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT_MASK 0x007f0000L +#define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x00000010 +#define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT_MASK 0x3f800000L +#define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x00000017 +#define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR_MASK 0x07fffffcL +#define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR__SHIFT 0x00000002 +#define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK_MASK 0x00000002L +#define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x00000001 +#define MC_XPB_XDMA_PEER_SYS_BAR0__VALID_MASK 0x00000001L +#define MC_XPB_XDMA_PEER_SYS_BAR0__VALID__SHIFT 0x00000000 +#define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR_MASK 0x07fffffcL +#define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR__SHIFT 0x00000002 +#define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK_MASK 0x00000002L +#define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x00000001 +#define MC_XPB_XDMA_PEER_SYS_BAR1__VALID_MASK 0x00000001L +#define MC_XPB_XDMA_PEER_SYS_BAR1__VALID__SHIFT 0x00000000 +#define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR_MASK 0x07fffffcL +#define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR__SHIFT 0x00000002 +#define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK_MASK 0x00000002L +#define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x00000001 +#define MC_XPB_XDMA_PEER_SYS_BAR2__VALID_MASK 0x00000001L +#define MC_XPB_XDMA_PEER_SYS_BAR2__VALID__SHIFT 0x00000000 +#define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR_MASK 0x07fffffcL +#define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR__SHIFT 0x00000002 +#define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK_MASK 0x00000002L +#define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x00000001 +#define MC_XPB_XDMA_PEER_SYS_BAR3__VALID_MASK 0x00000001L +#define MC_XPB_XDMA_PEER_SYS_BAR3__VALID__SHIFT 0x00000000 +#define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000L +#define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x0000001a +#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000ffffeL +#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x00000001 +#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_MASK 0x00f00000L +#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L +#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x00000018 +#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x00000014 +#define MC_XPB_XDMA_RTR_DEST_MAP0__NMR_MASK 0x00000001L +#define MC_XPB_XDMA_RTR_DEST_MAP0__NMR__SHIFT 0x00000000 +#define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK_MASK 0x02000000L +#define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x00000019 +#define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000L +#define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x0000001a +#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000ffffeL +#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x00000001 +#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_MASK 0x00f00000L +#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L +#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x00000018 +#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x00000014 +#define MC_XPB_XDMA_RTR_DEST_MAP1__NMR_MASK 0x00000001L +#define MC_XPB_XDMA_RTR_DEST_MAP1__NMR__SHIFT 0x00000000 +#define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK_MASK 0x02000000L +#define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x00000019 +#define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000L +#define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x0000001a +#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000ffffeL +#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x00000001 +#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_MASK 0x00f00000L +#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L +#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x00000018 +#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x00000014 +#define MC_XPB_XDMA_RTR_DEST_MAP2__NMR_MASK 0x00000001L +#define MC_XPB_XDMA_RTR_DEST_MAP2__NMR__SHIFT 0x00000000 +#define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK_MASK 0x02000000L +#define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x00000019 +#define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000L +#define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x0000001a +#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET_MASK 0x000ffffeL +#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x00000001 +#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_MASK 0x00f00000L +#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x01000000L +#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x00000018 +#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x00000014 +#define MC_XPB_XDMA_RTR_DEST_MAP3__NMR_MASK 0x00000001L +#define MC_XPB_XDMA_RTR_DEST_MAP3__NMR__SHIFT 0x00000000 +#define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK_MASK 0x02000000L +#define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x00000019 +#define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x01ffffffL +#define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x00000000 +#define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x01ffffffL +#define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x00000000 +#define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x01ffffffL +#define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x00000000 +#define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x01ffffffL +#define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x00000000 +#define MPLL_AD_FUNC_CNTL__SPARE_MASK 0xfffffff8L +#define MPLL_AD_FUNC_CNTL__SPARE__SHIFT 0x00000003 +#define MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK 0x00000007L +#define MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT 0x00000000 +#define MPLL_AD_STATUS__FREQ_LOCK_MASK 0x00040000L +#define MPLL_AD_STATUS__FREQ_LOCK__SHIFT 0x00000012 +#define MPLL_AD_STATUS__FREQ_UNLOCK_STICKY_MASK 0x00080000L +#define MPLL_AD_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x00000013 +#define MPLL_AD_STATUS__OINT_RESET_MASK 0x00020000L +#define MPLL_AD_STATUS__OINT_RESET__SHIFT 0x00000011 +#define MPLL_AD_STATUS__TEST_FBDIV_FRAC_MASK 0x00000070L +#define MPLL_AD_STATUS__TEST_FBDIV_FRAC__SHIFT 0x00000004 +#define MPLL_AD_STATUS__TEST_FBDIV_INT_MASK 0x0001ff80L +#define MPLL_AD_STATUS__TEST_FBDIV_INT__SHIFT 0x00000007 +#define MPLL_AD_STATUS__VCTRLADC_MASK 0x00000007L +#define MPLL_AD_STATUS__VCTRLADC__SHIFT 0x00000000 +#define MPLL_CNTL_MODE__FAST_LOCK_CNTRL_MASK 0x00600000L +#define MPLL_CNTL_MODE__FAST_LOCK_CNTRL__SHIFT 0x00000015 +#define MPLL_CNTL_MODE__FAST_LOCK_EN_MASK 0x00100000L +#define MPLL_CNTL_MODE__FAST_LOCK_EN__SHIFT 0x00000014 +#define MPLL_CNTL_MODE__FORCE_TESTMODE_MASK 0x00020000L +#define MPLL_CNTL_MODE__FORCE_TESTMODE__SHIFT 0x00000011 +#define MPLL_CNTL_MODE__GLOBAL_MPLL_RESET_MASK 0x80000000L +#define MPLL_CNTL_MODE__GLOBAL_MPLL_RESET__SHIFT 0x0000001f +#define MPLL_CNTL_MODE__INSTR_DELAY_MASK 0x000000ffL +#define MPLL_CNTL_MODE__INSTR_DELAY__SHIFT 0x00000000 +#define MPLL_CNTL_MODE__MPLL_CHG_STATUS_MASK 0x00010000L +#define MPLL_CNTL_MODE__MPLL_CHG_STATUS__SHIFT 0x00000010 +#define MPLL_CNTL_MODE__MPLL_CTLREQ_MASK 0x00004000L +#define MPLL_CNTL_MODE__MPLL_CTLREQ__SHIFT 0x0000000e +#define MPLL_CNTL_MODE__MPLL_MCLK_SEL_MASK 0x00000800L +#define MPLL_CNTL_MODE__MPLL_MCLK_SEL__SHIFT 0x0000000b +#define MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL_MASK 0x00000100L +#define MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL__SHIFT 0x00000008 +#define MPLL_CNTL_MODE__QDR_MASK 0x00002000L +#define MPLL_CNTL_MODE__QDR__SHIFT 0x0000000d +#define MPLL_CNTL_MODE__SPARE_1_MASK 0x00001000L +#define MPLL_CNTL_MODE__SPARE_1__SHIFT 0x0000000c +#define MPLL_CNTL_MODE__SPARE_2_MASK 0x00800000L +#define MPLL_CNTL_MODE__SPARE_2__SHIFT 0x00000017 +#define MPLL_CNTL_MODE__SPARE_3_MASK 0x70000000L +#define MPLL_CNTL_MODE__SPARE_3__SHIFT 0x0000001c +#define MPLL_CNTL_MODE__SS_DSMODE_EN_MASK 0x04000000L +#define MPLL_CNTL_MODE__SS_DSMODE_EN__SHIFT 0x0000001a +#define MPLL_CNTL_MODE__SS_SSEN_MASK 0x03000000L +#define MPLL_CNTL_MODE__SS_SSEN__SHIFT 0x00000018 +#define MPLL_CNTL_MODE__VTOI_BIAS_CNTRL_MASK 0x08000000L +#define MPLL_CNTL_MODE__VTOI_BIAS_CNTRL__SHIFT 0x0000001b +#define MPLL_CONTROL__AD_BG_PWRON_MASK 0x00001000L +#define MPLL_CONTROL__AD_BG_PWRON__SHIFT 0x0000000c +#define MPLL_CONTROL__AD_PLL_PWRON_MASK 0x00002000L +#define MPLL_CONTROL__AD_PLL_PWRON__SHIFT 0x0000000d +#define MPLL_CONTROL__AD_PLL_RESET_MASK 0x00004000L +#define MPLL_CONTROL__AD_PLL_RESET__SHIFT 0x0000000e +#define MPLL_CONTROL__DQ_0_0_BG_PWRON_MASK 0x00010000L +#define MPLL_CONTROL__DQ_0_0_BG_PWRON__SHIFT 0x00000010 +#define MPLL_CONTROL__DQ_0_0_PLL_PWRON_MASK 0x00020000L +#define MPLL_CONTROL__DQ_0_0_PLL_PWRON__SHIFT 0x00000011 +#define MPLL_CONTROL__DQ_0_0_PLL_RESET_MASK 0x00040000L +#define MPLL_CONTROL__DQ_0_0_PLL_RESET__SHIFT 0x00000012 +#define MPLL_CONTROL__DQ_0_1_BG_PWRON_MASK 0x00100000L +#define MPLL_CONTROL__DQ_0_1_BG_PWRON__SHIFT 0x00000014 +#define MPLL_CONTROL__DQ_0_1_PLL_PWRON_MASK 0x00200000L +#define MPLL_CONTROL__DQ_0_1_PLL_PWRON__SHIFT 0x00000015 +#define MPLL_CONTROL__DQ_0_1_PLL_RESET_MASK 0x00400000L +#define MPLL_CONTROL__DQ_0_1_PLL_RESET__SHIFT 0x00000016 +#define MPLL_CONTROL__DQ_1_0_BG_PWRON_MASK 0x01000000L +#define MPLL_CONTROL__DQ_1_0_BG_PWRON__SHIFT 0x00000018 +#define MPLL_CONTROL__DQ_1_0_PLL_PWRON_MASK 0x02000000L +#define MPLL_CONTROL__DQ_1_0_PLL_PWRON__SHIFT 0x00000019 +#define MPLL_CONTROL__DQ_1_0_PLL_RESET_MASK 0x04000000L +#define MPLL_CONTROL__DQ_1_0_PLL_RESET__SHIFT 0x0000001a +#define MPLL_CONTROL__DQ_1_1_BG_PWRON_MASK 0x10000000L +#define MPLL_CONTROL__DQ_1_1_BG_PWRON__SHIFT 0x0000001c +#define MPLL_CONTROL__DQ_1_1_PLL_PWRON_MASK 0x20000000L +#define MPLL_CONTROL__DQ_1_1_PLL_PWRON__SHIFT 0x0000001d +#define MPLL_CONTROL__DQ_1_1_PLL_RESET_MASK 0x40000000L +#define MPLL_CONTROL__DQ_1_1_PLL_RESET__SHIFT 0x0000001e +#define MPLL_CONTROL__GDDR_PWRON_MASK 0x00000001L +#define MPLL_CONTROL__GDDR_PWRON__SHIFT 0x00000000 +#define MPLL_CONTROL__PLL_BUF_PWRON_TX_MASK 0x00000004L +#define MPLL_CONTROL__PLL_BUF_PWRON_TX__SHIFT 0x00000002 +#define MPLL_CONTROL__REFCLK_PWRON_MASK 0x00000002L +#define MPLL_CONTROL__REFCLK_PWRON__SHIFT 0x00000001 +#define MPLL_CONTROL__SPARE_AD_0_MASK 0x00008000L +#define MPLL_CONTROL__SPARE_AD_0__SHIFT 0x0000000f +#define MPLL_CONTROL__SPARE_DQ_0_0_MASK 0x00080000L +#define MPLL_CONTROL__SPARE_DQ_0_0__SHIFT 0x00000013 +#define MPLL_CONTROL__SPARE_DQ_0_1_MASK 0x00800000L +#define MPLL_CONTROL__SPARE_DQ_0_1__SHIFT 0x00000017 +#define MPLL_CONTROL__SPARE_DQ_1_0_MASK 0x08000000L +#define MPLL_CONTROL__SPARE_DQ_1_0__SHIFT 0x0000001b +#define MPLL_CONTROL__SPARE_DQ_1_1_MASK 0x80000000L +#define MPLL_CONTROL__SPARE_DQ_1_1__SHIFT 0x0000001f +#define MPLL_DQ_0_0_STATUS__FREQ_LOCK_MASK 0x00040000L +#define MPLL_DQ_0_0_STATUS__FREQ_LOCK__SHIFT 0x00000012 +#define MPLL_DQ_0_0_STATUS__FREQ_UNLOCK_STICKY_MASK 0x00080000L +#define MPLL_DQ_0_0_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x00000013 +#define MPLL_DQ_0_0_STATUS__OINT_RESET_MASK 0x00020000L +#define MPLL_DQ_0_0_STATUS__OINT_RESET__SHIFT 0x00000011 +#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_FRAC_MASK 0x00000070L +#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_FRAC__SHIFT 0x00000004 +#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_INT_MASK 0x0001ff80L +#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_INT__SHIFT 0x00000007 +#define MPLL_DQ_0_0_STATUS__VCTRLADC_MASK 0x00000007L +#define MPLL_DQ_0_0_STATUS__VCTRLADC__SHIFT 0x00000000 +#define MPLL_DQ_0_1_STATUS__FREQ_LOCK_MASK 0x00040000L +#define MPLL_DQ_0_1_STATUS__FREQ_LOCK__SHIFT 0x00000012 +#define MPLL_DQ_0_1_STATUS__FREQ_UNLOCK_STICKY_MASK 0x00080000L +#define MPLL_DQ_0_1_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x00000013 +#define MPLL_DQ_0_1_STATUS__OINT_RESET_MASK 0x00020000L +#define MPLL_DQ_0_1_STATUS__OINT_RESET__SHIFT 0x00000011 +#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_FRAC_MASK 0x00000070L +#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_FRAC__SHIFT 0x00000004 +#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_INT_MASK 0x0001ff80L +#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_INT__SHIFT 0x00000007 +#define MPLL_DQ_0_1_STATUS__VCTRLADC_MASK 0x00000007L +#define MPLL_DQ_0_1_STATUS__VCTRLADC__SHIFT 0x00000000 +#define MPLL_DQ_1_0_STATUS__FREQ_LOCK_MASK 0x00040000L +#define MPLL_DQ_1_0_STATUS__FREQ_LOCK__SHIFT 0x00000012 +#define MPLL_DQ_1_0_STATUS__FREQ_UNLOCK_STICKY_MASK 0x00080000L +#define MPLL_DQ_1_0_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x00000013 +#define MPLL_DQ_1_0_STATUS__OINT_RESET_MASK 0x00020000L +#define MPLL_DQ_1_0_STATUS__OINT_RESET__SHIFT 0x00000011 +#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_FRAC_MASK 0x00000070L +#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_FRAC__SHIFT 0x00000004 +#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_INT_MASK 0x0001ff80L +#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_INT__SHIFT 0x00000007 +#define MPLL_DQ_1_0_STATUS__VCTRLADC_MASK 0x00000007L +#define MPLL_DQ_1_0_STATUS__VCTRLADC__SHIFT 0x00000000 +#define MPLL_DQ_1_1_STATUS__FREQ_LOCK_MASK 0x00040000L +#define MPLL_DQ_1_1_STATUS__FREQ_LOCK__SHIFT 0x00000012 +#define MPLL_DQ_1_1_STATUS__FREQ_UNLOCK_STICKY_MASK 0x00080000L +#define MPLL_DQ_1_1_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x00000013 +#define MPLL_DQ_1_1_STATUS__OINT_RESET_MASK 0x00020000L +#define MPLL_DQ_1_1_STATUS__OINT_RESET__SHIFT 0x00000011 +#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_FRAC_MASK 0x00000070L +#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_FRAC__SHIFT 0x00000004 +#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_INT_MASK 0x0001ff80L +#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_INT__SHIFT 0x00000007 +#define MPLL_DQ_1_1_STATUS__VCTRLADC_MASK 0x00000007L +#define MPLL_DQ_1_1_STATUS__VCTRLADC__SHIFT 0x00000000 +#define MPLL_DQ_FUNC_CNTL__SPARE_0_MASK 0x00000008L +#define MPLL_DQ_FUNC_CNTL__SPARE_0__SHIFT 0x00000003 +#define MPLL_DQ_FUNC_CNTL__SPARE_MASK 0xffffffe0L +#define MPLL_DQ_FUNC_CNTL__SPARE__SHIFT 0x00000005 +#define MPLL_DQ_FUNC_CNTL__YCLK_POST_DIV_MASK 0x00000007L +#define MPLL_DQ_FUNC_CNTL__YCLK_POST_DIV__SHIFT 0x00000000 +#define MPLL_DQ_FUNC_CNTL__YCLK_SEL_MASK 0x00000010L +#define MPLL_DQ_FUNC_CNTL__YCLK_SEL__SHIFT 0x00000004 +#define MPLL_FUNC_CNTL_1__CLKF_MASK 0x0fff0000L +#define MPLL_FUNC_CNTL_1__CLKFRAC_MASK 0x0000fff0L +#define MPLL_FUNC_CNTL_1__CLKFRAC__SHIFT 0x00000004 +#define MPLL_FUNC_CNTL_1__CLKF__SHIFT 0x00000010 +#define MPLL_FUNC_CNTL_1__SPARE_0_MASK 0x0000000cL +#define MPLL_FUNC_CNTL_1__SPARE_0__SHIFT 0x00000002 +#define MPLL_FUNC_CNTL_1__SPARE_1_MASK 0xf0000000L +#define MPLL_FUNC_CNTL_1__SPARE_1__SHIFT 0x0000001c +#define MPLL_FUNC_CNTL_1__VCO_MODE_MASK 0x00000003L +#define MPLL_FUNC_CNTL_1__VCO_MODE__SHIFT 0x00000000 +#define MPLL_FUNC_CNTL_2__BACKUP_2_MASK 0x000e0000L +#define MPLL_FUNC_CNTL_2__BACKUP_2__SHIFT 0x00000011 +#define MPLL_FUNC_CNTL_2__BACKUP_MASK 0xf8000000L +#define MPLL_FUNC_CNTL_2__BACKUP__SHIFT 0x0000001b +#define MPLL_FUNC_CNTL_2__LF_CNTRL_MASK 0x07f00000L +#define MPLL_FUNC_CNTL_2__LF_CNTRL__SHIFT 0x00000014 +#define MPLL_FUNC_CNTL_2__MPLL_UNLOCK_CLEAR_MASK 0x00000080L +#define MPLL_FUNC_CNTL_2__MPLL_UNLOCK_CLEAR__SHIFT 0x00000007 +#define MPLL_FUNC_CNTL_2__PFD_RESET_CNTRL_MASK 0x00003000L +#define MPLL_FUNC_CNTL_2__PFD_RESET_CNTRL__SHIFT 0x0000000c +#define MPLL_FUNC_CNTL_2__RESET_EN_MASK 0x00000004L +#define MPLL_FUNC_CNTL_2__RESET_EN__SHIFT 0x00000002 +#define MPLL_FUNC_CNTL_2__RESET_TIMER_MASK 0x00000c00L +#define MPLL_FUNC_CNTL_2__RESET_TIMER__SHIFT 0x0000000a +#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_EN_MASK 0x00000008L +#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_EN__SHIFT 0x00000003 +#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_SRC_MASK 0x00000010L +#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_SRC__SHIFT 0x00000004 +#define MPLL_FUNC_CNTL_2__TEST_BYPMCLK_MASK 0x00000040L +#define MPLL_FUNC_CNTL_2__TEST_BYPMCLK__SHIFT 0x00000006 +#define MPLL_FUNC_CNTL_2__TEST_FBDIV_FRAC_BYPASS_MASK 0x00000020L +#define MPLL_FUNC_CNTL_2__TEST_FBDIV_FRAC_BYPASS__SHIFT 0x00000005 +#define MPLL_FUNC_CNTL_2__TEST_FBDIV_SSC_BYPASS_MASK 0x00000200L +#define MPLL_FUNC_CNTL_2__TEST_FBDIV_SSC_BYPASS__SHIFT 0x00000009 +#define MPLL_FUNC_CNTL_2__TEST_VCTL_CNTRL_MASK 0x00000100L +#define MPLL_FUNC_CNTL_2__TEST_VCTL_CNTRL__SHIFT 0x00000008 +#define MPLL_FUNC_CNTL_2__TEST_VCTL_EN_MASK 0x00000002L +#define MPLL_FUNC_CNTL_2__TEST_VCTL_EN__SHIFT 0x00000001 +#define MPLL_FUNC_CNTL_2__VCTRLADC_EN_MASK 0x00000001L +#define MPLL_FUNC_CNTL_2__VCTRLADC_EN__SHIFT 0x00000000 +#define MPLL_FUNC_CNTL__BG_100ADJ_MASK 0x00000f00L +#define MPLL_FUNC_CNTL__BG_100ADJ__SHIFT 0x00000008 +#define MPLL_FUNC_CNTL__BG_135ADJ_MASK 0x000f0000L +#define MPLL_FUNC_CNTL__BG_135ADJ__SHIFT 0x00000010 +#define MPLL_FUNC_CNTL__BWCTRL_MASK 0x0ff00000L +#define MPLL_FUNC_CNTL__BWCTRL__SHIFT 0x00000014 +#define MPLL_FUNC_CNTL__REG_BIAS_MASK 0xc0000000L +#define MPLL_FUNC_CNTL__REG_BIAS__SHIFT 0x0000001e +#define MPLL_FUNC_CNTL__SPARE_0_MASK 0x00000020L +#define MPLL_FUNC_CNTL__SPARE_0__SHIFT 0x00000005 +#define MPLL_SEQ_UCODE_1__INSTR0_MASK 0x0000000fL +#define MPLL_SEQ_UCODE_1__INSTR0__SHIFT 0x00000000 +#define MPLL_SEQ_UCODE_1__INSTR1_MASK 0x000000f0L +#define MPLL_SEQ_UCODE_1__INSTR1__SHIFT 0x00000004 +#define MPLL_SEQ_UCODE_1__INSTR2_MASK 0x00000f00L +#define MPLL_SEQ_UCODE_1__INSTR2__SHIFT 0x00000008 +#define MPLL_SEQ_UCODE_1__INSTR3_MASK 0x0000f000L +#define MPLL_SEQ_UCODE_1__INSTR3__SHIFT 0x0000000c +#define MPLL_SEQ_UCODE_1__INSTR4_MASK 0x000f0000L +#define MPLL_SEQ_UCODE_1__INSTR4__SHIFT 0x00000010 +#define MPLL_SEQ_UCODE_1__INSTR5_MASK 0x00f00000L +#define MPLL_SEQ_UCODE_1__INSTR5__SHIFT 0x00000014 +#define MPLL_SEQ_UCODE_1__INSTR6_MASK 0x0f000000L +#define MPLL_SEQ_UCODE_1__INSTR6__SHIFT 0x00000018 +#define MPLL_SEQ_UCODE_1__INSTR7_MASK 0xf0000000L +#define MPLL_SEQ_UCODE_1__INSTR7__SHIFT 0x0000001c +#define MPLL_SEQ_UCODE_2__INSTR10_MASK 0x00000f00L +#define MPLL_SEQ_UCODE_2__INSTR10__SHIFT 0x00000008 +#define MPLL_SEQ_UCODE_2__INSTR11_MASK 0x0000f000L +#define MPLL_SEQ_UCODE_2__INSTR11__SHIFT 0x0000000c +#define MPLL_SEQ_UCODE_2__INSTR12_MASK 0x000f0000L +#define MPLL_SEQ_UCODE_2__INSTR12__SHIFT 0x00000010 +#define MPLL_SEQ_UCODE_2__INSTR13_MASK 0x00f00000L +#define MPLL_SEQ_UCODE_2__INSTR13__SHIFT 0x00000014 +#define MPLL_SEQ_UCODE_2__INSTR14_MASK 0x0f000000L +#define MPLL_SEQ_UCODE_2__INSTR14__SHIFT 0x00000018 +#define MPLL_SEQ_UCODE_2__INSTR15_MASK 0xf0000000L +#define MPLL_SEQ_UCODE_2__INSTR15__SHIFT 0x0000001c +#define MPLL_SEQ_UCODE_2__INSTR8_MASK 0x0000000fL +#define MPLL_SEQ_UCODE_2__INSTR8__SHIFT 0x00000000 +#define MPLL_SEQ_UCODE_2__INSTR9_MASK 0x000000f0L +#define MPLL_SEQ_UCODE_2__INSTR9__SHIFT 0x00000004 +#define MPLL_SS1__CLKV_MASK 0x03ffffffL +#define MPLL_SS1__CLKV__SHIFT 0x00000000 +#define MPLL_SS1__SPARE_MASK 0xfc000000L +#define MPLL_SS1__SPARE__SHIFT 0x0000001a +#define MPLL_SS2__CLKS_MASK 0x00000fffL +#define MPLL_SS2__CLKS__SHIFT 0x00000000 +#define MPLL_SS2__SPARE_MASK 0xfffff000L +#define MPLL_SS2__SPARE__SHIFT 0x0000000c +#define MPLL_TIME__MPLL_LOCK_TIME_MASK 0x0000ffffL +#define MPLL_TIME__MPLL_LOCK_TIME__SHIFT 0x00000000 +#define MPLL_TIME__MPLL_RESET_TIME_MASK 0xffff0000L +#define MPLL_TIME__MPLL_RESET_TIME__SHIFT 0x00000010 +#define VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000008L +#define VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x00000003 +#define VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L +#define VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x00000000 +#define VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x00000002L +#define VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x00000001 +#define VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x00000004L +#define VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x00000002 +#define VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x00000010L +#define VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x00000004 +#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L +#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000007 +#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000040L +#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000006 +#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x00000000 +#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x0f000000L +#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x00000018 +#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x00000001 +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000a +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000009 +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00000800L +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x0000000b +#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000016 +#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000015 +#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00800000L +#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x00000017 +#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L +#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000004 +#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000008L +#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000003 +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000010 +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000f +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00020000L +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x00000011 +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000d +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000c +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00004000L +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x0000000e +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000013 +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000012 +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00100000L +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x00000014 +#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0x0fffffffL +#define VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x00000000 +#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK 0x0fffffffL +#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT 0x00000000 +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0x000ff000L +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0x0000000c +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x01000000L +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x00000018 +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0x000000ffL +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x00000000 +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000L +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x00000019 +#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000008L +#define VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x00000003 +#define VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L +#define VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x00000000 +#define VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x00000002L +#define VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x00000001 +#define VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x00000004L +#define VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x00000002 +#define VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x00000010L +#define VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x00000004 +#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L +#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000007 +#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000040L +#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000006 +#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x00000000 +#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x0f000000L +#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x00000018 +#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x00000001 +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000a +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000009 +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00000800L +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x0000000b +#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000016 +#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000015 +#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00800000L +#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x00000017 +#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L +#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000004 +#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000008L +#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000003 +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000010 +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000f +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00020000L +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x00000011 +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000d +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000c +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00004000L +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x0000000e +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000013 +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000012 +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00100000L +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x00000014 +#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0x0fffffffL +#define VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x00000000 +#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK 0x0fffffffL +#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT 0x00000000 +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0x000ff000L +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0x0000000c +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x01000000L +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x00000018 +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0x000000ffL +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x00000000 +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000L +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x00000019 +#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x00000000 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0x0000000a +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0x0000000b +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0x0000000c +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0x0000000d +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0x0000000e +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0x0000000f +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x00000001 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x00000002 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x00000003 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x00000004 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x00000005 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x00000006 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x00000007 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x00000008 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x00000009 +#define VM_DEBUG__FLAGS_MASK 0xffffffffL +#define VM_DEBUG__FLAGS__SHIFT 0x00000000 +#define VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR_MASK 0x0fffffffL +#define VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR__SHIFT 0x00000000 +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x00000001 +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK_MASK 0x0000000cL +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK__SHIFT 0x00000002 +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x00000000 +#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK 0x000001ffL +#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK_MASK 0x0003fe00L +#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK__SHIFT 0x00000009 +#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT__SHIFT 0x00000000 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0_MASK 0x00000001L +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0__SHIFT 0x00000000 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10_MASK 0x00000400L +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10__SHIFT 0x0000000a +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11_MASK 0x00000800L +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11__SHIFT 0x0000000b +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12_MASK 0x00001000L +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12__SHIFT 0x0000000c +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13_MASK 0x00002000L +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13__SHIFT 0x0000000d +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14_MASK 0x00004000L +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14__SHIFT 0x0000000e +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15_MASK 0x00008000L +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15__SHIFT 0x0000000f +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1_MASK 0x00000002L +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1__SHIFT 0x00000001 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2_MASK 0x00000004L +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2__SHIFT 0x00000002 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3_MASK 0x00000008L +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3__SHIFT 0x00000003 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4_MASK 0x00000010L +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4__SHIFT 0x00000004 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5_MASK 0x00000020L +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5__SHIFT 0x00000005 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6_MASK 0x00000040L +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6__SHIFT 0x00000006 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7_MASK 0x00000080L +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7__SHIFT 0x00000007 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8_MASK 0x00000100L +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8__SHIFT 0x00000008 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9_MASK 0x00000200L +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9__SHIFT 0x00000009 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0_MASK 0x00000001L +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0__SHIFT 0x00000000 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10_MASK 0x00000400L +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10__SHIFT 0x0000000a +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11_MASK 0x00000800L +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11__SHIFT 0x0000000b +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12_MASK 0x00001000L +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12__SHIFT 0x0000000c +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13_MASK 0x00002000L +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13__SHIFT 0x0000000d +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14_MASK 0x00004000L +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14__SHIFT 0x0000000e +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15_MASK 0x00008000L +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15__SHIFT 0x0000000f +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1_MASK 0x00000002L +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1__SHIFT 0x00000001 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2_MASK 0x00000004L +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2__SHIFT 0x00000002 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3_MASK 0x00000008L +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3__SHIFT 0x00000003 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4_MASK 0x00000010L +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4__SHIFT 0x00000004 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5_MASK 0x00000020L +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5__SHIFT 0x00000005 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6_MASK 0x00000040L +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6__SHIFT 0x00000006 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7_MASK 0x00000080L +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7__SHIFT 0x00000007 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8_MASK 0x00000100L +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8__SHIFT 0x00000008 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9_MASK 0x00000200L +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9__SHIFT 0x00000009 +#define VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK_MASK 0x0fffffffL +#define VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK__SHIFT 0x00000000 +#define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK_MASK 0x000000ffL +#define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK__SHIFT 0x00000000 +#define VM_L2_CG__ENABLE_MASK 0x00040000L +#define VM_L2_CG__ENABLE__SHIFT 0x00000012 +#define VM_L2_CG__MEM_LS_ENABLE_MASK 0x00080000L +#define VM_L2_CG__MEM_LS_ENABLE__SHIFT 0x00000013 +#define VM_L2_CG__OFFDLY_MASK 0x00000fc0L +#define VM_L2_CG__OFFDLY__SHIFT 0x00000006 +#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L +#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x00000016 +#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L +#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x00000015 +#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L +#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x00000000 +#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0c000000L +#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x0000001a +#define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L +#define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x00000001 +#define VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE_MASK 0x03800000L +#define VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE__SHIFT 0x00000017 +#define VM_L2_CNTL3__BANK_SELECT_MASK 0x0000003fL +#define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x00000000 +#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00e00000L +#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x00000015 +#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L +#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x0000001c +#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L +#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x00000014 +#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0f000000L +#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x00000018 +#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L +#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x0000001d +#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000f8000L +#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x0000000f +#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000c0L +#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x00000006 +#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001f00L +#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x00000008 +#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L +#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x00000013 +#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L +#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0x0000000f +#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L +#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x00000000 +#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L +#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x00000001 +#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L +#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x0000000a +#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L +#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x00000009 +#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03e00000L +#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x00000015 +#define VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS_MASK 0x0c000000L +#define VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS__SHIFT 0x0000001a +#define VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS_MASK 0x70000000L +#define VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS__SHIFT 0x0000001c +#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L +#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x00000004 +#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000cL +#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x00000002 +#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L +#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0x0000000c +#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L +#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x00000008 +#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L +#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x00000012 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET_MASK 0x0fffffffL +#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET__SHIFT 0x00000000 +#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001fffeL +#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x00000001 +#define VM_L2_STATUS__L2_BUSY_MASK 0x00000001L +#define VM_L2_STATUS__L2_BUSY__SHIFT 0x00000000 +#define VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES_MASK 0x00000008L +#define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES__SHIFT 0x00000003 +#define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES_MASK 0x00000004L +#define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES__SHIFT 0x00000002 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_1_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_1_0_d.h new file mode 100644 index 000000000000..edc8a793a95d --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_1_0_d.h @@ -0,0 +1,275 @@ +/* + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef OSS_1_0_D_H +#define OSS_1_0_D_H + +#define ixCLIENT0_BM 0x0220 +#define ixCLIENT0_CD0 0x0210 +#define ixCLIENT0_CD1 0x0214 +#define ixCLIENT0_CD2 0x0218 +#define ixCLIENT0_CD3 0x021C +#define ixCLIENT0_CK0 0x0200 +#define ixCLIENT0_CK1 0x0204 +#define ixCLIENT0_CK2 0x0208 +#define ixCLIENT0_CK3 0x020C +#define ixCLIENT0_K0 0x01F0 +#define ixCLIENT0_K1 0x01F4 +#define ixCLIENT0_K2 0x01F8 +#define ixCLIENT0_K3 0x01FC +#define ixCLIENT0_OFFSET 0x0224 +#define ixCLIENT0_OFFSET_HI 0x0290 +#define ixCLIENT0_STATUS 0x0228 +#define ixCLIENT1_BM 0x025C +#define ixCLIENT1_CD0 0x024C +#define ixCLIENT1_CD1 0x0250 +#define ixCLIENT1_CD2 0x0254 +#define ixCLIENT1_CD3 0x0258 +#define ixCLIENT1_CK0 0x023C +#define ixCLIENT1_CK1 0x0240 +#define ixCLIENT1_CK2 0x0244 +#define ixCLIENT1_CK3 0x0248 +#define ixCLIENT1_K0 0x022C +#define ixCLIENT1_K1 0x0230 +#define ixCLIENT1_K2 0x0234 +#define ixCLIENT1_K3 0x0238 +#define ixCLIENT1_OFFSET 0x0260 +#define ixCLIENT1_OFFSET_HI 0x0294 +#define ixCLIENT1_PORT_STATUS 0x0264 +#define ixCLIENT2_BM 0x01E4 +#define ixCLIENT2_CD0 0x01D4 +#define ixCLIENT2_CD1 0x01D8 +#define ixCLIENT2_CD2 0x01DC +#define ixCLIENT2_CD3 0x01E0 +#define ixCLIENT2_CK0 0x01C4 +#define ixCLIENT2_CK1 0x01C8 +#define ixCLIENT2_CK2 0x01CC +#define ixCLIENT2_CK3 0x01D0 +#define ixCLIENT2_K0 0x01B4 +#define ixCLIENT2_K1 0x01B8 +#define ixCLIENT2_K2 0x01BC +#define ixCLIENT2_K3 0x01C0 +#define ixCLIENT2_OFFSET 0x01E8 +#define ixCLIENT2_OFFSET_HI 0x0298 +#define ixCLIENT2_STATUS 0x01EC +#define ixCLIENT3_BM 0x02D4 +#define ixCLIENT3_CD0 0x02C4 +#define ixCLIENT3_CD1 0x02C8 +#define ixCLIENT3_CD2 0x02CC +#define ixCLIENT3_CD3 0x02D0 +#define ixCLIENT3_CK0 0x02B4 +#define ixCLIENT3_CK1 0x02B8 +#define ixCLIENT3_CK2 0x02BC +#define ixCLIENT3_CK3 0x02C0 +#define ixCLIENT3_K0 0x02A4 +#define ixCLIENT3_K1 0x02A8 +#define ixCLIENT3_K2 0x02AC +#define ixCLIENT3_K3 0x02B0 +#define ixCLIENT3_OFFSET 0x02D8 +#define ixCLIENT3_OFFSET_HI 0x02A0 +#define ixCLIENT3_STATUS 0x02DC +#define ixDH_TEST 0x0000 +#define ixEXP0 0x0034 +#define ixEXP1 0x0038 +#define ixEXP2 0x003C +#define ixEXP3 0x0040 +#define ixEXP4 0x0044 +#define ixEXP5 0x0048 +#define ixEXP6 0x004C +#define ixEXP7 0x0050 +#define ixHFS_SEED0 0x0278 +#define ixHFS_SEED1 0x027C +#define ixHFS_SEED2 0x0280 +#define ixHFS_SEED3 0x0284 +#define ixKEFUSE0 0x0268 +#define ixKEFUSE1 0x026C +#define ixKEFUSE2 0x0270 +#define ixKEFUSE3 0x0274 +#define ixKHFS0 0x0004 +#define ixKHFS1 0x0008 +#define ixKHFS2 0x000C +#define ixKHFS3 0x0010 +#define ixKSESSION0 0x0014 +#define ixKSESSION1 0x0018 +#define ixKSESSION2 0x001C +#define ixKSESSION3 0x0020 +#define ixKSIG0 0x0024 +#define ixKSIG1 0x0028 +#define ixKSIG2 0x002C +#define ixKSIG3 0x0030 +#define ixLX0 0x0054 +#define ixLX1 0x0058 +#define ixLX2 0x005C +#define ixLX3 0x0060 +#define ixRINGOSC_MASK 0x0288 +#define ixSPU_PORT_STATUS 0x029C +#define mmCC_DRM_ID_STRAPS 0x1559 +#define mmCC_SYS_RB_BACKEND_DISABLE 0x03A0 +#define mmCC_SYS_RB_REDUNDANCY 0x039F +#define mmCGTT_DRM_CLK_CTRL0 0x1579 +#define mmCP_CONFIG 0x0F92 +#define mmDC_TEST_DEBUG_DATA 0x157D +#define mmDC_TEST_DEBUG_INDEX 0x157C +#define mmGC_USER_SYS_RB_BACKEND_DISABLE 0x03A1 +#define mmHDP_ADDR_CONFIG 0x0BD2 +#define mmHDP_DEBUG0 0x0BCC +#define mmHDP_DEBUG1 0x0BCD +#define mmHDP_HOST_PATH_CNTL 0x0B00 +#define mmHDP_LAST_SURFACE_HIT 0x0BCE +#define mmHDP_MEMIO_ADDR 0x0BF7 +#define mmHDP_MEMIO_CNTL 0x0BF6 +#define mmHDP_MEMIO_RD_DATA 0x0BFA +#define mmHDP_MEMIO_STATUS 0x0BF8 +#define mmHDP_MEMIO_WR_DATA 0x0BF9 +#define mmHDP_MEM_POWER_LS 0x0BD4 +#define mmHDP_MISC_CNTL 0x0BD3 +#define mmHDP_NONSURFACE_BASE 0x0B01 +#define mmHDP_NONSURFACE_INFO 0x0B02 +#define mmHDP_NONSURFACE_PREFETCH 0x0BD5 +#define mmHDP_NONSURFACE_SIZE 0x0B03 +#define mmHDP_NONSURF_FLAGS 0x0BC9 +#define mmHDP_NONSURF_FLAGS_CLR 0x0BCA +#define mmHDP_OUTSTANDING_REQ 0x0BD1 +#define mmHDP_SC_MULTI_CHIP_CNTL 0x0BD0 +#define mmHDP_SW_SEMAPHORE 0x0BCB +#define mmHDP_TILING_CONFIG 0x0BCF +#define mmHDP_XDP_BARS_ADDR_39_36 0x0C44 +#define mmHDP_XDP_BUSY_STS 0x0C3E +#define mmHDP_XDP_CGTT_BLK_CTRL 0x0C33 +#define mmHDP_XDP_CHKN 0x0C40 +#define mmHDP_XDP_D2H_BAR_UPDATE 0x0C02 +#define mmHDP_XDP_D2H_FLUSH 0x0C01 +#define mmHDP_XDP_D2H_RSVD_10 0x0C0A +#define mmHDP_XDP_D2H_RSVD_11 0x0C0B +#define mmHDP_XDP_D2H_RSVD_12 0x0C0C +#define mmHDP_XDP_D2H_RSVD_13 0x0C0D +#define mmHDP_XDP_D2H_RSVD_14 0x0C0E +#define mmHDP_XDP_D2H_RSVD_15 0x0C0F +#define mmHDP_XDP_D2H_RSVD_16 0x0C10 +#define mmHDP_XDP_D2H_RSVD_17 0x0C11 +#define mmHDP_XDP_D2H_RSVD_18 0x0C12 +#define mmHDP_XDP_D2H_RSVD_19 0x0C13 +#define mmHDP_XDP_D2H_RSVD_20 0x0C14 +#define mmHDP_XDP_D2H_RSVD_21 0x0C15 +#define mmHDP_XDP_D2H_RSVD_22 0x0C16 +#define mmHDP_XDP_D2H_RSVD_23 0x0C17 +#define mmHDP_XDP_D2H_RSVD_24 0x0C18 +#define mmHDP_XDP_D2H_RSVD_25 0x0C19 +#define mmHDP_XDP_D2H_RSVD_26 0x0C1A +#define mmHDP_XDP_D2H_RSVD_27 0x0C1B +#define mmHDP_XDP_D2H_RSVD_28 0x0C1C +#define mmHDP_XDP_D2H_RSVD_29 0x0C1D +#define mmHDP_XDP_D2H_RSVD_30 0x0C1E +#define mmHDP_XDP_D2H_RSVD_3 0x0C03 +#define mmHDP_XDP_D2H_RSVD_31 0x0C1F +#define mmHDP_XDP_D2H_RSVD_32 0x0C20 +#define mmHDP_XDP_D2H_RSVD_33 0x0C21 +#define mmHDP_XDP_D2H_RSVD_34 0x0C22 +#define mmHDP_XDP_D2H_RSVD_4 0x0C04 +#define mmHDP_XDP_D2H_RSVD_5 0x0C05 +#define mmHDP_XDP_D2H_RSVD_6 0x0C06 +#define mmHDP_XDP_D2H_RSVD_7 0x0C07 +#define mmHDP_XDP_D2H_RSVD_8 0x0C08 +#define mmHDP_XDP_D2H_RSVD_9 0x0C09 +#define mmHDP_XDP_DBG_ADDR 0x0C41 +#define mmHDP_XDP_DBG_DATA 0x0C42 +#define mmHDP_XDP_DBG_MASK 0x0C43 +#define mmHDP_XDP_DIRECT2HDP_FIRST 0x0C00 +#define mmHDP_XDP_DIRECT2HDP_LAST 0x0C23 +#define mmHDP_XDP_FLUSH_ARMED_STS 0x0C3C +#define mmHDP_XDP_FLUSH_CNTR0_STS 0x0C3D +#define mmHDP_XDP_HDP_IPH_CFG 0x0C31 +#define mmHDP_XDP_HDP_MBX_MC_CFG 0x0C2D +#define mmHDP_XDP_HDP_MC_CFG 0x0C2E +#define mmHDP_XDP_HST_CFG 0x0C2F +#define mmHDP_XDP_P2P_BAR0 0x0C34 +#define mmHDP_XDP_P2P_BAR1 0x0C35 +#define mmHDP_XDP_P2P_BAR2 0x0C36 +#define mmHDP_XDP_P2P_BAR3 0x0C37 +#define mmHDP_XDP_P2P_BAR4 0x0C38 +#define mmHDP_XDP_P2P_BAR5 0x0C39 +#define mmHDP_XDP_P2P_BAR6 0x0C3A +#define mmHDP_XDP_P2P_BAR7 0x0C3B +#define mmHDP_XDP_P2P_BAR_CFG 0x0C24 +#define mmHDP_XDP_P2P_MBX_ADDR0 0x0C26 +#define mmHDP_XDP_P2P_MBX_ADDR1 0x0C27 +#define mmHDP_XDP_P2P_MBX_ADDR2 0x0C28 +#define mmHDP_XDP_P2P_MBX_ADDR3 0x0C29 +#define mmHDP_XDP_P2P_MBX_ADDR4 0x0C2A +#define mmHDP_XDP_P2P_MBX_ADDR5 0x0C2B +#define mmHDP_XDP_P2P_MBX_ADDR6 0x0C2C +#define mmHDP_XDP_P2P_MBX_OFFSET 0x0C25 +#define mmHDP_XDP_SID_CFG 0x0C30 +#define mmHDP_XDP_SRBM_CFG 0x0C32 +#define mmHDP_XDP_STICKY 0x0C3F +#define mmIH_ADVFAULT_CNTL 0x0F8C +#define mmIH_CNTL 0x0F86 +#define mmIH_LEVEL_STATUS 0x0F87 +#define mmIH_PERFCOUNTER0_RESULT 0x0F8A +#define mmIH_PERFCOUNTER1_RESULT 0x0F8B +#define mmIH_PERFMON_CNTL 0x0F89 +#define mmIH_RB_BASE 0x0F81 +#define mmIH_RB_CNTL 0x0F80 +#define mmIH_RB_RPTR 0x0F82 +#define mmIH_RB_WPTR 0x0F83 +#define mmIH_RB_WPTR_ADDR_HI 0x0F84 +#define mmIH_RB_WPTR_ADDR_LO 0x0F85 +#define mmIH_STATUS 0x0F88 +#define mmSEM_MAILBOX 0x0F9B +#define mmSEM_MAILBOX_CLIENTCONFIG 0x0F9A +#define mmSEM_MAILBOX_CONTROL 0x0F9C +#define mmSEM_MCIF_CONFIG 0x0F90 +#define mmSRBM_CAM_DATA 0x0397 +#define mmSRBM_CAM_INDEX 0x0396 +#define mmSRBM_CHIP_REVISION 0x039B +#define mmSRBM_CNTL 0x0390 +#define mmSRBM_DEBUG 0x03A4 +#define mmSRBM_DEBUG_CNTL 0x0399 +#define mmSRBM_DEBUG_DATA 0x039A +#define mmSRBM_DEBUG_SNAPSHOT 0x03A5 +#define mmSRBM_GFX_CNTL 0x0391 +#define mmSRBM_INT_ACK 0x03AA +#define mmSRBM_INT_CNTL 0x03A8 +#define mmSRBM_INT_STATUS 0x03A9 +#define mmSRBM_MC_CLKEN_CNTL 0x03B3 +#define mmSRBM_PERFCOUNTER0_HI 0x0704 +#define mmSRBM_PERFCOUNTER0_LO 0x0703 +#define mmSRBM_PERFCOUNTER0_SELECT 0x0701 +#define mmSRBM_PERFCOUNTER1_HI 0x0706 +#define mmSRBM_PERFCOUNTER1_LO 0x0705 +#define mmSRBM_PERFCOUNTER1_SELECT 0x0702 +#define mmSRBM_PERFMON_CNTL 0x0700 +#define mmSRBM_READ_ERROR 0x03A6 +#define mmSRBM_SOFT_RESET 0x0398 +#define mmSRBM_STATUS 0x0394 +#define mmSRBM_STATUS2 0x0393 +#define mmSRBM_SYS_CLKEN_CNTL 0x03B4 +#define mmSRBM_UVD_CLKEN_CNTL 0x03B6 +#define mmSRBM_VCE_CLKEN_CNTL 0x03B5 +#define mmUVD_CONFIG 0x0F98 +#define mmVCE_CONFIG 0x0F94 +#define mmXDMA_MSTR_MEM_OVERFLOW_CNTL 0x03F8 + +/* from the old sid.h */ +#define mmDMA_TILING_CONFIG 0x342E + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_1_0_sh_mask.h new file mode 100644 index 000000000000..1c540fe136cb --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_1_0_sh_mask.h @@ -0,0 +1,1079 @@ +/* + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef OSS_1_0_SH_MASK_H +#define OSS_1_0_SH_MASK_H + +#define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000L +#define CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT 0x0000001c +#define CC_DRM_ID_STRAPS__DEVICE_ID_MASK 0x000ffff0L +#define CC_DRM_ID_STRAPS__DEVICE_ID__SHIFT 0x00000004 +#define CC_DRM_ID_STRAPS__MAJOR_REV_ID_MASK 0x00f00000L +#define CC_DRM_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x00000014 +#define CC_DRM_ID_STRAPS__MINOR_REV_ID_MASK 0x0f000000L +#define CC_DRM_ID_STRAPS__MINOR_REV_ID__SHIFT 0x00000018 +#define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00ff0000L +#define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x00000010 +#define CLIENT0_BM__RESERVED_MASK 0xffffffffL +#define CLIENT0_BM__RESERVED__SHIFT 0x00000000 +#define CLIENT0_CD0__RESERVED_MASK 0xffffffffL +#define CLIENT0_CD0__RESERVED__SHIFT 0x00000000 +#define CLIENT0_CD1__RESERVED_MASK 0xffffffffL +#define CLIENT0_CD1__RESERVED__SHIFT 0x00000000 +#define CLIENT0_CD2__RESERVED_MASK 0xffffffffL +#define CLIENT0_CD2__RESERVED__SHIFT 0x00000000 +#define CLIENT0_CD3__RESERVED_MASK 0xffffffffL +#define CLIENT0_CD3__RESERVED__SHIFT 0x00000000 +#define CLIENT0_CK0__RESERVED_MASK 0xffffffffL +#define CLIENT0_CK0__RESERVED__SHIFT 0x00000000 +#define CLIENT0_CK1__RESERVED_MASK 0xffffffffL +#define CLIENT0_CK1__RESERVED__SHIFT 0x00000000 +#define CLIENT0_CK2__RESERVED_MASK 0xffffffffL +#define CLIENT0_CK2__RESERVED__SHIFT 0x00000000 +#define CLIENT0_CK3__RESERVED_MASK 0xffffffffL +#define CLIENT0_CK3__RESERVED__SHIFT 0x00000000 +#define CLIENT0_K0__RESERVED_MASK 0xffffffffL +#define CLIENT0_K0__RESERVED__SHIFT 0x00000000 +#define CLIENT0_K1__RESERVED_MASK 0xffffffffL +#define CLIENT0_K1__RESERVED__SHIFT 0x00000000 +#define CLIENT0_K2__RESERVED_MASK 0xffffffffL +#define CLIENT0_K2__RESERVED__SHIFT 0x00000000 +#define CLIENT0_K3__RESERVED_MASK 0xffffffffL +#define CLIENT0_K3__RESERVED__SHIFT 0x00000000 +#define CLIENT0_OFFSET_HI__RESERVED_MASK 0xffffffffL +#define CLIENT0_OFFSET_HI__RESERVED__SHIFT 0x00000000 +#define CLIENT0_OFFSET__RESERVED_MASK 0xffffffffL +#define CLIENT0_OFFSET__RESERVED__SHIFT 0x00000000 +#define CLIENT0_STATUS__RESERVED_MASK 0xffffffffL +#define CLIENT0_STATUS__RESERVED__SHIFT 0x00000000 +#define CLIENT1_BM__RESERVED_MASK 0xffffffffL +#define CLIENT1_BM__RESERVED__SHIFT 0x00000000 +#define CLIENT1_CD0__RESERVED_MASK 0xffffffffL +#define CLIENT1_CD0__RESERVED__SHIFT 0x00000000 +#define CLIENT1_CD1__RESERVED_MASK 0xffffffffL +#define CLIENT1_CD1__RESERVED__SHIFT 0x00000000 +#define CLIENT1_CD2__RESERVED_MASK 0xffffffffL +#define CLIENT1_CD2__RESERVED__SHIFT 0x00000000 +#define CLIENT1_CD3__RESERVED_MASK 0xffffffffL +#define CLIENT1_CD3__RESERVED__SHIFT 0x00000000 +#define CLIENT1_CK0__RESERVED_MASK 0xffffffffL +#define CLIENT1_CK0__RESERVED__SHIFT 0x00000000 +#define CLIENT1_CK1__RESERVED_MASK 0xffffffffL +#define CLIENT1_CK1__RESERVED__SHIFT 0x00000000 +#define CLIENT1_CK2__RESERVED_MASK 0xffffffffL +#define CLIENT1_CK2__RESERVED__SHIFT 0x00000000 +#define CLIENT1_CK3__RESERVED_MASK 0xffffffffL +#define CLIENT1_CK3__RESERVED__SHIFT 0x00000000 +#define CLIENT1_K0__RESERVED_MASK 0xffffffffL +#define CLIENT1_K0__RESERVED__SHIFT 0x00000000 +#define CLIENT1_K1__RESERVED_MASK 0xffffffffL +#define CLIENT1_K1__RESERVED__SHIFT 0x00000000 +#define CLIENT1_K2__RESERVED_MASK 0xffffffffL +#define CLIENT1_K2__RESERVED__SHIFT 0x00000000 +#define CLIENT1_K3__RESERVED_MASK 0xffffffffL +#define CLIENT1_K3__RESERVED__SHIFT 0x00000000 +#define CLIENT1_OFFSET_HI__RESERVED_MASK 0xffffffffL +#define CLIENT1_OFFSET_HI__RESERVED__SHIFT 0x00000000 +#define CLIENT1_OFFSET__RESERVED_MASK 0xffffffffL +#define CLIENT1_OFFSET__RESERVED__SHIFT 0x00000000 +#define CLIENT1_PORT_STATUS__RESERVED_MASK 0xffffffffL +#define CLIENT1_PORT_STATUS__RESERVED__SHIFT 0x00000000 +#define CLIENT2_BM__RESERVED_MASK 0xffffffffL +#define CLIENT2_BM__RESERVED__SHIFT 0x00000000 +#define CLIENT2_CD0__RESERVED_MASK 0xffffffffL +#define CLIENT2_CD0__RESERVED__SHIFT 0x00000000 +#define CLIENT2_CD1__RESERVED_MASK 0xffffffffL +#define CLIENT2_CD1__RESERVED__SHIFT 0x00000000 +#define CLIENT2_CD2__RESERVED_MASK 0xffffffffL +#define CLIENT2_CD2__RESERVED__SHIFT 0x00000000 +#define CLIENT2_CD3__RESERVED_MASK 0xffffffffL +#define CLIENT2_CD3__RESERVED__SHIFT 0x00000000 +#define CLIENT2_CK0__RESERVED_MASK 0xffffffffL +#define CLIENT2_CK0__RESERVED__SHIFT 0x00000000 +#define CLIENT2_CK1__RESERVED_MASK 0xffffffffL +#define CLIENT2_CK1__RESERVED__SHIFT 0x00000000 +#define CLIENT2_CK2__RESERVED_MASK 0xffffffffL +#define CLIENT2_CK2__RESERVED__SHIFT 0x00000000 +#define CLIENT2_CK3__RESERVED_MASK 0xffffffffL +#define CLIENT2_CK3__RESERVED__SHIFT 0x00000000 +#define CLIENT2_K0__RESERVED_MASK 0xffffffffL +#define CLIENT2_K0__RESERVED__SHIFT 0x00000000 +#define CLIENT2_K1__RESERVED_MASK 0xffffffffL +#define CLIENT2_K1__RESERVED__SHIFT 0x00000000 +#define CLIENT2_K2__RESERVED_MASK 0xffffffffL +#define CLIENT2_K2__RESERVED__SHIFT 0x00000000 +#define CLIENT2_K3__RESERVED_MASK 0xffffffffL +#define CLIENT2_K3__RESERVED__SHIFT 0x00000000 +#define CLIENT2_OFFSET_HI__RESERVED_MASK 0xffffffffL +#define CLIENT2_OFFSET_HI__RESERVED__SHIFT 0x00000000 +#define CLIENT2_OFFSET__RESERVED_MASK 0xffffffffL +#define CLIENT2_OFFSET__RESERVED__SHIFT 0x00000000 +#define CLIENT2_STATUS__RESERVED_MASK 0xffffffffL +#define CLIENT2_STATUS__RESERVED__SHIFT 0x00000000 +#define CLIENT3_BM__RESERVED_MASK 0xffffffffL +#define CLIENT3_BM__RESERVED__SHIFT 0x00000000 +#define CLIENT3_CD0__RESERVED_MASK 0xffffffffL +#define CLIENT3_CD0__RESERVED__SHIFT 0x00000000 +#define CLIENT3_CD1__RESERVED_MASK 0xffffffffL +#define CLIENT3_CD1__RESERVED__SHIFT 0x00000000 +#define CLIENT3_CD2__RESERVED_MASK 0xffffffffL +#define CLIENT3_CD2__RESERVED__SHIFT 0x00000000 +#define CLIENT3_CD3__RESERVED_MASK 0xffffffffL +#define CLIENT3_CD3__RESERVED__SHIFT 0x00000000 +#define CLIENT3_CK0__RESERVED_MASK 0xffffffffL +#define CLIENT3_CK0__RESERVED__SHIFT 0x00000000 +#define CLIENT3_CK1__RESERVED_MASK 0xffffffffL +#define CLIENT3_CK1__RESERVED__SHIFT 0x00000000 +#define CLIENT3_CK2__RESERVED_MASK 0xffffffffL +#define CLIENT3_CK2__RESERVED__SHIFT 0x00000000 +#define CLIENT3_CK3__RESERVED_MASK 0xffffffffL +#define CLIENT3_CK3__RESERVED__SHIFT 0x00000000 +#define CLIENT3_K0__RESERVED_MASK 0xffffffffL +#define CLIENT3_K0__RESERVED__SHIFT 0x00000000 +#define CLIENT3_K1__RESERVED_MASK 0xffffffffL +#define CLIENT3_K1__RESERVED__SHIFT 0x00000000 +#define CLIENT3_K2__RESERVED_MASK 0xffffffffL +#define CLIENT3_K2__RESERVED__SHIFT 0x00000000 +#define CLIENT3_K3__RESERVED_MASK 0xffffffffL +#define CLIENT3_K3__RESERVED__SHIFT 0x00000000 +#define CLIENT3_OFFSET_HI__RESERVED_MASK 0xffffffffL +#define CLIENT3_OFFSET_HI__RESERVED__SHIFT 0x00000000 +#define CLIENT3_OFFSET__RESERVED_MASK 0xffffffffL +#define CLIENT3_OFFSET__RESERVED__SHIFT 0x00000000 +#define CLIENT3_STATUS__RESERVED_MASK 0xffffffffL +#define CLIENT3_STATUS__RESERVED__SHIFT 0x00000000 +#define CP_CONFIG__CP_RDREQ_URG_MASK 0x00000f00L +#define CP_CONFIG__CP_RDREQ_URG__SHIFT 0x00000008 +#define CP_CONFIG__CP_REQ_TRAN_MASK 0x00010000L +#define CP_CONFIG__CP_REQ_TRAN__SHIFT 0x00000010 +#define DC_TEST_DEBUG_DATA__DC_TEST_DEBUG_DATA_MASK 0xffffffffL +#define DC_TEST_DEBUG_DATA__DC_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define DH_TEST__DH_TEST_MASK 0x00000001L +#define DH_TEST__DH_TEST__SHIFT 0x00000000 +#define EXP0__RESERVED_MASK 0xffffffffL +#define EXP0__RESERVED__SHIFT 0x00000000 +#define EXP1__RESERVED_MASK 0xffffffffL +#define EXP1__RESERVED__SHIFT 0x00000000 +#define EXP2__RESERVED_MASK 0xffffffffL +#define EXP2__RESERVED__SHIFT 0x00000000 +#define EXP3__RESERVED_MASK 0xffffffffL +#define EXP3__RESERVED__SHIFT 0x00000000 +#define EXP4__RESERVED_MASK 0xffffffffL +#define EXP4__RESERVED__SHIFT 0x00000000 +#define EXP5__RESERVED_MASK 0xffffffffL +#define EXP5__RESERVED__SHIFT 0x00000000 +#define EXP6__RESERVED_MASK 0xffffffffL +#define EXP6__RESERVED__SHIFT 0x00000000 +#define EXP7__RESERVED_MASK 0xffffffffL +#define EXP7__RESERVED__SHIFT 0x00000000 +#define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00ff0000L +#define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x00000010 +#define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008 +#define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L +#define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x00000018 +#define HDP_ADDR_CONFIG__NUM_GPUS_MASK 0x00700000L +#define HDP_ADDR_CONFIG__NUM_GPUS__SHIFT 0x00000014 +#define HDP_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L +#define HDP_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e +#define HDP_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define HDP_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000 +#define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L +#define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c +#define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L +#define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004 +#define HDP_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L +#define HDP_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c +#define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L +#define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010 +#define HDP_DEBUG0__HDP_DEBUG__SHIFT 0x00000000 +#define HDP_DEBUG1__HDP_DEBUG__SHIFT 0x00000000 +#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK 0x20000000L +#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x0000001d +#define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT_MASK 0x00000007L +#define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT__SHIFT 0x00000000 +#define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE_MASK 0x00400000L +#define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE__SHIFT 0x00000016 +#define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK 0x00800000L +#define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS__SHIFT 0x00000017 +#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS_MASK 0x80000000L +#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS__SHIFT 0x0000001f +#define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT_MASK 0x000001f8L +#define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT__SHIFT 0x00000003 +#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK 0x00001800L +#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT 0x0000000b +#define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT_MASK 0x0f000000L +#define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT__SHIFT 0x00000018 +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK 0x00200000L +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT 0x00000015 +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK 0x00180000L +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x00000013 +#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS_MASK 0x40000000L +#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS__SHIFT 0x0000001e +#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK 0x00000600L +#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT 0x00000009 +#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK 0x0000003fL +#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT 0x00000000 +#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK 0xffffffffL +#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT 0x00000000 +#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK 0x00003f00L +#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT 0x00000008 +#define HDP_MEMIO_CNTL__MEMIO_BE_MASK 0x0000003cL +#define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x00000002 +#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK 0x00008000L +#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT 0x0000000f +#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK 0x00004000L +#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT 0x0000000e +#define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x00000002L +#define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT 0x00000001 +#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK 0x00000080L +#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT 0x00000007 +#define HDP_MEMIO_CNTL__MEMIO_SEND_MASK 0x00000001L +#define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x00000000 +#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK 0x00000040L +#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT 0x00000006 +#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK 0xffffffffL +#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT 0x00000000 +#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK 0x00000008L +#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT 0x00000003 +#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x00000002L +#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT 0x00000001 +#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK 0x00000004L +#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x00000002 +#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK 0x00000001L +#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT 0x00000000 +#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK 0xffffffffL +#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT 0x00000000 +#define HDP_MEM_POWER_LS__LS_ENABLE_MASK 0x00000001L +#define HDP_MEM_POWER_LS__LS_ENABLE__SHIFT 0x00000000 +#define HDP_MEM_POWER_LS__LS_HOLD_MASK 0x00001f80L +#define HDP_MEM_POWER_LS__LS_HOLD__SHIFT 0x00000007 +#define HDP_MEM_POWER_LS__LS_SETUP_MASK 0x0000007eL +#define HDP_MEM_POWER_LS__LS_SETUP__SHIFT 0x00000001 +#define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS_MASK 0x00100000L +#define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS__SHIFT 0x00000014 +#define HDP_MISC_CNTL__FED_ENABLE_MASK 0x00200000L +#define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x00000015 +#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK 0x00000001L +#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE__SHIFT 0x00000000 +#define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT_MASK 0x00000780L +#define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT__SHIFT 0x00000007 +#define HDP_MISC_CNTL__MC_RDREQ_CREDIT_MASK 0x0007e000L +#define HDP_MISC_CNTL__MC_RDREQ_CREDIT__SHIFT 0x0000000d +#define HDP_MISC_CNTL__MULTIPLE_READS_MASK 0x00000040L +#define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT 0x00000006 +#define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR_MASK 0x00001000L +#define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR__SHIFT 0x0000000c +#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x00000020L +#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x00000005 +#define HDP_MISC_CNTL__READ_CACHE_INVALIDATE_MASK 0x00080000L +#define HDP_MISC_CNTL__READ_CACHE_INVALIDATE__SHIFT 0x00000013 +#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x00000800L +#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0x0000000b +#define HDP_MISC_CNTL__VM_ID_MASK 0x0000001eL +#define HDP_MISC_CNTL__VM_ID__SHIFT 0x00000001 +#define HDP_NONSURFACE_BASE__NONSURF_BASE_MASK 0xffffffffL +#define HDP_NONSURFACE_BASE__NONSURF_BASE__SHIFT 0x00000000 +#define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE_MASK 0x00000001L +#define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE__SHIFT 0x00000000 +#define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE_MASK 0x0000001eL +#define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE__SHIFT 0x00000001 +#define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT_MASK 0x03000000L +#define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT__SHIFT 0x00000018 +#define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH_MASK 0x00c00000L +#define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH__SHIFT 0x00000016 +#define HDP_NONSURFACE_INFO__NONSURF_ENDIAN_MASK 0x00000060L +#define HDP_NONSURFACE_INFO__NONSURF_ENDIAN__SHIFT 0x00000005 +#define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT_MASK 0x0c000000L +#define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT__SHIFT 0x0000001a +#define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE_MASK 0x30000000L +#define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE__SHIFT 0x0000001c +#define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS_MASK 0x00300000L +#define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS__SHIFT 0x00000014 +#define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE_MASK 0x00000380L +#define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE__SHIFT 0x00000007 +#define HDP_NONSURFACE_INFO__NONSURF_PRIV_MASK 0x00008000L +#define HDP_NONSURFACE_INFO__NONSURF_PRIV__SHIFT 0x0000000f +#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM_MASK 0x00001c00L +#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM__SHIFT 0x0000000a +#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE_MASK 0x00006000L +#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE__SHIFT 0x0000000d +#define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB_MASK 0x40000000L +#define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB__SHIFT 0x0000001e +#define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT_MASK 0x00010000L +#define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT__SHIFT 0x00000010 +#define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT_MASK 0x000e0000L +#define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT__SHIFT 0x00000011 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG_MASK 0xf8000000L +#define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG__SHIFT 0x0000001b +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR_MASK 0x00000038L +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR__SHIFT 0x00000003 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z_MASK 0x000ffe00L +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z__SHIFT 0x00000009 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM_MASK 0x000001c0L +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM__SHIFT 0x00000006 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI_MASK 0x00000007L +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI__SHIFT 0x00000000 +#define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX_MASK 0x000007ffL +#define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX__SHIFT 0x00000000 +#define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX_MASK 0xfffff800L +#define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX__SHIFT 0x0000000b +#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x00000002L +#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT 0x00000001 +#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK 0x00000001L +#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT 0x00000000 +#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x00000002L +#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT 0x00000001 +#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK 0x00000001L +#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT 0x00000000 +#define HDP_OUTSTANDING_REQ__READ_REQ_MASK 0x0000ff00L +#define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT 0x00000008 +#define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK 0x000000ffL +#define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT 0x00000000 +#define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS_MASK 0x00000007L +#define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS__SHIFT 0x00000000 +#define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE_MASK 0x00000018L +#define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE__SHIFT 0x00000003 +#define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK 0xffffffffL +#define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT 0x00000000 +#define HDP_TILING_CONFIG__BANK_SWAPS_MASK 0x00003800L +#define HDP_TILING_CONFIG__BANK_SWAPS__SHIFT 0x0000000b +#define HDP_TILING_CONFIG__BANK_TILING_MASK 0x00000030L +#define HDP_TILING_CONFIG__BANK_TILING__SHIFT 0x00000004 +#define HDP_TILING_CONFIG__GROUP_SIZE_MASK 0x000000c0L +#define HDP_TILING_CONFIG__GROUP_SIZE__SHIFT 0x00000006 +#define HDP_TILING_CONFIG__PIPE_TILING_MASK 0x0000000eL +#define HDP_TILING_CONFIG__PIPE_TILING__SHIFT 0x00000001 +#define HDP_TILING_CONFIG__ROW_TILING_MASK 0x00000700L +#define HDP_TILING_CONFIG__ROW_TILING__SHIFT 0x00000008 +#define HDP_TILING_CONFIG__SAMPLE_SPLIT_MASK 0x0000c000L +#define HDP_TILING_CONFIG__SAMPLE_SPLIT__SHIFT 0x0000000e +#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK 0x0000000fL +#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT 0x00000000 +#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK 0x000000f0L +#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT 0x00000004 +#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK 0x00000f00L +#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT 0x00000008 +#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK 0x0000f000L +#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT 0x0000000c +#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK 0x000f0000L +#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT 0x00000010 +#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK 0x00f00000L +#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT 0x00000014 +#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK 0x0f000000L +#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT 0x00000018 +#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK 0xf0000000L +#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT 0x0000001c +#define HDP_XDP_BUSY_STS__BUSY_BITS_MASK 0x0003ffffL +#define HDP_XDP_BUSY_STS__BUSY_BITS__SHIFT 0x00000000 +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY_MASK 0x0000000fL +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY__SHIFT 0x00000000 +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY_MASK 0x00000ff0L +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY__SHIFT 0x00000004 +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD_MASK 0x3ffff000L +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD__SHIFT 0x0000000c +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE_MASK 0x40000000L +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE__SHIFT 0x0000001e +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE_MASK 0x80000000L +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE__SHIFT 0x0000001f +#define HDP_XDP_CHKN__CHKN_0_RSVD_MASK 0x000000ffL +#define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT 0x00000000 +#define HDP_XDP_CHKN__CHKN_1_RSVD_MASK 0x0000ff00L +#define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x00000008 +#define HDP_XDP_CHKN__CHKN_2_RSVD_MASK 0x00ff0000L +#define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT 0x00000010 +#define HDP_XDP_CHKN__CHKN_3_RSVD_MASK 0xff000000L +#define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT 0x00000018 +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK 0x0000ffffL +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT 0x00000000 +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK 0x00700000L +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x00000014 +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK 0x000f0000L +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x00000010 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK 0x00040000L +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT 0x00000012 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK 0x0000000fL +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT 0x00000000 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK 0x00000700L +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT 0x00000008 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK 0x000000f0L +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT 0x00000004 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK 0x00080000L +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT 0x00000013 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK 0x00100000L +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x00000014 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK 0x00010000L +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x00000010 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE_MASK 0x00020000L +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE__SHIFT 0x00000011 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK 0x0000f800L +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT 0x0000000b +#define HDP_XDP_D2H_RSVD_10__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_11__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_12__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_13__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_14__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_15__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_16__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_17__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_18__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_19__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_20__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_21__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_22__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_23__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_24__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_25__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_26__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_27__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_28__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_29__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_30__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_31__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_32__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_33__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_34__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_3__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_4__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_5__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_6__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_7__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_8__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_9__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_DBG_ADDR__CTRL_MASK 0xffff0000L +#define HDP_XDP_DBG_ADDR__CTRL__SHIFT 0x00000010 +#define HDP_XDP_DBG_ADDR__STS_MASK 0x0000ffffL +#define HDP_XDP_DBG_ADDR__STS__SHIFT 0x00000000 +#define HDP_XDP_DBG_DATA__CTRL_MASK 0xffff0000L +#define HDP_XDP_DBG_DATA__CTRL__SHIFT 0x00000010 +#define HDP_XDP_DBG_DATA__STS_MASK 0x0000ffffL +#define HDP_XDP_DBG_DATA__STS__SHIFT 0x00000000 +#define HDP_XDP_DBG_MASK__CTRL_MASK 0xffff0000L +#define HDP_XDP_DBG_MASK__CTRL__SHIFT 0x00000010 +#define HDP_XDP_DBG_MASK__STS_MASK 0x0000ffffL +#define HDP_XDP_DBG_MASK__STS__SHIFT 0x00000000 +#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK 0xffffffffL +#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK 0xffffffffL +#define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK 0xffffffffL +#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT 0x00000000 +#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK 0x03ffffffL +#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT 0x00000000 +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK 0x00001000L +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT 0x0000000c +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK 0x00002000L +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT 0x0000000d +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE_MASK 0x0000003fL +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE__SHIFT 0x00000000 +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE_MASK 0x00000fc0L +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE__SHIFT 0x00000006 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV_MASK 0x00000001L +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV__SHIFT 0x00000000 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK 0x00000006L +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT 0x00000001 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN_MASK 0x00000008L +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN__SHIFT 0x00000003 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK 0x000000f0L +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT 0x00000004 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV_MASK 0x00000001L +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV__SHIFT 0x00000000 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP_MASK 0x00000006L +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP__SHIFT 0x00000001 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN_MASK 0x00000008L +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN__SHIFT 0x00000003 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID_MASK 0x07800000L +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID__SHIFT 0x00000017 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK_MASK 0x00700000L +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK__SHIFT 0x00000014 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV_MASK 0x00000010L +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV__SHIFT 0x00000004 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP_MASK 0x00000060L +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP__SHIFT 0x00000005 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN_MASK 0x00000080L +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN__SHIFT 0x00000007 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID_MASK 0x78000000L +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID__SHIFT 0x0000001b +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK 0x000fc000L +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT 0x0000000e +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE_MASK 0x00003f00L +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE__SHIFT 0x00000008 +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK 0x00000001L +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT 0x00000000 +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK 0x00000006L +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT 0x00000001 +#define HDP_XDP_P2P_BAR0__ADDR_MASK 0x0000ffffL +#define HDP_XDP_P2P_BAR0__ADDR__SHIFT 0x00000000 +#define HDP_XDP_P2P_BAR0__FLUSH_MASK 0x000f0000L +#define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x00000010 +#define HDP_XDP_P2P_BAR0__VALID_MASK 0x00100000L +#define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x00000014 +#define HDP_XDP_P2P_BAR1__ADDR_MASK 0x0000ffffL +#define HDP_XDP_P2P_BAR1__ADDR__SHIFT 0x00000000 +#define HDP_XDP_P2P_BAR1__FLUSH_MASK 0x000f0000L +#define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x00000010 +#define HDP_XDP_P2P_BAR1__VALID_MASK 0x00100000L +#define HDP_XDP_P2P_BAR1__VALID__SHIFT 0x00000014 +#define HDP_XDP_P2P_BAR2__ADDR_MASK 0x0000ffffL +#define HDP_XDP_P2P_BAR2__ADDR__SHIFT 0x00000000 +#define HDP_XDP_P2P_BAR2__FLUSH_MASK 0x000f0000L +#define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x00000010 +#define HDP_XDP_P2P_BAR2__VALID_MASK 0x00100000L +#define HDP_XDP_P2P_BAR2__VALID__SHIFT 0x00000014 +#define HDP_XDP_P2P_BAR3__ADDR_MASK 0x0000ffffL +#define HDP_XDP_P2P_BAR3__ADDR__SHIFT 0x00000000 +#define HDP_XDP_P2P_BAR3__FLUSH_MASK 0x000f0000L +#define HDP_XDP_P2P_BAR3__FLUSH__SHIFT 0x00000010 +#define HDP_XDP_P2P_BAR3__VALID_MASK 0x00100000L +#define HDP_XDP_P2P_BAR3__VALID__SHIFT 0x00000014 +#define HDP_XDP_P2P_BAR4__ADDR_MASK 0x0000ffffL +#define HDP_XDP_P2P_BAR4__ADDR__SHIFT 0x00000000 +#define HDP_XDP_P2P_BAR4__FLUSH_MASK 0x000f0000L +#define HDP_XDP_P2P_BAR4__FLUSH__SHIFT 0x00000010 +#define HDP_XDP_P2P_BAR4__VALID_MASK 0x00100000L +#define HDP_XDP_P2P_BAR4__VALID__SHIFT 0x00000014 +#define HDP_XDP_P2P_BAR5__ADDR_MASK 0x0000ffffL +#define HDP_XDP_P2P_BAR5__ADDR__SHIFT 0x00000000 +#define HDP_XDP_P2P_BAR5__FLUSH_MASK 0x000f0000L +#define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x00000010 +#define HDP_XDP_P2P_BAR5__VALID_MASK 0x00100000L +#define HDP_XDP_P2P_BAR5__VALID__SHIFT 0x00000014 +#define HDP_XDP_P2P_BAR6__ADDR_MASK 0x0000ffffL +#define HDP_XDP_P2P_BAR6__ADDR__SHIFT 0x00000000 +#define HDP_XDP_P2P_BAR6__FLUSH_MASK 0x000f0000L +#define HDP_XDP_P2P_BAR6__FLUSH__SHIFT 0x00000010 +#define HDP_XDP_P2P_BAR6__VALID_MASK 0x00100000L +#define HDP_XDP_P2P_BAR6__VALID__SHIFT 0x00000014 +#define HDP_XDP_P2P_BAR7__ADDR_MASK 0x0000ffffL +#define HDP_XDP_P2P_BAR7__ADDR__SHIFT 0x00000000 +#define HDP_XDP_P2P_BAR7__FLUSH_MASK 0x000f0000L +#define HDP_XDP_P2P_BAR7__FLUSH__SHIFT 0x00000010 +#define HDP_XDP_P2P_BAR7__VALID_MASK 0x00100000L +#define HDP_XDP_P2P_BAR7__VALID__SHIFT 0x00000014 +#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK 0x0000000fL +#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT 0x00000000 +#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK 0x00000030L +#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT 0x00000004 +#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK 0x01e00000L +#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x00000015 +#define HDP_XDP_P2P_MBX_ADDR0__ADDR_MASK 0x001ffffeL +#define HDP_XDP_P2P_MBX_ADDR0__ADDR__SHIFT 0x00000001 +#define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK 0x00000001L +#define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT 0x00000000 +#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK 0x01e00000L +#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x00000015 +#define HDP_XDP_P2P_MBX_ADDR1__ADDR_MASK 0x001ffffeL +#define HDP_XDP_P2P_MBX_ADDR1__ADDR__SHIFT 0x00000001 +#define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK 0x00000001L +#define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT 0x00000000 +#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK 0x01e00000L +#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x00000015 +#define HDP_XDP_P2P_MBX_ADDR2__ADDR_MASK 0x001ffffeL +#define HDP_XDP_P2P_MBX_ADDR2__ADDR__SHIFT 0x00000001 +#define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK 0x00000001L +#define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT 0x00000000 +#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK 0x01e00000L +#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x00000015 +#define HDP_XDP_P2P_MBX_ADDR3__ADDR_MASK 0x001ffffeL +#define HDP_XDP_P2P_MBX_ADDR3__ADDR__SHIFT 0x00000001 +#define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK 0x00000001L +#define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT 0x00000000 +#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK 0x01e00000L +#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x00000015 +#define HDP_XDP_P2P_MBX_ADDR4__ADDR_MASK 0x001ffffeL +#define HDP_XDP_P2P_MBX_ADDR4__ADDR__SHIFT 0x00000001 +#define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK 0x00000001L +#define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT 0x00000000 +#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK 0x01e00000L +#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x00000015 +#define HDP_XDP_P2P_MBX_ADDR5__ADDR_MASK 0x001ffffeL +#define HDP_XDP_P2P_MBX_ADDR5__ADDR__SHIFT 0x00000001 +#define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK 0x00000001L +#define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT 0x00000000 +#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK 0x01e00000L +#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x00000015 +#define HDP_XDP_P2P_MBX_ADDR6__ADDR_MASK 0x001ffffeL +#define HDP_XDP_P2P_MBX_ADDR6__ADDR__SHIFT 0x00000001 +#define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK 0x00000001L +#define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT 0x00000000 +#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK 0x00003fffL +#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT 0x00000000 +#define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL_MASK 0x00000018L +#define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL__SHIFT 0x00000003 +#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN_MASK 0x00000001L +#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN__SHIFT 0x00000000 +#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER_MASK 0x00000006L +#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER__SHIFT 0x00000001 +#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT_MASK 0x0000003fL +#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT__SHIFT 0x00000000 +#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS_MASK 0x00000040L +#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS__SHIFT 0x00000006 +#define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK_MASK 0x00000080L +#define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK__SHIFT 0x00000007 +#define HDP_XDP_STICKY__STICKY_STS_MASK 0x0000ffffL +#define HDP_XDP_STICKY__STICKY_STS__SHIFT 0x00000000 +#define HDP_XDP_STICKY__STICKY_W1C_MASK 0xffff0000L +#define HDP_XDP_STICKY__STICKY_W1C__SHIFT 0x00000010 +#define HFS_SEED0__RESERVED_MASK 0xffffffffL +#define HFS_SEED0__RESERVED__SHIFT 0x00000000 +#define HFS_SEED1__RESERVED_MASK 0xffffffffL +#define HFS_SEED1__RESERVED__SHIFT 0x00000000 +#define HFS_SEED2__RESERVED_MASK 0xffffffffL +#define HFS_SEED2__RESERVED__SHIFT 0x00000000 +#define HFS_SEED3__RESERVED_MASK 0xffffffffL +#define HFS_SEED3__RESERVED__SHIFT 0x00000000 +#define IH_ADVFAULT_CNTL__NUM_FAULTS_DROPPED_MASK 0x0000ff00L +#define IH_ADVFAULT_CNTL__NUM_FAULTS_DROPPED__SHIFT 0x00000008 +#define IH_ADVFAULT_CNTL__WAIT_TIMER_MASK 0x3fff0000L +#define IH_ADVFAULT_CNTL__WAIT_TIMER__SHIFT 0x00000010 +#define IH_ADVFAULT_CNTL__WATERMARK_ENABLE_MASK 0x00000008L +#define IH_ADVFAULT_CNTL__WATERMARK_ENABLE__SHIFT 0x00000003 +#define IH_ADVFAULT_CNTL__WATERMARK_MASK 0x00000007L +#define IH_ADVFAULT_CNTL__WATERMARK_REACHED_MASK 0x00000010L +#define IH_ADVFAULT_CNTL__WATERMARK_REACHED__SHIFT 0x00000004 +#define IH_ADVFAULT_CNTL__WATERMARK__SHIFT 0x00000000 +#define IH_CNTL__CLIENT_FIFO_HIGHWATER_MASK 0x00000300L +#define IH_CNTL__CLIENT_FIFO_HIGHWATER__SHIFT 0x00000008 +#define IH_CNTL__ENABLE_INTR_MASK 0x00000001L +#define IH_CNTL__ENABLE_INTR__SHIFT 0x00000000 +#define IH_CNTL__MC_FIFO_HIGHWATER_MASK 0x00007c00L +#define IH_CNTL__MC_FIFO_HIGHWATER__SHIFT 0x0000000a +#define IH_CNTL__MC_SWAP_MASK 0x00000006L +#define IH_CNTL__MC_SWAP__SHIFT 0x00000001 +#define IH_CNTL__MC_TRAN_MASK 0x00000008L +#define IH_CNTL__MC_TRAN__SHIFT 0x00000003 +#define IH_CNTL__MC_VMID_MASK 0x1e000000L +#define IH_CNTL__MC_VMID__SHIFT 0x00000019 +#define IH_CNTL__MC_WR_CLEAN_CNT_MASK 0x01f00000L +#define IH_CNTL__MC_WR_CLEAN_CNT__SHIFT 0x00000014 +#define IH_CNTL__MC_WRREQ_CREDIT_MASK 0x000f8000L +#define IH_CNTL__MC_WRREQ_CREDIT__SHIFT 0x0000000f +#define IH_CNTL__RPTR_REARM_MASK 0x00000010L +#define IH_CNTL__RPTR_REARM__SHIFT 0x00000004 +#define IH_LEVEL_STATUS__BIF_STATUS_MASK 0x00000010L +#define IH_LEVEL_STATUS__BIF_STATUS__SHIFT 0x00000004 +#define IH_LEVEL_STATUS__DC_STATUS_MASK 0x00000001L +#define IH_LEVEL_STATUS__DC_STATUS__SHIFT 0x00000000 +#define IH_LEVEL_STATUS__ROM_STATUS_MASK 0x00000004L +#define IH_LEVEL_STATUS__ROM_STATUS__SHIFT 0x00000002 +#define IH_LEVEL_STATUS__SRBM_STATUS_MASK 0x00000008L +#define IH_LEVEL_STATUS__SRBM_STATUS__SHIFT 0x00000003 +#define IH_LEVEL_STATUS__XDMA_STATUS_MASK 0x00000020L +#define IH_LEVEL_STATUS__XDMA_STATUS__SHIFT 0x00000005 +#define IH_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffffL +#define IH_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x00000000 +#define IH_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffffL +#define IH_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x00000000 +#define IH_PERFMON_CNTL__CLEAR0_MASK 0x00000002L +#define IH_PERFMON_CNTL__CLEAR0__SHIFT 0x00000001 +#define IH_PERFMON_CNTL__CLEAR1_MASK 0x00000200L +#define IH_PERFMON_CNTL__CLEAR1__SHIFT 0x00000009 +#define IH_PERFMON_CNTL__ENABLE0_MASK 0x00000001L +#define IH_PERFMON_CNTL__ENABLE0__SHIFT 0x00000000 +#define IH_PERFMON_CNTL__ENABLE1_MASK 0x00000100L +#define IH_PERFMON_CNTL__ENABLE1__SHIFT 0x00000008 +#define IH_PERFMON_CNTL__PERF_SEL0_MASK 0x000000fcL +#define IH_PERFMON_CNTL__PERF_SEL0__SHIFT 0x00000002 +#define IH_PERFMON_CNTL__PERF_SEL1_MASK 0x0000fc00L +#define IH_PERFMON_CNTL__PERF_SEL1__SHIFT 0x0000000a +#define IH_RB_BASE__ADDR_MASK 0xffffffffL +#define IH_RB_BASE__ADDR__SHIFT 0x00000000 +#define IH_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define IH_RB_CNTL__RB_ENABLE__SHIFT 0x00000000 +#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE_MASK 0x00000040L +#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE__SHIFT 0x00000006 +#define IH_RB_CNTL__RB_GPU_TS_ENABLE_MASK 0x00000080L +#define IH_RB_CNTL__RB_GPU_TS_ENABLE__SHIFT 0x00000007 +#define IH_RB_CNTL__RB_SIZE_MASK 0x0000003eL +#define IH_RB_CNTL__RB_SIZE__SHIFT 0x00000001 +#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L +#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x0000001f +#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK 0x00010000L +#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE__SHIFT 0x00000010 +#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L +#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x00000008 +#define IH_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x00003e00L +#define IH_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x00000009 +#define IH_RB_RPTR__OFFSET_MASK 0x0003fffcL +#define IH_RB_RPTR__OFFSET__SHIFT 0x00000002 +#define IH_RB_WPTR_ADDR_HI__ADDR_MASK 0x000000ffL +#define IH_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x00000000 +#define IH_RB_WPTR_ADDR_LO__ADDR_MASK 0xfffffffcL +#define IH_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x00000002 +#define IH_RB_WPTR__OFFSET_MASK 0x0003fffcL +#define IH_RB_WPTR__OFFSET__SHIFT 0x00000002 +#define IH_RB_WPTR__RB_OVERFLOW_MASK 0x00000001L +#define IH_RB_WPTR__RB_OVERFLOW__SHIFT 0x00000000 +#define IH_STATUS__BIF_INTERRUPT_LINE_MASK 0x00000400L +#define IH_STATUS__BIF_INTERRUPT_LINE__SHIFT 0x0000000a +#define IH_STATUS__IDLE_MASK 0x00000001L +#define IH_STATUS__IDLE__SHIFT 0x00000000 +#define IH_STATUS__INPUT_IDLE_MASK 0x00000002L +#define IH_STATUS__INPUT_IDLE__SHIFT 0x00000001 +#define IH_STATUS__MC_WR_CLEAN_PENDING_MASK 0x00000100L +#define IH_STATUS__MC_WR_CLEAN_PENDING__SHIFT 0x00000008 +#define IH_STATUS__MC_WR_CLEAN_STALL_MASK 0x00000200L +#define IH_STATUS__MC_WR_CLEAN_STALL__SHIFT 0x00000009 +#define IH_STATUS__MC_WR_IDLE_MASK 0x00000040L +#define IH_STATUS__MC_WR_IDLE__SHIFT 0x00000006 +#define IH_STATUS__MC_WR_STALL_MASK 0x00000080L +#define IH_STATUS__MC_WR_STALL__SHIFT 0x00000007 +#define IH_STATUS__RB_FULL_DRAIN_MASK 0x00000010L +#define IH_STATUS__RB_FULL_DRAIN__SHIFT 0x00000004 +#define IH_STATUS__RB_FULL_MASK 0x00000008L +#define IH_STATUS__RB_FULL__SHIFT 0x00000003 +#define IH_STATUS__RB_IDLE_MASK 0x00000004L +#define IH_STATUS__RB_IDLE__SHIFT 0x00000002 +#define IH_STATUS__RB_OVERFLOW_MASK 0x00000020L +#define IH_STATUS__RB_OVERFLOW__SHIFT 0x00000005 +#define KEFUSE0__RESERVED_MASK 0xffffffffL +#define KEFUSE0__RESERVED__SHIFT 0x00000000 +#define KEFUSE1__RESERVED_MASK 0xffffffffL +#define KEFUSE1__RESERVED__SHIFT 0x00000000 +#define KEFUSE2__RESERVED_MASK 0xffffffffL +#define KEFUSE2__RESERVED__SHIFT 0x00000000 +#define KEFUSE3__RESERVED_MASK 0xffffffffL +#define KEFUSE3__RESERVED__SHIFT 0x00000000 +#define KHFS0__RESERVED_MASK 0xffffffffL +#define KHFS0__RESERVED__SHIFT 0x00000000 +#define KHFS1__RESERVED_MASK 0xffffffffL +#define KHFS1__RESERVED__SHIFT 0x00000000 +#define KHFS2__RESERVED_MASK 0xffffffffL +#define KHFS2__RESERVED__SHIFT 0x00000000 +#define KHFS3__RESERVED_MASK 0xffffffffL +#define KHFS3__RESERVED__SHIFT 0x00000000 +#define KSESSION0__RESERVED_MASK 0xffffffffL +#define KSESSION0__RESERVED__SHIFT 0x00000000 +#define KSESSION1__RESERVED_MASK 0xffffffffL +#define KSESSION1__RESERVED__SHIFT 0x00000000 +#define KSESSION2__RESERVED_MASK 0xffffffffL +#define KSESSION2__RESERVED__SHIFT 0x00000000 +#define KSESSION3__RESERVED_MASK 0xffffffffL +#define KSESSION3__RESERVED__SHIFT 0x00000000 +#define KSIG0__RESERVED_MASK 0xffffffffL +#define KSIG0__RESERVED__SHIFT 0x00000000 +#define KSIG1__RESERVED_MASK 0xffffffffL +#define KSIG1__RESERVED__SHIFT 0x00000000 +#define KSIG2__RESERVED_MASK 0xffffffffL +#define KSIG2__RESERVED__SHIFT 0x00000000 +#define KSIG3__RESERVED_MASK 0xffffffffL +#define KSIG3__RESERVED__SHIFT 0x00000000 +#define LX0__RESERVED_MASK 0xffffffffL +#define LX0__RESERVED__SHIFT 0x00000000 +#define LX1__RESERVED_MASK 0xffffffffL +#define LX1__RESERVED__SHIFT 0x00000000 +#define LX2__RESERVED_MASK 0xffffffffL +#define LX2__RESERVED__SHIFT 0x00000000 +#define LX3__RESERVED_MASK 0xffffffffL +#define LX3__RESERVED__SHIFT 0x00000000 +#define RINGOSC_MASK__MASK_MASK 0x0000ffffL +#define RINGOSC_MASK__MASK__SHIFT 0x00000000 +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0_MASK 0x00000007L +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0__SHIFT 0x00000000 +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1_MASK 0x00000038L +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1__SHIFT 0x00000003 +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2_MASK 0x000001c0L +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2__SHIFT 0x00000006 +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3_MASK 0x00000e00L +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3__SHIFT 0x00000009 +#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0_MASK 0x00038000L +#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT 0x0000000f +#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0_MASK 0x00e00000L +#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0__SHIFT 0x00000015 +#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_MASK 0x0000ff00L +#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT 0x00000008 +#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_MASK 0x000000ffL +#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE__SHIFT 0x00000000 +#define SEM_MAILBOX__HOSTPORT_MASK 0x0000ff00L +#define SEM_MAILBOX__HOSTPORT__SHIFT 0x00000008 +#define SEM_MAILBOX__SIDEPORT_MASK 0x000000ffL +#define SEM_MAILBOX__SIDEPORT__SHIFT 0x00000000 +#define SEM_MCIF_CONFIG__MC_REQ_SWAP_MASK 0x00000003L +#define SEM_MCIF_CONFIG__MC_REQ_SWAP__SHIFT 0x00000000 +#define SPU_PORT_STATUS__RESERVED_MASK 0xffffffffL +#define SPU_PORT_STATUS__RESERVED__SHIFT 0x00000000 +#define SRBM_CAM_DATA__CAM_ADDR_MASK 0x0000ffffL +#define SRBM_CAM_DATA__CAM_ADDR__SHIFT 0x00000000 +#define SRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000L +#define SRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x00000010 +#define SRBM_CAM_INDEX__CAM_INDEX_MASK 0x00000007L +#define SRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x00000000 +#define SRBM_CHIP_REVISION__CHIP_REVISION_MASK 0x000000ffL +#define SRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x00000000 +#define SRBM_CNTL__COMBINE_SYSTEM_MC_MASK 0x00020000L +#define SRBM_CNTL__COMBINE_SYSTEM_MC__SHIFT 0x00000011 +#define SRBM_CNTL__PWR_REQUEST_HALT_MASK 0x00010000L +#define SRBM_CNTL__PWR_REQUEST_HALT__SHIFT 0x00000010 +#define SRBM_CNTL__READ_TIMEOUT_MASK 0x000003ffL +#define SRBM_CNTL__READ_TIMEOUT__SHIFT 0x00000000 +#define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX_MASK 0x0000003fL +#define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX__SHIFT 0x00000000 +#define SRBM_DEBUG_DATA__DATA_MASK 0xffffffffL +#define SRBM_DEBUG_DATA__DATA__SHIFT 0x00000000 +#define SRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x00000002L +#define SRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x00000001 +#define SRBM_DEBUG__IGNORE_RDY_MASK 0x00000001L +#define SRBM_DEBUG__IGNORE_RDY__SHIFT 0x00000000 +#define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE_MASK 0x00000100L +#define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x00000008 +#define SRBM_DEBUG_SNAPSHOT__BIF_RDY_MASK 0x00000080L +#define SRBM_DEBUG_SNAPSHOT__BIF_RDY__SHIFT 0x00000007 +#define SRBM_DEBUG_SNAPSHOT__DC_RDY_MASK 0x00000040L +#define SRBM_DEBUG_SNAPSHOT__DC_RDY__SHIFT 0x00000006 +#define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x00000004L +#define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x00000002 +#define SRBM_DEBUG_SNAPSHOT__GRBM_RDY_MASK 0x00000020L +#define SRBM_DEBUG_SNAPSHOT__GRBM_RDY__SHIFT 0x00000005 +#define SRBM_DEBUG_SNAPSHOT__MCB_RDY_MASK 0x00000001L +#define SRBM_DEBUG_SNAPSHOT__MCB_RDY__SHIFT 0x00000000 +#define SRBM_DEBUG_SNAPSHOT__MCC0_RDY_MASK 0x10000000L +#define SRBM_DEBUG_SNAPSHOT__MCC0_RDY__SHIFT 0x0000001c +#define SRBM_DEBUG_SNAPSHOT__MCC1_RDY_MASK 0x08000000L +#define SRBM_DEBUG_SNAPSHOT__MCC1_RDY__SHIFT 0x0000001b +#define SRBM_DEBUG_SNAPSHOT__MCC2_RDY_MASK 0x04000000L +#define SRBM_DEBUG_SNAPSHOT__MCC2_RDY__SHIFT 0x0000001a +#define SRBM_DEBUG_SNAPSHOT__MCC3_RDY_MASK 0x02000000L +#define SRBM_DEBUG_SNAPSHOT__MCC3_RDY__SHIFT 0x00000019 +#define SRBM_DEBUG_SNAPSHOT__MCC4_RDY_MASK 0x01000000L +#define SRBM_DEBUG_SNAPSHOT__MCC4_RDY__SHIFT 0x00000018 +#define SRBM_DEBUG_SNAPSHOT__MCC5_RDY_MASK 0x00800000L +#define SRBM_DEBUG_SNAPSHOT__MCC5_RDY__SHIFT 0x00000017 +#define SRBM_DEBUG_SNAPSHOT__MCC6_RDY_MASK 0x00400000L +#define SRBM_DEBUG_SNAPSHOT__MCC6_RDY__SHIFT 0x00000016 +#define SRBM_DEBUG_SNAPSHOT__MCC7_RDY_MASK 0x00200000L +#define SRBM_DEBUG_SNAPSHOT__MCC7_RDY__SHIFT 0x00000015 +#define SRBM_DEBUG_SNAPSHOT__MCD0_RDY_MASK 0x00100000L +#define SRBM_DEBUG_SNAPSHOT__MCD0_RDY__SHIFT 0x00000014 +#define SRBM_DEBUG_SNAPSHOT__MCD1_RDY_MASK 0x00080000L +#define SRBM_DEBUG_SNAPSHOT__MCD1_RDY__SHIFT 0x00000013 +#define SRBM_DEBUG_SNAPSHOT__MCD2_RDY_MASK 0x00040000L +#define SRBM_DEBUG_SNAPSHOT__MCD2_RDY__SHIFT 0x00000012 +#define SRBM_DEBUG_SNAPSHOT__MCD3_RDY_MASK 0x00020000L +#define SRBM_DEBUG_SNAPSHOT__MCD3_RDY__SHIFT 0x00000011 +#define SRBM_DEBUG_SNAPSHOT__MCD4_RDY_MASK 0x00010000L +#define SRBM_DEBUG_SNAPSHOT__MCD4_RDY__SHIFT 0x00000010 +#define SRBM_DEBUG_SNAPSHOT__MCD5_RDY_MASK 0x00008000L +#define SRBM_DEBUG_SNAPSHOT__MCD5_RDY__SHIFT 0x0000000f +#define SRBM_DEBUG_SNAPSHOT__MCD6_RDY_MASK 0x00004000L +#define SRBM_DEBUG_SNAPSHOT__MCD6_RDY__SHIFT 0x0000000e +#define SRBM_DEBUG_SNAPSHOT__MCD7_RDY_MASK 0x00002000L +#define SRBM_DEBUG_SNAPSHOT__MCD7_RDY__SHIFT 0x0000000d +#define SRBM_DEBUG_SNAPSHOT__ORB_RDY_MASK 0x00001000L +#define SRBM_DEBUG_SNAPSHOT__ORB_RDY__SHIFT 0x0000000c +#define SRBM_DEBUG_SNAPSHOT__REGBB_RDY_MASK 0x00000800L +#define SRBM_DEBUG_SNAPSHOT__REGBB_RDY__SHIFT 0x0000000b +#define SRBM_DEBUG_SNAPSHOT__UVD_RDY_MASK 0x00000200L +#define SRBM_DEBUG_SNAPSHOT__UVD_RDY__SHIFT 0x00000009 +#define SRBM_DEBUG_SNAPSHOT__VCE_RDY_MASK 0x20000000L +#define SRBM_DEBUG_SNAPSHOT__VCE_RDY__SHIFT 0x0000001d +#define SRBM_DEBUG_SNAPSHOT__XDMA_RDY_MASK 0x00000100L +#define SRBM_DEBUG_SNAPSHOT__XDMA_RDY__SHIFT 0x00000008 +#define SRBM_DEBUG_SNAPSHOT__XSP_RDY_MASK 0x00000400L +#define SRBM_DEBUG_SNAPSHOT__XSP_RDY__SHIFT 0x0000000a +#define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE_MASK 0x00000010L +#define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x00000004 +#define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE_MASK 0x00000040L +#define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x00000006 +#define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE_MASK 0x00000020L +#define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x00000005 +#define SRBM_GFX_CNTL__VMID_MASK 0x000000f0L +#define SRBM_GFX_CNTL__VMID__SHIFT 0x00000004 +#define SRBM_INT_ACK__RDERR_INT_ACK_MASK 0x00000001L +#define SRBM_INT_ACK__RDERR_INT_ACK__SHIFT 0x00000000 +#define SRBM_INT_CNTL__RDERR_INT_MASK_MASK 0x00000001L +#define SRBM_INT_CNTL__RDERR_INT_MASK__SHIFT 0x00000000 +#define SRBM_INT_STATUS__RDERR_INT_STAT_MASK 0x00000001L +#define SRBM_INT_STATUS__RDERR_INT_STAT__SHIFT 0x00000000 +#define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001f00L +#define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x00000008 +#define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000fL +#define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x00000000 +#define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI_MASK 0xffffffffL +#define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI__SHIFT 0x00000000 +#define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO_MASK 0xffffffffL +#define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO__SHIFT 0x00000000 +#define SRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x0000003fL +#define SRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 +#define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI_MASK 0xffffffffL +#define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI__SHIFT 0x00000000 +#define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO_MASK 0xffffffffL +#define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO__SHIFT 0x00000000 +#define SRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x0000003fL +#define SRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 +#define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L +#define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x00000008 +#define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L +#define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0x0000000a +#define SRBM_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000fL +#define SRBM_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x00000000 +#define SRBM_READ_ERROR__READ_ADDRESS_MASK 0x0003fffcL +#define SRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x00000002 +#define SRBM_READ_ERROR__READ_ERROR_MASK 0x80000000L +#define SRBM_READ_ERROR__READ_ERROR__SHIFT 0x0000001f +#define SRBM_READ_ERROR__READ_REQUESTER_GRBM_MASK 0x02000000L +#define SRBM_READ_ERROR__READ_REQUESTER_GRBM__SHIFT 0x00000019 +#define SRBM_READ_ERROR__READ_REQUESTER_HI_MASK 0x01000000L +#define SRBM_READ_ERROR__READ_REQUESTER_HI__SHIFT 0x00000018 +#define SRBM_READ_ERROR__READ_REQUESTER_SMU_MASK 0x04000000L +#define SRBM_READ_ERROR__READ_REQUESTER_SMU__SHIFT 0x0000001a +#define SRBM_READ_ERROR__READ_REQUESTER_TST_MASK 0x00400000L +#define SRBM_READ_ERROR__READ_REQUESTER_TST__SHIFT 0x00000016 +#define SRBM_READ_ERROR__READ_REQUESTER_UVD_MASK 0x20000000L +#define SRBM_READ_ERROR__READ_REQUESTER_UVD__SHIFT 0x0000001d +#define SRBM_READ_ERROR__READ_REQUESTER_VCE_MASK 0x00100000L +#define SRBM_READ_ERROR__READ_REQUESTER_VCE__SHIFT 0x00000014 +#define SRBM_SOFT_RESET__SOFT_RESET_BIF_MASK 0x00000002L +#define SRBM_SOFT_RESET__SOFT_RESET_BIF__SHIFT 0x00000001 +#define SRBM_SOFT_RESET__SOFT_RESET_DC_MASK 0x00000020L +#define SRBM_SOFT_RESET__SOFT_RESET_DC__SHIFT 0x00000005 +#define SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK 0x00000100L +#define SRBM_SOFT_RESET__SOFT_RESET_GRBM__SHIFT 0x00000008 +#define SRBM_SOFT_RESET__SOFT_RESET_HDP_MASK 0x00000200L +#define SRBM_SOFT_RESET__SOFT_RESET_HDP__SHIFT 0x00000009 +#define SRBM_SOFT_RESET__SOFT_RESET_IH_MASK 0x00000400L +#define SRBM_SOFT_RESET__SOFT_RESET_IH__SHIFT 0x0000000a +#define SRBM_SOFT_RESET__SOFT_RESET_MC_MASK 0x00000800L +#define SRBM_SOFT_RESET__SOFT_RESET_MC__SHIFT 0x0000000b +#define SRBM_SOFT_RESET__SOFT_RESET_ORB_MASK 0x00800000L +#define SRBM_SOFT_RESET__SOFT_RESET_ORB__SHIFT 0x00000017 +#define SRBM_SOFT_RESET__SOFT_RESET_REGBB_MASK 0x00400000L +#define SRBM_SOFT_RESET__SOFT_RESET_REGBB__SHIFT 0x00000016 +#define SRBM_SOFT_RESET__SOFT_RESET_ROM_MASK 0x00004000L +#define SRBM_SOFT_RESET__SOFT_RESET_ROM__SHIFT 0x0000000e +#define SRBM_SOFT_RESET__SOFT_RESET_SEM_MASK 0x00008000L +#define SRBM_SOFT_RESET__SOFT_RESET_SEM__SHIFT 0x0000000f +#define SRBM_SOFT_RESET__SOFT_RESET_TST_MASK 0x00200000L +#define SRBM_SOFT_RESET__SOFT_RESET_TST__SHIFT 0x00000015 +#define SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK 0x00040000L +#define SRBM_SOFT_RESET__SOFT_RESET_UVD__SHIFT 0x00000012 +#define SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK 0x01000000L +#define SRBM_SOFT_RESET__SOFT_RESET_VCE__SHIFT 0x00000018 +#define SRBM_SOFT_RESET__SOFT_RESET_VMC_MASK 0x00020000L +#define SRBM_SOFT_RESET__SOFT_RESET_VMC__SHIFT 0x00000011 +#define SRBM_SOFT_RESET__SOFT_RESET_XDMA_MASK 0x02000000L +#define SRBM_SOFT_RESET__SOFT_RESET_XDMA__SHIFT 0x00000019 +#define SRBM_SOFT_RESET__SOFT_RESET_XSP_MASK 0x00080000L +#define SRBM_SOFT_RESET__SOFT_RESET_XSP__SHIFT 0x00000013 +#define SRBM_STATUS2__TST_RQ_PENDING_MASK 0x00000002L +#define SRBM_STATUS2__TST_RQ_PENDING__SHIFT 0x00000001 +#define SRBM_STATUS2__VCE_BUSY_MASK 0x00000080L +#define SRBM_STATUS2__VCE_BUSY__SHIFT 0x00000007 +#define SRBM_STATUS2__VCE_RQ_PENDING_MASK 0x00000008L +#define SRBM_STATUS2__VCE_RQ_PENDING__SHIFT 0x00000003 +#define SRBM_STATUS2__XDMA_BUSY_MASK 0x00000100L +#define SRBM_STATUS2__XDMA_BUSY__SHIFT 0x00000008 +#define SRBM_STATUS2__XSP_BUSY_MASK 0x00000010L +#define SRBM_STATUS2__XSP_BUSY__SHIFT 0x00000004 +#define SRBM_STATUS__BIF_BUSY_MASK 0x20000000L +#define SRBM_STATUS__BIF_BUSY__SHIFT 0x0000001d +#define SRBM_STATUS__GRBM_RQ_PENDING_MASK 0x00000020L +#define SRBM_STATUS__GRBM_RQ_PENDING__SHIFT 0x00000005 +#define SRBM_STATUS__HI_RQ_PENDING_MASK 0x00000040L +#define SRBM_STATUS__HI_RQ_PENDING__SHIFT 0x00000006 +#define SRBM_STATUS__IH_BUSY_MASK 0x00020000L +#define SRBM_STATUS__IH_BUSY__SHIFT 0x00000011 +#define SRBM_STATUS__IO_EXTERN_SIGNAL_MASK 0x00000080L +#define SRBM_STATUS__IO_EXTERN_SIGNAL__SHIFT 0x00000007 +#define SRBM_STATUS__MCB_BUSY_MASK 0x00000200L +#define SRBM_STATUS__MCB_BUSY__SHIFT 0x00000009 +#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK 0x00000400L +#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY__SHIFT 0x0000000a +#define SRBM_STATUS__MCC_BUSY_MASK 0x00000800L +#define SRBM_STATUS__MCC_BUSY__SHIFT 0x0000000b +#define SRBM_STATUS__MCD_BUSY_MASK 0x00001000L +#define SRBM_STATUS__MCD_BUSY__SHIFT 0x0000000c +#define SRBM_STATUS__SEM_BUSY_MASK 0x00004000L +#define SRBM_STATUS__SEM_BUSY__SHIFT 0x0000000e +#define SRBM_STATUS__SMU_RQ_PENDING_MASK 0x00000010L +#define SRBM_STATUS__SMU_RQ_PENDING__SHIFT 0x00000004 +#define SRBM_STATUS__UVD_BUSY_MASK 0x00080000L +#define SRBM_STATUS__UVD_BUSY__SHIFT 0x00000013 +#define SRBM_STATUS__UVD_RQ_PENDING_MASK 0x00000002L +#define SRBM_STATUS__UVD_RQ_PENDING__SHIFT 0x00000001 +#define SRBM_STATUS__VMC_BUSY_MASK 0x00000100L +#define SRBM_STATUS__VMC_BUSY__SHIFT 0x00000008 +#define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001f00L +#define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x00000008 +#define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000fL +#define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x00000000 +#define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001f00L +#define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x00000008 +#define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000fL +#define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x00000000 +#define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001f00L +#define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x00000008 +#define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000fL +#define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x00000000 +#define UVD_CONFIG__UVD_RDREQ_URG_MASK 0x00000f00L +#define UVD_CONFIG__UVD_RDREQ_URG__SHIFT 0x00000008 +#define UVD_CONFIG__UVD_REQ_TRAN_MASK 0x00010000L +#define UVD_CONFIG__UVD_REQ_TRAN__SHIFT 0x00000010 +#define VCE_CONFIG__VCE_RDREQ_URG_MASK 0x00000f00L +#define VCE_CONFIG__VCE_RDREQ_URG__SHIFT 0x00000008 +#define VCE_CONFIG__VCE_REQ_TRAN_MASK 0x00010000L +#define VCE_CONFIG__VCE_REQ_TRAN__SHIFT 0x00000010 +#define XDMA_MSTR_CNTL__XDMA_MSTR_LAT_TEST_EN_MASK 0x00080000L +#define XDMA_MSTR_CNTL__XDMA_MSTR_LAT_TEST_EN__SHIFT 0x00000013 +#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_COUNT_ENABLE_MASK 0x80000000L +#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_COUNT_ENABLE__SHIFT 0x0000001f +#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_COUNT_MASK 0x0000ffffL +#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_COUNT__SHIFT 0x00000000 +#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_THRESHOLD_MASK 0x3fff0000L +#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_THRESHOLD__SHIFT 0x00000010 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_6_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_6_0_d.h new file mode 100644 index 000000000000..6b10be61efc3 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_6_0_d.h @@ -0,0 +1,148 @@ +/* + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef SMU_6_0_D_H +#define SMU_6_0_D_H + +#define ixLCAC_MC0_CNTL 0x011C +#define ixLCAC_MC0_OVR_SEL 0x011D +#define ixLCAC_MC0_OVR_VAL 0x011E +#define ixLCAC_MC1_CNTL 0x011F +#define ixLCAC_MC1_OVR_SEL 0x0120 +#define ixLCAC_MC1_OVR_VAL 0x0121 +#define ixLCAC_MC2_CNTL 0x0122 +#define ixLCAC_MC2_OVR_SEL 0x0123 +#define ixLCAC_MC2_OVR_VAL 0x0124 +#define ixLCAC_MC3_CNTL 0x0125 +#define ixLCAC_MC3_OVR_SEL 0x0126 +#define ixLCAC_MC3_OVR_VAL 0x0127 +#define ixLCAC_MC4_CNTL 0x0128 +#define ixLCAC_MC4_OVR_SEL 0x0129 +#define ixLCAC_MC4_OVR_VAL 0x012A +#define ixLCAC_MC5_CNTL 0x012B +#define ixLCAC_MC5_OVR_SEL 0x012C +#define ixLCAC_MC5_OVR_VAL 0x012D +#define ixSMC_PC_C 0x80000370 +#define ixTHM_TMON0_DEBUG 0x03F0 +#define ixTHM_TMON0_INT_DATA 0x0380 +#define ixTHM_TMON0_RDIL0_DATA 0x0300 +#define ixTHM_TMON0_RDIL10_DATA 0x030A +#define ixTHM_TMON0_RDIL11_DATA 0x030B +#define ixTHM_TMON0_RDIL12_DATA 0x030C +#define ixTHM_TMON0_RDIL13_DATA 0x030D +#define ixTHM_TMON0_RDIL14_DATA 0x030E +#define ixTHM_TMON0_RDIL15_DATA 0x030F +#define ixTHM_TMON0_RDIL1_DATA 0x0301 +#define ixTHM_TMON0_RDIL2_DATA 0x0302 +#define ixTHM_TMON0_RDIL3_DATA 0x0303 +#define ixTHM_TMON0_RDIL4_DATA 0x0304 +#define ixTHM_TMON0_RDIL5_DATA 0x0305 +#define ixTHM_TMON0_RDIL6_DATA 0x0306 +#define ixTHM_TMON0_RDIL7_DATA 0x0307 +#define ixTHM_TMON0_RDIL8_DATA 0x0308 +#define ixTHM_TMON0_RDIL9_DATA 0x0309 +#define ixTHM_TMON0_RDIR0_DATA 0x0310 +#define ixTHM_TMON0_RDIR10_DATA 0x031A +#define ixTHM_TMON0_RDIR11_DATA 0x031B +#define ixTHM_TMON0_RDIR12_DATA 0x031C +#define ixTHM_TMON0_RDIR13_DATA 0x031D +#define ixTHM_TMON0_RDIR14_DATA 0x031E +#define ixTHM_TMON0_RDIR15_DATA 0x031F +#define ixTHM_TMON0_RDIR1_DATA 0x0311 +#define ixTHM_TMON0_RDIR2_DATA 0x0312 +#define ixTHM_TMON0_RDIR3_DATA 0x0313 +#define ixTHM_TMON0_RDIR4_DATA 0x0314 +#define ixTHM_TMON0_RDIR5_DATA 0x0315 +#define ixTHM_TMON0_RDIR6_DATA 0x0316 +#define ixTHM_TMON0_RDIR7_DATA 0x0317 +#define ixTHM_TMON0_RDIR8_DATA 0x0318 +#define ixTHM_TMON0_RDIR9_DATA 0x0319 +#define ixTHM_TMON1_DEBUG 0x03F1 +#define ixTHM_TMON1_INT_DATA 0x0381 +#define ixTHM_TMON1_RDIL0_DATA 0x0320 +#define ixTHM_TMON1_RDIL10_DATA 0x032A +#define ixTHM_TMON1_RDIL11_DATA 0x032B +#define ixTHM_TMON1_RDIL12_DATA 0x032C +#define ixTHM_TMON1_RDIL13_DATA 0x032D +#define ixTHM_TMON1_RDIL14_DATA 0x032E +#define ixTHM_TMON1_RDIL15_DATA 0x032F +#define ixTHM_TMON1_RDIL1_DATA 0x0321 +#define ixTHM_TMON1_RDIL2_DATA 0x0322 +#define ixTHM_TMON1_RDIL3_DATA 0x0323 +#define ixTHM_TMON1_RDIL4_DATA 0x0324 +#define ixTHM_TMON1_RDIL5_DATA 0x0325 +#define ixTHM_TMON1_RDIL6_DATA 0x0326 +#define ixTHM_TMON1_RDIL7_DATA 0x0327 +#define ixTHM_TMON1_RDIL8_DATA 0x0328 +#define ixTHM_TMON1_RDIL9_DATA 0x0329 +#define ixTHM_TMON1_RDIR0_DATA 0x0330 +#define ixTHM_TMON1_RDIR10_DATA 0x033A +#define ixTHM_TMON1_RDIR11_DATA 0x033B +#define ixTHM_TMON1_RDIR12_DATA 0x033C +#define ixTHM_TMON1_RDIR13_DATA 0x033D +#define ixTHM_TMON1_RDIR14_DATA 0x033E +#define ixTHM_TMON1_RDIR15_DATA 0x033F +#define ixTHM_TMON1_RDIR1_DATA 0x0331 +#define ixTHM_TMON1_RDIR2_DATA 0x0332 +#define ixTHM_TMON1_RDIR3_DATA 0x0333 +#define ixTHM_TMON1_RDIR4_DATA 0x0334 +#define ixTHM_TMON1_RDIR5_DATA 0x0335 +#define ixTHM_TMON1_RDIR6_DATA 0x0336 +#define ixTHM_TMON1_RDIR7_DATA 0x0337 +#define ixTHM_TMON1_RDIR8_DATA 0x0338 +#define ixTHM_TMON1_RDIR9_DATA 0x0339 +#define mmGPIOPAD_A 0x05E7 +#define mmGPIOPAD_EN 0x05E8 +#define mmGPIOPAD_EXTERN_TRIG_CNTL 0x05F1 +#define mmGPIOPAD_INT_EN 0x05EE +#define mmGPIOPAD_INT_POLARITY 0x05F0 +#define mmGPIOPAD_INT_STAT 0x05EC +#define mmGPIOPAD_INT_STAT_AK 0x05ED +#define mmGPIOPAD_INT_STAT_EN 0x05EB +#define mmGPIOPAD_INT_TYPE 0x05EF +#define mmGPIOPAD_MASK 0x05E6 +#define mmGPIOPAD_PD_EN 0x05F4 +#define mmGPIOPAD_PINSTRAPS 0x05EA +#define mmGPIOPAD_PU_EN 0x05F3 +#define mmGPIOPAD_RCVR_SEL 0x05F2 +#define mmGPIOPAD_STRENGTH 0x05E5 +#define mmGPIOPAD_SW_INT_STAT 0x05E4 +#define mmGPIOPAD_Y 0x05E9 +#define mmSMC_IND_ACCESS_CNTL 0x008A +#define mmSMC_IND_DATA_0 0x0081 +#define mmSMC_IND_DATA 0x0081 +#define mmSMC_IND_DATA_1 0x0083 +#define mmSMC_IND_DATA_2 0x0085 +#define mmSMC_IND_DATA_3 0x0087 +#define mmSMC_IND_INDEX_0 0x0080 +#define mmSMC_IND_INDEX 0x0080 +#define mmSMC_IND_INDEX_1 0x0082 +#define mmSMC_IND_INDEX_2 0x0084 +#define mmSMC_IND_INDEX_3 0x0086 +#define mmSMC_MESSAGE_0 0x008B +#define mmSMC_MESSAGE_1 0x008D +#define mmSMC_MESSAGE_2 0x008F +#define mmSMC_RESP_0 0x008C +#define mmSMC_RESP_1 0x008E +#define mmSMC_RESP_2 0x0090 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_6_0_sh_mask.h new file mode 100644 index 000000000000..7d3925b7266e --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_6_0_sh_mask.h @@ -0,0 +1,715 @@ +/* + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef SMU_6_0_SH_MASK_H +#define SMU_6_0_SH_MASK_H + +#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK 0x03ffffffL +#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x00000000 +#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK 0x000003f0L +#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x00000004 +#define GPIOPAD_A__GPIO_A_MASK 0x7fffffffL +#define GPIOPAD_A__GPIO_A__SHIFT 0x00000000 +#define GPIOPAD_EN__GPIO_EN_MASK 0x7fffffffL +#define GPIOPAD_EN__GPIO_EN__SHIFT 0x00000000 +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR_MASK 0x00000020L +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR__SHIFT 0x00000005 +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ_MASK 0x00000040L +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ__SHIFT 0x00000006 +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL_MASK 0x0000001fL +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL__SHIFT 0x00000000 +#define GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1fffffffL +#define GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x00000000 +#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000L +#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x0000001f +#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1fffffffL +#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x00000000 +#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000L +#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x0000001f +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x00000001L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x00000000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x00000400L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0x0000000a +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x00000800L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0x0000000b +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x00001000L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0x0000000c +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x00002000L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0x0000000d +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x00004000L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0x0000000e +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x00008000L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0x0000000f +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x00010000L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x00000010 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x00020000L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x00000011 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x00040000L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x00000012 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x00080000L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x00000013 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x00000002L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x00000001 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x00100000L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x00000014 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x00200000L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x00000015 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x00400000L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x00000016 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x00800000L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x00000017 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x01000000L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x00000018 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x02000000L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x00000019 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x04000000L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x0000001a +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x08000000L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x0000001b +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x0000001c +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x00000004L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x00000002 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x00000008L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x00000003 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x00000010L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x00000004 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x00000020L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x00000005 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x00000040L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x00000006 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x00000080L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x00000007 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x00000100L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x00000008 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x00000200L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x00000009 +#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000L +#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x0000001f +#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1fffffffL +#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x00000000 +#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000L +#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x0000001f +#define GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1fffffffL +#define GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x00000000 +#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000L +#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x0000001f +#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1fffffffL +#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x00000000 +#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000L +#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x0000001f +#define GPIOPAD_MASK__GPIO_MASK_MASK 0x7fffffffL +#define GPIOPAD_MASK__GPIO_MASK__SHIFT 0x00000000 +#define GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7fffffffL +#define GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x00000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x00000001L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x00000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x00000400L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0x0000000a +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x00000800L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0x0000000b +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x00001000L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0x0000000c +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x00002000L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0x0000000d +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x00004000L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0x0000000e +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x00008000L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0x0000000f +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x00010000L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x00000010 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x00020000L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x00000011 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x00040000L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x00000012 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x00080000L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x00000013 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x00000002L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x00000001 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x00100000L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x00000014 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x00200000L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x00000015 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x00400000L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x00000016 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x00800000L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x00000017 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x01000000L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x00000018 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x02000000L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x00000019 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x04000000L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x0000001a +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x08000000L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x0000001b +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x0000001c +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x0000001d +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x00000004L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x00000002 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x0000001e +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x00000008L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x00000003 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x00000010L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x00000004 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x00000020L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x00000005 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x00000040L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x00000006 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x00000080L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x00000007 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x00000100L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x00000008 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x00000200L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x00000009 +#define GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7fffffffL +#define GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x00000000 +#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL_MASK 0x7fffffffL +#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL__SHIFT 0x00000000 +#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN_MASK 0x0000000fL +#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN__SHIFT 0x00000000 +#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP_MASK 0x000000f0L +#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP__SHIFT 0x00000004 +#define GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x00000001L +#define GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x00000000 +#define GPIOPAD_Y__GPIO_Y_MASK 0x7fffffffL +#define GPIOPAD_Y__GPIO_Y__SHIFT 0x00000000 +#define LCAC_MC0_CNTL__MC0_ENABLE_MASK 0x00000001L +#define LCAC_MC0_CNTL__MC0_ENABLE__SHIFT 0x00000000 +#define LCAC_MC0_CNTL__MC0_THRESHOLD_MASK 0x0001fffeL +#define LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT 0x00000001 +#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL_MASK 0xffffffffL +#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL__SHIFT 0x00000000 +#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL_MASK 0xffffffffL +#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL__SHIFT 0x00000000 +#define LCAC_MC1_CNTL__MC1_ENABLE_MASK 0x00000001L +#define LCAC_MC1_CNTL__MC1_ENABLE__SHIFT 0x00000000 +#define LCAC_MC1_CNTL__MC1_THRESHOLD_MASK 0x0001fffeL +#define LCAC_MC1_CNTL__MC1_THRESHOLD__SHIFT 0x00000001 +#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL_MASK 0xffffffffL +#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL__SHIFT 0x00000000 +#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL_MASK 0xffffffffL +#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL__SHIFT 0x00000000 +#define LCAC_MC2_CNTL__MC2_ENABLE_MASK 0x00000001L +#define LCAC_MC2_CNTL__MC2_ENABLE__SHIFT 0x00000000 +#define LCAC_MC2_CNTL__MC2_THRESHOLD_MASK 0x0001fffeL +#define LCAC_MC2_CNTL__MC2_THRESHOLD__SHIFT 0x00000001 +#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL_MASK 0xffffffffL +#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL__SHIFT 0x00000000 +#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL_MASK 0xffffffffL +#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL__SHIFT 0x00000000 +#define LCAC_MC3_CNTL__MC3_ENABLE_MASK 0x00000001L +#define LCAC_MC3_CNTL__MC3_ENABLE__SHIFT 0x00000000 +#define LCAC_MC3_CNTL__MC3_THRESHOLD_MASK 0x0001fffeL +#define LCAC_MC3_CNTL__MC3_THRESHOLD__SHIFT 0x00000001 +#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL_MASK 0xffffffffL +#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL__SHIFT 0x00000000 +#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL_MASK 0xffffffffL +#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL__SHIFT 0x00000000 +#define LCAC_MC4_CNTL__MC4_ENABLE_MASK 0x00000001L +#define LCAC_MC4_CNTL__MC4_ENABLE__SHIFT 0x00000000 +#define LCAC_MC4_CNTL__MC4_THRESHOLD_MASK 0x0001fffeL +#define LCAC_MC4_CNTL__MC4_THRESHOLD__SHIFT 0x00000001 +#define LCAC_MC4_OVR_SEL__MC4_OVR_SEL_MASK 0xffffffffL +#define LCAC_MC4_OVR_SEL__MC4_OVR_SEL__SHIFT 0x00000000 +#define LCAC_MC4_OVR_VAL__MC4_OVR_VAL_MASK 0xffffffffL +#define LCAC_MC4_OVR_VAL__MC4_OVR_VAL__SHIFT 0x00000000 +#define LCAC_MC5_CNTL__MC5_ENABLE_MASK 0x00000001L +#define LCAC_MC5_CNTL__MC5_ENABLE__SHIFT 0x00000000 +#define LCAC_MC5_CNTL__MC5_THRESHOLD_MASK 0x0001fffeL +#define LCAC_MC5_CNTL__MC5_THRESHOLD__SHIFT 0x00000001 +#define LCAC_MC5_OVR_SEL__MC5_OVR_SEL_MASK 0xffffffffL +#define LCAC_MC5_OVR_SEL__MC5_OVR_SEL__SHIFT 0x00000000 +#define LCAC_MC5_OVR_VAL__MC5_OVR_VAL_MASK 0xffffffffL +#define LCAC_MC5_OVR_VAL__MC5_OVR_VAL__SHIFT 0x00000000 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK 0x00000001L +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0__SHIFT 0x00000000 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1_MASK 0x00000100L +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1__SHIFT 0x00000008 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2_MASK 0x00010000L +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2__SHIFT 0x00000010 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3_MASK 0x01000000L +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x00000018 +#define SMC_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffffL +#define SMC_IND_DATA_0__SMC_IND_DATA__SHIFT 0x00000000 +#define SMC_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffffL +#define SMC_IND_DATA_1__SMC_IND_DATA__SHIFT 0x00000000 +#define SMC_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffffL +#define SMC_IND_DATA_2__SMC_IND_DATA__SHIFT 0x00000000 +#define SMC_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffffL +#define SMC_IND_DATA_3__SMC_IND_DATA__SHIFT 0x00000000 +#define SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffffL +#define SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x00000000 +#define SMC_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffffL +#define SMC_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x00000000 +#define SMC_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffffL +#define SMC_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x00000000 +#define SMC_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffffL +#define SMC_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x00000000 +#define SMC_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffffL +#define SMC_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x00000000 +#define SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffffL +#define SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x00000000 +#define SMC_MESSAGE_0__SMC_MSG_MASK 0xffffffffL +#define SMC_MESSAGE_0__SMC_MSG__SHIFT 0x00000000 +#define SMC_MESSAGE_1__SMC_MSG_MASK 0xffffffffL +#define SMC_MESSAGE_1__SMC_MSG__SHIFT 0x00000000 +#define SMC_MESSAGE_2__SMC_MSG_MASK 0xffffffffL +#define SMC_MESSAGE_2__SMC_MSG__SHIFT 0x00000000 +#define SMC_PC_C__smc_pc_c_MASK 0xffffffffL +#define SMC_PC_C__smc_pc_c__SHIFT 0x00000000 +#define SMC_RESP_0__SMC_RESP_MASK 0xffffffffL +#define SMC_RESP_0__SMC_RESP__SHIFT 0x00000000 +#define SMC_RESP_1__SMC_RESP_MASK 0xffffffffL +#define SMC_RESP_1__SMC_RESP__SHIFT 0x00000000 +#define SMC_RESP_2__SMC_RESP_MASK 0xffffffffL +#define SMC_RESP_2__SMC_RESP__SHIFT 0x00000000 +#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT_MASK 0x000ff000L +#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT__SHIFT 0x0000000c +#define SPLL_CNTL_MODE__SPLL_ENSAT_MASK 0x00000010L +#define SPLL_CNTL_MODE__SPLL_ENSAT__SHIFT 0x00000004 +#define SPLL_CNTL_MODE__SPLL_FASTEN_MASK 0x00000008L +#define SPLL_CNTL_MODE__SPLL_FASTEN__SHIFT 0x00000003 +#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x00000002L +#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV__SHIFT 0x00000001 +#define SPLL_CNTL_MODE__SPLL_RESET_EN_MASK 0x10000000L +#define SPLL_CNTL_MODE__SPLL_RESET_EN__SHIFT 0x0000001c +#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x00000001L +#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x00000000 +#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV_MASK 0x00000c00L +#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV__SHIFT 0x0000000a +#define SPLL_CNTL_MODE__SPLL_TEST_MASK 0x00000004L +#define SPLL_CNTL_MODE__SPLL_TEST__SHIFT 0x00000002 +#define SPLL_CNTL_MODE__SPLL_VCO_MODE_MASK 0x60000000L +#define SPLL_CNTL_MODE__SPLL_VCO_MODE__SHIFT 0x0000001d +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK 0x0f000000L +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT 0x00000018 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX_MASK 0xf0000000L +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX__SHIFT 0x0000001c +#define THM_TMON0_DEBUG__DEBUG_RDI_MASK 0x0000001fL +#define THM_TMON0_DEBUG__DEBUG_RDI__SHIFT 0x00000000 +#define THM_TMON0_DEBUG__DEBUG_Z_MASK 0x0000ffe0L +#define THM_TMON0_DEBUG__DEBUG_Z__SHIFT 0x00000005 +#define THM_TMON0_INT_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_INT_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_INT_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_INT_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_INT_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_INT_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIL0_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIL0_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIL0_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL0_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIL0_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIL0_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIL10_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIL10_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIL10_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL10_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIL10_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIL10_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIL11_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIL11_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIL11_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL11_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIL11_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIL11_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIL12_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIL12_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIL12_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL12_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIL12_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIL12_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIL13_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIL13_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIL13_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL13_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIL13_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIL13_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIL14_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIL14_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIL14_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL14_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIL14_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIL14_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIL15_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIL15_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIL15_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL15_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIL15_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIL15_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIL1_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIL1_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIL1_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL1_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIL1_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIL1_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIL2_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIL2_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIL2_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL2_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIL2_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIL2_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIL3_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIL3_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIL3_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL3_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIL3_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIL3_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIL4_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIL4_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIL4_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL4_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIL4_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIL4_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIL5_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIL5_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIL5_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL5_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIL5_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIL5_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIL6_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIL6_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIL6_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL6_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIL6_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIL6_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIL7_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIL7_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIL7_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL7_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIL7_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIL7_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIL8_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIL8_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIL8_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL8_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIL8_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIL8_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIL9_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIL9_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIL9_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL9_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIL9_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIL9_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIR0_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIR0_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIR0_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR0_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIR0_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIR0_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIR10_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIR10_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIR10_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR10_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIR10_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIR10_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIR11_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIR11_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIR11_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR11_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIR11_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIR11_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIR12_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIR12_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIR12_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR12_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIR12_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIR12_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIR13_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIR13_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIR13_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR13_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIR13_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIR13_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIR14_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIR14_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIR14_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR14_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIR14_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIR14_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIR15_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIR15_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIR15_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR15_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIR15_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIR15_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIR1_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIR1_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIR1_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR1_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIR1_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIR1_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIR2_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIR2_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIR2_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR2_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIR2_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIR2_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIR3_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIR3_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIR3_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR3_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIR3_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIR3_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIR4_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIR4_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIR4_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR4_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIR4_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIR4_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIR5_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIR5_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIR5_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR5_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIR5_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIR5_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIR6_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIR6_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIR6_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR6_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIR6_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIR6_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIR7_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIR7_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIR7_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR7_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIR7_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIR7_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIR8_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIR8_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIR8_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR8_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIR8_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIR8_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIR9_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIR9_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIR9_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR9_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIR9_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIR9_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_DEBUG__DEBUG_RDI_MASK 0x0000001fL +#define THM_TMON1_DEBUG__DEBUG_RDI__SHIFT 0x00000000 +#define THM_TMON1_DEBUG__DEBUG_Z_MASK 0x0000ffe0L +#define THM_TMON1_DEBUG__DEBUG_Z__SHIFT 0x00000005 +#define THM_TMON1_INT_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_INT_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_INT_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_INT_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_INT_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_INT_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIL0_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIL0_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIL0_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL0_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIL0_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIL0_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIL10_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIL10_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIL10_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL10_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIL10_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIL10_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIL11_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIL11_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIL11_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL11_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIL11_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIL11_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIL12_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIL12_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIL12_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL12_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIL12_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIL12_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIL13_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIL13_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIL13_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL13_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIL13_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIL13_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIL14_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIL14_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIL14_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL14_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIL14_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIL14_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIL15_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIL15_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIL15_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL15_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIL15_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIL15_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIL1_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIL1_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIL1_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL1_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIL1_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIL1_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIL2_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIL2_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIL2_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL2_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIL2_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIL2_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIL3_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIL3_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIL3_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL3_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIL3_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIL3_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIL4_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIL4_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIL4_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL4_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIL4_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIL4_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIL5_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIL5_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIL5_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL5_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIL5_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIL5_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIL6_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIL6_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIL6_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL6_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIL6_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIL6_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIL7_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIL7_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIL7_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL7_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIL7_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIL7_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIL8_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIL8_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIL8_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL8_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIL8_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIL8_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIL9_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIL9_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIL9_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL9_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIL9_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIL9_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIR0_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIR0_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIR0_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR0_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIR0_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIR0_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIR10_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIR10_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIR10_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR10_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIR10_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIR10_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIR11_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIR11_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIR11_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR11_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIR11_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIR11_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIR12_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIR12_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIR12_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR12_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIR12_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIR12_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIR13_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIR13_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIR13_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR13_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIR13_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIR13_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIR14_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIR14_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIR14_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR14_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIR14_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIR14_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIR15_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIR15_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIR15_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR15_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIR15_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIR15_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIR1_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIR1_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIR1_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR1_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIR1_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIR1_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIR2_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIR2_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIR2_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR2_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIR2_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIR2_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIR3_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIR3_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIR3_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR3_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIR3_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIR3_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIR4_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIR4_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIR4_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR4_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIR4_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIR4_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIR5_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIR5_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIR5_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR5_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIR5_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIR5_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIR6_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIR6_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIR6_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR6_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIR6_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIR6_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIR7_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIR7_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIR7_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR7_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIR7_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIR7_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIR8_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIR8_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIR8_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR8_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIR8_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIR8_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIR9_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIR9_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIR9_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR9_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIR9_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIR9_DATA__Z__SHIFT 0x00000000 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h new file mode 100644 index 000000000000..5c0e3f3332e5 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h @@ -0,0 +1,96 @@ +/* + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef UVD_4_0_D_H +#define UVD_4_0_D_H + +#define ixUVD_CGC_CTRL2 0x00C1 +#define ixUVD_CGC_MEM_CTRL 0x00C0 +#define ixUVD_LMI_ADDR_EXT2 0x00AB +#define ixUVD_LMI_CACHE_CTRL 0x009B +#define ixUVD_LMI_SWAP_CNTL2 0x00AA +#define ixUVD_MIF_CURR_ADDR_CONFIG 0x0048 +#define ixUVD_MIF_RECON1_ADDR_CONFIG 0x0114 +#define ixUVD_MIF_REF_ADDR_CONFIG 0x004C +#define mmUVD_CGC_CTRL 0x3D2C +#define mmUVD_CGC_GATE 0x3D2A +#define mmUVD_CGC_STATUS 0x3D2B +#define mmUVD_CGC_UDEC_STATUS 0x3D2D +#define mmUVD_CONTEXT_ID 0x3DBD +#define mmUVD_CTX_DATA 0x3D29 +#define mmUVD_CTX_INDEX 0x3D28 +#define mmUVD_ENGINE_CNTL 0x3BC6 +#define mmUVD_GPCOM_VCPU_CMD 0x3BC3 +#define mmUVD_GPCOM_VCPU_DATA0 0x3BC4 +#define mmUVD_GPCOM_VCPU_DATA1 0x3BC5 +#define mmUVD_GP_SCRATCH4 0x3D38 +#define mmUVD_LMI_ADDR_EXT 0x3D65 +#define mmUVD_LMI_CTRL 0x3D66 +#define mmUVD_LMI_CTRL2 0x3D3D +#define mmUVD_LMI_EXT40_ADDR 0x3D26 +#define mmUVD_LMI_STATUS 0x3D67 +#define mmUVD_LMI_SWAP_CNTL 0x3D6D +#define mmUVD_MASTINT_EN 0x3D40 +#define mmUVD_MPC_CNTL 0x3D77 +#define mmUVD_MPC_SET_ALU 0x3D7E +#define mmUVD_MPC_SET_MUX 0x3D7D +#define mmUVD_MPC_SET_MUXA0 0x3D79 +#define mmUVD_MPC_SET_MUXA1 0x3D7A +#define mmUVD_MPC_SET_MUXB0 0x3D7B +#define mmUVD_MPC_SET_MUXB1 0x3D7C +#define mmUVD_MP_SWAP_CNTL 0x3D6F +#define mmUVD_NO_OP 0x3BFF +#define mmUVD_PGFSM_CONFIG 0x38F8 +#define mmUVD_PGFSM_READ_TILE1 0x38FA +#define mmUVD_PGFSM_READ_TILE2 0x38FB +#define mmUVD_POWER_STATUS 0x38FC +#define mmUVD_RBC_IB_BASE 0x3DA1 +#define mmUVD_RBC_IB_SIZE 0x3DA2 +#define mmUVD_RBC_IB_SIZE_UPDATE 0x3DF1 +#define mmUVD_RBC_RB_BASE 0x3DA3 +#define mmUVD_RBC_RB_CNTL 0x3DA9 +#define mmUVD_RBC_RB_RPTR 0x3DA4 +#define mmUVD_RBC_RB_RPTR_ADDR 0x3DAA +#define mmUVD_RBC_RB_WPTR 0x3DA5 +#define mmUVD_RBC_RB_WPTR_CNTL 0x3DA6 +#define mmUVD_SEMA_ADDR_HIGH 0x3BC1 +#define mmUVD_SEMA_ADDR_LOW 0x3BC0 +#define mmUVD_SEMA_CMD 0x3BC2 +#define mmUVD_SEMA_CNTL 0x3D00 +#define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0x3DB3 +#define mmUVD_SEMA_TIMEOUT_STATUS 0x3DB0 +#define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0x3DB2 +#define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0x3DB1 +#define mmUVD_SOFT_RESET 0x3DA0 +#define mmUVD_STATUS 0x3DAF +#define mmUVD_UDEC_ADDR_CONFIG 0x3BD3 +#define mmUVD_UDEC_DB_ADDR_CONFIG 0x3BD4 +#define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3BD5 +#define mmUVD_VCPU_CACHE_OFFSET0 0x3D36 +#define mmUVD_VCPU_CACHE_OFFSET1 0x3D38 +#define mmUVD_VCPU_CACHE_OFFSET2 0x3D3A +#define mmUVD_VCPU_CACHE_SIZE0 0x3D37 +#define mmUVD_VCPU_CACHE_SIZE1 0x3D39 +#define mmUVD_VCPU_CACHE_SIZE2 0x3D3B +#define mmUVD_VCPU_CNTL 0x3D98 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h new file mode 100644 index 000000000000..8ee3149df5b7 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h @@ -0,0 +1,795 @@ +/* + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef UVD_4_0_SH_MASK_H +#define UVD_4_0_SH_MASK_H + +#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x00000001L +#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x00000000 +#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x00000002L +#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x00000001 +#define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x0000001cL +#define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x00000002 +#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003cL +#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x00000002 +#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007c0L +#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x00000006 +#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L +#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x00000000 +#define UVD_CGC_CTRL__IDCT_MODE_MASK 0x00800000L +#define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x00000017 +#define UVD_CGC_CTRL__LBSI_MODE_MASK 0x04000000L +#define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x0000001a +#define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x00200000L +#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x00000015 +#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x00400000L +#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x00000016 +#define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x08000000L +#define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x0000001b +#define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L +#define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x00000019 +#define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x00040000L +#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x00000012 +#define UVD_CGC_CTRL__MPRD_MODE_MASK 0x01000000L +#define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x00000018 +#define UVD_CGC_CTRL__RBC_MODE_MASK 0x00100000L +#define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x00000014 +#define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L +#define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x00000013 +#define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000L +#define UVD_CGC_CTRL__SCPU_MODE__SHIFT 0x0000001e +#define UVD_CGC_CTRL__SYS_MODE_MASK 0x00010000L +#define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x00000010 +#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x00001000L +#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0x0000000c +#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x00004000L +#define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0x0000000e +#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L +#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0x0000000d +#define UVD_CGC_CTRL__UDEC_MODE_MASK 0x00020000L +#define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x00000011 +#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x00008000L +#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0x0000000f +#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x00000800L +#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0x0000000b +#define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000L +#define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x0000001d +#define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000L +#define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x0000001c +#define UVD_CGC_GATE__IDCT_MASK 0x00000080L +#define UVD_CGC_GATE__IDCT__SHIFT 0x00000007 +#define UVD_CGC_GATE__LBSI_MASK 0x00000400L +#define UVD_CGC_GATE__LBSI__SHIFT 0x0000000a +#define UVD_CGC_GATE__LMI_MC_MASK 0x00000020L +#define UVD_CGC_GATE__LMI_MC__SHIFT 0x00000005 +#define UVD_CGC_GATE__LMI_UMC_MASK 0x00000040L +#define UVD_CGC_GATE__LMI_UMC__SHIFT 0x00000006 +#define UVD_CGC_GATE__LRBBM_MASK 0x00000800L +#define UVD_CGC_GATE__LRBBM__SHIFT 0x0000000b +#define UVD_CGC_GATE__MPC_MASK 0x00000200L +#define UVD_CGC_GATE__MPC__SHIFT 0x00000009 +#define UVD_CGC_GATE__MPEG2_MASK 0x00000004L +#define UVD_CGC_GATE__MPEG2__SHIFT 0x00000002 +#define UVD_CGC_GATE__MPRD_MASK 0x00000100L +#define UVD_CGC_GATE__MPRD__SHIFT 0x00000008 +#define UVD_CGC_GATE__RBC_MASK 0x00000010L +#define UVD_CGC_GATE__RBC__SHIFT 0x00000004 +#define UVD_CGC_GATE__REGS_MASK 0x00000008L +#define UVD_CGC_GATE__REGS__SHIFT 0x00000003 +#define UVD_CGC_GATE__SCPU_MASK 0x00080000L +#define UVD_CGC_GATE__SCPU__SHIFT 0x00000013 +#define UVD_CGC_GATE__SYS_MASK 0x00000001L +#define UVD_CGC_GATE__SYS__SHIFT 0x00000000 +#define UVD_CGC_GATE__UDEC_CM_MASK 0x00002000L +#define UVD_CGC_GATE__UDEC_CM__SHIFT 0x0000000d +#define UVD_CGC_GATE__UDEC_DB_MASK 0x00008000L +#define UVD_CGC_GATE__UDEC_DB__SHIFT 0x0000000f +#define UVD_CGC_GATE__UDEC_IT_MASK 0x00004000L +#define UVD_CGC_GATE__UDEC_IT__SHIFT 0x0000000e +#define UVD_CGC_GATE__UDEC_MASK 0x00000002L +#define UVD_CGC_GATE__UDEC_MP_MASK 0x00010000L +#define UVD_CGC_GATE__UDEC_MP__SHIFT 0x00000010 +#define UVD_CGC_GATE__UDEC_RE_MASK 0x00001000L +#define UVD_CGC_GATE__UDEC_RE__SHIFT 0x0000000c +#define UVD_CGC_GATE__UDEC__SHIFT 0x00000001 +#define UVD_CGC_GATE__VCPU_MASK 0x00040000L +#define UVD_CGC_GATE__VCPU__SHIFT 0x00000012 +#define UVD_CGC_GATE__WCB_MASK 0x00020000L +#define UVD_CGC_GATE__WCB__SHIFT 0x00000011 +#define UVD_CGC_MEM_CTRL__LCM_LS_EN_MASK 0x00002000L +#define UVD_CGC_MEM_CTRL__LCM_LS_EN__SHIFT 0x0000000d +#define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN_MASK 0x00000001L +#define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN__SHIFT 0x00000000 +#define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0x00f00000L +#define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x00000014 +#define UVD_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0x000f0000L +#define UVD_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x00000010 +#define UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK 0x00001000L +#define UVD_CGC_MEM_CTRL__MIF_LS_EN__SHIFT 0x0000000c +#define UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK 0x00000002L +#define UVD_CGC_MEM_CTRL__MPC_LS_EN__SHIFT 0x00000001 +#define UVD_CGC_MEM_CTRL__MPRD_LS_EN_MASK 0x00000004L +#define UVD_CGC_MEM_CTRL__MPRD_LS_EN__SHIFT 0x00000002 +#define UVD_CGC_MEM_CTRL__SCPU_LS_EN_MASK 0x00000800L +#define UVD_CGC_MEM_CTRL__SCPU_LS_EN__SHIFT 0x0000000b +#define UVD_CGC_MEM_CTRL__SYS_LS_EN_MASK 0x00000200L +#define UVD_CGC_MEM_CTRL__SYS_LS_EN__SHIFT 0x00000009 +#define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN_MASK 0x00000020L +#define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN__SHIFT 0x00000005 +#define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN_MASK 0x00000080L +#define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN__SHIFT 0x00000007 +#define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN_MASK 0x00000040L +#define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN__SHIFT 0x00000006 +#define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN_MASK 0x00000100L +#define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN__SHIFT 0x00000008 +#define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN_MASK 0x00000010L +#define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN__SHIFT 0x00000004 +#define UVD_CGC_MEM_CTRL__VCPU_LS_EN_MASK 0x00000400L +#define UVD_CGC_MEM_CTRL__VCPU_LS_EN__SHIFT 0x0000000a +#define UVD_CGC_MEM_CTRL__WCB_LS_EN_MASK 0x00000008L +#define UVD_CGC_MEM_CTRL__WCB_LS_EN__SHIFT 0x00000003 +#define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x00004000L +#define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0x0000000e +#define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x00008000L +#define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0x0000000f +#define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x00200000L +#define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x00000015 +#define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x00400000L +#define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x00000016 +#define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x00001000L +#define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0x0000000c +#define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x00002000L +#define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0x0000000d +#define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x00800000L +#define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x00000017 +#define UVD_CGC_STATUS__MPC_DCLK_MASK 0x00100000L +#define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x00000014 +#define UVD_CGC_STATUS__MPC_SCLK_MASK 0x00080000L +#define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x00000013 +#define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x00000080L +#define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x00000007 +#define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x00000040L +#define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x00000006 +#define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x00000100L +#define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x00000008 +#define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x00020000L +#define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x00000011 +#define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x00010000L +#define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x00000010 +#define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x00040000L +#define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x00000012 +#define UVD_CGC_STATUS__RBC_SCLK_MASK 0x00000800L +#define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0x0000000b +#define UVD_CGC_STATUS__REGS_SCLK_MASK 0x00000200L +#define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x00000009 +#define UVD_CGC_STATUS__REGS_VCLK_MASK 0x00000400L +#define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0x0000000a +#define UVD_CGC_STATUS__SCPU_SCLK_MASK 0x08000000L +#define UVD_CGC_STATUS__SCPU_SCLK__SHIFT 0x0000001b +#define UVD_CGC_STATUS__SCPU_VCLK_MASK 0x10000000L +#define UVD_CGC_STATUS__SCPU_VCLK__SHIFT 0x0000001c +#define UVD_CGC_STATUS__SYS_DCLK_MASK 0x00000002L +#define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x00000001 +#define UVD_CGC_STATUS__SYS_SCLK_MASK 0x00000001L +#define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x00000000 +#define UVD_CGC_STATUS__SYS_VCLK_MASK 0x00000004L +#define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x00000002 +#define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x00000010L +#define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x00000004 +#define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x00000008L +#define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x00000003 +#define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x00000020L +#define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x00000005 +#define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x02000000L +#define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x00000019 +#define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x04000000L +#define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x0000001a +#define UVD_CGC_STATUS__WCB_SCLK_MASK 0x01000000L +#define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x00000018 +#define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x00000010L +#define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x00000004 +#define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x00000008L +#define UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT 0x00000003 +#define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x00000020L +#define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x00000005 +#define UVD_CGC_UDEC_STATUS__DB_DCLK_MASK 0x00000400L +#define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0x0000000a +#define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x00000200L +#define UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT 0x00000009 +#define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x00000800L +#define UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT 0x0000000b +#define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x00000080L +#define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x00000007 +#define UVD_CGC_UDEC_STATUS__IT_SCLK_MASK 0x00000040L +#define UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT 0x00000006 +#define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x00000100L +#define UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT 0x00000008 +#define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x00002000L +#define UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT 0x0000000d +#define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x00001000L +#define UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT 0x0000000c +#define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x00004000L +#define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0x0000000e +#define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x00000002L +#define UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT 0x00000001 +#define UVD_CGC_UDEC_STATUS__RE_SCLK_MASK 0x00000001L +#define UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT 0x00000000 +#define UVD_CGC_UDEC_STATUS__RE_VCLK_MASK 0x00000004L +#define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x00000002 +#define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xffffffffL +#define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x00000000 +#define UVD_CTX_DATA__DATA_MASK 0xffffffffL +#define UVD_CTX_DATA__DATA__SHIFT 0x00000000 +#define UVD_CTX_INDEX__INDEX_MASK 0x000001ffL +#define UVD_CTX_INDEX__INDEX__SHIFT 0x00000000 +#define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x00000001L +#define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x00000002L +#define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x00000001 +#define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x00000000 +#define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7ffffffeL +#define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x00000001L +#define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x00000000 +#define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x00000001 +#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000L +#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x0000001f +#define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xffffffffL +#define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x00000000 +#define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xffffffffL +#define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x00000000 +#define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT_MASK 0x0000000fL +#define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT__SHIFT 0x00000000 +#define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT_MASK 0x00000f00L +#define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT__SHIFT 0x00000008 +#define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT_MASK 0x0000f000L +#define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT__SHIFT 0x0000000c +#define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT_MASK 0x000000f0L +#define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT__SHIFT 0x00000004 +#define UVD_LMI_ADDR_EXT__CM_ADDR_EXT_MASK 0x000000f0L +#define UVD_LMI_ADDR_EXT__CM_ADDR_EXT__SHIFT 0x00000004 +#define UVD_LMI_ADDR_EXT__IT_ADDR_EXT_MASK 0x00000f00L +#define UVD_LMI_ADDR_EXT__IT_ADDR_EXT__SHIFT 0x00000008 +#define UVD_LMI_ADDR_EXT__MP_ADDR_EXT_MASK 0x00f00000L +#define UVD_LMI_ADDR_EXT__MP_ADDR_EXT__SHIFT 0x00000014 +#define UVD_LMI_ADDR_EXT__RE_ADDR_EXT_MASK 0x000f0000L +#define UVD_LMI_ADDR_EXT__RE_ADDR_EXT__SHIFT 0x00000010 +#define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT_MASK 0x0000000fL +#define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT__SHIFT 0x00000000 +#define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT_MASK 0x0f000000L +#define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT__SHIFT 0x00000018 +#define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT_MASK 0xf0000000L +#define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT__SHIFT 0x0000001c +#define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT_MASK 0x0000f000L +#define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT__SHIFT 0x0000000c +#define UVD_LMI_CACHE_CTRL__CM_EN_MASK 0x00000004L +#define UVD_LMI_CACHE_CTRL__CM_EN__SHIFT 0x00000002 +#define UVD_LMI_CACHE_CTRL__CM_FLUSH_MASK 0x00000008L +#define UVD_LMI_CACHE_CTRL__CM_FLUSH__SHIFT 0x00000003 +#define UVD_LMI_CACHE_CTRL__IT_EN_MASK 0x00000001L +#define UVD_LMI_CACHE_CTRL__IT_EN__SHIFT 0x00000000 +#define UVD_LMI_CACHE_CTRL__IT_FLUSH_MASK 0x00000002L +#define UVD_LMI_CACHE_CTRL__IT_FLUSH__SHIFT 0x00000001 +#define UVD_LMI_CACHE_CTRL__VCPU_EN_MASK 0x00000010L +#define UVD_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x00000004 +#define UVD_LMI_CACHE_CTRL__VCPU_FLUSH_MASK 0x00000020L +#define UVD_LMI_CACHE_CTRL__VCPU_FLUSH__SHIFT 0x00000005 +#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x00000004L +#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x00000002 +#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x00000080L +#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x00000007 +#define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x00000008L +#define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x00000003 +#define UVD_LMI_CTRL2__MCIF_WR_WATERMARK_MASK 0x00000070L +#define UVD_LMI_CTRL2__MCIF_WR_WATERMARK__SHIFT 0x00000004 +#define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x00000600L +#define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x00000009 +#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x00001800L +#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0x0000000b +#define UVD_LMI_CTRL2__SPH_DIS_MASK 0x00000001L +#define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x00000000 +#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x00008000L +#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN__SHIFT 0x0000000f +#define UVD_LMI_CTRL2__STALL_ARB_MASK 0x00000002L +#define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x00000001 +#define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L +#define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x00000008 +#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK 0x00002000L +#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT 0x0000000d +#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK 0x00004000L +#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0x0000000e +#define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000800L +#define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0x0000000b +#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x00400000L +#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x00000016 +#define UVD_LMI_CTRL__CRC_RESET_MASK 0x00004000L +#define UVD_LMI_CTRL__CRC_RESET__SHIFT 0x0000000e +#define UVD_LMI_CTRL__CRC_SEL_MASK 0x000f8000L +#define UVD_LMI_CTRL__CRC_SEL__SHIFT 0x0000000f +#define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x00002000L +#define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0x0000000d +#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x00800000L +#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x00000017 +#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x01000000L +#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x00000018 +#define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK 0x00100000L +#define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL__SHIFT 0x00000014 +#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x02000000L +#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x00000019 +#define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x00001000L +#define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0x0000000c +#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK 0x04000000L +#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT 0x0000001a +#define UVD_LMI_CTRL__REQ_MODE_MASK 0x00000200L +#define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x00000009 +#define UVD_LMI_CTRL__RFU_MASK 0xf8000000L +#define UVD_LMI_CTRL__RFU_MASK 0xfc000000L +#define UVD_LMI_CTRL__RFU__SHIFT 0x0000001a +#define UVD_LMI_CTRL__RFU__SHIFT 0x0000001b +#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x00200000L +#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x00000015 +#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x00000100L +#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x00000008 +#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0x000000ffL +#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x00000000 +#define UVD_LMI_EXT40_ADDR__ADDR_MASK 0x000000ffL +#define UVD_LMI_EXT40_ADDR__ADDR__SHIFT 0x00000000 +#define UVD_LMI_EXT40_ADDR__INDEX_MASK 0x001f0000L +#define UVD_LMI_EXT40_ADDR__INDEX__SHIFT 0x00000010 +#define UVD_LMI_EXT40_ADDR__WRITE_ADDR_MASK 0x80000000L +#define UVD_LMI_EXT40_ADDR__WRITE_ADDR__SHIFT 0x0000001f +#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x00001000L +#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT 0x0000000c +#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK 0x00002000L +#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT 0x0000000d +#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK 0x00000080L +#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT 0x00000007 +#define UVD_LMI_STATUS__READ_CLEAN_MASK 0x00000001L +#define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x00000100L +#define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT 0x00000008 +#define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x00000000 +#define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x00000800L +#define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT 0x0000000b +#define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK 0x00000010L +#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x00000200L +#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x00000009 +#define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT 0x00000004 +#define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK 0x00000400L +#define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0x0000000a +#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK 0x00000020L +#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x00000040L +#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x00000006 +#define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x00000005 +#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x00000008L +#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x00000003 +#define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x00000002L +#define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x00000004L +#define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x00000002 +#define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x00000001 +#define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP_MASK 0x00000003L +#define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP__SHIFT 0x00000000 +#define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP_MASK 0x0000000cL +#define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP__SHIFT 0x00000002 +#define UVD_LMI_SWAP_CNTL__CM_MC_SWAP_MASK 0x00000c00L +#define UVD_LMI_SWAP_CNTL__CM_MC_SWAP__SHIFT 0x0000000a +#define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP_MASK 0x000c0000L +#define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x00000012 +#define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP_MASK 0x0000c000L +#define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0x0000000e +#define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x00030000L +#define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP_MASK 0x03000000L +#define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x00000010 +#define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x00000018 +#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000cL +#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x00000002 +#define UVD_LMI_SWAP_CNTL__IT_MC_SWAP_MASK 0x00003000L +#define UVD_LMI_SWAP_CNTL__IT_MC_SWAP__SHIFT 0x0000000c +#define UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK 0xc0000000L +#define UVD_LMI_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x0000001e +#define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP_MASK 0x00c00000L +#define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP__SHIFT 0x00000016 +#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L +#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x00000000 +#define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK 0x00000030L +#define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT 0x00000004 +#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0x0c000000L +#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT 0x0000001a +#define UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000L +#define UVD_LMI_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x0000001c +#define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0x000000c0L +#define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x00000006 +#define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x00000300L +#define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x00000008 +#define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x007ffff0L +#define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x00000004 +#define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L +#define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x00000000 +#define UVD_MASTINT_EN__SYS_EN_MASK 0x00000004L +#define UVD_MASTINT_EN__SYS_EN__SHIFT 0x00000002 +#define UVD_MASTINT_EN__VCPU_EN_MASK 0x00000002L +#define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x00000001 +#define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008 +#define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L +#define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x00000018 +#define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS_MASK 0x00700000L +#define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS__SHIFT 0x00000014 +#define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L +#define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e +#define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000 +#define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L +#define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c +#define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L +#define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004 +#define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L +#define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c +#define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L +#define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010 +#define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008 +#define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L +#define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x00000018 +#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS_MASK 0x00700000L +#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS__SHIFT 0x00000014 +#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L +#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e +#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000 +#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L +#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c +#define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L +#define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004 +#define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L +#define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c +#define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L +#define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010 +#define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008 +#define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L +#define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x00000018 +#define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS_MASK 0x00700000L +#define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS__SHIFT 0x00000014 +#define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L +#define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e +#define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000 +#define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L +#define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c +#define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L +#define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004 +#define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L +#define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c +#define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L +#define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010 +#define UVD_MPC_CNTL__AVE_WEIGHT_MASK 0x00030000L +#define UVD_MPC_CNTL__AVE_WEIGHT__SHIFT 0x00000010 +#define UVD_MPC_CNTL__DBG_MUX_MASK 0x00000700L +#define UVD_MPC_CNTL__DBG_MUX__SHIFT 0x00000008 +#define UVD_MPC_CNTL__PERF_RST_MASK 0x00000040L +#define UVD_MPC_CNTL__PERF_RST__SHIFT 0x00000006 +#define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x00000038L +#define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x00000003 +#define UVD_MPC_CNTL__URGENT_EN_MASK 0x00040000L +#define UVD_MPC_CNTL__URGENT_EN__SHIFT 0x00000012 +#define UVD_MPC_SET_ALU__FUNCT_MASK 0x00000007L +#define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x00000000 +#define UVD_MPC_SET_ALU__OPERAND_MASK 0x00000ff0L +#define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x00000004 +#define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x0000003fL +#define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x00000000 +#define UVD_MPC_SET_MUXA0__VARA_1_MASK 0x00000fc0L +#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x00000006 +#define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x0003f000L +#define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0x0000000c +#define UVD_MPC_SET_MUXA0__VARA_3_MASK 0x00fc0000L +#define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x00000012 +#define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3f000000L +#define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x00000018 +#define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x0000003fL +#define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x00000000 +#define UVD_MPC_SET_MUXA1__VARA_6_MASK 0x00000fc0L +#define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x00000006 +#define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x0003f000L +#define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0x0000000c +#define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x0000003fL +#define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x00000000 +#define UVD_MPC_SET_MUXB0__VARB_1_MASK 0x00000fc0L +#define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x00000006 +#define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x0003f000L +#define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0x0000000c +#define UVD_MPC_SET_MUXB0__VARB_3_MASK 0x00fc0000L +#define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x00000012 +#define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3f000000L +#define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x00000018 +#define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x0000003fL +#define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x00000000 +#define UVD_MPC_SET_MUXB1__VARB_6_MASK 0x00000fc0L +#define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x00000006 +#define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x0003f000L +#define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0x0000000c +#define UVD_MPC_SET_MUX__SET_0_MASK 0x00000007L +#define UVD_MPC_SET_MUX__SET_0__SHIFT 0x00000000 +#define UVD_MPC_SET_MUX__SET_1_MASK 0x00000038L +#define UVD_MPC_SET_MUX__SET_1__SHIFT 0x00000003 +#define UVD_MPC_SET_MUX__SET_2_MASK 0x000001c0L +#define UVD_MPC_SET_MUX__SET_2__SHIFT 0x00000006 +#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK 0x00000003L +#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT 0x00000000 +#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK 0x00300000L +#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x00000014 +#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK 0x00c00000L +#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT 0x00000016 +#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK 0x03000000L +#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT 0x00000018 +#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK 0x0c000000L +#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT 0x0000001a +#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK 0x30000000L +#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT 0x0000001c +#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK 0xc0000000L +#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT 0x0000001e +#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK 0x0000000cL +#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x00000002 +#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK 0x00000030L +#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT 0x00000004 +#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK 0x000000c0L +#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT 0x00000006 +#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK 0x00000300L +#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT 0x00000008 +#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK 0x00000c00L +#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0x0000000a +#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK 0x00003000L +#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT 0x0000000c +#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK 0x0000c000L +#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0x0000000e +#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK 0x00030000L +#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT 0x00000010 +#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK 0x000c0000L +#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT 0x00000012 +#define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK 0x000000ffL +#define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR__SHIFT 0x00000000 +#define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK 0x00000400L +#define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT__SHIFT 0x0000000a +#define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT_MASK 0x00000800L +#define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT__SHIFT 0x0000000b +#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK 0x00000100L +#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN__SHIFT 0x00000008 +#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK 0x00000200L +#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP__SHIFT 0x00000009 +#define UVD_PGFSM_CONFIG__UVD_PGFSM_READ_MASK 0x00002000L +#define UVD_PGFSM_CONFIG__UVD_PGFSM_READ__SHIFT 0x0000000d +#define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR_MASK 0xf0000000L +#define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR__SHIFT 0x0000001c +#define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE_MASK 0x00001000L +#define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE__SHIFT 0x0000000c +#define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE_MASK 0x00ffffffL +#define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE__SHIFT 0x00000000 +#define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE_MASK 0x00ffffffL +#define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE__SHIFT 0x00000000 +#define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x00000001L +#define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x00000000 +#define UVD_RBC_IB_BASE__IB_BASE_MASK 0xffffffc0L +#define UVD_RBC_IB_BASE__IB_BASE__SHIFT 0x00000006 +#define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x007ffff0L +#define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x00000004 +#define UVD_RBC_RB_BASE__RB_BASE_MASK 0xffffffc0L +#define UVD_RBC_RB_BASE__RB_BASE__SHIFT 0x00000006 +#define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x00001f00L +#define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x00000008 +#define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x0000001fL +#define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x00000000 +#define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x00010000L +#define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x00000010 +#define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x01000000L +#define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x00000018 +#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000L +#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x0000001c +#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x00100000L +#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x00000014 +#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xffffffffL +#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000000 +#define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x007ffff0L +#define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x00000004 +#define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x007ffff0L +#define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x00000004 +#define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0x000fffffL +#define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x00000000 +#define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0x000fffffL +#define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x00000000 +#define UVD_SEMA_CMD__MODE_MASK 0x00000040L +#define UVD_SEMA_CMD__MODE__SHIFT 0x00000006 +#define UVD_SEMA_CMD__REQ_CMD_MASK 0x0000000fL +#define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x00000000 +#define UVD_SEMA_CMD__VMID_EN_MASK 0x00000080L +#define UVD_SEMA_CMD__VMID_EN__SHIFT 0x00000007 +#define UVD_SEMA_CMD__VMID_MASK 0x00000f00L +#define UVD_SEMA_CMD__VMID__SHIFT 0x00000008 +#define UVD_SEMA_CMD__WR_PHASE_MASK 0x00000030L +#define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x00000004 +#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x00000002L +#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x00000001 +#define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x00000001L +#define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x00000000 +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x00000018 +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x001ffffeL +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x00000001 +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x00000001L +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x00000000 +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000004L +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x00000002 +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x00000008L +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x00000003 +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x00000002L +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x00000001 +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000001L +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x00000000 +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x00000018 +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x001ffffeL +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x00000001 +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x00000001L +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x00000000 +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x00000018 +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x001ffffeL +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x00000001 +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x00000001L +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x00000000 +#define UVD_SOFT_RESET__CSM_SOFT_RESET_MASK 0x00000020L +#define UVD_SOFT_RESET__CSM_SOFT_RESET__SHIFT 0x00000005 +#define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x00000040L +#define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x00000006 +#define UVD_SOFT_RESET__FWV_SOFT_RESET_MASK 0x00000200L +#define UVD_SOFT_RESET__FWV_SOFT_RESET__SHIFT 0x00000009 +#define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x00001000L +#define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT 0x0000000c +#define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x00000400L +#define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0x0000000a +#define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x00000002L +#define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x00000001 +#define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x00010000L +#define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x00000010 +#define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x00000004L +#define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x00000002 +#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x00002000L +#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0x0000000d +#define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x00008000L +#define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0x0000000f +#define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x00000100L +#define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x00000008 +#define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x00000800L +#define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT 0x0000000b +#define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x00000001L +#define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x00000000 +#define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x00004000L +#define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0x0000000e +#define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000080L +#define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x00000007 +#define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x00000010L +#define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x00000004 +#define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x00000008L +#define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x00000003 +#define UVD_STATUS__RBC_BUSY_MASK 0x00000001L +#define UVD_STATUS__RBC_BUSY__SHIFT 0x00000000 +#define UVD_STATUS__VCPU_REPORT_MASK 0x000000feL +#define UVD_STATUS__VCPU_REPORT__SHIFT 0x00000001 +#define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008 +#define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L +#define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x00000018 +#define UVD_UDEC_ADDR_CONFIG__NUM_GPUS_MASK 0x00700000L +#define UVD_UDEC_ADDR_CONFIG__NUM_GPUS__SHIFT 0x00000014 +#define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L +#define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e +#define UVD_UDEC_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define UVD_UDEC_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000 +#define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L +#define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c +#define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L +#define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004 +#define UVD_UDEC_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L +#define UVD_UDEC_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c +#define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L +#define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010 +#define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008 +#define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L +#define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x00000018 +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS_MASK 0x00700000L +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x00000014 +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000 +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c +#define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L +#define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004 +#define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L +#define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c +#define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L +#define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010 +#define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008 +#define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L +#define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x00000018 +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK 0x00700000L +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS__SHIFT 0x00000014 +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000 +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c +#define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L +#define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004 +#define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L +#define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c +#define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L +#define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010 +#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x01ffffffL +#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x00000000 +#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x01ffffffL +#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x00000000 +#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x01ffffffL +#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x00000000 +#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x001fffffL +#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x00000000 +#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x001fffffL +#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x00000000 +#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x001fffffL +#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x00000000 +#define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x00000100L +#define UVD_VCPU_CNTL__ABORT_REQ__SHIFT 0x00000008 +#define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4_MASK 0x00000010L +#define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4__SHIFT 0x00000004 +#define UVD_VCPU_CNTL__CABAC_MB_ACC_MASK 0x10000000L +#define UVD_VCPU_CNTL__CABAC_MB_ACC__SHIFT 0x0000001c +#define UVD_VCPU_CNTL__CLK_ACTIVE_MASK 0x00020000L +#define UVD_VCPU_CNTL__CLK_ACTIVE__SHIFT 0x00000011 +#define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L +#define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x00000009 +#define UVD_VCPU_CNTL__DBG_MUX_MASK 0x0000e000L +#define UVD_VCPU_CNTL__DBG_MUX__SHIFT 0x0000000d +#define UVD_VCPU_CNTL__ECPU_AM32_EN_MASK 0x20000000L +#define UVD_VCPU_CNTL__ECPU_AM32_EN__SHIFT 0x0000001d +#define UVD_VCPU_CNTL__IRQ_ERR_MASK 0x0000000fL +#define UVD_VCPU_CNTL__IRQ_ERR__SHIFT 0x00000000 +#define UVD_VCPU_CNTL__JTAG_EN_MASK 0x00010000L +#define UVD_VCPU_CNTL__JTAG_EN__SHIFT 0x00000010 +#define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK 0x00000020L +#define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT 0x00000005 +#define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK 0x00000040L +#define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT 0x00000006 +#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0x0ff00000L +#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x00000014 +#define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x00000080L +#define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x00000007 +#define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK 0x00040000L +#define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT 0x00000012 +#define UVD_VCPU_CNTL__TRCE_EN_MASK 0x00000400L +#define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0x0000000a +#define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x00001800L +#define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0x0000000b +#define UVD_VCPU_CNTL__WMV9_EN_MASK 0x40000000L +#define UVD_VCPU_CNTL__WMV9_EN__SHIFT 0x0000001e + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_d.h new file mode 100644 index 000000000000..2176548e9203 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_d.h @@ -0,0 +1,64 @@ +/* + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef VCE_1_0_D_H +#define VCE_1_0_D_H + +#define mmVCE_CLOCK_GATING_A 0x80BE +#define mmVCE_CLOCK_GATING_B 0x80BF +#define mmVCE_LMI_CACHE_CTRL 0x83BD +#define mmVCE_LMI_CTRL 0x83A6 +#define mmVCE_LMI_CTRL2 0x839D +#define mmVCE_LMI_MISC_CTRL 0x83B5 +#define mmVCE_LMI_STATUS 0x83A7 +#define mmVCE_LMI_SWAP_CNTL 0x83AD +#define mmVCE_LMI_SWAP_CNTL1 0x83AE +#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR 0x8397 +#define mmVCE_LMI_VM_CTRL 0x83A8 +#define mmVCE_RB_ARB_CTRL 0x809F +#define mmVCE_RB_BASE_HI 0x8061 +#define mmVCE_RB_BASE_HI2 0x805C +#define mmVCE_RB_BASE_LO 0x8060 +#define mmVCE_RB_BASE_LO2 0x805B +#define mmVCE_RB_RPTR 0x8063 +#define mmVCE_RB_RPTR2 0x805E +#define mmVCE_RB_SIZE 0x8062 +#define mmVCE_RB_SIZE2 0x805D +#define mmVCE_RB_WPTR 0x8064 +#define mmVCE_RB_WPTR2 0x805F +#define mmVCE_SOFT_RESET 0x8048 +#define mmVCE_STATUS 0x8001 +#define mmVCE_SYS_INT_ACK 0x8341 +#define mmVCE_SYS_INT_EN 0x8340 +#define mmVCE_SYS_INT_STATUS 0x8341 +#define mmVCE_UENC_CLOCK_GATING 0x816F +#define mmVCE_UENC_DMA_DCLK_CTRL 0x8250 +#define mmVCE_UENC_REG_CLOCK_GATING 0x8170 +#define mmVCE_VCPU_CACHE_OFFSET0 0x8009 +#define mmVCE_VCPU_CACHE_OFFSET1 0x800B +#define mmVCE_VCPU_CACHE_OFFSET2 0x800D +#define mmVCE_VCPU_CACHE_SIZE0 0x800A +#define mmVCE_VCPU_CACHE_SIZE1 0x800C +#define mmVCE_VCPU_CACHE_SIZE2 0x800E +#define mmVCE_VCPU_CNTL 0x8005 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_sh_mask.h new file mode 100644 index 000000000000..ea5b26b11cb1 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_sh_mask.h @@ -0,0 +1,99 @@ +/* + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef VCE_1_0_SH_MASK_H +#define VCE_1_0_SH_MASK_H + +#define VCE_LMI_CACHE_CTRL__VCPU_EN_MASK 0x00000001L +#define VCE_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x00000000 +#define VCE_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L +#define VCE_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x00000008 +#define VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x00200000L +#define VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x00000015 +#define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP_MASK 0x00003ffcL +#define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP__SHIFT 0x00000002 +#define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP_MASK 0x00000003L +#define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP__SHIFT 0x00000000 +#define VCE_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x00000003L +#define VCE_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x00000000 +#define VCE_LMI_SWAP_CNTL__WR_MC_CID_SWAP_MASK 0x00003ffcL +#define VCE_LMI_SWAP_CNTL__WR_MC_CID_SWAP__SHIFT 0x00000002 +#define VCE_LMI_VCPU_CACHE_40BIT_BAR__BAR_MASK 0xffffffffL +#define VCE_LMI_VCPU_CACHE_40BIT_BAR__BAR__SHIFT 0x00000000 +#define VCE_RB_BASE_HI2__RB_BASE_HI_MASK 0xffffffffL +#define VCE_RB_BASE_HI2__RB_BASE_HI__SHIFT 0x00000000 +#define VCE_RB_BASE_HI__RB_BASE_HI_MASK 0xffffffffL +#define VCE_RB_BASE_HI__RB_BASE_HI__SHIFT 0x00000000 +#define VCE_RB_BASE_LO2__RB_BASE_LO_MASK 0xffffffc0L +#define VCE_RB_BASE_LO2__RB_BASE_LO__SHIFT 0x00000006 +#define VCE_RB_BASE_LO__RB_BASE_LO_MASK 0xffffffc0L +#define VCE_RB_BASE_LO__RB_BASE_LO__SHIFT 0x00000006 +#define VCE_RB_RPTR2__RB_RPTR_MASK 0x007ffff0L +#define VCE_RB_RPTR2__RB_RPTR__SHIFT 0x00000004 +#define VCE_RB_RPTR__RB_RPTR_MASK 0x007ffff0L +#define VCE_RB_RPTR__RB_RPTR__SHIFT 0x00000004 +#define VCE_RB_SIZE2__RB_SIZE_MASK 0x007ffff0L +#define VCE_RB_SIZE2__RB_SIZE__SHIFT 0x00000004 +#define VCE_RB_SIZE__RB_SIZE_MASK 0x007ffff0L +#define VCE_RB_SIZE__RB_SIZE__SHIFT 0x00000004 +#define VCE_RB_WPTR2__RB_WPTR_MASK 0x007ffff0L +#define VCE_RB_WPTR2__RB_WPTR__SHIFT 0x00000004 +#define VCE_RB_WPTR__RB_WPTR_MASK 0x007ffff0L +#define VCE_RB_WPTR__RB_WPTR__SHIFT 0x00000004 +#define VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK 0x00000001L +#define VCE_SOFT_RESET__ECPU_SOFT_RESET__SHIFT 0x00000000 +#define VCE_STATUS__JOB_BUSY_MASK 0x00000001L +#define VCE_STATUS__JOB_BUSY__SHIFT 0x00000000 +#define VCE_STATUS__UENC_BUSY_MASK 0x00000100L +#define VCE_STATUS__UENC_BUSY__SHIFT 0x00000008 +#define VCE_STATUS__VCPU_REPORT_MASK 0x000000feL +#define VCE_STATUS__VCPU_REPORT__SHIFT 0x00000001 +#define VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK_MASK 0x00000008L +#define VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK__SHIFT 0x00000003 +#define VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK 0x00000008L +#define VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN__SHIFT 0x00000003 +#define VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT_MASK 0x00000008L +#define VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT__SHIFT 0x00000003 +#define VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK 0x00000002L +#define VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON__SHIFT 0x00000001 +#define VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK 0x00000004L +#define VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON__SHIFT 0x00000002 +#define VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK 0x00000001L +#define VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON__SHIFT 0x00000000 +#define VCE_VCPU_CACHE_OFFSET0__OFFSET_MASK 0x0fffffffL +#define VCE_VCPU_CACHE_OFFSET0__OFFSET__SHIFT 0x00000000 +#define VCE_VCPU_CACHE_OFFSET1__OFFSET_MASK 0x0fffffffL +#define VCE_VCPU_CACHE_OFFSET1__OFFSET__SHIFT 0x00000000 +#define VCE_VCPU_CACHE_OFFSET2__OFFSET_MASK 0x0fffffffL +#define VCE_VCPU_CACHE_OFFSET2__OFFSET__SHIFT 0x00000000 +#define VCE_VCPU_CACHE_SIZE0__SIZE_MASK 0x00ffffffL +#define VCE_VCPU_CACHE_SIZE0__SIZE__SHIFT 0x00000000 +#define VCE_VCPU_CACHE_SIZE1__SIZE_MASK 0x00ffffffL +#define VCE_VCPU_CACHE_SIZE1__SIZE__SHIFT 0x00000000 +#define VCE_VCPU_CACHE_SIZE2__SIZE_MASK 0x00ffffffL +#define VCE_VCPU_CACHE_SIZE2__SIZE__SHIFT 0x00000000 +#define VCE_VCPU_CNTL__CLK_EN_MASK 0x00000001L +#define VCE_VCPU_CNTL__CLK_EN__SHIFT 0x00000000 +#define VCE_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x00040000L +#define VCE_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x00000012 + +#endif diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c index 0b1f2205c2f1..51a36077b993 100644 --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c @@ -41,7 +41,7 @@ #define PP_CHECK_HW(hwmgr) \ do { \ if ((hwmgr) == NULL || (hwmgr)->hwmgr_func == NULL) \ - return -EINVAL; \ + return 0; \ } while (0) static int pp_early_init(void *handle) @@ -115,6 +115,7 @@ static int pp_hw_init(void *handle) struct pp_instance *pp_handle; struct pp_smumgr *smumgr; struct pp_eventmgr *eventmgr; + struct pp_hwmgr *hwmgr; int ret = 0; if (handle == NULL) @@ -122,6 +123,7 @@ static int pp_hw_init(void *handle) pp_handle = (struct pp_instance *)handle; smumgr = pp_handle->smu_mgr; + hwmgr = pp_handle->hwmgr; if (smumgr == NULL || smumgr->smumgr_funcs == NULL || smumgr->smumgr_funcs->smu_init == NULL || @@ -141,9 +143,11 @@ static int pp_hw_init(void *handle) return ret; } - hw_init_power_state_table(pp_handle->hwmgr); - eventmgr = pp_handle->eventmgr; + PP_CHECK_HW(hwmgr); + + hw_init_power_state_table(hwmgr); + eventmgr = pp_handle->eventmgr; if (eventmgr == NULL || eventmgr->pp_eventmgr_init == NULL) return -EINVAL; @@ -243,7 +247,9 @@ static int pp_suspend(void *handle) pp_handle = (struct pp_instance *)handle; eventmgr = pp_handle->eventmgr; - pem_handle_event(eventmgr, AMD_PP_EVENT_SUSPEND, &event_data); + + if (eventmgr != NULL) + pem_handle_event(eventmgr, AMD_PP_EVENT_SUSPEND, &event_data); return 0; } @@ -273,7 +279,8 @@ static int pp_resume(void *handle) } eventmgr = pp_handle->eventmgr; - pem_handle_event(eventmgr, AMD_PP_EVENT_RESUME, &event_data); + if (eventmgr != NULL) + pem_handle_event(eventmgr, AMD_PP_EVENT_RESUME, &event_data); return 0; } @@ -340,8 +347,7 @@ static enum amd_dpm_forced_level pp_dpm_get_performance_level( hwmgr = ((struct pp_instance *)handle)->hwmgr; - if (hwmgr == NULL) - return -EINVAL; + PP_CHECK_HW(hwmgr); return (((struct pp_instance *)handle)->hwmgr->dpm_level); } @@ -448,6 +454,9 @@ static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id, if (pp_handle == NULL) return -EINVAL; + if (pp_handle->eventmgr == NULL) + return 0; + switch (event_id) { case AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE: ret = pem_handle_event(pp_handle->eventmgr, event_id, &data); @@ -582,6 +591,23 @@ static int pp_dpm_get_fan_speed_percent(void *handle, uint32_t *speed) return hwmgr->hwmgr_func->get_fan_speed_percent(hwmgr, speed); } +static int pp_dpm_get_fan_speed_rpm(void *handle, uint32_t *rpm) +{ + struct pp_hwmgr *hwmgr; + + if (handle == NULL) + return -EINVAL; + + hwmgr = ((struct pp_instance *)handle)->hwmgr; + + PP_CHECK_HW(hwmgr); + + if (hwmgr->hwmgr_func->get_fan_speed_rpm == NULL) + return -EINVAL; + + return hwmgr->hwmgr_func->get_fan_speed_rpm(hwmgr, rpm); +} + static int pp_dpm_get_temperature(void *handle) { struct pp_hwmgr *hwmgr; @@ -852,6 +878,7 @@ const struct amd_powerplay_funcs pp_dpm_funcs = { .get_fan_control_mode = pp_dpm_get_fan_control_mode, .set_fan_speed_percent = pp_dpm_set_fan_speed_percent, .get_fan_speed_percent = pp_dpm_get_fan_speed_percent, + .get_fan_speed_rpm = pp_dpm_get_fan_speed_rpm, .get_pp_num_states = pp_dpm_get_pp_num_states, .get_pp_table = pp_dpm_get_pp_table, .set_pp_table = pp_dpm_set_pp_table, @@ -881,6 +908,13 @@ static int amd_pp_instance_init(struct amd_pp_init *pp_init, if (ret) goto fail_smum; + + amd_pp->pp_handle = handle; + + if ((amdgpu_dpm == 0) + || cgs_is_virtualization_enabled(pp_init->device)) + return 0; + ret = hwmgr_init(pp_init, handle); if (ret) goto fail_hwmgr; @@ -889,7 +923,6 @@ static int amd_pp_instance_init(struct amd_pp_init *pp_init, if (ret) goto fail_eventmgr; - amd_pp->pp_handle = handle; return 0; fail_eventmgr: @@ -908,12 +941,13 @@ static int amd_pp_instance_fini(void *handle) if (instance == NULL) return -EINVAL; - eventmgr_fini(instance->eventmgr); - - hwmgr_fini(instance->hwmgr); + if ((amdgpu_dpm != 0) + && !cgs_is_virtualization_enabled(instance->smu_mgr->device)) { + eventmgr_fini(instance->eventmgr); + hwmgr_fini(instance->hwmgr); + } smum_fini(instance->smu_mgr); - kfree(handle); return 0; } @@ -972,6 +1006,10 @@ int amd_powerplay_reset(void *handle) hw_init_power_state_table(instance->hwmgr); + if ((amdgpu_dpm == 0) + || cgs_is_virtualization_enabled(instance->smu_mgr->device)) + return 0; + if (eventmgr == NULL || eventmgr->pp_eventmgr_init == NULL) return -EINVAL; @@ -993,6 +1031,8 @@ int amd_powerplay_display_configuration_change(void *handle, hwmgr = ((struct pp_instance *)handle)->hwmgr; + PP_CHECK_HW(hwmgr); + phm_store_dal_configuration_data(hwmgr, display_config); return 0; @@ -1010,6 +1050,8 @@ int amd_powerplay_get_display_power_level(void *handle, hwmgr = ((struct pp_instance *)handle)->hwmgr; + PP_CHECK_HW(hwmgr); + return phm_get_dal_power_level(hwmgr, output); } @@ -1027,6 +1069,8 @@ int amd_powerplay_get_current_clocks(void *handle, hwmgr = ((struct pp_instance *)handle)->hwmgr; + PP_CHECK_HW(hwmgr); + phm_get_dal_power_level(hwmgr, &simple_clocks); if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PowerContainment)) { @@ -1071,6 +1115,8 @@ int amd_powerplay_get_clock_by_type(void *handle, enum amd_pp_clock_type type, s hwmgr = ((struct pp_instance *)handle)->hwmgr; + PP_CHECK_HW(hwmgr); + result = phm_get_clock_by_type(hwmgr, type, clocks); return result; @@ -1089,6 +1135,8 @@ int amd_powerplay_get_display_mode_validation_clocks(void *handle, hwmgr = ((struct pp_instance *)handle)->hwmgr; + PP_CHECK_HW(hwmgr); + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DynamicPatchPowerState)) result = phm_get_max_high_clocks(hwmgr, clocks); diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c index 2028980f1ed4..b0c63c5f54c9 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c @@ -169,7 +169,7 @@ int cz_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate) if (bgate) { cgs_set_clockgating_state(hwmgr->device, AMD_IP_BLOCK_TYPE_UVD, - AMD_CG_STATE_UNGATE); + AMD_CG_STATE_GATE); cgs_set_powergating_state(hwmgr->device, AMD_IP_BLOCK_TYPE_UVD, AMD_PG_STATE_GATE); @@ -182,7 +182,7 @@ int cz_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate) AMD_CG_STATE_UNGATE); cgs_set_clockgating_state(hwmgr->device, AMD_IP_BLOCK_TYPE_UVD, - AMD_PG_STATE_GATE); + AMD_PG_STATE_UNGATE); cz_dpm_update_uvd_dpm(hwmgr, false); } diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c index 14f8c1f4da3d..0723758ed065 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c @@ -272,7 +272,7 @@ bool phm_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hw PHM_FUNC_CHECK(hwmgr); if (hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration == NULL) - return -EINVAL; + return false; return hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration(hwmgr); } diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c index 2ba7937d2545..dc6700aee18f 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c @@ -80,20 +80,17 @@ int hwmgr_init(struct amd_pp_init *pp_init, struct pp_instance *handle) switch (hwmgr->chip_id) { case CHIP_TOPAZ: topaz_set_asic_special_caps(hwmgr); - hwmgr->feature_mask &= ~(PP_SMC_VOLTAGE_CONTROL_MASK | - PP_VBI_TIME_SUPPORT_MASK | + hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK | PP_ENABLE_GFX_CG_THRU_SMU); hwmgr->pp_table_version = PP_TABLE_V0; break; case CHIP_TONGA: tonga_set_asic_special_caps(hwmgr); - hwmgr->feature_mask &= ~(PP_SMC_VOLTAGE_CONTROL_MASK | - PP_VBI_TIME_SUPPORT_MASK); + hwmgr->feature_mask &= ~PP_VBI_TIME_SUPPORT_MASK; break; case CHIP_FIJI: fiji_set_asic_special_caps(hwmgr); - hwmgr->feature_mask &= ~(PP_SMC_VOLTAGE_CONTROL_MASK | - PP_VBI_TIME_SUPPORT_MASK | + hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK | PP_ENABLE_GFX_CG_THRU_SMU); break; case CHIP_POLARIS11: @@ -685,20 +682,24 @@ void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr) int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr) { - if (amdgpu_sclk_deep_sleep_en) + if (amdgpu_pp_feature_mask & PP_SCLK_DEEP_SLEEP_MASK) phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep); else phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep); - if (amdgpu_powercontainment) + if (amdgpu_pp_feature_mask & PP_POWER_CONTAINMENT_MASK) { phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PowerContainment); - else + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_CAC); + } else { phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PowerContainment); - + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_CAC); + } hwmgr->feature_mask = amdgpu_pp_feature_mask; return 0; @@ -710,8 +711,10 @@ int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint32_t vol; int ret = 0; - if (hwmgr->chip_id < CHIP_POLARIS10) { - atomctrl_get_voltage_evv_on_sclk(hwmgr, voltage_type, sclk, id, voltage); + if (hwmgr->chip_id < CHIP_TONGA) { + ret = atomctrl_get_voltage_evv(hwmgr, id, voltage); + } else if (hwmgr->chip_id < CHIP_POLARIS10) { + ret = atomctrl_get_voltage_evv_on_sclk(hwmgr, voltage_type, sclk, id, voltage); if (*voltage >= 2000 || *voltage == 0) *voltage = 1150; } else { @@ -734,9 +737,6 @@ int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr) PHM_PlatformCaps_TCPRamping); phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_CAC); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_RegulatorHot); phm_cap_set(hwmgr->platform_descriptor.platformCaps, @@ -765,8 +765,6 @@ int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr) phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TablelessHardwareInterface); - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_CAC); return 0; } @@ -789,9 +787,6 @@ int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr) phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TablelessHardwareInterface); - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_CAC); - return 0; } @@ -808,8 +803,6 @@ int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr) phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TablelessHardwareInterface); phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_CAC); - phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_EVV); return 0; } diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c index cf2ee93d8475..a1fc4fcac1e0 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c @@ -149,7 +149,7 @@ int smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate) if (bgate) { cgs_set_clockgating_state(hwmgr->device, AMD_IP_BLOCK_TYPE_UVD, - AMD_CG_STATE_UNGATE); + AMD_CG_STATE_GATE); cgs_set_powergating_state(hwmgr->device, AMD_IP_BLOCK_TYPE_UVD, AMD_PG_STATE_GATE); @@ -162,7 +162,7 @@ int smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate) AMD_CG_STATE_UNGATE); cgs_set_clockgating_state(hwmgr->device, AMD_IP_BLOCK_TYPE_UVD, - AMD_CG_STATE_GATE); + AMD_CG_STATE_UNGATE); smu7_update_uvd_dpm(hwmgr, false); } diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c index 9e49f2777143..a74f60a575ae 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c @@ -993,13 +993,6 @@ static int smu7_start_dpm(struct pp_hwmgr *hwmgr) PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, SWRST_COMMAND_1, RESETLC, 0x0); - PP_ASSERT_WITH_CODE( - (0 == smum_send_msg_to_smc(hwmgr->smumgr, - PPSMC_MSG_Voltage_Cntl_Enable)), - "Failed to enable voltage DPM during DPM Start Function!", - return -EINVAL); - - if (smu7_enable_sclk_mclk_dpm(hwmgr)) { printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!"); return -EINVAL; @@ -1428,7 +1421,7 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr) phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ControlVDDCI); - if ((hwmgr->pp_table_version != PP_TABLE_V0) + if ((hwmgr->pp_table_version != PP_TABLE_V0) && (hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK) && (table_info->cac_dtp_table->usClockStretchAmount != 0)) phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ClockStretcher); @@ -1474,19 +1467,17 @@ static int smu7_get_evv_voltages(struct pp_hwmgr *hwmgr) struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = NULL; - if (table_info == NULL) - return -EINVAL; - - sclk_table = table_info->vdd_dep_on_sclk; - for (i = 0; i < SMU7_MAX_LEAKAGE_COUNT; i++) { vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i; if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) { - if (0 == phm_get_sclk_for_voltage_evv(hwmgr, + if ((hwmgr->pp_table_version == PP_TABLE_V1) + && !phm_get_sclk_for_voltage_evv(hwmgr, table_info->vddgfx_lookup_table, vv_id, &sclk)) { if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ClockStretcher)) { + sclk_table = table_info->vdd_dep_on_sclk; + for (j = 1; j < sclk_table->count; j++) { if (sclk_table->entries[j].clk == sclk && sclk_table->entries[j].cks_enable == 0) { @@ -1512,12 +1503,15 @@ static int smu7_get_evv_voltages(struct pp_hwmgr *hwmgr) } } } else { - if ((hwmgr->pp_table_version == PP_TABLE_V0) || !phm_get_sclk_for_voltage_evv(hwmgr, table_info->vddc_lookup_table, vv_id, &sclk)) { if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ClockStretcher)) { + if (table_info == NULL) + return -EINVAL; + sclk_table = table_info->vdd_dep_on_sclk; + for (j = 1; j < sclk_table->count; j++) { if (sclk_table->entries[j].clk == sclk && sclk_table->entries[j].cks_enable == 0) { @@ -2007,8 +2001,9 @@ static int smu7_thermal_parameter_init(struct pp_hwmgr *hwmgr) hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp = table_info->cac_dtp_table->usTargetOperatingTemp; - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ODFuzzyFanControlSupport); + if (hwmgr->feature_mask & PP_OD_FUZZY_FAN_CONTROL_MASK) + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_ODFuzzyFanControlSupport); } return 0; @@ -2147,9 +2142,11 @@ static int smu7_patch_limits_vddc(struct pp_hwmgr *hwmgr, struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); if (tab) { + vddc = tab->vddc; smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddc, &data->vddc_leakage); tab->vddc = vddc; + vddci = tab->vddci; smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddci, &data->vddci_leakage); tab->vddci = vddci; @@ -2995,19 +2992,19 @@ static int smu7_get_pp_table_entry_callback_func_v0(struct pp_hwmgr *hwmgr, if (!(data->mc_micro_code_feature & DISABLE_MC_LOADMICROCODE) && memory_clock > data->highest_mclk) data->highest_mclk = memory_clock; - performance_level = &(ps->performance_levels - [ps->performance_level_count++]); - PP_ASSERT_WITH_CODE( (ps->performance_level_count < smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_GRAPHICS)), "Performance levels exceeds SMC limit!", return -EINVAL); PP_ASSERT_WITH_CODE( - (ps->performance_level_count <= + (ps->performance_level_count < hwmgr->platform_descriptor.hardwareActivityPerformanceLevels), - "Performance levels exceeds Driver limit!", - return -EINVAL); + "Performance levels exceeds Driver limit, Skip!", + return 0); + + performance_level = &(ps->performance_levels + [ps->performance_level_count++]); /* Performance levels are arranged from low to high. */ performance_level->memory_clock = memory_clock; @@ -4247,18 +4244,26 @@ static int smu7_get_sclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks) { struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)hwmgr->pptable; - struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table; + struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table = NULL; + struct phm_clock_voltage_dependency_table *sclk_table; int i; - if (table_info == NULL) - return -EINVAL; - - dep_sclk_table = table_info->vdd_dep_on_sclk; - - for (i = 0; i < dep_sclk_table->count; i++) { - clocks->clock[i] = dep_sclk_table->entries[i].clk; - clocks->count++; + if (hwmgr->pp_table_version == PP_TABLE_V1) { + if (table_info == NULL || table_info->vdd_dep_on_sclk == NULL) + return -EINVAL; + dep_sclk_table = table_info->vdd_dep_on_sclk; + for (i = 0; i < dep_sclk_table->count; i++) { + clocks->clock[i] = dep_sclk_table->entries[i].clk; + clocks->count++; + } + } else if (hwmgr->pp_table_version == PP_TABLE_V0) { + sclk_table = hwmgr->dyn_state.vddc_dependency_on_sclk; + for (i = 0; i < sclk_table->count; i++) { + clocks->clock[i] = sclk_table->entries[i].clk; + clocks->count++; + } } + return 0; } @@ -4280,17 +4285,24 @@ static int smu7_get_mclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks) (struct phm_ppt_v1_information *)hwmgr->pptable; struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table; int i; + struct phm_clock_voltage_dependency_table *mclk_table; - if (table_info == NULL) - return -EINVAL; - - dep_mclk_table = table_info->vdd_dep_on_mclk; - - for (i = 0; i < dep_mclk_table->count; i++) { - clocks->clock[i] = dep_mclk_table->entries[i].clk; - clocks->latency[i] = smu7_get_mem_latency(hwmgr, + if (hwmgr->pp_table_version == PP_TABLE_V1) { + if (table_info == NULL) + return -EINVAL; + dep_mclk_table = table_info->vdd_dep_on_mclk; + for (i = 0; i < dep_mclk_table->count; i++) { + clocks->clock[i] = dep_mclk_table->entries[i].clk; + clocks->latency[i] = smu7_get_mem_latency(hwmgr, dep_mclk_table->entries[i].clk); - clocks->count++; + clocks->count++; + } + } else if (hwmgr->pp_table_version == PP_TABLE_V0) { + mclk_table = hwmgr->dyn_state.vddc_dependency_on_mclk; + for (i = 0; i < mclk_table->count; i++) { + clocks->clock[i] = mclk_table->entries[i].clk; + clocks->count++; + } } return 0; } diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c index 41b634ffa5b0..26477f0f09dc 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c @@ -603,9 +603,10 @@ int smu7_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n) return 0; } -static int smu7_set_overdriver_target_tdp(struct pp_hwmgr *pHwMgr, uint32_t target_tdp) +static int smu7_set_overdriver_target_tdp(struct pp_hwmgr *hwmgr, + uint32_t target_tdp) { - return smum_send_msg_to_smc_with_parameter(pHwMgr->smumgr, + return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp); } diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c index fb6c6f6106d5..29d0319b22e6 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c @@ -30,7 +30,7 @@ int smu7_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info) { if (hwmgr->thermal_controller.fanInfo.bNoFan) - return 0; + return -ENODEV; fan_speed_info->supports_percent_read = true; fan_speed_info->supports_percent_write = true; @@ -60,7 +60,7 @@ int smu7_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr, uint64_t tmp64; if (hwmgr->thermal_controller.fanInfo.bNoFan) - return 0; + return -ENODEV; duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL1, FMAX_DUTY100); @@ -89,7 +89,7 @@ int smu7_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed) if (hwmgr->thermal_controller.fanInfo.bNoFan || (hwmgr->thermal_controller.fanInfo. ucTachometerPulsesPerRevolution == 0)) - return 0; + return -ENODEV; tach_period = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_TACH_STATUS, TACH_PERIOD); diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h index eb3e83d7af31..3a883e6c601a 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h +++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h @@ -29,6 +29,8 @@ #include "amd_shared.h" #include "cgs_common.h" +extern int amdgpu_dpm; + enum amd_pp_sensors { AMDGPU_PP_SENSOR_GFX_SCLK = 0, AMDGPU_PP_SENSOR_VDDNB, @@ -349,6 +351,7 @@ struct amd_powerplay_funcs { int (*get_fan_control_mode)(void *handle); int (*set_fan_speed_percent)(void *handle, uint32_t percent); int (*get_fan_speed_percent)(void *handle, uint32_t *speed); + int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm); int (*get_pp_num_states)(void *handle, struct pp_states_info *data); int (*get_pp_table)(void *handle, char **table); int (*set_pp_table)(void *handle, const char *buf, size_t size); diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h index e38b999e3235..6cdb7cbf515e 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h @@ -38,8 +38,6 @@ struct pp_hwmgr; struct phm_fan_speed_info; struct pp_atomctrl_voltage_table; -extern int amdgpu_powercontainment; -extern int amdgpu_sclk_deep_sleep_en; extern unsigned amdgpu_pp_feature_mask; #define VOLTAGE_SCALE 4 @@ -85,7 +83,9 @@ enum PP_FEATURE_MASK { PP_SMC_VOLTAGE_CONTROL_MASK = 0x40, PP_VBI_TIME_SUPPORT_MASK = 0x80, PP_ULV_MASK = 0x100, - PP_ENABLE_GFX_CG_THRU_SMU = 0x200 + PP_ENABLE_GFX_CG_THRU_SMU = 0x200, + PP_CLOCK_STRETCH_MASK = 0x400, + PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800 }; enum PHM_BackEnd_Magic { diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c index b86e48fb40d1..26eff56b4a99 100755 --- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c @@ -396,7 +396,8 @@ static int fiji_start_smu(struct pp_smumgr *smumgr) struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend); /* Only start SMC if SMC RAM is not running */ - if (!smu7_is_smc_ram_running(smumgr)) { + if (!(smu7_is_smc_ram_running(smumgr) + || cgs_is_virtualization_enabled(smumgr->device))) { fiji_avfs_event_mgr(smumgr, false); /* Check if SMU is running in protected mode */ @@ -443,6 +444,9 @@ static bool fiji_is_hw_avfs_present(struct pp_smumgr *smumgr) uint32_t efuse = 0; uint32_t mask = (1 << ((AVFS_EN_MSB - AVFS_EN_LSB) + 1)) - 1; + if (cgs_is_virtualization_enabled(smumgr->device)) + return 0; + if (!atomctrl_read_efuse(smumgr->device, AVFS_EN_LSB, AVFS_EN_MSB, mask, &efuse)) { if (efuse) diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c index 006b22071685..8db8e209d915 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c @@ -2214,6 +2214,7 @@ uint32_t polaris10_get_mac_definition(uint32_t value) int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr) { struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); uint32_t tmp; int result; bool error = false; @@ -2233,8 +2234,10 @@ int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr) offsetof(SMU74_Firmware_Header, SoftRegisters), &tmp, SMC_RAM_END); - if (!result) + if (!result) { + data->soft_regs_start = tmp; smu_data->smu7_data.soft_regs_start = tmp; + } error |= (0 != result); diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c index 5f9124046b9b..eff9a232e72e 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c @@ -140,7 +140,8 @@ static int tonga_start_smu(struct pp_smumgr *smumgr) int result; /* Only start SMC if SMC RAM is not running */ - if (!smu7_is_smc_ram_running(smumgr)) { + if (!(smu7_is_smc_ram_running(smumgr) || + cgs_is_virtualization_enabled(smumgr->device))) { /*Check if SMU is running in protected mode*/ if (0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE)) { diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c index 09b2cf6ccfa4..1bf83ed113b3 100644 --- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c +++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c @@ -34,9 +34,6 @@ static bool amd_sched_entity_is_ready(struct amd_sched_entity *entity); static void amd_sched_wakeup(struct amd_gpu_scheduler *sched); static void amd_sched_process_job(struct dma_fence *f, struct dma_fence_cb *cb); -struct kmem_cache *sched_fence_slab; -atomic_t sched_fence_slab_ref = ATOMIC_INIT(0); - /* Initialize a given run queue struct */ static void amd_sched_rq_init(struct amd_sched_rq *rq) { @@ -619,13 +616,6 @@ int amd_sched_init(struct amd_gpu_scheduler *sched, INIT_LIST_HEAD(&sched->ring_mirror_list); spin_lock_init(&sched->job_list_lock); atomic_set(&sched->hw_rq_count, 0); - if (atomic_inc_return(&sched_fence_slab_ref) == 1) { - sched_fence_slab = kmem_cache_create( - "amd_sched_fence", sizeof(struct amd_sched_fence), 0, - SLAB_HWCACHE_ALIGN, NULL); - if (!sched_fence_slab) - return -ENOMEM; - } /* Each scheduler will run on a seperate kernel thread */ sched->thread = kthread_run(amd_sched_main, sched, sched->name); @@ -646,7 +636,4 @@ void amd_sched_fini(struct amd_gpu_scheduler *sched) { if (sched->thread) kthread_stop(sched->thread); - rcu_barrier(); - if (atomic_dec_and_test(&sched_fence_slab_ref)) - kmem_cache_destroy(sched_fence_slab); } diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h index 876aa43b57df..d8dc681bcda6 100644 --- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h +++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h @@ -30,9 +30,6 @@ struct amd_gpu_scheduler; struct amd_sched_rq; -extern struct kmem_cache *sched_fence_slab; -extern atomic_t sched_fence_slab_ref; - /** * A scheduler entity is a wrapper around a job queue or a group * of other entities. Entities take turns emitting jobs from their @@ -145,6 +142,9 @@ void amd_sched_entity_fini(struct amd_gpu_scheduler *sched, struct amd_sched_entity *entity); void amd_sched_entity_push_job(struct amd_sched_job *sched_job); +int amd_sched_fence_slab_init(void); +void amd_sched_fence_slab_fini(void); + struct amd_sched_fence *amd_sched_fence_create( struct amd_sched_entity *s_entity, void *owner); void amd_sched_fence_scheduled(struct amd_sched_fence *fence); diff --git a/drivers/gpu/drm/amd/scheduler/sched_fence.c b/drivers/gpu/drm/amd/scheduler/sched_fence.c index 91530e25aaff..33f54d0a5c4f 100644 --- a/drivers/gpu/drm/amd/scheduler/sched_fence.c +++ b/drivers/gpu/drm/amd/scheduler/sched_fence.c @@ -27,6 +27,25 @@ #include <drm/drmP.h> #include "gpu_scheduler.h" +static struct kmem_cache *sched_fence_slab; + +int amd_sched_fence_slab_init(void) +{ + sched_fence_slab = kmem_cache_create( + "amd_sched_fence", sizeof(struct amd_sched_fence), 0, + SLAB_HWCACHE_ALIGN, NULL); + if (!sched_fence_slab) + return -ENOMEM; + + return 0; +} + +void amd_sched_fence_slab_fini(void) +{ + rcu_barrier(); + kmem_cache_destroy(sched_fence_slab); +} + struct amd_sched_fence *amd_sched_fence_create(struct amd_sched_entity *entity, void *owner) { diff --git a/drivers/gpu/drm/arc/arcpgu_hdmi.c b/drivers/gpu/drm/arc/arcpgu_hdmi.c index b7a8b2ac4055..b69c66b4897e 100644 --- a/drivers/gpu/drm/arc/arcpgu_hdmi.c +++ b/drivers/gpu/drm/arc/arcpgu_hdmi.c @@ -14,170 +14,45 @@ * */ -#include <drm/drm_crtc_helper.h> +#include <drm/drm_crtc.h> #include <drm/drm_encoder_slave.h> -#include <drm/drm_atomic_helper.h> #include "arcpgu.h" -struct arcpgu_drm_connector { - struct drm_connector connector; - struct drm_encoder_slave *encoder_slave; -}; - -static int arcpgu_drm_connector_get_modes(struct drm_connector *connector) -{ - const struct drm_encoder_slave_funcs *sfuncs; - struct drm_encoder_slave *slave; - struct arcpgu_drm_connector *con = - container_of(connector, struct arcpgu_drm_connector, connector); - - slave = con->encoder_slave; - if (slave == NULL) { - dev_err(connector->dev->dev, - "connector_get_modes: cannot find slave encoder for connector\n"); - return 0; - } - - sfuncs = slave->slave_funcs; - if (sfuncs->get_modes == NULL) - return 0; - - return sfuncs->get_modes(&slave->base, connector); -} - -static enum drm_connector_status -arcpgu_drm_connector_detect(struct drm_connector *connector, bool force) -{ - enum drm_connector_status status = connector_status_unknown; - const struct drm_encoder_slave_funcs *sfuncs; - struct drm_encoder_slave *slave; - - struct arcpgu_drm_connector *con = - container_of(connector, struct arcpgu_drm_connector, connector); - - slave = con->encoder_slave; - if (slave == NULL) { - dev_err(connector->dev->dev, - "connector_detect: cannot find slave encoder for connector\n"); - return status; - } - - sfuncs = slave->slave_funcs; - if (sfuncs && sfuncs->detect) - return sfuncs->detect(&slave->base, connector); - - dev_err(connector->dev->dev, "connector_detect: could not detect slave funcs\n"); - return status; -} - -static void arcpgu_drm_connector_destroy(struct drm_connector *connector) -{ - drm_connector_unregister(connector); - drm_connector_cleanup(connector); -} - -static const struct drm_connector_helper_funcs -arcpgu_drm_connector_helper_funcs = { - .get_modes = arcpgu_drm_connector_get_modes, -}; - -static const struct drm_connector_funcs arcpgu_drm_connector_funcs = { - .dpms = drm_helper_connector_dpms, - .reset = drm_atomic_helper_connector_reset, - .detect = arcpgu_drm_connector_detect, - .fill_modes = drm_helper_probe_single_connector_modes, - .destroy = arcpgu_drm_connector_destroy, - .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, - .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, -}; - -static struct drm_encoder_helper_funcs arcpgu_drm_encoder_helper_funcs = { - .dpms = drm_i2c_encoder_dpms, - .mode_fixup = drm_i2c_encoder_mode_fixup, - .mode_set = drm_i2c_encoder_mode_set, - .prepare = drm_i2c_encoder_prepare, - .commit = drm_i2c_encoder_commit, - .detect = drm_i2c_encoder_detect, -}; - static struct drm_encoder_funcs arcpgu_drm_encoder_funcs = { .destroy = drm_encoder_cleanup, }; int arcpgu_drm_hdmi_init(struct drm_device *drm, struct device_node *np) { - struct arcpgu_drm_connector *arcpgu_connector; - struct drm_i2c_encoder_driver *driver; - struct drm_encoder_slave *encoder; - struct drm_connector *connector; - struct i2c_client *i2c_slave; - int ret; + struct drm_encoder *encoder; + struct drm_bridge *bridge; + + int ret = 0; encoder = devm_kzalloc(drm->dev, sizeof(*encoder), GFP_KERNEL); if (encoder == NULL) return -ENOMEM; - i2c_slave = of_find_i2c_device_by_node(np); - if (!i2c_slave || !i2c_get_clientdata(i2c_slave)) { - dev_err(drm->dev, "failed to find i2c slave encoder\n"); - return -EPROBE_DEFER; - } - - if (i2c_slave->dev.driver == NULL) { - dev_err(drm->dev, "failed to find i2c slave driver\n"); + /* Locate drm bridge from the hdmi encoder DT node */ + bridge = of_drm_find_bridge(np); + if (!bridge) return -EPROBE_DEFER; - } - driver = - to_drm_i2c_encoder_driver(to_i2c_driver(i2c_slave->dev.driver)); - ret = driver->encoder_init(i2c_slave, drm, encoder); - if (ret) { - dev_err(drm->dev, "failed to initialize i2c encoder slave\n"); - return ret; - } - - encoder->base.possible_crtcs = 1; - encoder->base.possible_clones = 0; - ret = drm_encoder_init(drm, &encoder->base, &arcpgu_drm_encoder_funcs, + encoder->possible_crtcs = 1; + encoder->possible_clones = 0; + ret = drm_encoder_init(drm, encoder, &arcpgu_drm_encoder_funcs, DRM_MODE_ENCODER_TMDS, NULL); if (ret) return ret; - drm_encoder_helper_add(&encoder->base, - &arcpgu_drm_encoder_helper_funcs); - - arcpgu_connector = devm_kzalloc(drm->dev, sizeof(*arcpgu_connector), - GFP_KERNEL); - if (!arcpgu_connector) { - ret = -ENOMEM; - goto error_encoder_cleanup; - } - - connector = &arcpgu_connector->connector; - drm_connector_helper_add(connector, &arcpgu_drm_connector_helper_funcs); - ret = drm_connector_init(drm, connector, &arcpgu_drm_connector_funcs, - DRM_MODE_CONNECTOR_HDMIA); - if (ret < 0) { - dev_err(drm->dev, "failed to initialize drm connector\n"); - goto error_encoder_cleanup; - } + /* Link drm_bridge to encoder */ + bridge->encoder = encoder; + encoder->bridge = bridge; - ret = drm_mode_connector_attach_encoder(connector, &encoder->base); - if (ret < 0) { - dev_err(drm->dev, "could not attach connector to encoder\n"); - drm_connector_unregister(connector); - goto error_connector_cleanup; - } - - arcpgu_connector->encoder_slave = encoder; - - return 0; - -error_connector_cleanup: - drm_connector_cleanup(connector); + ret = drm_bridge_attach(drm, bridge); + if (ret) + drm_encoder_cleanup(encoder); -error_encoder_cleanup: - drm_encoder_cleanup(&encoder->base); return ret; } diff --git a/drivers/gpu/drm/arm/hdlcd_crtc.c b/drivers/gpu/drm/arm/hdlcd_crtc.c index bbaa55add2d2..7d4e5aa77195 100644 --- a/drivers/gpu/drm/arm/hdlcd_crtc.c +++ b/drivers/gpu/drm/arm/hdlcd_crtc.c @@ -150,15 +150,14 @@ static void hdlcd_crtc_enable(struct drm_crtc *crtc) clk_prepare_enable(hdlcd->clk); hdlcd_crtc_mode_set_nofb(crtc); hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 1); + drm_crtc_vblank_on(crtc); } static void hdlcd_crtc_disable(struct drm_crtc *crtc) { struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); - if (!crtc->state->active) - return; - + drm_crtc_vblank_off(crtc); hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0); clk_disable_unprepare(hdlcd->clk); } diff --git a/drivers/gpu/drm/arm/hdlcd_drv.c b/drivers/gpu/drm/arm/hdlcd_drv.c index faab7f9bd3b7..e5f4f4a6546d 100644 --- a/drivers/gpu/drm/arm/hdlcd_drv.c +++ b/drivers/gpu/drm/arm/hdlcd_drv.c @@ -378,7 +378,6 @@ err_register: } err_fbdev: drm_kms_helper_poll_fini(drm); - drm_mode_config_cleanup(drm); drm_vblank_cleanup(drm); err_vblank: pm_runtime_disable(drm->dev); @@ -388,6 +387,7 @@ err_unload: drm_irq_uninstall(drm); of_reserved_mem_device_release(drm->dev); err_free: + drm_mode_config_cleanup(drm); dev_set_drvdata(dev, NULL); drm_dev_unref(drm); diff --git a/drivers/gpu/drm/armada/Makefile b/drivers/gpu/drm/armada/Makefile index ffd673615772..a18f156c8b66 100644 --- a/drivers/gpu/drm/armada/Makefile +++ b/drivers/gpu/drm/armada/Makefile @@ -1,5 +1,5 @@ armada-y := armada_crtc.o armada_drv.o armada_fb.o armada_fbdev.o \ - armada_gem.o armada_overlay.o + armada_gem.o armada_overlay.o armada_trace.o armada-y += armada_510.o armada-$(CONFIG_DEBUG_FS) += armada_debugfs.o diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armada/armada_crtc.c index a51f8cbcfe26..95cb3966b2ca 100644 --- a/drivers/gpu/drm/armada/armada_crtc.c +++ b/drivers/gpu/drm/armada/armada_crtc.c @@ -18,6 +18,7 @@ #include "armada_fb.h" #include "armada_gem.h" #include "armada_hw.h" +#include "armada_trace.h" struct armada_frame_work { struct armada_plane_work work; @@ -164,19 +165,37 @@ static void armada_drm_crtc_update(struct armada_crtc *dcrtc) } } +void armada_drm_plane_calc_addrs(u32 *addrs, struct drm_framebuffer *fb, + int x, int y) +{ + u32 addr = drm_fb_obj(fb)->dev_addr; + u32 pixel_format = fb->pixel_format; + int num_planes = drm_format_num_planes(pixel_format); + int i; + + if (num_planes > 3) + num_planes = 3; + + for (i = 0; i < num_planes; i++) + addrs[i] = addr + fb->offsets[i] + y * fb->pitches[i] + + x * drm_format_plane_cpp(pixel_format, i); + for (; i < 3; i++) + addrs[i] = 0; +} + static unsigned armada_drm_crtc_calc_fb(struct drm_framebuffer *fb, int x, int y, struct armada_regs *regs, bool interlaced) { - struct armada_gem_object *obj = drm_fb_obj(fb); unsigned pitch = fb->pitches[0]; - unsigned offset = y * pitch + x * fb->bits_per_pixel / 8; - uint32_t addr_odd, addr_even; + u32 addrs[3], addr_odd, addr_even; unsigned i = 0; DRM_DEBUG_DRIVER("pitch %u x %d y %d bpp %d\n", pitch, x, y, fb->bits_per_pixel); - addr_odd = addr_even = obj->dev_addr + offset; + armada_drm_plane_calc_addrs(addrs, fb, x, y); + + addr_odd = addr_even = addrs[0]; if (interlaced) { addr_even += pitch; @@ -192,17 +211,18 @@ static unsigned armada_drm_crtc_calc_fb(struct drm_framebuffer *fb, } static void armada_drm_plane_work_run(struct armada_crtc *dcrtc, - struct armada_plane *plane) + struct drm_plane *plane) { - struct armada_plane_work *work = xchg(&plane->work, NULL); + struct armada_plane *dplane = drm_to_armada_plane(plane); + struct armada_plane_work *work = xchg(&dplane->work, NULL); /* Handle any pending frame work. */ if (work) { - work->fn(dcrtc, plane, work); + work->fn(dcrtc, dplane, work); drm_crtc_vblank_put(&dcrtc->crtc); } - wake_up(&plane->frame_wait); + wake_up(&dplane->frame_wait); } int armada_drm_plane_work_queue(struct armada_crtc *dcrtc, @@ -307,14 +327,12 @@ static void armada_drm_crtc_finish_fb(struct armada_crtc *dcrtc, static void armada_drm_vblank_off(struct armada_crtc *dcrtc) { - struct armada_plane *plane = drm_to_armada_plane(dcrtc->crtc.primary); - /* * Tell the DRM core that vblank IRQs aren't going to happen for * a while. This cleans up any pending vblank events for us. */ drm_crtc_vblank_off(&dcrtc->crtc); - armada_drm_plane_work_run(dcrtc, plane); + armada_drm_plane_work_run(dcrtc, dcrtc->crtc.primary); } void armada_drm_crtc_gamma_set(struct drm_crtc *crtc, u16 r, u16 g, u16 b, @@ -416,10 +434,8 @@ static void armada_drm_crtc_irq(struct armada_crtc *dcrtc, u32 stat) spin_lock(&dcrtc->irq_lock); ovl_plane = dcrtc->plane; - if (ovl_plane) { - struct armada_plane *plane = drm_to_armada_plane(ovl_plane); - armada_drm_plane_work_run(dcrtc, plane); - } + if (ovl_plane) + armada_drm_plane_work_run(dcrtc, ovl_plane); if (stat & GRA_FRAME_IRQ && dcrtc->interlaced) { int i = stat & GRA_FRAME_IRQ0 ? 0 : 1; @@ -449,10 +465,8 @@ static void armada_drm_crtc_irq(struct armada_crtc *dcrtc, u32 stat) spin_unlock(&dcrtc->irq_lock); - if (stat & GRA_FRAME_IRQ) { - struct armada_plane *plane = drm_to_armada_plane(dcrtc->crtc.primary); - armada_drm_plane_work_run(dcrtc, plane); - } + if (stat & GRA_FRAME_IRQ) + armada_drm_plane_work_run(dcrtc, dcrtc->crtc.primary); } static irqreturn_t armada_drm_irq(int irq, void *arg) @@ -466,6 +480,8 @@ static irqreturn_t armada_drm_irq(int irq, void *arg) */ writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR); + trace_armada_drm_irq(&dcrtc->crtc, stat); + /* Mask out those interrupts we haven't enabled */ v = stat & dcrtc->irq_ena; @@ -531,6 +547,35 @@ static uint32_t armada_drm_crtc_calculate_csc(struct armada_crtc *dcrtc) return val; } +static void armada_drm_primary_set(struct drm_crtc *crtc, + struct drm_plane *plane, int x, int y) +{ + struct armada_plane_state *state = &drm_to_armada_plane(plane)->state; + struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); + struct armada_regs regs[8]; + bool interlaced = dcrtc->interlaced; + unsigned i; + u32 ctrl0; + + i = armada_drm_crtc_calc_fb(plane->fb, x, y, regs, interlaced); + + armada_reg_queue_set(regs, i, state->dst_yx, LCD_SPU_GRA_OVSA_HPXL_VLN); + armada_reg_queue_set(regs, i, state->src_hw, LCD_SPU_GRA_HPXL_VLN); + armada_reg_queue_set(regs, i, state->dst_hw, LCD_SPU_GZM_HPXL_VLN); + + ctrl0 = state->ctrl0; + if (interlaced) + ctrl0 |= CFG_GRA_FTOGGLE; + + armada_reg_queue_mod(regs, i, ctrl0, CFG_GRAFORMAT | + CFG_GRA_MOD(CFG_SWAPRB | CFG_SWAPUV | + CFG_SWAPYU | CFG_YUV2RGB) | + CFG_PALETTE_ENA | CFG_GRA_FTOGGLE, + LCD_SPU_DMA_CTRL0); + armada_reg_queue_end(regs, i); + armada_drm_crtc_update_regs(dcrtc, regs); +} + /* The mode_config.mutex will be held for this call */ static int armada_drm_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode, struct drm_display_mode *adj, @@ -547,9 +592,20 @@ static int armada_drm_crtc_mode_set(struct drm_crtc *crtc, interlaced = !!(adj->flags & DRM_MODE_FLAG_INTERLACE); - i = armada_drm_crtc_calc_fb(dcrtc->crtc.primary->fb, - x, y, regs, interlaced); + val = CFG_GRA_ENA | CFG_GRA_HSMOOTH; + val |= CFG_GRA_FMT(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt); + val |= CFG_GRA_MOD(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->mod); + + if (drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt > CFG_420) + val |= CFG_PALETTE_ENA; + + drm_to_armada_plane(crtc->primary)->state.ctrl0 = val; + drm_to_armada_plane(crtc->primary)->state.src_hw = + drm_to_armada_plane(crtc->primary)->state.dst_hw = + adj->crtc_vdisplay << 16 | adj->crtc_hdisplay; + drm_to_armada_plane(crtc->primary)->state.dst_yx = 0; + i = 0; rm = adj->crtc_hsync_start - adj->crtc_hdisplay; lm = adj->crtc_htotal - adj->crtc_hsync_end; bm = adj->crtc_vsync_start - adj->crtc_vdisplay; @@ -625,8 +681,6 @@ static int armada_drm_crtc_mode_set(struct drm_crtc *crtc, val = adj->crtc_vdisplay << 16 | adj->crtc_hdisplay; armada_reg_queue_set(regs, i, val, LCD_SPU_V_H_ACTIVE); - armada_reg_queue_set(regs, i, val, LCD_SPU_GRA_HPXL_VLN); - armada_reg_queue_set(regs, i, val, LCD_SPU_GZM_HPXL_VLN); armada_reg_queue_set(regs, i, (lm << 16) | rm, LCD_SPU_H_PORCH); armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_porch, LCD_SPU_V_PORCH); armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total, @@ -638,22 +692,6 @@ static int armada_drm_crtc_mode_set(struct drm_crtc *crtc, ADV_VSYNCOFFEN, LCD_SPU_ADV_REG); } - val = CFG_GRA_ENA | CFG_GRA_HSMOOTH; - val |= CFG_GRA_FMT(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt); - val |= CFG_GRA_MOD(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->mod); - - if (drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt > CFG_420) - val |= CFG_PALETTE_ENA; - - if (interlaced) - val |= CFG_GRA_FTOGGLE; - - armada_reg_queue_mod(regs, i, val, CFG_GRAFORMAT | - CFG_GRA_MOD(CFG_SWAPRB | CFG_SWAPUV | - CFG_SWAPYU | CFG_YUV2RGB) | - CFG_PALETTE_ENA | CFG_GRA_FTOGGLE, - LCD_SPU_DMA_CTRL0); - val = adj->flags & DRM_MODE_FLAG_NVSYNC ? CFG_VSYNC_INV : 0; armada_reg_queue_mod(regs, i, val, CFG_VSYNC_INV, LCD_SPU_DMA_CTRL1); @@ -662,6 +700,8 @@ static int armada_drm_crtc_mode_set(struct drm_crtc *crtc, armada_reg_queue_end(regs, i); armada_drm_crtc_update_regs(dcrtc, regs); + + armada_drm_primary_set(crtc, crtc->primary, x, y); spin_unlock_irqrestore(&dcrtc->irq_lock, flags); armada_drm_crtc_update(dcrtc); @@ -1038,7 +1078,7 @@ static int armada_drm_crtc_page_flip(struct drm_crtc *crtc, * interrupt, so complete it now. */ if (dpms_blanked(dcrtc->dpms)) - armada_drm_plane_work_run(dcrtc, drm_to_armada_plane(dcrtc->crtc.primary)); + armada_drm_plane_work_run(dcrtc, dcrtc->crtc.primary); return 0; } @@ -1172,7 +1212,6 @@ static int armada_drm_crtc_create(struct drm_device *drm, struct device *dev, CFG_PDWN32x32 | CFG_PDWN16x66 | CFG_PDWN32x66 | CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1); writel_relaxed(0x2032ff81, dcrtc->base + LCD_SPU_DMA_CTRL1); - writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_GRA_OVSA_HPXL_VLN); writel_relaxed(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA); writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR); diff --git a/drivers/gpu/drm/armada/armada_crtc.h b/drivers/gpu/drm/armada/armada_crtc.h index 04fdd22d483b..b08043e8cc3b 100644 --- a/drivers/gpu/drm/armada/armada_crtc.h +++ b/drivers/gpu/drm/armada/armada_crtc.h @@ -41,10 +41,18 @@ struct armada_plane_work { struct armada_plane_work *); }; +struct armada_plane_state { + u32 src_hw; + u32 dst_hw; + u32 dst_yx; + u32 ctrl0; +}; + struct armada_plane { struct drm_plane base; wait_queue_head_t frame_wait; struct armada_plane_work *work; + struct armada_plane_state state; }; #define drm_to_armada_plane(p) container_of(p, struct armada_plane, base) @@ -54,6 +62,8 @@ int armada_drm_plane_work_queue(struct armada_crtc *dcrtc, int armada_drm_plane_work_wait(struct armada_plane *plane, long timeout); struct armada_plane_work *armada_drm_plane_work_cancel( struct armada_crtc *dcrtc, struct armada_plane *plane); +void armada_drm_plane_calc_addrs(u32 *addrs, struct drm_framebuffer *fb, + int x, int y); struct armada_crtc { struct drm_crtc crtc; diff --git a/drivers/gpu/drm/armada/armada_debugfs.c b/drivers/gpu/drm/armada/armada_debugfs.c index d4f7ab0a30d4..90222e60d2d6 100644 --- a/drivers/gpu/drm/armada/armada_debugfs.c +++ b/drivers/gpu/drm/armada/armada_debugfs.c @@ -113,7 +113,7 @@ static int drm_add_fake_info_node(struct drm_minor *minor, struct dentry *ent, struct drm_info_node *node; node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL); - if (node == NULL) { + if (!node) { debugfs_remove(ent); return -ENOMEM; } diff --git a/drivers/gpu/drm/armada/armada_drm.h b/drivers/gpu/drm/armada/armada_drm.h index 3b2bb6128d40..77952d559a3c 100644 --- a/drivers/gpu/drm/armada/armada_drm.h +++ b/drivers/gpu/drm/armada/armada_drm.h @@ -53,6 +53,7 @@ struct armada_variant { extern const struct armada_variant armada510_ops; struct armada_private { + struct drm_device drm; struct work_struct fb_unref_work; DECLARE_KFIFO(fb_unref, struct drm_framebuffer *, 8); struct drm_fb_helper *fbdev; diff --git a/drivers/gpu/drm/armada/armada_drv.c b/drivers/gpu/drm/armada/armada_drv.c index 94e46da9a758..07086b427c22 100644 --- a/drivers/gpu/drm/armada/armada_drv.c +++ b/drivers/gpu/drm/armada/armada_drv.c @@ -49,106 +49,6 @@ void armada_drm_queue_unref_work(struct drm_device *dev, spin_unlock_irqrestore(&dev->event_lock, flags); } -static int armada_drm_load(struct drm_device *dev, unsigned long flags) -{ - struct armada_private *priv; - struct resource *mem = NULL; - int ret, n; - - for (n = 0; ; n++) { - struct resource *r = platform_get_resource(dev->platformdev, - IORESOURCE_MEM, n); - if (!r) - break; - - /* Resources above 64K are graphics memory */ - if (resource_size(r) > SZ_64K) - mem = r; - else - return -EINVAL; - } - - if (!mem) - return -ENXIO; - - if (!devm_request_mem_region(dev->dev, mem->start, - resource_size(mem), "armada-drm")) - return -EBUSY; - - priv = devm_kzalloc(dev->dev, sizeof(*priv), GFP_KERNEL); - if (!priv) { - DRM_ERROR("failed to allocate private\n"); - return -ENOMEM; - } - - platform_set_drvdata(dev->platformdev, dev); - dev->dev_private = priv; - - INIT_WORK(&priv->fb_unref_work, armada_drm_unref_work); - INIT_KFIFO(priv->fb_unref); - - /* Mode setting support */ - drm_mode_config_init(dev); - dev->mode_config.min_width = 320; - dev->mode_config.min_height = 200; - - /* - * With vscale enabled, the maximum width is 1920 due to the - * 1920 by 3 lines RAM - */ - dev->mode_config.max_width = 1920; - dev->mode_config.max_height = 2048; - - dev->mode_config.preferred_depth = 24; - dev->mode_config.funcs = &armada_drm_mode_config_funcs; - drm_mm_init(&priv->linear, mem->start, resource_size(mem)); - mutex_init(&priv->linear_lock); - - ret = component_bind_all(dev->dev, dev); - if (ret) - goto err_kms; - - ret = drm_vblank_init(dev, dev->mode_config.num_crtc); - if (ret) - goto err_comp; - - dev->irq_enabled = true; - - ret = armada_fbdev_init(dev); - if (ret) - goto err_comp; - - drm_kms_helper_poll_init(dev); - - return 0; - - err_comp: - component_unbind_all(dev->dev, dev); - err_kms: - drm_mode_config_cleanup(dev); - drm_mm_takedown(&priv->linear); - flush_work(&priv->fb_unref_work); - - return ret; -} - -static int armada_drm_unload(struct drm_device *dev) -{ - struct armada_private *priv = dev->dev_private; - - drm_kms_helper_poll_fini(dev); - armada_fbdev_fini(dev); - - component_unbind_all(dev->dev, dev); - - drm_mode_config_cleanup(dev); - drm_mm_takedown(&priv->linear); - flush_work(&priv->fb_unref_work); - dev->dev_private = NULL; - - return 0; -} - /* These are called under the vbl_lock. */ static int armada_drm_enable_vblank(struct drm_device *dev, unsigned int pipe) { @@ -186,16 +86,10 @@ static const struct file_operations armada_drm_fops = { }; static struct drm_driver armada_drm_driver = { - .load = armada_drm_load, .lastclose = armada_drm_lastclose, - .unload = armada_drm_unload, .get_vblank_counter = drm_vblank_no_hw_counter, .enable_vblank = armada_drm_enable_vblank, .disable_vblank = armada_drm_disable_vblank, -#ifdef CONFIG_DEBUG_FS - .debugfs_init = armada_drm_debugfs_init, - .debugfs_cleanup = armada_drm_debugfs_cleanup, -#endif .gem_free_object_unlocked = armada_gem_free_object, .prime_handle_to_fd = drm_gem_prime_handle_to_fd, .prime_fd_to_handle = drm_gem_prime_fd_to_handle, @@ -218,12 +112,138 @@ static struct drm_driver armada_drm_driver = { static int armada_drm_bind(struct device *dev) { - return drm_platform_init(&armada_drm_driver, to_platform_device(dev)); + struct armada_private *priv; + struct resource *mem = NULL; + int ret, n; + + for (n = 0; ; n++) { + struct resource *r = platform_get_resource(to_platform_device(dev), + IORESOURCE_MEM, n); + if (!r) + break; + + /* Resources above 64K are graphics memory */ + if (resource_size(r) > SZ_64K) + mem = r; + else + return -EINVAL; + } + + if (!mem) + return -ENXIO; + + if (!devm_request_mem_region(dev, mem->start, resource_size(mem), + "armada-drm")) + return -EBUSY; + + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + /* + * The drm_device structure must be at the start of + * armada_private for drm_dev_unref() to work correctly. + */ + BUILD_BUG_ON(offsetof(struct armada_private, drm) != 0); + + ret = drm_dev_init(&priv->drm, &armada_drm_driver, dev); + if (ret) { + dev_err(dev, "[" DRM_NAME ":%s] drm_dev_init failed: %d\n", + __func__, ret); + kfree(priv); + return ret; + } + + priv->drm.platformdev = to_platform_device(dev); + priv->drm.dev_private = priv; + + platform_set_drvdata(priv->drm.platformdev, &priv->drm); + + INIT_WORK(&priv->fb_unref_work, armada_drm_unref_work); + INIT_KFIFO(priv->fb_unref); + + /* Mode setting support */ + drm_mode_config_init(&priv->drm); + priv->drm.mode_config.min_width = 320; + priv->drm.mode_config.min_height = 200; + + /* + * With vscale enabled, the maximum width is 1920 due to the + * 1920 by 3 lines RAM + */ + priv->drm.mode_config.max_width = 1920; + priv->drm.mode_config.max_height = 2048; + + priv->drm.mode_config.preferred_depth = 24; + priv->drm.mode_config.funcs = &armada_drm_mode_config_funcs; + drm_mm_init(&priv->linear, mem->start, resource_size(mem)); + mutex_init(&priv->linear_lock); + + ret = component_bind_all(dev, &priv->drm); + if (ret) + goto err_kms; + + ret = drm_vblank_init(&priv->drm, priv->drm.mode_config.num_crtc); + if (ret) + goto err_comp; + + priv->drm.irq_enabled = true; + + ret = armada_fbdev_init(&priv->drm); + if (ret) + goto err_comp; + + drm_kms_helper_poll_init(&priv->drm); + + ret = drm_dev_register(&priv->drm, 0); + if (ret) + goto err_poll; + +#ifdef CONFIG_DEBUG_FS + armada_drm_debugfs_init(priv->drm.primary); +#endif + + DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n", + armada_drm_driver.name, armada_drm_driver.major, + armada_drm_driver.minor, armada_drm_driver.patchlevel, + armada_drm_driver.date, dev_name(dev), + priv->drm.primary->index); + + return 0; + + err_poll: + drm_kms_helper_poll_fini(&priv->drm); + armada_fbdev_fini(&priv->drm); + err_comp: + component_unbind_all(dev, &priv->drm); + err_kms: + drm_mode_config_cleanup(&priv->drm); + drm_mm_takedown(&priv->linear); + flush_work(&priv->fb_unref_work); + drm_dev_unref(&priv->drm); + return ret; } static void armada_drm_unbind(struct device *dev) { - drm_put_dev(dev_get_drvdata(dev)); + struct drm_device *drm = dev_get_drvdata(dev); + struct armada_private *priv = drm->dev_private; + + drm_kms_helper_poll_fini(&priv->drm); + armada_fbdev_fini(&priv->drm); + +#ifdef CONFIG_DEBUG_FS + armada_drm_debugfs_cleanup(priv->drm.primary); +#endif + drm_dev_unregister(&priv->drm); + + component_unbind_all(dev, &priv->drm); + + drm_mode_config_cleanup(&priv->drm); + drm_mm_takedown(&priv->linear); + flush_work(&priv->fb_unref_work); + + drm_dev_unref(&priv->drm); } static int compare_of(struct device *dev, void *data) diff --git a/drivers/gpu/drm/armada/armada_gem.c b/drivers/gpu/drm/armada/armada_gem.c index 806791897304..768087ddb046 100644 --- a/drivers/gpu/drm/armada/armada_gem.c +++ b/drivers/gpu/drm/armada/armada_gem.c @@ -212,7 +212,7 @@ armada_gem_alloc_private_object(struct drm_device *dev, size_t size) return obj; } -struct armada_gem_object *armada_gem_alloc_object(struct drm_device *dev, +static struct armada_gem_object *armada_gem_alloc_object(struct drm_device *dev, size_t size) { struct armada_gem_object *obj; @@ -419,7 +419,7 @@ int armada_gem_pwrite_ioctl(struct drm_device *dev, void *data, } /* Prime support */ -struct sg_table * +static struct sg_table * armada_gem_prime_map_dma_buf(struct dma_buf_attachment *attach, enum dma_data_direction dir) { @@ -594,11 +594,7 @@ int armada_gem_map_import(struct armada_gem_object *dobj) int ret; dobj->sgt = dma_buf_map_attachment(dobj->obj.import_attach, - DMA_TO_DEVICE); - if (!dobj->sgt) { - DRM_ERROR("dma_buf_map_attachment() returned NULL\n"); - return -EINVAL; - } + DMA_TO_DEVICE); if (IS_ERR(dobj->sgt)) { ret = PTR_ERR(dobj->sgt); dobj->sgt = NULL; diff --git a/drivers/gpu/drm/armada/armada_overlay.c b/drivers/gpu/drm/armada/armada_overlay.c index 152b4e716269..6743615232f5 100644 --- a/drivers/gpu/drm/armada/armada_overlay.c +++ b/drivers/gpu/drm/armada/armada_overlay.c @@ -15,6 +15,7 @@ #include "armada_hw.h" #include <drm/armada_drm.h> #include "armada_ioctlP.h" +#include "armada_trace.h" struct armada_ovl_plane_properties { uint32_t colorkey_yr; @@ -32,10 +33,6 @@ struct armada_ovl_plane_properties { struct armada_ovl_plane { struct armada_plane base; struct drm_framebuffer *old_fb; - uint32_t src_hw; - uint32_t dst_hw; - uint32_t dst_yx; - uint32_t ctrl0; struct { struct armada_plane_work work; struct armada_regs regs[13]; @@ -87,6 +84,8 @@ static void armada_ovl_plane_work(struct armada_crtc *dcrtc, { struct armada_ovl_plane *dplane = container_of(plane, struct armada_ovl_plane, base); + trace_armada_ovl_plane_work(&dcrtc->crtc, &plane->base); + armada_drm_crtc_update_regs(dcrtc, dplane->vbl.regs); armada_ovl_retire_fb(dplane, NULL); } @@ -120,6 +119,10 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, bool visible; int ret; + trace_armada_ovl_plane_update(plane, crtc, fb, + crtc_x, crtc_y, crtc_w, crtc_h, + src_x, src_y, src_w, src_h); + ret = drm_plane_helper_check_update(plane, crtc, fb, &src, &dest, &clip, DRM_ROTATE_0, 0, INT_MAX, true, false, &visible); @@ -141,22 +144,22 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, /* FIXME: overlay on an interlaced display */ /* Just updating the position/size? */ - if (plane->fb == fb && dplane->ctrl0 == ctrl0) { + if (plane->fb == fb && dplane->base.state.ctrl0 == ctrl0) { val = (drm_rect_height(&src) & 0xffff0000) | drm_rect_width(&src) >> 16; - dplane->src_hw = val; + dplane->base.state.src_hw = val; writel_relaxed(val, dcrtc->base + LCD_SPU_DMA_HPXL_VLN); val = drm_rect_height(&dest) << 16 | drm_rect_width(&dest); - dplane->dst_hw = val; + dplane->base.state.dst_hw = val; writel_relaxed(val, dcrtc->base + LCD_SPU_DZM_HPXL_VLN); val = dest.y1 << 16 | dest.x1; - dplane->dst_yx = val; + dplane->base.state.dst_yx = val; writel_relaxed(val, dcrtc->base + LCD_SPU_DMA_OVSA_HPXL_VLN); return 0; - } else if (~dplane->ctrl0 & ctrl0 & CFG_DMA_ENA) { + } else if (~dplane->base.state.ctrl0 & ctrl0 & CFG_DMA_ENA) { /* Power up the Y/U/V FIFOs on ENA 0->1 transitions */ armada_updatel(0, CFG_PDWN16x66 | CFG_PDWN32x66, dcrtc->base + LCD_SPU_SRAM_PARA1); @@ -166,9 +169,8 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, armada_drm_plane_work_cancel(dcrtc, &dplane->base); if (plane->fb != fb) { - struct armada_gem_object *obj = drm_fb_obj(fb); - uint32_t addr[3], pixel_format; - int i, num_planes, hsub; + u32 addrs[3], pixel_format; + int num_planes, hsub; /* * Take a reference on the new framebuffer - we want to @@ -182,6 +184,8 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, src_y = src.y1 >> 16; src_x = src.x1 >> 16; + armada_drm_plane_calc_addrs(addrs, fb, src_x, src_y); + pixel_format = fb->pixel_format; hsub = drm_format_horz_chroma_subsampling(pixel_format); num_planes = drm_format_num_planes(pixel_format); @@ -194,24 +198,17 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, if (src_x & (hsub - 1) && num_planes == 1) ctrl0 ^= CFG_DMA_MOD(CFG_SWAPUV); - for (i = 0; i < num_planes; i++) - addr[i] = obj->dev_addr + fb->offsets[i] + - src_y * fb->pitches[i] + - src_x * drm_format_plane_cpp(pixel_format, i); - for (; i < ARRAY_SIZE(addr); i++) - addr[i] = 0; - - armada_reg_queue_set(dplane->vbl.regs, idx, addr[0], + armada_reg_queue_set(dplane->vbl.regs, idx, addrs[0], LCD_SPU_DMA_START_ADDR_Y0); - armada_reg_queue_set(dplane->vbl.regs, idx, addr[1], + armada_reg_queue_set(dplane->vbl.regs, idx, addrs[1], LCD_SPU_DMA_START_ADDR_U0); - armada_reg_queue_set(dplane->vbl.regs, idx, addr[2], + armada_reg_queue_set(dplane->vbl.regs, idx, addrs[2], LCD_SPU_DMA_START_ADDR_V0); - armada_reg_queue_set(dplane->vbl.regs, idx, addr[0], + armada_reg_queue_set(dplane->vbl.regs, idx, addrs[0], LCD_SPU_DMA_START_ADDR_Y1); - armada_reg_queue_set(dplane->vbl.regs, idx, addr[1], + armada_reg_queue_set(dplane->vbl.regs, idx, addrs[1], LCD_SPU_DMA_START_ADDR_U1); - armada_reg_queue_set(dplane->vbl.regs, idx, addr[2], + armada_reg_queue_set(dplane->vbl.regs, idx, addrs[2], LCD_SPU_DMA_START_ADDR_V1); val = fb->pitches[0] << 16 | fb->pitches[0]; @@ -223,28 +220,28 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, } val = (drm_rect_height(&src) & 0xffff0000) | drm_rect_width(&src) >> 16; - if (dplane->src_hw != val) { - dplane->src_hw = val; + if (dplane->base.state.src_hw != val) { + dplane->base.state.src_hw = val; armada_reg_queue_set(dplane->vbl.regs, idx, val, LCD_SPU_DMA_HPXL_VLN); } val = drm_rect_height(&dest) << 16 | drm_rect_width(&dest); - if (dplane->dst_hw != val) { - dplane->dst_hw = val; + if (dplane->base.state.dst_hw != val) { + dplane->base.state.dst_hw = val; armada_reg_queue_set(dplane->vbl.regs, idx, val, LCD_SPU_DZM_HPXL_VLN); } val = dest.y1 << 16 | dest.x1; - if (dplane->dst_yx != val) { - dplane->dst_yx = val; + if (dplane->base.state.dst_yx != val) { + dplane->base.state.dst_yx = val; armada_reg_queue_set(dplane->vbl.regs, idx, val, LCD_SPU_DMA_OVSA_HPXL_VLN); } - if (dplane->ctrl0 != ctrl0) { - dplane->ctrl0 = ctrl0; + if (dplane->base.state.ctrl0 != ctrl0) { + dplane->base.state.ctrl0 = ctrl0; armada_reg_queue_mod(dplane->vbl.regs, idx, ctrl0, CFG_CBSH_ENA | CFG_DMAFORMAT | CFG_DMA_FTOGGLE | CFG_DMA_HSMOOTH | CFG_DMA_TSTMODE | @@ -275,7 +272,7 @@ static int armada_ovl_plane_disable(struct drm_plane *plane) armada_drm_crtc_plane_disable(dcrtc, plane); dcrtc->plane = NULL; - dplane->ctrl0 = 0; + dplane->base.state.ctrl0 = 0; fb = xchg(&dplane->old_fb, NULL); if (fb) diff --git a/drivers/gpu/drm/armada/armada_trace.c b/drivers/gpu/drm/armada/armada_trace.c new file mode 100644 index 000000000000..068b336ba75f --- /dev/null +++ b/drivers/gpu/drm/armada/armada_trace.c @@ -0,0 +1,4 @@ +#ifndef __CHECKER__ +#define CREATE_TRACE_POINTS +#include "armada_trace.h" +#endif diff --git a/drivers/gpu/drm/armada/armada_trace.h b/drivers/gpu/drm/armada/armada_trace.h new file mode 100644 index 000000000000..dc0cba70fd1a --- /dev/null +++ b/drivers/gpu/drm/armada/armada_trace.h @@ -0,0 +1,66 @@ +#if !defined(ARMADA_TRACE_H) || defined(TRACE_HEADER_MULTI_READ) +#define ARMADA_TRACE_H + +#include <linux/tracepoint.h> +#include <drm/drmP.h> + +#undef TRACE_SYSTEM +#define TRACE_SYSTEM armada +#define TRACE_INCLUDE_FILE armada_trace + +TRACE_EVENT(armada_drm_irq, + TP_PROTO(struct drm_crtc *crtc, u32 stat), + TP_ARGS(crtc, stat), + TP_STRUCT__entry( + __field(struct drm_crtc *, crtc) + __field(u32, stat) + ), + TP_fast_assign( + __entry->crtc = crtc; + __entry->stat = stat; + ), + TP_printk("crtc %p stat 0x%08x", + __entry->crtc, __entry->stat) +); + +TRACE_EVENT(armada_ovl_plane_update, + TP_PROTO(struct drm_plane *plane, struct drm_crtc *crtc, + struct drm_framebuffer *fb, + int crtc_x, int crtc_y, unsigned crtc_w, unsigned crtc_h, + uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h), + TP_ARGS(plane, crtc, fb, crtc_x, crtc_y, crtc_w, crtc_h, src_x, src_y, src_w, src_h), + TP_STRUCT__entry( + __field(struct drm_plane *, plane) + __field(struct drm_crtc *, crtc) + __field(struct drm_framebuffer *, fb) + ), + TP_fast_assign( + __entry->plane = plane; + __entry->crtc = crtc; + __entry->fb = fb; + ), + TP_printk("plane %p crtc %p fb %p", + __entry->plane, __entry->crtc, __entry->fb) +); + +TRACE_EVENT(armada_ovl_plane_work, + TP_PROTO(struct drm_crtc *crtc, struct drm_plane *plane), + TP_ARGS(crtc, plane), + TP_STRUCT__entry( + __field(struct drm_plane *, plane) + __field(struct drm_crtc *, crtc) + ), + TP_fast_assign( + __entry->plane = plane; + __entry->crtc = crtc; + ), + TP_printk("plane %p crtc %p", + __entry->plane, __entry->crtc) +); + +#endif + +/* This part must be outside protection */ +#undef TRACE_INCLUDE_PATH +#define TRACE_INCLUDE_PATH . +#include <trace/define_trace.h> diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index 29755bc32aab..eb8688ec6f18 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -90,6 +90,13 @@ config DRM_TOSHIBA_TC358767 ---help--- Toshiba TC358767 eDP bridge chip driver. +config DRM_TI_TFP410 + tristate "TI TFP410 DVI/HDMI bridge" + depends on OF + select DRM_KMS_HELPER + ---help--- + Texas Instruments TFP410 DVI/HDMI Transmitter driver + source "drivers/gpu/drm/bridge/analogix/Kconfig" source "drivers/gpu/drm/bridge/adv7511/Kconfig" diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile index 1439ad84ccb7..2e83a7855399 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -12,3 +12,4 @@ obj-$(CONFIG_DRM_SII902X) += sii902x.o obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/ obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/ +obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o diff --git a/drivers/gpu/drm/bridge/ti-tfp410.c b/drivers/gpu/drm/bridge/ti-tfp410.c new file mode 100644 index 000000000000..b054ea349952 --- /dev/null +++ b/drivers/gpu/drm/bridge/ti-tfp410.c @@ -0,0 +1,317 @@ +/* + * Copyright (C) 2016 Texas Instruments + * Author: Jyri Sarha <jsarha@ti.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + */ + +#include <linux/module.h> +#include <linux/of_graph.h> +#include <linux/platform_device.h> +#include <linux/i2c.h> + +#include <drm/drmP.h> +#include <drm/drm_atomic_helper.h> +#include <drm/drm_crtc.h> +#include <drm/drm_crtc_helper.h> + +struct tfp410 { + struct drm_bridge bridge; + struct drm_connector connector; + + struct i2c_adapter *ddc; + + struct device *dev; +}; + +static inline struct tfp410 * +drm_bridge_to_tfp410(struct drm_bridge *bridge) +{ + return container_of(bridge, struct tfp410, bridge); +} + +static inline struct tfp410 * +drm_connector_to_tfp410(struct drm_connector *connector) +{ + return container_of(connector, struct tfp410, connector); +} + +static int tfp410_get_modes(struct drm_connector *connector) +{ + struct tfp410 *dvi = drm_connector_to_tfp410(connector); + struct edid *edid; + int ret; + + if (!dvi->ddc) + goto fallback; + + edid = drm_get_edid(connector, dvi->ddc); + if (!edid) { + DRM_INFO("EDID read failed. Fallback to standard modes\n"); + goto fallback; + } + + drm_mode_connector_update_edid_property(connector, edid); + + return drm_add_edid_modes(connector, edid); +fallback: + /* No EDID, fallback on the XGA standard modes */ + ret = drm_add_modes_noedid(connector, 1920, 1200); + + /* And prefer a mode pretty much anything can handle */ + drm_set_preferred_mode(connector, 1024, 768); + + return ret; +} + +static const struct drm_connector_helper_funcs tfp410_con_helper_funcs = { + .get_modes = tfp410_get_modes, +}; + +static enum drm_connector_status +tfp410_connector_detect(struct drm_connector *connector, bool force) +{ + struct tfp410 *dvi = drm_connector_to_tfp410(connector); + + if (dvi->ddc) { + if (drm_probe_ddc(dvi->ddc)) + return connector_status_connected; + else + return connector_status_disconnected; + } + + return connector_status_unknown; +} + +static const struct drm_connector_funcs tfp410_con_funcs = { + .dpms = drm_atomic_helper_connector_dpms, + .detect = tfp410_connector_detect, + .fill_modes = drm_helper_probe_single_connector_modes, + .destroy = drm_connector_cleanup, + .reset = drm_atomic_helper_connector_reset, + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, +}; + +static int tfp410_attach(struct drm_bridge *bridge) +{ + struct tfp410 *dvi = drm_bridge_to_tfp410(bridge); + int ret; + + if (!bridge->encoder) { + dev_err(dvi->dev, "Missing encoder\n"); + return -ENODEV; + } + + drm_connector_helper_add(&dvi->connector, + &tfp410_con_helper_funcs); + ret = drm_connector_init(bridge->dev, &dvi->connector, + &tfp410_con_funcs, DRM_MODE_CONNECTOR_HDMIA); + if (ret) { + dev_err(dvi->dev, "drm_connector_init() failed: %d\n", ret); + return ret; + } + + drm_mode_connector_attach_encoder(&dvi->connector, + bridge->encoder); + + return 0; +} + +static const struct drm_bridge_funcs tfp410_bridge_funcs = { + .attach = tfp410_attach, +}; + +static int tfp410_get_connector_ddc(struct tfp410 *dvi) +{ + struct device_node *ep = NULL, *connector_node = NULL; + struct device_node *ddc_phandle = NULL; + int ret = 0; + + /* port@1 is the connector node */ + ep = of_graph_get_endpoint_by_regs(dvi->dev->of_node, 1, -1); + if (!ep) + goto fail; + + connector_node = of_graph_get_remote_port_parent(ep); + if (!connector_node) + goto fail; + + ddc_phandle = of_parse_phandle(connector_node, "ddc-i2c-bus", 0); + if (!ddc_phandle) + goto fail; + + dvi->ddc = of_get_i2c_adapter_by_node(ddc_phandle); + if (dvi->ddc) + dev_info(dvi->dev, "Connector's ddc i2c bus found\n"); + else + ret = -EPROBE_DEFER; + +fail: + of_node_put(ep); + of_node_put(connector_node); + of_node_put(ddc_phandle); + return ret; +} + +static int tfp410_init(struct device *dev) +{ + struct tfp410 *dvi; + int ret; + + if (!dev->of_node) { + dev_err(dev, "device-tree data is missing\n"); + return -ENXIO; + } + + dvi = devm_kzalloc(dev, sizeof(*dvi), GFP_KERNEL); + if (!dvi) + return -ENOMEM; + dev_set_drvdata(dev, dvi); + + dvi->bridge.funcs = &tfp410_bridge_funcs; + dvi->bridge.of_node = dev->of_node; + dvi->dev = dev; + + ret = tfp410_get_connector_ddc(dvi); + if (ret) + goto fail; + + ret = drm_bridge_add(&dvi->bridge); + if (ret) { + dev_err(dev, "drm_bridge_add() failed: %d\n", ret); + goto fail; + } + + return 0; +fail: + i2c_put_adapter(dvi->ddc); + return ret; +} + +static int tfp410_fini(struct device *dev) +{ + struct tfp410 *dvi = dev_get_drvdata(dev); + + drm_bridge_remove(&dvi->bridge); + + if (dvi->ddc) + i2c_put_adapter(dvi->ddc); + + return 0; +} + +static int tfp410_probe(struct platform_device *pdev) +{ + return tfp410_init(&pdev->dev); +} + +static int tfp410_remove(struct platform_device *pdev) +{ + return tfp410_fini(&pdev->dev); +} + +static const struct of_device_id tfp410_match[] = { + { .compatible = "ti,tfp410" }, + {}, +}; +MODULE_DEVICE_TABLE(of, tfp410_match); + +struct platform_driver tfp410_platform_driver = { + .probe = tfp410_probe, + .remove = tfp410_remove, + .driver = { + .name = "tfp410-bridge", + .of_match_table = tfp410_match, + }, +}; + +#if IS_ENABLED(CONFIG_I2C) +/* There is currently no i2c functionality. */ +static int tfp410_i2c_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int reg; + + if (!client->dev.of_node || + of_property_read_u32(client->dev.of_node, "reg", ®)) { + dev_err(&client->dev, + "Can't get i2c reg property from device-tree\n"); + return -ENXIO; + } + + return tfp410_init(&client->dev); +} + +static int tfp410_i2c_remove(struct i2c_client *client) +{ + return tfp410_fini(&client->dev); +} + +static const struct i2c_device_id tfp410_i2c_ids[] = { + { "tfp410", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, tfp410_i2c_ids); + +static struct i2c_driver tfp410_i2c_driver = { + .driver = { + .name = "tfp410", + .of_match_table = of_match_ptr(tfp410_match), + }, + .id_table = tfp410_i2c_ids, + .probe = tfp410_i2c_probe, + .remove = tfp410_i2c_remove, +}; +#endif /* IS_ENABLED(CONFIG_I2C) */ + +static struct { + uint i2c:1; + uint platform:1; +} tfp410_registered_driver; + +static int __init tfp410_module_init(void) +{ + int ret; + +#if IS_ENABLED(CONFIG_I2C) + ret = i2c_add_driver(&tfp410_i2c_driver); + if (ret) + pr_err("%s: registering i2c driver failed: %d", + __func__, ret); + else + tfp410_registered_driver.i2c = 1; +#endif + + ret = platform_driver_register(&tfp410_platform_driver); + if (ret) + pr_err("%s: registering platform driver failed: %d", + __func__, ret); + else + tfp410_registered_driver.platform = 1; + + if (tfp410_registered_driver.i2c || + tfp410_registered_driver.platform) + return 0; + + return ret; +} +module_init(tfp410_module_init); + +static void __exit tfp410_module_exit(void) +{ +#if IS_ENABLED(CONFIG_I2C) + if (tfp410_registered_driver.i2c) + i2c_del_driver(&tfp410_i2c_driver); +#endif + if (tfp410_registered_driver.platform) + platform_driver_unregister(&tfp410_platform_driver); +} +module_exit(tfp410_module_exit); + +MODULE_AUTHOR("Jyri Sarha <jsarha@ti.com>"); +MODULE_DESCRIPTION("TI TFP410 DVI bridge driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c index cc6c2530764b..f74b7d06ec01 100644 --- a/drivers/gpu/drm/drm_drv.c +++ b/drivers/gpu/drm/drm_drv.c @@ -303,9 +303,10 @@ void drm_minor_release(struct drm_minor *minor) * callbacks implemented by the driver. The driver then needs to initialize all * the various subsystems for the drm device like memory management, vblank * handling, modesetting support and intial output configuration plus obviously - * initialize all the corresponding hardware bits. Finally when everything is up - * and running and ready for userspace the device instance can be published - * using drm_dev_register(). + * initialize all the corresponding hardware bits. An important part of this is + * also calling drm_dev_set_unique() to set the userspace-visible unique name of + * this device instance. Finally when everything is up and running and ready for + * userspace the device instance can be published using drm_dev_register(). * * There is also deprecated support for initalizing device instances using * bus-specific helpers and the ->load() callback. But due to @@ -327,17 +328,6 @@ void drm_minor_release(struct drm_minor *minor) * dev_priv field of &drm_device. */ -static int drm_dev_set_unique(struct drm_device *dev, const char *name) -{ - if (!name) - return -EINVAL; - - kfree(dev->unique); - dev->unique = kstrdup(name, GFP_KERNEL); - - return dev->unique ? 0 : -ENOMEM; -} - /** * drm_put_dev - Unregister and release a DRM device * @dev: DRM device @@ -754,6 +744,26 @@ void drm_dev_unregister(struct drm_device *dev) } EXPORT_SYMBOL(drm_dev_unregister); +/** + * drm_dev_set_unique - Set the unique name of a DRM device + * @dev: device of which to set the unique name + * @name: unique name + * + * Sets the unique name of a DRM device using the specified string. Drivers + * can use this at driver probe time if the unique name of the devices they + * drive is static. + * + * Return: 0 on success or a negative error code on failure. + */ +int drm_dev_set_unique(struct drm_device *dev, const char *name) +{ + kfree(dev->unique); + dev->unique = kstrdup(name, GFP_KERNEL); + + return dev->unique ? 0 : -ENOMEM; +} +EXPORT_SYMBOL(drm_dev_set_unique); + /* * DRM Core * The DRM core module initializes all global DRM objects and makes them diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 728990fee4ef..336be31ff3de 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -3653,32 +3653,6 @@ int drm_av_sync_delay(struct drm_connector *connector, EXPORT_SYMBOL(drm_av_sync_delay); /** - * drm_select_eld - select one ELD from multiple HDMI/DP sinks - * @encoder: the encoder just changed display mode - * - * It's possible for one encoder to be associated with multiple HDMI/DP sinks. - * The policy is now hard coded to simply use the first HDMI/DP sink's ELD. - * - * Return: The connector associated with the first HDMI/DP sink that has ELD - * attached to it. - */ -struct drm_connector *drm_select_eld(struct drm_encoder *encoder) -{ - struct drm_connector *connector; - struct drm_device *dev = encoder->dev; - - WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); - WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); - - drm_for_each_connector(connector, dev) - if (connector->encoder == encoder && connector->eld[0]) - return connector; - - return NULL; -} -EXPORT_SYMBOL(drm_select_eld); - -/** * drm_detect_hdmi_monitor - detect whether monitor is HDMI * @edid: monitor EDID information * diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c index 0ad2c47f808f..71c3473476c7 100644 --- a/drivers/gpu/drm/drm_ioctl.c +++ b/drivers/gpu/drm/drm_ioctl.c @@ -254,10 +254,12 @@ static int drm_getcap(struct drm_device *dev, void *data, struct drm_file *file_ req->value = dev->mode_config.async_page_flip; break; case DRM_CAP_PAGE_FLIP_TARGET: - req->value = 1; - drm_for_each_crtc(crtc, dev) { - if (!crtc->funcs->page_flip_target) - req->value = 0; + if (drm_core_check_feature(dev, DRIVER_MODESET)) { + req->value = 1; + drm_for_each_crtc(crtc, dev) { + if (!crtc->funcs->page_flip_target) + req->value = 0; + } } break; case DRM_CAP_CURSOR_WIDTH: diff --git a/drivers/gpu/drm/etnaviv/cmdstream.xml.h b/drivers/gpu/drm/etnaviv/cmdstream.xml.h index 8c44ba9a694e..65f1ba1099bd 100644 --- a/drivers/gpu/drm/etnaviv/cmdstream.xml.h +++ b/drivers/gpu/drm/etnaviv/cmdstream.xml.h @@ -8,10 +8,34 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng git clone git://0x04.net/rules-ng-ng The rules-ng-ng source files this header was generated from are: -- cmdstream.xml ( 12589 bytes, from 2014-02-17 14:57:56) -- common.xml ( 18437 bytes, from 2015-03-25 11:27:41) - -Copyright (C) 2014 +- cmdstream.xml ( 14094 bytes, from 2016-11-11 06:55:14) +- copyright.xml ( 1597 bytes, from 2016-10-29 07:29:22) +- common.xml ( 23344 bytes, from 2016-11-10 15:14:07) + +Copyright (C) 2012-2016 by the following authors: +- Wladimir J. van der Laan <laanwj@gmail.com> +- Christian Gmeiner <christian.gmeiner@gmail.com> +- Lucas Stach <l.stach@pengutronix.de> +- Russell King <rmk@arm.linux.org.uk> + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +the rights to use, copy, modify, merge, publish, distribute, sub license, +and/or sell copies of the Software, and to permit persons to whom the +Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial portions +of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +DEALINGS IN THE SOFTWARE. */ @@ -26,6 +50,7 @@ Copyright (C) 2014 #define FE_OPCODE_STALL 0x00000009 #define FE_OPCODE_CALL 0x0000000a #define FE_OPCODE_RETURN 0x0000000b +#define FE_OPCODE_DRAW_INSTANCED 0x0000000c #define FE_OPCODE_CHIP_SELECT 0x0000000d #define PRIMITIVE_TYPE_POINTS 0x00000001 #define PRIMITIVE_TYPE_LINES 0x00000002 @@ -214,5 +239,32 @@ Copyright (C) 2014 #define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP1 0x00000002 #define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP0 0x00000001 +#define VIV_FE_DRAW_INSTANCED 0x00000000 + +#define VIV_FE_DRAW_INSTANCED_HEADER 0x00000000 +#define VIV_FE_DRAW_INSTANCED_HEADER_OP__MASK 0xf8000000 +#define VIV_FE_DRAW_INSTANCED_HEADER_OP__SHIFT 27 +#define VIV_FE_DRAW_INSTANCED_HEADER_OP_DRAW_INSTANCED 0x60000000 +#define VIV_FE_DRAW_INSTANCED_HEADER_INDEXED 0x00100000 +#define VIV_FE_DRAW_INSTANCED_HEADER_TYPE__MASK 0x000f0000 +#define VIV_FE_DRAW_INSTANCED_HEADER_TYPE__SHIFT 16 +#define VIV_FE_DRAW_INSTANCED_HEADER_TYPE(x) (((x) << VIV_FE_DRAW_INSTANCED_HEADER_TYPE__SHIFT) & VIV_FE_DRAW_INSTANCED_HEADER_TYPE__MASK) +#define VIV_FE_DRAW_INSTANCED_HEADER_INSTANCE_COUNT_LO__MASK 0x0000ffff +#define VIV_FE_DRAW_INSTANCED_HEADER_INSTANCE_COUNT_LO__SHIFT 0 +#define VIV_FE_DRAW_INSTANCED_HEADER_INSTANCE_COUNT_LO(x) (((x) << VIV_FE_DRAW_INSTANCED_HEADER_INSTANCE_COUNT_LO__SHIFT) & VIV_FE_DRAW_INSTANCED_HEADER_INSTANCE_COUNT_LO__MASK) + +#define VIV_FE_DRAW_INSTANCED_COUNT 0x00000004 +#define VIV_FE_DRAW_INSTANCED_COUNT_INSTANCE_COUNT_HI__MASK 0xff000000 +#define VIV_FE_DRAW_INSTANCED_COUNT_INSTANCE_COUNT_HI__SHIFT 24 +#define VIV_FE_DRAW_INSTANCED_COUNT_INSTANCE_COUNT_HI(x) (((x) << VIV_FE_DRAW_INSTANCED_COUNT_INSTANCE_COUNT_HI__SHIFT) & VIV_FE_DRAW_INSTANCED_COUNT_INSTANCE_COUNT_HI__MASK) +#define VIV_FE_DRAW_INSTANCED_COUNT_VERTEX_COUNT__MASK 0x00ffffff +#define VIV_FE_DRAW_INSTANCED_COUNT_VERTEX_COUNT__SHIFT 0 +#define VIV_FE_DRAW_INSTANCED_COUNT_VERTEX_COUNT(x) (((x) << VIV_FE_DRAW_INSTANCED_COUNT_VERTEX_COUNT__SHIFT) & VIV_FE_DRAW_INSTANCED_COUNT_VERTEX_COUNT__MASK) + +#define VIV_FE_DRAW_INSTANCED_START 0x00000008 +#define VIV_FE_DRAW_INSTANCED_START_INDEX__MASK 0xffffffff +#define VIV_FE_DRAW_INSTANCED_START_INDEX__SHIFT 0 +#define VIV_FE_DRAW_INSTANCED_START_INDEX(x) (((x) << VIV_FE_DRAW_INSTANCED_START_INDEX__SHIFT) & VIV_FE_DRAW_INSTANCED_START_INDEX__MASK) + #endif /* CMDSTREAM_XML */ diff --git a/drivers/gpu/drm/etnaviv/etnaviv_cmd_parser.c b/drivers/gpu/drm/etnaviv/etnaviv_cmd_parser.c index dcfd565c88d1..2a2e5e366ab7 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_cmd_parser.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_cmd_parser.c @@ -143,6 +143,7 @@ static bool etnaviv_validate_load_state(struct etna_validation_state *state, static uint8_t cmd_length[32] = { [FE_OPCODE_DRAW_PRIMITIVES] = 4, [FE_OPCODE_DRAW_INDEXED_PRIMITIVES] = 6, + [FE_OPCODE_DRAW_INSTANCED] = 4, [FE_OPCODE_NOP] = 2, [FE_OPCODE_STALL] = 2, }; diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.c b/drivers/gpu/drm/etnaviv/etnaviv_drv.c index a6799b0aa3d9..00368b14d08d 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_drv.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_drv.c @@ -504,6 +504,7 @@ static struct drm_driver etnaviv_drm_driver = { .gem_prime_import_sg_table = etnaviv_gem_prime_import_sg_table, .gem_prime_vmap = etnaviv_gem_prime_vmap, .gem_prime_vunmap = etnaviv_gem_prime_vunmap, + .gem_prime_mmap = etnaviv_gem_prime_mmap, #ifdef CONFIG_DEBUG_FS .debugfs_init = etnaviv_debugfs_init, .debugfs_cleanup = etnaviv_debugfs_cleanup, diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.h b/drivers/gpu/drm/etnaviv/etnaviv_drv.h index 65e057639653..c255eda40526 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_drv.h +++ b/drivers/gpu/drm/etnaviv/etnaviv_drv.h @@ -78,6 +78,8 @@ int etnaviv_gem_mmap_offset(struct drm_gem_object *obj, u64 *offset); struct sg_table *etnaviv_gem_prime_get_sg_table(struct drm_gem_object *obj); void *etnaviv_gem_prime_vmap(struct drm_gem_object *obj); void etnaviv_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); +int etnaviv_gem_prime_mmap(struct drm_gem_object *obj, + struct vm_area_struct *vma); struct drm_gem_object *etnaviv_gem_prime_import_sg_table(struct drm_device *dev, struct dma_buf_attachment *attach, struct sg_table *sg); int etnaviv_gem_prime_pin(struct drm_gem_object *obj); diff --git a/drivers/gpu/drm/etnaviv/etnaviv_dump.c b/drivers/gpu/drm/etnaviv/etnaviv_dump.c index 2bef501d4a17..af65491a78e2 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_dump.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_dump.c @@ -160,7 +160,8 @@ void etnaviv_core_dump(struct etnaviv_gpu *gpu) file_size += sizeof(*iter.hdr) * n_obj; /* Allocate the file in vmalloc memory, it's likely to be big */ - iter.start = vmalloc(file_size); + iter.start = __vmalloc(file_size, GFP_KERNEL | __GFP_HIGHMEM | + __GFP_NOWARN | __GFP_NORETRY, PAGE_KERNEL); if (!iter.start) { dev_warn(gpu->dev, "failed to allocate devcoredump file\n"); return; diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c b/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c index b93618c1aa69..62b47972a52e 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c @@ -23,10 +23,12 @@ struct sg_table *etnaviv_gem_prime_get_sg_table(struct drm_gem_object *obj) { struct etnaviv_gem_object *etnaviv_obj = to_etnaviv_bo(obj); + int npages = obj->size >> PAGE_SHIFT; - BUG_ON(!etnaviv_obj->sgt); /* should have already pinned! */ + if (WARN_ON(!etnaviv_obj->pages)) /* should have already pinned! */ + return NULL; - return etnaviv_obj->sgt; + return drm_prime_pages_to_sg(etnaviv_obj->pages, npages); } void *etnaviv_gem_prime_vmap(struct drm_gem_object *obj) @@ -39,6 +41,19 @@ void etnaviv_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr) /* TODO msm_gem_vunmap() */ } +int etnaviv_gem_prime_mmap(struct drm_gem_object *obj, + struct vm_area_struct *vma) +{ + struct etnaviv_gem_object *etnaviv_obj = to_etnaviv_bo(obj); + int ret; + + ret = drm_gem_mmap_obj(obj, obj->size, vma); + if (ret < 0) + return ret; + + return etnaviv_obj->ops->mmap(etnaviv_obj, vma); +} + int etnaviv_gem_prime_pin(struct drm_gem_object *obj) { if (!obj->import_attach) { diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c index d2211825e5c8..0a67124bb2a4 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c @@ -639,6 +639,10 @@ int etnaviv_gpu_init(struct etnaviv_gpu *gpu) gpu->memory_base = PHYS_OFFSET; else gpu->memory_base = dma_mask - SZ_2G + 1; + } else if (PHYS_OFFSET >= SZ_2G) { + dev_info(gpu->dev, "Need to move linear window on MC1.0, disabling TS\n"); + gpu->memory_base = PHYS_OFFSET; + gpu->identity.features &= ~chipFeatures_FAST_CLEAR; } ret = etnaviv_hw_reset(gpu); diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig index 465d344f3391..d706ca4e2f02 100644 --- a/drivers/gpu/drm/exynos/Kconfig +++ b/drivers/gpu/drm/exynos/Kconfig @@ -114,7 +114,7 @@ config DRM_EXYNOS_ROTATOR config DRM_EXYNOS_GSC bool "GScaler" - depends on DRM_EXYNOS_IPP && ARCH_EXYNOS5 && !VIDEO_SAMSUNG_EXYNOS_GSC + depends on DRM_EXYNOS_IPP && ARCH_EXYNOS5 && VIDEO_SAMSUNG_EXYNOS_GSC=n help Choose this option if you want to use Exynos GSC for DRM. diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimc.c b/drivers/gpu/drm/exynos/exynos_drm_fimc.c index 147ef0d298cb..95871577015d 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimc.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimc.c @@ -1433,7 +1433,7 @@ static int fimc_ippdrv_start(struct device *dev, enum drm_exynos_ipp_cmd cmd) &img_pos[EXYNOS_DRM_OPS_SRC], &img_pos[EXYNOS_DRM_OPS_DST]); if (ret) { - dev_err(dev, "failed to set precalser.\n"); + dev_err(dev, "failed to set prescaler.\n"); return ret; } diff --git a/drivers/gpu/drm/exynos/exynos_drm_gem.c b/drivers/gpu/drm/exynos/exynos_drm_gem.c index f2ae72ba7d5a..ea7a18230888 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_gem.c +++ b/drivers/gpu/drm/exynos/exynos_drm_gem.c @@ -231,12 +231,12 @@ struct exynos_drm_gem *exynos_drm_gem_create(struct drm_device *dev, int ret; if (flags & ~(EXYNOS_BO_MASK)) { - DRM_ERROR("invalid flags.\n"); + DRM_ERROR("invalid GEM buffer flags: %u\n", flags); return ERR_PTR(-EINVAL); } if (!size) { - DRM_ERROR("invalid size.\n"); + DRM_ERROR("invalid GEM buffer size: %lu\n", size); return ERR_PTR(-EINVAL); } diff --git a/drivers/gpu/drm/exynos/exynos_drm_gsc.c b/drivers/gpu/drm/exynos/exynos_drm_gsc.c index 52a9d269484e..bef57987759d 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_gsc.c +++ b/drivers/gpu/drm/exynos/exynos_drm_gsc.c @@ -1610,7 +1610,7 @@ static int gsc_ippdrv_start(struct device *dev, enum drm_exynos_ipp_cmd cmd) &img_pos[EXYNOS_DRM_OPS_SRC], &img_pos[EXYNOS_DRM_OPS_DST]); if (ret) { - dev_err(dev, "failed to set precalser.\n"); + dev_err(dev, "failed to set prescaler.\n"); return ret; } diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c index e8fb6ef947ee..5ed8b1effe71 100644 --- a/drivers/gpu/drm/exynos/exynos_hdmi.c +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c @@ -47,19 +47,6 @@ #define HOTPLUG_DEBOUNCE_MS 1100 -/* AVI header and aspect ratio */ -#define HDMI_AVI_VERSION 0x02 -#define HDMI_AVI_LENGTH 0x0d - -/* AUI header info */ -#define HDMI_AUI_VERSION 0x01 -#define HDMI_AUI_LENGTH 0x0a - -/* AVI active format aspect ratio */ -#define AVI_SAME_AS_PIC_ASPECT_RATIO 0x08 -#define AVI_4_3_CENTER_RATIO 0x09 -#define AVI_16_9_CENTER_RATIO 0x0a - enum hdmi_type { HDMI_TYPE13, HDMI_TYPE14, @@ -131,7 +118,6 @@ struct hdmi_context { bool dvi_mode; struct delayed_work hotplug_work; struct drm_display_mode current_mode; - u8 cea_video_id; const struct hdmi_driver_data *drv_data; void __iomem *regs; @@ -681,6 +667,13 @@ static inline void hdmi_reg_writev(struct hdmi_context *hdata, u32 reg_id, } } +static inline void hdmi_reg_write_buf(struct hdmi_context *hdata, u32 reg_id, + u8 *buf, int size) +{ + for (reg_id = hdmi_map_reg(hdata, reg_id); size; --size, reg_id += 4) + writel(*buf++, hdata->regs + reg_id); +} + static inline void hdmi_reg_writemask(struct hdmi_context *hdata, u32 reg_id, u32 value, u32 mask) { @@ -762,93 +755,50 @@ static int hdmi_clk_set_parents(struct hdmi_context *hdata, bool to_phy) return ret; } -static u8 hdmi_chksum(struct hdmi_context *hdata, - u32 start, u8 len, u32 hdr_sum) -{ - int i; - - /* hdr_sum : header0 + header1 + header2 - * start : start address of packet byte1 - * len : packet bytes - 1 */ - for (i = 0; i < len; ++i) - hdr_sum += 0xff & hdmi_reg_read(hdata, start + i * 4); - - /* return 2's complement of 8 bit hdr_sum */ - return (u8)(~(hdr_sum & 0xff) + 1); -} - -static void hdmi_reg_infoframe(struct hdmi_context *hdata, - union hdmi_infoframe *infoframe) +static void hdmi_reg_infoframes(struct hdmi_context *hdata) { - u32 hdr_sum; - u8 chksum; - u8 ar; + union hdmi_infoframe frm; + u8 buf[25]; + int ret; if (hdata->dvi_mode) { - hdmi_reg_writeb(hdata, HDMI_VSI_CON, - HDMI_VSI_CON_DO_NOT_TRANSMIT); hdmi_reg_writeb(hdata, HDMI_AVI_CON, HDMI_AVI_CON_DO_NOT_TRANSMIT); + hdmi_reg_writeb(hdata, HDMI_VSI_CON, + HDMI_VSI_CON_DO_NOT_TRANSMIT); hdmi_reg_writeb(hdata, HDMI_AUI_CON, HDMI_AUI_CON_NO_TRAN); return; } - switch (infoframe->any.type) { - case HDMI_INFOFRAME_TYPE_AVI: + ret = drm_hdmi_avi_infoframe_from_display_mode(&frm.avi, + &hdata->current_mode); + if (!ret) + ret = hdmi_avi_infoframe_pack(&frm.avi, buf, sizeof(buf)); + if (ret > 0) { hdmi_reg_writeb(hdata, HDMI_AVI_CON, HDMI_AVI_CON_EVERY_VSYNC); - hdmi_reg_writeb(hdata, HDMI_AVI_HEADER0, infoframe->any.type); - hdmi_reg_writeb(hdata, HDMI_AVI_HEADER1, - infoframe->any.version); - hdmi_reg_writeb(hdata, HDMI_AVI_HEADER2, infoframe->any.length); - hdr_sum = infoframe->any.type + infoframe->any.version + - infoframe->any.length; - - /* Output format zero hardcoded ,RGB YBCR selection */ - hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(1), 0 << 5 | - AVI_ACTIVE_FORMAT_VALID | - AVI_UNDERSCANNED_DISPLAY_VALID); - - /* - * Set the aspect ratio as per the mode, mentioned in - * Table 9 AVI InfoFrame Data Byte 2 of CEA-861-D Standard - */ - ar = hdata->current_mode.picture_aspect_ratio; - switch (ar) { - case HDMI_PICTURE_ASPECT_4_3: - ar |= AVI_4_3_CENTER_RATIO; - break; - case HDMI_PICTURE_ASPECT_16_9: - ar |= AVI_16_9_CENTER_RATIO; - break; - case HDMI_PICTURE_ASPECT_NONE: - default: - ar |= AVI_SAME_AS_PIC_ASPECT_RATIO; - break; - } - hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2), ar); + hdmi_reg_write_buf(hdata, HDMI_AVI_HEADER0, buf, ret); + } else { + DRM_INFO("%s: invalid AVI infoframe (%d)\n", __func__, ret); + } - hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(4), hdata->cea_video_id); + ret = drm_hdmi_vendor_infoframe_from_display_mode(&frm.vendor.hdmi, + &hdata->current_mode); + if (!ret) + ret = hdmi_vendor_infoframe_pack(&frm.vendor.hdmi, buf, + sizeof(buf)); + if (ret > 0) { + hdmi_reg_writeb(hdata, HDMI_VSI_CON, HDMI_VSI_CON_EVERY_VSYNC); + hdmi_reg_write_buf(hdata, HDMI_VSI_HEADER0, buf, ret); + } - chksum = hdmi_chksum(hdata, HDMI_AVI_BYTE(1), - infoframe->any.length, hdr_sum); - DRM_DEBUG_KMS("AVI checksum = 0x%x\n", chksum); - hdmi_reg_writeb(hdata, HDMI_AVI_CHECK_SUM, chksum); - break; - case HDMI_INFOFRAME_TYPE_AUDIO: - hdmi_reg_writeb(hdata, HDMI_AUI_CON, 0x02); - hdmi_reg_writeb(hdata, HDMI_AUI_HEADER0, infoframe->any.type); - hdmi_reg_writeb(hdata, HDMI_AUI_HEADER1, - infoframe->any.version); - hdmi_reg_writeb(hdata, HDMI_AUI_HEADER2, infoframe->any.length); - hdr_sum = infoframe->any.type + infoframe->any.version + - infoframe->any.length; - chksum = hdmi_chksum(hdata, HDMI_AUI_BYTE(1), - infoframe->any.length, hdr_sum); - DRM_DEBUG_KMS("AUI checksum = 0x%x\n", chksum); - hdmi_reg_writeb(hdata, HDMI_AUI_CHECK_SUM, chksum); - break; - default: - break; + ret = hdmi_audio_infoframe_init(&frm.audio); + if (!ret) { + frm.audio.channels = 2; + ret = hdmi_audio_infoframe_pack(&frm.audio, buf, sizeof(buf)); + } + if (ret > 0) { + hdmi_reg_writeb(hdata, HDMI_AUI_CON, HDMI_AUI_CON_EVERY_VSYNC); + hdmi_reg_write_buf(hdata, HDMI_AUI_HEADER0, buf, ret); } } @@ -1127,8 +1077,6 @@ static void hdmi_start(struct hdmi_context *hdata, bool start) static void hdmi_conf_init(struct hdmi_context *hdata) { - union hdmi_infoframe infoframe; - /* disable HPD interrupts from HDMI IP block, use GPIO instead */ hdmi_reg_writemask(hdata, HDMI_INTC_CON, 0, HDMI_INTC_EN_GLOBAL | HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG); @@ -1164,15 +1112,7 @@ static void hdmi_conf_init(struct hdmi_context *hdata) hdmi_reg_writeb(hdata, HDMI_V13_AUI_CON, 0x02); hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 0x04); } else { - infoframe.any.type = HDMI_INFOFRAME_TYPE_AVI; - infoframe.any.version = HDMI_AVI_VERSION; - infoframe.any.length = HDMI_AVI_LENGTH; - hdmi_reg_infoframe(hdata, &infoframe); - - infoframe.any.type = HDMI_INFOFRAME_TYPE_AUDIO; - infoframe.any.version = HDMI_AUI_VERSION; - infoframe.any.length = HDMI_AUI_LENGTH; - hdmi_reg_infoframe(hdata, &infoframe); + hdmi_reg_infoframes(hdata); /* enable AVI packet every vsync, fixes purple line problem */ hdmi_reg_writemask(hdata, HDMI_CON_1, 2, 3 << 5); @@ -1458,7 +1398,6 @@ static void hdmi_mode_set(struct drm_encoder *encoder, "INTERLACED" : "PROGRESSIVE"); drm_mode_copy(&hdata->current_mode, m); - hdata->cea_video_id = drm_match_cea_mode(mode); } static void hdmi_set_refclk(struct hdmi_context *hdata, bool on) @@ -1907,6 +1846,8 @@ err_disable_pm_runtime: err_hdmiphy: if (hdata->hdmiphy_port) put_device(&hdata->hdmiphy_port->dev); + if (hdata->regs_hdmiphy) + iounmap(hdata->regs_hdmiphy); err_ddc: put_device(&hdata->ddc_adpt->dev); @@ -1929,6 +1870,9 @@ static int hdmi_remove(struct platform_device *pdev) if (hdata->hdmiphy_port) put_device(&hdata->hdmiphy_port->dev); + if (hdata->regs_hdmiphy) + iounmap(hdata->regs_hdmiphy); + put_device(&hdata->ddc_adpt->dev); return 0; diff --git a/drivers/gpu/drm/exynos/regs-hdmi.h b/drivers/gpu/drm/exynos/regs-hdmi.h index 169667a22bdc..a0507dc18d9e 100644 --- a/drivers/gpu/drm/exynos/regs-hdmi.h +++ b/drivers/gpu/drm/exynos/regs-hdmi.h @@ -361,9 +361,11 @@ /* AUI bit definition */ #define HDMI_AUI_CON_NO_TRAN (0 << 0) +#define HDMI_AUI_CON_EVERY_VSYNC (1 << 1) /* VSI bit definition */ #define HDMI_VSI_CON_DO_NOT_TRANSMIT (0 << 0) +#define HDMI_VSI_CON_EVERY_VSYNC (1 << 1) /* HDCP related registers */ #define HDMI_HDCP_SHA1(n) HDMI_CORE_BASE(0x7000 + 4 * (n)) diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c index b2d5e188b1b8..deb57435cc89 100644 --- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c +++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c @@ -25,8 +25,13 @@ static void fsl_dcu_drm_crtc_atomic_flush(struct drm_crtc *crtc, struct drm_crtc_state *old_crtc_state) { + struct drm_device *dev = crtc->dev; + struct fsl_dcu_drm_device *fsl_dev = dev->dev_private; struct drm_pending_vblank_event *event = crtc->state->event; + regmap_write(fsl_dev->regmap, + DCU_UPDATE_MODE, DCU_UPDATE_MODE_READREG); + if (event) { crtc->state->event = NULL; @@ -39,11 +44,15 @@ static void fsl_dcu_drm_crtc_atomic_flush(struct drm_crtc *crtc, } } -static void fsl_dcu_drm_disable_crtc(struct drm_crtc *crtc) +static void fsl_dcu_drm_crtc_atomic_disable(struct drm_crtc *crtc, + struct drm_crtc_state *old_crtc_state) { struct drm_device *dev = crtc->dev; struct fsl_dcu_drm_device *fsl_dev = dev->dev_private; + /* always disable planes on the CRTC */ + drm_atomic_helper_disable_planes_on_crtc(old_crtc_state, true); + drm_crtc_vblank_off(crtc); regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE, @@ -122,8 +131,8 @@ static void fsl_dcu_drm_crtc_mode_set_nofb(struct drm_crtc *crtc) } static const struct drm_crtc_helper_funcs fsl_dcu_drm_crtc_helper_funcs = { + .atomic_disable = fsl_dcu_drm_crtc_atomic_disable, .atomic_flush = fsl_dcu_drm_crtc_atomic_flush, - .disable = fsl_dcu_drm_disable_crtc, .enable = fsl_dcu_drm_crtc_enable, .mode_set_nofb = fsl_dcu_drm_crtc_mode_set_nofb, }; diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c index 0b0d1cb11641..320e4728c9b9 100644 --- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c +++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c @@ -59,8 +59,6 @@ static int fsl_dcu_drm_irq_init(struct drm_device *dev) regmap_write(fsl_dev->regmap, DCU_INT_STATUS, 0); regmap_write(fsl_dev->regmap, DCU_INT_MASK, ~0); - regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE, - DCU_UPDATE_MODE_READREG); return ret; } @@ -139,8 +137,6 @@ static irqreturn_t fsl_dcu_drm_irq(int irq, void *arg) drm_handle_vblank(dev, 0); regmap_write(fsl_dev->regmap, DCU_INT_STATUS, int_status); - regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE, - DCU_UPDATE_MODE_READREG); return IRQ_HANDLED; } diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c index 9e6f7d8112b3..a99f48847420 100644 --- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c +++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c @@ -160,11 +160,6 @@ static void fsl_dcu_drm_plane_atomic_update(struct drm_plane *plane, DCU_LAYER_POST_SKIP(0) | DCU_LAYER_PRE_SKIP(0)); } - regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE, - DCU_MODE_DCU_MODE_MASK, - DCU_MODE_DCU_MODE(DCU_MODE_NORMAL)); - regmap_write(fsl_dev->regmap, - DCU_UPDATE_MODE, DCU_UPDATE_MODE_READREG); return; } diff --git a/drivers/gpu/drm/i2c/tda998x_drv.c b/drivers/gpu/drm/i2c/tda998x_drv.c index 027521f30b6e..86f47e190309 100644 --- a/drivers/gpu/drm/i2c/tda998x_drv.c +++ b/drivers/gpu/drm/i2c/tda998x_drv.c @@ -41,12 +41,15 @@ struct tda998x_priv { struct i2c_client *hdmi; struct mutex mutex; u16 rev; + u8 cec_addr; u8 current_page; - int dpms; - bool is_hdmi_sink; + bool is_on; + bool supports_infoframes; + bool sink_has_audio; u8 vip_cntrl_0; u8 vip_cntrl_1; u8 vip_cntrl_2; + unsigned long tmds_clock; struct tda998x_audio_params audio_params; struct platform_device *audio_pdev; @@ -105,6 +108,8 @@ struct tda998x_priv { # define I2C_MASTER_DIS_FILT (1 << 1) # define I2C_MASTER_APP_STRT_LAT (1 << 2) #define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */ +# define FEAT_POWERDOWN_PREFILT BIT(0) +# define FEAT_POWERDOWN_CSC BIT(1) # define FEAT_POWERDOWN_SPDIF (1 << 3) #define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */ #define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */ @@ -370,35 +375,46 @@ struct tda998x_priv { static void cec_write(struct tda998x_priv *priv, u16 addr, u8 val) { - struct i2c_client *client = priv->cec; u8 buf[] = {addr, val}; + struct i2c_msg msg = { + .addr = priv->cec_addr, + .len = 2, + .buf = buf, + }; int ret; - ret = i2c_master_send(client, buf, sizeof(buf)); + ret = i2c_transfer(priv->hdmi->adapter, &msg, 1); if (ret < 0) - dev_err(&client->dev, "Error %d writing to cec:0x%x\n", ret, addr); + dev_err(&priv->hdmi->dev, "Error %d writing to cec:0x%x\n", + ret, addr); } static u8 cec_read(struct tda998x_priv *priv, u8 addr) { - struct i2c_client *client = priv->cec; u8 val; + struct i2c_msg msg[2] = { + { + .addr = priv->cec_addr, + .len = 1, + .buf = &addr, + }, { + .addr = priv->cec_addr, + .flags = I2C_M_RD, + .len = 1, + .buf = &val, + }, + }; int ret; - ret = i2c_master_send(client, &addr, sizeof(addr)); - if (ret < 0) - goto fail; - - ret = i2c_master_recv(client, &val, sizeof(val)); - if (ret < 0) - goto fail; + ret = i2c_transfer(priv->hdmi->adapter, msg, ARRAY_SIZE(msg)); + if (ret < 0) { + dev_err(&priv->hdmi->dev, "Error %d reading from cec:0x%x\n", + ret, addr); + val = 0; + } return val; - -fail: - dev_err(&client->dev, "Error %d reading from cec:0x%x\n", ret, addr); - return 0; } static int @@ -579,9 +595,9 @@ tda998x_reset(struct tda998x_priv *priv) * HPD assertion: it needs a delay of 100ms to avoid timing out while * trying to read EDID data. * - * However, tda998x_encoder_get_modes() may be called at any moment + * However, tda998x_connector_get_modes() may be called at any moment * after tda998x_connector_detect() indicates that we are connected, so - * we need to delay probing modes in tda998x_encoder_get_modes() after + * we need to delay probing modes in tda998x_connector_get_modes() after * we have seen a HPD inactive->active transition. This code implements * that delay. */ @@ -630,28 +646,30 @@ static irqreturn_t tda998x_irq_thread(int irq, void *data) bool handled = false; sta = cec_read(priv, REG_CEC_INTSTATUS); - cec = cec_read(priv, REG_CEC_RXSHPDINT); - lvl = cec_read(priv, REG_CEC_RXSHPDLEV); - flag0 = reg_read(priv, REG_INT_FLAGS_0); - flag1 = reg_read(priv, REG_INT_FLAGS_1); - flag2 = reg_read(priv, REG_INT_FLAGS_2); - DRM_DEBUG_DRIVER( - "tda irq sta %02x cec %02x lvl %02x f0 %02x f1 %02x f2 %02x\n", - sta, cec, lvl, flag0, flag1, flag2); - - if (cec & CEC_RXSHPDINT_HPD) { - if (lvl & CEC_RXSHPDLEV_HPD) - tda998x_edid_delay_start(priv); - else - schedule_work(&priv->detect_work); - - handled = true; - } + if (sta & CEC_INTSTATUS_HDMI) { + cec = cec_read(priv, REG_CEC_RXSHPDINT); + lvl = cec_read(priv, REG_CEC_RXSHPDLEV); + flag0 = reg_read(priv, REG_INT_FLAGS_0); + flag1 = reg_read(priv, REG_INT_FLAGS_1); + flag2 = reg_read(priv, REG_INT_FLAGS_2); + DRM_DEBUG_DRIVER( + "tda irq sta %02x cec %02x lvl %02x f0 %02x f1 %02x f2 %02x\n", + sta, cec, lvl, flag0, flag1, flag2); + + if (cec & CEC_RXSHPDINT_HPD) { + if (lvl & CEC_RXSHPDLEV_HPD) + tda998x_edid_delay_start(priv); + else + schedule_work(&priv->detect_work); + + handled = true; + } - if ((flag2 & INT_FLAGS_2_EDID_BLK_RD) && priv->wq_edid_wait) { - priv->wq_edid_wait = 0; - wake_up(&priv->wq_edid); - handled = true; + if ((flag2 & INT_FLAGS_2_EDID_BLK_RD) && priv->wq_edid_wait) { + priv->wq_edid_wait = 0; + wake_up(&priv->wq_edid); + handled = true; + } } return IRQ_RETVAL(handled); @@ -700,6 +718,8 @@ tda998x_write_avi(struct tda998x_priv *priv, struct drm_display_mode *mode) tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, &frame); } +/* Audio support */ + static void tda998x_audio_mute(struct tda998x_priv *priv, bool on) { if (on) { @@ -713,8 +733,7 @@ static void tda998x_audio_mute(struct tda998x_priv *priv, bool on) static int tda998x_configure_audio(struct tda998x_priv *priv, - struct tda998x_audio_params *params, - unsigned mode_clock) + struct tda998x_audio_params *params) { u8 buf[6], clksel_aip, clksel_fs, cts_n, adiv; u32 n; @@ -771,7 +790,7 @@ tda998x_configure_audio(struct tda998x_priv *priv, * assume 100MHz requires larger divider. */ adiv = AUDIO_DIV_SERCLK_8; - if (mode_clock > 100000) + if (priv->tmds_clock > 100000) adiv++; /* AUDIO_DIV_SERCLK_16 */ /* S/PDIF asks for a larger divider */ @@ -819,58 +838,281 @@ tda998x_configure_audio(struct tda998x_priv *priv, return tda998x_write_aif(priv, ¶ms->cea); } -/* DRM encoder functions */ +static int tda998x_audio_hw_params(struct device *dev, void *data, + struct hdmi_codec_daifmt *daifmt, + struct hdmi_codec_params *params) +{ + struct tda998x_priv *priv = dev_get_drvdata(dev); + int i, ret; + struct tda998x_audio_params audio = { + .sample_width = params->sample_width, + .sample_rate = params->sample_rate, + .cea = params->cea, + }; + + memcpy(audio.status, params->iec.status, + min(sizeof(audio.status), sizeof(params->iec.status))); -static void tda998x_encoder_set_config(struct tda998x_priv *priv, - const struct tda998x_encoder_params *p) + switch (daifmt->fmt) { + case HDMI_I2S: + if (daifmt->bit_clk_inv || daifmt->frame_clk_inv || + daifmt->bit_clk_master || daifmt->frame_clk_master) { + dev_err(dev, "%s: Bad flags %d %d %d %d\n", __func__, + daifmt->bit_clk_inv, daifmt->frame_clk_inv, + daifmt->bit_clk_master, + daifmt->frame_clk_master); + return -EINVAL; + } + for (i = 0; i < ARRAY_SIZE(priv->audio_port); i++) + if (priv->audio_port[i].format == AFMT_I2S) + audio.config = priv->audio_port[i].config; + audio.format = AFMT_I2S; + break; + case HDMI_SPDIF: + for (i = 0; i < ARRAY_SIZE(priv->audio_port); i++) + if (priv->audio_port[i].format == AFMT_SPDIF) + audio.config = priv->audio_port[i].config; + audio.format = AFMT_SPDIF; + break; + default: + dev_err(dev, "%s: Invalid format %d\n", __func__, daifmt->fmt); + return -EINVAL; + } + + if (audio.config == 0) { + dev_err(dev, "%s: No audio configuration found\n", __func__); + return -EINVAL; + } + + mutex_lock(&priv->audio_mutex); + if (priv->supports_infoframes && priv->sink_has_audio) + ret = tda998x_configure_audio(priv, &audio); + else + ret = 0; + + if (ret == 0) + priv->audio_params = audio; + mutex_unlock(&priv->audio_mutex); + + return ret; +} + +static void tda998x_audio_shutdown(struct device *dev, void *data) { - priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) | - (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) | - VIP_CNTRL_0_SWAP_B(p->swap_b) | - (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0); - priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) | - (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) | - VIP_CNTRL_1_SWAP_D(p->swap_d) | - (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0); - priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) | - (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) | - VIP_CNTRL_2_SWAP_F(p->swap_f) | - (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0); + struct tda998x_priv *priv = dev_get_drvdata(dev); - priv->audio_params = p->audio_params; + mutex_lock(&priv->audio_mutex); + + reg_write(priv, REG_ENA_AP, 0); + + priv->audio_params.format = AFMT_UNUSED; + + mutex_unlock(&priv->audio_mutex); } -static void tda998x_encoder_dpms(struct drm_encoder *encoder, int mode) +int tda998x_audio_digital_mute(struct device *dev, void *data, bool enable) { - struct tda998x_priv *priv = enc_to_tda998x_priv(encoder); + struct tda998x_priv *priv = dev_get_drvdata(dev); - /* we only care about on or off: */ - if (mode != DRM_MODE_DPMS_ON) - mode = DRM_MODE_DPMS_OFF; + mutex_lock(&priv->audio_mutex); - if (mode == priv->dpms) - return; + tda998x_audio_mute(priv, enable); - switch (mode) { - case DRM_MODE_DPMS_ON: - /* enable video ports, audio will be enabled later */ - reg_write(priv, REG_ENA_VP_0, 0xff); - reg_write(priv, REG_ENA_VP_1, 0xff); - reg_write(priv, REG_ENA_VP_2, 0xff); - /* set muxing after enabling ports: */ - reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0); - reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1); - reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2); - break; - case DRM_MODE_DPMS_OFF: - /* disable video ports */ - reg_write(priv, REG_ENA_VP_0, 0x00); - reg_write(priv, REG_ENA_VP_1, 0x00); - reg_write(priv, REG_ENA_VP_2, 0x00); - break; + mutex_unlock(&priv->audio_mutex); + return 0; +} + +static int tda998x_audio_get_eld(struct device *dev, void *data, + uint8_t *buf, size_t len) +{ + struct tda998x_priv *priv = dev_get_drvdata(dev); + + mutex_lock(&priv->audio_mutex); + memcpy(buf, priv->connector.eld, + min(sizeof(priv->connector.eld), len)); + mutex_unlock(&priv->audio_mutex); + + return 0; +} + +static const struct hdmi_codec_ops audio_codec_ops = { + .hw_params = tda998x_audio_hw_params, + .audio_shutdown = tda998x_audio_shutdown, + .digital_mute = tda998x_audio_digital_mute, + .get_eld = tda998x_audio_get_eld, +}; + +static int tda998x_audio_codec_init(struct tda998x_priv *priv, + struct device *dev) +{ + struct hdmi_codec_pdata codec_data = { + .ops = &audio_codec_ops, + .max_i2s_channels = 2, + }; + int i; + + for (i = 0; i < ARRAY_SIZE(priv->audio_port); i++) { + if (priv->audio_port[i].format == AFMT_I2S && + priv->audio_port[i].config != 0) + codec_data.i2s = 1; + if (priv->audio_port[i].format == AFMT_SPDIF && + priv->audio_port[i].config != 0) + codec_data.spdif = 1; } - priv->dpms = mode; + priv->audio_pdev = platform_device_register_data( + dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO, + &codec_data, sizeof(codec_data)); + + return PTR_ERR_OR_ZERO(priv->audio_pdev); +} + +/* DRM connector functions */ + +static int tda998x_connector_dpms(struct drm_connector *connector, int mode) +{ + if (drm_core_check_feature(connector->dev, DRIVER_ATOMIC)) + return drm_atomic_helper_connector_dpms(connector, mode); + else + return drm_helper_connector_dpms(connector, mode); +} + +static int tda998x_connector_fill_modes(struct drm_connector *connector, + uint32_t maxX, uint32_t maxY) +{ + struct tda998x_priv *priv = conn_to_tda998x_priv(connector); + int ret; + + mutex_lock(&priv->audio_mutex); + ret = drm_helper_probe_single_connector_modes(connector, maxX, maxY); + + if (connector->edid_blob_ptr) { + struct edid *edid = (void *)connector->edid_blob_ptr->data; + + priv->sink_has_audio = drm_detect_monitor_audio(edid); + } else { + priv->sink_has_audio = false; + } + mutex_unlock(&priv->audio_mutex); + + return ret; +} + +static enum drm_connector_status +tda998x_connector_detect(struct drm_connector *connector, bool force) +{ + struct tda998x_priv *priv = conn_to_tda998x_priv(connector); + u8 val = cec_read(priv, REG_CEC_RXSHPDLEV); + + return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected : + connector_status_disconnected; +} + +static void tda998x_connector_destroy(struct drm_connector *connector) +{ + drm_connector_cleanup(connector); +} + +static const struct drm_connector_funcs tda998x_connector_funcs = { + .dpms = tda998x_connector_dpms, + .reset = drm_atomic_helper_connector_reset, + .fill_modes = tda998x_connector_fill_modes, + .detect = tda998x_connector_detect, + .destroy = tda998x_connector_destroy, + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, +}; + +static int read_edid_block(void *data, u8 *buf, unsigned int blk, size_t length) +{ + struct tda998x_priv *priv = data; + u8 offset, segptr; + int ret, i; + + offset = (blk & 1) ? 128 : 0; + segptr = blk / 2; + + reg_write(priv, REG_DDC_ADDR, 0xa0); + reg_write(priv, REG_DDC_OFFS, offset); + reg_write(priv, REG_DDC_SEGM_ADDR, 0x60); + reg_write(priv, REG_DDC_SEGM, segptr); + + /* enable reading EDID: */ + priv->wq_edid_wait = 1; + reg_write(priv, REG_EDID_CTRL, 0x1); + + /* flag must be cleared by sw: */ + reg_write(priv, REG_EDID_CTRL, 0x0); + + /* wait for block read to complete: */ + if (priv->hdmi->irq) { + i = wait_event_timeout(priv->wq_edid, + !priv->wq_edid_wait, + msecs_to_jiffies(100)); + if (i < 0) { + dev_err(&priv->hdmi->dev, "read edid wait err %d\n", i); + return i; + } + } else { + for (i = 100; i > 0; i--) { + msleep(1); + ret = reg_read(priv, REG_INT_FLAGS_2); + if (ret < 0) + return ret; + if (ret & INT_FLAGS_2_EDID_BLK_RD) + break; + } + } + + if (i == 0) { + dev_err(&priv->hdmi->dev, "read edid timeout\n"); + return -ETIMEDOUT; + } + + ret = reg_read_range(priv, REG_EDID_DATA_0, buf, length); + if (ret != length) { + dev_err(&priv->hdmi->dev, "failed to read edid block %d: %d\n", + blk, ret); + return ret; + } + + return 0; +} + +static int tda998x_connector_get_modes(struct drm_connector *connector) +{ + struct tda998x_priv *priv = conn_to_tda998x_priv(connector); + struct edid *edid; + int n; + + /* + * If we get killed while waiting for the HPD timeout, return + * no modes found: we are not in a restartable path, so we + * can't handle signals gracefully. + */ + if (tda998x_edid_delay_wait(priv)) + return 0; + + if (priv->rev == TDA19988) + reg_clear(priv, REG_TX4, TX4_PD_RAM); + + edid = drm_do_get_edid(connector, read_edid_block, priv); + + if (priv->rev == TDA19988) + reg_set(priv, REG_TX4, TX4_PD_RAM); + + if (!edid) { + dev_warn(&priv->hdmi->dev, "failed to read EDID\n"); + return 0; + } + + drm_mode_connector_update_edid_property(connector, edid); + n = drm_add_edid_modes(connector, edid); + drm_edid_to_eld(connector, edid); + + kfree(edid); + + return n; } static int tda998x_connector_mode_valid(struct drm_connector *connector, @@ -888,6 +1130,80 @@ static int tda998x_connector_mode_valid(struct drm_connector *connector, return MODE_OK; } +static struct drm_encoder * +tda998x_connector_best_encoder(struct drm_connector *connector) +{ + struct tda998x_priv *priv = conn_to_tda998x_priv(connector); + + return &priv->encoder; +} + +static +const struct drm_connector_helper_funcs tda998x_connector_helper_funcs = { + .get_modes = tda998x_connector_get_modes, + .mode_valid = tda998x_connector_mode_valid, + .best_encoder = tda998x_connector_best_encoder, +}; + +static int tda998x_connector_init(struct tda998x_priv *priv, + struct drm_device *drm) +{ + struct drm_connector *connector = &priv->connector; + int ret; + + connector->interlace_allowed = 1; + + if (priv->hdmi->irq) + connector->polled = DRM_CONNECTOR_POLL_HPD; + else + connector->polled = DRM_CONNECTOR_POLL_CONNECT | + DRM_CONNECTOR_POLL_DISCONNECT; + + drm_connector_helper_add(connector, &tda998x_connector_helper_funcs); + ret = drm_connector_init(drm, connector, &tda998x_connector_funcs, + DRM_MODE_CONNECTOR_HDMIA); + if (ret) + return ret; + + drm_mode_connector_attach_encoder(&priv->connector, &priv->encoder); + + return 0; +} + +/* DRM encoder functions */ + +static void tda998x_encoder_dpms(struct drm_encoder *encoder, int mode) +{ + struct tda998x_priv *priv = enc_to_tda998x_priv(encoder); + bool on; + + /* we only care about on or off: */ + on = mode == DRM_MODE_DPMS_ON; + + if (on == priv->is_on) + return; + + if (on) { + /* enable video ports, audio will be enabled later */ + reg_write(priv, REG_ENA_VP_0, 0xff); + reg_write(priv, REG_ENA_VP_1, 0xff); + reg_write(priv, REG_ENA_VP_2, 0xff); + /* set muxing after enabling ports: */ + reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0); + reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1); + reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2); + + priv->is_on = true; + } else { + /* disable video ports */ + reg_write(priv, REG_ENA_VP_0, 0x00); + reg_write(priv, REG_ENA_VP_1, 0x00); + reg_write(priv, REG_ENA_VP_2, 0x00); + + priv->is_on = false; + } +} + static void tda998x_encoder_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, @@ -971,6 +1287,8 @@ tda998x_encoder_mode_set(struct drm_encoder *encoder, div = 3; } + mutex_lock(&priv->audio_mutex); + /* mute the audio FIFO: */ reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); @@ -982,6 +1300,7 @@ tda998x_encoder_mode_set(struct drm_encoder *encoder, /* no pre-filter or interpolator: */ reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) | HVF_CNTRL_0_INTPOL(0)); + reg_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_PREFILT); reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0)); reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) | VIP_CNTRL_4_BLC(0)); @@ -1004,6 +1323,7 @@ tda998x_encoder_mode_set(struct drm_encoder *encoder, /* set color matrix bypass flag: */ reg_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP | MAT_CONTRL_MAT_SC(1)); + reg_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_CSC); /* set BIAS tmds value: */ reg_write(priv, REG_ANA_GENERAL, 0x09); @@ -1064,8 +1384,22 @@ tda998x_encoder_mode_set(struct drm_encoder *encoder, /* must be last register set: */ reg_write(priv, REG_TBG_CNTRL_0, 0); - /* Only setup the info frames if the sink is HDMI */ - if (priv->is_hdmi_sink) { + priv->tmds_clock = adjusted_mode->clock; + + /* CEA-861B section 6 says that: + * CEA version 1 (CEA-861) has no support for infoframes. + * CEA version 2 (CEA-861A) supports version 1 AVI infoframes, + * and optional basic audio. + * CEA version 3 (CEA-861B) supports version 1 and 2 AVI infoframes, + * and optional digital audio, with audio infoframes. + * + * Since we only support generation of version 2 AVI infoframes, + * ignore CEA version 2 and below (iow, behave as if we're a + * CEA-861 source.) + */ + priv->supports_infoframes = priv->connector.display_info.cea_rev >= 3; + + if (priv->supports_infoframes) { /* We need to turn HDMI HDCP stuff on to get audio through */ reg &= ~TBG_CNTRL_1_DWIN_DIS; reg_write(priv, REG_TBG_CNTRL_1, reg); @@ -1074,127 +1408,12 @@ tda998x_encoder_mode_set(struct drm_encoder *encoder, tda998x_write_avi(priv, adjusted_mode); - if (priv->audio_params.format != AFMT_UNUSED) { - mutex_lock(&priv->audio_mutex); - tda998x_configure_audio(priv, - &priv->audio_params, - adjusted_mode->clock); - mutex_unlock(&priv->audio_mutex); - } + if (priv->audio_params.format != AFMT_UNUSED && + priv->sink_has_audio) + tda998x_configure_audio(priv, &priv->audio_params); } -} -static enum drm_connector_status -tda998x_connector_detect(struct drm_connector *connector, bool force) -{ - struct tda998x_priv *priv = conn_to_tda998x_priv(connector); - u8 val = cec_read(priv, REG_CEC_RXSHPDLEV); - - return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected : - connector_status_disconnected; -} - -static int read_edid_block(void *data, u8 *buf, unsigned int blk, size_t length) -{ - struct tda998x_priv *priv = data; - u8 offset, segptr; - int ret, i; - - offset = (blk & 1) ? 128 : 0; - segptr = blk / 2; - - reg_write(priv, REG_DDC_ADDR, 0xa0); - reg_write(priv, REG_DDC_OFFS, offset); - reg_write(priv, REG_DDC_SEGM_ADDR, 0x60); - reg_write(priv, REG_DDC_SEGM, segptr); - - /* enable reading EDID: */ - priv->wq_edid_wait = 1; - reg_write(priv, REG_EDID_CTRL, 0x1); - - /* flag must be cleared by sw: */ - reg_write(priv, REG_EDID_CTRL, 0x0); - - /* wait for block read to complete: */ - if (priv->hdmi->irq) { - i = wait_event_timeout(priv->wq_edid, - !priv->wq_edid_wait, - msecs_to_jiffies(100)); - if (i < 0) { - dev_err(&priv->hdmi->dev, "read edid wait err %d\n", i); - return i; - } - } else { - for (i = 100; i > 0; i--) { - msleep(1); - ret = reg_read(priv, REG_INT_FLAGS_2); - if (ret < 0) - return ret; - if (ret & INT_FLAGS_2_EDID_BLK_RD) - break; - } - } - - if (i == 0) { - dev_err(&priv->hdmi->dev, "read edid timeout\n"); - return -ETIMEDOUT; - } - - ret = reg_read_range(priv, REG_EDID_DATA_0, buf, length); - if (ret != length) { - dev_err(&priv->hdmi->dev, "failed to read edid block %d: %d\n", - blk, ret); - return ret; - } - - return 0; -} - -static int tda998x_connector_get_modes(struct drm_connector *connector) -{ - struct tda998x_priv *priv = conn_to_tda998x_priv(connector); - struct edid *edid; - int n; - - /* - * If we get killed while waiting for the HPD timeout, return - * no modes found: we are not in a restartable path, so we - * can't handle signals gracefully. - */ - if (tda998x_edid_delay_wait(priv)) - return 0; - - if (priv->rev == TDA19988) - reg_clear(priv, REG_TX4, TX4_PD_RAM); - - edid = drm_do_get_edid(connector, read_edid_block, priv); - - if (priv->rev == TDA19988) - reg_set(priv, REG_TX4, TX4_PD_RAM); - - if (!edid) { - dev_warn(&priv->hdmi->dev, "failed to read EDID\n"); - return 0; - } - - drm_mode_connector_update_edid_property(connector, edid); - n = drm_add_edid_modes(connector, edid); - priv->is_hdmi_sink = drm_detect_hdmi_monitor(edid); - drm_edid_to_eld(connector, edid); - - kfree(edid); - - return n; -} - -static void tda998x_encoder_set_polling(struct tda998x_priv *priv, - struct drm_connector *connector) -{ - if (priv->hdmi->irq) - connector->polled = DRM_CONNECTOR_POLL_HPD; - else - connector->polled = DRM_CONNECTOR_POLL_CONNECT | - DRM_CONNECTOR_POLL_DISCONNECT; + mutex_unlock(&priv->audio_mutex); } static void tda998x_destroy(struct tda998x_priv *priv) @@ -1215,146 +1434,6 @@ static void tda998x_destroy(struct tda998x_priv *priv) i2c_unregister_device(priv->cec); } -static int tda998x_audio_hw_params(struct device *dev, void *data, - struct hdmi_codec_daifmt *daifmt, - struct hdmi_codec_params *params) -{ - struct tda998x_priv *priv = dev_get_drvdata(dev); - int i, ret; - struct tda998x_audio_params audio = { - .sample_width = params->sample_width, - .sample_rate = params->sample_rate, - .cea = params->cea, - }; - - if (!priv->encoder.crtc) - return -ENODEV; - - memcpy(audio.status, params->iec.status, - min(sizeof(audio.status), sizeof(params->iec.status))); - - switch (daifmt->fmt) { - case HDMI_I2S: - if (daifmt->bit_clk_inv || daifmt->frame_clk_inv || - daifmt->bit_clk_master || daifmt->frame_clk_master) { - dev_err(dev, "%s: Bad flags %d %d %d %d\n", __func__, - daifmt->bit_clk_inv, daifmt->frame_clk_inv, - daifmt->bit_clk_master, - daifmt->frame_clk_master); - return -EINVAL; - } - for (i = 0; i < ARRAY_SIZE(priv->audio_port); i++) - if (priv->audio_port[i].format == AFMT_I2S) - audio.config = priv->audio_port[i].config; - audio.format = AFMT_I2S; - break; - case HDMI_SPDIF: - for (i = 0; i < ARRAY_SIZE(priv->audio_port); i++) - if (priv->audio_port[i].format == AFMT_SPDIF) - audio.config = priv->audio_port[i].config; - audio.format = AFMT_SPDIF; - break; - default: - dev_err(dev, "%s: Invalid format %d\n", __func__, daifmt->fmt); - return -EINVAL; - } - - if (audio.config == 0) { - dev_err(dev, "%s: No audio configutation found\n", __func__); - return -EINVAL; - } - - mutex_lock(&priv->audio_mutex); - ret = tda998x_configure_audio(priv, - &audio, - priv->encoder.crtc->hwmode.clock); - - if (ret == 0) - priv->audio_params = audio; - mutex_unlock(&priv->audio_mutex); - - return ret; -} - -static void tda998x_audio_shutdown(struct device *dev, void *data) -{ - struct tda998x_priv *priv = dev_get_drvdata(dev); - - mutex_lock(&priv->audio_mutex); - - reg_write(priv, REG_ENA_AP, 0); - - priv->audio_params.format = AFMT_UNUSED; - - mutex_unlock(&priv->audio_mutex); -} - -static int -tda998x_audio_digital_mute(struct device *dev, void *data, bool enable) -{ - struct tda998x_priv *priv = dev_get_drvdata(dev); - - mutex_lock(&priv->audio_mutex); - - tda998x_audio_mute(priv, enable); - - mutex_unlock(&priv->audio_mutex); - return 0; -} - -static int tda998x_audio_get_eld(struct device *dev, void *data, - uint8_t *buf, size_t len) -{ - struct tda998x_priv *priv = dev_get_drvdata(dev); - struct drm_mode_config *config = &priv->encoder.dev->mode_config; - struct drm_connector *connector; - int ret = -ENODEV; - - mutex_lock(&config->mutex); - list_for_each_entry(connector, &config->connector_list, head) { - if (&priv->encoder == connector->encoder) { - memcpy(buf, connector->eld, - min(sizeof(connector->eld), len)); - ret = 0; - } - } - mutex_unlock(&config->mutex); - - return ret; -} - -static const struct hdmi_codec_ops audio_codec_ops = { - .hw_params = tda998x_audio_hw_params, - .audio_shutdown = tda998x_audio_shutdown, - .digital_mute = tda998x_audio_digital_mute, - .get_eld = tda998x_audio_get_eld, -}; - -static int tda998x_audio_codec_init(struct tda998x_priv *priv, - struct device *dev) -{ - struct hdmi_codec_pdata codec_data = { - .ops = &audio_codec_ops, - .max_i2s_channels = 2, - }; - int i; - - for (i = 0; i < ARRAY_SIZE(priv->audio_port); i++) { - if (priv->audio_port[i].format == AFMT_I2S && - priv->audio_port[i].config != 0) - codec_data.i2s = 1; - if (priv->audio_port[i].format == AFMT_SPDIF && - priv->audio_port[i].config != 0) - codec_data.spdif = 1; - } - - priv->audio_pdev = platform_device_register_data( - dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO, - &codec_data, sizeof(codec_data)); - - return PTR_ERR_OR_ZERO(priv->audio_pdev); -} - /* I2C driver functions */ static int tda998x_get_audio_ports(struct tda998x_priv *priv, @@ -1404,22 +1483,21 @@ static int tda998x_create(struct i2c_client *client, struct tda998x_priv *priv) struct device_node *np = client->dev.of_node; u32 video; int rev_lo, rev_hi, ret; - unsigned short cec_addr; + + mutex_init(&priv->audio_mutex); /* Protect access from audio thread */ priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3); priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1); priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5); + /* CEC I2C address bound to TDA998x I2C addr by configuration pins */ + priv->cec_addr = 0x34 + (client->addr & 0x03); priv->current_page = 0xff; priv->hdmi = client; - /* CEC I2C address bound to TDA998x I2C addr by configuration pins */ - cec_addr = 0x34 + (client->addr & 0x03); - priv->cec = i2c_new_dummy(client->adapter, cec_addr); + priv->cec = i2c_new_dummy(client->adapter, priv->cec_addr); if (!priv->cec) return -ENODEV; - priv->dpms = DRM_MODE_DPMS_OFF; - mutex_init(&priv->mutex); /* protect the page access */ init_waitqueue_head(&priv->edid_delay_waitq); setup_timer(&priv->edid_delay_timer, tda998x_edid_delay_done, @@ -1479,7 +1557,7 @@ static int tda998x_create(struct i2c_client *client, struct tda998x_priv *priv) /* initialize the optional IRQ */ if (client->irq) { - int irqf_trigger; + unsigned long irq_flags; /* init read EDID waitqueue and HDP work */ init_waitqueue_head(&priv->wq_edid); @@ -1489,11 +1567,11 @@ static int tda998x_create(struct i2c_client *client, struct tda998x_priv *priv) reg_read(priv, REG_INT_FLAGS_1); reg_read(priv, REG_INT_FLAGS_2); - irqf_trigger = + irq_flags = irqd_get_trigger_type(irq_get_irq_data(client->irq)); + irq_flags |= IRQF_SHARED | IRQF_ONESHOT; ret = request_threaded_irq(client->irq, NULL, - tda998x_irq_thread, - irqf_trigger | IRQF_ONESHOT, + tda998x_irq_thread, irq_flags, "tda998x", priv); if (ret) { dev_err(&client->dev, @@ -1520,8 +1598,6 @@ static int tda998x_create(struct i2c_client *client, struct tda998x_priv *priv) priv->vip_cntrl_2 = video; } - mutex_init(&priv->audio_mutex); /* Protect access from audio thread */ - ret = tda998x_get_audio_ports(priv, np); if (ret) goto fail; @@ -1568,44 +1644,25 @@ static const struct drm_encoder_funcs tda998x_encoder_funcs = { .destroy = tda998x_encoder_destroy, }; -static struct drm_encoder * -tda998x_connector_best_encoder(struct drm_connector *connector) -{ - struct tda998x_priv *priv = conn_to_tda998x_priv(connector); - - return &priv->encoder; -} - -static -const struct drm_connector_helper_funcs tda998x_connector_helper_funcs = { - .get_modes = tda998x_connector_get_modes, - .mode_valid = tda998x_connector_mode_valid, - .best_encoder = tda998x_connector_best_encoder, -}; - -static void tda998x_connector_destroy(struct drm_connector *connector) +static void tda998x_set_config(struct tda998x_priv *priv, + const struct tda998x_encoder_params *p) { - drm_connector_cleanup(connector); -} + priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) | + (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) | + VIP_CNTRL_0_SWAP_B(p->swap_b) | + (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0); + priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) | + (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) | + VIP_CNTRL_1_SWAP_D(p->swap_d) | + (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0); + priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) | + (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) | + VIP_CNTRL_2_SWAP_F(p->swap_f) | + (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0); -static int tda998x_connector_dpms(struct drm_connector *connector, int mode) -{ - if (drm_core_check_feature(connector->dev, DRIVER_ATOMIC)) - return drm_atomic_helper_connector_dpms(connector, mode); - else - return drm_helper_connector_dpms(connector, mode); + priv->audio_params = p->audio_params; } -static const struct drm_connector_funcs tda998x_connector_funcs = { - .dpms = tda998x_connector_dpms, - .reset = drm_atomic_helper_connector_reset, - .fill_modes = drm_helper_probe_single_connector_modes, - .detect = tda998x_connector_detect, - .destroy = tda998x_connector_destroy, - .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, - .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, -}; - static int tda998x_bind(struct device *dev, struct device *master, void *data) { struct tda998x_encoder_params *params = dev->platform_data; @@ -1630,7 +1687,6 @@ static int tda998x_bind(struct device *dev, struct device *master, void *data) crtcs = 1 << 0; } - priv->connector.interlace_allowed = 1; priv->encoder.possible_crtcs = crtcs; ret = tda998x_create(client, priv); @@ -1638,9 +1694,7 @@ static int tda998x_bind(struct device *dev, struct device *master, void *data) return ret; if (!dev->of_node && params) - tda998x_encoder_set_config(priv, params); - - tda998x_encoder_set_polling(priv, &priv->connector); + tda998x_set_config(priv, params); drm_encoder_helper_add(&priv->encoder, &tda998x_encoder_helper_funcs); ret = drm_encoder_init(drm, &priv->encoder, &tda998x_encoder_funcs, @@ -1648,16 +1702,10 @@ static int tda998x_bind(struct device *dev, struct device *master, void *data) if (ret) goto err_encoder; - drm_connector_helper_add(&priv->connector, - &tda998x_connector_helper_funcs); - ret = drm_connector_init(drm, &priv->connector, - &tda998x_connector_funcs, - DRM_MODE_CONNECTOR_HDMIA); + ret = tda998x_connector_init(priv, drm); if (ret) goto err_connector; - drm_mode_connector_attach_encoder(&priv->connector, &priv->encoder); - return 0; err_connector: @@ -1685,6 +1733,10 @@ static const struct component_ops tda998x_ops = { static int tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id) { + if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { + dev_warn(&client->dev, "adapter does not support I2C\n"); + return -EIO; + } return component_add(&client->dev, &tda998x_ops); } diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig index df96aed6975a..5ddde7349fbd 100644 --- a/drivers/gpu/drm/i915/Kconfig +++ b/drivers/gpu/drm/i915/Kconfig @@ -36,15 +36,20 @@ config DRM_I915 If "M" is selected, the module will be called i915. -config DRM_I915_PRELIMINARY_HW_SUPPORT - bool "Enable preliminary support for prerelease Intel hardware by default" +config DRM_I915_ALPHA_SUPPORT + bool "Enable alpha quality support for new Intel hardware by default" depends on DRM_I915 default n help - Choose this option if you have prerelease Intel hardware and want the - i915 driver to support it by default. You can enable such support at - runtime with the module option i915.preliminary_hw_support=1; this - option changes the default for that module option. + Choose this option if you have new Intel hardware and want to enable + the alpha quality i915 driver support for the hardware in this kernel + version. You can also enable the support at runtime using the module + parameter i915.alpha_support=1; this option changes the default for + that module parameter. + + It is recommended to upgrade to a kernel version with proper support + as soon as it is available. Generally fixes for platforms with alpha + support are not backported to older kernels. If in doubt, say "N". @@ -107,6 +112,15 @@ config DRM_I915_GVT If in doubt, say "N". +config DRM_I915_GVT_KVMGT + tristate "Enable KVM/VFIO support for Intel GVT-g" + depends on DRM_I915_GVT + depends on KVM + default n + help + Choose this option if you want to enable KVMGT support for + Intel GVT-g. + menu "drm/i915 Debugging" depends on DRM_I915 depends on EXPERT diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 0857e5035f4d..3dea46af9fe6 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -33,7 +33,7 @@ i915-y += i915_cmd_parser.o \ i915_gem_dmabuf.o \ i915_gem_evict.o \ i915_gem_execbuffer.o \ - i915_gem_fence.o \ + i915_gem_fence_reg.o \ i915_gem_gtt.o \ i915_gem_internal.o \ i915_gem.o \ @@ -45,6 +45,7 @@ i915-y += i915_cmd_parser.o \ i915_gem_timeline.o \ i915_gem_userptr.o \ i915_trace_points.o \ + i915_vma.o \ intel_breadcrumbs.o \ intel_engine_cs.o \ intel_hangcheck.o \ diff --git a/drivers/gpu/drm/i915/gvt/Makefile b/drivers/gpu/drm/i915/gvt/Makefile index 34ea4776af70..8a46a7f31d53 100644 --- a/drivers/gpu/drm/i915/gvt/Makefile +++ b/drivers/gpu/drm/i915/gvt/Makefile @@ -3,5 +3,8 @@ GVT_SOURCE := gvt.o aperture_gm.o handlers.o vgpu.o trace_points.o firmware.o \ interrupt.o gtt.o cfg_space.o opregion.o mmio.o display.o edid.o \ execlist.o scheduler.o sched_policy.o render.o cmd_parser.o -ccflags-y += -I$(src) -I$(src)/$(GVT_DIR) -Wall -i915-y += $(addprefix $(GVT_DIR)/, $(GVT_SOURCE)) +ccflags-y += -I$(src) -I$(src)/$(GVT_DIR) -Wall +i915-y += $(addprefix $(GVT_DIR)/, $(GVT_SOURCE)) + +CFLAGS_kvmgt.o := -Wno-unused-function +obj-$(CONFIG_DRM_I915_GVT_KVMGT) += $(GVT_DIR)/kvmgt.o diff --git a/drivers/gpu/drm/i915/gvt/cfg_space.c b/drivers/gpu/drm/i915/gvt/cfg_space.c index 4c687740f5f1..db516382a4d4 100644 --- a/drivers/gpu/drm/i915/gvt/cfg_space.c +++ b/drivers/gpu/drm/i915/gvt/cfg_space.c @@ -47,11 +47,9 @@ enum { * Returns: * Zero on success, negative error code if failed. */ -int intel_vgpu_emulate_cfg_read(void *__vgpu, unsigned int offset, +int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { - struct intel_vgpu *vgpu = __vgpu; - if (WARN_ON(bytes > 4)) return -EINVAL; @@ -82,9 +80,8 @@ static int map_aperture(struct intel_vgpu *vgpu, bool map) ret = intel_gvt_hypervisor_map_gfn_to_mfn(vgpu, first_gfn, first_mfn, - vgpu_aperture_sz(vgpu) - >> PAGE_SHIFT, map, - GVT_MAP_APERTURE); + vgpu_aperture_sz(vgpu) >> + PAGE_SHIFT, map); if (ret) return ret; @@ -235,10 +232,9 @@ static int emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset, * Returns: * Zero on success, negative error code if failed. */ -int intel_vgpu_emulate_cfg_write(void *__vgpu, unsigned int offset, +int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { - struct intel_vgpu *vgpu = __vgpu; int ret; if (WARN_ON(bytes > 4)) diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c index 0084ece8d8ff..d26a092c70e8 100644 --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c @@ -1418,8 +1418,8 @@ static int cmd_handler_mi_op_2e(struct parser_exec_state *s) static int cmd_handler_mi_op_2f(struct parser_exec_state *s) { int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd; - int op_size = ((1 << (cmd_val(s, 0) & GENMASK(20, 19) >> 19)) * - sizeof(u32)); + int op_size = (1 << ((cmd_val(s, 0) & GENMASK(20, 19)) >> 19)) * + sizeof(u32); unsigned long gma, gma_high; int ret = 0; @@ -2537,7 +2537,8 @@ static int scan_workload(struct intel_vgpu_workload *workload) s.rb_va = workload->shadow_ring_buffer_va; s.workload = workload; - if (bypass_scan_mask & (1 << workload->ring_id)) + if ((bypass_scan_mask & (1 << workload->ring_id)) || + gma_head == gma_tail) return 0; ret = ip_gma_set(&s, gma_head); diff --git a/drivers/gpu/drm/i915/gvt/edid.c b/drivers/gpu/drm/i915/gvt/edid.c index 7e1da1c563ca..bda85dff7b2a 100644 --- a/drivers/gpu/drm/i915/gvt/edid.c +++ b/drivers/gpu/drm/i915/gvt/edid.c @@ -502,8 +502,7 @@ void intel_gvt_i2c_handle_aux_ch_write(struct intel_vgpu *vgpu, * ACK of I2C_WRITE * returned byte if it is READ */ - - aux_data_for_write |= (GVT_AUX_I2C_REPLY_ACK & 0xff) << 24; + aux_data_for_write |= GVT_AUX_I2C_REPLY_ACK << 24; vgpu_vreg(vgpu, offset + 4) = aux_data_for_write; } diff --git a/drivers/gpu/drm/i915/gvt/edid.h b/drivers/gpu/drm/i915/gvt/edid.h index de366b1d5196..f6dfc8b795ec 100644 --- a/drivers/gpu/drm/i915/gvt/edid.h +++ b/drivers/gpu/drm/i915/gvt/edid.h @@ -44,7 +44,7 @@ #define GVT_AUX_I2C_READ 0x1 #define GVT_AUX_I2C_STATUS 0x2 #define GVT_AUX_I2C_MOT 0x4 -#define GVT_AUX_I2C_REPLY_ACK (0x0 << 6) +#define GVT_AUX_I2C_REPLY_ACK 0x0 struct intel_vgpu_edid_data { bool data_valid; diff --git a/drivers/gpu/drm/i915/gvt/execlist.c b/drivers/gpu/drm/i915/gvt/execlist.c index c1f6019d8895..f32bb6f6495c 100644 --- a/drivers/gpu/drm/i915/gvt/execlist.c +++ b/drivers/gpu/drm/i915/gvt/execlist.c @@ -838,23 +838,21 @@ int intel_vgpu_init_execlist(struct intel_vgpu *vgpu) } void intel_vgpu_reset_execlist(struct intel_vgpu *vgpu, - unsigned long ring_bitmap) + unsigned long engine_mask) { - int bit; - struct list_head *pos, *n; - struct intel_vgpu_workload *workload = NULL; + struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; + struct intel_engine_cs *engine; + struct intel_vgpu_workload *pos, *n; + unsigned int tmp; - for_each_set_bit(bit, &ring_bitmap, sizeof(ring_bitmap) * 8) { - if (bit >= I915_NUM_ENGINES) - break; + for_each_engine_masked(engine, dev_priv, engine_mask, tmp) { /* free the unsubmited workload in the queue */ - list_for_each_safe(pos, n, &vgpu->workload_q_head[bit]) { - workload = container_of(pos, - struct intel_vgpu_workload, list); - list_del_init(&workload->list); - free_workload(workload); + list_for_each_entry_safe(pos, n, + &vgpu->workload_q_head[engine->id], list) { + list_del_init(&pos->list); + free_workload(pos); } - init_vgpu_execlist(vgpu, bit); + init_vgpu_execlist(vgpu, engine->id); } } diff --git a/drivers/gpu/drm/i915/gvt/execlist.h b/drivers/gpu/drm/i915/gvt/execlist.h index 635f31c6dcc1..7eced40a1e30 100644 --- a/drivers/gpu/drm/i915/gvt/execlist.h +++ b/drivers/gpu/drm/i915/gvt/execlist.h @@ -183,6 +183,6 @@ int intel_vgpu_init_execlist(struct intel_vgpu *vgpu); int intel_vgpu_submit_execlist(struct intel_vgpu *vgpu, int ring_id); void intel_vgpu_reset_execlist(struct intel_vgpu *vgpu, - unsigned long ring_bitmap); + unsigned long engine_mask); #endif /*_GVT_EXECLIST_H_*/ diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c index 6554da9f9f5b..7eaaf1c9ed2b 100644 --- a/drivers/gpu/drm/i915/gvt/gtt.c +++ b/drivers/gpu/drm/i915/gvt/gtt.c @@ -138,36 +138,6 @@ int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index, memcpy(&(e)->val64, &v, sizeof(v)); \ } while (0) -enum { - GTT_TYPE_INVALID = -1, - - GTT_TYPE_GGTT_PTE, - - GTT_TYPE_PPGTT_PTE_4K_ENTRY, - GTT_TYPE_PPGTT_PTE_2M_ENTRY, - GTT_TYPE_PPGTT_PTE_1G_ENTRY, - - GTT_TYPE_PPGTT_PTE_ENTRY, - - GTT_TYPE_PPGTT_PDE_ENTRY, - GTT_TYPE_PPGTT_PDP_ENTRY, - GTT_TYPE_PPGTT_PML4_ENTRY, - - GTT_TYPE_PPGTT_ROOT_ENTRY, - - GTT_TYPE_PPGTT_ROOT_L3_ENTRY, - GTT_TYPE_PPGTT_ROOT_L4_ENTRY, - - GTT_TYPE_PPGTT_ENTRY, - - GTT_TYPE_PPGTT_PTE_PT, - GTT_TYPE_PPGTT_PDE_PT, - GTT_TYPE_PPGTT_PDP_PT, - GTT_TYPE_PPGTT_PML4_PT, - - GTT_TYPE_MAX, -}; - /* * Mappings between GTT_TYPE* enumerations. * Following information can be found according to the given type: @@ -842,13 +812,18 @@ static int ppgtt_invalidate_shadow_page_by_shadow_entry(struct intel_vgpu *vgpu, { struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops; struct intel_vgpu_ppgtt_spt *s; + intel_gvt_gtt_type_t cur_pt_type; if (WARN_ON(!gtt_type_is_pt(get_next_pt_type(e->type)))) return -EINVAL; - if (ops->get_pfn(e) == vgpu->gtt.scratch_page_mfn) - return 0; - + if (e->type != GTT_TYPE_PPGTT_ROOT_L3_ENTRY + && e->type != GTT_TYPE_PPGTT_ROOT_L4_ENTRY) { + cur_pt_type = get_next_pt_type(e->type) + 1; + if (ops->get_pfn(e) == + vgpu->gtt.scratch_pt[cur_pt_type].page_mfn) + return 0; + } s = ppgtt_find_shadow_page(vgpu, ops->get_pfn(e)); if (!s) { gvt_err("vgpu%d: fail to find shadow page: mfn: 0x%lx\n", @@ -999,7 +974,7 @@ fail: } static int ppgtt_handle_guest_entry_removal(struct intel_vgpu_guest_page *gpt, - struct intel_gvt_gtt_entry *we, unsigned long index) + unsigned long index) { struct intel_vgpu_ppgtt_spt *spt = guest_page_to_ppgtt_spt(gpt); struct intel_vgpu_shadow_page *sp = &spt->shadow_page; @@ -1008,34 +983,35 @@ static int ppgtt_handle_guest_entry_removal(struct intel_vgpu_guest_page *gpt, struct intel_gvt_gtt_entry e; int ret; - trace_gpt_change(spt->vgpu->id, "remove", spt, sp->type, - we->val64, index); - ppgtt_get_shadow_entry(spt, &e, index); + + trace_gpt_change(spt->vgpu->id, "remove", spt, sp->type, e.val64, + index); + if (!ops->test_present(&e)) return 0; - if (ops->get_pfn(&e) == vgpu->gtt.scratch_page_mfn) + if (ops->get_pfn(&e) == vgpu->gtt.scratch_pt[sp->type].page_mfn) return 0; - if (gtt_type_is_pt(get_next_pt_type(we->type))) { - struct intel_vgpu_guest_page *g = - intel_vgpu_find_guest_page(vgpu, ops->get_pfn(we)); - if (!g) { + if (gtt_type_is_pt(get_next_pt_type(e.type))) { + struct intel_vgpu_ppgtt_spt *s = + ppgtt_find_shadow_page(vgpu, ops->get_pfn(&e)); + if (!s) { gvt_err("fail to find guest page\n"); ret = -ENXIO; goto fail; } - ret = ppgtt_invalidate_shadow_page(guest_page_to_ppgtt_spt(g)); + ret = ppgtt_invalidate_shadow_page(s); if (ret) goto fail; } - ops->set_pfn(&e, vgpu->gtt.scratch_page_mfn); + ops->set_pfn(&e, vgpu->gtt.scratch_pt[sp->type].page_mfn); ppgtt_set_shadow_entry(spt, &e, index); return 0; fail: gvt_err("vgpu%d: fail: shadow page %p guest entry 0x%llx type %d\n", - vgpu->id, spt, we->val64, we->type); + vgpu->id, spt, e.val64, e.type); return ret; } @@ -1256,23 +1232,16 @@ static int ppgtt_handle_guest_write_page_table( struct intel_vgpu_ppgtt_spt *spt = guest_page_to_ppgtt_spt(gpt); struct intel_vgpu *vgpu = spt->vgpu; struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops; - struct intel_gvt_gtt_entry ge; - int old_present, new_present; int ret; + int new_present; - ppgtt_get_guest_entry(spt, &ge, index); - - old_present = ops->test_present(&ge); new_present = ops->test_present(we); - ppgtt_set_guest_entry(spt, we, index); + ret = ppgtt_handle_guest_entry_removal(gpt, index); + if (ret) + goto fail; - if (old_present) { - ret = ppgtt_handle_guest_entry_removal(gpt, &ge, index); - if (ret) - goto fail; - } if (new_present) { ret = ppgtt_handle_guest_entry_add(gpt, we, index); if (ret) @@ -1318,7 +1287,7 @@ int intel_vgpu_flush_post_shadow(struct intel_vgpu *vgpu) { struct list_head *pos, *n; struct intel_vgpu_ppgtt_spt *spt; - struct intel_gvt_gtt_entry ge, e; + struct intel_gvt_gtt_entry ge; unsigned long index; int ret; @@ -1329,9 +1298,6 @@ int intel_vgpu_flush_post_shadow(struct intel_vgpu *vgpu) for_each_set_bit(index, spt->post_shadow_bitmap, GTT_ENTRY_NUM_IN_ONE_PAGE) { ppgtt_get_guest_entry(spt, &ge, index); - e = ge; - e.val64 = 0; - ppgtt_set_guest_entry(spt, &e, index); ret = ppgtt_handle_guest_write_page_table( &spt->guest_page, &ge, index); @@ -1359,8 +1325,6 @@ static int ppgtt_handle_guest_write_page_table_bytes(void *gp, index = (pa & (PAGE_SIZE - 1)) >> info->gtt_entry_size_shift; ppgtt_get_guest_entry(spt, &we, index); - memcpy((void *)&we.val64 + (pa & (info->gtt_entry_size - 1)), - p_data, bytes); ops->test_pse(&we); @@ -1369,19 +1333,13 @@ static int ppgtt_handle_guest_write_page_table_bytes(void *gp, if (ret) return ret; } else { - struct intel_gvt_gtt_entry ge; - - ppgtt_get_guest_entry(spt, &ge, index); - if (!test_bit(index, spt->post_shadow_bitmap)) { - ret = ppgtt_handle_guest_entry_removal(gpt, - &ge, index); + ret = ppgtt_handle_guest_entry_removal(gpt, index); if (ret) return ret; } ppgtt_set_post_shadow(spt, index); - ppgtt_set_guest_entry(spt, &we, index); } if (!enable_out_of_sync) @@ -1921,47 +1879,101 @@ int intel_vgpu_emulate_gtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off, return ret; } -static int create_scratch_page(struct intel_vgpu *vgpu) +static int alloc_scratch_pages(struct intel_vgpu *vgpu, + intel_gvt_gtt_type_t type) { struct intel_vgpu_gtt *gtt = &vgpu->gtt; - void *p; - void *vaddr; + struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops; + int page_entry_num = GTT_PAGE_SIZE >> + vgpu->gvt->device_info.gtt_entry_size_shift; + struct page *scratch_pt; unsigned long mfn; + int i; + void *p; + + if (WARN_ON(type < GTT_TYPE_PPGTT_PTE_PT || type >= GTT_TYPE_MAX)) + return -EINVAL; - gtt->scratch_page = alloc_page(GFP_KERNEL); - if (!gtt->scratch_page) { - gvt_err("Failed to allocate scratch page.\n"); + scratch_pt = alloc_page(GFP_KERNEL | GFP_ATOMIC | __GFP_ZERO); + if (!scratch_pt) { + gvt_err("fail to allocate scratch page\n"); return -ENOMEM; } - /* set to zero */ - p = kmap_atomic(gtt->scratch_page); - memset(p, 0, PAGE_SIZE); + p = kmap_atomic(scratch_pt); + mfn = intel_gvt_hypervisor_virt_to_mfn(p); + if (mfn == INTEL_GVT_INVALID_ADDR) { + gvt_err("fail to translate vaddr:0x%llx\n", (u64)p); + kunmap_atomic(p); + __free_page(scratch_pt); + return -EFAULT; + } + gtt->scratch_pt[type].page_mfn = mfn; + gtt->scratch_pt[type].page = scratch_pt; + gvt_dbg_mm("vgpu%d create scratch_pt: type %d mfn=0x%lx\n", + vgpu->id, type, mfn); + + /* Build the tree by full filled the scratch pt with the entries which + * point to the next level scratch pt or scratch page. The + * scratch_pt[type] indicate the scratch pt/scratch page used by the + * 'type' pt. + * e.g. scratch_pt[GTT_TYPE_PPGTT_PDE_PT] is used by + * GTT_TYPE_PPGTT_PDE_PT level pt, that means this scatch_pt it self + * is GTT_TYPE_PPGTT_PTE_PT, and full filled by scratch page mfn. + */ + if (type > GTT_TYPE_PPGTT_PTE_PT && type < GTT_TYPE_MAX) { + struct intel_gvt_gtt_entry se; + + memset(&se, 0, sizeof(struct intel_gvt_gtt_entry)); + se.type = get_entry_type(type - 1); + ops->set_pfn(&se, gtt->scratch_pt[type - 1].page_mfn); + + /* The entry parameters like present/writeable/cache type + * set to the same as i915's scratch page tree. + */ + se.val64 |= _PAGE_PRESENT | _PAGE_RW; + if (type == GTT_TYPE_PPGTT_PDE_PT) + se.val64 |= PPAT_CACHED_INDEX; + + for (i = 0; i < page_entry_num; i++) + ops->set_entry(p, &se, i, false, 0, vgpu); + } + kunmap_atomic(p); - /* translate page to mfn */ - vaddr = page_address(gtt->scratch_page); - mfn = intel_gvt_hypervisor_virt_to_mfn(vaddr); + return 0; +} + +static int release_scratch_page_tree(struct intel_vgpu *vgpu) +{ + int i; - if (mfn == INTEL_GVT_INVALID_ADDR) { - gvt_err("fail to translate vaddr: 0x%p\n", vaddr); - __free_page(gtt->scratch_page); - gtt->scratch_page = NULL; - return -ENXIO; + for (i = GTT_TYPE_PPGTT_PTE_PT; i < GTT_TYPE_MAX; i++) { + if (vgpu->gtt.scratch_pt[i].page != NULL) { + __free_page(vgpu->gtt.scratch_pt[i].page); + vgpu->gtt.scratch_pt[i].page = NULL; + vgpu->gtt.scratch_pt[i].page_mfn = 0; + } } - gtt->scratch_page_mfn = mfn; - gvt_dbg_core("vgpu%d create scratch page: mfn=0x%lx\n", vgpu->id, mfn); return 0; } -static void release_scratch_page(struct intel_vgpu *vgpu) +static int create_scratch_page_tree(struct intel_vgpu *vgpu) { - if (vgpu->gtt.scratch_page != NULL) { - __free_page(vgpu->gtt.scratch_page); - vgpu->gtt.scratch_page = NULL; - vgpu->gtt.scratch_page_mfn = 0; + int i, ret; + + for (i = GTT_TYPE_PPGTT_PTE_PT; i < GTT_TYPE_MAX; i++) { + ret = alloc_scratch_pages(vgpu, i); + if (ret) + goto err; } + + return 0; + +err: + release_scratch_page_tree(vgpu); + return ret; } /** @@ -1995,7 +2007,7 @@ int intel_vgpu_init_gtt(struct intel_vgpu *vgpu) gtt->ggtt_mm = ggtt_mm; - return create_scratch_page(vgpu); + return create_scratch_page_tree(vgpu); } /** @@ -2014,7 +2026,7 @@ void intel_vgpu_clean_gtt(struct intel_vgpu *vgpu) struct intel_vgpu_mm *mm; ppgtt_free_all_shadow_page(vgpu); - release_scratch_page(vgpu); + release_scratch_page_tree(vgpu); list_for_each_safe(pos, n, &vgpu->gtt.mm_list_head) { mm = container_of(pos, struct intel_vgpu_mm, list); diff --git a/drivers/gpu/drm/i915/gvt/gtt.h b/drivers/gpu/drm/i915/gvt/gtt.h index e4dcde78f3f9..d250013bc37b 100644 --- a/drivers/gpu/drm/i915/gvt/gtt.h +++ b/drivers/gpu/drm/i915/gvt/gtt.h @@ -88,6 +88,36 @@ enum { INTEL_GVT_MM_PPGTT, }; +typedef enum { + GTT_TYPE_INVALID = -1, + + GTT_TYPE_GGTT_PTE, + + GTT_TYPE_PPGTT_PTE_4K_ENTRY, + GTT_TYPE_PPGTT_PTE_2M_ENTRY, + GTT_TYPE_PPGTT_PTE_1G_ENTRY, + + GTT_TYPE_PPGTT_PTE_ENTRY, + + GTT_TYPE_PPGTT_PDE_ENTRY, + GTT_TYPE_PPGTT_PDP_ENTRY, + GTT_TYPE_PPGTT_PML4_ENTRY, + + GTT_TYPE_PPGTT_ROOT_ENTRY, + + GTT_TYPE_PPGTT_ROOT_L3_ENTRY, + GTT_TYPE_PPGTT_ROOT_L4_ENTRY, + + GTT_TYPE_PPGTT_ENTRY, + + GTT_TYPE_PPGTT_PTE_PT, + GTT_TYPE_PPGTT_PDE_PT, + GTT_TYPE_PPGTT_PDP_PT, + GTT_TYPE_PPGTT_PML4_PT, + + GTT_TYPE_MAX, +} intel_gvt_gtt_type_t; + struct intel_vgpu_mm { int type; bool initialized; @@ -151,6 +181,12 @@ extern void intel_vgpu_destroy_mm(struct kref *mm_ref); struct intel_vgpu_guest_page; +struct intel_vgpu_scratch_pt { + struct page *page; + unsigned long page_mfn; +}; + + struct intel_vgpu_gtt { struct intel_vgpu_mm *ggtt_mm; unsigned long active_ppgtt_mm_bitmap; @@ -160,8 +196,8 @@ struct intel_vgpu_gtt { atomic_t n_write_protected_guest_page; struct list_head oos_page_list_head; struct list_head post_shadow_list_head; - struct page *scratch_page; - unsigned long scratch_page_mfn; + struct intel_vgpu_scratch_pt scratch_pt[GTT_TYPE_MAX]; + }; extern int intel_vgpu_init_gtt(struct intel_vgpu *vgpu); diff --git a/drivers/gpu/drm/i915/gvt/gvt.c b/drivers/gpu/drm/i915/gvt/gvt.c index 385969a89216..398877c3d2fd 100644 --- a/drivers/gpu/drm/i915/gvt/gvt.c +++ b/drivers/gpu/drm/i915/gvt/gvt.c @@ -44,11 +44,14 @@ static const char * const supported_hypervisors[] = { [INTEL_GVT_HYPERVISOR_KVM] = "KVM", }; -struct intel_gvt_io_emulation_ops intel_gvt_io_emulation_ops = { +static const struct intel_gvt_ops intel_gvt_ops = { .emulate_cfg_read = intel_vgpu_emulate_cfg_read, .emulate_cfg_write = intel_vgpu_emulate_cfg_write, .emulate_mmio_read = intel_vgpu_emulate_mmio_read, .emulate_mmio_write = intel_vgpu_emulate_mmio_write, + .vgpu_create = intel_gvt_create_vgpu, + .vgpu_destroy = intel_gvt_destroy_vgpu, + .vgpu_reset = intel_gvt_reset_vgpu, }; /** @@ -81,10 +84,12 @@ int intel_gvt_init_host(void) symbol_get(xengt_mpt), "xengt"); intel_gvt_host.hypervisor_type = INTEL_GVT_HYPERVISOR_XEN; } else { +#if IS_ENABLED(CONFIG_DRM_I915_GVT_KVMGT) /* not in Xen. Try KVMGT */ intel_gvt_host.mpt = try_then_request_module( - symbol_get(kvmgt_mpt), "kvm"); + symbol_get(kvmgt_mpt), "kvmgt"); intel_gvt_host.hypervisor_type = INTEL_GVT_HYPERVISOR_KVM; +#endif } /* Fail to load MPT modules - bail out */ @@ -193,6 +198,9 @@ void intel_gvt_clean_device(struct drm_i915_private *dev_priv) intel_gvt_clean_mmio_info(gvt); intel_gvt_free_firmware(gvt); + intel_gvt_hypervisor_host_exit(&dev_priv->drm.pdev->dev, gvt); + intel_gvt_clean_vgpu_types(gvt); + kfree(dev_priv->gvt); dev_priv->gvt = NULL; } @@ -270,10 +278,25 @@ int intel_gvt_init_device(struct drm_i915_private *dev_priv) if (ret) goto out_clean_cmd_parser; - gvt_dbg_core("gvt device creation is done\n"); + ret = intel_gvt_init_vgpu_types(gvt); + if (ret) + goto out_clean_thread; + + ret = intel_gvt_hypervisor_host_init(&dev_priv->drm.pdev->dev, gvt, + &intel_gvt_ops); + if (ret) { + gvt_err("failed to register gvt-g host device: %d\n", ret); + goto out_clean_types; + } + + gvt_dbg_core("gvt device initialization is done\n"); dev_priv->gvt = gvt; return 0; +out_clean_types: + intel_gvt_clean_vgpu_types(gvt); +out_clean_thread: + clean_service_thread(gvt); out_clean_cmd_parser: intel_gvt_clean_cmd_parser(gvt); out_clean_sched_policy: diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h index 62fc9e3ac5c6..3d4223e8ebe3 100644 --- a/drivers/gpu/drm/i915/gvt/gvt.h +++ b/drivers/gpu/drm/i915/gvt/gvt.h @@ -161,6 +161,20 @@ struct intel_vgpu { DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES); struct i915_gem_context *shadow_ctx; struct notifier_block shadow_ctx_notifier_block; + +#if IS_ENABLED(CONFIG_DRM_I915_GVT_KVMGT) + struct { + struct device *mdev; + struct vfio_region *region; + int num_regions; + struct eventfd_ctx *intx_trigger; + struct eventfd_ctx *msi_trigger; + struct rb_root cache; + struct mutex cache_lock; + void *vfio_group; + struct notifier_block iommu_notifier; + } vdev; +#endif }; struct intel_gvt_gm { @@ -190,6 +204,16 @@ struct intel_gvt_opregion { u32 opregion_pa; }; +#define NR_MAX_INTEL_VGPU_TYPES 20 +struct intel_vgpu_type { + char name[16]; + unsigned int max_instance; + unsigned int avail_instance; + unsigned int low_gm_size; + unsigned int high_gm_size; + unsigned int fence; +}; + struct intel_gvt { struct mutex lock; struct drm_i915_private *dev_priv; @@ -205,6 +229,8 @@ struct intel_gvt { struct intel_gvt_opregion opregion; struct intel_gvt_workload_scheduler scheduler; DECLARE_HASHTABLE(cmd_table, GVT_CMD_HASH_BITS); + struct intel_vgpu_type *types; + unsigned int num_types; struct task_struct *service_thread; wait_queue_head_t service_thread_wq; @@ -231,6 +257,14 @@ void intel_gvt_free_firmware(struct intel_gvt *gvt); int intel_gvt_load_firmware(struct intel_gvt *gvt); /* Aperture/GM space definitions for GVT device */ +#define MB_TO_BYTES(mb) ((mb) << 20ULL) +#define BYTES_TO_MB(b) ((b) >> 20ULL) + +#define HOST_LOW_GM_SIZE MB_TO_BYTES(128) +#define HOST_HIGH_GM_SIZE MB_TO_BYTES(384) +#define HOST_FENCE 4 + +/* Aperture/GM space definitions for GVT device */ #define gvt_aperture_sz(gvt) (gvt->dev_priv->ggtt.mappable_end) #define gvt_aperture_pa_base(gvt) (gvt->dev_priv->ggtt.mappable_base) @@ -330,11 +364,14 @@ static inline void intel_vgpu_write_pci_bar(struct intel_vgpu *vgpu, } } -struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt, - struct intel_vgpu_creation_params * - param); +int intel_gvt_init_vgpu_types(struct intel_gvt *gvt); +void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt); +struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt, + struct intel_vgpu_type *type); void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu); +void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu); + /* validating GM functions */ #define vgpu_gmadr_is_aperture(vgpu, gmadr) \ @@ -369,10 +406,10 @@ int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index, int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index, unsigned long *g_index); -int intel_vgpu_emulate_cfg_read(void *__vgpu, unsigned int offset, +int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes); -int intel_vgpu_emulate_cfg_write(void *__vgpu, unsigned int offset, +int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes); void intel_gvt_clean_opregion(struct intel_gvt *gvt); @@ -385,6 +422,22 @@ int intel_vgpu_emulate_opregion_request(struct intel_vgpu *vgpu, u32 swsci); int setup_vgpu_mmio(struct intel_vgpu *vgpu); void populate_pvinfo_page(struct intel_vgpu *vgpu); +struct intel_gvt_ops { + int (*emulate_cfg_read)(struct intel_vgpu *, unsigned int, void *, + unsigned int); + int (*emulate_cfg_write)(struct intel_vgpu *, unsigned int, void *, + unsigned int); + int (*emulate_mmio_read)(struct intel_vgpu *, u64, void *, + unsigned int); + int (*emulate_mmio_write)(struct intel_vgpu *, u64, void *, + unsigned int); + struct intel_vgpu *(*vgpu_create)(struct intel_gvt *, + struct intel_vgpu_type *); + void (*vgpu_destroy)(struct intel_vgpu *); + void (*vgpu_reset)(struct intel_vgpu *); +}; + + #include "mpt.h" #endif diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 9ab1f95dddc5..522809710312 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -1158,7 +1158,10 @@ static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu, static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { - u32 mode = *(u32 *)p_data; + u32 mode; + + write_vreg(vgpu, offset, p_data, bytes); + mode = vgpu_vreg(vgpu, offset); if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) { WARN_ONCE(1, "VM(%d): iGVT-g doesn't supporte GuC\n", @@ -1275,19 +1278,18 @@ static int skl_misc_ctl_write(struct intel_vgpu *vgpu, unsigned int offset, switch (offset) { case 0x4ddc: vgpu_vreg(vgpu, offset) = 0x8000003c; + /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl */ + I915_WRITE(reg, vgpu_vreg(vgpu, offset)); break; case 0x42080: vgpu_vreg(vgpu, offset) = 0x8000; + /* WaCompressedResourceDisplayNewHashMode:skl */ + I915_WRITE(reg, vgpu_vreg(vgpu, offset)); break; default: return -EINVAL; } - /** - * TODO: need detect stepping info after gvt contain such information - * 0x4ddc enabled after C0, 0x42080 enabled after E0. - */ - I915_WRITE(reg, vgpu_vreg(vgpu, offset)); return 0; } @@ -1367,6 +1369,9 @@ static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu, int rc = 0; unsigned int id = 0; + write_vreg(vgpu, offset, p_data, bytes); + vgpu_vreg(vgpu, offset) = 0; + switch (offset) { case 0x4260: id = RCS; @@ -1392,6 +1397,23 @@ static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu, return rc; } +static int ring_reset_ctl_write(struct intel_vgpu *vgpu, + unsigned int offset, void *p_data, unsigned int bytes) +{ + u32 data; + + write_vreg(vgpu, offset, p_data, bytes); + data = vgpu_vreg(vgpu, offset); + + if (data & _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET)) + data |= RESET_CTL_READY_TO_RESET; + else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET)) + data &= ~RESET_CTL_READY_TO_RESET; + + vgpu_vreg(vgpu, offset) = data; + return 0; +} + #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \ ret = new_mmio_info(gvt, INTEL_GVT_MMIO_OFFSET(reg), \ f, s, am, rm, d, r, w); \ @@ -1485,7 +1507,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK, NULL, NULL); MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK, NULL, NULL); - MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK, NULL, NULL); + MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); MMIO_DFH(0x20dc, D_ALL, F_MODE_MASK, NULL, NULL); MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK, NULL, NULL); @@ -1494,7 +1516,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) MMIO_DFH(0x2470, D_ALL, F_MODE_MASK, NULL, NULL); MMIO_D(GAM_ECOCHK, D_ALL); MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK, NULL, NULL); - MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK, NULL, NULL); + MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); MMIO_D(0x9030, D_ALL); MMIO_D(0x20a0, D_ALL); MMIO_D(0x2420, D_ALL); @@ -1503,7 +1525,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) MMIO_D(0x2438, D_ALL); MMIO_D(0x243c, D_ALL); MMIO_DFH(0x7018, D_ALL, F_MODE_MASK, NULL, NULL); - MMIO_DFH(0xe184, D_ALL, F_MODE_MASK, NULL, NULL); + MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); MMIO_DFH(0xe100, D_ALL, F_MODE_MASK, NULL, NULL); /* display */ @@ -2116,6 +2138,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) MMIO_D(GEN6_MBCTL, D_ALL); MMIO_D(0x911c, D_ALL); MMIO_D(0x9120, D_ALL); + MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL); MMIO_D(GAB_CTL, D_ALL); MMIO_D(0x48800, D_ALL); @@ -2298,6 +2321,15 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt) MMIO_RING_D(RING_ACTHD_UDW, D_BDW_PLUS); +#define RING_REG(base) (base + 0xd0) + MMIO_RING_F(RING_REG, 4, F_RO, 0, + ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL, + ring_reset_ctl_write); + MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 4, F_RO, 0, + ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL, + ring_reset_ctl_write); +#undef RING_REG + #define RING_REG(base) (base + 0x230) MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write); MMIO_DH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, elsp_mmio_write); @@ -2345,7 +2377,7 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt) MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, NULL); MMIO_GM(0x1c080, D_BDW_PLUS, NULL, NULL); - MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); + MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW); MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW); @@ -2364,7 +2396,7 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt) MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS); MMIO_D(0xfdc, D_BDW); - MMIO_D(GEN8_ROW_CHICKEN, D_BDW_PLUS); + MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); MMIO_D(GEN7_ROW_CHICKEN2, D_BDW_PLUS); MMIO_D(GEN8_UCGCTL6, D_BDW_PLUS); @@ -2375,10 +2407,10 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt) MMIO_D(0xb10c, D_BDW); MMIO_D(0xb110, D_BDW); - MMIO_DH(0x24d0, D_BDW_PLUS, NULL, NULL); - MMIO_DH(0x24d4, D_BDW_PLUS, NULL, NULL); - MMIO_DH(0x24d8, D_BDW_PLUS, NULL, NULL); - MMIO_DH(0x24dc, D_BDW_PLUS, NULL, NULL); + MMIO_DFH(0x24d0, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); + MMIO_DFH(0x24d4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); + MMIO_DFH(0x24d8, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); + MMIO_DFH(0x24dc, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); MMIO_D(0x83a4, D_BDW); MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS); @@ -2392,9 +2424,9 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt) MMIO_D(0x6e570, D_BDW_PLUS); MMIO_D(0x65f10, D_BDW_PLUS); - MMIO_DFH(0xe194, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); - MMIO_DFH(0xe188, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); - MMIO_DFH(0xe180, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); + MMIO_DFH(0xe194, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); + MMIO_DFH(0xe188, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); + MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); MMIO_DFH(0x2580, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); MMIO_D(0x2248, D_BDW); @@ -2425,6 +2457,7 @@ static int init_skl_mmio_info(struct intel_gvt *gvt) MMIO_D(0xa210, D_SKL_PLUS); MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS); MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS); + MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); MMIO_DH(0x4ddc, D_SKL, NULL, skl_misc_ctl_write); MMIO_DH(0x42080, D_SKL, NULL, skl_misc_ctl_write); MMIO_D(0x45504, D_SKL); @@ -2574,8 +2607,8 @@ static int init_skl_mmio_info(struct intel_gvt *gvt) MMIO_D(0x51000, D_SKL); MMIO_D(0x6c00c, D_SKL); - MMIO_F(0xc800, 0x7f8, 0, 0, 0, D_SKL, NULL, NULL); - MMIO_F(0xb020, 0x80, 0, 0, 0, D_SKL, NULL, NULL); + MMIO_F(0xc800, 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL, NULL, NULL); + MMIO_F(0xb020, 0x80, F_CMD_ACCESS, 0, 0, D_SKL, NULL, NULL); MMIO_D(0xd08, D_SKL); MMIO_D(0x20e0, D_SKL); diff --git a/drivers/gpu/drm/i915/gvt/hypercall.h b/drivers/gpu/drm/i915/gvt/hypercall.h index 027ef558d91c..30e543f5a703 100644 --- a/drivers/gpu/drm/i915/gvt/hypercall.h +++ b/drivers/gpu/drm/i915/gvt/hypercall.h @@ -33,21 +33,14 @@ #ifndef _GVT_HYPERCALL_H_ #define _GVT_HYPERCALL_H_ -struct intel_gvt_io_emulation_ops { - int (*emulate_cfg_read)(void *, unsigned int, void *, unsigned int); - int (*emulate_cfg_write)(void *, unsigned int, void *, unsigned int); - int (*emulate_mmio_read)(void *, u64, void *, unsigned int); - int (*emulate_mmio_write)(void *, u64, void *, unsigned int); -}; - -extern struct intel_gvt_io_emulation_ops intel_gvt_io_emulation_ops; - /* * Specific GVT-g MPT modules function collections. Currently GVT-g supports * both Xen and KVM by providing dedicated hypervisor-related MPT modules. */ struct intel_gvt_mpt { int (*detect_host)(void); + int (*host_init)(struct device *dev, void *gvt, const void *ops); + void (*host_exit)(struct device *dev, void *gvt); int (*attach_vgpu)(void *vgpu, unsigned long *handle); void (*detach_vgpu)(unsigned long handle); int (*inject_msi)(unsigned long handle, u32 addr, u16 data); @@ -60,8 +53,7 @@ struct intel_gvt_mpt { unsigned long len); unsigned long (*gfn_to_mfn)(unsigned long handle, unsigned long gfn); int (*map_gfn_to_mfn)(unsigned long handle, unsigned long gfn, - unsigned long mfn, unsigned int nr, bool map, - int type); + unsigned long mfn, unsigned int nr, bool map); int (*set_trap_area)(unsigned long handle, u64 start, u64 end, bool map); }; diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c new file mode 100644 index 000000000000..dc0365033157 --- /dev/null +++ b/drivers/gpu/drm/i915/gvt/kvmgt.c @@ -0,0 +1,597 @@ +/* + * KVMGT - the implementation of Intel mediated pass-through framework for KVM + * + * Copyright(c) 2014-2016 Intel Corporation. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Authors: + * Kevin Tian <kevin.tian@intel.com> + * Jike Song <jike.song@intel.com> + * Xiaoguang Chen <xiaoguang.chen@intel.com> + */ + +#include <linux/init.h> +#include <linux/device.h> +#include <linux/mm.h> +#include <linux/types.h> +#include <linux/list.h> +#include <linux/rbtree.h> +#include <linux/spinlock.h> +#include <linux/eventfd.h> +#include <linux/uuid.h> +#include <linux/kvm_host.h> +#include <linux/vfio.h> + +#include "i915_drv.h" +#include "gvt.h" + +static inline long kvmgt_pin_pages(struct device *dev, unsigned long *user_pfn, + long npage, int prot, unsigned long *phys_pfn) +{ + return 0; +} +static inline long kvmgt_unpin_pages(struct device *dev, unsigned long *pfn, + long npage) +{ + return 0; +} + +static const struct intel_gvt_ops *intel_gvt_ops; + + +/* helper macros copied from vfio-pci */ +#define VFIO_PCI_OFFSET_SHIFT 40 +#define VFIO_PCI_OFFSET_TO_INDEX(off) (off >> VFIO_PCI_OFFSET_SHIFT) +#define VFIO_PCI_INDEX_TO_OFFSET(index) ((u64)(index) << VFIO_PCI_OFFSET_SHIFT) +#define VFIO_PCI_OFFSET_MASK (((u64)(1) << VFIO_PCI_OFFSET_SHIFT) - 1) + +struct vfio_region { + u32 type; + u32 subtype; + size_t size; + u32 flags; +}; + +struct kvmgt_pgfn { + gfn_t gfn; + struct hlist_node hnode; +}; + +struct kvmgt_guest_info { + struct kvm *kvm; + struct intel_vgpu *vgpu; + struct kvm_page_track_notifier_node track_node; +#define NR_BKT (1 << 18) + struct hlist_head ptable[NR_BKT]; +#undef NR_BKT +}; + +struct gvt_dma { + struct rb_node node; + gfn_t gfn; + kvm_pfn_t pfn; +}; + +static struct gvt_dma *__gvt_cache_find(struct intel_vgpu *vgpu, gfn_t gfn) +{ + struct rb_node *node = vgpu->vdev.cache.rb_node; + struct gvt_dma *ret = NULL; + + while (node) { + struct gvt_dma *itr = rb_entry(node, struct gvt_dma, node); + + if (gfn < itr->gfn) + node = node->rb_left; + else if (gfn > itr->gfn) + node = node->rb_right; + else { + ret = itr; + goto out; + } + } + +out: + return ret; +} + +static kvm_pfn_t gvt_cache_find(struct intel_vgpu *vgpu, gfn_t gfn) +{ + struct gvt_dma *entry; + + mutex_lock(&vgpu->vdev.cache_lock); + entry = __gvt_cache_find(vgpu, gfn); + mutex_unlock(&vgpu->vdev.cache_lock); + + return entry == NULL ? 0 : entry->pfn; +} + +static void gvt_cache_add(struct intel_vgpu *vgpu, gfn_t gfn, kvm_pfn_t pfn) +{ + struct gvt_dma *new, *itr; + struct rb_node **link = &vgpu->vdev.cache.rb_node, *parent = NULL; + + new = kzalloc(sizeof(struct gvt_dma), GFP_KERNEL); + if (!new) + return; + + new->gfn = gfn; + new->pfn = pfn; + + mutex_lock(&vgpu->vdev.cache_lock); + while (*link) { + parent = *link; + itr = rb_entry(parent, struct gvt_dma, node); + + if (gfn == itr->gfn) + goto out; + else if (gfn < itr->gfn) + link = &parent->rb_left; + else + link = &parent->rb_right; + } + + rb_link_node(&new->node, parent, link); + rb_insert_color(&new->node, &vgpu->vdev.cache); + mutex_unlock(&vgpu->vdev.cache_lock); + return; + +out: + mutex_unlock(&vgpu->vdev.cache_lock); + kfree(new); +} + +static void __gvt_cache_remove_entry(struct intel_vgpu *vgpu, + struct gvt_dma *entry) +{ + rb_erase(&entry->node, &vgpu->vdev.cache); + kfree(entry); +} + +static void gvt_cache_remove(struct intel_vgpu *vgpu, gfn_t gfn) +{ + struct device *dev = vgpu->vdev.mdev; + struct gvt_dma *this; + unsigned long pfn; + + mutex_lock(&vgpu->vdev.cache_lock); + this = __gvt_cache_find(vgpu, gfn); + if (!this) { + mutex_unlock(&vgpu->vdev.cache_lock); + return; + } + + pfn = this->pfn; + WARN_ON((kvmgt_unpin_pages(dev, &pfn, 1) != 1)); + __gvt_cache_remove_entry(vgpu, this); + mutex_unlock(&vgpu->vdev.cache_lock); +} + +static void gvt_cache_init(struct intel_vgpu *vgpu) +{ + vgpu->vdev.cache = RB_ROOT; + mutex_init(&vgpu->vdev.cache_lock); +} + +static void gvt_cache_destroy(struct intel_vgpu *vgpu) +{ + struct gvt_dma *dma; + struct rb_node *node = NULL; + struct device *dev = vgpu->vdev.mdev; + unsigned long pfn; + + mutex_lock(&vgpu->vdev.cache_lock); + while ((node = rb_first(&vgpu->vdev.cache))) { + dma = rb_entry(node, struct gvt_dma, node); + pfn = dma->pfn; + + kvmgt_unpin_pages(dev, &pfn, 1); + __gvt_cache_remove_entry(vgpu, dma); + } + mutex_unlock(&vgpu->vdev.cache_lock); +} + +static struct intel_vgpu_type *intel_gvt_find_vgpu_type(struct intel_gvt *gvt, + const char *name) +{ + int i; + struct intel_vgpu_type *t; + const char *driver_name = dev_driver_string( + &gvt->dev_priv->drm.pdev->dev); + + for (i = 0; i < gvt->num_types; i++) { + t = &gvt->types[i]; + if (!strncmp(t->name, name + strlen(driver_name) + 1, + sizeof(t->name))) + return t; + } + + return NULL; +} + +static struct attribute *type_attrs[] = { + NULL, +}; + +static struct attribute_group *intel_vgpu_type_groups[] = { + [0 ... NR_MAX_INTEL_VGPU_TYPES - 1] = NULL, +}; + +static bool intel_gvt_init_vgpu_type_groups(struct intel_gvt *gvt) +{ + int i, j; + struct intel_vgpu_type *type; + struct attribute_group *group; + + for (i = 0; i < gvt->num_types; i++) { + type = &gvt->types[i]; + + group = kzalloc(sizeof(struct attribute_group), GFP_KERNEL); + if (WARN_ON(!group)) + goto unwind; + + group->name = type->name; + group->attrs = type_attrs; + intel_vgpu_type_groups[i] = group; + } + + return true; + +unwind: + for (j = 0; j < i; j++) { + group = intel_vgpu_type_groups[j]; + kfree(group); + } + + return false; +} + +static void intel_gvt_cleanup_vgpu_type_groups(struct intel_gvt *gvt) +{ + int i; + struct attribute_group *group; + + for (i = 0; i < gvt->num_types; i++) { + group = intel_vgpu_type_groups[i]; + kfree(group); + } +} + +static void kvmgt_protect_table_init(struct kvmgt_guest_info *info) +{ + hash_init(info->ptable); +} + +static void kvmgt_protect_table_destroy(struct kvmgt_guest_info *info) +{ + struct kvmgt_pgfn *p; + struct hlist_node *tmp; + int i; + + hash_for_each_safe(info->ptable, i, tmp, p, hnode) { + hash_del(&p->hnode); + kfree(p); + } +} + +static struct kvmgt_pgfn * +__kvmgt_protect_table_find(struct kvmgt_guest_info *info, gfn_t gfn) +{ + struct kvmgt_pgfn *p, *res = NULL; + + hash_for_each_possible(info->ptable, p, hnode, gfn) { + if (gfn == p->gfn) { + res = p; + break; + } + } + + return res; +} + +static bool kvmgt_gfn_is_write_protected(struct kvmgt_guest_info *info, + gfn_t gfn) +{ + struct kvmgt_pgfn *p; + + p = __kvmgt_protect_table_find(info, gfn); + return !!p; +} + +static void kvmgt_protect_table_add(struct kvmgt_guest_info *info, gfn_t gfn) +{ + struct kvmgt_pgfn *p; + + if (kvmgt_gfn_is_write_protected(info, gfn)) + return; + + p = kmalloc(sizeof(struct kvmgt_pgfn), GFP_ATOMIC); + if (WARN(!p, "gfn: 0x%llx\n", gfn)) + return; + + p->gfn = gfn; + hash_add(info->ptable, &p->hnode, gfn); +} + +static void kvmgt_protect_table_del(struct kvmgt_guest_info *info, + gfn_t gfn) +{ + struct kvmgt_pgfn *p; + + p = __kvmgt_protect_table_find(info, gfn); + if (p) { + hash_del(&p->hnode); + kfree(p); + } +} + +static int kvmgt_host_init(struct device *dev, void *gvt, const void *ops) +{ + if (!intel_gvt_init_vgpu_type_groups(gvt)) + return -EFAULT; + + intel_gvt_ops = ops; + + /* MDEV is not yet available */ + return -ENODEV; +} + +static void kvmgt_host_exit(struct device *dev, void *gvt) +{ + intel_gvt_cleanup_vgpu_type_groups(gvt); +} + +static int kvmgt_write_protect_add(unsigned long handle, u64 gfn) +{ + struct kvmgt_guest_info *info = (struct kvmgt_guest_info *)handle; + struct kvm *kvm = info->kvm; + struct kvm_memory_slot *slot; + int idx; + + idx = srcu_read_lock(&kvm->srcu); + slot = gfn_to_memslot(kvm, gfn); + + spin_lock(&kvm->mmu_lock); + + if (kvmgt_gfn_is_write_protected(info, gfn)) + goto out; + + kvm_slot_page_track_add_page(kvm, slot, gfn, KVM_PAGE_TRACK_WRITE); + kvmgt_protect_table_add(info, gfn); + +out: + spin_unlock(&kvm->mmu_lock); + srcu_read_unlock(&kvm->srcu, idx); + return 0; +} + +static int kvmgt_write_protect_remove(unsigned long handle, u64 gfn) +{ + struct kvmgt_guest_info *info = (struct kvmgt_guest_info *)handle; + struct kvm *kvm = info->kvm; + struct kvm_memory_slot *slot; + int idx; + + idx = srcu_read_lock(&kvm->srcu); + slot = gfn_to_memslot(kvm, gfn); + + spin_lock(&kvm->mmu_lock); + + if (!kvmgt_gfn_is_write_protected(info, gfn)) + goto out; + + kvm_slot_page_track_remove_page(kvm, slot, gfn, KVM_PAGE_TRACK_WRITE); + kvmgt_protect_table_del(info, gfn); + +out: + spin_unlock(&kvm->mmu_lock); + srcu_read_unlock(&kvm->srcu, idx); + return 0; +} + +static void kvmgt_page_track_write(struct kvm_vcpu *vcpu, gpa_t gpa, + const u8 *val, int len, + struct kvm_page_track_notifier_node *node) +{ + struct kvmgt_guest_info *info = container_of(node, + struct kvmgt_guest_info, track_node); + + if (kvmgt_gfn_is_write_protected(info, gpa_to_gfn(gpa))) + intel_gvt_ops->emulate_mmio_write(info->vgpu, gpa, + (void *)val, len); +} + +static void kvmgt_page_track_flush_slot(struct kvm *kvm, + struct kvm_memory_slot *slot, + struct kvm_page_track_notifier_node *node) +{ + int i; + gfn_t gfn; + struct kvmgt_guest_info *info = container_of(node, + struct kvmgt_guest_info, track_node); + + spin_lock(&kvm->mmu_lock); + for (i = 0; i < slot->npages; i++) { + gfn = slot->base_gfn + i; + if (kvmgt_gfn_is_write_protected(info, gfn)) { + kvm_slot_page_track_remove_page(kvm, slot, gfn, + KVM_PAGE_TRACK_WRITE); + kvmgt_protect_table_del(info, gfn); + } + } + spin_unlock(&kvm->mmu_lock); +} + +static bool kvmgt_check_guest(void) +{ + unsigned int eax, ebx, ecx, edx; + char s[12]; + unsigned int *i; + + eax = KVM_CPUID_SIGNATURE; + ebx = ecx = edx = 0; + + asm volatile ("cpuid" + : "+a"(eax), "=b"(ebx), "=c"(ecx), "=d"(edx) + : + : "cc", "memory"); + i = (unsigned int *)s; + i[0] = ebx; + i[1] = ecx; + i[2] = edx; + + return !strncmp(s, "KVMKVMKVM", strlen("KVMKVMKVM")); +} + +/** + * NOTE: + * It's actually impossible to check if we are running in KVM host, + * since the "KVM host" is simply native. So we only dectect guest here. + */ +static int kvmgt_detect_host(void) +{ +#ifdef CONFIG_INTEL_IOMMU + if (intel_iommu_gfx_mapped) { + gvt_err("Hardware IOMMU compatibility not yet supported, try to boot with intel_iommu=igfx_off\n"); + return -ENODEV; + } +#endif + return kvmgt_check_guest() ? -ENODEV : 0; +} + +static int kvmgt_attach_vgpu(void *vgpu, unsigned long *handle) +{ + /* nothing to do here */ + return 0; +} + +static void kvmgt_detach_vgpu(unsigned long handle) +{ + /* nothing to do here */ +} + +static int kvmgt_inject_msi(unsigned long handle, u32 addr, u16 data) +{ + struct kvmgt_guest_info *info = (struct kvmgt_guest_info *)handle; + struct intel_vgpu *vgpu = info->vgpu; + + if (vgpu->vdev.msi_trigger) + return eventfd_signal(vgpu->vdev.msi_trigger, 1) == 1; + + return false; +} + +static unsigned long kvmgt_gfn_to_pfn(unsigned long handle, unsigned long gfn) +{ + unsigned long pfn; + struct kvmgt_guest_info *info = (struct kvmgt_guest_info *)handle; + int rc; + + pfn = gvt_cache_find(info->vgpu, gfn); + if (pfn != 0) + return pfn; + + rc = kvmgt_pin_pages(info->vgpu->vdev.mdev, &gfn, 1, + IOMMU_READ | IOMMU_WRITE, &pfn); + if (rc != 1) { + gvt_err("vfio_pin_pages failed for gfn: 0x%lx\n", gfn); + return 0; + } + + gvt_cache_add(info->vgpu, gfn, pfn); + return pfn; +} + +static void *kvmgt_gpa_to_hva(unsigned long handle, unsigned long gpa) +{ + unsigned long pfn; + gfn_t gfn = gpa_to_gfn(gpa); + + pfn = kvmgt_gfn_to_pfn(handle, gfn); + if (!pfn) + return NULL; + + return (char *)pfn_to_kaddr(pfn) + offset_in_page(gpa); +} + +static int kvmgt_rw_gpa(unsigned long handle, unsigned long gpa, + void *buf, unsigned long len, bool write) +{ + void *hva = NULL; + + hva = kvmgt_gpa_to_hva(handle, gpa); + if (!hva) + return -EFAULT; + + if (write) + memcpy(hva, buf, len); + else + memcpy(buf, hva, len); + + return 0; +} + +static int kvmgt_read_gpa(unsigned long handle, unsigned long gpa, + void *buf, unsigned long len) +{ + return kvmgt_rw_gpa(handle, gpa, buf, len, false); +} + +static int kvmgt_write_gpa(unsigned long handle, unsigned long gpa, + void *buf, unsigned long len) +{ + return kvmgt_rw_gpa(handle, gpa, buf, len, true); +} + +static unsigned long kvmgt_virt_to_pfn(void *addr) +{ + return PFN_DOWN(__pa(addr)); +} + +struct intel_gvt_mpt kvmgt_mpt = { + .detect_host = kvmgt_detect_host, + .host_init = kvmgt_host_init, + .host_exit = kvmgt_host_exit, + .attach_vgpu = kvmgt_attach_vgpu, + .detach_vgpu = kvmgt_detach_vgpu, + .inject_msi = kvmgt_inject_msi, + .from_virt_to_mfn = kvmgt_virt_to_pfn, + .set_wp_page = kvmgt_write_protect_add, + .unset_wp_page = kvmgt_write_protect_remove, + .read_gpa = kvmgt_read_gpa, + .write_gpa = kvmgt_write_gpa, + .gfn_to_mfn = kvmgt_gfn_to_pfn, +}; +EXPORT_SYMBOL_GPL(kvmgt_mpt); + +static int __init kvmgt_init(void) +{ + return 0; +} + +static void __exit kvmgt_exit(void) +{ +} + +module_init(kvmgt_init); +module_exit(kvmgt_exit); + +MODULE_LICENSE("GPL and additional rights"); +MODULE_AUTHOR("Intel Corporation"); diff --git a/drivers/gpu/drm/i915/gvt/mmio.c b/drivers/gpu/drm/i915/gvt/mmio.c index 585b01f63254..09c9450a1946 100644 --- a/drivers/gpu/drm/i915/gvt/mmio.c +++ b/drivers/gpu/drm/i915/gvt/mmio.c @@ -67,10 +67,9 @@ int intel_vgpu_gpa_to_mmio_offset(struct intel_vgpu *vgpu, u64 gpa) * Returns: * Zero on success, negative error code if failed */ -int intel_vgpu_emulate_mmio_read(void *__vgpu, uint64_t pa, +int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, uint64_t pa, void *p_data, unsigned int bytes) { - struct intel_vgpu *vgpu = __vgpu; struct intel_gvt *gvt = vgpu->gvt; struct intel_gvt_mmio_info *mmio; unsigned int offset = 0; @@ -179,10 +178,9 @@ err: * Returns: * Zero on success, negative error code if failed */ -int intel_vgpu_emulate_mmio_write(void *__vgpu, uint64_t pa, +int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, uint64_t pa, void *p_data, unsigned int bytes) { - struct intel_vgpu *vgpu = __vgpu; struct intel_gvt *gvt = vgpu->gvt; struct intel_gvt_mmio_info *mmio; unsigned int offset = 0; diff --git a/drivers/gpu/drm/i915/gvt/mmio.h b/drivers/gpu/drm/i915/gvt/mmio.h index 9dc739a01892..87d5b5e366a3 100644 --- a/drivers/gpu/drm/i915/gvt/mmio.h +++ b/drivers/gpu/drm/i915/gvt/mmio.h @@ -87,10 +87,11 @@ struct intel_gvt_mmio_info *intel_gvt_find_mmio_info(struct intel_gvt *gvt, }) int intel_vgpu_gpa_to_mmio_offset(struct intel_vgpu *vgpu, u64 gpa); -int intel_vgpu_emulate_mmio_read(void *__vgpu, u64 pa, void *p_data, - unsigned int bytes); -int intel_vgpu_emulate_mmio_write(void *__vgpu, u64 pa, void *p_data, - unsigned int bytes); + +int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, u64 pa, + void *p_data, unsigned int bytes); +int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, u64 pa, + void *p_data, unsigned int bytes); bool intel_gvt_mmio_is_cmd_access(struct intel_gvt *gvt, unsigned int offset); bool intel_gvt_mmio_is_unalign(struct intel_gvt *gvt, unsigned int offset); diff --git a/drivers/gpu/drm/i915/gvt/mpt.h b/drivers/gpu/drm/i915/gvt/mpt.h index 67858782d327..1af5830c0a56 100644 --- a/drivers/gpu/drm/i915/gvt/mpt.h +++ b/drivers/gpu/drm/i915/gvt/mpt.h @@ -56,6 +56,35 @@ static inline int intel_gvt_hypervisor_detect_host(void) } /** + * intel_gvt_hypervisor_host_init - init GVT-g host side + * + * Returns: + * Zero on success, negative error code if failed + */ +static inline int intel_gvt_hypervisor_host_init(struct device *dev, + void *gvt, const void *ops) +{ + /* optional to provide */ + if (!intel_gvt_host.mpt->host_init) + return 0; + + return intel_gvt_host.mpt->host_init(dev, gvt, ops); +} + +/** + * intel_gvt_hypervisor_host_exit - exit GVT-g host side + */ +static inline void intel_gvt_hypervisor_host_exit(struct device *dev, + void *gvt) +{ + /* optional to provide */ + if (!intel_gvt_host.mpt->host_exit) + return; + + intel_gvt_host.mpt->host_exit(dev, gvt); +} + +/** * intel_gvt_hypervisor_attach_vgpu - call hypervisor to initialize vGPU * related stuffs inside hypervisor. * @@ -64,6 +93,10 @@ static inline int intel_gvt_hypervisor_detect_host(void) */ static inline int intel_gvt_hypervisor_attach_vgpu(struct intel_vgpu *vgpu) { + /* optional to provide */ + if (!intel_gvt_host.mpt->attach_vgpu) + return 0; + return intel_gvt_host.mpt->attach_vgpu(vgpu, &vgpu->handle); } @@ -76,6 +109,10 @@ static inline int intel_gvt_hypervisor_attach_vgpu(struct intel_vgpu *vgpu) */ static inline void intel_gvt_hypervisor_detach_vgpu(struct intel_vgpu *vgpu) { + /* optional to provide */ + if (!intel_gvt_host.mpt->detach_vgpu) + return; + intel_gvt_host.mpt->detach_vgpu(vgpu->handle); } @@ -224,11 +261,6 @@ static inline unsigned long intel_gvt_hypervisor_gfn_to_mfn( return intel_gvt_host.mpt->gfn_to_mfn(vgpu->handle, gfn); } -enum { - GVT_MAP_APERTURE = 0, - GVT_MAP_OPREGION, -}; - /** * intel_gvt_hypervisor_map_gfn_to_mfn - map a GFN region to MFN * @vgpu: a vGPU @@ -236,7 +268,6 @@ enum { * @mfn: host PFN * @nr: amount of PFNs * @map: map or unmap - * @type: map type * * Returns: * Zero on success, negative error code if failed. @@ -244,10 +275,14 @@ enum { static inline int intel_gvt_hypervisor_map_gfn_to_mfn( struct intel_vgpu *vgpu, unsigned long gfn, unsigned long mfn, unsigned int nr, - bool map, int type) + bool map) { + /* a MPT implementation could have MMIO mapped elsewhere */ + if (!intel_gvt_host.mpt->map_gfn_to_mfn) + return 0; + return intel_gvt_host.mpt->map_gfn_to_mfn(vgpu->handle, gfn, mfn, nr, - map, type); + map); } /** @@ -263,6 +298,10 @@ static inline int intel_gvt_hypervisor_map_gfn_to_mfn( static inline int intel_gvt_hypervisor_set_trap_area( struct intel_vgpu *vgpu, u64 start, u64 end, bool map) { + /* a MPT implementation could have MMIO trapped elsewhere */ + if (!intel_gvt_host.mpt->set_trap_area) + return 0; + return intel_gvt_host.mpt->set_trap_area(vgpu->handle, start, end, map); } diff --git a/drivers/gpu/drm/i915/gvt/opregion.c b/drivers/gpu/drm/i915/gvt/opregion.c index 95218913b0bc..d2a0fbc896c3 100644 --- a/drivers/gpu/drm/i915/gvt/opregion.c +++ b/drivers/gpu/drm/i915/gvt/opregion.c @@ -73,7 +73,7 @@ static int map_vgpu_opregion(struct intel_vgpu *vgpu, bool map) } ret = intel_gvt_hypervisor_map_gfn_to_mfn(vgpu, vgpu_opregion(vgpu)->gfn[i], - mfn, 1, map, GVT_MAP_OPREGION); + mfn, 1, map); if (ret) { gvt_err("fail to map GFN to MFN, errno: %d\n", ret); return ret; @@ -89,28 +89,18 @@ static int map_vgpu_opregion(struct intel_vgpu *vgpu, bool map) */ void intel_vgpu_clean_opregion(struct intel_vgpu *vgpu) { - int i; - gvt_dbg_core("vgpu%d: clean vgpu opregion\n", vgpu->id); if (!vgpu_opregion(vgpu)->va) return; - if (intel_gvt_host.hypervisor_type == INTEL_GVT_HYPERVISOR_KVM) { - vunmap(vgpu_opregion(vgpu)->va); - for (i = 0; i < INTEL_GVT_OPREGION_PAGES; i++) { - if (vgpu_opregion(vgpu)->pages[i]) { - put_page(vgpu_opregion(vgpu)->pages[i]); - vgpu_opregion(vgpu)->pages[i] = NULL; - } - } - } else { + if (intel_gvt_host.hypervisor_type == INTEL_GVT_HYPERVISOR_XEN) { map_vgpu_opregion(vgpu, false); free_pages((unsigned long)vgpu_opregion(vgpu)->va, INTEL_GVT_OPREGION_PORDER); - } - vgpu_opregion(vgpu)->va = NULL; + vgpu_opregion(vgpu)->va = NULL; + } } /** @@ -137,22 +127,8 @@ int intel_vgpu_init_opregion(struct intel_vgpu *vgpu, u32 gpa) ret = map_vgpu_opregion(vgpu, true); if (ret) return ret; - } else { - gvt_dbg_core("emulate opregion from userspace\n"); - - /* - * If opregion pages are not allocated from host kenrel, - * most of the params are meaningless - */ - ret = intel_gvt_hypervisor_map_gfn_to_mfn(vgpu, - 0, /* not used */ - 0, /* not used */ - 2, /* not used */ - 1, - GVT_MAP_OPREGION); - if (ret) - return ret; } + return 0; } diff --git a/drivers/gpu/drm/i915/gvt/render.c b/drivers/gpu/drm/i915/gvt/render.c index 3af894b3d257..44136b1f3aab 100644 --- a/drivers/gpu/drm/i915/gvt/render.c +++ b/drivers/gpu/drm/i915/gvt/render.c @@ -152,6 +152,8 @@ static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id) if (wait_for_atomic((I915_READ_FW(reg) == 0), 50)) gvt_err("timeout in invalidate ring (%d) tlb\n", ring_id); + else + vgpu_vreg(vgpu, regs[ring_id]) = 0; intel_uncore_forcewake_put(dev_priv, fw); diff --git a/drivers/gpu/drm/i915/gvt/sched_policy.c b/drivers/gpu/drm/i915/gvt/sched_policy.c index 1df6a5460f3e..678b0be85376 100644 --- a/drivers/gpu/drm/i915/gvt/sched_policy.c +++ b/drivers/gpu/drm/i915/gvt/sched_policy.c @@ -36,12 +36,10 @@ static bool vgpu_has_pending_workload(struct intel_vgpu *vgpu) { - struct intel_vgpu_execlist *execlist; enum intel_engine_id i; struct intel_engine_cs *engine; for_each_engine(engine, vgpu->gvt->dev_priv, i) { - execlist = &vgpu->execlist[i]; if (!list_empty(workload_q_head(vgpu, i))) return true; } diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c index 18acb45dd14d..f898df38dd9a 100644 --- a/drivers/gpu/drm/i915/gvt/scheduler.c +++ b/drivers/gpu/drm/i915/gvt/scheduler.c @@ -89,15 +89,15 @@ static int populate_shadow_context(struct intel_vgpu_workload *workload) } page = i915_gem_object_get_page(ctx_obj, LRC_PPHWSP_PN + i); - dst = kmap_atomic(page); + dst = kmap(page); intel_gvt_hypervisor_read_gpa(vgpu, context_gpa, dst, GTT_PAGE_SIZE); - kunmap_atomic(dst); + kunmap(page); i++; } page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN); - shadow_ring_context = kmap_atomic(page); + shadow_ring_context = kmap(page); #define COPY_REG(name) \ intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \ @@ -123,7 +123,7 @@ static int populate_shadow_context(struct intel_vgpu_workload *workload) sizeof(*shadow_ring_context), GTT_PAGE_SIZE - sizeof(*shadow_ring_context)); - kunmap_atomic(shadow_ring_context); + kunmap(page); return 0; } @@ -160,8 +160,6 @@ static int shadow_context_status_change(struct notifier_block *nb, static int dispatch_workload(struct intel_vgpu_workload *workload) { - struct intel_vgpu *vgpu = workload->vgpu; - struct intel_gvt *gvt = vgpu->gvt; int ring_id = workload->ring_id; struct i915_gem_context *shadow_ctx = workload->vgpu->shadow_ctx; struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv; @@ -174,6 +172,8 @@ static int dispatch_workload(struct intel_vgpu_workload *workload) shadow_ctx->desc_template = workload->ctx_desc.addressing_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT; + mutex_lock(&dev_priv->drm.struct_mutex); + rq = i915_gem_request_alloc(dev_priv->engine[ring_id], shadow_ctx); if (IS_ERR(rq)) { gvt_err("fail to allocate gem request\n"); @@ -185,40 +185,35 @@ static int dispatch_workload(struct intel_vgpu_workload *workload) workload->req = i915_gem_request_get(rq); - mutex_lock(&gvt->lock); - ret = intel_gvt_scan_and_shadow_workload(workload); if (ret) - goto err; + goto out; ret = intel_gvt_scan_and_shadow_wa_ctx(&workload->wa_ctx); if (ret) - goto err; + goto out; ret = populate_shadow_context(workload); if (ret) - goto err; + goto out; if (workload->prepare) { ret = workload->prepare(workload); if (ret) - goto err; + goto out; } - mutex_unlock(&gvt->lock); - gvt_dbg_sched("ring id %d submit workload to i915 %p\n", ring_id, workload->req); - i915_add_request_no_flush(rq); + ret = 0; workload->dispatched = true; - return 0; -err: - workload->status = ret; - - mutex_unlock(&gvt->lock); +out: + if (ret) + workload->status = ret; i915_add_request_no_flush(rq); + mutex_unlock(&dev_priv->drm.struct_mutex); return ret; } @@ -318,10 +313,10 @@ static void update_guest_context(struct intel_vgpu_workload *workload) } page = i915_gem_object_get_page(ctx_obj, LRC_PPHWSP_PN + i); - src = kmap_atomic(page); + src = kmap(page); intel_gvt_hypervisor_write_gpa(vgpu, context_gpa, src, GTT_PAGE_SIZE); - kunmap_atomic(src); + kunmap(page); i++; } @@ -329,7 +324,7 @@ static void update_guest_context(struct intel_vgpu_workload *workload) RING_CTX_OFF(ring_header.val), &workload->rb_tail, 4); page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN); - shadow_ring_context = kmap_atomic(page); + shadow_ring_context = kmap(page); #define COPY_REG(name) \ intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa + \ @@ -347,7 +342,7 @@ static void update_guest_context(struct intel_vgpu_workload *workload) sizeof(*shadow_ring_context), GTT_PAGE_SIZE - sizeof(*shadow_ring_context)); - kunmap_atomic(shadow_ring_context); + kunmap(page); } static void complete_current_workload(struct intel_gvt *gvt, int ring_id) @@ -438,9 +433,9 @@ static int workload_thread(void *priv) intel_uncore_forcewake_get(gvt->dev_priv, FORCEWAKE_ALL); - mutex_lock(&gvt->dev_priv->drm.struct_mutex); + mutex_lock(&gvt->lock); ret = dispatch_workload(workload); - mutex_unlock(&gvt->dev_priv->drm.struct_mutex); + mutex_unlock(&gvt->lock); if (ret) { gvt_err("fail to dispatch workload, skip\n"); @@ -455,15 +450,15 @@ static int workload_thread(void *priv) if (lret < 0) { workload->status = lret; gvt_err("fail to wait workload, skip\n"); + } else { + workload->status = 0; } complete: gvt_dbg_sched("will complete workload %p\n, status: %d\n", workload, workload->status); - mutex_lock(&gvt->dev_priv->drm.struct_mutex); complete_current_workload(gvt, ring_id); - mutex_unlock(&gvt->dev_priv->drm.struct_mutex); i915_gem_request_put(fetch_and_zero(&workload->req)); diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c index 4f54005b976d..4f64845d8a4c 100644 --- a/drivers/gpu/drm/i915/gvt/vgpu.c +++ b/drivers/gpu/drm/i915/gvt/vgpu.c @@ -46,9 +46,13 @@ int setup_vgpu_mmio(struct intel_vgpu *vgpu) struct intel_gvt *gvt = vgpu->gvt; const struct intel_gvt_device_info *info = &gvt->device_info; - vgpu->mmio.vreg = vzalloc(info->mmio_size * 2); - if (!vgpu->mmio.vreg) - return -ENOMEM; + if (vgpu->mmio.vreg) + memset(vgpu->mmio.vreg, 0, info->mmio_size * 2); + else { + vgpu->mmio.vreg = vzalloc(info->mmio_size * 2); + if (!vgpu->mmio.vreg) + return -ENOMEM; + } vgpu->mmio.sreg = vgpu->mmio.vreg + info->mmio_size; @@ -95,6 +99,7 @@ static void setup_vgpu_cfg_space(struct intel_vgpu *vgpu, */ memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_1, 0, 4); memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_3, 0, 4); + memset(vgpu_cfg_space(vgpu) + INTEL_GVT_PCI_OPREGION, 0, 4); for (i = 0; i < INTEL_GVT_MAX_BAR_NUM; i++) { vgpu->cfg_space.bar[i].size = pci_resource_len( @@ -133,6 +138,106 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu) } /** + * intel_gvt_init_vgpu_types - initialize vGPU type list + * @gvt : GVT device + * + * Initialize vGPU type list based on available resource. + * + */ +int intel_gvt_init_vgpu_types(struct intel_gvt *gvt) +{ + unsigned int num_types; + unsigned int i, low_avail; + unsigned int min_low; + + /* vGPU type name is defined as GVTg_Vx_y which contains + * physical GPU generation type and 'y' means maximum vGPU + * instances user can create on one physical GPU for this + * type. + * + * Depend on physical SKU resource, might see vGPU types like + * GVTg_V4_8, GVTg_V4_4, GVTg_V4_2, etc. We can create + * different types of vGPU on same physical GPU depending on + * available resource. Each vGPU type will have "avail_instance" + * to indicate how many vGPU instance can be created for this + * type. + * + * Currently use static size here as we init type earlier.. + */ + low_avail = MB_TO_BYTES(256) - HOST_LOW_GM_SIZE; + num_types = 4; + + gvt->types = kzalloc(num_types * sizeof(struct intel_vgpu_type), + GFP_KERNEL); + if (!gvt->types) + return -ENOMEM; + + min_low = MB_TO_BYTES(32); + for (i = 0; i < num_types; ++i) { + if (low_avail / min_low == 0) + break; + gvt->types[i].low_gm_size = min_low; + gvt->types[i].high_gm_size = 3 * gvt->types[i].low_gm_size; + gvt->types[i].fence = 4; + gvt->types[i].max_instance = low_avail / min_low; + gvt->types[i].avail_instance = gvt->types[i].max_instance; + + if (IS_GEN8(gvt->dev_priv)) + sprintf(gvt->types[i].name, "GVTg_V4_%u", + gvt->types[i].max_instance); + else if (IS_GEN9(gvt->dev_priv)) + sprintf(gvt->types[i].name, "GVTg_V5_%u", + gvt->types[i].max_instance); + + min_low <<= 1; + gvt_dbg_core("type[%d]: %s max %u avail %u low %u high %u fence %u\n", + i, gvt->types[i].name, gvt->types[i].max_instance, + gvt->types[i].avail_instance, + gvt->types[i].low_gm_size, + gvt->types[i].high_gm_size, gvt->types[i].fence); + } + + gvt->num_types = i; + return 0; +} + +void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt) +{ + kfree(gvt->types); +} + +static void intel_gvt_update_vgpu_types(struct intel_gvt *gvt) +{ + int i; + unsigned int low_gm_avail, high_gm_avail, fence_avail; + unsigned int low_gm_min, high_gm_min, fence_min, total_min; + + /* Need to depend on maxium hw resource size but keep on + * static config for now. + */ + low_gm_avail = MB_TO_BYTES(256) - HOST_LOW_GM_SIZE - + gvt->gm.vgpu_allocated_low_gm_size; + high_gm_avail = MB_TO_BYTES(256) * 3 - HOST_HIGH_GM_SIZE - + gvt->gm.vgpu_allocated_high_gm_size; + fence_avail = gvt_fence_sz(gvt) - HOST_FENCE - + gvt->fence.vgpu_allocated_fence_num; + + for (i = 0; i < gvt->num_types; i++) { + low_gm_min = low_gm_avail / gvt->types[i].low_gm_size; + high_gm_min = high_gm_avail / gvt->types[i].high_gm_size; + fence_min = fence_avail / gvt->types[i].fence; + total_min = min(min(low_gm_min, high_gm_min), fence_min); + gvt->types[i].avail_instance = min(gvt->types[i].max_instance, + total_min); + + gvt_dbg_core("update type[%d]: %s max %u avail %u low %u high %u fence %u\n", + i, gvt->types[i].name, gvt->types[i].max_instance, + gvt->types[i].avail_instance, gvt->types[i].low_gm_size, + gvt->types[i].high_gm_size, gvt->types[i].fence); + } +} + +/** * intel_gvt_destroy_vgpu - destroy a virtual GPU * @vgpu: virtual GPU * @@ -166,20 +271,11 @@ void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu) clean_vgpu_mmio(vgpu); vfree(vgpu); + intel_gvt_update_vgpu_types(gvt); mutex_unlock(&gvt->lock); } -/** - * intel_gvt_create_vgpu - create a virtual GPU - * @gvt: GVT device - * @param: vGPU creation parameters - * - * This function is called when user wants to create a virtual GPU. - * - * Returns: - * pointer to intel_vgpu, error pointer if failed. - */ -struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt, +static struct intel_vgpu *__intel_gvt_create_vgpu(struct intel_gvt *gvt, struct intel_vgpu_creation_params *param) { struct intel_vgpu *vgpu; @@ -224,15 +320,9 @@ struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt, if (ret) goto out_detach_hypervisor_vgpu; - if (intel_gvt_host.hypervisor_type == INTEL_GVT_HYPERVISOR_KVM) { - ret = intel_vgpu_init_opregion(vgpu, 0); - if (ret) - goto out_clean_gtt; - } - ret = intel_vgpu_init_display(vgpu); if (ret) - goto out_clean_opregion; + goto out_clean_gtt; ret = intel_vgpu_init_execlist(vgpu); if (ret) @@ -257,8 +347,6 @@ out_clean_execlist: intel_vgpu_clean_execlist(vgpu); out_clean_display: intel_vgpu_clean_display(vgpu); -out_clean_opregion: - intel_vgpu_clean_opregion(vgpu); out_clean_gtt: intel_vgpu_clean_gtt(vgpu); out_detach_hypervisor_vgpu: @@ -272,3 +360,49 @@ out_free_vgpu: mutex_unlock(&gvt->lock); return ERR_PTR(ret); } + +/** + * intel_gvt_create_vgpu - create a virtual GPU + * @gvt: GVT device + * @type: type of the vGPU to create + * + * This function is called when user wants to create a virtual GPU. + * + * Returns: + * pointer to intel_vgpu, error pointer if failed. + */ +struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt, + struct intel_vgpu_type *type) +{ + struct intel_vgpu_creation_params param; + struct intel_vgpu *vgpu; + + param.handle = 0; + param.low_gm_sz = type->low_gm_size; + param.high_gm_sz = type->high_gm_size; + param.fence_sz = type->fence; + + /* XXX current param based on MB */ + param.low_gm_sz = BYTES_TO_MB(param.low_gm_sz); + param.high_gm_sz = BYTES_TO_MB(param.high_gm_sz); + + vgpu = __intel_gvt_create_vgpu(gvt, ¶m); + if (IS_ERR(vgpu)) + return vgpu; + + /* calculate left instance change for types */ + intel_gvt_update_vgpu_types(gvt); + + return vgpu; +} + +/** + * intel_gvt_reset_vgpu - reset a virtual GPU + * @vgpu: virtual GPU + * + * This function is called when user wants to reset a virtual GPU. + * + */ +void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu) +{ +} diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 6b159bab42b0..b7f42c448a44 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -547,11 +547,11 @@ static int i915_gem_pageflip_info(struct seq_file *m, void *data) pipe, plane); } if (work->flip_queued_req) { - struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req); + struct intel_engine_cs *engine = work->flip_queued_req->engine; seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n", engine->name, - i915_gem_request_get_seqno(work->flip_queued_req), + work->flip_queued_req->global_seqno, atomic_read(&dev_priv->gt.global_timeline.next_seqno), intel_engine_get_seqno(engine), i915_gem_request_completed(work->flip_queued_req)); @@ -631,8 +631,9 @@ static void print_request(struct seq_file *m, struct drm_i915_gem_request *rq, const char *prefix) { - seq_printf(m, "%s%x [%x:%x] @ %d: %s\n", prefix, + seq_printf(m, "%s%x [%x:%x] prio=%d @ %dms: %s\n", prefix, rq->global_seqno, rq->ctx->hw_id, rq->fence.seqno, + rq->priotree.priority, jiffies_to_msecs(jiffies - rq->emitted_jiffies), rq->timeline->common->name); } @@ -1761,8 +1762,7 @@ static int i915_sr_status(struct seq_file *m, void *unused) intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); intel_runtime_pm_put(dev_priv); - seq_printf(m, "self-refresh: %s\n", - sr_enabled ? "enabled" : "disabled"); + seq_printf(m, "self-refresh: %s\n", enableddisabled(sr_enabled)); return 0; } @@ -3216,6 +3216,7 @@ static int i915_engine_info(struct seq_file *m, void *unused) if (i915.enable_execlists) { u32 ptr, read, write; + struct rb_node *rb; seq_printf(m, "\tExeclist status: 0x%08x %08x\n", I915_READ(RING_EXECLIST_STATUS_LO(engine)), @@ -3254,11 +3255,12 @@ static int i915_engine_info(struct seq_file *m, void *unused) seq_printf(m, "\t\tELSP[1] idle\n"); rcu_read_unlock(); - spin_lock_irq(&engine->execlist_lock); - list_for_each_entry(rq, &engine->execlist_queue, execlist_link) { + spin_lock_irq(&engine->timeline->lock); + for (rb = engine->execlist_first; rb; rb = rb_next(rb)) { + rq = rb_entry(rb, typeof(*rq), priotree.node); print_request(m, rq, "\t\tQ "); } - spin_unlock_irq(&engine->execlist_lock); + spin_unlock_irq(&engine->timeline->lock); } else if (INTEL_GEN(dev_priv) > 6) { seq_printf(m, "\tPP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(engine))); diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 0213a3090ab3..445fec9c2841 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -150,7 +150,7 @@ static void intel_detect_pch(struct drm_device *dev) /* In all current cases, num_pipes is equivalent to the PCH_NOP setting * (which really amounts to a PCH but no South Display). */ - if (INTEL_INFO(dev)->num_pipes == 0) { + if (INTEL_INFO(dev_priv)->num_pipes == 0) { dev_priv->pch_type = PCH_NOP; return; } @@ -323,6 +323,10 @@ static int i915_getparam(struct drm_device *dev, void *data, */ value = i915_gem_mmap_gtt_version(); break; + case I915_PARAM_HAS_SCHEDULER: + value = dev_priv->engine[RCS] && + dev_priv->engine[RCS]->schedule; + break; case I915_PARAM_MMAP_VERSION: /* Remember to bump this if the version changes! */ case I915_PARAM_HAS_GEM: @@ -374,12 +378,12 @@ static int intel_alloc_mchbar_resource(struct drm_device *dev) { struct drm_i915_private *dev_priv = to_i915(dev); - int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; + int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; u32 temp_lo, temp_hi = 0; u64 mchbar_addr; int ret; - if (INTEL_INFO(dev)->gen >= 4) + if (INTEL_GEN(dev_priv) >= 4) pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); mchbar_addr = ((u64)temp_hi << 32) | temp_lo; @@ -406,7 +410,7 @@ intel_alloc_mchbar_resource(struct drm_device *dev) return ret; } - if (INTEL_INFO(dev)->gen >= 4) + if (INTEL_GEN(dev_priv) >= 4) pci_write_config_dword(dev_priv->bridge_dev, reg + 4, upper_32_bits(dev_priv->mch_res.start)); @@ -420,7 +424,7 @@ static void intel_setup_mchbar(struct drm_device *dev) { struct drm_i915_private *dev_priv = to_i915(dev); - int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; + int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; u32 temp; bool enabled; @@ -460,7 +464,7 @@ static void intel_teardown_mchbar(struct drm_device *dev) { struct drm_i915_private *dev_priv = to_i915(dev); - int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; + int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; if (dev_priv->mchbar_need_disable) { if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { @@ -491,7 +495,7 @@ static unsigned int i915_vga_set_decode(void *cookie, bool state) { struct drm_device *dev = cookie; - intel_modeset_vga_set_state(dev, state); + intel_modeset_vga_set_state(to_i915(dev), state); if (state) return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; @@ -607,7 +611,7 @@ static int i915_load_modeset_init(struct drm_device *dev) intel_modeset_gem_init(dev); - if (INTEL_INFO(dev)->num_pipes == 0) + if (INTEL_INFO(dev_priv)->num_pipes == 0) return 0; ret = intel_fbdev_init(dev); @@ -879,7 +883,7 @@ static int i915_mmio_setup(struct drm_device *dev) * the register BAR remains the same size for all the earlier * generations up to Ironlake. */ - if (INTEL_INFO(dev)->gen < 5) + if (INTEL_GEN(dev_priv) < 5) mmio_size = 512 * 1024; else mmio_size = 2 * 1024 * 1024; @@ -1168,8 +1172,8 @@ static void i915_driver_unregister(struct drm_i915_private *dev_priv) /** * i915_driver_load - setup chip and create an initial config - * @dev: DRM device - * @flags: startup flags + * @pdev: PCI device + * @ent: matching PCI ID entry * * The driver load routine has to do several things: * - drive output discovery via intel_modeset_init() @@ -1438,7 +1442,7 @@ static int i915_drm_suspend(struct drm_device *dev) intel_suspend_hw(dev_priv); - i915_gem_suspend_gtt_mappings(dev); + i915_gem_suspend_gtt_mappings(dev_priv); i915_save_state(dev); @@ -1512,7 +1516,7 @@ static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation) * Fujitsu FSC S7110 * Acer Aspire 1830T */ - if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6)) + if (!(hibernation && INTEL_GEN(dev_priv) < 6)) pci_set_power_state(pdev, PCI_D3hot); dev_priv->suspended_to_idle = suspend_to_idle(dev_priv); @@ -2422,7 +2426,7 @@ static int intel_runtime_resume(struct device *kdev) * No point of rolling back things in case of an error, as the best * we can do is to hope that things will still work (and disable RPM). */ - i915_gem_init_swizzling(dev); + i915_gem_init_swizzling(dev_priv); intel_runtime_pm_enable_interrupts(dev_priv); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 6f4a6bcf6ed4..56002a52936d 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -60,11 +60,15 @@ #include "intel_ringbuffer.h" #include "i915_gem.h" +#include "i915_gem_fence_reg.h" +#include "i915_gem_object.h" #include "i915_gem_gtt.h" #include "i915_gem_render_state.h" #include "i915_gem_request.h" #include "i915_gem_timeline.h" +#include "i915_vma.h" + #include "intel_gvt.h" /* General customization: @@ -72,8 +76,8 @@ #define DRIVER_NAME "i915" #define DRIVER_DESC "Intel Graphics" -#define DRIVER_DATE "20161108" -#define DRIVER_TIMESTAMP 1478587895 +#define DRIVER_DATE "20161121" +#define DRIVER_TIMESTAMP 1479717903 #undef WARN_ON /* Many gcc seem to no see through this and fall over :( */ @@ -125,6 +129,11 @@ static inline const char *onoff(bool v) return v ? "on" : "off"; } +static inline const char *enableddisabled(bool v) +{ + return v ? "enabled" : "disabled"; +} + enum pipe { INVALID_PIPE = -1, PIPE_A = 0, @@ -459,23 +468,6 @@ struct intel_opregion { struct intel_overlay; struct intel_overlay_error_state; -struct drm_i915_fence_reg { - struct list_head link; - struct drm_i915_private *i915; - struct i915_vma *vma; - int pin_count; - int id; - /** - * Whether the tiling parameters for the currently - * associated fence register have changed. Note that - * for the purposes of tracking tiling changes we also - * treat the unfenced register, the register slot that - * the object occupies whilst it executes a fenced - * command (such as BLT on gen2/3), as a "fence". - */ - bool dirty; -}; - struct sdvo_device_mapping { u8 initialized; u8 dvo_port; @@ -487,6 +479,7 @@ struct sdvo_device_mapping { struct intel_connector; struct intel_encoder; +struct intel_atomic_state; struct intel_crtc_state; struct intel_initial_plane_config; struct intel_crtc; @@ -500,8 +493,12 @@ struct drm_i915_display_funcs { int (*compute_intermediate_wm)(struct drm_device *dev, struct intel_crtc *intel_crtc, struct intel_crtc_state *newstate); - void (*initial_watermarks)(struct intel_crtc_state *cstate); - void (*optimize_watermarks)(struct intel_crtc_state *cstate); + void (*initial_watermarks)(struct intel_atomic_state *state, + struct intel_crtc_state *cstate); + void (*atomic_update_watermarks)(struct intel_atomic_state *state, + struct intel_crtc_state *cstate); + void (*optimize_watermarks)(struct intel_atomic_state *state, + struct intel_crtc_state *cstate); int (*compute_global_watermarks)(struct drm_atomic_state *state); void (*update_wm)(struct intel_crtc *crtc); int (*modeset_calc_cdclk)(struct drm_atomic_state *state); @@ -562,6 +559,18 @@ enum forcewake_domains { #define FW_REG_READ (1) #define FW_REG_WRITE (2) +enum decoupled_power_domain { + GEN9_DECOUPLED_PD_BLITTER = 0, + GEN9_DECOUPLED_PD_RENDER, + GEN9_DECOUPLED_PD_MEDIA, + GEN9_DECOUPLED_PD_ALL +}; + +enum decoupled_ops { + GEN9_DECOUPLED_OP_WRITE = 0, + GEN9_DECOUPLED_OP_READ +}; + enum forcewake_domains intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv, i915_reg_t reg, unsigned int op); @@ -668,7 +677,7 @@ struct intel_csr { func(is_skylake); \ func(is_broxton); \ func(is_kabylake); \ - func(is_preliminary); \ + func(is_alpha_support); \ /* Keep has_* in alphabetical order */ \ func(has_64bit_reloc); \ func(has_csr); \ @@ -696,7 +705,8 @@ struct intel_csr { func(cursor_needs_physical); \ func(hws_needs_physical); \ func(overlay_needs_physical); \ - func(supports_tv) + func(supports_tv); \ + func(has_decoupled_mmio) struct sseu_dev_info { u8 slice_mask; @@ -949,6 +959,7 @@ struct i915_gem_context { /* Unique identifier for this context, used by the hw for tracking */ unsigned int hw_id; u32 user_handle; + int priority; /* greater priorities are serviced first */ u32 ggtt_alignment; @@ -1791,6 +1802,7 @@ struct drm_i915_private { struct kmem_cache *objects; struct kmem_cache *vmas; struct kmem_cache *requests; + struct kmem_cache *dependencies; const struct intel_device_info info; @@ -2053,13 +2065,6 @@ struct drm_i915_private { */ uint16_t skl_latency[8]; - /* - * The skl_wm_values structure is a bit too big for stack - * allocation, so we keep the staging struct where we store - * intermediate results here instead. - */ - struct skl_wm_values skl_results; - /* current hardware state */ union { struct ilk_wm_values hw; @@ -2179,31 +2184,6 @@ enum hdmi_force_audio { #define I915_GTT_OFFSET_NONE ((u32)-1) -struct drm_i915_gem_object_ops { - unsigned int flags; -#define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1 -#define I915_GEM_OBJECT_IS_SHRINKABLE 0x2 - - /* Interface between the GEM object and its backing storage. - * get_pages() is called once prior to the use of the associated set - * of pages before to binding them into the GTT, and put_pages() is - * called after we no longer need them. As we expect there to be - * associated cost with migrating pages between the backing storage - * and making them available for the GPU (e.g. clflush), we may hold - * onto the pages after they are no longer referenced by the GPU - * in case they may be used again shortly (for example migrating the - * pages to a different memory domain within the GTT). put_pages() - * will therefore most likely be called when the object itself is - * being released or under memory pressure (where we attempt to - * reap pages for the shrinker). - */ - struct sg_table *(*get_pages)(struct drm_i915_gem_object *); - void (*put_pages)(struct drm_i915_gem_object *, struct sg_table *); - - int (*dmabuf_export)(struct drm_i915_gem_object *); - void (*release)(struct drm_i915_gem_object *); -}; - /* * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is * considered to be the frontbuffer for the given plane interface-wise. This @@ -2225,292 +2205,6 @@ struct drm_i915_gem_object_ops { #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) -struct drm_i915_gem_object { - struct drm_gem_object base; - - const struct drm_i915_gem_object_ops *ops; - - /** List of VMAs backed by this object */ - struct list_head vma_list; - struct rb_root vma_tree; - - /** Stolen memory for this object, instead of being backed by shmem. */ - struct drm_mm_node *stolen; - struct list_head global_link; - union { - struct rcu_head rcu; - struct llist_node freed; - }; - - /** - * Whether the object is currently in the GGTT mmap. - */ - struct list_head userfault_link; - - /** Used in execbuf to temporarily hold a ref */ - struct list_head obj_exec_link; - - struct list_head batch_pool_link; - - unsigned long flags; - - /** - * Have we taken a reference for the object for incomplete GPU - * activity? - */ -#define I915_BO_ACTIVE_REF 0 - - /* - * Is the object to be mapped as read-only to the GPU - * Only honoured if hardware has relevant pte bit - */ - unsigned long gt_ro:1; - unsigned int cache_level:3; - unsigned int cache_dirty:1; - - atomic_t frontbuffer_bits; - unsigned int frontbuffer_ggtt_origin; /* write once */ - - /** Current tiling stride for the object, if it's tiled. */ - unsigned int tiling_and_stride; -#define FENCE_MINIMUM_STRIDE 128 /* See i915_tiling_ok() */ -#define TILING_MASK (FENCE_MINIMUM_STRIDE-1) -#define STRIDE_MASK (~TILING_MASK) - - /** Count of VMA actually bound by this object */ - unsigned int bind_count; - unsigned int active_count; - unsigned int pin_display; - - struct { - struct mutex lock; /* protects the pages and their use */ - atomic_t pages_pin_count; - - struct sg_table *pages; - void *mapping; - - struct i915_gem_object_page_iter { - struct scatterlist *sg_pos; - unsigned int sg_idx; /* in pages, but 32bit eek! */ - - struct radix_tree_root radix; - struct mutex lock; /* protects this cache */ - } get_page; - - /** - * Advice: are the backing pages purgeable? - */ - unsigned int madv:2; - - /** - * This is set if the object has been written to since the - * pages were last acquired. - */ - bool dirty:1; - - /** - * This is set if the object has been pinned due to unknown - * swizzling. - */ - bool quirked:1; - } mm; - - /** Breadcrumb of last rendering to the buffer. - * There can only be one writer, but we allow for multiple readers. - * If there is a writer that necessarily implies that all other - * read requests are complete - but we may only be lazily clearing - * the read requests. A read request is naturally the most recent - * request on a ring, so we may have two different write and read - * requests on one ring where the write request is older than the - * read request. This allows for the CPU to read from an active - * buffer by only waiting for the write to complete. - */ - struct reservation_object *resv; - - /** References from framebuffers, locks out tiling changes. */ - unsigned long framebuffer_references; - - /** Record of address bit 17 of each page at last unbind. */ - unsigned long *bit_17; - - struct i915_gem_userptr { - uintptr_t ptr; - unsigned read_only :1; - - struct i915_mm_struct *mm; - struct i915_mmu_object *mmu_object; - struct work_struct *work; - } userptr; - - /** for phys allocated objects */ - struct drm_dma_handle *phys_handle; - - struct reservation_object __builtin_resv; -}; - -static inline struct drm_i915_gem_object * -to_intel_bo(struct drm_gem_object *gem) -{ - /* Assert that to_intel_bo(NULL) == NULL */ - BUILD_BUG_ON(offsetof(struct drm_i915_gem_object, base)); - - return container_of(gem, struct drm_i915_gem_object, base); -} - -/** - * i915_gem_object_lookup_rcu - look up a temporary GEM object from its handle - * @filp: DRM file private date - * @handle: userspace handle - * - * Returns: - * - * A pointer to the object named by the handle if such exists on @filp, NULL - * otherwise. This object is only valid whilst under the RCU read lock, and - * note carefully the object may be in the process of being destroyed. - */ -static inline struct drm_i915_gem_object * -i915_gem_object_lookup_rcu(struct drm_file *file, u32 handle) -{ -#ifdef CONFIG_LOCKDEP - WARN_ON(debug_locks && !lock_is_held(&rcu_lock_map)); -#endif - return idr_find(&file->object_idr, handle); -} - -static inline struct drm_i915_gem_object * -i915_gem_object_lookup(struct drm_file *file, u32 handle) -{ - struct drm_i915_gem_object *obj; - - rcu_read_lock(); - obj = i915_gem_object_lookup_rcu(file, handle); - if (obj && !kref_get_unless_zero(&obj->base.refcount)) - obj = NULL; - rcu_read_unlock(); - - return obj; -} - -__deprecated -extern struct drm_gem_object * -drm_gem_object_lookup(struct drm_file *file, u32 handle); - -__attribute__((nonnull)) -static inline struct drm_i915_gem_object * -i915_gem_object_get(struct drm_i915_gem_object *obj) -{ - drm_gem_object_reference(&obj->base); - return obj; -} - -__deprecated -extern void drm_gem_object_reference(struct drm_gem_object *); - -__attribute__((nonnull)) -static inline void -i915_gem_object_put(struct drm_i915_gem_object *obj) -{ - __drm_gem_object_unreference(&obj->base); -} - -__deprecated -extern void drm_gem_object_unreference(struct drm_gem_object *); - -__deprecated -extern void drm_gem_object_unreference_unlocked(struct drm_gem_object *); - -static inline bool -i915_gem_object_is_dead(const struct drm_i915_gem_object *obj) -{ - return atomic_read(&obj->base.refcount.refcount) == 0; -} - -static inline bool -i915_gem_object_has_struct_page(const struct drm_i915_gem_object *obj) -{ - return obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE; -} - -static inline bool -i915_gem_object_is_shrinkable(const struct drm_i915_gem_object *obj) -{ - return obj->ops->flags & I915_GEM_OBJECT_IS_SHRINKABLE; -} - -static inline bool -i915_gem_object_is_active(const struct drm_i915_gem_object *obj) -{ - return obj->active_count; -} - -static inline bool -i915_gem_object_has_active_reference(const struct drm_i915_gem_object *obj) -{ - return test_bit(I915_BO_ACTIVE_REF, &obj->flags); -} - -static inline void -i915_gem_object_set_active_reference(struct drm_i915_gem_object *obj) -{ - lockdep_assert_held(&obj->base.dev->struct_mutex); - __set_bit(I915_BO_ACTIVE_REF, &obj->flags); -} - -static inline void -i915_gem_object_clear_active_reference(struct drm_i915_gem_object *obj) -{ - lockdep_assert_held(&obj->base.dev->struct_mutex); - __clear_bit(I915_BO_ACTIVE_REF, &obj->flags); -} - -void __i915_gem_object_release_unless_active(struct drm_i915_gem_object *obj); - -static inline unsigned int -i915_gem_object_get_tiling(struct drm_i915_gem_object *obj) -{ - return obj->tiling_and_stride & TILING_MASK; -} - -static inline bool -i915_gem_object_is_tiled(struct drm_i915_gem_object *obj) -{ - return i915_gem_object_get_tiling(obj) != I915_TILING_NONE; -} - -static inline unsigned int -i915_gem_object_get_stride(struct drm_i915_gem_object *obj) -{ - return obj->tiling_and_stride & STRIDE_MASK; -} - -static inline struct intel_engine_cs * -i915_gem_object_last_write_engine(struct drm_i915_gem_object *obj) -{ - struct intel_engine_cs *engine = NULL; - struct dma_fence *fence; - - rcu_read_lock(); - fence = reservation_object_get_excl_rcu(obj->resv); - rcu_read_unlock(); - - if (fence && dma_fence_is_i915(fence) && !dma_fence_is_signaled(fence)) - engine = to_request(fence)->engine; - dma_fence_put(fence); - - return engine; -} - -static inline struct i915_vma *i915_vma_get(struct i915_vma *vma) -{ - i915_gem_object_get(vma->obj); - return vma; -} - -static inline void i915_vma_put(struct i915_vma *vma) -{ - i915_gem_object_put(vma->obj); -} - /* * Optimised SGL iterator for GEM objects */ @@ -2683,24 +2377,19 @@ struct drm_i915_cmd_table { int count; }; -/* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */ -#define __I915__(p) ({ \ - struct drm_i915_private *__p; \ - if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \ - __p = (struct drm_i915_private *)p; \ - else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \ - __p = to_i915((struct drm_device *)p); \ - else \ - BUILD_BUG(); \ - __p; \ -}) -#define INTEL_INFO(p) (&__I915__(p)->info) +static inline const struct intel_device_info * +intel_info(const struct drm_i915_private *dev_priv) +{ + return &dev_priv->info; +} + +#define INTEL_INFO(dev_priv) intel_info((dev_priv)) #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen) #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id) #define REVID_FOREVER 0xff -#define INTEL_REVID(p) (__I915__(p)->drm.pdev->revision) +#define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision) #define GEN_FOREVER (0) /* @@ -2797,7 +2486,7 @@ struct drm_i915_cmd_table { #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \ (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030) -#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) +#define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support) #define SKL_REVID_A0 0x0 #define SKL_REVID_B0 0x1 @@ -2851,28 +2540,31 @@ struct drm_i915_cmd_table { #define ALL_ENGINES (~0) #define HAS_ENGINE(dev_priv, id) \ - (!!(INTEL_INFO(dev_priv)->ring_mask & ENGINE_MASK(id))) + (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id))) #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS) #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2) #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS) #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS) -#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) -#define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop) -#define HAS_EDRAM(dev) (!!(__I915__(dev)->edram_cap & EDRAM_ENABLED)) +#define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc) +#define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop) +#define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED)) #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \ IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv)) -#define HWS_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->hws_needs_physical) -#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->has_hw_contexts) -#define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->has_logical_ring_contexts) -#define USES_PPGTT(dev) (i915.enable_ppgtt) -#define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2) -#define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3) +#define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical) -#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) -#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) +#define HAS_HW_CONTEXTS(dev_priv) ((dev_priv)->info.has_hw_contexts) +#define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \ + ((dev_priv)->info.has_logical_ring_contexts) +#define USES_PPGTT(dev_priv) (i915.enable_ppgtt) +#define USES_FULL_PPGTT(dev_priv) (i915.enable_ppgtt >= 2) +#define USES_FULL_48BIT_PPGTT(dev_priv) (i915.enable_ppgtt == 3) + +#define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay) +#define OVERLAY_NEEDS_PHYSICAL(dev_priv) \ + ((dev_priv)->info.overlay_needs_physical) /* Early gen2 have a totally busted CS tlb and require pinned batches. */ #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_845G(dev_priv)) @@ -2889,8 +2581,8 @@ struct drm_i915_cmd_table { * legacy irq no. is shared with another device. The kernel then disables that * interrupt source and so prevents the other device from working properly. */ -#define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) -#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->has_gmbus_irq) +#define HAS_AUX_IRQ(dev_priv) ((dev_priv)->info.gen >= 5) +#define HAS_GMBUS_IRQ(dev_priv) ((dev_priv)->info.has_gmbus_irq) /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte * rows, which changed the alignment requirements and fence programming. @@ -2898,24 +2590,24 @@ struct drm_i915_cmd_table { #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \ !(IS_I915G(dev_priv) || \ IS_I915GM(dev_priv))) -#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) -#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) +#define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv) +#define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug) -#define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2) -#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) -#define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) +#define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2) +#define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr) +#define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc) #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv)) -#define HAS_DP_MST(dev) (INTEL_INFO(dev)->has_dp_mst) +#define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst) -#define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi) -#define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) -#define HAS_PSR(dev) (INTEL_INFO(dev)->has_psr) -#define HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6) -#define HAS_RC6p(dev) (INTEL_INFO(dev)->has_rc6p) +#define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi) +#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg) +#define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr) +#define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6) +#define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p) -#define HAS_CSR(dev) (INTEL_INFO(dev)->has_csr) +#define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr) #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm) #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc) @@ -2925,13 +2617,13 @@ struct drm_i915_cmd_table { * command submission once loaded. But these are logically independent * properties, so we have separate macros to test them. */ -#define HAS_GUC(dev) (INTEL_INFO(dev)->has_guc) -#define HAS_GUC_UCODE(dev) (HAS_GUC(dev)) -#define HAS_GUC_SCHED(dev) (HAS_GUC(dev)) +#define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc) +#define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv)) +#define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv)) -#define HAS_RESOURCE_STREAMER(dev) (INTEL_INFO(dev)->has_resource_streamer) +#define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer) -#define HAS_POOLED_EU(dev) (INTEL_INFO(dev)->has_pooled_eu) +#define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu) #define INTEL_PCH_DEVICE_ID_MASK 0xff00 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 @@ -2971,6 +2663,8 @@ struct drm_i915_cmd_table { #define GT_FREQUENCY_MULTIPLIER 50 #define GEN9_FREQ_SCALER 3 +#define HAS_DECOUPLED_MMIO(dev_priv) (INTEL_INFO(dev_priv)->has_decoupled_mmio) + #include "i915_trace.h" static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv) @@ -3222,13 +2916,6 @@ i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, u64 alignment, u64 flags); -int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, - u32 flags); -void __i915_vma_set_map_and_fenceable(struct i915_vma *vma); -int __must_check i915_vma_unbind(struct i915_vma *vma); -void i915_vma_close(struct i915_vma *vma); -void i915_vma_destroy(struct i915_vma *vma); - int i915_gem_object_unbind(struct drm_i915_gem_object *obj); void i915_gem_release_mmap(struct drm_i915_gem_object *obj); @@ -3405,10 +3092,10 @@ static inline u32 i915_reset_count(struct i915_gpu_error *error) void i915_gem_reset(struct drm_i915_private *dev_priv); void i915_gem_set_wedged(struct drm_i915_private *dev_priv); -bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); +void i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); int __must_check i915_gem_init(struct drm_device *dev); int __must_check i915_gem_init_hw(struct drm_device *dev); -void i915_gem_init_swizzling(struct drm_device *dev); +void i915_gem_init_swizzling(struct drm_i915_private *dev_priv); void i915_gem_cleanup_engines(struct drm_device *dev); int __must_check i915_gem_wait_for_idle(struct drm_i915_private *dev_priv, unsigned int flags); @@ -3419,6 +3106,11 @@ int i915_gem_object_wait(struct drm_i915_gem_object *obj, unsigned int flags, long timeout, struct intel_rps_client *rps); +int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj, + unsigned int flags, + int priority); +#define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX + int __must_check i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write); @@ -3478,57 +3170,13 @@ i915_gem_object_ggtt_offset(struct drm_i915_gem_object *o, return i915_ggtt_offset(i915_gem_object_to_ggtt(o, view)); } -/* i915_gem_fence.c */ +/* i915_gem_fence_reg.c */ int __must_check i915_vma_get_fence(struct i915_vma *vma); int __must_check i915_vma_put_fence(struct i915_vma *vma); -/** - * i915_vma_pin_fence - pin fencing state - * @vma: vma to pin fencing for - * - * This pins the fencing state (whether tiled or untiled) to make sure the - * vma (and its object) is ready to be used as a scanout target. Fencing - * status must be synchronize first by calling i915_vma_get_fence(): - * - * The resulting fence pin reference must be released again with - * i915_vma_unpin_fence(). - * - * Returns: - * - * True if the vma has a fence, false otherwise. - */ -static inline bool -i915_vma_pin_fence(struct i915_vma *vma) -{ - lockdep_assert_held(&vma->vm->dev->struct_mutex); - if (vma->fence) { - vma->fence->pin_count++; - return true; - } else - return false; -} - -/** - * i915_vma_unpin_fence - unpin fencing state - * @vma: vma to unpin fencing for - * - * This releases the fence pin reference acquired through - * i915_vma_pin_fence. It will handle both objects with and without an - * attached fence correctly, callers do not need to distinguish this. - */ -static inline void -i915_vma_unpin_fence(struct i915_vma *vma) -{ - lockdep_assert_held(&vma->vm->dev->struct_mutex); - if (vma->fence) { - GEM_BUG_ON(vma->fence->pin_count <= 0); - vma->fence->pin_count--; - } -} - -void i915_gem_restore_fences(struct drm_device *dev); +void i915_gem_restore_fences(struct drm_i915_private *dev_priv); -void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); +void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv); void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj, struct sg_table *pages); void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj, @@ -3631,7 +3279,7 @@ int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv, u64 end); void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv, struct drm_mm_node *node); -int i915_gem_init_stolen(struct drm_device *dev); +int i915_gem_init_stolen(struct drm_i915_private *dev_priv); void i915_gem_cleanup_stolen(struct drm_device *dev); struct drm_i915_gem_object * i915_gem_object_create_stolen(struct drm_device *dev, u32 size); @@ -3833,10 +3481,11 @@ extern void intel_modeset_gem_init(struct drm_device *dev); extern void intel_modeset_cleanup(struct drm_device *dev); extern int intel_connector_register(struct drm_connector *); extern void intel_connector_unregister(struct drm_connector *); -extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); +extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, + bool state); extern void intel_display_resume(struct drm_device *dev); -extern void i915_redisable_vga(struct drm_device *dev); -extern void i915_redisable_vga_power_on(struct drm_device *dev); +extern void i915_redisable_vga(struct drm_i915_private *dev_priv); +extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv); extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val); extern void intel_init_pch_refclk(struct drm_device *dev); extern void intel_set_rps(struct drm_i915_private *dev_priv, u8 val); @@ -3855,7 +3504,7 @@ extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, extern struct intel_display_error_state * intel_display_capture_error_state(struct drm_i915_private *dev_priv); extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, - struct drm_device *dev, + struct drm_i915_private *dev_priv, struct intel_display_error_state *error); int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val); diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 41e697e5dbcd..902fa427c196 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -34,6 +34,7 @@ #include "intel_drv.h" #include "intel_frontbuffer.h" #include "intel_mocs.h" +#include <linux/dma-fence-array.h> #include <linux/reservation.h> #include <linux/shmem_fs.h> #include <linux/slab.h> @@ -48,7 +49,7 @@ static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *o static bool cpu_cache_is_coherent(struct drm_device *dev, enum i915_cache_level level) { - return HAS_LLC(dev) || level != I915_CACHE_NONE; + return HAS_LLC(to_i915(dev)) || level != I915_CACHE_NONE; } static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) @@ -220,15 +221,17 @@ i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj) } static void -__i915_gem_object_release_shmem(struct drm_i915_gem_object *obj) +__i915_gem_object_release_shmem(struct drm_i915_gem_object *obj, + struct sg_table *pages) { GEM_BUG_ON(obj->mm.madv == __I915_MADV_PURGED); if (obj->mm.madv == I915_MADV_DONTNEED) obj->mm.dirty = false; - if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) - i915_gem_clflush_object(obj, false); + if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0 && + !cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) + drm_clflush_sg(pages); obj->base.read_domains = I915_GEM_DOMAIN_CPU; obj->base.write_domain = I915_GEM_DOMAIN_CPU; @@ -238,7 +241,7 @@ static void i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj, struct sg_table *pages) { - __i915_gem_object_release_shmem(obj); + __i915_gem_object_release_shmem(obj, pages); if (obj->mm.dirty) { struct address_space *mapping = obj->base.filp->f_mapping; @@ -433,6 +436,70 @@ i915_gem_object_wait_reservation(struct reservation_object *resv, return timeout; } +static void __fence_set_priority(struct dma_fence *fence, int prio) +{ + struct drm_i915_gem_request *rq; + struct intel_engine_cs *engine; + + if (!dma_fence_is_i915(fence)) + return; + + rq = to_request(fence); + engine = rq->engine; + if (!engine->schedule) + return; + + engine->schedule(rq, prio); +} + +static void fence_set_priority(struct dma_fence *fence, int prio) +{ + /* Recurse once into a fence-array */ + if (dma_fence_is_array(fence)) { + struct dma_fence_array *array = to_dma_fence_array(fence); + int i; + + for (i = 0; i < array->num_fences; i++) + __fence_set_priority(array->fences[i], prio); + } else { + __fence_set_priority(fence, prio); + } +} + +int +i915_gem_object_wait_priority(struct drm_i915_gem_object *obj, + unsigned int flags, + int prio) +{ + struct dma_fence *excl; + + if (flags & I915_WAIT_ALL) { + struct dma_fence **shared; + unsigned int count, i; + int ret; + + ret = reservation_object_get_fences_rcu(obj->resv, + &excl, &count, &shared); + if (ret) + return ret; + + for (i = 0; i < count; i++) { + fence_set_priority(shared[i], prio); + dma_fence_put(shared[i]); + } + + kfree(shared); + } else { + excl = reservation_object_get_excl_rcu(obj->resv); + } + + if (excl) { + fence_set_priority(excl, prio); + dma_fence_put(excl); + } + return 0; +} + /** * Waits for rendering to the object to be completed * @obj: i915 gem object @@ -1757,7 +1824,7 @@ int i915_gem_fault(struct vm_area_struct *area, struct vm_fault *vmf) goto err_rpm; /* Access to snoopable pages through the GTT is incoherent. */ - if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { + if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv)) { ret = -EFAULT; goto err_unlock; } @@ -2150,7 +2217,7 @@ i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj, struct sgt_iter sgt_iter; struct page *page; - __i915_gem_object_release_shmem(obj); + __i915_gem_object_release_shmem(obj, pages); i915_gem_gtt_finish_pages(obj, pages); @@ -2232,6 +2299,30 @@ static unsigned int swiotlb_max_size(void) #endif } +static void i915_sg_trim(struct sg_table *orig_st) +{ + struct sg_table new_st; + struct scatterlist *sg, *new_sg; + unsigned int i; + + if (orig_st->nents == orig_st->orig_nents) + return; + + if (sg_alloc_table(&new_st, orig_st->nents, GFP_KERNEL)) + return; + + new_sg = new_st.sgl; + for_each_sg(orig_st->sgl, sg, orig_st->nents, i) { + sg_set_page(new_sg, sg_page(sg), sg->length, 0); + /* called before being DMA mapped, no need to copy sg->dma_* */ + new_sg = sg_next(new_sg); + } + + sg_free_table(orig_st); + + *orig_st = new_st; +} + static struct sg_table * i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) { @@ -2296,7 +2387,7 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) page = shmem_read_mapping_page(mapping, i); if (IS_ERR(page)) { ret = PTR_ERR(page); - goto err_pages; + goto err_sg; } } if (!i || @@ -2317,6 +2408,9 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) if (sg) /* loop terminated early; short sg table */ sg_mark_end(sg); + /* Trim unused sg entries to avoid wasting memory. */ + i915_sg_trim(st); + ret = i915_gem_gtt_prepare_pages(obj, st); if (ret) goto err_pages; @@ -2326,8 +2420,9 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) return st; -err_pages: +err_sg: sg_mark_end(sg); +err_pages: for_each_sgt_page(page, sgt_iter, st) put_page(page); sg_free_table(st); @@ -2657,7 +2752,7 @@ void i915_gem_reset(struct drm_i915_private *dev_priv) for_each_engine(engine, dev_priv, id) i915_gem_reset_engine(engine); - i915_gem_restore_fences(&dev_priv->drm); + i915_gem_restore_fences(dev_priv); if (dev_priv->gt.awake) { intel_sanitize_gt_powersave(dev_priv); @@ -2689,12 +2784,17 @@ static void i915_gem_cleanup_engine(struct intel_engine_cs *engine) */ if (i915.enable_execlists) { - spin_lock(&engine->execlist_lock); - INIT_LIST_HEAD(&engine->execlist_queue); + unsigned long flags; + + spin_lock_irqsave(&engine->timeline->lock, flags); + i915_gem_request_put(engine->execlist_port[0].request); i915_gem_request_put(engine->execlist_port[1].request); memset(engine->execlist_port, 0, sizeof(engine->execlist_port)); - spin_unlock(&engine->execlist_lock); + engine->execlist_queue = RB_ROOT; + engine->execlist_first = NULL; + + spin_unlock_irqrestore(&engine->timeline->lock, flags); } } @@ -2892,117 +2992,6 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) return ret; } -static void __i915_vma_iounmap(struct i915_vma *vma) -{ - GEM_BUG_ON(i915_vma_is_pinned(vma)); - - if (vma->iomap == NULL) - return; - - io_mapping_unmap(vma->iomap); - vma->iomap = NULL; -} - -int i915_vma_unbind(struct i915_vma *vma) -{ - struct drm_i915_gem_object *obj = vma->obj; - unsigned long active; - int ret; - - lockdep_assert_held(&obj->base.dev->struct_mutex); - - /* First wait upon any activity as retiring the request may - * have side-effects such as unpinning or even unbinding this vma. - */ - active = i915_vma_get_active(vma); - if (active) { - int idx; - - /* When a closed VMA is retired, it is unbound - eek. - * In order to prevent it from being recursively closed, - * take a pin on the vma so that the second unbind is - * aborted. - * - * Even more scary is that the retire callback may free - * the object (last active vma). To prevent the explosion - * we defer the actual object free to a worker that can - * only proceed once it acquires the struct_mutex (which - * we currently hold, therefore it cannot free this object - * before we are finished). - */ - __i915_vma_pin(vma); - - for_each_active(active, idx) { - ret = i915_gem_active_retire(&vma->last_read[idx], - &vma->vm->dev->struct_mutex); - if (ret) - break; - } - - __i915_vma_unpin(vma); - if (ret) - return ret; - - GEM_BUG_ON(i915_vma_is_active(vma)); - } - - if (i915_vma_is_pinned(vma)) - return -EBUSY; - - if (!drm_mm_node_allocated(&vma->node)) - goto destroy; - - GEM_BUG_ON(obj->bind_count == 0); - GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj)); - - if (i915_vma_is_map_and_fenceable(vma)) { - /* release the fence reg _after_ flushing */ - ret = i915_vma_put_fence(vma); - if (ret) - return ret; - - /* Force a pagefault for domain tracking on next user access */ - i915_gem_release_mmap(obj); - - __i915_vma_iounmap(vma); - vma->flags &= ~I915_VMA_CAN_FENCE; - } - - if (likely(!vma->vm->closed)) { - trace_i915_vma_unbind(vma); - vma->vm->unbind_vma(vma); - } - vma->flags &= ~(I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND); - - drm_mm_remove_node(&vma->node); - list_move_tail(&vma->vm_link, &vma->vm->unbound_list); - - if (vma->pages != obj->mm.pages) { - GEM_BUG_ON(!vma->pages); - sg_free_table(vma->pages); - kfree(vma->pages); - } - vma->pages = NULL; - - /* Since the unbound list is global, only move to that list if - * no more VMAs exist. */ - if (--obj->bind_count == 0) - list_move_tail(&obj->global_link, - &to_i915(obj->base.dev)->mm.unbound_list); - - /* And finally now the object is completely decoupled from this vma, - * we can drop its hold on the backing storage and allow it to be - * reaped by the shrinker. - */ - i915_gem_object_unpin_pages(obj); - -destroy: - if (unlikely(i915_vma_is_closed(vma))) - i915_vma_destroy(vma); - - return 0; -} - static int wait_for_timeline(struct i915_gem_timeline *tl, unsigned int flags) { int ret, i; @@ -3018,201 +3007,43 @@ static int wait_for_timeline(struct i915_gem_timeline *tl, unsigned int flags) int i915_gem_wait_for_idle(struct drm_i915_private *i915, unsigned int flags) { - struct i915_gem_timeline *tl; int ret; - list_for_each_entry(tl, &i915->gt.timelines, link) { - ret = wait_for_timeline(tl, flags); - if (ret) - return ret; - } - - return 0; -} - -static bool i915_gem_valid_gtt_space(struct i915_vma *vma, - unsigned long cache_level) -{ - struct drm_mm_node *gtt_space = &vma->node; - struct drm_mm_node *other; - - /* - * On some machines we have to be careful when putting differing types - * of snoopable memory together to avoid the prefetcher crossing memory - * domains and dying. During vm initialisation, we decide whether or not - * these constraints apply and set the drm_mm.color_adjust - * appropriately. - */ - if (vma->vm->mm.color_adjust == NULL) - return true; - - if (!drm_mm_node_allocated(gtt_space)) - return true; - - if (list_empty(>t_space->node_list)) - return true; - - other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); - if (other->allocated && !other->hole_follows && other->color != cache_level) - return false; + if (flags & I915_WAIT_LOCKED) { + struct i915_gem_timeline *tl; - other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); - if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) - return false; + lockdep_assert_held(&i915->drm.struct_mutex); - return true; -} - -/** - * i915_vma_insert - finds a slot for the vma in its address space - * @vma: the vma - * @size: requested size in bytes (can be larger than the VMA) - * @alignment: required alignment - * @flags: mask of PIN_* flags to use - * - * First we try to allocate some free space that meets the requirements for - * the VMA. Failiing that, if the flags permit, it will evict an old VMA, - * preferrably the oldest idle entry to make room for the new VMA. - * - * Returns: - * 0 on success, negative error code otherwise. - */ -static int -i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) -{ - struct drm_i915_private *dev_priv = to_i915(vma->vm->dev); - struct drm_i915_gem_object *obj = vma->obj; - u64 start, end; - int ret; - - GEM_BUG_ON(vma->flags & (I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND)); - GEM_BUG_ON(drm_mm_node_allocated(&vma->node)); - - size = max(size, vma->size); - if (flags & PIN_MAPPABLE) - size = i915_gem_get_ggtt_size(dev_priv, size, - i915_gem_object_get_tiling(obj)); - - alignment = max(max(alignment, vma->display_alignment), - i915_gem_get_ggtt_alignment(dev_priv, size, - i915_gem_object_get_tiling(obj), - flags & PIN_MAPPABLE)); - - start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0; - - end = vma->vm->total; - if (flags & PIN_MAPPABLE) - end = min_t(u64, end, dev_priv->ggtt.mappable_end); - if (flags & PIN_ZONE_4G) - end = min_t(u64, end, (1ULL << 32) - PAGE_SIZE); - - /* If binding the object/GGTT view requires more space than the entire - * aperture has, reject it early before evicting everything in a vain - * attempt to find space. - */ - if (size > end) { - DRM_DEBUG("Attempting to bind an object larger than the aperture: request=%llu [object=%zd] > %s aperture=%llu\n", - size, obj->base.size, - flags & PIN_MAPPABLE ? "mappable" : "total", - end); - return -E2BIG; - } - - ret = i915_gem_object_pin_pages(obj); - if (ret) - return ret; - - if (flags & PIN_OFFSET_FIXED) { - u64 offset = flags & PIN_OFFSET_MASK; - if (offset & (alignment - 1) || offset > end - size) { - ret = -EINVAL; - goto err_unpin; - } - - vma->node.start = offset; - vma->node.size = size; - vma->node.color = obj->cache_level; - ret = drm_mm_reserve_node(&vma->vm->mm, &vma->node); - if (ret) { - ret = i915_gem_evict_for_vma(vma); - if (ret == 0) - ret = drm_mm_reserve_node(&vma->vm->mm, &vma->node); + list_for_each_entry(tl, &i915->gt.timelines, link) { + ret = wait_for_timeline(tl, flags); if (ret) - goto err_unpin; + return ret; } } else { - u32 search_flag, alloc_flag; - - if (flags & PIN_HIGH) { - search_flag = DRM_MM_SEARCH_BELOW; - alloc_flag = DRM_MM_CREATE_TOP; - } else { - search_flag = DRM_MM_SEARCH_DEFAULT; - alloc_flag = DRM_MM_CREATE_DEFAULT; - } - - /* We only allocate in PAGE_SIZE/GTT_PAGE_SIZE (4096) chunks, - * so we know that we always have a minimum alignment of 4096. - * The drm_mm range manager is optimised to return results - * with zero alignment, so where possible use the optimal - * path. - */ - if (alignment <= 4096) - alignment = 0; - -search_free: - ret = drm_mm_insert_node_in_range_generic(&vma->vm->mm, - &vma->node, - size, alignment, - obj->cache_level, - start, end, - search_flag, - alloc_flag); - if (ret) { - ret = i915_gem_evict_something(vma->vm, size, alignment, - obj->cache_level, - start, end, - flags); - if (ret == 0) - goto search_free; - - goto err_unpin; - } - - GEM_BUG_ON(vma->node.start < start); - GEM_BUG_ON(vma->node.start + vma->node.size > end); + ret = wait_for_timeline(&i915->gt.global_timeline, flags); + if (ret) + return ret; } - GEM_BUG_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level)); - - list_move_tail(&obj->global_link, &dev_priv->mm.bound_list); - list_move_tail(&vma->vm_link, &vma->vm->inactive_list); - obj->bind_count++; - GEM_BUG_ON(atomic_read(&obj->mm.pages_pin_count) < obj->bind_count); return 0; - -err_unpin: - i915_gem_object_unpin_pages(obj); - return ret; } -bool -i915_gem_clflush_object(struct drm_i915_gem_object *obj, - bool force) +void i915_gem_clflush_object(struct drm_i915_gem_object *obj, + bool force) { /* If we don't have a page list set up, then we're not pinned * to GPU, and we can ignore the cache flush because it'll happen * again at bind time. */ if (!obj->mm.pages) - return false; + return; /* * Stolen memory is always coherent with the GPU as it is explicitly * marked as wc by the system, or the system is cache-coherent. */ if (obj->stolen || obj->phys_handle) - return false; + return; /* If the GPU is snooping the contents of the CPU cache, * we do not need to manually clear the CPU cache lines. However, @@ -3224,14 +3055,12 @@ i915_gem_clflush_object(struct drm_i915_gem_object *obj, */ if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) { obj->cache_dirty = true; - return false; + return; } trace_i915_gem_object_clflush(obj); drm_clflush_sg(obj->mm.pages); obj->cache_dirty = false; - - return true; } /** Flushes the GTT write domain for the object if it's dirty. */ @@ -3277,9 +3106,7 @@ i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) return; - if (i915_gem_clflush_object(obj, obj->pin_display)) - i915_gem_chipset_flush(to_i915(obj->base.dev)); - + i915_gem_clflush_object(obj, obj->pin_display); intel_fb_obj_flush(obj, false, ORIGIN_CPU); obj->base.write_domain = 0; @@ -3378,12 +3205,12 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, enum i915_cache_level cache_level) { struct i915_vma *vma; - int ret = 0; + int ret; lockdep_assert_held(&obj->base.dev->struct_mutex); if (obj->cache_level == cache_level) - goto out; + return 0; /* Inspect the list of currently bound VMA and unbind any that would * be invalid given the new cache-level. This is principally to @@ -3435,7 +3262,8 @@ restart: if (ret) return ret; - if (!HAS_LLC(obj->base.dev) && cache_level != I915_CACHE_NONE) { + if (!HAS_LLC(to_i915(obj->base.dev)) && + cache_level != I915_CACHE_NONE) { /* Access to snoopable pages through the GTT is * incoherent and on some machines causes a hard * lockup. Relinquish the CPU mmaping to force @@ -3477,20 +3305,14 @@ restart: } } + if (obj->base.write_domain == I915_GEM_DOMAIN_CPU && + cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) + obj->cache_dirty = true; + list_for_each_entry(vma, &obj->vma_list, obj_link) vma->node.color = cache_level; obj->cache_level = cache_level; -out: - /* Flush the dirty CPU caches to the backing storage so that the - * object is now coherent at its new cache level (with respect - * to the access domain). - */ - if (obj->cache_dirty && cpu_write_needs_clflush(obj)) { - if (i915_gem_clflush_object(obj, true)) - i915_gem_chipset_flush(to_i915(obj->base.dev)); - } - return 0; } @@ -3646,7 +3468,11 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, vma->display_alignment = max_t(u64, vma->display_alignment, alignment); - i915_gem_object_flush_cpu_write_domain(obj); + /* Treat this as an end-of-frame, like intel_user_framebuffer_dirty() */ + if (obj->cache_dirty) { + i915_gem_clflush_object(obj, true); + intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); + } old_write_domain = obj->base.write_domain; old_read_domains = obj->base.read_domains; @@ -3798,100 +3624,6 @@ i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) return ret < 0 ? ret : 0; } -static bool -i915_vma_misplaced(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) -{ - if (!drm_mm_node_allocated(&vma->node)) - return false; - - if (vma->node.size < size) - return true; - - if (alignment && vma->node.start & (alignment - 1)) - return true; - - if (flags & PIN_MAPPABLE && !i915_vma_is_map_and_fenceable(vma)) - return true; - - if (flags & PIN_OFFSET_BIAS && - vma->node.start < (flags & PIN_OFFSET_MASK)) - return true; - - if (flags & PIN_OFFSET_FIXED && - vma->node.start != (flags & PIN_OFFSET_MASK)) - return true; - - return false; -} - -void __i915_vma_set_map_and_fenceable(struct i915_vma *vma) -{ - struct drm_i915_gem_object *obj = vma->obj; - struct drm_i915_private *dev_priv = to_i915(obj->base.dev); - bool mappable, fenceable; - u32 fence_size, fence_alignment; - - fence_size = i915_gem_get_ggtt_size(dev_priv, - vma->size, - i915_gem_object_get_tiling(obj)); - fence_alignment = i915_gem_get_ggtt_alignment(dev_priv, - vma->size, - i915_gem_object_get_tiling(obj), - true); - - fenceable = (vma->node.size == fence_size && - (vma->node.start & (fence_alignment - 1)) == 0); - - mappable = (vma->node.start + fence_size <= - dev_priv->ggtt.mappable_end); - - /* - * Explicitly disable for rotated VMA since the display does not - * need the fence and the VMA is not accessible to other users. - */ - if (mappable && fenceable && - vma->ggtt_view.type != I915_GGTT_VIEW_ROTATED) - vma->flags |= I915_VMA_CAN_FENCE; - else - vma->flags &= ~I915_VMA_CAN_FENCE; -} - -int __i915_vma_do_pin(struct i915_vma *vma, - u64 size, u64 alignment, u64 flags) -{ - unsigned int bound = vma->flags; - int ret; - - lockdep_assert_held(&vma->vm->dev->struct_mutex); - GEM_BUG_ON((flags & (PIN_GLOBAL | PIN_USER)) == 0); - GEM_BUG_ON((flags & PIN_GLOBAL) && !i915_vma_is_ggtt(vma)); - - if (WARN_ON(bound & I915_VMA_PIN_OVERFLOW)) { - ret = -EBUSY; - goto err; - } - - if ((bound & I915_VMA_BIND_MASK) == 0) { - ret = i915_vma_insert(vma, size, alignment, flags); - if (ret) - goto err; - } - - ret = i915_vma_bind(vma, vma->obj->cache_level, flags); - if (ret) - goto err; - - if ((bound ^ vma->flags) & I915_VMA_GLOBAL_BIND) - __i915_vma_set_map_and_fenceable(vma); - - GEM_BUG_ON(i915_vma_misplaced(vma, size, alignment, flags)); - return 0; - -err: - __i915_vma_unpin(vma); - return ret; -} - struct i915_vma * i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, const struct i915_ggtt_view *view, @@ -4156,6 +3888,16 @@ out: return err; } +static void +frontbuffer_retire(struct i915_gem_active *active, + struct drm_i915_gem_request *request) +{ + struct drm_i915_gem_object *obj = + container_of(active, typeof(*obj), frontbuffer_write); + + intel_fb_obj_flush(obj, true, ORIGIN_CS); +} + void i915_gem_object_init(struct drm_i915_gem_object *obj, const struct drm_i915_gem_object_ops *ops) { @@ -4173,6 +3915,7 @@ void i915_gem_object_init(struct drm_i915_gem_object *obj, obj->resv = &obj->__builtin_resv; obj->frontbuffer_ggtt_origin = ORIGIN_GTT; + init_request_active(&obj->frontbuffer_write, frontbuffer_retire); obj->mm.madv = I915_MADV_WILLNEED; INIT_RADIX_TREE(&obj->mm.get_page.radix, GFP_KERNEL | __GFP_NOWARN); @@ -4235,7 +3978,7 @@ i915_gem_object_create(struct drm_device *dev, u64 size) obj->base.write_domain = I915_GEM_DOMAIN_CPU; obj->base.read_domains = I915_GEM_DOMAIN_CPU; - if (HAS_LLC(dev)) { + if (HAS_LLC(dev_priv)) { /* On some devices, we can have the GPU use the LLC (the CPU * cache) for about a 10% performance improvement * compared to uncached. Graphics requests other than @@ -4481,7 +4224,7 @@ int i915_gem_suspend(struct drm_device *dev) * machines is a good idea, we don't - just in case it leaves the * machine in an unusable condition. */ - if (HAS_HW_CONTEXTS(dev)) { + if (HAS_HW_CONTEXTS(dev_priv)) { int reset = intel_gpu_reset(dev_priv, ALL_ENGINES); WARN_ON(reset && reset != -ENODEV); } @@ -4500,7 +4243,7 @@ void i915_gem_resume(struct drm_device *dev) WARN_ON(dev_priv->gt.awake); mutex_lock(&dev->struct_mutex); - i915_gem_restore_gtt_mappings(dev); + i915_gem_restore_gtt_mappings(dev_priv); /* As we didn't flush the kernel context before suspend, we cannot * guarantee that the context image is complete. So let's just reset @@ -4511,11 +4254,9 @@ void i915_gem_resume(struct drm_device *dev) mutex_unlock(&dev->struct_mutex); } -void i915_gem_init_swizzling(struct drm_device *dev) +void i915_gem_init_swizzling(struct drm_i915_private *dev_priv) { - struct drm_i915_private *dev_priv = to_i915(dev); - - if (INTEL_INFO(dev)->gen < 5 || + if (INTEL_GEN(dev_priv) < 5 || dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) return; @@ -4574,7 +4315,7 @@ i915_gem_init_hw(struct drm_device *dev) /* Double layer security blanket, see i915_gem_init() */ intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); - if (HAS_EDRAM(dev) && INTEL_GEN(dev_priv) < 9) + if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9) I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); if (IS_HASWELL(dev_priv)) @@ -4586,14 +4327,14 @@ i915_gem_init_hw(struct drm_device *dev) u32 temp = I915_READ(GEN7_MSG_CTL); temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); I915_WRITE(GEN7_MSG_CTL, temp); - } else if (INTEL_INFO(dev)->gen >= 7) { + } else if (INTEL_GEN(dev_priv) >= 7) { u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); temp &= ~RESET_PCH_HANDSHAKE_ENABLE; I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); } } - i915_gem_init_swizzling(dev); + i915_gem_init_swizzling(dev_priv); /* * At least 830 can leave some of the unused rings @@ -4605,7 +4346,7 @@ i915_gem_init_hw(struct drm_device *dev) BUG_ON(!dev_priv->kernel_context); - ret = i915_ppgtt_init_hw(dev); + ret = i915_ppgtt_init_hw(dev_priv); if (ret) { DRM_ERROR("PPGTT enable HW failed %d\n", ret); goto out; @@ -4720,7 +4461,6 @@ i915_gem_cleanup_engines(struct drm_device *dev) void i915_gem_load_init_fences(struct drm_i915_private *dev_priv) { - struct drm_device *dev = &dev_priv->drm; int i; if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) && @@ -4744,9 +4484,9 @@ i915_gem_load_init_fences(struct drm_i915_private *dev_priv) fence->id = i; list_add_tail(&fence->link, &dev_priv->mm.fence_list); } - i915_gem_restore_fences(dev); + i915_gem_restore_fences(dev_priv); - i915_gem_detect_bit_6_swizzle(dev); + i915_gem_detect_bit_6_swizzle(dev_priv); } int @@ -4770,14 +4510,18 @@ i915_gem_load_init(struct drm_device *dev) if (!dev_priv->requests) goto err_vmas; + dev_priv->dependencies = KMEM_CACHE(i915_dependency, + SLAB_HWCACHE_ALIGN | + SLAB_RECLAIM_ACCOUNT); + if (!dev_priv->dependencies) + goto err_requests; + mutex_lock(&dev_priv->drm.struct_mutex); INIT_LIST_HEAD(&dev_priv->gt.timelines); - err = i915_gem_timeline_init(dev_priv, - &dev_priv->gt.global_timeline, - "[execution]"); + err = i915_gem_timeline_init__global(dev_priv); mutex_unlock(&dev_priv->drm.struct_mutex); if (err) - goto err_requests; + goto err_dependencies; INIT_LIST_HEAD(&dev_priv->context_list); INIT_WORK(&dev_priv->mm.free_work, __i915_gem_free_work); @@ -4805,6 +4549,8 @@ i915_gem_load_init(struct drm_device *dev) return 0; +err_dependencies: + kmem_cache_destroy(dev_priv->dependencies); err_requests: kmem_cache_destroy(dev_priv->requests); err_vmas: @@ -4821,6 +4567,12 @@ void i915_gem_load_cleanup(struct drm_device *dev) WARN_ON(!llist_empty(&dev_priv->mm.free_list)); + mutex_lock(&dev_priv->drm.struct_mutex); + i915_gem_timeline_fini(&dev_priv->gt.global_timeline); + WARN_ON(!list_empty(&dev_priv->gt.timelines)); + mutex_unlock(&dev_priv->drm.struct_mutex); + + kmem_cache_destroy(dev_priv->dependencies); kmem_cache_destroy(dev_priv->requests); kmem_cache_destroy(dev_priv->vmas); kmem_cache_destroy(dev_priv->objects); @@ -4905,7 +4657,7 @@ int i915_gem_open(struct drm_device *dev, struct drm_file *file) struct drm_i915_file_private *file_priv; int ret; - DRM_DEBUG_DRIVER("\n"); + DRM_DEBUG("\n"); file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); if (!file_priv) diff --git a/drivers/gpu/drm/i915/i915_gem.h b/drivers/gpu/drm/i915/i915_gem.h index 735580d72eb1..51ec793f2e20 100644 --- a/drivers/gpu/drm/i915/i915_gem.h +++ b/drivers/gpu/drm/i915/i915_gem.h @@ -28,7 +28,7 @@ #ifdef CONFIG_DRM_I915_DEBUG_GEM #define GEM_BUG_ON(expr) BUG_ON(expr) #else -#define GEM_BUG_ON(expr) +#define GEM_BUG_ON(expr) do { } while (0) #endif #define I915_NUM_ENGINES 5 diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 6dd475735f0a..1f94b8d6d83d 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -476,6 +476,7 @@ int i915_gem_context_init(struct drm_device *dev) return PTR_ERR(ctx); } + ctx->priority = I915_PRIORITY_MIN; /* lowest priority; idle task */ dev_priv->kernel_context = ctx; DRM_DEBUG_DRIVER("%s context support initialized\n", diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index fb5b44339f71..097d9d8c2315 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -287,7 +287,7 @@ static inline int use_cpu_reloc(struct drm_i915_gem_object *obj) if (DBG_USE_CPU_RELOC) return DBG_USE_CPU_RELOC > 0; - return (HAS_LLC(obj->base.dev) || + return (HAS_LLC(to_i915(obj->base.dev)) || obj->base.write_domain == I915_GEM_DOMAIN_CPU || obj->cache_level != I915_CACHE_NONE); } @@ -833,7 +833,7 @@ need_reloc_mappable(struct i915_vma *vma) return false; /* See also use_cpu_reloc() */ - if (HAS_LLC(vma->obj->base.dev)) + if (HAS_LLC(to_i915(vma->obj->base.dev))) return false; if (vma->obj->base.write_domain == I915_GEM_DOMAIN_CPU) @@ -1276,9 +1276,8 @@ void i915_vma_move_to_active(struct i915_vma *vma, list_move_tail(&vma->vm_link, &vma->vm->active_list); if (flags & EXEC_OBJECT_WRITE) { - i915_gem_active_set(&vma->last_write, req); - - intel_fb_obj_invalidate(obj, ORIGIN_CS); + if (intel_fb_obj_invalidate(obj, ORIGIN_CS)) + i915_gem_active_set(&obj->frontbuffer_write, req); /* update for the implicit flush after a batch */ obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; @@ -1624,7 +1623,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data, } if (args->flags & I915_EXEC_RESOURCE_STREAMER) { - if (!HAS_RESOURCE_STREAMER(dev)) { + if (!HAS_RESOURCE_STREAMER(dev_priv)) { DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n"); return -EINVAL; } @@ -1878,7 +1877,7 @@ i915_gem_execbuffer(struct drm_device *dev, void *data, exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; exec2_list[i].alignment = exec_list[i].alignment; exec2_list[i].offset = exec_list[i].offset; - if (INTEL_INFO(dev)->gen < 4) + if (INTEL_GEN(to_i915(dev)) < 4) exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; else exec2_list[i].flags = 0; diff --git a/drivers/gpu/drm/i915/i915_gem_fence.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c index cd59dbc6588c..0efa3571afc3 100644 --- a/drivers/gpu/drm/i915/i915_gem_fence.c +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c @@ -368,15 +368,14 @@ i915_vma_get_fence(struct i915_vma *vma) /** * i915_gem_restore_fences - restore fence state - * @dev: DRM device + * @dev_priv: i915 device private * * Restore the hw fence state to match the software tracking again, to be called * after a gpu reset and on resume. Note that on runtime suspend we only cancel * the fences, to be reacquired by the user later. */ -void i915_gem_restore_fences(struct drm_device *dev) +void i915_gem_restore_fences(struct drm_i915_private *dev_priv) { - struct drm_i915_private *dev_priv = to_i915(dev); int i; for (i = 0; i < dev_priv->num_fence_regs; i++) { @@ -451,15 +450,14 @@ void i915_gem_restore_fences(struct drm_device *dev) /** * i915_gem_detect_bit_6_swizzle - detect bit 6 swizzling pattern - * @dev: DRM device + * @dev_priv: i915 device private * * Detects bit 6 swizzling of address lookup between IGD access and CPU * access through main memory. */ void -i915_gem_detect_bit_6_swizzle(struct drm_device *dev) +i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv) { - struct drm_i915_private *dev_priv = to_i915(dev); uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; @@ -473,7 +471,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) */ swizzle_x = I915_BIT_6_SWIZZLE_NONE; swizzle_y = I915_BIT_6_SWIZZLE_NONE; - } else if (INTEL_INFO(dev)->gen >= 6) { + } else if (INTEL_GEN(dev_priv) >= 6) { if (dev_priv->preserve_bios_swizzle) { if (I915_READ(DISP_ARB_CTL) & DISP_TILE_SURFACE_SWIZZLING) { diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.h b/drivers/gpu/drm/i915/i915_gem_fence_reg.h new file mode 100644 index 000000000000..22c4a2d01adf --- /dev/null +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.h @@ -0,0 +1,51 @@ +/* + * Copyright © 2016 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +#ifndef __I915_FENCE_REG_H__ +#define __I915_FENCE_REG_H__ + +#include <linux/list.h> + +struct drm_i915_private; +struct i915_vma; + +struct drm_i915_fence_reg { + struct list_head link; + struct drm_i915_private *i915; + struct i915_vma *vma; + int pin_count; + int id; + /** + * Whether the tiling parameters for the currently + * associated fence register have changed. Note that + * for the purposes of tracking tiling changes we also + * treat the unfenced register, the register slot that + * the object occupies whilst it executes a fenced + * command (such as BLT on gen2/3), as a "fence". + */ + bool dirty; +}; + +#endif + diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index a5fafa3d4fc8..b4bde1452f2a 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -96,13 +96,6 @@ * */ -static inline struct i915_ggtt * -i915_vm_to_ggtt(struct i915_address_space *vm) -{ - GEM_BUG_ON(!i915_is_ggtt(vm)); - return container_of(vm, struct i915_ggtt, base); -} - static int i915_get_ggtt_vma_pages(struct i915_vma *vma); @@ -327,10 +320,10 @@ static gen6_pte_t iris_pte_encode(dma_addr_t addr, return pte; } -static int __setup_page_dma(struct drm_device *dev, +static int __setup_page_dma(struct drm_i915_private *dev_priv, struct i915_page_dma *p, gfp_t flags) { - struct device *kdev = &dev->pdev->dev; + struct device *kdev = &dev_priv->drm.pdev->dev; p->page = alloc_page(flags); if (!p->page) @@ -347,14 +340,16 @@ static int __setup_page_dma(struct drm_device *dev, return 0; } -static int setup_page_dma(struct drm_device *dev, struct i915_page_dma *p) +static int setup_page_dma(struct drm_i915_private *dev_priv, + struct i915_page_dma *p) { - return __setup_page_dma(dev, p, I915_GFP_DMA); + return __setup_page_dma(dev_priv, p, I915_GFP_DMA); } -static void cleanup_page_dma(struct drm_device *dev, struct i915_page_dma *p) +static void cleanup_page_dma(struct drm_i915_private *dev_priv, + struct i915_page_dma *p) { - struct pci_dev *pdev = dev->pdev; + struct pci_dev *pdev = dev_priv->drm.pdev; if (WARN_ON(!p->page)) return; @@ -387,8 +382,8 @@ static void kunmap_page_dma(struct drm_i915_private *dev_priv, void *vaddr) #define kunmap_px(ppgtt, vaddr) \ kunmap_page_dma(to_i915((ppgtt)->base.dev), (vaddr)) -#define setup_px(dev, px) setup_page_dma((dev), px_base(px)) -#define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px)) +#define setup_px(dev_priv, px) setup_page_dma((dev_priv), px_base(px)) +#define cleanup_px(dev_priv, px) cleanup_page_dma((dev_priv), px_base(px)) #define fill_px(dev_priv, px, v) fill_page_dma((dev_priv), px_base(px), (v)) #define fill32_px(dev_priv, px, v) \ fill_page_dma_32((dev_priv), px_base(px), (v)) @@ -416,24 +411,23 @@ static void fill_page_dma_32(struct drm_i915_private *dev_priv, } static int -setup_scratch_page(struct drm_device *dev, +setup_scratch_page(struct drm_i915_private *dev_priv, struct i915_page_dma *scratch, gfp_t gfp) { - return __setup_page_dma(dev, scratch, gfp | __GFP_ZERO); + return __setup_page_dma(dev_priv, scratch, gfp | __GFP_ZERO); } -static void cleanup_scratch_page(struct drm_device *dev, +static void cleanup_scratch_page(struct drm_i915_private *dev_priv, struct i915_page_dma *scratch) { - cleanup_page_dma(dev, scratch); + cleanup_page_dma(dev_priv, scratch); } -static struct i915_page_table *alloc_pt(struct drm_device *dev) +static struct i915_page_table *alloc_pt(struct drm_i915_private *dev_priv) { struct i915_page_table *pt; - const size_t count = INTEL_INFO(dev)->gen >= 8 ? - GEN8_PTES : GEN6_PTES; + const size_t count = INTEL_GEN(dev_priv) >= 8 ? GEN8_PTES : GEN6_PTES; int ret = -ENOMEM; pt = kzalloc(sizeof(*pt), GFP_KERNEL); @@ -446,7 +440,7 @@ static struct i915_page_table *alloc_pt(struct drm_device *dev) if (!pt->used_ptes) goto fail_bitmap; - ret = setup_px(dev, pt); + ret = setup_px(dev_priv, pt); if (ret) goto fail_page_m; @@ -460,9 +454,10 @@ fail_bitmap: return ERR_PTR(ret); } -static void free_pt(struct drm_device *dev, struct i915_page_table *pt) +static void free_pt(struct drm_i915_private *dev_priv, + struct i915_page_table *pt) { - cleanup_px(dev, pt); + cleanup_px(dev_priv, pt); kfree(pt->used_ptes); kfree(pt); } @@ -491,7 +486,7 @@ static void gen6_initialize_pt(struct i915_address_space *vm, fill32_px(to_i915(vm->dev), pt, scratch_pte); } -static struct i915_page_directory *alloc_pd(struct drm_device *dev) +static struct i915_page_directory *alloc_pd(struct drm_i915_private *dev_priv) { struct i915_page_directory *pd; int ret = -ENOMEM; @@ -505,7 +500,7 @@ static struct i915_page_directory *alloc_pd(struct drm_device *dev) if (!pd->used_pdes) goto fail_bitmap; - ret = setup_px(dev, pd); + ret = setup_px(dev_priv, pd); if (ret) goto fail_page_m; @@ -519,10 +514,11 @@ fail_bitmap: return ERR_PTR(ret); } -static void free_pd(struct drm_device *dev, struct i915_page_directory *pd) +static void free_pd(struct drm_i915_private *dev_priv, + struct i915_page_directory *pd) { if (px_page(pd)) { - cleanup_px(dev, pd); + cleanup_px(dev_priv, pd); kfree(pd->used_pdes); kfree(pd); } @@ -538,10 +534,10 @@ static void gen8_initialize_pd(struct i915_address_space *vm, fill_px(to_i915(vm->dev), pd, scratch_pde); } -static int __pdp_init(struct drm_device *dev, +static int __pdp_init(struct drm_i915_private *dev_priv, struct i915_page_directory_pointer *pdp) { - size_t pdpes = I915_PDPES_PER_PDP(dev); + size_t pdpes = I915_PDPES_PER_PDP(dev_priv); pdp->used_pdpes = kcalloc(BITS_TO_LONGS(pdpes), sizeof(unsigned long), @@ -570,22 +566,22 @@ static void __pdp_fini(struct i915_page_directory_pointer *pdp) } static struct -i915_page_directory_pointer *alloc_pdp(struct drm_device *dev) +i915_page_directory_pointer *alloc_pdp(struct drm_i915_private *dev_priv) { struct i915_page_directory_pointer *pdp; int ret = -ENOMEM; - WARN_ON(!USES_FULL_48BIT_PPGTT(dev)); + WARN_ON(!USES_FULL_48BIT_PPGTT(dev_priv)); pdp = kzalloc(sizeof(*pdp), GFP_KERNEL); if (!pdp) return ERR_PTR(-ENOMEM); - ret = __pdp_init(dev, pdp); + ret = __pdp_init(dev_priv, pdp); if (ret) goto fail_bitmap; - ret = setup_px(dev, pdp); + ret = setup_px(dev_priv, pdp); if (ret) goto fail_page_m; @@ -599,12 +595,12 @@ fail_bitmap: return ERR_PTR(ret); } -static void free_pdp(struct drm_device *dev, +static void free_pdp(struct drm_i915_private *dev_priv, struct i915_page_directory_pointer *pdp) { __pdp_fini(pdp); - if (USES_FULL_48BIT_PPGTT(dev)) { - cleanup_px(dev, pdp); + if (USES_FULL_48BIT_PPGTT(dev_priv)) { + cleanup_px(dev_priv, pdp); kfree(pdp); } } @@ -638,7 +634,7 @@ gen8_setup_page_directory(struct i915_hw_ppgtt *ppgtt, { gen8_ppgtt_pdpe_t *page_directorypo; - if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) + if (!USES_FULL_48BIT_PPGTT(to_i915(ppgtt->base.dev))) return; page_directorypo = kmap_px(pdp); @@ -654,7 +650,7 @@ gen8_setup_page_directory_pointer(struct i915_hw_ppgtt *ppgtt, { gen8_ppgtt_pml4e_t *pagemap = kmap_px(pml4); - WARN_ON(!USES_FULL_48BIT_PPGTT(ppgtt->base.dev)); + WARN_ON(!USES_FULL_48BIT_PPGTT(to_i915(ppgtt->base.dev))); pagemap[index] = gen8_pml4e_encode(px_dma(pdp), I915_CACHE_LLC); kunmap_px(ppgtt, pagemap); } @@ -714,7 +710,7 @@ static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt, */ static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt) { - ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask; + ppgtt->pd_dirty_rings = INTEL_INFO(to_i915(ppgtt->base.dev))->ring_mask; } /* Removes entries from a single page table, releasing it if it's empty. @@ -741,7 +737,7 @@ static bool gen8_ppgtt_clear_pt(struct i915_address_space *vm, bitmap_clear(pt->used_ptes, pte, num_entries); if (bitmap_empty(pt->used_ptes, GEN8_PTES)) { - free_pt(vm->dev, pt); + free_pt(to_i915(vm->dev), pt); return true; } @@ -783,7 +779,7 @@ static bool gen8_ppgtt_clear_pd(struct i915_address_space *vm, } if (bitmap_empty(pd->used_pdes, I915_PDES)) { - free_pd(vm->dev, pd); + free_pd(to_i915(vm->dev), pd); return true; } @@ -799,6 +795,7 @@ static bool gen8_ppgtt_clear_pdp(struct i915_address_space *vm, uint64_t length) { struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); + struct drm_i915_private *dev_priv = to_i915(vm->dev); struct i915_page_directory *pd; uint64_t pdpe; gen8_ppgtt_pdpe_t *pdpe_vaddr; @@ -811,7 +808,7 @@ static bool gen8_ppgtt_clear_pdp(struct i915_address_space *vm, if (gen8_ppgtt_clear_pd(vm, pd, start, length)) { __clear_bit(pdpe, pdp->used_pdpes); - if (USES_FULL_48BIT_PPGTT(vm->dev)) { + if (USES_FULL_48BIT_PPGTT(dev_priv)) { pdpe_vaddr = kmap_px(pdp); pdpe_vaddr[pdpe] = scratch_pdpe; kunmap_px(ppgtt, pdpe_vaddr); @@ -821,9 +818,9 @@ static bool gen8_ppgtt_clear_pdp(struct i915_address_space *vm, mark_tlbs_dirty(ppgtt); - if (USES_FULL_48BIT_PPGTT(vm->dev) && - bitmap_empty(pdp->used_pdpes, I915_PDPES_PER_PDP(vm->dev))) { - free_pdp(vm->dev, pdp); + if (USES_FULL_48BIT_PPGTT(dev_priv) && + bitmap_empty(pdp->used_pdpes, I915_PDPES_PER_PDP(dev_priv))) { + free_pdp(dev_priv, pdp); return true; } @@ -846,7 +843,7 @@ static void gen8_ppgtt_clear_pml4(struct i915_address_space *vm, gen8_ppgtt_pml4e_t scratch_pml4e = gen8_pml4e_encode(px_dma(vm->scratch_pdp), I915_CACHE_LLC); - GEM_BUG_ON(!USES_FULL_48BIT_PPGTT(vm->dev)); + GEM_BUG_ON(!USES_FULL_48BIT_PPGTT(to_i915(vm->dev))); gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { if (WARN_ON(!pml4->pdps[pml4e])) @@ -866,7 +863,7 @@ static void gen8_ppgtt_clear_range(struct i915_address_space *vm, { struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); - if (USES_FULL_48BIT_PPGTT(vm->dev)) + if (USES_FULL_48BIT_PPGTT(to_i915(vm->dev))) gen8_ppgtt_clear_pml4(vm, &ppgtt->pml4, start, length); else gen8_ppgtt_clear_pdp(vm, &ppgtt->pdp, start, length); @@ -901,7 +898,7 @@ gen8_ppgtt_insert_pte_entries(struct i915_address_space *vm, kunmap_px(ppgtt, pt_vaddr); pt_vaddr = NULL; if (++pde == I915_PDES) { - if (++pdpe == I915_PDPES_PER_PDP(vm->dev)) + if (++pdpe == I915_PDPES_PER_PDP(to_i915(vm->dev))) break; pde = 0; } @@ -924,7 +921,7 @@ static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, __sg_page_iter_start(&sg_iter, pages->sgl, sg_nents(pages->sgl), 0); - if (!USES_FULL_48BIT_PPGTT(vm->dev)) { + if (!USES_FULL_48BIT_PPGTT(to_i915(vm->dev))) { gen8_ppgtt_insert_pte_entries(vm, &ppgtt->pdp, &sg_iter, start, cache_level); } else { @@ -939,7 +936,7 @@ static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, } } -static void gen8_free_page_tables(struct drm_device *dev, +static void gen8_free_page_tables(struct drm_i915_private *dev_priv, struct i915_page_directory *pd) { int i; @@ -951,34 +948,34 @@ static void gen8_free_page_tables(struct drm_device *dev, if (WARN_ON(!pd->page_table[i])) continue; - free_pt(dev, pd->page_table[i]); + free_pt(dev_priv, pd->page_table[i]); pd->page_table[i] = NULL; } } static int gen8_init_scratch(struct i915_address_space *vm) { - struct drm_device *dev = vm->dev; + struct drm_i915_private *dev_priv = to_i915(vm->dev); int ret; - ret = setup_scratch_page(dev, &vm->scratch_page, I915_GFP_DMA); + ret = setup_scratch_page(dev_priv, &vm->scratch_page, I915_GFP_DMA); if (ret) return ret; - vm->scratch_pt = alloc_pt(dev); + vm->scratch_pt = alloc_pt(dev_priv); if (IS_ERR(vm->scratch_pt)) { ret = PTR_ERR(vm->scratch_pt); goto free_scratch_page; } - vm->scratch_pd = alloc_pd(dev); + vm->scratch_pd = alloc_pd(dev_priv); if (IS_ERR(vm->scratch_pd)) { ret = PTR_ERR(vm->scratch_pd); goto free_pt; } - if (USES_FULL_48BIT_PPGTT(dev)) { - vm->scratch_pdp = alloc_pdp(dev); + if (USES_FULL_48BIT_PPGTT(dev_priv)) { + vm->scratch_pdp = alloc_pdp(dev_priv); if (IS_ERR(vm->scratch_pdp)) { ret = PTR_ERR(vm->scratch_pdp); goto free_pd; @@ -987,17 +984,17 @@ static int gen8_init_scratch(struct i915_address_space *vm) gen8_initialize_pt(vm, vm->scratch_pt); gen8_initialize_pd(vm, vm->scratch_pd); - if (USES_FULL_48BIT_PPGTT(dev)) + if (USES_FULL_48BIT_PPGTT(dev_priv)) gen8_initialize_pdp(vm, vm->scratch_pdp); return 0; free_pd: - free_pd(dev, vm->scratch_pd); + free_pd(dev_priv, vm->scratch_pd); free_pt: - free_pt(dev, vm->scratch_pt); + free_pt(dev_priv, vm->scratch_pt); free_scratch_page: - cleanup_scratch_page(dev, &vm->scratch_page); + cleanup_scratch_page(dev_priv, &vm->scratch_page); return ret; } @@ -1035,54 +1032,56 @@ static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool create) static void gen8_free_scratch(struct i915_address_space *vm) { - struct drm_device *dev = vm->dev; + struct drm_i915_private *dev_priv = to_i915(vm->dev); - if (USES_FULL_48BIT_PPGTT(dev)) - free_pdp(dev, vm->scratch_pdp); - free_pd(dev, vm->scratch_pd); - free_pt(dev, vm->scratch_pt); - cleanup_scratch_page(dev, &vm->scratch_page); + if (USES_FULL_48BIT_PPGTT(dev_priv)) + free_pdp(dev_priv, vm->scratch_pdp); + free_pd(dev_priv, vm->scratch_pd); + free_pt(dev_priv, vm->scratch_pt); + cleanup_scratch_page(dev_priv, &vm->scratch_page); } -static void gen8_ppgtt_cleanup_3lvl(struct drm_device *dev, +static void gen8_ppgtt_cleanup_3lvl(struct drm_i915_private *dev_priv, struct i915_page_directory_pointer *pdp) { int i; - for_each_set_bit(i, pdp->used_pdpes, I915_PDPES_PER_PDP(dev)) { + for_each_set_bit(i, pdp->used_pdpes, I915_PDPES_PER_PDP(dev_priv)) { if (WARN_ON(!pdp->page_directory[i])) continue; - gen8_free_page_tables(dev, pdp->page_directory[i]); - free_pd(dev, pdp->page_directory[i]); + gen8_free_page_tables(dev_priv, pdp->page_directory[i]); + free_pd(dev_priv, pdp->page_directory[i]); } - free_pdp(dev, pdp); + free_pdp(dev_priv, pdp); } static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt *ppgtt) { + struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev); int i; for_each_set_bit(i, ppgtt->pml4.used_pml4es, GEN8_PML4ES_PER_PML4) { if (WARN_ON(!ppgtt->pml4.pdps[i])) continue; - gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, ppgtt->pml4.pdps[i]); + gen8_ppgtt_cleanup_3lvl(dev_priv, ppgtt->pml4.pdps[i]); } - cleanup_px(ppgtt->base.dev, &ppgtt->pml4); + cleanup_px(dev_priv, &ppgtt->pml4); } static void gen8_ppgtt_cleanup(struct i915_address_space *vm) { + struct drm_i915_private *dev_priv = to_i915(vm->dev); struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); - if (intel_vgpu_active(to_i915(vm->dev))) + if (intel_vgpu_active(dev_priv)) gen8_ppgtt_notify_vgt(ppgtt, false); - if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) - gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, &ppgtt->pdp); + if (!USES_FULL_48BIT_PPGTT(dev_priv)) + gen8_ppgtt_cleanup_3lvl(dev_priv, &ppgtt->pdp); else gen8_ppgtt_cleanup_4lvl(ppgtt); @@ -1113,7 +1112,7 @@ static int gen8_ppgtt_alloc_pagetabs(struct i915_address_space *vm, uint64_t length, unsigned long *new_pts) { - struct drm_device *dev = vm->dev; + struct drm_i915_private *dev_priv = to_i915(vm->dev); struct i915_page_table *pt; uint32_t pde; @@ -1125,7 +1124,7 @@ static int gen8_ppgtt_alloc_pagetabs(struct i915_address_space *vm, continue; } - pt = alloc_pt(dev); + pt = alloc_pt(dev_priv); if (IS_ERR(pt)) goto unwind_out; @@ -1139,7 +1138,7 @@ static int gen8_ppgtt_alloc_pagetabs(struct i915_address_space *vm, unwind_out: for_each_set_bit(pde, new_pts, I915_PDES) - free_pt(dev, pd->page_table[pde]); + free_pt(dev_priv, pd->page_table[pde]); return -ENOMEM; } @@ -1174,10 +1173,10 @@ gen8_ppgtt_alloc_page_directories(struct i915_address_space *vm, uint64_t length, unsigned long *new_pds) { - struct drm_device *dev = vm->dev; + struct drm_i915_private *dev_priv = to_i915(vm->dev); struct i915_page_directory *pd; uint32_t pdpe; - uint32_t pdpes = I915_PDPES_PER_PDP(dev); + uint32_t pdpes = I915_PDPES_PER_PDP(dev_priv); WARN_ON(!bitmap_empty(new_pds, pdpes)); @@ -1185,7 +1184,7 @@ gen8_ppgtt_alloc_page_directories(struct i915_address_space *vm, if (test_bit(pdpe, pdp->used_pdpes)) continue; - pd = alloc_pd(dev); + pd = alloc_pd(dev_priv); if (IS_ERR(pd)) goto unwind_out; @@ -1199,7 +1198,7 @@ gen8_ppgtt_alloc_page_directories(struct i915_address_space *vm, unwind_out: for_each_set_bit(pdpe, new_pds, pdpes) - free_pd(dev, pdp->page_directory[pdpe]); + free_pd(dev_priv, pdp->page_directory[pdpe]); return -ENOMEM; } @@ -1227,7 +1226,7 @@ gen8_ppgtt_alloc_page_dirpointers(struct i915_address_space *vm, uint64_t length, unsigned long *new_pdps) { - struct drm_device *dev = vm->dev; + struct drm_i915_private *dev_priv = to_i915(vm->dev); struct i915_page_directory_pointer *pdp; uint32_t pml4e; @@ -1235,7 +1234,7 @@ gen8_ppgtt_alloc_page_dirpointers(struct i915_address_space *vm, gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { if (!test_bit(pml4e, pml4->used_pml4es)) { - pdp = alloc_pdp(dev); + pdp = alloc_pdp(dev_priv); if (IS_ERR(pdp)) goto unwind_out; @@ -1253,7 +1252,7 @@ gen8_ppgtt_alloc_page_dirpointers(struct i915_address_space *vm, unwind_out: for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4) - free_pdp(dev, pml4->pdps[pml4e]); + free_pdp(dev_priv, pml4->pdps[pml4e]); return -ENOMEM; } @@ -1302,12 +1301,12 @@ static int gen8_alloc_va_range_3lvl(struct i915_address_space *vm, { struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); unsigned long *new_page_dirs, *new_page_tables; - struct drm_device *dev = vm->dev; + struct drm_i915_private *dev_priv = to_i915(vm->dev); struct i915_page_directory *pd; const uint64_t orig_start = start; const uint64_t orig_length = length; uint32_t pdpe; - uint32_t pdpes = I915_PDPES_PER_PDP(dev); + uint32_t pdpes = I915_PDPES_PER_PDP(dev_priv); int ret; /* Wrap is never okay since we can only represent 48b, and we don't @@ -1395,11 +1394,12 @@ err_out: for_each_set_bit(temp, new_page_tables + pdpe * BITS_TO_LONGS(I915_PDES), I915_PDES) - free_pt(dev, pdp->page_directory[pdpe]->page_table[temp]); + free_pt(dev_priv, + pdp->page_directory[pdpe]->page_table[temp]); } for_each_set_bit(pdpe, new_page_dirs, pdpes) - free_pd(dev, pdp->page_directory[pdpe]); + free_pd(dev_priv, pdp->page_directory[pdpe]); free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); mark_tlbs_dirty(ppgtt); @@ -1450,7 +1450,7 @@ static int gen8_alloc_va_range_4lvl(struct i915_address_space *vm, err_out: for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4) - gen8_ppgtt_cleanup_3lvl(vm->dev, pml4->pdps[pml4e]); + gen8_ppgtt_cleanup_3lvl(to_i915(vm->dev), pml4->pdps[pml4e]); return ret; } @@ -1460,7 +1460,7 @@ static int gen8_alloc_va_range(struct i915_address_space *vm, { struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); - if (USES_FULL_48BIT_PPGTT(vm->dev)) + if (USES_FULL_48BIT_PPGTT(to_i915(vm->dev))) return gen8_alloc_va_range_4lvl(vm, &ppgtt->pml4, start, length); else return gen8_alloc_va_range_3lvl(vm, &ppgtt->pdp, start, length); @@ -1531,7 +1531,7 @@ static void gen8_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) gen8_pte_t scratch_pte = gen8_pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC); - if (!USES_FULL_48BIT_PPGTT(vm->dev)) { + if (!USES_FULL_48BIT_PPGTT(to_i915(vm->dev))) { gen8_dump_pdp(&ppgtt->pdp, start, length, scratch_pte, m); } else { uint64_t pml4e; @@ -1551,7 +1551,7 @@ static void gen8_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) static int gen8_preallocate_top_level_pdps(struct i915_hw_ppgtt *ppgtt) { unsigned long *new_page_dirs, *new_page_tables; - uint32_t pdpes = I915_PDPES_PER_PDP(dev); + uint32_t pdpes = I915_PDPES_PER_PDP(to_i915(ppgtt->base.dev)); int ret; /* We allocate temp bitmap for page tables for no gain @@ -1584,6 +1584,7 @@ static int gen8_preallocate_top_level_pdps(struct i915_hw_ppgtt *ppgtt) */ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt) { + struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev); int ret; ret = gen8_init_scratch(&ppgtt->base); @@ -1599,8 +1600,8 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt) ppgtt->base.bind_vma = ppgtt_bind_vma; ppgtt->debug_dump = gen8_dump_ppgtt; - if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) { - ret = setup_px(ppgtt->base.dev, &ppgtt->pml4); + if (USES_FULL_48BIT_PPGTT(dev_priv)) { + ret = setup_px(dev_priv, &ppgtt->pml4); if (ret) goto free_scratch; @@ -1609,7 +1610,7 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt) ppgtt->base.total = 1ULL << 48; ppgtt->switch_mm = gen8_48b_mm_switch; } else { - ret = __pdp_init(ppgtt->base.dev, &ppgtt->pdp); + ret = __pdp_init(dev_priv, &ppgtt->pdp); if (ret) goto free_scratch; @@ -1619,14 +1620,14 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt) 0, 0, GEN8_PML4E_SHIFT); - if (intel_vgpu_active(to_i915(ppgtt->base.dev))) { + if (intel_vgpu_active(dev_priv)) { ret = gen8_preallocate_top_level_pdps(ppgtt); if (ret) goto free_scratch; } } - if (intel_vgpu_active(to_i915(ppgtt->base.dev))) + if (intel_vgpu_active(dev_priv)) gen8_ppgtt_notify_vgt(ppgtt, true); return 0; @@ -1801,22 +1802,21 @@ static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt, return 0; } -static void gen8_ppgtt_enable(struct drm_device *dev) +static void gen8_ppgtt_enable(struct drm_i915_private *dev_priv) { - struct drm_i915_private *dev_priv = to_i915(dev); struct intel_engine_cs *engine; enum intel_engine_id id; for_each_engine(engine, dev_priv, id) { - u32 four_level = USES_FULL_48BIT_PPGTT(dev) ? GEN8_GFX_PPGTT_48B : 0; + u32 four_level = USES_FULL_48BIT_PPGTT(dev_priv) ? + GEN8_GFX_PPGTT_48B : 0; I915_WRITE(RING_MODE_GEN7(engine), _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level)); } } -static void gen7_ppgtt_enable(struct drm_device *dev) +static void gen7_ppgtt_enable(struct drm_i915_private *dev_priv) { - struct drm_i915_private *dev_priv = to_i915(dev); struct intel_engine_cs *engine; uint32_t ecochk, ecobits; enum intel_engine_id id; @@ -1840,9 +1840,8 @@ static void gen7_ppgtt_enable(struct drm_device *dev) } } -static void gen6_ppgtt_enable(struct drm_device *dev) +static void gen6_ppgtt_enable(struct drm_i915_private *dev_priv) { - struct drm_i915_private *dev_priv = to_i915(dev); uint32_t ecochk, gab_ctl, ecobits; ecobits = I915_READ(GAC_ECO_BITS); @@ -1928,8 +1927,7 @@ static int gen6_alloc_va_range(struct i915_address_space *vm, uint64_t start_in, uint64_t length_in) { DECLARE_BITMAP(new_page_tables, I915_PDES); - struct drm_device *dev = vm->dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(vm->dev); struct i915_ggtt *ggtt = &dev_priv->ggtt; struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); struct i915_page_table *pt; @@ -1959,7 +1957,7 @@ static int gen6_alloc_va_range(struct i915_address_space *vm, /* We've already allocated a page table */ WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES)); - pt = alloc_pt(dev); + pt = alloc_pt(dev_priv); if (IS_ERR(pt)) { ret = PTR_ERR(pt); goto unwind_out; @@ -2007,7 +2005,7 @@ unwind_out: struct i915_page_table *pt = ppgtt->pd.page_table[pde]; ppgtt->pd.page_table[pde] = vm->scratch_pt; - free_pt(vm->dev, pt); + free_pt(dev_priv, pt); } mark_tlbs_dirty(ppgtt); @@ -2016,16 +2014,16 @@ unwind_out: static int gen6_init_scratch(struct i915_address_space *vm) { - struct drm_device *dev = vm->dev; + struct drm_i915_private *dev_priv = to_i915(vm->dev); int ret; - ret = setup_scratch_page(dev, &vm->scratch_page, I915_GFP_DMA); + ret = setup_scratch_page(dev_priv, &vm->scratch_page, I915_GFP_DMA); if (ret) return ret; - vm->scratch_pt = alloc_pt(dev); + vm->scratch_pt = alloc_pt(dev_priv); if (IS_ERR(vm->scratch_pt)) { - cleanup_scratch_page(dev, &vm->scratch_page); + cleanup_scratch_page(dev_priv, &vm->scratch_page); return PTR_ERR(vm->scratch_pt); } @@ -2036,17 +2034,17 @@ static int gen6_init_scratch(struct i915_address_space *vm) static void gen6_free_scratch(struct i915_address_space *vm) { - struct drm_device *dev = vm->dev; + struct drm_i915_private *dev_priv = to_i915(vm->dev); - free_pt(dev, vm->scratch_pt); - cleanup_scratch_page(dev, &vm->scratch_page); + free_pt(dev_priv, vm->scratch_pt); + cleanup_scratch_page(dev_priv, &vm->scratch_page); } static void gen6_ppgtt_cleanup(struct i915_address_space *vm) { struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); struct i915_page_directory *pd = &ppgtt->pd; - struct drm_device *dev = vm->dev; + struct drm_i915_private *dev_priv = to_i915(vm->dev); struct i915_page_table *pt; uint32_t pde; @@ -2054,7 +2052,7 @@ static void gen6_ppgtt_cleanup(struct i915_address_space *vm) gen6_for_all_pdes(pt, pd, pde) if (pt != vm->scratch_pt) - free_pt(dev, pt); + free_pt(dev_priv, pt); gen6_free_scratch(vm); } @@ -2062,8 +2060,7 @@ static void gen6_ppgtt_cleanup(struct i915_address_space *vm) static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt) { struct i915_address_space *vm = &ppgtt->base; - struct drm_device *dev = ppgtt->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev); struct i915_ggtt *ggtt = &dev_priv->ggtt; bool retried = false; int ret; @@ -2128,8 +2125,7 @@ static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt, static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) { - struct drm_device *dev = ppgtt->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev); struct i915_ggtt *ggtt = &dev_priv->ggtt; int ret; @@ -2200,10 +2196,15 @@ static void i915_address_space_init(struct i915_address_space *vm, list_add_tail(&vm->global_link, &dev_priv->vm_list); } -static void gtt_write_workarounds(struct drm_device *dev) +static void i915_address_space_fini(struct i915_address_space *vm) { - struct drm_i915_private *dev_priv = to_i915(dev); + i915_gem_timeline_fini(&vm->timeline); + drm_mm_takedown(&vm->mm); + list_del(&vm->global_link); +} +static void gtt_write_workarounds(struct drm_i915_private *dev_priv) +{ /* This function is for gtt related workarounds. This function is * called on driver load and after a GPU reset, so you can place * workarounds here even if they get overwritten by GPU reset. @@ -2236,11 +2237,9 @@ static int i915_ppgtt_init(struct i915_hw_ppgtt *ppgtt, return ret; } -int i915_ppgtt_init_hw(struct drm_device *dev) +int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv) { - struct drm_i915_private *dev_priv = to_i915(dev); - - gtt_write_workarounds(dev); + gtt_write_workarounds(dev_priv); /* In the case of execlists, PPGTT is enabled by the context descriptor * and the PDPs are contained within the context itself. We don't @@ -2248,17 +2247,17 @@ int i915_ppgtt_init_hw(struct drm_device *dev) if (i915.enable_execlists) return 0; - if (!USES_PPGTT(dev)) + if (!USES_PPGTT(dev_priv)) return 0; if (IS_GEN6(dev_priv)) - gen6_ppgtt_enable(dev); + gen6_ppgtt_enable(dev_priv); else if (IS_GEN7(dev_priv)) - gen7_ppgtt_enable(dev); - else if (INTEL_INFO(dev)->gen >= 8) - gen8_ppgtt_enable(dev); + gen7_ppgtt_enable(dev_priv); + else if (INTEL_GEN(dev_priv) >= 8) + gen8_ppgtt_enable(dev_priv); else - MISSING_CASE(INTEL_INFO(dev)->gen); + MISSING_CASE(INTEL_GEN(dev_priv)); return 0; } @@ -2286,7 +2285,7 @@ i915_ppgtt_create(struct drm_i915_private *dev_priv, return ppgtt; } -void i915_ppgtt_release(struct kref *kref) +void i915_ppgtt_release(struct kref *kref) { struct i915_hw_ppgtt *ppgtt = container_of(kref, struct i915_hw_ppgtt, ref); @@ -2298,9 +2297,7 @@ void i915_ppgtt_release(struct kref *kref) WARN_ON(!list_empty(&ppgtt->base.inactive_list)); WARN_ON(!list_empty(&ppgtt->base.unbound_list)); - i915_gem_timeline_fini(&ppgtt->base.timeline); - list_del(&ppgtt->base.global_link); - drm_mm_takedown(&ppgtt->base.mm); + i915_address_space_fini(&ppgtt->base); ppgtt->base.cleanup(&ppgtt->base); kfree(ppgtt); @@ -2362,15 +2359,14 @@ static void i915_ggtt_flush(struct drm_i915_private *dev_priv) } } -void i915_gem_suspend_gtt_mappings(struct drm_device *dev) +void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv) { - struct drm_i915_private *dev_priv = to_i915(dev); struct i915_ggtt *ggtt = &dev_priv->ggtt; /* Don't bother messing with faults pre GEN6 as we have little * documentation supporting that it's a good idea. */ - if (INTEL_INFO(dev)->gen < 6) + if (INTEL_GEN(dev_priv) < 6) return; i915_check_and_clear_faults(dev_priv); @@ -2842,8 +2838,9 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv) if (drm_mm_initialized(&ggtt->base.mm)) { intel_vgt_deballoon(dev_priv); - drm_mm_takedown(&ggtt->base.mm); - list_del(&ggtt->base.global_link); + mutex_lock(&dev_priv->drm.struct_mutex); + i915_address_space_fini(&ggtt->base); + mutex_unlock(&dev_priv->drm.struct_mutex); } ggtt->base.cleanup(&ggtt->base); @@ -2932,6 +2929,7 @@ static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl) static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) { + struct drm_i915_private *dev_priv = to_i915(ggtt->base.dev); struct pci_dev *pdev = ggtt->base.dev->pdev; phys_addr_t phys_addr; int ret; @@ -2946,7 +2944,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) * resort to an uncached mapping. The WC issue is easily caught by the * readback check when writing GTT PTE entries. */ - if (IS_BROXTON(to_i915(ggtt->base.dev))) + if (IS_BROXTON(dev_priv)) ggtt->gsm = ioremap_nocache(phys_addr, size); else ggtt->gsm = ioremap_wc(phys_addr, size); @@ -2955,9 +2953,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) return -ENOMEM; } - ret = setup_scratch_page(ggtt->base.dev, - &ggtt->base.scratch_page, - GFP_DMA32); + ret = setup_scratch_page(dev_priv, &ggtt->base.scratch_page, GFP_DMA32); if (ret) { DRM_ERROR("Scratch setup failed\n"); /* iounmap will also get called at remove, but meh */ @@ -3046,7 +3042,7 @@ static void gen6_gmch_remove(struct i915_address_space *vm) struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); iounmap(ggtt->gsm); - cleanup_scratch_page(vm->dev, &vm->scratch_page); + cleanup_scratch_page(to_i915(vm->dev), &vm->scratch_page); } static int gen8_gmch_probe(struct i915_ggtt *ggtt) @@ -3262,7 +3258,7 @@ int i915_ggtt_init_hw(struct drm_i915_private *dev_priv) * Initialise stolen early so that we may reserve preallocated * objects for the BIOS to KMS transition. */ - ret = i915_gem_init_stolen(&dev_priv->drm); + ret = i915_gem_init_stolen(dev_priv); if (ret) goto out_gtt_cleanup; @@ -3281,9 +3277,8 @@ int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv) return 0; } -void i915_gem_restore_gtt_mappings(struct drm_device *dev) +void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv) { - struct drm_i915_private *dev_priv = to_i915(dev); struct i915_ggtt *ggtt = &dev_priv->ggtt; struct drm_i915_gem_object *obj, *on; @@ -3318,7 +3313,7 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev) ggtt->base.closed = false; - if (INTEL_INFO(dev)->gen >= 8) { + if (INTEL_GEN(dev_priv) >= 8) { if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv)) chv_setup_private_ppat(dev_priv); else @@ -3327,7 +3322,7 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev) return; } - if (USES_PPGTT(dev)) { + if (USES_PPGTT(dev_priv)) { struct i915_address_space *vm; list_for_each_entry(vm, &dev_priv->vm_list, global_link) { @@ -3348,176 +3343,6 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev) i915_ggtt_flush(dev_priv); } -static void -i915_vma_retire(struct i915_gem_active *active, - struct drm_i915_gem_request *rq) -{ - const unsigned int idx = rq->engine->id; - struct i915_vma *vma = - container_of(active, struct i915_vma, last_read[idx]); - struct drm_i915_gem_object *obj = vma->obj; - - GEM_BUG_ON(!i915_vma_has_active_engine(vma, idx)); - - i915_vma_clear_active(vma, idx); - if (i915_vma_is_active(vma)) - return; - - list_move_tail(&vma->vm_link, &vma->vm->inactive_list); - if (unlikely(i915_vma_is_closed(vma) && !i915_vma_is_pinned(vma))) - WARN_ON(i915_vma_unbind(vma)); - - GEM_BUG_ON(!i915_gem_object_is_active(obj)); - if (--obj->active_count) - return; - - /* Bump our place on the bound list to keep it roughly in LRU order - * so that we don't steal from recently used but inactive objects - * (unless we are forced to ofc!) - */ - if (obj->bind_count) - list_move_tail(&obj->global_link, &rq->i915->mm.bound_list); - - obj->mm.dirty = true; /* be paranoid */ - - if (i915_gem_object_has_active_reference(obj)) { - i915_gem_object_clear_active_reference(obj); - i915_gem_object_put(obj); - } -} - -static void -i915_ggtt_retire__write(struct i915_gem_active *active, - struct drm_i915_gem_request *request) -{ - struct i915_vma *vma = - container_of(active, struct i915_vma, last_write); - - intel_fb_obj_flush(vma->obj, true, ORIGIN_CS); -} - -void i915_vma_destroy(struct i915_vma *vma) -{ - GEM_BUG_ON(vma->node.allocated); - GEM_BUG_ON(i915_vma_is_active(vma)); - GEM_BUG_ON(!i915_vma_is_closed(vma)); - GEM_BUG_ON(vma->fence); - - list_del(&vma->vm_link); - if (!i915_vma_is_ggtt(vma)) - i915_ppgtt_put(i915_vm_to_ppgtt(vma->vm)); - - kmem_cache_free(to_i915(vma->obj->base.dev)->vmas, vma); -} - -void i915_vma_close(struct i915_vma *vma) -{ - GEM_BUG_ON(i915_vma_is_closed(vma)); - vma->flags |= I915_VMA_CLOSED; - - list_del(&vma->obj_link); - rb_erase(&vma->obj_node, &vma->obj->vma_tree); - - if (!i915_vma_is_active(vma) && !i915_vma_is_pinned(vma)) - WARN_ON(i915_vma_unbind(vma)); -} - -static inline long vma_compare(struct i915_vma *vma, - struct i915_address_space *vm, - const struct i915_ggtt_view *view) -{ - GEM_BUG_ON(view && !i915_is_ggtt(vm)); - - if (vma->vm != vm) - return vma->vm - vm; - - if (!view) - return vma->ggtt_view.type; - - if (vma->ggtt_view.type != view->type) - return vma->ggtt_view.type - view->type; - - return memcmp(&vma->ggtt_view.params, - &view->params, - sizeof(view->params)); -} - -static struct i915_vma * -__i915_vma_create(struct drm_i915_gem_object *obj, - struct i915_address_space *vm, - const struct i915_ggtt_view *view) -{ - struct i915_vma *vma; - struct rb_node *rb, **p; - int i; - - GEM_BUG_ON(vm->closed); - - vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL); - if (vma == NULL) - return ERR_PTR(-ENOMEM); - - INIT_LIST_HEAD(&vma->exec_list); - for (i = 0; i < ARRAY_SIZE(vma->last_read); i++) - init_request_active(&vma->last_read[i], i915_vma_retire); - init_request_active(&vma->last_write, - i915_is_ggtt(vm) ? i915_ggtt_retire__write : NULL); - init_request_active(&vma->last_fence, NULL); - list_add(&vma->vm_link, &vm->unbound_list); - vma->vm = vm; - vma->obj = obj; - vma->size = obj->base.size; - - if (view) { - vma->ggtt_view = *view; - if (view->type == I915_GGTT_VIEW_PARTIAL) { - vma->size = view->params.partial.size; - vma->size <<= PAGE_SHIFT; - } else if (view->type == I915_GGTT_VIEW_ROTATED) { - vma->size = - intel_rotation_info_size(&view->params.rotated); - vma->size <<= PAGE_SHIFT; - } - } - - if (i915_is_ggtt(vm)) { - vma->flags |= I915_VMA_GGTT; - list_add(&vma->obj_link, &obj->vma_list); - } else { - i915_ppgtt_get(i915_vm_to_ppgtt(vm)); - list_add_tail(&vma->obj_link, &obj->vma_list); - } - - rb = NULL; - p = &obj->vma_tree.rb_node; - while (*p) { - struct i915_vma *pos; - - rb = *p; - pos = rb_entry(rb, struct i915_vma, obj_node); - if (vma_compare(pos, vm, view) < 0) - p = &rb->rb_right; - else - p = &rb->rb_left; - } - rb_link_node(&vma->obj_node, rb, p); - rb_insert_color(&vma->obj_node, &obj->vma_tree); - - return vma; -} - -struct i915_vma * -i915_vma_create(struct drm_i915_gem_object *obj, - struct i915_address_space *vm, - const struct i915_ggtt_view *view) -{ - lockdep_assert_held(&obj->base.dev->struct_mutex); - GEM_BUG_ON(view && !i915_is_ggtt(vm)); - GEM_BUG_ON(i915_gem_obj_to_vma(obj, vm, view)); - - return __i915_vma_create(obj, vm, view); -} - struct i915_vma * i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, struct i915_address_space *vm, @@ -3530,7 +3355,7 @@ i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, struct i915_vma *vma = rb_entry(rb, struct i915_vma, obj_node); long cmp; - cmp = vma_compare(vma, vm, view); + cmp = i915_vma_compare(vma, vm, view); if (cmp == 0) return vma; @@ -3555,7 +3380,7 @@ i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, vma = i915_gem_obj_to_vma(obj, vm, view); if (!vma) { - vma = __i915_vma_create(obj, vm, view); + vma = i915_vma_create(obj, vm, view); GEM_BUG_ON(vma != i915_gem_obj_to_vma(obj, vm, view)); } @@ -3747,99 +3572,3 @@ i915_get_ggtt_vma_pages(struct i915_vma *vma) return ret; } -/** - * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space. - * @vma: VMA to map - * @cache_level: mapping cache level - * @flags: flags like global or local mapping - * - * DMA addresses are taken from the scatter-gather table of this object (or of - * this VMA in case of non-default GGTT views) and PTE entries set up. - * Note that DMA addresses are also the only part of the SG table we care about. - */ -int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, - u32 flags) -{ - u32 bind_flags; - u32 vma_flags; - int ret; - - if (WARN_ON(flags == 0)) - return -EINVAL; - - bind_flags = 0; - if (flags & PIN_GLOBAL) - bind_flags |= I915_VMA_GLOBAL_BIND; - if (flags & PIN_USER) - bind_flags |= I915_VMA_LOCAL_BIND; - - vma_flags = vma->flags & (I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND); - if (flags & PIN_UPDATE) - bind_flags |= vma_flags; - else - bind_flags &= ~vma_flags; - if (bind_flags == 0) - return 0; - - if (vma_flags == 0 && vma->vm->allocate_va_range) { - trace_i915_va_alloc(vma); - ret = vma->vm->allocate_va_range(vma->vm, - vma->node.start, - vma->node.size); - if (ret) - return ret; - } - - ret = vma->vm->bind_vma(vma, cache_level, bind_flags); - if (ret) - return ret; - - vma->flags |= bind_flags; - return 0; -} - -void __iomem *i915_vma_pin_iomap(struct i915_vma *vma) -{ - void __iomem *ptr; - - /* Access through the GTT requires the device to be awake. */ - assert_rpm_wakelock_held(to_i915(vma->vm->dev)); - - lockdep_assert_held(&vma->vm->dev->struct_mutex); - if (WARN_ON(!i915_vma_is_map_and_fenceable(vma))) - return IO_ERR_PTR(-ENODEV); - - GEM_BUG_ON(!i915_vma_is_ggtt(vma)); - GEM_BUG_ON((vma->flags & I915_VMA_GLOBAL_BIND) == 0); - - ptr = vma->iomap; - if (ptr == NULL) { - ptr = io_mapping_map_wc(&i915_vm_to_ggtt(vma->vm)->mappable, - vma->node.start, - vma->node.size); - if (ptr == NULL) - return IO_ERR_PTR(-ENOMEM); - - vma->iomap = ptr; - } - - __i915_vma_pin(vma); - return ptr; -} - -void i915_vma_unpin_and_release(struct i915_vma **p_vma) -{ - struct i915_vma *vma; - struct drm_i915_gem_object *obj; - - vma = fetch_and_zero(p_vma); - if (!vma) - return; - - obj = vma->obj; - - i915_vma_unpin(vma); - i915_vma_close(vma); - - __i915_gem_object_release_unless_active(obj); -} diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h index c23ef9db1f53..4f35be4c26c7 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.h +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h @@ -35,7 +35,9 @@ #define __I915_GEM_GTT_H__ #include <linux/io-mapping.h> +#include <linux/mm.h> +#include "i915_gem_timeline.h" #include "i915_gem_request.h" #define I915_FENCE_REG_NONE -1 @@ -118,8 +120,8 @@ typedef uint64_t gen8_ppgtt_pml4e_t; #define GEN8_LEGACY_PDPES 4 #define GEN8_PTES I915_PTES(sizeof(gen8_pte_t)) -#define I915_PDPES_PER_PDP(dev) (USES_FULL_48BIT_PPGTT(dev) ?\ - GEN8_PML4ES_PER_PML4 : GEN8_LEGACY_PDPES) +#define I915_PDPES_PER_PDP(dev_priv) (USES_FULL_48BIT_PPGTT(dev_priv) ?\ + GEN8_PML4ES_PER_PML4 : GEN8_LEGACY_PDPES) #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD) #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */ @@ -138,6 +140,8 @@ typedef uint64_t gen8_ppgtt_pml4e_t; #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8)) +struct sg_table; + enum i915_ggtt_view_type { I915_GGTT_VIEW_NORMAL = 0, I915_GGTT_VIEW_ROTATED, @@ -168,135 +172,7 @@ extern const struct i915_ggtt_view i915_ggtt_view_rotated; enum i915_cache_level; -/** - * A VMA represents a GEM BO that is bound into an address space. Therefore, a - * VMA's presence cannot be guaranteed before binding, or after unbinding the - * object into/from the address space. - * - * To make things as simple as possible (ie. no refcounting), a VMA's lifetime - * will always be <= an objects lifetime. So object refcounting should cover us. - */ -struct i915_vma { - struct drm_mm_node node; - struct drm_i915_gem_object *obj; - struct i915_address_space *vm; - struct drm_i915_fence_reg *fence; - struct sg_table *pages; - void __iomem *iomap; - u64 size; - u64 display_alignment; - - unsigned int flags; - /** - * How many users have pinned this object in GTT space. The following - * users can each hold at most one reference: pwrite/pread, execbuffer - * (objects are not allowed multiple times for the same batchbuffer), - * and the framebuffer code. When switching/pageflipping, the - * framebuffer code has at most two buffers pinned per crtc. - * - * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 - * bits with absolutely no headroom. So use 4 bits. - */ -#define I915_VMA_PIN_MASK 0xf -#define I915_VMA_PIN_OVERFLOW BIT(5) - - /** Flags and address space this VMA is bound to */ -#define I915_VMA_GLOBAL_BIND BIT(6) -#define I915_VMA_LOCAL_BIND BIT(7) -#define I915_VMA_BIND_MASK (I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND | I915_VMA_PIN_OVERFLOW) - -#define I915_VMA_GGTT BIT(8) -#define I915_VMA_CAN_FENCE BIT(9) -#define I915_VMA_CLOSED BIT(10) - - unsigned int active; - struct i915_gem_active last_read[I915_NUM_ENGINES]; - struct i915_gem_active last_write; - struct i915_gem_active last_fence; - - /** - * Support different GGTT views into the same object. - * This means there can be multiple VMA mappings per object and per VM. - * i915_ggtt_view_type is used to distinguish between those entries. - * The default one of zero (I915_GGTT_VIEW_NORMAL) is default and also - * assumed in GEM functions which take no ggtt view parameter. - */ - struct i915_ggtt_view ggtt_view; - - /** This object's place on the active/inactive lists */ - struct list_head vm_link; - - struct list_head obj_link; /* Link in the object's VMA list */ - struct rb_node obj_node; - - /** This vma's place in the batchbuffer or on the eviction list */ - struct list_head exec_list; - - /** - * Used for performing relocations during execbuffer insertion. - */ - struct hlist_node exec_node; - unsigned long exec_handle; - struct drm_i915_gem_exec_object2 *exec_entry; -}; - -struct i915_vma * -i915_vma_create(struct drm_i915_gem_object *obj, - struct i915_address_space *vm, - const struct i915_ggtt_view *view); -void i915_vma_unpin_and_release(struct i915_vma **p_vma); - -static inline bool i915_vma_is_ggtt(const struct i915_vma *vma) -{ - return vma->flags & I915_VMA_GGTT; -} - -static inline bool i915_vma_is_map_and_fenceable(const struct i915_vma *vma) -{ - return vma->flags & I915_VMA_CAN_FENCE; -} - -static inline bool i915_vma_is_closed(const struct i915_vma *vma) -{ - return vma->flags & I915_VMA_CLOSED; -} - -static inline unsigned int i915_vma_get_active(const struct i915_vma *vma) -{ - return vma->active; -} - -static inline bool i915_vma_is_active(const struct i915_vma *vma) -{ - return i915_vma_get_active(vma); -} - -static inline void i915_vma_set_active(struct i915_vma *vma, - unsigned int engine) -{ - vma->active |= BIT(engine); -} - -static inline void i915_vma_clear_active(struct i915_vma *vma, - unsigned int engine) -{ - vma->active &= ~BIT(engine); -} - -static inline bool i915_vma_has_active_engine(const struct i915_vma *vma, - unsigned int engine) -{ - return vma->active & BIT(engine); -} - -static inline u32 i915_ggtt_offset(const struct i915_vma *vma) -{ - GEM_BUG_ON(!i915_vma_is_ggtt(vma)); - GEM_BUG_ON(!vma->node.allocated); - GEM_BUG_ON(upper_32_bits(vma->node.start)); - GEM_BUG_ON(upper_32_bits(vma->node.start + vma->node.size - 1)); - return lower_32_bits(vma->node.start); -} +struct i915_vma; struct i915_page_dma { struct page *page; @@ -606,13 +482,20 @@ i915_page_dir_dma_addr(const struct i915_hw_ppgtt *ppgtt, const unsigned n) px_dma(ppgtt->base.scratch_pd); } +static inline struct i915_ggtt * +i915_vm_to_ggtt(struct i915_address_space *vm) +{ + GEM_BUG_ON(!i915_is_ggtt(vm)); + return container_of(vm, struct i915_ggtt, base); +} + int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv); int i915_ggtt_init_hw(struct drm_i915_private *dev_priv); int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv); int i915_gem_init_ggtt(struct drm_i915_private *dev_priv); void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv); -int i915_ppgtt_init_hw(struct drm_device *dev); +int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv); void i915_ppgtt_release(struct kref *kref); struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_i915_private *dev_priv, struct drm_i915_file_private *fpriv, @@ -629,8 +512,8 @@ static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt) } void i915_check_and_clear_faults(struct drm_i915_private *dev_priv); -void i915_gem_suspend_gtt_mappings(struct drm_device *dev); -void i915_gem_restore_gtt_mappings(struct drm_device *dev); +void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv); +void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv); int __must_check i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj, struct sg_table *pages); @@ -653,88 +536,4 @@ void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj, #define PIN_OFFSET_FIXED BIT(11) #define PIN_OFFSET_MASK (~4095) -int __i915_vma_do_pin(struct i915_vma *vma, - u64 size, u64 alignment, u64 flags); -static inline int __must_check -i915_vma_pin(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) -{ - BUILD_BUG_ON(PIN_MBZ != I915_VMA_PIN_OVERFLOW); - BUILD_BUG_ON(PIN_GLOBAL != I915_VMA_GLOBAL_BIND); - BUILD_BUG_ON(PIN_USER != I915_VMA_LOCAL_BIND); - - /* Pin early to prevent the shrinker/eviction logic from destroying - * our vma as we insert and bind. - */ - if (likely(((++vma->flags ^ flags) & I915_VMA_BIND_MASK) == 0)) - return 0; - - return __i915_vma_do_pin(vma, size, alignment, flags); -} - -static inline int i915_vma_pin_count(const struct i915_vma *vma) -{ - return vma->flags & I915_VMA_PIN_MASK; -} - -static inline bool i915_vma_is_pinned(const struct i915_vma *vma) -{ - return i915_vma_pin_count(vma); -} - -static inline void __i915_vma_pin(struct i915_vma *vma) -{ - vma->flags++; - GEM_BUG_ON(vma->flags & I915_VMA_PIN_OVERFLOW); -} - -static inline void __i915_vma_unpin(struct i915_vma *vma) -{ - GEM_BUG_ON(!i915_vma_is_pinned(vma)); - vma->flags--; -} - -static inline void i915_vma_unpin(struct i915_vma *vma) -{ - GEM_BUG_ON(!drm_mm_node_allocated(&vma->node)); - __i915_vma_unpin(vma); -} - -/** - * i915_vma_pin_iomap - calls ioremap_wc to map the GGTT VMA via the aperture - * @vma: VMA to iomap - * - * The passed in VMA has to be pinned in the global GTT mappable region. - * An extra pinning of the VMA is acquired for the return iomapping, - * the caller must call i915_vma_unpin_iomap to relinquish the pinning - * after the iomapping is no longer required. - * - * Callers must hold the struct_mutex. - * - * Returns a valid iomapped pointer or ERR_PTR. - */ -void __iomem *i915_vma_pin_iomap(struct i915_vma *vma); -#define IO_ERR_PTR(x) ((void __iomem *)ERR_PTR(x)) - -/** - * i915_vma_unpin_iomap - unpins the mapping returned from i915_vma_iomap - * @vma: VMA to unpin - * - * Unpins the previously iomapped VMA from i915_vma_pin_iomap(). - * - * Callers must hold the struct_mutex. This function is only valid to be - * called on a VMA previously iomapped by the caller with i915_vma_pin_iomap(). - */ -static inline void i915_vma_unpin_iomap(struct i915_vma *vma) -{ - lockdep_assert_held(&vma->vm->dev->struct_mutex); - GEM_BUG_ON(vma->iomap == NULL); - i915_vma_unpin(vma); -} - -static inline struct page *i915_vma_first_page(struct i915_vma *vma) -{ - GEM_BUG_ON(!vma->pages); - return sg_page(vma->pages->sgl); -} - #endif diff --git a/drivers/gpu/drm/i915/i915_gem_object.h b/drivers/gpu/drm/i915/i915_gem_object.h new file mode 100644 index 000000000000..6a368de9d81e --- /dev/null +++ b/drivers/gpu/drm/i915/i915_gem_object.h @@ -0,0 +1,338 @@ +/* + * Copyright © 2016 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +#ifndef __I915_GEM_OBJECT_H__ +#define __I915_GEM_OBJECT_H__ + +#include <linux/reservation.h> + +#include <drm/drm_vma_manager.h> +#include <drm/drm_gem.h> +#include <drm/drmP.h> + +#include <drm/i915_drm.h> + +struct drm_i915_gem_object_ops { + unsigned int flags; +#define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1 +#define I915_GEM_OBJECT_IS_SHRINKABLE 0x2 + + /* Interface between the GEM object and its backing storage. + * get_pages() is called once prior to the use of the associated set + * of pages before to binding them into the GTT, and put_pages() is + * called after we no longer need them. As we expect there to be + * associated cost with migrating pages between the backing storage + * and making them available for the GPU (e.g. clflush), we may hold + * onto the pages after they are no longer referenced by the GPU + * in case they may be used again shortly (for example migrating the + * pages to a different memory domain within the GTT). put_pages() + * will therefore most likely be called when the object itself is + * being released or under memory pressure (where we attempt to + * reap pages for the shrinker). + */ + struct sg_table *(*get_pages)(struct drm_i915_gem_object *); + void (*put_pages)(struct drm_i915_gem_object *, struct sg_table *); + + int (*dmabuf_export)(struct drm_i915_gem_object *); + void (*release)(struct drm_i915_gem_object *); +}; + +struct drm_i915_gem_object { + struct drm_gem_object base; + + const struct drm_i915_gem_object_ops *ops; + + /** List of VMAs backed by this object */ + struct list_head vma_list; + struct rb_root vma_tree; + + /** Stolen memory for this object, instead of being backed by shmem. */ + struct drm_mm_node *stolen; + struct list_head global_link; + union { + struct rcu_head rcu; + struct llist_node freed; + }; + + /** + * Whether the object is currently in the GGTT mmap. + */ + struct list_head userfault_link; + + /** Used in execbuf to temporarily hold a ref */ + struct list_head obj_exec_link; + + struct list_head batch_pool_link; + + unsigned long flags; + + /** + * Have we taken a reference for the object for incomplete GPU + * activity? + */ +#define I915_BO_ACTIVE_REF 0 + + /* + * Is the object to be mapped as read-only to the GPU + * Only honoured if hardware has relevant pte bit + */ + unsigned long gt_ro:1; + unsigned int cache_level:3; + unsigned int cache_dirty:1; + + atomic_t frontbuffer_bits; + unsigned int frontbuffer_ggtt_origin; /* write once */ + struct i915_gem_active frontbuffer_write; + + /** Current tiling stride for the object, if it's tiled. */ + unsigned int tiling_and_stride; +#define FENCE_MINIMUM_STRIDE 128 /* See i915_tiling_ok() */ +#define TILING_MASK (FENCE_MINIMUM_STRIDE-1) +#define STRIDE_MASK (~TILING_MASK) + + /** Count of VMA actually bound by this object */ + unsigned int bind_count; + unsigned int active_count; + unsigned int pin_display; + + struct { + struct mutex lock; /* protects the pages and their use */ + atomic_t pages_pin_count; + + struct sg_table *pages; + void *mapping; + + struct i915_gem_object_page_iter { + struct scatterlist *sg_pos; + unsigned int sg_idx; /* in pages, but 32bit eek! */ + + struct radix_tree_root radix; + struct mutex lock; /* protects this cache */ + } get_page; + + /** + * Advice: are the backing pages purgeable? + */ + unsigned int madv:2; + + /** + * This is set if the object has been written to since the + * pages were last acquired. + */ + bool dirty:1; + + /** + * This is set if the object has been pinned due to unknown + * swizzling. + */ + bool quirked:1; + } mm; + + /** Breadcrumb of last rendering to the buffer. + * There can only be one writer, but we allow for multiple readers. + * If there is a writer that necessarily implies that all other + * read requests are complete - but we may only be lazily clearing + * the read requests. A read request is naturally the most recent + * request on a ring, so we may have two different write and read + * requests on one ring where the write request is older than the + * read request. This allows for the CPU to read from an active + * buffer by only waiting for the write to complete. + */ + struct reservation_object *resv; + + /** References from framebuffers, locks out tiling changes. */ + unsigned long framebuffer_references; + + /** Record of address bit 17 of each page at last unbind. */ + unsigned long *bit_17; + + struct i915_gem_userptr { + uintptr_t ptr; + unsigned read_only :1; + + struct i915_mm_struct *mm; + struct i915_mmu_object *mmu_object; + struct work_struct *work; + } userptr; + + /** for phys allocated objects */ + struct drm_dma_handle *phys_handle; + + struct reservation_object __builtin_resv; +}; + +static inline struct drm_i915_gem_object * +to_intel_bo(struct drm_gem_object *gem) +{ + /* Assert that to_intel_bo(NULL) == NULL */ + BUILD_BUG_ON(offsetof(struct drm_i915_gem_object, base)); + + return container_of(gem, struct drm_i915_gem_object, base); +} + +/** + * i915_gem_object_lookup_rcu - look up a temporary GEM object from its handle + * @filp: DRM file private date + * @handle: userspace handle + * + * Returns: + * + * A pointer to the object named by the handle if such exists on @filp, NULL + * otherwise. This object is only valid whilst under the RCU read lock, and + * note carefully the object may be in the process of being destroyed. + */ +static inline struct drm_i915_gem_object * +i915_gem_object_lookup_rcu(struct drm_file *file, u32 handle) +{ +#ifdef CONFIG_LOCKDEP + WARN_ON(debug_locks && !lock_is_held(&rcu_lock_map)); +#endif + return idr_find(&file->object_idr, handle); +} + +static inline struct drm_i915_gem_object * +i915_gem_object_lookup(struct drm_file *file, u32 handle) +{ + struct drm_i915_gem_object *obj; + + rcu_read_lock(); + obj = i915_gem_object_lookup_rcu(file, handle); + if (obj && !kref_get_unless_zero(&obj->base.refcount)) + obj = NULL; + rcu_read_unlock(); + + return obj; +} + +__deprecated +extern struct drm_gem_object * +drm_gem_object_lookup(struct drm_file *file, u32 handle); + +__attribute__((nonnull)) +static inline struct drm_i915_gem_object * +i915_gem_object_get(struct drm_i915_gem_object *obj) +{ + drm_gem_object_reference(&obj->base); + return obj; +} + +__deprecated +extern void drm_gem_object_reference(struct drm_gem_object *); + +__attribute__((nonnull)) +static inline void +i915_gem_object_put(struct drm_i915_gem_object *obj) +{ + __drm_gem_object_unreference(&obj->base); +} + +__deprecated +extern void drm_gem_object_unreference(struct drm_gem_object *); + +__deprecated +extern void drm_gem_object_unreference_unlocked(struct drm_gem_object *); + +static inline bool +i915_gem_object_is_dead(const struct drm_i915_gem_object *obj) +{ + return atomic_read(&obj->base.refcount.refcount) == 0; +} + +static inline bool +i915_gem_object_has_struct_page(const struct drm_i915_gem_object *obj) +{ + return obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE; +} + +static inline bool +i915_gem_object_is_shrinkable(const struct drm_i915_gem_object *obj) +{ + return obj->ops->flags & I915_GEM_OBJECT_IS_SHRINKABLE; +} + +static inline bool +i915_gem_object_is_active(const struct drm_i915_gem_object *obj) +{ + return obj->active_count; +} + +static inline bool +i915_gem_object_has_active_reference(const struct drm_i915_gem_object *obj) +{ + return test_bit(I915_BO_ACTIVE_REF, &obj->flags); +} + +static inline void +i915_gem_object_set_active_reference(struct drm_i915_gem_object *obj) +{ + lockdep_assert_held(&obj->base.dev->struct_mutex); + __set_bit(I915_BO_ACTIVE_REF, &obj->flags); +} + +static inline void +i915_gem_object_clear_active_reference(struct drm_i915_gem_object *obj) +{ + lockdep_assert_held(&obj->base.dev->struct_mutex); + __clear_bit(I915_BO_ACTIVE_REF, &obj->flags); +} + +void __i915_gem_object_release_unless_active(struct drm_i915_gem_object *obj); + +static inline unsigned int +i915_gem_object_get_tiling(struct drm_i915_gem_object *obj) +{ + return obj->tiling_and_stride & TILING_MASK; +} + +static inline bool +i915_gem_object_is_tiled(struct drm_i915_gem_object *obj) +{ + return i915_gem_object_get_tiling(obj) != I915_TILING_NONE; +} + +static inline unsigned int +i915_gem_object_get_stride(struct drm_i915_gem_object *obj) +{ + return obj->tiling_and_stride & STRIDE_MASK; +} + +static inline struct intel_engine_cs * +i915_gem_object_last_write_engine(struct drm_i915_gem_object *obj) +{ + struct intel_engine_cs *engine = NULL; + struct dma_fence *fence; + + rcu_read_lock(); + fence = reservation_object_get_excl_rcu(obj->resv); + rcu_read_unlock(); + + if (fence && dma_fence_is_i915(fence) && !dma_fence_is_signaled(fence)) + engine = to_request(fence)->engine; + dma_fence_put(fence); + + return engine; +} + +#endif + diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c index 0b3b051a5683..27e8f257fb39 100644 --- a/drivers/gpu/drm/i915/i915_gem_request.c +++ b/drivers/gpu/drm/i915/i915_gem_request.c @@ -113,6 +113,82 @@ i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) spin_unlock(&file_priv->mm.lock); } +static struct i915_dependency * +i915_dependency_alloc(struct drm_i915_private *i915) +{ + return kmem_cache_alloc(i915->dependencies, GFP_KERNEL); +} + +static void +i915_dependency_free(struct drm_i915_private *i915, + struct i915_dependency *dep) +{ + kmem_cache_free(i915->dependencies, dep); +} + +static void +__i915_priotree_add_dependency(struct i915_priotree *pt, + struct i915_priotree *signal, + struct i915_dependency *dep, + unsigned long flags) +{ + INIT_LIST_HEAD(&dep->dfs_link); + list_add(&dep->wait_link, &signal->waiters_list); + list_add(&dep->signal_link, &pt->signalers_list); + dep->signaler = signal; + dep->flags = flags; +} + +static int +i915_priotree_add_dependency(struct drm_i915_private *i915, + struct i915_priotree *pt, + struct i915_priotree *signal) +{ + struct i915_dependency *dep; + + dep = i915_dependency_alloc(i915); + if (!dep) + return -ENOMEM; + + __i915_priotree_add_dependency(pt, signal, dep, I915_DEPENDENCY_ALLOC); + return 0; +} + +static void +i915_priotree_fini(struct drm_i915_private *i915, struct i915_priotree *pt) +{ + struct i915_dependency *dep, *next; + + GEM_BUG_ON(!RB_EMPTY_NODE(&pt->node)); + + /* Everyone we depended upon (the fences we wait to be signaled) + * should retire before us and remove themselves from our list. + * However, retirement is run independently on each timeline and + * so we may be called out-of-order. + */ + list_for_each_entry_safe(dep, next, &pt->signalers_list, signal_link) { + list_del(&dep->wait_link); + if (dep->flags & I915_DEPENDENCY_ALLOC) + i915_dependency_free(i915, dep); + } + + /* Remove ourselves from everyone who depends upon us */ + list_for_each_entry_safe(dep, next, &pt->waiters_list, wait_link) { + list_del(&dep->signal_link); + if (dep->flags & I915_DEPENDENCY_ALLOC) + i915_dependency_free(i915, dep); + } +} + +static void +i915_priotree_init(struct i915_priotree *pt) +{ + INIT_LIST_HEAD(&pt->signalers_list); + INIT_LIST_HEAD(&pt->waiters_list); + RB_CLEAR_NODE(&pt->node); + pt->priority = INT_MIN; +} + void i915_gem_retire_noop(struct i915_gem_active *active, struct drm_i915_gem_request *request) { @@ -124,7 +200,10 @@ static void i915_gem_request_retire(struct drm_i915_gem_request *request) struct i915_gem_active *active, *next; lockdep_assert_held(&request->i915->drm.struct_mutex); + GEM_BUG_ON(!i915_sw_fence_done(&request->submit)); + GEM_BUG_ON(!i915_sw_fence_done(&request->execute)); GEM_BUG_ON(!i915_gem_request_completed(request)); + GEM_BUG_ON(!request->i915->gt.active_requests); trace_i915_gem_request_retire(request); @@ -142,7 +221,12 @@ static void i915_gem_request_retire(struct drm_i915_gem_request *request) */ list_del(&request->ring_link); request->ring->last_retired_head = request->postfix; - request->i915->gt.active_requests--; + if (!--request->i915->gt.active_requests) { + GEM_BUG_ON(!request->i915->gt.awake); + mod_delayed_work(request->i915->wq, + &request->i915->gt.idle_work, + msecs_to_jiffies(100)); + } /* Walk through the active list, calling retire on each. This allows * objects to track their GPU activity and mark themselves as idle @@ -182,6 +266,8 @@ static void i915_gem_request_retire(struct drm_i915_gem_request *request) i915_gem_context_put(request->ctx); dma_fence_signal(&request->fence); + + i915_priotree_fini(request->i915, &request->priotree); i915_gem_request_put(request); } @@ -241,9 +327,8 @@ static int i915_gem_init_global_seqno(struct drm_i915_private *i915, u32 seqno) /* If the seqno wraps around, we need to clear the breadcrumb rbtree */ if (!i915_seqno_passed(seqno, atomic_read(&timeline->next_seqno))) { - while (intel_kick_waiters(i915) || intel_kick_signalers(i915)) - yield(); - yield(); + while (intel_breadcrumbs_busy(i915)) + cond_resched(); /* spin until threads are complete */ } atomic_set(&timeline->next_seqno, seqno); @@ -307,25 +392,16 @@ static u32 timeline_get_seqno(struct i915_gem_timeline *tl) return atomic_inc_return(&tl->next_seqno); } -static int __i915_sw_fence_call -submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state) +void __i915_gem_request_submit(struct drm_i915_gem_request *request) { - struct drm_i915_gem_request *request = - container_of(fence, typeof(*request), submit); struct intel_engine_cs *engine = request->engine; struct intel_timeline *timeline; - unsigned long flags; u32 seqno; - if (state != FENCE_COMPLETE) - return NOTIFY_DONE; - /* Transfer from per-context onto the global per-engine timeline */ timeline = engine->timeline; GEM_BUG_ON(timeline == request->timeline); - - /* Will be called from irq-context when using foreign DMA fences */ - spin_lock_irqsave(&timeline->lock, flags); + assert_spin_locked(&timeline->lock); seqno = timeline_get_seqno(timeline->common); GEM_BUG_ON(!seqno); @@ -345,14 +421,43 @@ submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state) GEM_BUG_ON(!request->global_seqno); engine->emit_breadcrumb(request, request->ring->vaddr + request->postfix); - engine->submit_request(request); - spin_lock_nested(&request->timeline->lock, SINGLE_DEPTH_NESTING); + spin_lock(&request->timeline->lock); list_move_tail(&request->link, &timeline->requests); spin_unlock(&request->timeline->lock); - spin_unlock_irqrestore(&timeline->lock, flags); + i915_sw_fence_commit(&request->execute); +} + +void i915_gem_request_submit(struct drm_i915_gem_request *request) +{ + struct intel_engine_cs *engine = request->engine; + unsigned long flags; + + /* Will be called from irq-context when using foreign fences. */ + spin_lock_irqsave(&engine->timeline->lock, flags); + + __i915_gem_request_submit(request); + + spin_unlock_irqrestore(&engine->timeline->lock, flags); +} + +static int __i915_sw_fence_call +submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state) +{ + if (state == FENCE_COMPLETE) { + struct drm_i915_gem_request *request = + container_of(fence, typeof(*request), submit); + + request->engine->submit_request(request); + } + + return NOTIFY_DONE; +} +static int __i915_sw_fence_call +execute_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state) +{ return NOTIFY_DONE; } @@ -441,6 +546,14 @@ i915_gem_request_alloc(struct intel_engine_cs *engine, __timeline_get_seqno(req->timeline->common)); i915_sw_fence_init(&req->submit, submit_notify); + i915_sw_fence_init(&req->execute, execute_notify); + /* Ensure that the execute fence completes after the submit fence - + * as we complete the execute fence from within the submit fence + * callback, its completion would otherwise be visible first. + */ + i915_sw_fence_await_sw_fence(&req->execute, &req->submit, &req->execq); + + i915_priotree_init(&req->priotree); INIT_LIST_HEAD(&req->active_list); req->i915 = dev_priv; @@ -495,6 +608,14 @@ i915_gem_request_await_request(struct drm_i915_gem_request *to, GEM_BUG_ON(to == from); + if (to->engine->schedule) { + ret = i915_priotree_add_dependency(to->i915, + &to->priotree, + &from->priotree); + if (ret < 0) + return ret; + } + if (to->timeline == from->timeline) return 0; @@ -650,6 +771,8 @@ static void i915_gem_mark_busy(const struct intel_engine_cs *engine) if (dev_priv->gt.awake) return; + GEM_BUG_ON(!dev_priv->gt.active_requests); + intel_runtime_pm_get_noresume(dev_priv); dev_priv->gt.awake = true; @@ -718,9 +841,15 @@ void __i915_add_request(struct drm_i915_gem_request *request, bool flush_caches) prev = i915_gem_active_raw(&timeline->last_request, &request->i915->drm.struct_mutex); - if (prev) + if (prev) { i915_sw_fence_await_sw_fence(&request->submit, &prev->submit, &request->submitq); + if (engine->schedule) + __i915_priotree_add_dependency(&request->priotree, + &prev->priotree, + &request->dep, + 0); + } spin_lock_irq(&timeline->lock); list_add_tail(&request->link, &timeline->requests); @@ -737,6 +866,19 @@ void __i915_add_request(struct drm_i915_gem_request *request, bool flush_caches) i915_gem_mark_busy(engine); + /* Let the backend know a new request has arrived that may need + * to adjust the existing execution schedule due to a high priority + * request - i.e. we may want to preempt the current request in order + * to run a high priority dependency chain *before* we can execute this + * request. + * + * This is called before the request is ready to run so that we can + * decide whether to preempt the entire chain so that it is ready to + * run at the earliest possible convenience. + */ + if (engine->schedule) + engine->schedule(request, request->ctx->priority); + local_bh_disable(); i915_sw_fence_commit(&request->submit); local_bh_enable(); /* Kick the execlists tasklet if just scheduled */ @@ -817,9 +959,9 @@ bool __i915_spin_request(const struct drm_i915_gem_request *req, } static long -__i915_request_wait_for_submit(struct drm_i915_gem_request *request, - unsigned int flags, - long timeout) +__i915_request_wait_for_execute(struct drm_i915_gem_request *request, + unsigned int flags, + long timeout) { const int state = flags & I915_WAIT_INTERRUPTIBLE ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE; @@ -831,9 +973,9 @@ __i915_request_wait_for_submit(struct drm_i915_gem_request *request, add_wait_queue(q, &reset); do { - prepare_to_wait(&request->submit.wait, &wait, state); + prepare_to_wait(&request->execute.wait, &wait, state); - if (i915_sw_fence_done(&request->submit)) + if (i915_sw_fence_done(&request->execute)) break; if (flags & I915_WAIT_LOCKED && @@ -851,7 +993,7 @@ __i915_request_wait_for_submit(struct drm_i915_gem_request *request, timeout = io_schedule_timeout(timeout); } while (timeout); - finish_wait(&request->submit.wait, &wait); + finish_wait(&request->execute.wait, &wait); if (flags & I915_WAIT_LOCKED) remove_wait_queue(q, &reset); @@ -903,13 +1045,14 @@ long i915_wait_request(struct drm_i915_gem_request *req, trace_i915_gem_request_wait_begin(req); - if (!i915_sw_fence_done(&req->submit)) { - timeout = __i915_request_wait_for_submit(req, flags, timeout); + if (!i915_sw_fence_done(&req->execute)) { + timeout = __i915_request_wait_for_execute(req, flags, timeout); if (timeout < 0) goto complete; - GEM_BUG_ON(!i915_sw_fence_done(&req->submit)); + GEM_BUG_ON(!i915_sw_fence_done(&req->execute)); } + GEM_BUG_ON(!i915_sw_fence_done(&req->submit)); GEM_BUG_ON(!req->global_seqno); /* Optimistic short spin before touching IRQs */ @@ -1013,13 +1156,6 @@ void i915_gem_retire_requests(struct drm_i915_private *dev_priv) if (!dev_priv->gt.active_requests) return; - GEM_BUG_ON(!dev_priv->gt.awake); - for_each_engine(engine, dev_priv, id) engine_retire_requests(engine); - - if (!dev_priv->gt.active_requests) - mod_delayed_work(dev_priv->wq, - &dev_priv->gt.idle_work, - msecs_to_jiffies(100)); } diff --git a/drivers/gpu/drm/i915/i915_gem_request.h b/drivers/gpu/drm/i915/i915_gem_request.h index 75f8360b3421..e2b077df2da0 100644 --- a/drivers/gpu/drm/i915/i915_gem_request.h +++ b/drivers/gpu/drm/i915/i915_gem_request.h @@ -30,6 +30,9 @@ #include "i915_gem.h" #include "i915_sw_fence.h" +struct drm_file; +struct drm_i915_gem_object; + struct intel_wait { struct rb_node node; struct task_struct *tsk; @@ -41,6 +44,33 @@ struct intel_signal_node { struct intel_wait wait; }; +struct i915_dependency { + struct i915_priotree *signaler; + struct list_head signal_link; + struct list_head wait_link; + struct list_head dfs_link; + unsigned long flags; +#define I915_DEPENDENCY_ALLOC BIT(0) +}; + +/* Requests exist in a complex web of interdependencies. Each request + * has to wait for some other request to complete before it is ready to be run + * (e.g. we have to wait until the pixels have been rendering into a texture + * before we can copy from it). We track the readiness of a request in terms + * of fences, but we also need to keep the dependency tree for the lifetime + * of the request (beyond the life of an individual fence). We use the tree + * at various points to reorder the requests whilst keeping the requests + * in order with respect to their various dependencies. + */ +struct i915_priotree { + struct list_head signalers_list; /* those before us, we depend upon */ + struct list_head waiters_list; /* those after us, they depend upon us */ + struct rb_node node; + int priority; +#define I915_PRIORITY_MAX 1024 +#define I915_PRIORITY_MIN (-I915_PRIORITY_MAX) +}; + /** * Request queue structure. * @@ -84,8 +114,34 @@ struct drm_i915_gem_request { struct intel_timeline *timeline; struct intel_signal_node signaling; + /* Fences for the various phases in the request's lifetime. + * + * The submit fence is used to await upon all of the request's + * dependencies. When it is signaled, the request is ready to run. + * It is used by the driver to then queue the request for execution. + * + * The execute fence is used to signal when the request has been + * sent to hardware. + * + * It is illegal for the submit fence of one request to wait upon the + * execute fence of an earlier request. It should be sufficient to + * wait upon the submit fence of the earlier request. + */ struct i915_sw_fence submit; + struct i915_sw_fence execute; wait_queue_t submitq; + wait_queue_t execq; + + /* A list of everyone we wait upon, and everyone who waits upon us. + * Even though we will not be submitted to the hardware before the + * submit fence is signaled (it waits for all external events as well + * as our own requests), the scheduler still needs to know the + * dependency tree for the lifetime of the request (from execbuf + * to retirement), i.e. bidirectional dependency information for the + * request not tied to individual fences. + */ + struct i915_priotree priotree; + struct i915_dependency dep; u32 global_seqno; @@ -143,9 +199,6 @@ struct drm_i915_gem_request { struct drm_i915_file_private *file_priv; /** file_priv list entry for this request */ struct list_head client_list; - - /** Link in the execlist submission queue, guarded by execlist_lock. */ - struct list_head execlist_link; }; extern const struct dma_fence_ops i915_fence_ops; @@ -162,18 +215,6 @@ int i915_gem_request_add_to_client(struct drm_i915_gem_request *req, struct drm_file *file); void i915_gem_request_retire_upto(struct drm_i915_gem_request *req); -static inline u32 -i915_gem_request_get_seqno(struct drm_i915_gem_request *req) -{ - return req ? req->global_seqno : 0; -} - -static inline struct intel_engine_cs * -i915_gem_request_get_engine(struct drm_i915_gem_request *req) -{ - return req ? req->engine : NULL; -} - static inline struct drm_i915_gem_request * to_request(struct dma_fence *fence) { @@ -226,6 +267,9 @@ void __i915_add_request(struct drm_i915_gem_request *req, bool flush_caches); #define i915_add_request_no_flush(req) \ __i915_add_request(req, false) +void __i915_gem_request_submit(struct drm_i915_gem_request *request); +void i915_gem_request_submit(struct drm_i915_gem_request *request); + struct intel_rps_client; #define NO_WAITBOOST ERR_PTR(-1) #define IS_RPS_CLIENT(p) (!IS_ERR(p)) diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c index b1d367dba347..ebaa941c83af 100644 --- a/drivers/gpu/drm/i915/i915_gem_stolen.c +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c @@ -89,9 +89,8 @@ void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv, mutex_unlock(&dev_priv->mm.stolen_lock); } -static unsigned long i915_stolen_to_physical(struct drm_device *dev) +static unsigned long i915_stolen_to_physical(struct drm_i915_private *dev_priv) { - struct drm_i915_private *dev_priv = to_i915(dev); struct pci_dev *pdev = dev_priv->drm.pdev; struct i915_ggtt *ggtt = &dev_priv->ggtt; struct resource *r; @@ -253,7 +252,7 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev) * kernel. So if the region is already marked as busy, something * is seriously wrong. */ - r = devm_request_mem_region(dev->dev, base, ggtt->stolen_size, + r = devm_request_mem_region(dev_priv->drm.dev, base, ggtt->stolen_size, "Graphics Stolen Memory"); if (r == NULL) { /* @@ -264,7 +263,7 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev) * PCI bus, but have an off-by-one error. Hence retry the * reservation starting from 1 instead of 0. */ - r = devm_request_mem_region(dev->dev, base + 1, + r = devm_request_mem_region(dev_priv->drm.dev, base + 1, ggtt->stolen_size - 1, "Graphics Stolen Memory"); /* @@ -408,9 +407,8 @@ static void bdw_get_stolen_reserved(struct drm_i915_private *dev_priv, *size = stolen_top - *base; } -int i915_gem_init_stolen(struct drm_device *dev) +int i915_gem_init_stolen(struct drm_i915_private *dev_priv) { - struct drm_i915_private *dev_priv = to_i915(dev); struct i915_ggtt *ggtt = &dev_priv->ggtt; unsigned long reserved_total, reserved_base = 0, reserved_size; unsigned long stolen_top; @@ -418,7 +416,7 @@ int i915_gem_init_stolen(struct drm_device *dev) mutex_init(&dev_priv->mm.stolen_lock); #ifdef CONFIG_INTEL_IOMMU - if (intel_iommu_gfx_mapped && INTEL_INFO(dev)->gen < 8) { + if (intel_iommu_gfx_mapped && INTEL_GEN(dev_priv) < 8) { DRM_INFO("DMAR active, disabling use of stolen memory\n"); return 0; } @@ -427,7 +425,7 @@ int i915_gem_init_stolen(struct drm_device *dev) if (ggtt->stolen_size == 0) return 0; - dev_priv->mm.stolen_base = i915_stolen_to_physical(dev); + dev_priv->mm.stolen_base = i915_stolen_to_physical(dev_priv); if (dev_priv->mm.stolen_base == 0) return 0; @@ -515,12 +513,10 @@ i915_pages_create_for_stolen(struct drm_device *dev, u32 offset, u32 size) { struct drm_i915_private *dev_priv = to_i915(dev); - struct i915_ggtt *ggtt = &dev_priv->ggtt; struct sg_table *st; struct scatterlist *sg; - DRM_DEBUG_DRIVER("offset=0x%x, size=%d\n", offset, size); - BUG_ON(offset > ggtt->stolen_size - size); + GEM_BUG_ON(offset > dev_priv->ggtt.stolen_size - size); /* We hide that we have no struct page backing our stolen object * by wrapping the contiguous physical allocation with a fake @@ -529,11 +525,11 @@ i915_pages_create_for_stolen(struct drm_device *dev, st = kmalloc(sizeof(*st), GFP_KERNEL); if (st == NULL) - return NULL; + return ERR_PTR(-ENOMEM); if (sg_alloc_table(st, 1, GFP_KERNEL)) { kfree(st); - return NULL; + return ERR_PTR(-ENOMEM); } sg = st->sgl; @@ -557,7 +553,7 @@ i915_gem_object_get_pages_stolen(struct drm_i915_gem_object *obj) static void i915_gem_object_put_pages_stolen(struct drm_i915_gem_object *obj, struct sg_table *pages) { - /* Should only be called during free */ + /* Should only be called from i915_gem_object_release_stolen() */ sg_free_table(pages); kfree(pages); } @@ -566,15 +562,16 @@ static void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj) { struct drm_i915_private *dev_priv = to_i915(obj->base.dev); + struct drm_mm_node *stolen = fetch_and_zero(&obj->stolen); + + GEM_BUG_ON(!stolen); __i915_gem_object_unpin_pages(obj); - if (obj->stolen) { - i915_gem_stolen_remove_node(dev_priv, obj->stolen); - kfree(obj->stolen); - obj->stolen = NULL; - } + i915_gem_stolen_remove_node(dev_priv, stolen); + kfree(stolen); } + static const struct drm_i915_gem_object_ops i915_gem_object_stolen_ops = { .get_pages = i915_gem_object_get_pages_stolen, .put_pages = i915_gem_object_put_pages_stolen, @@ -596,7 +593,8 @@ _i915_gem_object_create_stolen(struct drm_device *dev, obj->stolen = stolen; obj->base.read_domains = I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT; - obj->cache_level = HAS_LLC(dev) ? I915_CACHE_LLC : I915_CACHE_NONE; + obj->cache_level = HAS_LLC(to_i915(dev)) ? + I915_CACHE_LLC : I915_CACHE_NONE; if (i915_gem_object_pin_pages(obj)) goto cleanup; @@ -619,7 +617,6 @@ i915_gem_object_create_stolen(struct drm_device *dev, u32 size) if (!drm_mm_initialized(&dev_priv->mm.stolen)) return NULL; - DRM_DEBUG_KMS("creating stolen object: size=%x\n", size); if (size == 0) return NULL; diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c index 251d51b01174..c85e7b06bdba 100644 --- a/drivers/gpu/drm/i915/i915_gem_tiling.c +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c @@ -60,9 +60,9 @@ /* Check pitch constriants for all chips & tiling formats */ static bool -i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode) +i915_tiling_ok(struct drm_i915_private *dev_priv, + int stride, int size, int tiling_mode) { - struct drm_i915_private *dev_priv = to_i915(dev); int tile_width; /* Linear is always fine */ @@ -81,10 +81,10 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode) /* check maximum stride & object size */ /* i965+ stores the end address of the gtt mapping in the fence * reg, so dont bother to check the size */ - if (INTEL_INFO(dev)->gen >= 7) { + if (INTEL_GEN(dev_priv) >= 7) { if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL) return false; - } else if (INTEL_INFO(dev)->gen >= 4) { + } else if (INTEL_GEN(dev_priv) >= 4) { if (stride / 128 > I965_FENCE_MAX_PITCH_VAL) return false; } else { @@ -104,7 +104,7 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode) return false; /* 965+ just needs multiples of tile width */ - if (INTEL_INFO(dev)->gen >= 4) { + if (INTEL_GEN(dev_priv) >= 4) { if (stride & (tile_width - 1)) return false; return true; @@ -199,7 +199,7 @@ i915_gem_set_tiling(struct drm_device *dev, void *data, if (!obj) return -ENOENT; - if (!i915_tiling_ok(dev, + if (!i915_tiling_ok(dev_priv, args->stride, obj->base.size, args->tiling_mode)) { i915_gem_object_put(obj); return -EINVAL; diff --git a/drivers/gpu/drm/i915/i915_gem_timeline.c b/drivers/gpu/drm/i915/i915_gem_timeline.c index fc8f13a79f8f..bf8a471b61e6 100644 --- a/drivers/gpu/drm/i915/i915_gem_timeline.c +++ b/drivers/gpu/drm/i915/i915_gem_timeline.c @@ -24,9 +24,11 @@ #include "i915_drv.h" -int i915_gem_timeline_init(struct drm_i915_private *i915, - struct i915_gem_timeline *timeline, - const char *name) +static int __i915_gem_timeline_init(struct drm_i915_private *i915, + struct i915_gem_timeline *timeline, + const char *name, + struct lock_class_key *lockclass, + const char *lockname) { unsigned int i; u64 fences; @@ -47,8 +49,11 @@ int i915_gem_timeline_init(struct drm_i915_private *i915, tl->fence_context = fences++; tl->common = timeline; - +#ifdef CONFIG_DEBUG_SPINLOCK + __raw_spin_lock_init(&tl->lock.rlock, lockname, lockclass); +#else spin_lock_init(&tl->lock); +#endif init_request_active(&tl->last_request, NULL); INIT_LIST_HEAD(&tl->requests); } @@ -56,6 +61,26 @@ int i915_gem_timeline_init(struct drm_i915_private *i915, return 0; } +int i915_gem_timeline_init(struct drm_i915_private *i915, + struct i915_gem_timeline *timeline, + const char *name) +{ + static struct lock_class_key class; + + return __i915_gem_timeline_init(i915, timeline, name, + &class, "&timeline->lock"); +} + +int i915_gem_timeline_init__global(struct drm_i915_private *i915) +{ + static struct lock_class_key class; + + return __i915_gem_timeline_init(i915, + &i915->gt.global_timeline, + "[execution]", + &class, "&global_timeline->lock"); +} + void i915_gem_timeline_fini(struct i915_gem_timeline *tl) { lockdep_assert_held(&tl->i915->drm.struct_mutex); diff --git a/drivers/gpu/drm/i915/i915_gem_timeline.h b/drivers/gpu/drm/i915/i915_gem_timeline.h index f2bf7b1d49a1..98d99a62b4ae 100644 --- a/drivers/gpu/drm/i915/i915_gem_timeline.h +++ b/drivers/gpu/drm/i915/i915_gem_timeline.h @@ -67,6 +67,7 @@ struct i915_gem_timeline { int i915_gem_timeline_init(struct drm_i915_private *i915, struct i915_gem_timeline *tl, const char *name); +int i915_gem_timeline_init__global(struct drm_i915_private *i915); void i915_gem_timeline_fini(struct i915_gem_timeline *tl); #endif diff --git a/drivers/gpu/drm/i915/i915_gem_userptr.c b/drivers/gpu/drm/i915/i915_gem_userptr.c index 64261639f547..107ddf51065e 100644 --- a/drivers/gpu/drm/i915/i915_gem_userptr.c +++ b/drivers/gpu/drm/i915/i915_gem_userptr.c @@ -753,12 +753,13 @@ static const struct drm_i915_gem_object_ops i915_gem_userptr_ops = { int i915_gem_userptr_ioctl(struct drm_device *dev, void *data, struct drm_file *file) { + struct drm_i915_private *dev_priv = to_i915(dev); struct drm_i915_gem_userptr *args = data; struct drm_i915_gem_object *obj; int ret; u32 handle; - if (!HAS_LLC(dev) && !HAS_SNOOP(dev)) { + if (!HAS_LLC(dev_priv) && !HAS_SNOOP(dev_priv)) { /* We cannot support coherent userptr objects on hw without * LLC and broken snooping. */ diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index 204093f3eaa5..ae84aa4b1467 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -528,8 +528,7 @@ static void err_print_capabilities(struct drm_i915_error_state_buf *m, int i915_error_state_to_str(struct drm_i915_error_state_buf *m, const struct i915_error_state_file_priv *error_priv) { - struct drm_device *dev = error_priv->dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(error_priv->dev); struct pci_dev *pdev = dev_priv->drm.pdev; struct drm_i915_error_state *error = error_priv->error; struct drm_i915_error_object *obj; @@ -573,7 +572,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m, pdev->subsystem_device); err_printf(m, "IOMMU enabled?: %d\n", error->iommu); - if (HAS_CSR(dev)) { + if (HAS_CSR(dev_priv)) { struct intel_csr *csr = &dev_priv->csr; err_printf(m, "DMC loaded: %s\n", @@ -585,7 +584,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m, err_printf(m, "EIR: 0x%08x\n", error->eir); err_printf(m, "IER: 0x%08x\n", error->ier); - if (INTEL_INFO(dev)->gen >= 8) { + if (INTEL_GEN(dev_priv) >= 8) { for (i = 0; i < 4; i++) err_printf(m, "GTIER gt %d: 0x%08x\n", i, error->gtier[i]); @@ -600,10 +599,10 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m, for (i = 0; i < dev_priv->num_fence_regs; i++) err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]); - if (INTEL_INFO(dev)->gen >= 6) { + if (INTEL_GEN(dev_priv) >= 6) { err_printf(m, "ERROR: 0x%08x\n", error->error); - if (INTEL_INFO(dev)->gen >= 8) + if (INTEL_GEN(dev_priv) >= 8) err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n", error->fault_data1, error->fault_data0); @@ -708,7 +707,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m, intel_overlay_print_error_state(m, error->overlay); if (error->display) - intel_display_print_error_state(m, dev, error->display); + intel_display_print_error_state(m, dev_priv, error->display); out: if (m->bytes == 0 && m->err) @@ -861,16 +860,19 @@ out: static inline uint32_t __active_get_seqno(struct i915_gem_active *active) { - return i915_gem_request_get_seqno(__i915_gem_active_peek(active)); + struct drm_i915_gem_request *request; + + request = __i915_gem_active_peek(active); + return request ? request->global_seqno : 0; } static inline int __active_get_engine_id(struct i915_gem_active *active) { - struct intel_engine_cs *engine; + struct drm_i915_gem_request *request; - engine = i915_gem_request_get_engine(__i915_gem_active_peek(active)); - return engine ? engine->id : -1; + request = __i915_gem_active_peek(active); + return request ? request->engine->id : -1; } static void capture_bo(struct drm_i915_error_buffer *err, @@ -884,8 +886,8 @@ static void capture_bo(struct drm_i915_error_buffer *err, for (i = 0; i < I915_NUM_ENGINES; i++) err->rseqno[i] = __active_get_seqno(&vma->last_read[i]); - err->wseqno = __active_get_seqno(&vma->last_write); - err->engine = __active_get_engine_id(&vma->last_write); + err->wseqno = __active_get_seqno(&obj->frontbuffer_write); + err->engine = __active_get_engine_id(&obj->frontbuffer_write); err->gtt_offset = vma->node.start; err->read_domains = obj->base.read_domains; @@ -1440,7 +1442,6 @@ static void i915_gem_capture_guc_log_buffer(struct drm_i915_private *dev_priv, static void i915_capture_reg_state(struct drm_i915_private *dev_priv, struct drm_i915_error_state *error) { - struct drm_device *dev = &dev_priv->drm; int i; /* General organization @@ -1461,7 +1462,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv, if (IS_GEN7(dev_priv)) error->err_int = I915_READ(GEN7_ERR_INT); - if (INTEL_INFO(dev)->gen >= 8) { + if (INTEL_GEN(dev_priv) >= 8) { error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0); error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1); } @@ -1473,10 +1474,10 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv, } /* 2: Registers which belong to multiple generations */ - if (INTEL_INFO(dev)->gen >= 7) + if (INTEL_GEN(dev_priv) >= 7) error->forcewake = I915_READ_FW(FORCEWAKE_MT); - if (INTEL_INFO(dev)->gen >= 6) { + if (INTEL_GEN(dev_priv) >= 6) { error->derrmr = I915_READ(DERRMR); error->error = I915_READ(ERROR_GEN6); error->done_reg = I915_READ(DONE_REG); @@ -1489,10 +1490,10 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv, } /* 4: Everything else */ - if (HAS_HW_CONTEXTS(dev)) + if (HAS_HW_CONTEXTS(dev_priv)) error->ccid = I915_READ(CCID); - if (INTEL_INFO(dev)->gen >= 8) { + if (INTEL_GEN(dev_priv) >= 8) { error->ier = I915_READ(GEN8_DE_MISC_IER); for (i = 0; i < 4; i++) error->gtier[i] = I915_READ(GEN8_GT_IER(i)); diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c index 666dab7a675a..4462112725ef 100644 --- a/drivers/gpu/drm/i915/i915_guc_submission.c +++ b/drivers/gpu/drm/i915/i915_guc_submission.c @@ -629,11 +629,23 @@ static int guc_ring_doorbell(struct i915_guc_client *gc) static void i915_guc_submit(struct drm_i915_gem_request *rq) { struct drm_i915_private *dev_priv = rq->i915; - unsigned int engine_id = rq->engine->id; + struct intel_engine_cs *engine = rq->engine; + unsigned int engine_id = engine->id; struct intel_guc *guc = &rq->i915->guc; struct i915_guc_client *client = guc->execbuf_client; int b_ret; + /* We keep the previous context alive until we retire the following + * request. This ensures that any the context object is still pinned + * for any residual writes the HW makes into it on the context switch + * into the next object following the breadcrumb. Otherwise, we may + * retire the context too early. + */ + rq->previous_context = engine->last_context; + engine->last_context = rq->ctx; + + i915_gem_request_submit(rq); + spin_lock(&client->wq_lock); guc_wq_item_append(client, rq); @@ -1520,6 +1532,7 @@ int i915_guc_submission_enable(struct drm_i915_private *dev_priv) /* Take over from manual control of ELSP (execlists) */ for_each_engine(engine, dev_priv, id) { engine->submit_request = i915_guc_submit; + engine->schedule = NULL; /* Replay the current set of previously submitted requests */ list_for_each_entry(request, diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 6d7505b5c5e7..07ca71cabb2b 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2848,10 +2848,8 @@ static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe) spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); } -static void ibx_irq_reset(struct drm_device *dev) +static void ibx_irq_reset(struct drm_i915_private *dev_priv) { - struct drm_i915_private *dev_priv = to_i915(dev); - if (HAS_PCH_NOP(dev_priv)) return; @@ -2881,12 +2879,10 @@ static void ibx_irq_pre_postinstall(struct drm_device *dev) POSTING_READ(SDEIER); } -static void gen5_gt_irq_reset(struct drm_device *dev) +static void gen5_gt_irq_reset(struct drm_i915_private *dev_priv) { - struct drm_i915_private *dev_priv = to_i915(dev); - GEN5_IRQ_RESET(GT); - if (INTEL_INFO(dev)->gen >= 6) + if (INTEL_GEN(dev_priv) >= 6) GEN5_IRQ_RESET(GEN6_PM); } @@ -2951,9 +2947,9 @@ static void ironlake_irq_reset(struct drm_device *dev) if (IS_GEN7(dev_priv)) I915_WRITE(GEN7_ERR_INT, 0xffffffff); - gen5_gt_irq_reset(dev); + gen5_gt_irq_reset(dev_priv); - ibx_irq_reset(dev); + ibx_irq_reset(dev_priv); } static void valleyview_irq_preinstall(struct drm_device *dev) @@ -2963,7 +2959,7 @@ static void valleyview_irq_preinstall(struct drm_device *dev) I915_WRITE(VLV_MASTER_IER, 0); POSTING_READ(VLV_MASTER_IER); - gen5_gt_irq_reset(dev); + gen5_gt_irq_reset(dev_priv); spin_lock_irq(&dev_priv->irq_lock); if (dev_priv->display_irqs_enabled) @@ -2999,7 +2995,7 @@ static void gen8_irq_reset(struct drm_device *dev) GEN5_IRQ_RESET(GEN8_PCU_); if (HAS_PCH_SPLIT(dev_priv)) - ibx_irq_reset(dev); + ibx_irq_reset(dev_priv); } void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, @@ -3222,7 +3218,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev) GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs); - if (INTEL_INFO(dev)->gen >= 6) { + if (INTEL_GEN(dev_priv) >= 6) { /* * RPS interrupts will get enabled/disabled on demand when RPS * itself is enabled/disabled. @@ -3242,7 +3238,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev) struct drm_i915_private *dev_priv = to_i915(dev); u32 display_mask, extra_mask; - if (INTEL_INFO(dev)->gen >= 7) { + if (INTEL_GEN(dev_priv) >= 7) { display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB | DE_PLANEB_FLIP_DONE_IVB | @@ -3466,7 +3462,7 @@ static void valleyview_irq_uninstall(struct drm_device *dev) I915_WRITE(VLV_MASTER_IER, 0); POSTING_READ(VLV_MASTER_IER); - gen5_gt_irq_reset(dev); + gen5_gt_irq_reset(dev_priv); I915_WRITE(HWSTAM, 0xffffffff); @@ -3678,7 +3674,7 @@ static void i915_irq_preinstall(struct drm_device * dev) struct drm_i915_private *dev_priv = to_i915(dev); int pipe; - if (I915_HAS_HOTPLUG(dev)) { + if (I915_HAS_HOTPLUG(dev_priv)) { i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); } @@ -3712,7 +3708,7 @@ static int i915_irq_postinstall(struct drm_device *dev) I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | I915_USER_INTERRUPT; - if (I915_HAS_HOTPLUG(dev)) { + if (I915_HAS_HOTPLUG(dev_priv)) { i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); POSTING_READ(PORT_HOTPLUG_EN); @@ -3880,7 +3876,7 @@ static void i915_irq_uninstall(struct drm_device * dev) struct drm_i915_private *dev_priv = to_i915(dev); int pipe; - if (I915_HAS_HOTPLUG(dev)) { + if (I915_HAS_HOTPLUG(dev_priv)) { i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); } @@ -4145,7 +4141,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv) INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); - if (HAS_GUC_SCHED(dev)) + if (HAS_GUC_SCHED(dev_priv)) dev_priv->pm_guc_events = GEN9_GUC_TO_HOST_INT_EVENT; /* Let's track the enabled rps events */ diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c index 629e4334719c..d46ffe7086bc 100644 --- a/drivers/gpu/drm/i915/i915_params.c +++ b/drivers/gpu/drm/i915/i915_params.c @@ -39,7 +39,7 @@ struct i915_params i915 __read_mostly = { .enable_hangcheck = true, .enable_ppgtt = -1, .enable_psr = -1, - .preliminary_hw_support = IS_ENABLED(CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT), + .alpha_support = IS_ENABLED(CONFIG_DRM_I915_ALPHA_SUPPORT), .disable_power_well = -1, .enable_ips = 1, .fastboot = 0, @@ -145,9 +145,10 @@ MODULE_PARM_DESC(enable_psr, "Enable PSR " "(0=disabled, 1=enabled - link mode chosen per-platform, 2=force link-standby mode, 3=force link-off mode) " "Default: -1 (use per-chip default)"); -module_param_named_unsafe(preliminary_hw_support, i915.preliminary_hw_support, int, 0400); -MODULE_PARM_DESC(preliminary_hw_support, - "Enable preliminary hardware support."); +module_param_named_unsafe(alpha_support, i915.alpha_support, int, 0400); +MODULE_PARM_DESC(alpha_support, + "Enable alpha quality driver support for latest hardware. " + "See also CONFIG_DRM_I915_ALPHA_SUPPORT."); module_param_named_unsafe(disable_power_well, i915.disable_power_well, int, 0400); MODULE_PARM_DESC(disable_power_well, diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index 94efc899c1ef..817ad959941e 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -40,7 +40,7 @@ struct i915_params { int enable_ppgtt; int enable_execlists; int enable_psr; - unsigned int preliminary_hw_support; + unsigned int alpha_support; int disable_power_well; int enable_ips; int invert_brightness; diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 2a419500b81a..fce8e198bc76 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -363,6 +363,7 @@ static const struct intel_device_info intel_broxton_info = { .has_hw_contexts = 1, .has_logical_ring_contexts = 1, .has_guc = 1, + .has_decoupled_mmio = 1, .ddb_size = 512, GEN_DEFAULT_PIPEOFFSETS, IVB_CURSOR_OFFSETS, @@ -439,9 +440,10 @@ static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) struct intel_device_info *intel_info = (struct intel_device_info *) ent->driver_data; - if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) { - DRM_INFO("This hardware requires preliminary hardware support.\n" - "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n"); + if (IS_ALPHA_SUPPORT(intel_info) && !i915.alpha_support) { + DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n" + "See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n" + "to enable support in this kernel version, or check for kernel updates.\n"); return -ENODEV; } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3361d7ffc63e..c70c07a7b586 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7342,6 +7342,13 @@ enum { #define SKL_FUSE_PG1_DIST_STATUS (1<<26) #define SKL_FUSE_PG2_DIST_STATUS (1<<25) +/* Decoupled MMIO register pair for kernel driver */ +#define GEN9_DECOUPLED_REG0_DW0 _MMIO(0xF00) +#define GEN9_DECOUPLED_REG0_DW1 _MMIO(0xF04) +#define GEN9_DECOUPLED_DW1_GO (1<<31) +#define GEN9_DECOUPLED_PD_SHIFT 28 +#define GEN9_DECOUPLED_OP_SHIFT 24 + /* Per-pipe DDI Function Control */ #define _TRANS_DDI_FUNC_CTL_A 0x60400 #define _TRANS_DDI_FUNC_CTL_B 0x61400 diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c index 344cbf39cfa9..b0e1e7ca75da 100644 --- a/drivers/gpu/drm/i915/i915_suspend.c +++ b/drivers/gpu/drm/i915/i915_suspend.c @@ -29,12 +29,10 @@ #include "intel_drv.h" #include "i915_reg.h" -static void i915_save_display(struct drm_device *dev) +static void i915_save_display(struct drm_i915_private *dev_priv) { - struct drm_i915_private *dev_priv = to_i915(dev); - /* Display arbitration control */ - if (INTEL_INFO(dev)->gen <= 4) + if (INTEL_GEN(dev_priv) <= 4) dev_priv->regfile.saveDSPARB = I915_READ(DSPARB); /* save FBC interval */ @@ -42,12 +40,10 @@ static void i915_save_display(struct drm_device *dev) dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL); } -static void i915_restore_display(struct drm_device *dev) +static void i915_restore_display(struct drm_i915_private *dev_priv) { - struct drm_i915_private *dev_priv = to_i915(dev); - /* Display arbitration */ - if (INTEL_INFO(dev)->gen <= 4) + if (INTEL_GEN(dev_priv) <= 4) I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB); /* only restore FBC info on the platform that supports FBC*/ @@ -57,7 +53,7 @@ static void i915_restore_display(struct drm_device *dev) if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv)) I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL); - i915_redisable_vga(dev); + i915_redisable_vga(dev_priv); } int i915_save_state(struct drm_device *dev) @@ -68,14 +64,14 @@ int i915_save_state(struct drm_device *dev) mutex_lock(&dev->struct_mutex); - i915_save_display(dev); + i915_save_display(dev_priv); if (IS_GEN4(dev_priv)) pci_read_config_word(pdev, GCDGMBUS, &dev_priv->regfile.saveGCDGMBUS); /* Cache mode state */ - if (INTEL_INFO(dev)->gen < 7) + if (INTEL_GEN(dev_priv) < 7) dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); /* Memory Arbitration state */ @@ -114,15 +110,15 @@ int i915_restore_state(struct drm_device *dev) mutex_lock(&dev->struct_mutex); - i915_gem_restore_fences(dev); + i915_gem_restore_fences(dev_priv); if (IS_GEN4(dev_priv)) pci_write_config_word(pdev, GCDGMBUS, dev_priv->regfile.saveGCDGMBUS); - i915_restore_display(dev); + i915_restore_display(dev_priv); /* Cache mode state */ - if (INTEL_INFO(dev)->gen < 7) + if (INTEL_GEN(dev_priv) < 7) I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 | 0xffff0000); diff --git a/drivers/gpu/drm/i915/i915_sw_fence.c b/drivers/gpu/drm/i915/i915_sw_fence.c index 95f2f12e0917..147420ccf49c 100644 --- a/drivers/gpu/drm/i915/i915_sw_fence.c +++ b/drivers/gpu/drm/i915/i915_sw_fence.c @@ -116,11 +116,14 @@ static void i915_sw_fence_await(struct i915_sw_fence *fence) WARN_ON(atomic_inc_return(&fence->pending) <= 1); } -void i915_sw_fence_init(struct i915_sw_fence *fence, i915_sw_fence_notify_t fn) +void __i915_sw_fence_init(struct i915_sw_fence *fence, + i915_sw_fence_notify_t fn, + const char *name, + struct lock_class_key *key) { BUG_ON((unsigned long)fn & ~I915_SW_FENCE_MASK); - init_waitqueue_head(&fence->wait); + __init_waitqueue_head(&fence->wait, name, key); kref_init(&fence->kref); atomic_set(&fence->pending, 1); fence->flags = (unsigned long)fn; diff --git a/drivers/gpu/drm/i915/i915_sw_fence.h b/drivers/gpu/drm/i915/i915_sw_fence.h index 707dfc4f0da5..7508d23f823b 100644 --- a/drivers/gpu/drm/i915/i915_sw_fence.h +++ b/drivers/gpu/drm/i915/i915_sw_fence.h @@ -40,7 +40,22 @@ typedef int (*i915_sw_fence_notify_t)(struct i915_sw_fence *, enum i915_sw_fence_notify state); #define __i915_sw_fence_call __aligned(4) -void i915_sw_fence_init(struct i915_sw_fence *fence, i915_sw_fence_notify_t fn); +void __i915_sw_fence_init(struct i915_sw_fence *fence, + i915_sw_fence_notify_t fn, + const char *name, + struct lock_class_key *key); +#ifdef CONFIG_LOCKDEP +#define i915_sw_fence_init(fence, fn) \ +do { \ + static struct lock_class_key __key; \ + \ + __i915_sw_fence_init((fence), (fn), #fence, &__key); \ +} while (0) +#else +#define i915_sw_fence_init(fence, fn) \ + __i915_sw_fence_init((fence), (fn), NULL, NULL) +#endif + void i915_sw_fence_commit(struct i915_sw_fence *fence); int i915_sw_fence_await_sw_fence(struct i915_sw_fence *fence, diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c new file mode 100644 index 000000000000..a792dcb902b5 --- /dev/null +++ b/drivers/gpu/drm/i915/i915_vma.c @@ -0,0 +1,638 @@ +/* + * Copyright © 2016 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +#include "i915_vma.h" + +#include "i915_drv.h" +#include "intel_ringbuffer.h" +#include "intel_frontbuffer.h" + +#include <drm/drm_gem.h> + +static void +i915_vma_retire(struct i915_gem_active *active, + struct drm_i915_gem_request *rq) +{ + const unsigned int idx = rq->engine->id; + struct i915_vma *vma = + container_of(active, struct i915_vma, last_read[idx]); + struct drm_i915_gem_object *obj = vma->obj; + + GEM_BUG_ON(!i915_vma_has_active_engine(vma, idx)); + + i915_vma_clear_active(vma, idx); + if (i915_vma_is_active(vma)) + return; + + list_move_tail(&vma->vm_link, &vma->vm->inactive_list); + if (unlikely(i915_vma_is_closed(vma) && !i915_vma_is_pinned(vma))) + WARN_ON(i915_vma_unbind(vma)); + + GEM_BUG_ON(!i915_gem_object_is_active(obj)); + if (--obj->active_count) + return; + + /* Bump our place on the bound list to keep it roughly in LRU order + * so that we don't steal from recently used but inactive objects + * (unless we are forced to ofc!) + */ + if (obj->bind_count) + list_move_tail(&obj->global_link, &rq->i915->mm.bound_list); + + obj->mm.dirty = true; /* be paranoid */ + + if (i915_gem_object_has_active_reference(obj)) { + i915_gem_object_clear_active_reference(obj); + i915_gem_object_put(obj); + } +} + +static struct i915_vma * +__i915_vma_create(struct drm_i915_gem_object *obj, + struct i915_address_space *vm, + const struct i915_ggtt_view *view) +{ + struct i915_vma *vma; + struct rb_node *rb, **p; + int i; + + GEM_BUG_ON(vm->closed); + + vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL); + if (vma == NULL) + return ERR_PTR(-ENOMEM); + + INIT_LIST_HEAD(&vma->exec_list); + for (i = 0; i < ARRAY_SIZE(vma->last_read); i++) + init_request_active(&vma->last_read[i], i915_vma_retire); + init_request_active(&vma->last_fence, NULL); + list_add(&vma->vm_link, &vm->unbound_list); + vma->vm = vm; + vma->obj = obj; + vma->size = obj->base.size; + + if (view) { + vma->ggtt_view = *view; + if (view->type == I915_GGTT_VIEW_PARTIAL) { + vma->size = view->params.partial.size; + vma->size <<= PAGE_SHIFT; + } else if (view->type == I915_GGTT_VIEW_ROTATED) { + vma->size = + intel_rotation_info_size(&view->params.rotated); + vma->size <<= PAGE_SHIFT; + } + } + + if (i915_is_ggtt(vm)) { + vma->flags |= I915_VMA_GGTT; + list_add(&vma->obj_link, &obj->vma_list); + } else { + i915_ppgtt_get(i915_vm_to_ppgtt(vm)); + list_add_tail(&vma->obj_link, &obj->vma_list); + } + + rb = NULL; + p = &obj->vma_tree.rb_node; + while (*p) { + struct i915_vma *pos; + + rb = *p; + pos = rb_entry(rb, struct i915_vma, obj_node); + if (i915_vma_compare(pos, vm, view) < 0) + p = &rb->rb_right; + else + p = &rb->rb_left; + } + rb_link_node(&vma->obj_node, rb, p); + rb_insert_color(&vma->obj_node, &obj->vma_tree); + + return vma; +} + +struct i915_vma * +i915_vma_create(struct drm_i915_gem_object *obj, + struct i915_address_space *vm, + const struct i915_ggtt_view *view) +{ + lockdep_assert_held(&obj->base.dev->struct_mutex); + GEM_BUG_ON(view && !i915_is_ggtt(vm)); + GEM_BUG_ON(i915_gem_obj_to_vma(obj, vm, view)); + + return __i915_vma_create(obj, vm, view); +} + +/** + * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space. + * @vma: VMA to map + * @cache_level: mapping cache level + * @flags: flags like global or local mapping + * + * DMA addresses are taken from the scatter-gather table of this object (or of + * this VMA in case of non-default GGTT views) and PTE entries set up. + * Note that DMA addresses are also the only part of the SG table we care about. + */ +int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, + u32 flags) +{ + u32 bind_flags; + u32 vma_flags; + int ret; + + if (WARN_ON(flags == 0)) + return -EINVAL; + + bind_flags = 0; + if (flags & PIN_GLOBAL) + bind_flags |= I915_VMA_GLOBAL_BIND; + if (flags & PIN_USER) + bind_flags |= I915_VMA_LOCAL_BIND; + + vma_flags = vma->flags & (I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND); + if (flags & PIN_UPDATE) + bind_flags |= vma_flags; + else + bind_flags &= ~vma_flags; + if (bind_flags == 0) + return 0; + + if (vma_flags == 0 && vma->vm->allocate_va_range) { + trace_i915_va_alloc(vma); + ret = vma->vm->allocate_va_range(vma->vm, + vma->node.start, + vma->node.size); + if (ret) + return ret; + } + + ret = vma->vm->bind_vma(vma, cache_level, bind_flags); + if (ret) + return ret; + + vma->flags |= bind_flags; + return 0; +} + +void __iomem *i915_vma_pin_iomap(struct i915_vma *vma) +{ + void __iomem *ptr; + + /* Access through the GTT requires the device to be awake. */ + assert_rpm_wakelock_held(to_i915(vma->vm->dev)); + + lockdep_assert_held(&vma->vm->dev->struct_mutex); + if (WARN_ON(!i915_vma_is_map_and_fenceable(vma))) + return IO_ERR_PTR(-ENODEV); + + GEM_BUG_ON(!i915_vma_is_ggtt(vma)); + GEM_BUG_ON((vma->flags & I915_VMA_GLOBAL_BIND) == 0); + + ptr = vma->iomap; + if (ptr == NULL) { + ptr = io_mapping_map_wc(&i915_vm_to_ggtt(vma->vm)->mappable, + vma->node.start, + vma->node.size); + if (ptr == NULL) + return IO_ERR_PTR(-ENOMEM); + + vma->iomap = ptr; + } + + __i915_vma_pin(vma); + return ptr; +} + +void i915_vma_unpin_and_release(struct i915_vma **p_vma) +{ + struct i915_vma *vma; + struct drm_i915_gem_object *obj; + + vma = fetch_and_zero(p_vma); + if (!vma) + return; + + obj = vma->obj; + + i915_vma_unpin(vma); + i915_vma_close(vma); + + __i915_gem_object_release_unless_active(obj); +} + +bool +i915_vma_misplaced(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) +{ + if (!drm_mm_node_allocated(&vma->node)) + return false; + + if (vma->node.size < size) + return true; + + if (alignment && vma->node.start & (alignment - 1)) + return true; + + if (flags & PIN_MAPPABLE && !i915_vma_is_map_and_fenceable(vma)) + return true; + + if (flags & PIN_OFFSET_BIAS && + vma->node.start < (flags & PIN_OFFSET_MASK)) + return true; + + if (flags & PIN_OFFSET_FIXED && + vma->node.start != (flags & PIN_OFFSET_MASK)) + return true; + + return false; +} + +void __i915_vma_set_map_and_fenceable(struct i915_vma *vma) +{ + struct drm_i915_gem_object *obj = vma->obj; + struct drm_i915_private *dev_priv = to_i915(obj->base.dev); + bool mappable, fenceable; + u32 fence_size, fence_alignment; + + fence_size = i915_gem_get_ggtt_size(dev_priv, + vma->size, + i915_gem_object_get_tiling(obj)); + fence_alignment = i915_gem_get_ggtt_alignment(dev_priv, + vma->size, + i915_gem_object_get_tiling(obj), + true); + + fenceable = (vma->node.size == fence_size && + (vma->node.start & (fence_alignment - 1)) == 0); + + mappable = (vma->node.start + fence_size <= + dev_priv->ggtt.mappable_end); + + /* + * Explicitly disable for rotated VMA since the display does not + * need the fence and the VMA is not accessible to other users. + */ + if (mappable && fenceable && + vma->ggtt_view.type != I915_GGTT_VIEW_ROTATED) + vma->flags |= I915_VMA_CAN_FENCE; + else + vma->flags &= ~I915_VMA_CAN_FENCE; +} + +bool i915_gem_valid_gtt_space(struct i915_vma *vma, + unsigned long cache_level) +{ + struct drm_mm_node *gtt_space = &vma->node; + struct drm_mm_node *other; + + /* + * On some machines we have to be careful when putting differing types + * of snoopable memory together to avoid the prefetcher crossing memory + * domains and dying. During vm initialisation, we decide whether or not + * these constraints apply and set the drm_mm.color_adjust + * appropriately. + */ + if (vma->vm->mm.color_adjust == NULL) + return true; + + if (!drm_mm_node_allocated(gtt_space)) + return true; + + if (list_empty(>t_space->node_list)) + return true; + + other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); + if (other->allocated && !other->hole_follows && other->color != cache_level) + return false; + + other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); + if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) + return false; + + return true; +} + +/** + * i915_vma_insert - finds a slot for the vma in its address space + * @vma: the vma + * @size: requested size in bytes (can be larger than the VMA) + * @alignment: required alignment + * @flags: mask of PIN_* flags to use + * + * First we try to allocate some free space that meets the requirements for + * the VMA. Failiing that, if the flags permit, it will evict an old VMA, + * preferrably the oldest idle entry to make room for the new VMA. + * + * Returns: + * 0 on success, negative error code otherwise. + */ +static int +i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) +{ + struct drm_i915_private *dev_priv = to_i915(vma->vm->dev); + struct drm_i915_gem_object *obj = vma->obj; + u64 start, end; + int ret; + + GEM_BUG_ON(vma->flags & (I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND)); + GEM_BUG_ON(drm_mm_node_allocated(&vma->node)); + + size = max(size, vma->size); + if (flags & PIN_MAPPABLE) + size = i915_gem_get_ggtt_size(dev_priv, size, + i915_gem_object_get_tiling(obj)); + + alignment = max(max(alignment, vma->display_alignment), + i915_gem_get_ggtt_alignment(dev_priv, size, + i915_gem_object_get_tiling(obj), + flags & PIN_MAPPABLE)); + + start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0; + + end = vma->vm->total; + if (flags & PIN_MAPPABLE) + end = min_t(u64, end, dev_priv->ggtt.mappable_end); + if (flags & PIN_ZONE_4G) + end = min_t(u64, end, (1ULL << 32) - PAGE_SIZE); + + /* If binding the object/GGTT view requires more space than the entire + * aperture has, reject it early before evicting everything in a vain + * attempt to find space. + */ + if (size > end) { + DRM_DEBUG("Attempting to bind an object larger than the aperture: request=%llu [object=%zd] > %s aperture=%llu\n", + size, obj->base.size, + flags & PIN_MAPPABLE ? "mappable" : "total", + end); + return -E2BIG; + } + + ret = i915_gem_object_pin_pages(obj); + if (ret) + return ret; + + if (flags & PIN_OFFSET_FIXED) { + u64 offset = flags & PIN_OFFSET_MASK; + if (offset & (alignment - 1) || offset > end - size) { + ret = -EINVAL; + goto err_unpin; + } + + vma->node.start = offset; + vma->node.size = size; + vma->node.color = obj->cache_level; + ret = drm_mm_reserve_node(&vma->vm->mm, &vma->node); + if (ret) { + ret = i915_gem_evict_for_vma(vma); + if (ret == 0) + ret = drm_mm_reserve_node(&vma->vm->mm, &vma->node); + if (ret) + goto err_unpin; + } + } else { + u32 search_flag, alloc_flag; + + if (flags & PIN_HIGH) { + search_flag = DRM_MM_SEARCH_BELOW; + alloc_flag = DRM_MM_CREATE_TOP; + } else { + search_flag = DRM_MM_SEARCH_DEFAULT; + alloc_flag = DRM_MM_CREATE_DEFAULT; + } + + /* We only allocate in PAGE_SIZE/GTT_PAGE_SIZE (4096) chunks, + * so we know that we always have a minimum alignment of 4096. + * The drm_mm range manager is optimised to return results + * with zero alignment, so where possible use the optimal + * path. + */ + if (alignment <= 4096) + alignment = 0; + +search_free: + ret = drm_mm_insert_node_in_range_generic(&vma->vm->mm, + &vma->node, + size, alignment, + obj->cache_level, + start, end, + search_flag, + alloc_flag); + if (ret) { + ret = i915_gem_evict_something(vma->vm, size, alignment, + obj->cache_level, + start, end, + flags); + if (ret == 0) + goto search_free; + + goto err_unpin; + } + + GEM_BUG_ON(vma->node.start < start); + GEM_BUG_ON(vma->node.start + vma->node.size > end); + } + GEM_BUG_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level)); + + list_move_tail(&obj->global_link, &dev_priv->mm.bound_list); + list_move_tail(&vma->vm_link, &vma->vm->inactive_list); + obj->bind_count++; + GEM_BUG_ON(atomic_read(&obj->mm.pages_pin_count) < obj->bind_count); + + return 0; + +err_unpin: + i915_gem_object_unpin_pages(obj); + return ret; +} + +int __i915_vma_do_pin(struct i915_vma *vma, + u64 size, u64 alignment, u64 flags) +{ + unsigned int bound = vma->flags; + int ret; + + lockdep_assert_held(&vma->vm->dev->struct_mutex); + GEM_BUG_ON((flags & (PIN_GLOBAL | PIN_USER)) == 0); + GEM_BUG_ON((flags & PIN_GLOBAL) && !i915_vma_is_ggtt(vma)); + + if (WARN_ON(bound & I915_VMA_PIN_OVERFLOW)) { + ret = -EBUSY; + goto err; + } + + if ((bound & I915_VMA_BIND_MASK) == 0) { + ret = i915_vma_insert(vma, size, alignment, flags); + if (ret) + goto err; + } + + ret = i915_vma_bind(vma, vma->obj->cache_level, flags); + if (ret) + goto err; + + if ((bound ^ vma->flags) & I915_VMA_GLOBAL_BIND) + __i915_vma_set_map_and_fenceable(vma); + + GEM_BUG_ON(i915_vma_misplaced(vma, size, alignment, flags)); + return 0; + +err: + __i915_vma_unpin(vma); + return ret; +} + +void i915_vma_destroy(struct i915_vma *vma) +{ + GEM_BUG_ON(vma->node.allocated); + GEM_BUG_ON(i915_vma_is_active(vma)); + GEM_BUG_ON(!i915_vma_is_closed(vma)); + GEM_BUG_ON(vma->fence); + + list_del(&vma->vm_link); + if (!i915_vma_is_ggtt(vma)) + i915_ppgtt_put(i915_vm_to_ppgtt(vma->vm)); + + kmem_cache_free(to_i915(vma->obj->base.dev)->vmas, vma); +} + +void i915_vma_close(struct i915_vma *vma) +{ + GEM_BUG_ON(i915_vma_is_closed(vma)); + vma->flags |= I915_VMA_CLOSED; + + list_del(&vma->obj_link); + rb_erase(&vma->obj_node, &vma->obj->vma_tree); + + if (!i915_vma_is_active(vma) && !i915_vma_is_pinned(vma)) + WARN_ON(i915_vma_unbind(vma)); +} + +static void __i915_vma_iounmap(struct i915_vma *vma) +{ + GEM_BUG_ON(i915_vma_is_pinned(vma)); + + if (vma->iomap == NULL) + return; + + io_mapping_unmap(vma->iomap); + vma->iomap = NULL; +} + +int i915_vma_unbind(struct i915_vma *vma) +{ + struct drm_i915_gem_object *obj = vma->obj; + unsigned long active; + int ret; + + lockdep_assert_held(&obj->base.dev->struct_mutex); + + /* First wait upon any activity as retiring the request may + * have side-effects such as unpinning or even unbinding this vma. + */ + active = i915_vma_get_active(vma); + if (active) { + int idx; + + /* When a closed VMA is retired, it is unbound - eek. + * In order to prevent it from being recursively closed, + * take a pin on the vma so that the second unbind is + * aborted. + * + * Even more scary is that the retire callback may free + * the object (last active vma). To prevent the explosion + * we defer the actual object free to a worker that can + * only proceed once it acquires the struct_mutex (which + * we currently hold, therefore it cannot free this object + * before we are finished). + */ + __i915_vma_pin(vma); + + for_each_active(active, idx) { + ret = i915_gem_active_retire(&vma->last_read[idx], + &vma->vm->dev->struct_mutex); + if (ret) + break; + } + + __i915_vma_unpin(vma); + if (ret) + return ret; + + GEM_BUG_ON(i915_vma_is_active(vma)); + } + + if (i915_vma_is_pinned(vma)) + return -EBUSY; + + if (!drm_mm_node_allocated(&vma->node)) + goto destroy; + + GEM_BUG_ON(obj->bind_count == 0); + GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj)); + + if (i915_vma_is_map_and_fenceable(vma)) { + /* release the fence reg _after_ flushing */ + ret = i915_vma_put_fence(vma); + if (ret) + return ret; + + /* Force a pagefault for domain tracking on next user access */ + i915_gem_release_mmap(obj); + + __i915_vma_iounmap(vma); + vma->flags &= ~I915_VMA_CAN_FENCE; + } + + if (likely(!vma->vm->closed)) { + trace_i915_vma_unbind(vma); + vma->vm->unbind_vma(vma); + } + vma->flags &= ~(I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND); + + drm_mm_remove_node(&vma->node); + list_move_tail(&vma->vm_link, &vma->vm->unbound_list); + + if (vma->pages != obj->mm.pages) { + GEM_BUG_ON(!vma->pages); + sg_free_table(vma->pages); + kfree(vma->pages); + } + vma->pages = NULL; + + /* Since the unbound list is global, only move to that list if + * no more VMAs exist. */ + if (--obj->bind_count == 0) + list_move_tail(&obj->global_link, + &to_i915(obj->base.dev)->mm.unbound_list); + + /* And finally now the object is completely decoupled from this vma, + * we can drop its hold on the backing storage and allow it to be + * reaped by the shrinker. + */ + i915_gem_object_unpin_pages(obj); + +destroy: + if (unlikely(i915_vma_is_closed(vma))) + i915_vma_destroy(vma); + + return 0; +} + diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h new file mode 100644 index 000000000000..85446f0b0b3f --- /dev/null +++ b/drivers/gpu/drm/i915/i915_vma.h @@ -0,0 +1,341 @@ +/* + * Copyright © 2016 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +#ifndef __I915_VMA_H__ +#define __I915_VMA_H__ + +#include <linux/io-mapping.h> + +#include <drm/drm_mm.h> + +#include "i915_gem_gtt.h" +#include "i915_gem_fence_reg.h" +#include "i915_gem_object.h" +#include "i915_gem_request.h" + + +enum i915_cache_level; + +/** + * A VMA represents a GEM BO that is bound into an address space. Therefore, a + * VMA's presence cannot be guaranteed before binding, or after unbinding the + * object into/from the address space. + * + * To make things as simple as possible (ie. no refcounting), a VMA's lifetime + * will always be <= an objects lifetime. So object refcounting should cover us. + */ +struct i915_vma { + struct drm_mm_node node; + struct drm_i915_gem_object *obj; + struct i915_address_space *vm; + struct drm_i915_fence_reg *fence; + struct sg_table *pages; + void __iomem *iomap; + u64 size; + u64 display_alignment; + + unsigned int flags; + /** + * How many users have pinned this object in GTT space. The following + * users can each hold at most one reference: pwrite/pread, execbuffer + * (objects are not allowed multiple times for the same batchbuffer), + * and the framebuffer code. When switching/pageflipping, the + * framebuffer code has at most two buffers pinned per crtc. + * + * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 + * bits with absolutely no headroom. So use 4 bits. + */ +#define I915_VMA_PIN_MASK 0xf +#define I915_VMA_PIN_OVERFLOW BIT(5) + + /** Flags and address space this VMA is bound to */ +#define I915_VMA_GLOBAL_BIND BIT(6) +#define I915_VMA_LOCAL_BIND BIT(7) +#define I915_VMA_BIND_MASK (I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND | I915_VMA_PIN_OVERFLOW) + +#define I915_VMA_GGTT BIT(8) +#define I915_VMA_CAN_FENCE BIT(9) +#define I915_VMA_CLOSED BIT(10) + + unsigned int active; + struct i915_gem_active last_read[I915_NUM_ENGINES]; + struct i915_gem_active last_fence; + + /** + * Support different GGTT views into the same object. + * This means there can be multiple VMA mappings per object and per VM. + * i915_ggtt_view_type is used to distinguish between those entries. + * The default one of zero (I915_GGTT_VIEW_NORMAL) is default and also + * assumed in GEM functions which take no ggtt view parameter. + */ + struct i915_ggtt_view ggtt_view; + + /** This object's place on the active/inactive lists */ + struct list_head vm_link; + + struct list_head obj_link; /* Link in the object's VMA list */ + struct rb_node obj_node; + + /** This vma's place in the batchbuffer or on the eviction list */ + struct list_head exec_list; + + /** + * Used for performing relocations during execbuffer insertion. + */ + struct hlist_node exec_node; + unsigned long exec_handle; + struct drm_i915_gem_exec_object2 *exec_entry; +}; + +struct i915_vma * +i915_vma_create(struct drm_i915_gem_object *obj, + struct i915_address_space *vm, + const struct i915_ggtt_view *view); + +void i915_vma_unpin_and_release(struct i915_vma **p_vma); + +static inline bool i915_vma_is_ggtt(const struct i915_vma *vma) +{ + return vma->flags & I915_VMA_GGTT; +} + +static inline bool i915_vma_is_map_and_fenceable(const struct i915_vma *vma) +{ + return vma->flags & I915_VMA_CAN_FENCE; +} + +static inline bool i915_vma_is_closed(const struct i915_vma *vma) +{ + return vma->flags & I915_VMA_CLOSED; +} + +static inline unsigned int i915_vma_get_active(const struct i915_vma *vma) +{ + return vma->active; +} + +static inline bool i915_vma_is_active(const struct i915_vma *vma) +{ + return i915_vma_get_active(vma); +} + +static inline void i915_vma_set_active(struct i915_vma *vma, + unsigned int engine) +{ + vma->active |= BIT(engine); +} + +static inline void i915_vma_clear_active(struct i915_vma *vma, + unsigned int engine) +{ + vma->active &= ~BIT(engine); +} + +static inline bool i915_vma_has_active_engine(const struct i915_vma *vma, + unsigned int engine) +{ + return vma->active & BIT(engine); +} + +static inline u32 i915_ggtt_offset(const struct i915_vma *vma) +{ + GEM_BUG_ON(!i915_vma_is_ggtt(vma)); + GEM_BUG_ON(!vma->node.allocated); + GEM_BUG_ON(upper_32_bits(vma->node.start)); + GEM_BUG_ON(upper_32_bits(vma->node.start + vma->node.size - 1)); + return lower_32_bits(vma->node.start); +} + +static inline struct i915_vma *i915_vma_get(struct i915_vma *vma) +{ + i915_gem_object_get(vma->obj); + return vma; +} + +static inline void i915_vma_put(struct i915_vma *vma) +{ + i915_gem_object_put(vma->obj); +} + +static inline long +i915_vma_compare(struct i915_vma *vma, + struct i915_address_space *vm, + const struct i915_ggtt_view *view) +{ + GEM_BUG_ON(view && !i915_is_ggtt(vm)); + + if (vma->vm != vm) + return vma->vm - vm; + + if (!view) + return vma->ggtt_view.type; + + if (vma->ggtt_view.type != view->type) + return vma->ggtt_view.type - view->type; + + return memcmp(&vma->ggtt_view.params, + &view->params, + sizeof(view->params)); +} + +int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, + u32 flags); +bool i915_gem_valid_gtt_space(struct i915_vma *vma, unsigned long cache_level); +bool +i915_vma_misplaced(struct i915_vma *vma, u64 size, u64 alignment, u64 flags); +void __i915_vma_set_map_and_fenceable(struct i915_vma *vma); +int __must_check i915_vma_unbind(struct i915_vma *vma); +void i915_vma_close(struct i915_vma *vma); +void i915_vma_destroy(struct i915_vma *vma); + +int __i915_vma_do_pin(struct i915_vma *vma, + u64 size, u64 alignment, u64 flags); +static inline int __must_check +i915_vma_pin(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) +{ + BUILD_BUG_ON(PIN_MBZ != I915_VMA_PIN_OVERFLOW); + BUILD_BUG_ON(PIN_GLOBAL != I915_VMA_GLOBAL_BIND); + BUILD_BUG_ON(PIN_USER != I915_VMA_LOCAL_BIND); + + /* Pin early to prevent the shrinker/eviction logic from destroying + * our vma as we insert and bind. + */ + if (likely(((++vma->flags ^ flags) & I915_VMA_BIND_MASK) == 0)) + return 0; + + return __i915_vma_do_pin(vma, size, alignment, flags); +} + +static inline int i915_vma_pin_count(const struct i915_vma *vma) +{ + return vma->flags & I915_VMA_PIN_MASK; +} + +static inline bool i915_vma_is_pinned(const struct i915_vma *vma) +{ + return i915_vma_pin_count(vma); +} + +static inline void __i915_vma_pin(struct i915_vma *vma) +{ + vma->flags++; + GEM_BUG_ON(vma->flags & I915_VMA_PIN_OVERFLOW); +} + +static inline void __i915_vma_unpin(struct i915_vma *vma) +{ + GEM_BUG_ON(!i915_vma_is_pinned(vma)); + vma->flags--; +} + +static inline void i915_vma_unpin(struct i915_vma *vma) +{ + GEM_BUG_ON(!drm_mm_node_allocated(&vma->node)); + __i915_vma_unpin(vma); +} + +/** + * i915_vma_pin_iomap - calls ioremap_wc to map the GGTT VMA via the aperture + * @vma: VMA to iomap + * + * The passed in VMA has to be pinned in the global GTT mappable region. + * An extra pinning of the VMA is acquired for the return iomapping, + * the caller must call i915_vma_unpin_iomap to relinquish the pinning + * after the iomapping is no longer required. + * + * Callers must hold the struct_mutex. + * + * Returns a valid iomapped pointer or ERR_PTR. + */ +void __iomem *i915_vma_pin_iomap(struct i915_vma *vma); +#define IO_ERR_PTR(x) ((void __iomem *)ERR_PTR(x)) + +/** + * i915_vma_unpin_iomap - unpins the mapping returned from i915_vma_iomap + * @vma: VMA to unpin + * + * Unpins the previously iomapped VMA from i915_vma_pin_iomap(). + * + * Callers must hold the struct_mutex. This function is only valid to be + * called on a VMA previously iomapped by the caller with i915_vma_pin_iomap(). + */ +static inline void i915_vma_unpin_iomap(struct i915_vma *vma) +{ + lockdep_assert_held(&vma->vm->dev->struct_mutex); + GEM_BUG_ON(vma->iomap == NULL); + i915_vma_unpin(vma); +} + +static inline struct page *i915_vma_first_page(struct i915_vma *vma) +{ + GEM_BUG_ON(!vma->pages); + return sg_page(vma->pages->sgl); +} + +/** + * i915_vma_pin_fence - pin fencing state + * @vma: vma to pin fencing for + * + * This pins the fencing state (whether tiled or untiled) to make sure the + * vma (and its object) is ready to be used as a scanout target. Fencing + * status must be synchronize first by calling i915_vma_get_fence(): + * + * The resulting fence pin reference must be released again with + * i915_vma_unpin_fence(). + * + * Returns: + * + * True if the vma has a fence, false otherwise. + */ +static inline bool +i915_vma_pin_fence(struct i915_vma *vma) +{ + lockdep_assert_held(&vma->vm->dev->struct_mutex); + if (vma->fence) { + vma->fence->pin_count++; + return true; + } else + return false; +} + +/** + * i915_vma_unpin_fence - unpin fencing state + * @vma: vma to unpin fencing for + * + * This releases the fence pin reference acquired through + * i915_vma_pin_fence. It will handle both objects with and without an + * attached fence correctly, callers do not need to distinguish this. + */ +static inline void +i915_vma_unpin_fence(struct i915_vma *vma) +{ + lockdep_assert_held(&vma->vm->dev->struct_mutex); + if (vma->fence) { + GEM_BUG_ON(vma->fence->pin_count <= 0); + vma->fence->pin_count--; + } +} + +#endif + diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c index 71ab735cb82b..dbe9fb41ae53 100644 --- a/drivers/gpu/drm/i915/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c @@ -106,6 +106,7 @@ intel_plane_destroy_state(struct drm_plane *plane, static int intel_plane_atomic_check(struct drm_plane *plane, struct drm_plane_state *state) { + struct drm_i915_private *dev_priv = to_i915(plane->dev); struct drm_crtc *crtc = state->crtc; struct intel_crtc *intel_crtc; struct intel_crtc_state *crtc_state; @@ -167,6 +168,14 @@ static int intel_plane_atomic_check(struct drm_plane *plane, } } + /* CHV ignores the mirror bit when the rotate bit is set :( */ + if (IS_CHERRYVIEW(dev_priv) && + state->rotation & DRM_ROTATE_180 && + state->rotation & DRM_REFLECT_X) { + DRM_DEBUG_KMS("Cannot rotate and reflect at the same time\n"); + return -EINVAL; + } + intel_state->base.visible = false; ret = intel_plane->check_plane(plane, crtc_state, intel_state); if (ret) diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c index 813fd74d9c8d..1c509f7410f5 100644 --- a/drivers/gpu/drm/i915/intel_audio.c +++ b/drivers/gpu/drm/i915/intel_audio.c @@ -574,23 +574,26 @@ static void ilk_audio_codec_enable(struct drm_connector *connector, /** * intel_audio_codec_enable - Enable the audio codec for HD audio * @intel_encoder: encoder on which to enable audio + * @crtc_state: pointer to the current crtc state. + * @conn_state: pointer to the current connector state. * * The enable sequences may only be performed after enabling the transcoder and * port, and after completed link training. */ -void intel_audio_codec_enable(struct intel_encoder *intel_encoder) +void intel_audio_codec_enable(struct intel_encoder *intel_encoder, + const struct intel_crtc_state *crtc_state, + const struct drm_connector_state *conn_state) { struct drm_encoder *encoder = &intel_encoder->base; - struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); - const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; + const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; struct drm_connector *connector; struct drm_i915_private *dev_priv = to_i915(encoder->dev); struct i915_audio_component *acomp = dev_priv->audio_component; enum port port = intel_encoder->port; - enum pipe pipe = crtc->pipe; + enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe; - connector = drm_select_eld(encoder); - if (!connector) + connector = conn_state->connector; + if (!connector || !connector->eld[0]) return; DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", @@ -601,7 +604,7 @@ void intel_audio_codec_enable(struct intel_encoder *intel_encoder) /* ELD Conn_Type */ connector->eld[5] &= ~(3 << 2); - if (intel_crtc_has_dp_encoder(crtc->config)) + if (intel_crtc_has_dp_encoder(crtc_state)) connector->eld[5] |= (1 << 2); connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2; diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c index 5ab646ef8c9f..7ffab1abc518 100644 --- a/drivers/gpu/drm/i915/intel_bios.c +++ b/drivers/gpu/drm/i915/intel_bios.c @@ -1147,7 +1147,7 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port, if (!child) return; - aux_channel = child->raw[25]; + aux_channel = child->common.aux_channel; ddc_pin = child->common.ddc_pin; is_dvi = child->common.device_type & DEVICE_TYPE_TMDS_DVI_SIGNALING; @@ -1677,7 +1677,8 @@ bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port) return false; } -bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port) +static bool child_dev_is_dp_dual_mode(const union child_device_config *p_child, + enum port port) { static const struct { u16 dp, hdmi; @@ -1691,22 +1692,35 @@ bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum por [PORT_D] = { DVO_PORT_DPD, DVO_PORT_HDMID, }, [PORT_E] = { DVO_PORT_DPE, DVO_PORT_HDMIE, }, }; - int i; if (port == PORT_A || port >= ARRAY_SIZE(port_mapping)) return false; - if (!dev_priv->vbt.child_dev_num) + if ((p_child->common.device_type & DEVICE_TYPE_DP_DUAL_MODE_BITS) != + (DEVICE_TYPE_DP_DUAL_MODE & DEVICE_TYPE_DP_DUAL_MODE_BITS)) return false; + if (p_child->common.dvo_port == port_mapping[port].dp) + return true; + + /* Only accept a HDMI dvo_port as DP++ if it has an AUX channel */ + if (p_child->common.dvo_port == port_mapping[port].hdmi && + p_child->common.aux_channel != 0) + return true; + + return false; +} + +bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, + enum port port) +{ + int i; + for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { const union child_device_config *p_child = &dev_priv->vbt.child_dev[i]; - if ((p_child->common.dvo_port == port_mapping[port].dp || - p_child->common.dvo_port == port_mapping[port].hdmi) && - (p_child->common.device_type & DEVICE_TYPE_DP_DUAL_MODE_BITS) == - (DEVICE_TYPE_DP_DUAL_MODE & DEVICE_TYPE_DP_DUAL_MODE_BITS)) + if (child_dev_is_dp_dual_mode(p_child, port)) return true; } diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c b/drivers/gpu/drm/i915/intel_breadcrumbs.c index c410d3d6465f..c9c46a538edb 100644 --- a/drivers/gpu/drm/i915/intel_breadcrumbs.c +++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c @@ -629,35 +629,28 @@ void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine) cancel_fake_irq(engine); } -unsigned int intel_kick_waiters(struct drm_i915_private *i915) +unsigned int intel_breadcrumbs_busy(struct drm_i915_private *i915) { struct intel_engine_cs *engine; enum intel_engine_id id; unsigned int mask = 0; - /* To avoid the task_struct disappearing beneath us as we wake up - * the process, we must first inspect the task_struct->state under the - * RCU lock, i.e. as we call wake_up_process() we must be holding the - * rcu_read_lock(). - */ - for_each_engine(engine, i915, id) - if (unlikely(intel_engine_wakeup(engine))) - mask |= intel_engine_flag(engine); + for_each_engine(engine, i915, id) { + struct intel_breadcrumbs *b = &engine->breadcrumbs; - return mask; -} + spin_lock_irq(&b->lock); -unsigned int intel_kick_signalers(struct drm_i915_private *i915) -{ - struct intel_engine_cs *engine; - enum intel_engine_id id; - unsigned int mask = 0; + if (b->first_wait) { + wake_up_process(b->first_wait->tsk); + mask |= intel_engine_flag(engine); + } - for_each_engine(engine, i915, id) { - if (unlikely(READ_ONCE(engine->breadcrumbs.first_signal))) { - wake_up_process(engine->breadcrumbs.signaler); + if (b->first_signal) { + wake_up_process(b->signaler); mask |= intel_engine_flag(engine); } + + spin_unlock_irq(&b->lock); } return mask; diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index 445108855275..d81232b79f00 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -95,8 +95,7 @@ static void ctm_mult_by_limited(uint64_t *result, int64_t *input) static void i9xx_load_csc_matrix(struct drm_crtc_state *crtc_state) { struct drm_crtc *crtc = crtc_state->crtc; - struct drm_device *dev = crtc->dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(crtc->dev); struct intel_crtc *intel_crtc = to_intel_crtc(crtc); int i, pipe = intel_crtc->pipe; uint16_t coeffs[9] = { 0, }; @@ -180,7 +179,7 @@ static void i9xx_load_csc_matrix(struct drm_crtc_state *crtc_state) I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); - if (INTEL_INFO(dev)->gen > 6) { + if (INTEL_GEN(dev_priv) > 6) { uint16_t postoff = 0; if (intel_crtc_state->limited_color_range) @@ -345,11 +344,10 @@ static void haswell_load_luts(struct drm_crtc_state *crtc_state) static void broadwell_load_luts(struct drm_crtc_state *state) { struct drm_crtc *crtc = state->crtc; - struct drm_device *dev = crtc->dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(crtc->dev); struct intel_crtc_state *intel_state = to_intel_crtc_state(state); enum pipe pipe = to_intel_crtc(crtc)->pipe; - uint32_t i, lut_size = INTEL_INFO(dev)->color.degamma_lut_size; + uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size; if (crtc_state_is_legacy(state)) { haswell_load_luts(state); @@ -428,8 +426,7 @@ static void broadwell_load_luts(struct drm_crtc_state *state) static void cherryview_load_luts(struct drm_crtc_state *state) { struct drm_crtc *crtc = state->crtc; - struct drm_device *dev = crtc->dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(crtc->dev); enum pipe pipe = to_intel_crtc(crtc)->pipe; struct drm_color_lut *lut; uint32_t i, lut_size; @@ -446,7 +443,7 @@ static void cherryview_load_luts(struct drm_crtc_state *state) if (state->degamma_lut) { lut = (struct drm_color_lut *) state->degamma_lut->data; - lut_size = INTEL_INFO(dev)->color.degamma_lut_size; + lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size; for (i = 0; i < lut_size; i++) { /* Write LUT in U0.14 format. */ word0 = @@ -461,7 +458,7 @@ static void cherryview_load_luts(struct drm_crtc_state *state) if (state->gamma_lut) { lut = (struct drm_color_lut *) state->gamma_lut->data; - lut_size = INTEL_INFO(dev)->color.gamma_lut_size; + lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; for (i = 0; i < lut_size; i++) { /* Write LUT in U0.10 format. */ word0 = @@ -497,12 +494,12 @@ void intel_color_load_luts(struct drm_crtc_state *crtc_state) int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state) { - struct drm_device *dev = crtc->dev; + struct drm_i915_private *dev_priv = to_i915(crtc->dev); size_t gamma_length, degamma_length; - degamma_length = INTEL_INFO(dev)->color.degamma_lut_size * + degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size * sizeof(struct drm_color_lut); - gamma_length = INTEL_INFO(dev)->color.gamma_lut_size * + gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size * sizeof(struct drm_color_lut); /* @@ -529,8 +526,7 @@ int intel_color_check(struct drm_crtc *crtc, void intel_color_init(struct drm_crtc *crtc) { - struct drm_device *dev = crtc->dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(crtc->dev); drm_mode_crtc_set_gamma_size(crtc, 256); @@ -549,10 +545,10 @@ void intel_color_init(struct drm_crtc *crtc) } /* Enable color management support when we have degamma & gamma LUTs. */ - if (INTEL_INFO(dev)->color.degamma_lut_size != 0 && - INTEL_INFO(dev)->color.gamma_lut_size != 0) + if (INTEL_INFO(dev_priv)->color.degamma_lut_size != 0 && + INTEL_INFO(dev_priv)->color.gamma_lut_size != 0) drm_crtc_enable_color_mgmt(crtc, - INTEL_INFO(dev)->color.degamma_lut_size, - true, - INTEL_INFO(dev)->color.gamma_lut_size); + INTEL_INFO(dev_priv)->color.degamma_lut_size, + true, + INTEL_INFO(dev_priv)->color.gamma_lut_size); } diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c index 30eb95b54dcf..86ecec5601d4 100644 --- a/drivers/gpu/drm/i915/intel_crt.c +++ b/drivers/gpu/drm/i915/intel_crt.c @@ -147,14 +147,13 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, int mode) { - struct drm_device *dev = encoder->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_crt *crt = intel_encoder_to_crt(encoder); struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; u32 adpa; - if (INTEL_INFO(dev)->gen >= 5) + if (INTEL_GEN(dev_priv) >= 5) adpa = ADPA_HOTPLUG_BITS; else adpa = 0; @@ -673,8 +672,7 @@ static const struct dmi_system_id intel_spurious_crt_detect[] = { static enum drm_connector_status intel_crt_detect(struct drm_connector *connector, bool force) { - struct drm_device *dev = connector->dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(connector->dev); struct intel_crt *crt = intel_attached_crt(connector); struct intel_encoder *intel_encoder = &crt->base; enum intel_display_power_domain power_domain; @@ -693,7 +691,7 @@ intel_crt_detect(struct drm_connector *connector, bool force) power_domain = intel_display_port_power_domain(intel_encoder); intel_display_power_get(dev_priv, power_domain); - if (I915_HAS_HOTPLUG(dev)) { + if (I915_HAS_HOTPLUG(dev_priv)) { /* We can not rely on the HPD pin always being correctly wired * up, for example many KVM do not pass it through, and so * only trust an assertion that the monitor is connected. @@ -715,7 +713,7 @@ intel_crt_detect(struct drm_connector *connector, bool force) * broken monitor (without edid) to work behind a broken kvm (that fails * to have the right resistors for HP detection) needs to fix this up. * For now just bail out. */ - if (I915_HAS_HOTPLUG(dev) && !i915.load_detect_test) { + if (I915_HAS_HOTPLUG(dev_priv) && !i915.load_detect_test) { status = connector_status_disconnected; goto out; } @@ -731,7 +729,7 @@ intel_crt_detect(struct drm_connector *connector, bool force) if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) { if (intel_crt_detect_ddc(connector)) status = connector_status_connected; - else if (INTEL_INFO(dev)->gen < 4) + else if (INTEL_GEN(dev_priv) < 4) status = intel_crt_load_detect(crt, to_intel_crtc(connector->state->crtc)->pipe); else if (i915.load_detect_test) @@ -793,11 +791,10 @@ static int intel_crt_set_property(struct drm_connector *connector, void intel_crt_reset(struct drm_encoder *encoder) { - struct drm_device *dev = encoder->dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(encoder->dev); struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder)); - if (INTEL_INFO(dev)->gen >= 5) { + if (INTEL_GEN(dev_priv) >= 5) { u32 adpa; adpa = I915_READ(crt->adpa_reg); @@ -915,7 +912,7 @@ void intel_crt_init(struct drm_device *dev) crt->base.disable = intel_disable_crt; } crt->base.enable = intel_enable_crt; - if (I915_HAS_HOTPLUG(dev) && + if (I915_HAS_HOTPLUG(dev_priv) && !dmi_check_system(intel_spurious_crt_detect)) crt->base.hpd_pin = HPD_CRT; if (HAS_DDI(dev_priv)) { @@ -932,7 +929,7 @@ void intel_crt_init(struct drm_device *dev) drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); - if (!I915_HAS_HOTPLUG(dev)) + if (!I915_HAS_HOTPLUG(dev_priv)) intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; /* diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 938ac4dbcb45..10ec9d4b7d45 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1753,8 +1753,7 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder, struct drm_connector_state *old_conn_state) { struct drm_encoder *encoder = &intel_encoder->base; - struct drm_device *dev = encoder->dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(encoder->dev); enum port port = intel_ddi_get_encoder_port(intel_encoder); int type = intel_encoder->type; uint32_t val; @@ -1787,7 +1786,7 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder, if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port))); - else if (INTEL_INFO(dev)->gen < 9) + else if (INTEL_GEN(dev_priv) < 9) I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); if (type == INTEL_OUTPUT_HDMI) { @@ -1837,8 +1836,7 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder, struct drm_encoder *encoder = &intel_encoder->base; struct drm_crtc *crtc = encoder->crtc; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - struct drm_device *dev = encoder->dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(encoder->dev); enum port port = intel_ddi_get_encoder_port(intel_encoder); int type = intel_encoder->type; @@ -1856,7 +1854,7 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder, } else if (type == INTEL_OUTPUT_EDP) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); - if (port == PORT_A && INTEL_INFO(dev)->gen < 9) + if (port == PORT_A && INTEL_GEN(dev_priv) < 9) intel_dp_stop_link_train(intel_dp); intel_edp_backlight_on(intel_dp); @@ -1866,7 +1864,7 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder, if (intel_crtc->config->has_audio) { intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); - intel_audio_codec_enable(intel_encoder); + intel_audio_codec_enable(intel_encoder, pipe_config, conn_state); } } diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index c63ba7f435bb..962aae631f13 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1035,9 +1035,8 @@ enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, return crtc->config->cpu_transcoder; } -static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) +static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe) { - struct drm_i915_private *dev_priv = to_i915(dev); i915_reg_t reg = PIPEDSL(pipe); u32 line1, line2; u32 line_mask; @@ -1072,12 +1071,11 @@ static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) */ static void intel_wait_for_pipe_off(struct intel_crtc *crtc) { - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; enum pipe pipe = crtc->pipe; - if (INTEL_INFO(dev)->gen >= 4) { + if (INTEL_GEN(dev_priv) >= 4) { i915_reg_t reg = PIPECONF(cpu_transcoder); /* Wait for the Pipe State to go off */ @@ -1087,7 +1085,7 @@ static void intel_wait_for_pipe_off(struct intel_crtc *crtc) WARN(1, "pipe_off wait timed out\n"); } else { /* Wait for the display line to settle */ - if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) + if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100)) WARN(1, "pipe_off wait timed out\n"); } } @@ -1293,11 +1291,10 @@ static void assert_plane(struct drm_i915_private *dev_priv, static void assert_planes_disabled(struct drm_i915_private *dev_priv, enum pipe pipe) { - struct drm_device *dev = &dev_priv->drm; int i; /* Primary planes are fixed to pipes on gen4+ */ - if (INTEL_INFO(dev)->gen >= 4) { + if (INTEL_GEN(dev_priv) >= 4) { u32 val = I915_READ(DSPCNTR(pipe)); I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, "plane %c assertion failure, should be disabled but not\n", @@ -1319,10 +1316,9 @@ static void assert_planes_disabled(struct drm_i915_private *dev_priv, static void assert_sprites_disabled(struct drm_i915_private *dev_priv, enum pipe pipe) { - struct drm_device *dev = &dev_priv->drm; int sprite; - if (INTEL_INFO(dev)->gen >= 9) { + if (INTEL_GEN(dev_priv) >= 9) { for_each_sprite(dev_priv, pipe, sprite) { u32 val = I915_READ(PLANE_CTL(pipe, sprite)); I915_STATE_WARN(val & PLANE_CTL_ENABLE, @@ -1336,12 +1332,12 @@ static void assert_sprites_disabled(struct drm_i915_private *dev_priv, "sprite %c assertion failure, should be off on pipe %c but is still active\n", sprite_name(pipe, sprite), pipe_name(pipe)); } - } else if (INTEL_INFO(dev)->gen >= 7) { + } else if (INTEL_GEN(dev_priv) >= 7) { u32 val = I915_READ(SPRCTL(pipe)); I915_STATE_WARN(val & SPRITE_ENABLE, "sprite %c assertion failure, should be off on pipe %c but is still active\n", plane_name(pipe), pipe_name(pipe)); - } else if (INTEL_INFO(dev)->gen >= 5) { + } else if (INTEL_GEN(dev_priv) >= 5) { u32 val = I915_READ(DVSCNTR(pipe)); I915_STATE_WARN(val & DVS_ENABLE, "sprite %c assertion failure, should be off on pipe %c but is still active\n", @@ -1595,12 +1591,12 @@ static void chv_enable_pll(struct intel_crtc *crtc, } } -static int intel_num_dvo_pipes(struct drm_device *dev) +static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv) { struct intel_crtc *crtc; int count = 0; - for_each_intel_crtc(dev, crtc) { + for_each_intel_crtc(&dev_priv->drm, crtc) { count += crtc->base.state->active && intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO); } @@ -1610,8 +1606,7 @@ static int intel_num_dvo_pipes(struct drm_device *dev) static void i9xx_enable_pll(struct intel_crtc *crtc) { - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); i915_reg_t reg = DPLL(crtc->pipe); u32 dpll = crtc->config->dpll_hw_state.dpll; @@ -1622,7 +1617,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc) assert_panel_unlocked(dev_priv, crtc->pipe); /* Enable DVO 2x clock on both PLLs if necessary */ - if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev) > 0) { + if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) { /* * It appears to be important that we don't enable this * for the current pipe before otherwise configuring the @@ -1647,7 +1642,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc) POSTING_READ(reg); udelay(150); - if (INTEL_INFO(dev)->gen >= 4) { + if (INTEL_GEN(dev_priv) >= 4) { I915_WRITE(DPLL_MD(crtc->pipe), crtc->config->dpll_hw_state.dpll_md); } else { @@ -1682,14 +1677,13 @@ static void i9xx_enable_pll(struct intel_crtc *crtc) */ static void i9xx_disable_pll(struct intel_crtc *crtc) { - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; /* Disable DVO 2x clock on both PLLs if necessary */ if (IS_I830(dev_priv) && intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) && - !intel_num_dvo_pipes(dev)) { + !intel_num_dvo_pipes(dev_priv)) { I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); I915_WRITE(DPLL(PIPE_A), @@ -3004,11 +2998,9 @@ static void i9xx_update_primary_plane(struct drm_plane *primary, const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct drm_device *dev = primary->dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(primary->dev); struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); struct drm_framebuffer *fb = plane_state->base.fb; - struct drm_i915_gem_object *obj = intel_fb_obj(fb); int plane = intel_crtc->plane; u32 linear_offset; u32 dspcntr; @@ -3021,7 +3013,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary, dspcntr |= DISPLAY_PLANE_ENABLE; - if (INTEL_INFO(dev)->gen < 4) { + if (INTEL_GEN(dev_priv) < 4) { if (intel_crtc->pipe == PIPE_B) dspcntr |= DISPPLANE_SEL_PIPE_B; @@ -3070,25 +3062,31 @@ static void i9xx_update_primary_plane(struct drm_plane *primary, fb->modifier == I915_FORMAT_MOD_X_TILED) dspcntr |= DISPPLANE_TILED; + if (rotation & DRM_ROTATE_180) + dspcntr |= DISPPLANE_ROTATE_180; + + if (rotation & DRM_REFLECT_X) + dspcntr |= DISPPLANE_MIRROR; + if (IS_G4X(dev_priv)) dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; intel_add_fb_offsets(&x, &y, plane_state, 0); - if (INTEL_INFO(dev)->gen >= 4) + if (INTEL_GEN(dev_priv) >= 4) intel_crtc->dspaddr_offset = intel_compute_tile_offset(&x, &y, plane_state, 0); - if (rotation == DRM_ROTATE_180) { - dspcntr |= DISPPLANE_ROTATE_180; - - x += (crtc_state->pipe_src_w - 1); - y += (crtc_state->pipe_src_h - 1); + if (rotation & DRM_ROTATE_180) { + x += crtc_state->pipe_src_w - 1; + y += crtc_state->pipe_src_h - 1; + } else if (rotation & DRM_REFLECT_X) { + x += crtc_state->pipe_src_w - 1; } linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); - if (INTEL_INFO(dev)->gen < 4) + if (INTEL_GEN(dev_priv) < 4) intel_crtc->dspaddr_offset = linear_offset; intel_crtc->adjusted_x = x; @@ -3097,14 +3095,17 @@ static void i9xx_update_primary_plane(struct drm_plane *primary, I915_WRITE(reg, dspcntr); I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); - if (INTEL_INFO(dev)->gen >= 4) { + if (INTEL_GEN(dev_priv) >= 4) { I915_WRITE(DSPSURF(plane), intel_fb_gtt_offset(fb, rotation) + intel_crtc->dspaddr_offset); I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); I915_WRITE(DSPLINOFF(plane), linear_offset); - } else - I915_WRITE(DSPADDR(plane), i915_gem_object_ggtt_offset(obj, NULL) + linear_offset); + } else { + I915_WRITE(DSPADDR(plane), + intel_fb_gtt_offset(fb, rotation) + + intel_crtc->dspaddr_offset); + } POSTING_READ(reg); } @@ -3172,6 +3173,9 @@ static void ironlake_update_primary_plane(struct drm_plane *primary, if (fb->modifier == I915_FORMAT_MOD_X_TILED) dspcntr |= DISPPLANE_TILED; + if (rotation & DRM_ROTATE_180) + dspcntr |= DISPPLANE_ROTATE_180; + if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; @@ -3180,13 +3184,11 @@ static void ironlake_update_primary_plane(struct drm_plane *primary, intel_crtc->dspaddr_offset = intel_compute_tile_offset(&x, &y, plane_state, 0); - if (rotation == DRM_ROTATE_180) { - dspcntr |= DISPPLANE_ROTATE_180; - - if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) { - x += (crtc_state->pipe_src_w - 1); - y += (crtc_state->pipe_src_h - 1); - } + /* HSW+ does this automagically in hardware */ + if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv) && + rotation & DRM_ROTATE_180) { + x += crtc_state->pipe_src_w - 1; + y += crtc_state->pipe_src_h - 1; } linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); @@ -3376,9 +3378,6 @@ static void skylake_update_primary_plane(struct drm_plane *plane, struct drm_i915_private *dev_priv = to_i915(dev); struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); struct drm_framebuffer *fb = plane_state->base.fb; - const struct skl_wm_values *wm = &dev_priv->wm.skl_results; - const struct skl_plane_wm *p_wm = - &crtc_state->wm.skl.optimal.planes[0]; int pipe = intel_crtc->pipe; u32 plane_ctl; unsigned int rotation = plane_state->base.rotation; @@ -3414,9 +3413,6 @@ static void skylake_update_primary_plane(struct drm_plane *plane, intel_crtc->adjusted_x = src_x; intel_crtc->adjusted_y = src_y; - if (wm->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) - skl_write_plane_wm(intel_crtc, p_wm, &wm->ddb, 0); - I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); I915_WRITE(PLANE_OFFSET(pipe, 0), (src_y << 16) | src_x); I915_WRITE(PLANE_STRIDE(pipe, 0), stride); @@ -3449,18 +3445,8 @@ static void skylake_disable_primary_plane(struct drm_plane *primary, struct drm_device *dev = crtc->dev; struct drm_i915_private *dev_priv = to_i915(dev); struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state); - const struct skl_plane_wm *p_wm = &cstate->wm.skl.optimal.planes[0]; int pipe = intel_crtc->pipe; - /* - * We only populate skl_results on watermark updates, and if the - * plane's visiblity isn't actually changing neither is its watermarks. - */ - if (!crtc->primary->state->visible) - skl_write_plane_wm(intel_crtc, p_wm, - &dev_priv->wm.skl_results.ddb, 0); - I915_WRITE(PLANE_CTL(pipe, 0), 0); I915_WRITE(PLANE_SURF(pipe, 0), 0); POSTING_READ(PLANE_SURF(pipe, 0)); @@ -3510,7 +3496,7 @@ __intel_display_resume(struct drm_device *dev, int i, ret; intel_modeset_setup_hw_state(dev); - i915_redisable_vga(dev); + i915_redisable_vga(to_i915(dev)); if (!state) return 0; @@ -3687,8 +3673,7 @@ static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) static void intel_update_pipe_config(struct intel_crtc *crtc, struct intel_crtc_state *old_crtc_state) { - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc->base.state); @@ -3713,7 +3698,7 @@ static void intel_update_pipe_config(struct intel_crtc *crtc, (pipe_config->pipe_src_h - 1)); /* on skylake this is done by detaching scalers */ - if (INTEL_INFO(dev)->gen >= 9) { + if (INTEL_GEN(dev_priv) >= 9) { skl_detach_scalers(crtc); if (pipe_config->pch_pfit.enabled) @@ -4734,13 +4719,8 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, */ int skl_update_scaler_crtc(struct intel_crtc_state *state) { - struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; - DRM_DEBUG_KMS("Updating scaler for [CRTC:%d:%s] scaler_user index %u.%u\n", - intel_crtc->base.base.id, intel_crtc->base.name, - intel_crtc->pipe, SKL_CRTC_INDEX); - return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, &state->scaler_state.scaler_id, DRM_ROTATE_0, state->pipe_src_w, state->pipe_src_h, @@ -4761,7 +4741,6 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, struct intel_plane_state *plane_state) { - struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); struct intel_plane *intel_plane = to_intel_plane(plane_state->base.plane); struct drm_framebuffer *fb = plane_state->base.fb; @@ -4769,10 +4748,6 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, bool force_detach = !fb || !plane_state->base.visible; - DRM_DEBUG_KMS("Updating scaler for [PLANE:%d:%s] scaler_user index %u.%u\n", - intel_plane->base.base.id, intel_plane->base.name, - intel_crtc->pipe, drm_plane_index(&intel_plane->base)); - ret = skl_update_scaler(crtc_state, force_detach, drm_plane_index(&intel_plane->base), &plane_state->scaler_id, @@ -5096,6 +5071,8 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state) struct drm_plane_state *old_pri_state = drm_atomic_get_existing_plane_state(old_state, primary); bool modeset = needs_modeset(&pipe_config->base); + struct intel_atomic_state *old_intel_state = + to_intel_atomic_state(old_state); if (old_pri_state) { struct intel_plane_state *primary_state = @@ -5163,7 +5140,8 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state) * us to. */ if (dev_priv->display.initial_watermarks != NULL) - dev_priv->display.initial_watermarks(pipe_config); + dev_priv->display.initial_watermarks(old_intel_state, + pipe_config); else if (pipe_config->update_wm_pre) intel_update_watermarks(crtc); } @@ -5319,6 +5297,8 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config, struct drm_i915_private *dev_priv = to_i915(dev); struct intel_crtc *intel_crtc = to_intel_crtc(crtc); int pipe = intel_crtc->pipe; + struct intel_atomic_state *old_intel_state = + to_intel_atomic_state(old_state); if (WARN_ON(intel_crtc->active)) return; @@ -5377,7 +5357,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config, intel_color_load_luts(&pipe_config->base); if (dev_priv->display.initial_watermarks != NULL) - dev_priv->display.initial_watermarks(intel_crtc->config); + dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config); intel_enable_pipe(intel_crtc); if (intel_crtc->config->has_pch_encoder) @@ -5408,11 +5388,12 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, struct drm_atomic_state *old_state) { struct drm_crtc *crtc = pipe_config->base.crtc; - struct drm_device *dev = crtc->dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(crtc->dev); struct intel_crtc *intel_crtc = to_intel_crtc(crtc); int pipe = intel_crtc->pipe, hsw_workaround_pipe; enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; + struct intel_atomic_state *old_intel_state = + to_intel_atomic_state(old_state); if (WARN_ON(intel_crtc->active)) return; @@ -5467,7 +5448,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, if (!transcoder_is_dsi(cpu_transcoder)) intel_ddi_enable_pipe_clock(intel_crtc); - if (INTEL_INFO(dev)->gen >= 9) + if (INTEL_GEN(dev_priv) >= 9) skylake_pfit_enable(intel_crtc); else ironlake_pfit_enable(intel_crtc); @@ -5483,7 +5464,8 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, intel_ddi_enable_transcoder_func(crtc); if (dev_priv->display.initial_watermarks != NULL) - dev_priv->display.initial_watermarks(pipe_config); + dev_priv->display.initial_watermarks(old_intel_state, + pipe_config); else intel_update_watermarks(intel_crtc); @@ -5494,7 +5476,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, if (intel_crtc->config->has_pch_encoder) lpt_pch_enable(crtc); - if (intel_crtc->config->dp_encoder_is_mst) + if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST)) intel_ddi_set_vc_payload_alloc(crtc, true); assert_vblank_disabled(crtc); @@ -5599,8 +5581,7 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state, struct drm_atomic_state *old_state) { struct drm_crtc *crtc = old_crtc_state->base.crtc; - struct drm_device *dev = crtc->dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(crtc->dev); struct intel_crtc *intel_crtc = to_intel_crtc(crtc); enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; @@ -5617,13 +5598,13 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state, if (!transcoder_is_dsi(cpu_transcoder)) intel_disable_pipe(intel_crtc); - if (intel_crtc->config->dp_encoder_is_mst) + if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST)) intel_ddi_set_vc_payload_alloc(crtc, false); if (!transcoder_is_dsi(cpu_transcoder)) intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); - if (INTEL_INFO(dev)->gen >= 9) + if (INTEL_GEN(dev_priv) >= 9) skylake_scaler_disable(intel_crtc); else ironlake_pfit_disable(intel_crtc, false); @@ -7051,7 +7032,7 @@ static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, } } - if (INTEL_INFO(dev)->num_pipes == 2) + if (INTEL_INFO(dev_priv)->num_pipes == 2) return 0; /* Ivybridge 3 pipe is really complicated */ @@ -7192,7 +7173,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; int clock_limit = dev_priv->max_dotclk_freq; - if (INTEL_INFO(dev)->gen < 4) { + if (INTEL_GEN(dev_priv) < 4) { clock_limit = dev_priv->max_cdclk_freq * 9 / 10; /* @@ -7786,12 +7767,11 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, struct intel_link_m_n *m_n, struct intel_link_m_n *m2_n2) { - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); int pipe = crtc->pipe; enum transcoder transcoder = crtc->config->cpu_transcoder; - if (INTEL_INFO(dev)->gen >= 5) { + if (INTEL_GEN(dev_priv) >= 5) { I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); @@ -8245,8 +8225,7 @@ static void i8xx_compute_dpll(struct intel_crtc *crtc, static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) { - struct drm_device *dev = intel_crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); enum pipe pipe = intel_crtc->pipe; enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; @@ -8272,7 +8251,7 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) vsyncshift += adjusted_mode->crtc_htotal; } - if (INTEL_INFO(dev)->gen > 3) + if (INTEL_GEN(dev_priv) > 3) I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); I915_WRITE(HTOTAL(cpu_transcoder), @@ -8395,8 +8374,7 @@ void intel_mode_from_pipe_config(struct drm_display_mode *mode, static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) { - struct drm_device *dev = intel_crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); uint32_t pipeconf; pipeconf = 0; @@ -8432,7 +8410,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) } } - if (HAS_PIPE_CXSR(dev)) { + if (HAS_PIPE_CXSR(dev_priv)) { if (intel_crtc->lowfreq_avail) { DRM_DEBUG_KMS("enabling CxSR downclocking\n"); pipeconf |= PIPECONF_CXSR_DOWNCLOCK; @@ -8442,7 +8420,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) } if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { - if (INTEL_INFO(dev)->gen < 4 || + if (INTEL_GEN(dev_priv) < 4 || intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; else @@ -8650,8 +8628,7 @@ static int vlv_crtc_compute_clock(struct intel_crtc *crtc, static void i9xx_get_pfit_config(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) { - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); uint32_t tmp; if (INTEL_GEN(dev_priv) <= 3 && @@ -8663,7 +8640,7 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc, return; /* Check whether the pfit is attached to our pipe. */ - if (INTEL_INFO(dev)->gen < 4) { + if (INTEL_GEN(dev_priv) < 4) { if (crtc->pipe != PIPE_B) return; } else { @@ -8727,7 +8704,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, fb = &intel_fb->base; - if (INTEL_INFO(dev)->gen >= 4) { + if (INTEL_GEN(dev_priv) >= 4) { if (val & DISPPLANE_TILED) { plane_config->tiling = I915_TILING_X; fb->modifier = I915_FORMAT_MOD_X_TILED; @@ -8739,7 +8716,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, fb->pixel_format = fourcc; fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; - if (INTEL_INFO(dev)->gen >= 4) { + if (INTEL_GEN(dev_priv) >= 4) { if (plane_config->tiling) offset = I915_READ(DSPTILEOFF(plane)); else @@ -8808,8 +8785,7 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc, static bool i9xx_get_pipe_config(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) { - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum intel_display_power_domain power_domain; uint32_t tmp; bool ret; @@ -8848,7 +8824,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, (tmp & PIPECONF_COLOR_RANGE_SELECT)) pipe_config->limited_color_range = true; - if (INTEL_INFO(dev)->gen < 4) + if (INTEL_GEN(dev_priv) < 4) pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; intel_get_pipe_timings(crtc, pipe_config); @@ -8856,7 +8832,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, i9xx_get_pfit_config(crtc, pipe_config); - if (INTEL_INFO(dev)->gen >= 4) { + if (INTEL_GEN(dev_priv) >= 4) { /* No way to read it out on pipes B and C */ if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) tmp = dev_priv->chv_dpll_md[crtc->pipe]; @@ -9653,11 +9629,10 @@ static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, struct intel_link_m_n *m_n, struct intel_link_m_n *m2_n2) { - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; - if (INTEL_INFO(dev)->gen >= 5) { + if (INTEL_GEN(dev_priv) >= 5) { m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) @@ -9669,7 +9644,7 @@ static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, * gen < 8) and if DRRS is supported (to make sure the * registers are not unnecessarily read). */ - if (m2_n2 && INTEL_INFO(dev)->gen < 8 && + if (m2_n2 && INTEL_GEN(dev_priv) < 8 && crtc->config->has_drrs) { m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); @@ -9871,7 +9846,7 @@ ironlake_get_initial_plane_config(struct intel_crtc *crtc, fb = &intel_fb->base; - if (INTEL_INFO(dev)->gen >= 4) { + if (INTEL_GEN(dev_priv) >= 4) { if (val & DISPPLANE_TILED) { plane_config->tiling = I915_TILING_X; fb->modifier = I915_FORMAT_MOD_X_TILED; @@ -10661,8 +10636,7 @@ static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, static void haswell_get_ddi_port_state(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) { - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct intel_shared_dpll *pll; enum port port; uint32_t tmp; @@ -10689,7 +10663,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc, * DDI E. So just check whether this pipe is wired to DDI E and whether * the PCH transcoder is on. */ - if (INTEL_INFO(dev)->gen < 9 && + if (INTEL_GEN(dev_priv) < 9 && (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { pipe_config->has_pch_encoder = true; @@ -10704,8 +10678,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc, static bool haswell_get_pipe_config(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) { - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum intel_display_power_domain power_domain; unsigned long power_domain_mask; bool active; @@ -10738,7 +10711,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, pipe_config->gamma_mode = I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK; - if (INTEL_INFO(dev)->gen >= 9) { + if (INTEL_GEN(dev_priv) >= 9) { skl_init_scalers(dev_priv, crtc, pipe_config); pipe_config->scaler_state.scaler_id = -1; @@ -10748,7 +10721,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { power_domain_mask |= BIT(power_domain); - if (INTEL_INFO(dev)->gen >= 9) + if (INTEL_GEN(dev_priv) >= 9) skylake_get_pfit_config(crtc, pipe_config); else ironlake_get_pfit_config(crtc, pipe_config); @@ -10842,16 +10815,9 @@ static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, struct drm_device *dev = crtc->dev; struct drm_i915_private *dev_priv = to_i915(dev); struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state); - const struct skl_wm_values *wm = &dev_priv->wm.skl_results; - const struct skl_plane_wm *p_wm = - &cstate->wm.skl.optimal.planes[PLANE_CURSOR]; int pipe = intel_crtc->pipe; uint32_t cntl = 0; - if (INTEL_GEN(dev_priv) >= 9 && wm->dirty_pipes & drm_crtc_mask(crtc)) - skl_write_cursor_wm(intel_crtc, p_wm, &wm->ddb); - if (plane_state && plane_state->base.visible) { cntl = MCURSOR_GAMMA_ENABLE; switch (plane_state->base.crtc_w) { @@ -10873,7 +10839,7 @@ static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, if (HAS_DDI(dev_priv)) cntl |= CURSOR_PIPE_CSC_ENABLE; - if (plane_state->base.rotation == DRM_ROTATE_180) + if (plane_state->base.rotation & DRM_ROTATE_180) cntl |= CURSOR_ROTATE_180; } @@ -10919,7 +10885,7 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc, /* ILK+ do this automagically */ if (HAS_GMCH_DISPLAY(dev_priv) && - plane_state->base.rotation == DRM_ROTATE_180) { + plane_state->base.rotation & DRM_ROTATE_180) { base += (plane_state->base.crtc_h * plane_state->base.crtc_w - 1) * 4; } @@ -12062,6 +12028,7 @@ static void intel_mmio_flip_work_func(struct work_struct *w) to_intel_framebuffer(crtc->base.primary->fb); struct drm_i915_gem_object *obj = intel_fb->obj; + i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY); WARN_ON(i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT, NULL) < 0); intel_pipe_update_start(crtc); @@ -12186,7 +12153,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, * TILEOFF/LINOFF registers can't be changed via MI display flips. * Note that pitch changes could also affect these register. */ - if (INTEL_INFO(dev)->gen > 3 && + if (INTEL_GEN(dev_priv) > 3 && (fb->offsets[0] != crtc->primary->fb->offsets[0] || fb->pitches[0] != crtc->primary->fb->pitches[0])) return -EINVAL; @@ -12246,7 +12213,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error); if (i915_reset_in_progress_or_wedged(&dev_priv->gpu_error)) { ret = -EIO; - goto cleanup; + goto unlock; } atomic_inc(&intel_crtc->unpin_work_count); @@ -12261,7 +12228,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, engine = NULL; } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) { engine = dev_priv->engine[BCS]; - } else if (INTEL_INFO(dev)->gen >= 7) { + } else if (INTEL_GEN(dev_priv) >= 7) { engine = i915_gem_object_last_write_engine(obj); if (engine == NULL || engine->id != RCS) engine = dev_priv->engine[BCS]; @@ -12334,6 +12301,7 @@ cleanup_unpin: intel_unpin_fb_obj(fb, crtc->primary->state->rotation); cleanup_pending: atomic_dec(&intel_crtc->unpin_work_count); +unlock: mutex_unlock(&dev->struct_mutex); cleanup: crtc->primary->fb = old_fb; @@ -12518,7 +12486,7 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, /* Pre-gen9 platforms need two-step watermark updates */ if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) && - INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks) + INTEL_GEN(dev_priv) < 9 && dev_priv->display.optimize_watermarks) to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true; if (visible || was_visible) @@ -12623,7 +12591,7 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc, * old state and the new state. We can program these * immediately. */ - ret = dev_priv->display.compute_intermediate_wm(crtc->dev, + ret = dev_priv->display.compute_intermediate_wm(dev, intel_crtc, pipe_config); if (ret) { @@ -12635,7 +12603,7 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc, pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal; } - if (INTEL_INFO(dev)->gen >= 9) { + if (INTEL_GEN(dev_priv) >= 9) { if (mode_changed) ret = skl_update_scaler_crtc(pipe_config); @@ -12748,6 +12716,16 @@ static void intel_dump_crtc_timings(const struct drm_display_mode *mode) mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); } +static inline void +intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id, + unsigned int lane_count, struct intel_link_m_n *m_n) +{ + DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", + id, lane_count, + m_n->gmch_m, m_n->gmch_n, + m_n->link_m, m_n->link_n, m_n->tu); +} + static void intel_dump_pipe_config(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config, const char *context) @@ -12759,61 +12737,58 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc, struct intel_plane_state *state; struct drm_framebuffer *fb; - DRM_DEBUG_KMS("[CRTC:%d:%s]%s config %p for pipe %c\n", - crtc->base.base.id, crtc->base.name, - context, pipe_config, pipe_name(crtc->pipe)); + DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n", + crtc->base.base.id, crtc->base.name, context); - DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder)); - DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", + DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n", + transcoder_name(pipe_config->cpu_transcoder), pipe_config->pipe_bpp, pipe_config->dither); - DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", - pipe_config->has_pch_encoder, - pipe_config->fdi_lanes, - pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, - pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, - pipe_config->fdi_m_n.tu); - DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", - intel_crtc_has_dp_encoder(pipe_config), - pipe_config->lane_count, - pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, - pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, - pipe_config->dp_m_n.tu); - - DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", - intel_crtc_has_dp_encoder(pipe_config), - pipe_config->lane_count, - pipe_config->dp_m2_n2.gmch_m, - pipe_config->dp_m2_n2.gmch_n, - pipe_config->dp_m2_n2.link_m, - pipe_config->dp_m2_n2.link_n, - pipe_config->dp_m2_n2.tu); + + if (pipe_config->has_pch_encoder) + intel_dump_m_n_config(pipe_config, "fdi", + pipe_config->fdi_lanes, + &pipe_config->fdi_m_n); + + if (intel_crtc_has_dp_encoder(pipe_config)) { + intel_dump_m_n_config(pipe_config, "dp m_n", + pipe_config->lane_count, &pipe_config->dp_m_n); + if (pipe_config->has_drrs) + intel_dump_m_n_config(pipe_config, "dp m2_n2", + pipe_config->lane_count, + &pipe_config->dp_m2_n2); + } DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", - pipe_config->has_audio, - pipe_config->has_infoframe); + pipe_config->has_audio, pipe_config->has_infoframe); DRM_DEBUG_KMS("requested mode:\n"); drm_mode_debug_printmodeline(&pipe_config->base.mode); DRM_DEBUG_KMS("adjusted mode:\n"); drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); - DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); - DRM_DEBUG_KMS("pipe src size: %dx%d\n", + DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d\n", + pipe_config->port_clock, pipe_config->pipe_src_w, pipe_config->pipe_src_h); - DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", - crtc->num_scalers, - pipe_config->scaler_state.scaler_users, - pipe_config->scaler_state.scaler_id); - DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", - pipe_config->gmch_pfit.control, - pipe_config->gmch_pfit.pgm_ratios, - pipe_config->gmch_pfit.lvds_border_bits); - DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", - pipe_config->pch_pfit.pos, - pipe_config->pch_pfit.size, - pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); - DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); - DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); + + if (INTEL_GEN(dev_priv) >= 9) + DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", + crtc->num_scalers, + pipe_config->scaler_state.scaler_users, + pipe_config->scaler_state.scaler_id); + + if (HAS_GMCH_DISPLAY(dev_priv)) + DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", + pipe_config->gmch_pfit.control, + pipe_config->gmch_pfit.pgm_ratios, + pipe_config->gmch_pfit.lvds_border_bits); + else + DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", + pipe_config->pch_pfit.pos, + pipe_config->pch_pfit.size, + enableddisabled(pipe_config->pch_pfit.enabled)); + + DRM_DEBUG_KMS("ips: %i, double wide: %i\n", + pipe_config->ips_enabled, pipe_config->double_wide); if (IS_BROXTON(dev_priv)) { DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," @@ -12864,20 +12839,20 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc, continue; } - DRM_DEBUG_KMS("[PLANE:%d:%s] enabled", - plane->base.id, plane->name); - DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = %s", + DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n", + plane->base.id, plane->name, fb->base.id, fb->width, fb->height, drm_get_format_name(fb->pixel_format, &format_name)); - DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n", - state->scaler_id, - state->base.src.x1 >> 16, - state->base.src.y1 >> 16, - drm_rect_width(&state->base.src) >> 16, - drm_rect_height(&state->base.src) >> 16, - state->base.dst.x1, state->base.dst.y1, - drm_rect_width(&state->base.dst), - drm_rect_height(&state->base.dst)); + if (INTEL_GEN(dev_priv) >= 9) + DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n", + state->scaler_id, + state->base.src.x1 >> 16, + state->base.src.y1 >> 16, + drm_rect_width(&state->base.src) >> 16, + drm_rect_height(&state->base.src) >> 16, + state->base.dst.x1, state->base.dst.y1, + drm_rect_width(&state->base.dst), + drm_rect_height(&state->base.dst)); } } @@ -13192,12 +13167,11 @@ intel_compare_link_m_n(const struct intel_link_m_n *m_n, } static bool -intel_pipe_config_compare(struct drm_device *dev, +intel_pipe_config_compare(struct drm_i915_private *dev_priv, struct intel_crtc_state *current_config, struct intel_crtc_state *pipe_config, bool adjust) { - struct drm_i915_private *dev_priv = to_i915(dev); bool ret = true; #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \ @@ -13317,7 +13291,7 @@ intel_pipe_config_compare(struct drm_device *dev, PIPE_CONF_CHECK_I(lane_count); PIPE_CONF_CHECK_X(lane_lat_optim_mask); - if (INTEL_INFO(dev)->gen < 8) { + if (INTEL_GEN(dev_priv) < 8) { PIPE_CONF_CHECK_M_N(dp_m_n); if (current_config->has_drrs) @@ -13366,7 +13340,7 @@ intel_pipe_config_compare(struct drm_device *dev, PIPE_CONF_CHECK_X(gmch_pfit.control); /* pfit ratios are autocomputed by the hw on gen4+ */ - if (INTEL_INFO(dev)->gen < 4) + if (INTEL_GEN(dev_priv) < 4) PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); @@ -13441,8 +13415,7 @@ static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, static void verify_wm_state(struct drm_crtc *crtc, struct drm_crtc_state *new_state) { - struct drm_device *dev = crtc->dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(crtc->dev); struct skl_ddb_allocation hw_ddb, *sw_ddb; struct skl_pipe_wm hw_wm, *sw_wm; struct skl_plane_wm *hw_plane_wm, *sw_plane_wm; @@ -13451,7 +13424,7 @@ static void verify_wm_state(struct drm_crtc *crtc, const enum pipe pipe = intel_crtc->pipe; int plane, level, max_level = ilk_wm_max_level(dev_priv); - if (INTEL_INFO(dev)->gen < 9 || !new_state->active) + if (INTEL_GEN(dev_priv) < 9 || !new_state->active) return; skl_pipe_wm_get_hw_state(crtc, &hw_wm); @@ -13557,11 +13530,15 @@ static void verify_wm_state(struct drm_crtc *crtc, } static void -verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc) +verify_connector_state(struct drm_device *dev, + struct drm_atomic_state *state, + struct drm_crtc *crtc) { struct drm_connector *connector; + struct drm_connector_state *old_conn_state; + int i; - drm_for_each_connector(connector, dev) { + for_each_connector_in_state(state, connector, old_conn_state, i) { struct drm_encoder *encoder = connector->encoder; struct drm_connector_state *state = connector->state; @@ -13676,7 +13653,7 @@ verify_crtc_state(struct drm_crtc *crtc, intel_pipe_config_sanity_check(dev_priv, pipe_config); sw_config = to_intel_crtc_state(crtc->state); - if (!intel_pipe_config_compare(dev, sw_config, + if (!intel_pipe_config_compare(dev_priv, sw_config, pipe_config, false)) { I915_STATE_WARN(1, "pipe state doesn't match!\n"); intel_dump_pipe_config(intel_crtc, pipe_config, @@ -13769,15 +13746,16 @@ verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc, static void intel_modeset_verify_crtc(struct drm_crtc *crtc, - struct drm_crtc_state *old_state, - struct drm_crtc_state *new_state) + struct drm_atomic_state *state, + struct drm_crtc_state *old_state, + struct drm_crtc_state *new_state) { if (!needs_modeset(new_state) && !to_intel_crtc_state(new_state)->update_pipe) return; verify_wm_state(crtc, new_state); - verify_connector_state(crtc->dev, crtc); + verify_connector_state(crtc->dev, state, crtc); verify_crtc_state(crtc, old_state, new_state); verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state); } @@ -13793,10 +13771,11 @@ verify_disabled_dpll_state(struct drm_device *dev) } static void -intel_modeset_verify_disabled(struct drm_device *dev) +intel_modeset_verify_disabled(struct drm_device *dev, + struct drm_atomic_state *state) { verify_encoder_state(dev); - verify_connector_state(dev, NULL); + verify_connector_state(dev, state, NULL); verify_disabled_dpll_state(dev); } @@ -14094,7 +14073,7 @@ static int intel_atomic_check(struct drm_device *dev, } if (i915.fastboot && - intel_pipe_config_compare(dev, + intel_pipe_config_compare(dev_priv, to_intel_crtc_state(crtc->state), pipe_config, true)) { crtc_state->mode_changed = false; @@ -14294,6 +14273,14 @@ static void skl_update_crtcs(struct drm_atomic_state *state, unsigned int updated = 0; bool progress; enum pipe pipe; + int i; + + const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {}; + + for_each_crtc_in_state(state, crtc, old_crtc_state, i) + /* ignore allocations for crtc's that have been turned off. */ + if (crtc->state->active) + entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb; /* * Whenever the number of active pipes changes, we need to make sure we @@ -14302,7 +14289,6 @@ static void skl_update_crtcs(struct drm_atomic_state *state, * cause pipe underruns and other bad stuff. */ do { - int i; progress = false; for_each_crtc_in_state(state, crtc, old_crtc_state, i) { @@ -14313,12 +14299,14 @@ static void skl_update_crtcs(struct drm_atomic_state *state, cstate = to_intel_crtc_state(crtc->state); pipe = intel_crtc->pipe; - if (updated & cmask || !crtc->state->active) + if (updated & cmask || !cstate->base.active) continue; - if (skl_ddb_allocation_overlaps(state, intel_crtc)) + + if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i)) continue; updated |= cmask; + entries[i] = &cstate->wm.skl.ddb; /* * If this is an already active pipe, it's DDB changed, @@ -14327,7 +14315,7 @@ static void skl_update_crtcs(struct drm_atomic_state *state, * new ddb allocation to take effect. */ if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb, - &intel_crtc->hw_ddb) && + &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) && !crtc->state->active_changed && intel_state->wm_results.dirty_pipes != updated) vbl_wait = true; @@ -14358,14 +14346,8 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state) drm_atomic_helper_wait_for_dependencies(state); - if (intel_state->modeset) { - memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, - sizeof(intel_state->min_pixclk)); - dev_priv->active_crtcs = intel_state->active_crtcs; - dev_priv->atomic_cdclk_freq = intel_state->cdclk; - + if (intel_state->modeset) intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); - } for_each_crtc_in_state(state, crtc, old_crtc_state, i) { struct intel_crtc *intel_crtc = to_intel_crtc(crtc); @@ -14398,8 +14380,17 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state) intel_check_cpu_fifo_underruns(dev_priv); intel_check_pch_fifo_underruns(dev_priv); - if (!crtc->state->active) - intel_update_watermarks(intel_crtc); + if (!crtc->state->active) { + /* + * Make sure we don't call initial_watermarks + * for ILK-style watermark updates. + */ + if (dev_priv->display.atomic_update_watermarks) + dev_priv->display.initial_watermarks(intel_state, + to_intel_crtc_state(crtc->state)); + else + intel_update_watermarks(intel_crtc); + } } } @@ -14422,7 +14413,7 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state) if (!intel_can_enable_sagv(state)) intel_disable_sagv(dev_priv); - intel_modeset_verify_disabled(dev); + intel_modeset_verify_disabled(dev, state); } /* Complete the events for pipes that have now been disabled */ @@ -14465,7 +14456,8 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state) intel_cstate = to_intel_crtc_state(crtc->state); if (dev_priv->display.optimize_watermarks) - dev_priv->display.optimize_watermarks(intel_cstate); + dev_priv->display.optimize_watermarks(intel_state, + intel_cstate); } for_each_crtc_in_state(state, crtc, old_crtc_state, i) { @@ -14474,7 +14466,7 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state) if (put_domains[i]) modeset_put_power_domains(dev_priv, put_domains[i]); - intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state); + intel_modeset_verify_crtc(crtc, state, old_crtc_state, crtc->state); } if (intel_state->modeset && intel_can_enable_sagv(state)) @@ -14557,10 +14549,6 @@ static void intel_atomic_track_fbs(struct drm_atomic_state *state) * This function commits a top-level state object that has been validated * with drm_atomic_helper_check(). * - * FIXME: Atomic modeset support for i915 is not yet complete. At the moment - * nonblocking commits are only safe for pure plane updates. Everything else - * should work though. - * * RETURNS * Zero for success or -errno. */ @@ -14572,11 +14560,6 @@ static int intel_atomic_commit(struct drm_device *dev, struct drm_i915_private *dev_priv = to_i915(dev); int ret = 0; - if (intel_state->modeset && nonblock) { - DRM_DEBUG_KMS("nonblocking commit for modeset not yet implemented.\n"); - return -EINVAL; - } - ret = drm_atomic_helper_setup_commit(state, nonblock); if (ret) return ret; @@ -14594,10 +14577,16 @@ static int intel_atomic_commit(struct drm_device *dev, drm_atomic_helper_swap_state(state, true); dev_priv->wm.distrust_bios_wm = false; - dev_priv->wm.skl_results = intel_state->wm_results; intel_shared_dpll_commit(state); intel_atomic_track_fbs(state); + if (intel_state->modeset) { + memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, + sizeof(intel_state->min_pixclk)); + dev_priv->active_crtcs = intel_state->active_crtcs; + dev_priv->atomic_cdclk_freq = intel_state->cdclk; + } + drm_atomic_state_get(state); INIT_WORK(&state->commit_work, nonblock ? intel_atomic_commit_work : NULL); @@ -14720,8 +14709,7 @@ intel_prepare_plane_fb(struct drm_plane *plane, { struct intel_atomic_state *intel_state = to_intel_atomic_state(new_state->state); - struct drm_device *dev = plane->dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(plane->dev); struct drm_framebuffer *fb = new_state->fb; struct drm_i915_gem_object *obj = intel_fb_obj(fb); struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); @@ -14775,10 +14763,12 @@ intel_prepare_plane_fb(struct drm_plane *plane, GFP_KERNEL); if (ret < 0) return ret; + + i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY); } if (plane->type == DRM_PLANE_TYPE_CURSOR && - INTEL_INFO(dev)->cursor_needs_physical) { + INTEL_INFO(dev_priv)->cursor_needs_physical) { int align = IS_I830(dev_priv) ? 16 * 1024 : 256; ret = i915_gem_object_attach_phys(obj, align); if (ret) { @@ -14811,7 +14801,7 @@ void intel_cleanup_plane_fb(struct drm_plane *plane, struct drm_plane_state *old_state) { - struct drm_device *dev = plane->dev; + struct drm_i915_private *dev_priv = to_i915(plane->dev); struct intel_plane_state *old_intel_state; struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb); struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb); @@ -14822,7 +14812,7 @@ intel_cleanup_plane_fb(struct drm_plane *plane, return; if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR || - !INTEL_INFO(dev)->cursor_needs_physical)) + !INTEL_INFO(dev_priv)->cursor_needs_physical)) intel_unpin_fb_obj(old_state->fb, old_state->rotation); } @@ -14900,30 +14890,32 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc, struct intel_crtc *intel_crtc = to_intel_crtc(crtc); struct intel_crtc_state *intel_cstate = to_intel_crtc_state(crtc->state); - struct intel_crtc_state *old_intel_state = + struct intel_crtc_state *old_intel_cstate = to_intel_crtc_state(old_crtc_state); + struct intel_atomic_state *old_intel_state = + to_intel_atomic_state(old_crtc_state->state); bool modeset = needs_modeset(crtc->state); - enum pipe pipe = intel_crtc->pipe; /* Perform vblank evasion around commit operation */ intel_pipe_update_start(intel_crtc); if (modeset) - return; + goto out; if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) { intel_color_set_csc(crtc->state); intel_color_load_luts(crtc->state); } - if (intel_cstate->update_pipe) { - intel_update_pipe_config(intel_crtc, old_intel_state); - } else if (INTEL_GEN(dev_priv) >= 9) { + if (intel_cstate->update_pipe) + intel_update_pipe_config(intel_crtc, old_intel_cstate); + else if (INTEL_GEN(dev_priv) >= 9) skl_detach_scalers(intel_crtc); - I915_WRITE(PIPE_WM_LINETIME(pipe), - intel_cstate->wm.skl.optimal.linetime); - } +out: + if (dev_priv->display.atomic_update_watermarks) + dev_priv->display.atomic_update_watermarks(old_intel_state, + intel_cstate); } static void intel_finish_crtc_commit(struct drm_crtc *crtc, @@ -14989,11 +14981,16 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) state->scaler_id = -1; } primary->pipe = pipe; - primary->plane = pipe; + /* + * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS + * port is hooked to pipe B. Hence we want plane A feeding pipe B. + */ + if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4) + primary->plane = (enum plane) !pipe; + else + primary->plane = (enum plane) pipe; primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); primary->check_plane = intel_check_primary_plane; - if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4) - primary->plane = !pipe; if (INTEL_GEN(dev_priv) >= 9) { intel_primary_formats = skl_primary_formats; @@ -15046,6 +15043,10 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) supported_rotations = DRM_ROTATE_0 | DRM_ROTATE_90 | DRM_ROTATE_180 | DRM_ROTATE_270; + } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { + supported_rotations = + DRM_ROTATE_0 | DRM_ROTATE_180 | + DRM_REFLECT_X; } else if (INTEL_GEN(dev_priv) >= 4) { supported_rotations = DRM_ROTATE_0 | DRM_ROTATE_180; @@ -15147,13 +15148,13 @@ intel_update_cursor_plane(struct drm_plane *plane, { struct drm_crtc *crtc = crtc_state->base.crtc; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - struct drm_device *dev = plane->dev; + struct drm_i915_private *dev_priv = to_i915(plane->dev); struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); uint32_t addr; if (!obj) addr = 0; - else if (!INTEL_INFO(dev)->cursor_needs_physical) + else if (!INTEL_INFO(dev_priv)->cursor_needs_physical) addr = i915_gem_object_ggtt_offset(obj, NULL); else addr = obj->phys_handle->busaddr; @@ -15280,14 +15281,14 @@ static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) struct intel_plane *plane; plane = intel_sprite_plane_create(dev_priv, pipe, sprite); - if (!plane) { + if (IS_ERR(plane)) { ret = PTR_ERR(plane); goto fail; } } cursor = intel_cursor_plane_create(dev_priv, pipe); - if (!cursor) { + if (IS_ERR(cursor)) { ret = PTR_ERR(cursor); goto fail; } @@ -15299,16 +15300,8 @@ static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) if (ret) goto fail; - /* - * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port - * is hooked to pipe B. Hence we want plane A feeding pipe B. - */ intel_crtc->pipe = pipe; - intel_crtc->plane = (enum plane) pipe; - if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4) { - DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); - intel_crtc->plane = !pipe; - } + intel_crtc->plane = primary->plane; intel_crtc->cursor_base = ~0; intel_crtc->cursor_cntl = ~0; @@ -15401,11 +15394,9 @@ static bool has_edp_a(struct drm_i915_private *dev_priv) return true; } -static bool intel_crt_present(struct drm_device *dev) +static bool intel_crt_present(struct drm_i915_private *dev_priv) { - struct drm_i915_private *dev_priv = to_i915(dev); - - if (INTEL_INFO(dev)->gen >= 9) + if (INTEL_GEN(dev_priv) >= 9) return false; if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) @@ -15479,7 +15470,7 @@ static void intel_setup_outputs(struct drm_device *dev) */ intel_lvds_init(dev); - if (intel_crt_present(dev)) + if (intel_crt_present(dev_priv)) intel_crt_init(dev); if (IS_BROXTON(dev_priv)) { @@ -15527,7 +15518,7 @@ static void intel_setup_outputs(struct drm_device *dev) } else if (HAS_PCH_SPLIT(dev_priv)) { int found; - dpd_is_edp = intel_dp_is_edp(dev, PORT_D); + dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D); if (has_edp_a(dev_priv)) intel_dp_init(dev, DP_A, PORT_A); @@ -15570,14 +15561,14 @@ static void intel_setup_outputs(struct drm_device *dev) * trust the port type the VBT declares as we've seen at least * HDMI ports that the VBT claim are DP or eDP. */ - has_edp = intel_dp_is_edp(dev, PORT_B); + has_edp = intel_dp_is_edp(dev_priv, PORT_B); has_port = intel_bios_is_port_present(dev_priv, PORT_B); if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port) has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B); if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) intel_hdmi_init(dev, VLV_HDMIB, PORT_B); - has_edp = intel_dp_is_edp(dev, PORT_C); + has_edp = intel_dp_is_edp(dev_priv, PORT_C); has_port = intel_bios_is_port_present(dev_priv, PORT_C); if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port) has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C); @@ -15634,7 +15625,7 @@ static void intel_setup_outputs(struct drm_device *dev) } else if (IS_GEN2(dev_priv)) intel_dvo_init(dev); - if (SUPPORTS_TV(dev)) + if (SUPPORTS_TV(dev_priv)) intel_tv_init(dev); intel_psr_init(dev); @@ -15689,6 +15680,8 @@ static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, struct drm_i915_gem_object *obj = intel_fb->obj; mutex_lock(&dev->struct_mutex); + if (obj->pin_display && obj->cache_dirty) + i915_gem_clflush_object(obj, true); intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); mutex_unlock(&dev->struct_mutex); @@ -15769,7 +15762,7 @@ static int intel_framebuffer_init(struct drm_device *dev, switch (mode_cmd->modifier[0]) { case I915_FORMAT_MOD_Y_TILED: case I915_FORMAT_MOD_Yf_TILED: - if (INTEL_INFO(dev)->gen < 9) { + if (INTEL_GEN(dev_priv) < 9) { DRM_DEBUG("Unsupported tiling 0x%llx!\n", mode_cmd->modifier[0]); return -EINVAL; @@ -15832,7 +15825,7 @@ static int intel_framebuffer_init(struct drm_device *dev, case DRM_FORMAT_ARGB8888: break; case DRM_FORMAT_XRGB1555: - if (INTEL_INFO(dev)->gen > 3) { + if (INTEL_GEN(dev_priv) > 3) { DRM_DEBUG("unsupported pixel format: %s\n", drm_get_format_name(mode_cmd->pixel_format, &format_name)); return -EINVAL; @@ -15840,7 +15833,7 @@ static int intel_framebuffer_init(struct drm_device *dev, break; case DRM_FORMAT_ABGR8888: if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && - INTEL_INFO(dev)->gen < 9) { + INTEL_GEN(dev_priv) < 9) { DRM_DEBUG("unsupported pixel format: %s\n", drm_get_format_name(mode_cmd->pixel_format, &format_name)); return -EINVAL; @@ -15849,7 +15842,7 @@ static int intel_framebuffer_init(struct drm_device *dev, case DRM_FORMAT_XBGR8888: case DRM_FORMAT_XRGB2101010: case DRM_FORMAT_XBGR2101010: - if (INTEL_INFO(dev)->gen < 4) { + if (INTEL_GEN(dev_priv) < 4) { DRM_DEBUG("unsupported pixel format: %s\n", drm_get_format_name(mode_cmd->pixel_format, &format_name)); return -EINVAL; @@ -15866,7 +15859,7 @@ static int intel_framebuffer_init(struct drm_device *dev, case DRM_FORMAT_UYVY: case DRM_FORMAT_YVYU: case DRM_FORMAT_VYUY: - if (INTEL_INFO(dev)->gen < 5) { + if (INTEL_GEN(dev_priv) < 5) { DRM_DEBUG("unsupported pixel format: %s\n", drm_get_format_name(mode_cmd->pixel_format, &format_name)); return -EINVAL; @@ -16295,9 +16288,8 @@ static void intel_init_quirks(struct drm_device *dev) } /* Disable the VGA plane that we never use */ -static void i915_disable_vga(struct drm_device *dev) +static void i915_disable_vga(struct drm_i915_private *dev_priv) { - struct drm_i915_private *dev_priv = to_i915(dev); struct pci_dev *pdev = dev_priv->drm.pdev; u8 sr1; i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv); @@ -16339,6 +16331,7 @@ static void sanitize_watermarks(struct drm_device *dev) { struct drm_i915_private *dev_priv = to_i915(dev); struct drm_atomic_state *state; + struct intel_atomic_state *intel_state; struct drm_crtc *crtc; struct drm_crtc_state *cstate; struct drm_modeset_acquire_ctx ctx; @@ -16367,12 +16360,14 @@ retry: if (WARN_ON(IS_ERR(state))) goto fail; + intel_state = to_intel_atomic_state(state); + /* * Hardware readout is the only time we don't want to calculate * intermediate watermarks (since we don't trust the current * watermarks). */ - to_intel_atomic_state(state)->skip_intermediate_wm = true; + intel_state->skip_intermediate_wm = true; ret = intel_atomic_check(dev, state); if (ret) { @@ -16396,7 +16391,7 @@ retry: struct intel_crtc_state *cs = to_intel_crtc_state(cstate); cs->wm.need_postvbl_update = true; - dev_priv->display.optimize_watermarks(cs); + dev_priv->display.optimize_watermarks(intel_state, cs); } put_state: @@ -16429,7 +16424,7 @@ int intel_modeset_init(struct drm_device *dev) intel_init_pm(dev_priv); - if (INTEL_INFO(dev)->num_pipes == 0) + if (INTEL_INFO(dev_priv)->num_pipes == 0) return 0; /* @@ -16475,8 +16470,8 @@ int intel_modeset_init(struct drm_device *dev) dev->mode_config.fb_base = ggtt->mappable_base; DRM_DEBUG_KMS("%d display pipe%s available.\n", - INTEL_INFO(dev)->num_pipes, - INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); + INTEL_INFO(dev_priv)->num_pipes, + INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : ""); for_each_pipe(dev_priv, pipe) { int ret; @@ -16497,7 +16492,7 @@ int intel_modeset_init(struct drm_device *dev) intel_update_max_cdclk(dev_priv); /* Just disable it once at startup */ - i915_disable_vga(dev); + i915_disable_vga(dev_priv); intel_setup_outputs(dev); drm_modeset_lock_all(dev); @@ -16564,11 +16559,10 @@ static void intel_enable_pipe_a(struct drm_device *dev) static bool intel_check_plane_mapping(struct intel_crtc *crtc) { - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); u32 val; - if (INTEL_INFO(dev)->num_pipes == 1) + if (INTEL_INFO(dev_priv)->num_pipes == 1) return true; val = I915_READ(DSPCNTR(!crtc->plane)); @@ -16642,7 +16636,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc) /* We need to sanitize the plane -> pipe mapping first because this will * disable the crtc (and hence change the state) if it is wrong. Note * that gen4+ has a fixed plane -> pipe mapping. */ - if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { + if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) { bool plane; DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n", @@ -16744,21 +16738,18 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder) * the crtc fixup. */ } -void i915_redisable_vga_power_on(struct drm_device *dev) +void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv) { - struct drm_i915_private *dev_priv = to_i915(dev); i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv); if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); - i915_disable_vga(dev); + i915_disable_vga(dev_priv); } } -void i915_redisable_vga(struct drm_device *dev) +void i915_redisable_vga(struct drm_i915_private *dev_priv) { - struct drm_i915_private *dev_priv = to_i915(dev); - /* This function can be called both from intel_modeset_setup_hw_state or * at a very early point in our resume sequence, where the power well * structures are not yet restored. Since this function is at a very @@ -16769,7 +16760,7 @@ void i915_redisable_vga(struct drm_device *dev) if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA)) return; - i915_redisable_vga_power_on(dev); + i915_redisable_vga_power_on(dev_priv); intel_display_power_put(dev_priv, POWER_DOMAIN_VGA); } @@ -16841,7 +16832,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n", crtc->base.base.id, crtc->base.name, - crtc->active ? "enabled" : "disabled"); + enableddisabled(crtc->active)); } for (i = 0; i < dev_priv->num_shared_dpll; i++) { @@ -16874,9 +16865,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) } DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", - encoder->base.base.id, - encoder->base.name, - encoder->base.crtc ? "enabled" : "disabled", + encoder->base.base.id, encoder->base.name, + enableddisabled(encoder->base.crtc), pipe_name(pipe)); } @@ -16905,9 +16895,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) connector->base.encoder = NULL; } DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", - connector->base.base.id, - connector->base.name, - connector->base.encoder ? "enabled" : "disabled"); + connector->base.base.id, connector->base.name, + enableddisabled(connector->base.encoder)); } for_each_intel_crtc(dev, crtc) { @@ -17155,10 +17144,9 @@ void intel_connector_attach_encoder(struct intel_connector *connector, /* * set vga decode state - true == enable VGA decode */ -int intel_modeset_vga_set_state(struct drm_device *dev, bool state) +int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state) { - struct drm_i915_private *dev_priv = to_i915(dev); - unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; + unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; u16 gmch_ctrl; if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { @@ -17312,16 +17300,15 @@ intel_display_capture_error_state(struct drm_i915_private *dev_priv) void intel_display_print_error_state(struct drm_i915_error_state_buf *m, - struct drm_device *dev, + struct drm_i915_private *dev_priv, struct intel_display_error_state *error) { - struct drm_i915_private *dev_priv = to_i915(dev); int i; if (!error) return; - err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); + err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes); if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) err_printf(m, "PWR_WELL_CTL2: %08x\n", error->power_well_driver); @@ -17335,13 +17322,13 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m, err_printf(m, "Plane [%d]:\n", i); err_printf(m, " CNTR: %08x\n", error->plane[i].control); err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); - if (INTEL_INFO(dev)->gen <= 3) { + if (INTEL_GEN(dev_priv) <= 3) { err_printf(m, " SIZE: %08x\n", error->plane[i].size); err_printf(m, " POS: %08x\n", error->plane[i].pos); } if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) err_printf(m, " ADDR: %08x\n", error->plane[i].addr); - if (INTEL_INFO(dev)->gen >= 4) { + if (INTEL_GEN(dev_priv) >= 4) { err_printf(m, " SURF: %08x\n", error->plane[i].surface); err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); } diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 9df331b3305b..90283edcafba 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -942,14 +942,14 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, uint8_t *recv, int recv_size) { struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); - struct drm_device *dev = intel_dig_port->base.base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = + to_i915(intel_dig_port->base.base.dev); i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; uint32_t aux_clock_divider; int i, ret, recv_bytes; uint32_t status; int try, clock = 0; - bool has_aux_irq = HAS_AUX_IRQ(dev); + bool has_aux_irq = HAS_AUX_IRQ(dev_priv); bool vdd; pps_lock(intel_dp); @@ -1542,8 +1542,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state) { - struct drm_device *dev = encoder->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); enum port port = dp_to_dig_port(intel_dp)->port; @@ -1578,7 +1577,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, intel_fixed_panel_mode(intel_connector->panel.fixed_mode, adjusted_mode); - if (INTEL_INFO(dev)->gen >= 9) { + if (INTEL_GEN(dev_priv) >= 9) { int ret; ret = skl_update_scaler_crtc(pipe_config); if (ret) @@ -1791,9 +1790,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder, trans_dp &= ~TRANS_DP_ENH_FRAMING; I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp); } else { - if (!HAS_PCH_SPLIT(dev_priv) && !IS_VALLEYVIEW(dev_priv) && - !IS_CHERRYVIEW(dev_priv) && - pipe_config->limited_color_range) + if (IS_G4X(dev_priv) && pipe_config->limited_color_range) intel_dp->DP |= DP_COLOR_RANGE_16_235; if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) @@ -2515,8 +2512,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder, pipe_config->base.adjusted_mode.flags |= flags; - if (!HAS_PCH_SPLIT(dev_priv) && !IS_VALLEYVIEW(dev_priv) && - !IS_CHERRYVIEW(dev_priv) && tmp & DP_COLOR_RANGE_16_235) + if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235) pipe_config->limited_color_range = true; pipe_config->lane_count = @@ -2735,7 +2731,8 @@ static void intel_dp_enable_port(struct intel_dp *intel_dp, } static void intel_enable_dp(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config) + struct intel_crtc_state *pipe_config, + struct drm_connector_state *conn_state) { struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); struct drm_device *dev = encoder->base.dev; @@ -2777,7 +2774,7 @@ static void intel_enable_dp(struct intel_encoder *encoder, if (pipe_config->has_audio) { DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", pipe_name(pipe)); - intel_audio_codec_enable(encoder); + intel_audio_codec_enable(encoder, pipe_config, conn_state); } } @@ -2787,7 +2784,7 @@ static void g4x_enable_dp(struct intel_encoder *encoder, { struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); - intel_enable_dp(encoder, pipe_config); + intel_enable_dp(encoder, pipe_config, conn_state); intel_edp_backlight_on(intel_dp); } @@ -2924,7 +2921,7 @@ static void vlv_pre_enable_dp(struct intel_encoder *encoder, { vlv_phy_pre_encoder_enable(encoder); - intel_enable_dp(encoder, pipe_config); + intel_enable_dp(encoder, pipe_config, conn_state); } static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder, @@ -2942,7 +2939,7 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder, { chv_phy_pre_encoder_enable(encoder); - intel_enable_dp(encoder, pipe_config); + intel_enable_dp(encoder, pipe_config, conn_state); /* Second common lane will stay alive on its own now */ chv_phy_release_cl2_override(encoder); @@ -2979,13 +2976,12 @@ intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_ uint8_t intel_dp_voltage_max(struct intel_dp *intel_dp) { - struct drm_device *dev = intel_dp_to_dev(intel_dp); - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); enum port port = dp_to_dig_port(intel_dp)->port; if (IS_BROXTON(dev_priv)) return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; - else if (INTEL_INFO(dev)->gen >= 9) { + else if (INTEL_GEN(dev_priv) >= 9) { if (dev_priv->vbt.edp.low_vswing && port == PORT_A) return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; @@ -4873,15 +4869,13 @@ put_power: } /* check the VBT to see whether the eDP is on another port */ -bool intel_dp_is_edp(struct drm_device *dev, enum port port) +bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port) { - struct drm_i915_private *dev_priv = to_i915(dev); - /* * eDP not supported on g4x. so bail out early just * for a bit extra safety in case the VBT is bonkers. */ - if (INTEL_INFO(dev)->gen < 5) + if (INTEL_GEN(dev_priv) < 5) return false; if (port == PORT_A) @@ -5483,7 +5477,7 @@ intel_dp_drrs_init(struct intel_connector *intel_connector, INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work); mutex_init(&dev_priv->drrs.mutex); - if (INTEL_INFO(dev)->gen <= 6) { + if (INTEL_GEN(dev_priv) <= 6) { DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); return NULL; } @@ -5657,7 +5651,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, intel_dp->pps_pipe = INVALID_PIPE; /* intel_dp vfuncs */ - if (INTEL_INFO(dev)->gen >= 9) + if (INTEL_GEN(dev_priv) >= 9) intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; @@ -5666,7 +5660,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, else intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider; - if (INTEL_INFO(dev)->gen >= 9) + if (INTEL_GEN(dev_priv) >= 9) intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; else intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; @@ -5678,7 +5672,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, intel_dp->DP = I915_READ(intel_dp->output_reg); intel_dp->attached_connector = intel_connector; - if (intel_dp_is_edp(dev, port)) + if (intel_dp_is_edp(dev_priv, port)) type = DRM_MODE_CONNECTOR_eDP; else type = DRM_MODE_CONNECTOR_DisplayPort; @@ -5742,7 +5736,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, } /* init MST on ports that can support it */ - if (HAS_DP_MST(dev) && !is_edp(intel_dp) && + if (HAS_DP_MST(dev_priv) && !is_edp(intel_dp) && (port == PORT_B || port == PORT_C || port == PORT_D)) intel_dp_mst_encoder_init(intel_dig_port, intel_connector->base.base.id); @@ -5816,7 +5810,7 @@ bool intel_dp_init(struct drm_device *dev, } else { intel_encoder->pre_enable = g4x_pre_enable_dp; intel_encoder->enable = g4x_enable_dp; - if (INTEL_INFO(dev)->gen >= 5) + if (INTEL_GEN(dev_priv) >= 5) intel_encoder->post_disable = ilk_post_disable_dp; } diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c index 3ffbd69e4551..b029d1026a28 100644 --- a/drivers/gpu/drm/i915/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/intel_dp_mst.c @@ -43,7 +43,6 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder, const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; int mst_pbn; - pipe_config->dp_encoder_is_mst = true; pipe_config->has_pch_encoder = false; bpp = 24; /* diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c index 21853a17b6d9..58a756f2f224 100644 --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c @@ -188,13 +188,12 @@ out: void intel_disable_shared_dpll(struct intel_crtc *crtc) { - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct intel_shared_dpll *pll = crtc->config->shared_dpll; unsigned crtc_mask = 1 << drm_crtc_index(&crtc->base); /* PCH only available on ILK+ */ - if (INTEL_INFO(dev)->gen < 5) + if (INTEL_GEN(dev_priv) < 5) return; if (pll == NULL) diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 398195bf6dd1..cd132c216a67 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -294,6 +294,9 @@ struct intel_connector { */ struct intel_encoder *encoder; + /* ACPI device id for ACPI and driver cooperation */ + u32 acpi_device_id; + /* Reads out the current hw, returning true if the connector is enabled * and active (i.e. dpms ON state). */ bool (*get_hw_state)(struct intel_connector *); @@ -652,7 +655,6 @@ struct intel_crtc_state { bool double_wide; - bool dp_encoder_is_mst; int pbn; struct intel_crtc_scaler_state scaler_state; @@ -728,9 +730,6 @@ struct intel_crtc { bool cxsr_allowed; } wm; - /* gen9+: ddb allocation currently being used */ - struct skl_ddb_entry hw_ddb; - int scanline_offset; struct { @@ -1187,7 +1186,9 @@ u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv, /* intel_audio.c */ void intel_init_audio_hooks(struct drm_i915_private *dev_priv); -void intel_audio_codec_enable(struct intel_encoder *encoder); +void intel_audio_codec_enable(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + const struct drm_connector_state *conn_state); void intel_audio_codec_disable(struct intel_encoder *encoder); void i915_audio_component_init(struct drm_i915_private *dev_priv); void i915_audio_component_cleanup(struct drm_i915_private *dev_priv); @@ -1392,7 +1393,7 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc); bool intel_dp_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state); -bool intel_dp_is_edp(struct drm_device *dev, enum port port); +bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port); enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd); void intel_edp_backlight_on(struct intel_dp *intel_dp); @@ -1738,18 +1739,9 @@ int intel_enable_sagv(struct drm_i915_private *dev_priv); int intel_disable_sagv(struct drm_i915_private *dev_priv); bool skl_wm_level_equals(const struct skl_wm_level *l1, const struct skl_wm_level *l2); -bool skl_ddb_allocation_equals(const struct skl_ddb_allocation *old, - const struct skl_ddb_allocation *new, - enum pipe pipe); -bool skl_ddb_allocation_overlaps(struct drm_atomic_state *state, - struct intel_crtc *intel_crtc); -void skl_write_cursor_wm(struct intel_crtc *intel_crtc, - const struct skl_plane_wm *wm, - const struct skl_ddb_allocation *ddb); -void skl_write_plane_wm(struct intel_crtc *intel_crtc, - const struct skl_plane_wm *wm, - const struct skl_ddb_allocation *ddb, - int plane); +bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries, + const struct skl_ddb_entry *ddb, + int ignore); uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config); bool ilk_disable_lp_wm(struct drm_device *dev); int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6); diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c index 9f279a3d0f74..0d8ff0034b88 100644 --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c @@ -774,9 +774,8 @@ struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id) 8); intel_dsi->clk_hs_to_lp_count += extra_byte_count; - DRM_DEBUG_KMS("Eot %s\n", intel_dsi->eotp_pkt ? "enabled" : "disabled"); - DRM_DEBUG_KMS("Clockstop %s\n", intel_dsi->clock_stop ? - "disabled" : "enabled"); + DRM_DEBUG_KMS("Eot %s\n", enableddisabled(intel_dsi->eotp_pkt)); + DRM_DEBUG_KMS("Clockstop %s\n", enableddisabled(!intel_dsi->clock_stop)); DRM_DEBUG_KMS("Mode %s\n", intel_dsi->operation_mode ? "command" : "video"); if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_FRONT_BACK\n"); @@ -795,8 +794,7 @@ struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id) DRM_DEBUG_KMS("LP to HS Clock Count 0x%x\n", intel_dsi->clk_lp_to_hs_count); DRM_DEBUG_KMS("HS to LP Clock Count 0x%x\n", intel_dsi->clk_hs_to_lp_count); DRM_DEBUG_KMS("BTA %s\n", - intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA ? - "disabled" : "enabled"); + enableddisabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA))); /* delays in VBT are in unit of 100us, so need to convert * here in ms diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index 841f8d1e1410..3da4d466e332 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -102,6 +102,9 @@ intel_engine_setup(struct drm_i915_private *dev_priv, engine->mmio_base = info->mmio_base; engine->irq_shift = info->irq_shift; + /* Nothing to do here, execute in order of dependencies */ + engine->schedule = NULL; + dev_priv->engine[id] = engine; return 0; } @@ -236,8 +239,8 @@ static void intel_engine_init_timeline(struct intel_engine_cs *engine) */ void intel_engine_setup_common(struct intel_engine_cs *engine) { - INIT_LIST_HEAD(&engine->execlist_queue); - spin_lock_init(&engine->execlist_lock); + engine->execlist_queue = RB_ROOT; + engine->execlist_first = NULL; intel_engine_init_timeline(engine); intel_engine_init_hangcheck(engine); diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index e230d480c5e6..62f215b12eb5 100644 --- a/drivers/gpu/drm/i915/intel_fbc.c +++ b/drivers/gpu/drm/i915/intel_fbc.c @@ -48,17 +48,17 @@ static inline bool fbc_supported(struct drm_i915_private *dev_priv) static inline bool fbc_on_pipe_a_only(struct drm_i915_private *dev_priv) { - return IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8; + return IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8; } static inline bool fbc_on_plane_a_only(struct drm_i915_private *dev_priv) { - return INTEL_INFO(dev_priv)->gen < 4; + return INTEL_GEN(dev_priv) < 4; } static inline bool no_fbc_on_multiple_pipes(struct drm_i915_private *dev_priv) { - return INTEL_INFO(dev_priv)->gen <= 3; + return INTEL_GEN(dev_priv) <= 3; } /* @@ -351,7 +351,7 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv) static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv) { - if (INTEL_INFO(dev_priv)->gen >= 5) + if (INTEL_GEN(dev_priv) >= 5) return ilk_fbc_is_active(dev_priv); else if (IS_GM45(dev_priv)) return g4x_fbc_is_active(dev_priv); @@ -365,9 +365,9 @@ static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv) fbc->active = true; - if (INTEL_INFO(dev_priv)->gen >= 7) + if (INTEL_GEN(dev_priv) >= 7) gen7_fbc_activate(dev_priv); - else if (INTEL_INFO(dev_priv)->gen >= 5) + else if (INTEL_GEN(dev_priv) >= 5) ilk_fbc_activate(dev_priv); else if (IS_GM45(dev_priv)) g4x_fbc_activate(dev_priv); @@ -381,7 +381,7 @@ static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv) fbc->active = false; - if (INTEL_INFO(dev_priv)->gen >= 5) + if (INTEL_GEN(dev_priv) >= 5) ilk_fbc_deactivate(dev_priv); else if (IS_GM45(dev_priv)) g4x_fbc_deactivate(dev_priv); @@ -561,7 +561,7 @@ again: ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1, 4096, 0, end); - if (ret && INTEL_INFO(dev_priv)->gen <= 4) { + if (ret && INTEL_GEN(dev_priv) <= 4) { return 0; } else if (ret) { compression_threshold <<= 1; @@ -594,7 +594,7 @@ static int intel_fbc_alloc_cfb(struct intel_crtc *crtc) fbc->threshold = ret; - if (INTEL_INFO(dev_priv)->gen >= 5) + if (INTEL_GEN(dev_priv) >= 5) I915_WRITE(ILK_DPFC_CB_BASE, fbc->compressed_fb.start); else if (IS_GM45(dev_priv)) { I915_WRITE(DPFC_CB_BASE, fbc->compressed_fb.start); @@ -708,10 +708,10 @@ static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc) struct intel_fbc *fbc = &dev_priv->fbc; unsigned int effective_w, effective_h, max_w, max_h; - if (INTEL_INFO(dev_priv)->gen >= 8 || IS_HASWELL(dev_priv)) { + if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) { max_w = 4096; max_h = 4096; - } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) { + } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { max_w = 4096; max_h = 2048; } else { @@ -812,7 +812,7 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc) fbc->no_fbc_reason = "framebuffer not tiled or fenced"; return false; } - if (INTEL_INFO(dev_priv)->gen <= 4 && !IS_G4X(dev_priv) && + if (INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv) && cache->plane.rotation != DRM_ROTATE_0) { fbc->no_fbc_reason = "rotation unsupported"; return false; @@ -854,9 +854,8 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc) return true; } -static bool intel_fbc_can_choose(struct intel_crtc *crtc) +static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct intel_fbc *fbc = &dev_priv->fbc; if (intel_vgpu_active(dev_priv)) { @@ -874,16 +873,6 @@ static bool intel_fbc_can_choose(struct intel_crtc *crtc) return false; } - if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A) { - fbc->no_fbc_reason = "no enabled pipes can have FBC"; - return false; - } - - if (fbc_on_plane_a_only(dev_priv) && crtc->plane != PLANE_A) { - fbc->no_fbc_reason = "no enabled planes can have FBC"; - return false; - } - return true; } @@ -1066,23 +1055,19 @@ void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv, struct drm_atomic_state *state) { struct intel_fbc *fbc = &dev_priv->fbc; - struct drm_crtc *crtc; - struct drm_crtc_state *crtc_state; struct drm_plane *plane; struct drm_plane_state *plane_state; - bool fbc_crtc_present = false; - int i, j; + bool crtc_chosen = false; + int i; mutex_lock(&fbc->lock); - for_each_crtc_in_state(state, crtc, crtc_state, i) { - if (fbc->crtc == to_intel_crtc(crtc)) { - fbc_crtc_present = true; - break; - } - } - /* This atomic commit doesn't involve the CRTC currently tied to FBC. */ - if (!fbc_crtc_present && fbc->crtc != NULL) + /* Does this atomic commit involve the CRTC currently tied to FBC? */ + if (fbc->crtc && + !drm_atomic_get_existing_crtc_state(state, &fbc->crtc->base)) + goto out; + + if (!intel_fbc_can_enable(dev_priv)) goto out; /* Simply choose the first CRTC that is compatible and has a visible @@ -1092,25 +1077,29 @@ void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv, for_each_plane_in_state(state, plane, plane_state, i) { struct intel_plane_state *intel_plane_state = to_intel_plane_state(plane_state); + struct intel_crtc_state *intel_crtc_state; + struct intel_crtc *crtc = to_intel_crtc(plane_state->crtc); if (!intel_plane_state->base.visible) continue; - for_each_crtc_in_state(state, crtc, crtc_state, j) { - struct intel_crtc_state *intel_crtc_state = - to_intel_crtc_state(crtc_state); + if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A) + continue; - if (plane_state->crtc != crtc) - continue; + if (fbc_on_plane_a_only(dev_priv) && crtc->plane != PLANE_A) + continue; - if (!intel_fbc_can_choose(to_intel_crtc(crtc))) - break; + intel_crtc_state = to_intel_crtc_state( + drm_atomic_get_existing_crtc_state(state, &crtc->base)); - intel_crtc_state->enable_fbc = true; - goto out; - } + intel_crtc_state->enable_fbc = true; + crtc_chosen = true; + break; } + if (!crtc_chosen) + fbc->no_fbc_reason = "no suitable CRTC for FBC"; + out: mutex_unlock(&fbc->lock); } @@ -1386,7 +1375,7 @@ void intel_fbc_init(struct drm_i915_private *dev_priv) } /* This value was pulled out of someone's hat */ - if (INTEL_INFO(dev_priv)->gen <= 4 && !IS_GM45(dev_priv)) + if (INTEL_GEN(dev_priv) <= 4 && !IS_GM45(dev_priv)) I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT); /* We still don't have any sort of hardware state readout for FBC, so diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c index 977e39722894..beb08982dc0b 100644 --- a/drivers/gpu/drm/i915/intel_fbdev.c +++ b/drivers/gpu/drm/i915/intel_fbdev.c @@ -356,7 +356,7 @@ static bool intel_fb_initial_config(struct drm_fb_helper *fb_helper, struct drm_fb_offset *offsets, bool *enabled, int width, int height) { - struct drm_device *dev = fb_helper->dev; + struct drm_i915_private *dev_priv = to_i915(fb_helper->dev); unsigned long conn_configured, mask; unsigned int count = min(fb_helper->connector_count, BITS_PER_LONG); int i, j; @@ -509,7 +509,7 @@ retry: * fbdev helper library. */ if (num_connectors_enabled != num_connectors_detected && - num_connectors_enabled < INTEL_INFO(dev)->num_pipes) { + num_connectors_enabled < INTEL_INFO(dev_priv)->num_pipes) { DRM_DEBUG_KMS("fallback: Not all outputs enabled\n"); DRM_DEBUG_KMS("Enabled: %i, detected: %i\n", num_connectors_enabled, num_connectors_detected); @@ -697,11 +697,11 @@ static void intel_fbdev_suspend_worker(struct work_struct *work) int intel_fbdev_init(struct drm_device *dev) { - struct intel_fbdev *ifbdev; struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_fbdev *ifbdev; int ret; - if (WARN_ON(INTEL_INFO(dev)->num_pipes == 0)) + if (WARN_ON(INTEL_INFO(dev_priv)->num_pipes == 0)) return -ENODEV; ifbdev = kzalloc(sizeof(struct intel_fbdev), GFP_KERNEL); @@ -714,7 +714,7 @@ int intel_fbdev_init(struct drm_device *dev) ifbdev->preferred_bpp = 32; ret = drm_fb_helper_init(dev, &ifbdev->helper, - INTEL_INFO(dev)->num_pipes, 4); + INTEL_INFO(dev_priv)->num_pipes, 4); if (ret) { kfree(ifbdev); return ret; diff --git a/drivers/gpu/drm/i915/intel_frontbuffer.h b/drivers/gpu/drm/i915/intel_frontbuffer.h index 76ceb539f9f0..7bab41218cf7 100644 --- a/drivers/gpu/drm/i915/intel_frontbuffer.h +++ b/drivers/gpu/drm/i915/intel_frontbuffer.h @@ -53,16 +53,17 @@ void __intel_fb_obj_flush(struct drm_i915_gem_object *obj, * until the rendering completes or a flip on this frontbuffer plane is * scheduled. */ -static inline void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj, +static inline bool intel_fb_obj_invalidate(struct drm_i915_gem_object *obj, enum fb_op_origin origin) { unsigned int frontbuffer_bits; frontbuffer_bits = atomic_read(&obj->frontbuffer_bits); if (!frontbuffer_bits) - return; + return false; __intel_fb_obj_invalidate(obj, origin, frontbuffer_bits); + return true; } /** diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c index 1aa85236b788..34d6ad2cf7c1 100644 --- a/drivers/gpu/drm/i915/intel_guc_loader.c +++ b/drivers/gpu/drm/i915/intel_guc_loader.c @@ -566,7 +566,7 @@ fail: ret = 0; } - if (err == 0 && !HAS_GUC_UCODE(dev)) + if (err == 0 && !HAS_GUC_UCODE(dev_priv)) ; /* Don't mention the GuC! */ else if (err == 0) DRM_INFO("GuC firmware load skipped\n"); @@ -725,18 +725,18 @@ void intel_guc_init(struct drm_device *dev) struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; const char *fw_path; - if (!HAS_GUC(dev)) { + if (!HAS_GUC(dev_priv)) { i915.enable_guc_loading = 0; i915.enable_guc_submission = 0; } else { /* A negative value means "use platform default" */ if (i915.enable_guc_loading < 0) - i915.enable_guc_loading = HAS_GUC_UCODE(dev); + i915.enable_guc_loading = HAS_GUC_UCODE(dev_priv); if (i915.enable_guc_submission < 0) - i915.enable_guc_submission = HAS_GUC_SCHED(dev); + i915.enable_guc_submission = HAS_GUC_SCHED(dev_priv); } - if (!HAS_GUC_UCODE(dev)) { + if (!HAS_GUC_UCODE(dev_priv)) { fw_path = NULL; } else if (IS_SKYLAKE(dev_priv)) { fw_path = I915_SKL_GUC_UCODE; diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 35ada4e1c6cf..fb88e32e25a3 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -975,14 +975,16 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder, pipe_config->lane_count = 4; } -static void intel_enable_hdmi_audio(struct intel_encoder *encoder) +static void intel_enable_hdmi_audio(struct intel_encoder *encoder, + struct intel_crtc_state *pipe_config, + struct drm_connector_state *conn_state) { struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); WARN_ON(!crtc->config->has_hdmi_sink); DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", pipe_name(crtc->pipe)); - intel_audio_codec_enable(encoder); + intel_audio_codec_enable(encoder, pipe_config, conn_state); } static void g4x_enable_hdmi(struct intel_encoder *encoder, @@ -991,21 +993,20 @@ static void g4x_enable_hdmi(struct intel_encoder *encoder, { struct drm_device *dev = encoder->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); - struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); u32 temp; temp = I915_READ(intel_hdmi->hdmi_reg); temp |= SDVO_ENABLE; - if (crtc->config->has_audio) + if (pipe_config->has_audio) temp |= SDVO_AUDIO_ENABLE; I915_WRITE(intel_hdmi->hdmi_reg, temp); POSTING_READ(intel_hdmi->hdmi_reg); - if (crtc->config->has_audio) - intel_enable_hdmi_audio(encoder); + if (pipe_config->has_audio) + intel_enable_hdmi_audio(encoder, pipe_config, conn_state); } static void ibx_enable_hdmi(struct intel_encoder *encoder, @@ -1040,8 +1041,8 @@ static void ibx_enable_hdmi(struct intel_encoder *encoder, * FIXME: BSpec says this should be done at the end of * of the modeset sequence, so not sure if this isn't too soon. */ - if (crtc->config->pipe_bpp > 24 && - crtc->config->pixel_multiplier > 1) { + if (pipe_config->pipe_bpp > 24 && + pipe_config->pixel_multiplier > 1) { I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); POSTING_READ(intel_hdmi->hdmi_reg); @@ -1055,8 +1056,8 @@ static void ibx_enable_hdmi(struct intel_encoder *encoder, POSTING_READ(intel_hdmi->hdmi_reg); } - if (crtc->config->has_audio) - intel_enable_hdmi_audio(encoder); + if (pipe_config->has_audio) + intel_enable_hdmi_audio(encoder, pipe_config, conn_state); } static void cpt_enable_hdmi(struct intel_encoder *encoder, @@ -1073,7 +1074,7 @@ static void cpt_enable_hdmi(struct intel_encoder *encoder, temp = I915_READ(intel_hdmi->hdmi_reg); temp |= SDVO_ENABLE; - if (crtc->config->has_audio) + if (pipe_config->has_audio) temp |= SDVO_AUDIO_ENABLE; /* @@ -1086,7 +1087,7 @@ static void cpt_enable_hdmi(struct intel_encoder *encoder, * 4. enable HDMI clock gating */ - if (crtc->config->pipe_bpp > 24) { + if (pipe_config->pipe_bpp > 24) { I915_WRITE(TRANS_CHICKEN1(pipe), I915_READ(TRANS_CHICKEN1(pipe)) | TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); @@ -1098,7 +1099,7 @@ static void cpt_enable_hdmi(struct intel_encoder *encoder, I915_WRITE(intel_hdmi->hdmi_reg, temp); POSTING_READ(intel_hdmi->hdmi_reg); - if (crtc->config->pipe_bpp > 24) { + if (pipe_config->pipe_bpp > 24) { temp &= ~SDVO_COLOR_FORMAT_MASK; temp |= HDMI_COLOR_FORMAT_12bpc; @@ -1110,8 +1111,8 @@ static void cpt_enable_hdmi(struct intel_encoder *encoder, ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); } - if (crtc->config->has_audio) - intel_enable_hdmi_audio(encoder); + if (pipe_config->has_audio) + intel_enable_hdmi_audio(encoder, pipe_config, conn_state); } static void vlv_enable_hdmi(struct intel_encoder *encoder, @@ -1178,9 +1179,7 @@ static void g4x_disable_hdmi(struct intel_encoder *encoder, struct intel_crtc_state *old_crtc_state, struct drm_connector_state *old_conn_state) { - struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); - - if (crtc->config->has_audio) + if (old_crtc_state->has_audio) intel_audio_codec_disable(encoder); intel_disable_hdmi(encoder, old_crtc_state, old_conn_state); @@ -1190,9 +1189,7 @@ static void pch_disable_hdmi(struct intel_encoder *encoder, struct intel_crtc_state *old_crtc_state, struct drm_connector_state *old_conn_state) { - struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); - - if (crtc->config->has_audio) + if (old_crtc_state->has_audio) intel_audio_codec_disable(encoder); } @@ -1645,13 +1642,12 @@ static void intel_hdmi_pre_enable(struct intel_encoder *encoder, struct drm_connector_state *conn_state) { struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); - struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); - const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; + const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; intel_hdmi_prepare(encoder); intel_hdmi->set_infoframes(&encoder->base, - intel_crtc->config->has_hdmi_sink, + pipe_config->has_hdmi_sink, adjusted_mode); } @@ -1663,9 +1659,7 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder, struct intel_hdmi *intel_hdmi = &dport->hdmi; struct drm_device *dev = encoder->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); - struct intel_crtc *intel_crtc = - to_intel_crtc(encoder->base.crtc); - const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; + const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; vlv_phy_pre_encoder_enable(encoder); @@ -1674,7 +1668,7 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder, 0x2b247878); intel_hdmi->set_infoframes(&encoder->base, - intel_crtc->config->has_hdmi_sink, + pipe_config->has_hdmi_sink, adjusted_mode); g4x_enable_hdmi(encoder, pipe_config, conn_state); diff --git a/drivers/gpu/drm/i915/intel_hotplug.c b/drivers/gpu/drm/i915/intel_hotplug.c index 334d47b5811a..3d546c019de0 100644 --- a/drivers/gpu/drm/i915/intel_hotplug.c +++ b/drivers/gpu/drm/i915/intel_hotplug.c @@ -501,7 +501,7 @@ static void i915_hpd_poll_init_work(struct work_struct *work) if (intel_connector->mst_port) continue; - if (!connector->polled && I915_HAS_HOTPLUG(dev) && + if (!connector->polled && I915_HAS_HOTPLUG(dev_priv) && intel_connector->encoder->hpd_pin > HPD_NONE) { connector->polled = enabled ? DRM_CONNECTOR_POLL_CONNECT | diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index dde04b7643b1..0a09024d6ca3 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -432,8 +432,10 @@ static bool can_merge_ctx(const struct i915_gem_context *prev, static void execlists_dequeue(struct intel_engine_cs *engine) { - struct drm_i915_gem_request *cursor, *last; + struct drm_i915_gem_request *last; struct execlist_port *port = engine->execlist_port; + unsigned long flags; + struct rb_node *rb; bool submit = false; last = port->request; @@ -469,8 +471,12 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * and context switches) submission. */ - spin_lock(&engine->execlist_lock); - list_for_each_entry(cursor, &engine->execlist_queue, execlist_link) { + spin_lock_irqsave(&engine->timeline->lock, flags); + rb = engine->execlist_first; + while (rb) { + struct drm_i915_gem_request *cursor = + rb_entry(rb, typeof(*cursor), priotree.node); + /* Can we combine this request with the current port? It has to * be the same context/ringbuffer and not have any exceptions * (e.g. GVT saying never to combine contexts). @@ -493,7 +499,8 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * context (even though a different request) to * the second port. */ - if (ctx_single_port_submission(cursor->ctx)) + if (ctx_single_port_submission(last->ctx) || + ctx_single_port_submission(cursor->ctx)) break; GEM_BUG_ON(last->ctx == cursor->ctx); @@ -501,17 +508,30 @@ static void execlists_dequeue(struct intel_engine_cs *engine) i915_gem_request_assign(&port->request, last); port++; } + + rb = rb_next(rb); + rb_erase(&cursor->priotree.node, &engine->execlist_queue); + RB_CLEAR_NODE(&cursor->priotree.node); + cursor->priotree.priority = INT_MAX; + + /* We keep the previous context alive until we retire the + * following request. This ensures that any the context object + * is still pinned for any residual writes the HW makes into it + * on the context switch into the next object following the + * breadcrumb. Otherwise, we may retire the context too early. + */ + cursor->previous_context = engine->last_context; + engine->last_context = cursor->ctx; + + __i915_gem_request_submit(cursor); last = cursor; submit = true; } if (submit) { - /* Decouple all the requests submitted from the queue */ - engine->execlist_queue.next = &cursor->execlist_link; - cursor->execlist_link.prev = &engine->execlist_queue; - i915_gem_request_assign(&port->request, last); + engine->execlist_first = rb; } - spin_unlock(&engine->execlist_lock); + spin_unlock_irqrestore(&engine->timeline->lock, flags); if (submit) execlists_submit_ports(engine); @@ -614,27 +634,147 @@ static void intel_lrc_irq_handler(unsigned long data) intel_uncore_forcewake_put(dev_priv, engine->fw_domains); } +static bool insert_request(struct i915_priotree *pt, struct rb_root *root) +{ + struct rb_node **p, *rb; + bool first = true; + + /* most positive priority is scheduled first, equal priorities fifo */ + rb = NULL; + p = &root->rb_node; + while (*p) { + struct i915_priotree *pos; + + rb = *p; + pos = rb_entry(rb, typeof(*pos), node); + if (pt->priority > pos->priority) { + p = &rb->rb_left; + } else { + p = &rb->rb_right; + first = false; + } + } + rb_link_node(&pt->node, rb, p); + rb_insert_color(&pt->node, root); + + return first; +} + static void execlists_submit_request(struct drm_i915_gem_request *request) { struct intel_engine_cs *engine = request->engine; unsigned long flags; - spin_lock_irqsave(&engine->execlist_lock, flags); + /* Will be called from irq-context when using foreign fences. */ + spin_lock_irqsave(&engine->timeline->lock, flags); - /* We keep the previous context alive until we retire the following - * request. This ensures that any the context object is still pinned - * for any residual writes the HW makes into it on the context switch - * into the next object following the breadcrumb. Otherwise, we may - * retire the context too early. - */ - request->previous_context = engine->last_context; - engine->last_context = request->ctx; - - list_add_tail(&request->execlist_link, &engine->execlist_queue); + if (insert_request(&request->priotree, &engine->execlist_queue)) + engine->execlist_first = &request->priotree.node; if (execlists_elsp_idle(engine)) tasklet_hi_schedule(&engine->irq_tasklet); - spin_unlock_irqrestore(&engine->execlist_lock, flags); + spin_unlock_irqrestore(&engine->timeline->lock, flags); +} + +static struct intel_engine_cs * +pt_lock_engine(struct i915_priotree *pt, struct intel_engine_cs *locked) +{ + struct intel_engine_cs *engine; + + engine = container_of(pt, + struct drm_i915_gem_request, + priotree)->engine; + if (engine != locked) { + if (locked) + spin_unlock_irq(&locked->timeline->lock); + spin_lock_irq(&engine->timeline->lock); + } + + return engine; +} + +static void execlists_schedule(struct drm_i915_gem_request *request, int prio) +{ + static DEFINE_MUTEX(lock); + struct intel_engine_cs *engine = NULL; + struct i915_dependency *dep, *p; + struct i915_dependency stack; + LIST_HEAD(dfs); + + if (prio <= READ_ONCE(request->priotree.priority)) + return; + + /* Need global lock to use the temporary link inside i915_dependency */ + mutex_lock(&lock); + + stack.signaler = &request->priotree; + list_add(&stack.dfs_link, &dfs); + + /* Recursively bump all dependent priorities to match the new request. + * + * A naive approach would be to use recursion: + * static void update_priorities(struct i915_priotree *pt, prio) { + * list_for_each_entry(dep, &pt->signalers_list, signal_link) + * update_priorities(dep->signal, prio) + * insert_request(pt); + * } + * but that may have unlimited recursion depth and so runs a very + * real risk of overunning the kernel stack. Instead, we build + * a flat list of all dependencies starting with the current request. + * As we walk the list of dependencies, we add all of its dependencies + * to the end of the list (this may include an already visited + * request) and continue to walk onwards onto the new dependencies. The + * end result is a topological list of requests in reverse order, the + * last element in the list is the request we must execute first. + */ + list_for_each_entry_safe(dep, p, &dfs, dfs_link) { + struct i915_priotree *pt = dep->signaler; + + list_for_each_entry(p, &pt->signalers_list, signal_link) + if (prio > READ_ONCE(p->signaler->priority)) + list_move_tail(&p->dfs_link, &dfs); + + p = list_next_entry(dep, dfs_link); + if (!RB_EMPTY_NODE(&pt->node)) + continue; + + engine = pt_lock_engine(pt, engine); + + /* If it is not already in the rbtree, we can update the + * priority inplace and skip over it (and its dependencies) + * if it is referenced *again* as we descend the dfs. + */ + if (prio > pt->priority && RB_EMPTY_NODE(&pt->node)) { + pt->priority = prio; + list_del_init(&dep->dfs_link); + } + } + + /* Fifo and depth-first replacement ensure our deps execute before us */ + list_for_each_entry_safe_reverse(dep, p, &dfs, dfs_link) { + struct i915_priotree *pt = dep->signaler; + + INIT_LIST_HEAD(&dep->dfs_link); + + engine = pt_lock_engine(pt, engine); + + if (prio <= pt->priority) + continue; + + GEM_BUG_ON(RB_EMPTY_NODE(&pt->node)); + + pt->priority = prio; + rb_erase(&pt->node, &engine->execlist_queue); + if (insert_request(pt, &engine->execlist_queue)) + engine->execlist_first = &pt->node; + } + + if (engine) + spin_unlock_irq(&engine->timeline->lock); + + mutex_unlock(&lock); + + /* XXX Do we need to preempt to make room for us and our deps? */ } int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request) @@ -1673,8 +1813,10 @@ void intel_execlists_enable_submission(struct drm_i915_private *dev_priv) struct intel_engine_cs *engine; enum intel_engine_id id; - for_each_engine(engine, dev_priv, id) + for_each_engine(engine, dev_priv, id) { engine->submit_request = execlists_submit_request; + engine->schedule = execlists_schedule; + } } static void @@ -1687,6 +1829,7 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine) engine->emit_breadcrumb = gen8_emit_breadcrumb; engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_sz; engine->submit_request = execlists_submit_request; + engine->schedule = execlists_schedule; engine->irq_enable = gen8_logical_ring_enable_irq; engine->irq_disable = gen8_logical_ring_disable_irq; diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c index de7b3e6ed477..d12ef0047d49 100644 --- a/drivers/gpu/drm/i915/intel_lvds.c +++ b/drivers/gpu/drm/i915/intel_lvds.c @@ -122,8 +122,7 @@ out: static void intel_lvds_get_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) { - struct drm_device *dev = encoder->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); u32 tmp, flags = 0; @@ -139,12 +138,12 @@ static void intel_lvds_get_config(struct intel_encoder *encoder, pipe_config->base.adjusted_mode.flags |= flags; - if (INTEL_INFO(dev)->gen < 5) + if (INTEL_GEN(dev_priv) < 5) pipe_config->gmch_pfit.lvds_border_bits = tmp & LVDS_BORDER_ENABLE; /* gen2/3 store dither state in pfit control, needs to match */ - if (INTEL_INFO(dev)->gen < 4) { + if (INTEL_GEN(dev_priv) < 4) { tmp = I915_READ(PFIT_CONTROL); pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE; diff --git a/drivers/gpu/drm/i915/intel_opregion.c b/drivers/gpu/drm/i915/intel_opregion.c index 7acbbbf97833..f4429f67a4e3 100644 --- a/drivers/gpu/drm/i915/intel_opregion.c +++ b/drivers/gpu/drm/i915/intel_opregion.c @@ -642,24 +642,6 @@ static struct notifier_block intel_opregion_notifier = { * (version 3) */ -static u32 get_did(struct intel_opregion *opregion, int i) -{ - u32 did; - - if (i < ARRAY_SIZE(opregion->acpi->didl)) { - did = opregion->acpi->didl[i]; - } else { - i -= ARRAY_SIZE(opregion->acpi->didl); - - if (WARN_ON(i >= ARRAY_SIZE(opregion->acpi->did2))) - return 0; - - did = opregion->acpi->did2[i]; - } - - return did; -} - static void set_did(struct intel_opregion *opregion, int i, u32 val) { if (i < ARRAY_SIZE(opregion->acpi->didl)) { @@ -674,11 +656,11 @@ static void set_did(struct intel_opregion *opregion, int i, u32 val) } } -static u32 acpi_display_type(struct drm_connector *connector) +static u32 acpi_display_type(struct intel_connector *connector) { u32 display_type; - switch (connector->connector_type) { + switch (connector->base.connector_type) { case DRM_MODE_CONNECTOR_VGA: case DRM_MODE_CONNECTOR_DVIA: display_type = ACPI_DISPLAY_TYPE_VGA; @@ -707,7 +689,7 @@ static u32 acpi_display_type(struct drm_connector *connector) display_type = ACPI_DISPLAY_TYPE_OTHER; break; default: - MISSING_CASE(connector->connector_type); + MISSING_CASE(connector->base.connector_type); display_type = ACPI_DISPLAY_TYPE_OTHER; break; } @@ -718,34 +700,9 @@ static u32 acpi_display_type(struct drm_connector *connector) static void intel_didl_outputs(struct drm_i915_private *dev_priv) { struct intel_opregion *opregion = &dev_priv->opregion; - struct pci_dev *pdev = dev_priv->drm.pdev; - struct drm_connector *connector; - acpi_handle handle; - struct acpi_device *acpi_dev, *acpi_cdev, *acpi_video_bus = NULL; - unsigned long long device_id; - acpi_status status; - u32 temp, max_outputs; - int i = 0; - - handle = ACPI_HANDLE(&pdev->dev); - if (!handle || acpi_bus_get_device(handle, &acpi_dev)) - return; - - if (acpi_is_video_device(handle)) - acpi_video_bus = acpi_dev; - else { - list_for_each_entry(acpi_cdev, &acpi_dev->children, node) { - if (acpi_is_video_device(acpi_cdev->handle)) { - acpi_video_bus = acpi_cdev; - break; - } - } - } - - if (!acpi_video_bus) { - DRM_DEBUG_KMS("No ACPI video bus found\n"); - return; - } + struct intel_connector *connector; + int i = 0, max_outputs; + int display_index[16] = {}; /* * In theory, did2, the extended didl, gets added at opregion version @@ -757,64 +714,58 @@ static void intel_didl_outputs(struct drm_i915_private *dev_priv) max_outputs = ARRAY_SIZE(opregion->acpi->didl) + ARRAY_SIZE(opregion->acpi->did2); - list_for_each_entry(acpi_cdev, &acpi_video_bus->children, node) { - if (i >= max_outputs) { - DRM_DEBUG_KMS("More than %u outputs detected via ACPI\n", - max_outputs); - return; - } - status = acpi_evaluate_integer(acpi_cdev->handle, "_ADR", - NULL, &device_id); - if (ACPI_SUCCESS(status)) { - if (!device_id) - goto blind_set; - set_did(opregion, i++, (u32)(device_id & 0x0f0f)); - } + for_each_intel_connector(&dev_priv->drm, connector) { + u32 device_id, type; + + device_id = acpi_display_type(connector); + + /* Use display type specific display index. */ + type = (device_id & ACPI_DISPLAY_TYPE_MASK) + >> ACPI_DISPLAY_TYPE_SHIFT; + device_id |= display_index[type]++ << ACPI_DISPLAY_INDEX_SHIFT; + + connector->acpi_device_id = device_id; + if (i < max_outputs) + set_did(opregion, i, device_id); + i++; } -end: DRM_DEBUG_KMS("%d outputs detected\n", i); + if (i > max_outputs) + DRM_ERROR("More than %d outputs in connector list\n", + max_outputs); + /* If fewer than max outputs, the list must be null terminated */ if (i < max_outputs) set_did(opregion, i, 0); - return; - -blind_set: - i = 0; - list_for_each_entry(connector, - &dev_priv->drm.mode_config.connector_list, head) { - int display_type = acpi_display_type(connector); - - if (i >= max_outputs) { - DRM_DEBUG_KMS("More than %u outputs in connector list\n", - max_outputs); - return; - } - - temp = get_did(opregion, i); - set_did(opregion, i, temp | (1 << 31) | display_type | i); - i++; - } - goto end; } static void intel_setup_cadls(struct drm_i915_private *dev_priv) { struct intel_opregion *opregion = &dev_priv->opregion; + struct intel_connector *connector; int i = 0; - u32 disp_id; - - /* Initialize the CADL field by duplicating the DIDL values. - * Technically, this is not always correct as display outputs may exist, - * but not active. This initialization is necessary for some Clevo - * laptops that check this field before processing the brightness and - * display switching hotkeys. Just like DIDL, CADL is NULL-terminated if - * there are less than eight devices. */ - do { - disp_id = get_did(opregion, i); - opregion->acpi->cadl[i] = disp_id; - } while (++i < 8 && disp_id != 0); + + /* + * Initialize the CADL field from the connector device ids. This is + * essentially the same as copying from the DIDL. Technically, this is + * not always correct as display outputs may exist, but not active. This + * initialization is necessary for some Clevo laptops that check this + * field before processing the brightness and display switching hotkeys. + * + * Note that internal panels should be at the front of the connector + * list already, ensuring they're not left out. + */ + for_each_intel_connector(&dev_priv->drm, connector) { + if (i >= ARRAY_SIZE(opregion->acpi->cadl)) + break; + opregion->acpi->cadl[i++] = connector->acpi_device_id; + } + + /* If fewer than 8 active devices, the list must be null terminated */ + if (i < ARRAY_SIZE(opregion->acpi->cadl)) + opregion->acpi->cadl[i] = 0; } void intel_opregion_register(struct drm_i915_private *dev_priv) diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c index be4b4d546fd9..08ab6d762ca4 100644 --- a/drivers/gpu/drm/i915/intel_panel.c +++ b/drivers/gpu/drm/i915/intel_panel.c @@ -304,7 +304,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc, struct intel_crtc_state *pipe_config, int fitting_mode) { - struct drm_device *dev = intel_crtc->base.dev; + struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0; struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; @@ -325,7 +325,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc, break; case DRM_MODE_SCALE_ASPECT: /* Scale but preserve the aspect ratio */ - if (INTEL_INFO(dev)->gen >= 4) + if (INTEL_GEN(dev_priv) >= 4) i965_scale_aspect(pipe_config, &pfit_control); else i9xx_scale_aspect(pipe_config, &pfit_control, @@ -339,7 +339,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc, if (pipe_config->pipe_src_h != adjusted_mode->crtc_vdisplay || pipe_config->pipe_src_w != adjusted_mode->crtc_hdisplay) { pfit_control |= PFIT_ENABLE; - if (INTEL_INFO(dev)->gen >= 4) + if (INTEL_GEN(dev_priv) >= 4) pfit_control |= PFIT_SCALING_AUTO; else pfit_control |= (VERT_AUTO_SCALE | @@ -355,7 +355,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc, /* 965+ wants fuzzy fitting */ /* FIXME: handle multiple panels by failing gracefully */ - if (INTEL_INFO(dev)->gen >= 4) + if (INTEL_GEN(dev_priv) >= 4) pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) | PFIT_FILTER_FUZZY); @@ -366,7 +366,7 @@ out: } /* Make sure pre-965 set dither correctly for 18bpp panels. */ - if (INTEL_INFO(dev)->gen < 4 && pipe_config->pipe_bpp == 18) + if (INTEL_GEN(dev_priv) < 4 && pipe_config->pipe_bpp == 18) pfit_control |= PANEL_8TO6_DITHER_ENABLE; pipe_config->gmch_pfit.control = pfit_control; @@ -1722,7 +1722,7 @@ int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe) DRM_DEBUG_KMS("Connector %s backlight initialized, %s, brightness %u/%u\n", connector->name, - panel->backlight.enabled ? "enabled" : "disabled", + enableddisabled(panel->backlight.enabled), panel->backlight.level, panel->backlight.max); return 0; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 6f516491a172..bbb1eaf1e6db 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -347,8 +347,7 @@ void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable) return; } - DRM_DEBUG_KMS("memory self-refresh is %s\n", - enable ? "enabled" : "disabled"); + DRM_DEBUG_KMS("memory self-refresh is %s\n", enableddisabled(enable)); } @@ -1061,7 +1060,8 @@ static void vlv_invert_wms(struct intel_crtc *crtc) for (level = 0; level < wm_state->num_levels; level++) { struct drm_device *dev = crtc->base.dev; - const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1; + const int sr_fifo_size = + INTEL_INFO(to_i915(dev))->num_pipes * 512 - 1; struct intel_plane *plane; wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane; @@ -1091,15 +1091,16 @@ static void vlv_invert_wms(struct intel_crtc *crtc) static void vlv_compute_wm(struct intel_crtc *crtc) { struct drm_device *dev = crtc->base.dev; + struct drm_i915_private *dev_priv = to_i915(dev); struct vlv_wm_state *wm_state = &crtc->wm_state; struct intel_plane *plane; - int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1; + int sr_fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1; int level; memset(wm_state, 0, sizeof(*wm_state)); wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed; - wm_state->num_levels = to_i915(dev)->wm.max_level + 1; + wm_state->num_levels = dev_priv->wm.max_level + 1; wm_state->num_active_planes = 0; @@ -1179,7 +1180,7 @@ static void vlv_compute_wm(struct intel_crtc *crtc) } /* clear any (partially) filled invalid levels */ - for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) { + for (level = wm_state->num_levels; level < dev_priv->wm.max_level + 1; level++) { memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level])); memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level])); } @@ -1861,23 +1862,25 @@ static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate, return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp); } -static unsigned int ilk_display_fifo_size(const struct drm_device *dev) +static unsigned int +ilk_display_fifo_size(const struct drm_i915_private *dev_priv) { - if (INTEL_INFO(dev)->gen >= 8) + if (INTEL_GEN(dev_priv) >= 8) return 3072; - else if (INTEL_INFO(dev)->gen >= 7) + else if (INTEL_GEN(dev_priv) >= 7) return 768; else return 512; } -static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev, - int level, bool is_sprite) +static unsigned int +ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv, + int level, bool is_sprite) { - if (INTEL_INFO(dev)->gen >= 8) + if (INTEL_GEN(dev_priv) >= 8) /* BDW primary/sprite plane watermarks */ return level == 0 ? 255 : 2047; - else if (INTEL_INFO(dev)->gen >= 7) + else if (INTEL_GEN(dev_priv) >= 7) /* IVB/HSW primary/sprite plane watermarks */ return level == 0 ? 127 : 1023; else if (!is_sprite) @@ -1888,18 +1891,18 @@ static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev, return level == 0 ? 63 : 255; } -static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev, - int level) +static unsigned int +ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level) { - if (INTEL_INFO(dev)->gen >= 7) + if (INTEL_GEN(dev_priv) >= 7) return level == 0 ? 63 : 255; else return level == 0 ? 31 : 63; } -static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev) +static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv) { - if (INTEL_INFO(dev)->gen >= 8) + if (INTEL_GEN(dev_priv) >= 8) return 31; else return 15; @@ -1912,7 +1915,8 @@ static unsigned int ilk_plane_wm_max(const struct drm_device *dev, enum intel_ddb_partitioning ddb_partitioning, bool is_sprite) { - unsigned int fifo_size = ilk_display_fifo_size(dev); + struct drm_i915_private *dev_priv = to_i915(dev); + unsigned int fifo_size = ilk_display_fifo_size(dev_priv); /* if sprites aren't enabled, sprites get nothing */ if (is_sprite && !config->sprites_enabled) @@ -1920,14 +1924,14 @@ static unsigned int ilk_plane_wm_max(const struct drm_device *dev, /* HSW allows LP1+ watermarks even with multiple pipes */ if (level == 0 || config->num_pipes_active > 1) { - fifo_size /= INTEL_INFO(dev)->num_pipes; + fifo_size /= INTEL_INFO(dev_priv)->num_pipes; /* * For some reason the non self refresh * FIFO size is only half of the self * refresh FIFO size on ILK/SNB. */ - if (INTEL_INFO(dev)->gen <= 6) + if (INTEL_GEN(dev_priv) <= 6) fifo_size /= 2; } @@ -1943,7 +1947,7 @@ static unsigned int ilk_plane_wm_max(const struct drm_device *dev, } /* clamp to max that the registers can hold */ - return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite)); + return min(fifo_size, ilk_plane_wm_reg_max(dev_priv, level, is_sprite)); } /* Calculate the maximum cursor plane watermark */ @@ -1956,7 +1960,7 @@ static unsigned int ilk_cursor_wm_max(const struct drm_device *dev, return 64; /* otherwise just report max that registers can hold */ - return ilk_cursor_wm_reg_max(dev, level); + return ilk_cursor_wm_reg_max(to_i915(dev), level); } static void ilk_compute_wm_maximums(const struct drm_device *dev, @@ -1968,17 +1972,17 @@ static void ilk_compute_wm_maximums(const struct drm_device *dev, max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false); max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true); max->cur = ilk_cursor_wm_max(dev, level, config); - max->fbc = ilk_fbc_wm_reg_max(dev); + max->fbc = ilk_fbc_wm_reg_max(to_i915(dev)); } -static void ilk_compute_wm_reg_maximums(struct drm_device *dev, +static void ilk_compute_wm_reg_maximums(const struct drm_i915_private *dev_priv, int level, struct ilk_wm_maximums *max) { - max->pri = ilk_plane_wm_reg_max(dev, level, false); - max->spr = ilk_plane_wm_reg_max(dev, level, true); - max->cur = ilk_cursor_wm_reg_max(dev, level); - max->fbc = ilk_fbc_wm_reg_max(dev); + max->pri = ilk_plane_wm_reg_max(dev_priv, level, false); + max->spr = ilk_plane_wm_reg_max(dev_priv, level, true); + max->cur = ilk_cursor_wm_reg_max(dev_priv, level); + max->fbc = ilk_fbc_wm_reg_max(dev_priv); } static bool ilk_validate_wm_level(int level, @@ -2382,7 +2386,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate) usable_level = max_level; /* ILK/SNB: LP2+ watermarks only w/o sprites */ - if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled) + if (INTEL_GEN(dev_priv) <= 6 && pipe_wm->sprites_enabled) usable_level = 1; /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */ @@ -2401,7 +2405,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate) if (!ilk_validate_pipe_wm(dev, pipe_wm)) return -EINVAL; - ilk_compute_wm_reg_maximums(dev, 1, &max); + ilk_compute_wm_reg_maximums(dev_priv, 1, &max); for (level = 1; level <= max_level; level++) { struct intel_wm_level *wm = &pipe_wm->raw_wm[level]; @@ -2530,7 +2534,7 @@ static void ilk_wm_merge(struct drm_device *dev, last_enabled_level = 0; /* ILK: FBC WM must be disabled always */ - merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6; + merged->fbc_wm_enabled = INTEL_GEN(dev_priv) >= 6; /* merge each WM1+ level */ for (level = 1; level <= max_level; level++) { @@ -2593,6 +2597,7 @@ static void ilk_compute_wm_results(struct drm_device *dev, enum intel_ddb_partitioning partitioning, struct ilk_wm_values *results) { + struct drm_i915_private *dev_priv = to_i915(dev); struct intel_crtc *intel_crtc; int level, wm_lp; @@ -2619,7 +2624,7 @@ static void ilk_compute_wm_results(struct drm_device *dev, if (r->enable) results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN; - if (INTEL_INFO(dev)->gen >= 8) + if (INTEL_GEN(dev_priv) >= 8) results->wm_lp[wm_lp - 1] |= r->fbc_val << WM1_LP_FBC_SHIFT_BDW; else @@ -2630,7 +2635,7 @@ static void ilk_compute_wm_results(struct drm_device *dev, * Always set WM1S_LP_EN when spr_val != 0, even if the * level is disabled. Doing otherwise could cause underruns. */ - if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) { + if (INTEL_GEN(dev_priv) <= 6 && r->spr_val) { WARN_ON(wm_lp != 1); results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val; } else @@ -2780,7 +2785,6 @@ static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv, static void ilk_write_wm_values(struct drm_i915_private *dev_priv, struct ilk_wm_values *results) { - struct drm_device *dev = &dev_priv->drm; struct ilk_wm_values *previous = &dev_priv->wm.hw; unsigned int dirty; uint32_t val; @@ -2836,7 +2840,7 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv, previous->wm_lp_spr[0] != results->wm_lp_spr[0]) I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]); - if (INTEL_INFO(dev)->gen >= 7) { + if (INTEL_GEN(dev_priv) >= 7) { if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1]) I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]); if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2]) @@ -3118,7 +3122,11 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device *dev, * we currently hold. */ if (!intel_state->active_pipe_changes) { - *alloc = to_intel_crtc(for_crtc)->hw_ddb; + /* + * alloc may be cleared by clear_intel_crtc_state, + * copy from old state to be sure + */ + *alloc = to_intel_crtc_state(for_crtc->state)->wm.skl.ddb; return; } @@ -3624,6 +3632,9 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, y_min_scanlines = 4; } + if (apply_memory_bw_wa) + y_min_scanlines *= 2; + plane_bytes_per_line = width * cpp; if (fb->modifier == I915_FORMAT_MOD_Y_TILED || fb->modifier == I915_FORMAT_MOD_Yf_TILED) { @@ -3644,8 +3655,6 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, plane_blocks_per_line); y_tile_minimum = plane_blocks_per_line * y_min_scanlines; - if (apply_memory_bw_wa) - y_tile_minimum *= 2; if (fb->modifier == I915_FORMAT_MOD_Y_TILED || fb->modifier == I915_FORMAT_MOD_Yf_TILED) { @@ -3906,25 +3915,16 @@ static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a, return a->start < b->end && b->start < a->end; } -bool skl_ddb_allocation_overlaps(struct drm_atomic_state *state, - struct intel_crtc *intel_crtc) +bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries, + const struct skl_ddb_entry *ddb, + int ignore) { - struct drm_crtc *other_crtc; - struct drm_crtc_state *other_cstate; - struct intel_crtc *other_intel_crtc; - const struct skl_ddb_entry *ddb = - &to_intel_crtc_state(intel_crtc->base.state)->wm.skl.ddb; int i; - for_each_crtc_in_state(state, other_crtc, other_cstate, i) { - other_intel_crtc = to_intel_crtc(other_crtc); - - if (other_intel_crtc == intel_crtc) - continue; - - if (skl_ddb_entries_overlap(ddb, &other_intel_crtc->hw_ddb)) + for (i = 0; i < I915_MAX_PIPES; i++) + if (i != ignore && entries[i] && + skl_ddb_entries_overlap(ddb, entries[i])) return true; - } return false; } @@ -4193,14 +4193,35 @@ skl_compute_wm(struct drm_atomic_state *state) return 0; } -static void skl_update_wm(struct intel_crtc *intel_crtc) +static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state, + struct intel_crtc_state *cstate) +{ + struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc); + struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal; + const struct skl_ddb_allocation *ddb = &state->wm_results.ddb; + enum pipe pipe = crtc->pipe; + int plane; + + if (!(state->wm_results.dirty_pipes & drm_crtc_mask(&crtc->base))) + return; + + I915_WRITE(PIPE_WM_LINETIME(pipe), pipe_wm->linetime); + + for_each_universal_plane(dev_priv, pipe, plane) + skl_write_plane_wm(crtc, &pipe_wm->planes[plane], ddb, plane); + + skl_write_cursor_wm(crtc, &pipe_wm->planes[PLANE_CURSOR], ddb); +} + +static void skl_initial_wm(struct intel_atomic_state *state, + struct intel_crtc_state *cstate) { + struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc); struct drm_device *dev = intel_crtc->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); - struct skl_wm_values *results = &dev_priv->wm.skl_results; + struct skl_wm_values *results = &state->wm_results; struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw; - struct intel_crtc_state *cstate = to_intel_crtc_state(intel_crtc->base.state); - struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal; enum pipe pipe = intel_crtc->pipe; if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0) @@ -4208,27 +4229,11 @@ static void skl_update_wm(struct intel_crtc *intel_crtc) mutex_lock(&dev_priv->wm.wm_mutex); - /* - * If this pipe isn't active already, we're going to be enabling it - * very soon. Since it's safe to update a pipe's ddb allocation while - * the pipe's shut off, just do so here. Already active pipes will have - * their watermarks updated once we update their planes. - */ - if (intel_crtc->base.state->active_changed) { - int plane; - - for_each_universal_plane(dev_priv, pipe, plane) - skl_write_plane_wm(intel_crtc, &pipe_wm->planes[plane], - &results->ddb, plane); - - skl_write_cursor_wm(intel_crtc, &pipe_wm->planes[PLANE_CURSOR], - &results->ddb); - } + if (cstate->base.active_changed) + skl_atomic_update_crtc_wm(state, cstate); skl_copy_wm_for_pipe(hw_vals, results, pipe); - intel_crtc->hw_ddb = cstate->wm.skl.ddb; - mutex_unlock(&dev_priv->wm.wm_mutex); } @@ -4265,7 +4270,7 @@ static void ilk_program_watermarks(struct drm_i915_private *dev_priv) ilk_wm_merge(dev, &config, &max, &lp_wm_1_2); /* 5/6 split only in single pipe config on IVB+ */ - if (INTEL_INFO(dev)->gen >= 7 && + if (INTEL_GEN(dev_priv) >= 7 && config.num_pipes_active == 1 && config.sprites_enabled) { ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max); ilk_wm_merge(dev, &config, &max, &lp_wm_5_6); @@ -4283,7 +4288,8 @@ static void ilk_program_watermarks(struct drm_i915_private *dev_priv) ilk_write_wm_values(dev_priv, &results); } -static void ilk_initial_watermarks(struct intel_crtc_state *cstate) +static void ilk_initial_watermarks(struct intel_atomic_state *state, + struct intel_crtc_state *cstate) { struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev); struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc); @@ -4294,7 +4300,8 @@ static void ilk_initial_watermarks(struct intel_crtc_state *cstate) mutex_unlock(&dev_priv->wm.wm_mutex); } -static void ilk_optimize_watermarks(struct intel_crtc_state *cstate) +static void ilk_optimize_watermarks(struct intel_atomic_state *state, + struct intel_crtc_state *cstate) { struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev); struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc); @@ -4605,7 +4612,7 @@ void ilk_wm_get_hw_state(struct drm_device *dev) hw->wm_lp[2] = I915_READ(WM3_LP_ILK); hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK); - if (INTEL_INFO(dev)->gen >= 7) { + if (INTEL_GEN(dev_priv) >= 7) { hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB); hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB); } @@ -7690,7 +7697,8 @@ void intel_init_pm(struct drm_i915_private *dev_priv) /* For FIFO watermark updates */ if (INTEL_GEN(dev_priv) >= 9) { skl_setup_wm_latency(dev_priv); - dev_priv->display.update_wm = skl_update_wm; + dev_priv->display.initial_watermarks = skl_initial_wm; + dev_priv->display.atomic_update_watermarks = skl_atomic_update_crtc_wm; dev_priv->display.compute_global_watermarks = skl_compute_wm; } else if (HAS_PCH_SPLIT(dev_priv)) { ilk_setup_wm_latency(dev_priv); diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 271a3e29ff23..7b488e2793d9 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -427,7 +427,7 @@ void intel_psr_enable(struct intel_dp *intel_dp) struct drm_i915_private *dev_priv = to_i915(dev); struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); - if (!HAS_PSR(dev)) { + if (!HAS_PSR(dev_priv)) { DRM_DEBUG_KMS("PSR not supported on this platform\n"); return; } @@ -472,7 +472,7 @@ void intel_psr_enable(struct intel_dp *intel_dp) /* Enable PSR on the panel */ hsw_psr_enable_sink(intel_dp); - if (INTEL_INFO(dev)->gen >= 9) + if (INTEL_GEN(dev_priv) >= 9) intel_psr_activate(intel_dp); } else { vlv_psr_setup_vsc(intel_dp); @@ -498,7 +498,7 @@ void intel_psr_enable(struct intel_dp *intel_dp) * - On HSW/BDW we get a recoverable frozen screen until next * exit-activate sequence. */ - if (INTEL_INFO(dev)->gen < 9) + if (INTEL_GEN(dev_priv) < 9) schedule_delayed_work(&dev_priv->psr.work, msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 700e93d80616..aeb637dc1fdf 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1294,6 +1294,8 @@ static void i9xx_submit_request(struct drm_i915_gem_request *request) { struct drm_i915_private *dev_priv = request->i915; + i915_gem_request_submit(request); + I915_WRITE_TAIL(request->engine, request->tail); } diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 642b54692d0d..3466b4e77e7c 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -267,6 +267,15 @@ struct intel_engine_cs { */ void (*submit_request)(struct drm_i915_gem_request *req); + /* Call when the priority on a request has changed and it and its + * dependencies may need rescheduling. Note the request itself may + * not be ready to run! + * + * Called under the struct_mutex. + */ + void (*schedule)(struct drm_i915_gem_request *request, + int priority); + /* Some chipsets are not quite as coherent as advertised and need * an expensive kick to force a true read of the up-to-date seqno. * However, the up-to-date seqno is not always required and the last @@ -335,12 +344,12 @@ struct intel_engine_cs { /* Execlists */ struct tasklet_struct irq_tasklet; - spinlock_t execlist_lock; /* used inside tasklet, use spin_lock_bh */ struct execlist_port { struct drm_i915_gem_request *request; unsigned int count; } execlist_port[2]; - struct list_head execlist_queue; + struct rb_root execlist_queue; + struct rb_node *execlist_first; unsigned int fw_domains; bool disable_lite_restore_wa; bool preempt_wa; @@ -578,7 +587,6 @@ static inline bool intel_engine_wakeup(const struct intel_engine_cs *engine) void intel_engine_reset_breadcrumbs(struct intel_engine_cs *engine); void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine); -unsigned int intel_kick_waiters(struct drm_i915_private *i915); -unsigned int intel_kick_signalers(struct drm_i915_private *i915); +unsigned int intel_breadcrumbs_busy(struct drm_i915_private *i915); #endif /* _INTEL_RINGBUFFER_H_ */ diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 05994083e161..356c662ad453 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -1066,7 +1066,7 @@ static void vlv_display_power_well_init(struct drm_i915_private *dev_priv) * * CHV DPLL B/C have some issues if VGA mode is enabled. */ - for_each_pipe(&dev_priv->drm, pipe) { + for_each_pipe(dev_priv, pipe) { u32 val = I915_READ(DPLL(pipe)); val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; @@ -1097,7 +1097,7 @@ static void vlv_display_power_well_init(struct drm_i915_private *dev_priv) intel_crt_reset(&encoder->base); } - i915_redisable_vga_power_on(&dev_priv->drm); + i915_redisable_vga_power_on(dev_priv); intel_pps_unlock_regs_wa(dev_priv); } diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index 3990c805a5b5..27808e91cb5a 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c @@ -1195,8 +1195,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder, struct intel_crtc_state *crtc_state, struct drm_connector_state *conn_state) { - struct drm_device *dev = intel_encoder->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; struct drm_display_mode *mode = &crtc_state->base.mode; @@ -1269,13 +1268,13 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder, return; /* Set the SDVO control regs. */ - if (INTEL_INFO(dev)->gen >= 4) { + if (INTEL_GEN(dev_priv) >= 4) { /* The real mode polarity is set by the SDVO commands, using * struct intel_sdvo_dtd. */ sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH; if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range) sdvox |= HDMI_COLOR_RANGE_16_235; - if (INTEL_INFO(dev)->gen < 5) + if (INTEL_GEN(dev_priv) < 5) sdvox |= SDVO_BORDER_ENABLE; } else { sdvox = I915_READ(intel_sdvo->sdvo_reg); @@ -1294,7 +1293,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder, if (intel_sdvo->has_hdmi_audio) sdvox |= SDVO_AUDIO_ENABLE; - if (INTEL_INFO(dev)->gen >= 4) { + if (INTEL_GEN(dev_priv) >= 4) { /* done in crtc_mode_set as the dpll_md reg must be written early */ } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || IS_G33(dev_priv)) { @@ -1305,7 +1304,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder, } if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL && - INTEL_INFO(dev)->gen < 5) + INTEL_GEN(dev_priv) < 5) sdvox |= SDVO_STALL_SELECT; intel_sdvo_write_sdvox(intel_sdvo, sdvox); } diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index ca02855435d9..8f131a08d440 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -203,13 +203,8 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_i915_private *dev_priv = to_i915(dev); struct intel_plane *intel_plane = to_intel_plane(drm_plane); struct drm_framebuffer *fb = plane_state->base.fb; - const struct skl_wm_values *wm = &dev_priv->wm.skl_results; - struct drm_crtc *crtc = crtc_state->base.crtc; - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); const int pipe = intel_plane->pipe; const int plane = intel_plane->plane + 1; - const struct skl_plane_wm *p_wm = - &crtc_state->wm.skl.optimal.planes[plane]; u32 plane_ctl; const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; u32 surf_addr = plane_state->main.offset; @@ -233,9 +228,6 @@ skl_update_plane(struct drm_plane *drm_plane, plane_ctl |= skl_plane_ctl_rotation(rotation); - if (wm->dirty_pipes & drm_crtc_mask(crtc)) - skl_write_plane_wm(intel_crtc, p_wm, &wm->ddb, plane); - if (key->flags) { I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value); I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value); @@ -291,19 +283,9 @@ skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc) struct drm_device *dev = dplane->dev; struct drm_i915_private *dev_priv = to_i915(dev); struct intel_plane *intel_plane = to_intel_plane(dplane); - struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state); const int pipe = intel_plane->pipe; const int plane = intel_plane->plane + 1; - /* - * We only populate skl_results on watermark updates, and if the - * plane's visiblity isn't actually changing neither is its watermarks. - */ - if (!dplane->state->visible) - skl_write_plane_wm(to_intel_crtc(crtc), - &cstate->wm.skl.optimal.planes[plane], - &dev_priv->wm.skl_results.ddb, plane); - I915_WRITE(PLANE_CTL(pipe, plane), 0); I915_WRITE(PLANE_SURF(pipe, plane), 0); @@ -362,7 +344,7 @@ vlv_update_plane(struct drm_plane *dplane, int plane = intel_plane->plane; u32 sprctl; u32 sprsurf_offset, linear_offset; - unsigned int rotation = dplane->state->rotation; + unsigned int rotation = plane_state->base.rotation; const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; int crtc_x = plane_state->base.dst.x1; int crtc_y = plane_state->base.dst.y1; @@ -427,6 +409,12 @@ vlv_update_plane(struct drm_plane *dplane, if (fb->modifier == I915_FORMAT_MOD_X_TILED) sprctl |= SP_TILED; + if (rotation & DRM_ROTATE_180) + sprctl |= SP_ROTATE_180; + + if (rotation & DRM_REFLECT_X) + sprctl |= SP_MIRROR; + /* Sizes are 0 based */ src_w--; src_h--; @@ -436,11 +424,11 @@ vlv_update_plane(struct drm_plane *dplane, intel_add_fb_offsets(&x, &y, plane_state, 0); sprsurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0); - if (rotation == DRM_ROTATE_180) { - sprctl |= SP_ROTATE_180; - + if (rotation & DRM_ROTATE_180) { x += src_w; y += src_h; + } else if (rotation & DRM_REFLECT_X) { + x += src_w; } linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); @@ -546,6 +534,9 @@ ivb_update_plane(struct drm_plane *plane, if (fb->modifier == I915_FORMAT_MOD_X_TILED) sprctl |= SPRITE_TILED; + if (rotation & DRM_ROTATE_180) + sprctl |= SPRITE_ROTATE_180; + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE; else @@ -566,14 +557,11 @@ ivb_update_plane(struct drm_plane *plane, intel_add_fb_offsets(&x, &y, plane_state, 0); sprsurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0); - if (rotation == DRM_ROTATE_180) { - sprctl |= SPRITE_ROTATE_180; - - /* HSW and BDW does this automagically in hardware */ - if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) { - x += src_w; - y += src_h; - } + /* HSW+ does this automagically in hardware */ + if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv) && + rotation & DRM_ROTATE_180) { + x += src_w; + y += src_h; } linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); @@ -684,6 +672,9 @@ ilk_update_plane(struct drm_plane *plane, if (fb->modifier == I915_FORMAT_MOD_X_TILED) dvscntr |= DVS_TILED; + if (rotation & DRM_ROTATE_180) + dvscntr |= DVS_ROTATE_180; + if (IS_GEN6(dev_priv)) dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */ @@ -700,9 +691,7 @@ ilk_update_plane(struct drm_plane *plane, intel_add_fb_offsets(&x, &y, plane_state, 0); dvssurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0); - if (rotation == DRM_ROTATE_180) { - dvscntr |= DVS_ROTATE_180; - + if (rotation & DRM_ROTATE_180) { x += src_w; y += src_h; } @@ -1112,6 +1101,10 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, supported_rotations = DRM_ROTATE_0 | DRM_ROTATE_90 | DRM_ROTATE_180 | DRM_ROTATE_270; + } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { + supported_rotations = + DRM_ROTATE_0 | DRM_ROTATE_180 | + DRM_REFLECT_X; } else { supported_rotations = DRM_ROTATE_0 | DRM_ROTATE_180; diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c index 9212f00d5752..78cdfc6833d6 100644 --- a/drivers/gpu/drm/i915/intel_tv.c +++ b/drivers/gpu/drm/i915/intel_tv.c @@ -1029,8 +1029,7 @@ static void intel_tv_pre_enable(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state) { - struct drm_device *dev = encoder->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); struct intel_tv *intel_tv = enc_to_tv(encoder); const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv); @@ -1116,7 +1115,7 @@ static void intel_tv_pre_enable(struct intel_encoder *encoder, set_color_conversion(dev_priv, color_conversion); - if (INTEL_INFO(dev)->gen >= 4) + if (INTEL_GEN(dev_priv) >= 4) I915_WRITE(TV_CLR_KNOBS, 0x00404000); else I915_WRITE(TV_CLR_KNOBS, 0x00606000); diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index e2b188dcf908..d7be0d94ba4d 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -402,6 +402,8 @@ check_for_unclaimed_mmio(struct drm_i915_private *dev_priv) static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv, bool restore_forcewake) { + struct intel_device_info *info = mkwrite_device_info(dev_priv); + /* clear out unclaimed reg detection bit */ if (check_for_unclaimed_mmio(dev_priv)) DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n"); @@ -419,6 +421,10 @@ static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv, GT_FIFO_CTL_RC6_POLICY_STALL); } + /* Enable Decoupled MMIO only on BXT C stepping onwards */ + if (!IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER)) + info->has_decoupled_mmio = false; + intel_uncore_forcewake_reset(dev_priv, restore_forcewake); } @@ -641,6 +647,8 @@ intel_fw_table_check(struct drm_i915_private *dev_priv) num_ranges = dev_priv->uncore.fw_domains_table_entries; for (i = 0, prev = -1; i < num_ranges; i++, ranges++) { + WARN_ON_ONCE(IS_GEN9(dev_priv) && + (prev + 1) != (s32)ranges->start); WARN_ON_ONCE(prev >= (s32)ranges->start); prev = ranges->start; WARN_ON_ONCE(prev >= (s32)ranges->end); @@ -783,7 +791,7 @@ static const struct intel_forcewake_range __gen9_fw_ranges[] = { GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER), GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER), - GEN_FW_RANGE(0xb480, 0xbfff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0xb480, 0xcfff, FORCEWAKE_BLITTER), GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA), GEN_FW_RANGE(0xd800, 0xdfff, FORCEWAKE_BLITTER), GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER), @@ -831,6 +839,66 @@ unclaimed_reg_debug(struct drm_i915_private *dev_priv, __unclaimed_reg_debug(dev_priv, reg, read, before); } +static const enum decoupled_power_domain fw2dpd_domain[] = { + GEN9_DECOUPLED_PD_RENDER, + GEN9_DECOUPLED_PD_BLITTER, + GEN9_DECOUPLED_PD_ALL, + GEN9_DECOUPLED_PD_MEDIA, + GEN9_DECOUPLED_PD_ALL, + GEN9_DECOUPLED_PD_ALL, + GEN9_DECOUPLED_PD_ALL +}; + +/* + * Decoupled MMIO access for only 1 DWORD + */ +static void __gen9_decoupled_mmio_access(struct drm_i915_private *dev_priv, + u32 reg, + enum forcewake_domains fw_domain, + enum decoupled_ops operation) +{ + enum decoupled_power_domain dp_domain; + u32 ctrl_reg_data = 0; + + dp_domain = fw2dpd_domain[fw_domain - 1]; + + ctrl_reg_data |= reg; + ctrl_reg_data |= (operation << GEN9_DECOUPLED_OP_SHIFT); + ctrl_reg_data |= (dp_domain << GEN9_DECOUPLED_PD_SHIFT); + ctrl_reg_data |= GEN9_DECOUPLED_DW1_GO; + __raw_i915_write32(dev_priv, GEN9_DECOUPLED_REG0_DW1, ctrl_reg_data); + + if (wait_for_atomic((__raw_i915_read32(dev_priv, + GEN9_DECOUPLED_REG0_DW1) & + GEN9_DECOUPLED_DW1_GO) == 0, + FORCEWAKE_ACK_TIMEOUT_MS)) + DRM_ERROR("Decoupled MMIO wait timed out\n"); +} + +static inline u32 +__gen9_decoupled_mmio_read32(struct drm_i915_private *dev_priv, + u32 reg, + enum forcewake_domains fw_domain) +{ + __gen9_decoupled_mmio_access(dev_priv, reg, fw_domain, + GEN9_DECOUPLED_OP_READ); + + return __raw_i915_read32(dev_priv, GEN9_DECOUPLED_REG0_DW0); +} + +static inline void +__gen9_decoupled_mmio_write(struct drm_i915_private *dev_priv, + u32 reg, u32 data, + enum forcewake_domains fw_domain) +{ + + __raw_i915_write32(dev_priv, GEN9_DECOUPLED_REG0_DW0, data); + + __gen9_decoupled_mmio_access(dev_priv, reg, fw_domain, + GEN9_DECOUPLED_OP_WRITE); +} + + #define GEN2_READ_HEADER(x) \ u##x val = 0; \ assert_rpm_wakelock_held(dev_priv); @@ -935,6 +1003,28 @@ fwtable_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { GEN6_READ_FOOTER; \ } +#define __gen9_decoupled_read(x) \ +static u##x \ +gen9_decoupled_read##x(struct drm_i915_private *dev_priv, \ + i915_reg_t reg, bool trace) { \ + enum forcewake_domains fw_engine; \ + GEN6_READ_HEADER(x); \ + fw_engine = __fwtable_reg_read_fw_domains(offset); \ + if (fw_engine & ~dev_priv->uncore.fw_domains_active) { \ + unsigned i; \ + u32 *ptr_data = (u32 *) &val; \ + for (i = 0; i < x/32; i++, offset += sizeof(u32), ptr_data++) \ + *ptr_data = __gen9_decoupled_mmio_read32(dev_priv, \ + offset, \ + fw_engine); \ + } else { \ + val = __raw_i915_read##x(dev_priv, reg); \ + } \ + GEN6_READ_FOOTER; \ +} + +__gen9_decoupled_read(32) +__gen9_decoupled_read(64) __fwtable_read(8) __fwtable_read(16) __fwtable_read(32) @@ -1064,6 +1154,25 @@ fwtable_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bo GEN6_WRITE_FOOTER; \ } +#define __gen9_decoupled_write(x) \ +static void \ +gen9_decoupled_write##x(struct drm_i915_private *dev_priv, \ + i915_reg_t reg, u##x val, \ + bool trace) { \ + enum forcewake_domains fw_engine; \ + GEN6_WRITE_HEADER; \ + fw_engine = __fwtable_reg_write_fw_domains(offset); \ + if (fw_engine & ~dev_priv->uncore.fw_domains_active) \ + __gen9_decoupled_mmio_write(dev_priv, \ + offset, \ + val, \ + fw_engine); \ + else \ + __raw_i915_write##x(dev_priv, reg, val); \ + GEN6_WRITE_FOOTER; \ +} + +__gen9_decoupled_write(32) __fwtable_write(8) __fwtable_write(16) __fwtable_write(32) @@ -1287,6 +1396,14 @@ void intel_uncore_init(struct drm_i915_private *dev_priv) ASSIGN_FW_DOMAINS_TABLE(__gen9_fw_ranges); ASSIGN_WRITE_MMIO_VFUNCS(fwtable); ASSIGN_READ_MMIO_VFUNCS(fwtable); + if (HAS_DECOUPLED_MMIO(dev_priv)) { + dev_priv->uncore.funcs.mmio_readl = + gen9_decoupled_read32; + dev_priv->uncore.funcs.mmio_readq = + gen9_decoupled_read64; + dev_priv->uncore.funcs.mmio_writel = + gen9_decoupled_write32; + } break; case 8: if (IS_CHERRYVIEW(dev_priv)) { @@ -1368,7 +1485,7 @@ int i915_reg_read_ioctl(struct drm_device *dev, for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) { if (i915_mmio_reg_offset(entry->offset_ldw) == (reg->offset & -entry->size) && - (INTEL_INFO(dev)->gen_mask & entry->gen_bitmask)) + (INTEL_INFO(dev_priv)->gen_mask & entry->gen_bitmask)) break; } diff --git a/drivers/gpu/drm/i915/intel_vbt_defs.h b/drivers/gpu/drm/i915/intel_vbt_defs.h index 68db9621f1f0..8886cab19f98 100644 --- a/drivers/gpu/drm/i915/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/intel_vbt_defs.h @@ -280,7 +280,8 @@ struct common_child_dev_config { u8 dp_support:1; u8 tmds_support:1; u8 support_reserved:5; - u8 not_common3[12]; + u8 aux_channel; + u8 not_common3[11]; u8 iboost_level; } __packed; diff --git a/drivers/gpu/drm/imx/ipuv3-crtc.c b/drivers/gpu/drm/imx/ipuv3-crtc.c index 4e1ae3fc462d..6be515a9fb69 100644 --- a/drivers/gpu/drm/imx/ipuv3-crtc.c +++ b/drivers/gpu/drm/imx/ipuv3-crtc.c @@ -68,6 +68,12 @@ static void ipu_crtc_atomic_disable(struct drm_crtc *crtc, ipu_dc_disable_channel(ipu_crtc->dc); ipu_di_disable(ipu_crtc->di); + /* + * Planes must be disabled before DC clock is removed, as otherwise the + * attached IDMACs will be left in undefined state, possibly hanging + * the IPU or even system. + */ + drm_atomic_helper_disable_planes_on_crtc(old_crtc_state, false); ipu_dc_disable(ipu); spin_lock_irq(&crtc->dev->event_lock); @@ -77,9 +83,6 @@ static void ipu_crtc_atomic_disable(struct drm_crtc *crtc, } spin_unlock_irq(&crtc->dev->event_lock); - /* always disable planes on the CRTC */ - drm_atomic_helper_disable_planes_on_crtc(old_crtc_state, true); - drm_crtc_vblank_off(crtc); } diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 019b7ca392d7..c70310206ac5 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -80,6 +80,7 @@ static void mtk_ovl_enable_vblank(struct mtk_ddp_comp *comp, ddp_comp); priv->crtc = crtc; + writel(0x0, comp->regs + DISP_REG_OVL_INTSTA); writel_relaxed(OVL_FME_CPL_INT, comp->regs + DISP_REG_OVL_INTEN); } @@ -250,13 +251,6 @@ static int mtk_disp_ovl_probe(struct platform_device *pdev) if (irq < 0) return irq; - ret = devm_request_irq(dev, irq, mtk_disp_ovl_irq_handler, - IRQF_TRIGGER_NONE, dev_name(dev), priv); - if (ret < 0) { - dev_err(dev, "Failed to request irq %d: %d\n", irq, ret); - return ret; - } - comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_OVL); if (comp_id < 0) { dev_err(dev, "Failed to identify by alias: %d\n", comp_id); @@ -272,6 +266,13 @@ static int mtk_disp_ovl_probe(struct platform_device *pdev) platform_set_drvdata(pdev, priv); + ret = devm_request_irq(dev, irq, mtk_disp_ovl_irq_handler, + IRQF_TRIGGER_NONE, dev_name(dev), priv); + if (ret < 0) { + dev_err(dev, "Failed to request irq %d: %d\n", irq, ret); + return ret; + } + ret = component_add(dev, &mtk_disp_ovl_component_ops); if (ret) dev_err(dev, "Failed to add component: %d\n", ret); diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 0186e500d2a5..90fb831ef031 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -432,11 +432,16 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, unsigned long pll_rate; unsigned int factor; + /* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */ pix_rate = 1000UL * mode->clock; - if (mode->clock <= 74000) + if (mode->clock <= 27000) + factor = 16 * 3; + else if (mode->clock <= 84000) factor = 8 * 3; - else + else if (mode->clock <= 167000) factor = 4 * 3; + else + factor = 2 * 3; pll_rate = pix_rate * factor; dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n", diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index df33b3ca6ffd..48cc01fd20c7 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -123,7 +123,7 @@ static void mtk_od_config(struct mtk_ddp_comp *comp, unsigned int w, unsigned int bpc) { writel(w << 16 | h, comp->regs + DISP_OD_SIZE); - writel(OD_RELAYMODE, comp->regs + OD_RELAYMODE); + writel(OD_RELAYMODE, comp->regs + DISP_OD_CFG); mtk_dither_set(comp, bpc, DISP_OD_CFG); } diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index 30027b26a59f..2c42f90809d8 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -86,7 +86,7 @@ #define DSI_PHY_TIMECON0 0x110 #define LPX (0xff << 0) -#define HS_PRPR (0xff << 8) +#define HS_PREP (0xff << 8) #define HS_ZERO (0xff << 16) #define HS_TRAIL (0xff << 24) @@ -102,10 +102,16 @@ #define CLK_TRAIL (0xff << 24) #define DSI_PHY_TIMECON3 0x11c -#define CLK_HS_PRPR (0xff << 0) +#define CLK_HS_PREP (0xff << 0) #define CLK_HS_POST (0xff << 8) #define CLK_HS_EXIT (0xff << 16) +#define T_LPX 5 +#define T_HS_PREP 6 +#define T_HS_TRAIL 8 +#define T_HS_EXIT 7 +#define T_HS_ZERO 10 + #define NS_TO_CYCLE(n, c) ((n) / (c) + (((n) % (c)) ? 1 : 0)) struct phy; @@ -161,20 +167,18 @@ static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data) static void dsi_phy_timconfig(struct mtk_dsi *dsi) { u32 timcon0, timcon1, timcon2, timcon3; - unsigned int ui, cycle_time; - unsigned int lpx; + u32 ui, cycle_time; ui = 1000 / dsi->data_rate + 0x01; cycle_time = 8000 / dsi->data_rate + 0x01; - lpx = 5; - timcon0 = (8 << 24) | (0xa << 16) | (0x6 << 8) | lpx; - timcon1 = (7 << 24) | (5 * lpx << 16) | ((3 * lpx) / 2) << 8 | - (4 * lpx); + timcon0 = T_LPX | T_HS_PREP << 8 | T_HS_ZERO << 16 | T_HS_TRAIL << 24; + timcon1 = 4 * T_LPX | (3 * T_LPX / 2) << 8 | 5 * T_LPX << 16 | + T_HS_EXIT << 24; timcon2 = ((NS_TO_CYCLE(0x64, cycle_time) + 0xa) << 24) | (NS_TO_CYCLE(0x150, cycle_time) << 16); - timcon3 = (2 * lpx) << 16 | NS_TO_CYCLE(80 + 52 * ui, cycle_time) << 8 | - NS_TO_CYCLE(0x40, cycle_time); + timcon3 = NS_TO_CYCLE(0x40, cycle_time) | (2 * T_LPX) << 16 | + NS_TO_CYCLE(80 + 52 * ui, cycle_time) << 8; writel(timcon0, dsi->regs + DSI_PHY_TIMECON0); writel(timcon1, dsi->regs + DSI_PHY_TIMECON1); @@ -202,19 +206,47 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) { struct device *dev = dsi->dev; int ret; + u64 pixel_clock, total_bits; + u32 htotal, htotal_bits, bit_per_pixel, overhead_cycles, overhead_bits; if (++dsi->refcount != 1) return 0; + switch (dsi->format) { + case MIPI_DSI_FMT_RGB565: + bit_per_pixel = 16; + break; + case MIPI_DSI_FMT_RGB666_PACKED: + bit_per_pixel = 18; + break; + case MIPI_DSI_FMT_RGB666: + case MIPI_DSI_FMT_RGB888: + default: + bit_per_pixel = 24; + break; + } + /** - * data_rate = (pixel_clock / 1000) * pixel_dipth * mipi_ratio; - * pixel_clock unit is Khz, data_rata unit is MHz, so need divide 1000. - * mipi_ratio is mipi clk coefficient for balance the pixel clk in mipi. - * we set mipi_ratio is 1.05. + * vm.pixelclock is in kHz, pixel_clock unit is Hz, so multiply by 1000 + * htotal_time = htotal * byte_per_pixel / num_lanes + * overhead_time = lpx + hs_prepare + hs_zero + hs_trail + hs_exit + * mipi_ratio = (htotal_time + overhead_time) / htotal_time + * data_rate = pixel_clock * bit_per_pixel * mipi_ratio / num_lanes; */ - dsi->data_rate = dsi->vm.pixelclock * 3 * 21 / (1 * 1000 * 10); + pixel_clock = dsi->vm.pixelclock * 1000; + htotal = dsi->vm.hactive + dsi->vm.hback_porch + dsi->vm.hfront_porch + + dsi->vm.hsync_len; + htotal_bits = htotal * bit_per_pixel; + + overhead_cycles = T_LPX + T_HS_PREP + T_HS_ZERO + T_HS_TRAIL + + T_HS_EXIT; + overhead_bits = overhead_cycles * dsi->lanes * 8; + total_bits = htotal_bits + overhead_bits; + + dsi->data_rate = DIV_ROUND_UP_ULL(pixel_clock * total_bits, + htotal * dsi->lanes); - ret = clk_set_rate(dsi->hs_clk, dsi->data_rate * 1000000); + ret = clk_set_rate(dsi->hs_clk, dsi->data_rate); if (ret < 0) { dev_err(dev, "Failed to set data rate: %d\n", ret); goto err_refcount; diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c index 71227deef21b..0e8c4d9af340 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c @@ -1133,12 +1133,6 @@ static int mtk_hdmi_output_set_display_mode(struct mtk_hdmi *hdmi, phy_power_on(hdmi->phy); mtk_hdmi_aud_output_config(hdmi, mode); - mtk_hdmi_setup_audio_infoframe(hdmi); - mtk_hdmi_setup_avi_infoframe(hdmi, mode); - mtk_hdmi_setup_spd_infoframe(hdmi, "mediatek", "On-chip HDMI"); - if (mode->flags & DRM_MODE_FLAG_3D_MASK) - mtk_hdmi_setup_vendor_specific_infoframe(hdmi, mode); - mtk_hdmi_hw_vid_black(hdmi, false); mtk_hdmi_hw_aud_unmute(hdmi); mtk_hdmi_hw_send_av_unmute(hdmi); @@ -1401,6 +1395,16 @@ static void mtk_hdmi_bridge_pre_enable(struct drm_bridge *bridge) hdmi->powered = true; } +static void mtk_hdmi_send_infoframe(struct mtk_hdmi *hdmi, + struct drm_display_mode *mode) +{ + mtk_hdmi_setup_audio_infoframe(hdmi); + mtk_hdmi_setup_avi_infoframe(hdmi, mode); + mtk_hdmi_setup_spd_infoframe(hdmi, "mediatek", "On-chip HDMI"); + if (mode->flags & DRM_MODE_FLAG_3D_MASK) + mtk_hdmi_setup_vendor_specific_infoframe(hdmi, mode); +} + static void mtk_hdmi_bridge_enable(struct drm_bridge *bridge) { struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); @@ -1409,6 +1413,7 @@ static void mtk_hdmi_bridge_enable(struct drm_bridge *bridge) clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]); clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]); phy_power_on(hdmi->phy); + mtk_hdmi_send_infoframe(hdmi, &hdmi->mode); hdmi->enabled = true; } diff --git a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c index 8a24754b440f..51cb9cfb6646 100644 --- a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c +++ b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c @@ -265,6 +265,9 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); unsigned int pre_div; unsigned int div; + unsigned int pre_ibias; + unsigned int hdmi_ibias; + unsigned int imp_en; dev_dbg(hdmi_phy->dev, "%s: %lu Hz, parent: %lu Hz\n", __func__, rate, parent_rate); @@ -298,18 +301,31 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, (0x1 << PLL_BR_SHIFT), RG_HDMITX_PLL_BP | RG_HDMITX_PLL_BC | RG_HDMITX_PLL_BR); - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, RG_HDMITX_PRD_IMP_EN); + if (rate < 165000000) { + mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, + RG_HDMITX_PRD_IMP_EN); + pre_ibias = 0x3; + imp_en = 0x0; + hdmi_ibias = hdmi_phy->ibias; + } else { + mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3, + RG_HDMITX_PRD_IMP_EN); + pre_ibias = 0x6; + imp_en = 0xf; + hdmi_ibias = hdmi_phy->ibias_up; + } mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4, - (0x3 << PRD_IBIAS_CLK_SHIFT) | - (0x3 << PRD_IBIAS_D2_SHIFT) | - (0x3 << PRD_IBIAS_D1_SHIFT) | - (0x3 << PRD_IBIAS_D0_SHIFT), + (pre_ibias << PRD_IBIAS_CLK_SHIFT) | + (pre_ibias << PRD_IBIAS_D2_SHIFT) | + (pre_ibias << PRD_IBIAS_D1_SHIFT) | + (pre_ibias << PRD_IBIAS_D0_SHIFT), RG_HDMITX_PRD_IBIAS_CLK | RG_HDMITX_PRD_IBIAS_D2 | RG_HDMITX_PRD_IBIAS_D1 | RG_HDMITX_PRD_IBIAS_D0); mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3, - (0x0 << DRV_IMP_EN_SHIFT), RG_HDMITX_DRV_IMP_EN); + (imp_en << DRV_IMP_EN_SHIFT), + RG_HDMITX_DRV_IMP_EN); mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT) | (hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) | @@ -318,12 +334,14 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 | RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0); mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5, - (hdmi_phy->ibias << DRV_IBIAS_CLK_SHIFT) | - (hdmi_phy->ibias << DRV_IBIAS_D2_SHIFT) | - (hdmi_phy->ibias << DRV_IBIAS_D1_SHIFT) | - (hdmi_phy->ibias << DRV_IBIAS_D0_SHIFT), - RG_HDMITX_DRV_IBIAS_CLK | RG_HDMITX_DRV_IBIAS_D2 | - RG_HDMITX_DRV_IBIAS_D1 | RG_HDMITX_DRV_IBIAS_D0); + (hdmi_ibias << DRV_IBIAS_CLK_SHIFT) | + (hdmi_ibias << DRV_IBIAS_D2_SHIFT) | + (hdmi_ibias << DRV_IBIAS_D1_SHIFT) | + (hdmi_ibias << DRV_IBIAS_D0_SHIFT), + RG_HDMITX_DRV_IBIAS_CLK | + RG_HDMITX_DRV_IBIAS_D2 | + RG_HDMITX_DRV_IBIAS_D1 | + RG_HDMITX_DRV_IBIAS_D0); return 0; } diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index 4e2806cf778c..028c24df2291 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -6,6 +6,8 @@ msm-y := \ adreno/adreno_gpu.o \ adreno/a3xx_gpu.o \ adreno/a4xx_gpu.o \ + adreno/a5xx_gpu.o \ + adreno/a5xx_power.o \ hdmi/hdmi.o \ hdmi/hdmi_audio.o \ hdmi/hdmi_bridge.o \ @@ -37,6 +39,7 @@ msm-y := \ mdp/mdp5/mdp5_irq.o \ mdp/mdp5/mdp5_mdss.o \ mdp/mdp5/mdp5_kms.o \ + mdp/mdp5/mdp5_pipe.o \ mdp/mdp5/mdp5_plane.o \ mdp/mdp5/mdp5_smp.o \ msm_atomic.o \ @@ -48,6 +51,7 @@ msm-y := \ msm_gem_prime.o \ msm_gem_shrinker.o \ msm_gem_submit.o \ + msm_gem_vma.o \ msm_gpu.o \ msm_iommu.o \ msm_perf.o \ diff --git a/drivers/gpu/drm/msm/adreno/a2xx.xml.h b/drivers/gpu/drm/msm/adreno/a2xx.xml.h index fee24297fb92..4be092f911f9 100644 --- a/drivers/gpu/drm/msm/adreno/a2xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a2xx.xml.h @@ -8,16 +8,17 @@ http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31) +- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2016-04-26 17:56:44) - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 11518 bytes, from 2016-02-10 21:03:25) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 16166 bytes, from 2016-02-11 21:20:31) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83967 bytes, from 2016-02-10 17:07:21) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 109916 bytes, from 2016-02-20 18:44:48) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32907 bytes, from 2016-11-26 23:01:08) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2016-11-26 23:01:08) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 22544 bytes, from 2016-11-26 23:01:08) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2016-11-26 23:01:08) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110765 bytes, from 2016-11-26 23:01:48) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 90321 bytes, from 2016-11-28 16:50:05) - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00) -Copyright (C) 2013-2015 by the following authors: +Copyright (C) 2013-2016 by the following authors: - Rob Clark <robdclark@gmail.com> (robclark) - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) @@ -206,12 +207,12 @@ enum a2xx_rb_copy_sample_select { }; enum a2xx_rb_blend_opcode { - BLEND_DST_PLUS_SRC = 0, - BLEND_SRC_MINUS_DST = 1, - BLEND_MIN_DST_SRC = 2, - BLEND_MAX_DST_SRC = 3, - BLEND_DST_MINUS_SRC = 4, - BLEND_DST_PLUS_SRC_BIAS = 5, + BLEND2_DST_PLUS_SRC = 0, + BLEND2_SRC_MINUS_DST = 1, + BLEND2_MIN_DST_SRC = 2, + BLEND2_MAX_DST_SRC = 3, + BLEND2_DST_MINUS_SRC = 4, + BLEND2_DST_PLUS_SRC_BIAS = 5, }; enum adreno_mmu_clnt_beh { diff --git a/drivers/gpu/drm/msm/adreno/a3xx.xml.h b/drivers/gpu/drm/msm/adreno/a3xx.xml.h index 27dabd5e57fb..a066c8b9eccd 100644 --- a/drivers/gpu/drm/msm/adreno/a3xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a3xx.xml.h @@ -8,13 +8,14 @@ http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31) +- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2016-04-26 17:56:44) - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 11518 bytes, from 2016-02-10 21:03:25) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 16166 bytes, from 2016-02-11 21:20:31) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83967 bytes, from 2016-02-10 17:07:21) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 109916 bytes, from 2016-02-20 18:44:48) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32907 bytes, from 2016-11-26 23:01:08) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2016-11-26 23:01:08) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 22544 bytes, from 2016-11-26 23:01:08) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2016-11-26 23:01:08) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110765 bytes, from 2016-11-26 23:01:48) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 90321 bytes, from 2016-11-28 16:50:05) - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00) Copyright (C) 2013-2016 by the following authors: @@ -129,10 +130,14 @@ enum a3xx_tex_fmt { TFMT_Z16_UNORM = 9, TFMT_X8Z24_UNORM = 10, TFMT_Z32_FLOAT = 11, - TFMT_NV12_UV_TILED = 17, - TFMT_NV12_Y_TILED = 19, - TFMT_NV12_UV = 21, - TFMT_NV12_Y = 23, + TFMT_UV_64X32 = 16, + TFMT_VU_64X32 = 17, + TFMT_Y_64X32 = 18, + TFMT_NV12_64X32 = 19, + TFMT_UV_LINEAR = 20, + TFMT_VU_LINEAR = 21, + TFMT_Y_LINEAR = 22, + TFMT_NV12_LINEAR = 23, TFMT_I420_Y = 24, TFMT_I420_U = 26, TFMT_I420_V = 27, @@ -525,14 +530,6 @@ enum a3xx_uche_perfcounter_select { UCHE_UCHEPERF_ACTIVE_CYCLES = 20, }; -enum a3xx_rb_blend_opcode { - BLEND_DST_PLUS_SRC = 0, - BLEND_SRC_MINUS_DST = 1, - BLEND_DST_MINUS_SRC = 2, - BLEND_MIN_DST_SRC = 3, - BLEND_MAX_DST_SRC = 4, -}; - enum a3xx_intp_mode { SMOOTH = 0, FLAT = 1, @@ -1393,13 +1390,14 @@ static inline uint32_t A3XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mod { return ((val) << A3XX_RB_COPY_CONTROL_MODE__SHIFT) & A3XX_RB_COPY_CONTROL_MODE__MASK; } +#define A3XX_RB_COPY_CONTROL_MSAA_SRGB_DOWNSAMPLE 0x00000080 #define A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK 0x00000f00 #define A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT 8 static inline uint32_t A3XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val) { return ((val) << A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK; } -#define A3XX_RB_COPY_CONTROL_UNK12 0x00001000 +#define A3XX_RB_COPY_CONTROL_DEPTH32_RESOLVE 0x00001000 #define A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xffffc000 #define A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14 static inline uint32_t A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) @@ -1472,7 +1470,7 @@ static inline uint32_t A3XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val) { return ((val) << A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK; } -#define A3XX_RB_DEPTH_CONTROL_BF_ENABLE 0x00000080 +#define A3XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE 0x00000080 #define A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000 #define REG_A3XX_RB_DEPTH_CLEAR 0x00002101 diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c index fd266ed963b6..b999349b7d2d 100644 --- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c @@ -41,7 +41,7 @@ extern bool hang_debug; static void a3xx_dump(struct msm_gpu *gpu); -static void a3xx_me_init(struct msm_gpu *gpu) +static bool a3xx_me_init(struct msm_gpu *gpu) { struct msm_ringbuffer *ring = gpu->rb; @@ -65,7 +65,7 @@ static void a3xx_me_init(struct msm_gpu *gpu) OUT_RING(ring, 0x00000000); gpu->funcs->flush(gpu); - gpu->funcs->idle(gpu); + return gpu->funcs->idle(gpu); } static int a3xx_hw_init(struct msm_gpu *gpu) @@ -294,15 +294,20 @@ static int a3xx_hw_init(struct msm_gpu *gpu) /* clear ME_HALT to start micro engine */ gpu_write(gpu, REG_AXXX_CP_ME_CNTL, 0); - a3xx_me_init(gpu); - - return 0; + return a3xx_me_init(gpu) ? 0 : -EINVAL; } static void a3xx_recover(struct msm_gpu *gpu) { + int i; + adreno_dump_info(gpu); + for (i = 0; i < 8; i++) { + printk("CP_SCRATCH_REG%d: %u\n", i, + gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i)); + } + /* dump registers before resetting gpu, if enabled: */ if (hang_debug) a3xx_dump(gpu); @@ -330,17 +335,22 @@ static void a3xx_destroy(struct msm_gpu *gpu) kfree(a3xx_gpu); } -static void a3xx_idle(struct msm_gpu *gpu) +static bool a3xx_idle(struct msm_gpu *gpu) { /* wait for ringbuffer to drain: */ - adreno_idle(gpu); + if (!adreno_idle(gpu)) + return false; /* then wait for GPU to finish: */ if (spin_until(!(gpu_read(gpu, REG_A3XX_RBBM_STATUS) & - A3XX_RBBM_STATUS_GPU_BUSY))) + A3XX_RBBM_STATUS_GPU_BUSY))) { DRM_ERROR("%s: timeout waiting for GPU to idle!\n", gpu->name); - /* TODO maybe we need to reset GPU here to recover from hang? */ + /* TODO maybe we need to reset GPU here to recover from hang? */ + return false; + } + + return true; } static irqreturn_t a3xx_irq(struct msm_gpu *gpu) @@ -419,91 +429,13 @@ static void a3xx_dump(struct msm_gpu *gpu) } /* Register offset defines for A3XX */ static const unsigned int a3xx_register_offsets[REG_ADRENO_REGISTER_MAX] = { - REG_ADRENO_DEFINE(REG_ADRENO_CP_DEBUG, REG_AXXX_CP_DEBUG), - REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_RAM_WADDR, REG_AXXX_CP_ME_RAM_WADDR), - REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_RAM_DATA, REG_AXXX_CP_ME_RAM_DATA), - REG_ADRENO_DEFINE(REG_ADRENO_CP_PFP_UCODE_DATA, - REG_A3XX_CP_PFP_UCODE_DATA), - REG_ADRENO_DEFINE(REG_ADRENO_CP_PFP_UCODE_ADDR, - REG_A3XX_CP_PFP_UCODE_ADDR), - REG_ADRENO_DEFINE(REG_ADRENO_CP_WFI_PEND_CTR, REG_A3XX_CP_WFI_PEND_CTR), REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_BASE, REG_AXXX_CP_RB_BASE), + REG_ADRENO_SKIP(REG_ADRENO_CP_RB_BASE_HI), REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR_ADDR, REG_AXXX_CP_RB_RPTR_ADDR), + REG_ADRENO_SKIP(REG_ADRENO_CP_RB_RPTR_ADDR_HI), REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR, REG_AXXX_CP_RB_RPTR), REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_WPTR, REG_AXXX_CP_RB_WPTR), - REG_ADRENO_DEFINE(REG_ADRENO_CP_PROTECT_CTRL, REG_A3XX_CP_PROTECT_CTRL), - REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_CNTL, REG_AXXX_CP_ME_CNTL), REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_CNTL, REG_AXXX_CP_RB_CNTL), - REG_ADRENO_DEFINE(REG_ADRENO_CP_IB1_BASE, REG_AXXX_CP_IB1_BASE), - REG_ADRENO_DEFINE(REG_ADRENO_CP_IB1_BUFSZ, REG_AXXX_CP_IB1_BUFSZ), - REG_ADRENO_DEFINE(REG_ADRENO_CP_IB2_BASE, REG_AXXX_CP_IB2_BASE), - REG_ADRENO_DEFINE(REG_ADRENO_CP_IB2_BUFSZ, REG_AXXX_CP_IB2_BUFSZ), - REG_ADRENO_DEFINE(REG_ADRENO_CP_TIMESTAMP, REG_AXXX_CP_SCRATCH_REG0), - REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_RAM_RADDR, REG_AXXX_CP_ME_RAM_RADDR), - REG_ADRENO_DEFINE(REG_ADRENO_SCRATCH_ADDR, REG_AXXX_SCRATCH_ADDR), - REG_ADRENO_DEFINE(REG_ADRENO_SCRATCH_UMSK, REG_AXXX_SCRATCH_UMSK), - REG_ADRENO_DEFINE(REG_ADRENO_CP_ROQ_ADDR, REG_A3XX_CP_ROQ_ADDR), - REG_ADRENO_DEFINE(REG_ADRENO_CP_ROQ_DATA, REG_A3XX_CP_ROQ_DATA), - REG_ADRENO_DEFINE(REG_ADRENO_CP_MERCIU_ADDR, REG_A3XX_CP_MERCIU_ADDR), - REG_ADRENO_DEFINE(REG_ADRENO_CP_MERCIU_DATA, REG_A3XX_CP_MERCIU_DATA), - REG_ADRENO_DEFINE(REG_ADRENO_CP_MERCIU_DATA2, REG_A3XX_CP_MERCIU_DATA2), - REG_ADRENO_DEFINE(REG_ADRENO_CP_MEQ_ADDR, REG_A3XX_CP_MEQ_ADDR), - REG_ADRENO_DEFINE(REG_ADRENO_CP_MEQ_DATA, REG_A3XX_CP_MEQ_DATA), - REG_ADRENO_DEFINE(REG_ADRENO_CP_HW_FAULT, REG_A3XX_CP_HW_FAULT), - REG_ADRENO_DEFINE(REG_ADRENO_CP_PROTECT_STATUS, - REG_A3XX_CP_PROTECT_STATUS), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_STATUS, REG_A3XX_RBBM_STATUS), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_CTL, - REG_A3XX_RBBM_PERFCTR_CTL), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_LOAD_CMD0, - REG_A3XX_RBBM_PERFCTR_LOAD_CMD0), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_LOAD_CMD1, - REG_A3XX_RBBM_PERFCTR_LOAD_CMD1), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_PWR_1_LO, - REG_A3XX_RBBM_PERFCTR_PWR_1_LO), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_INT_0_MASK, REG_A3XX_RBBM_INT_0_MASK), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_INT_0_STATUS, - REG_A3XX_RBBM_INT_0_STATUS), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_AHB_ERROR_STATUS, - REG_A3XX_RBBM_AHB_ERROR_STATUS), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_AHB_CMD, REG_A3XX_RBBM_AHB_CMD), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_INT_CLEAR_CMD, - REG_A3XX_RBBM_INT_CLEAR_CMD), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_CLOCK_CTL, REG_A3XX_RBBM_CLOCK_CTL), - REG_ADRENO_DEFINE(REG_ADRENO_VPC_DEBUG_RAM_SEL, - REG_A3XX_VPC_VPC_DEBUG_RAM_SEL), - REG_ADRENO_DEFINE(REG_ADRENO_VPC_DEBUG_RAM_READ, - REG_A3XX_VPC_VPC_DEBUG_RAM_READ), - REG_ADRENO_DEFINE(REG_ADRENO_VSC_SIZE_ADDRESS, - REG_A3XX_VSC_SIZE_ADDRESS), - REG_ADRENO_DEFINE(REG_ADRENO_VFD_CONTROL_0, REG_A3XX_VFD_CONTROL_0), - REG_ADRENO_DEFINE(REG_ADRENO_VFD_INDEX_MAX, REG_A3XX_VFD_INDEX_MAX), - REG_ADRENO_DEFINE(REG_ADRENO_SP_VS_PVT_MEM_ADDR_REG, - REG_A3XX_SP_VS_PVT_MEM_ADDR_REG), - REG_ADRENO_DEFINE(REG_ADRENO_SP_FS_PVT_MEM_ADDR_REG, - REG_A3XX_SP_FS_PVT_MEM_ADDR_REG), - REG_ADRENO_DEFINE(REG_ADRENO_SP_VS_OBJ_START_REG, - REG_A3XX_SP_VS_OBJ_START_REG), - REG_ADRENO_DEFINE(REG_ADRENO_SP_FS_OBJ_START_REG, - REG_A3XX_SP_FS_OBJ_START_REG), - REG_ADRENO_DEFINE(REG_ADRENO_PA_SC_AA_CONFIG, REG_A3XX_PA_SC_AA_CONFIG), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PM_OVERRIDE2, - REG_A3XX_RBBM_PM_OVERRIDE2), - REG_ADRENO_DEFINE(REG_ADRENO_SCRATCH_REG2, REG_AXXX_CP_SCRATCH_REG2), - REG_ADRENO_DEFINE(REG_ADRENO_SQ_GPR_MANAGEMENT, - REG_A3XX_SQ_GPR_MANAGEMENT), - REG_ADRENO_DEFINE(REG_ADRENO_SQ_INST_STORE_MANAGMENT, - REG_A3XX_SQ_INST_STORE_MANAGMENT), - REG_ADRENO_DEFINE(REG_ADRENO_TP0_CHICKEN, REG_A3XX_TP0_CHICKEN), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_RBBM_CTL, REG_A3XX_RBBM_RBBM_CTL), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_SW_RESET_CMD, - REG_A3XX_RBBM_SW_RESET_CMD), - REG_ADRENO_DEFINE(REG_ADRENO_UCHE_INVALIDATE0, - REG_A3XX_UCHE_CACHE_INVALIDATE0_REG), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_LOAD_VALUE_LO, - REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_LO), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_LOAD_VALUE_HI, - REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_HI), }; static const struct adreno_gpu_funcs funcs = { @@ -583,7 +515,7 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev) #endif } - if (!gpu->mmu) { + if (!gpu->aspace) { /* TODO we think it is possible to configure the GPU to * restrict access to VRAM carveout. But the required * registers are unknown. For now just bail out and diff --git a/drivers/gpu/drm/msm/adreno/a4xx.xml.h b/drivers/gpu/drm/msm/adreno/a4xx.xml.h index 3220b91f559a..4ce21b902779 100644 --- a/drivers/gpu/drm/msm/adreno/a4xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a4xx.xml.h @@ -8,13 +8,14 @@ http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31) +- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2016-04-26 17:56:44) - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 11518 bytes, from 2016-02-10 21:03:25) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 16166 bytes, from 2016-02-11 21:20:31) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83967 bytes, from 2016-02-10 17:07:21) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 109916 bytes, from 2016-02-20 18:44:48) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32907 bytes, from 2016-11-26 23:01:08) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2016-11-26 23:01:08) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 22544 bytes, from 2016-11-26 23:01:08) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2016-11-26 23:01:08) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110765 bytes, from 2016-11-26 23:01:48) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 90321 bytes, from 2016-11-28 16:50:05) - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00) Copyright (C) 2013-2016 by the following authors: @@ -46,6 +47,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. enum a4xx_color_fmt { RB4_A8_UNORM = 1, RB4_R8_UNORM = 2, + RB4_R8_SNORM = 3, + RB4_R8_UINT = 4, + RB4_R8_SINT = 5, RB4_R4G4B4A4_UNORM = 8, RB4_R5G5B5A1_UNORM = 10, RB4_R5G6B5_UNORM = 14, @@ -89,17 +93,10 @@ enum a4xx_color_fmt { enum a4xx_tile_mode { TILE4_LINEAR = 0, + TILE4_2 = 2, TILE4_3 = 3, }; -enum a4xx_rb_blend_opcode { - BLEND_DST_PLUS_SRC = 0, - BLEND_SRC_MINUS_DST = 1, - BLEND_DST_MINUS_SRC = 2, - BLEND_MIN_DST_SRC = 3, - BLEND_MAX_DST_SRC = 4, -}; - enum a4xx_vtx_fmt { VFMT4_32_FLOAT = 1, VFMT4_32_32_FLOAT = 2, @@ -940,6 +937,7 @@ static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val) { return ((val >> 5) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK; } +#define A4XX_RB_MODE_CONTROL_ENABLE_GMEM 0x00010000 #define REG_A4XX_RB_RENDER_CONTROL 0x000020a1 #define A4XX_RB_RENDER_CONTROL_BINNING_PASS 0x00000001 @@ -1043,7 +1041,7 @@ static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_b } #define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5 -static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a4xx_rb_blend_opcode val) +static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) { return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; } @@ -1061,7 +1059,7 @@ static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb } #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21 -static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a4xx_rb_blend_opcode val) +static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) { return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; } @@ -1073,12 +1071,18 @@ static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_r } #define REG_A4XX_RB_BLEND_RED 0x000020f0 -#define A4XX_RB_BLEND_RED_UINT__MASK 0x0000ffff +#define A4XX_RB_BLEND_RED_UINT__MASK 0x000000ff #define A4XX_RB_BLEND_RED_UINT__SHIFT 0 static inline uint32_t A4XX_RB_BLEND_RED_UINT(uint32_t val) { return ((val) << A4XX_RB_BLEND_RED_UINT__SHIFT) & A4XX_RB_BLEND_RED_UINT__MASK; } +#define A4XX_RB_BLEND_RED_SINT__MASK 0x0000ff00 +#define A4XX_RB_BLEND_RED_SINT__SHIFT 8 +static inline uint32_t A4XX_RB_BLEND_RED_SINT(uint32_t val) +{ + return ((val) << A4XX_RB_BLEND_RED_SINT__SHIFT) & A4XX_RB_BLEND_RED_SINT__MASK; +} #define A4XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000 #define A4XX_RB_BLEND_RED_FLOAT__SHIFT 16 static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val) @@ -1095,12 +1099,18 @@ static inline uint32_t A4XX_RB_BLEND_RED_F32(float val) } #define REG_A4XX_RB_BLEND_GREEN 0x000020f2 -#define A4XX_RB_BLEND_GREEN_UINT__MASK 0x0000ffff +#define A4XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff #define A4XX_RB_BLEND_GREEN_UINT__SHIFT 0 static inline uint32_t A4XX_RB_BLEND_GREEN_UINT(uint32_t val) { return ((val) << A4XX_RB_BLEND_GREEN_UINT__SHIFT) & A4XX_RB_BLEND_GREEN_UINT__MASK; } +#define A4XX_RB_BLEND_GREEN_SINT__MASK 0x0000ff00 +#define A4XX_RB_BLEND_GREEN_SINT__SHIFT 8 +static inline uint32_t A4XX_RB_BLEND_GREEN_SINT(uint32_t val) +{ + return ((val) << A4XX_RB_BLEND_GREEN_SINT__SHIFT) & A4XX_RB_BLEND_GREEN_SINT__MASK; +} #define A4XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000 #define A4XX_RB_BLEND_GREEN_FLOAT__SHIFT 16 static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val) @@ -1117,12 +1127,18 @@ static inline uint32_t A4XX_RB_BLEND_GREEN_F32(float val) } #define REG_A4XX_RB_BLEND_BLUE 0x000020f4 -#define A4XX_RB_BLEND_BLUE_UINT__MASK 0x0000ffff +#define A4XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff #define A4XX_RB_BLEND_BLUE_UINT__SHIFT 0 static inline uint32_t A4XX_RB_BLEND_BLUE_UINT(uint32_t val) { return ((val) << A4XX_RB_BLEND_BLUE_UINT__SHIFT) & A4XX_RB_BLEND_BLUE_UINT__MASK; } +#define A4XX_RB_BLEND_BLUE_SINT__MASK 0x0000ff00 +#define A4XX_RB_BLEND_BLUE_SINT__SHIFT 8 +static inline uint32_t A4XX_RB_BLEND_BLUE_SINT(uint32_t val) +{ + return ((val) << A4XX_RB_BLEND_BLUE_SINT__SHIFT) & A4XX_RB_BLEND_BLUE_SINT__MASK; +} #define A4XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000 #define A4XX_RB_BLEND_BLUE_FLOAT__SHIFT 16 static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val) @@ -1139,12 +1155,18 @@ static inline uint32_t A4XX_RB_BLEND_BLUE_F32(float val) } #define REG_A4XX_RB_BLEND_ALPHA 0x000020f6 -#define A4XX_RB_BLEND_ALPHA_UINT__MASK 0x0000ffff +#define A4XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff #define A4XX_RB_BLEND_ALPHA_UINT__SHIFT 0 static inline uint32_t A4XX_RB_BLEND_ALPHA_UINT(uint32_t val) { return ((val) << A4XX_RB_BLEND_ALPHA_UINT__SHIFT) & A4XX_RB_BLEND_ALPHA_UINT__MASK; } +#define A4XX_RB_BLEND_ALPHA_SINT__MASK 0x0000ff00 +#define A4XX_RB_BLEND_ALPHA_SINT__SHIFT 8 +static inline uint32_t A4XX_RB_BLEND_ALPHA_SINT(uint32_t val) +{ + return ((val) << A4XX_RB_BLEND_ALPHA_SINT__SHIFT) & A4XX_RB_BLEND_ALPHA_SINT__MASK; +} #define A4XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000 #define A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16 static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val) @@ -1348,7 +1370,7 @@ static inline uint32_t A4XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val) { return ((val) << A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK; } -#define A4XX_RB_DEPTH_CONTROL_BF_ENABLE 0x00000080 +#define A4XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE 0x00000080 #define A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00010000 #define A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS 0x00020000 #define A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000 @@ -2177,11 +2199,23 @@ static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) #define REG_A4XX_CP_DRAW_STATE_ADDR 0x00000232 -#define REG_A4XX_CP_PROTECT_REG_0 0x00000240 - static inline uint32_t REG_A4XX_CP_PROTECT(uint32_t i0) { return 0x00000240 + 0x1*i0; } static inline uint32_t REG_A4XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000240 + 0x1*i0; } +#define A4XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0001ffff +#define A4XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0 +static inline uint32_t A4XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) +{ + return ((val) << A4XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A4XX_CP_PROTECT_REG_BASE_ADDR__MASK; +} +#define A4XX_CP_PROTECT_REG_MASK_LEN__MASK 0x1f000000 +#define A4XX_CP_PROTECT_REG_MASK_LEN__SHIFT 24 +static inline uint32_t A4XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) +{ + return ((val) << A4XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A4XX_CP_PROTECT_REG_MASK_LEN__MASK; +} +#define A4XX_CP_PROTECT_REG_TRAP_WRITE 0x20000000 +#define A4XX_CP_PROTECT_REG_TRAP_READ 0x40000000 #define REG_A4XX_CP_PROTECT_CTRL 0x00000250 @@ -2272,7 +2306,7 @@ static inline uint32_t A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) { return ((val) << A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; } -#define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00 +#define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 #define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 static inline uint32_t A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) { @@ -2420,7 +2454,7 @@ static inline uint32_t A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) { return ((val) << A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; } -#define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00 +#define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 #define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 static inline uint32_t A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) { @@ -3117,6 +3151,8 @@ static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_GS(uint32_t val) #define REG_A4XX_GRAS_CL_CLIP_CNTL 0x00002000 #define A4XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE 0x00008000 +#define A4XX_GRAS_CL_CLIP_CNTL_ZNEAR_CLIP_DISABLE 0x00010000 +#define A4XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE 0x00020000 #define A4XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z 0x00400000 #define REG_A4XX_GRAS_CLEAR_CNTL 0x00002003 @@ -3253,6 +3289,7 @@ static inline uint32_t A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val) return ((((int32_t)(val * 4.0))) << A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK; } #define A4XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800 +#define A4XX_GRAS_SU_MODE_CONTROL_MSAA_ENABLE 0x00002000 #define A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS 0x00100000 #define REG_A4XX_GRAS_SC_CONTROL 0x0000207b @@ -3670,6 +3707,8 @@ static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val) #define REG_A4XX_PC_BINNING_COMMAND 0x00000d00 #define A4XX_PC_BINNING_COMMAND_BINNING_ENABLE 0x00000001 +#define REG_A4XX_PC_TESSFACTOR_ADDR 0x00000d08 + #define REG_A4XX_PC_DRAWCALL_SETUP_OVERRIDE 0x00000d0c #define REG_A4XX_PC_PERFCTR_PC_SEL_0 0x00000d10 @@ -3690,6 +3729,20 @@ static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val) #define REG_A4XX_PC_BIN_BASE 0x000021c0 +#define REG_A4XX_PC_VSTREAM_CONTROL 0x000021c2 +#define A4XX_PC_VSTREAM_CONTROL_SIZE__MASK 0x003f0000 +#define A4XX_PC_VSTREAM_CONTROL_SIZE__SHIFT 16 +static inline uint32_t A4XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val) +{ + return ((val) << A4XX_PC_VSTREAM_CONTROL_SIZE__SHIFT) & A4XX_PC_VSTREAM_CONTROL_SIZE__MASK; +} +#define A4XX_PC_VSTREAM_CONTROL_N__MASK 0x07c00000 +#define A4XX_PC_VSTREAM_CONTROL_N__SHIFT 22 +static inline uint32_t A4XX_PC_VSTREAM_CONTROL_N(uint32_t val) +{ + return ((val) << A4XX_PC_VSTREAM_CONTROL_N__SHIFT) & A4XX_PC_VSTREAM_CONTROL_N__MASK; +} + #define REG_A4XX_PC_PRIM_VTX_CNTL 0x000021c4 #define A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK 0x0000000f #define A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT 0 @@ -3752,12 +3805,8 @@ static inline uint32_t A4XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val) { return ((val) << A4XX_PC_HS_PARAM_SPACING__SHIFT) & A4XX_PC_HS_PARAM_SPACING__MASK; } -#define A4XX_PC_HS_PARAM_PRIMTYPE__MASK 0x01800000 -#define A4XX_PC_HS_PARAM_PRIMTYPE__SHIFT 23 -static inline uint32_t A4XX_PC_HS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val) -{ - return ((val) << A4XX_PC_HS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_HS_PARAM_PRIMTYPE__MASK; -} +#define A4XX_PC_HS_PARAM_CW 0x00800000 +#define A4XX_PC_HS_PARAM_CONNECTED 0x01000000 #define REG_A4XX_VBIF_VERSION 0x00003000 diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c index d0d3c7baa8fe..511bc855cc7f 100644 --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c @@ -113,7 +113,7 @@ static void a4xx_enable_hwcg(struct msm_gpu *gpu) } -static void a4xx_me_init(struct msm_gpu *gpu) +static bool a4xx_me_init(struct msm_gpu *gpu) { struct msm_ringbuffer *ring = gpu->rb; @@ -137,7 +137,7 @@ static void a4xx_me_init(struct msm_gpu *gpu) OUT_RING(ring, 0x00000000); gpu->funcs->flush(gpu); - gpu->funcs->idle(gpu); + return gpu->funcs->idle(gpu); } static int a4xx_hw_init(struct msm_gpu *gpu) @@ -292,15 +292,20 @@ static int a4xx_hw_init(struct msm_gpu *gpu) /* clear ME_HALT to start micro engine */ gpu_write(gpu, REG_A4XX_CP_ME_CNTL, 0); - a4xx_me_init(gpu); - - return 0; + return a4xx_me_init(gpu) ? 0 : -EINVAL; } static void a4xx_recover(struct msm_gpu *gpu) { + int i; + adreno_dump_info(gpu); + for (i = 0; i < 8; i++) { + printk("CP_SCRATCH_REG%d: %u\n", i, + gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i)); + } + /* dump registers before resetting gpu, if enabled: */ if (hang_debug) a4xx_dump(gpu); @@ -328,17 +333,21 @@ static void a4xx_destroy(struct msm_gpu *gpu) kfree(a4xx_gpu); } -static void a4xx_idle(struct msm_gpu *gpu) +static bool a4xx_idle(struct msm_gpu *gpu) { /* wait for ringbuffer to drain: */ - adreno_idle(gpu); + if (!adreno_idle(gpu)) + return false; /* then wait for GPU to finish: */ if (spin_until(!(gpu_read(gpu, REG_A4XX_RBBM_STATUS) & - A4XX_RBBM_STATUS_GPU_BUSY))) + A4XX_RBBM_STATUS_GPU_BUSY))) { DRM_ERROR("%s: timeout waiting for GPU to idle!\n", gpu->name); + /* TODO maybe we need to reset GPU here to recover from hang? */ + return false; + } - /* TODO maybe we need to reset GPU here to recover from hang? */ + return true; } static irqreturn_t a4xx_irq(struct msm_gpu *gpu) @@ -460,87 +469,13 @@ static void a4xx_show(struct msm_gpu *gpu, struct seq_file *m) /* Register offset defines for A4XX, in order of enum adreno_regs */ static const unsigned int a4xx_register_offsets[REG_ADRENO_REGISTER_MAX] = { - REG_ADRENO_DEFINE(REG_ADRENO_CP_DEBUG, REG_A4XX_CP_DEBUG), - REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_RAM_WADDR, REG_A4XX_CP_ME_RAM_WADDR), - REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_RAM_DATA, REG_A4XX_CP_ME_RAM_DATA), - REG_ADRENO_DEFINE(REG_ADRENO_CP_PFP_UCODE_DATA, - REG_A4XX_CP_PFP_UCODE_DATA), - REG_ADRENO_DEFINE(REG_ADRENO_CP_PFP_UCODE_ADDR, - REG_A4XX_CP_PFP_UCODE_ADDR), - REG_ADRENO_DEFINE(REG_ADRENO_CP_WFI_PEND_CTR, REG_A4XX_CP_WFI_PEND_CTR), REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_BASE, REG_A4XX_CP_RB_BASE), + REG_ADRENO_SKIP(REG_ADRENO_CP_RB_BASE_HI), REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR_ADDR, REG_A4XX_CP_RB_RPTR_ADDR), + REG_ADRENO_SKIP(REG_ADRENO_CP_RB_RPTR_ADDR_HI), REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR, REG_A4XX_CP_RB_RPTR), REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_WPTR, REG_A4XX_CP_RB_WPTR), - REG_ADRENO_DEFINE(REG_ADRENO_CP_PROTECT_CTRL, REG_A4XX_CP_PROTECT_CTRL), - REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_CNTL, REG_A4XX_CP_ME_CNTL), REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_CNTL, REG_A4XX_CP_RB_CNTL), - REG_ADRENO_DEFINE(REG_ADRENO_CP_IB1_BASE, REG_A4XX_CP_IB1_BASE), - REG_ADRENO_DEFINE(REG_ADRENO_CP_IB1_BUFSZ, REG_A4XX_CP_IB1_BUFSZ), - REG_ADRENO_DEFINE(REG_ADRENO_CP_IB2_BASE, REG_A4XX_CP_IB2_BASE), - REG_ADRENO_DEFINE(REG_ADRENO_CP_IB2_BUFSZ, REG_A4XX_CP_IB2_BUFSZ), - REG_ADRENO_DEFINE(REG_ADRENO_CP_TIMESTAMP, REG_AXXX_CP_SCRATCH_REG0), - REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_RAM_RADDR, REG_A4XX_CP_ME_RAM_RADDR), - REG_ADRENO_DEFINE(REG_ADRENO_CP_ROQ_ADDR, REG_A4XX_CP_ROQ_ADDR), - REG_ADRENO_DEFINE(REG_ADRENO_CP_ROQ_DATA, REG_A4XX_CP_ROQ_DATA), - REG_ADRENO_DEFINE(REG_ADRENO_CP_MERCIU_ADDR, REG_A4XX_CP_MERCIU_ADDR), - REG_ADRENO_DEFINE(REG_ADRENO_CP_MERCIU_DATA, REG_A4XX_CP_MERCIU_DATA), - REG_ADRENO_DEFINE(REG_ADRENO_CP_MERCIU_DATA2, REG_A4XX_CP_MERCIU_DATA2), - REG_ADRENO_DEFINE(REG_ADRENO_CP_MEQ_ADDR, REG_A4XX_CP_MEQ_ADDR), - REG_ADRENO_DEFINE(REG_ADRENO_CP_MEQ_DATA, REG_A4XX_CP_MEQ_DATA), - REG_ADRENO_DEFINE(REG_ADRENO_CP_HW_FAULT, REG_A4XX_CP_HW_FAULT), - REG_ADRENO_DEFINE(REG_ADRENO_CP_PROTECT_STATUS, - REG_A4XX_CP_PROTECT_STATUS), - REG_ADRENO_DEFINE(REG_ADRENO_SCRATCH_ADDR, REG_A4XX_CP_SCRATCH_ADDR), - REG_ADRENO_DEFINE(REG_ADRENO_SCRATCH_UMSK, REG_A4XX_CP_SCRATCH_UMASK), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_STATUS, REG_A4XX_RBBM_STATUS), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_CTL, - REG_A4XX_RBBM_PERFCTR_CTL), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_LOAD_CMD0, - REG_A4XX_RBBM_PERFCTR_LOAD_CMD0), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_LOAD_CMD1, - REG_A4XX_RBBM_PERFCTR_LOAD_CMD1), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_LOAD_CMD2, - REG_A4XX_RBBM_PERFCTR_LOAD_CMD2), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_PWR_1_LO, - REG_A4XX_RBBM_PERFCTR_PWR_1_LO), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_INT_0_MASK, REG_A4XX_RBBM_INT_0_MASK), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_INT_0_STATUS, - REG_A4XX_RBBM_INT_0_STATUS), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_AHB_ERROR_STATUS, - REG_A4XX_RBBM_AHB_ERROR_STATUS), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_AHB_CMD, REG_A4XX_RBBM_AHB_CMD), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_CLOCK_CTL, REG_A4XX_RBBM_CLOCK_CTL), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_AHB_ME_SPLIT_STATUS, - REG_A4XX_RBBM_AHB_ME_SPLIT_STATUS), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_AHB_PFP_SPLIT_STATUS, - REG_A4XX_RBBM_AHB_PFP_SPLIT_STATUS), - REG_ADRENO_DEFINE(REG_ADRENO_VPC_DEBUG_RAM_SEL, - REG_A4XX_VPC_DEBUG_RAM_SEL), - REG_ADRENO_DEFINE(REG_ADRENO_VPC_DEBUG_RAM_READ, - REG_A4XX_VPC_DEBUG_RAM_READ), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_INT_CLEAR_CMD, - REG_A4XX_RBBM_INT_CLEAR_CMD), - REG_ADRENO_DEFINE(REG_ADRENO_VSC_SIZE_ADDRESS, - REG_A4XX_VSC_SIZE_ADDRESS), - REG_ADRENO_DEFINE(REG_ADRENO_VFD_CONTROL_0, REG_A4XX_VFD_CONTROL_0), - REG_ADRENO_DEFINE(REG_ADRENO_SP_VS_PVT_MEM_ADDR_REG, - REG_A4XX_SP_VS_PVT_MEM_ADDR), - REG_ADRENO_DEFINE(REG_ADRENO_SP_FS_PVT_MEM_ADDR_REG, - REG_A4XX_SP_FS_PVT_MEM_ADDR), - REG_ADRENO_DEFINE(REG_ADRENO_SP_VS_OBJ_START_REG, - REG_A4XX_SP_VS_OBJ_START), - REG_ADRENO_DEFINE(REG_ADRENO_SP_FS_OBJ_START_REG, - REG_A4XX_SP_FS_OBJ_START), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_RBBM_CTL, REG_A4XX_RBBM_RBBM_CTL), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_SW_RESET_CMD, - REG_A4XX_RBBM_SW_RESET_CMD), - REG_ADRENO_DEFINE(REG_ADRENO_UCHE_INVALIDATE0, - REG_A4XX_UCHE_INVALIDATE0), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_LOAD_VALUE_LO, - REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_LO), - REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_LOAD_VALUE_HI, - REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_HI), }; static void a4xx_dump(struct msm_gpu *gpu) @@ -587,16 +522,8 @@ static int a4xx_pm_suspend(struct msm_gpu *gpu) { static int a4xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) { - uint32_t hi, lo, tmp; - - tmp = gpu_read(gpu, REG_A4XX_RBBM_PERFCTR_CP_0_HI); - do { - hi = tmp; - lo = gpu_read(gpu, REG_A4XX_RBBM_PERFCTR_CP_0_LO); - tmp = gpu_read(gpu, REG_A4XX_RBBM_PERFCTR_CP_0_HI); - } while (tmp != hi); - - *value = (((uint64_t)hi) << 32) | lo; + *value = gpu_read64(gpu, REG_A4XX_RBBM_PERFCTR_CP_0_LO, + REG_A4XX_RBBM_PERFCTR_CP_0_HI); return 0; } @@ -672,7 +599,7 @@ struct msm_gpu *a4xx_gpu_init(struct drm_device *dev) #endif } - if (!gpu->mmu) { + if (!gpu->aspace) { /* TODO we think it is possible to configure the GPU to * restrict access to VRAM carveout. But the required * registers are unknown. For now just bail out and diff --git a/drivers/gpu/drm/msm/adreno/a5xx.xml.h b/drivers/gpu/drm/msm/adreno/a5xx.xml.h new file mode 100644 index 000000000000..b6fe763ddf34 --- /dev/null +++ b/drivers/gpu/drm/msm/adreno/a5xx.xml.h @@ -0,0 +1,3757 @@ +#ifndef A5XX_XML +#define A5XX_XML + +/* Autogenerated file, DO NOT EDIT manually! + +This file was generated by the rules-ng-ng headergen tool in this git repository: +http://github.com/freedreno/envytools/ +git clone https://github.com/freedreno/envytools.git + +The rules-ng-ng source files this header was generated from are: +- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2016-04-26 17:56:44) +- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32907 bytes, from 2016-11-26 23:01:08) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2016-11-26 23:01:08) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 22544 bytes, from 2016-11-26 23:01:08) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2016-11-26 23:01:08) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110765 bytes, from 2016-11-26 23:01:48) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 90321 bytes, from 2016-11-28 16:50:05) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00) + +Copyright (C) 2013-2016 by the following authors: +- Rob Clark <robdclark@gmail.com> (robclark) +- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + + +enum a5xx_color_fmt { + RB5_R8_UNORM = 3, + RB5_R4G4B4A4_UNORM = 8, + RB5_R5G5B5A1_UNORM = 10, + RB5_R5G6B5_UNORM = 14, + RB5_R16_FLOAT = 23, + RB5_R8G8B8A8_UNORM = 48, + RB5_R8G8B8_UNORM = 49, + RB5_R8G8B8A8_UINT = 51, + RB5_R10G10B10A2_UINT = 58, + RB5_R16G16_FLOAT = 69, + RB5_R32_FLOAT = 74, + RB5_R16G16B16A16_FLOAT = 98, + RB5_R32G32_FLOAT = 103, + RB5_R32G32B32A32_FLOAT = 130, +}; + +enum a5xx_tile_mode { + TILE5_LINEAR = 0, + TILE5_2 = 2, + TILE5_3 = 3, +}; + +enum a5xx_vtx_fmt { + VFMT5_8_UNORM = 3, + VFMT5_8_SNORM = 4, + VFMT5_8_UINT = 5, + VFMT5_8_SINT = 6, + VFMT5_8_8_UNORM = 15, + VFMT5_8_8_SNORM = 16, + VFMT5_8_8_UINT = 17, + VFMT5_8_8_SINT = 18, + VFMT5_16_UNORM = 21, + VFMT5_16_SNORM = 22, + VFMT5_16_FLOAT = 23, + VFMT5_16_UINT = 24, + VFMT5_16_SINT = 25, + VFMT5_8_8_8_UNORM = 33, + VFMT5_8_8_8_SNORM = 34, + VFMT5_8_8_8_UINT = 35, + VFMT5_8_8_8_SINT = 36, + VFMT5_8_8_8_8_UNORM = 48, + VFMT5_8_8_8_8_SNORM = 50, + VFMT5_8_8_8_8_UINT = 51, + VFMT5_8_8_8_8_SINT = 52, + VFMT5_16_16_UNORM = 67, + VFMT5_16_16_SNORM = 68, + VFMT5_16_16_FLOAT = 69, + VFMT5_16_16_UINT = 70, + VFMT5_16_16_SINT = 71, + VFMT5_32_UNORM = 72, + VFMT5_32_SNORM = 73, + VFMT5_32_FLOAT = 74, + VFMT5_32_UINT = 75, + VFMT5_32_SINT = 76, + VFMT5_32_FIXED = 77, + VFMT5_16_16_16_UNORM = 88, + VFMT5_16_16_16_SNORM = 89, + VFMT5_16_16_16_FLOAT = 90, + VFMT5_16_16_16_UINT = 91, + VFMT5_16_16_16_SINT = 92, + VFMT5_16_16_16_16_UNORM = 96, + VFMT5_16_16_16_16_SNORM = 97, + VFMT5_16_16_16_16_FLOAT = 98, + VFMT5_16_16_16_16_UINT = 99, + VFMT5_16_16_16_16_SINT = 100, + VFMT5_32_32_UNORM = 101, + VFMT5_32_32_SNORM = 102, + VFMT5_32_32_FLOAT = 103, + VFMT5_32_32_UINT = 104, + VFMT5_32_32_SINT = 105, + VFMT5_32_32_FIXED = 106, + VFMT5_32_32_32_UNORM = 112, + VFMT5_32_32_32_SNORM = 113, + VFMT5_32_32_32_UINT = 114, + VFMT5_32_32_32_SINT = 115, + VFMT5_32_32_32_FLOAT = 116, + VFMT5_32_32_32_FIXED = 117, + VFMT5_32_32_32_32_UNORM = 128, + VFMT5_32_32_32_32_SNORM = 129, + VFMT5_32_32_32_32_FLOAT = 130, + VFMT5_32_32_32_32_UINT = 131, + VFMT5_32_32_32_32_SINT = 132, + VFMT5_32_32_32_32_FIXED = 133, +}; + +enum a5xx_tex_fmt { + TFMT5_A8_UNORM = 2, + TFMT5_8_UNORM = 3, + TFMT5_4_4_4_4_UNORM = 8, + TFMT5_5_5_5_1_UNORM = 10, + TFMT5_5_6_5_UNORM = 14, + TFMT5_8_8_UNORM = 15, + TFMT5_8_8_SNORM = 16, + TFMT5_L8_A8_UNORM = 19, + TFMT5_16_FLOAT = 23, + TFMT5_8_8_8_8_UNORM = 48, + TFMT5_8_8_8_UNORM = 49, + TFMT5_8_8_8_SNORM = 50, + TFMT5_9_9_9_E5_FLOAT = 53, + TFMT5_10_10_10_2_UNORM = 54, + TFMT5_11_11_10_FLOAT = 66, + TFMT5_16_16_FLOAT = 69, + TFMT5_32_FLOAT = 74, + TFMT5_16_16_16_16_FLOAT = 98, + TFMT5_32_32_FLOAT = 103, + TFMT5_32_32_32_32_FLOAT = 130, + TFMT5_X8Z24_UNORM = 160, +}; + +enum a5xx_tex_fetchsize { + TFETCH5_1_BYTE = 0, + TFETCH5_2_BYTE = 1, + TFETCH5_4_BYTE = 2, + TFETCH5_8_BYTE = 3, + TFETCH5_16_BYTE = 4, +}; + +enum a5xx_depth_format { + DEPTH5_NONE = 0, + DEPTH5_16 = 1, + DEPTH5_24_8 = 2, + DEPTH5_32 = 4, +}; + +enum a5xx_blit_buf { + BLIT_MRT0 = 0, + BLIT_MRT1 = 1, + BLIT_MRT2 = 2, + BLIT_MRT3 = 3, + BLIT_MRT4 = 4, + BLIT_MRT5 = 5, + BLIT_MRT6 = 6, + BLIT_MRT7 = 7, + BLIT_ZS = 8, + BLIT_Z32 = 9, +}; + +enum a5xx_tex_filter { + A5XX_TEX_NEAREST = 0, + A5XX_TEX_LINEAR = 1, + A5XX_TEX_ANISO = 2, +}; + +enum a5xx_tex_clamp { + A5XX_TEX_REPEAT = 0, + A5XX_TEX_CLAMP_TO_EDGE = 1, + A5XX_TEX_MIRROR_REPEAT = 2, + A5XX_TEX_CLAMP_TO_BORDER = 3, + A5XX_TEX_MIRROR_CLAMP = 4, +}; + +enum a5xx_tex_aniso { + A5XX_TEX_ANISO_1 = 0, + A5XX_TEX_ANISO_2 = 1, + A5XX_TEX_ANISO_4 = 2, + A5XX_TEX_ANISO_8 = 3, + A5XX_TEX_ANISO_16 = 4, +}; + +enum a5xx_tex_swiz { + A5XX_TEX_X = 0, + A5XX_TEX_Y = 1, + A5XX_TEX_Z = 2, + A5XX_TEX_W = 3, + A5XX_TEX_ZERO = 4, + A5XX_TEX_ONE = 5, +}; + +enum a5xx_tex_type { + A5XX_TEX_1D = 0, + A5XX_TEX_2D = 1, + A5XX_TEX_CUBE = 2, + A5XX_TEX_3D = 3, +}; + +#define A5XX_INT0_RBBM_GPU_IDLE 0x00000001 +#define A5XX_INT0_RBBM_AHB_ERROR 0x00000002 +#define A5XX_INT0_RBBM_TRANSFER_TIMEOUT 0x00000004 +#define A5XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008 +#define A5XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010 +#define A5XX_INT0_RBBM_ETS_MS_TIMEOUT 0x00000020 +#define A5XX_INT0_RBBM_ATB_ASYNC_OVERFLOW 0x00000040 +#define A5XX_INT0_RBBM_GPC_ERROR 0x00000080 +#define A5XX_INT0_CP_SW 0x00000100 +#define A5XX_INT0_CP_HW_ERROR 0x00000200 +#define A5XX_INT0_CP_CCU_FLUSH_DEPTH_TS 0x00000400 +#define A5XX_INT0_CP_CCU_FLUSH_COLOR_TS 0x00000800 +#define A5XX_INT0_CP_CCU_RESOLVE_TS 0x00001000 +#define A5XX_INT0_CP_IB2 0x00002000 +#define A5XX_INT0_CP_IB1 0x00004000 +#define A5XX_INT0_CP_RB 0x00008000 +#define A5XX_INT0_CP_UNUSED_1 0x00010000 +#define A5XX_INT0_CP_RB_DONE_TS 0x00020000 +#define A5XX_INT0_CP_WT_DONE_TS 0x00040000 +#define A5XX_INT0_UNKNOWN_1 0x00080000 +#define A5XX_INT0_CP_CACHE_FLUSH_TS 0x00100000 +#define A5XX_INT0_UNUSED_2 0x00200000 +#define A5XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00400000 +#define A5XX_INT0_MISC_HANG_DETECT 0x00800000 +#define A5XX_INT0_UCHE_OOB_ACCESS 0x01000000 +#define A5XX_INT0_UCHE_TRAP_INTR 0x02000000 +#define A5XX_INT0_DEBBUS_INTR_0 0x04000000 +#define A5XX_INT0_DEBBUS_INTR_1 0x08000000 +#define A5XX_INT0_GPMU_VOLTAGE_DROOP 0x10000000 +#define A5XX_INT0_GPMU_FIRMWARE 0x20000000 +#define A5XX_INT0_ISDB_CPU_IRQ 0x40000000 +#define A5XX_INT0_ISDB_UNDER_DEBUG 0x80000000 +#define A5XX_CP_INT_CP_OPCODE_ERROR 0x00000001 +#define A5XX_CP_INT_CP_RESERVED_BIT_ERROR 0x00000002 +#define A5XX_CP_INT_CP_HW_FAULT_ERROR 0x00000004 +#define A5XX_CP_INT_CP_DMA_ERROR 0x00000008 +#define A5XX_CP_INT_CP_REGISTER_PROTECTION_ERROR 0x00000010 +#define A5XX_CP_INT_CP_AHB_ERROR 0x00000020 +#define REG_A5XX_CP_RB_BASE 0x00000800 + +#define REG_A5XX_CP_RB_BASE_HI 0x00000801 + +#define REG_A5XX_CP_RB_CNTL 0x00000802 + +#define REG_A5XX_CP_RB_RPTR_ADDR 0x00000804 + +#define REG_A5XX_CP_RB_RPTR_ADDR_HI 0x00000805 + +#define REG_A5XX_CP_RB_RPTR 0x00000806 + +#define REG_A5XX_CP_RB_WPTR 0x00000807 + +#define REG_A5XX_CP_PFP_STAT_ADDR 0x00000808 + +#define REG_A5XX_CP_PFP_STAT_DATA 0x00000809 + +#define REG_A5XX_CP_DRAW_STATE_ADDR 0x0000080b + +#define REG_A5XX_CP_DRAW_STATE_DATA 0x0000080c + +#define REG_A5XX_CP_CRASH_SCRIPT_BASE_LO 0x00000817 + +#define REG_A5XX_CP_CRASH_SCRIPT_BASE_HI 0x00000818 + +#define REG_A5XX_CP_CRASH_DUMP_CNTL 0x00000819 + +#define REG_A5XX_CP_ME_STAT_ADDR 0x0000081a + +#define REG_A5XX_CP_ROQ_THRESHOLDS_1 0x0000081f + +#define REG_A5XX_CP_ROQ_THRESHOLDS_2 0x00000820 + +#define REG_A5XX_CP_ROQ_DBG_ADDR 0x00000821 + +#define REG_A5XX_CP_ROQ_DBG_DATA 0x00000822 + +#define REG_A5XX_CP_MEQ_DBG_ADDR 0x00000823 + +#define REG_A5XX_CP_MEQ_DBG_DATA 0x00000824 + +#define REG_A5XX_CP_MEQ_THRESHOLDS 0x00000825 + +#define REG_A5XX_CP_MERCIU_SIZE 0x00000826 + +#define REG_A5XX_CP_MERCIU_DBG_ADDR 0x00000827 + +#define REG_A5XX_CP_MERCIU_DBG_DATA_1 0x00000828 + +#define REG_A5XX_CP_MERCIU_DBG_DATA_2 0x00000829 + +#define REG_A5XX_CP_PFP_UCODE_DBG_ADDR 0x0000082a + +#define REG_A5XX_CP_PFP_UCODE_DBG_DATA 0x0000082b + +#define REG_A5XX_CP_ME_UCODE_DBG_ADDR 0x0000082f + +#define REG_A5XX_CP_ME_UCODE_DBG_DATA 0x00000830 + +#define REG_A5XX_CP_CNTL 0x00000831 + +#define REG_A5XX_CP_PFP_ME_CNTL 0x00000832 + +#define REG_A5XX_CP_CHICKEN_DBG 0x00000833 + +#define REG_A5XX_CP_PFP_INSTR_BASE_LO 0x00000835 + +#define REG_A5XX_CP_PFP_INSTR_BASE_HI 0x00000836 + +#define REG_A5XX_CP_ME_INSTR_BASE_LO 0x00000838 + +#define REG_A5XX_CP_ME_INSTR_BASE_HI 0x00000839 + +#define REG_A5XX_CP_CONTEXT_SWITCH_CNTL 0x0000083b + +#define REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_LO 0x0000083c + +#define REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_HI 0x0000083d + +#define REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_LO 0x0000083e + +#define REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_HI 0x0000083f + +#define REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO 0x00000840 + +#define REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI 0x00000841 + +#define REG_A5XX_CP_ADDR_MODE_CNTL 0x00000860 + +#define REG_A5XX_CP_ME_STAT_DATA 0x00000b14 + +#define REG_A5XX_CP_WFI_PEND_CTR 0x00000b15 + +#define REG_A5XX_CP_INTERRUPT_STATUS 0x00000b18 + +#define REG_A5XX_CP_HW_FAULT 0x00000b1a + +#define REG_A5XX_CP_PROTECT_STATUS 0x00000b1c + +#define REG_A5XX_CP_IB1_BASE 0x00000b1f + +#define REG_A5XX_CP_IB1_BASE_HI 0x00000b20 + +#define REG_A5XX_CP_IB1_BUFSZ 0x00000b21 + +#define REG_A5XX_CP_IB2_BASE 0x00000b22 + +#define REG_A5XX_CP_IB2_BASE_HI 0x00000b23 + +#define REG_A5XX_CP_IB2_BUFSZ 0x00000b24 + +static inline uint32_t REG_A5XX_CP_SCRATCH(uint32_t i0) { return 0x00000b78 + 0x1*i0; } + +static inline uint32_t REG_A5XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000b78 + 0x1*i0; } + +static inline uint32_t REG_A5XX_CP_PROTECT(uint32_t i0) { return 0x00000880 + 0x1*i0; } + +static inline uint32_t REG_A5XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000880 + 0x1*i0; } +#define A5XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0001ffff +#define A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0 +static inline uint32_t A5XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) +{ + return ((val) << A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A5XX_CP_PROTECT_REG_BASE_ADDR__MASK; +} +#define A5XX_CP_PROTECT_REG_MASK_LEN__MASK 0x1f000000 +#define A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT 24 +static inline uint32_t A5XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) +{ + return ((val) << A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A5XX_CP_PROTECT_REG_MASK_LEN__MASK; +} +#define A5XX_CP_PROTECT_REG_TRAP_WRITE 0x20000000 +#define A5XX_CP_PROTECT_REG_TRAP_READ 0x40000000 + +#define REG_A5XX_CP_PROTECT_CNTL 0x000008a0 + +#define REG_A5XX_CP_AHB_FAULT 0x00000b1b + +#define REG_A5XX_CP_PERFCTR_CP_SEL_0 0x00000bb0 + +#define REG_A5XX_CP_PERFCTR_CP_SEL_1 0x00000bb1 + +#define REG_A5XX_CP_PERFCTR_CP_SEL_2 0x00000bb2 + +#define REG_A5XX_CP_PERFCTR_CP_SEL_3 0x00000bb3 + +#define REG_A5XX_CP_PERFCTR_CP_SEL_4 0x00000bb4 + +#define REG_A5XX_CP_PERFCTR_CP_SEL_5 0x00000bb5 + +#define REG_A5XX_CP_PERFCTR_CP_SEL_6 0x00000bb6 + +#define REG_A5XX_CP_PERFCTR_CP_SEL_7 0x00000bb7 + +#define REG_A5XX_VSC_ADDR_MODE_CNTL 0x00000bc1 + +#define REG_A5XX_CP_POWERCTR_CP_SEL_0 0x00000bba + +#define REG_A5XX_CP_POWERCTR_CP_SEL_1 0x00000bbb + +#define REG_A5XX_CP_POWERCTR_CP_SEL_2 0x00000bbc + +#define REG_A5XX_CP_POWERCTR_CP_SEL_3 0x00000bbd + +#define REG_A5XX_RBBM_CFG_DBGBUS_SEL_A 0x00000004 + +#define REG_A5XX_RBBM_CFG_DBGBUS_SEL_B 0x00000005 + +#define REG_A5XX_RBBM_CFG_DBGBUS_SEL_C 0x00000006 + +#define REG_A5XX_RBBM_CFG_DBGBUS_SEL_D 0x00000007 + +#define REG_A5XX_RBBM_CFG_DBGBUS_CNTLT 0x00000008 + +#define REG_A5XX_RBBM_CFG_DBGBUS_CNTLM 0x00000009 + +#define REG_A5XX_RBBM_CFG_DEBBUS_CTLTM_ENABLE_SHIFT 0x00000018 + +#define REG_A5XX_RBBM_CFG_DBGBUS_OPL 0x0000000a + +#define REG_A5XX_RBBM_CFG_DBGBUS_OPE 0x0000000b + +#define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_0 0x0000000c + +#define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_1 0x0000000d + +#define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_2 0x0000000e + +#define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_3 0x0000000f + +#define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_0 0x00000010 + +#define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_1 0x00000011 + +#define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_2 0x00000012 + +#define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_3 0x00000013 + +#define REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_0 0x00000014 + +#define REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_1 0x00000015 + +#define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_0 0x00000016 + +#define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_1 0x00000017 + +#define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_2 0x00000018 + +#define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_3 0x00000019 + +#define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_0 0x0000001a + +#define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_1 0x0000001b + +#define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_2 0x0000001c + +#define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_3 0x0000001d + +#define REG_A5XX_RBBM_CFG_DBGBUS_NIBBLEE 0x0000001e + +#define REG_A5XX_RBBM_CFG_DBGBUS_PTRC0 0x0000001f + +#define REG_A5XX_RBBM_CFG_DBGBUS_PTRC1 0x00000020 + +#define REG_A5XX_RBBM_CFG_DBGBUS_LOADREG 0x00000021 + +#define REG_A5XX_RBBM_CFG_DBGBUS_IDX 0x00000022 + +#define REG_A5XX_RBBM_CFG_DBGBUS_CLRC 0x00000023 + +#define REG_A5XX_RBBM_CFG_DBGBUS_LOADIVT 0x00000024 + +#define REG_A5XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0000002f + +#define REG_A5XX_RBBM_INT_CLEAR_CMD 0x00000037 + +#define REG_A5XX_RBBM_INT_0_MASK 0x00000038 +#define A5XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE 0x00000001 +#define A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR 0x00000002 +#define A5XX_RBBM_INT_0_MASK_RBBM_TRANSFER_TIMEOUT 0x00000004 +#define A5XX_RBBM_INT_0_MASK_RBBM_ME_MS_TIMEOUT 0x00000008 +#define A5XX_RBBM_INT_0_MASK_RBBM_PFP_MS_TIMEOUT 0x00000010 +#define A5XX_RBBM_INT_0_MASK_RBBM_ETS_MS_TIMEOUT 0x00000020 +#define A5XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNC_OVERFLOW 0x00000040 +#define A5XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR 0x00000080 +#define A5XX_RBBM_INT_0_MASK_CP_SW 0x00000100 +#define A5XX_RBBM_INT_0_MASK_CP_HW_ERROR 0x00000200 +#define A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS 0x00000400 +#define A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS 0x00000800 +#define A5XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS 0x00001000 +#define A5XX_RBBM_INT_0_MASK_CP_IB2 0x00002000 +#define A5XX_RBBM_INT_0_MASK_CP_IB1 0x00004000 +#define A5XX_RBBM_INT_0_MASK_CP_RB 0x00008000 +#define A5XX_RBBM_INT_0_MASK_CP_RB_DONE_TS 0x00020000 +#define A5XX_RBBM_INT_0_MASK_CP_WT_DONE_TS 0x00040000 +#define A5XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS 0x00100000 +#define A5XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW 0x00400000 +#define A5XX_RBBM_INT_0_MASK_MISC_HANG_DETECT 0x00800000 +#define A5XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS 0x01000000 +#define A5XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR 0x02000000 +#define A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 0x04000000 +#define A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 0x08000000 +#define A5XX_RBBM_INT_0_MASK_GPMU_VOLTAGE_DROOP 0x10000000 +#define A5XX_RBBM_INT_0_MASK_GPMU_FIRMWARE 0x20000000 +#define A5XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ 0x40000000 +#define A5XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG 0x80000000 + +#define REG_A5XX_RBBM_AHB_DBG_CNTL 0x0000003f + +#define REG_A5XX_RBBM_EXT_VBIF_DBG_CNTL 0x00000041 + +#define REG_A5XX_RBBM_SW_RESET_CMD 0x00000043 + +#define REG_A5XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045 + +#define REG_A5XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046 + +#define REG_A5XX_RBBM_DBG_LO_HI_GPIO 0x00000048 + +#define REG_A5XX_RBBM_EXT_TRACE_BUS_CNTL 0x00000049 + +#define REG_A5XX_RBBM_CLOCK_CNTL_TP0 0x0000004a + +#define REG_A5XX_RBBM_CLOCK_CNTL_TP1 0x0000004b + +#define REG_A5XX_RBBM_CLOCK_CNTL_TP2 0x0000004c + +#define REG_A5XX_RBBM_CLOCK_CNTL_TP3 0x0000004d + +#define REG_A5XX_RBBM_CLOCK_CNTL2_TP0 0x0000004e + +#define REG_A5XX_RBBM_CLOCK_CNTL2_TP1 0x0000004f + +#define REG_A5XX_RBBM_CLOCK_CNTL2_TP2 0x00000050 + +#define REG_A5XX_RBBM_CLOCK_CNTL2_TP3 0x00000051 + +#define REG_A5XX_RBBM_CLOCK_CNTL3_TP0 0x00000052 + +#define REG_A5XX_RBBM_CLOCK_CNTL3_TP1 0x00000053 + +#define REG_A5XX_RBBM_CLOCK_CNTL3_TP2 0x00000054 + +#define REG_A5XX_RBBM_CLOCK_CNTL3_TP3 0x00000055 + +#define REG_A5XX_RBBM_READ_AHB_THROUGH_DBG 0x00000059 + +#define REG_A5XX_RBBM_CLOCK_CNTL_UCHE 0x0000005a + +#define REG_A5XX_RBBM_CLOCK_CNTL2_UCHE 0x0000005b + +#define REG_A5XX_RBBM_CLOCK_CNTL3_UCHE 0x0000005c + +#define REG_A5XX_RBBM_CLOCK_CNTL4_UCHE 0x0000005d + +#define REG_A5XX_RBBM_CLOCK_HYST_UCHE 0x0000005e + +#define REG_A5XX_RBBM_CLOCK_DELAY_UCHE 0x0000005f + +#define REG_A5XX_RBBM_CLOCK_MODE_GPC 0x00000060 + +#define REG_A5XX_RBBM_CLOCK_DELAY_GPC 0x00000061 + +#define REG_A5XX_RBBM_CLOCK_HYST_GPC 0x00000062 + +#define REG_A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM 0x00000063 + +#define REG_A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x00000064 + +#define REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x00000065 + +#define REG_A5XX_RBBM_CLOCK_DELAY_HLSQ 0x00000066 + +#define REG_A5XX_RBBM_CLOCK_CNTL 0x00000067 + +#define REG_A5XX_RBBM_CLOCK_CNTL_SP0 0x00000068 + +#define REG_A5XX_RBBM_CLOCK_CNTL_SP1 0x00000069 + +#define REG_A5XX_RBBM_CLOCK_CNTL_SP2 0x0000006a + +#define REG_A5XX_RBBM_CLOCK_CNTL_SP3 0x0000006b + +#define REG_A5XX_RBBM_CLOCK_CNTL2_SP0 0x0000006c + +#define REG_A5XX_RBBM_CLOCK_CNTL2_SP1 0x0000006d + +#define REG_A5XX_RBBM_CLOCK_CNTL2_SP2 0x0000006e + +#define REG_A5XX_RBBM_CLOCK_CNTL2_SP3 0x0000006f + +#define REG_A5XX_RBBM_CLOCK_HYST_SP0 0x00000070 + +#define REG_A5XX_RBBM_CLOCK_HYST_SP1 0x00000071 + +#define REG_A5XX_RBBM_CLOCK_HYST_SP2 0x00000072 + +#define REG_A5XX_RBBM_CLOCK_HYST_SP3 0x00000073 + +#define REG_A5XX_RBBM_CLOCK_DELAY_SP0 0x00000074 + +#define REG_A5XX_RBBM_CLOCK_DELAY_SP1 0x00000075 + +#define REG_A5XX_RBBM_CLOCK_DELAY_SP2 0x00000076 + +#define REG_A5XX_RBBM_CLOCK_DELAY_SP3 0x00000077 + +#define REG_A5XX_RBBM_CLOCK_CNTL_RB0 0x00000078 + +#define REG_A5XX_RBBM_CLOCK_CNTL_RB1 0x00000079 + +#define REG_A5XX_RBBM_CLOCK_CNTL_RB2 0x0000007a + +#define REG_A5XX_RBBM_CLOCK_CNTL_RB3 0x0000007b + +#define REG_A5XX_RBBM_CLOCK_CNTL2_RB0 0x0000007c + +#define REG_A5XX_RBBM_CLOCK_CNTL2_RB1 0x0000007d + +#define REG_A5XX_RBBM_CLOCK_CNTL2_RB2 0x0000007e + +#define REG_A5XX_RBBM_CLOCK_CNTL2_RB3 0x0000007f + +#define REG_A5XX_RBBM_CLOCK_HYST_RAC 0x00000080 + +#define REG_A5XX_RBBM_CLOCK_DELAY_RAC 0x00000081 + +#define REG_A5XX_RBBM_CLOCK_CNTL_CCU0 0x00000082 + +#define REG_A5XX_RBBM_CLOCK_CNTL_CCU1 0x00000083 + +#define REG_A5XX_RBBM_CLOCK_CNTL_CCU2 0x00000084 + +#define REG_A5XX_RBBM_CLOCK_CNTL_CCU3 0x00000085 + +#define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU0 0x00000086 + +#define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU1 0x00000087 + +#define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU2 0x00000088 + +#define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU3 0x00000089 + +#define REG_A5XX_RBBM_CLOCK_CNTL_RAC 0x0000008a + +#define REG_A5XX_RBBM_CLOCK_CNTL2_RAC 0x0000008b + +#define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0 0x0000008c + +#define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_1 0x0000008d + +#define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_2 0x0000008e + +#define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_3 0x0000008f + +#define REG_A5XX_RBBM_CLOCK_HYST_VFD 0x00000090 + +#define REG_A5XX_RBBM_CLOCK_MODE_VFD 0x00000091 + +#define REG_A5XX_RBBM_CLOCK_DELAY_VFD 0x00000092 + +#define REG_A5XX_RBBM_AHB_CNTL0 0x00000093 + +#define REG_A5XX_RBBM_AHB_CNTL1 0x00000094 + +#define REG_A5XX_RBBM_AHB_CNTL2 0x00000095 + +#define REG_A5XX_RBBM_AHB_CMD 0x00000096 + +#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL11 0x0000009c + +#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL12 0x0000009d + +#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL13 0x0000009e + +#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL14 0x0000009f + +#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL15 0x000000a0 + +#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL16 0x000000a1 + +#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL17 0x000000a2 + +#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL18 0x000000a3 + +#define REG_A5XX_RBBM_CLOCK_DELAY_TP0 0x000000a4 + +#define REG_A5XX_RBBM_CLOCK_DELAY_TP1 0x000000a5 + +#define REG_A5XX_RBBM_CLOCK_DELAY_TP2 0x000000a6 + +#define REG_A5XX_RBBM_CLOCK_DELAY_TP3 0x000000a7 + +#define REG_A5XX_RBBM_CLOCK_DELAY2_TP0 0x000000a8 + +#define REG_A5XX_RBBM_CLOCK_DELAY2_TP1 0x000000a9 + +#define REG_A5XX_RBBM_CLOCK_DELAY2_TP2 0x000000aa + +#define REG_A5XX_RBBM_CLOCK_DELAY2_TP3 0x000000ab + +#define REG_A5XX_RBBM_CLOCK_DELAY3_TP0 0x000000ac + +#define REG_A5XX_RBBM_CLOCK_DELAY3_TP1 0x000000ad + +#define REG_A5XX_RBBM_CLOCK_DELAY3_TP2 0x000000ae + +#define REG_A5XX_RBBM_CLOCK_DELAY3_TP3 0x000000af + +#define REG_A5XX_RBBM_CLOCK_HYST_TP0 0x000000b0 + +#define REG_A5XX_RBBM_CLOCK_HYST_TP1 0x000000b1 + +#define REG_A5XX_RBBM_CLOCK_HYST_TP2 0x000000b2 + +#define REG_A5XX_RBBM_CLOCK_HYST_TP3 0x000000b3 + +#define REG_A5XX_RBBM_CLOCK_HYST2_TP0 0x000000b4 + +#define REG_A5XX_RBBM_CLOCK_HYST2_TP1 0x000000b5 + +#define REG_A5XX_RBBM_CLOCK_HYST2_TP2 0x000000b6 + +#define REG_A5XX_RBBM_CLOCK_HYST2_TP3 0x000000b7 + +#define REG_A5XX_RBBM_CLOCK_HYST3_TP0 0x000000b8 + +#define REG_A5XX_RBBM_CLOCK_HYST3_TP1 0x000000b9 + +#define REG_A5XX_RBBM_CLOCK_HYST3_TP2 0x000000ba + +#define REG_A5XX_RBBM_CLOCK_HYST3_TP3 0x000000bb + +#define REG_A5XX_RBBM_CLOCK_CNTL_GPMU 0x000000c8 + +#define REG_A5XX_RBBM_CLOCK_DELAY_GPMU 0x000000c9 + +#define REG_A5XX_RBBM_CLOCK_HYST_GPMU 0x000000ca + +#define REG_A5XX_RBBM_PERFCTR_CP_0_LO 0x000003a0 + +#define REG_A5XX_RBBM_PERFCTR_CP_0_HI 0x000003a1 + +#define REG_A5XX_RBBM_PERFCTR_CP_1_LO 0x000003a2 + +#define REG_A5XX_RBBM_PERFCTR_CP_1_HI 0x000003a3 + +#define REG_A5XX_RBBM_PERFCTR_CP_2_LO 0x000003a4 + +#define REG_A5XX_RBBM_PERFCTR_CP_2_HI 0x000003a5 + +#define REG_A5XX_RBBM_PERFCTR_CP_3_LO 0x000003a6 + +#define REG_A5XX_RBBM_PERFCTR_CP_3_HI 0x000003a7 + +#define REG_A5XX_RBBM_PERFCTR_CP_4_LO 0x000003a8 + +#define REG_A5XX_RBBM_PERFCTR_CP_4_HI 0x000003a9 + +#define REG_A5XX_RBBM_PERFCTR_CP_5_LO 0x000003aa + +#define REG_A5XX_RBBM_PERFCTR_CP_5_HI 0x000003ab + +#define REG_A5XX_RBBM_PERFCTR_CP_6_LO 0x000003ac + +#define REG_A5XX_RBBM_PERFCTR_CP_6_HI 0x000003ad + +#define REG_A5XX_RBBM_PERFCTR_CP_7_LO 0x000003ae + +#define REG_A5XX_RBBM_PERFCTR_CP_7_HI 0x000003af + +#define REG_A5XX_RBBM_PERFCTR_RBBM_0_LO 0x000003b0 + +#define REG_A5XX_RBBM_PERFCTR_RBBM_0_HI 0x000003b1 + +#define REG_A5XX_RBBM_PERFCTR_RBBM_1_LO 0x000003b2 + +#define REG_A5XX_RBBM_PERFCTR_RBBM_1_HI 0x000003b3 + +#define REG_A5XX_RBBM_PERFCTR_RBBM_2_LO 0x000003b4 + +#define REG_A5XX_RBBM_PERFCTR_RBBM_2_HI 0x000003b5 + +#define REG_A5XX_RBBM_PERFCTR_RBBM_3_LO 0x000003b6 + +#define REG_A5XX_RBBM_PERFCTR_RBBM_3_HI 0x000003b7 + +#define REG_A5XX_RBBM_PERFCTR_PC_0_LO 0x000003b8 + +#define REG_A5XX_RBBM_PERFCTR_PC_0_HI 0x000003b9 + +#define REG_A5XX_RBBM_PERFCTR_PC_1_LO 0x000003ba + +#define REG_A5XX_RBBM_PERFCTR_PC_1_HI 0x000003bb + +#define REG_A5XX_RBBM_PERFCTR_PC_2_LO 0x000003bc + +#define REG_A5XX_RBBM_PERFCTR_PC_2_HI 0x000003bd + +#define REG_A5XX_RBBM_PERFCTR_PC_3_LO 0x000003be + +#define REG_A5XX_RBBM_PERFCTR_PC_3_HI 0x000003bf + +#define REG_A5XX_RBBM_PERFCTR_PC_4_LO 0x000003c0 + +#define REG_A5XX_RBBM_PERFCTR_PC_4_HI 0x000003c1 + +#define REG_A5XX_RBBM_PERFCTR_PC_5_LO 0x000003c2 + +#define REG_A5XX_RBBM_PERFCTR_PC_5_HI 0x000003c3 + +#define REG_A5XX_RBBM_PERFCTR_PC_6_LO 0x000003c4 + +#define REG_A5XX_RBBM_PERFCTR_PC_6_HI 0x000003c5 + +#define REG_A5XX_RBBM_PERFCTR_PC_7_LO 0x000003c6 + +#define REG_A5XX_RBBM_PERFCTR_PC_7_HI 0x000003c7 + +#define REG_A5XX_RBBM_PERFCTR_VFD_0_LO 0x000003c8 + +#define REG_A5XX_RBBM_PERFCTR_VFD_0_HI 0x000003c9 + +#define REG_A5XX_RBBM_PERFCTR_VFD_1_LO 0x000003ca + +#define REG_A5XX_RBBM_PERFCTR_VFD_1_HI 0x000003cb + +#define REG_A5XX_RBBM_PERFCTR_VFD_2_LO 0x000003cc + +#define REG_A5XX_RBBM_PERFCTR_VFD_2_HI 0x000003cd + +#define REG_A5XX_RBBM_PERFCTR_VFD_3_LO 0x000003ce + +#define REG_A5XX_RBBM_PERFCTR_VFD_3_HI 0x000003cf + +#define REG_A5XX_RBBM_PERFCTR_VFD_4_LO 0x000003d0 + +#define REG_A5XX_RBBM_PERFCTR_VFD_4_HI 0x000003d1 + +#define REG_A5XX_RBBM_PERFCTR_VFD_5_LO 0x000003d2 + +#define REG_A5XX_RBBM_PERFCTR_VFD_5_HI 0x000003d3 + +#define REG_A5XX_RBBM_PERFCTR_VFD_6_LO 0x000003d4 + +#define REG_A5XX_RBBM_PERFCTR_VFD_6_HI 0x000003d5 + +#define REG_A5XX_RBBM_PERFCTR_VFD_7_LO 0x000003d6 + +#define REG_A5XX_RBBM_PERFCTR_VFD_7_HI 0x000003d7 + +#define REG_A5XX_RBBM_PERFCTR_HLSQ_0_LO 0x000003d8 + +#define REG_A5XX_RBBM_PERFCTR_HLSQ_0_HI 0x000003d9 + +#define REG_A5XX_RBBM_PERFCTR_HLSQ_1_LO 0x000003da + +#define REG_A5XX_RBBM_PERFCTR_HLSQ_1_HI 0x000003db + +#define REG_A5XX_RBBM_PERFCTR_HLSQ_2_LO 0x000003dc + +#define REG_A5XX_RBBM_PERFCTR_HLSQ_2_HI 0x000003dd + +#define REG_A5XX_RBBM_PERFCTR_HLSQ_3_LO 0x000003de + +#define REG_A5XX_RBBM_PERFCTR_HLSQ_3_HI 0x000003df + +#define REG_A5XX_RBBM_PERFCTR_HLSQ_4_LO 0x000003e0 + +#define REG_A5XX_RBBM_PERFCTR_HLSQ_4_HI 0x000003e1 + +#define REG_A5XX_RBBM_PERFCTR_HLSQ_5_LO 0x000003e2 + +#define REG_A5XX_RBBM_PERFCTR_HLSQ_5_HI 0x000003e3 + +#define REG_A5XX_RBBM_PERFCTR_HLSQ_6_LO 0x000003e4 + +#define REG_A5XX_RBBM_PERFCTR_HLSQ_6_HI 0x000003e5 + +#define REG_A5XX_RBBM_PERFCTR_HLSQ_7_LO 0x000003e6 + +#define REG_A5XX_RBBM_PERFCTR_HLSQ_7_HI 0x000003e7 + +#define REG_A5XX_RBBM_PERFCTR_VPC_0_LO 0x000003e8 + +#define REG_A5XX_RBBM_PERFCTR_VPC_0_HI 0x000003e9 + +#define REG_A5XX_RBBM_PERFCTR_VPC_1_LO 0x000003ea + +#define REG_A5XX_RBBM_PERFCTR_VPC_1_HI 0x000003eb + +#define REG_A5XX_RBBM_PERFCTR_VPC_2_LO 0x000003ec + +#define REG_A5XX_RBBM_PERFCTR_VPC_2_HI 0x000003ed + +#define REG_A5XX_RBBM_PERFCTR_VPC_3_LO 0x000003ee + +#define REG_A5XX_RBBM_PERFCTR_VPC_3_HI 0x000003ef + +#define REG_A5XX_RBBM_PERFCTR_CCU_0_LO 0x000003f0 + +#define REG_A5XX_RBBM_PERFCTR_CCU_0_HI 0x000003f1 + +#define REG_A5XX_RBBM_PERFCTR_CCU_1_LO 0x000003f2 + +#define REG_A5XX_RBBM_PERFCTR_CCU_1_HI 0x000003f3 + +#define REG_A5XX_RBBM_PERFCTR_CCU_2_LO 0x000003f4 + +#define REG_A5XX_RBBM_PERFCTR_CCU_2_HI 0x000003f5 + +#define REG_A5XX_RBBM_PERFCTR_CCU_3_LO 0x000003f6 + +#define REG_A5XX_RBBM_PERFCTR_CCU_3_HI 0x000003f7 + +#define REG_A5XX_RBBM_PERFCTR_TSE_0_LO 0x000003f8 + +#define REG_A5XX_RBBM_PERFCTR_TSE_0_HI 0x000003f9 + +#define REG_A5XX_RBBM_PERFCTR_TSE_1_LO 0x000003fa + +#define REG_A5XX_RBBM_PERFCTR_TSE_1_HI 0x000003fb + +#define REG_A5XX_RBBM_PERFCTR_TSE_2_LO 0x000003fc + +#define REG_A5XX_RBBM_PERFCTR_TSE_2_HI 0x000003fd + +#define REG_A5XX_RBBM_PERFCTR_TSE_3_LO 0x000003fe + +#define REG_A5XX_RBBM_PERFCTR_TSE_3_HI 0x000003ff + +#define REG_A5XX_RBBM_PERFCTR_RAS_0_LO 0x00000400 + +#define REG_A5XX_RBBM_PERFCTR_RAS_0_HI 0x00000401 + +#define REG_A5XX_RBBM_PERFCTR_RAS_1_LO 0x00000402 + +#define REG_A5XX_RBBM_PERFCTR_RAS_1_HI 0x00000403 + +#define REG_A5XX_RBBM_PERFCTR_RAS_2_LO 0x00000404 + +#define REG_A5XX_RBBM_PERFCTR_RAS_2_HI 0x00000405 + +#define REG_A5XX_RBBM_PERFCTR_RAS_3_LO 0x00000406 + +#define REG_A5XX_RBBM_PERFCTR_RAS_3_HI 0x00000407 + +#define REG_A5XX_RBBM_PERFCTR_UCHE_0_LO 0x00000408 + +#define REG_A5XX_RBBM_PERFCTR_UCHE_0_HI 0x00000409 + +#define REG_A5XX_RBBM_PERFCTR_UCHE_1_LO 0x0000040a + +#define REG_A5XX_RBBM_PERFCTR_UCHE_1_HI 0x0000040b + +#define REG_A5XX_RBBM_PERFCTR_UCHE_2_LO 0x0000040c + +#define REG_A5XX_RBBM_PERFCTR_UCHE_2_HI 0x0000040d + +#define REG_A5XX_RBBM_PERFCTR_UCHE_3_LO 0x0000040e + +#define REG_A5XX_RBBM_PERFCTR_UCHE_3_HI 0x0000040f + +#define REG_A5XX_RBBM_PERFCTR_UCHE_4_LO 0x00000410 + +#define REG_A5XX_RBBM_PERFCTR_UCHE_4_HI 0x00000411 + +#define REG_A5XX_RBBM_PERFCTR_UCHE_5_LO 0x00000412 + +#define REG_A5XX_RBBM_PERFCTR_UCHE_5_HI 0x00000413 + +#define REG_A5XX_RBBM_PERFCTR_UCHE_6_LO 0x00000414 + +#define REG_A5XX_RBBM_PERFCTR_UCHE_6_HI 0x00000415 + +#define REG_A5XX_RBBM_PERFCTR_UCHE_7_LO 0x00000416 + +#define REG_A5XX_RBBM_PERFCTR_UCHE_7_HI 0x00000417 + +#define REG_A5XX_RBBM_PERFCTR_TP_0_LO 0x00000418 + +#define REG_A5XX_RBBM_PERFCTR_TP_0_HI 0x00000419 + +#define REG_A5XX_RBBM_PERFCTR_TP_1_LO 0x0000041a + +#define REG_A5XX_RBBM_PERFCTR_TP_1_HI 0x0000041b + +#define REG_A5XX_RBBM_PERFCTR_TP_2_LO 0x0000041c + +#define REG_A5XX_RBBM_PERFCTR_TP_2_HI 0x0000041d + +#define REG_A5XX_RBBM_PERFCTR_TP_3_LO 0x0000041e + +#define REG_A5XX_RBBM_PERFCTR_TP_3_HI 0x0000041f + +#define REG_A5XX_RBBM_PERFCTR_TP_4_LO 0x00000420 + +#define REG_A5XX_RBBM_PERFCTR_TP_4_HI 0x00000421 + +#define REG_A5XX_RBBM_PERFCTR_TP_5_LO 0x00000422 + +#define REG_A5XX_RBBM_PERFCTR_TP_5_HI 0x00000423 + +#define REG_A5XX_RBBM_PERFCTR_TP_6_LO 0x00000424 + +#define REG_A5XX_RBBM_PERFCTR_TP_6_HI 0x00000425 + +#define REG_A5XX_RBBM_PERFCTR_TP_7_LO 0x00000426 + +#define REG_A5XX_RBBM_PERFCTR_TP_7_HI 0x00000427 + +#define REG_A5XX_RBBM_PERFCTR_SP_0_LO 0x00000428 + +#define REG_A5XX_RBBM_PERFCTR_SP_0_HI 0x00000429 + +#define REG_A5XX_RBBM_PERFCTR_SP_1_LO 0x0000042a + +#define REG_A5XX_RBBM_PERFCTR_SP_1_HI 0x0000042b + +#define REG_A5XX_RBBM_PERFCTR_SP_2_LO 0x0000042c + +#define REG_A5XX_RBBM_PERFCTR_SP_2_HI 0x0000042d + +#define REG_A5XX_RBBM_PERFCTR_SP_3_LO 0x0000042e + +#define REG_A5XX_RBBM_PERFCTR_SP_3_HI 0x0000042f + +#define REG_A5XX_RBBM_PERFCTR_SP_4_LO 0x00000430 + +#define REG_A5XX_RBBM_PERFCTR_SP_4_HI 0x00000431 + +#define REG_A5XX_RBBM_PERFCTR_SP_5_LO 0x00000432 + +#define REG_A5XX_RBBM_PERFCTR_SP_5_HI 0x00000433 + +#define REG_A5XX_RBBM_PERFCTR_SP_6_LO 0x00000434 + +#define REG_A5XX_RBBM_PERFCTR_SP_6_HI 0x00000435 + +#define REG_A5XX_RBBM_PERFCTR_SP_7_LO 0x00000436 + +#define REG_A5XX_RBBM_PERFCTR_SP_7_HI 0x00000437 + +#define REG_A5XX_RBBM_PERFCTR_SP_8_LO 0x00000438 + +#define REG_A5XX_RBBM_PERFCTR_SP_8_HI 0x00000439 + +#define REG_A5XX_RBBM_PERFCTR_SP_9_LO 0x0000043a + +#define REG_A5XX_RBBM_PERFCTR_SP_9_HI 0x0000043b + +#define REG_A5XX_RBBM_PERFCTR_SP_10_LO 0x0000043c + +#define REG_A5XX_RBBM_PERFCTR_SP_10_HI 0x0000043d + +#define REG_A5XX_RBBM_PERFCTR_SP_11_LO 0x0000043e + +#define REG_A5XX_RBBM_PERFCTR_SP_11_HI 0x0000043f + +#define REG_A5XX_RBBM_PERFCTR_RB_0_LO 0x00000440 + +#define REG_A5XX_RBBM_PERFCTR_RB_0_HI 0x00000441 + +#define REG_A5XX_RBBM_PERFCTR_RB_1_LO 0x00000442 + +#define REG_A5XX_RBBM_PERFCTR_RB_1_HI 0x00000443 + +#define REG_A5XX_RBBM_PERFCTR_RB_2_LO 0x00000444 + +#define REG_A5XX_RBBM_PERFCTR_RB_2_HI 0x00000445 + +#define REG_A5XX_RBBM_PERFCTR_RB_3_LO 0x00000446 + +#define REG_A5XX_RBBM_PERFCTR_RB_3_HI 0x00000447 + +#define REG_A5XX_RBBM_PERFCTR_RB_4_LO 0x00000448 + +#define REG_A5XX_RBBM_PERFCTR_RB_4_HI 0x00000449 + +#define REG_A5XX_RBBM_PERFCTR_RB_5_LO 0x0000044a + +#define REG_A5XX_RBBM_PERFCTR_RB_5_HI 0x0000044b + +#define REG_A5XX_RBBM_PERFCTR_RB_6_LO 0x0000044c + +#define REG_A5XX_RBBM_PERFCTR_RB_6_HI 0x0000044d + +#define REG_A5XX_RBBM_PERFCTR_RB_7_LO 0x0000044e + +#define REG_A5XX_RBBM_PERFCTR_RB_7_HI 0x0000044f + +#define REG_A5XX_RBBM_PERFCTR_VSC_0_LO 0x00000450 + +#define REG_A5XX_RBBM_PERFCTR_VSC_0_HI 0x00000451 + +#define REG_A5XX_RBBM_PERFCTR_VSC_1_LO 0x00000452 + +#define REG_A5XX_RBBM_PERFCTR_VSC_1_HI 0x00000453 + +#define REG_A5XX_RBBM_PERFCTR_LRZ_0_LO 0x00000454 + +#define REG_A5XX_RBBM_PERFCTR_LRZ_0_HI 0x00000455 + +#define REG_A5XX_RBBM_PERFCTR_LRZ_1_LO 0x00000456 + +#define REG_A5XX_RBBM_PERFCTR_LRZ_1_HI 0x00000457 + +#define REG_A5XX_RBBM_PERFCTR_LRZ_2_LO 0x00000458 + +#define REG_A5XX_RBBM_PERFCTR_LRZ_2_HI 0x00000459 + +#define REG_A5XX_RBBM_PERFCTR_LRZ_3_LO 0x0000045a + +#define REG_A5XX_RBBM_PERFCTR_LRZ_3_HI 0x0000045b + +#define REG_A5XX_RBBM_PERFCTR_CMP_0_LO 0x0000045c + +#define REG_A5XX_RBBM_PERFCTR_CMP_0_HI 0x0000045d + +#define REG_A5XX_RBBM_PERFCTR_CMP_1_LO 0x0000045e + +#define REG_A5XX_RBBM_PERFCTR_CMP_1_HI 0x0000045f + +#define REG_A5XX_RBBM_PERFCTR_CMP_2_LO 0x00000460 + +#define REG_A5XX_RBBM_PERFCTR_CMP_2_HI 0x00000461 + +#define REG_A5XX_RBBM_PERFCTR_CMP_3_LO 0x00000462 + +#define REG_A5XX_RBBM_PERFCTR_CMP_3_HI 0x00000463 + +#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0 0x0000046b + +#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_1 0x0000046c + +#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_2 0x0000046d + +#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000046e + +#define REG_A5XX_RBBM_ALWAYSON_COUNTER_LO 0x000004d2 + +#define REG_A5XX_RBBM_ALWAYSON_COUNTER_HI 0x000004d3 + +#define REG_A5XX_RBBM_STATUS 0x000004f5 +#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB 0x80000000 +#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP 0x40000000 +#define A5XX_RBBM_STATUS_HLSQ_BUSY 0x20000000 +#define A5XX_RBBM_STATUS_VSC_BUSY 0x10000000 +#define A5XX_RBBM_STATUS_TPL1_BUSY 0x08000000 +#define A5XX_RBBM_STATUS_SP_BUSY 0x04000000 +#define A5XX_RBBM_STATUS_UCHE_BUSY 0x02000000 +#define A5XX_RBBM_STATUS_VPC_BUSY 0x01000000 +#define A5XX_RBBM_STATUS_VFDP_BUSY 0x00800000 +#define A5XX_RBBM_STATUS_VFD_BUSY 0x00400000 +#define A5XX_RBBM_STATUS_TESS_BUSY 0x00200000 +#define A5XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000 +#define A5XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000 +#define A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY 0x00040000 +#define A5XX_RBBM_STATUS_DCOM_BUSY 0x00020000 +#define A5XX_RBBM_STATUS_COM_BUSY 0x00010000 +#define A5XX_RBBM_STATUS_LRZ_BUZY 0x00008000 +#define A5XX_RBBM_STATUS_A2D_DSP_BUSY 0x00004000 +#define A5XX_RBBM_STATUS_CCUFCHE_BUSY 0x00002000 +#define A5XX_RBBM_STATUS_RB_BUSY 0x00001000 +#define A5XX_RBBM_STATUS_RAS_BUSY 0x00000800 +#define A5XX_RBBM_STATUS_TSE_BUSY 0x00000400 +#define A5XX_RBBM_STATUS_VBIF_BUSY 0x00000200 +#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST 0x00000100 +#define A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST 0x00000080 +#define A5XX_RBBM_STATUS_CP_BUSY 0x00000040 +#define A5XX_RBBM_STATUS_GPMU_MASTER_BUSY 0x00000020 +#define A5XX_RBBM_STATUS_CP_CRASH_BUSY 0x00000010 +#define A5XX_RBBM_STATUS_CP_ETS_BUSY 0x00000008 +#define A5XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004 +#define A5XX_RBBM_STATUS_CP_ME_BUSY 0x00000002 +#define A5XX_RBBM_STATUS_HI_BUSY 0x00000001 + +#define REG_A5XX_RBBM_STATUS3 0x00000530 + +#define REG_A5XX_RBBM_INT_0_STATUS 0x000004e1 + +#define REG_A5XX_RBBM_AHB_ME_SPLIT_STATUS 0x000004f0 + +#define REG_A5XX_RBBM_AHB_PFP_SPLIT_STATUS 0x000004f1 + +#define REG_A5XX_RBBM_AHB_ETS_SPLIT_STATUS 0x000004f3 + +#define REG_A5XX_RBBM_AHB_ERROR_STATUS 0x000004f4 + +#define REG_A5XX_RBBM_PERFCTR_CNTL 0x00000464 + +#define REG_A5XX_RBBM_PERFCTR_LOAD_CMD0 0x00000465 + +#define REG_A5XX_RBBM_PERFCTR_LOAD_CMD1 0x00000466 + +#define REG_A5XX_RBBM_PERFCTR_LOAD_CMD2 0x00000467 + +#define REG_A5XX_RBBM_PERFCTR_LOAD_CMD3 0x00000468 + +#define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000469 + +#define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x0000046a + +#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0 0x0000046b + +#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_1 0x0000046c + +#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_2 0x0000046d + +#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000046e + +#define REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000046f + +#define REG_A5XX_RBBM_AHB_ERROR 0x000004ed + +#define REG_A5XX_RBBM_CFG_DBGBUS_EVENT_LOGIC 0x00000504 + +#define REG_A5XX_RBBM_CFG_DBGBUS_OVER 0x00000505 + +#define REG_A5XX_RBBM_CFG_DBGBUS_COUNT0 0x00000506 + +#define REG_A5XX_RBBM_CFG_DBGBUS_COUNT1 0x00000507 + +#define REG_A5XX_RBBM_CFG_DBGBUS_COUNT2 0x00000508 + +#define REG_A5XX_RBBM_CFG_DBGBUS_COUNT3 0x00000509 + +#define REG_A5XX_RBBM_CFG_DBGBUS_COUNT4 0x0000050a + +#define REG_A5XX_RBBM_CFG_DBGBUS_COUNT5 0x0000050b + +#define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_ADDR 0x0000050c + +#define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF0 0x0000050d + +#define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF1 0x0000050e + +#define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF2 0x0000050f + +#define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF3 0x00000510 + +#define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF4 0x00000511 + +#define REG_A5XX_RBBM_CFG_DBGBUS_MISR0 0x00000512 + +#define REG_A5XX_RBBM_CFG_DBGBUS_MISR1 0x00000513 + +#define REG_A5XX_RBBM_ISDB_CNT 0x00000533 + +#define REG_A5XX_RBBM_SECVID_TRUST_CONFIG 0x0000f000 + +#define REG_A5XX_RBBM_SECVID_TRUST_CNTL 0x0000f400 + +#define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO 0x0000f800 + +#define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI 0x0000f801 + +#define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE 0x0000f802 + +#define REG_A5XX_RBBM_SECVID_TSB_CNTL 0x0000f803 + +#define REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_LO 0x0000f804 + +#define REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_HI 0x0000f805 + +#define REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_LO 0x0000f806 + +#define REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_HI 0x0000f807 + +#define REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL 0x0000f810 + +#define REG_A5XX_VSC_PIPE_DATA_LENGTH_0 0x00000c00 + +#define REG_A5XX_VSC_PERFCTR_VSC_SEL_0 0x00000c60 + +#define REG_A5XX_VSC_PERFCTR_VSC_SEL_1 0x00000c61 + +#define REG_A5XX_VSC_BIN_SIZE 0x00000cdd +#define A5XX_VSC_BIN_SIZE_WINDOW_OFFSET_DISABLE 0x80000000 +#define A5XX_VSC_BIN_SIZE_X__MASK 0x00007fff +#define A5XX_VSC_BIN_SIZE_X__SHIFT 0 +static inline uint32_t A5XX_VSC_BIN_SIZE_X(uint32_t val) +{ + return ((val) << A5XX_VSC_BIN_SIZE_X__SHIFT) & A5XX_VSC_BIN_SIZE_X__MASK; +} +#define A5XX_VSC_BIN_SIZE_Y__MASK 0x7fff0000 +#define A5XX_VSC_BIN_SIZE_Y__SHIFT 16 +static inline uint32_t A5XX_VSC_BIN_SIZE_Y(uint32_t val) +{ + return ((val) << A5XX_VSC_BIN_SIZE_Y__SHIFT) & A5XX_VSC_BIN_SIZE_Y__MASK; +} + +#define REG_A5XX_GRAS_ADDR_MODE_CNTL 0x00000c81 + +#define REG_A5XX_GRAS_PERFCTR_TSE_SEL_0 0x00000c90 + +#define REG_A5XX_GRAS_PERFCTR_TSE_SEL_1 0x00000c91 + +#define REG_A5XX_GRAS_PERFCTR_TSE_SEL_2 0x00000c92 + +#define REG_A5XX_GRAS_PERFCTR_TSE_SEL_3 0x00000c93 + +#define REG_A5XX_GRAS_PERFCTR_RAS_SEL_0 0x00000c94 + +#define REG_A5XX_GRAS_PERFCTR_RAS_SEL_1 0x00000c95 + +#define REG_A5XX_GRAS_PERFCTR_RAS_SEL_2 0x00000c96 + +#define REG_A5XX_GRAS_PERFCTR_RAS_SEL_3 0x00000c97 + +#define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_0 0x00000c98 + +#define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_1 0x00000c99 + +#define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_2 0x00000c9a + +#define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_3 0x00000c9b + +#define REG_A5XX_RB_DBG_ECO_CNTL 0x00000cc4 + +#define REG_A5XX_RB_ADDR_MODE_CNTL 0x00000cc5 + +#define REG_A5XX_RB_MODE_CNTL 0x00000cc6 + +#define REG_A5XX_RB_CCU_CNTL 0x00000cc7 + +#define REG_A5XX_RB_PERFCTR_RB_SEL_0 0x00000cd0 + +#define REG_A5XX_RB_PERFCTR_RB_SEL_1 0x00000cd1 + +#define REG_A5XX_RB_PERFCTR_RB_SEL_2 0x00000cd2 + +#define REG_A5XX_RB_PERFCTR_RB_SEL_3 0x00000cd3 + +#define REG_A5XX_RB_PERFCTR_RB_SEL_4 0x00000cd4 + +#define REG_A5XX_RB_PERFCTR_RB_SEL_5 0x00000cd5 + +#define REG_A5XX_RB_PERFCTR_RB_SEL_6 0x00000cd6 + +#define REG_A5XX_RB_PERFCTR_RB_SEL_7 0x00000cd7 + +#define REG_A5XX_RB_PERFCTR_CCU_SEL_0 0x00000cd8 + +#define REG_A5XX_RB_PERFCTR_CCU_SEL_1 0x00000cd9 + +#define REG_A5XX_RB_PERFCTR_CCU_SEL_2 0x00000cda + +#define REG_A5XX_RB_PERFCTR_CCU_SEL_3 0x00000cdb + +#define REG_A5XX_RB_POWERCTR_RB_SEL_0 0x00000ce0 + +#define REG_A5XX_RB_POWERCTR_RB_SEL_1 0x00000ce1 + +#define REG_A5XX_RB_POWERCTR_RB_SEL_2 0x00000ce2 + +#define REG_A5XX_RB_POWERCTR_RB_SEL_3 0x00000ce3 + +#define REG_A5XX_RB_POWERCTR_CCU_SEL_0 0x00000ce4 + +#define REG_A5XX_RB_POWERCTR_CCU_SEL_1 0x00000ce5 + +#define REG_A5XX_RB_PERFCTR_CMP_SEL_0 0x00000cec + +#define REG_A5XX_RB_PERFCTR_CMP_SEL_1 0x00000ced + +#define REG_A5XX_RB_PERFCTR_CMP_SEL_2 0x00000cee + +#define REG_A5XX_RB_PERFCTR_CMP_SEL_3 0x00000cef + +#define REG_A5XX_PC_DBG_ECO_CNTL 0x00000d00 +#define A5XX_PC_DBG_ECO_CNTL_TWOPASSUSEWFI 0x00000100 + +#define REG_A5XX_PC_ADDR_MODE_CNTL 0x00000d01 + +#define REG_A5XX_PC_MODE_CNTL 0x00000d02 + +#define REG_A5XX_UNKNOWN_0D08 0x00000d08 + +#define REG_A5XX_UNKNOWN_0D09 0x00000d09 + +#define REG_A5XX_PC_PERFCTR_PC_SEL_0 0x00000d10 + +#define REG_A5XX_PC_PERFCTR_PC_SEL_1 0x00000d11 + +#define REG_A5XX_PC_PERFCTR_PC_SEL_2 0x00000d12 + +#define REG_A5XX_PC_PERFCTR_PC_SEL_3 0x00000d13 + +#define REG_A5XX_PC_PERFCTR_PC_SEL_4 0x00000d14 + +#define REG_A5XX_PC_PERFCTR_PC_SEL_5 0x00000d15 + +#define REG_A5XX_PC_PERFCTR_PC_SEL_6 0x00000d16 + +#define REG_A5XX_PC_PERFCTR_PC_SEL_7 0x00000d17 + +#define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0 0x00000e00 + +#define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_1 0x00000e01 + +#define REG_A5XX_HLSQ_ADDR_MODE_CNTL 0x00000e05 + +#define REG_A5XX_HLSQ_MODE_CNTL 0x00000e06 + +#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x00000e10 + +#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x00000e11 + +#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x00000e12 + +#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x00000e13 + +#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x00000e14 + +#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x00000e15 + +#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_6 0x00000e16 + +#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_7 0x00000e17 + +#define REG_A5XX_HLSQ_SPTP_RDSEL 0x00000f08 + +#define REG_A5XX_HLSQ_DBG_READ_SEL 0x0000bc00 + +#define REG_A5XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000a000 + +#define REG_A5XX_VFD_ADDR_MODE_CNTL 0x00000e41 + +#define REG_A5XX_VFD_MODE_CNTL 0x00000e42 + +#define REG_A5XX_VFD_PERFCTR_VFD_SEL_0 0x00000e50 + +#define REG_A5XX_VFD_PERFCTR_VFD_SEL_1 0x00000e51 + +#define REG_A5XX_VFD_PERFCTR_VFD_SEL_2 0x00000e52 + +#define REG_A5XX_VFD_PERFCTR_VFD_SEL_3 0x00000e53 + +#define REG_A5XX_VFD_PERFCTR_VFD_SEL_4 0x00000e54 + +#define REG_A5XX_VFD_PERFCTR_VFD_SEL_5 0x00000e55 + +#define REG_A5XX_VFD_PERFCTR_VFD_SEL_6 0x00000e56 + +#define REG_A5XX_VFD_PERFCTR_VFD_SEL_7 0x00000e57 + +#define REG_A5XX_VPC_DBG_ECO_CNTL 0x00000e60 + +#define REG_A5XX_VPC_ADDR_MODE_CNTL 0x00000e61 + +#define REG_A5XX_VPC_MODE_CNTL 0x00000e62 + +#define REG_A5XX_VPC_PERFCTR_VPC_SEL_0 0x00000e64 + +#define REG_A5XX_VPC_PERFCTR_VPC_SEL_1 0x00000e65 + +#define REG_A5XX_VPC_PERFCTR_VPC_SEL_2 0x00000e66 + +#define REG_A5XX_VPC_PERFCTR_VPC_SEL_3 0x00000e67 + +#define REG_A5XX_UCHE_ADDR_MODE_CNTL 0x00000e80 + +#define REG_A5XX_UCHE_SVM_CNTL 0x00000e82 + +#define REG_A5XX_UCHE_WRITE_THRU_BASE_LO 0x00000e87 + +#define REG_A5XX_UCHE_WRITE_THRU_BASE_HI 0x00000e88 + +#define REG_A5XX_UCHE_TRAP_BASE_LO 0x00000e89 + +#define REG_A5XX_UCHE_TRAP_BASE_HI 0x00000e8a + +#define REG_A5XX_UCHE_GMEM_RANGE_MIN_LO 0x00000e8b + +#define REG_A5XX_UCHE_GMEM_RANGE_MIN_HI 0x00000e8c + +#define REG_A5XX_UCHE_GMEM_RANGE_MAX_LO 0x00000e8d + +#define REG_A5XX_UCHE_GMEM_RANGE_MAX_HI 0x00000e8e + +#define REG_A5XX_UCHE_DBG_ECO_CNTL_2 0x00000e8f + +#define REG_A5XX_UCHE_DBG_ECO_CNTL 0x00000e90 + +#define REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_LO 0x00000e91 + +#define REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_HI 0x00000e92 + +#define REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_LO 0x00000e93 + +#define REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_HI 0x00000e94 + +#define REG_A5XX_UCHE_CACHE_INVALIDATE 0x00000e95 + +#define REG_A5XX_UCHE_CACHE_WAYS 0x00000e96 + +#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000ea0 + +#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000ea1 + +#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000ea2 + +#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000ea3 + +#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000ea4 + +#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000ea5 + +#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000ea6 + +#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000ea7 + +#define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_0 0x00000ea8 + +#define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_1 0x00000ea9 + +#define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_2 0x00000eaa + +#define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_3 0x00000eab + +#define REG_A5XX_UCHE_TRAP_LOG_LO 0x00000eb1 + +#define REG_A5XX_UCHE_TRAP_LOG_HI 0x00000eb2 + +#define REG_A5XX_SP_DBG_ECO_CNTL 0x00000ec0 + +#define REG_A5XX_SP_ADDR_MODE_CNTL 0x00000ec1 + +#define REG_A5XX_SP_MODE_CNTL 0x00000ec2 + +#define REG_A5XX_SP_PERFCTR_SP_SEL_0 0x00000ed0 + +#define REG_A5XX_SP_PERFCTR_SP_SEL_1 0x00000ed1 + +#define REG_A5XX_SP_PERFCTR_SP_SEL_2 0x00000ed2 + +#define REG_A5XX_SP_PERFCTR_SP_SEL_3 0x00000ed3 + +#define REG_A5XX_SP_PERFCTR_SP_SEL_4 0x00000ed4 + +#define REG_A5XX_SP_PERFCTR_SP_SEL_5 0x00000ed5 + +#define REG_A5XX_SP_PERFCTR_SP_SEL_6 0x00000ed6 + +#define REG_A5XX_SP_PERFCTR_SP_SEL_7 0x00000ed7 + +#define REG_A5XX_SP_PERFCTR_SP_SEL_8 0x00000ed8 + +#define REG_A5XX_SP_PERFCTR_SP_SEL_9 0x00000ed9 + +#define REG_A5XX_SP_PERFCTR_SP_SEL_10 0x00000eda + +#define REG_A5XX_SP_PERFCTR_SP_SEL_11 0x00000edb + +#define REG_A5XX_SP_POWERCTR_SP_SEL_0 0x00000edc + +#define REG_A5XX_SP_POWERCTR_SP_SEL_1 0x00000edd + +#define REG_A5XX_SP_POWERCTR_SP_SEL_2 0x00000ede + +#define REG_A5XX_SP_POWERCTR_SP_SEL_3 0x00000edf + +#define REG_A5XX_TPL1_ADDR_MODE_CNTL 0x00000f01 + +#define REG_A5XX_TPL1_MODE_CNTL 0x00000f02 + +#define REG_A5XX_TPL1_PERFCTR_TP_SEL_0 0x00000f10 + +#define REG_A5XX_TPL1_PERFCTR_TP_SEL_1 0x00000f11 + +#define REG_A5XX_TPL1_PERFCTR_TP_SEL_2 0x00000f12 + +#define REG_A5XX_TPL1_PERFCTR_TP_SEL_3 0x00000f13 + +#define REG_A5XX_TPL1_PERFCTR_TP_SEL_4 0x00000f14 + +#define REG_A5XX_TPL1_PERFCTR_TP_SEL_5 0x00000f15 + +#define REG_A5XX_TPL1_PERFCTR_TP_SEL_6 0x00000f16 + +#define REG_A5XX_TPL1_PERFCTR_TP_SEL_7 0x00000f17 + +#define REG_A5XX_TPL1_POWERCTR_TP_SEL_0 0x00000f18 + +#define REG_A5XX_TPL1_POWERCTR_TP_SEL_1 0x00000f19 + +#define REG_A5XX_TPL1_POWERCTR_TP_SEL_2 0x00000f1a + +#define REG_A5XX_TPL1_POWERCTR_TP_SEL_3 0x00000f1b + +#define REG_A5XX_VBIF_VERSION 0x00003000 + +#define REG_A5XX_VBIF_CLKON 0x00003001 + +#define REG_A5XX_VBIF_ABIT_SORT 0x00003028 + +#define REG_A5XX_VBIF_ABIT_SORT_CONF 0x00003029 + +#define REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049 + +#define REG_A5XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a + +#define REG_A5XX_VBIF_IN_RD_LIM_CONF0 0x0000302c + +#define REG_A5XX_VBIF_IN_RD_LIM_CONF1 0x0000302d + +#define REG_A5XX_VBIF_XIN_HALT_CTRL0 0x00003080 + +#define REG_A5XX_VBIF_XIN_HALT_CTRL1 0x00003081 + +#define REG_A5XX_VBIF_TEST_BUS_OUT_CTRL 0x00003084 + +#define REG_A5XX_VBIF_TEST_BUS1_CTRL0 0x00003085 + +#define REG_A5XX_VBIF_TEST_BUS1_CTRL1 0x00003086 + +#define REG_A5XX_VBIF_TEST_BUS2_CTRL0 0x00003087 + +#define REG_A5XX_VBIF_TEST_BUS2_CTRL1 0x00003088 + +#define REG_A5XX_VBIF_TEST_BUS_OUT 0x0000308c + +#define REG_A5XX_VBIF_PERF_CNT_SEL0 0x000030d0 + +#define REG_A5XX_VBIF_PERF_CNT_SEL1 0x000030d1 + +#define REG_A5XX_VBIF_PERF_CNT_SEL2 0x000030d2 + +#define REG_A5XX_VBIF_PERF_CNT_SEL3 0x000030d3 + +#define REG_A5XX_VBIF_PERF_CNT_LOW0 0x000030d8 + +#define REG_A5XX_VBIF_PERF_CNT_LOW1 0x000030d9 + +#define REG_A5XX_VBIF_PERF_CNT_LOW2 0x000030da + +#define REG_A5XX_VBIF_PERF_CNT_LOW3 0x000030db + +#define REG_A5XX_VBIF_PERF_CNT_HIGH0 0x000030e0 + +#define REG_A5XX_VBIF_PERF_CNT_HIGH1 0x000030e1 + +#define REG_A5XX_VBIF_PERF_CNT_HIGH2 0x000030e2 + +#define REG_A5XX_VBIF_PERF_CNT_HIGH3 0x000030e3 + +#define REG_A5XX_VBIF_PERF_PWR_CNT_EN0 0x00003100 + +#define REG_A5XX_VBIF_PERF_PWR_CNT_EN1 0x00003101 + +#define REG_A5XX_VBIF_PERF_PWR_CNT_EN2 0x00003102 + +#define REG_A5XX_VBIF_PERF_PWR_CNT_LOW0 0x00003110 + +#define REG_A5XX_VBIF_PERF_PWR_CNT_LOW1 0x00003111 + +#define REG_A5XX_VBIF_PERF_PWR_CNT_LOW2 0x00003112 + +#define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH0 0x00003118 + +#define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH1 0x00003119 + +#define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a + +#define REG_A5XX_GPMU_INST_RAM_BASE 0x00008800 + +#define REG_A5XX_GPMU_DATA_RAM_BASE 0x00009800 + +#define REG_A5XX_GPMU_SP_POWER_CNTL 0x0000a881 + +#define REG_A5XX_GPMU_RBCCU_CLOCK_CNTL 0x0000a886 + +#define REG_A5XX_GPMU_RBCCU_POWER_CNTL 0x0000a887 + +#define REG_A5XX_GPMU_SP_PWR_CLK_STATUS 0x0000a88b +#define A5XX_GPMU_SP_PWR_CLK_STATUS_PWR_ON 0x00100000 + +#define REG_A5XX_GPMU_RBCCU_PWR_CLK_STATUS 0x0000a88d +#define A5XX_GPMU_RBCCU_PWR_CLK_STATUS_PWR_ON 0x00100000 + +#define REG_A5XX_GPMU_PWR_COL_STAGGER_DELAY 0x0000a891 + +#define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_CTRL 0x0000a892 + +#define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_HYST 0x0000a893 + +#define REG_A5XX_GPMU_PWR_COL_BINNING_CTRL 0x0000a894 + +#define REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL 0x0000a8a3 + +#define REG_A5XX_GPMU_WFI_CONFIG 0x0000a8c1 + +#define REG_A5XX_GPMU_RBBM_INTR_INFO 0x0000a8d6 + +#define REG_A5XX_GPMU_CM3_SYSRESET 0x0000a8d8 + +#define REG_A5XX_GPMU_GENERAL_0 0x0000a8e0 + +#define REG_A5XX_GPMU_GENERAL_1 0x0000a8e1 + +#define REG_A5XX_SP_POWER_COUNTER_0_LO 0x0000a840 + +#define REG_A5XX_SP_POWER_COUNTER_0_HI 0x0000a841 + +#define REG_A5XX_SP_POWER_COUNTER_1_LO 0x0000a842 + +#define REG_A5XX_SP_POWER_COUNTER_1_HI 0x0000a843 + +#define REG_A5XX_SP_POWER_COUNTER_2_LO 0x0000a844 + +#define REG_A5XX_SP_POWER_COUNTER_2_HI 0x0000a845 + +#define REG_A5XX_SP_POWER_COUNTER_3_LO 0x0000a846 + +#define REG_A5XX_SP_POWER_COUNTER_3_HI 0x0000a847 + +#define REG_A5XX_TP_POWER_COUNTER_0_LO 0x0000a848 + +#define REG_A5XX_TP_POWER_COUNTER_0_HI 0x0000a849 + +#define REG_A5XX_TP_POWER_COUNTER_1_LO 0x0000a84a + +#define REG_A5XX_TP_POWER_COUNTER_1_HI 0x0000a84b + +#define REG_A5XX_TP_POWER_COUNTER_2_LO 0x0000a84c + +#define REG_A5XX_TP_POWER_COUNTER_2_HI 0x0000a84d + +#define REG_A5XX_TP_POWER_COUNTER_3_LO 0x0000a84e + +#define REG_A5XX_TP_POWER_COUNTER_3_HI 0x0000a84f + +#define REG_A5XX_RB_POWER_COUNTER_0_LO 0x0000a850 + +#define REG_A5XX_RB_POWER_COUNTER_0_HI 0x0000a851 + +#define REG_A5XX_RB_POWER_COUNTER_1_LO 0x0000a852 + +#define REG_A5XX_RB_POWER_COUNTER_1_HI 0x0000a853 + +#define REG_A5XX_RB_POWER_COUNTER_2_LO 0x0000a854 + +#define REG_A5XX_RB_POWER_COUNTER_2_HI 0x0000a855 + +#define REG_A5XX_RB_POWER_COUNTER_3_LO 0x0000a856 + +#define REG_A5XX_RB_POWER_COUNTER_3_HI 0x0000a857 + +#define REG_A5XX_CCU_POWER_COUNTER_0_LO 0x0000a858 + +#define REG_A5XX_CCU_POWER_COUNTER_0_HI 0x0000a859 + +#define REG_A5XX_CCU_POWER_COUNTER_1_LO 0x0000a85a + +#define REG_A5XX_CCU_POWER_COUNTER_1_HI 0x0000a85b + +#define REG_A5XX_UCHE_POWER_COUNTER_0_LO 0x0000a85c + +#define REG_A5XX_UCHE_POWER_COUNTER_0_HI 0x0000a85d + +#define REG_A5XX_UCHE_POWER_COUNTER_1_LO 0x0000a85e + +#define REG_A5XX_UCHE_POWER_COUNTER_1_HI 0x0000a85f + +#define REG_A5XX_UCHE_POWER_COUNTER_2_LO 0x0000a860 + +#define REG_A5XX_UCHE_POWER_COUNTER_2_HI 0x0000a861 + +#define REG_A5XX_UCHE_POWER_COUNTER_3_LO 0x0000a862 + +#define REG_A5XX_UCHE_POWER_COUNTER_3_HI 0x0000a863 + +#define REG_A5XX_CP_POWER_COUNTER_0_LO 0x0000a864 + +#define REG_A5XX_CP_POWER_COUNTER_0_HI 0x0000a865 + +#define REG_A5XX_CP_POWER_COUNTER_1_LO 0x0000a866 + +#define REG_A5XX_CP_POWER_COUNTER_1_HI 0x0000a867 + +#define REG_A5XX_CP_POWER_COUNTER_2_LO 0x0000a868 + +#define REG_A5XX_CP_POWER_COUNTER_2_HI 0x0000a869 + +#define REG_A5XX_CP_POWER_COUNTER_3_LO 0x0000a86a + +#define REG_A5XX_CP_POWER_COUNTER_3_HI 0x0000a86b + +#define REG_A5XX_GPMU_POWER_COUNTER_0_LO 0x0000a86c + +#define REG_A5XX_GPMU_POWER_COUNTER_0_HI 0x0000a86d + +#define REG_A5XX_GPMU_POWER_COUNTER_1_LO 0x0000a86e + +#define REG_A5XX_GPMU_POWER_COUNTER_1_HI 0x0000a86f + +#define REG_A5XX_GPMU_POWER_COUNTER_2_LO 0x0000a870 + +#define REG_A5XX_GPMU_POWER_COUNTER_2_HI 0x0000a871 + +#define REG_A5XX_GPMU_POWER_COUNTER_3_LO 0x0000a872 + +#define REG_A5XX_GPMU_POWER_COUNTER_3_HI 0x0000a873 + +#define REG_A5XX_GPMU_POWER_COUNTER_4_LO 0x0000a874 + +#define REG_A5XX_GPMU_POWER_COUNTER_4_HI 0x0000a875 + +#define REG_A5XX_GPMU_POWER_COUNTER_5_LO 0x0000a876 + +#define REG_A5XX_GPMU_POWER_COUNTER_5_HI 0x0000a877 + +#define REG_A5XX_GPMU_POWER_COUNTER_ENABLE 0x0000a878 + +#define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_LO 0x0000a879 + +#define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_HI 0x0000a87a + +#define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_RESET 0x0000a87b + +#define REG_A5XX_GPMU_POWER_COUNTER_SELECT_0 0x0000a87c + +#define REG_A5XX_GPMU_POWER_COUNTER_SELECT_1 0x0000a87d + +#define REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL 0x0000a8a3 + +#define REG_A5XX_GPMU_THROTTLE_UNMASK_FORCE_CTRL 0x0000a8a8 + +#define REG_A5XX_GPMU_TEMP_SENSOR_ID 0x0000ac00 + +#define REG_A5XX_GPMU_TEMP_SENSOR_CONFIG 0x0000ac01 + +#define REG_A5XX_GPMU_TEMP_VAL 0x0000ac02 + +#define REG_A5XX_GPMU_DELTA_TEMP_THRESHOLD 0x0000ac03 + +#define REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_STATUS 0x0000ac05 + +#define REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_EN_MASK 0x0000ac06 + +#define REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_0_1 0x0000ac40 + +#define REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_2_3 0x0000ac41 + +#define REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_0_1 0x0000ac42 + +#define REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_2_3 0x0000ac43 + +#define REG_A5XX_GPMU_BASE_LEAKAGE 0x0000ac46 + +#define REG_A5XX_GPMU_GPMU_VOLTAGE 0x0000ac60 + +#define REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_STATUS 0x0000ac61 + +#define REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_EN_MASK 0x0000ac62 + +#define REG_A5XX_GPMU_GPMU_PWR_THRESHOLD 0x0000ac80 + +#define REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_CTRL 0x0000acc4 + +#define REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_STATUS 0x0000acc5 + +#define REG_A5XX_GDPM_CONFIG1 0x0000b80c + +#define REG_A5XX_GDPM_CONFIG2 0x0000b80d + +#define REG_A5XX_GDPM_INT_EN 0x0000b80f + +#define REG_A5XX_GDPM_INT_MASK 0x0000b811 + +#define REG_A5XX_GPMU_BEC_ENABLE 0x0000b9a0 + +#define REG_A5XX_GPU_CS_SENSOR_GENERAL_STATUS 0x0000c41a + +#define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_0 0x0000c41d + +#define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_2 0x0000c41f + +#define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_4 0x0000c421 + +#define REG_A5XX_GPU_CS_ENABLE_REG 0x0000c520 + +#define REG_A5XX_GPU_CS_AMP_CALIBRATION_CONTROL1 0x0000c557 + +#define REG_A5XX_GRAS_CL_CNTL 0x0000e000 + +#define REG_A5XX_UNKNOWN_E001 0x0000e001 + +#define REG_A5XX_UNKNOWN_E004 0x0000e004 + +#define REG_A5XX_GRAS_CNTL 0x0000e005 +#define A5XX_GRAS_CNTL_VARYING 0x00000001 + +#define REG_A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x0000e006 +#define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000003ff +#define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT 0 +static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val) +{ + return ((val) << A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK; +} +#define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK 0x000ffc00 +#define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT 10 +static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val) +{ + return ((val) << A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK; +} + +#define REG_A5XX_GRAS_CL_VPORT_XOFFSET_0 0x0000e010 +#define A5XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff +#define A5XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0 +static inline uint32_t A5XX_GRAS_CL_VPORT_XOFFSET_0(float val) +{ + return ((fui(val)) << A5XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_XOFFSET_0__MASK; +} + +#define REG_A5XX_GRAS_CL_VPORT_XSCALE_0 0x0000e011 +#define A5XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff +#define A5XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0 +static inline uint32_t A5XX_GRAS_CL_VPORT_XSCALE_0(float val) +{ + return ((fui(val)) << A5XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_XSCALE_0__MASK; +} + +#define REG_A5XX_GRAS_CL_VPORT_YOFFSET_0 0x0000e012 +#define A5XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff +#define A5XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0 +static inline uint32_t A5XX_GRAS_CL_VPORT_YOFFSET_0(float val) +{ + return ((fui(val)) << A5XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_YOFFSET_0__MASK; +} + +#define REG_A5XX_GRAS_CL_VPORT_YSCALE_0 0x0000e013 +#define A5XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff +#define A5XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0 +static inline uint32_t A5XX_GRAS_CL_VPORT_YSCALE_0(float val) +{ + return ((fui(val)) << A5XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_YSCALE_0__MASK; +} + +#define REG_A5XX_GRAS_CL_VPORT_ZOFFSET_0 0x0000e014 +#define A5XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff +#define A5XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0 +static inline uint32_t A5XX_GRAS_CL_VPORT_ZOFFSET_0(float val) +{ + return ((fui(val)) << A5XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_ZOFFSET_0__MASK; +} + +#define REG_A5XX_GRAS_CL_VPORT_ZSCALE_0 0x0000e015 +#define A5XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff +#define A5XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0 +static inline uint32_t A5XX_GRAS_CL_VPORT_ZSCALE_0(float val) +{ + return ((fui(val)) << A5XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_ZSCALE_0__MASK; +} + +#define REG_A5XX_GRAS_SU_CNTL 0x0000e090 +#define A5XX_GRAS_SU_CNTL_FRONT_CW 0x00000004 +#define A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK 0x000007f8 +#define A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT 3 +static inline uint32_t A5XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val) +{ + return ((((int32_t)(val * 4.0))) << A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK; +} +#define A5XX_GRAS_SU_CNTL_POLY_OFFSET 0x00000800 +#define A5XX_GRAS_SU_CNTL_MSAA_ENABLE 0x00002000 + +#define REG_A5XX_GRAS_SU_POINT_MINMAX 0x0000e091 +#define A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff +#define A5XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0 +static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MIN(float val) +{ + return ((((uint32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK; +} +#define A5XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000 +#define A5XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16 +static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MAX(float val) +{ + return ((((uint32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A5XX_GRAS_SU_POINT_MINMAX_MAX__MASK; +} + +#define REG_A5XX_GRAS_SU_POINT_SIZE 0x0000e092 +#define A5XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff +#define A5XX_GRAS_SU_POINT_SIZE__SHIFT 0 +static inline uint32_t A5XX_GRAS_SU_POINT_SIZE(float val) +{ + return ((((int32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_SIZE__SHIFT) & A5XX_GRAS_SU_POINT_SIZE__MASK; +} + +#define REG_A5XX_UNKNOWN_E093 0x0000e093 + +#define REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL 0x0000e094 +#define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_ALPHA_TEST_ENABLE 0x00000001 + +#define REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE 0x0000e095 +#define A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff +#define A5XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0 +static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_SCALE(float val) +{ + return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK; +} + +#define REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET 0x0000e096 +#define A5XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff +#define A5XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0 +static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) +{ + return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; +} + +#define REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP 0x0000e097 +#define A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK 0xffffffff +#define A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT 0 +static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val) +{ + return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK; +} + +#define REG_A5XX_GRAS_SU_DEPTH_BUFFER_INFO 0x0000e098 +#define A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 +#define A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 +static inline uint32_t A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val) +{ + return ((val) << A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; +} + +#define REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL 0x0000e099 + +#define REG_A5XX_GRAS_SC_CNTL 0x0000e0a0 +#define A5XX_GRAS_SC_CNTL_SAMPLES_PASSED 0x00008000 + +#define REG_A5XX_GRAS_SC_BIN_CNTL 0x0000e0a1 + +#define REG_A5XX_GRAS_SC_RAS_MSAA_CNTL 0x0000e0a2 +#define A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 +#define A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 +static inline uint32_t A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) +{ + return ((val) << A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__MASK; +} + +#define REG_A5XX_GRAS_SC_DEST_MSAA_CNTL 0x0000e0a3 +#define A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 +#define A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 +static inline uint32_t A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) +{ + return ((val) << A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__MASK; +} +#define A5XX_GRAS_SC_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 + +#define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_CNTL 0x0000e0a4 + +#define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0 0x0000e0aa +#define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000 +#define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK 0x00007fff +#define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT 0 +static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(uint32_t val) +{ + return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK; +} +#define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK 0x7fff0000 +#define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT 16 +static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(uint32_t val) +{ + return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK; +} + +#define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0 0x0000e0ab +#define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000 +#define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK 0x00007fff +#define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT 0 +static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X(uint32_t val) +{ + return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK; +} +#define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK 0x7fff0000 +#define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT 16 +static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y(uint32_t val) +{ + return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK; +} + +#define REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0 0x0000e0ca +#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000 +#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK 0x00007fff +#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT 0 +static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(uint32_t val) +{ + return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK; +} +#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK 0x7fff0000 +#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT 16 +static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(uint32_t val) +{ + return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK; +} + +#define REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0 0x0000e0cb +#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000 +#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK 0x00007fff +#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT 0 +static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X(uint32_t val) +{ + return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK; +} +#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK 0x7fff0000 +#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT 16 +static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y(uint32_t val) +{ + return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK; +} + +#define REG_A5XX_GRAS_SC_WINDOW_SCISSOR_TL 0x0000e0ea +#define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 +#define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff +#define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 +static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) +{ + return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; +} +#define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 +#define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 +static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) +{ + return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; +} + +#define REG_A5XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000e0eb +#define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 +#define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff +#define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 +static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) +{ + return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; +} +#define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 +#define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 +static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) +{ + return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; +} + +#define REG_A5XX_GRAS_LRZ_CNTL 0x0000e100 + +#define REG_A5XX_GRAS_LRZ_BUFFER_BASE_LO 0x0000e101 + +#define REG_A5XX_GRAS_LRZ_BUFFER_BASE_HI 0x0000e102 + +#define REG_A5XX_GRAS_LRZ_BUFFER_PITCH 0x0000e103 + +#define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO 0x0000e104 + +#define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI 0x0000e105 + +#define REG_A5XX_RB_CNTL 0x0000e140 +#define A5XX_RB_CNTL_WIDTH__MASK 0x000000ff +#define A5XX_RB_CNTL_WIDTH__SHIFT 0 +static inline uint32_t A5XX_RB_CNTL_WIDTH(uint32_t val) +{ + return ((val >> 5) << A5XX_RB_CNTL_WIDTH__SHIFT) & A5XX_RB_CNTL_WIDTH__MASK; +} +#define A5XX_RB_CNTL_HEIGHT__MASK 0x0001fe00 +#define A5XX_RB_CNTL_HEIGHT__SHIFT 9 +static inline uint32_t A5XX_RB_CNTL_HEIGHT(uint32_t val) +{ + return ((val >> 5) << A5XX_RB_CNTL_HEIGHT__SHIFT) & A5XX_RB_CNTL_HEIGHT__MASK; +} +#define A5XX_RB_CNTL_BYPASS 0x00020000 + +#define REG_A5XX_RB_RENDER_CNTL 0x0000e141 +#define A5XX_RB_RENDER_CNTL_SAMPLES_PASSED 0x00000040 +#define A5XX_RB_RENDER_CNTL_FLAG_DEPTH 0x00004000 +#define A5XX_RB_RENDER_CNTL_FLAG_DEPTH2 0x00008000 +#define A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK 0x00ff0000 +#define A5XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT 16 +static inline uint32_t A5XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val) +{ + return ((val) << A5XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK; +} +#define A5XX_RB_RENDER_CNTL_FLAG_MRTS2__MASK 0xff000000 +#define A5XX_RB_RENDER_CNTL_FLAG_MRTS2__SHIFT 24 +static inline uint32_t A5XX_RB_RENDER_CNTL_FLAG_MRTS2(uint32_t val) +{ + return ((val) << A5XX_RB_RENDER_CNTL_FLAG_MRTS2__SHIFT) & A5XX_RB_RENDER_CNTL_FLAG_MRTS2__MASK; +} + +#define REG_A5XX_RB_RAS_MSAA_CNTL 0x0000e142 +#define A5XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 +#define A5XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 +static inline uint32_t A5XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) +{ + return ((val) << A5XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK; +} + +#define REG_A5XX_RB_DEST_MSAA_CNTL 0x0000e143 +#define A5XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 +#define A5XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 +static inline uint32_t A5XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) +{ + return ((val) << A5XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK; +} +#define A5XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 + +#define REG_A5XX_RB_RENDER_CONTROL0 0x0000e144 +#define A5XX_RB_RENDER_CONTROL0_VARYING 0x00000001 +#define A5XX_RB_RENDER_CONTROL0_XCOORD 0x00000040 +#define A5XX_RB_RENDER_CONTROL0_YCOORD 0x00000080 +#define A5XX_RB_RENDER_CONTROL0_ZCOORD 0x00000100 +#define A5XX_RB_RENDER_CONTROL0_WCOORD 0x00000200 + +#define REG_A5XX_RB_RENDER_CONTROL1 0x0000e145 +#define A5XX_RB_RENDER_CONTROL1_FACENESS 0x00000002 + +#define REG_A5XX_RB_FS_OUTPUT_CNTL 0x0000e146 +#define A5XX_RB_FS_OUTPUT_CNTL_MRT__MASK 0x0000000f +#define A5XX_RB_FS_OUTPUT_CNTL_MRT__SHIFT 0 +static inline uint32_t A5XX_RB_FS_OUTPUT_CNTL_MRT(uint32_t val) +{ + return ((val) << A5XX_RB_FS_OUTPUT_CNTL_MRT__SHIFT) & A5XX_RB_FS_OUTPUT_CNTL_MRT__MASK; +} +#define A5XX_RB_FS_OUTPUT_CNTL_FRAG_WRITES_Z 0x00000020 + +#define REG_A5XX_RB_RENDER_COMPONENTS 0x0000e147 +#define A5XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f +#define A5XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0 +static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT0(uint32_t val) +{ + return ((val) << A5XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT0__MASK; +} +#define A5XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0 +#define A5XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4 +static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT1(uint32_t val) +{ + return ((val) << A5XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT1__MASK; +} +#define A5XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00 +#define A5XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8 +static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT2(uint32_t val) +{ + return ((val) << A5XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT2__MASK; +} +#define A5XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000 +#define A5XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12 +static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT3(uint32_t val) +{ + return ((val) << A5XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT3__MASK; +} +#define A5XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000 +#define A5XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16 +static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT4(uint32_t val) +{ + return ((val) << A5XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT4__MASK; +} +#define A5XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000 +#define A5XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20 +static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT5(uint32_t val) +{ + return ((val) << A5XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT5__MASK; +} +#define A5XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000 +#define A5XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24 +static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT6(uint32_t val) +{ + return ((val) << A5XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT6__MASK; +} +#define A5XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000 +#define A5XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28 +static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT7(uint32_t val) +{ + return ((val) << A5XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT7__MASK; +} + +static inline uint32_t REG_A5XX_RB_MRT(uint32_t i0) { return 0x0000e150 + 0x7*i0; } + +static inline uint32_t REG_A5XX_RB_MRT_CONTROL(uint32_t i0) { return 0x0000e150 + 0x7*i0; } +#define A5XX_RB_MRT_CONTROL_BLEND 0x00000001 +#define A5XX_RB_MRT_CONTROL_BLEND2 0x00000002 +#define A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x00000780 +#define A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 7 +static inline uint32_t A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) +{ + return ((val) << A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; +} + +static inline uint32_t REG_A5XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x0000e151 + 0x7*i0; } +#define A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f +#define A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0 +static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) +{ + return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; +} +#define A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0 +#define A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5 +static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) +{ + return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; +} +#define A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00 +#define A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8 +static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) +{ + return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; +} +#define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000 +#define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16 +static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) +{ + return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; +} +#define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000 +#define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21 +static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) +{ + return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; +} +#define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000 +#define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24 +static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) +{ + return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; +} + +static inline uint32_t REG_A5XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x0000e152 + 0x7*i0; } +#define A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x000000ff +#define A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 +static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) +{ + return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; +} +#define A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x00000300 +#define A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 8 +static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a5xx_tile_mode val) +{ + return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; +} +#define A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000 +#define A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13 +static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) +{ + return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; +} +#define A5XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00008000 + +static inline uint32_t REG_A5XX_RB_MRT_PITCH(uint32_t i0) { return 0x0000e153 + 0x7*i0; } +#define A5XX_RB_MRT_PITCH__MASK 0xffffffff +#define A5XX_RB_MRT_PITCH__SHIFT 0 +static inline uint32_t A5XX_RB_MRT_PITCH(uint32_t val) +{ + return ((val >> 6) << A5XX_RB_MRT_PITCH__SHIFT) & A5XX_RB_MRT_PITCH__MASK; +} + +static inline uint32_t REG_A5XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x0000e154 + 0x7*i0; } +#define A5XX_RB_MRT_ARRAY_PITCH__MASK 0xffffffff +#define A5XX_RB_MRT_ARRAY_PITCH__SHIFT 0 +static inline uint32_t A5XX_RB_MRT_ARRAY_PITCH(uint32_t val) +{ + return ((val >> 6) << A5XX_RB_MRT_ARRAY_PITCH__SHIFT) & A5XX_RB_MRT_ARRAY_PITCH__MASK; +} + +static inline uint32_t REG_A5XX_RB_MRT_BASE_LO(uint32_t i0) { return 0x0000e155 + 0x7*i0; } + +static inline uint32_t REG_A5XX_RB_MRT_BASE_HI(uint32_t i0) { return 0x0000e156 + 0x7*i0; } + +#define REG_A5XX_RB_BLEND_RED 0x0000e1a0 +#define A5XX_RB_BLEND_RED_UINT__MASK 0x000000ff +#define A5XX_RB_BLEND_RED_UINT__SHIFT 0 +static inline uint32_t A5XX_RB_BLEND_RED_UINT(uint32_t val) +{ + return ((val) << A5XX_RB_BLEND_RED_UINT__SHIFT) & A5XX_RB_BLEND_RED_UINT__MASK; +} +#define A5XX_RB_BLEND_RED_SINT__MASK 0x0000ff00 +#define A5XX_RB_BLEND_RED_SINT__SHIFT 8 +static inline uint32_t A5XX_RB_BLEND_RED_SINT(uint32_t val) +{ + return ((val) << A5XX_RB_BLEND_RED_SINT__SHIFT) & A5XX_RB_BLEND_RED_SINT__MASK; +} +#define A5XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000 +#define A5XX_RB_BLEND_RED_FLOAT__SHIFT 16 +static inline uint32_t A5XX_RB_BLEND_RED_FLOAT(float val) +{ + return ((util_float_to_half(val)) << A5XX_RB_BLEND_RED_FLOAT__SHIFT) & A5XX_RB_BLEND_RED_FLOAT__MASK; +} + +#define REG_A5XX_RB_BLEND_RED_F32 0x0000e1a1 +#define A5XX_RB_BLEND_RED_F32__MASK 0xffffffff +#define A5XX_RB_BLEND_RED_F32__SHIFT 0 +static inline uint32_t A5XX_RB_BLEND_RED_F32(float val) +{ + return ((fui(val)) << A5XX_RB_BLEND_RED_F32__SHIFT) & A5XX_RB_BLEND_RED_F32__MASK; +} + +#define REG_A5XX_RB_BLEND_GREEN 0x0000e1a2 +#define A5XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff +#define A5XX_RB_BLEND_GREEN_UINT__SHIFT 0 +static inline uint32_t A5XX_RB_BLEND_GREEN_UINT(uint32_t val) +{ + return ((val) << A5XX_RB_BLEND_GREEN_UINT__SHIFT) & A5XX_RB_BLEND_GREEN_UINT__MASK; +} +#define A5XX_RB_BLEND_GREEN_SINT__MASK 0x0000ff00 +#define A5XX_RB_BLEND_GREEN_SINT__SHIFT 8 +static inline uint32_t A5XX_RB_BLEND_GREEN_SINT(uint32_t val) +{ + return ((val) << A5XX_RB_BLEND_GREEN_SINT__SHIFT) & A5XX_RB_BLEND_GREEN_SINT__MASK; +} +#define A5XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000 +#define A5XX_RB_BLEND_GREEN_FLOAT__SHIFT 16 +static inline uint32_t A5XX_RB_BLEND_GREEN_FLOAT(float val) +{ + return ((util_float_to_half(val)) << A5XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A5XX_RB_BLEND_GREEN_FLOAT__MASK; +} + +#define REG_A5XX_RB_BLEND_GREEN_F32 0x0000e1a3 +#define A5XX_RB_BLEND_GREEN_F32__MASK 0xffffffff +#define A5XX_RB_BLEND_GREEN_F32__SHIFT 0 +static inline uint32_t A5XX_RB_BLEND_GREEN_F32(float val) +{ + return ((fui(val)) << A5XX_RB_BLEND_GREEN_F32__SHIFT) & A5XX_RB_BLEND_GREEN_F32__MASK; +} + +#define REG_A5XX_RB_BLEND_BLUE 0x0000e1a4 +#define A5XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff +#define A5XX_RB_BLEND_BLUE_UINT__SHIFT 0 +static inline uint32_t A5XX_RB_BLEND_BLUE_UINT(uint32_t val) +{ + return ((val) << A5XX_RB_BLEND_BLUE_UINT__SHIFT) & A5XX_RB_BLEND_BLUE_UINT__MASK; +} +#define A5XX_RB_BLEND_BLUE_SINT__MASK 0x0000ff00 +#define A5XX_RB_BLEND_BLUE_SINT__SHIFT 8 +static inline uint32_t A5XX_RB_BLEND_BLUE_SINT(uint32_t val) +{ + return ((val) << A5XX_RB_BLEND_BLUE_SINT__SHIFT) & A5XX_RB_BLEND_BLUE_SINT__MASK; +} +#define A5XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000 +#define A5XX_RB_BLEND_BLUE_FLOAT__SHIFT 16 +static inline uint32_t A5XX_RB_BLEND_BLUE_FLOAT(float val) +{ + return ((util_float_to_half(val)) << A5XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A5XX_RB_BLEND_BLUE_FLOAT__MASK; +} + +#define REG_A5XX_RB_BLEND_BLUE_F32 0x0000e1a5 +#define A5XX_RB_BLEND_BLUE_F32__MASK 0xffffffff +#define A5XX_RB_BLEND_BLUE_F32__SHIFT 0 +static inline uint32_t A5XX_RB_BLEND_BLUE_F32(float val) +{ + return ((fui(val)) << A5XX_RB_BLEND_BLUE_F32__SHIFT) & A5XX_RB_BLEND_BLUE_F32__MASK; +} + +#define REG_A5XX_RB_BLEND_ALPHA 0x0000e1a6 +#define A5XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff +#define A5XX_RB_BLEND_ALPHA_UINT__SHIFT 0 +static inline uint32_t A5XX_RB_BLEND_ALPHA_UINT(uint32_t val) +{ + return ((val) << A5XX_RB_BLEND_ALPHA_UINT__SHIFT) & A5XX_RB_BLEND_ALPHA_UINT__MASK; +} +#define A5XX_RB_BLEND_ALPHA_SINT__MASK 0x0000ff00 +#define A5XX_RB_BLEND_ALPHA_SINT__SHIFT 8 +static inline uint32_t A5XX_RB_BLEND_ALPHA_SINT(uint32_t val) +{ + return ((val) << A5XX_RB_BLEND_ALPHA_SINT__SHIFT) & A5XX_RB_BLEND_ALPHA_SINT__MASK; +} +#define A5XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000 +#define A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16 +static inline uint32_t A5XX_RB_BLEND_ALPHA_FLOAT(float val) +{ + return ((util_float_to_half(val)) << A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A5XX_RB_BLEND_ALPHA_FLOAT__MASK; +} + +#define REG_A5XX_RB_BLEND_ALPHA_F32 0x0000e1a7 +#define A5XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff +#define A5XX_RB_BLEND_ALPHA_F32__SHIFT 0 +static inline uint32_t A5XX_RB_BLEND_ALPHA_F32(float val) +{ + return ((fui(val)) << A5XX_RB_BLEND_ALPHA_F32__SHIFT) & A5XX_RB_BLEND_ALPHA_F32__MASK; +} + +#define REG_A5XX_RB_ALPHA_CONTROL 0x0000e1a8 +#define A5XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff +#define A5XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0 +static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val) +{ + return ((val) << A5XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A5XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK; +} +#define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100 +#define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00 +#define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9 +static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) +{ + return ((val) << A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK; +} + +#define REG_A5XX_RB_BLEND_CNTL 0x0000e1a9 +#define A5XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff +#define A5XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT 0 +static inline uint32_t A5XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val) +{ + return ((val) << A5XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A5XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK; +} +#define A5XX_RB_BLEND_CNTL_INDEPENDENT_BLEND 0x00000100 +#define A5XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK 0xffff0000 +#define A5XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT 16 +static inline uint32_t A5XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val) +{ + return ((val) << A5XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A5XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK; +} + +#define REG_A5XX_RB_DEPTH_PLANE_CNTL 0x0000e1b0 +#define A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001 + +#define REG_A5XX_RB_DEPTH_CNTL 0x0000e1b1 +#define A5XX_RB_DEPTH_CNTL_Z_ENABLE 0x00000001 +#define A5XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE 0x00000002 +#define A5XX_RB_DEPTH_CNTL_ZFUNC__MASK 0x0000001c +#define A5XX_RB_DEPTH_CNTL_ZFUNC__SHIFT 2 +static inline uint32_t A5XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val) +{ + return ((val) << A5XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A5XX_RB_DEPTH_CNTL_ZFUNC__MASK; +} +#define A5XX_RB_DEPTH_CNTL_Z_TEST_ENABLE 0x00000040 + +#define REG_A5XX_RB_DEPTH_BUFFER_INFO 0x0000e1b2 +#define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 +#define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 +static inline uint32_t A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val) +{ + return ((val) << A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; +} + +#define REG_A5XX_RB_DEPTH_BUFFER_BASE_LO 0x0000e1b3 + +#define REG_A5XX_RB_DEPTH_BUFFER_BASE_HI 0x0000e1b4 + +#define REG_A5XX_RB_DEPTH_BUFFER_PITCH 0x0000e1b5 +#define A5XX_RB_DEPTH_BUFFER_PITCH__MASK 0xffffffff +#define A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT 0 +static inline uint32_t A5XX_RB_DEPTH_BUFFER_PITCH(uint32_t val) +{ + return ((val >> 5) << A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_PITCH__MASK; +} + +#define REG_A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x0000e1b6 +#define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK 0xffffffff +#define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0 +static inline uint32_t A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val) +{ + return ((val >> 5) << A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK; +} + +#define REG_A5XX_RB_STENCIL_CONTROL 0x0000e1c0 +#define A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001 +#define A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002 +#define A5XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004 +#define A5XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700 +#define A5XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8 +static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) +{ + return ((val) << A5XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A5XX_RB_STENCIL_CONTROL_FUNC__MASK; +} +#define A5XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800 +#define A5XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11 +static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) +{ + return ((val) << A5XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A5XX_RB_STENCIL_CONTROL_FAIL__MASK; +} +#define A5XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000 +#define A5XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14 +static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) +{ + return ((val) << A5XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZPASS__MASK; +} +#define A5XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000 +#define A5XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17 +static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) +{ + return ((val) << A5XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZFAIL__MASK; +} +#define A5XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000 +#define A5XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20 +static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) +{ + return ((val) << A5XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; +} +#define A5XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000 +#define A5XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23 +static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) +{ + return ((val) << A5XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; +} +#define A5XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000 +#define A5XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26 +static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) +{ + return ((val) << A5XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; +} +#define A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000 +#define A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29 +static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) +{ + return ((val) << A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; +} + +#define REG_A5XX_RB_STENCIL_INFO 0x0000e1c1 +#define A5XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001 + +#define REG_A5XX_RB_STENCIL_BASE_LO 0x0000e1c2 + +#define REG_A5XX_RB_STENCIL_BASE_HI 0x0000e1c3 + +#define REG_A5XX_RB_STENCIL_PITCH 0x0000e1c4 +#define A5XX_RB_STENCIL_PITCH__MASK 0xffffffff +#define A5XX_RB_STENCIL_PITCH__SHIFT 0 +static inline uint32_t A5XX_RB_STENCIL_PITCH(uint32_t val) +{ + return ((val >> 6) << A5XX_RB_STENCIL_PITCH__SHIFT) & A5XX_RB_STENCIL_PITCH__MASK; +} + +#define REG_A5XX_RB_STENCIL_ARRAY_PITCH 0x0000e1c5 +#define A5XX_RB_STENCIL_ARRAY_PITCH__MASK 0xffffffff +#define A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT 0 +static inline uint32_t A5XX_RB_STENCIL_ARRAY_PITCH(uint32_t val) +{ + return ((val >> 6) << A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT) & A5XX_RB_STENCIL_ARRAY_PITCH__MASK; +} + +#define REG_A5XX_RB_STENCILREFMASK 0x0000e1c6 +#define A5XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff +#define A5XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 +static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) +{ + return ((val) << A5XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILREF__MASK; +} +#define A5XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 +#define A5XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 +static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) +{ + return ((val) << A5XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILMASK__MASK; +} +#define A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 +#define A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 +static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) +{ + return ((val) << A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; +} + +#define REG_A5XX_UNKNOWN_E1C7 0x0000e1c7 + +#define REG_A5XX_RB_WINDOW_OFFSET 0x0000e1d0 +#define A5XX_RB_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000 +#define A5XX_RB_WINDOW_OFFSET_X__MASK 0x00007fff +#define A5XX_RB_WINDOW_OFFSET_X__SHIFT 0 +static inline uint32_t A5XX_RB_WINDOW_OFFSET_X(uint32_t val) +{ + return ((val) << A5XX_RB_WINDOW_OFFSET_X__SHIFT) & A5XX_RB_WINDOW_OFFSET_X__MASK; +} +#define A5XX_RB_WINDOW_OFFSET_Y__MASK 0x7fff0000 +#define A5XX_RB_WINDOW_OFFSET_Y__SHIFT 16 +static inline uint32_t A5XX_RB_WINDOW_OFFSET_Y(uint32_t val) +{ + return ((val) << A5XX_RB_WINDOW_OFFSET_Y__SHIFT) & A5XX_RB_WINDOW_OFFSET_Y__MASK; +} + +#define REG_A5XX_RB_BLIT_CNTL 0x0000e210 +#define A5XX_RB_BLIT_CNTL_BUF__MASK 0x0000003f +#define A5XX_RB_BLIT_CNTL_BUF__SHIFT 0 +static inline uint32_t A5XX_RB_BLIT_CNTL_BUF(enum a5xx_blit_buf val) +{ + return ((val) << A5XX_RB_BLIT_CNTL_BUF__SHIFT) & A5XX_RB_BLIT_CNTL_BUF__MASK; +} + +#define REG_A5XX_RB_RESOLVE_CNTL_1 0x0000e211 +#define A5XX_RB_RESOLVE_CNTL_1_WINDOW_OFFSET_DISABLE 0x80000000 +#define A5XX_RB_RESOLVE_CNTL_1_X__MASK 0x00007fff +#define A5XX_RB_RESOLVE_CNTL_1_X__SHIFT 0 +static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_X(uint32_t val) +{ + return ((val) << A5XX_RB_RESOLVE_CNTL_1_X__SHIFT) & A5XX_RB_RESOLVE_CNTL_1_X__MASK; +} +#define A5XX_RB_RESOLVE_CNTL_1_Y__MASK 0x7fff0000 +#define A5XX_RB_RESOLVE_CNTL_1_Y__SHIFT 16 +static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_Y(uint32_t val) +{ + return ((val) << A5XX_RB_RESOLVE_CNTL_1_Y__SHIFT) & A5XX_RB_RESOLVE_CNTL_1_Y__MASK; +} + +#define REG_A5XX_RB_RESOLVE_CNTL_2 0x0000e212 +#define A5XX_RB_RESOLVE_CNTL_2_WINDOW_OFFSET_DISABLE 0x80000000 +#define A5XX_RB_RESOLVE_CNTL_2_X__MASK 0x00007fff +#define A5XX_RB_RESOLVE_CNTL_2_X__SHIFT 0 +static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_X(uint32_t val) +{ + return ((val) << A5XX_RB_RESOLVE_CNTL_2_X__SHIFT) & A5XX_RB_RESOLVE_CNTL_2_X__MASK; +} +#define A5XX_RB_RESOLVE_CNTL_2_Y__MASK 0x7fff0000 +#define A5XX_RB_RESOLVE_CNTL_2_Y__SHIFT 16 +static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_Y(uint32_t val) +{ + return ((val) << A5XX_RB_RESOLVE_CNTL_2_Y__SHIFT) & A5XX_RB_RESOLVE_CNTL_2_Y__MASK; +} + +#define REG_A5XX_RB_RESOLVE_CNTL_3 0x0000e213 + +#define REG_A5XX_RB_BLIT_DST_LO 0x0000e214 + +#define REG_A5XX_RB_BLIT_DST_HI 0x0000e215 + +#define REG_A5XX_RB_BLIT_DST_PITCH 0x0000e216 +#define A5XX_RB_BLIT_DST_PITCH__MASK 0xffffffff +#define A5XX_RB_BLIT_DST_PITCH__SHIFT 0 +static inline uint32_t A5XX_RB_BLIT_DST_PITCH(uint32_t val) +{ + return ((val >> 6) << A5XX_RB_BLIT_DST_PITCH__SHIFT) & A5XX_RB_BLIT_DST_PITCH__MASK; +} + +#define REG_A5XX_RB_BLIT_DST_ARRAY_PITCH 0x0000e217 +#define A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK 0xffffffff +#define A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT 0 +static inline uint32_t A5XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val) +{ + return ((val >> 6) << A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK; +} + +#define REG_A5XX_RB_CLEAR_COLOR_DW0 0x0000e218 + +#define REG_A5XX_RB_CLEAR_COLOR_DW1 0x0000e219 + +#define REG_A5XX_RB_CLEAR_COLOR_DW2 0x0000e21a + +#define REG_A5XX_RB_CLEAR_COLOR_DW3 0x0000e21b + +#define REG_A5XX_RB_CLEAR_CNTL 0x0000e21c +#define A5XX_RB_CLEAR_CNTL_FAST_CLEAR 0x00000002 +#define A5XX_RB_CLEAR_CNTL_MASK__MASK 0x000000f0 +#define A5XX_RB_CLEAR_CNTL_MASK__SHIFT 4 +static inline uint32_t A5XX_RB_CLEAR_CNTL_MASK(uint32_t val) +{ + return ((val) << A5XX_RB_CLEAR_CNTL_MASK__SHIFT) & A5XX_RB_CLEAR_CNTL_MASK__MASK; +} + +#define REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_LO 0x0000e240 + +#define REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_HI 0x0000e241 + +#define REG_A5XX_RB_DEPTH_FLAG_BUFFER_PITCH 0x0000e242 + +static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x0000e243 + 0x4*i0; } + +static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) { return 0x0000e243 + 0x4*i0; } + +static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0) { return 0x0000e244 + 0x4*i0; } + +static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x0000e245 + 0x4*i0; } +#define A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK 0xffffffff +#define A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT 0 +static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t val) +{ + return ((val >> 6) << A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT) & A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK; +} + +static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t i0) { return 0x0000e246 + 0x4*i0; } +#define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK 0xffffffff +#define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0 +static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t val) +{ + return ((val >> 6) << A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK; +} + +#define REG_A5XX_RB_BLIT_FLAG_DST_LO 0x0000e263 + +#define REG_A5XX_RB_BLIT_FLAG_DST_HI 0x0000e264 + +#define REG_A5XX_RB_BLIT_FLAG_DST_PITCH 0x0000e265 +#define A5XX_RB_BLIT_FLAG_DST_PITCH__MASK 0xffffffff +#define A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT 0 +static inline uint32_t A5XX_RB_BLIT_FLAG_DST_PITCH(uint32_t val) +{ + return ((val >> 6) << A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_PITCH__MASK; +} + +#define REG_A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH 0x0000e266 +#define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK 0xffffffff +#define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT 0 +static inline uint32_t A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH(uint32_t val) +{ + return ((val >> 6) << A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK; +} + +#define REG_A5XX_VPC_CNTL_0 0x0000e280 +#define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK 0x0000007f +#define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT 0 +static inline uint32_t A5XX_VPC_CNTL_0_STRIDE_IN_VPC(uint32_t val) +{ + return ((val) << A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT) & A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK; +} +#define A5XX_VPC_CNTL_0_VARYING 0x00000800 + +static inline uint32_t REG_A5XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x0000e282 + 0x1*i0; } + +static inline uint32_t REG_A5XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x0000e282 + 0x1*i0; } + +static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000e28a + 0x1*i0; } + +static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000e28a + 0x1*i0; } + +#define REG_A5XX_UNKNOWN_E292 0x0000e292 + +#define REG_A5XX_UNKNOWN_E293 0x0000e293 + +static inline uint32_t REG_A5XX_VPC_VAR(uint32_t i0) { return 0x0000e294 + 0x1*i0; } + +static inline uint32_t REG_A5XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x0000e294 + 0x1*i0; } + +#define REG_A5XX_VPC_GS_SIV_CNTL 0x0000e298 + +#define REG_A5XX_UNKNOWN_E29A 0x0000e29a + +#define REG_A5XX_VPC_PACK 0x0000e29d +#define A5XX_VPC_PACK_NUMNONPOSVAR__MASK 0x000000ff +#define A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT 0 +static inline uint32_t A5XX_VPC_PACK_NUMNONPOSVAR(uint32_t val) +{ + return ((val) << A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT) & A5XX_VPC_PACK_NUMNONPOSVAR__MASK; +} + +#define REG_A5XX_VPC_FS_PRIMITIVEID_CNTL 0x0000e2a0 + +#define REG_A5XX_UNKNOWN_E2A1 0x0000e2a1 + +#define REG_A5XX_VPC_SO_OVERRIDE 0x0000e2a2 + +#define REG_A5XX_VPC_SO_BUFFER_BASE_LO_0 0x0000e2a7 + +#define REG_A5XX_VPC_SO_BUFFER_BASE_HI_0 0x0000e2a8 + +#define REG_A5XX_VPC_SO_BUFFER_SIZE_0 0x0000e2a9 + +#define REG_A5XX_UNKNOWN_E2AB 0x0000e2ab + +#define REG_A5XX_VPC_SO_FLUSH_BASE_LO_0 0x0000e2ac + +#define REG_A5XX_VPC_SO_FLUSH_BASE_HI_0 0x0000e2ad + +#define REG_A5XX_UNKNOWN_E2AE 0x0000e2ae + +#define REG_A5XX_UNKNOWN_E2B2 0x0000e2b2 + +#define REG_A5XX_UNKNOWN_E2B9 0x0000e2b9 + +#define REG_A5XX_UNKNOWN_E2C0 0x0000e2c0 + +#define REG_A5XX_PC_PRIMITIVE_CNTL 0x0000e384 +#define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK 0x0000007f +#define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT 0 +static inline uint32_t A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(uint32_t val) +{ + return ((val) << A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT) & A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK; +} + +#define REG_A5XX_PC_PRIM_VTX_CNTL 0x0000e385 +#define A5XX_PC_PRIM_VTX_CNTL_PSIZE 0x00000800 + +#define REG_A5XX_PC_RASTER_CNTL 0x0000e388 + +#define REG_A5XX_UNKNOWN_E389 0x0000e389 + +#define REG_A5XX_PC_RESTART_INDEX 0x0000e38c + +#define REG_A5XX_UNKNOWN_E38D 0x0000e38d + +#define REG_A5XX_PC_GS_PARAM 0x0000e38e + +#define REG_A5XX_PC_HS_PARAM 0x0000e38f + +#define REG_A5XX_PC_POWER_CNTL 0x0000e3b0 + +#define REG_A5XX_VFD_CONTROL_0 0x0000e400 +#define A5XX_VFD_CONTROL_0_VTXCNT__MASK 0x0000003f +#define A5XX_VFD_CONTROL_0_VTXCNT__SHIFT 0 +static inline uint32_t A5XX_VFD_CONTROL_0_VTXCNT(uint32_t val) +{ + return ((val) << A5XX_VFD_CONTROL_0_VTXCNT__SHIFT) & A5XX_VFD_CONTROL_0_VTXCNT__MASK; +} + +#define REG_A5XX_VFD_CONTROL_1 0x0000e401 +#define A5XX_VFD_CONTROL_1_REGID4INST__MASK 0x0000ff00 +#define A5XX_VFD_CONTROL_1_REGID4INST__SHIFT 8 +static inline uint32_t A5XX_VFD_CONTROL_1_REGID4INST(uint32_t val) +{ + return ((val) << A5XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A5XX_VFD_CONTROL_1_REGID4INST__MASK; +} +#define A5XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000 +#define A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16 +static inline uint32_t A5XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) +{ + return ((val) << A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A5XX_VFD_CONTROL_1_REGID4VTX__MASK; +} + +#define REG_A5XX_VFD_CONTROL_2 0x0000e402 + +#define REG_A5XX_VFD_CONTROL_3 0x0000e403 + +#define REG_A5XX_VFD_CONTROL_4 0x0000e404 + +#define REG_A5XX_VFD_CONTROL_5 0x0000e405 + +#define REG_A5XX_VFD_INDEX_OFFSET 0x0000e408 + +#define REG_A5XX_VFD_INSTANCE_START_OFFSET 0x0000e409 + +static inline uint32_t REG_A5XX_VFD_FETCH(uint32_t i0) { return 0x0000e40a + 0x4*i0; } + +static inline uint32_t REG_A5XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000e40a + 0x4*i0; } + +static inline uint32_t REG_A5XX_VFD_FETCH_BASE_HI(uint32_t i0) { return 0x0000e40b + 0x4*i0; } + +static inline uint32_t REG_A5XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000e40c + 0x4*i0; } + +static inline uint32_t REG_A5XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000e40d + 0x4*i0; } + +static inline uint32_t REG_A5XX_VFD_DECODE(uint32_t i0) { return 0x0000e48a + 0x2*i0; } + +static inline uint32_t REG_A5XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000e48a + 0x2*i0; } +#define A5XX_VFD_DECODE_INSTR_IDX__MASK 0x0000001f +#define A5XX_VFD_DECODE_INSTR_IDX__SHIFT 0 +static inline uint32_t A5XX_VFD_DECODE_INSTR_IDX(uint32_t val) +{ + return ((val) << A5XX_VFD_DECODE_INSTR_IDX__SHIFT) & A5XX_VFD_DECODE_INSTR_IDX__MASK; +} +#define A5XX_VFD_DECODE_INSTR_FORMAT__MASK 0x3ff00000 +#define A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT 20 +static inline uint32_t A5XX_VFD_DECODE_INSTR_FORMAT(enum a5xx_vtx_fmt val) +{ + return ((val) << A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A5XX_VFD_DECODE_INSTR_FORMAT__MASK; +} +#define A5XX_VFD_DECODE_INSTR_SWAP__MASK 0xc0000000 +#define A5XX_VFD_DECODE_INSTR_SWAP__SHIFT 30 +static inline uint32_t A5XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) +{ + return ((val) << A5XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A5XX_VFD_DECODE_INSTR_SWAP__MASK; +} + +static inline uint32_t REG_A5XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000e48b + 0x2*i0; } + +static inline uint32_t REG_A5XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000e4ca + 0x1*i0; } + +static inline uint32_t REG_A5XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000e4ca + 0x1*i0; } +#define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK 0x0000000f +#define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT 0 +static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val) +{ + return ((val) << A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK; +} +#define A5XX_VFD_DEST_CNTL_INSTR_REGID__MASK 0x00000ff0 +#define A5XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT 4 +static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val) +{ + return ((val) << A5XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A5XX_VFD_DEST_CNTL_INSTR_REGID__MASK; +} + +#define REG_A5XX_VFD_POWER_CNTL 0x0000e4f0 + +#define REG_A5XX_SP_SP_CNTL 0x0000e580 + +#define REG_A5XX_SP_VS_CONTROL_REG 0x0000e584 +#define A5XX_SP_VS_CONTROL_REG_ENABLED 0x00000001 +#define A5XX_SP_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe +#define A5XX_SP_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1 +static inline uint32_t A5XX_SP_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) +{ + return ((val) << A5XX_SP_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; +} +#define A5XX_SP_VS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00 +#define A5XX_SP_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8 +static inline uint32_t A5XX_SP_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) +{ + return ((val) << A5XX_SP_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_VS_CONTROL_REG_SHADEROBJOFFSET__MASK; +} + +#define REG_A5XX_SP_FS_CONTROL_REG 0x0000e585 +#define A5XX_SP_FS_CONTROL_REG_ENABLED 0x00000001 +#define A5XX_SP_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe +#define A5XX_SP_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1 +static inline uint32_t A5XX_SP_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) +{ + return ((val) << A5XX_SP_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; +} +#define A5XX_SP_FS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00 +#define A5XX_SP_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8 +static inline uint32_t A5XX_SP_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) +{ + return ((val) << A5XX_SP_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_FS_CONTROL_REG_SHADEROBJOFFSET__MASK; +} + +#define REG_A5XX_SP_HS_CONTROL_REG 0x0000e586 +#define A5XX_SP_HS_CONTROL_REG_ENABLED 0x00000001 +#define A5XX_SP_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe +#define A5XX_SP_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1 +static inline uint32_t A5XX_SP_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) +{ + return ((val) << A5XX_SP_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; +} +#define A5XX_SP_HS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00 +#define A5XX_SP_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8 +static inline uint32_t A5XX_SP_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) +{ + return ((val) << A5XX_SP_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_HS_CONTROL_REG_SHADEROBJOFFSET__MASK; +} + +#define REG_A5XX_SP_DS_CONTROL_REG 0x0000e587 +#define A5XX_SP_DS_CONTROL_REG_ENABLED 0x00000001 +#define A5XX_SP_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe +#define A5XX_SP_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1 +static inline uint32_t A5XX_SP_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) +{ + return ((val) << A5XX_SP_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; +} +#define A5XX_SP_DS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00 +#define A5XX_SP_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8 +static inline uint32_t A5XX_SP_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) +{ + return ((val) << A5XX_SP_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_DS_CONTROL_REG_SHADEROBJOFFSET__MASK; +} + +#define REG_A5XX_SP_GS_CONTROL_REG 0x0000e588 +#define A5XX_SP_GS_CONTROL_REG_ENABLED 0x00000001 +#define A5XX_SP_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe +#define A5XX_SP_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1 +static inline uint32_t A5XX_SP_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) +{ + return ((val) << A5XX_SP_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; +} +#define A5XX_SP_GS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00 +#define A5XX_SP_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8 +static inline uint32_t A5XX_SP_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) +{ + return ((val) << A5XX_SP_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_GS_CONTROL_REG_SHADEROBJOFFSET__MASK; +} + +#define REG_A5XX_SP_CS_CONFIG 0x0000e589 + +#define REG_A5XX_SP_VS_CONFIG_MAX_CONST 0x0000e58a + +#define REG_A5XX_SP_FS_CONFIG_MAX_CONST 0x0000e58b + +#define REG_A5XX_SP_VS_CTRL_REG0 0x0000e590 +#define A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 +#define A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 +static inline uint32_t A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) +{ + return ((val) << A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; +} +#define A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 +#define A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 +static inline uint32_t A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) +{ + return ((val) << A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; +} +#define A5XX_SP_VS_CTRL_REG0_VARYING 0x00010000 +#define A5XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00100000 + +#define REG_A5XX_SP_PRIMITIVE_CNTL 0x0000e592 +#define A5XX_SP_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK 0x0000001f +#define A5XX_SP_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT 0 +static inline uint32_t A5XX_SP_PRIMITIVE_CNTL_STRIDE_IN_VPC(uint32_t val) +{ + return ((val >> 2) << A5XX_SP_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT) & A5XX_SP_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK; +} + +static inline uint32_t REG_A5XX_SP_VS_OUT(uint32_t i0) { return 0x0000e593 + 0x1*i0; } + +static inline uint32_t REG_A5XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000e593 + 0x1*i0; } +#define A5XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff +#define A5XX_SP_VS_OUT_REG_A_REGID__SHIFT 0 +static inline uint32_t A5XX_SP_VS_OUT_REG_A_REGID(uint32_t val) +{ + return ((val) << A5XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A5XX_SP_VS_OUT_REG_A_REGID__MASK; +} +#define A5XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00000f00 +#define A5XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 8 +static inline uint32_t A5XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) +{ + return ((val) << A5XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A5XX_SP_VS_OUT_REG_A_COMPMASK__MASK; +} +#define A5XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000 +#define A5XX_SP_VS_OUT_REG_B_REGID__SHIFT 16 +static inline uint32_t A5XX_SP_VS_OUT_REG_B_REGID(uint32_t val) +{ + return ((val) << A5XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A5XX_SP_VS_OUT_REG_B_REGID__MASK; +} +#define A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x0f000000 +#define A5XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 24 +static inline uint32_t A5XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) +{ + return ((val) << A5XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK; +} + +static inline uint32_t REG_A5XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; } + +static inline uint32_t REG_A5XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; } +#define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff +#define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0 +static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) +{ + return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; +} +#define A5XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 +#define A5XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8 +static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) +{ + return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; +} +#define A5XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 +#define A5XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16 +static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) +{ + return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; +} +#define A5XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 +#define A5XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24 +static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) +{ + return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; +} + +#define REG_A5XX_UNKNOWN_E5AB 0x0000e5ab + +#define REG_A5XX_SP_VS_OBJ_START_LO 0x0000e5ac + +#define REG_A5XX_SP_VS_OBJ_START_HI 0x0000e5ad + +#define REG_A5XX_SP_FS_CTRL_REG0 0x0000e5c0 +#define A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 +#define A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 +static inline uint32_t A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) +{ + return ((val) << A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; +} +#define A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 +#define A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 +static inline uint32_t A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) +{ + return ((val) << A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; +} +#define A5XX_SP_FS_CTRL_REG0_VARYING 0x00010000 +#define A5XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00100000 + +#define REG_A5XX_UNKNOWN_E5C2 0x0000e5c2 + +#define REG_A5XX_SP_FS_OBJ_START_LO 0x0000e5c3 + +#define REG_A5XX_SP_FS_OBJ_START_HI 0x0000e5c4 + +#define REG_A5XX_SP_BLEND_CNTL 0x0000e5c9 + +#define REG_A5XX_SP_FS_OUTPUT_CNTL 0x0000e5ca +#define A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK 0x0000000f +#define A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT 0 +static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_MRT(uint32_t val) +{ + return ((val) << A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK; +} +#define A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__MASK 0x00001fe0 +#define A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__SHIFT 5 +static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(uint32_t val) +{ + return ((val) << A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__MASK; +} +#define A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK 0x001fe000 +#define A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__SHIFT 13 +static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(uint32_t val) +{ + return ((val) << A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK; +} + +static inline uint32_t REG_A5XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000e5cb + 0x1*i0; } + +static inline uint32_t REG_A5XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000e5cb + 0x1*i0; } +#define A5XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff +#define A5XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0 +static inline uint32_t A5XX_SP_FS_OUTPUT_REG_REGID(uint32_t val) +{ + return ((val) << A5XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_REG_REGID__MASK; +} +#define A5XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100 + +static inline uint32_t REG_A5XX_SP_FS_MRT(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; } + +static inline uint32_t REG_A5XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; } +#define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x000000ff +#define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT 0 +static inline uint32_t A5XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a5xx_color_fmt val) +{ + return ((val) << A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK; +} + +#define REG_A5XX_UNKNOWN_E5DB 0x0000e5db + +#define REG_A5XX_SP_CS_CNTL_0 0x0000e5f0 + +#define REG_A5XX_UNKNOWN_E600 0x0000e600 + +#define REG_A5XX_UNKNOWN_E640 0x0000e640 + +#define REG_A5XX_TPL1_TP_RAS_MSAA_CNTL 0x0000e704 +#define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 +#define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 +static inline uint32_t A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) +{ + return ((val) << A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__MASK; +} + +#define REG_A5XX_TPL1_TP_DEST_MSAA_CNTL 0x0000e705 +#define A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 +#define A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 +static inline uint32_t A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) +{ + return ((val) << A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__MASK; +} +#define A5XX_TPL1_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 + +#define REG_A5XX_TPL1_VS_TEX_COUNT 0x0000e700 + +#define REG_A5XX_TPL1_VS_TEX_SAMP_LO 0x0000e722 + +#define REG_A5XX_TPL1_VS_TEX_SAMP_HI 0x0000e723 + +#define REG_A5XX_TPL1_VS_TEX_CONST_LO 0x0000e72a + +#define REG_A5XX_TPL1_VS_TEX_CONST_HI 0x0000e72b + +#define REG_A5XX_TPL1_FS_TEX_COUNT 0x0000e750 + +#define REG_A5XX_TPL1_FS_TEX_SAMP_LO 0x0000e75a + +#define REG_A5XX_TPL1_FS_TEX_SAMP_HI 0x0000e75b + +#define REG_A5XX_TPL1_FS_TEX_CONST_LO 0x0000e75e + +#define REG_A5XX_TPL1_FS_TEX_CONST_HI 0x0000e75f + +#define REG_A5XX_TPL1_TP_FS_ROTATION_CNTL 0x0000e764 + +#define REG_A5XX_HLSQ_CONTROL_0_REG 0x0000e784 + +#define REG_A5XX_HLSQ_CONTROL_1_REG 0x0000e785 +#define A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK 0x0000003f +#define A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT 0 +static inline uint32_t A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(uint32_t val) +{ + return ((val) << A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT) & A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK; +} + +#define REG_A5XX_HLSQ_CONTROL_2_REG 0x0000e786 +#define A5XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff +#define A5XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0 +static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) +{ + return ((val) << A5XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK; +} + +#define REG_A5XX_HLSQ_CONTROL_3_REG 0x0000e787 +#define A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK 0x000000ff +#define A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT 0 +static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(uint32_t val) +{ + return ((val) << A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK; +} + +#define REG_A5XX_HLSQ_CONTROL_4_REG 0x0000e788 +#define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000 +#define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16 +static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val) +{ + return ((val) << A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK; +} +#define A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000 +#define A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24 +static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val) +{ + return ((val) << A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK; +} + +#define REG_A5XX_HLSQ_UPDATE_CNTL 0x0000e78a + +#define REG_A5XX_HLSQ_VS_CONTROL_REG 0x0000e78b +#define A5XX_HLSQ_VS_CONTROL_REG_ENABLED 0x00000001 +#define A5XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe +#define A5XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1 +static inline uint32_t A5XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) +{ + return ((val) << A5XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; +} +#define A5XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00 +#define A5XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8 +static inline uint32_t A5XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) +{ + return ((val) << A5XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK; +} + +#define REG_A5XX_HLSQ_FS_CONTROL_REG 0x0000e78c +#define A5XX_HLSQ_FS_CONTROL_REG_ENABLED 0x00000001 +#define A5XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe +#define A5XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1 +static inline uint32_t A5XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) +{ + return ((val) << A5XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; +} +#define A5XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00 +#define A5XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8 +static inline uint32_t A5XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) +{ + return ((val) << A5XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK; +} + +#define REG_A5XX_HLSQ_HS_CONTROL_REG 0x0000e78d +#define A5XX_HLSQ_HS_CONTROL_REG_ENABLED 0x00000001 +#define A5XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe +#define A5XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1 +static inline uint32_t A5XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) +{ + return ((val) << A5XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; +} +#define A5XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00 +#define A5XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8 +static inline uint32_t A5XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) +{ + return ((val) << A5XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK; +} + +#define REG_A5XX_HLSQ_DS_CONTROL_REG 0x0000e78e +#define A5XX_HLSQ_DS_CONTROL_REG_ENABLED 0x00000001 +#define A5XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe +#define A5XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1 +static inline uint32_t A5XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) +{ + return ((val) << A5XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; +} +#define A5XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00 +#define A5XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8 +static inline uint32_t A5XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) +{ + return ((val) << A5XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK; +} + +#define REG_A5XX_HLSQ_GS_CONTROL_REG 0x0000e78f +#define A5XX_HLSQ_GS_CONTROL_REG_ENABLED 0x00000001 +#define A5XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe +#define A5XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1 +static inline uint32_t A5XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) +{ + return ((val) << A5XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; +} +#define A5XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00 +#define A5XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8 +static inline uint32_t A5XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) +{ + return ((val) << A5XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK; +} + +#define REG_A5XX_HLSQ_CS_CONFIG 0x0000e790 + +#define REG_A5XX_HLSQ_VS_CNTL 0x0000e791 +#define A5XX_HLSQ_VS_CNTL_INSTRLEN__MASK 0xfffffffe +#define A5XX_HLSQ_VS_CNTL_INSTRLEN__SHIFT 1 +static inline uint32_t A5XX_HLSQ_VS_CNTL_INSTRLEN(uint32_t val) +{ + return ((val) << A5XX_HLSQ_VS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_VS_CNTL_INSTRLEN__MASK; +} + +#define REG_A5XX_HLSQ_FS_CNTL 0x0000e792 +#define A5XX_HLSQ_FS_CNTL_INSTRLEN__MASK 0xfffffffe +#define A5XX_HLSQ_FS_CNTL_INSTRLEN__SHIFT 1 +static inline uint32_t A5XX_HLSQ_FS_CNTL_INSTRLEN(uint32_t val) +{ + return ((val) << A5XX_HLSQ_FS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_FS_CNTL_INSTRLEN__MASK; +} + +#define REG_A5XX_HLSQ_HS_CNTL 0x0000e793 +#define A5XX_HLSQ_HS_CNTL_INSTRLEN__MASK 0xfffffffe +#define A5XX_HLSQ_HS_CNTL_INSTRLEN__SHIFT 1 +static inline uint32_t A5XX_HLSQ_HS_CNTL_INSTRLEN(uint32_t val) +{ + return ((val) << A5XX_HLSQ_HS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_HS_CNTL_INSTRLEN__MASK; +} + +#define REG_A5XX_HLSQ_DS_CNTL 0x0000e794 +#define A5XX_HLSQ_DS_CNTL_INSTRLEN__MASK 0xfffffffe +#define A5XX_HLSQ_DS_CNTL_INSTRLEN__SHIFT 1 +static inline uint32_t A5XX_HLSQ_DS_CNTL_INSTRLEN(uint32_t val) +{ + return ((val) << A5XX_HLSQ_DS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_DS_CNTL_INSTRLEN__MASK; +} + +#define REG_A5XX_HLSQ_GS_CNTL 0x0000e795 +#define A5XX_HLSQ_GS_CNTL_INSTRLEN__MASK 0xfffffffe +#define A5XX_HLSQ_GS_CNTL_INSTRLEN__SHIFT 1 +static inline uint32_t A5XX_HLSQ_GS_CNTL_INSTRLEN(uint32_t val) +{ + return ((val) << A5XX_HLSQ_GS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_GS_CNTL_INSTRLEN__MASK; +} + +#define REG_A5XX_HLSQ_CS_CNTL 0x0000e796 +#define A5XX_HLSQ_CS_CNTL_INSTRLEN__MASK 0xfffffffe +#define A5XX_HLSQ_CS_CNTL_INSTRLEN__SHIFT 1 +static inline uint32_t A5XX_HLSQ_CS_CNTL_INSTRLEN(uint32_t val) +{ + return ((val) << A5XX_HLSQ_CS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_CS_CNTL_INSTRLEN__MASK; +} + +#define REG_A5XX_HLSQ_CS_KERNEL_GROUP_X 0x0000e7b9 + +#define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000e7ba + +#define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000e7bb + +#define REG_A5XX_HLSQ_CS_NDRANGE_0 0x0000e7b0 + +#define REG_A5XX_HLSQ_CS_NDRANGE_1 0x0000e7b1 + +#define REG_A5XX_HLSQ_CS_NDRANGE_2 0x0000e7b2 + +#define REG_A5XX_HLSQ_CS_NDRANGE_3 0x0000e7b3 + +#define REG_A5XX_HLSQ_CS_NDRANGE_4 0x0000e7b4 + +#define REG_A5XX_HLSQ_CS_NDRANGE_5 0x0000e7b5 + +#define REG_A5XX_HLSQ_CS_NDRANGE_6 0x0000e7b6 + +#define REG_A5XX_HLSQ_CS_CNTL_0 0x0000e7b7 + +#define REG_A5XX_HLSQ_CS_CNTL_1 0x0000e7b8 + +#define REG_A5XX_UNKNOWN_E7C0 0x0000e7c0 + +#define REG_A5XX_HLSQ_VS_CONSTLEN 0x0000e7c3 + +#define REG_A5XX_HLSQ_VS_INSTRLEN 0x0000e7c4 + +#define REG_A5XX_UNKNOWN_E7C5 0x0000e7c5 + +#define REG_A5XX_UNKNOWN_E7CA 0x0000e7ca + +#define REG_A5XX_HLSQ_FS_CONSTLEN 0x0000e7d7 + +#define REG_A5XX_HLSQ_FS_INSTRLEN 0x0000e7d8 + +#define REG_A5XX_HLSQ_HS_CONSTLEN 0x0000e7c8 + +#define REG_A5XX_HLSQ_HS_INSTRLEN 0x0000e7c9 + +#define REG_A5XX_HLSQ_DS_CONSTLEN 0x0000e7cd + +#define REG_A5XX_HLSQ_DS_INSTRLEN 0x0000e7ce + +#define REG_A5XX_UNKNOWN_E7CF 0x0000e7cf + +#define REG_A5XX_HLSQ_GS_CONSTLEN 0x0000e7d2 + +#define REG_A5XX_HLSQ_GS_INSTRLEN 0x0000e7d3 + +#define REG_A5XX_UNKNOWN_E7D4 0x0000e7d4 + +#define REG_A5XX_UNKNOWN_E7D9 0x0000e7d9 + +#define REG_A5XX_HLSQ_CONTEXT_SWITCH_CS_SW_3 0x0000e7dc + +#define REG_A5XX_HLSQ_CONTEXT_SWITCH_CS_SW_4 0x0000e7dd + +#define REG_A5XX_RB_2D_DST_FILL 0x00002101 + +#define REG_A5XX_RB_2D_SRC_INFO 0x00002107 +#define A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff +#define A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0 +static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) +{ + return ((val) << A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK; +} +#define A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00 +#define A5XX_RB_2D_SRC_INFO_COLOR_SWAP__SHIFT 10 +static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val) +{ + return ((val) << A5XX_RB_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK; +} + +#define REG_A5XX_RB_2D_SRC_LO 0x00002108 + +#define REG_A5XX_RB_2D_SRC_HI 0x00002109 + +#define REG_A5XX_RB_2D_DST_INFO 0x00002110 +#define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff +#define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT 0 +static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) +{ + return ((val) << A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK; +} +#define A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00 +#define A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT 10 +static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) +{ + return ((val) << A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK; +} + +#define REG_A5XX_RB_2D_SRC_FLAGS_LO 0x00002140 + +#define REG_A5XX_RB_2D_SRC_FLAGS_HI 0x00002141 + +#define REG_A5XX_RB_2D_DST_LO 0x00002111 + +#define REG_A5XX_RB_2D_DST_HI 0x00002112 + +#define REG_A5XX_RB_2D_DST_FLAGS_LO 0x00002143 + +#define REG_A5XX_RB_2D_DST_FLAGS_HI 0x00002144 + +#define REG_A5XX_GRAS_2D_SRC_INFO 0x00002181 +#define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff +#define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0 +static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) +{ + return ((val) << A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK; +} +#define A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00 +#define A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__SHIFT 10 +static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val) +{ + return ((val) << A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK; +} + +#define REG_A5XX_GRAS_2D_DST_INFO 0x00002182 +#define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff +#define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__SHIFT 0 +static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) +{ + return ((val) << A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK; +} +#define A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00 +#define A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT 10 +static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) +{ + return ((val) << A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT) & A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK; +} + +#define REG_A5XX_TEX_SAMP_0 0x00000000 +#define A5XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001 +#define A5XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006 +#define A5XX_TEX_SAMP_0_XY_MAG__SHIFT 1 +static inline uint32_t A5XX_TEX_SAMP_0_XY_MAG(enum a5xx_tex_filter val) +{ + return ((val) << A5XX_TEX_SAMP_0_XY_MAG__SHIFT) & A5XX_TEX_SAMP_0_XY_MAG__MASK; +} +#define A5XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018 +#define A5XX_TEX_SAMP_0_XY_MIN__SHIFT 3 +static inline uint32_t A5XX_TEX_SAMP_0_XY_MIN(enum a5xx_tex_filter val) +{ + return ((val) << A5XX_TEX_SAMP_0_XY_MIN__SHIFT) & A5XX_TEX_SAMP_0_XY_MIN__MASK; +} +#define A5XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0 +#define A5XX_TEX_SAMP_0_WRAP_S__SHIFT 5 +static inline uint32_t A5XX_TEX_SAMP_0_WRAP_S(enum a5xx_tex_clamp val) +{ + return ((val) << A5XX_TEX_SAMP_0_WRAP_S__SHIFT) & A5XX_TEX_SAMP_0_WRAP_S__MASK; +} +#define A5XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700 +#define A5XX_TEX_SAMP_0_WRAP_T__SHIFT 8 +static inline uint32_t A5XX_TEX_SAMP_0_WRAP_T(enum a5xx_tex_clamp val) +{ + return ((val) << A5XX_TEX_SAMP_0_WRAP_T__SHIFT) & A5XX_TEX_SAMP_0_WRAP_T__MASK; +} +#define A5XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800 +#define A5XX_TEX_SAMP_0_WRAP_R__SHIFT 11 +static inline uint32_t A5XX_TEX_SAMP_0_WRAP_R(enum a5xx_tex_clamp val) +{ + return ((val) << A5XX_TEX_SAMP_0_WRAP_R__SHIFT) & A5XX_TEX_SAMP_0_WRAP_R__MASK; +} +#define A5XX_TEX_SAMP_0_ANISO__MASK 0x0001c000 +#define A5XX_TEX_SAMP_0_ANISO__SHIFT 14 +static inline uint32_t A5XX_TEX_SAMP_0_ANISO(enum a5xx_tex_aniso val) +{ + return ((val) << A5XX_TEX_SAMP_0_ANISO__SHIFT) & A5XX_TEX_SAMP_0_ANISO__MASK; +} +#define A5XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000 +#define A5XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19 +static inline uint32_t A5XX_TEX_SAMP_0_LOD_BIAS(float val) +{ + return ((((int32_t)(val * 256.0))) << A5XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A5XX_TEX_SAMP_0_LOD_BIAS__MASK; +} + +#define REG_A5XX_TEX_SAMP_1 0x00000001 +#define A5XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e +#define A5XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1 +static inline uint32_t A5XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val) +{ + return ((val) << A5XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A5XX_TEX_SAMP_1_COMPARE_FUNC__MASK; +} +#define A5XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010 +#define A5XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020 +#define A5XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040 +#define A5XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00 +#define A5XX_TEX_SAMP_1_MAX_LOD__SHIFT 8 +static inline uint32_t A5XX_TEX_SAMP_1_MAX_LOD(float val) +{ + return ((((uint32_t)(val * 256.0))) << A5XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A5XX_TEX_SAMP_1_MAX_LOD__MASK; +} +#define A5XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000 +#define A5XX_TEX_SAMP_1_MIN_LOD__SHIFT 20 +static inline uint32_t A5XX_TEX_SAMP_1_MIN_LOD(float val) +{ + return ((((uint32_t)(val * 256.0))) << A5XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A5XX_TEX_SAMP_1_MIN_LOD__MASK; +} + +#define REG_A5XX_TEX_SAMP_2 0x00000002 + +#define REG_A5XX_TEX_SAMP_3 0x00000003 + +#define REG_A5XX_TEX_CONST_0 0x00000000 +#define A5XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003 +#define A5XX_TEX_CONST_0_TILE_MODE__SHIFT 0 +static inline uint32_t A5XX_TEX_CONST_0_TILE_MODE(enum a5xx_tile_mode val) +{ + return ((val) << A5XX_TEX_CONST_0_TILE_MODE__SHIFT) & A5XX_TEX_CONST_0_TILE_MODE__MASK; +} +#define A5XX_TEX_CONST_0_SRGB 0x00000004 +#define A5XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070 +#define A5XX_TEX_CONST_0_SWIZ_X__SHIFT 4 +static inline uint32_t A5XX_TEX_CONST_0_SWIZ_X(enum a5xx_tex_swiz val) +{ + return ((val) << A5XX_TEX_CONST_0_SWIZ_X__SHIFT) & A5XX_TEX_CONST_0_SWIZ_X__MASK; +} +#define A5XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380 +#define A5XX_TEX_CONST_0_SWIZ_Y__SHIFT 7 +static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Y(enum a5xx_tex_swiz val) +{ + return ((val) << A5XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A5XX_TEX_CONST_0_SWIZ_Y__MASK; +} +#define A5XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00 +#define A5XX_TEX_CONST_0_SWIZ_Z__SHIFT 10 +static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Z(enum a5xx_tex_swiz val) +{ + return ((val) << A5XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A5XX_TEX_CONST_0_SWIZ_Z__MASK; +} +#define A5XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000 +#define A5XX_TEX_CONST_0_SWIZ_W__SHIFT 13 +static inline uint32_t A5XX_TEX_CONST_0_SWIZ_W(enum a5xx_tex_swiz val) +{ + return ((val) << A5XX_TEX_CONST_0_SWIZ_W__SHIFT) & A5XX_TEX_CONST_0_SWIZ_W__MASK; +} +#define A5XX_TEX_CONST_0_FMT__MASK 0x3fc00000 +#define A5XX_TEX_CONST_0_FMT__SHIFT 22 +static inline uint32_t A5XX_TEX_CONST_0_FMT(enum a5xx_tex_fmt val) +{ + return ((val) << A5XX_TEX_CONST_0_FMT__SHIFT) & A5XX_TEX_CONST_0_FMT__MASK; +} +#define A5XX_TEX_CONST_0_SWAP__MASK 0xc0000000 +#define A5XX_TEX_CONST_0_SWAP__SHIFT 30 +static inline uint32_t A5XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val) +{ + return ((val) << A5XX_TEX_CONST_0_SWAP__SHIFT) & A5XX_TEX_CONST_0_SWAP__MASK; +} + +#define REG_A5XX_TEX_CONST_1 0x00000001 +#define A5XX_TEX_CONST_1_WIDTH__MASK 0x00007fff +#define A5XX_TEX_CONST_1_WIDTH__SHIFT 0 +static inline uint32_t A5XX_TEX_CONST_1_WIDTH(uint32_t val) +{ + return ((val) << A5XX_TEX_CONST_1_WIDTH__SHIFT) & A5XX_TEX_CONST_1_WIDTH__MASK; +} +#define A5XX_TEX_CONST_1_HEIGHT__MASK 0x3fff8000 +#define A5XX_TEX_CONST_1_HEIGHT__SHIFT 15 +static inline uint32_t A5XX_TEX_CONST_1_HEIGHT(uint32_t val) +{ + return ((val) << A5XX_TEX_CONST_1_HEIGHT__SHIFT) & A5XX_TEX_CONST_1_HEIGHT__MASK; +} + +#define REG_A5XX_TEX_CONST_2 0x00000002 +#define A5XX_TEX_CONST_2_FETCHSIZE__MASK 0x0000000f +#define A5XX_TEX_CONST_2_FETCHSIZE__SHIFT 0 +static inline uint32_t A5XX_TEX_CONST_2_FETCHSIZE(enum a5xx_tex_fetchsize val) +{ + return ((val) << A5XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A5XX_TEX_CONST_2_FETCHSIZE__MASK; +} +#define A5XX_TEX_CONST_2_PITCH__MASK 0x1fffff80 +#define A5XX_TEX_CONST_2_PITCH__SHIFT 7 +static inline uint32_t A5XX_TEX_CONST_2_PITCH(uint32_t val) +{ + return ((val) << A5XX_TEX_CONST_2_PITCH__SHIFT) & A5XX_TEX_CONST_2_PITCH__MASK; +} +#define A5XX_TEX_CONST_2_TYPE__MASK 0x60000000 +#define A5XX_TEX_CONST_2_TYPE__SHIFT 29 +static inline uint32_t A5XX_TEX_CONST_2_TYPE(enum a5xx_tex_type val) +{ + return ((val) << A5XX_TEX_CONST_2_TYPE__SHIFT) & A5XX_TEX_CONST_2_TYPE__MASK; +} + +#define REG_A5XX_TEX_CONST_3 0x00000003 +#define A5XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff +#define A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT 0 +static inline uint32_t A5XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val) +{ + return ((val >> 12) << A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A5XX_TEX_CONST_3_ARRAY_PITCH__MASK; +} +#define A5XX_TEX_CONST_3_FLAG 0x10000000 + +#define REG_A5XX_TEX_CONST_4 0x00000004 +#define A5XX_TEX_CONST_4_BASE_LO__MASK 0xffffffe0 +#define A5XX_TEX_CONST_4_BASE_LO__SHIFT 5 +static inline uint32_t A5XX_TEX_CONST_4_BASE_LO(uint32_t val) +{ + return ((val >> 5) << A5XX_TEX_CONST_4_BASE_LO__SHIFT) & A5XX_TEX_CONST_4_BASE_LO__MASK; +} + +#define REG_A5XX_TEX_CONST_5 0x00000005 +#define A5XX_TEX_CONST_5_BASE_HI__MASK 0x0001ffff +#define A5XX_TEX_CONST_5_BASE_HI__SHIFT 0 +static inline uint32_t A5XX_TEX_CONST_5_BASE_HI(uint32_t val) +{ + return ((val) << A5XX_TEX_CONST_5_BASE_HI__SHIFT) & A5XX_TEX_CONST_5_BASE_HI__MASK; +} +#define A5XX_TEX_CONST_5_DEPTH__MASK 0x3ffe0000 +#define A5XX_TEX_CONST_5_DEPTH__SHIFT 17 +static inline uint32_t A5XX_TEX_CONST_5_DEPTH(uint32_t val) +{ + return ((val) << A5XX_TEX_CONST_5_DEPTH__SHIFT) & A5XX_TEX_CONST_5_DEPTH__MASK; +} + +#define REG_A5XX_TEX_CONST_6 0x00000006 + +#define REG_A5XX_TEX_CONST_7 0x00000007 + +#define REG_A5XX_TEX_CONST_8 0x00000008 + +#define REG_A5XX_TEX_CONST_9 0x00000009 + +#define REG_A5XX_TEX_CONST_10 0x0000000a + +#define REG_A5XX_TEX_CONST_11 0x0000000b + + +#endif /* A5XX_XML */ diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c new file mode 100644 index 000000000000..b8647198c11c --- /dev/null +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -0,0 +1,888 @@ +/* Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include "msm_gem.h" +#include "a5xx_gpu.h" + +extern bool hang_debug; +static void a5xx_dump(struct msm_gpu *gpu); + +static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, + struct msm_file_private *ctx) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct msm_drm_private *priv = gpu->dev->dev_private; + struct msm_ringbuffer *ring = gpu->rb; + unsigned int i, ibs = 0; + + for (i = 0; i < submit->nr_cmds; i++) { + switch (submit->cmd[i].type) { + case MSM_SUBMIT_CMD_IB_TARGET_BUF: + break; + case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: + if (priv->lastctx == ctx) + break; + case MSM_SUBMIT_CMD_BUF: + OUT_PKT7(ring, CP_INDIRECT_BUFFER_PFE, 3); + OUT_RING(ring, lower_32_bits(submit->cmd[i].iova)); + OUT_RING(ring, upper_32_bits(submit->cmd[i].iova)); + OUT_RING(ring, submit->cmd[i].size); + ibs++; + break; + } + } + + OUT_PKT4(ring, REG_A5XX_CP_SCRATCH_REG(2), 1); + OUT_RING(ring, submit->fence->seqno); + + OUT_PKT7(ring, CP_EVENT_WRITE, 4); + OUT_RING(ring, CACHE_FLUSH_TS | (1 << 31)); + OUT_RING(ring, lower_32_bits(rbmemptr(adreno_gpu, fence))); + OUT_RING(ring, upper_32_bits(rbmemptr(adreno_gpu, fence))); + OUT_RING(ring, submit->fence->seqno); + + gpu->funcs->flush(gpu); +} + +struct a5xx_hwcg { + u32 offset; + u32 value; +}; + +static const struct a5xx_hwcg a530_hwcg[] = { + {REG_A5XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, + {REG_A5XX_RBBM_CLOCK_CNTL_SP1, 0x02222222}, + {REG_A5XX_RBBM_CLOCK_CNTL_SP2, 0x02222222}, + {REG_A5XX_RBBM_CLOCK_CNTL_SP3, 0x02222222}, + {REG_A5XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, + {REG_A5XX_RBBM_CLOCK_CNTL2_SP1, 0x02222220}, + {REG_A5XX_RBBM_CLOCK_CNTL2_SP2, 0x02222220}, + {REG_A5XX_RBBM_CLOCK_CNTL2_SP3, 0x02222220}, + {REG_A5XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, + {REG_A5XX_RBBM_CLOCK_HYST_SP1, 0x0000F3CF}, + {REG_A5XX_RBBM_CLOCK_HYST_SP2, 0x0000F3CF}, + {REG_A5XX_RBBM_CLOCK_HYST_SP3, 0x0000F3CF}, + {REG_A5XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, + {REG_A5XX_RBBM_CLOCK_DELAY_SP1, 0x00000080}, + {REG_A5XX_RBBM_CLOCK_DELAY_SP2, 0x00000080}, + {REG_A5XX_RBBM_CLOCK_DELAY_SP3, 0x00000080}, + {REG_A5XX_RBBM_CLOCK_CNTL_TP0, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL_TP1, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL_TP2, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL_TP3, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL2_TP2, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL2_TP3, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL3_TP0, 0x00002222}, + {REG_A5XX_RBBM_CLOCK_CNTL3_TP1, 0x00002222}, + {REG_A5XX_RBBM_CLOCK_CNTL3_TP2, 0x00002222}, + {REG_A5XX_RBBM_CLOCK_CNTL3_TP3, 0x00002222}, + {REG_A5XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, + {REG_A5XX_RBBM_CLOCK_HYST_TP1, 0x77777777}, + {REG_A5XX_RBBM_CLOCK_HYST_TP2, 0x77777777}, + {REG_A5XX_RBBM_CLOCK_HYST_TP3, 0x77777777}, + {REG_A5XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, + {REG_A5XX_RBBM_CLOCK_HYST2_TP1, 0x77777777}, + {REG_A5XX_RBBM_CLOCK_HYST2_TP2, 0x77777777}, + {REG_A5XX_RBBM_CLOCK_HYST2_TP3, 0x77777777}, + {REG_A5XX_RBBM_CLOCK_HYST3_TP0, 0x00007777}, + {REG_A5XX_RBBM_CLOCK_HYST3_TP1, 0x00007777}, + {REG_A5XX_RBBM_CLOCK_HYST3_TP2, 0x00007777}, + {REG_A5XX_RBBM_CLOCK_HYST3_TP3, 0x00007777}, + {REG_A5XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, + {REG_A5XX_RBBM_CLOCK_DELAY_TP1, 0x11111111}, + {REG_A5XX_RBBM_CLOCK_DELAY_TP2, 0x11111111}, + {REG_A5XX_RBBM_CLOCK_DELAY_TP3, 0x11111111}, + {REG_A5XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, + {REG_A5XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111}, + {REG_A5XX_RBBM_CLOCK_DELAY2_TP2, 0x11111111}, + {REG_A5XX_RBBM_CLOCK_DELAY2_TP3, 0x11111111}, + {REG_A5XX_RBBM_CLOCK_DELAY3_TP0, 0x00001111}, + {REG_A5XX_RBBM_CLOCK_DELAY3_TP1, 0x00001111}, + {REG_A5XX_RBBM_CLOCK_DELAY3_TP2, 0x00001111}, + {REG_A5XX_RBBM_CLOCK_DELAY3_TP3, 0x00001111}, + {REG_A5XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222}, + {REG_A5XX_RBBM_CLOCK_HYST_UCHE, 0x00444444}, + {REG_A5XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, + {REG_A5XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL_RB1, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL_RB2, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL_RB3, 0x22222222}, + {REG_A5XX_RBBM_CLOCK_CNTL2_RB0, 0x00222222}, + {REG_A5XX_RBBM_CLOCK_CNTL2_RB1, 0x00222222}, + {REG_A5XX_RBBM_CLOCK_CNTL2_RB2, 0x00222222}, + {REG_A5XX_RBBM_CLOCK_CNTL2_RB3, 0x00222222}, + {REG_A5XX_RBBM_CLOCK_CNTL_CCU0, 0x00022220}, + {REG_A5XX_RBBM_CLOCK_CNTL_CCU1, 0x00022220}, + {REG_A5XX_RBBM_CLOCK_CNTL_CCU2, 0x00022220}, + {REG_A5XX_RBBM_CLOCK_CNTL_CCU3, 0x00022220}, + {REG_A5XX_RBBM_CLOCK_CNTL_RAC, 0x05522222}, + {REG_A5XX_RBBM_CLOCK_CNTL2_RAC, 0x00505555}, + {REG_A5XX_RBBM_CLOCK_HYST_RB_CCU0, 0x04040404}, + {REG_A5XX_RBBM_CLOCK_HYST_RB_CCU1, 0x04040404}, + {REG_A5XX_RBBM_CLOCK_HYST_RB_CCU2, 0x04040404}, + {REG_A5XX_RBBM_CLOCK_HYST_RB_CCU3, 0x04040404}, + {REG_A5XX_RBBM_CLOCK_HYST_RAC, 0x07444044}, + {REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0, 0x00000002}, + {REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_1, 0x00000002}, + {REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_2, 0x00000002}, + {REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_3, 0x00000002}, + {REG_A5XX_RBBM_CLOCK_DELAY_RAC, 0x00010011}, + {REG_A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, + {REG_A5XX_RBBM_CLOCK_MODE_GPC, 0x02222222}, + {REG_A5XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, + {REG_A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, + {REG_A5XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, + {REG_A5XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, + {REG_A5XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, + {REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, + {REG_A5XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, + {REG_A5XX_RBBM_CLOCK_DELAY_VFD, 0x00002222} +}; + +static const struct { + int (*test)(struct adreno_gpu *gpu); + const struct a5xx_hwcg *regs; + unsigned int count; +} a5xx_hwcg_regs[] = { + { adreno_is_a530, a530_hwcg, ARRAY_SIZE(a530_hwcg), }, +}; + +static void _a5xx_enable_hwcg(struct msm_gpu *gpu, + const struct a5xx_hwcg *regs, unsigned int count) +{ + unsigned int i; + + for (i = 0; i < count; i++) + gpu_write(gpu, regs[i].offset, regs[i].value); + + gpu_write(gpu, REG_A5XX_RBBM_CLOCK_CNTL, 0xAAA8AA00); + gpu_write(gpu, REG_A5XX_RBBM_ISDB_CNT, 0x182); +} + +static void a5xx_enable_hwcg(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(a5xx_hwcg_regs); i++) { + if (a5xx_hwcg_regs[i].test(adreno_gpu)) { + _a5xx_enable_hwcg(gpu, a5xx_hwcg_regs[i].regs, + a5xx_hwcg_regs[i].count); + return; + } + } +} + +static int a5xx_me_init(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct msm_ringbuffer *ring = gpu->rb; + + OUT_PKT7(ring, CP_ME_INIT, 8); + + OUT_RING(ring, 0x0000002F); + + /* Enable multiple hardware contexts */ + OUT_RING(ring, 0x00000003); + + /* Enable error detection */ + OUT_RING(ring, 0x20000000); + + /* Don't enable header dump */ + OUT_RING(ring, 0x00000000); + OUT_RING(ring, 0x00000000); + + /* Specify workarounds for various microcode issues */ + if (adreno_is_a530(adreno_gpu)) { + /* Workaround for token end syncs + * Force a WFI after every direct-render 3D mode draw and every + * 2D mode 3 draw + */ + OUT_RING(ring, 0x0000000B); + } else { + /* No workarounds enabled */ + OUT_RING(ring, 0x00000000); + } + + OUT_RING(ring, 0x00000000); + OUT_RING(ring, 0x00000000); + + gpu->funcs->flush(gpu); + + return gpu->funcs->idle(gpu) ? 0 : -EINVAL; +} + +static struct drm_gem_object *a5xx_ucode_load_bo(struct msm_gpu *gpu, + const struct firmware *fw, u64 *iova) +{ + struct drm_device *drm = gpu->dev; + struct drm_gem_object *bo; + void *ptr; + + mutex_lock(&drm->struct_mutex); + bo = msm_gem_new(drm, fw->size - 4, MSM_BO_UNCACHED); + mutex_unlock(&drm->struct_mutex); + + if (IS_ERR(bo)) + return bo; + + ptr = msm_gem_get_vaddr(bo); + if (!ptr) { + drm_gem_object_unreference_unlocked(bo); + return ERR_PTR(-ENOMEM); + } + + if (iova) { + int ret = msm_gem_get_iova(bo, gpu->id, iova); + + if (ret) { + drm_gem_object_unreference_unlocked(bo); + return ERR_PTR(ret); + } + } + + memcpy(ptr, &fw->data[4], fw->size - 4); + + msm_gem_put_vaddr(bo); + return bo; +} + +static int a5xx_ucode_init(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu); + int ret; + + if (!a5xx_gpu->pm4_bo) { + a5xx_gpu->pm4_bo = a5xx_ucode_load_bo(gpu, adreno_gpu->pm4, + &a5xx_gpu->pm4_iova); + + if (IS_ERR(a5xx_gpu->pm4_bo)) { + ret = PTR_ERR(a5xx_gpu->pm4_bo); + a5xx_gpu->pm4_bo = NULL; + dev_err(gpu->dev->dev, "could not allocate PM4: %d\n", + ret); + return ret; + } + } + + if (!a5xx_gpu->pfp_bo) { + a5xx_gpu->pfp_bo = a5xx_ucode_load_bo(gpu, adreno_gpu->pfp, + &a5xx_gpu->pfp_iova); + + if (IS_ERR(a5xx_gpu->pfp_bo)) { + ret = PTR_ERR(a5xx_gpu->pfp_bo); + a5xx_gpu->pfp_bo = NULL; + dev_err(gpu->dev->dev, "could not allocate PFP: %d\n", + ret); + return ret; + } + } + + gpu_write64(gpu, REG_A5XX_CP_ME_INSTR_BASE_LO, + REG_A5XX_CP_ME_INSTR_BASE_HI, a5xx_gpu->pm4_iova); + + gpu_write64(gpu, REG_A5XX_CP_PFP_INSTR_BASE_LO, + REG_A5XX_CP_PFP_INSTR_BASE_HI, a5xx_gpu->pfp_iova); + + return 0; +} + +#define A5XX_INT_MASK (A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR | \ + A5XX_RBBM_INT_0_MASK_RBBM_TRANSFER_TIMEOUT | \ + A5XX_RBBM_INT_0_MASK_RBBM_ME_MS_TIMEOUT | \ + A5XX_RBBM_INT_0_MASK_RBBM_PFP_MS_TIMEOUT | \ + A5XX_RBBM_INT_0_MASK_RBBM_ETS_MS_TIMEOUT | \ + A5XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNC_OVERFLOW | \ + A5XX_RBBM_INT_0_MASK_CP_HW_ERROR | \ + A5XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS | \ + A5XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \ + A5XX_RBBM_INT_0_MASK_GPMU_VOLTAGE_DROOP) + +static int a5xx_hw_init(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + int ret; + + gpu_write(gpu, REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000003); + + /* Make all blocks contribute to the GPU BUSY perf counter */ + gpu_write(gpu, REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xFFFFFFFF); + + /* Enable RBBM error reporting bits */ + gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL0, 0x00000001); + + if (adreno_gpu->quirks & ADRENO_QUIRK_FAULT_DETECT_MASK) { + /* + * Mask out the activity signals from RB1-3 to avoid false + * positives + */ + + gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL11, + 0xF0000000); + gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL12, + 0xFFFFFFFF); + gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL13, + 0xFFFFFFFF); + gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL14, + 0xFFFFFFFF); + gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL15, + 0xFFFFFFFF); + gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL16, + 0xFFFFFFFF); + gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL17, + 0xFFFFFFFF); + gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL18, + 0xFFFFFFFF); + } + + /* Enable fault detection */ + gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_INT_CNTL, + (1 << 30) | 0xFFFF); + + /* Turn on performance counters */ + gpu_write(gpu, REG_A5XX_RBBM_PERFCTR_CNTL, 0x01); + + /* Increase VFD cache access so LRZ and other data gets evicted less */ + gpu_write(gpu, REG_A5XX_UCHE_CACHE_WAYS, 0x02); + + /* Disable L2 bypass in the UCHE */ + gpu_write(gpu, REG_A5XX_UCHE_TRAP_BASE_LO, 0xFFFF0000); + gpu_write(gpu, REG_A5XX_UCHE_TRAP_BASE_HI, 0x0001FFFF); + gpu_write(gpu, REG_A5XX_UCHE_WRITE_THRU_BASE_LO, 0xFFFF0000); + gpu_write(gpu, REG_A5XX_UCHE_WRITE_THRU_BASE_HI, 0x0001FFFF); + + /* Set the GMEM VA range (0 to gpu->gmem) */ + gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MIN_LO, 0x00100000); + gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MIN_HI, 0x00000000); + gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_LO, + 0x00100000 + adreno_gpu->gmem - 1); + gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_HI, 0x00000000); + + gpu_write(gpu, REG_A5XX_CP_MEQ_THRESHOLDS, 0x40); + gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x40); + gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_2, 0x80000060); + gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_1, 0x40201B16); + + gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, (0x400 << 11 | 0x300 << 22)); + + if (adreno_gpu->quirks & ADRENO_QUIRK_TWO_PASS_USE_WFI) + gpu_rmw(gpu, REG_A5XX_PC_DBG_ECO_CNTL, 0, (1 << 8)); + + gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, 0xc0200100); + + /* Enable USE_RETENTION_FLOPS */ + gpu_write(gpu, REG_A5XX_CP_CHICKEN_DBG, 0x02000000); + + /* Enable ME/PFP split notification */ + gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL1, 0xA6FFFFFF); + + /* Enable HWCG */ + a5xx_enable_hwcg(gpu); + + gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL2, 0x0000003F); + + /* Set the highest bank bit */ + gpu_write(gpu, REG_A5XX_TPL1_MODE_CNTL, 2 << 7); + gpu_write(gpu, REG_A5XX_RB_MODE_CNTL, 2 << 1); + + /* Protect registers from the CP */ + gpu_write(gpu, REG_A5XX_CP_PROTECT_CNTL, 0x00000007); + + /* RBBM */ + gpu_write(gpu, REG_A5XX_CP_PROTECT(0), ADRENO_PROTECT_RW(0x04, 4)); + gpu_write(gpu, REG_A5XX_CP_PROTECT(1), ADRENO_PROTECT_RW(0x08, 8)); + gpu_write(gpu, REG_A5XX_CP_PROTECT(2), ADRENO_PROTECT_RW(0x10, 16)); + gpu_write(gpu, REG_A5XX_CP_PROTECT(3), ADRENO_PROTECT_RW(0x20, 32)); + gpu_write(gpu, REG_A5XX_CP_PROTECT(4), ADRENO_PROTECT_RW(0x40, 64)); + gpu_write(gpu, REG_A5XX_CP_PROTECT(5), ADRENO_PROTECT_RW(0x80, 64)); + + /* Content protect */ + gpu_write(gpu, REG_A5XX_CP_PROTECT(6), + ADRENO_PROTECT_RW(REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO, + 16)); + gpu_write(gpu, REG_A5XX_CP_PROTECT(7), + ADRENO_PROTECT_RW(REG_A5XX_RBBM_SECVID_TRUST_CNTL, 2)); + + /* CP */ + gpu_write(gpu, REG_A5XX_CP_PROTECT(8), ADRENO_PROTECT_RW(0x800, 64)); + gpu_write(gpu, REG_A5XX_CP_PROTECT(9), ADRENO_PROTECT_RW(0x840, 8)); + gpu_write(gpu, REG_A5XX_CP_PROTECT(10), ADRENO_PROTECT_RW(0x880, 32)); + gpu_write(gpu, REG_A5XX_CP_PROTECT(11), ADRENO_PROTECT_RW(0xAA0, 1)); + + /* RB */ + gpu_write(gpu, REG_A5XX_CP_PROTECT(12), ADRENO_PROTECT_RW(0xCC0, 1)); + gpu_write(gpu, REG_A5XX_CP_PROTECT(13), ADRENO_PROTECT_RW(0xCF0, 2)); + + /* VPC */ + gpu_write(gpu, REG_A5XX_CP_PROTECT(14), ADRENO_PROTECT_RW(0xE68, 8)); + gpu_write(gpu, REG_A5XX_CP_PROTECT(15), ADRENO_PROTECT_RW(0xE70, 4)); + + /* UCHE */ + gpu_write(gpu, REG_A5XX_CP_PROTECT(16), ADRENO_PROTECT_RW(0xE80, 16)); + + if (adreno_is_a530(adreno_gpu)) + gpu_write(gpu, REG_A5XX_CP_PROTECT(17), + ADRENO_PROTECT_RW(0x10000, 0x8000)); + + gpu_write(gpu, REG_A5XX_RBBM_SECVID_TSB_CNTL, 0); + /* + * Disable the trusted memory range - we don't actually supported secure + * memory rendering at this point in time and we don't want to block off + * part of the virtual memory space. + */ + gpu_write64(gpu, REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO, + REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI, 0x00000000); + gpu_write(gpu, REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000); + + /* Load the GPMU firmware before starting the HW init */ + a5xx_gpmu_ucode_init(gpu); + + ret = adreno_hw_init(gpu); + if (ret) + return ret; + + ret = a5xx_ucode_init(gpu); + if (ret) + return ret; + + /* Disable the interrupts through the initial bringup stage */ + gpu_write(gpu, REG_A5XX_RBBM_INT_0_MASK, A5XX_INT_MASK); + + /* Clear ME_HALT to start the micro engine */ + gpu_write(gpu, REG_A5XX_CP_PFP_ME_CNTL, 0); + ret = a5xx_me_init(gpu); + if (ret) + return ret; + + ret = a5xx_power_init(gpu); + if (ret) + return ret; + + /* + * Send a pipeline event stat to get misbehaving counters to start + * ticking correctly + */ + if (adreno_is_a530(adreno_gpu)) { + OUT_PKT7(gpu->rb, CP_EVENT_WRITE, 1); + OUT_RING(gpu->rb, 0x0F); + + gpu->funcs->flush(gpu); + if (!gpu->funcs->idle(gpu)) + return -EINVAL; + } + + /* Put the GPU into unsecure mode */ + gpu_write(gpu, REG_A5XX_RBBM_SECVID_TRUST_CNTL, 0x0); + + return 0; +} + +static void a5xx_recover(struct msm_gpu *gpu) +{ + int i; + + adreno_dump_info(gpu); + + for (i = 0; i < 8; i++) { + printk("CP_SCRATCH_REG%d: %u\n", i, + gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(i))); + } + + if (hang_debug) + a5xx_dump(gpu); + + gpu_write(gpu, REG_A5XX_RBBM_SW_RESET_CMD, 1); + gpu_read(gpu, REG_A5XX_RBBM_SW_RESET_CMD); + gpu_write(gpu, REG_A5XX_RBBM_SW_RESET_CMD, 0); + adreno_recover(gpu); +} + +static void a5xx_destroy(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu); + + DBG("%s", gpu->name); + + if (a5xx_gpu->pm4_bo) { + if (a5xx_gpu->pm4_iova) + msm_gem_put_iova(a5xx_gpu->pm4_bo, gpu->id); + drm_gem_object_unreference_unlocked(a5xx_gpu->pm4_bo); + } + + if (a5xx_gpu->pfp_bo) { + if (a5xx_gpu->pfp_iova) + msm_gem_put_iova(a5xx_gpu->pfp_bo, gpu->id); + drm_gem_object_unreference_unlocked(a5xx_gpu->pfp_bo); + } + + if (a5xx_gpu->gpmu_bo) { + if (a5xx_gpu->gpmu_bo) + msm_gem_put_iova(a5xx_gpu->gpmu_bo, gpu->id); + drm_gem_object_unreference_unlocked(a5xx_gpu->gpmu_bo); + } + + adreno_gpu_cleanup(adreno_gpu); + kfree(a5xx_gpu); +} + +static inline bool _a5xx_check_idle(struct msm_gpu *gpu) +{ + if (gpu_read(gpu, REG_A5XX_RBBM_STATUS) & ~A5XX_RBBM_STATUS_HI_BUSY) + return false; + + /* + * Nearly every abnormality ends up pausing the GPU and triggering a + * fault so we can safely just watch for this one interrupt to fire + */ + return !(gpu_read(gpu, REG_A5XX_RBBM_INT_0_STATUS) & + A5XX_RBBM_INT_0_MASK_MISC_HANG_DETECT); +} + +static bool a5xx_idle(struct msm_gpu *gpu) +{ + /* wait for CP to drain ringbuffer: */ + if (!adreno_idle(gpu)) + return false; + + if (spin_until(_a5xx_check_idle(gpu))) { + DRM_ERROR("%s: %ps: timeout waiting for GPU to idle: status %8.8X irq %8.8X\n", + gpu->name, __builtin_return_address(0), + gpu_read(gpu, REG_A5XX_RBBM_STATUS), + gpu_read(gpu, REG_A5XX_RBBM_INT_0_STATUS)); + + return false; + } + + return true; +} + +static void a5xx_cp_err_irq(struct msm_gpu *gpu) +{ + u32 status = gpu_read(gpu, REG_A5XX_CP_INTERRUPT_STATUS); + + if (status & A5XX_CP_INT_CP_OPCODE_ERROR) { + u32 val; + + gpu_write(gpu, REG_A5XX_CP_PFP_STAT_ADDR, 0); + + /* + * REG_A5XX_CP_PFP_STAT_DATA is indexed, and we want index 1 so + * read it twice + */ + + gpu_read(gpu, REG_A5XX_CP_PFP_STAT_DATA); + val = gpu_read(gpu, REG_A5XX_CP_PFP_STAT_DATA); + + dev_err_ratelimited(gpu->dev->dev, "CP | opcode error | possible opcode=0x%8.8X\n", + val); + } + + if (status & A5XX_CP_INT_CP_HW_FAULT_ERROR) + dev_err_ratelimited(gpu->dev->dev, "CP | HW fault | status=0x%8.8X\n", + gpu_read(gpu, REG_A5XX_CP_HW_FAULT)); + + if (status & A5XX_CP_INT_CP_DMA_ERROR) + dev_err_ratelimited(gpu->dev->dev, "CP | DMA error\n"); + + if (status & A5XX_CP_INT_CP_REGISTER_PROTECTION_ERROR) { + u32 val = gpu_read(gpu, REG_A5XX_CP_PROTECT_STATUS); + + dev_err_ratelimited(gpu->dev->dev, + "CP | protected mode error | %s | addr=0x%8.8X | status=0x%8.8X\n", + val & (1 << 24) ? "WRITE" : "READ", + (val & 0xFFFFF) >> 2, val); + } + + if (status & A5XX_CP_INT_CP_AHB_ERROR) { + u32 status = gpu_read(gpu, REG_A5XX_CP_AHB_FAULT); + const char *access[16] = { "reserved", "reserved", + "timestamp lo", "timestamp hi", "pfp read", "pfp write", + "", "", "me read", "me write", "", "", "crashdump read", + "crashdump write" }; + + dev_err_ratelimited(gpu->dev->dev, + "CP | AHB error | addr=%X access=%s error=%d | status=0x%8.8X\n", + status & 0xFFFFF, access[(status >> 24) & 0xF], + (status & (1 << 31)), status); + } +} + +static void a5xx_rbbm_err_irq(struct msm_gpu *gpu) +{ + u32 status = gpu_read(gpu, REG_A5XX_RBBM_INT_0_STATUS); + + if (status & A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR) { + u32 val = gpu_read(gpu, REG_A5XX_RBBM_AHB_ERROR_STATUS); + + dev_err_ratelimited(gpu->dev->dev, + "RBBM | AHB bus error | %s | addr=0x%X | ports=0x%X:0x%X\n", + val & (1 << 28) ? "WRITE" : "READ", + (val & 0xFFFFF) >> 2, (val >> 20) & 0x3, + (val >> 24) & 0xF); + + /* Clear the error */ + gpu_write(gpu, REG_A5XX_RBBM_AHB_CMD, (1 << 4)); + } + + if (status & A5XX_RBBM_INT_0_MASK_RBBM_TRANSFER_TIMEOUT) + dev_err_ratelimited(gpu->dev->dev, "RBBM | AHB transfer timeout\n"); + + if (status & A5XX_RBBM_INT_0_MASK_RBBM_ME_MS_TIMEOUT) + dev_err_ratelimited(gpu->dev->dev, "RBBM | ME master split | status=0x%X\n", + gpu_read(gpu, REG_A5XX_RBBM_AHB_ME_SPLIT_STATUS)); + + if (status & A5XX_RBBM_INT_0_MASK_RBBM_PFP_MS_TIMEOUT) + dev_err_ratelimited(gpu->dev->dev, "RBBM | PFP master split | status=0x%X\n", + gpu_read(gpu, REG_A5XX_RBBM_AHB_PFP_SPLIT_STATUS)); + + if (status & A5XX_RBBM_INT_0_MASK_RBBM_ETS_MS_TIMEOUT) + dev_err_ratelimited(gpu->dev->dev, "RBBM | ETS master split | status=0x%X\n", + gpu_read(gpu, REG_A5XX_RBBM_AHB_ETS_SPLIT_STATUS)); + + if (status & A5XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNC_OVERFLOW) + dev_err_ratelimited(gpu->dev->dev, "RBBM | ATB ASYNC overflow\n"); + + if (status & A5XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW) + dev_err_ratelimited(gpu->dev->dev, "RBBM | ATB bus overflow\n"); +} + +static void a5xx_uche_err_irq(struct msm_gpu *gpu) +{ + uint64_t addr = (uint64_t) gpu_read(gpu, REG_A5XX_UCHE_TRAP_LOG_HI); + + addr |= gpu_read(gpu, REG_A5XX_UCHE_TRAP_LOG_LO); + + dev_err_ratelimited(gpu->dev->dev, "UCHE | Out of bounds access | addr=0x%llX\n", + addr); +} + +static void a5xx_gpmu_err_irq(struct msm_gpu *gpu) +{ + dev_err_ratelimited(gpu->dev->dev, "GPMU | voltage droop\n"); +} + +#define RBBM_ERROR_MASK \ + (A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR | \ + A5XX_RBBM_INT_0_MASK_RBBM_TRANSFER_TIMEOUT | \ + A5XX_RBBM_INT_0_MASK_RBBM_ME_MS_TIMEOUT | \ + A5XX_RBBM_INT_0_MASK_RBBM_PFP_MS_TIMEOUT | \ + A5XX_RBBM_INT_0_MASK_RBBM_ETS_MS_TIMEOUT | \ + A5XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNC_OVERFLOW) + +static irqreturn_t a5xx_irq(struct msm_gpu *gpu) +{ + u32 status = gpu_read(gpu, REG_A5XX_RBBM_INT_0_STATUS); + + gpu_write(gpu, REG_A5XX_RBBM_INT_CLEAR_CMD, status); + + if (status & RBBM_ERROR_MASK) + a5xx_rbbm_err_irq(gpu); + + if (status & A5XX_RBBM_INT_0_MASK_CP_HW_ERROR) + a5xx_cp_err_irq(gpu); + + if (status & A5XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS) + a5xx_uche_err_irq(gpu); + + if (status & A5XX_RBBM_INT_0_MASK_GPMU_VOLTAGE_DROOP) + a5xx_gpmu_err_irq(gpu); + + if (status & A5XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS) + msm_gpu_retire(gpu); + + return IRQ_HANDLED; +} + +static const u32 a5xx_register_offsets[REG_ADRENO_REGISTER_MAX] = { + REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_BASE, REG_A5XX_CP_RB_BASE), + REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_BASE_HI, REG_A5XX_CP_RB_BASE_HI), + REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR_ADDR, REG_A5XX_CP_RB_RPTR_ADDR), + REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR_ADDR_HI, + REG_A5XX_CP_RB_RPTR_ADDR_HI), + REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR, REG_A5XX_CP_RB_RPTR), + REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_WPTR, REG_A5XX_CP_RB_WPTR), + REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_CNTL, REG_A5XX_CP_RB_CNTL), +}; + +static const u32 a5xx_registers[] = { + 0x0000, 0x0002, 0x0004, 0x0020, 0x0022, 0x0026, 0x0029, 0x002B, + 0x002E, 0x0035, 0x0038, 0x0042, 0x0044, 0x0044, 0x0047, 0x0095, + 0x0097, 0x00BB, 0x03A0, 0x0464, 0x0469, 0x046F, 0x04D2, 0x04D3, + 0x04E0, 0x0533, 0x0540, 0x0555, 0xF400, 0xF400, 0xF800, 0xF807, + 0x0800, 0x081A, 0x081F, 0x0841, 0x0860, 0x0860, 0x0880, 0x08A0, + 0x0B00, 0x0B12, 0x0B15, 0x0B28, 0x0B78, 0x0B7F, 0x0BB0, 0x0BBD, + 0x0BC0, 0x0BC6, 0x0BD0, 0x0C53, 0x0C60, 0x0C61, 0x0C80, 0x0C82, + 0x0C84, 0x0C85, 0x0C90, 0x0C98, 0x0CA0, 0x0CA0, 0x0CB0, 0x0CB2, + 0x2180, 0x2185, 0x2580, 0x2585, 0x0CC1, 0x0CC1, 0x0CC4, 0x0CC7, + 0x0CCC, 0x0CCC, 0x0CD0, 0x0CD8, 0x0CE0, 0x0CE5, 0x0CE8, 0x0CE8, + 0x0CEC, 0x0CF1, 0x0CFB, 0x0D0E, 0x2100, 0x211E, 0x2140, 0x2145, + 0x2500, 0x251E, 0x2540, 0x2545, 0x0D10, 0x0D17, 0x0D20, 0x0D23, + 0x0D30, 0x0D30, 0x20C0, 0x20C0, 0x24C0, 0x24C0, 0x0E40, 0x0E43, + 0x0E4A, 0x0E4A, 0x0E50, 0x0E57, 0x0E60, 0x0E7C, 0x0E80, 0x0E8E, + 0x0E90, 0x0E96, 0x0EA0, 0x0EA8, 0x0EB0, 0x0EB2, 0xE140, 0xE147, + 0xE150, 0xE187, 0xE1A0, 0xE1A9, 0xE1B0, 0xE1B6, 0xE1C0, 0xE1C7, + 0xE1D0, 0xE1D1, 0xE200, 0xE201, 0xE210, 0xE21C, 0xE240, 0xE268, + 0xE000, 0xE006, 0xE010, 0xE09A, 0xE0A0, 0xE0A4, 0xE0AA, 0xE0EB, + 0xE100, 0xE105, 0xE380, 0xE38F, 0xE3B0, 0xE3B0, 0xE400, 0xE405, + 0xE408, 0xE4E9, 0xE4F0, 0xE4F0, 0xE280, 0xE280, 0xE282, 0xE2A3, + 0xE2A5, 0xE2C2, 0xE940, 0xE947, 0xE950, 0xE987, 0xE9A0, 0xE9A9, + 0xE9B0, 0xE9B6, 0xE9C0, 0xE9C7, 0xE9D0, 0xE9D1, 0xEA00, 0xEA01, + 0xEA10, 0xEA1C, 0xEA40, 0xEA68, 0xE800, 0xE806, 0xE810, 0xE89A, + 0xE8A0, 0xE8A4, 0xE8AA, 0xE8EB, 0xE900, 0xE905, 0xEB80, 0xEB8F, + 0xEBB0, 0xEBB0, 0xEC00, 0xEC05, 0xEC08, 0xECE9, 0xECF0, 0xECF0, + 0xEA80, 0xEA80, 0xEA82, 0xEAA3, 0xEAA5, 0xEAC2, 0xA800, 0xA8FF, + 0xAC60, 0xAC60, 0xB000, 0xB97F, 0xB9A0, 0xB9BF, + ~0 +}; + +static void a5xx_dump(struct msm_gpu *gpu) +{ + dev_info(gpu->dev->dev, "status: %08x\n", + gpu_read(gpu, REG_A5XX_RBBM_STATUS)); + adreno_dump(gpu); +} + +static int a5xx_pm_resume(struct msm_gpu *gpu) +{ + int ret; + + /* Turn on the core power */ + ret = msm_gpu_pm_resume(gpu); + if (ret) + return ret; + + /* Turn the RBCCU domain first to limit the chances of voltage droop */ + gpu_write(gpu, REG_A5XX_GPMU_RBCCU_POWER_CNTL, 0x778000); + + /* Wait 3 usecs before polling */ + udelay(3); + + ret = spin_usecs(gpu, 20, REG_A5XX_GPMU_RBCCU_PWR_CLK_STATUS, + (1 << 20), (1 << 20)); + if (ret) { + DRM_ERROR("%s: timeout waiting for RBCCU GDSC enable: %X\n", + gpu->name, + gpu_read(gpu, REG_A5XX_GPMU_RBCCU_PWR_CLK_STATUS)); + return ret; + } + + /* Turn on the SP domain */ + gpu_write(gpu, REG_A5XX_GPMU_SP_POWER_CNTL, 0x778000); + ret = spin_usecs(gpu, 20, REG_A5XX_GPMU_SP_PWR_CLK_STATUS, + (1 << 20), (1 << 20)); + if (ret) + DRM_ERROR("%s: timeout waiting for SP GDSC enable\n", + gpu->name); + + return ret; +} + +static int a5xx_pm_suspend(struct msm_gpu *gpu) +{ + /* Clear the VBIF pipe before shutting down */ + gpu_write(gpu, REG_A5XX_VBIF_XIN_HALT_CTRL0, 0xF); + spin_until((gpu_read(gpu, REG_A5XX_VBIF_XIN_HALT_CTRL1) & 0xF) == 0xF); + + gpu_write(gpu, REG_A5XX_VBIF_XIN_HALT_CTRL0, 0); + + /* + * Reset the VBIF before power collapse to avoid issue with FIFO + * entries + */ + gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, 0x003C0000); + gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, 0x00000000); + + return msm_gpu_pm_suspend(gpu); +} + +static int a5xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) +{ + *value = gpu_read64(gpu, REG_A5XX_RBBM_PERFCTR_CP_0_LO, + REG_A5XX_RBBM_PERFCTR_CP_0_HI); + + return 0; +} + +#ifdef CONFIG_DEBUG_FS +static void a5xx_show(struct msm_gpu *gpu, struct seq_file *m) +{ + gpu->funcs->pm_resume(gpu); + + seq_printf(m, "status: %08x\n", + gpu_read(gpu, REG_A5XX_RBBM_STATUS)); + gpu->funcs->pm_suspend(gpu); + + adreno_show(gpu, m); +} +#endif + +static const struct adreno_gpu_funcs funcs = { + .base = { + .get_param = adreno_get_param, + .hw_init = a5xx_hw_init, + .pm_suspend = a5xx_pm_suspend, + .pm_resume = a5xx_pm_resume, + .recover = a5xx_recover, + .last_fence = adreno_last_fence, + .submit = a5xx_submit, + .flush = adreno_flush, + .idle = a5xx_idle, + .irq = a5xx_irq, + .destroy = a5xx_destroy, + .show = a5xx_show, + }, + .get_timestamp = a5xx_get_timestamp, +}; + +struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) +{ + struct msm_drm_private *priv = dev->dev_private; + struct platform_device *pdev = priv->gpu_pdev; + struct a5xx_gpu *a5xx_gpu = NULL; + struct adreno_gpu *adreno_gpu; + struct msm_gpu *gpu; + int ret; + + if (!pdev) { + dev_err(dev->dev, "No A5XX device is defined\n"); + return ERR_PTR(-ENXIO); + } + + a5xx_gpu = kzalloc(sizeof(*a5xx_gpu), GFP_KERNEL); + if (!a5xx_gpu) + return ERR_PTR(-ENOMEM); + + adreno_gpu = &a5xx_gpu->base; + gpu = &adreno_gpu->base; + + a5xx_gpu->pdev = pdev; + adreno_gpu->registers = a5xx_registers; + adreno_gpu->reg_offsets = a5xx_register_offsets; + + a5xx_gpu->lm_leakage = 0x4E001A; + + ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs); + if (ret) { + a5xx_destroy(&(a5xx_gpu->base.base)); + return ERR_PTR(ret); + } + + return gpu; +} diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.h b/drivers/gpu/drm/msm/adreno/a5xx_gpu.h new file mode 100644 index 000000000000..1590f845d554 --- /dev/null +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.h @@ -0,0 +1,60 @@ +/* Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#ifndef __A5XX_GPU_H__ +#define __A5XX_GPU_H__ + +#include "adreno_gpu.h" + +/* Bringing over the hack from the previous targets */ +#undef ROP_COPY +#undef ROP_XOR + +#include "a5xx.xml.h" + +struct a5xx_gpu { + struct adreno_gpu base; + struct platform_device *pdev; + + struct drm_gem_object *pm4_bo; + uint64_t pm4_iova; + + struct drm_gem_object *pfp_bo; + uint64_t pfp_iova; + + struct drm_gem_object *gpmu_bo; + uint64_t gpmu_iova; + uint32_t gpmu_dwords; + + uint32_t lm_leakage; +}; + +#define to_a5xx_gpu(x) container_of(x, struct a5xx_gpu, base) + +int a5xx_power_init(struct msm_gpu *gpu); +void a5xx_gpmu_ucode_init(struct msm_gpu *gpu); + +static inline int spin_usecs(struct msm_gpu *gpu, uint32_t usecs, + uint32_t reg, uint32_t mask, uint32_t value) +{ + while (usecs--) { + udelay(1); + if ((gpu_read(gpu, reg) & mask) == value) + return 0; + cpu_relax(); + } + + return -ETIMEDOUT; +} + + +#endif /* __A5XX_GPU_H__ */ diff --git a/drivers/gpu/drm/msm/adreno/a5xx_power.c b/drivers/gpu/drm/msm/adreno/a5xx_power.c new file mode 100644 index 000000000000..72d52c71f769 --- /dev/null +++ b/drivers/gpu/drm/msm/adreno/a5xx_power.c @@ -0,0 +1,344 @@ +/* Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/pm_opp.h> +#include "a5xx_gpu.h" + +/* + * The GPMU data block is a block of shared registers that can be used to + * communicate back and forth. These "registers" are by convention with the GPMU + * firwmare and not bound to any specific hardware design + */ + +#define AGC_INIT_BASE REG_A5XX_GPMU_DATA_RAM_BASE +#define AGC_INIT_MSG_MAGIC (AGC_INIT_BASE + 5) +#define AGC_MSG_BASE (AGC_INIT_BASE + 7) + +#define AGC_MSG_STATE (AGC_MSG_BASE + 0) +#define AGC_MSG_COMMAND (AGC_MSG_BASE + 1) +#define AGC_MSG_PAYLOAD_SIZE (AGC_MSG_BASE + 3) +#define AGC_MSG_PAYLOAD(_o) ((AGC_MSG_BASE + 5) + (_o)) + +#define AGC_POWER_CONFIG_PRODUCTION_ID 1 +#define AGC_INIT_MSG_VALUE 0xBABEFACE + +static struct { + uint32_t reg; + uint32_t value; +} a5xx_sequence_regs[] = { + { 0xB9A1, 0x00010303 }, + { 0xB9A2, 0x13000000 }, + { 0xB9A3, 0x00460020 }, + { 0xB9A4, 0x10000000 }, + { 0xB9A5, 0x040A1707 }, + { 0xB9A6, 0x00010000 }, + { 0xB9A7, 0x0E000904 }, + { 0xB9A8, 0x10000000 }, + { 0xB9A9, 0x01165000 }, + { 0xB9AA, 0x000E0002 }, + { 0xB9AB, 0x03884141 }, + { 0xB9AC, 0x10000840 }, + { 0xB9AD, 0x572A5000 }, + { 0xB9AE, 0x00000003 }, + { 0xB9AF, 0x00000000 }, + { 0xB9B0, 0x10000000 }, + { 0xB828, 0x6C204010 }, + { 0xB829, 0x6C204011 }, + { 0xB82A, 0x6C204012 }, + { 0xB82B, 0x6C204013 }, + { 0xB82C, 0x6C204014 }, + { 0xB90F, 0x00000004 }, + { 0xB910, 0x00000002 }, + { 0xB911, 0x00000002 }, + { 0xB912, 0x00000002 }, + { 0xB913, 0x00000002 }, + { 0xB92F, 0x00000004 }, + { 0xB930, 0x00000005 }, + { 0xB931, 0x00000005 }, + { 0xB932, 0x00000005 }, + { 0xB933, 0x00000005 }, + { 0xB96F, 0x00000001 }, + { 0xB970, 0x00000003 }, + { 0xB94F, 0x00000004 }, + { 0xB950, 0x0000000B }, + { 0xB951, 0x0000000B }, + { 0xB952, 0x0000000B }, + { 0xB953, 0x0000000B }, + { 0xB907, 0x00000019 }, + { 0xB927, 0x00000019 }, + { 0xB947, 0x00000019 }, + { 0xB967, 0x00000019 }, + { 0xB987, 0x00000019 }, + { 0xB906, 0x00220001 }, + { 0xB926, 0x00220001 }, + { 0xB946, 0x00220001 }, + { 0xB966, 0x00220001 }, + { 0xB986, 0x00300000 }, + { 0xAC40, 0x0340FF41 }, + { 0xAC41, 0x03BEFED0 }, + { 0xAC42, 0x00331FED }, + { 0xAC43, 0x021FFDD3 }, + { 0xAC44, 0x5555AAAA }, + { 0xAC45, 0x5555AAAA }, + { 0xB9BA, 0x00000008 }, +}; + +/* + * Get the actual voltage value for the operating point at the specified + * frequency + */ +static inline uint32_t _get_mvolts(struct msm_gpu *gpu, uint32_t freq) +{ + struct drm_device *dev = gpu->dev; + struct msm_drm_private *priv = dev->dev_private; + struct platform_device *pdev = priv->gpu_pdev; + struct dev_pm_opp *opp; + + opp = dev_pm_opp_find_freq_exact(&pdev->dev, freq, true); + + return (!IS_ERR(opp)) ? dev_pm_opp_get_voltage(opp) / 1000 : 0; +} + +/* Setup thermal limit management */ +static void a5xx_lm_setup(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu); + unsigned int i; + + /* Write the block of sequence registers */ + for (i = 0; i < ARRAY_SIZE(a5xx_sequence_regs); i++) + gpu_write(gpu, a5xx_sequence_regs[i].reg, + a5xx_sequence_regs[i].value); + + /* Hard code the A530 GPU thermal sensor ID for the GPMU */ + gpu_write(gpu, REG_A5XX_GPMU_TEMP_SENSOR_ID, 0x60007); + gpu_write(gpu, REG_A5XX_GPMU_DELTA_TEMP_THRESHOLD, 0x01); + gpu_write(gpu, REG_A5XX_GPMU_TEMP_SENSOR_CONFIG, 0x01); + + /* Until we get clock scaling 0 is always the active power level */ + gpu_write(gpu, REG_A5XX_GPMU_GPMU_VOLTAGE, 0x80000000 | 0); + + gpu_write(gpu, REG_A5XX_GPMU_BASE_LEAKAGE, a5xx_gpu->lm_leakage); + + /* The threshold is fixed at 6000 for A530 */ + gpu_write(gpu, REG_A5XX_GPMU_GPMU_PWR_THRESHOLD, 0x80000000 | 6000); + + gpu_write(gpu, REG_A5XX_GPMU_BEC_ENABLE, 0x10001FFF); + gpu_write(gpu, REG_A5XX_GDPM_CONFIG1, 0x00201FF1); + + /* Write the voltage table */ + gpu_write(gpu, REG_A5XX_GPMU_BEC_ENABLE, 0x10001FFF); + gpu_write(gpu, REG_A5XX_GDPM_CONFIG1, 0x201FF1); + + gpu_write(gpu, AGC_MSG_STATE, 1); + gpu_write(gpu, AGC_MSG_COMMAND, AGC_POWER_CONFIG_PRODUCTION_ID); + + /* Write the max power - hard coded to 5448 for A530 */ + gpu_write(gpu, AGC_MSG_PAYLOAD(0), 5448); + gpu_write(gpu, AGC_MSG_PAYLOAD(1), 1); + + /* + * For now just write the one voltage level - we will do more when we + * can do scaling + */ + gpu_write(gpu, AGC_MSG_PAYLOAD(2), _get_mvolts(gpu, gpu->fast_rate)); + gpu_write(gpu, AGC_MSG_PAYLOAD(3), gpu->fast_rate / 1000000); + + gpu_write(gpu, AGC_MSG_PAYLOAD_SIZE, 4 * sizeof(uint32_t)); + gpu_write(gpu, AGC_INIT_MSG_MAGIC, AGC_INIT_MSG_VALUE); +} + +/* Enable SP/TP cpower collapse */ +static void a5xx_pc_init(struct msm_gpu *gpu) +{ + gpu_write(gpu, REG_A5XX_GPMU_PWR_COL_INTER_FRAME_CTRL, 0x7F); + gpu_write(gpu, REG_A5XX_GPMU_PWR_COL_BINNING_CTRL, 0); + gpu_write(gpu, REG_A5XX_GPMU_PWR_COL_INTER_FRAME_HYST, 0xA0080); + gpu_write(gpu, REG_A5XX_GPMU_PWR_COL_STAGGER_DELAY, 0x600040); +} + +/* Enable the GPMU microcontroller */ +static int a5xx_gpmu_init(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu); + struct msm_ringbuffer *ring = gpu->rb; + + if (!a5xx_gpu->gpmu_dwords) + return 0; + + /* Turn off protected mode for this operation */ + OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1); + OUT_RING(ring, 0); + + /* Kick off the IB to load the GPMU microcode */ + OUT_PKT7(ring, CP_INDIRECT_BUFFER_PFE, 3); + OUT_RING(ring, lower_32_bits(a5xx_gpu->gpmu_iova)); + OUT_RING(ring, upper_32_bits(a5xx_gpu->gpmu_iova)); + OUT_RING(ring, a5xx_gpu->gpmu_dwords); + + /* Turn back on protected mode */ + OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1); + OUT_RING(ring, 1); + + gpu->funcs->flush(gpu); + + if (!gpu->funcs->idle(gpu)) { + DRM_ERROR("%s: Unable to load GPMU firmware. GPMU will not be active\n", + gpu->name); + return -EINVAL; + } + + gpu_write(gpu, REG_A5XX_GPMU_WFI_CONFIG, 0x4014); + + /* Kick off the GPMU */ + gpu_write(gpu, REG_A5XX_GPMU_CM3_SYSRESET, 0x0); + + /* + * Wait for the GPMU to respond. It isn't fatal if it doesn't, we just + * won't have advanced power collapse. + */ + if (spin_usecs(gpu, 25, REG_A5XX_GPMU_GENERAL_0, 0xFFFFFFFF, + 0xBABEFACE)) + DRM_ERROR("%s: GPMU firmware initialization timed out\n", + gpu->name); + + return 0; +} + +/* Enable limits management */ +static void a5xx_lm_enable(struct msm_gpu *gpu) +{ + gpu_write(gpu, REG_A5XX_GDPM_INT_MASK, 0x0); + gpu_write(gpu, REG_A5XX_GDPM_INT_EN, 0x0A); + gpu_write(gpu, REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_EN_MASK, 0x01); + gpu_write(gpu, REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_EN_MASK, 0x50000); + gpu_write(gpu, REG_A5XX_GPMU_THROTTLE_UNMASK_FORCE_CTRL, 0x30000); + + gpu_write(gpu, REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL, 0x011); +} + +int a5xx_power_init(struct msm_gpu *gpu) +{ + int ret; + + /* Set up the limits management */ + a5xx_lm_setup(gpu); + + /* Set up SP/TP power collpase */ + a5xx_pc_init(gpu); + + /* Start the GPMU */ + ret = a5xx_gpmu_init(gpu); + if (ret) + return ret; + + /* Start the limits management */ + a5xx_lm_enable(gpu); + + return 0; +} + +void a5xx_gpmu_ucode_init(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu); + struct drm_device *drm = gpu->dev; + const struct firmware *fw; + uint32_t dwords = 0, offset = 0, bosize; + unsigned int *data, *ptr, *cmds; + unsigned int cmds_size; + + if (a5xx_gpu->gpmu_bo) + return; + + /* Get the firmware */ + if (request_firmware(&fw, adreno_gpu->info->gpmufw, drm->dev)) { + DRM_ERROR("%s: Could not get GPMU firmware. GPMU will not be active\n", + gpu->name); + return; + } + + data = (unsigned int *) fw->data; + + /* + * The first dword is the size of the remaining data in dwords. Use it + * as a checksum of sorts and make sure it matches the actual size of + * the firmware that we read + */ + + if (fw->size < 8 || (data[0] < 2) || (data[0] >= (fw->size >> 2))) + goto out; + + /* The second dword is an ID - look for 2 (GPMU_FIRMWARE_ID) */ + if (data[1] != 2) + goto out; + + cmds = data + data[2] + 3; + cmds_size = data[0] - data[2] - 2; + + /* + * A single type4 opcode can only have so many values attached so + * add enough opcodes to load the all the commands + */ + bosize = (cmds_size + (cmds_size / TYPE4_MAX_PAYLOAD) + 1) << 2; + + mutex_lock(&drm->struct_mutex); + a5xx_gpu->gpmu_bo = msm_gem_new(drm, bosize, MSM_BO_UNCACHED); + mutex_unlock(&drm->struct_mutex); + + if (IS_ERR(a5xx_gpu->gpmu_bo)) + goto err; + + if (msm_gem_get_iova(a5xx_gpu->gpmu_bo, gpu->id, &a5xx_gpu->gpmu_iova)) + goto err; + + ptr = msm_gem_get_vaddr(a5xx_gpu->gpmu_bo); + if (!ptr) + goto err; + + while (cmds_size > 0) { + int i; + uint32_t _size = cmds_size > TYPE4_MAX_PAYLOAD ? + TYPE4_MAX_PAYLOAD : cmds_size; + + ptr[dwords++] = PKT4(REG_A5XX_GPMU_INST_RAM_BASE + offset, + _size); + + for (i = 0; i < _size; i++) + ptr[dwords++] = *cmds++; + + offset += _size; + cmds_size -= _size; + } + + msm_gem_put_vaddr(a5xx_gpu->gpmu_bo); + a5xx_gpu->gpmu_dwords = dwords; + + goto out; + +err: + if (a5xx_gpu->gpmu_iova) + msm_gem_put_iova(a5xx_gpu->gpmu_bo, gpu->id); + if (a5xx_gpu->gpmu_bo) + drm_gem_object_unreference_unlocked(a5xx_gpu->gpmu_bo); + + a5xx_gpu->gpmu_bo = NULL; + a5xx_gpu->gpmu_iova = 0; + a5xx_gpu->gpmu_dwords = 0; + +out: + /* No need to keep that firmware laying around anymore */ + release_firmware(fw); +} diff --git a/drivers/gpu/drm/msm/adreno/adreno_common.xml.h b/drivers/gpu/drm/msm/adreno/adreno_common.xml.h index e81481d1b7df..4a33ba6f1244 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_common.xml.h +++ b/drivers/gpu/drm/msm/adreno/adreno_common.xml.h @@ -8,13 +8,14 @@ http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31) +- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2016-04-26 17:56:44) - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 11518 bytes, from 2016-02-10 21:03:25) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 16166 bytes, from 2016-02-11 21:20:31) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83967 bytes, from 2016-02-10 17:07:21) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 109916 bytes, from 2016-02-20 18:44:48) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32907 bytes, from 2016-11-26 23:01:08) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2016-11-26 23:01:08) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 22544 bytes, from 2016-11-26 23:01:08) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2016-11-26 23:01:08) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110765 bytes, from 2016-11-26 23:01:48) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 90321 bytes, from 2016-11-28 16:50:05) - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00) Copyright (C) 2013-2016 by the following authors: @@ -172,6 +173,14 @@ enum a3xx_color_swap { XYZW = 3, }; +enum a3xx_rb_blend_opcode { + BLEND_DST_PLUS_SRC = 0, + BLEND_SRC_MINUS_DST = 1, + BLEND_DST_MINUS_SRC = 2, + BLEND_MIN_DST_SRC = 3, + BLEND_MAX_DST_SRC = 4, +}; + #define REG_AXXX_CP_RB_BASE 0x000001c0 #define REG_AXXX_CP_RB_CNTL 0x000001c1 diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 7250ffc6322f..893eb2b2531b 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -74,6 +74,15 @@ static const struct adreno_info gpulist[] = { .pfpfw = "a420_pfp.fw", .gmem = (SZ_1M + SZ_512K), .init = a4xx_gpu_init, + }, { + .rev = ADRENO_REV(5, 3, 0, ANY_ID), + .revn = 530, + .name = "A530", + .pm4fw = "a530_pm4.fw", + .pfpfw = "a530_pfp.fw", + .gmem = SZ_1M, + .init = a5xx_gpu_init, + .gpmufw = "a530v3_gpmu.fw2", }, }; @@ -83,6 +92,8 @@ MODULE_FIRMWARE("a330_pm4.fw"); MODULE_FIRMWARE("a330_pfp.fw"); MODULE_FIRMWARE("a420_pm4.fw"); MODULE_FIRMWARE("a420_pfp.fw"); +MODULE_FIRMWARE("a530_fm4.fw"); +MODULE_FIRMWARE("a530_pfp.fw"); static inline bool _rev_match(uint8_t entry, uint8_t id) { @@ -145,12 +156,16 @@ struct msm_gpu *adreno_load_gpu(struct drm_device *dev) mutex_lock(&dev->struct_mutex); gpu->funcs->pm_resume(gpu); mutex_unlock(&dev->struct_mutex); + + disable_irq(gpu->irq); + ret = gpu->funcs->hw_init(gpu); if (ret) { dev_err(dev->dev, "gpu hw init failed: %d\n", ret); gpu->funcs->destroy(gpu); gpu = NULL; } else { + enable_irq(gpu->irq); /* give inactive pm a chance to kick in: */ msm_gpu_retire(gpu); } @@ -166,12 +181,20 @@ static void set_gpu_pdev(struct drm_device *dev, priv->gpu_pdev = pdev; } +static const struct { + const char *str; + uint32_t flag; +} quirks[] = { + { "qcom,gpu-quirk-two-pass-use-wfi", ADRENO_QUIRK_TWO_PASS_USE_WFI }, + { "qcom,gpu-quirk-fault-detect-mask", ADRENO_QUIRK_FAULT_DETECT_MASK }, +}; + static int adreno_bind(struct device *dev, struct device *master, void *data) { static struct adreno_platform_config config = {}; struct device_node *child, *node = dev->of_node; u32 val; - int ret; + int ret, i; ret = of_property_read_u32(node, "qcom,chipid", &val); if (ret) { @@ -205,6 +228,10 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) return -ENXIO; } + for (i = 0; i < ARRAY_SIZE(quirks); i++) + if (of_property_read_bool(node, quirks[i].str)) + config.quirks |= quirks[i].flag; + dev->platform_data = &config; set_gpu_pdev(dev_get_drvdata(master), to_platform_device(dev)); return 0; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index f386f463278d..a18126150e11 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -22,7 +22,7 @@ #include "msm_mmu.h" #define RB_SIZE SZ_32K -#define RB_BLKSIZE 16 +#define RB_BLKSIZE 32 int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value) { @@ -54,9 +54,6 @@ int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value) } } -#define rbmemptr(adreno_gpu, member) \ - ((adreno_gpu)->memptrs_iova + offsetof(struct adreno_rbmemptrs, member)) - int adreno_hw_init(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); @@ -79,11 +76,14 @@ int adreno_hw_init(struct msm_gpu *gpu) (adreno_is_a430(adreno_gpu) ? AXXX_CP_RB_CNTL_NO_UPDATE : 0)); /* Setup ringbuffer address: */ - adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_BASE, gpu->rb_iova); + adreno_gpu_write64(adreno_gpu, REG_ADRENO_CP_RB_BASE, + REG_ADRENO_CP_RB_BASE_HI, gpu->rb_iova); - if (!adreno_is_a430(adreno_gpu)) - adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_RPTR_ADDR, - rbmemptr(adreno_gpu, rptr)); + if (!adreno_is_a430(adreno_gpu)) { + adreno_gpu_write64(adreno_gpu, REG_ADRENO_CP_RB_RPTR_ADDR, + REG_ADRENO_CP_RB_RPTR_ADDR_HI, + rbmemptr(adreno_gpu, rptr)); + } return 0; } @@ -126,11 +126,14 @@ void adreno_recover(struct msm_gpu *gpu) adreno_gpu->memptrs->wptr = 0; gpu->funcs->pm_resume(gpu); + + disable_irq(gpu->irq); ret = gpu->funcs->hw_init(gpu); if (ret) { dev_err(dev->dev, "gpu hw init failed: %d\n", ret); /* hmm, oh well? */ } + enable_irq(gpu->irq); } void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, @@ -218,19 +221,18 @@ void adreno_flush(struct msm_gpu *gpu) adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_WPTR, wptr); } -void adreno_idle(struct msm_gpu *gpu) +bool adreno_idle(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); uint32_t wptr = get_wptr(gpu->rb); - int ret; /* wait for CP to drain ringbuffer: */ - ret = spin_until(get_rptr(adreno_gpu) == wptr); - - if (ret) - DRM_ERROR("%s: timeout waiting to drain ringbuffer!\n", gpu->name); + if (!spin_until(get_rptr(adreno_gpu) == wptr)) + return true; /* TODO maybe we need to reset GPU here to recover from hang? */ + DRM_ERROR("%s: timeout waiting to drain ringbuffer!\n", gpu->name); + return false; } #ifdef CONFIG_DEBUG_FS @@ -278,7 +280,6 @@ void adreno_show(struct msm_gpu *gpu, struct seq_file *m) void adreno_dump_info(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); - int i; printk("revision: %d (%d.%d.%d.%d)\n", adreno_gpu->info->revn, adreno_gpu->rev.core, @@ -290,11 +291,6 @@ void adreno_dump_info(struct msm_gpu *gpu) printk("rptr: %d\n", get_rptr(adreno_gpu)); printk("wptr: %d\n", adreno_gpu->memptrs->wptr); printk("rb wptr: %d\n", get_wptr(gpu->rb)); - - for (i = 0; i < 8; i++) { - printk("CP_SCRATCH_REG%d: %u\n", i, - gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i)); - } } /* would be nice to not have to duplicate the _show() stuff with printk(): */ @@ -350,6 +346,7 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, adreno_gpu->gmem = adreno_gpu->info->gmem; adreno_gpu->revn = adreno_gpu->info->revn; adreno_gpu->rev = config->rev; + adreno_gpu->quirks = config->quirks; gpu->fast_rate = config->fast_rate; gpu->slow_rate = config->slow_rate; @@ -381,7 +378,7 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, return ret; } - mmu = gpu->mmu; + mmu = gpu->aspace->mmu; if (mmu) { ret = mmu->funcs->attach(mmu, iommu_ports, ARRAY_SIZE(iommu_ports)); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 07d99bdf7c99..e8d55b0306ed 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -28,6 +28,9 @@ #include "adreno_pm4.xml.h" #define REG_ADRENO_DEFINE(_offset, _reg) [_offset] = (_reg) + 1 +#define REG_SKIP ~0 +#define REG_ADRENO_SKIP(_offset) [_offset] = REG_SKIP + /** * adreno_regs: List of registers that are used in across all * 3D devices. Each device type has different offset value for the same @@ -35,73 +38,21 @@ * and are indexed by the enumeration values defined in this enum */ enum adreno_regs { - REG_ADRENO_CP_DEBUG, - REG_ADRENO_CP_ME_RAM_WADDR, - REG_ADRENO_CP_ME_RAM_DATA, - REG_ADRENO_CP_PFP_UCODE_DATA, - REG_ADRENO_CP_PFP_UCODE_ADDR, - REG_ADRENO_CP_WFI_PEND_CTR, REG_ADRENO_CP_RB_BASE, + REG_ADRENO_CP_RB_BASE_HI, REG_ADRENO_CP_RB_RPTR_ADDR, + REG_ADRENO_CP_RB_RPTR_ADDR_HI, REG_ADRENO_CP_RB_RPTR, REG_ADRENO_CP_RB_WPTR, - REG_ADRENO_CP_PROTECT_CTRL, - REG_ADRENO_CP_ME_CNTL, REG_ADRENO_CP_RB_CNTL, - REG_ADRENO_CP_IB1_BASE, - REG_ADRENO_CP_IB1_BUFSZ, - REG_ADRENO_CP_IB2_BASE, - REG_ADRENO_CP_IB2_BUFSZ, - REG_ADRENO_CP_TIMESTAMP, - REG_ADRENO_CP_ME_RAM_RADDR, - REG_ADRENO_CP_ROQ_ADDR, - REG_ADRENO_CP_ROQ_DATA, - REG_ADRENO_CP_MERCIU_ADDR, - REG_ADRENO_CP_MERCIU_DATA, - REG_ADRENO_CP_MERCIU_DATA2, - REG_ADRENO_CP_MEQ_ADDR, - REG_ADRENO_CP_MEQ_DATA, - REG_ADRENO_CP_HW_FAULT, - REG_ADRENO_CP_PROTECT_STATUS, - REG_ADRENO_SCRATCH_ADDR, - REG_ADRENO_SCRATCH_UMSK, - REG_ADRENO_SCRATCH_REG2, - REG_ADRENO_RBBM_STATUS, - REG_ADRENO_RBBM_PERFCTR_CTL, - REG_ADRENO_RBBM_PERFCTR_LOAD_CMD0, - REG_ADRENO_RBBM_PERFCTR_LOAD_CMD1, - REG_ADRENO_RBBM_PERFCTR_LOAD_CMD2, - REG_ADRENO_RBBM_PERFCTR_PWR_1_LO, - REG_ADRENO_RBBM_INT_0_MASK, - REG_ADRENO_RBBM_INT_0_STATUS, - REG_ADRENO_RBBM_AHB_ERROR_STATUS, - REG_ADRENO_RBBM_PM_OVERRIDE2, - REG_ADRENO_RBBM_AHB_CMD, - REG_ADRENO_RBBM_INT_CLEAR_CMD, - REG_ADRENO_RBBM_SW_RESET_CMD, - REG_ADRENO_RBBM_CLOCK_CTL, - REG_ADRENO_RBBM_AHB_ME_SPLIT_STATUS, - REG_ADRENO_RBBM_AHB_PFP_SPLIT_STATUS, - REG_ADRENO_VPC_DEBUG_RAM_SEL, - REG_ADRENO_VPC_DEBUG_RAM_READ, - REG_ADRENO_VSC_SIZE_ADDRESS, - REG_ADRENO_VFD_CONTROL_0, - REG_ADRENO_VFD_INDEX_MAX, - REG_ADRENO_SP_VS_PVT_MEM_ADDR_REG, - REG_ADRENO_SP_FS_PVT_MEM_ADDR_REG, - REG_ADRENO_SP_VS_OBJ_START_REG, - REG_ADRENO_SP_FS_OBJ_START_REG, - REG_ADRENO_PA_SC_AA_CONFIG, - REG_ADRENO_SQ_GPR_MANAGEMENT, - REG_ADRENO_SQ_INST_STORE_MANAGMENT, - REG_ADRENO_TP0_CHICKEN, - REG_ADRENO_RBBM_RBBM_CTL, - REG_ADRENO_UCHE_INVALIDATE0, - REG_ADRENO_RBBM_PERFCTR_LOAD_VALUE_LO, - REG_ADRENO_RBBM_PERFCTR_LOAD_VALUE_HI, REG_ADRENO_REGISTER_MAX, }; +enum adreno_quirks { + ADRENO_QUIRK_TWO_PASS_USE_WFI = 1, + ADRENO_QUIRK_FAULT_DETECT_MASK = 2, +}; + struct adreno_rev { uint8_t core; uint8_t major; @@ -122,12 +73,16 @@ struct adreno_info { uint32_t revn; const char *name; const char *pm4fw, *pfpfw; + const char *gpmufw; uint32_t gmem; struct msm_gpu *(*init)(struct drm_device *dev); }; const struct adreno_info *adreno_info(struct adreno_rev rev); +#define rbmemptr(adreno_gpu, member) \ + ((adreno_gpu)->memptrs_iova + offsetof(struct adreno_rbmemptrs, member)) + struct adreno_rbmemptrs { volatile uint32_t rptr; volatile uint32_t wptr; @@ -153,7 +108,7 @@ struct adreno_gpu { // different for z180.. struct adreno_rbmemptrs *memptrs; struct drm_gem_object *memptrs_bo; - uint32_t memptrs_iova; + uint64_t memptrs_iova; /* * Register offsets are different between some GPUs. @@ -161,6 +116,8 @@ struct adreno_gpu { * code (a3xx_gpu.c) and stored in this common location. */ const unsigned int *reg_offsets; + + uint32_t quirks; }; #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base) @@ -171,6 +128,7 @@ struct adreno_platform_config { #ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING struct msm_bus_scale_pdata *bus_scale_table; #endif + uint32_t quirks; }; #define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000) @@ -234,6 +192,11 @@ static inline int adreno_is_a430(struct adreno_gpu *gpu) return gpu->revn == 430; } +static inline int adreno_is_a530(struct adreno_gpu *gpu) +{ + return gpu->revn == 530; +} + int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value); int adreno_hw_init(struct msm_gpu *gpu); uint32_t adreno_last_fence(struct msm_gpu *gpu); @@ -241,7 +204,7 @@ void adreno_recover(struct msm_gpu *gpu); void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, struct msm_file_private *ctx); void adreno_flush(struct msm_gpu *gpu); -void adreno_idle(struct msm_gpu *gpu); +bool adreno_idle(struct msm_gpu *gpu); #ifdef CONFIG_DEBUG_FS void adreno_show(struct msm_gpu *gpu, struct seq_file *m); #endif @@ -278,8 +241,38 @@ OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt) OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8)); } +static inline u32 PM4_PARITY(u32 val) +{ + return (0x9669 >> (0xF & (val ^ + (val >> 4) ^ (val >> 8) ^ (val >> 12) ^ + (val >> 16) ^ ((val) >> 20) ^ (val >> 24) ^ + (val >> 28)))) & 1; +} + +/* Maximum number of values that can be executed for one opcode */ +#define TYPE4_MAX_PAYLOAD 127 + +#define PKT4(_reg, _cnt) \ + (CP_TYPE4_PKT | ((_cnt) << 0) | (PM4_PARITY((_cnt)) << 7) | \ + (((_reg) & 0x3FFFF) << 8) | (PM4_PARITY((_reg)) << 27)) + +static inline void +OUT_PKT4(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt) +{ + adreno_wait_ring(ring->gpu, cnt + 1); + OUT_RING(ring, PKT4(regindx, cnt)); +} + +static inline void +OUT_PKT7(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt) +{ + adreno_wait_ring(ring->gpu, cnt + 1); + OUT_RING(ring, CP_TYPE7_PKT | (cnt << 0) | (PM4_PARITY(cnt) << 15) | + ((opcode & 0x7F) << 16) | (PM4_PARITY(opcode) << 23)); +} + /* - * adreno_checkreg_off() - Checks the validity of a register enum + * adreno_reg_check() - Checks the validity of a register enum * @gpu: Pointer to struct adreno_gpu * @offset_name: The register enum that is checked */ @@ -290,6 +283,16 @@ static inline bool adreno_reg_check(struct adreno_gpu *gpu, !gpu->reg_offsets[offset_name]) { BUG(); } + + /* + * REG_SKIP is a special value that tell us that the register in + * question isn't implemented on target but don't trigger a BUG(). This + * is used to cleanly implement adreno_gpu_write64() and + * adreno_gpu_read64() in a generic fashion + */ + if (gpu->reg_offsets[offset_name] == REG_SKIP) + return false; + return true; } @@ -313,5 +316,37 @@ static inline void adreno_gpu_write(struct adreno_gpu *gpu, struct msm_gpu *a3xx_gpu_init(struct drm_device *dev); struct msm_gpu *a4xx_gpu_init(struct drm_device *dev); +struct msm_gpu *a5xx_gpu_init(struct drm_device *dev); + +static inline void adreno_gpu_write64(struct adreno_gpu *gpu, + enum adreno_regs lo, enum adreno_regs hi, u64 data) +{ + adreno_gpu_write(gpu, lo, lower_32_bits(data)); + adreno_gpu_write(gpu, hi, upper_32_bits(data)); +} + +/* + * Given a register and a count, return a value to program into + * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len + * registers starting at _reg. + * + * The register base needs to be a multiple of the length. If it is not, the + * hardware will quietly mask off the bits for you and shift the size. For + * example, if you intend the protection to start at 0x07 for a length of 4 + * (0x07-0x0A) the hardware will actually protect (0x04-0x07) which might + * expose registers you intended to protect! + */ +#define ADRENO_PROTECT_RW(_reg, _len) \ + ((1 << 30) | (1 << 29) | \ + ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF)) + +/* + * Same as above, but allow reads over the range. For areas of mixed use (such + * as performance counters) this allows us to protect a much larger range with a + * single register + */ +#define ADRENO_PROTECT_RDONLY(_reg, _len) \ + ((1 << 29) \ + ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF)) #endif /* __ADRENO_GPU_H__ */ diff --git a/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h b/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h index d7477ff867c9..6a2930e75503 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h +++ b/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h @@ -8,13 +8,14 @@ http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31) +- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2016-04-26 17:56:44) - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 11518 bytes, from 2016-02-10 21:03:25) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 16166 bytes, from 2016-02-11 21:20:31) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83967 bytes, from 2016-02-10 17:07:21) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 109916 bytes, from 2016-02-20 18:44:48) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32907 bytes, from 2016-11-26 23:01:08) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2016-11-26 23:01:08) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 22544 bytes, from 2016-11-26 23:01:08) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2016-11-26 23:01:08) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110765 bytes, from 2016-11-26 23:01:48) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 90321 bytes, from 2016-11-28 16:50:05) - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00) Copyright (C) 2013-2016 by the following authors: @@ -58,6 +59,7 @@ enum vgt_event_type { RST_PIX_CNT = 13, RST_VTX_CNT = 14, TILE_FLUSH = 15, + STAT_EVENT = 16, CACHE_FLUSH_AND_INV_TS_EVENT = 20, ZPASS_DONE = 21, CACHE_FLUSH_AND_INV_EVENT = 22, @@ -65,6 +67,10 @@ enum vgt_event_type { PERFCOUNTER_STOP = 24, VS_FETCH_DONE = 27, FACENESS_FLUSH = 28, + UNK_1C = 28, + UNK_1D = 29, + BLIT = 30, + UNK_26 = 38, }; enum pc_di_primtype { @@ -82,7 +88,6 @@ enum pc_di_primtype { DI_PT_LINESTRIP_ADJ = 11, DI_PT_TRI_ADJ = 12, DI_PT_TRISTRIP_ADJ = 13, - DI_PT_PATCHES = 34, }; enum pc_di_src_sel { @@ -110,11 +115,15 @@ enum adreno_pm4_packet_type { CP_TYPE1_PKT = 0x40000000, CP_TYPE2_PKT = 0x80000000, CP_TYPE3_PKT = 0xc0000000, + CP_TYPE4_PKT = 0x40000000, + CP_TYPE7_PKT = 0x70000000, }; enum adreno_pm4_type3_packets { CP_ME_INIT = 72, CP_NOP = 16, + CP_PREEMPT_ENABLE = 28, + CP_PREEMPT_TOKEN = 30, CP_INDIRECT_BUFFER = 63, CP_INDIRECT_BUFFER_PFD = 55, CP_WAIT_FOR_IDLE = 38, @@ -163,6 +172,7 @@ enum adreno_pm4_type3_packets { CP_TEST_TWO_MEMS = 113, CP_REG_WR_NO_CTXT = 120, CP_RECORD_PFP_TIMESTAMP = 17, + CP_SET_SECURE_MODE = 102, CP_WAIT_FOR_ME = 19, CP_SET_DRAW_STATE = 67, CP_DRAW_INDX_OFFSET = 56, @@ -178,6 +188,22 @@ enum adreno_pm4_type3_packets { CP_WAIT_MEM_WRITES = 18, CP_COND_REG_EXEC = 71, CP_MEM_TO_REG = 66, + CP_EXEC_CS = 51, + CP_PERFCOUNTER_ACTION = 80, + CP_SMMU_TABLE_UPDATE = 83, + CP_CONTEXT_REG_BUNCH = 92, + CP_YIELD_ENABLE = 28, + CP_SKIP_IB2_ENABLE_GLOBAL = 29, + CP_SKIP_IB2_ENABLE_LOCAL = 35, + CP_SET_SUBDRAW_SIZE = 53, + CP_SET_VISIBILITY_OVERRIDE = 100, + CP_PREEMPT_ENABLE_GLOBAL = 105, + CP_PREEMPT_ENABLE_LOCAL = 106, + CP_CONTEXT_SWITCH_YIELD = 107, + CP_SET_RENDER_MODE = 108, + CP_COMPUTE_CHECKPOINT = 110, + CP_MEM_TO_MEM = 115, + CP_BLIT = 44, IN_IB_PREFETCH_END = 23, IN_SUBBLK_PREFETCH = 31, IN_INSTR_PREFETCH = 32, @@ -196,6 +222,7 @@ enum adreno_state_block { SB_VERT_SHADER = 4, SB_GEOM_SHADER = 5, SB_FRAG_SHADER = 6, + SB_COMPUTE_SHADER = 7, }; enum adreno_state_type { @@ -218,6 +245,17 @@ enum a4xx_index_size { INDEX4_SIZE_32_BIT = 2, }; +enum render_mode_cmd { + BYPASS = 1, + GMEM = 3, + BLIT2D = 5, +}; + +enum cp_blit_cmd { + BLIT_OP_FILL = 0, + BLIT_OP_BLIT = 1, +}; + #define REG_CP_LOAD_STATE_0 0x00000000 #define CP_LOAD_STATE_0_DST_OFF__MASK 0x0000ffff #define CP_LOAD_STATE_0_DST_OFF__SHIFT 0 @@ -258,6 +296,14 @@ static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val) return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK; } +#define REG_CP_LOAD_STATE_2 0x00000002 +#define CP_LOAD_STATE_2_EXT_SRC_ADDR_HI__MASK 0xffffffff +#define CP_LOAD_STATE_2_EXT_SRC_ADDR_HI__SHIFT 0 +static inline uint32_t CP_LOAD_STATE_2_EXT_SRC_ADDR_HI(uint32_t val) +{ + return ((val) << CP_LOAD_STATE_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE_2_EXT_SRC_ADDR_HI__MASK; +} + #define REG_CP_DRAW_INDX_0 0x00000000 #define CP_DRAW_INDX_0_VIZ_QUERY__MASK 0xffffffff #define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT 0 @@ -389,7 +435,12 @@ static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel va { return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK; } -#define CP_DRAW_INDX_OFFSET_0_TESSELLATE 0x00000100 +#define CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK 0x00000300 +#define CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT 8 +static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val) +{ + return ((val) << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK; +} #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK 0x00000c00 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT 10 static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val) @@ -437,30 +488,40 @@ static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val) return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK; } -#define REG_CP_SET_DRAW_STATE_0 0x00000000 -#define CP_SET_DRAW_STATE_0_COUNT__MASK 0x0000ffff -#define CP_SET_DRAW_STATE_0_COUNT__SHIFT 0 -static inline uint32_t CP_SET_DRAW_STATE_0_COUNT(uint32_t val) +static inline uint32_t REG_CP_SET_DRAW_STATE_(uint32_t i0) { return 0x00000000 + 0x3*i0; } + +static inline uint32_t REG_CP_SET_DRAW_STATE__0(uint32_t i0) { return 0x00000000 + 0x3*i0; } +#define CP_SET_DRAW_STATE__0_COUNT__MASK 0x0000ffff +#define CP_SET_DRAW_STATE__0_COUNT__SHIFT 0 +static inline uint32_t CP_SET_DRAW_STATE__0_COUNT(uint32_t val) { - return ((val) << CP_SET_DRAW_STATE_0_COUNT__SHIFT) & CP_SET_DRAW_STATE_0_COUNT__MASK; + return ((val) << CP_SET_DRAW_STATE__0_COUNT__SHIFT) & CP_SET_DRAW_STATE__0_COUNT__MASK; } -#define CP_SET_DRAW_STATE_0_DIRTY 0x00010000 -#define CP_SET_DRAW_STATE_0_DISABLE 0x00020000 -#define CP_SET_DRAW_STATE_0_DISABLE_ALL_GROUPS 0x00040000 -#define CP_SET_DRAW_STATE_0_LOAD_IMMED 0x00080000 -#define CP_SET_DRAW_STATE_0_GROUP_ID__MASK 0x1f000000 -#define CP_SET_DRAW_STATE_0_GROUP_ID__SHIFT 24 -static inline uint32_t CP_SET_DRAW_STATE_0_GROUP_ID(uint32_t val) +#define CP_SET_DRAW_STATE__0_DIRTY 0x00010000 +#define CP_SET_DRAW_STATE__0_DISABLE 0x00020000 +#define CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS 0x00040000 +#define CP_SET_DRAW_STATE__0_LOAD_IMMED 0x00080000 +#define CP_SET_DRAW_STATE__0_GROUP_ID__MASK 0x1f000000 +#define CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT 24 +static inline uint32_t CP_SET_DRAW_STATE__0_GROUP_ID(uint32_t val) { - return ((val) << CP_SET_DRAW_STATE_0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE_0_GROUP_ID__MASK; + return ((val) << CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE__0_GROUP_ID__MASK; } -#define REG_CP_SET_DRAW_STATE_1 0x00000001 -#define CP_SET_DRAW_STATE_1_ADDR__MASK 0xffffffff -#define CP_SET_DRAW_STATE_1_ADDR__SHIFT 0 -static inline uint32_t CP_SET_DRAW_STATE_1_ADDR(uint32_t val) +static inline uint32_t REG_CP_SET_DRAW_STATE__1(uint32_t i0) { return 0x00000001 + 0x3*i0; } +#define CP_SET_DRAW_STATE__1_ADDR_LO__MASK 0xffffffff +#define CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT 0 +static inline uint32_t CP_SET_DRAW_STATE__1_ADDR_LO(uint32_t val) { - return ((val) << CP_SET_DRAW_STATE_1_ADDR__SHIFT) & CP_SET_DRAW_STATE_1_ADDR__MASK; + return ((val) << CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT) & CP_SET_DRAW_STATE__1_ADDR_LO__MASK; +} + +static inline uint32_t REG_CP_SET_DRAW_STATE__2(uint32_t i0) { return 0x00000002 + 0x3*i0; } +#define CP_SET_DRAW_STATE__2_ADDR_HI__MASK 0xffffffff +#define CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT 0 +static inline uint32_t CP_SET_DRAW_STATE__2_ADDR_HI(uint32_t val) +{ + return ((val) << CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT) & CP_SET_DRAW_STATE__2_ADDR_HI__MASK; } #define REG_CP_SET_BIN_0 0x00000000 @@ -533,5 +594,192 @@ static inline uint32_t CP_REG_TO_MEM_1_DEST(uint32_t val) return ((val) << CP_REG_TO_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_1_DEST__MASK; } +#define REG_CP_DISPATCH_COMPUTE_0 0x00000000 + +#define REG_CP_DISPATCH_COMPUTE_1 0x00000001 +#define CP_DISPATCH_COMPUTE_1_X__MASK 0xffffffff +#define CP_DISPATCH_COMPUTE_1_X__SHIFT 0 +static inline uint32_t CP_DISPATCH_COMPUTE_1_X(uint32_t val) +{ + return ((val) << CP_DISPATCH_COMPUTE_1_X__SHIFT) & CP_DISPATCH_COMPUTE_1_X__MASK; +} + +#define REG_CP_DISPATCH_COMPUTE_2 0x00000002 +#define CP_DISPATCH_COMPUTE_2_Y__MASK 0xffffffff +#define CP_DISPATCH_COMPUTE_2_Y__SHIFT 0 +static inline uint32_t CP_DISPATCH_COMPUTE_2_Y(uint32_t val) +{ + return ((val) << CP_DISPATCH_COMPUTE_2_Y__SHIFT) & CP_DISPATCH_COMPUTE_2_Y__MASK; +} + +#define REG_CP_DISPATCH_COMPUTE_3 0x00000003 +#define CP_DISPATCH_COMPUTE_3_Z__MASK 0xffffffff +#define CP_DISPATCH_COMPUTE_3_Z__SHIFT 0 +static inline uint32_t CP_DISPATCH_COMPUTE_3_Z(uint32_t val) +{ + return ((val) << CP_DISPATCH_COMPUTE_3_Z__SHIFT) & CP_DISPATCH_COMPUTE_3_Z__MASK; +} + +#define REG_CP_SET_RENDER_MODE_0 0x00000000 +#define CP_SET_RENDER_MODE_0_MODE__MASK 0x000001ff +#define CP_SET_RENDER_MODE_0_MODE__SHIFT 0 +static inline uint32_t CP_SET_RENDER_MODE_0_MODE(enum render_mode_cmd val) +{ + return ((val) << CP_SET_RENDER_MODE_0_MODE__SHIFT) & CP_SET_RENDER_MODE_0_MODE__MASK; +} + +#define REG_CP_SET_RENDER_MODE_1 0x00000001 +#define CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK 0xffffffff +#define CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT 0 +static inline uint32_t CP_SET_RENDER_MODE_1_ADDR_0_LO(uint32_t val) +{ + return ((val) << CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT) & CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK; +} + +#define REG_CP_SET_RENDER_MODE_2 0x00000002 +#define CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK 0xffffffff +#define CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT 0 +static inline uint32_t CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val) +{ + return ((val) << CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT) & CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK; +} + +#define REG_CP_SET_RENDER_MODE_3 0x00000003 +#define CP_SET_RENDER_MODE_3_GMEM_ENABLE 0x00000010 + +#define REG_CP_SET_RENDER_MODE_4 0x00000004 + +#define REG_CP_SET_RENDER_MODE_5 0x00000005 +#define CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK 0xffffffff +#define CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT 0 +static inline uint32_t CP_SET_RENDER_MODE_5_ADDR_1_LEN(uint32_t val) +{ + return ((val) << CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT) & CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK; +} + +#define REG_CP_SET_RENDER_MODE_6 0x00000006 +#define CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK 0xffffffff +#define CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT 0 +static inline uint32_t CP_SET_RENDER_MODE_6_ADDR_1_LO(uint32_t val) +{ + return ((val) << CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT) & CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK; +} + +#define REG_CP_SET_RENDER_MODE_7 0x00000007 +#define CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK 0xffffffff +#define CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT 0 +static inline uint32_t CP_SET_RENDER_MODE_7_ADDR_1_HI(uint32_t val) +{ + return ((val) << CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT) & CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK; +} + +#define REG_CP_PERFCOUNTER_ACTION_0 0x00000000 + +#define REG_CP_PERFCOUNTER_ACTION_1 0x00000001 +#define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK 0xffffffff +#define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT 0 +static inline uint32_t CP_PERFCOUNTER_ACTION_1_ADDR_0_LO(uint32_t val) +{ + return ((val) << CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT) & CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK; +} + +#define REG_CP_PERFCOUNTER_ACTION_2 0x00000002 +#define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK 0xffffffff +#define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT 0 +static inline uint32_t CP_PERFCOUNTER_ACTION_2_ADDR_0_HI(uint32_t val) +{ + return ((val) << CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT) & CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK; +} + +#define REG_CP_EVENT_WRITE_0 0x00000000 +#define CP_EVENT_WRITE_0_EVENT__MASK 0x000000ff +#define CP_EVENT_WRITE_0_EVENT__SHIFT 0 +static inline uint32_t CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val) +{ + return ((val) << CP_EVENT_WRITE_0_EVENT__SHIFT) & CP_EVENT_WRITE_0_EVENT__MASK; +} + +#define REG_CP_EVENT_WRITE_1 0x00000001 +#define CP_EVENT_WRITE_1_ADDR_0_LO__MASK 0xffffffff +#define CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT 0 +static inline uint32_t CP_EVENT_WRITE_1_ADDR_0_LO(uint32_t val) +{ + return ((val) << CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT) & CP_EVENT_WRITE_1_ADDR_0_LO__MASK; +} + +#define REG_CP_EVENT_WRITE_2 0x00000002 +#define CP_EVENT_WRITE_2_ADDR_0_HI__MASK 0xffffffff +#define CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT 0 +static inline uint32_t CP_EVENT_WRITE_2_ADDR_0_HI(uint32_t val) +{ + return ((val) << CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT) & CP_EVENT_WRITE_2_ADDR_0_HI__MASK; +} + +#define REG_CP_EVENT_WRITE_3 0x00000003 + +#define REG_CP_BLIT_0 0x00000000 +#define CP_BLIT_0_OP__MASK 0x0000000f +#define CP_BLIT_0_OP__SHIFT 0 +static inline uint32_t CP_BLIT_0_OP(enum cp_blit_cmd val) +{ + return ((val) << CP_BLIT_0_OP__SHIFT) & CP_BLIT_0_OP__MASK; +} + +#define REG_CP_BLIT_1 0x00000001 +#define CP_BLIT_1_SRC_X1__MASK 0x0000ffff +#define CP_BLIT_1_SRC_X1__SHIFT 0 +static inline uint32_t CP_BLIT_1_SRC_X1(uint32_t val) +{ + return ((val) << CP_BLIT_1_SRC_X1__SHIFT) & CP_BLIT_1_SRC_X1__MASK; +} +#define CP_BLIT_1_SRC_Y1__MASK 0xffff0000 +#define CP_BLIT_1_SRC_Y1__SHIFT 16 +static inline uint32_t CP_BLIT_1_SRC_Y1(uint32_t val) +{ + return ((val) << CP_BLIT_1_SRC_Y1__SHIFT) & CP_BLIT_1_SRC_Y1__MASK; +} + +#define REG_CP_BLIT_2 0x00000002 +#define CP_BLIT_2_SRC_X2__MASK 0x0000ffff +#define CP_BLIT_2_SRC_X2__SHIFT 0 +static inline uint32_t CP_BLIT_2_SRC_X2(uint32_t val) +{ + return ((val) << CP_BLIT_2_SRC_X2__SHIFT) & CP_BLIT_2_SRC_X2__MASK; +} +#define CP_BLIT_2_SRC_Y2__MASK 0xffff0000 +#define CP_BLIT_2_SRC_Y2__SHIFT 16 +static inline uint32_t CP_BLIT_2_SRC_Y2(uint32_t val) +{ + return ((val) << CP_BLIT_2_SRC_Y2__SHIFT) & CP_BLIT_2_SRC_Y2__MASK; +} + +#define REG_CP_BLIT_3 0x00000003 +#define CP_BLIT_3_DST_X1__MASK 0x0000ffff +#define CP_BLIT_3_DST_X1__SHIFT 0 +static inline uint32_t CP_BLIT_3_DST_X1(uint32_t val) +{ + return ((val) << CP_BLIT_3_DST_X1__SHIFT) & CP_BLIT_3_DST_X1__MASK; +} +#define CP_BLIT_3_DST_Y1__MASK 0xffff0000 +#define CP_BLIT_3_DST_Y1__SHIFT 16 +static inline uint32_t CP_BLIT_3_DST_Y1(uint32_t val) +{ + return ((val) << CP_BLIT_3_DST_Y1__SHIFT) & CP_BLIT_3_DST_Y1__MASK; +} + +#define REG_CP_BLIT_4 0x00000004 +#define CP_BLIT_4_DST_X2__MASK 0x0000ffff +#define CP_BLIT_4_DST_X2__SHIFT 0 +static inline uint32_t CP_BLIT_4_DST_X2(uint32_t val) +{ + return ((val) << CP_BLIT_4_DST_X2__SHIFT) & CP_BLIT_4_DST_X2__MASK; +} +#define CP_BLIT_4_DST_Y2__MASK 0xffff0000 +#define CP_BLIT_4_DST_Y2__SHIFT 16 +static inline uint32_t CP_BLIT_4_DST_Y2(uint32_t val) +{ + return ((val) << CP_BLIT_4_DST_Y2__SHIFT) & CP_BLIT_4_DST_Y2__MASK; +} + #endif /* ADRENO_PM4_XML */ diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h b/drivers/gpu/drm/msm/dsi/dsi.xml.h index 4958594d5266..39dff7d5e89b 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.xml.h +++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h @@ -12,7 +12,7 @@ The rules-ng-ng source files this header was generated from are: - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36965 bytes, from 2016-11-26 23:01:08) - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52) - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02) - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index f05ed0e1f3d6..3819fdefcae2 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -139,6 +139,7 @@ struct msm_dsi_host { u32 err_work_state; struct work_struct err_work; + struct work_struct hpd_work; struct workqueue_struct *workqueue; /* DSI 6G TX buffer*/ @@ -981,7 +982,7 @@ static int dsi_tx_buf_alloc(struct msm_dsi_host *msm_host, int size) struct drm_device *dev = msm_host->dev; const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; int ret; - u32 iova; + uint64_t iova; if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) { mutex_lock(&dev->struct_mutex); @@ -1146,7 +1147,7 @@ static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len) { const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; int ret; - u32 dma_base; + uint64_t dma_base; bool triggered; if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) { @@ -1294,6 +1295,14 @@ static void dsi_sw_reset_restore(struct msm_dsi_host *msm_host) wmb(); /* make sure dsi controller enabled again */ } +static void dsi_hpd_worker(struct work_struct *work) +{ + struct msm_dsi_host *msm_host = + container_of(work, struct msm_dsi_host, hpd_work); + + drm_helper_hpd_irq_event(msm_host->dev); +} + static void dsi_err_worker(struct work_struct *work) { struct msm_dsi_host *msm_host = @@ -1480,7 +1489,7 @@ static int dsi_host_attach(struct mipi_dsi_host *host, DBG("id=%d", msm_host->id); if (msm_host->dev) - drm_helper_hpd_irq_event(msm_host->dev); + queue_work(msm_host->workqueue, &msm_host->hpd_work); return 0; } @@ -1494,7 +1503,7 @@ static int dsi_host_detach(struct mipi_dsi_host *host, DBG("id=%d", msm_host->id); if (msm_host->dev) - drm_helper_hpd_irq_event(msm_host->dev); + queue_work(msm_host->workqueue, &msm_host->hpd_work); return 0; } @@ -1748,6 +1757,7 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi) /* setup workqueue */ msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0); INIT_WORK(&msm_host->err_work, dsi_err_worker); + INIT_WORK(&msm_host->hpd_work, dsi_hpd_worker); msm_dsi->host = &msm_host->base; msm_dsi->id = msm_host->id; diff --git a/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h b/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h index 2d999494cdea..8b9f3ebaeba7 100644 --- a/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h +++ b/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h @@ -12,7 +12,7 @@ The rules-ng-ng source files this header was generated from are: - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36965 bytes, from 2016-11-26 23:01:08) - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52) - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02) - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14) diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c index 598fdaff0a41..26e3a01a99c2 100644 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c @@ -521,6 +521,7 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm) .parent_names = (const char *[]){ "xo" }, .num_parents = 1, .name = vco_name, + .flags = CLK_IGNORE_UNUSED, .ops = &clk_ops_dsi_pll_28nm_vco, }; struct device *dev = &pll_28nm->pdev->dev; diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c index 38c90e1eb002..49008451085b 100644 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c @@ -412,6 +412,7 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm) struct clk_init_data vco_init = { .parent_names = (const char *[]){ "pxo" }, .num_parents = 1, + .flags = CLK_IGNORE_UNUSED, .ops = &clk_ops_dsi_pll_28nm_vco, }; struct device *dev = &pll_28nm->pdev->dev; diff --git a/drivers/gpu/drm/msm/dsi/sfpb.xml.h b/drivers/gpu/drm/msm/dsi/sfpb.xml.h index 506434fac993..3fcbb30dc241 100644 --- a/drivers/gpu/drm/msm/dsi/sfpb.xml.h +++ b/drivers/gpu/drm/msm/dsi/sfpb.xml.h @@ -12,7 +12,7 @@ The rules-ng-ng source files this header was generated from are: - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36965 bytes, from 2016-11-26 23:01:08) - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52) - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02) - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14) diff --git a/drivers/gpu/drm/msm/edp/edp.xml.h b/drivers/gpu/drm/msm/edp/edp.xml.h index f1072c18c81e..d7bf3232dc88 100644 --- a/drivers/gpu/drm/msm/edp/edp.xml.h +++ b/drivers/gpu/drm/msm/edp/edp.xml.h @@ -12,7 +12,7 @@ The rules-ng-ng source files this header was generated from are: - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36965 bytes, from 2016-11-26 23:01:08) - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52) - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02) - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14) diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h index 34c7df6549c1..0a97ff75ed6f 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h +++ b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h @@ -12,7 +12,7 @@ The rules-ng-ng source files this header was generated from are: - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36965 bytes, from 2016-11-26 23:01:08) - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52) - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02) - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14) diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c b/drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c index aa94a553794f..143eab46ba68 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c @@ -702,6 +702,7 @@ static struct clk_init_data pll_init = { .ops = &hdmi_8996_pll_ops, .parent_names = hdmi_pll_parents, .num_parents = ARRAY_SIZE(hdmi_pll_parents), + .flags = CLK_IGNORE_UNUSED, }; int msm_hdmi_pll_8996_init(struct platform_device *pdev) diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c b/drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c index 92da69aa6187..99590758c68b 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c @@ -424,6 +424,7 @@ static struct clk_init_data pll_init = { .ops = &hdmi_pll_ops, .parent_names = hdmi_pll_parents, .num_parents = ARRAY_SIZE(hdmi_pll_parents), + .flags = CLK_IGNORE_UNUSED, }; int msm_hdmi_pll_8960_init(struct platform_device *pdev) diff --git a/drivers/gpu/drm/msm/hdmi/qfprom.xml.h b/drivers/gpu/drm/msm/hdmi/qfprom.xml.h index 6eab7d0cf6b5..1b996ede7a65 100644 --- a/drivers/gpu/drm/msm/hdmi/qfprom.xml.h +++ b/drivers/gpu/drm/msm/hdmi/qfprom.xml.h @@ -12,7 +12,7 @@ The rules-ng-ng source files this header was generated from are: - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36965 bytes, from 2016-11-26 23:01:08) - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52) - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02) - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14) diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h b/drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h index 6688e79cc88e..88037889589b 100644 --- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h +++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h @@ -12,7 +12,7 @@ The rules-ng-ng source files this header was generated from are: - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36965 bytes, from 2016-11-26 23:01:08) - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52) - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02) - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14) diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c index 9527dafc3e69..1c29618f4ddb 100644 --- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c +++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c @@ -373,7 +373,7 @@ static void update_cursor(struct drm_crtc *crtc) if (mdp4_crtc->cursor.stale) { struct drm_gem_object *next_bo = mdp4_crtc->cursor.next_bo; struct drm_gem_object *prev_bo = mdp4_crtc->cursor.scanout_bo; - uint32_t iova = mdp4_crtc->cursor.next_iova; + uint64_t iova = mdp4_crtc->cursor.next_iova; if (next_bo) { /* take a obj ref + iova ref when we start scanning out: */ @@ -418,7 +418,7 @@ static int mdp4_crtc_cursor_set(struct drm_crtc *crtc, struct drm_device *dev = crtc->dev; struct drm_gem_object *cursor_bo, *old_bo; unsigned long flags; - uint32_t iova; + uint64_t iova; int ret; if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) { diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c index 571a91ee9607..b782efd4b95f 100644 --- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c +++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c @@ -17,6 +17,7 @@ #include "msm_drv.h" +#include "msm_gem.h" #include "msm_mmu.h" #include "mdp4_kms.h" @@ -159,17 +160,18 @@ static void mdp4_destroy(struct msm_kms *kms) { struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); struct device *dev = mdp4_kms->dev->dev; - struct msm_mmu *mmu = mdp4_kms->mmu; - - if (mmu) { - mmu->funcs->detach(mmu, iommu_ports, ARRAY_SIZE(iommu_ports)); - mmu->funcs->destroy(mmu); - } + struct msm_gem_address_space *aspace = mdp4_kms->aspace; if (mdp4_kms->blank_cursor_iova) msm_gem_put_iova(mdp4_kms->blank_cursor_bo, mdp4_kms->id); drm_gem_object_unreference_unlocked(mdp4_kms->blank_cursor_bo); + if (aspace) { + aspace->mmu->funcs->detach(aspace->mmu, + iommu_ports, ARRAY_SIZE(iommu_ports)); + msm_gem_address_space_destroy(aspace); + } + if (mdp4_kms->rpm_enabled) pm_runtime_disable(dev); @@ -440,7 +442,7 @@ struct msm_kms *mdp4_kms_init(struct drm_device *dev) struct mdp4_platform_config *config = mdp4_get_config(pdev); struct mdp4_kms *mdp4_kms; struct msm_kms *kms = NULL; - struct msm_mmu *mmu; + struct msm_gem_address_space *aspace; int irq, ret; mdp4_kms = kzalloc(sizeof(*mdp4_kms), GFP_KERNEL); @@ -531,24 +533,26 @@ struct msm_kms *mdp4_kms_init(struct drm_device *dev) mdelay(16); if (config->iommu) { - mmu = msm_iommu_new(&pdev->dev, config->iommu); - if (IS_ERR(mmu)) { - ret = PTR_ERR(mmu); + aspace = msm_gem_address_space_create(&pdev->dev, + config->iommu, "mdp4"); + if (IS_ERR(aspace)) { + ret = PTR_ERR(aspace); goto fail; } - ret = mmu->funcs->attach(mmu, iommu_ports, + + mdp4_kms->aspace = aspace; + + ret = aspace->mmu->funcs->attach(aspace->mmu, iommu_ports, ARRAY_SIZE(iommu_ports)); if (ret) goto fail; - - mdp4_kms->mmu = mmu; } else { dev_info(dev->dev, "no iommu, fallback to phys " "contig buffers for scanout\n"); - mmu = NULL; + aspace = NULL; } - mdp4_kms->id = msm_register_mmu(dev, mmu); + mdp4_kms->id = msm_register_address_space(dev, aspace); if (mdp4_kms->id < 0) { ret = mdp4_kms->id; dev_err(dev->dev, "failed to register mdp4 iommu: %d\n", ret); @@ -598,6 +602,10 @@ static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev) /* TODO: Chips that aren't apq8064 have a 200 Mhz max_clk */ config.max_clk = 266667000; config.iommu = iommu_domain_alloc(&platform_bus_type); + if (config.iommu) { + config.iommu->geometry.aperture_start = 0x1000; + config.iommu->geometry.aperture_end = 0xffffffff; + } return &config; } diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h index 25fb83997119..62712ca164ee 100644 --- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h +++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h @@ -43,7 +43,7 @@ struct mdp4_kms { struct clk *pclk; struct clk *lut_clk; struct clk *axi_clk; - struct msm_mmu *mmu; + struct msm_gem_address_space *aspace; struct mdp_irq error_handler; @@ -51,7 +51,7 @@ struct mdp4_kms { /* empty/blank cursor bo to use when cursor is "disabled" */ struct drm_gem_object *blank_cursor_bo; - uint32_t blank_cursor_iova; + uint64_t blank_cursor_iova; }; #define to_mdp4_kms(x) container_of(x, struct mdp4_kms, base) diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h index ca6ca30650a0..27d5371acee0 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h @@ -8,9 +8,17 @@ http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /local/mnt/workspace/source_trees/envytools/rnndb/../rnndb/mdp/mdp5.xml ( 36965 bytes, from 2016-05-10 05:06:30) -- /local/mnt/workspace/source_trees/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-05-09 06:32:54) -- /local/mnt/workspace/source_trees/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2016-01-07 08:45:55) +- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14) +- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36965 bytes, from 2016-11-26 23:01:08) +- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52) +- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02) +- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14) +- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07) +- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18) +- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14) Copyright (C) 2013-2016 by the following authors: - Rob Clark <robdclark@gmail.com> (robclark) diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c index ac9e4cde1380..618b2ffed9b4 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c @@ -272,7 +272,7 @@ const struct mdp5_cfg_hw msm8x16_config = { .count = 2, .base = { 0x14000, 0x16000 }, .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP | - MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION, + MDP_PIPE_CAP_DECIMATION, }, .pipe_dma = { .count = 1, @@ -282,7 +282,7 @@ const struct mdp5_cfg_hw msm8x16_config = { .lm = { .count = 2, /* LM0 and LM3 */ .base = { 0x44000, 0x47000 }, - .nb_stages = 5, + .nb_stages = 8, .max_width = 2048, .max_height = 0xFFFF, }, @@ -550,6 +550,10 @@ static struct mdp5_cfg_platform *mdp5_get_config(struct platform_device *dev) static struct mdp5_cfg_platform config = {}; config.iommu = iommu_domain_alloc(&platform_bus_type); + if (config.iommu) { + config.iommu->geometry.aperture_start = 0x1000; + config.iommu->geometry.aperture_end = 0xffffffff; + } return &config; } diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c index fa2be7ce9468..1ce8a01a5a28 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c @@ -27,11 +27,8 @@ #define CURSOR_WIDTH 64 #define CURSOR_HEIGHT 64 -#define SSPP_MAX (SSPP_RGB3 + 1) /* TODO: Add SSPP_MAX in mdp5.xml.h */ - struct mdp5_crtc { struct drm_crtc base; - char name[8]; int id; bool enabled; @@ -102,7 +99,7 @@ static u32 crtc_flush(struct drm_crtc *crtc, u32 flush_mask) { struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); - DBG("%s: flush=%08x", mdp5_crtc->name, flush_mask); + DBG("%s: flush=%08x", crtc->name, flush_mask); return mdp5_ctl_commit(mdp5_crtc->ctl, flush_mask); } @@ -136,7 +133,6 @@ static void complete_flip(struct drm_crtc *crtc, struct drm_file *file) struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); struct drm_device *dev = crtc->dev; struct drm_pending_vblank_event *event; - struct drm_plane *plane; unsigned long flags; spin_lock_irqsave(&dev->event_lock, flags); @@ -148,16 +144,12 @@ static void complete_flip(struct drm_crtc *crtc, struct drm_file *file) */ if (!file || (event->base.file_priv == file)) { mdp5_crtc->event = NULL; - DBG("%s: send event: %p", mdp5_crtc->name, event); + DBG("%s: send event: %p", crtc->name, event); drm_crtc_send_vblank_event(crtc, event); } } spin_unlock_irqrestore(&dev->event_lock, flags); - drm_atomic_crtc_for_each_plane(plane, crtc) { - mdp5_plane_complete_flip(plane); - } - if (mdp5_crtc->ctl && !crtc->state->enable) { /* set STAGE_UNUSED for all layers */ mdp5_ctl_blend(mdp5_crtc->ctl, NULL, 0, 0); @@ -223,12 +215,7 @@ static void blend_setup(struct drm_crtc *crtc) plane_cnt++; } - /* - * If there is no base layer, enable border color. - * Although it's not possbile in current blend logic, - * put it here as a reminder. - */ - if (!pstates[STAGE_BASE] && plane_cnt) { + if (!pstates[STAGE_BASE]) { ctl_blend_flags |= MDP5_CTL_BLEND_OP_FLAG_BORDER_OUT; DBG("Border Color is enabled"); } @@ -300,7 +287,7 @@ static void mdp5_crtc_mode_set_nofb(struct drm_crtc *crtc) mode = &crtc->state->adjusted_mode; DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x", - mdp5_crtc->name, mode->base.id, mode->name, + crtc->name, mode->base.id, mode->name, mode->vrefresh, mode->clock, mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal, @@ -320,7 +307,7 @@ static void mdp5_crtc_disable(struct drm_crtc *crtc) struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); struct mdp5_kms *mdp5_kms = get_kms(crtc); - DBG("%s", mdp5_crtc->name); + DBG("%s", crtc->name); if (WARN_ON(!mdp5_crtc->enabled)) return; @@ -339,7 +326,7 @@ static void mdp5_crtc_enable(struct drm_crtc *crtc) struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); struct mdp5_kms *mdp5_kms = get_kms(crtc); - DBG("%s", mdp5_crtc->name); + DBG("%s", crtc->name); if (WARN_ON(mdp5_crtc->enabled)) return; @@ -365,31 +352,29 @@ static int pstate_cmp(const void *a, const void *b) return pa->state->zpos - pb->state->zpos; } +/* is there a helper for this? */ +static bool is_fullscreen(struct drm_crtc_state *cstate, + struct drm_plane_state *pstate) +{ + return (pstate->crtc_x <= 0) && (pstate->crtc_y <= 0) && + ((pstate->crtc_x + pstate->crtc_w) >= cstate->mode.hdisplay) && + ((pstate->crtc_y + pstate->crtc_h) >= cstate->mode.vdisplay); +} + static int mdp5_crtc_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state) { - struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); struct mdp5_kms *mdp5_kms = get_kms(crtc); struct drm_plane *plane; struct drm_device *dev = crtc->dev; struct plane_state pstates[STAGE_MAX + 1]; const struct mdp5_cfg_hw *hw_cfg; const struct drm_plane_state *pstate; - int cnt = 0, i; + int cnt = 0, base = 0, i; - DBG("%s: check", mdp5_crtc->name); + DBG("%s: check", crtc->name); - /* verify that there are not too many planes attached to crtc - * and that we don't have conflicting mixer stages: - */ - hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) { - if (cnt >= (hw_cfg->lm.nb_stages)) { - dev_err(dev->dev, "too many planes!\n"); - return -EINVAL; - } - - pstates[cnt].plane = plane; pstates[cnt].state = to_mdp5_plane_state(pstate); @@ -399,10 +384,26 @@ static int mdp5_crtc_atomic_check(struct drm_crtc *crtc, /* assign a stage based on sorted zpos property */ sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL); + /* if the bottom-most layer is not fullscreen, we need to use + * it for solid-color: + */ + if ((cnt > 0) && !is_fullscreen(state, &pstates[0].state->base)) + base++; + + /* verify that there are not too many planes attached to crtc + * and that we don't have conflicting mixer stages: + */ + hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); + + if ((cnt + base) >= hw_cfg->lm.nb_stages) { + dev_err(dev->dev, "too many planes! cnt=%d, base=%d\n", cnt, base); + return -EINVAL; + } + for (i = 0; i < cnt; i++) { - pstates[i].state->stage = STAGE_BASE + i; - DBG("%s: assign pipe %s on stage=%d", mdp5_crtc->name, - pipe2name(mdp5_plane_pipe(pstates[i].plane)), + pstates[i].state->stage = STAGE_BASE + i + base; + DBG("%s: assign pipe %s on stage=%d", crtc->name, + pstates[i].plane->name, pstates[i].state->stage); } @@ -412,8 +413,7 @@ static int mdp5_crtc_atomic_check(struct drm_crtc *crtc, static void mdp5_crtc_atomic_begin(struct drm_crtc *crtc, struct drm_crtc_state *old_crtc_state) { - struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); - DBG("%s: begin", mdp5_crtc->name); + DBG("%s: begin", crtc->name); } static void mdp5_crtc_atomic_flush(struct drm_crtc *crtc, @@ -423,7 +423,7 @@ static void mdp5_crtc_atomic_flush(struct drm_crtc *crtc, struct drm_device *dev = crtc->dev; unsigned long flags; - DBG("%s: event: %p", mdp5_crtc->name, crtc->state->event); + DBG("%s: event: %p", crtc->name, crtc->state->event); WARN_ON(mdp5_crtc->event); @@ -489,7 +489,8 @@ static int mdp5_crtc_cursor_set(struct drm_crtc *crtc, struct drm_device *dev = crtc->dev; struct mdp5_kms *mdp5_kms = get_kms(crtc); struct drm_gem_object *cursor_bo, *old_bo = NULL; - uint32_t blendcfg, cursor_addr, stride; + uint32_t blendcfg, stride; + uint64_t cursor_addr; int ret, lm; enum mdp5_cursor_alpha cur_alpha = CURSOR_ALPHA_PER_PIXEL; uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0); @@ -643,7 +644,7 @@ static void mdp5_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus) { struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc, err); - DBG("%s: error: %08x", mdp5_crtc->name, irqstatus); + DBG("%s: error: %08x", mdp5_crtc->base.name, irqstatus); } static void mdp5_crtc_pp_done_irq(struct mdp_irq *irq, uint32_t irqstatus) @@ -765,9 +766,6 @@ struct drm_crtc *mdp5_crtc_init(struct drm_device *dev, mdp5_crtc->vblank.irq = mdp5_crtc_vblank_irq; mdp5_crtc->err.irq = mdp5_crtc_err_irq; - snprintf(mdp5_crtc->name, sizeof(mdp5_crtc->name), "%s:%d", - pipe2name(mdp5_plane_pipe(plane)), id); - drm_crtc_init_with_planes(dev, crtc, plane, NULL, &mdp5_crtc_funcs, NULL); diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c index 5c5940db898e..3ce8b9dec9c1 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c @@ -41,6 +41,8 @@ static void mdp5_irq_error_handler(struct mdp_irq *irq, uint32_t irqstatus) if (dumpstate && __ratelimit(&rs)) { struct drm_printer p = drm_info_printer(mdp5_kms->dev->dev); drm_state_dump(mdp5_kms->dev, &p); + if (mdp5_kms->smp) + mdp5_smp_dump(mdp5_kms->smp, &p); } } diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c index ed7143d35b25..5f6cd8745dbc 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c @@ -19,6 +19,7 @@ #include <linux/of_irq.h> #include "msm_drv.h" +#include "msm_gem.h" #include "msm_mmu.h" #include "mdp5_kms.h" @@ -71,10 +72,49 @@ static int mdp5_hw_init(struct msm_kms *kms) return 0; } +struct mdp5_state *mdp5_get_state(struct drm_atomic_state *s) +{ + struct msm_drm_private *priv = s->dev->dev_private; + struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); + struct msm_kms_state *state = to_kms_state(s); + struct mdp5_state *new_state; + int ret; + + if (state->state) + return state->state; + + ret = drm_modeset_lock(&mdp5_kms->state_lock, s->acquire_ctx); + if (ret) + return ERR_PTR(ret); + + new_state = kmalloc(sizeof(*mdp5_kms->state), GFP_KERNEL); + if (!new_state) + return ERR_PTR(-ENOMEM); + + /* Copy state: */ + new_state->hwpipe = mdp5_kms->state->hwpipe; + if (mdp5_kms->smp) + new_state->smp = mdp5_kms->state->smp; + + state->state = new_state; + + return new_state; +} + +static void mdp5_swap_state(struct msm_kms *kms, struct drm_atomic_state *state) +{ + struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); + swap(to_kms_state(state)->state, mdp5_kms->state); +} + static void mdp5_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state) { struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); + mdp5_enable(mdp5_kms); + + if (mdp5_kms->smp) + mdp5_smp_prepare_commit(mdp5_kms->smp, &mdp5_kms->state->smp); } static void mdp5_complete_commit(struct msm_kms *kms, struct drm_atomic_state *state) @@ -87,6 +127,9 @@ static void mdp5_complete_commit(struct msm_kms *kms, struct drm_atomic_state *s for_each_plane_in_state(state, plane, plane_state, i) mdp5_plane_complete_commit(plane, plane_state); + if (mdp5_kms->smp) + mdp5_smp_complete_commit(mdp5_kms->smp, &mdp5_kms->state->smp); + mdp5_disable(mdp5_kms); } @@ -117,14 +160,66 @@ static int mdp5_set_split_display(struct msm_kms *kms, static void mdp5_kms_destroy(struct msm_kms *kms) { struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); - struct msm_mmu *mmu = mdp5_kms->mmu; + struct msm_gem_address_space *aspace = mdp5_kms->aspace; + int i; + + for (i = 0; i < mdp5_kms->num_hwpipes; i++) + mdp5_pipe_destroy(mdp5_kms->hwpipes[i]); - if (mmu) { - mmu->funcs->detach(mmu, iommu_ports, ARRAY_SIZE(iommu_ports)); - mmu->funcs->destroy(mmu); + if (aspace) { + aspace->mmu->funcs->detach(aspace->mmu, + iommu_ports, ARRAY_SIZE(iommu_ports)); + msm_gem_address_space_destroy(aspace); } } +#ifdef CONFIG_DEBUG_FS +static int smp_show(struct seq_file *m, void *arg) +{ + struct drm_info_node *node = (struct drm_info_node *) m->private; + struct drm_device *dev = node->minor->dev; + struct msm_drm_private *priv = dev->dev_private; + struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); + struct drm_printer p = drm_seq_file_printer(m); + + if (!mdp5_kms->smp) { + drm_printf(&p, "no SMP pool\n"); + return 0; + } + + mdp5_smp_dump(mdp5_kms->smp, &p); + + return 0; +} + +static struct drm_info_list mdp5_debugfs_list[] = { + {"smp", smp_show }, +}; + +static int mdp5_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor) +{ + struct drm_device *dev = minor->dev; + int ret; + + ret = drm_debugfs_create_files(mdp5_debugfs_list, + ARRAY_SIZE(mdp5_debugfs_list), + minor->debugfs_root, minor); + + if (ret) { + dev_err(dev->dev, "could not install mdp5_debugfs_list\n"); + return ret; + } + + return 0; +} + +static void mdp5_kms_debugfs_cleanup(struct msm_kms *kms, struct drm_minor *minor) +{ + drm_debugfs_remove_files(mdp5_debugfs_list, + ARRAY_SIZE(mdp5_debugfs_list), minor); +} +#endif + static const struct mdp_kms_funcs kms_funcs = { .base = { .hw_init = mdp5_hw_init, @@ -134,6 +229,7 @@ static const struct mdp_kms_funcs kms_funcs = { .irq = mdp5_irq, .enable_vblank = mdp5_enable_vblank, .disable_vblank = mdp5_disable_vblank, + .swap_state = mdp5_swap_state, .prepare_commit = mdp5_prepare_commit, .complete_commit = mdp5_complete_commit, .wait_for_crtc_commit_done = mdp5_wait_for_crtc_commit_done, @@ -141,6 +237,10 @@ static const struct mdp_kms_funcs kms_funcs = { .round_pixclk = mdp5_round_pixclk, .set_split_display = mdp5_set_split_display, .destroy = mdp5_kms_destroy, +#ifdef CONFIG_DEBUG_FS + .debugfs_init = mdp5_kms_debugfs_init, + .debugfs_cleanup = mdp5_kms_debugfs_cleanup, +#endif }, .set_irqmask = mdp5_set_irqmask, }; @@ -321,15 +421,6 @@ static int modeset_init_intf(struct mdp5_kms *mdp5_kms, int intf_num) static int modeset_init(struct mdp5_kms *mdp5_kms) { - static const enum mdp5_pipe crtcs[] = { - SSPP_RGB0, SSPP_RGB1, SSPP_RGB2, SSPP_RGB3, - }; - static const enum mdp5_pipe vig_planes[] = { - SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3, - }; - static const enum mdp5_pipe dma_planes[] = { - SSPP_DMA0, SSPP_DMA1, - }; struct drm_device *dev = mdp5_kms->dev; struct msm_drm_private *priv = dev->dev_private; const struct mdp5_cfg_hw *hw_cfg; @@ -337,58 +428,35 @@ static int modeset_init(struct mdp5_kms *mdp5_kms) hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); - /* construct CRTCs and their private planes: */ - for (i = 0; i < hw_cfg->pipe_rgb.count; i++) { + /* Construct planes equaling the number of hw pipes, and CRTCs + * for the N layer-mixers (LM). The first N planes become primary + * planes for the CRTCs, with the remainder as overlay planes: + */ + for (i = 0; i < mdp5_kms->num_hwpipes; i++) { + bool primary = i < mdp5_cfg->lm.count; struct drm_plane *plane; struct drm_crtc *crtc; - plane = mdp5_plane_init(dev, crtcs[i], true, - hw_cfg->pipe_rgb.base[i], hw_cfg->pipe_rgb.caps); + plane = mdp5_plane_init(dev, primary); if (IS_ERR(plane)) { ret = PTR_ERR(plane); - dev_err(dev->dev, "failed to construct plane for %s (%d)\n", - pipe2name(crtcs[i]), ret); + dev_err(dev->dev, "failed to construct plane %d (%d)\n", i, ret); goto fail; } + priv->planes[priv->num_planes++] = plane; + + if (!primary) + continue; crtc = mdp5_crtc_init(dev, plane, i); if (IS_ERR(crtc)) { ret = PTR_ERR(crtc); - dev_err(dev->dev, "failed to construct crtc for %s (%d)\n", - pipe2name(crtcs[i]), ret); + dev_err(dev->dev, "failed to construct crtc %d (%d)\n", i, ret); goto fail; } priv->crtcs[priv->num_crtcs++] = crtc; } - /* Construct video planes: */ - for (i = 0; i < hw_cfg->pipe_vig.count; i++) { - struct drm_plane *plane; - - plane = mdp5_plane_init(dev, vig_planes[i], false, - hw_cfg->pipe_vig.base[i], hw_cfg->pipe_vig.caps); - if (IS_ERR(plane)) { - ret = PTR_ERR(plane); - dev_err(dev->dev, "failed to construct %s plane: %d\n", - pipe2name(vig_planes[i]), ret); - goto fail; - } - } - - /* DMA planes */ - for (i = 0; i < hw_cfg->pipe_dma.count; i++) { - struct drm_plane *plane; - - plane = mdp5_plane_init(dev, dma_planes[i], false, - hw_cfg->pipe_dma.base[i], hw_cfg->pipe_dma.caps); - if (IS_ERR(plane)) { - ret = PTR_ERR(plane); - dev_err(dev->dev, "failed to construct %s plane: %d\n", - pipe2name(dma_planes[i]), ret); - goto fail; - } - } - /* Construct encoders and modeset initialize connector devices * for each external display interface. */ @@ -564,7 +632,7 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev) struct mdp5_kms *mdp5_kms; struct mdp5_cfg *config; struct msm_kms *kms; - struct msm_mmu *mmu; + struct msm_gem_address_space *aspace; int irq, i, ret; /* priv->kms would have been populated by the MDP5 driver */ @@ -606,30 +674,29 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev) mdelay(16); if (config->platform.iommu) { - mmu = msm_iommu_new(&pdev->dev, config->platform.iommu); - if (IS_ERR(mmu)) { - ret = PTR_ERR(mmu); - dev_err(&pdev->dev, "failed to init iommu: %d\n", ret); - iommu_domain_free(config->platform.iommu); + aspace = msm_gem_address_space_create(&pdev->dev, + config->platform.iommu, "mdp5"); + if (IS_ERR(aspace)) { + ret = PTR_ERR(aspace); goto fail; } - ret = mmu->funcs->attach(mmu, iommu_ports, + mdp5_kms->aspace = aspace; + + ret = aspace->mmu->funcs->attach(aspace->mmu, iommu_ports, ARRAY_SIZE(iommu_ports)); if (ret) { dev_err(&pdev->dev, "failed to attach iommu: %d\n", ret); - mmu->funcs->destroy(mmu); goto fail; } } else { dev_info(&pdev->dev, "no iommu, fallback to phys contig buffers for scanout\n"); - mmu = NULL; + aspace = NULL;; } - mdp5_kms->mmu = mmu; - mdp5_kms->id = msm_register_mmu(dev, mmu); + mdp5_kms->id = msm_register_address_space(dev, aspace); if (mdp5_kms->id < 0) { ret = mdp5_kms->id; dev_err(&pdev->dev, "failed to register mdp5 iommu: %d\n", ret); @@ -644,8 +711,8 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev) dev->mode_config.min_width = 0; dev->mode_config.min_height = 0; - dev->mode_config.max_width = config->hw->lm.max_width; - dev->mode_config.max_height = config->hw->lm.max_height; + dev->mode_config.max_width = 0xffff; + dev->mode_config.max_height = 0xffff; dev->driver->get_vblank_timestamp = mdp5_get_vblank_timestamp; dev->driver->get_scanout_position = mdp5_get_scanoutpos; @@ -673,6 +740,69 @@ static void mdp5_destroy(struct platform_device *pdev) if (mdp5_kms->rpm_enabled) pm_runtime_disable(&pdev->dev); + + kfree(mdp5_kms->state); +} + +static int construct_pipes(struct mdp5_kms *mdp5_kms, int cnt, + const enum mdp5_pipe *pipes, const uint32_t *offsets, + uint32_t caps) +{ + struct drm_device *dev = mdp5_kms->dev; + int i, ret; + + for (i = 0; i < cnt; i++) { + struct mdp5_hw_pipe *hwpipe; + + hwpipe = mdp5_pipe_init(pipes[i], offsets[i], caps); + if (IS_ERR(hwpipe)) { + ret = PTR_ERR(hwpipe); + dev_err(dev->dev, "failed to construct pipe for %s (%d)\n", + pipe2name(pipes[i]), ret); + return ret; + } + hwpipe->idx = mdp5_kms->num_hwpipes; + mdp5_kms->hwpipes[mdp5_kms->num_hwpipes++] = hwpipe; + } + + return 0; +} + +static int hwpipe_init(struct mdp5_kms *mdp5_kms) +{ + static const enum mdp5_pipe rgb_planes[] = { + SSPP_RGB0, SSPP_RGB1, SSPP_RGB2, SSPP_RGB3, + }; + static const enum mdp5_pipe vig_planes[] = { + SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3, + }; + static const enum mdp5_pipe dma_planes[] = { + SSPP_DMA0, SSPP_DMA1, + }; + const struct mdp5_cfg_hw *hw_cfg; + int ret; + + hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); + + /* Construct RGB pipes: */ + ret = construct_pipes(mdp5_kms, hw_cfg->pipe_rgb.count, rgb_planes, + hw_cfg->pipe_rgb.base, hw_cfg->pipe_rgb.caps); + if (ret) + return ret; + + /* Construct video (VIG) pipes: */ + ret = construct_pipes(mdp5_kms, hw_cfg->pipe_vig.count, vig_planes, + hw_cfg->pipe_vig.base, hw_cfg->pipe_vig.caps); + if (ret) + return ret; + + /* Construct DMA pipes: */ + ret = construct_pipes(mdp5_kms, hw_cfg->pipe_dma.count, dma_planes, + hw_cfg->pipe_dma.base, hw_cfg->pipe_dma.caps); + if (ret) + return ret; + + return 0; } static int mdp5_init(struct platform_device *pdev, struct drm_device *dev) @@ -696,6 +826,13 @@ static int mdp5_init(struct platform_device *pdev, struct drm_device *dev) mdp5_kms->dev = dev; mdp5_kms->pdev = pdev; + drm_modeset_lock_init(&mdp5_kms->state_lock); + mdp5_kms->state = kzalloc(sizeof(*mdp5_kms->state), GFP_KERNEL); + if (!mdp5_kms->state) { + ret = -ENOMEM; + goto fail; + } + mdp5_kms->mmio = msm_ioremap(pdev, "mdp_phys", "MDP5"); if (IS_ERR(mdp5_kms->mmio)) { ret = PTR_ERR(mdp5_kms->mmio); @@ -749,7 +886,7 @@ static int mdp5_init(struct platform_device *pdev, struct drm_device *dev) * this section initializes the SMP: */ if (mdp5_kms->caps & MDP_CAP_SMP) { - mdp5_kms->smp = mdp5_smp_init(mdp5_kms->dev, &config->hw->smp); + mdp5_kms->smp = mdp5_smp_init(mdp5_kms, &config->hw->smp); if (IS_ERR(mdp5_kms->smp)) { ret = PTR_ERR(mdp5_kms->smp); mdp5_kms->smp = NULL; @@ -764,6 +901,10 @@ static int mdp5_init(struct platform_device *pdev, struct drm_device *dev) goto fail; } + ret = hwpipe_init(mdp5_kms); + if (ret) + goto fail; + /* set uninit-ed kms */ priv->kms = &mdp5_kms->base.base; diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h index c6fbcfad2d59..17b0cc101171 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h @@ -24,8 +24,11 @@ #include "mdp5_cfg.h" /* must be included before mdp5.xml.h */ #include "mdp5.xml.h" #include "mdp5_ctl.h" +#include "mdp5_pipe.h" #include "mdp5_smp.h" +struct mdp5_state; + struct mdp5_kms { struct mdp_kms base; @@ -33,13 +36,21 @@ struct mdp5_kms { struct platform_device *pdev; + unsigned num_hwpipes; + struct mdp5_hw_pipe *hwpipes[SSPP_MAX]; + struct mdp5_cfg_handler *cfg; uint32_t caps; /* MDP capabilities (MDP_CAP_XXX bits) */ + /** + * Global atomic state. Do not access directly, use mdp5_get_state() + */ + struct mdp5_state *state; + struct drm_modeset_lock state_lock; /* mapper-id used to request GEM buffer mapped for scanout: */ int id; - struct msm_mmu *mmu; + struct msm_gem_address_space *aspace; struct mdp5_smp *smp; struct mdp5_ctl_manager *ctlm; @@ -65,9 +76,27 @@ struct mdp5_kms { }; #define to_mdp5_kms(x) container_of(x, struct mdp5_kms, base) +/* Global atomic state for tracking resources that are shared across + * multiple kms objects (planes/crtcs/etc). + * + * For atomic updates which require modifying global state, + */ +struct mdp5_state { + struct mdp5_hw_pipe_state hwpipe; + struct mdp5_smp_state smp; +}; + +struct mdp5_state *__must_check +mdp5_get_state(struct drm_atomic_state *s); + +/* Atomic plane state. Subclasses the base drm_plane_state in order to + * track assigned hwpipe and hw specific state. + */ struct mdp5_plane_state { struct drm_plane_state base; + struct mdp5_hw_pipe *hwpipe; + /* aligned with property */ uint8_t premultiplied; uint8_t zpos; @@ -76,11 +105,6 @@ struct mdp5_plane_state { /* assigned by crtc blender */ enum mdp_mixer_stage_id stage; - /* some additional transactional status to help us know in the - * apply path whether we need to update SMP allocation, and - * whether current update is still pending: - */ - bool mode_changed : 1; bool pending : 1; }; #define to_mdp5_plane_state(x) \ @@ -208,13 +232,10 @@ int mdp5_irq_domain_init(struct mdp5_kms *mdp5_kms); void mdp5_irq_domain_fini(struct mdp5_kms *mdp5_kms); uint32_t mdp5_plane_get_flush(struct drm_plane *plane); -void mdp5_plane_complete_flip(struct drm_plane *plane); void mdp5_plane_complete_commit(struct drm_plane *plane, struct drm_plane_state *state); enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane); -struct drm_plane *mdp5_plane_init(struct drm_device *dev, - enum mdp5_pipe pipe, bool private_plane, - uint32_t reg_offset, uint32_t caps); +struct drm_plane *mdp5_plane_init(struct drm_device *dev, bool primary); uint32_t mdp5_crtc_vblank(struct drm_crtc *crtc); diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_pipe.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_pipe.c new file mode 100644 index 000000000000..1ae9dc8d260d --- /dev/null +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_pipe.c @@ -0,0 +1,133 @@ +/* + * Copyright (C) 2016 Red Hat + * Author: Rob Clark <robdclark@gmail.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "mdp5_kms.h" + +struct mdp5_hw_pipe *mdp5_pipe_assign(struct drm_atomic_state *s, + struct drm_plane *plane, uint32_t caps, uint32_t blkcfg) +{ + struct msm_drm_private *priv = s->dev->dev_private; + struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); + struct mdp5_state *state; + struct mdp5_hw_pipe_state *old_state, *new_state; + struct mdp5_hw_pipe *hwpipe = NULL; + int i; + + state = mdp5_get_state(s); + if (IS_ERR(state)) + return ERR_CAST(state); + + /* grab old_state after mdp5_get_state(), since now we hold lock: */ + old_state = &mdp5_kms->state->hwpipe; + new_state = &state->hwpipe; + + for (i = 0; i < mdp5_kms->num_hwpipes; i++) { + struct mdp5_hw_pipe *cur = mdp5_kms->hwpipes[i]; + + /* skip if already in-use.. check both new and old state, + * since we cannot immediately re-use a pipe that is + * released in the current update in some cases: + * (1) mdp5 can have SMP (non-double-buffered) + * (2) hw pipe previously assigned to different CRTC + * (vblanks might not be aligned) + */ + if (new_state->hwpipe_to_plane[cur->idx] || + old_state->hwpipe_to_plane[cur->idx]) + continue; + + /* skip if doesn't support some required caps: */ + if (caps & ~cur->caps) + continue; + + /* possible candidate, take the one with the + * fewest unneeded caps bits set: + */ + if (!hwpipe || (hweight_long(cur->caps & ~caps) < + hweight_long(hwpipe->caps & ~caps))) + hwpipe = cur; + } + + if (!hwpipe) + return ERR_PTR(-ENOMEM); + + if (mdp5_kms->smp) { + int ret; + + DBG("%s: alloc SMP blocks", hwpipe->name); + ret = mdp5_smp_assign(mdp5_kms->smp, &state->smp, + hwpipe->pipe, blkcfg); + if (ret) + return ERR_PTR(-ENOMEM); + + hwpipe->blkcfg = blkcfg; + } + + DBG("%s: assign to plane %s for caps %x", + hwpipe->name, plane->name, caps); + new_state->hwpipe_to_plane[hwpipe->idx] = plane; + + return hwpipe; +} + +void mdp5_pipe_release(struct drm_atomic_state *s, struct mdp5_hw_pipe *hwpipe) +{ + struct msm_drm_private *priv = s->dev->dev_private; + struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); + struct mdp5_state *state = mdp5_get_state(s); + struct mdp5_hw_pipe_state *new_state = &state->hwpipe; + + if (!hwpipe) + return; + + if (WARN_ON(!new_state->hwpipe_to_plane[hwpipe->idx])) + return; + + DBG("%s: release from plane %s", hwpipe->name, + new_state->hwpipe_to_plane[hwpipe->idx]->name); + + if (mdp5_kms->smp) { + DBG("%s: free SMP blocks", hwpipe->name); + mdp5_smp_release(mdp5_kms->smp, &state->smp, hwpipe->pipe); + } + + new_state->hwpipe_to_plane[hwpipe->idx] = NULL; +} + +void mdp5_pipe_destroy(struct mdp5_hw_pipe *hwpipe) +{ + kfree(hwpipe); +} + +struct mdp5_hw_pipe *mdp5_pipe_init(enum mdp5_pipe pipe, + uint32_t reg_offset, uint32_t caps) +{ + struct mdp5_hw_pipe *hwpipe; + + hwpipe = kzalloc(sizeof(*hwpipe), GFP_KERNEL); + if (!hwpipe) + return ERR_PTR(-ENOMEM); + + hwpipe->name = pipe2name(pipe); + hwpipe->pipe = pipe; + hwpipe->reg_offset = reg_offset; + hwpipe->caps = caps; + hwpipe->flush_mask = mdp_ctl_flush_mask_pipe(pipe); + + spin_lock_init(&hwpipe->pipe_lock); + + return hwpipe; +} diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_pipe.h b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_pipe.h new file mode 100644 index 000000000000..611da7a660c9 --- /dev/null +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_pipe.h @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2016 Red Hat + * Author: Rob Clark <robdclark@gmail.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __MDP5_PIPE_H__ +#define __MDP5_PIPE_H__ + +#define SSPP_MAX (SSPP_RGB3 + 1) /* TODO: Add SSPP_MAX in mdp5.xml.h */ + +/* represents a hw pipe, which is dynamically assigned to a plane */ +struct mdp5_hw_pipe { + int idx; + + const char *name; + enum mdp5_pipe pipe; + + spinlock_t pipe_lock; /* protect REG_MDP5_PIPE_* registers */ + uint32_t reg_offset; + uint32_t caps; + + uint32_t flush_mask; /* used to commit pipe registers */ + + /* number of smp blocks per plane, ie: + * nblks_y | (nblks_u << 8) | (nblks_v << 16) + */ + uint32_t blkcfg; +}; + +/* global atomic state of assignment between pipes and planes: */ +struct mdp5_hw_pipe_state { + struct drm_plane *hwpipe_to_plane[SSPP_MAX]; +}; + +struct mdp5_hw_pipe *__must_check +mdp5_pipe_assign(struct drm_atomic_state *s, struct drm_plane *plane, + uint32_t caps, uint32_t blkcfg); +void mdp5_pipe_release(struct drm_atomic_state *s, struct mdp5_hw_pipe *hwpipe); + +struct mdp5_hw_pipe *mdp5_pipe_init(enum mdp5_pipe pipe, + uint32_t reg_offset, uint32_t caps); +void mdp5_pipe_destroy(struct mdp5_hw_pipe *hwpipe); + +#endif /* __MDP5_PIPE_H__ */ diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c index 8bf55e3450c5..c099da7bc212 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c @@ -21,15 +21,6 @@ struct mdp5_plane { struct drm_plane base; - const char *name; - - enum mdp5_pipe pipe; - - spinlock_t pipe_lock; /* protect REG_MDP5_PIPE_* registers */ - uint32_t reg_offset; - uint32_t caps; - - uint32_t flush_mask; /* used to commit pipe registers */ uint32_t nformats; uint32_t formats[32]; @@ -70,12 +61,6 @@ static void mdp5_plane_destroy(struct drm_plane *plane) static void mdp5_plane_install_rotation_property(struct drm_device *dev, struct drm_plane *plane) { - struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane); - - if (!(mdp5_plane->caps & MDP_PIPE_CAP_HFLIP) && - !(mdp5_plane->caps & MDP_PIPE_CAP_VFLIP)) - return; - drm_plane_create_rotation_property(plane, DRM_ROTATE_0, DRM_ROTATE_0 | @@ -188,11 +173,12 @@ mdp5_plane_atomic_print_state(struct drm_printer *p, { struct mdp5_plane_state *pstate = to_mdp5_plane_state(state); + drm_printf(p, "\thwpipe=%s\n", pstate->hwpipe ? + pstate->hwpipe->name : "(null)"); drm_printf(p, "\tpremultiplied=%u\n", pstate->premultiplied); drm_printf(p, "\tzpos=%u\n", pstate->zpos); drm_printf(p, "\talpha=%u\n", pstate->alpha); drm_printf(p, "\tstage=%s\n", stage2name(pstate->stage)); - drm_printf(p, "\tmode_changed=%u\n", pstate->mode_changed); drm_printf(p, "\tpending=%u\n", pstate->pending); } @@ -234,7 +220,6 @@ mdp5_plane_duplicate_state(struct drm_plane *plane) if (mdp5_state && mdp5_state->base.fb) drm_framebuffer_reference(mdp5_state->base.fb); - mdp5_state->mode_changed = false; mdp5_state->pending = false; return &mdp5_state->base; @@ -243,10 +228,12 @@ mdp5_plane_duplicate_state(struct drm_plane *plane) static void mdp5_plane_destroy_state(struct drm_plane *plane, struct drm_plane_state *state) { + struct mdp5_plane_state *pstate = to_mdp5_plane_state(state); + if (state->fb) drm_framebuffer_unreference(state->fb); - kfree(to_mdp5_plane_state(state)); + kfree(pstate); } static const struct drm_plane_funcs mdp5_plane_funcs = { @@ -265,104 +252,115 @@ static const struct drm_plane_funcs mdp5_plane_funcs = { static int mdp5_plane_prepare_fb(struct drm_plane *plane, struct drm_plane_state *new_state) { - struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane); struct mdp5_kms *mdp5_kms = get_kms(plane); struct drm_framebuffer *fb = new_state->fb; if (!new_state->fb) return 0; - DBG("%s: prepare: FB[%u]", mdp5_plane->name, fb->base.id); + DBG("%s: prepare: FB[%u]", plane->name, fb->base.id); return msm_framebuffer_prepare(fb, mdp5_kms->id); } static void mdp5_plane_cleanup_fb(struct drm_plane *plane, struct drm_plane_state *old_state) { - struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane); struct mdp5_kms *mdp5_kms = get_kms(plane); struct drm_framebuffer *fb = old_state->fb; if (!fb) return; - DBG("%s: cleanup: FB[%u]", mdp5_plane->name, fb->base.id); + DBG("%s: cleanup: FB[%u]", plane->name, fb->base.id); msm_framebuffer_cleanup(fb, mdp5_kms->id); } static int mdp5_plane_atomic_check(struct drm_plane *plane, struct drm_plane_state *state) { - struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane); + struct mdp5_plane_state *mdp5_state = to_mdp5_plane_state(state); struct drm_plane_state *old_state = plane->state; - const struct mdp_format *format; - bool vflip, hflip; + struct mdp5_cfg *config = mdp5_cfg_get_config(get_kms(plane)->cfg); + bool new_hwpipe = false; + uint32_t max_width, max_height; + uint32_t caps = 0; - DBG("%s: check (%d -> %d)", mdp5_plane->name, + DBG("%s: check (%d -> %d)", plane->name, plane_enabled(old_state), plane_enabled(state)); + /* We don't allow faster-than-vblank updates.. if we did add this + * some day, we would need to disallow in cases where hwpipe + * changes + */ + if (WARN_ON(to_mdp5_plane_state(old_state)->pending)) + return -EBUSY; + + max_width = config->hw->lm.max_width << 16; + max_height = config->hw->lm.max_height << 16; + + /* Make sure source dimensions are within bounds. */ + if ((state->src_w > max_width) || (state->src_h > max_height)) { + struct drm_rect src = drm_plane_state_src(state); + DBG("Invalid source size "DRM_RECT_FP_FMT, + DRM_RECT_FP_ARG(&src)); + return -ERANGE; + } + if (plane_enabled(state)) { unsigned int rotation; + const struct mdp_format *format; + struct mdp5_kms *mdp5_kms = get_kms(plane); + uint32_t blkcfg = 0; format = to_mdp_format(msm_framebuffer_format(state->fb)); - if (MDP_FORMAT_IS_YUV(format) && - !pipe_supports_yuv(mdp5_plane->caps)) { - dev_err(plane->dev->dev, - "Pipe doesn't support YUV\n"); - - return -EINVAL; - } - - if (!(mdp5_plane->caps & MDP_PIPE_CAP_SCALE) && - (((state->src_w >> 16) != state->crtc_w) || - ((state->src_h >> 16) != state->crtc_h))) { - dev_err(plane->dev->dev, - "Pipe doesn't support scaling (%dx%d -> %dx%d)\n", - state->src_w >> 16, state->src_h >> 16, - state->crtc_w, state->crtc_h); + if (MDP_FORMAT_IS_YUV(format)) + caps |= MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC; - return -EINVAL; - } + if (((state->src_w >> 16) != state->crtc_w) || + ((state->src_h >> 16) != state->crtc_h)) + caps |= MDP_PIPE_CAP_SCALE; rotation = drm_rotation_simplify(state->rotation, DRM_ROTATE_0 | DRM_REFLECT_X | DRM_REFLECT_Y); - hflip = !!(rotation & DRM_REFLECT_X); - vflip = !!(rotation & DRM_REFLECT_Y); - if ((vflip && !(mdp5_plane->caps & MDP_PIPE_CAP_VFLIP)) || - (hflip && !(mdp5_plane->caps & MDP_PIPE_CAP_HFLIP))) { - dev_err(plane->dev->dev, - "Pipe doesn't support flip\n"); + if (rotation & DRM_REFLECT_X) + caps |= MDP_PIPE_CAP_HFLIP; - return -EINVAL; - } - } + if (rotation & DRM_REFLECT_Y) + caps |= MDP_PIPE_CAP_VFLIP; - if (plane_enabled(state) && plane_enabled(old_state)) { - /* we cannot change SMP block configuration during scanout: */ - bool full_modeset = false; - if (state->fb->pixel_format != old_state->fb->pixel_format) { - DBG("%s: pixel_format change!", mdp5_plane->name); - full_modeset = true; - } - if (state->src_w != old_state->src_w) { - DBG("%s: src_w change!", mdp5_plane->name); - full_modeset = true; - } - if (to_mdp5_plane_state(old_state)->pending) { - DBG("%s: still pending!", mdp5_plane->name); - full_modeset = true; + /* (re)allocate hw pipe if we don't have one or caps-mismatch: */ + if (!mdp5_state->hwpipe || (caps & ~mdp5_state->hwpipe->caps)) + new_hwpipe = true; + + if (mdp5_kms->smp) { + const struct mdp_format *format = + to_mdp_format(msm_framebuffer_format(state->fb)); + + blkcfg = mdp5_smp_calculate(mdp5_kms->smp, format, + state->src_w >> 16, false); + + if (mdp5_state->hwpipe && (mdp5_state->hwpipe->blkcfg != blkcfg)) + new_hwpipe = true; } - if (full_modeset) { - struct drm_crtc_state *crtc_state = - drm_atomic_get_crtc_state(state->state, state->crtc); - crtc_state->mode_changed = true; - to_mdp5_plane_state(state)->mode_changed = true; + + /* (re)assign hwpipe if needed, otherwise keep old one: */ + if (new_hwpipe) { + /* TODO maybe we want to re-assign hwpipe sometimes + * in cases when we no-longer need some caps to make + * it available for other planes? + */ + struct mdp5_hw_pipe *old_hwpipe = mdp5_state->hwpipe; + mdp5_state->hwpipe = mdp5_pipe_assign(state->state, + plane, caps, blkcfg); + if (IS_ERR(mdp5_state->hwpipe)) { + DBG("%s: failed to assign hwpipe!", plane->name); + return PTR_ERR(mdp5_state->hwpipe); + } + mdp5_pipe_release(state->state, old_hwpipe); } - } else { - to_mdp5_plane_state(state)->mode_changed = true; } return 0; @@ -371,16 +369,16 @@ static int mdp5_plane_atomic_check(struct drm_plane *plane, static void mdp5_plane_atomic_update(struct drm_plane *plane, struct drm_plane_state *old_state) { - struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane); struct drm_plane_state *state = plane->state; + struct mdp5_plane_state *mdp5_state = to_mdp5_plane_state(state); + + DBG("%s: update", plane->name); - DBG("%s: update", mdp5_plane->name); + mdp5_state->pending = true; - if (!plane_enabled(state)) { - to_mdp5_plane_state(state)->pending = true; - } else if (to_mdp5_plane_state(state)->mode_changed) { + if (plane_enabled(state)) { int ret; - to_mdp5_plane_state(state)->pending = true; + ret = mdp5_plane_mode_set(plane, state->crtc, state->fb, state->crtc_x, state->crtc_y, @@ -389,11 +387,6 @@ static void mdp5_plane_atomic_update(struct drm_plane *plane, state->src_w, state->src_h); /* atomic_check should have ensured that this doesn't fail */ WARN_ON(ret < 0); - } else { - unsigned long flags; - spin_lock_irqsave(&mdp5_plane->pipe_lock, flags); - set_scanout_locked(plane, state->fb); - spin_unlock_irqrestore(&mdp5_plane->pipe_lock, flags); } } @@ -407,9 +400,9 @@ static const struct drm_plane_helper_funcs mdp5_plane_helper_funcs = { static void set_scanout_locked(struct drm_plane *plane, struct drm_framebuffer *fb) { - struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane); struct mdp5_kms *mdp5_kms = get_kms(plane); - enum mdp5_pipe pipe = mdp5_plane->pipe; + struct mdp5_hw_pipe *hwpipe = to_mdp5_plane_state(plane->state)->hwpipe; + enum mdp5_pipe pipe = hwpipe->pipe; mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_A(pipe), MDP5_PIPE_SRC_STRIDE_A_P0(fb->pitches[0]) | @@ -689,14 +682,14 @@ static int mdp5_plane_mode_set(struct drm_plane *plane, uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h) { - struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane); struct drm_plane_state *pstate = plane->state; + struct mdp5_hw_pipe *hwpipe = to_mdp5_plane_state(pstate)->hwpipe; struct mdp5_kms *mdp5_kms = get_kms(plane); - enum mdp5_pipe pipe = mdp5_plane->pipe; + enum mdp5_pipe pipe = hwpipe->pipe; const struct mdp_format *format; uint32_t nplanes, config = 0; uint32_t phasex_step[COMP_MAX] = {0,}, phasey_step[COMP_MAX] = {0,}; - bool pe = mdp5_plane->caps & MDP_PIPE_CAP_SW_PIX_EXT; + bool pe = hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT; int pe_left[COMP_MAX], pe_right[COMP_MAX]; int pe_top[COMP_MAX], pe_bottom[COMP_MAX]; uint32_t hdecm = 0, vdecm = 0; @@ -721,27 +714,10 @@ static int mdp5_plane_mode_set(struct drm_plane *plane, src_w = src_w >> 16; src_h = src_h >> 16; - DBG("%s: FB[%u] %u,%u,%u,%u -> CRTC[%u] %d,%d,%u,%u", mdp5_plane->name, + DBG("%s: FB[%u] %u,%u,%u,%u -> CRTC[%u] %d,%d,%u,%u", plane->name, fb->base.id, src_x, src_y, src_w, src_h, crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h); - /* Request some memory from the SMP: */ - if (mdp5_kms->smp) { - ret = mdp5_smp_request(mdp5_kms->smp, - mdp5_plane->pipe, format, src_w, false); - if (ret) - return ret; - } - - /* - * Currently we update the hw for allocations/requests immediately, - * but once atomic modeset/pageflip is in place, the allocation - * would move into atomic->check_plane_state(), while updating the - * hw would remain here: - */ - if (mdp5_kms->smp) - mdp5_smp_configure(mdp5_kms->smp, pipe); - ret = calc_scalex_steps(plane, pix_format, src_w, crtc_w, phasex_step); if (ret) return ret; @@ -750,7 +726,7 @@ static int mdp5_plane_mode_set(struct drm_plane *plane, if (ret) return ret; - if (mdp5_plane->caps & MDP_PIPE_CAP_SW_PIX_EXT) { + if (hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT) { calc_pixel_ext(format, src_w, crtc_w, phasex_step, pe_left, pe_right, true); calc_pixel_ext(format, src_h, crtc_h, phasey_step, @@ -771,11 +747,11 @@ static int mdp5_plane_mode_set(struct drm_plane *plane, hflip = !!(rotation & DRM_REFLECT_X); vflip = !!(rotation & DRM_REFLECT_Y); - spin_lock_irqsave(&mdp5_plane->pipe_lock, flags); + spin_lock_irqsave(&hwpipe->pipe_lock, flags); mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_IMG_SIZE(pipe), - MDP5_PIPE_SRC_IMG_SIZE_WIDTH(fb->width) | - MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(fb->height)); + MDP5_PIPE_SRC_IMG_SIZE_WIDTH(min(fb->width, src_w)) | + MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(min(fb->height, src_h))); mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_SIZE(pipe), MDP5_PIPE_SRC_SIZE_WIDTH(src_w) | @@ -820,12 +796,12 @@ static int mdp5_plane_mode_set(struct drm_plane *plane, /* not using secure mode: */ mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(pipe), 0); - if (mdp5_plane->caps & MDP_PIPE_CAP_SW_PIX_EXT) + if (hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT) mdp5_write_pixel_ext(mdp5_kms, pipe, format, src_w, pe_left, pe_right, src_h, pe_top, pe_bottom); - if (mdp5_plane->caps & MDP_PIPE_CAP_SCALE) { + if (hwpipe->caps & MDP_PIPE_CAP_SCALE) { mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_X(pipe), phasex_step[COMP_0]); mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(pipe), @@ -840,7 +816,7 @@ static int mdp5_plane_mode_set(struct drm_plane *plane, mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CONFIG(pipe), config); } - if (mdp5_plane->caps & MDP_PIPE_CAP_CSC) { + if (hwpipe->caps & MDP_PIPE_CAP_CSC) { if (MDP_FORMAT_IS_YUV(format)) csc_enable(mdp5_kms, pipe, mdp_get_default_csc_cfg(CSC_YUV2RGB)); @@ -850,56 +826,42 @@ static int mdp5_plane_mode_set(struct drm_plane *plane, set_scanout_locked(plane, fb); - spin_unlock_irqrestore(&mdp5_plane->pipe_lock, flags); + spin_unlock_irqrestore(&hwpipe->pipe_lock, flags); return ret; } -void mdp5_plane_complete_flip(struct drm_plane *plane) +enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane) { - struct mdp5_kms *mdp5_kms = get_kms(plane); - struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane); - enum mdp5_pipe pipe = mdp5_plane->pipe; - - DBG("%s: complete flip", mdp5_plane->name); + struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state); - if (mdp5_kms->smp) - mdp5_smp_commit(mdp5_kms->smp, pipe); + if (WARN_ON(!pstate->hwpipe)) + return 0; - to_mdp5_plane_state(plane->state)->pending = false; -} - -enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane) -{ - struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane); - return mdp5_plane->pipe; + return pstate->hwpipe->pipe; } uint32_t mdp5_plane_get_flush(struct drm_plane *plane) { - struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane); + struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state); - return mdp5_plane->flush_mask; + if (WARN_ON(!pstate->hwpipe)) + return 0; + + return pstate->hwpipe->flush_mask; } /* called after vsync in thread context */ void mdp5_plane_complete_commit(struct drm_plane *plane, struct drm_plane_state *state) { - struct mdp5_kms *mdp5_kms = get_kms(plane); - struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane); - enum mdp5_pipe pipe = mdp5_plane->pipe; + struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state); - if (!plane_enabled(plane->state) && mdp5_kms->smp) { - DBG("%s: free SMP", mdp5_plane->name); - mdp5_smp_release(mdp5_kms->smp, pipe); - } + pstate->pending = false; } /* initialize plane */ -struct drm_plane *mdp5_plane_init(struct drm_device *dev, - enum mdp5_pipe pipe, bool private_plane, uint32_t reg_offset, - uint32_t caps) +struct drm_plane *mdp5_plane_init(struct drm_device *dev, bool primary) { struct drm_plane *plane = NULL; struct mdp5_plane *mdp5_plane; @@ -914,22 +876,13 @@ struct drm_plane *mdp5_plane_init(struct drm_device *dev, plane = &mdp5_plane->base; - mdp5_plane->pipe = pipe; - mdp5_plane->name = pipe2name(pipe); - mdp5_plane->caps = caps; - mdp5_plane->nformats = mdp_get_formats(mdp5_plane->formats, - ARRAY_SIZE(mdp5_plane->formats), - !pipe_supports_yuv(mdp5_plane->caps)); - - mdp5_plane->flush_mask = mdp_ctl_flush_mask_pipe(pipe); - mdp5_plane->reg_offset = reg_offset; - spin_lock_init(&mdp5_plane->pipe_lock); + ARRAY_SIZE(mdp5_plane->formats), false); - type = private_plane ? DRM_PLANE_TYPE_PRIMARY : DRM_PLANE_TYPE_OVERLAY; + type = primary ? DRM_PLANE_TYPE_PRIMARY : DRM_PLANE_TYPE_OVERLAY; ret = drm_universal_plane_init(dev, plane, 0xff, &mdp5_plane_funcs, mdp5_plane->formats, mdp5_plane->nformats, - type, "%s", mdp5_plane->name); + type, NULL); if (ret) goto fail; diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c index 27d7b55b52c9..58f712d37e7f 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c @@ -21,72 +21,6 @@ #include "mdp5_smp.h" -/* SMP - Shared Memory Pool - * - * These are shared between all the clients, where each plane in a - * scanout buffer is a SMP client. Ie. scanout of 3 plane I420 on - * pipe VIG0 => 3 clients: VIG0_Y, VIG0_CB, VIG0_CR. - * - * Based on the size of the attached scanout buffer, a certain # of - * blocks must be allocated to that client out of the shared pool. - * - * In some hw, some blocks are statically allocated for certain pipes - * and CANNOT be re-allocated (eg: MMB0 and MMB1 both tied to RGB0). - * - * For each block that can be dynamically allocated, it can be either - * free: - * The block is free. - * - * pending: - * The block is allocated to some client and not free. - * - * configured: - * The block is allocated to some client, and assigned to that - * client in MDP5_SMP_ALLOC registers. - * - * inuse: - * The block is being actively used by a client. - * - * The updates happen in the following steps: - * - * 1) mdp5_smp_request(): - * When plane scanout is setup, calculate required number of - * blocks needed per client, and request. Blocks neither inuse nor - * configured nor pending by any other client are added to client's - * pending set. - * For shrinking, blocks in pending but not in configured can be freed - * directly, but those already in configured will be freed later by - * mdp5_smp_commit. - * - * 2) mdp5_smp_configure(): - * As hw is programmed, before FLUSH, MDP5_SMP_ALLOC registers - * are configured for the union(pending, inuse) - * Current pending is copied to configured. - * It is assumed that mdp5_smp_request and mdp5_smp_configure not run - * concurrently for the same pipe. - * - * 3) mdp5_smp_commit(): - * After next vblank, copy configured -> inuse. Optionally update - * MDP5_SMP_ALLOC registers if there are newly unused blocks - * - * 4) mdp5_smp_release(): - * Must be called after the pipe is disabled and no longer uses any SMB - * - * On the next vblank after changes have been committed to hw, the - * client's pending blocks become it's in-use blocks (and no-longer - * in-use blocks become available to other clients). - * - * btw, hurray for confusing overloaded acronyms! :-/ - * - * NOTE: for atomic modeset/pageflip NONBLOCK operations, step #1 - * should happen at (or before)? atomic->check(). And we'd need - * an API to discard previous requests if update is aborted or - * (test-only). - * - * TODO would perhaps be nice to have debugfs to dump out kernel - * inuse and pending state of all clients.. - */ - struct mdp5_smp { struct drm_device *dev; @@ -94,16 +28,8 @@ struct mdp5_smp { int blk_cnt; int blk_size; - - spinlock_t state_lock; - mdp5_smp_state_t state; /* to track smp allocation amongst pipes: */ - - struct mdp5_client_smp_state client_state[MAX_CLIENTS]; }; -static void update_smp_state(struct mdp5_smp *smp, - u32 cid, mdp5_smp_state_t *assigned); - static inline struct mdp5_kms *get_kms(struct mdp5_smp *smp) { @@ -134,57 +60,38 @@ static inline u32 pipe2client(enum mdp5_pipe pipe, int plane) return mdp5_cfg->smp.clients[pipe] + plane; } -/* step #1: update # of blocks pending for the client: */ +/* allocate blocks for the specified request: */ static int smp_request_block(struct mdp5_smp *smp, + struct mdp5_smp_state *state, u32 cid, int nblks) { - struct mdp5_kms *mdp5_kms = get_kms(smp); - struct mdp5_client_smp_state *ps = &smp->client_state[cid]; - int i, ret, avail, cur_nblks, cnt = smp->blk_cnt; + void *cs = state->client_state[cid]; + int i, avail, cnt = smp->blk_cnt; uint8_t reserved; - unsigned long flags; - reserved = smp->reserved[cid]; + /* we shouldn't be requesting blocks for an in-use client: */ + WARN_ON(bitmap_weight(cs, cnt) > 0); - spin_lock_irqsave(&smp->state_lock, flags); + reserved = smp->reserved[cid]; if (reserved) { nblks = max(0, nblks - reserved); DBG("%d MMBs allocated (%d reserved)", nblks, reserved); } - avail = cnt - bitmap_weight(smp->state, cnt); + avail = cnt - bitmap_weight(state->state, cnt); if (nblks > avail) { - dev_err(mdp5_kms->dev->dev, "out of blks (req=%d > avail=%d)\n", + dev_err(smp->dev->dev, "out of blks (req=%d > avail=%d)\n", nblks, avail); - ret = -ENOSPC; - goto fail; + return -ENOSPC; } - cur_nblks = bitmap_weight(ps->pending, cnt); - if (nblks > cur_nblks) { - /* grow the existing pending reservation: */ - for (i = cur_nblks; i < nblks; i++) { - int blk = find_first_zero_bit(smp->state, cnt); - set_bit(blk, ps->pending); - set_bit(blk, smp->state); - } - } else { - /* shrink the existing pending reservation: */ - for (i = cur_nblks; i > nblks; i--) { - int blk = find_first_bit(ps->pending, cnt); - clear_bit(blk, ps->pending); - - /* clear in global smp_state if not in configured - * otherwise until _commit() - */ - if (!test_bit(blk, ps->configured)) - clear_bit(blk, smp->state); - } + for (i = 0; i < nblks; i++) { + int blk = find_first_zero_bit(state->state, cnt); + set_bit(blk, cs); + set_bit(blk, state->state); } -fail: - spin_unlock_irqrestore(&smp->state_lock, flags); return 0; } @@ -209,14 +116,15 @@ static void set_fifo_thresholds(struct mdp5_smp *smp, * decimated width. Ie. SMP buffering sits downstream of decimation (which * presumably happens during the dma from scanout buffer). */ -int mdp5_smp_request(struct mdp5_smp *smp, enum mdp5_pipe pipe, - const struct mdp_format *format, u32 width, bool hdecim) +uint32_t mdp5_smp_calculate(struct mdp5_smp *smp, + const struct mdp_format *format, + u32 width, bool hdecim) { struct mdp5_kms *mdp5_kms = get_kms(smp); - struct drm_device *dev = mdp5_kms->dev; int rev = mdp5_cfg_get_hw_rev(mdp5_kms->cfg); - int i, hsub, nplanes, nlines, nblks, ret; + int i, hsub, nplanes, nlines; u32 fmt = format->base.pixel_format; + uint32_t blkcfg = 0; nplanes = drm_format_num_planes(fmt); hsub = drm_format_horz_chroma_subsampling(fmt); @@ -239,7 +147,7 @@ int mdp5_smp_request(struct mdp5_smp *smp, enum mdp5_pipe pipe, hsub = 1; } - for (i = 0, nblks = 0; i < nplanes; i++) { + for (i = 0; i < nplanes; i++) { int n, fetch_stride, cpp; cpp = drm_format_plane_cpp(fmt, i); @@ -251,60 +159,72 @@ int mdp5_smp_request(struct mdp5_smp *smp, enum mdp5_pipe pipe, if (rev == 0) n = roundup_pow_of_two(n); + blkcfg |= (n << (8 * i)); + } + + return blkcfg; +} + +int mdp5_smp_assign(struct mdp5_smp *smp, struct mdp5_smp_state *state, + enum mdp5_pipe pipe, uint32_t blkcfg) +{ + struct mdp5_kms *mdp5_kms = get_kms(smp); + struct drm_device *dev = mdp5_kms->dev; + int i, ret; + + for (i = 0; i < pipe2nclients(pipe); i++) { + u32 cid = pipe2client(pipe, i); + int n = blkcfg & 0xff; + + if (!n) + continue; + DBG("%s[%d]: request %d SMP blocks", pipe2name(pipe), i, n); - ret = smp_request_block(smp, pipe2client(pipe, i), n); + ret = smp_request_block(smp, state, cid, n); if (ret) { dev_err(dev->dev, "Cannot allocate %d SMP blocks: %d\n", n, ret); return ret; } - nblks += n; + blkcfg >>= 8; } - set_fifo_thresholds(smp, pipe, nblks); + state->assigned |= (1 << pipe); return 0; } /* Release SMP blocks for all clients of the pipe */ -void mdp5_smp_release(struct mdp5_smp *smp, enum mdp5_pipe pipe) +void mdp5_smp_release(struct mdp5_smp *smp, struct mdp5_smp_state *state, + enum mdp5_pipe pipe) { int i; - unsigned long flags; int cnt = smp->blk_cnt; for (i = 0; i < pipe2nclients(pipe); i++) { - mdp5_smp_state_t assigned; u32 cid = pipe2client(pipe, i); - struct mdp5_client_smp_state *ps = &smp->client_state[cid]; - - spin_lock_irqsave(&smp->state_lock, flags); - - /* clear hw assignment */ - bitmap_or(assigned, ps->inuse, ps->configured, cnt); - update_smp_state(smp, CID_UNUSED, &assigned); - - /* free to global pool */ - bitmap_andnot(smp->state, smp->state, ps->pending, cnt); - bitmap_andnot(smp->state, smp->state, assigned, cnt); + void *cs = state->client_state[cid]; - /* clear client's infor */ - bitmap_zero(ps->pending, cnt); - bitmap_zero(ps->configured, cnt); - bitmap_zero(ps->inuse, cnt); + /* update global state: */ + bitmap_andnot(state->state, state->state, cs, cnt); - spin_unlock_irqrestore(&smp->state_lock, flags); + /* clear client's state */ + bitmap_zero(cs, cnt); } - set_fifo_thresholds(smp, pipe, 0); + state->released |= (1 << pipe); } -static void update_smp_state(struct mdp5_smp *smp, +/* NOTE: SMP_ALLOC_* regs are *not* double buffered, so release has to + * happen after scanout completes. + */ +static unsigned update_smp_state(struct mdp5_smp *smp, u32 cid, mdp5_smp_state_t *assigned) { struct mdp5_kms *mdp5_kms = get_kms(smp); int cnt = smp->blk_cnt; + unsigned nblks = 0; u32 blk, val; for_each_set_bit(blk, *assigned, cnt) { @@ -330,62 +250,88 @@ static void update_smp_state(struct mdp5_smp *smp, mdp5_write(mdp5_kms, REG_MDP5_SMP_ALLOC_W_REG(idx), val); mdp5_write(mdp5_kms, REG_MDP5_SMP_ALLOC_R_REG(idx), val); + + nblks++; } + + return nblks; } -/* step #2: configure hw for union(pending, inuse): */ -void mdp5_smp_configure(struct mdp5_smp *smp, enum mdp5_pipe pipe) +void mdp5_smp_prepare_commit(struct mdp5_smp *smp, struct mdp5_smp_state *state) { - int cnt = smp->blk_cnt; - mdp5_smp_state_t assigned; - int i; + enum mdp5_pipe pipe; - for (i = 0; i < pipe2nclients(pipe); i++) { - u32 cid = pipe2client(pipe, i); - struct mdp5_client_smp_state *ps = &smp->client_state[cid]; + for_each_set_bit(pipe, &state->assigned, sizeof(state->assigned) * 8) { + unsigned i, nblks = 0; - /* - * if vblank has not happened since last smp_configure - * skip the configure for now - */ - if (!bitmap_equal(ps->inuse, ps->configured, cnt)) - continue; + for (i = 0; i < pipe2nclients(pipe); i++) { + u32 cid = pipe2client(pipe, i); + void *cs = state->client_state[cid]; - bitmap_copy(ps->configured, ps->pending, cnt); - bitmap_or(assigned, ps->inuse, ps->configured, cnt); - update_smp_state(smp, cid, &assigned); + nblks += update_smp_state(smp, cid, cs); + + DBG("assign %s:%u, %u blks", + pipe2name(pipe), i, nblks); + } + + set_fifo_thresholds(smp, pipe, nblks); } + + state->assigned = 0; } -/* step #3: after vblank, copy configured -> inuse: */ -void mdp5_smp_commit(struct mdp5_smp *smp, enum mdp5_pipe pipe) +void mdp5_smp_complete_commit(struct mdp5_smp *smp, struct mdp5_smp_state *state) { - int cnt = smp->blk_cnt; - mdp5_smp_state_t released; - int i; - - for (i = 0; i < pipe2nclients(pipe); i++) { - u32 cid = pipe2client(pipe, i); - struct mdp5_client_smp_state *ps = &smp->client_state[cid]; + enum mdp5_pipe pipe; - /* - * Figure out if there are any blocks we where previously - * using, which can be released and made available to other - * clients: - */ - if (bitmap_andnot(released, ps->inuse, ps->configured, cnt)) { - unsigned long flags; + for_each_set_bit(pipe, &state->released, sizeof(state->released) * 8) { + DBG("release %s", pipe2name(pipe)); + set_fifo_thresholds(smp, pipe, 0); + } - spin_lock_irqsave(&smp->state_lock, flags); - /* clear released blocks: */ - bitmap_andnot(smp->state, smp->state, released, cnt); - spin_unlock_irqrestore(&smp->state_lock, flags); + state->released = 0; +} - update_smp_state(smp, CID_UNUSED, &released); +void mdp5_smp_dump(struct mdp5_smp *smp, struct drm_printer *p) +{ + struct mdp5_kms *mdp5_kms = get_kms(smp); + struct mdp5_hw_pipe_state *hwpstate; + struct mdp5_smp_state *state; + int total = 0, i, j; + + drm_printf(p, "name\tinuse\tplane\n"); + drm_printf(p, "----\t-----\t-----\n"); + + if (drm_can_sleep()) + drm_modeset_lock(&mdp5_kms->state_lock, NULL); + + /* grab these *after* we hold the state_lock */ + hwpstate = &mdp5_kms->state->hwpipe; + state = &mdp5_kms->state->smp; + + for (i = 0; i < mdp5_kms->num_hwpipes; i++) { + struct mdp5_hw_pipe *hwpipe = mdp5_kms->hwpipes[i]; + struct drm_plane *plane = hwpstate->hwpipe_to_plane[hwpipe->idx]; + enum mdp5_pipe pipe = hwpipe->pipe; + for (j = 0; j < pipe2nclients(pipe); j++) { + u32 cid = pipe2client(pipe, j); + void *cs = state->client_state[cid]; + int inuse = bitmap_weight(cs, smp->blk_cnt); + + drm_printf(p, "%s:%d\t%d\t%s\n", + pipe2name(pipe), j, inuse, + plane ? plane->name : NULL); + + total += inuse; } - - bitmap_copy(ps->inuse, ps->configured, cnt); } + + drm_printf(p, "TOTAL:\t%d\t(of %d)\n", total, smp->blk_cnt); + drm_printf(p, "AVAIL:\t%d\n", smp->blk_cnt - + bitmap_weight(state->state, smp->blk_cnt)); + + if (drm_can_sleep()) + drm_modeset_unlock(&mdp5_kms->state_lock); } void mdp5_smp_destroy(struct mdp5_smp *smp) @@ -393,8 +339,9 @@ void mdp5_smp_destroy(struct mdp5_smp *smp) kfree(smp); } -struct mdp5_smp *mdp5_smp_init(struct drm_device *dev, const struct mdp5_smp_block *cfg) +struct mdp5_smp *mdp5_smp_init(struct mdp5_kms *mdp5_kms, const struct mdp5_smp_block *cfg) { + struct mdp5_smp_state *state = &mdp5_kms->state->smp; struct mdp5_smp *smp = NULL; int ret; @@ -404,14 +351,13 @@ struct mdp5_smp *mdp5_smp_init(struct drm_device *dev, const struct mdp5_smp_blo goto fail; } - smp->dev = dev; + smp->dev = mdp5_kms->dev; smp->blk_cnt = cfg->mmb_count; smp->blk_size = cfg->mmb_size; /* statically tied MMBs cannot be re-allocated: */ - bitmap_copy(smp->state, cfg->reserved_state, smp->blk_cnt); + bitmap_copy(state->state, cfg->reserved_state, smp->blk_cnt); memcpy(smp->reserved, cfg->reserved, sizeof(smp->reserved)); - spin_lock_init(&smp->state_lock); return smp; fail: diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.h b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.h index 20b87e800ea3..b41d0448fbe8 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.h +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.h @@ -19,12 +19,53 @@ #ifndef __MDP5_SMP_H__ #define __MDP5_SMP_H__ +#include <drm/drm_print.h> + #include "msm_drv.h" -struct mdp5_client_smp_state { - mdp5_smp_state_t inuse; - mdp5_smp_state_t configured; - mdp5_smp_state_t pending; +/* + * SMP - Shared Memory Pool: + * + * SMP blocks are shared between all the clients, where each plane in + * a scanout buffer is a SMP client. Ie. scanout of 3 plane I420 on + * pipe VIG0 => 3 clients: VIG0_Y, VIG0_CB, VIG0_CR. + * + * Based on the size of the attached scanout buffer, a certain # of + * blocks must be allocated to that client out of the shared pool. + * + * In some hw, some blocks are statically allocated for certain pipes + * and CANNOT be re-allocated (eg: MMB0 and MMB1 both tied to RGB0). + * + * + * Atomic SMP State: + * + * On atomic updates that modify SMP configuration, the state is cloned + * (copied) and modified. For test-only, or in cases where atomic + * update fails (or if we hit ww_mutex deadlock/backoff condition) the + * new state is simply thrown away. + * + * Because the SMP registers are not double buffered, updates are a + * two step process: + * + * 1) in _prepare_commit() we configure things (via read-modify-write) + * for the newly assigned pipes, so we don't take away blocks + * assigned to pipes that are still scanning out + * 2) in _complete_commit(), after vblank/etc, we clear things for the + * released clients, since at that point old pipes are no longer + * scanning out. + */ +struct mdp5_smp_state { + /* global state of what blocks are in use: */ + mdp5_smp_state_t state; + + /* per client state of what blocks they are using: */ + mdp5_smp_state_t client_state[MAX_CLIENTS]; + + /* assigned pipes (hw updated at _prepare_commit()): */ + unsigned long assigned; + + /* released pipes (hw updated at _complete_commit()): */ + unsigned long released; }; struct mdp5_kms; @@ -36,13 +77,22 @@ struct mdp5_smp; * which is then used to call the other mdp5_smp_*(handler, ...) functions. */ -struct mdp5_smp *mdp5_smp_init(struct drm_device *dev, const struct mdp5_smp_block *cfg); +struct mdp5_smp *mdp5_smp_init(struct mdp5_kms *mdp5_kms, + const struct mdp5_smp_block *cfg); void mdp5_smp_destroy(struct mdp5_smp *smp); -int mdp5_smp_request(struct mdp5_smp *smp, enum mdp5_pipe pipe, - const struct mdp_format *format, u32 width, bool hdecim); -void mdp5_smp_configure(struct mdp5_smp *smp, enum mdp5_pipe pipe); -void mdp5_smp_commit(struct mdp5_smp *smp, enum mdp5_pipe pipe); -void mdp5_smp_release(struct mdp5_smp *smp, enum mdp5_pipe pipe); +void mdp5_smp_dump(struct mdp5_smp *smp, struct drm_printer *p); + +uint32_t mdp5_smp_calculate(struct mdp5_smp *smp, + const struct mdp_format *format, + u32 width, bool hdecim); + +int mdp5_smp_assign(struct mdp5_smp *smp, struct mdp5_smp_state *state, + enum mdp5_pipe pipe, uint32_t blkcfg); +void mdp5_smp_release(struct mdp5_smp *smp, struct mdp5_smp_state *state, + enum mdp5_pipe pipe); + +void mdp5_smp_prepare_commit(struct mdp5_smp *smp, struct mdp5_smp_state *state); +void mdp5_smp_complete_commit(struct mdp5_smp *smp, struct mdp5_smp_state *state); #endif /* __MDP5_SMP_H__ */ diff --git a/drivers/gpu/drm/msm/mdp/mdp_common.xml.h b/drivers/gpu/drm/msm/mdp/mdp_common.xml.h index 452e3518f98b..8994c365e218 100644 --- a/drivers/gpu/drm/msm/mdp/mdp_common.xml.h +++ b/drivers/gpu/drm/msm/mdp/mdp_common.xml.h @@ -12,7 +12,7 @@ The rules-ng-ng source files this header was generated from are: - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36965 bytes, from 2016-11-26 23:01:08) - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52) - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02) - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14) diff --git a/drivers/gpu/drm/msm/msm_atomic.c b/drivers/gpu/drm/msm/msm_atomic.c index 4e21e1d72378..30b5d23e53b4 100644 --- a/drivers/gpu/drm/msm/msm_atomic.c +++ b/drivers/gpu/drm/msm/msm_atomic.c @@ -241,6 +241,10 @@ int msm_atomic_commit(struct drm_device *dev, drm_atomic_helper_swap_state(state, true); + /* swap driver private state while still holding state_lock */ + if (to_kms_state(state)->state) + priv->kms->funcs->swap_state(priv->kms, state); + /* * Everything below can be run asynchronously without the need to grab * any modeset locks at all under one conditions: It must be guaranteed @@ -271,3 +275,30 @@ error: drm_atomic_helper_cleanup_planes(dev, state); return ret; } + +struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev) +{ + struct msm_kms_state *state = kzalloc(sizeof(*state), GFP_KERNEL); + + if (!state || drm_atomic_state_init(dev, &state->base) < 0) { + kfree(state); + return NULL; + } + + return &state->base; +} + +void msm_atomic_state_clear(struct drm_atomic_state *s) +{ + struct msm_kms_state *state = to_kms_state(s); + drm_atomic_state_default_clear(&state->base); + kfree(state->state); + state->state = NULL; +} + +void msm_atomic_state_free(struct drm_atomic_state *state) +{ + kfree(to_kms_state(state)->state); + drm_atomic_state_default_release(state); + kfree(state); +} diff --git a/drivers/gpu/drm/msm/msm_debugfs.c b/drivers/gpu/drm/msm/msm_debugfs.c index 3c853733c99a..c1b40f5adb60 100644 --- a/drivers/gpu/drm/msm/msm_debugfs.c +++ b/drivers/gpu/drm/msm/msm_debugfs.c @@ -18,6 +18,7 @@ #ifdef CONFIG_DEBUG_FS #include "msm_drv.h" #include "msm_gpu.h" +#include "msm_kms.h" #include "msm_debugfs.h" static int msm_gpu_show(struct drm_device *dev, struct seq_file *m) @@ -142,6 +143,7 @@ int msm_debugfs_late_init(struct drm_device *dev) int msm_debugfs_init(struct drm_minor *minor) { struct drm_device *dev = minor->dev; + struct msm_drm_private *priv = dev->dev_private; int ret; ret = drm_debugfs_create_files(msm_debugfs_list, @@ -153,15 +155,25 @@ int msm_debugfs_init(struct drm_minor *minor) return ret; } - return 0; + if (priv->kms->funcs->debugfs_init) + ret = priv->kms->funcs->debugfs_init(priv->kms, minor); + + return ret; } void msm_debugfs_cleanup(struct drm_minor *minor) { + struct drm_device *dev = minor->dev; + struct msm_drm_private *priv = dev->dev_private; + drm_debugfs_remove_files(msm_debugfs_list, ARRAY_SIZE(msm_debugfs_list), minor); - if (!minor->dev->dev_private) + if (!priv) return; + + if (priv->kms->funcs->debugfs_cleanup) + priv->kms->funcs->debugfs_cleanup(priv->kms, minor); + msm_rd_debugfs_cleanup(minor); msm_perf_debugfs_cleanup(minor); } diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 8d21fb27a401..e29bb66f55b1 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -46,17 +46,21 @@ static const struct drm_mode_config_funcs mode_config_funcs = { .output_poll_changed = msm_fb_output_poll_changed, .atomic_check = msm_atomic_check, .atomic_commit = msm_atomic_commit, + .atomic_state_alloc = msm_atomic_state_alloc, + .atomic_state_clear = msm_atomic_state_clear, + .atomic_state_free = msm_atomic_state_free, }; -int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu) +int msm_register_address_space(struct drm_device *dev, + struct msm_gem_address_space *aspace) { struct msm_drm_private *priv = dev->dev_private; - int idx = priv->num_mmus++; + int idx = priv->num_aspaces++; - if (WARN_ON(idx >= ARRAY_SIZE(priv->mmus))) + if (WARN_ON(idx >= ARRAY_SIZE(priv->aspace))) return -EINVAL; - priv->mmus[idx] = mmu; + priv->aspace[idx] = aspace; return idx; } @@ -234,7 +238,7 @@ static int msm_drm_uninit(struct device *dev) flush_workqueue(priv->atomic_wq); destroy_workqueue(priv->atomic_wq); - if (kms) + if (kms && kms->funcs) kms->funcs->destroy(kms); if (gpu) { @@ -907,10 +911,8 @@ static int add_components_mdp(struct device *mdp_dev, * remote-endpoint isn't a component that we need to add */ if (of_device_is_compatible(np, "qcom,mdp4") && - ep.port == 0) { - of_node_put(ep_node); + ep.port == 0) continue; - } /* * It's okay if some of the ports don't have a remote endpoint @@ -918,15 +920,12 @@ static int add_components_mdp(struct device *mdp_dev, * any external interface. */ intf = of_graph_get_remote_port_parent(ep_node); - if (!intf) { - of_node_put(ep_node); + if (!intf) continue; - } drm_of_component_match_add(master_dev, matchptr, compare_of, intf); of_node_put(intf); - of_node_put(ep_node); } return 0; @@ -1039,7 +1038,13 @@ static int msm_pdev_probe(struct platform_device *pdev) if (ret) return ret; - pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); + /* on all devices that I am aware of, iommu's which can map + * any address the cpu can see are used: + */ + ret = dma_set_mask_and_coherent(&pdev->dev, ~0); + if (ret) + return ret; + return component_master_add_with_match(&pdev->dev, &msm_drm_ops, match); } diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 940bf4992fe2..ed4dad3ca133 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -52,6 +52,8 @@ struct msm_perf_state; struct msm_gem_submit; struct msm_fence_context; struct msm_fence_cb; +struct msm_gem_address_space; +struct msm_gem_vma; #define NUM_DOMAINS 2 /* one for KMS, then one per gpu core (?) */ @@ -121,12 +123,16 @@ struct msm_drm_private { uint32_t pending_crtcs; wait_queue_head_t pending_crtcs_event; - /* registered MMUs: */ - unsigned int num_mmus; - struct msm_mmu *mmus[NUM_DOMAINS]; + /* Registered address spaces.. currently this is fixed per # of + * iommu's. Ie. one for display block and one for gpu block. + * Eventually, to do per-process gpu pagetables, we'll want one + * of these per-process. + */ + unsigned int num_aspaces; + struct msm_gem_address_space *aspace[NUM_DOMAINS]; unsigned int num_planes; - struct drm_plane *planes[8]; + struct drm_plane *planes[16]; unsigned int num_crtcs; struct drm_crtc *crtcs[8]; @@ -173,8 +179,22 @@ int msm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state); int msm_atomic_commit(struct drm_device *dev, struct drm_atomic_state *state, bool nonblock); +struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev); +void msm_atomic_state_clear(struct drm_atomic_state *state); +void msm_atomic_state_free(struct drm_atomic_state *state); + +int msm_register_address_space(struct drm_device *dev, + struct msm_gem_address_space *aspace); + +void msm_gem_unmap_vma(struct msm_gem_address_space *aspace, + struct msm_gem_vma *vma, struct sg_table *sgt); +int msm_gem_map_vma(struct msm_gem_address_space *aspace, + struct msm_gem_vma *vma, struct sg_table *sgt, int npages); -int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu); +void msm_gem_address_space_destroy(struct msm_gem_address_space *aspace); +struct msm_gem_address_space * +msm_gem_address_space_create(struct device *dev, struct iommu_domain *domain, + const char *name); void msm_gem_submit_free(struct msm_gem_submit *submit); int msm_ioctl_gem_submit(struct drm_device *dev, void *data, @@ -189,9 +209,9 @@ int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma); int msm_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj); int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id, - uint32_t *iova); -int msm_gem_get_iova(struct drm_gem_object *obj, int id, uint32_t *iova); -uint32_t msm_gem_iova(struct drm_gem_object *obj, int id); + uint64_t *iova); +int msm_gem_get_iova(struct drm_gem_object *obj, int id, uint64_t *iova); +uint64_t msm_gem_iova(struct drm_gem_object *obj, int id); struct page **msm_gem_get_pages(struct drm_gem_object *obj); void msm_gem_put_pages(struct drm_gem_object *obj); void msm_gem_put_iova(struct drm_gem_object *obj, int id); @@ -303,8 +323,8 @@ void __iomem *msm_ioremap(struct platform_device *pdev, const char *name, void msm_writel(u32 data, void __iomem *addr); u32 msm_readl(const void __iomem *addr); -#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) -#define VERB(fmt, ...) if (0) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) +#define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) +#define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) static inline int align_pitch(int width, int bpp) { diff --git a/drivers/gpu/drm/msm/msm_fb.c b/drivers/gpu/drm/msm/msm_fb.c index 95cf8fe72ee5..9acf544e7a8f 100644 --- a/drivers/gpu/drm/msm/msm_fb.c +++ b/drivers/gpu/drm/msm/msm_fb.c @@ -88,11 +88,11 @@ int msm_framebuffer_prepare(struct drm_framebuffer *fb, int id) { struct msm_framebuffer *msm_fb = to_msm_framebuffer(fb); int ret, i, n = drm_format_num_planes(fb->pixel_format); - uint32_t iova; + uint64_t iova; for (i = 0; i < n; i++) { ret = msm_gem_get_iova(msm_fb->planes[i], id, &iova); - DBG("FB[%u]: iova[%d]: %08x (%d)", fb->base.id, i, iova, ret); + DBG("FB[%u]: iova[%d]: %08llx (%d)", fb->base.id, i, iova, ret); if (ret) return ret; } diff --git a/drivers/gpu/drm/msm/msm_fbdev.c b/drivers/gpu/drm/msm/msm_fbdev.c index d29f5e82a410..bffe93498512 100644 --- a/drivers/gpu/drm/msm/msm_fbdev.c +++ b/drivers/gpu/drm/msm/msm_fbdev.c @@ -76,7 +76,7 @@ static int msm_fbdev_create(struct drm_fb_helper *helper, struct drm_framebuffer *fb = NULL; struct fb_info *fbi = NULL; struct drm_mode_fb_cmd2 mode_cmd = {0}; - uint32_t paddr; + uint64_t paddr; int ret, size; DBG("create fbdev: %dx%d@%d (%dx%d)", sizes->surface_width, diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c index 57db7dbbb618..cd06cfd94687 100644 --- a/drivers/gpu/drm/msm/msm_gem.c +++ b/drivers/gpu/drm/msm/msm_gem.c @@ -296,12 +296,8 @@ put_iova(struct drm_gem_object *obj) WARN_ON(!mutex_is_locked(&dev->struct_mutex)); for (id = 0; id < ARRAY_SIZE(msm_obj->domain); id++) { - struct msm_mmu *mmu = priv->mmus[id]; - if (mmu && msm_obj->domain[id].iova) { - uint32_t offset = msm_obj->domain[id].iova; - mmu->funcs->unmap(mmu, offset, msm_obj->sgt, obj->size); - msm_obj->domain[id].iova = 0; - } + msm_gem_unmap_vma(priv->aspace[id], + &msm_obj->domain[id], msm_obj->sgt); } } @@ -313,7 +309,7 @@ put_iova(struct drm_gem_object *obj) * the refcnt counter needs to be atomic_t. */ int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id, - uint32_t *iova) + uint64_t *iova) { struct msm_gem_object *msm_obj = to_msm_bo(obj); int ret = 0; @@ -326,16 +322,8 @@ int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id, return PTR_ERR(pages); if (iommu_present(&platform_bus_type)) { - struct msm_mmu *mmu = priv->mmus[id]; - uint32_t offset; - - if (WARN_ON(!mmu)) - return -EINVAL; - - offset = (uint32_t)mmap_offset(obj); - ret = mmu->funcs->map(mmu, offset, msm_obj->sgt, - obj->size, IOMMU_READ | IOMMU_WRITE); - msm_obj->domain[id].iova = offset; + ret = msm_gem_map_vma(priv->aspace[id], &msm_obj->domain[id], + msm_obj->sgt, obj->size >> PAGE_SHIFT); } else { msm_obj->domain[id].iova = physaddr(obj); } @@ -348,7 +336,7 @@ int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id, } /* get iova, taking a reference. Should have a matching put */ -int msm_gem_get_iova(struct drm_gem_object *obj, int id, uint32_t *iova) +int msm_gem_get_iova(struct drm_gem_object *obj, int id, uint64_t *iova) { struct msm_gem_object *msm_obj = to_msm_bo(obj); int ret; @@ -370,7 +358,7 @@ int msm_gem_get_iova(struct drm_gem_object *obj, int id, uint32_t *iova) /* get iova without taking a reference, used in places where you have * already done a 'msm_gem_get_iova()'. */ -uint32_t msm_gem_iova(struct drm_gem_object *obj, int id) +uint64_t msm_gem_iova(struct drm_gem_object *obj, int id) { struct msm_gem_object *msm_obj = to_msm_bo(obj); WARN_ON(!msm_obj->domain[id].iova); @@ -631,9 +619,11 @@ void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m) struct msm_gem_object *msm_obj = to_msm_bo(obj); struct reservation_object *robj = msm_obj->resv; struct reservation_object_list *fobj; + struct msm_drm_private *priv = obj->dev->dev_private; struct dma_fence *fence; uint64_t off = drm_vma_node_start(&obj->vma_node); const char *madv; + unsigned id; WARN_ON(!mutex_is_locked(&obj->dev->struct_mutex)); @@ -650,10 +640,15 @@ void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m) break; } - seq_printf(m, "%08x: %c %2d (%2d) %08llx %p %zu%s\n", + seq_printf(m, "%08x: %c %2d (%2d) %08llx %p\t", msm_obj->flags, is_active(msm_obj) ? 'A' : 'I', obj->name, obj->refcount.refcount.counter, - off, msm_obj->vaddr, obj->size, madv); + off, msm_obj->vaddr); + + for (id = 0; id < priv->num_aspaces; id++) + seq_printf(m, " %08llx", msm_obj->domain[id].iova); + + seq_printf(m, " %zu%s\n", obj->size, madv); rcu_read_lock(); fobj = rcu_dereference(robj->fence); @@ -761,7 +756,6 @@ static int msm_gem_new_impl(struct drm_device *dev, { struct msm_drm_private *priv = dev->dev_private; struct msm_gem_object *msm_obj; - unsigned sz; bool use_vram = false; switch (flags & MSM_BO_CACHE_MASK) { @@ -783,16 +777,12 @@ static int msm_gem_new_impl(struct drm_device *dev, if (WARN_ON(use_vram && !priv->vram.size)) return -EINVAL; - sz = sizeof(*msm_obj); - if (use_vram) - sz += sizeof(struct drm_mm_node); - - msm_obj = kzalloc(sz, GFP_KERNEL); + msm_obj = kzalloc(sizeof(*msm_obj), GFP_KERNEL); if (!msm_obj) return -ENOMEM; if (use_vram) - msm_obj->vram_node = (void *)&msm_obj[1]; + msm_obj->vram_node = &msm_obj->domain[0].node; msm_obj->flags = flags; msm_obj->madv = MSM_MADV_WILLNEED; diff --git a/drivers/gpu/drm/msm/msm_gem.h b/drivers/gpu/drm/msm/msm_gem.h index 2cb8551fda70..7d529516b332 100644 --- a/drivers/gpu/drm/msm/msm_gem.h +++ b/drivers/gpu/drm/msm/msm_gem.h @@ -24,6 +24,20 @@ /* Additional internal-use only BO flags: */ #define MSM_BO_STOLEN 0x10000000 /* try to use stolen/splash memory */ +struct msm_gem_address_space { + const char *name; + /* NOTE: mm managed at the page level, size is in # of pages + * and position mm_node->start is in # of pages: + */ + struct drm_mm mm; + struct msm_mmu *mmu; +}; + +struct msm_gem_vma { + struct drm_mm_node node; + uint64_t iova; +}; + struct msm_gem_object { struct drm_gem_object base; @@ -61,10 +75,7 @@ struct msm_gem_object { struct sg_table *sgt; void *vaddr; - struct { - // XXX - uint32_t iova; - } domain[NUM_DOMAINS]; + struct msm_gem_vma domain[NUM_DOMAINS]; /* normally (resv == &_resv) except for imported bo's */ struct reservation_object *resv; @@ -112,13 +123,13 @@ struct msm_gem_submit { struct { uint32_t type; uint32_t size; /* in dwords */ - uint32_t iova; + uint64_t iova; uint32_t idx; /* cmdstream buffer idx in bos[] */ } *cmd; /* array of size nr_cmds */ struct { uint32_t flags; struct msm_gem_object *obj; - uint32_t iova; + uint64_t iova; } bos[0]; }; diff --git a/drivers/gpu/drm/msm/msm_gem_shrinker.c b/drivers/gpu/drm/msm/msm_gem_shrinker.c index 283d2841ba58..192b2d3a79cb 100644 --- a/drivers/gpu/drm/msm/msm_gem_shrinker.c +++ b/drivers/gpu/drm/msm/msm_gem_shrinker.c @@ -163,6 +163,9 @@ void msm_gem_shrinker_init(struct drm_device *dev) void msm_gem_shrinker_cleanup(struct drm_device *dev) { struct msm_drm_private *priv = dev->dev_private; - WARN_ON(unregister_vmap_purge_notifier(&priv->vmap_notifier)); - unregister_shrinker(&priv->shrinker); + + if (priv->shrinker.nr_deferred) { + WARN_ON(unregister_vmap_purge_notifier(&priv->vmap_notifier)); + unregister_shrinker(&priv->shrinker); + } } diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c b/drivers/gpu/drm/msm/msm_gem_submit.c index 25e8786fa4ca..166e84e4f0d4 100644 --- a/drivers/gpu/drm/msm/msm_gem_submit.c +++ b/drivers/gpu/drm/msm/msm_gem_submit.c @@ -241,7 +241,7 @@ static int submit_pin_objects(struct msm_gem_submit *submit) for (i = 0; i < submit->nr_bos; i++) { struct msm_gem_object *msm_obj = submit->bos[i].obj; - uint32_t iova; + uint64_t iova; /* if locking succeeded, pin bo: */ ret = msm_gem_get_iova_locked(&msm_obj->base, @@ -266,7 +266,7 @@ static int submit_pin_objects(struct msm_gem_submit *submit) } static int submit_bo(struct msm_gem_submit *submit, uint32_t idx, - struct msm_gem_object **obj, uint32_t *iova, bool *valid) + struct msm_gem_object **obj, uint64_t *iova, bool *valid) { if (idx >= submit->nr_bos) { DRM_ERROR("invalid buffer index: %u (out of %u)\n", @@ -312,7 +312,8 @@ static int submit_reloc(struct msm_gem_submit *submit, struct msm_gem_object *ob struct drm_msm_gem_submit_reloc submit_reloc; void __user *userptr = u64_to_user_ptr(relocs + (i * sizeof(submit_reloc))); - uint32_t iova, off; + uint32_t off; + uint64_t iova; bool valid; ret = copy_from_user(&submit_reloc, userptr, sizeof(submit_reloc)); @@ -461,7 +462,7 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data, void __user *userptr = u64_to_user_ptr(args->cmds + (i * sizeof(submit_cmd))); struct msm_gem_object *msm_obj; - uint32_t iova; + uint64_t iova; ret = copy_from_user(&submit_cmd, userptr, sizeof(submit_cmd)); if (ret) { diff --git a/drivers/gpu/drm/msm/msm_gem_vma.c b/drivers/gpu/drm/msm/msm_gem_vma.c new file mode 100644 index 000000000000..a311d26ccb21 --- /dev/null +++ b/drivers/gpu/drm/msm/msm_gem_vma.c @@ -0,0 +1,90 @@ +/* + * Copyright (C) 2016 Red Hat + * Author: Rob Clark <robdclark@gmail.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "msm_drv.h" +#include "msm_gem.h" +#include "msm_mmu.h" + +void +msm_gem_unmap_vma(struct msm_gem_address_space *aspace, + struct msm_gem_vma *vma, struct sg_table *sgt) +{ + if (!vma->iova) + return; + + if (aspace->mmu) { + unsigned size = vma->node.size << PAGE_SHIFT; + aspace->mmu->funcs->unmap(aspace->mmu, vma->iova, sgt, size); + } + + drm_mm_remove_node(&vma->node); + + vma->iova = 0; +} + +int +msm_gem_map_vma(struct msm_gem_address_space *aspace, + struct msm_gem_vma *vma, struct sg_table *sgt, int npages) +{ + int ret; + + if (WARN_ON(drm_mm_node_allocated(&vma->node))) + return 0; + + ret = drm_mm_insert_node(&aspace->mm, &vma->node, npages, + 0, DRM_MM_SEARCH_DEFAULT); + if (ret) + return ret; + + vma->iova = vma->node.start << PAGE_SHIFT; + + if (aspace->mmu) { + unsigned size = npages << PAGE_SHIFT; + ret = aspace->mmu->funcs->map(aspace->mmu, vma->iova, sgt, + size, IOMMU_READ | IOMMU_WRITE); + } + + return ret; +} + +void +msm_gem_address_space_destroy(struct msm_gem_address_space *aspace) +{ + drm_mm_takedown(&aspace->mm); + if (aspace->mmu) + aspace->mmu->funcs->destroy(aspace->mmu); + kfree(aspace); +} + +struct msm_gem_address_space * +msm_gem_address_space_create(struct device *dev, struct iommu_domain *domain, + const char *name) +{ + struct msm_gem_address_space *aspace; + + aspace = kzalloc(sizeof(*aspace), GFP_KERNEL); + if (!aspace) + return ERR_PTR(-ENOMEM); + + aspace->name = name; + aspace->mmu = msm_iommu_new(dev, domain); + + drm_mm_init(&aspace->mm, (domain->geometry.aperture_start >> PAGE_SHIFT), + (domain->geometry.aperture_end >> PAGE_SHIFT) - 1); + + return aspace; +} diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index 3249707e6834..b28527a65d09 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -91,21 +91,20 @@ static int disable_pwrrail(struct msm_gpu *gpu) static int enable_clk(struct msm_gpu *gpu) { - struct clk *rate_clk = NULL; int i; - /* NOTE: kgsl_pwrctrl_clk() ignores grp_clks[0].. */ - for (i = ARRAY_SIZE(gpu->grp_clks) - 1; i > 0; i--) { - if (gpu->grp_clks[i]) { - clk_prepare(gpu->grp_clks[i]); - rate_clk = gpu->grp_clks[i]; - } - } + if (gpu->grp_clks[0] && gpu->fast_rate) + clk_set_rate(gpu->grp_clks[0], gpu->fast_rate); - if (rate_clk && gpu->fast_rate) - clk_set_rate(rate_clk, gpu->fast_rate); + /* Set the RBBM timer rate to 19.2Mhz */ + if (gpu->grp_clks[2]) + clk_set_rate(gpu->grp_clks[2], 19200000); - for (i = ARRAY_SIZE(gpu->grp_clks) - 1; i > 0; i--) + for (i = ARRAY_SIZE(gpu->grp_clks) - 1; i >= 0; i--) + if (gpu->grp_clks[i]) + clk_prepare(gpu->grp_clks[i]); + + for (i = ARRAY_SIZE(gpu->grp_clks) - 1; i >= 0; i--) if (gpu->grp_clks[i]) clk_enable(gpu->grp_clks[i]); @@ -114,24 +113,22 @@ static int enable_clk(struct msm_gpu *gpu) static int disable_clk(struct msm_gpu *gpu) { - struct clk *rate_clk = NULL; int i; - /* NOTE: kgsl_pwrctrl_clk() ignores grp_clks[0].. */ - for (i = ARRAY_SIZE(gpu->grp_clks) - 1; i > 0; i--) { - if (gpu->grp_clks[i]) { + for (i = ARRAY_SIZE(gpu->grp_clks) - 1; i >= 0; i--) + if (gpu->grp_clks[i]) clk_disable(gpu->grp_clks[i]); - rate_clk = gpu->grp_clks[i]; - } - } - - if (rate_clk && gpu->slow_rate) - clk_set_rate(rate_clk, gpu->slow_rate); - for (i = ARRAY_SIZE(gpu->grp_clks) - 1; i > 0; i--) + for (i = ARRAY_SIZE(gpu->grp_clks) - 1; i >= 0; i--) if (gpu->grp_clks[i]) clk_unprepare(gpu->grp_clks[i]); + if (gpu->grp_clks[0] && gpu->slow_rate) + clk_set_rate(gpu->grp_clks[0], gpu->slow_rate); + + if (gpu->grp_clks[2]) + clk_set_rate(gpu->grp_clks[2], 0); + return 0; } @@ -528,7 +525,7 @@ void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, for (i = 0; i < submit->nr_bos; i++) { struct msm_gem_object *msm_obj = submit->bos[i].obj; - uint32_t iova; + uint64_t iova; /* can't happen yet.. but when we add 2d support we'll have * to deal w/ cross-ring synchronization: @@ -563,8 +560,8 @@ static irqreturn_t irq_handler(int irq, void *data) } static const char *clk_names[] = { - "src_clk", "core_clk", "iface_clk", "mem_clk", "mem_iface_clk", - "alt_mem_iface_clk", + "core_clk", "iface_clk", "rbbmtimer_clk", "mem_clk", + "mem_iface_clk", "alt_mem_iface_clk", }; int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, @@ -656,12 +653,17 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, */ iommu = iommu_domain_alloc(&platform_bus_type); if (iommu) { + /* TODO 32b vs 64b address space.. */ + iommu->geometry.aperture_start = SZ_16M; + iommu->geometry.aperture_end = 0xffffffff; + dev_info(drm->dev, "%s: using IOMMU\n", name); - gpu->mmu = msm_iommu_new(&pdev->dev, iommu); - if (IS_ERR(gpu->mmu)) { - ret = PTR_ERR(gpu->mmu); + gpu->aspace = msm_gem_address_space_create(&pdev->dev, + iommu, "gpu"); + if (IS_ERR(gpu->aspace)) { + ret = PTR_ERR(gpu->aspace); dev_err(drm->dev, "failed to init iommu: %d\n", ret); - gpu->mmu = NULL; + gpu->aspace = NULL; iommu_domain_free(iommu); goto fail; } @@ -669,7 +671,7 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, } else { dev_info(drm->dev, "%s: no IOMMU, fallback to VRAM carveout!\n", name); } - gpu->id = msm_register_mmu(drm, gpu->mmu); + gpu->id = msm_register_address_space(drm, gpu->aspace); /* Create ringbuffer: */ @@ -705,8 +707,8 @@ void msm_gpu_cleanup(struct msm_gpu *gpu) msm_ringbuffer_destroy(gpu->rb); } - if (gpu->mmu) - gpu->mmu->funcs->destroy(gpu->mmu); + if (gpu->aspace) + msm_gem_address_space_destroy(gpu->aspace); if (gpu->fctx) msm_fence_context_free(gpu->fctx); diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index d61d98a6e047..c4c39d3272c7 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -50,7 +50,7 @@ struct msm_gpu_funcs { void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit, struct msm_file_private *ctx); void (*flush)(struct msm_gpu *gpu); - void (*idle)(struct msm_gpu *gpu); + bool (*idle)(struct msm_gpu *gpu); irqreturn_t (*irq)(struct msm_gpu *irq); uint32_t (*last_fence)(struct msm_gpu *gpu); void (*recover)(struct msm_gpu *gpu); @@ -80,7 +80,7 @@ struct msm_gpu { /* ringbuffer: */ struct msm_ringbuffer *rb; - uint32_t rb_iova; + uint64_t rb_iova; /* list of GEM active objects: */ struct list_head active_list; @@ -98,7 +98,7 @@ struct msm_gpu { void __iomem *mmio; int irq; - struct msm_mmu *mmu; + struct msm_gem_address_space *aspace; int id; /* Power Control: */ @@ -154,6 +154,45 @@ static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg) return msm_readl(gpu->mmio + (reg << 2)); } +static inline void gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or) +{ + uint32_t val = gpu_read(gpu, reg); + + val &= ~mask; + gpu_write(gpu, reg, val | or); +} + +static inline u64 gpu_read64(struct msm_gpu *gpu, u32 lo, u32 hi) +{ + u64 val; + + /* + * Why not a readq here? Two reasons: 1) many of the LO registers are + * not quad word aligned and 2) the GPU hardware designers have a bit + * of a history of putting registers where they fit, especially in + * spins. The longer a GPU family goes the higher the chance that + * we'll get burned. We could do a series of validity checks if we + * wanted to, but really is a readq() that much better? Nah. + */ + + /* + * For some lo/hi registers (like perfcounters), the hi value is latched + * when the lo is read, so make sure to read the lo first to trigger + * that + */ + val = (u64) msm_readl(gpu->mmio + (lo << 2)); + val |= ((u64) msm_readl(gpu->mmio + (hi << 2)) << 32); + + return val; +} + +static inline void gpu_write64(struct msm_gpu *gpu, u32 lo, u32 hi, u64 val) +{ + /* Why not a writeq here? Read the screed above */ + msm_writel(lower_32_bits(val), gpu->mmio + (lo << 2)); + msm_writel(upper_32_bits(val), gpu->mmio + (hi << 2)); +} + int msm_gpu_pm_suspend(struct msm_gpu *gpu); int msm_gpu_pm_resume(struct msm_gpu *gpu); diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c index 3a294d0da3a0..61aaaa1de6eb 100644 --- a/drivers/gpu/drm/msm/msm_iommu.c +++ b/drivers/gpu/drm/msm/msm_iommu.c @@ -45,13 +45,13 @@ static void msm_iommu_detach(struct msm_mmu *mmu, const char * const *names, iommu_detach_device(iommu->domain, mmu->dev); } -static int msm_iommu_map(struct msm_mmu *mmu, uint32_t iova, +static int msm_iommu_map(struct msm_mmu *mmu, uint64_t iova, struct sg_table *sgt, unsigned len, int prot) { struct msm_iommu *iommu = to_msm_iommu(mmu); struct iommu_domain *domain = iommu->domain; struct scatterlist *sg; - unsigned int da = iova; + unsigned long da = iova; unsigned int i, j; int ret; @@ -62,7 +62,7 @@ static int msm_iommu_map(struct msm_mmu *mmu, uint32_t iova, dma_addr_t pa = sg_phys(sg) - sg->offset; size_t bytes = sg->length + sg->offset; - VERB("map[%d]: %08x %08lx(%zx)", i, da, (unsigned long)pa, bytes); + VERB("map[%d]: %08lx %08lx(%zx)", i, da, (unsigned long)pa, bytes); ret = iommu_map(domain, da, pa, bytes, prot); if (ret) @@ -84,13 +84,13 @@ fail: return ret; } -static int msm_iommu_unmap(struct msm_mmu *mmu, uint32_t iova, +static int msm_iommu_unmap(struct msm_mmu *mmu, uint64_t iova, struct sg_table *sgt, unsigned len) { struct msm_iommu *iommu = to_msm_iommu(mmu); struct iommu_domain *domain = iommu->domain; struct scatterlist *sg; - unsigned int da = iova; + unsigned long da = iova; int i; for_each_sg(sgt->sgl, sg, sgt->nents, i) { @@ -101,7 +101,7 @@ static int msm_iommu_unmap(struct msm_mmu *mmu, uint32_t iova, if (unmapped < bytes) return unmapped; - VERB("unmap[%d]: %08x(%zx)", i, da, bytes); + VERB("unmap[%d]: %08lx(%zx)", i, da, bytes); BUG_ON(!PAGE_ALIGNED(bytes)); diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h index 40e41e5cdbc6..e470f4cf8f76 100644 --- a/drivers/gpu/drm/msm/msm_kms.h +++ b/drivers/gpu/drm/msm/msm_kms.h @@ -40,6 +40,8 @@ struct msm_kms_funcs { irqreturn_t (*irq)(struct msm_kms *kms); int (*enable_vblank)(struct msm_kms *kms, struct drm_crtc *crtc); void (*disable_vblank)(struct msm_kms *kms, struct drm_crtc *crtc); + /* swap global atomic state: */ + void (*swap_state)(struct msm_kms *kms, struct drm_atomic_state *state); /* modeset, bracketing atomic_commit(): */ void (*prepare_commit)(struct msm_kms *kms, struct drm_atomic_state *state); void (*complete_commit)(struct msm_kms *kms, struct drm_atomic_state *state); @@ -56,6 +58,11 @@ struct msm_kms_funcs { bool is_cmd_mode); /* cleanup: */ void (*destroy)(struct msm_kms *kms); +#ifdef CONFIG_DEBUG_FS + /* debugfs: */ + int (*debugfs_init)(struct msm_kms *kms, struct drm_minor *minor); + void (*debugfs_cleanup)(struct msm_kms *kms, struct drm_minor *minor); +#endif }; struct msm_kms { @@ -65,6 +72,18 @@ struct msm_kms { int irq; }; +/** + * Subclass of drm_atomic_state, to allow kms backend to have driver + * private global state. The kms backend can do whatever it wants + * with the ->state ptr. On ->atomic_state_clear() the ->state ptr + * is kfree'd and set back to NULL. + */ +struct msm_kms_state { + struct drm_atomic_state base; + void *state; +}; +#define to_kms_state(x) container_of(x, struct msm_kms_state, base) + static inline void msm_kms_init(struct msm_kms *kms, const struct msm_kms_funcs *funcs) { diff --git a/drivers/gpu/drm/msm/msm_mmu.h b/drivers/gpu/drm/msm/msm_mmu.h index b8ca9a0e9170..f85c879e68d2 100644 --- a/drivers/gpu/drm/msm/msm_mmu.h +++ b/drivers/gpu/drm/msm/msm_mmu.h @@ -23,9 +23,9 @@ struct msm_mmu_funcs { int (*attach)(struct msm_mmu *mmu, const char * const *names, int cnt); void (*detach)(struct msm_mmu *mmu, const char * const *names, int cnt); - int (*map)(struct msm_mmu *mmu, uint32_t iova, struct sg_table *sgt, + int (*map)(struct msm_mmu *mmu, uint64_t iova, struct sg_table *sgt, unsigned len, int prot); - int (*unmap)(struct msm_mmu *mmu, uint32_t iova, struct sg_table *sgt, + int (*unmap)(struct msm_mmu *mmu, uint64_t iova, struct sg_table *sgt, unsigned len); void (*destroy)(struct msm_mmu *mmu); }; diff --git a/drivers/gpu/drm/msm/msm_rd.c b/drivers/gpu/drm/msm/msm_rd.c index 8487f461f05f..6607456dc626 100644 --- a/drivers/gpu/drm/msm/msm_rd.c +++ b/drivers/gpu/drm/msm/msm_rd.c @@ -289,7 +289,7 @@ void msm_rd_debugfs_cleanup(struct drm_minor *minor) static void snapshot_buf(struct msm_rd_state *rd, struct msm_gem_submit *submit, int idx, - uint32_t iova, uint32_t size) + uint64_t iova, uint32_t size) { struct msm_gem_object *obj = submit->bos[idx].obj; const char *buf; @@ -306,7 +306,7 @@ static void snapshot_buf(struct msm_rd_state *rd, } rd_write_section(rd, RD_GPUADDR, - (uint32_t[2]){ iova, size }, 8); + (uint32_t[3]){ iova, size, iova >> 32 }, 12); rd_write_section(rd, RD_BUFFER_CONTENTS, buf, size); msm_gem_put_vaddr_locked(&obj->base); diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/boost.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/boost.h index 934b0ae5521d..2ff64a20c0ec 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/boost.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/boost.h @@ -1,6 +1,6 @@ #ifndef __NVBIOS_BOOST_H__ #define __NVBIOS_BOOST_H__ -u16 nvbios_boostTe(struct nvkm_bios *, u8 *, u8 *, u8 *, u8 *, u8 *, u8 *); +u32 nvbios_boostTe(struct nvkm_bios *, u8 *, u8 *, u8 *, u8 *, u8 *, u8 *); struct nvbios_boostE { u8 pstate; @@ -8,10 +8,10 @@ struct nvbios_boostE { u32 max; }; -u16 nvbios_boostEe(struct nvkm_bios *, int idx, u8 *, u8 *, u8 *, u8 *); -u16 nvbios_boostEp(struct nvkm_bios *, int idx, u8 *, u8 *, u8 *, u8 *, +u32 nvbios_boostEe(struct nvkm_bios *, int idx, u8 *, u8 *, u8 *, u8 *); +u32 nvbios_boostEp(struct nvkm_bios *, int idx, u8 *, u8 *, u8 *, u8 *, struct nvbios_boostE *); -u16 nvbios_boostEm(struct nvkm_bios *, u8, u8 *, u8 *, u8 *, u8 *, +u32 nvbios_boostEm(struct nvkm_bios *, u8, u8 *, u8 *, u8 *, u8 *, struct nvbios_boostE *); struct nvbios_boostS { @@ -21,7 +21,7 @@ struct nvbios_boostS { u32 max; }; -u16 nvbios_boostSe(struct nvkm_bios *, int, u16, u8 *, u8 *, u8, u8); -u16 nvbios_boostSp(struct nvkm_bios *, int, u16, u8 *, u8 *, u8, u8, +u32 nvbios_boostSe(struct nvkm_bios *, int, u32, u8 *, u8 *, u8, u8); +u32 nvbios_boostSp(struct nvkm_bios *, int, u32, u8 *, u8 *, u8, u8, struct nvbios_boostS *); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/cstep.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/cstep.h index 2f0e0c8e83be..76fe7d50a1ce 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/cstep.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/cstep.h @@ -1,6 +1,6 @@ #ifndef __NVBIOS_CSTEP_H__ #define __NVBIOS_CSTEP_H__ -u16 nvbios_cstepTe(struct nvkm_bios *, +u32 nvbios_cstepTe(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *xnr, u8 *xsz); struct nvbios_cstepE { @@ -8,10 +8,10 @@ struct nvbios_cstepE { u8 index; }; -u16 nvbios_cstepEe(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr); -u16 nvbios_cstepEp(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr, +u32 nvbios_cstepEe(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr); +u32 nvbios_cstepEp(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr, struct nvbios_cstepE *); -u16 nvbios_cstepEm(struct nvkm_bios *, u8 pstate, u8 *ver, u8 *hdr, +u32 nvbios_cstepEm(struct nvkm_bios *, u8 pstate, u8 *ver, u8 *hdr, struct nvbios_cstepE *); struct nvbios_cstepX { @@ -20,7 +20,7 @@ struct nvbios_cstepX { u8 voltage; }; -u16 nvbios_cstepXe(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr); -u16 nvbios_cstepXp(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr, +u32 nvbios_cstepXe(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr); +u32 nvbios_cstepXp(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr, struct nvbios_cstepX *); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/fan.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/fan.h index 693ea7d9ec43..a7513e8406a3 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/fan.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/fan.h @@ -2,5 +2,5 @@ #define __NVBIOS_FAN_H__ #include <subdev/bios/therm.h> -u16 nvbios_fan_parse(struct nvkm_bios *bios, struct nvbios_therm_fan *fan); +u32 nvbios_fan_parse(struct nvkm_bios *bios, struct nvbios_therm_fan *fan); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/perf.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/perf.h index d3bd250103d5..478b1c0d2089 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/perf.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/perf.h @@ -1,6 +1,6 @@ #ifndef __NVBIOS_PERF_H__ #define __NVBIOS_PERF_H__ -u16 nvbios_perf_table(struct nvkm_bios *, u8 *ver, u8 *hdr, +u32 nvbios_perf_table(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz); struct nvbios_perfE { @@ -17,9 +17,9 @@ struct nvbios_perfE { u8 pcie_width; }; -u16 nvbios_perf_entry(struct nvkm_bios *, int idx, +u32 nvbios_perf_entry(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr, u8 *cnt, u8 *len); -u16 nvbios_perfEp(struct nvkm_bios *, int idx, +u32 nvbios_perfEp(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_perfE *); struct nvbios_perfS { diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/timing.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/timing.h index 339a826aa176..38188d4c9ab5 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/timing.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/timing.h @@ -2,10 +2,10 @@ #define __NVBIOS_TIMING_H__ #include <subdev/bios/ramcfg.h> -u16 nvbios_timingTe(struct nvkm_bios *, +u32 nvbios_timingTe(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz); -u16 nvbios_timingEe(struct nvkm_bios *, int idx, +u32 nvbios_timingEe(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr, u8 *cnt, u8 *len); -u16 nvbios_timingEp(struct nvkm_bios *, int idx, +u32 nvbios_timingEp(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ramcfg *); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/vmap.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/vmap.h index 8fa1294c27b7..bea31cdd1dd1 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/vmap.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/vmap.h @@ -6,8 +6,8 @@ struct nvbios_vmap { u8 max2; }; -u16 nvbios_vmap_table(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len); -u16 nvbios_vmap_parse(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, +u32 nvbios_vmap_table(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len); +u32 nvbios_vmap_parse(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_vmap *); struct nvbios_vmap_entry { @@ -18,7 +18,7 @@ struct nvbios_vmap_entry { s32 arg[6]; }; -u16 nvbios_vmap_entry(struct nvkm_bios *, int idx, u8 *ver, u8 *len); -u16 nvbios_vmap_entry_parse(struct nvkm_bios *, int idx, u8 *ver, u8 *len, +u32 nvbios_vmap_entry(struct nvkm_bios *, int idx, u8 *ver, u8 *len); +u32 nvbios_vmap_entry_parse(struct nvkm_bios *, int idx, u8 *ver, u8 *len, struct nvbios_vmap_entry *); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/volt.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/volt.h index 23f3d1b93ebb..f0baa2c7de09 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/volt.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/volt.h @@ -22,8 +22,8 @@ struct nvbios_volt { u32 pwm_range; }; -u16 nvbios_volt_table(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len); -u16 nvbios_volt_parse(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, +u32 nvbios_volt_table(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len); +u32 nvbios_volt_parse(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_volt *); struct nvbios_volt_entry { @@ -31,7 +31,7 @@ struct nvbios_volt_entry { u8 vid; }; -u16 nvbios_volt_entry(struct nvkm_bios *, int idx, u8 *ver, u8 *len); -u16 nvbios_volt_entry_parse(struct nvkm_bios *, int idx, u8 *ver, u8 *len, +u32 nvbios_volt_entry(struct nvkm_bios *, int idx, u8 *ver, u8 *len); +u32 nvbios_volt_entry_parse(struct nvkm_bios *, int idx, u8 *ver, u8 *len, struct nvbios_volt_entry *); #endif diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c index bd37ae127582..cef08da1da4e 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.c +++ b/drivers/gpu/drm/nouveau/nouveau_display.c @@ -349,21 +349,10 @@ static struct nouveau_drm_prop_enum_list dither_depth[] = { } \ } while(0) -#ifdef CONFIG_ACPI - -/* - * Hans de Goede: This define belongs in acpi/video.h, I've submitted a patch - * to the acpi subsys to move it there from drivers/acpi/acpi_video.c . - * This should be dropped once that is merged. - */ -#ifndef ACPI_VIDEO_NOTIFY_PROBE -#define ACPI_VIDEO_NOTIFY_PROBE 0x81 -#endif - static void -nouveau_display_acpi_work(struct work_struct *work) +nouveau_display_hpd_work(struct work_struct *work) { - struct nouveau_drm *drm = container_of(work, typeof(*drm), acpi_work); + struct nouveau_drm *drm = container_of(work, typeof(*drm), hpd_work); pm_runtime_get_sync(drm->dev->dev); @@ -373,6 +362,17 @@ nouveau_display_acpi_work(struct work_struct *work) pm_runtime_put_sync(drm->dev->dev); } +#ifdef CONFIG_ACPI + +/* + * Hans de Goede: This define belongs in acpi/video.h, I've submitted a patch + * to the acpi subsys to move it there from drivers/acpi/acpi_video.c . + * This should be dropped once that is merged. + */ +#ifndef ACPI_VIDEO_NOTIFY_PROBE +#define ACPI_VIDEO_NOTIFY_PROBE 0x81 +#endif + static int nouveau_display_acpi_ntfy(struct notifier_block *nb, unsigned long val, void *data) @@ -385,9 +385,9 @@ nouveau_display_acpi_ntfy(struct notifier_block *nb, unsigned long val, /* * This may be the only indication we receive of a * connector hotplug on a runtime suspended GPU, - * schedule acpi_work to check. + * schedule hpd_work to check. */ - schedule_work(&drm->acpi_work); + schedule_work(&drm->hpd_work); /* acpi-video should not generate keypresses for this */ return NOTIFY_BAD; @@ -582,8 +582,8 @@ nouveau_display_create(struct drm_device *dev) } nouveau_backlight_init(dev); + INIT_WORK(&drm->hpd_work, nouveau_display_hpd_work); #ifdef CONFIG_ACPI - INIT_WORK(&drm->acpi_work, nouveau_display_acpi_work); drm->acpi_nb.notifier_call = nouveau_display_acpi_ntfy; register_acpi_notifier(&drm->acpi_nb); #endif diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c index 9876e6fcfcf0..064a925ed69a 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c @@ -699,7 +699,12 @@ nouveau_pmops_resume(struct device *dev) return ret; pci_set_master(pdev); - return nouveau_do_resume(drm_dev, false); + ret = nouveau_do_resume(drm_dev, false); + + /* Monitors may have been connected / disconnected during suspend */ + schedule_work(&nouveau_drm(drm_dev)->hpd_work); + + return ret; } static int @@ -773,6 +778,10 @@ nouveau_pmops_runtime_resume(struct device *dev) nvif_mask(&device->object, 0x088488, (1 << 25), (1 << 25)); vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON); drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; + + /* Monitors may have been connected / disconnected during suspend */ + schedule_work(&nouveau_drm(drm_dev)->hpd_work); + return ret; } diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h index ae1fd641c96e..9730c0ef6c6a 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/drivers/gpu/drm/nouveau/nouveau_drv.h @@ -163,9 +163,9 @@ struct nouveau_drm { struct nvbios vbios; struct nouveau_display *display; struct backlight_device *backlight; + struct work_struct hpd_work; #ifdef CONFIG_ACPI struct notifier_block acpi_nb; - struct work_struct acpi_work; #endif /* power management */ diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c index 22a8b70a4d1e..7a1aa9161982 100644 --- a/drivers/gpu/drm/nouveau/nv50_display.c +++ b/drivers/gpu/drm/nouveau/nv50_display.c @@ -4090,6 +4090,8 @@ nv50_disp_atomic_commit_tail(struct drm_atomic_state *state) for_each_crtc_in_state(state, crtc, crtc_state, i) { if (crtc->state->event) { unsigned long flags; + /* Get correct count/ts if racing with vblank irq */ + drm_accurate_vblank_count(crtc); spin_lock_irqsave(&crtc->dev->event_lock, flags); drm_crtc_send_vblank_event(crtc, crtc->state->event); spin_unlock_irqrestore(&crtc->dev->event_lock, flags); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/boost.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/boost.c index 3756ec91a88d..eaf74eb72983 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/boost.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/boost.c @@ -25,16 +25,16 @@ #include <subdev/bios/bit.h> #include <subdev/bios/boost.h> -u16 +u32 nvbios_boostTe(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz) { struct bit_entry bit_P; - u16 boost = 0x0000; + u32 boost = 0; if (!bit_entry(bios, 'P', &bit_P)) { if (bit_P.version == 2) - boost = nvbios_rd16(bios, bit_P.offset + 0x30); + boost = nvbios_rd32(bios, bit_P.offset + 0x30); if (boost) { *ver = nvbios_rd08(bios, boost + 0); @@ -52,15 +52,15 @@ nvbios_boostTe(struct nvkm_bios *bios, } } - return 0x0000; + return 0; } -u16 +u32 nvbios_boostEe(struct nvkm_bios *bios, int idx, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) { u8 snr, ssz; - u16 data = nvbios_boostTe(bios, ver, hdr, cnt, len, &snr, &ssz); + u32 data = nvbios_boostTe(bios, ver, hdr, cnt, len, &snr, &ssz); if (data && idx < *cnt) { data = data + *hdr + (idx * (*len + (snr * ssz))); *hdr = *len; @@ -68,14 +68,14 @@ nvbios_boostEe(struct nvkm_bios *bios, int idx, *len = ssz; return data; } - return 0x0000; + return 0; } -u16 +u32 nvbios_boostEp(struct nvkm_bios *bios, int idx, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_boostE *info) { - u16 data = nvbios_boostEe(bios, idx, ver, hdr, cnt, len); + u32 data = nvbios_boostEe(bios, idx, ver, hdr, cnt, len); memset(info, 0x00, sizeof(*info)); if (data) { info->pstate = (nvbios_rd16(bios, data + 0x00) & 0x01e0) >> 5; @@ -85,7 +85,7 @@ nvbios_boostEp(struct nvkm_bios *bios, int idx, return data; } -u16 +u32 nvbios_boostEm(struct nvkm_bios *bios, u8 pstate, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_boostE *info) { @@ -97,21 +97,21 @@ nvbios_boostEm(struct nvkm_bios *bios, u8 pstate, return data; } -u16 +u32 nvbios_boostSe(struct nvkm_bios *bios, int idx, - u16 data, u8 *ver, u8 *hdr, u8 cnt, u8 len) + u32 data, u8 *ver, u8 *hdr, u8 cnt, u8 len) { if (data && idx < cnt) { data = data + *hdr + (idx * len); *hdr = len; return data; } - return 0x0000; + return 0; } -u16 +u32 nvbios_boostSp(struct nvkm_bios *bios, int idx, - u16 data, u8 *ver, u8 *hdr, u8 cnt, u8 len, + u32 data, u8 *ver, u8 *hdr, u8 cnt, u8 len, struct nvbios_boostS *info) { data = nvbios_boostSe(bios, idx, data, ver, hdr, cnt, len); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/cstep.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/cstep.c index 32e01624a162..5063382d8a6c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/cstep.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/cstep.c @@ -25,16 +25,16 @@ #include <subdev/bios/bit.h> #include <subdev/bios/cstep.h> -u16 +u32 nvbios_cstepTe(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *xnr, u8 *xsz) { struct bit_entry bit_P; - u16 cstep = 0x0000; + u32 cstep = 0; if (!bit_entry(bios, 'P', &bit_P)) { if (bit_P.version == 2) - cstep = nvbios_rd16(bios, bit_P.offset + 0x34); + cstep = nvbios_rd32(bios, bit_P.offset + 0x34); if (cstep) { *ver = nvbios_rd08(bios, cstep + 0); @@ -52,27 +52,27 @@ nvbios_cstepTe(struct nvkm_bios *bios, } } - return 0x0000; + return 0; } -u16 +u32 nvbios_cstepEe(struct nvkm_bios *bios, int idx, u8 *ver, u8 *hdr) { u8 cnt, len, xnr, xsz; - u16 data = nvbios_cstepTe(bios, ver, hdr, &cnt, &len, &xnr, &xsz); + u32 data = nvbios_cstepTe(bios, ver, hdr, &cnt, &len, &xnr, &xsz); if (data && idx < cnt) { data = data + *hdr + (idx * len); *hdr = len; return data; } - return 0x0000; + return 0; } -u16 +u32 nvbios_cstepEp(struct nvkm_bios *bios, int idx, u8 *ver, u8 *hdr, struct nvbios_cstepE *info) { - u16 data = nvbios_cstepEe(bios, idx, ver, hdr); + u32 data = nvbios_cstepEe(bios, idx, ver, hdr); memset(info, 0x00, sizeof(*info)); if (data) { info->pstate = (nvbios_rd16(bios, data + 0x00) & 0x01e0) >> 5; @@ -81,7 +81,7 @@ nvbios_cstepEp(struct nvkm_bios *bios, int idx, u8 *ver, u8 *hdr, return data; } -u16 +u32 nvbios_cstepEm(struct nvkm_bios *bios, u8 pstate, u8 *ver, u8 *hdr, struct nvbios_cstepE *info) { @@ -93,24 +93,24 @@ nvbios_cstepEm(struct nvkm_bios *bios, u8 pstate, u8 *ver, u8 *hdr, return data; } -u16 +u32 nvbios_cstepXe(struct nvkm_bios *bios, int idx, u8 *ver, u8 *hdr) { u8 cnt, len, xnr, xsz; - u16 data = nvbios_cstepTe(bios, ver, hdr, &cnt, &len, &xnr, &xsz); + u32 data = nvbios_cstepTe(bios, ver, hdr, &cnt, &len, &xnr, &xsz); if (data && idx < xnr) { data = data + *hdr + (cnt * len) + (idx * xsz); *hdr = xsz; return data; } - return 0x0000; + return 0; } -u16 +u32 nvbios_cstepXp(struct nvkm_bios *bios, int idx, u8 *ver, u8 *hdr, struct nvbios_cstepX *info) { - u16 data = nvbios_cstepXe(bios, idx, ver, hdr); + u32 data = nvbios_cstepXe(bios, idx, ver, hdr); memset(info, 0x00, sizeof(*info)); if (data) { info->freq = nvbios_rd16(bios, data + 0x00) * 1000; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/fan.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/fan.c index e2905815049b..456f9ea920dc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/fan.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/fan.c @@ -25,15 +25,15 @@ #include <subdev/bios/bit.h> #include <subdev/bios/fan.h> -static u16 +static u32 nvbios_fan_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) { struct bit_entry bit_P; - u16 fan = 0x0000; + u32 fan = 0; if (!bit_entry(bios, 'P', &bit_P)) { if (bit_P.version == 2 && bit_P.length >= 0x5a) - fan = nvbios_rd16(bios, bit_P.offset + 0x58); + fan = nvbios_rd32(bios, bit_P.offset + 0x58); if (fan) { *ver = nvbios_rd08(bios, fan + 0); @@ -49,25 +49,25 @@ nvbios_fan_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) } } - return 0x0000; + return 0; } -static u16 +static u32 nvbios_fan_entry(struct nvkm_bios *bios, int idx, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) { - u16 data = nvbios_fan_table(bios, ver, hdr, cnt, len); + u32 data = nvbios_fan_table(bios, ver, hdr, cnt, len); if (data && idx < *cnt) return data + *hdr + (idx * (*len)); - return 0x0000; + return 0; } -u16 +u32 nvbios_fan_parse(struct nvkm_bios *bios, struct nvbios_therm_fan *fan) { u8 ver, hdr, cnt, len; - u16 data = nvbios_fan_entry(bios, 0, &ver, &hdr, &cnt, &len); + u32 data = nvbios_fan_entry(bios, 0, &ver, &hdr, &cnt, &len); if (data) { u8 type = nvbios_rd08(bios, data + 0x00); switch (type) { diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/iccsense.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/iccsense.c index aafd5e17b1c8..3953d11844ea 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/iccsense.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/iccsense.c @@ -26,18 +26,18 @@ #include <subdev/bios/extdev.h> #include <subdev/bios/iccsense.h> -static u16 +static u32 nvbios_iccsense_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) { struct bit_entry bit_P; - u16 iccsense; + u32 iccsense; if (bit_entry(bios, 'P', &bit_P) || bit_P.version != 2 || bit_P.length < 0x2c) return 0; - iccsense = nvbios_rd16(bios, bit_P.offset + 0x28); + iccsense = nvbios_rd32(bios, bit_P.offset + 0x28); if (!iccsense) return 0; @@ -61,7 +61,7 @@ nvbios_iccsense_parse(struct nvkm_bios *bios, struct nvbios_iccsense *iccsense) { struct nvkm_subdev *subdev = &bios->subdev; u8 ver, hdr, cnt, len, i; - u16 table, entry; + u32 table, entry; table = nvbios_iccsense_table(bios, &ver, &hdr, &cnt, &len); if (!table || !cnt) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/mxm.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/mxm.c index 3ddf0939ded3..994cc2d7759b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/mxm.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/mxm.c @@ -81,7 +81,7 @@ mxm_sor_map(struct nvkm_bios *bios, u8 conn) u16 map = nvbios_rd16(bios, mxm + 4); if (map) { ver = nvbios_rd08(bios, map); - if (ver == 0x10) { + if (ver == 0x10 || ver == 0x11) { if (conn < nvbios_rd08(bios, map + 3)) { map += nvbios_rd08(bios, map + 1); map += conn; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c index 636bfb665bb9..c3068358f695 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c @@ -26,16 +26,16 @@ #include <subdev/bios/perf.h> #include <subdev/pci.h> -u16 +u32 nvbios_perf_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz) { struct bit_entry bit_P; - u16 perf = 0x0000; + u32 perf = 0; if (!bit_entry(bios, 'P', &bit_P)) { if (bit_P.version <= 2) { - perf = nvbios_rd16(bios, bit_P.offset + 0); + perf = nvbios_rd32(bios, bit_P.offset + 0); if (perf) { *ver = nvbios_rd08(bios, perf + 0); *hdr = nvbios_rd08(bios, perf + 1); @@ -72,15 +72,15 @@ nvbios_perf_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, } } - return 0x0000; + return 0; } -u16 +u32 nvbios_perf_entry(struct nvkm_bios *bios, int idx, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) { u8 snr, ssz; - u16 perf = nvbios_perf_table(bios, ver, hdr, cnt, len, &snr, &ssz); + u32 perf = nvbios_perf_table(bios, ver, hdr, cnt, len, &snr, &ssz); if (perf && idx < *cnt) { perf = perf + *hdr + (idx * (*len + (snr * ssz))); *hdr = *len; @@ -88,14 +88,14 @@ nvbios_perf_entry(struct nvkm_bios *bios, int idx, *len = ssz; return perf; } - return 0x0000; + return 0; } -u16 +u32 nvbios_perfEp(struct nvkm_bios *bios, int idx, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_perfE *info) { - u16 perf = nvbios_perf_entry(bios, idx, ver, hdr, cnt, len); + u32 perf = nvbios_perf_entry(bios, idx, ver, hdr, cnt, len); memset(info, 0x00, sizeof(*info)); info->pstate = nvbios_rd08(bios, perf + 0x00); switch (!!perf * *ver) { @@ -163,7 +163,7 @@ nvbios_perfEp(struct nvkm_bios *bios, int idx, info->pcie_width = 0xff; break; default: - return 0x0000; + return 0; } return perf; } @@ -202,7 +202,7 @@ nvbios_perf_fan_parse(struct nvkm_bios *bios, struct nvbios_perf_fan *fan) { u8 ver, hdr, cnt, len, snr, ssz; - u16 perf = nvbios_perf_table(bios, &ver, &hdr, &cnt, &len, &snr, &ssz); + u32 perf = nvbios_perf_table(bios, &ver, &hdr, &cnt, &len, &snr, &ssz); if (!perf) return -ENODEV; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/therm.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/therm.c index a54cfec0550d..5babc5a7c7d5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/therm.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/therm.c @@ -25,17 +25,17 @@ #include <subdev/bios/bit.h> #include <subdev/bios/therm.h> -static u16 +static u32 therm_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *len, u8 *cnt) { struct bit_entry bit_P; - u16 therm = 0; + u32 therm = 0; if (!bit_entry(bios, 'P', &bit_P)) { if (bit_P.version == 1) - therm = nvbios_rd16(bios, bit_P.offset + 12); + therm = nvbios_rd32(bios, bit_P.offset + 12); else if (bit_P.version == 2) - therm = nvbios_rd16(bios, bit_P.offset + 16); + therm = nvbios_rd32(bios, bit_P.offset + 16); else nvkm_error(&bios->subdev, "unknown offset for thermal in BIT P %d\n", @@ -44,7 +44,7 @@ therm_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *len, u8 *cnt) /* exit now if we haven't found the thermal table */ if (!therm) - return 0x0000; + return 0; *ver = nvbios_rd08(bios, therm + 0); *hdr = nvbios_rd08(bios, therm + 1); @@ -53,14 +53,14 @@ therm_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *len, u8 *cnt) return therm + nvbios_rd08(bios, therm + 1); } -static u16 +static u32 nvbios_therm_entry(struct nvkm_bios *bios, int idx, u8 *ver, u8 *len) { u8 hdr, cnt; - u16 therm = therm_table(bios, ver, &hdr, len, &cnt); + u32 therm = therm_table(bios, ver, &hdr, len, &cnt); if (therm && idx < cnt) return therm + idx * *len; - return 0x0000; + return 0; } int @@ -70,7 +70,7 @@ nvbios_therm_sensor_parse(struct nvkm_bios *bios, { s8 thrs_section, sensor_section, offset; u8 ver, len, i; - u16 entry; + u32 entry; /* we only support the core domain for now */ if (domain != NVBIOS_THERM_DOMAIN_CORE) @@ -154,7 +154,7 @@ nvbios_therm_fan_parse(struct nvkm_bios *bios, struct nvbios_therm_fan *fan) { struct nvbios_therm_trip_point *cur_trip = NULL; u8 ver, len, i; - u16 entry; + u32 entry; uint8_t duty_lut[] = { 0, 0, 25, 0, 40, 0, 50, 0, 75, 0, 85, 0, 100, 0, 100, 0 }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c index 99f6432ac0af..7e83c3985020 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c @@ -25,19 +25,19 @@ #include <subdev/bios/bit.h> #include <subdev/bios/timing.h> -u16 +u32 nvbios_timingTe(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz) { struct bit_entry bit_P; - u16 timing = 0x0000; + u32 timing = 0; if (!bit_entry(bios, 'P', &bit_P)) { if (bit_P.version == 1) - timing = nvbios_rd16(bios, bit_P.offset + 4); + timing = nvbios_rd32(bios, bit_P.offset + 4); else if (bit_P.version == 2) - timing = nvbios_rd16(bios, bit_P.offset + 8); + timing = nvbios_rd32(bios, bit_P.offset + 8); if (timing) { *ver = nvbios_rd08(bios, timing + 0); @@ -62,15 +62,15 @@ nvbios_timingTe(struct nvkm_bios *bios, } } - return 0x0000; + return 0; } -u16 +u32 nvbios_timingEe(struct nvkm_bios *bios, int idx, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) { u8 snr, ssz; - u16 timing = nvbios_timingTe(bios, ver, hdr, cnt, len, &snr, &ssz); + u32 timing = nvbios_timingTe(bios, ver, hdr, cnt, len, &snr, &ssz); if (timing && idx < *cnt) { timing += *hdr + idx * (*len + (snr * ssz)); *hdr = *len; @@ -78,14 +78,14 @@ nvbios_timingEe(struct nvkm_bios *bios, int idx, *len = ssz; return timing; } - return 0x0000; + return 0; } -u16 +u32 nvbios_timingEp(struct nvkm_bios *bios, int idx, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ramcfg *p) { - u16 data = nvbios_timingEe(bios, idx, ver, hdr, cnt, len), temp; + u32 data = nvbios_timingEe(bios, idx, ver, hdr, cnt, len), temp; p->timing_ver = *ver; p->timing_hdr = *hdr; switch (!!data * *ver) { diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/vmap.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/vmap.c index 32bd8b1d154f..c228ca15fa3b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/vmap.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/vmap.c @@ -25,15 +25,15 @@ #include <subdev/bios/bit.h> #include <subdev/bios/vmap.h> -u16 +u32 nvbios_vmap_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) { struct bit_entry bit_P; - u16 vmap = 0x0000; + u32 vmap = 0; if (!bit_entry(bios, 'P', &bit_P)) { if (bit_P.version == 2) { - vmap = nvbios_rd16(bios, bit_P.offset + 0x20); + vmap = nvbios_rd32(bios, bit_P.offset + 0x20); if (vmap) { *ver = nvbios_rd08(bios, vmap + 0); switch (*ver) { @@ -50,14 +50,14 @@ nvbios_vmap_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) } } - return 0x0000; + return 0; } -u16 +u32 nvbios_vmap_parse(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_vmap *info) { - u16 vmap = nvbios_vmap_table(bios, ver, hdr, cnt, len); + u32 vmap = nvbios_vmap_table(bios, ver, hdr, cnt, len); memset(info, 0x00, sizeof(*info)); switch (!!vmap * *ver) { case 0x10: @@ -77,23 +77,23 @@ nvbios_vmap_parse(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, return vmap; } -u16 +u32 nvbios_vmap_entry(struct nvkm_bios *bios, int idx, u8 *ver, u8 *len) { u8 hdr, cnt; - u16 vmap = nvbios_vmap_table(bios, ver, &hdr, &cnt, len); + u32 vmap = nvbios_vmap_table(bios, ver, &hdr, &cnt, len); if (vmap && idx < cnt) { vmap = vmap + hdr + (idx * *len); return vmap; } - return 0x0000; + return 0; } -u16 +u32 nvbios_vmap_entry_parse(struct nvkm_bios *bios, int idx, u8 *ver, u8 *len, struct nvbios_vmap_entry *info) { - u16 vmap = nvbios_vmap_entry(bios, idx, ver, len); + u32 vmap = nvbios_vmap_entry(bios, idx, ver, len); memset(info, 0x00, sizeof(*info)); switch (!!vmap * *ver) { case 0x10: diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.c index 4504822ace51..a7797a9e9cbc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.c @@ -25,18 +25,18 @@ #include <subdev/bios/bit.h> #include <subdev/bios/volt.h> -u16 +u32 nvbios_volt_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) { struct bit_entry bit_P; - u16 volt = 0x0000; + u32 volt = 0; if (!bit_entry(bios, 'P', &bit_P)) { if (bit_P.version == 2) - volt = nvbios_rd16(bios, bit_P.offset + 0x0c); + volt = nvbios_rd32(bios, bit_P.offset + 0x0c); else if (bit_P.version == 1) - volt = nvbios_rd16(bios, bit_P.offset + 0x10); + volt = nvbios_rd32(bios, bit_P.offset + 0x10); if (volt) { *ver = nvbios_rd08(bios, volt + 0); @@ -62,14 +62,14 @@ nvbios_volt_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) } } - return 0x0000; + return 0; } -u16 +u32 nvbios_volt_parse(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_volt *info) { - u16 volt = nvbios_volt_table(bios, ver, hdr, cnt, len); + u32 volt = nvbios_volt_table(bios, ver, hdr, cnt, len); memset(info, 0x00, sizeof(*info)); switch (!!volt * *ver) { case 0x12: @@ -119,23 +119,23 @@ nvbios_volt_parse(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, return volt; } -u16 +u32 nvbios_volt_entry(struct nvkm_bios *bios, int idx, u8 *ver, u8 *len) { u8 hdr, cnt; - u16 volt = nvbios_volt_table(bios, ver, &hdr, &cnt, len); + u32 volt = nvbios_volt_table(bios, ver, &hdr, &cnt, len); if (volt && idx < cnt) { volt = volt + hdr + (idx * *len); return volt; } - return 0x0000; + return 0; } -u16 +u32 nvbios_volt_entry_parse(struct nvkm_bios *bios, int idx, u8 *ver, u8 *len, struct nvbios_volt_entry *info) { - u16 volt = nvbios_volt_entry(bios, idx, ver, len); + u32 volt = nvbios_volt_entry(bios, idx, ver, len); memset(info, 0x00, sizeof(*info)); switch (!!volt * *ver) { case 0x12: diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c index fa1c12185e19..e4c8d310d870 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c @@ -44,13 +44,13 @@ nvkm_clk_adjust(struct nvkm_clk *clk, bool adjust, struct nvkm_bios *bios = clk->subdev.device->bios; struct nvbios_boostE boostE; u8 ver, hdr, cnt, len; - u16 data; + u32 data; data = nvbios_boostEm(bios, pstate, &ver, &hdr, &cnt, &len, &boostE); if (data) { struct nvbios_boostS boostS; u8 idx = 0, sver, shdr; - u16 subd; + u32 subd; input = max(boostE.min, input); input = min(boostE.max, input); @@ -229,7 +229,7 @@ nvkm_cstate_new(struct nvkm_clk *clk, int idx, struct nvkm_pstate *pstate) struct nvkm_cstate *cstate = NULL; struct nvbios_cstepX cstepX; u8 ver, hdr; - u16 data; + u32 data; data = nvbios_cstepXp(bios, idx, &ver, &hdr, &cstepX); if (!data) @@ -408,7 +408,7 @@ nvkm_pstate_new(struct nvkm_clk *clk, int idx) struct nvbios_cstepE cstepE; struct nvbios_perfE perfE; u8 ver, hdr, cnt, len; - u16 data; + u32 data; data = nvbios_perfEp(bios, idx, &ver, &hdr, &cnt, &len, &perfE); if (!data) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm200.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm200.c index 42d94731655a..1730371933df 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm200.c @@ -130,6 +130,7 @@ gm200_devinit_post(struct nvkm_devinit *base, bool post) /* upload first chunk of init data */ if (post) { + // devinit tables u32 pmu = pmu_args(init, args + 0x08, 0x08); u32 img = nvbios_rd16(bios, bit_I.offset + 0x14); u32 len = nvbios_rd16(bios, bit_I.offset + 0x16); @@ -138,6 +139,7 @@ gm200_devinit_post(struct nvkm_devinit *base, bool post) /* upload second chunk of init data */ if (post) { + // devinit boot scripts u32 pmu = pmu_args(init, args + 0x08, 0x10); u32 img = nvbios_rd16(bios, bit_I.offset + 0x18); u32 len = nvbios_rd16(bios, bit_I.offset + 0x1a); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgp100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgp100.c index f3be408b5e5e..405faabe8dcd 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgp100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgp100.c @@ -92,13 +92,13 @@ gp100_ram_new(struct nvkm_fb *fb, struct nvkm_ram **pram) enum nvkm_ram_type type = nvkm_fb_bios_memtype(device->bios); const u32 rsvd_head = ( 256 * 1024); /* vga memory */ const u32 rsvd_tail = (1024 * 1024); /* vbios etc */ - u32 fbpa_num = nvkm_rd32(device, 0x022438), fbpa; + u32 fbpa_num = nvkm_rd32(device, 0x02243c), fbpa; u32 fbio_opt = nvkm_rd32(device, 0x021c14); u64 part, size = 0, comm = ~0ULL; bool mixed = false; int ret; - nvkm_debug(subdev, "022438: %08x\n", fbpa_num); + nvkm_debug(subdev, "02243c: %08x\n", fbpa_num); nvkm_debug(subdev, "021c14: %08x\n", fbio_opt); for (fbpa = 0; fbpa < fbpa_num; fbpa++) { if (!(fbio_opt & (1 << fbpa))) { diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/nv50.c index db14fad2ddfc..844971e5e874 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/nv50.c @@ -190,8 +190,8 @@ mxm_dcb_sanitise(struct nvkm_mxm *mxm) struct nvkm_bios *bios = subdev->device->bios; u8 ver, hdr, cnt, len; u16 dcb = dcb_table(bios, &ver, &hdr, &cnt, &len); - if (dcb == 0x0000 || ver != 0x40) { - nvkm_debug(subdev, "unsupported DCB version\n"); + if (dcb == 0x0000 || (ver != 0x40 && ver != 0x41)) { + nvkm_warn(subdev, "unsupported DCB version\n"); return; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.c index e8569b04b55d..e344901cfdc7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.c @@ -84,7 +84,7 @@ nvkm_volt_map_min(struct nvkm_volt *volt, u8 id) struct nvkm_bios *bios = volt->subdev.device->bios; struct nvbios_vmap_entry info; u8 ver, len; - u16 vmap; + u32 vmap; vmap = nvbios_vmap_entry_parse(bios, id, &ver, &len, &info); if (vmap) { @@ -106,7 +106,7 @@ nvkm_volt_map(struct nvkm_volt *volt, u8 id, u8 temp) struct nvkm_bios *bios = volt->subdev.device->bios; struct nvbios_vmap_entry info; u8 ver, len; - u16 vmap; + u32 vmap; vmap = nvbios_vmap_entry_parse(bios, id, &ver, &len, &info); if (vmap) { @@ -189,7 +189,7 @@ nvkm_volt_parse_bios(struct nvkm_bios *bios, struct nvkm_volt *volt) struct nvbios_volt_entry ivid; struct nvbios_volt info; u8 ver, hdr, cnt, len; - u16 data; + u32 data; int i; data = nvbios_volt_parse(bios, &ver, &hdr, &cnt, &len, &info); diff --git a/drivers/gpu/drm/qxl/qxl_cmd.c b/drivers/gpu/drm/qxl/qxl_cmd.c index 04270f5d110c..74fc9362ecf9 100644 --- a/drivers/gpu/drm/qxl/qxl_cmd.c +++ b/drivers/gpu/drm/qxl/qxl_cmd.c @@ -578,7 +578,7 @@ int qxl_hw_surface_dealloc(struct qxl_device *qdev, return 0; } -int qxl_update_surface(struct qxl_device *qdev, struct qxl_bo *surf) +static int qxl_update_surface(struct qxl_device *qdev, struct qxl_bo *surf) { struct qxl_rect rect; int ret; diff --git a/drivers/gpu/drm/qxl/qxl_display.c b/drivers/gpu/drm/qxl/qxl_display.c index a61c0d460ec2..4b5eab8a47b3 100644 --- a/drivers/gpu/drm/qxl/qxl_display.c +++ b/drivers/gpu/drm/qxl/qxl_display.c @@ -36,7 +36,7 @@ static bool qxl_head_enabled(struct qxl_head *head) return head->width && head->height; } -void qxl_alloc_client_monitors_config(struct qxl_device *qdev, unsigned count) +static void qxl_alloc_client_monitors_config(struct qxl_device *qdev, unsigned count) { if (qdev->client_monitors_config && count > qdev->client_monitors_config->count) { @@ -57,11 +57,18 @@ void qxl_alloc_client_monitors_config(struct qxl_device *qdev, unsigned count) qdev->client_monitors_config->count = count; } +enum { + MONITORS_CONFIG_MODIFIED, + MONITORS_CONFIG_UNCHANGED, + MONITORS_CONFIG_BAD_CRC, +}; + static int qxl_display_copy_rom_client_monitors_config(struct qxl_device *qdev) { int i; int num_monitors; uint32_t crc; + int status = MONITORS_CONFIG_UNCHANGED; num_monitors = qdev->rom->client_monitors_config.count; crc = crc32(0, (const uint8_t *)&qdev->rom->client_monitors_config, @@ -70,7 +77,7 @@ static int qxl_display_copy_rom_client_monitors_config(struct qxl_device *qdev) qxl_io_log(qdev, "crc mismatch: have %X (%zd) != %X\n", crc, sizeof(qdev->rom->client_monitors_config), qdev->rom->client_monitors_config_crc); - return 1; + return MONITORS_CONFIG_BAD_CRC; } if (num_monitors > qdev->monitors_config->max_allowed) { DRM_DEBUG_KMS("client monitors list will be truncated: %d < %d\n", @@ -79,6 +86,10 @@ static int qxl_display_copy_rom_client_monitors_config(struct qxl_device *qdev) } else { num_monitors = qdev->rom->client_monitors_config.count; } + if (qdev->client_monitors_config + && (num_monitors != qdev->client_monitors_config->count)) { + status = MONITORS_CONFIG_MODIFIED; + } qxl_alloc_client_monitors_config(qdev, num_monitors); /* we copy max from the client but it isn't used */ qdev->client_monitors_config->max_allowed = @@ -88,17 +99,39 @@ static int qxl_display_copy_rom_client_monitors_config(struct qxl_device *qdev) &qdev->rom->client_monitors_config.heads[i]; struct qxl_head *client_head = &qdev->client_monitors_config->heads[i]; - client_head->x = c_rect->left; - client_head->y = c_rect->top; - client_head->width = c_rect->right - c_rect->left; - client_head->height = c_rect->bottom - c_rect->top; - client_head->surface_id = 0; - client_head->id = i; - client_head->flags = 0; + if (client_head->x != c_rect->left) { + client_head->x = c_rect->left; + status = MONITORS_CONFIG_MODIFIED; + } + if (client_head->y != c_rect->top) { + client_head->y = c_rect->top; + status = MONITORS_CONFIG_MODIFIED; + } + if (client_head->width != c_rect->right - c_rect->left) { + client_head->width = c_rect->right - c_rect->left; + status = MONITORS_CONFIG_MODIFIED; + } + if (client_head->height != c_rect->bottom - c_rect->top) { + client_head->height = c_rect->bottom - c_rect->top; + status = MONITORS_CONFIG_MODIFIED; + } + if (client_head->surface_id != 0) { + client_head->surface_id = 0; + status = MONITORS_CONFIG_MODIFIED; + } + if (client_head->id != i) { + client_head->id = i; + status = MONITORS_CONFIG_MODIFIED; + } + if (client_head->flags != 0) { + client_head->flags = 0; + status = MONITORS_CONFIG_MODIFIED; + } DRM_DEBUG_KMS("read %dx%d+%d+%d\n", client_head->width, client_head->height, client_head->x, client_head->y); } - return 0; + + return status; } static void qxl_update_offset_props(struct qxl_device *qdev) @@ -124,9 +157,18 @@ void qxl_display_read_client_monitors_config(struct qxl_device *qdev) { struct drm_device *dev = qdev->ddev; - while (qxl_display_copy_rom_client_monitors_config(qdev)) { + int status; + + status = qxl_display_copy_rom_client_monitors_config(qdev); + while (status == MONITORS_CONFIG_BAD_CRC) { qxl_io_log(qdev, "failed crc check for client_monitors_config," " retrying\n"); + status = qxl_display_copy_rom_client_monitors_config(qdev); + } + if (status == MONITORS_CONFIG_UNCHANGED) { + qxl_io_log(qdev, "config unchanged\n"); + DRM_DEBUG("ignoring unchanged client monitors config"); + return; } drm_modeset_lock_all(dev); @@ -157,6 +199,9 @@ static int qxl_add_monitors_config_modes(struct drm_connector *connector, mode = drm_cvt_mode(dev, head->width, head->height, 60, false, false, false); mode->type |= DRM_MODE_TYPE_PREFERRED; + mode->hdisplay = head->width; + mode->vdisplay = head->height; + drm_mode_set_name(mode); *pwidth = head->width; *pheight = head->height; drm_mode_probed_add(connector, mode); @@ -607,7 +652,7 @@ static bool qxl_crtc_mode_fixup(struct drm_crtc *crtc, return true; } -void +static void qxl_send_monitors_config(struct qxl_device *qdev) { int i; diff --git a/drivers/gpu/drm/qxl/qxl_drv.h b/drivers/gpu/drm/qxl/qxl_drv.h index 84995ebc6ffc..785aad42e9bb 100644 --- a/drivers/gpu/drm/qxl/qxl_drv.h +++ b/drivers/gpu/drm/qxl/qxl_drv.h @@ -395,16 +395,11 @@ qxl_framebuffer_init(struct drm_device *dev, struct drm_gem_object *obj, const struct drm_framebuffer_funcs *funcs); void qxl_display_read_client_monitors_config(struct qxl_device *qdev); -void qxl_send_monitors_config(struct qxl_device *qdev); int qxl_create_monitors_object(struct qxl_device *qdev); int qxl_destroy_monitors_object(struct qxl_device *qdev); -/* used by qxl_debugfs only */ -void qxl_crtc_set_from_monitors_config(struct qxl_device *qdev); -void qxl_alloc_client_monitors_config(struct qxl_device *qdev, unsigned count); - /* qxl_gem.c */ -int qxl_gem_init(struct qxl_device *qdev); +void qxl_gem_init(struct qxl_device *qdev); void qxl_gem_fini(struct qxl_device *qdev); int qxl_gem_object_create(struct qxl_device *qdev, int size, int alignment, int initial_domain, @@ -574,6 +569,5 @@ int qxl_bo_check_id(struct qxl_device *qdev, struct qxl_bo *bo); struct qxl_drv_surface * qxl_surface_lookup(struct drm_device *dev, int surface_id); void qxl_surface_evict(struct qxl_device *qdev, struct qxl_bo *surf, bool freeing); -int qxl_update_surface(struct qxl_device *qdev, struct qxl_bo *surf); #endif diff --git a/drivers/gpu/drm/qxl/qxl_fb.c b/drivers/gpu/drm/qxl/qxl_fb.c index 7e305d8a4146..fd7e5e94be5b 100644 --- a/drivers/gpu/drm/qxl/qxl_fb.c +++ b/drivers/gpu/drm/qxl/qxl_fb.c @@ -191,7 +191,7 @@ static int qxlfb_framebuffer_dirty(struct drm_framebuffer *fb, /* * we are using a shadow draw buffer, at qdev->surface0_shadow */ - qxl_io_log(qdev, "dirty x[%d, %d], y[%d, %d]", clips->x1, clips->x2, + qxl_io_log(qdev, "dirty x[%d, %d], y[%d, %d]\n", clips->x1, clips->x2, clips->y1, clips->y2); image->dx = clips->x1; image->dy = clips->y1; diff --git a/drivers/gpu/drm/qxl/qxl_gem.c b/drivers/gpu/drm/qxl/qxl_gem.c index d9746e904ef1..3f185c4da5b7 100644 --- a/drivers/gpu/drm/qxl/qxl_gem.c +++ b/drivers/gpu/drm/qxl/qxl_gem.c @@ -111,10 +111,9 @@ void qxl_gem_object_close(struct drm_gem_object *obj, { } -int qxl_gem_init(struct qxl_device *qdev) +void qxl_gem_init(struct qxl_device *qdev) { INIT_LIST_HEAD(&qdev->gem.objects); - return 0; } void qxl_gem_fini(struct qxl_device *qdev) diff --git a/drivers/gpu/drm/qxl/qxl_kms.c b/drivers/gpu/drm/qxl/qxl_kms.c index e642242728c0..af685f1d91f8 100644 --- a/drivers/gpu/drm/qxl/qxl_kms.c +++ b/drivers/gpu/drm/qxl/qxl_kms.c @@ -131,7 +131,7 @@ static int qxl_device_init(struct qxl_device *qdev, mutex_init(&qdev->update_area_mutex); mutex_init(&qdev->release_mutex); mutex_init(&qdev->surf_evict_mutex); - INIT_LIST_HEAD(&qdev->gem.objects); + qxl_gem_init(qdev); qdev->rom_base = pci_resource_start(pdev, 2); qdev->rom_size = pci_resource_len(pdev, 2); @@ -273,6 +273,7 @@ static void qxl_device_fini(struct qxl_device *qdev) qxl_ring_free(qdev->command_ring); qxl_ring_free(qdev->cursor_ring); qxl_ring_free(qdev->release_ring); + qxl_gem_fini(qdev); qxl_bo_fini(qdev); io_mapping_free(qdev->surface_mapping); io_mapping_free(qdev->vram_mapping); diff --git a/drivers/gpu/drm/radeon/radeon_atpx_handler.c b/drivers/gpu/drm/radeon/radeon_atpx_handler.c index 2fdcd04bc93f..0ae13cd2adda 100644 --- a/drivers/gpu/drm/radeon/radeon_atpx_handler.c +++ b/drivers/gpu/drm/radeon/radeon_atpx_handler.c @@ -34,6 +34,7 @@ struct radeon_atpx { static struct radeon_atpx_priv { bool atpx_detected; + bool bridge_pm_usable; /* handle for device - and atpx */ acpi_handle dhandle; struct radeon_atpx atpx; @@ -203,7 +204,11 @@ static int radeon_atpx_validate(struct radeon_atpx *atpx) atpx->is_hybrid = false; if (valid_bits & ATPX_MS_HYBRID_GFX_SUPPORTED) { printk("ATPX Hybrid Graphics\n"); - atpx->functions.power_cntl = false; + /* + * Disable legacy PM methods only when pcie port PM is usable, + * otherwise the device might fail to power off or power on. + */ + atpx->functions.power_cntl = !radeon_atpx_priv.bridge_pm_usable; atpx->is_hybrid = true; } @@ -548,11 +553,16 @@ static bool radeon_atpx_detect(void) struct pci_dev *pdev = NULL; bool has_atpx = false; int vga_count = 0; + bool d3_supported = false; + struct pci_dev *parent_pdev; while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { vga_count++; has_atpx |= (radeon_atpx_pci_probe_handle(pdev) == true); + + parent_pdev = pci_upstream_bridge(pdev); + d3_supported |= parent_pdev && parent_pdev->bridge_d3; } /* some newer PX laptops mark the dGPU as a non-VGA display device */ @@ -560,6 +570,9 @@ static bool radeon_atpx_detect(void) vga_count++; has_atpx |= (radeon_atpx_pci_probe_handle(pdev) == true); + + parent_pdev = pci_upstream_bridge(pdev); + d3_supported |= parent_pdev && parent_pdev->bridge_d3; } if (has_atpx && vga_count == 2) { @@ -567,6 +580,7 @@ static bool radeon_atpx_detect(void) printk(KERN_INFO "vga_switcheroo: detected switching method %s handle\n", acpi_method_name); radeon_atpx_priv.atpx_detected = true; + radeon_atpx_priv.bridge_pm_usable = d3_supported; radeon_atpx_init(); return true; } diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c index e18839d52e3e..27affbde058c 100644 --- a/drivers/gpu/drm/radeon/radeon_connectors.c +++ b/drivers/gpu/drm/radeon/radeon_connectors.c @@ -931,7 +931,7 @@ static void radeon_connector_unregister(struct drm_connector *connector) { struct radeon_connector *radeon_connector = to_radeon_connector(connector); - if (radeon_connector->ddc_bus->has_aux) { + if (radeon_connector->ddc_bus && radeon_connector->ddc_bus->has_aux) { drm_dp_aux_unregister(&radeon_connector->ddc_bus->aux); radeon_connector->ddc_bus->has_aux = false; } diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c index 2ce5ace5008a..8a1df2a1afbd 100644 --- a/drivers/gpu/drm/radeon/radeon_device.c +++ b/drivers/gpu/drm/radeon/radeon_device.c @@ -104,6 +104,14 @@ static const char radeon_family_name[][16] = { "LAST", }; +#if defined(CONFIG_VGA_SWITCHEROO) +bool radeon_has_atpx_dgpu_power_cntl(void); +bool radeon_is_atpx_hybrid(void); +#else +static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; } +static inline bool radeon_is_atpx_hybrid(void) { return false; } +#endif + #define RADEON_PX_QUIRK_DISABLE_PX (1 << 0) #define RADEON_PX_QUIRK_LONG_WAKEUP (1 << 1) @@ -160,6 +168,11 @@ static void radeon_device_handle_px_quirks(struct radeon_device *rdev) if (rdev->px_quirk_flags & RADEON_PX_QUIRK_DISABLE_PX) rdev->flags &= ~RADEON_IS_PX; + + /* disable PX is the system doesn't support dGPU power control or hybrid gfx */ + if (!radeon_is_atpx_hybrid() && + !radeon_has_atpx_dgpu_power_cntl()) + rdev->flags &= ~RADEON_IS_PX; } /** diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4i_drv.c index 2891aa914cfa..4ce665349f6b 100644 --- a/drivers/gpu/drm/sun4i/sun4i_drv.c +++ b/drivers/gpu/drm/sun4i/sun4i_drv.c @@ -141,9 +141,9 @@ static int sun4i_drv_bind(struct device *dev) /* Create our layers */ drv->layers = sun4i_layers_init(drm); - if (!drv->layers) { + if (IS_ERR(drv->layers)) { dev_err(drm->dev, "Couldn't create the planes\n"); - ret = -EINVAL; + ret = PTR_ERR(drv->layers); goto free_drm; } diff --git a/drivers/gpu/drm/sun4i/sun4i_rgb.c b/drivers/gpu/drm/sun4i/sun4i_rgb.c index 5380085b3c06..f5e86fe7750e 100644 --- a/drivers/gpu/drm/sun4i/sun4i_rgb.c +++ b/drivers/gpu/drm/sun4i/sun4i_rgb.c @@ -145,15 +145,13 @@ static void sun4i_rgb_encoder_enable(struct drm_encoder *encoder) DRM_DEBUG_DRIVER("Enabling RGB output\n"); - if (!IS_ERR(tcon->panel)) { + if (!IS_ERR(tcon->panel)) drm_panel_prepare(tcon->panel); - drm_panel_enable(tcon->panel); - } - - /* encoder->bridge can be NULL; drm_bridge_enable checks for it */ - drm_bridge_enable(encoder->bridge); sun4i_tcon_channel_enable(tcon, 0); + + if (!IS_ERR(tcon->panel)) + drm_panel_enable(tcon->panel); } static void sun4i_rgb_encoder_disable(struct drm_encoder *encoder) @@ -164,15 +162,13 @@ static void sun4i_rgb_encoder_disable(struct drm_encoder *encoder) DRM_DEBUG_DRIVER("Disabling RGB output\n"); - sun4i_tcon_channel_disable(tcon, 0); + if (!IS_ERR(tcon->panel)) + drm_panel_disable(tcon->panel); - /* encoder->bridge can be NULL; drm_bridge_disable checks for it */ - drm_bridge_disable(encoder->bridge); + sun4i_tcon_channel_disable(tcon, 0); - if (!IS_ERR(tcon->panel)) { - drm_panel_disable(tcon->panel); + if (!IS_ERR(tcon->panel)) drm_panel_unprepare(tcon->panel); - } } static void sun4i_rgb_encoder_mode_set(struct drm_encoder *encoder, diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c index 822531ebd4b0..9942b0577d6e 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c +++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c @@ -21,11 +21,15 @@ #include <drm/drm_flip_work.h> #include <drm/drm_plane_helper.h> #include <linux/workqueue.h> +#include <linux/completion.h> +#include <linux/dma-mapping.h> #include "tilcdc_drv.h" #include "tilcdc_regs.h" -#define TILCDC_VBLANK_SAFETY_THRESHOLD_US 1000 +#define TILCDC_VBLANK_SAFETY_THRESHOLD_US 1000 +#define TILCDC_PALETTE_SIZE 32 +#define TILCDC_PALETTE_FIRST_ENTRY 0x4000 struct tilcdc_crtc { struct drm_crtc base; @@ -33,7 +37,9 @@ struct tilcdc_crtc { struct drm_plane primary; const struct tilcdc_panel_info *info; struct drm_pending_vblank_event *event; + struct mutex enable_lock; bool enabled; + bool shutdown; wait_queue_head_t frame_done_wq; bool frame_done; spinlock_t irq_lock; @@ -53,6 +59,11 @@ struct tilcdc_crtc { int sync_lost_count; bool frame_intact; + struct work_struct recover_work; + + dma_addr_t palette_dma_handle; + u16 *palette_base; + struct completion palette_loaded; }; #define to_tilcdc_crtc(x) container_of(x, struct tilcdc_crtc, base) @@ -71,6 +82,7 @@ static void set_scanout(struct drm_crtc *crtc, struct drm_framebuffer *fb) { struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); struct drm_device *dev = crtc->dev; + struct tilcdc_drm_private *priv = dev->dev_private; struct drm_gem_cma_object *gem; dma_addr_t start, end; u64 dma_base_and_ceiling; @@ -88,7 +100,10 @@ static void set_scanout(struct drm_crtc *crtc, struct drm_framebuffer *fb) * unlikely that LCDC would fetch the DMA addresses in the middle of * an update. */ - dma_base_and_ceiling = (u64)(end - 1) << 32 | start; + if (priv->rev == 1) + end -= 1; + + dma_base_and_ceiling = (u64)end << 32 | start; tilcdc_write64(dev, LCDC_DMA_FB_BASE_ADDR_0_REG, dma_base_and_ceiling); if (tilcdc_crtc->curr_fb) @@ -98,6 +113,56 @@ static void set_scanout(struct drm_crtc *crtc, struct drm_framebuffer *fb) tilcdc_crtc->curr_fb = fb; } +/* + * The driver currently only supports only true color formats. For + * true color the palette block is bypassed, but a 32 byte palette + * should still be loaded. The first 16-bit entry must be 0x4000 while + * all other entries must be zeroed. + */ +static void tilcdc_crtc_load_palette(struct drm_crtc *crtc) +{ + struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); + struct drm_device *dev = crtc->dev; + struct tilcdc_drm_private *priv = dev->dev_private; + int ret; + + reinit_completion(&tilcdc_crtc->palette_loaded); + + /* Tell the LCDC where the palette is located. */ + tilcdc_write(dev, LCDC_DMA_FB_BASE_ADDR_0_REG, + tilcdc_crtc->palette_dma_handle); + tilcdc_write(dev, LCDC_DMA_FB_CEILING_ADDR_0_REG, + (u32) tilcdc_crtc->palette_dma_handle + + TILCDC_PALETTE_SIZE - 1); + + /* Set dma load mode for palette loading only. */ + tilcdc_write_mask(dev, LCDC_RASTER_CTRL_REG, + LCDC_PALETTE_LOAD_MODE(PALETTE_ONLY), + LCDC_PALETTE_LOAD_MODE_MASK); + + /* Enable DMA Palette Loaded Interrupt */ + if (priv->rev == 1) + tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_V1_PL_INT_ENA); + else + tilcdc_write(dev, LCDC_INT_ENABLE_SET_REG, LCDC_V2_PL_INT_ENA); + + /* Enable LCDC DMA and wait for palette to be loaded. */ + tilcdc_clear_irqstatus(dev, 0xffffffff); + tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE); + + ret = wait_for_completion_timeout(&tilcdc_crtc->palette_loaded, + msecs_to_jiffies(50)); + if (ret == 0) + dev_err(dev->dev, "%s: Palette loading timeout", __func__); + + /* Disable LCDC DMA and DMA Palette Loaded Interrupt. */ + tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE); + if (priv->rev == 1) + tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_V1_PL_INT_ENA); + else + tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG, LCDC_V2_PL_INT_ENA); +} + static void tilcdc_crtc_enable_irqs(struct drm_device *dev) { struct tilcdc_drm_private *priv = dev->dev_private; @@ -106,6 +171,7 @@ static void tilcdc_crtc_enable_irqs(struct drm_device *dev) if (priv->rev == 1) { tilcdc_set(dev, LCDC_RASTER_CTRL_REG, + LCDC_V1_SYNC_LOST_INT_ENA | LCDC_V1_FRAME_DONE_INT_ENA | LCDC_V1_UNDERFLOW_INT_ENA); tilcdc_set(dev, LCDC_DMA_CTRL_REG, LCDC_V1_END_OF_FRAME_INT_ENA); @@ -124,6 +190,7 @@ static void tilcdc_crtc_disable_irqs(struct drm_device *dev) /* disable irqs that we might have enabled: */ if (priv->rev == 1) { tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, + LCDC_V1_SYNC_LOST_INT_ENA | LCDC_V1_FRAME_DONE_INT_ENA | LCDC_V1_UNDERFLOW_INT_ENA | LCDC_V1_PL_INT_ENA); tilcdc_clear(dev, LCDC_DMA_CTRL_REG, LCDC_V1_END_OF_FRAME_INT_ENA); @@ -148,193 +215,68 @@ static void reset(struct drm_crtc *crtc) tilcdc_clear(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET); } -static void tilcdc_crtc_enable(struct drm_crtc *crtc) +/* + * Calculate the percentage difference between the requested pixel clock rate + * and the effective rate resulting from calculating the clock divider value. + */ +static unsigned int tilcdc_pclk_diff(unsigned long rate, + unsigned long real_rate) { - struct drm_device *dev = crtc->dev; - struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); - - WARN_ON(!drm_modeset_is_locked(&crtc->mutex)); - - if (tilcdc_crtc->enabled) - return; - - pm_runtime_get_sync(dev->dev); - - reset(crtc); - - tilcdc_crtc_enable_irqs(dev); - - tilcdc_clear(dev, LCDC_DMA_CTRL_REG, LCDC_DUAL_FRAME_BUFFER_ENABLE); - tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_PALETTE_LOAD_MODE(DATA_ONLY)); - tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE); - - drm_crtc_vblank_on(crtc); + int r = rate / 100, rr = real_rate / 100; - tilcdc_crtc->enabled = true; + return (unsigned int)(abs(((rr - r) * 100) / r)); } -void tilcdc_crtc_disable(struct drm_crtc *crtc) +static void tilcdc_crtc_set_clk(struct drm_crtc *crtc) { - struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); struct drm_device *dev = crtc->dev; struct tilcdc_drm_private *priv = dev->dev_private; - - WARN_ON(!drm_modeset_is_locked(&crtc->mutex)); - - if (!tilcdc_crtc->enabled) - return; - - tilcdc_crtc->frame_done = false; - tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE); - - /* - * if necessary wait for framedone irq which will still come - * before putting things to sleep.. - */ - if (priv->rev == 2) { - int ret = wait_event_timeout(tilcdc_crtc->frame_done_wq, - tilcdc_crtc->frame_done, - msecs_to_jiffies(500)); - if (ret == 0) - dev_err(dev->dev, "%s: timeout waiting for framedone\n", - __func__); - } - - drm_crtc_vblank_off(crtc); - - tilcdc_crtc_disable_irqs(dev); - - pm_runtime_put_sync(dev->dev); - - if (tilcdc_crtc->next_fb) { - drm_flip_work_queue(&tilcdc_crtc->unref_work, - tilcdc_crtc->next_fb); - tilcdc_crtc->next_fb = NULL; - } - - if (tilcdc_crtc->curr_fb) { - drm_flip_work_queue(&tilcdc_crtc->unref_work, - tilcdc_crtc->curr_fb); - tilcdc_crtc->curr_fb = NULL; - } - - drm_flip_work_commit(&tilcdc_crtc->unref_work, priv->wq); - tilcdc_crtc->last_vblank = ktime_set(0, 0); - - tilcdc_crtc->enabled = false; -} - -static bool tilcdc_crtc_is_on(struct drm_crtc *crtc) -{ - return crtc->state && crtc->state->enable && crtc->state->active; -} - -static void tilcdc_crtc_destroy(struct drm_crtc *crtc) -{ - struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); - struct tilcdc_drm_private *priv = crtc->dev->dev_private; - - drm_modeset_lock_crtc(crtc, NULL); - tilcdc_crtc_disable(crtc); - drm_modeset_unlock_crtc(crtc); - - flush_workqueue(priv->wq); - - of_node_put(crtc->port); - drm_crtc_cleanup(crtc); - drm_flip_work_cleanup(&tilcdc_crtc->unref_work); -} - -int tilcdc_crtc_update_fb(struct drm_crtc *crtc, - struct drm_framebuffer *fb, - struct drm_pending_vblank_event *event) -{ - struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); - struct drm_device *dev = crtc->dev; - unsigned long flags; - - WARN_ON(!drm_modeset_is_locked(&crtc->mutex)); - - if (tilcdc_crtc->event) { - dev_err(dev->dev, "already pending page flip!\n"); - return -EBUSY; - } - - drm_framebuffer_reference(fb); - - crtc->primary->fb = fb; - - spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags); - - if (crtc->hwmode.vrefresh && ktime_to_ns(tilcdc_crtc->last_vblank)) { - ktime_t next_vblank; - s64 tdiff; - - next_vblank = ktime_add_us(tilcdc_crtc->last_vblank, - 1000000 / crtc->hwmode.vrefresh); - - tdiff = ktime_to_us(ktime_sub(next_vblank, ktime_get())); - - if (tdiff < TILCDC_VBLANK_SAFETY_THRESHOLD_US) - tilcdc_crtc->next_fb = fb; - } - - if (tilcdc_crtc->next_fb != fb) - set_scanout(crtc, fb); - - tilcdc_crtc->event = event; - - spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags); - - return 0; -} - -static bool tilcdc_crtc_mode_fixup(struct drm_crtc *crtc, - const struct drm_display_mode *mode, - struct drm_display_mode *adjusted_mode) -{ struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); + unsigned long clk_rate, real_rate, req_rate; + unsigned int clkdiv; + int ret; - if (!tilcdc_crtc->simulate_vesa_sync) - return true; + clkdiv = 2; /* first try using a standard divider of 2 */ - /* - * tilcdc does not generate VESA-compliant sync but aligns - * VS on the second edge of HS instead of first edge. - * We use adjusted_mode, to fixup sync by aligning both rising - * edges and add HSKEW offset to fix the sync. - */ - adjusted_mode->hskew = mode->hsync_end - mode->hsync_start; - adjusted_mode->flags |= DRM_MODE_FLAG_HSKEW; + /* mode.clock is in KHz, set_rate wants parameter in Hz */ + req_rate = crtc->mode.clock * 1000; - if (mode->flags & DRM_MODE_FLAG_NHSYNC) { - adjusted_mode->flags |= DRM_MODE_FLAG_PHSYNC; - adjusted_mode->flags &= ~DRM_MODE_FLAG_NHSYNC; - } else { - adjusted_mode->flags |= DRM_MODE_FLAG_NHSYNC; - adjusted_mode->flags &= ~DRM_MODE_FLAG_PHSYNC; - } + ret = clk_set_rate(priv->clk, req_rate * clkdiv); + clk_rate = clk_get_rate(priv->clk); + if (ret < 0) { + /* + * If we fail to set the clock rate (some architectures don't + * use the common clock framework yet and may not implement + * all the clk API calls for every clock), try the next best + * thing: adjusting the clock divider, unless clk_get_rate() + * failed as well. + */ + if (!clk_rate) { + /* Nothing more we can do. Just bail out. */ + dev_err(dev->dev, + "failed to set the pixel clock - unable to read current lcdc clock rate\n"); + return; + } - return true; -} + clkdiv = DIV_ROUND_CLOSEST(clk_rate, req_rate); -static void tilcdc_crtc_set_clk(struct drm_crtc *crtc) -{ - struct drm_device *dev = crtc->dev; - struct tilcdc_drm_private *priv = dev->dev_private; - struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); - const unsigned clkdiv = 2; /* using a fixed divider of 2 */ - int ret; + /* + * Emit a warning if the real clock rate resulting from the + * calculated divider differs much from the requested rate. + * + * 5% is an arbitrary value - LCDs are usually quite tolerant + * about pixel clock rates. + */ + real_rate = clkdiv * req_rate; - /* mode.clock is in KHz, set_rate wants parameter in Hz */ - ret = clk_set_rate(priv->clk, crtc->mode.clock * 1000 * clkdiv); - if (ret < 0) { - dev_err(dev->dev, "failed to set display clock rate to: %d\n", - crtc->mode.clock); - return; + if (tilcdc_pclk_diff(clk_rate, real_rate) > 5) { + dev_warn(dev->dev, + "effective pixel clock rate (%luHz) differs from the calculated rate (%luHz)\n", + clk_rate, real_rate); + } } - tilcdc_crtc->lcd_fck_rate = clk_get_rate(priv->clk); + tilcdc_crtc->lcd_fck_rate = clk_rate; DBG("lcd_clk=%u, mode clock=%d, div=%u", tilcdc_crtc->lcd_fck_rate, crtc->mode.clock, clkdiv); @@ -349,7 +291,7 @@ static void tilcdc_crtc_set_clk(struct drm_crtc *crtc) LCDC_V2_CORE_CLK_EN); } -static void tilcdc_crtc_mode_set_nofb(struct drm_crtc *crtc) +static void tilcdc_crtc_set_mode(struct drm_crtc *crtc) { struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); struct drm_device *dev = crtc->dev; @@ -359,8 +301,6 @@ static void tilcdc_crtc_mode_set_nofb(struct drm_crtc *crtc) struct drm_display_mode *mode = &crtc->state->adjusted_mode; struct drm_framebuffer *fb = crtc->primary->state->fb; - WARN_ON(!drm_modeset_is_locked(&crtc->mutex)); - if (WARN_ON(!info)) return; @@ -509,15 +449,226 @@ static void tilcdc_crtc_mode_set_nofb(struct drm_crtc *crtc) else tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER); - drm_framebuffer_reference(fb); + tilcdc_crtc_set_clk(crtc); + + tilcdc_crtc_load_palette(crtc); set_scanout(crtc, fb); - tilcdc_crtc_set_clk(crtc); + drm_framebuffer_reference(fb); crtc->hwmode = crtc->state->adjusted_mode; } +static void tilcdc_crtc_enable(struct drm_crtc *crtc) +{ + struct drm_device *dev = crtc->dev; + struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); + + WARN_ON(!drm_modeset_is_locked(&crtc->mutex)); + mutex_lock(&tilcdc_crtc->enable_lock); + if (tilcdc_crtc->enabled || tilcdc_crtc->shutdown) { + mutex_unlock(&tilcdc_crtc->enable_lock); + return; + } + + pm_runtime_get_sync(dev->dev); + + reset(crtc); + + tilcdc_crtc_set_mode(crtc); + + tilcdc_crtc_enable_irqs(dev); + + tilcdc_clear(dev, LCDC_DMA_CTRL_REG, LCDC_DUAL_FRAME_BUFFER_ENABLE); + tilcdc_write_mask(dev, LCDC_RASTER_CTRL_REG, + LCDC_PALETTE_LOAD_MODE(DATA_ONLY), + LCDC_PALETTE_LOAD_MODE_MASK); + tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE); + + drm_crtc_vblank_on(crtc); + + tilcdc_crtc->enabled = true; + mutex_unlock(&tilcdc_crtc->enable_lock); +} + +static void tilcdc_crtc_off(struct drm_crtc *crtc, bool shutdown) +{ + struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); + struct drm_device *dev = crtc->dev; + struct tilcdc_drm_private *priv = dev->dev_private; + int ret; + + mutex_lock(&tilcdc_crtc->enable_lock); + if (shutdown) + tilcdc_crtc->shutdown = true; + if (!tilcdc_crtc->enabled) { + mutex_unlock(&tilcdc_crtc->enable_lock); + return; + } + tilcdc_crtc->frame_done = false; + tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE); + + /* + * Wait for framedone irq which will still come before putting + * things to sleep.. + */ + ret = wait_event_timeout(tilcdc_crtc->frame_done_wq, + tilcdc_crtc->frame_done, + msecs_to_jiffies(500)); + if (ret == 0) + dev_err(dev->dev, "%s: timeout waiting for framedone\n", + __func__); + + drm_crtc_vblank_off(crtc); + + tilcdc_crtc_disable_irqs(dev); + + pm_runtime_put_sync(dev->dev); + + if (tilcdc_crtc->next_fb) { + drm_flip_work_queue(&tilcdc_crtc->unref_work, + tilcdc_crtc->next_fb); + tilcdc_crtc->next_fb = NULL; + } + + if (tilcdc_crtc->curr_fb) { + drm_flip_work_queue(&tilcdc_crtc->unref_work, + tilcdc_crtc->curr_fb); + tilcdc_crtc->curr_fb = NULL; + } + + drm_flip_work_commit(&tilcdc_crtc->unref_work, priv->wq); + tilcdc_crtc->last_vblank = ktime_set(0, 0); + + tilcdc_crtc->enabled = false; + mutex_unlock(&tilcdc_crtc->enable_lock); +} + +static void tilcdc_crtc_disable(struct drm_crtc *crtc) +{ + WARN_ON(!drm_modeset_is_locked(&crtc->mutex)); + tilcdc_crtc_off(crtc, false); +} + +void tilcdc_crtc_shutdown(struct drm_crtc *crtc) +{ + tilcdc_crtc_off(crtc, true); +} + +static bool tilcdc_crtc_is_on(struct drm_crtc *crtc) +{ + return crtc->state && crtc->state->enable && crtc->state->active; +} + +static void tilcdc_crtc_recover_work(struct work_struct *work) +{ + struct tilcdc_crtc *tilcdc_crtc = + container_of(work, struct tilcdc_crtc, recover_work); + struct drm_crtc *crtc = &tilcdc_crtc->base; + + dev_info(crtc->dev->dev, "%s: Reset CRTC", __func__); + + drm_modeset_lock_crtc(crtc, NULL); + + if (!tilcdc_crtc_is_on(crtc)) + goto out; + + tilcdc_crtc_disable(crtc); + tilcdc_crtc_enable(crtc); +out: + drm_modeset_unlock_crtc(crtc); +} + +static void tilcdc_crtc_destroy(struct drm_crtc *crtc) +{ + struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); + struct tilcdc_drm_private *priv = crtc->dev->dev_private; + + drm_modeset_lock_crtc(crtc, NULL); + tilcdc_crtc_disable(crtc); + drm_modeset_unlock_crtc(crtc); + + flush_workqueue(priv->wq); + + of_node_put(crtc->port); + drm_crtc_cleanup(crtc); + drm_flip_work_cleanup(&tilcdc_crtc->unref_work); +} + +int tilcdc_crtc_update_fb(struct drm_crtc *crtc, + struct drm_framebuffer *fb, + struct drm_pending_vblank_event *event) +{ + struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); + struct drm_device *dev = crtc->dev; + unsigned long flags; + + WARN_ON(!drm_modeset_is_locked(&crtc->mutex)); + + if (tilcdc_crtc->event) { + dev_err(dev->dev, "already pending page flip!\n"); + return -EBUSY; + } + + drm_framebuffer_reference(fb); + + crtc->primary->fb = fb; + + spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags); + + if (crtc->hwmode.vrefresh && ktime_to_ns(tilcdc_crtc->last_vblank)) { + ktime_t next_vblank; + s64 tdiff; + + next_vblank = ktime_add_us(tilcdc_crtc->last_vblank, + 1000000 / crtc->hwmode.vrefresh); + + tdiff = ktime_to_us(ktime_sub(next_vblank, ktime_get())); + + if (tdiff < TILCDC_VBLANK_SAFETY_THRESHOLD_US) + tilcdc_crtc->next_fb = fb; + } + + if (tilcdc_crtc->next_fb != fb) + set_scanout(crtc, fb); + + tilcdc_crtc->event = event; + + spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags); + + return 0; +} + +static bool tilcdc_crtc_mode_fixup(struct drm_crtc *crtc, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); + + if (!tilcdc_crtc->simulate_vesa_sync) + return true; + + /* + * tilcdc does not generate VESA-compliant sync but aligns + * VS on the second edge of HS instead of first edge. + * We use adjusted_mode, to fixup sync by aligning both rising + * edges and add HSKEW offset to fix the sync. + */ + adjusted_mode->hskew = mode->hsync_end - mode->hsync_start; + adjusted_mode->flags |= DRM_MODE_FLAG_HSKEW; + + if (mode->flags & DRM_MODE_FLAG_NHSYNC) { + adjusted_mode->flags |= DRM_MODE_FLAG_PHSYNC; + adjusted_mode->flags &= ~DRM_MODE_FLAG_NHSYNC; + } else { + adjusted_mode->flags |= DRM_MODE_FLAG_NHSYNC; + adjusted_mode->flags &= ~DRM_MODE_FLAG_PHSYNC; + } + + return true; +} + static int tilcdc_crtc_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state) { @@ -558,7 +709,6 @@ static const struct drm_crtc_helper_funcs tilcdc_crtc_helper_funcs = { .enable = tilcdc_crtc_enable, .disable = tilcdc_crtc_disable, .atomic_check = tilcdc_crtc_atomic_check, - .mode_set_nofb = tilcdc_crtc_mode_set_nofb, }; int tilcdc_crtc_max_width(struct drm_crtc *crtc) @@ -754,28 +904,48 @@ irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc) } if (stat & LCDC_FIFO_UNDERFLOW) - dev_err_ratelimited(dev->dev, "%s(0x%08x): FIFO underfow", + dev_err_ratelimited(dev->dev, "%s(0x%08x): FIFO underflow", __func__, stat); - /* For revision 2 only */ - if (priv->rev == 2) { - if (stat & LCDC_FRAME_DONE) { - tilcdc_crtc->frame_done = true; - wake_up(&tilcdc_crtc->frame_done_wq); - } + if (stat & LCDC_PL_LOAD_DONE) { + complete(&tilcdc_crtc->palette_loaded); + if (priv->rev == 1) + tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, + LCDC_V1_PL_INT_ENA); + else + tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG, + LCDC_V2_PL_INT_ENA); + } - if (stat & LCDC_SYNC_LOST) { - dev_err_ratelimited(dev->dev, "%s(0x%08x): Sync lost", - __func__, stat); - tilcdc_crtc->frame_intact = false; - if (tilcdc_crtc->sync_lost_count++ > - SYNC_LOST_COUNT_LIMIT) { - dev_err(dev->dev, "%s(0x%08x): Sync lost flood detected, disabling the interrupt", __func__, stat); + if (stat & LCDC_SYNC_LOST) { + dev_err_ratelimited(dev->dev, "%s(0x%08x): Sync lost", + __func__, stat); + tilcdc_crtc->frame_intact = false; + if (tilcdc_crtc->sync_lost_count++ > + SYNC_LOST_COUNT_LIMIT) { + dev_err(dev->dev, "%s(0x%08x): Sync lost flood detected, recovering", __func__, stat); + queue_work(system_wq, &tilcdc_crtc->recover_work); + if (priv->rev == 1) + tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, + LCDC_V1_SYNC_LOST_INT_ENA); + else tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG, LCDC_SYNC_LOST); - } + tilcdc_crtc->sync_lost_count = 0; } + } + + if (stat & LCDC_FRAME_DONE) { + tilcdc_crtc->frame_done = true; + wake_up(&tilcdc_crtc->frame_done_wq); + /* rev 1 lcdc appears to hang if irq is not disbaled here */ + if (priv->rev == 1) + tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, + LCDC_V1_FRAME_DONE_INT_ENA); + } + /* For revision 2 only */ + if (priv->rev == 2) { /* Indicate to LCDC that the interrupt service routine has * completed, see 13.3.6.1.6 in AM335x TRM. */ @@ -785,7 +955,7 @@ irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc) return IRQ_HANDLED; } -struct drm_crtc *tilcdc_crtc_create(struct drm_device *dev) +int tilcdc_crtc_create(struct drm_device *dev) { struct tilcdc_drm_private *priv = dev->dev_private; struct tilcdc_crtc *tilcdc_crtc; @@ -795,21 +965,33 @@ struct drm_crtc *tilcdc_crtc_create(struct drm_device *dev) tilcdc_crtc = devm_kzalloc(dev->dev, sizeof(*tilcdc_crtc), GFP_KERNEL); if (!tilcdc_crtc) { dev_err(dev->dev, "allocation failed\n"); - return NULL; + return -ENOMEM; } + init_completion(&tilcdc_crtc->palette_loaded); + tilcdc_crtc->palette_base = dmam_alloc_coherent(dev->dev, + TILCDC_PALETTE_SIZE, + &tilcdc_crtc->palette_dma_handle, + GFP_KERNEL | __GFP_ZERO); + if (!tilcdc_crtc->palette_base) + return -ENOMEM; + *tilcdc_crtc->palette_base = TILCDC_PALETTE_FIRST_ENTRY; + crtc = &tilcdc_crtc->base; ret = tilcdc_plane_init(dev, &tilcdc_crtc->primary); if (ret < 0) goto fail; + mutex_init(&tilcdc_crtc->enable_lock); + init_waitqueue_head(&tilcdc_crtc->frame_done_wq); drm_flip_work_init(&tilcdc_crtc->unref_work, "unref", unref_worker); spin_lock_init(&tilcdc_crtc->irq_lock); + INIT_WORK(&tilcdc_crtc->recover_work, tilcdc_crtc_recover_work); ret = drm_crtc_init_with_planes(dev, crtc, &tilcdc_crtc->primary, @@ -835,13 +1017,15 @@ struct drm_crtc *tilcdc_crtc_create(struct drm_device *dev) if (!crtc->port) { /* This should never happen */ dev_err(dev->dev, "Port node not found in %s\n", dev->dev->of_node->full_name); + ret = -EINVAL; goto fail; } } - return crtc; + priv->crtc = crtc; + return 0; fail: tilcdc_crtc_destroy(crtc); - return NULL; + return -ENOMEM; } diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.c b/drivers/gpu/drm/tilcdc/tilcdc_drv.c index 0f58a74f25d1..bd0a3bd07167 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_drv.c +++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.c @@ -127,18 +127,12 @@ static int tilcdc_commit(struct drm_device *dev, * current layout. */ - /* Keep HW on while we commit the state. */ - pm_runtime_get_sync(dev->dev); - drm_atomic_helper_commit_modeset_disables(dev, state); drm_atomic_helper_commit_planes(dev, state, 0); drm_atomic_helper_commit_modeset_enables(dev, state); - /* Now HW should remain on if need becase the crtc is enabled */ - pm_runtime_put_sync(dev->dev); - drm_atomic_helper_wait_for_vblanks(dev, state); drm_atomic_helper_cleanup_planes(dev, state); @@ -153,15 +147,11 @@ static const struct drm_mode_config_funcs mode_config_funcs = { .atomic_commit = tilcdc_commit, }; -static int modeset_init(struct drm_device *dev) +static void modeset_init(struct drm_device *dev) { struct tilcdc_drm_private *priv = dev->dev_private; struct tilcdc_module *mod; - drm_mode_config_init(dev); - - priv->crtc = tilcdc_crtc_create(dev); - list_for_each_entry(mod, &module_list, list) { DBG("loading module: %s", mod->name); mod->funcs->modeset_init(mod, dev); @@ -172,8 +162,6 @@ static int modeset_init(struct drm_device *dev) dev->mode_config.max_width = tilcdc_crtc_max_width(priv->crtc); dev->mode_config.max_height = 2048; dev->mode_config.funcs = &mode_config_funcs; - - return 0; } #ifdef CONFIG_CPU_FREQ @@ -194,22 +182,29 @@ static int cpufreq_transition(struct notifier_block *nb, * DRM operations: */ -static int tilcdc_unload(struct drm_device *dev) +static void tilcdc_fini(struct drm_device *dev) { struct tilcdc_drm_private *priv = dev->dev_private; - tilcdc_remove_external_encoders(dev); + if (priv->crtc) + tilcdc_crtc_shutdown(priv->crtc); + + if (priv->is_registered) + drm_dev_unregister(dev); - drm_fbdev_cma_fini(priv->fbdev); drm_kms_helper_poll_fini(dev); - drm_mode_config_cleanup(dev); - drm_vblank_cleanup(dev); + + if (priv->fbdev) + drm_fbdev_cma_fini(priv->fbdev); drm_irq_uninstall(dev); + drm_mode_config_cleanup(dev); + tilcdc_remove_external_device(dev); #ifdef CONFIG_CPU_FREQ - cpufreq_unregister_notifier(&priv->freq_transition, - CPUFREQ_TRANSITION_NOTIFIER); + if (priv->freq_transition.notifier_call) + cpufreq_unregister_notifier(&priv->freq_transition, + CPUFREQ_TRANSITION_NOTIFIER); #endif if (priv->clk) @@ -218,61 +213,71 @@ static int tilcdc_unload(struct drm_device *dev) if (priv->mmio) iounmap(priv->mmio); - flush_workqueue(priv->wq); - destroy_workqueue(priv->wq); + if (priv->wq) { + flush_workqueue(priv->wq); + destroy_workqueue(priv->wq); + } dev->dev_private = NULL; pm_runtime_disable(dev->dev); - return 0; + drm_dev_unref(dev); } -static int tilcdc_load(struct drm_device *dev, unsigned long flags) +static int tilcdc_init(struct drm_driver *ddrv, struct device *dev) { - struct platform_device *pdev = dev->platformdev; - struct device_node *node = pdev->dev.of_node; + struct drm_device *ddev; + struct platform_device *pdev = to_platform_device(dev); + struct device_node *node = dev->of_node; struct tilcdc_drm_private *priv; struct resource *res; u32 bpp = 0; int ret; - priv = devm_kzalloc(dev->dev, sizeof(*priv), GFP_KERNEL); + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) { - dev_err(dev->dev, "failed to allocate private data\n"); + dev_err(dev, "failed to allocate private data\n"); return -ENOMEM; } - dev->dev_private = priv; + ddev = drm_dev_alloc(ddrv, dev); + if (IS_ERR(ddev)) + return PTR_ERR(ddev); + + ddev->platformdev = pdev; + ddev->dev_private = priv; + platform_set_drvdata(pdev, ddev); + drm_mode_config_init(ddev); priv->is_componentized = - tilcdc_get_external_components(dev->dev, NULL) > 0; + tilcdc_get_external_components(dev, NULL) > 0; priv->wq = alloc_ordered_workqueue("tilcdc", 0); if (!priv->wq) { ret = -ENOMEM; - goto fail_unset_priv; + goto init_failed; } res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) { - dev_err(dev->dev, "failed to get memory resource\n"); + dev_err(dev, "failed to get memory resource\n"); ret = -EINVAL; - goto fail_free_wq; + goto init_failed; } priv->mmio = ioremap_nocache(res->start, resource_size(res)); if (!priv->mmio) { - dev_err(dev->dev, "failed to ioremap\n"); + dev_err(dev, "failed to ioremap\n"); ret = -ENOMEM; - goto fail_free_wq; + goto init_failed; } - priv->clk = clk_get(dev->dev, "fck"); + priv->clk = clk_get(dev, "fck"); if (IS_ERR(priv->clk)) { - dev_err(dev->dev, "failed to get functional clock\n"); + dev_err(dev, "failed to get functional clock\n"); ret = -ENODEV; - goto fail_iounmap; + goto init_failed; } #ifdef CONFIG_CPU_FREQ @@ -280,8 +285,9 @@ static int tilcdc_load(struct drm_device *dev, unsigned long flags) ret = cpufreq_register_notifier(&priv->freq_transition, CPUFREQ_TRANSITION_NOTIFIER); if (ret) { - dev_err(dev->dev, "failed to register cpufreq notifier\n"); - goto fail_put_clk; + dev_err(dev, "failed to register cpufreq notifier\n"); + priv->freq_transition.notifier_call = NULL; + goto init_failed; } #endif @@ -290,22 +296,22 @@ static int tilcdc_load(struct drm_device *dev, unsigned long flags) DBG("Maximum Bandwidth Value %d", priv->max_bandwidth); - if (of_property_read_u32(node, "ti,max-width", &priv->max_width)) + if (of_property_read_u32(node, "max-width", &priv->max_width)) priv->max_width = TILCDC_DEFAULT_MAX_WIDTH; DBG("Maximum Horizontal Pixel Width Value %dpixels", priv->max_width); - if (of_property_read_u32(node, "ti,max-pixelclock", + if (of_property_read_u32(node, "max-pixelclock", &priv->max_pixelclock)) priv->max_pixelclock = TILCDC_DEFAULT_MAX_PIXELCLOCK; DBG("Maximum Pixel Clock Value %dKHz", priv->max_pixelclock); - pm_runtime_enable(dev->dev); + pm_runtime_enable(dev); /* Determine LCD IP Version */ - pm_runtime_get_sync(dev->dev); - switch (tilcdc_read(dev, LCDC_PID_REG)) { + pm_runtime_get_sync(dev); + switch (tilcdc_read(ddev, LCDC_PID_REG)) { case 0x4c100102: priv->rev = 1; break; @@ -314,14 +320,14 @@ static int tilcdc_load(struct drm_device *dev, unsigned long flags) priv->rev = 2; break; default: - dev_warn(dev->dev, "Unknown PID Reg value 0x%08x, " - "defaulting to LCD revision 1\n", - tilcdc_read(dev, LCDC_PID_REG)); + dev_warn(dev, "Unknown PID Reg value 0x%08x, " + "defaulting to LCD revision 1\n", + tilcdc_read(ddev, LCDC_PID_REG)); priv->rev = 1; break; } - pm_runtime_put_sync(dev->dev); + pm_runtime_put_sync(dev); if (priv->rev == 1) { DBG("Revision 1 LCDC supports only RGB565 format"); @@ -354,91 +360,67 @@ static int tilcdc_load(struct drm_device *dev, unsigned long flags) } } - ret = modeset_init(dev); + ret = tilcdc_crtc_create(ddev); if (ret < 0) { - dev_err(dev->dev, "failed to initialize mode setting\n"); - goto fail_cpufreq_unregister; + dev_err(dev, "failed to create crtc\n"); + goto init_failed; } - - platform_set_drvdata(pdev, dev); + modeset_init(ddev); if (priv->is_componentized) { - ret = component_bind_all(dev->dev, dev); + ret = component_bind_all(dev, ddev); if (ret < 0) - goto fail_mode_config_cleanup; + goto init_failed; - ret = tilcdc_add_external_encoders(dev); + ret = tilcdc_add_component_encoder(ddev); if (ret < 0) - goto fail_component_cleanup; + goto init_failed; + } else { + ret = tilcdc_attach_external_device(ddev); + if (ret) + goto init_failed; } - if ((priv->num_encoders == 0) || (priv->num_connectors == 0)) { - dev_err(dev->dev, "no encoders/connectors found\n"); + if (!priv->external_connector && + ((priv->num_encoders == 0) || (priv->num_connectors == 0))) { + dev_err(dev, "no encoders/connectors found\n"); ret = -ENXIO; - goto fail_external_cleanup; + goto init_failed; } - ret = drm_vblank_init(dev, 1); + ret = drm_vblank_init(ddev, 1); if (ret < 0) { - dev_err(dev->dev, "failed to initialize vblank\n"); - goto fail_external_cleanup; + dev_err(dev, "failed to initialize vblank\n"); + goto init_failed; } - ret = drm_irq_install(dev, platform_get_irq(dev->platformdev, 0)); + ret = drm_irq_install(ddev, platform_get_irq(pdev, 0)); if (ret < 0) { - dev_err(dev->dev, "failed to install IRQ handler\n"); - goto fail_vblank_cleanup; + dev_err(dev, "failed to install IRQ handler\n"); + goto init_failed; } - drm_mode_config_reset(dev); + drm_mode_config_reset(ddev); - priv->fbdev = drm_fbdev_cma_init(dev, bpp, - dev->mode_config.num_crtc, - dev->mode_config.num_connector); + priv->fbdev = drm_fbdev_cma_init(ddev, bpp, + ddev->mode_config.num_crtc, + ddev->mode_config.num_connector); if (IS_ERR(priv->fbdev)) { ret = PTR_ERR(priv->fbdev); - goto fail_irq_uninstall; + goto init_failed; } - drm_kms_helper_poll_init(dev); + drm_kms_helper_poll_init(ddev); - return 0; - -fail_irq_uninstall: - drm_irq_uninstall(dev); - -fail_vblank_cleanup: - drm_vblank_cleanup(dev); - -fail_component_cleanup: - if (priv->is_componentized) - component_unbind_all(dev->dev, dev); - -fail_mode_config_cleanup: - drm_mode_config_cleanup(dev); - -fail_external_cleanup: - tilcdc_remove_external_encoders(dev); - -fail_cpufreq_unregister: - pm_runtime_disable(dev->dev); -#ifdef CONFIG_CPU_FREQ - cpufreq_unregister_notifier(&priv->freq_transition, - CPUFREQ_TRANSITION_NOTIFIER); - -fail_put_clk: -#endif - clk_put(priv->clk); - -fail_iounmap: - iounmap(priv->mmio); + ret = drm_dev_register(ddev, 0); + if (ret) + goto init_failed; -fail_free_wq: - flush_workqueue(priv->wq); - destroy_workqueue(priv->wq); + priv->is_registered = true; + return 0; -fail_unset_priv: - dev->dev_private = NULL; +init_failed: + tilcdc_fini(ddev); return ret; } @@ -583,8 +565,6 @@ static const struct file_operations fops = { static struct drm_driver tilcdc_driver = { .driver_features = (DRIVER_HAVE_IRQ | DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME | DRIVER_ATOMIC), - .load = tilcdc_load, - .unload = tilcdc_unload, .lastclose = tilcdc_lastclose, .irq_handler = tilcdc_irq, .get_vblank_counter = drm_vblank_no_hw_counter, @@ -658,10 +638,9 @@ static const struct dev_pm_ops tilcdc_pm_ops = { /* * Platform driver: */ - static int tilcdc_bind(struct device *dev) { - return drm_platform_init(&tilcdc_driver, to_platform_device(dev)); + return tilcdc_init(&tilcdc_driver, dev); } static void tilcdc_unbind(struct device *dev) @@ -672,7 +651,7 @@ static void tilcdc_unbind(struct device *dev) if (!ddev->dev_private) return; - drm_put_dev(dev_get_drvdata(dev)); + tilcdc_fini(dev_get_drvdata(dev)); } static const struct component_master_ops tilcdc_comp_ops = { @@ -695,7 +674,7 @@ static int tilcdc_pdev_probe(struct platform_device *pdev) if (ret < 0) return ret; else if (ret == 0) - return drm_platform_init(&tilcdc_driver, pdev); + return tilcdc_init(&tilcdc_driver, &pdev->dev); else return component_master_add_with_match(&pdev->dev, &tilcdc_comp_ops, @@ -710,7 +689,7 @@ static int tilcdc_pdev_remove(struct platform_device *pdev) if (ret < 0) return ret; else if (ret == 0) - drm_put_dev(platform_get_drvdata(pdev)); + tilcdc_fini(platform_get_drvdata(pdev)); else component_master_del(&pdev->dev, &tilcdc_comp_ops); @@ -719,6 +698,7 @@ static int tilcdc_pdev_remove(struct platform_device *pdev) static struct of_device_id tilcdc_of_match[] = { { .compatible = "ti,am33xx-tilcdc", }, + { .compatible = "ti,da850-tilcdc", }, { }, }; MODULE_DEVICE_TABLE(of, tilcdc_of_match); diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.h b/drivers/gpu/drm/tilcdc/tilcdc_drv.h index 9780c37ec4cd..0e71daf5b5cb 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_drv.h +++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.h @@ -33,6 +33,7 @@ #include <drm/drm_crtc_helper.h> #include <drm/drm_gem_cma_helper.h> #include <drm/drm_fb_cma_helper.h> +#include <drm/drm_bridge.h> /* Defaulting to pixel clock defined on AM335x */ #define TILCDC_DEFAULT_MAX_PIXELCLOCK 126000 @@ -87,8 +88,12 @@ struct tilcdc_drm_private { unsigned int num_connectors; struct drm_connector *connectors[8]; - const struct drm_connector_helper_funcs *connector_funcs[8]; + struct drm_encoder *external_encoder; + struct drm_connector *external_connector; + const struct drm_connector_helper_funcs *connector_funcs; + + bool is_registered; bool is_componentized; }; @@ -163,7 +168,7 @@ struct tilcdc_panel_info { #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) -struct drm_crtc *tilcdc_crtc_create(struct drm_device *dev); +int tilcdc_crtc_create(struct drm_device *dev); irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc); void tilcdc_crtc_update_clk(struct drm_crtc *crtc); void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc, @@ -172,7 +177,7 @@ void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc *crtc, bool simulate_vesa_sync); int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode); int tilcdc_crtc_max_width(struct drm_crtc *crtc); -void tilcdc_crtc_disable(struct drm_crtc *crtc); +void tilcdc_crtc_shutdown(struct drm_crtc *crtc); int tilcdc_crtc_update_fb(struct drm_crtc *crtc, struct drm_framebuffer *fb, struct drm_pending_vblank_event *event); diff --git a/drivers/gpu/drm/tilcdc/tilcdc_external.c b/drivers/gpu/drm/tilcdc/tilcdc_external.c index 06a4c584f3cb..c67d7cd7d57e 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_external.c +++ b/drivers/gpu/drm/tilcdc/tilcdc_external.c @@ -28,44 +28,50 @@ static const struct tilcdc_panel_info panel_info_tda998x = { .raster_order = 0, }; +static const struct tilcdc_panel_info panel_info_default = { + .ac_bias = 255, + .ac_bias_intrpt = 0, + .dma_burst_sz = 16, + .bpp = 16, + .fdd = 0x80, + .tft_alt_mode = 0, + .sync_edge = 0, + .sync_ctrl = 1, + .raster_order = 0, +}; + static int tilcdc_external_mode_valid(struct drm_connector *connector, struct drm_display_mode *mode) { struct tilcdc_drm_private *priv = connector->dev->dev_private; - int ret, i; + int ret; ret = tilcdc_crtc_mode_valid(priv->crtc, mode); if (ret != MODE_OK) return ret; - for (i = 0; i < priv->num_connectors && - priv->connectors[i] != connector; i++) - ; - - BUG_ON(priv->connectors[i] != connector); - BUG_ON(!priv->connector_funcs[i]); + BUG_ON(priv->external_connector != connector); + BUG_ON(!priv->connector_funcs); /* If the connector has its own mode_valid call it. */ - if (!IS_ERR(priv->connector_funcs[i]) && - priv->connector_funcs[i]->mode_valid) - return priv->connector_funcs[i]->mode_valid(connector, mode); + if (!IS_ERR(priv->connector_funcs) && + priv->connector_funcs->mode_valid) + return priv->connector_funcs->mode_valid(connector, mode); return MODE_OK; } -static int tilcdc_add_external_encoder(struct drm_device *dev, - struct drm_connector *connector) +static int tilcdc_add_external_connector(struct drm_device *dev, + struct drm_connector *connector) { struct tilcdc_drm_private *priv = dev->dev_private; struct drm_connector_helper_funcs *connector_funcs; - priv->connectors[priv->num_connectors] = connector; - priv->encoders[priv->num_encoders++] = connector->encoder; - - /* Only tda998x is supported at the moment. */ - tilcdc_crtc_set_simulate_vesa_sync(priv->crtc, true); - tilcdc_crtc_set_panel_info(priv->crtc, &panel_info_tda998x); + /* There should never be more than one connector */ + if (WARN_ON(priv->external_connector)) + return -EINVAL; + priv->external_connector = connector; connector_funcs = devm_kzalloc(dev->dev, sizeof(*connector_funcs), GFP_KERNEL); if (!connector_funcs) @@ -78,56 +84,177 @@ static int tilcdc_add_external_encoder(struct drm_device *dev, * everything else but use our own mode_valid() (above). */ if (connector->helper_private) { - priv->connector_funcs[priv->num_connectors] = - connector->helper_private; - *connector_funcs = *priv->connector_funcs[priv->num_connectors]; + priv->connector_funcs = connector->helper_private; + *connector_funcs = *priv->connector_funcs; } else { - priv->connector_funcs[priv->num_connectors] = ERR_PTR(-ENOENT); + priv->connector_funcs = ERR_PTR(-ENOENT); } connector_funcs->mode_valid = tilcdc_external_mode_valid; drm_connector_helper_add(connector, connector_funcs); - priv->num_connectors++; - dev_dbg(dev->dev, "External encoder '%s' connected\n", - connector->encoder->name); + dev_dbg(dev->dev, "External connector '%s' connected\n", + connector->name); return 0; } -int tilcdc_add_external_encoders(struct drm_device *dev) +static +struct drm_connector *tilcdc_encoder_find_connector(struct drm_device *ddev, + struct drm_encoder *encoder) { - struct tilcdc_drm_private *priv = dev->dev_private; struct drm_connector *connector; - int num_internal_connectors = priv->num_connectors; - - list_for_each_entry(connector, &dev->mode_config.connector_list, head) { - bool found = false; - int i, ret; - - for (i = 0; i < num_internal_connectors; i++) - if (connector == priv->connectors[i]) - found = true; - if (!found) { - ret = tilcdc_add_external_encoder(dev, connector); - if (ret) - return ret; - } + int i; + + list_for_each_entry(connector, &ddev->mode_config.connector_list, head) + for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) + if (connector->encoder_ids[i] == encoder->base.id) + return connector; + + dev_err(ddev->dev, "No connector found for %s encoder (id %d)\n", + encoder->name, encoder->base.id); + + return NULL; +} + +int tilcdc_add_component_encoder(struct drm_device *ddev) +{ + struct tilcdc_drm_private *priv = ddev->dev_private; + struct drm_connector *connector; + struct drm_encoder *encoder; + + list_for_each_entry(encoder, &ddev->mode_config.encoder_list, head) + if (encoder->possible_crtcs & (1 << priv->crtc->index)) + break; + + if (!encoder) { + dev_err(ddev->dev, "%s: No suitable encoder found\n", __func__); + return -ENODEV; } - return 0; + + connector = tilcdc_encoder_find_connector(ddev, encoder); + + if (!connector) + return -ENODEV; + + /* Only tda998x is supported at the moment. */ + tilcdc_crtc_set_simulate_vesa_sync(priv->crtc, true); + tilcdc_crtc_set_panel_info(priv->crtc, &panel_info_tda998x); + + return tilcdc_add_external_connector(ddev, connector); } -void tilcdc_remove_external_encoders(struct drm_device *dev) +void tilcdc_remove_external_device(struct drm_device *dev) { struct tilcdc_drm_private *priv = dev->dev_private; - int i; /* Restore the original helper functions, if any. */ - for (i = 0; i < priv->num_connectors; i++) - if (IS_ERR(priv->connector_funcs[i])) - drm_connector_helper_add(priv->connectors[i], NULL); - else if (priv->connector_funcs[i]) - drm_connector_helper_add(priv->connectors[i], - priv->connector_funcs[i]); + if (IS_ERR(priv->connector_funcs)) + drm_connector_helper_add(priv->external_connector, NULL); + else if (priv->connector_funcs) + drm_connector_helper_add(priv->external_connector, + priv->connector_funcs); +} + +static const struct drm_encoder_funcs tilcdc_external_encoder_funcs = { + .destroy = drm_encoder_cleanup, +}; + +static +int tilcdc_attach_bridge(struct drm_device *ddev, struct drm_bridge *bridge) +{ + struct tilcdc_drm_private *priv = ddev->dev_private; + struct drm_connector *connector; + int ret; + + priv->external_encoder->possible_crtcs = BIT(0); + priv->external_encoder->bridge = bridge; + bridge->encoder = priv->external_encoder; + + ret = drm_bridge_attach(ddev, bridge); + if (ret) { + dev_err(ddev->dev, "drm_bridge_attach() failed %d\n", ret); + return ret; + } + + tilcdc_crtc_set_panel_info(priv->crtc, &panel_info_default); + + connector = tilcdc_encoder_find_connector(ddev, priv->external_encoder); + if (!connector) + return -ENODEV; + + ret = tilcdc_add_external_connector(ddev, connector); + + return ret; +} + +static int tilcdc_node_has_port(struct device_node *dev_node) +{ + struct device_node *node; + + node = of_get_child_by_name(dev_node, "ports"); + if (!node) + node = of_get_child_by_name(dev_node, "port"); + if (!node) + return 0; + of_node_put(node); + + return 1; +} + +static +struct device_node *tilcdc_get_remote_node(struct device_node *node) +{ + struct device_node *ep; + struct device_node *parent; + + if (!tilcdc_node_has_port(node)) + return NULL; + + ep = of_graph_get_next_endpoint(node, NULL); + if (!ep) + return NULL; + + parent = of_graph_get_remote_port_parent(ep); + of_node_put(ep); + + return parent; +} + +int tilcdc_attach_external_device(struct drm_device *ddev) +{ + struct tilcdc_drm_private *priv = ddev->dev_private; + struct device_node *remote_node; + struct drm_bridge *bridge; + int ret; + + remote_node = tilcdc_get_remote_node(ddev->dev->of_node); + if (!remote_node) + return 0; + + bridge = of_drm_find_bridge(remote_node); + of_node_put(remote_node); + if (!bridge) + return -EPROBE_DEFER; + + priv->external_encoder = devm_kzalloc(ddev->dev, + sizeof(*priv->external_encoder), + GFP_KERNEL); + if (!priv->external_encoder) + return -ENOMEM; + + ret = drm_encoder_init(ddev, priv->external_encoder, + &tilcdc_external_encoder_funcs, + DRM_MODE_ENCODER_NONE, NULL); + if (ret) { + dev_err(ddev->dev, "drm_encoder_init() failed %d\n", ret); + return ret; + } + + ret = tilcdc_attach_bridge(ddev, bridge); + if (ret) + drm_encoder_cleanup(priv->external_encoder); + + return ret; } static int dev_match_of(struct device *dev, void *data) @@ -141,16 +268,10 @@ int tilcdc_get_external_components(struct device *dev, struct device_node *node; struct device_node *ep = NULL; int count = 0; + int ret = 0; - /* Avoid error print by of_graph_get_next_endpoint() if there - * is no ports present. - */ - node = of_get_child_by_name(dev->of_node, "ports"); - if (!node) - node = of_get_child_by_name(dev->of_node, "port"); - if (!node) + if (!tilcdc_node_has_port(dev->of_node)) return 0; - of_node_put(node); while ((ep = of_graph_get_next_endpoint(dev->of_node, ep))) { node = of_graph_get_remote_port_parent(ep); @@ -160,17 +281,20 @@ int tilcdc_get_external_components(struct device *dev, } dev_dbg(dev, "Subdevice node '%s' found\n", node->name); - if (match) - drm_of_component_match_add(dev, match, dev_match_of, - node); - of_node_put(node); - count++; - } - if (count > 1) { - dev_err(dev, "Only one external encoder is supported\n"); - return -EINVAL; + if (of_device_is_compatible(node, "nxp,tda998x")) { + if (match) + drm_of_component_match_add(dev, match, + dev_match_of, node); + ret = 1; + } + + of_node_put(node); + if (count++ > 1) { + dev_err(dev, "Only one port is supported\n"); + return -EINVAL; + } } - return count; + return ret; } diff --git a/drivers/gpu/drm/tilcdc/tilcdc_external.h b/drivers/gpu/drm/tilcdc/tilcdc_external.h index c700e0c1623e..763d18f006c7 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_external.h +++ b/drivers/gpu/drm/tilcdc/tilcdc_external.h @@ -18,8 +18,9 @@ #ifndef __TILCDC_EXTERNAL_H__ #define __TILCDC_EXTERNAL_H__ -int tilcdc_add_external_encoders(struct drm_device *dev); -void tilcdc_remove_external_encoders(struct drm_device *dev); +int tilcdc_add_component_encoder(struct drm_device *dev); +void tilcdc_remove_external_device(struct drm_device *dev); int tilcdc_get_external_components(struct device *dev, struct component_match **match); +int tilcdc_attach_external_device(struct drm_device *ddev); #endif /* __TILCDC_SLAVE_H__ */ diff --git a/drivers/gpu/drm/tilcdc/tilcdc_panel.c b/drivers/gpu/drm/tilcdc/tilcdc_panel.c index e634201db821..28c3e2f44f64 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_panel.c +++ b/drivers/gpu/drm/tilcdc/tilcdc_panel.c @@ -232,8 +232,6 @@ static struct drm_connector *panel_connector_create(struct drm_device *dev, if (ret) goto fail; - drm_connector_register(connector); - return connector; fail: diff --git a/drivers/gpu/drm/tilcdc/tilcdc_regs.h b/drivers/gpu/drm/tilcdc/tilcdc_regs.h index f57c0d62c76a..9d528c0a67a4 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_regs.h +++ b/drivers/gpu/drm/tilcdc/tilcdc_regs.h @@ -34,11 +34,14 @@ /* LCDC DMA Control Register */ #define LCDC_DMA_BURST_SIZE(x) ((x) << 4) +#define LCDC_DMA_BURST_SIZE_MASK ((0x7) << 4) #define LCDC_DMA_BURST_1 0x0 #define LCDC_DMA_BURST_2 0x1 #define LCDC_DMA_BURST_4 0x2 #define LCDC_DMA_BURST_8 0x3 #define LCDC_DMA_BURST_16 0x4 +#define LCDC_DMA_FIFO_THRESHOLD(x) ((x) << 8) +#define LCDC_DMA_FIFO_THRESHOLD_MASK ((0x3) << 8) #define LCDC_V1_END_OF_FRAME_INT_ENA BIT(2) #define LCDC_V2_END_OF_FRAME0_INT_ENA BIT(8) #define LCDC_V2_END_OF_FRAME1_INT_ENA BIT(9) @@ -46,10 +49,12 @@ /* LCDC Control Register */ #define LCDC_CLK_DIVISOR(x) ((x) << 8) +#define LCDC_CLK_DIVISOR_MASK ((0xFF) << 8) #define LCDC_RASTER_MODE 0x01 /* LCDC Raster Control Register */ #define LCDC_PALETTE_LOAD_MODE(x) ((x) << 20) +#define LCDC_PALETTE_LOAD_MODE_MASK ((0x3) << 20) #define PALETTE_AND_DATA 0x00 #define PALETTE_ONLY 0x01 #define DATA_ONLY 0x02 @@ -61,6 +66,8 @@ #define LCDC_V2_UNDERFLOW_INT_ENA BIT(5) #define LCDC_V1_PL_INT_ENA BIT(4) #define LCDC_V2_PL_INT_ENA BIT(6) +#define LCDC_V1_SYNC_LOST_INT_ENA BIT(5) +#define LCDC_V1_FRAME_DONE_INT_ENA BIT(3) #define LCDC_MONOCHROME_MODE BIT(1) #define LCDC_RASTER_ENABLE BIT(0) #define LCDC_TFT_ALT_ENABLE BIT(23) @@ -74,7 +81,9 @@ /* LCDC Raster Timing 2 Register */ #define LCDC_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16) +#define LCDC_AC_BIAS_TRANSITIONS_PER_INT_MASK ((0xF) << 16) #define LCDC_AC_BIAS_FREQUENCY(x) ((x) << 8) +#define LCDC_AC_BIAS_FREQUENCY_MASK ((0xFF) << 8) #define LCDC_SYNC_CTRL BIT(25) #define LCDC_SYNC_EDGE BIT(24) #define LCDC_INVERT_PIXEL_CLOCK BIT(22) @@ -139,6 +148,12 @@ static inline u32 tilcdc_read(struct drm_device *dev, u32 reg) return ioread32(priv->mmio + reg); } +static inline void tilcdc_write_mask(struct drm_device *dev, u32 reg, + u32 val, u32 mask) +{ + tilcdc_write(dev, reg, (tilcdc_read(dev, reg) & ~mask) | (val & mask)); +} + static inline void tilcdc_set(struct drm_device *dev, u32 reg, u32 mask) { tilcdc_write(dev, reg, tilcdc_read(dev, reg) | mask); diff --git a/drivers/gpu/drm/tilcdc/tilcdc_tfp410.c b/drivers/gpu/drm/tilcdc/tilcdc_tfp410.c index 458043a53995..aabfad882e23 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_tfp410.c +++ b/drivers/gpu/drm/tilcdc/tilcdc_tfp410.c @@ -249,8 +249,6 @@ static struct drm_connector *tfp410_connector_create(struct drm_device *dev, if (ret) goto fail; - drm_connector_register(connector); - return connector; fail: diff --git a/drivers/gpu/drm/udl/udl_main.c b/drivers/gpu/drm/udl/udl_main.c index 29f0207fa677..873f010d9616 100644 --- a/drivers/gpu/drm/udl/udl_main.c +++ b/drivers/gpu/drm/udl/udl_main.c @@ -98,17 +98,23 @@ success: static int udl_select_std_channel(struct udl_device *udl) { int ret; - u8 set_def_chn[] = {0x57, 0xCD, 0xDC, 0xA7, - 0x1C, 0x88, 0x5E, 0x15, - 0x60, 0xFE, 0xC6, 0x97, - 0x16, 0x3D, 0x47, 0xF2}; + static const u8 set_def_chn[] = {0x57, 0xCD, 0xDC, 0xA7, + 0x1C, 0x88, 0x5E, 0x15, + 0x60, 0xFE, 0xC6, 0x97, + 0x16, 0x3D, 0x47, 0xF2}; + void *sendbuf; + + sendbuf = kmemdup(set_def_chn, sizeof(set_def_chn), GFP_KERNEL); + if (!sendbuf) + return -ENOMEM; ret = usb_control_msg(udl->udev, usb_sndctrlpipe(udl->udev, 0), NR_USB_REQUEST_CHANNEL, (USB_DIR_OUT | USB_TYPE_VENDOR), 0, 0, - set_def_chn, sizeof(set_def_chn), + sendbuf, sizeof(set_def_chn), USB_CTRL_SET_TIMEOUT); + kfree(sendbuf); return ret < 0 ? ret : 0; } diff --git a/drivers/gpu/drm/virtio/virtgpu_drm_bus.c b/drivers/gpu/drm/virtio/virtgpu_drm_bus.c index 49e5996cb9f2..3b97d50fd392 100644 --- a/drivers/gpu/drm/virtio/virtgpu_drm_bus.c +++ b/drivers/gpu/drm/virtio/virtgpu_drm_bus.c @@ -28,16 +28,6 @@ #include "virtgpu_drv.h" -int drm_virtio_set_busid(struct drm_device *dev, struct drm_master *master) -{ - struct pci_dev *pdev = dev->pdev; - - if (pdev) { - return drm_pci_set_busid(dev, master); - } - return 0; -} - static void virtio_pci_kick_out_firmware_fb(struct pci_dev *pci_dev) { struct apertures_struct *ap; @@ -71,13 +61,22 @@ int drm_virtio_init(struct drm_driver *driver, struct virtio_device *vdev) if (strcmp(vdev->dev.parent->bus->name, "pci") == 0) { struct pci_dev *pdev = to_pci_dev(vdev->dev.parent); + const char *pname = dev_name(&pdev->dev); bool vga = (pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA; + char unique[20]; - DRM_INFO("pci: %s detected\n", - vga ? "virtio-vga" : "virtio-gpu-pci"); + DRM_INFO("pci: %s detected at %s\n", + vga ? "virtio-vga" : "virtio-gpu-pci", + pname); dev->pdev = pdev; if (vga) virtio_pci_kick_out_firmware_fb(pdev); + + snprintf(unique, sizeof(unique), "pci:%s", pname); + ret = drm_dev_set_unique(dev, unique); + if (ret) + goto err_free; + } ret = drm_dev_register(dev, 0); diff --git a/drivers/gpu/drm/virtio/virtgpu_drv.c b/drivers/gpu/drm/virtio/virtgpu_drv.c index 04d98db75c64..d82489815096 100644 --- a/drivers/gpu/drm/virtio/virtgpu_drv.c +++ b/drivers/gpu/drm/virtio/virtgpu_drv.c @@ -115,7 +115,6 @@ static const struct file_operations virtio_gpu_driver_fops = { static struct drm_driver driver = { .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME | DRIVER_RENDER | DRIVER_ATOMIC, - .set_busid = drm_virtio_set_busid, .load = virtio_gpu_driver_load, .unload = virtio_gpu_driver_unload, .open = virtio_gpu_driver_open, diff --git a/drivers/gpu/drm/virtio/virtgpu_drv.h b/drivers/gpu/drm/virtio/virtgpu_drv.h index ec1ebdcfe80b..08906c8ce3fa 100644 --- a/drivers/gpu/drm/virtio/virtgpu_drv.h +++ b/drivers/gpu/drm/virtio/virtgpu_drv.h @@ -49,7 +49,6 @@ #define DRIVER_PATCHLEVEL 1 /* virtgpu_drm_bus.c */ -int drm_virtio_set_busid(struct drm_device *dev, struct drm_master *master); int drm_virtio_init(struct drm_driver *driver, struct virtio_device *vdev); struct virtio_gpu_object { diff --git a/drivers/gpu/drm/virtio/virtgpu_vq.c b/drivers/gpu/drm/virtio/virtgpu_vq.c index 5a0f8a745b9d..974f9410474b 100644 --- a/drivers/gpu/drm/virtio/virtgpu_vq.c +++ b/drivers/gpu/drm/virtio/virtgpu_vq.c @@ -75,7 +75,7 @@ void virtio_gpu_cursor_ack(struct virtqueue *vq) int virtio_gpu_alloc_vbufs(struct virtio_gpu_device *vgdev) { struct virtio_gpu_vbuffer *vbuf; - int i, size, count = 0; + int i, size, count = 16; void *ptr; INIT_LIST_HEAD(&vgdev->free_vbufs); diff --git a/drivers/hid/hid-cp2112.c b/drivers/hid/hid-cp2112.c index 086d8a507157..60d30203a5fa 100644 --- a/drivers/hid/hid-cp2112.c +++ b/drivers/hid/hid-cp2112.c @@ -32,6 +32,11 @@ #include <linux/usb/ch9.h> #include "hid-ids.h" +#define CP2112_REPORT_MAX_LENGTH 64 +#define CP2112_GPIO_CONFIG_LENGTH 5 +#define CP2112_GPIO_GET_LENGTH 2 +#define CP2112_GPIO_SET_LENGTH 3 + enum { CP2112_GPIO_CONFIG = 0x02, CP2112_GPIO_GET = 0x03, @@ -161,6 +166,8 @@ struct cp2112_device { atomic_t read_avail; atomic_t xfer_avail; struct gpio_chip gc; + u8 *in_out_buffer; + spinlock_t lock; }; static int gpio_push_pull = 0xFF; @@ -171,62 +178,86 @@ static int cp2112_gpio_direction_input(struct gpio_chip *chip, unsigned offset) { struct cp2112_device *dev = gpiochip_get_data(chip); struct hid_device *hdev = dev->hdev; - u8 buf[5]; + u8 *buf = dev->in_out_buffer; + unsigned long flags; int ret; + spin_lock_irqsave(&dev->lock, flags); + ret = hid_hw_raw_request(hdev, CP2112_GPIO_CONFIG, buf, - sizeof(buf), HID_FEATURE_REPORT, - HID_REQ_GET_REPORT); - if (ret != sizeof(buf)) { + CP2112_GPIO_CONFIG_LENGTH, HID_FEATURE_REPORT, + HID_REQ_GET_REPORT); + if (ret != CP2112_GPIO_CONFIG_LENGTH) { hid_err(hdev, "error requesting GPIO config: %d\n", ret); - return ret; + goto exit; } buf[1] &= ~(1 << offset); buf[2] = gpio_push_pull; - ret = hid_hw_raw_request(hdev, CP2112_GPIO_CONFIG, buf, sizeof(buf), - HID_FEATURE_REPORT, HID_REQ_SET_REPORT); + ret = hid_hw_raw_request(hdev, CP2112_GPIO_CONFIG, buf, + CP2112_GPIO_CONFIG_LENGTH, HID_FEATURE_REPORT, + HID_REQ_SET_REPORT); if (ret < 0) { hid_err(hdev, "error setting GPIO config: %d\n", ret); - return ret; + goto exit; } - return 0; + ret = 0; + +exit: + spin_unlock_irqrestore(&dev->lock, flags); + return ret <= 0 ? ret : -EIO; } static void cp2112_gpio_set(struct gpio_chip *chip, unsigned offset, int value) { struct cp2112_device *dev = gpiochip_get_data(chip); struct hid_device *hdev = dev->hdev; - u8 buf[3]; + u8 *buf = dev->in_out_buffer; + unsigned long flags; int ret; + spin_lock_irqsave(&dev->lock, flags); + buf[0] = CP2112_GPIO_SET; buf[1] = value ? 0xff : 0; buf[2] = 1 << offset; - ret = hid_hw_raw_request(hdev, CP2112_GPIO_SET, buf, sizeof(buf), - HID_FEATURE_REPORT, HID_REQ_SET_REPORT); + ret = hid_hw_raw_request(hdev, CP2112_GPIO_SET, buf, + CP2112_GPIO_SET_LENGTH, HID_FEATURE_REPORT, + HID_REQ_SET_REPORT); if (ret < 0) hid_err(hdev, "error setting GPIO values: %d\n", ret); + + spin_unlock_irqrestore(&dev->lock, flags); } static int cp2112_gpio_get(struct gpio_chip *chip, unsigned offset) { struct cp2112_device *dev = gpiochip_get_data(chip); struct hid_device *hdev = dev->hdev; - u8 buf[2]; + u8 *buf = dev->in_out_buffer; + unsigned long flags; int ret; - ret = hid_hw_raw_request(hdev, CP2112_GPIO_GET, buf, sizeof(buf), - HID_FEATURE_REPORT, HID_REQ_GET_REPORT); - if (ret != sizeof(buf)) { + spin_lock_irqsave(&dev->lock, flags); + + ret = hid_hw_raw_request(hdev, CP2112_GPIO_GET, buf, + CP2112_GPIO_GET_LENGTH, HID_FEATURE_REPORT, + HID_REQ_GET_REPORT); + if (ret != CP2112_GPIO_GET_LENGTH) { hid_err(hdev, "error requesting GPIO values: %d\n", ret); - return ret; + ret = ret < 0 ? ret : -EIO; + goto exit; } - return (buf[1] >> offset) & 1; + ret = (buf[1] >> offset) & 1; + +exit: + spin_unlock_irqrestore(&dev->lock, flags); + + return ret; } static int cp2112_gpio_direction_output(struct gpio_chip *chip, @@ -234,27 +265,33 @@ static int cp2112_gpio_direction_output(struct gpio_chip *chip, { struct cp2112_device *dev = gpiochip_get_data(chip); struct hid_device *hdev = dev->hdev; - u8 buf[5]; + u8 *buf = dev->in_out_buffer; + unsigned long flags; int ret; + spin_lock_irqsave(&dev->lock, flags); + ret = hid_hw_raw_request(hdev, CP2112_GPIO_CONFIG, buf, - sizeof(buf), HID_FEATURE_REPORT, - HID_REQ_GET_REPORT); - if (ret != sizeof(buf)) { + CP2112_GPIO_CONFIG_LENGTH, HID_FEATURE_REPORT, + HID_REQ_GET_REPORT); + if (ret != CP2112_GPIO_CONFIG_LENGTH) { hid_err(hdev, "error requesting GPIO config: %d\n", ret); - return ret; + goto fail; } buf[1] |= 1 << offset; buf[2] = gpio_push_pull; - ret = hid_hw_raw_request(hdev, CP2112_GPIO_CONFIG, buf, sizeof(buf), - HID_FEATURE_REPORT, HID_REQ_SET_REPORT); + ret = hid_hw_raw_request(hdev, CP2112_GPIO_CONFIG, buf, + CP2112_GPIO_CONFIG_LENGTH, HID_FEATURE_REPORT, + HID_REQ_SET_REPORT); if (ret < 0) { hid_err(hdev, "error setting GPIO config: %d\n", ret); - return ret; + goto fail; } + spin_unlock_irqrestore(&dev->lock, flags); + /* * Set gpio value when output direction is already set, * as specified in AN495, Rev. 0.2, cpt. 4.4 @@ -262,6 +299,10 @@ static int cp2112_gpio_direction_output(struct gpio_chip *chip, cp2112_gpio_set(chip, offset, value); return 0; + +fail: + spin_unlock_irqrestore(&dev->lock, flags); + return ret < 0 ? ret : -EIO; } static int cp2112_hid_get(struct hid_device *hdev, unsigned char report_number, @@ -1007,6 +1048,17 @@ static int cp2112_probe(struct hid_device *hdev, const struct hid_device_id *id) struct cp2112_smbus_config_report config; int ret; + dev = devm_kzalloc(&hdev->dev, sizeof(*dev), GFP_KERNEL); + if (!dev) + return -ENOMEM; + + dev->in_out_buffer = devm_kzalloc(&hdev->dev, CP2112_REPORT_MAX_LENGTH, + GFP_KERNEL); + if (!dev->in_out_buffer) + return -ENOMEM; + + spin_lock_init(&dev->lock); + ret = hid_parse(hdev); if (ret) { hid_err(hdev, "parse failed\n"); @@ -1063,12 +1115,6 @@ static int cp2112_probe(struct hid_device *hdev, const struct hid_device_id *id) goto err_power_normal; } - dev = kzalloc(sizeof(*dev), GFP_KERNEL); - if (!dev) { - ret = -ENOMEM; - goto err_power_normal; - } - hid_set_drvdata(hdev, (void *)dev); dev->hdev = hdev; dev->adap.owner = THIS_MODULE; @@ -1087,7 +1133,7 @@ static int cp2112_probe(struct hid_device *hdev, const struct hid_device_id *id) if (ret) { hid_err(hdev, "error registering i2c adapter\n"); - goto err_free_dev; + goto err_power_normal; } hid_dbg(hdev, "adapter registered\n"); @@ -1123,8 +1169,6 @@ err_gpiochip_remove: gpiochip_remove(&dev->gc); err_free_i2c: i2c_del_adapter(&dev->adap); -err_free_dev: - kfree(dev); err_power_normal: hid_hw_power(hdev, PM_HINT_NORMAL); err_hid_close: @@ -1149,7 +1193,6 @@ static void cp2112_remove(struct hid_device *hdev) */ hid_hw_close(hdev); hid_hw_stop(hdev); - kfree(dev); } static int cp2112_raw_event(struct hid_device *hdev, struct hid_report *report, diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h index 6cfb5cacc253..575aa65436d1 100644 --- a/drivers/hid/hid-ids.h +++ b/drivers/hid/hid-ids.h @@ -179,6 +179,7 @@ #define USB_DEVICE_ID_ATEN_4PORTKVM 0x2205 #define USB_DEVICE_ID_ATEN_4PORTKVMC 0x2208 #define USB_DEVICE_ID_ATEN_CS682 0x2213 +#define USB_DEVICE_ID_ATEN_CS692 0x8021 #define USB_VENDOR_ID_ATMEL 0x03eb #define USB_DEVICE_ID_ATMEL_MULTITOUCH 0x211c diff --git a/drivers/hid/hid-lg.c b/drivers/hid/hid-lg.c index 76f644deb0a7..c5c5fbe9d605 100644 --- a/drivers/hid/hid-lg.c +++ b/drivers/hid/hid-lg.c @@ -756,11 +756,16 @@ static int lg_probe(struct hid_device *hdev, const struct hid_device_id *id) /* Setup wireless link with Logitech Wii wheel */ if (hdev->product == USB_DEVICE_ID_LOGITECH_WII_WHEEL) { - unsigned char buf[] = { 0x00, 0xAF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; + const unsigned char cbuf[] = { 0x00, 0xAF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; + u8 *buf = kmemdup(cbuf, sizeof(cbuf), GFP_KERNEL); - ret = hid_hw_raw_request(hdev, buf[0], buf, sizeof(buf), - HID_FEATURE_REPORT, HID_REQ_SET_REPORT); + if (!buf) { + ret = -ENOMEM; + goto err_free; + } + ret = hid_hw_raw_request(hdev, buf[0], buf, sizeof(cbuf), + HID_FEATURE_REPORT, HID_REQ_SET_REPORT); if (ret >= 0) { /* insert a little delay of 10 jiffies ~ 40ms */ wait_queue_head_t wait; @@ -772,9 +777,10 @@ static int lg_probe(struct hid_device *hdev, const struct hid_device_id *id) buf[1] = 0xB2; get_random_bytes(&buf[2], 2); - ret = hid_hw_raw_request(hdev, buf[0], buf, sizeof(buf), + ret = hid_hw_raw_request(hdev, buf[0], buf, sizeof(cbuf), HID_FEATURE_REPORT, HID_REQ_SET_REPORT); } + kfree(buf); } if (drv_data->quirks & LG_FF) diff --git a/drivers/hid/hid-magicmouse.c b/drivers/hid/hid-magicmouse.c index d6fa496d0ca2..20b40ad26325 100644 --- a/drivers/hid/hid-magicmouse.c +++ b/drivers/hid/hid-magicmouse.c @@ -493,7 +493,8 @@ static int magicmouse_input_configured(struct hid_device *hdev, static int magicmouse_probe(struct hid_device *hdev, const struct hid_device_id *id) { - __u8 feature[] = { 0xd7, 0x01 }; + const u8 feature[] = { 0xd7, 0x01 }; + u8 *buf; struct magicmouse_sc *msc; struct hid_report *report; int ret; @@ -544,6 +545,12 @@ static int magicmouse_probe(struct hid_device *hdev, } report->size = 6; + buf = kmemdup(feature, sizeof(feature), GFP_KERNEL); + if (!buf) { + ret = -ENOMEM; + goto err_stop_hw; + } + /* * Some devices repond with 'invalid report id' when feature * report switching it into multitouch mode is sent to it. @@ -552,8 +559,9 @@ static int magicmouse_probe(struct hid_device *hdev, * but there seems to be no other way of switching the mode. * Thus the super-ugly hacky success check below. */ - ret = hid_hw_raw_request(hdev, feature[0], feature, sizeof(feature), + ret = hid_hw_raw_request(hdev, buf[0], buf, sizeof(feature), HID_FEATURE_REPORT, HID_REQ_SET_REPORT); + kfree(buf); if (ret != -EIO && ret != sizeof(feature)) { hid_err(hdev, "unable to request touch data (%d)\n", ret); goto err_stop_hw; diff --git a/drivers/hid/hid-rmi.c b/drivers/hid/hid-rmi.c index 9cd2ca34a6be..be89bcbf6a71 100644 --- a/drivers/hid/hid-rmi.c +++ b/drivers/hid/hid-rmi.c @@ -188,10 +188,16 @@ static int rmi_set_page(struct hid_device *hdev, u8 page) static int rmi_set_mode(struct hid_device *hdev, u8 mode) { int ret; - u8 txbuf[2] = {RMI_SET_RMI_MODE_REPORT_ID, mode}; + const u8 txbuf[2] = {RMI_SET_RMI_MODE_REPORT_ID, mode}; + u8 *buf; - ret = hid_hw_raw_request(hdev, RMI_SET_RMI_MODE_REPORT_ID, txbuf, + buf = kmemdup(txbuf, sizeof(txbuf), GFP_KERNEL); + if (!buf) + return -ENOMEM; + + ret = hid_hw_raw_request(hdev, RMI_SET_RMI_MODE_REPORT_ID, buf, sizeof(txbuf), HID_FEATURE_REPORT, HID_REQ_SET_REPORT); + kfree(buf); if (ret < 0) { dev_err(&hdev->dev, "unable to set rmi mode to %d (%d)\n", mode, ret); diff --git a/drivers/hid/hid-sensor-custom.c b/drivers/hid/hid-sensor-custom.c index 5614fee82347..3a84aaf1418b 100644 --- a/drivers/hid/hid-sensor-custom.c +++ b/drivers/hid/hid-sensor-custom.c @@ -292,11 +292,11 @@ static ssize_t show_value(struct device *dev, struct device_attribute *attr, bool input = false; int value = 0; - if (sscanf(attr->attr.name, "feature-%d-%x-%s", &index, &usage, + if (sscanf(attr->attr.name, "feature-%x-%x-%s", &index, &usage, name) == 3) { feature = true; field_index = index + sensor_inst->input_field_count; - } else if (sscanf(attr->attr.name, "input-%d-%x-%s", &index, &usage, + } else if (sscanf(attr->attr.name, "input-%x-%x-%s", &index, &usage, name) == 3) { input = true; field_index = index; @@ -398,7 +398,7 @@ static ssize_t store_value(struct device *dev, struct device_attribute *attr, char name[HID_CUSTOM_NAME_LENGTH]; int value; - if (sscanf(attr->attr.name, "feature-%d-%x-%s", &index, &usage, + if (sscanf(attr->attr.name, "feature-%x-%x-%s", &index, &usage, name) == 3) { field_index = index + sensor_inst->input_field_count; } else diff --git a/drivers/hid/hid-sensor-hub.c b/drivers/hid/hid-sensor-hub.c index 658a607dc6d9..60875625cbdf 100644 --- a/drivers/hid/hid-sensor-hub.c +++ b/drivers/hid/hid-sensor-hub.c @@ -212,6 +212,7 @@ int sensor_hub_set_feature(struct hid_sensor_hub_device *hsdev, u32 report_id, __s32 value; int ret = 0; + memset(buffer, 0, buffer_size); mutex_lock(&data->mutex); report = sensor_hub_report(report_id, hsdev->hdev, HID_FEATURE_REPORT); if (!report || (field_index >= report->maxfield)) { @@ -251,6 +252,9 @@ int sensor_hub_get_feature(struct hid_sensor_hub_device *hsdev, u32 report_id, struct sensor_hub_data *data = hid_get_drvdata(hsdev->hdev); int report_size; int ret = 0; + u8 *val_ptr; + int buffer_index = 0; + int i; mutex_lock(&data->mutex); report = sensor_hub_report(report_id, hsdev->hdev, HID_FEATURE_REPORT); @@ -271,7 +275,17 @@ int sensor_hub_get_feature(struct hid_sensor_hub_device *hsdev, u32 report_id, goto done_proc; } ret = min(report_size, buffer_size); - memcpy(buffer, report->field[field_index]->value, ret); + + val_ptr = (u8 *)report->field[field_index]->value; + for (i = 0; i < report->field[field_index]->report_count; ++i) { + if (buffer_index >= ret) + break; + + memcpy(&((u8 *)buffer)[buffer_index], val_ptr, + report->field[field_index]->report_size / 8); + val_ptr += sizeof(__s32); + buffer_index += (report->field[field_index]->report_size / 8); + } done_proc: mutex_unlock(&data->mutex); diff --git a/drivers/hid/intel-ish-hid/ipc/ipc.c b/drivers/hid/intel-ish-hid/ipc/ipc.c index e2517c11e0ee..0c9ac4d5d850 100644 --- a/drivers/hid/intel-ish-hid/ipc/ipc.c +++ b/drivers/hid/intel-ish-hid/ipc/ipc.c @@ -638,6 +638,58 @@ eoi: } /** + * ish_disable_dma() - disable dma communication between host and ISHFW + * @dev: ishtp device pointer + * + * Clear the dma enable bit and wait for dma inactive. + * + * Return: 0 for success else error code. + */ +static int ish_disable_dma(struct ishtp_device *dev) +{ + unsigned int dma_delay; + + /* Clear the dma enable bit */ + ish_reg_write(dev, IPC_REG_ISH_RMP2, 0); + + /* wait for dma inactive */ + for (dma_delay = 0; dma_delay < MAX_DMA_DELAY && + _ish_read_fw_sts_reg(dev) & (IPC_ISH_IN_DMA); + dma_delay += 5) + mdelay(5); + + if (dma_delay >= MAX_DMA_DELAY) { + dev_err(dev->devc, + "Wait for DMA inactive timeout\n"); + return -EBUSY; + } + + return 0; +} + +/** + * ish_wakeup() - wakeup ishfw from waiting-for-host state + * @dev: ishtp device pointer + * + * Set the dma enable bit and send a void message to FW, + * it wil wakeup FW from waiting-for-host state. + */ +static void ish_wakeup(struct ishtp_device *dev) +{ + /* Set dma enable bit */ + ish_reg_write(dev, IPC_REG_ISH_RMP2, IPC_RMP2_DMA_ENABLED); + + /* + * Send 0 IPC message so that ISH FW wakes up if it was already + * asleep. + */ + ish_reg_write(dev, IPC_REG_HOST2ISH_DRBL, IPC_DRBL_BUSY_BIT); + + /* Flush writes to doorbell and REMAP2 */ + ish_reg_read(dev, IPC_REG_ISH_HOST_FWSTS); +} + +/** * _ish_hw_reset() - HW reset * @dev: ishtp device pointer * @@ -649,7 +701,6 @@ static int _ish_hw_reset(struct ishtp_device *dev) { struct pci_dev *pdev = dev->pdev; int rv; - unsigned int dma_delay; uint16_t csr; if (!pdev) @@ -664,15 +715,8 @@ static int _ish_hw_reset(struct ishtp_device *dev) return -EINVAL; } - /* Now trigger reset to FW */ - ish_reg_write(dev, IPC_REG_ISH_RMP2, 0); - - for (dma_delay = 0; dma_delay < MAX_DMA_DELAY && - _ish_read_fw_sts_reg(dev) & (IPC_ISH_IN_DMA); - dma_delay += 5) - mdelay(5); - - if (dma_delay >= MAX_DMA_DELAY) { + /* Disable dma communication between FW and host */ + if (ish_disable_dma(dev)) { dev_err(&pdev->dev, "Can't reset - stuck with DMA in-progress\n"); return -EBUSY; @@ -690,16 +734,8 @@ static int _ish_hw_reset(struct ishtp_device *dev) csr |= PCI_D0; pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, csr); - ish_reg_write(dev, IPC_REG_ISH_RMP2, IPC_RMP2_DMA_ENABLED); - - /* - * Send 0 IPC message so that ISH FW wakes up if it was already - * asleep - */ - ish_reg_write(dev, IPC_REG_HOST2ISH_DRBL, IPC_DRBL_BUSY_BIT); - - /* Flush writes to doorbell and REMAP2 */ - ish_reg_read(dev, IPC_REG_ISH_HOST_FWSTS); + /* Now we can enable ISH DMA operation and wakeup ISHFW */ + ish_wakeup(dev); return 0; } @@ -758,16 +794,9 @@ static int _ish_ipc_reset(struct ishtp_device *dev) int ish_hw_start(struct ishtp_device *dev) { ish_set_host_rdy(dev); - /* After that we can enable ISH DMA operation */ - ish_reg_write(dev, IPC_REG_ISH_RMP2, IPC_RMP2_DMA_ENABLED); - /* - * Send 0 IPC message so that ISH FW wakes up if it was already - * asleep - */ - ish_reg_write(dev, IPC_REG_HOST2ISH_DRBL, IPC_DRBL_BUSY_BIT); - /* Flush write to doorbell */ - ish_reg_read(dev, IPC_REG_ISH_HOST_FWSTS); + /* After that we can enable ISH DMA operation and wakeup ISHFW */ + ish_wakeup(dev); set_host_ready(dev); @@ -876,6 +905,21 @@ struct ishtp_device *ish_dev_init(struct pci_dev *pdev) */ void ish_device_disable(struct ishtp_device *dev) { + struct pci_dev *pdev = dev->pdev; + + if (!pdev) + return; + + /* Disable dma communication between FW and host */ + if (ish_disable_dma(dev)) { + dev_err(&pdev->dev, + "Can't reset - stuck with DMA in-progress\n"); + return; + } + + /* Put ISH to D3hot state for power saving */ + pci_set_power_state(pdev, PCI_D3hot); + dev->dev_state = ISHTP_DEV_DISABLED; ish_clr_host_rdy(dev); } diff --git a/drivers/hid/intel-ish-hid/ipc/pci-ish.c b/drivers/hid/intel-ish-hid/ipc/pci-ish.c index 42f0beeb09fd..20d647d2dd2c 100644 --- a/drivers/hid/intel-ish-hid/ipc/pci-ish.c +++ b/drivers/hid/intel-ish-hid/ipc/pci-ish.c @@ -146,7 +146,7 @@ static int ish_probe(struct pci_dev *pdev, const struct pci_device_id *ent) pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; /* request and enable interrupt */ - ret = request_irq(pdev->irq, ish_irq_handler, IRQF_NO_SUSPEND, + ret = request_irq(pdev->irq, ish_irq_handler, IRQF_SHARED, KBUILD_MODNAME, dev); if (ret) { dev_err(&pdev->dev, "ISH: request IRQ failure (%d)\n", @@ -202,6 +202,7 @@ static void ish_remove(struct pci_dev *pdev) kfree(ishtp_dev); } +#ifdef CONFIG_PM static struct device *ish_resume_device; /** @@ -293,7 +294,6 @@ static int ish_resume(struct device *device) return 0; } -#ifdef CONFIG_PM static const struct dev_pm_ops ish_pm_ops = { .suspend = ish_suspend, .resume = ish_resume, @@ -301,7 +301,7 @@ static const struct dev_pm_ops ish_pm_ops = { #define ISHTP_ISH_PM_OPS (&ish_pm_ops) #else #define ISHTP_ISH_PM_OPS NULL -#endif +#endif /* CONFIG_PM */ static struct pci_driver ish_driver = { .name = KBUILD_MODNAME, diff --git a/drivers/hid/usbhid/hid-quirks.c b/drivers/hid/usbhid/hid-quirks.c index 354d49ea36dd..e6cfd323babc 100644 --- a/drivers/hid/usbhid/hid-quirks.c +++ b/drivers/hid/usbhid/hid-quirks.c @@ -63,6 +63,7 @@ static const struct hid_blacklist { { USB_VENDOR_ID_ATEN, USB_DEVICE_ID_ATEN_4PORTKVM, HID_QUIRK_NOGET }, { USB_VENDOR_ID_ATEN, USB_DEVICE_ID_ATEN_4PORTKVMC, HID_QUIRK_NOGET }, { USB_VENDOR_ID_ATEN, USB_DEVICE_ID_ATEN_CS682, HID_QUIRK_NOGET }, + { USB_VENDOR_ID_ATEN, USB_DEVICE_ID_ATEN_CS692, HID_QUIRK_NOGET }, { USB_VENDOR_ID_CH, USB_DEVICE_ID_CH_FIGHTERSTICK, HID_QUIRK_NOGET }, { USB_VENDOR_ID_CH, USB_DEVICE_ID_CH_COMBATSTICK, HID_QUIRK_NOGET }, { USB_VENDOR_ID_CH, USB_DEVICE_ID_CH_FLIGHT_SIM_ECLIPSE_YOKE, HID_QUIRK_NOGET }, diff --git a/drivers/hv/vmbus_drv.c b/drivers/hv/vmbus_drv.c index a259e18d22d5..0276d2ef06ee 100644 --- a/drivers/hv/vmbus_drv.c +++ b/drivers/hv/vmbus_drv.c @@ -961,7 +961,7 @@ int vmbus_device_register(struct hv_device *child_device_obj) { int ret = 0; - dev_set_name(&child_device_obj->device, "vmbus-%pUl", + dev_set_name(&child_device_obj->device, "%pUl", child_device_obj->channel->offermsg.offer.if_instance.b); child_device_obj->device.bus = &hv_bus; diff --git a/drivers/hwmon/hwmon.c b/drivers/hwmon/hwmon.c index adae6848ffb2..a74c075a30ec 100644 --- a/drivers/hwmon/hwmon.c +++ b/drivers/hwmon/hwmon.c @@ -536,8 +536,10 @@ __hwmon_device_register(struct device *dev, const char *name, void *drvdata, hwdev->groups = devm_kcalloc(dev, ngroups, sizeof(*groups), GFP_KERNEL); - if (!hwdev->groups) - return ERR_PTR(-ENOMEM); + if (!hwdev->groups) { + err = -ENOMEM; + goto free_hwmon; + } attrs = __hwmon_create_attrs(dev, drvdata, chip); if (IS_ERR(attrs)) { diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index d223650a97e4..11edabf425ae 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -59,7 +59,6 @@ config I2C_CHARDEV config I2C_MUX tristate "I2C bus multiplexing support" - depends on HAS_IOMEM help Say Y here if you want the I2C core to support the ability to handle multiplexed I2C bus topologies, by presenting each diff --git a/drivers/i2c/busses/i2c-designware-core.c b/drivers/i2c/busses/i2c-designware-core.c index 11e866d05368..b403fa5ecf49 100644 --- a/drivers/i2c/busses/i2c-designware-core.c +++ b/drivers/i2c/busses/i2c-designware-core.c @@ -91,9 +91,7 @@ DW_IC_INTR_TX_ABRT | \ DW_IC_INTR_STOP_DET) -#define DW_IC_STATUS_ACTIVITY 0x1 -#define DW_IC_STATUS_TFE BIT(2) -#define DW_IC_STATUS_MST_ACTIVITY BIT(5) +#define DW_IC_STATUS_ACTIVITY 0x1 #define DW_IC_SDA_HOLD_RX_SHIFT 16 #define DW_IC_SDA_HOLD_RX_MASK GENMASK(23, DW_IC_SDA_HOLD_RX_SHIFT) @@ -478,25 +476,9 @@ static void i2c_dw_xfer_init(struct dw_i2c_dev *dev) { struct i2c_msg *msgs = dev->msgs; u32 ic_tar = 0; - bool enabled; - enabled = dw_readl(dev, DW_IC_ENABLE_STATUS) & 1; - - if (enabled) { - u32 ic_status; - - /* - * Only disable adapter if ic_tar and ic_con can't be - * dynamically updated - */ - ic_status = dw_readl(dev, DW_IC_STATUS); - if (!dev->dynamic_tar_update_enabled || - (ic_status & DW_IC_STATUS_MST_ACTIVITY) || - !(ic_status & DW_IC_STATUS_TFE)) { - __i2c_dw_enable_and_wait(dev, false); - enabled = false; - } - } + /* Disable the adapter */ + __i2c_dw_enable_and_wait(dev, false); /* if the slave address is ten bit address, enable 10BITADDR */ if (dev->dynamic_tar_update_enabled) { @@ -526,8 +508,8 @@ static void i2c_dw_xfer_init(struct dw_i2c_dev *dev) /* enforce disabled interrupts (due to HW issues) */ i2c_dw_disable_int(dev); - if (!enabled) - __i2c_dw_enable(dev, true); + /* Enable the adapter */ + __i2c_dw_enable(dev, true); /* Clear and enable interrupts */ dw_readl(dev, DW_IC_CLR_INTR); @@ -611,7 +593,7 @@ i2c_dw_xfer_msg(struct dw_i2c_dev *dev) if (msgs[dev->msg_write_idx].flags & I2C_M_RD) { /* avoid rx buffer overrun */ - if (rx_limit - dev->rx_outstanding <= 0) + if (dev->rx_outstanding >= dev->rx_fifo_depth) break; dw_writel(dev, cmd | 0x100, DW_IC_DATA_CMD); @@ -708,8 +690,7 @@ static int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev) } /* - * Prepare controller for a transaction and start transfer by calling - * i2c_dw_xfer_init() + * Prepare controller for a transaction and call i2c_dw_xfer_msg */ static int i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) @@ -752,13 +733,23 @@ i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) goto done; } + /* + * We must disable the adapter before returning and signaling the end + * of the current transfer. Otherwise the hardware might continue + * generating interrupts which in turn causes a race condition with + * the following transfer. Needs some more investigation if the + * additional interrupts are a hardware bug or this driver doesn't + * handle them correctly yet. + */ + __i2c_dw_enable(dev, false); + if (dev->msg_err) { ret = dev->msg_err; goto done; } /* no error */ - if (likely(!dev->cmd_err)) { + if (likely(!dev->cmd_err && !dev->status)) { ret = num; goto done; } @@ -768,6 +759,11 @@ i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) ret = i2c_dw_handle_tx_abort(dev); goto done; } + + if (dev->status) + dev_err(dev->dev, + "transfer terminated early - interrupt latency too high?\n"); + ret = -EIO; done: @@ -888,19 +884,9 @@ static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id) */ tx_aborted: - if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) - || dev->msg_err) { - /* - * We must disable interruts before returning and signaling - * the end of the current transfer. Otherwise the hardware - * might continue generating interrupts for non-existent - * transfers. - */ - i2c_dw_disable_int(dev); - dw_readl(dev, DW_IC_CLR_INTR); - + if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err) complete(&dev->cmd_complete); - } else if (unlikely(dev->accessor_flags & ACCESS_INTR_MASK)) { + else if (unlikely(dev->accessor_flags & ACCESS_INTR_MASK)) { /* workaround to trigger pending interrupt */ stat = dw_readl(dev, DW_IC_INTR_MASK); i2c_dw_disable_int(dev); diff --git a/drivers/i2c/busses/i2c-digicolor.c b/drivers/i2c/busses/i2c-digicolor.c index 49f2084f7bb5..50813a24c541 100644 --- a/drivers/i2c/busses/i2c-digicolor.c +++ b/drivers/i2c/busses/i2c-digicolor.c @@ -347,7 +347,7 @@ static int dc_i2c_probe(struct platform_device *pdev) ret = i2c_add_adapter(&i2c->adap); if (ret < 0) { - clk_unprepare(i2c->clk); + clk_disable_unprepare(i2c->clk); return ret; } diff --git a/drivers/i2c/busses/i2c-octeon-core.c b/drivers/i2c/busses/i2c-octeon-core.c index 419b54bfc7c7..5e63b17f935d 100644 --- a/drivers/i2c/busses/i2c-octeon-core.c +++ b/drivers/i2c/busses/i2c-octeon-core.c @@ -381,9 +381,7 @@ static int octeon_i2c_read(struct octeon_i2c *i2c, int target, if (result) return result; - data[i] = octeon_i2c_data_read(i2c, &result); - if (result) - return result; + data[i] = octeon_i2c_data_read(i2c); if (recv_len && i == 0) { if (data[i] > I2C_SMBUS_BLOCK_MAX + 1) return -EPROTO; diff --git a/drivers/i2c/busses/i2c-octeon-core.h b/drivers/i2c/busses/i2c-octeon-core.h index 1db7c835a454..87151ea74acd 100644 --- a/drivers/i2c/busses/i2c-octeon-core.h +++ b/drivers/i2c/busses/i2c-octeon-core.h @@ -5,7 +5,6 @@ #include <linux/i2c.h> #include <linux/i2c-smbus.h> #include <linux/io.h> -#include <linux/iopoll.h> #include <linux/kernel.h> #include <linux/pci.h> @@ -145,9 +144,9 @@ static inline void octeon_i2c_reg_write(struct octeon_i2c *i2c, u64 eop_reg, u8 u64 tmp; __raw_writeq(SW_TWSI_V | eop_reg | data, i2c->twsi_base + SW_TWSI(i2c)); - - readq_poll_timeout(i2c->twsi_base + SW_TWSI(i2c), tmp, tmp & SW_TWSI_V, - I2C_OCTEON_EVENT_WAIT, i2c->adap.timeout); + do { + tmp = __raw_readq(i2c->twsi_base + SW_TWSI(i2c)); + } while ((tmp & SW_TWSI_V) != 0); } #define octeon_i2c_ctl_write(i2c, val) \ @@ -164,28 +163,24 @@ static inline void octeon_i2c_reg_write(struct octeon_i2c *i2c, u64 eop_reg, u8 * * The I2C core registers are accessed indirectly via the SW_TWSI CSR. */ -static inline int octeon_i2c_reg_read(struct octeon_i2c *i2c, u64 eop_reg, - int *error) +static inline u8 octeon_i2c_reg_read(struct octeon_i2c *i2c, u64 eop_reg) { u64 tmp; - int ret; __raw_writeq(SW_TWSI_V | eop_reg | SW_TWSI_R, i2c->twsi_base + SW_TWSI(i2c)); + do { + tmp = __raw_readq(i2c->twsi_base + SW_TWSI(i2c)); + } while ((tmp & SW_TWSI_V) != 0); - ret = readq_poll_timeout(i2c->twsi_base + SW_TWSI(i2c), tmp, - tmp & SW_TWSI_V, I2C_OCTEON_EVENT_WAIT, - i2c->adap.timeout); - if (error) - *error = ret; return tmp & 0xFF; } #define octeon_i2c_ctl_read(i2c) \ - octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_CTL, NULL) -#define octeon_i2c_data_read(i2c, error) \ - octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_DATA, error) + octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_CTL) +#define octeon_i2c_data_read(i2c) \ + octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_DATA) #define octeon_i2c_stat_read(i2c) \ - octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_STAT, NULL) + octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_STAT) /** * octeon_i2c_read_int - read the TWSI_INT register diff --git a/drivers/i2c/muxes/Kconfig b/drivers/i2c/muxes/Kconfig index e280c8ecc0b5..96de9ce5669b 100644 --- a/drivers/i2c/muxes/Kconfig +++ b/drivers/i2c/muxes/Kconfig @@ -63,6 +63,7 @@ config I2C_MUX_PINCTRL config I2C_MUX_REG tristate "Register-based I2C multiplexer" + depends on HAS_IOMEM help If you say yes to this option, support will be included for a register based I2C multiplexer. This driver provides access to diff --git a/drivers/i2c/muxes/i2c-demux-pinctrl.c b/drivers/i2c/muxes/i2c-demux-pinctrl.c index b3893f6282ba..3e6fe1760d82 100644 --- a/drivers/i2c/muxes/i2c-demux-pinctrl.c +++ b/drivers/i2c/muxes/i2c-demux-pinctrl.c @@ -69,10 +69,28 @@ static int i2c_demux_activate_master(struct i2c_demux_pinctrl_priv *priv, u32 ne goto err_with_revert; } - p = devm_pinctrl_get_select(adap->dev.parent, priv->bus_name); + /* + * Check if there are pinctrl states at all. Note: we cant' use + * devm_pinctrl_get_select() because we need to distinguish between + * the -ENODEV from devm_pinctrl_get() and pinctrl_lookup_state(). + */ + p = devm_pinctrl_get(adap->dev.parent); if (IS_ERR(p)) { ret = PTR_ERR(p); - goto err_with_put; + /* continue if just no pinctrl states (e.g. i2c-gpio), otherwise exit */ + if (ret != -ENODEV) + goto err_with_put; + } else { + /* there are states. check and use them */ + struct pinctrl_state *s = pinctrl_lookup_state(p, priv->bus_name); + + if (IS_ERR(s)) { + ret = PTR_ERR(s); + goto err_with_put; + } + ret = pinctrl_select_state(p, s); + if (ret < 0) + goto err_with_put; } priv->chan[new_chan].parent_adap = adap; diff --git a/drivers/i2c/muxes/i2c-mux-pca954x.c b/drivers/i2c/muxes/i2c-mux-pca954x.c index 1091346f2480..8bc3d36d2837 100644 --- a/drivers/i2c/muxes/i2c-mux-pca954x.c +++ b/drivers/i2c/muxes/i2c-mux-pca954x.c @@ -268,9 +268,9 @@ static int pca954x_probe(struct i2c_client *client, /* discard unconfigured channels */ break; idle_disconnect_pd = pdata->modes[num].deselect_on_exit; - data->deselect |= (idle_disconnect_pd - || idle_disconnect_dt) << num; } + data->deselect |= (idle_disconnect_pd || + idle_disconnect_dt) << num; ret = i2c_mux_add_adapter(muxc, force, num, class); diff --git a/drivers/iio/accel/st_accel_core.c b/drivers/iio/accel/st_accel_core.c index da3fb069ec5c..ce69048c88e9 100644 --- a/drivers/iio/accel/st_accel_core.c +++ b/drivers/iio/accel/st_accel_core.c @@ -743,8 +743,8 @@ static int st_accel_read_raw(struct iio_dev *indio_dev, return IIO_VAL_INT; case IIO_CHAN_INFO_SCALE: - *val = 0; - *val2 = adata->current_fullscale->gain; + *val = adata->current_fullscale->gain / 1000000; + *val2 = adata->current_fullscale->gain % 1000000; return IIO_VAL_INT_PLUS_MICRO; case IIO_CHAN_INFO_SAMP_FREQ: *val = adata->odr; @@ -763,9 +763,13 @@ static int st_accel_write_raw(struct iio_dev *indio_dev, int err; switch (mask) { - case IIO_CHAN_INFO_SCALE: - err = st_sensors_set_fullscale_by_gain(indio_dev, val2); + case IIO_CHAN_INFO_SCALE: { + int gain; + + gain = val * 1000000 + val2; + err = st_sensors_set_fullscale_by_gain(indio_dev, gain); break; + } case IIO_CHAN_INFO_SAMP_FREQ: if (val2) return -EINVAL; diff --git a/drivers/iio/common/hid-sensors/hid-sensor-attributes.c b/drivers/iio/common/hid-sensors/hid-sensor-attributes.c index dc33c1dd5191..b5beea53d6f6 100644 --- a/drivers/iio/common/hid-sensors/hid-sensor-attributes.c +++ b/drivers/iio/common/hid-sensors/hid-sensor-attributes.c @@ -30,26 +30,26 @@ static struct { u32 usage_id; int unit; /* 0 for default others from HID sensor spec */ int scale_val0; /* scale, whole number */ - int scale_val1; /* scale, fraction in micros */ + int scale_val1; /* scale, fraction in nanos */ } unit_conversion[] = { - {HID_USAGE_SENSOR_ACCEL_3D, 0, 9, 806650}, + {HID_USAGE_SENSOR_ACCEL_3D, 0, 9, 806650000}, {HID_USAGE_SENSOR_ACCEL_3D, HID_USAGE_SENSOR_UNITS_METERS_PER_SEC_SQRD, 1, 0}, {HID_USAGE_SENSOR_ACCEL_3D, - HID_USAGE_SENSOR_UNITS_G, 9, 806650}, + HID_USAGE_SENSOR_UNITS_G, 9, 806650000}, - {HID_USAGE_SENSOR_GYRO_3D, 0, 0, 17453}, + {HID_USAGE_SENSOR_GYRO_3D, 0, 0, 17453293}, {HID_USAGE_SENSOR_GYRO_3D, HID_USAGE_SENSOR_UNITS_RADIANS_PER_SECOND, 1, 0}, {HID_USAGE_SENSOR_GYRO_3D, - HID_USAGE_SENSOR_UNITS_DEGREES_PER_SECOND, 0, 17453}, + HID_USAGE_SENSOR_UNITS_DEGREES_PER_SECOND, 0, 17453293}, - {HID_USAGE_SENSOR_COMPASS_3D, 0, 0, 1000}, + {HID_USAGE_SENSOR_COMPASS_3D, 0, 0, 1000000}, {HID_USAGE_SENSOR_COMPASS_3D, HID_USAGE_SENSOR_UNITS_GAUSS, 1, 0}, - {HID_USAGE_SENSOR_INCLINOMETER_3D, 0, 0, 17453}, + {HID_USAGE_SENSOR_INCLINOMETER_3D, 0, 0, 17453293}, {HID_USAGE_SENSOR_INCLINOMETER_3D, - HID_USAGE_SENSOR_UNITS_DEGREES, 0, 17453}, + HID_USAGE_SENSOR_UNITS_DEGREES, 0, 17453293}, {HID_USAGE_SENSOR_INCLINOMETER_3D, HID_USAGE_SENSOR_UNITS_RADIANS, 1, 0}, @@ -57,7 +57,7 @@ static struct { {HID_USAGE_SENSOR_ALS, HID_USAGE_SENSOR_UNITS_LUX, 1, 0}, {HID_USAGE_SENSOR_PRESSURE, 0, 100, 0}, - {HID_USAGE_SENSOR_PRESSURE, HID_USAGE_SENSOR_UNITS_PASCAL, 0, 1000}, + {HID_USAGE_SENSOR_PRESSURE, HID_USAGE_SENSOR_UNITS_PASCAL, 0, 1000000}, }; static int pow_10(unsigned power) @@ -266,15 +266,15 @@ EXPORT_SYMBOL(hid_sensor_write_raw_hyst_value); /* * This fuction applies the unit exponent to the scale. * For example: - * 9.806650 ->exp:2-> val0[980]val1[665000] - * 9.000806 ->exp:2-> val0[900]val1[80600] - * 0.174535 ->exp:2-> val0[17]val1[453500] - * 1.001745 ->exp:0-> val0[1]val1[1745] - * 1.001745 ->exp:2-> val0[100]val1[174500] - * 1.001745 ->exp:4-> val0[10017]val1[450000] - * 9.806650 ->exp:-2-> val0[0]val1[98066] + * 9.806650000 ->exp:2-> val0[980]val1[665000000] + * 9.000806000 ->exp:2-> val0[900]val1[80600000] + * 0.174535293 ->exp:2-> val0[17]val1[453529300] + * 1.001745329 ->exp:0-> val0[1]val1[1745329] + * 1.001745329 ->exp:2-> val0[100]val1[174532900] + * 1.001745329 ->exp:4-> val0[10017]val1[453290000] + * 9.806650000 ->exp:-2-> val0[0]val1[98066500] */ -static void adjust_exponent_micro(int *val0, int *val1, int scale0, +static void adjust_exponent_nano(int *val0, int *val1, int scale0, int scale1, int exp) { int i; @@ -285,32 +285,32 @@ static void adjust_exponent_micro(int *val0, int *val1, int scale0, if (exp > 0) { *val0 = scale0 * pow_10(exp); res = 0; - if (exp > 6) { + if (exp > 9) { *val1 = 0; return; } for (i = 0; i < exp; ++i) { - x = scale1 / pow_10(5 - i); + x = scale1 / pow_10(8 - i); res += (pow_10(exp - 1 - i) * x); - scale1 = scale1 % pow_10(5 - i); + scale1 = scale1 % pow_10(8 - i); } *val0 += res; *val1 = scale1 * pow_10(exp); } else if (exp < 0) { exp = abs(exp); - if (exp > 6) { + if (exp > 9) { *val0 = *val1 = 0; return; } *val0 = scale0 / pow_10(exp); rem = scale0 % pow_10(exp); res = 0; - for (i = 0; i < (6 - exp); ++i) { - x = scale1 / pow_10(5 - i); - res += (pow_10(5 - exp - i) * x); - scale1 = scale1 % pow_10(5 - i); + for (i = 0; i < (9 - exp); ++i) { + x = scale1 / pow_10(8 - i); + res += (pow_10(8 - exp - i) * x); + scale1 = scale1 % pow_10(8 - i); } - *val1 = rem * pow_10(6 - exp) + res; + *val1 = rem * pow_10(9 - exp) + res; } else { *val0 = scale0; *val1 = scale1; @@ -332,14 +332,14 @@ int hid_sensor_format_scale(u32 usage_id, unit_conversion[i].unit == attr_info->units) { exp = hid_sensor_convert_exponent( attr_info->unit_expo); - adjust_exponent_micro(val0, val1, + adjust_exponent_nano(val0, val1, unit_conversion[i].scale_val0, unit_conversion[i].scale_val1, exp); break; } } - return IIO_VAL_INT_PLUS_MICRO; + return IIO_VAL_INT_PLUS_NANO; } EXPORT_SYMBOL(hid_sensor_format_scale); diff --git a/drivers/iio/common/st_sensors/st_sensors_core.c b/drivers/iio/common/st_sensors/st_sensors_core.c index 285a64a589d7..975a1f19f747 100644 --- a/drivers/iio/common/st_sensors/st_sensors_core.c +++ b/drivers/iio/common/st_sensors/st_sensors_core.c @@ -612,7 +612,7 @@ EXPORT_SYMBOL(st_sensors_sysfs_sampling_frequency_avail); ssize_t st_sensors_sysfs_scale_avail(struct device *dev, struct device_attribute *attr, char *buf) { - int i, len = 0; + int i, len = 0, q, r; struct iio_dev *indio_dev = dev_get_drvdata(dev); struct st_sensor_data *sdata = iio_priv(indio_dev); @@ -621,8 +621,10 @@ ssize_t st_sensors_sysfs_scale_avail(struct device *dev, if (sdata->sensor_settings->fs.fs_avl[i].num == 0) break; - len += scnprintf(buf + len, PAGE_SIZE - len, "0.%06u ", - sdata->sensor_settings->fs.fs_avl[i].gain); + q = sdata->sensor_settings->fs.fs_avl[i].gain / 1000000; + r = sdata->sensor_settings->fs.fs_avl[i].gain % 1000000; + + len += scnprintf(buf + len, PAGE_SIZE - len, "%u.%06u ", q, r); } mutex_unlock(&indio_dev->mlock); buf[len - 1] = '\n'; diff --git a/drivers/iio/orientation/hid-sensor-rotation.c b/drivers/iio/orientation/hid-sensor-rotation.c index b98b9d94d184..a97e802ca523 100644 --- a/drivers/iio/orientation/hid-sensor-rotation.c +++ b/drivers/iio/orientation/hid-sensor-rotation.c @@ -335,6 +335,7 @@ static struct platform_driver hid_dev_rot_platform_driver = { .id_table = hid_dev_rot_ids, .driver = { .name = KBUILD_MODNAME, + .pm = &hid_sensor_pm_ops, }, .probe = hid_dev_rot_probe, .remove = hid_dev_rot_remove, diff --git a/drivers/iio/temperature/maxim_thermocouple.c b/drivers/iio/temperature/maxim_thermocouple.c index 066161a4bccd..f962f31a5eb2 100644 --- a/drivers/iio/temperature/maxim_thermocouple.c +++ b/drivers/iio/temperature/maxim_thermocouple.c @@ -136,6 +136,8 @@ static int maxim_thermocouple_read(struct maxim_thermocouple_data *data, ret = spi_read(data->spi, (void *)&buf32, storage_bytes); *val = be32_to_cpu(buf32); break; + default: + ret = -EINVAL; } if (ret) diff --git a/drivers/infiniband/core/addr.c b/drivers/infiniband/core/addr.c index b136d3acc5bd..0f58f46dbad7 100644 --- a/drivers/infiniband/core/addr.c +++ b/drivers/infiniband/core/addr.c @@ -699,13 +699,16 @@ EXPORT_SYMBOL(rdma_addr_cancel); struct resolve_cb_context { struct rdma_dev_addr *addr; struct completion comp; + int status; }; static void resolve_cb(int status, struct sockaddr *src_addr, struct rdma_dev_addr *addr, void *context) { - memcpy(((struct resolve_cb_context *)context)->addr, addr, sizeof(struct - rdma_dev_addr)); + if (!status) + memcpy(((struct resolve_cb_context *)context)->addr, + addr, sizeof(struct rdma_dev_addr)); + ((struct resolve_cb_context *)context)->status = status; complete(&((struct resolve_cb_context *)context)->comp); } @@ -743,6 +746,10 @@ int rdma_addr_find_l2_eth_by_grh(const union ib_gid *sgid, wait_for_completion(&ctx.comp); + ret = ctx.status; + if (ret) + return ret; + memcpy(dmac, dev_addr.dst_dev_addr, ETH_ALEN); dev = dev_get_by_index(&init_net, dev_addr.bound_dev_if); if (!dev) diff --git a/drivers/infiniband/core/cm.c b/drivers/infiniband/core/cm.c index c99525512b34..71c7c4c328ef 100644 --- a/drivers/infiniband/core/cm.c +++ b/drivers/infiniband/core/cm.c @@ -80,6 +80,8 @@ static struct ib_cm { __be32 random_id_operand; struct list_head timewait_list; struct workqueue_struct *wq; + /* Sync on cm change port state */ + spinlock_t state_lock; } cm; /* Counter indexes ordered by attribute ID */ @@ -161,6 +163,8 @@ struct cm_port { struct ib_mad_agent *mad_agent; struct kobject port_obj; u8 port_num; + struct list_head cm_priv_prim_list; + struct list_head cm_priv_altr_list; struct cm_counter_group counter_group[CM_COUNTER_GROUPS]; }; @@ -241,6 +245,12 @@ struct cm_id_private { u8 service_timeout; u8 target_ack_delay; + struct list_head prim_list; + struct list_head altr_list; + /* Indicates that the send port mad is registered and av is set */ + int prim_send_port_not_ready; + int altr_send_port_not_ready; + struct list_head work_list; atomic_t work_count; }; @@ -259,20 +269,47 @@ static int cm_alloc_msg(struct cm_id_private *cm_id_priv, struct ib_mad_agent *mad_agent; struct ib_mad_send_buf *m; struct ib_ah *ah; + struct cm_av *av; + unsigned long flags, flags2; + int ret = 0; + /* don't let the port to be released till the agent is down */ + spin_lock_irqsave(&cm.state_lock, flags2); + spin_lock_irqsave(&cm.lock, flags); + if (!cm_id_priv->prim_send_port_not_ready) + av = &cm_id_priv->av; + else if (!cm_id_priv->altr_send_port_not_ready && + (cm_id_priv->alt_av.port)) + av = &cm_id_priv->alt_av; + else { + pr_info("%s: not valid CM id\n", __func__); + ret = -ENODEV; + spin_unlock_irqrestore(&cm.lock, flags); + goto out; + } + spin_unlock_irqrestore(&cm.lock, flags); + /* Make sure the port haven't released the mad yet */ mad_agent = cm_id_priv->av.port->mad_agent; - ah = ib_create_ah(mad_agent->qp->pd, &cm_id_priv->av.ah_attr); - if (IS_ERR(ah)) - return PTR_ERR(ah); + if (!mad_agent) { + pr_info("%s: not a valid MAD agent\n", __func__); + ret = -ENODEV; + goto out; + } + ah = ib_create_ah(mad_agent->qp->pd, &av->ah_attr); + if (IS_ERR(ah)) { + ret = PTR_ERR(ah); + goto out; + } m = ib_create_send_mad(mad_agent, cm_id_priv->id.remote_cm_qpn, - cm_id_priv->av.pkey_index, + av->pkey_index, 0, IB_MGMT_MAD_HDR, IB_MGMT_MAD_DATA, GFP_ATOMIC, IB_MGMT_BASE_VERSION); if (IS_ERR(m)) { ib_destroy_ah(ah); - return PTR_ERR(m); + ret = PTR_ERR(m); + goto out; } /* Timeout set by caller if response is expected. */ @@ -282,7 +319,10 @@ static int cm_alloc_msg(struct cm_id_private *cm_id_priv, atomic_inc(&cm_id_priv->refcount); m->context[0] = cm_id_priv; *msg = m; - return 0; + +out: + spin_unlock_irqrestore(&cm.state_lock, flags2); + return ret; } static int cm_alloc_response_msg(struct cm_port *port, @@ -352,7 +392,8 @@ static void cm_init_av_for_response(struct cm_port *port, struct ib_wc *wc, grh, &av->ah_attr); } -static int cm_init_av_by_path(struct ib_sa_path_rec *path, struct cm_av *av) +static int cm_init_av_by_path(struct ib_sa_path_rec *path, struct cm_av *av, + struct cm_id_private *cm_id_priv) { struct cm_device *cm_dev; struct cm_port *port = NULL; @@ -387,7 +428,17 @@ static int cm_init_av_by_path(struct ib_sa_path_rec *path, struct cm_av *av) &av->ah_attr); av->timeout = path->packet_life_time + 1; - return 0; + spin_lock_irqsave(&cm.lock, flags); + if (&cm_id_priv->av == av) + list_add_tail(&cm_id_priv->prim_list, &port->cm_priv_prim_list); + else if (&cm_id_priv->alt_av == av) + list_add_tail(&cm_id_priv->altr_list, &port->cm_priv_altr_list); + else + ret = -EINVAL; + + spin_unlock_irqrestore(&cm.lock, flags); + + return ret; } static int cm_alloc_id(struct cm_id_private *cm_id_priv) @@ -677,6 +728,8 @@ struct ib_cm_id *ib_create_cm_id(struct ib_device *device, spin_lock_init(&cm_id_priv->lock); init_completion(&cm_id_priv->comp); INIT_LIST_HEAD(&cm_id_priv->work_list); + INIT_LIST_HEAD(&cm_id_priv->prim_list); + INIT_LIST_HEAD(&cm_id_priv->altr_list); atomic_set(&cm_id_priv->work_count, -1); atomic_set(&cm_id_priv->refcount, 1); return &cm_id_priv->id; @@ -892,6 +945,15 @@ retest: break; } + spin_lock_irq(&cm.lock); + if (!list_empty(&cm_id_priv->altr_list) && + (!cm_id_priv->altr_send_port_not_ready)) + list_del(&cm_id_priv->altr_list); + if (!list_empty(&cm_id_priv->prim_list) && + (!cm_id_priv->prim_send_port_not_ready)) + list_del(&cm_id_priv->prim_list); + spin_unlock_irq(&cm.lock); + cm_free_id(cm_id->local_id); cm_deref_id(cm_id_priv); wait_for_completion(&cm_id_priv->comp); @@ -1192,12 +1254,13 @@ int ib_send_cm_req(struct ib_cm_id *cm_id, goto out; } - ret = cm_init_av_by_path(param->primary_path, &cm_id_priv->av); + ret = cm_init_av_by_path(param->primary_path, &cm_id_priv->av, + cm_id_priv); if (ret) goto error1; if (param->alternate_path) { ret = cm_init_av_by_path(param->alternate_path, - &cm_id_priv->alt_av); + &cm_id_priv->alt_av, cm_id_priv); if (ret) goto error1; } @@ -1653,7 +1716,8 @@ static int cm_req_handler(struct cm_work *work) dev_put(gid_attr.ndev); } work->path[0].gid_type = gid_attr.gid_type; - ret = cm_init_av_by_path(&work->path[0], &cm_id_priv->av); + ret = cm_init_av_by_path(&work->path[0], &cm_id_priv->av, + cm_id_priv); } if (ret) { int err = ib_get_cached_gid(work->port->cm_dev->ib_device, @@ -1672,7 +1736,8 @@ static int cm_req_handler(struct cm_work *work) goto rejected; } if (req_msg->alt_local_lid) { - ret = cm_init_av_by_path(&work->path[1], &cm_id_priv->alt_av); + ret = cm_init_av_by_path(&work->path[1], &cm_id_priv->alt_av, + cm_id_priv); if (ret) { ib_send_cm_rej(cm_id, IB_CM_REJ_INVALID_ALT_GID, &work->path[0].sgid, @@ -2727,7 +2792,8 @@ int ib_send_cm_lap(struct ib_cm_id *cm_id, goto out; } - ret = cm_init_av_by_path(alternate_path, &cm_id_priv->alt_av); + ret = cm_init_av_by_path(alternate_path, &cm_id_priv->alt_av, + cm_id_priv); if (ret) goto out; cm_id_priv->alt_av.timeout = @@ -2839,7 +2905,8 @@ static int cm_lap_handler(struct cm_work *work) cm_init_av_for_response(work->port, work->mad_recv_wc->wc, work->mad_recv_wc->recv_buf.grh, &cm_id_priv->av); - cm_init_av_by_path(param->alternate_path, &cm_id_priv->alt_av); + cm_init_av_by_path(param->alternate_path, &cm_id_priv->alt_av, + cm_id_priv); ret = atomic_inc_and_test(&cm_id_priv->work_count); if (!ret) list_add_tail(&work->list, &cm_id_priv->work_list); @@ -3031,7 +3098,7 @@ int ib_send_cm_sidr_req(struct ib_cm_id *cm_id, return -EINVAL; cm_id_priv = container_of(cm_id, struct cm_id_private, id); - ret = cm_init_av_by_path(param->path, &cm_id_priv->av); + ret = cm_init_av_by_path(param->path, &cm_id_priv->av, cm_id_priv); if (ret) goto out; @@ -3468,7 +3535,9 @@ out: static int cm_migrate(struct ib_cm_id *cm_id) { struct cm_id_private *cm_id_priv; + struct cm_av tmp_av; unsigned long flags; + int tmp_send_port_not_ready; int ret = 0; cm_id_priv = container_of(cm_id, struct cm_id_private, id); @@ -3477,7 +3546,14 @@ static int cm_migrate(struct ib_cm_id *cm_id) (cm_id->lap_state == IB_CM_LAP_UNINIT || cm_id->lap_state == IB_CM_LAP_IDLE)) { cm_id->lap_state = IB_CM_LAP_IDLE; + /* Swap address vector */ + tmp_av = cm_id_priv->av; cm_id_priv->av = cm_id_priv->alt_av; + cm_id_priv->alt_av = tmp_av; + /* Swap port send ready state */ + tmp_send_port_not_ready = cm_id_priv->prim_send_port_not_ready; + cm_id_priv->prim_send_port_not_ready = cm_id_priv->altr_send_port_not_ready; + cm_id_priv->altr_send_port_not_ready = tmp_send_port_not_ready; } else ret = -EINVAL; spin_unlock_irqrestore(&cm_id_priv->lock, flags); @@ -3888,6 +3964,9 @@ static void cm_add_one(struct ib_device *ib_device) port->cm_dev = cm_dev; port->port_num = i; + INIT_LIST_HEAD(&port->cm_priv_prim_list); + INIT_LIST_HEAD(&port->cm_priv_altr_list); + ret = cm_create_port_fs(port); if (ret) goto error1; @@ -3945,6 +4024,8 @@ static void cm_remove_one(struct ib_device *ib_device, void *client_data) { struct cm_device *cm_dev = client_data; struct cm_port *port; + struct cm_id_private *cm_id_priv; + struct ib_mad_agent *cur_mad_agent; struct ib_port_modify port_modify = { .clr_port_cap_mask = IB_PORT_CM_SUP }; @@ -3968,15 +4049,27 @@ static void cm_remove_one(struct ib_device *ib_device, void *client_data) port = cm_dev->port[i-1]; ib_modify_port(ib_device, port->port_num, 0, &port_modify); + /* Mark all the cm_id's as not valid */ + spin_lock_irq(&cm.lock); + list_for_each_entry(cm_id_priv, &port->cm_priv_altr_list, altr_list) + cm_id_priv->altr_send_port_not_ready = 1; + list_for_each_entry(cm_id_priv, &port->cm_priv_prim_list, prim_list) + cm_id_priv->prim_send_port_not_ready = 1; + spin_unlock_irq(&cm.lock); /* * We flush the queue here after the going_down set, this * verify that no new works will be queued in the recv handler, * after that we can call the unregister_mad_agent */ flush_workqueue(cm.wq); - ib_unregister_mad_agent(port->mad_agent); + spin_lock_irq(&cm.state_lock); + cur_mad_agent = port->mad_agent; + port->mad_agent = NULL; + spin_unlock_irq(&cm.state_lock); + ib_unregister_mad_agent(cur_mad_agent); cm_remove_port_fs(port); } + device_unregister(cm_dev->device); kfree(cm_dev); } @@ -3989,6 +4082,7 @@ static int __init ib_cm_init(void) INIT_LIST_HEAD(&cm.device_list); rwlock_init(&cm.device_lock); spin_lock_init(&cm.lock); + spin_lock_init(&cm.state_lock); cm.listen_service_table = RB_ROOT; cm.listen_service_id = be64_to_cpu(IB_CM_ASSIGN_SERVICE_ID); cm.remote_id_table = RB_ROOT; diff --git a/drivers/infiniband/core/cma.c b/drivers/infiniband/core/cma.c index 36bf50ebb187..2a6fc47a1dfb 100644 --- a/drivers/infiniband/core/cma.c +++ b/drivers/infiniband/core/cma.c @@ -1094,47 +1094,47 @@ static void cma_save_ib_info(struct sockaddr *src_addr, } } -static void cma_save_ip4_info(struct sockaddr *src_addr, - struct sockaddr *dst_addr, +static void cma_save_ip4_info(struct sockaddr_in *src_addr, + struct sockaddr_in *dst_addr, struct cma_hdr *hdr, __be16 local_port) { - struct sockaddr_in *ip4; - if (src_addr) { - ip4 = (struct sockaddr_in *)src_addr; - ip4->sin_family = AF_INET; - ip4->sin_addr.s_addr = hdr->dst_addr.ip4.addr; - ip4->sin_port = local_port; + *src_addr = (struct sockaddr_in) { + .sin_family = AF_INET, + .sin_addr.s_addr = hdr->dst_addr.ip4.addr, + .sin_port = local_port, + }; } if (dst_addr) { - ip4 = (struct sockaddr_in *)dst_addr; - ip4->sin_family = AF_INET; - ip4->sin_addr.s_addr = hdr->src_addr.ip4.addr; - ip4->sin_port = hdr->port; + *dst_addr = (struct sockaddr_in) { + .sin_family = AF_INET, + .sin_addr.s_addr = hdr->src_addr.ip4.addr, + .sin_port = hdr->port, + }; } } -static void cma_save_ip6_info(struct sockaddr *src_addr, - struct sockaddr *dst_addr, +static void cma_save_ip6_info(struct sockaddr_in6 *src_addr, + struct sockaddr_in6 *dst_addr, struct cma_hdr *hdr, __be16 local_port) { - struct sockaddr_in6 *ip6; - if (src_addr) { - ip6 = (struct sockaddr_in6 *)src_addr; - ip6->sin6_family = AF_INET6; - ip6->sin6_addr = hdr->dst_addr.ip6; - ip6->sin6_port = local_port; + *src_addr = (struct sockaddr_in6) { + .sin6_family = AF_INET6, + .sin6_addr = hdr->dst_addr.ip6, + .sin6_port = local_port, + }; } if (dst_addr) { - ip6 = (struct sockaddr_in6 *)dst_addr; - ip6->sin6_family = AF_INET6; - ip6->sin6_addr = hdr->src_addr.ip6; - ip6->sin6_port = hdr->port; + *dst_addr = (struct sockaddr_in6) { + .sin6_family = AF_INET6, + .sin6_addr = hdr->src_addr.ip6, + .sin6_port = hdr->port, + }; } } @@ -1159,10 +1159,12 @@ static int cma_save_ip_info(struct sockaddr *src_addr, switch (cma_get_ip_ver(hdr)) { case 4: - cma_save_ip4_info(src_addr, dst_addr, hdr, port); + cma_save_ip4_info((struct sockaddr_in *)src_addr, + (struct sockaddr_in *)dst_addr, hdr, port); break; case 6: - cma_save_ip6_info(src_addr, dst_addr, hdr, port); + cma_save_ip6_info((struct sockaddr_in6 *)src_addr, + (struct sockaddr_in6 *)dst_addr, hdr, port); break; default: return -EAFNOSUPPORT; @@ -2436,6 +2438,18 @@ static int iboe_tos_to_sl(struct net_device *ndev, int tos) return 0; } +static enum ib_gid_type cma_route_gid_type(enum rdma_network_type network_type, + unsigned long supported_gids, + enum ib_gid_type default_gid) +{ + if ((network_type == RDMA_NETWORK_IPV4 || + network_type == RDMA_NETWORK_IPV6) && + test_bit(IB_GID_TYPE_ROCE_UDP_ENCAP, &supported_gids)) + return IB_GID_TYPE_ROCE_UDP_ENCAP; + + return default_gid; +} + static int cma_resolve_iboe_route(struct rdma_id_private *id_priv) { struct rdma_route *route = &id_priv->id.route; @@ -2461,6 +2475,8 @@ static int cma_resolve_iboe_route(struct rdma_id_private *id_priv) route->num_paths = 1; if (addr->dev_addr.bound_dev_if) { + unsigned long supported_gids; + ndev = dev_get_by_index(&init_net, addr->dev_addr.bound_dev_if); if (!ndev) { ret = -ENODEV; @@ -2484,7 +2500,12 @@ static int cma_resolve_iboe_route(struct rdma_id_private *id_priv) route->path_rec->net = &init_net; route->path_rec->ifindex = ndev->ifindex; - route->path_rec->gid_type = id_priv->gid_type; + supported_gids = roce_gid_type_mask_support(id_priv->id.device, + id_priv->id.port_num); + route->path_rec->gid_type = + cma_route_gid_type(addr->dev_addr.network, + supported_gids, + id_priv->gid_type); } if (!ndev) { ret = -ENODEV; diff --git a/drivers/infiniband/core/umem.c b/drivers/infiniband/core/umem.c index 224ad274ea0b..84b4eff90395 100644 --- a/drivers/infiniband/core/umem.c +++ b/drivers/infiniband/core/umem.c @@ -175,7 +175,7 @@ struct ib_umem *ib_umem_get(struct ib_ucontext *context, unsigned long addr, cur_base = addr & PAGE_MASK; - if (npages == 0) { + if (npages == 0 || npages > UINT_MAX) { ret = -EINVAL; goto out; } diff --git a/drivers/infiniband/core/uverbs_main.c b/drivers/infiniband/core/uverbs_main.c index 0012fa58c105..44b1104eb168 100644 --- a/drivers/infiniband/core/uverbs_main.c +++ b/drivers/infiniband/core/uverbs_main.c @@ -262,12 +262,9 @@ static int ib_uverbs_cleanup_ucontext(struct ib_uverbs_file *file, container_of(uobj, struct ib_uqp_object, uevent.uobject); idr_remove_uobj(&ib_uverbs_qp_idr, uobj); - if (qp != qp->real_qp) { - ib_close_qp(qp); - } else { + if (qp == qp->real_qp) ib_uverbs_detach_umcast(qp, uqp); - ib_destroy_qp(qp); - } + ib_destroy_qp(qp); ib_uverbs_release_uevent(file, &uqp->uevent); kfree(uqp); } diff --git a/drivers/infiniband/hw/cxgb4/cq.c b/drivers/infiniband/hw/cxgb4/cq.c index 867b8cf82be8..19c6477af19f 100644 --- a/drivers/infiniband/hw/cxgb4/cq.c +++ b/drivers/infiniband/hw/cxgb4/cq.c @@ -666,18 +666,6 @@ skip_cqe: return ret; } -static void invalidate_mr(struct c4iw_dev *rhp, u32 rkey) -{ - struct c4iw_mr *mhp; - unsigned long flags; - - spin_lock_irqsave(&rhp->lock, flags); - mhp = get_mhp(rhp, rkey >> 8); - if (mhp) - mhp->attr.state = 0; - spin_unlock_irqrestore(&rhp->lock, flags); -} - /* * Get one cq entry from c4iw and map it to openib. * @@ -733,7 +721,7 @@ static int c4iw_poll_cq_one(struct c4iw_cq *chp, struct ib_wc *wc) CQE_OPCODE(&cqe) == FW_RI_SEND_WITH_SE_INV) { wc->ex.invalidate_rkey = CQE_WRID_STAG(&cqe); wc->wc_flags |= IB_WC_WITH_INVALIDATE; - invalidate_mr(qhp->rhp, wc->ex.invalidate_rkey); + c4iw_invalidate_mr(qhp->rhp, wc->ex.invalidate_rkey); } } else { switch (CQE_OPCODE(&cqe)) { @@ -762,7 +750,8 @@ static int c4iw_poll_cq_one(struct c4iw_cq *chp, struct ib_wc *wc) /* Invalidate the MR if the fastreg failed */ if (CQE_STATUS(&cqe) != T4_ERR_SUCCESS) - invalidate_mr(qhp->rhp, CQE_WRID_FR_STAG(&cqe)); + c4iw_invalidate_mr(qhp->rhp, + CQE_WRID_FR_STAG(&cqe)); break; default: printk(KERN_ERR MOD "Unexpected opcode %d " diff --git a/drivers/infiniband/hw/cxgb4/iw_cxgb4.h b/drivers/infiniband/hw/cxgb4/iw_cxgb4.h index 7e7f79e55006..4788e1a46fde 100644 --- a/drivers/infiniband/hw/cxgb4/iw_cxgb4.h +++ b/drivers/infiniband/hw/cxgb4/iw_cxgb4.h @@ -999,6 +999,6 @@ extern int db_coalescing_threshold; extern int use_dsgl; void c4iw_drain_rq(struct ib_qp *qp); void c4iw_drain_sq(struct ib_qp *qp); - +void c4iw_invalidate_mr(struct c4iw_dev *rhp, u32 rkey); #endif diff --git a/drivers/infiniband/hw/cxgb4/mem.c b/drivers/infiniband/hw/cxgb4/mem.c index 80e27749420a..410408f886c1 100644 --- a/drivers/infiniband/hw/cxgb4/mem.c +++ b/drivers/infiniband/hw/cxgb4/mem.c @@ -770,3 +770,15 @@ int c4iw_dereg_mr(struct ib_mr *ib_mr) kfree(mhp); return 0; } + +void c4iw_invalidate_mr(struct c4iw_dev *rhp, u32 rkey) +{ + struct c4iw_mr *mhp; + unsigned long flags; + + spin_lock_irqsave(&rhp->lock, flags); + mhp = get_mhp(rhp, rkey >> 8); + if (mhp) + mhp->attr.state = 0; + spin_unlock_irqrestore(&rhp->lock, flags); +} diff --git a/drivers/infiniband/hw/cxgb4/qp.c b/drivers/infiniband/hw/cxgb4/qp.c index f57deba6717c..b7ac97b27c88 100644 --- a/drivers/infiniband/hw/cxgb4/qp.c +++ b/drivers/infiniband/hw/cxgb4/qp.c @@ -706,12 +706,8 @@ static int build_memreg(struct t4_sq *sq, union t4_wr *wqe, return 0; } -static int build_inv_stag(struct c4iw_dev *dev, union t4_wr *wqe, - struct ib_send_wr *wr, u8 *len16) +static int build_inv_stag(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16) { - struct c4iw_mr *mhp = get_mhp(dev, wr->ex.invalidate_rkey >> 8); - - mhp->attr.state = 0; wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey); wqe->inv.r2 = 0; *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16); @@ -797,11 +793,13 @@ int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, spin_lock_irqsave(&qhp->lock, flag); if (t4_wq_in_error(&qhp->wq)) { spin_unlock_irqrestore(&qhp->lock, flag); + *bad_wr = wr; return -EINVAL; } num_wrs = t4_sq_avail(&qhp->wq); if (num_wrs == 0) { spin_unlock_irqrestore(&qhp->lock, flag); + *bad_wr = wr; return -ENOMEM; } while (wr) { @@ -840,10 +838,13 @@ int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, case IB_WR_RDMA_READ_WITH_INV: fw_opcode = FW_RI_RDMA_READ_WR; swsqe->opcode = FW_RI_READ_REQ; - if (wr->opcode == IB_WR_RDMA_READ_WITH_INV) + if (wr->opcode == IB_WR_RDMA_READ_WITH_INV) { + c4iw_invalidate_mr(qhp->rhp, + wr->sg_list[0].lkey); fw_flags = FW_RI_RDMA_READ_INVALIDATE; - else + } else { fw_flags = 0; + } err = build_rdma_read(wqe, wr, &len16); if (err) break; @@ -876,7 +877,8 @@ int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, fw_flags |= FW_RI_LOCAL_FENCE_FLAG; fw_opcode = FW_RI_INV_LSTAG_WR; swsqe->opcode = FW_RI_LOCAL_INV; - err = build_inv_stag(qhp->rhp, wqe, wr, &len16); + err = build_inv_stag(wqe, wr, &len16); + c4iw_invalidate_mr(qhp->rhp, wr->ex.invalidate_rkey); break; default: PDBG("%s post of type=%d TBD!\n", __func__, @@ -934,11 +936,13 @@ int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr, spin_lock_irqsave(&qhp->lock, flag); if (t4_wq_in_error(&qhp->wq)) { spin_unlock_irqrestore(&qhp->lock, flag); + *bad_wr = wr; return -EINVAL; } num_wrs = t4_rq_avail(&qhp->wq); if (num_wrs == 0) { spin_unlock_irqrestore(&qhp->lock, flag); + *bad_wr = wr; return -ENOMEM; } while (wr) { diff --git a/drivers/infiniband/hw/hfi1/affinity.c b/drivers/infiniband/hw/hfi1/affinity.c index a26a9a0bfc41..67ea85a56945 100644 --- a/drivers/infiniband/hw/hfi1/affinity.c +++ b/drivers/infiniband/hw/hfi1/affinity.c @@ -775,75 +775,3 @@ void hfi1_put_proc_affinity(int cpu) } mutex_unlock(&affinity->lock); } - -int hfi1_set_sdma_affinity(struct hfi1_devdata *dd, const char *buf, - size_t count) -{ - struct hfi1_affinity_node *entry; - cpumask_var_t mask; - int ret, i; - - mutex_lock(&node_affinity.lock); - entry = node_affinity_lookup(dd->node); - - if (!entry) { - ret = -EINVAL; - goto unlock; - } - - ret = zalloc_cpumask_var(&mask, GFP_KERNEL); - if (!ret) { - ret = -ENOMEM; - goto unlock; - } - - ret = cpulist_parse(buf, mask); - if (ret) - goto out; - - if (!cpumask_subset(mask, cpu_online_mask) || cpumask_empty(mask)) { - dd_dev_warn(dd, "Invalid CPU mask\n"); - ret = -EINVAL; - goto out; - } - - /* reset the SDMA interrupt affinity details */ - init_cpu_mask_set(&entry->def_intr); - cpumask_copy(&entry->def_intr.mask, mask); - - /* Reassign the affinity for each SDMA interrupt. */ - for (i = 0; i < dd->num_msix_entries; i++) { - struct hfi1_msix_entry *msix; - - msix = &dd->msix_entries[i]; - if (msix->type != IRQ_SDMA) - continue; - - ret = get_irq_affinity(dd, msix); - - if (ret) - break; - } -out: - free_cpumask_var(mask); -unlock: - mutex_unlock(&node_affinity.lock); - return ret ? ret : strnlen(buf, PAGE_SIZE); -} - -int hfi1_get_sdma_affinity(struct hfi1_devdata *dd, char *buf) -{ - struct hfi1_affinity_node *entry; - - mutex_lock(&node_affinity.lock); - entry = node_affinity_lookup(dd->node); - - if (!entry) { - mutex_unlock(&node_affinity.lock); - return -EINVAL; - } - - cpumap_print_to_pagebuf(true, buf, &entry->def_intr.mask); - mutex_unlock(&node_affinity.lock); - return strnlen(buf, PAGE_SIZE); -} diff --git a/drivers/infiniband/hw/hfi1/affinity.h b/drivers/infiniband/hw/hfi1/affinity.h index b89ea3c0ee1a..42e63316afd1 100644 --- a/drivers/infiniband/hw/hfi1/affinity.h +++ b/drivers/infiniband/hw/hfi1/affinity.h @@ -102,10 +102,6 @@ int hfi1_get_proc_affinity(int); /* Release a CPU used by a user process. */ void hfi1_put_proc_affinity(int); -int hfi1_get_sdma_affinity(struct hfi1_devdata *dd, char *buf); -int hfi1_set_sdma_affinity(struct hfi1_devdata *dd, const char *buf, - size_t count); - struct hfi1_affinity_node { int node; struct cpu_mask_set def_intr; diff --git a/drivers/infiniband/hw/hfi1/chip.c b/drivers/infiniband/hw/hfi1/chip.c index 9bf5f23544d4..24d0820873cf 100644 --- a/drivers/infiniband/hw/hfi1/chip.c +++ b/drivers/infiniband/hw/hfi1/chip.c @@ -6301,19 +6301,8 @@ void set_up_vl15(struct hfi1_devdata *dd, u8 vau, u16 vl15buf) /* leave shared count at zero for both global and VL15 */ write_global_credit(dd, vau, vl15buf, 0); - /* We may need some credits for another VL when sending packets - * with the snoop interface. Dividing it down the middle for VL15 - * and VL0 should suffice. - */ - if (unlikely(dd->hfi1_snoop.mode_flag == HFI1_PORT_SNOOP_MODE)) { - write_csr(dd, SEND_CM_CREDIT_VL15, (u64)(vl15buf >> 1) - << SEND_CM_CREDIT_VL15_DEDICATED_LIMIT_VL_SHIFT); - write_csr(dd, SEND_CM_CREDIT_VL, (u64)(vl15buf >> 1) - << SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SHIFT); - } else { - write_csr(dd, SEND_CM_CREDIT_VL15, (u64)vl15buf - << SEND_CM_CREDIT_VL15_DEDICATED_LIMIT_VL_SHIFT); - } + write_csr(dd, SEND_CM_CREDIT_VL15, (u64)vl15buf + << SEND_CM_CREDIT_VL15_DEDICATED_LIMIT_VL_SHIFT); } /* @@ -9915,9 +9904,6 @@ static void set_lidlmc(struct hfi1_pportdata *ppd) u32 mask = ~((1U << ppd->lmc) - 1); u64 c1 = read_csr(ppd->dd, DCC_CFG_PORT_CONFIG1); - if (dd->hfi1_snoop.mode_flag) - dd_dev_info(dd, "Set lid/lmc while snooping"); - c1 &= ~(DCC_CFG_PORT_CONFIG1_TARGET_DLID_SMASK | DCC_CFG_PORT_CONFIG1_DLID_MASK_SMASK); c1 |= ((ppd->lid & DCC_CFG_PORT_CONFIG1_TARGET_DLID_MASK) @@ -12112,7 +12098,7 @@ static void update_synth_timer(unsigned long opaque) mod_timer(&dd->synth_stats_timer, jiffies + HZ * SYNTH_CNT_TIME); } -#define C_MAX_NAME 13 /* 12 chars + one for /0 */ +#define C_MAX_NAME 16 /* 15 chars + one for /0 */ static int init_cntrs(struct hfi1_devdata *dd) { int i, rcv_ctxts, j; @@ -14463,7 +14449,7 @@ struct hfi1_devdata *hfi1_init_dd(struct pci_dev *pdev, * Any error printing is already done by the init code. * On return, we have the chip mapped. */ - ret = hfi1_pcie_ddinit(dd, pdev, ent); + ret = hfi1_pcie_ddinit(dd, pdev); if (ret < 0) goto bail_free; @@ -14691,6 +14677,11 @@ struct hfi1_devdata *hfi1_init_dd(struct pci_dev *pdev, if (ret) goto bail_free_cntrs; + init_completion(&dd->user_comp); + + /* The user refcount starts with one to inidicate an active device */ + atomic_set(&dd->user_refcount, 1); + goto bail; bail_free_rcverr: diff --git a/drivers/infiniband/hw/hfi1/chip.h b/drivers/infiniband/hw/hfi1/chip.h index 92345259a8f4..043fd21dc5f3 100644 --- a/drivers/infiniband/hw/hfi1/chip.h +++ b/drivers/infiniband/hw/hfi1/chip.h @@ -320,6 +320,9 @@ /* DC_DC8051_CFG_MODE.GENERAL bits */ #define DISABLE_SELF_GUID_CHECK 0x2 +/* Bad L2 frame error code */ +#define BAD_L2_ERR 0x6 + /* * Eager buffer minimum and maximum sizes supported by the hardware. * All power-of-two sizes in between are supported as well. diff --git a/drivers/infiniband/hw/hfi1/driver.c b/drivers/infiniband/hw/hfi1/driver.c index 6563e4d38b80..c5efff29c147 100644 --- a/drivers/infiniband/hw/hfi1/driver.c +++ b/drivers/infiniband/hw/hfi1/driver.c @@ -599,7 +599,6 @@ static void __prescan_rxq(struct hfi1_packet *packet) dd->rhf_offset; struct rvt_qp *qp; struct ib_header *hdr; - struct ib_other_headers *ohdr; struct rvt_dev_info *rdi = &dd->verbs_dev.rdi; u64 rhf = rhf_to_cpu(rhf_addr); u32 etype = rhf_rcv_type(rhf), qpn, bth1; @@ -615,18 +614,21 @@ static void __prescan_rxq(struct hfi1_packet *packet) if (etype != RHF_RCV_TYPE_IB) goto next; - hdr = hfi1_get_msgheader(dd, rhf_addr); + packet->hdr = hfi1_get_msgheader(dd, rhf_addr); + hdr = packet->hdr; lnh = be16_to_cpu(hdr->lrh[0]) & 3; - if (lnh == HFI1_LRH_BTH) - ohdr = &hdr->u.oth; - else if (lnh == HFI1_LRH_GRH) - ohdr = &hdr->u.l.oth; - else + if (lnh == HFI1_LRH_BTH) { + packet->ohdr = &hdr->u.oth; + } else if (lnh == HFI1_LRH_GRH) { + packet->ohdr = &hdr->u.l.oth; + packet->rcv_flags |= HFI1_HAS_GRH; + } else { goto next; /* just in case */ + } - bth1 = be32_to_cpu(ohdr->bth[1]); + bth1 = be32_to_cpu(packet->ohdr->bth[1]); is_ecn = !!(bth1 & (HFI1_FECN_SMASK | HFI1_BECN_SMASK)); if (!is_ecn) @@ -646,7 +648,7 @@ static void __prescan_rxq(struct hfi1_packet *packet) /* turn off BECN, FECN */ bth1 &= ~(HFI1_FECN_SMASK | HFI1_BECN_SMASK); - ohdr->bth[1] = cpu_to_be32(bth1); + packet->ohdr->bth[1] = cpu_to_be32(bth1); next: update_ps_mdata(&mdata, rcd); } @@ -1360,12 +1362,25 @@ int process_receive_ib(struct hfi1_packet *packet) int process_receive_bypass(struct hfi1_packet *packet) { + struct hfi1_devdata *dd = packet->rcd->dd; + if (unlikely(rhf_err_flags(packet->rhf))) handle_eflags(packet); - dd_dev_err(packet->rcd->dd, + dd_dev_err(dd, "Bypass packets are not supported in normal operation. Dropping\n"); - incr_cntr64(&packet->rcd->dd->sw_rcv_bypass_packet_errors); + incr_cntr64(&dd->sw_rcv_bypass_packet_errors); + if (!(dd->err_info_rcvport.status_and_code & OPA_EI_STATUS_SMASK)) { + u64 *flits = packet->ebuf; + + if (flits && !(packet->rhf & RHF_LEN_ERR)) { + dd->err_info_rcvport.packet_flit1 = flits[0]; + dd->err_info_rcvport.packet_flit2 = + packet->tlen > sizeof(flits[0]) ? flits[1] : 0; + } + dd->err_info_rcvport.status_and_code |= + (OPA_EI_STATUS_SMASK | BAD_L2_ERR); + } return RHF_RCV_CONTINUE; } diff --git a/drivers/infiniband/hw/hfi1/file_ops.c b/drivers/infiniband/hw/hfi1/file_ops.c index 677efa0e8cd6..bd786b7bd30b 100644 --- a/drivers/infiniband/hw/hfi1/file_ops.c +++ b/drivers/infiniband/hw/hfi1/file_ops.c @@ -172,6 +172,9 @@ static int hfi1_file_open(struct inode *inode, struct file *fp) struct hfi1_devdata, user_cdev); + if (!atomic_inc_not_zero(&dd->user_refcount)) + return -ENXIO; + /* Just take a ref now. Not all opens result in a context assign */ kobject_get(&dd->kobj); @@ -183,11 +186,17 @@ static int hfi1_file_open(struct inode *inode, struct file *fp) fd->rec_cpu_num = -1; /* no cpu affinity by default */ fd->mm = current->mm; atomic_inc(&fd->mm->mm_count); - } + fp->private_data = fd; + } else { + fp->private_data = NULL; + + if (atomic_dec_and_test(&dd->user_refcount)) + complete(&dd->user_comp); - fp->private_data = fd; + return -ENOMEM; + } - return fd ? 0 : -ENOMEM; + return 0; } static long hfi1_file_ioctl(struct file *fp, unsigned int cmd, @@ -798,6 +807,10 @@ static int hfi1_file_close(struct inode *inode, struct file *fp) done: mmdrop(fdata->mm); kobject_put(&dd->kobj); + + if (atomic_dec_and_test(&dd->user_refcount)) + complete(&dd->user_comp); + kfree(fdata); return 0; } diff --git a/drivers/infiniband/hw/hfi1/hfi.h b/drivers/infiniband/hw/hfi1/hfi.h index 7eef11b316ff..cc87fd4e534b 100644 --- a/drivers/infiniband/hw/hfi1/hfi.h +++ b/drivers/infiniband/hw/hfi1/hfi.h @@ -367,26 +367,6 @@ struct hfi1_packet { u8 etype; }; -/* - * Private data for snoop/capture support. - */ -struct hfi1_snoop_data { - int mode_flag; - struct cdev cdev; - struct device *class_dev; - /* protect snoop data */ - spinlock_t snoop_lock; - struct list_head queue; - wait_queue_head_t waitq; - void *filter_value; - int (*filter_callback)(void *hdr, void *data, void *value); - u64 dcc_cfg; /* saved value of DCC Cfg register */ -}; - -/* snoop mode_flag values */ -#define HFI1_PORT_SNOOP_MODE 1U -#define HFI1_PORT_CAPTURE_MODE 2U - struct rvt_sge_state; /* @@ -613,8 +593,6 @@ struct hfi1_pportdata { struct mutex hls_lock; u32 host_link_state; - spinlock_t sdma_alllock ____cacheline_aligned_in_smp; - u32 lstate; /* logical link state */ /* these are the "32 bit" regs */ @@ -1104,8 +1082,6 @@ struct hfi1_devdata { char *portcntrnames; size_t portcntrnameslen; - struct hfi1_snoop_data hfi1_snoop; - struct err_info_rcvport err_info_rcvport; struct err_info_constraint err_info_rcv_constraint; struct err_info_constraint err_info_xmit_constraint; @@ -1141,8 +1117,8 @@ struct hfi1_devdata { rhf_rcv_function_ptr normal_rhf_rcv_functions[8]; /* - * Handlers for outgoing data so that snoop/capture does not - * have to have its hooks in the send path + * Capability to have different send engines simply by changing a + * pointer value. */ send_routine process_pio_send; send_routine process_dma_send; @@ -1174,6 +1150,10 @@ struct hfi1_devdata { spinlock_t aspm_lock; /* Number of verbs contexts which have disabled ASPM */ atomic_t aspm_disabled_cnt; + /* Keeps track of user space clients */ + atomic_t user_refcount; + /* Used to wait for outstanding user space clients before dev removal */ + struct completion user_comp; struct hfi1_affinity *affinity; struct rhashtable sdma_rht; @@ -1221,8 +1201,6 @@ struct hfi1_devdata *hfi1_lookup(int unit); extern u32 hfi1_cpulist_count; extern unsigned long *hfi1_cpulist; -extern unsigned int snoop_drop_send; -extern unsigned int snoop_force_capture; int hfi1_init(struct hfi1_devdata *, int); int hfi1_count_units(int *npresentp, int *nupp); int hfi1_count_active_units(void); @@ -1557,13 +1535,6 @@ void set_up_vl15(struct hfi1_devdata *dd, u8 vau, u16 vl15buf); void reset_link_credits(struct hfi1_devdata *dd); void assign_remote_cm_au_table(struct hfi1_devdata *dd, u8 vcu); -int snoop_recv_handler(struct hfi1_packet *packet); -int snoop_send_dma_handler(struct rvt_qp *qp, struct hfi1_pkt_state *ps, - u64 pbc); -int snoop_send_pio_handler(struct rvt_qp *qp, struct hfi1_pkt_state *ps, - u64 pbc); -void snoop_inline_pio_send(struct hfi1_devdata *dd, struct pio_buf *pbuf, - u64 pbc, const void *from, size_t count); int set_buffer_control(struct hfi1_pportdata *ppd, struct buffer_control *bc); static inline struct hfi1_devdata *dd_from_ppd(struct hfi1_pportdata *ppd) @@ -1763,8 +1734,7 @@ int qsfp_dump(struct hfi1_pportdata *ppd, char *buf, int len); int hfi1_pcie_init(struct pci_dev *, const struct pci_device_id *); void hfi1_pcie_cleanup(struct pci_dev *); -int hfi1_pcie_ddinit(struct hfi1_devdata *, struct pci_dev *, - const struct pci_device_id *); +int hfi1_pcie_ddinit(struct hfi1_devdata *, struct pci_dev *); void hfi1_pcie_ddcleanup(struct hfi1_devdata *); void hfi1_pcie_flr(struct hfi1_devdata *); int pcie_speeds(struct hfi1_devdata *); @@ -1799,8 +1769,6 @@ int kdeth_process_expected(struct hfi1_packet *packet); int kdeth_process_eager(struct hfi1_packet *packet); int process_receive_invalid(struct hfi1_packet *packet); -extern rhf_rcv_function_ptr snoop_rhf_rcv_functions[8]; - void update_sge(struct rvt_sge_state *ss, u32 length); /* global module parameter variables */ @@ -1827,9 +1795,6 @@ extern struct mutex hfi1_mutex; #define DRIVER_NAME "hfi1" #define HFI1_USER_MINOR_BASE 0 #define HFI1_TRACE_MINOR 127 -#define HFI1_DIAGPKT_MINOR 128 -#define HFI1_DIAG_MINOR_BASE 129 -#define HFI1_SNOOP_CAPTURE_BASE 200 #define HFI1_NMINORS 255 #define PCI_VENDOR_ID_INTEL 0x8086 @@ -1848,7 +1813,13 @@ extern struct mutex hfi1_mutex; static inline u64 hfi1_pkt_default_send_ctxt_mask(struct hfi1_devdata *dd, u16 ctxt_type) { - u64 base_sc_integrity = + u64 base_sc_integrity; + + /* No integrity checks if HFI1_CAP_NO_INTEGRITY is set */ + if (HFI1_CAP_IS_KSET(NO_INTEGRITY)) + return 0; + + base_sc_integrity = SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK | SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK @@ -1863,7 +1834,6 @@ static inline u64 hfi1_pkt_default_send_ctxt_mask(struct hfi1_devdata *dd, | SEND_CTXT_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK | SEND_CTXT_CHECK_ENABLE_CHECK_OPCODE_SMASK | SEND_CTXT_CHECK_ENABLE_CHECK_SLID_SMASK - | SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK | SEND_CTXT_CHECK_ENABLE_CHECK_VL_SMASK | SEND_CTXT_CHECK_ENABLE_CHECK_ENABLE_SMASK; @@ -1872,18 +1842,23 @@ static inline u64 hfi1_pkt_default_send_ctxt_mask(struct hfi1_devdata *dd, else base_sc_integrity |= HFI1_PKT_KERNEL_SC_INTEGRITY; - if (is_ax(dd)) - /* turn off send-side job key checks - A0 */ - return base_sc_integrity & - ~SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK; + /* turn on send-side job key checks if !A0 */ + if (!is_ax(dd)) + base_sc_integrity |= SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK; + return base_sc_integrity; } static inline u64 hfi1_pkt_base_sdma_integrity(struct hfi1_devdata *dd) { - u64 base_sdma_integrity = + u64 base_sdma_integrity; + + /* No integrity checks if HFI1_CAP_NO_INTEGRITY is set */ + if (HFI1_CAP_IS_KSET(NO_INTEGRITY)) + return 0; + + base_sdma_integrity = SEND_DMA_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK - | SEND_DMA_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK | SEND_DMA_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK @@ -1895,14 +1870,18 @@ static inline u64 hfi1_pkt_base_sdma_integrity(struct hfi1_devdata *dd) | SEND_DMA_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK | SEND_DMA_CHECK_ENABLE_CHECK_OPCODE_SMASK | SEND_DMA_CHECK_ENABLE_CHECK_SLID_SMASK - | SEND_DMA_CHECK_ENABLE_CHECK_JOB_KEY_SMASK | SEND_DMA_CHECK_ENABLE_CHECK_VL_SMASK | SEND_DMA_CHECK_ENABLE_CHECK_ENABLE_SMASK; - if (is_ax(dd)) - /* turn off send-side job key checks - A0 */ - return base_sdma_integrity & - ~SEND_DMA_CHECK_ENABLE_CHECK_JOB_KEY_SMASK; + if (!HFI1_CAP_IS_KSET(STATIC_RATE_CTRL)) + base_sdma_integrity |= + SEND_DMA_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK; + + /* turn on send-side job key checks if !A0 */ + if (!is_ax(dd)) + base_sdma_integrity |= + SEND_DMA_CHECK_ENABLE_CHECK_JOB_KEY_SMASK; + return base_sdma_integrity; } diff --git a/drivers/infiniband/hw/hfi1/init.c b/drivers/infiniband/hw/hfi1/init.c index 60db61536fed..e3b5bc93bc70 100644 --- a/drivers/infiniband/hw/hfi1/init.c +++ b/drivers/infiniband/hw/hfi1/init.c @@ -144,6 +144,8 @@ int hfi1_create_ctxts(struct hfi1_devdata *dd) struct hfi1_ctxtdata *rcd; ppd = dd->pport + (i % dd->num_pports); + + /* dd->rcd[i] gets assigned inside the callee */ rcd = hfi1_create_ctxtdata(ppd, i, dd->node); if (!rcd) { dd_dev_err(dd, @@ -169,8 +171,6 @@ int hfi1_create_ctxts(struct hfi1_devdata *dd) if (!rcd->sc) { dd_dev_err(dd, "Unable to allocate kernel send context, failing\n"); - dd->rcd[rcd->ctxt] = NULL; - hfi1_free_ctxtdata(dd, rcd); goto nomem; } @@ -178,9 +178,6 @@ int hfi1_create_ctxts(struct hfi1_devdata *dd) if (ret < 0) { dd_dev_err(dd, "Failed to setup kernel receive context, failing\n"); - sc_free(rcd->sc); - dd->rcd[rcd->ctxt] = NULL; - hfi1_free_ctxtdata(dd, rcd); ret = -EFAULT; goto bail; } @@ -196,6 +193,10 @@ int hfi1_create_ctxts(struct hfi1_devdata *dd) nomem: ret = -ENOMEM; bail: + if (dd->rcd) { + for (i = 0; i < dd->num_rcv_contexts; ++i) + hfi1_free_ctxtdata(dd, dd->rcd[i]); + } kfree(dd->rcd); dd->rcd = NULL; return ret; @@ -216,7 +217,7 @@ struct hfi1_ctxtdata *hfi1_create_ctxtdata(struct hfi1_pportdata *ppd, u32 ctxt, dd->num_rcv_contexts - dd->first_user_ctxt) kctxt_ngroups = (dd->rcv_entries.nctxt_extra - (dd->num_rcv_contexts - dd->first_user_ctxt)); - rcd = kzalloc(sizeof(*rcd), GFP_KERNEL); + rcd = kzalloc_node(sizeof(*rcd), GFP_KERNEL, numa); if (rcd) { u32 rcvtids, max_entries; @@ -261,13 +262,6 @@ struct hfi1_ctxtdata *hfi1_create_ctxtdata(struct hfi1_pportdata *ppd, u32 ctxt, } rcd->eager_base = base * dd->rcv_entries.group_size; - /* Validate and initialize Rcv Hdr Q variables */ - if (rcvhdrcnt % HDRQ_INCREMENT) { - dd_dev_err(dd, - "ctxt%u: header queue count %d must be divisible by %lu\n", - rcd->ctxt, rcvhdrcnt, HDRQ_INCREMENT); - goto bail; - } rcd->rcvhdrq_cnt = rcvhdrcnt; rcd->rcvhdrqentsize = hfi1_hdrq_entsize; /* @@ -506,7 +500,6 @@ void hfi1_init_pportdata(struct pci_dev *pdev, struct hfi1_pportdata *ppd, INIT_WORK(&ppd->qsfp_info.qsfp_work, qsfp_event); mutex_init(&ppd->hls_lock); - spin_lock_init(&ppd->sdma_alllock); spin_lock_init(&ppd->qsfp_info.qsfp_lock); ppd->qsfp_info.ppd = ppd; @@ -1399,28 +1392,43 @@ static void postinit_cleanup(struct hfi1_devdata *dd) hfi1_free_devdata(dd); } +static int init_validate_rcvhdrcnt(struct device *dev, uint thecnt) +{ + if (thecnt <= HFI1_MIN_HDRQ_EGRBUF_CNT) { + hfi1_early_err(dev, "Receive header queue count too small\n"); + return -EINVAL; + } + + if (thecnt > HFI1_MAX_HDRQ_EGRBUF_CNT) { + hfi1_early_err(dev, + "Receive header queue count cannot be greater than %u\n", + HFI1_MAX_HDRQ_EGRBUF_CNT); + return -EINVAL; + } + + if (thecnt % HDRQ_INCREMENT) { + hfi1_early_err(dev, "Receive header queue count %d must be divisible by %lu\n", + thecnt, HDRQ_INCREMENT); + return -EINVAL; + } + + return 0; +} + static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent) { int ret = 0, j, pidx, initfail; - struct hfi1_devdata *dd = ERR_PTR(-EINVAL); + struct hfi1_devdata *dd; struct hfi1_pportdata *ppd; /* First, lock the non-writable module parameters */ HFI1_CAP_LOCK(); /* Validate some global module parameters */ - if (rcvhdrcnt <= HFI1_MIN_HDRQ_EGRBUF_CNT) { - hfi1_early_err(&pdev->dev, "Header queue count too small\n"); - ret = -EINVAL; - goto bail; - } - if (rcvhdrcnt > HFI1_MAX_HDRQ_EGRBUF_CNT) { - hfi1_early_err(&pdev->dev, - "Receive header queue count cannot be greater than %u\n", - HFI1_MAX_HDRQ_EGRBUF_CNT); - ret = -EINVAL; + ret = init_validate_rcvhdrcnt(&pdev->dev, rcvhdrcnt); + if (ret) goto bail; - } + /* use the encoding function as a sanitization check */ if (!encode_rcv_header_entry_size(hfi1_hdrq_entsize)) { hfi1_early_err(&pdev->dev, "Invalid HdrQ Entry size %u\n", @@ -1461,26 +1469,25 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent) if (ret) goto bail; - /* - * Do device-specific initialization, function table setup, dd - * allocation, etc. - */ - switch (ent->device) { - case PCI_DEVICE_ID_INTEL0: - case PCI_DEVICE_ID_INTEL1: - dd = hfi1_init_dd(pdev, ent); - break; - default: + if (!(ent->device == PCI_DEVICE_ID_INTEL0 || + ent->device == PCI_DEVICE_ID_INTEL1)) { hfi1_early_err(&pdev->dev, "Failing on unknown Intel deviceid 0x%x\n", ent->device); ret = -ENODEV; + goto clean_bail; } - if (IS_ERR(dd)) + /* + * Do device-specific initialization, function table setup, dd + * allocation, etc. + */ + dd = hfi1_init_dd(pdev, ent); + + if (IS_ERR(dd)) { ret = PTR_ERR(dd); - if (ret) goto clean_bail; /* error already printed */ + } ret = create_workqueues(dd); if (ret) @@ -1538,12 +1545,31 @@ bail: return ret; } +static void wait_for_clients(struct hfi1_devdata *dd) +{ + /* + * Remove the device init value and complete the device if there is + * no clients or wait for active clients to finish. + */ + if (atomic_dec_and_test(&dd->user_refcount)) + complete(&dd->user_comp); + + wait_for_completion(&dd->user_comp); +} + static void remove_one(struct pci_dev *pdev) { struct hfi1_devdata *dd = pci_get_drvdata(pdev); /* close debugfs files before ib unregister */ hfi1_dbg_ibdev_exit(&dd->verbs_dev); + + /* remove the /dev hfi1 interface */ + hfi1_device_remove(dd); + + /* wait for existing user space clients to finish */ + wait_for_clients(dd); + /* unregister from IB core */ hfi1_unregister_ib_device(dd); @@ -1558,8 +1584,6 @@ static void remove_one(struct pci_dev *pdev) /* wait until all of our (qsfp) queue_work() calls complete */ flush_workqueue(ib_wq); - hfi1_device_remove(dd); - postinit_cleanup(dd); } diff --git a/drivers/infiniband/hw/hfi1/pcie.c b/drivers/infiniband/hw/hfi1/pcie.c index 89c68da1c273..4ac8f330c5cb 100644 --- a/drivers/infiniband/hw/hfi1/pcie.c +++ b/drivers/infiniband/hw/hfi1/pcie.c @@ -157,8 +157,7 @@ void hfi1_pcie_cleanup(struct pci_dev *pdev) * fields required to re-initialize after a chip reset, or for * various other purposes */ -int hfi1_pcie_ddinit(struct hfi1_devdata *dd, struct pci_dev *pdev, - const struct pci_device_id *ent) +int hfi1_pcie_ddinit(struct hfi1_devdata *dd, struct pci_dev *pdev) { unsigned long len; resource_size_t addr; diff --git a/drivers/infiniband/hw/hfi1/pio.c b/drivers/infiniband/hw/hfi1/pio.c index 50a3a36d9363..d89b8745d4c1 100644 --- a/drivers/infiniband/hw/hfi1/pio.c +++ b/drivers/infiniband/hw/hfi1/pio.c @@ -668,19 +668,12 @@ void sc_set_cr_threshold(struct send_context *sc, u32 new_threshold) void set_pio_integrity(struct send_context *sc) { struct hfi1_devdata *dd = sc->dd; - u64 reg = 0; u32 hw_context = sc->hw_context; int type = sc->type; - /* - * No integrity checks if HFI1_CAP_NO_INTEGRITY is set, or if - * we're snooping. - */ - if (likely(!HFI1_CAP_IS_KSET(NO_INTEGRITY)) && - dd->hfi1_snoop.mode_flag != HFI1_PORT_SNOOP_MODE) - reg = hfi1_pkt_default_send_ctxt_mask(dd, type); - - write_kctxt_csr(dd, hw_context, SC(CHECK_ENABLE), reg); + write_kctxt_csr(dd, hw_context, + SC(CHECK_ENABLE), + hfi1_pkt_default_send_ctxt_mask(dd, type)); } static u32 get_buffers_allocated(struct send_context *sc) diff --git a/drivers/infiniband/hw/hfi1/rc.c b/drivers/infiniband/hw/hfi1/rc.c index 8bc5013f39a1..83198a8a8797 100644 --- a/drivers/infiniband/hw/hfi1/rc.c +++ b/drivers/infiniband/hw/hfi1/rc.c @@ -89,7 +89,7 @@ void hfi1_add_rnr_timer(struct rvt_qp *qp, u32 to) lockdep_assert_held(&qp->s_lock); qp->s_flags |= RVT_S_WAIT_RNR; - qp->s_timer.expires = jiffies + usecs_to_jiffies(to); + priv->s_rnr_timer.expires = jiffies + usecs_to_jiffies(to); add_timer(&priv->s_rnr_timer); } diff --git a/drivers/infiniband/hw/hfi1/sdma.c b/drivers/infiniband/hw/hfi1/sdma.c index fd39bcaa062d..9cbe52d21077 100644 --- a/drivers/infiniband/hw/hfi1/sdma.c +++ b/drivers/infiniband/hw/hfi1/sdma.c @@ -2009,11 +2009,6 @@ static void sdma_hw_start_up(struct sdma_engine *sde) write_sde_csr(sde, SD(ENG_ERR_CLEAR), reg); } -#define CLEAR_STATIC_RATE_CONTROL_SMASK(r) \ -(r &= ~SEND_DMA_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK) - -#define SET_STATIC_RATE_CONTROL_SMASK(r) \ -(r |= SEND_DMA_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK) /* * set_sdma_integrity * @@ -2022,19 +2017,9 @@ static void sdma_hw_start_up(struct sdma_engine *sde) static void set_sdma_integrity(struct sdma_engine *sde) { struct hfi1_devdata *dd = sde->dd; - u64 reg; - - if (unlikely(HFI1_CAP_IS_KSET(NO_INTEGRITY))) - return; - - reg = hfi1_pkt_base_sdma_integrity(dd); - - if (HFI1_CAP_IS_KSET(STATIC_RATE_CTRL)) - CLEAR_STATIC_RATE_CONTROL_SMASK(reg); - else - SET_STATIC_RATE_CONTROL_SMASK(reg); - write_sde_csr(sde, SD(CHECK_ENABLE), reg); + write_sde_csr(sde, SD(CHECK_ENABLE), + hfi1_pkt_base_sdma_integrity(dd)); } static void init_sdma_regs( diff --git a/drivers/infiniband/hw/hfi1/sysfs.c b/drivers/infiniband/hw/hfi1/sysfs.c index edba22461a9c..919a5474e651 100644 --- a/drivers/infiniband/hw/hfi1/sysfs.c +++ b/drivers/infiniband/hw/hfi1/sysfs.c @@ -49,7 +49,6 @@ #include "hfi.h" #include "mad.h" #include "trace.h" -#include "affinity.h" /* * Start of per-port congestion control structures and support code @@ -623,27 +622,6 @@ static ssize_t show_tempsense(struct device *device, return ret; } -static ssize_t show_sdma_affinity(struct device *device, - struct device_attribute *attr, char *buf) -{ - struct hfi1_ibdev *dev = - container_of(device, struct hfi1_ibdev, rdi.ibdev.dev); - struct hfi1_devdata *dd = dd_from_dev(dev); - - return hfi1_get_sdma_affinity(dd, buf); -} - -static ssize_t store_sdma_affinity(struct device *device, - struct device_attribute *attr, - const char *buf, size_t count) -{ - struct hfi1_ibdev *dev = - container_of(device, struct hfi1_ibdev, rdi.ibdev.dev); - struct hfi1_devdata *dd = dd_from_dev(dev); - - return hfi1_set_sdma_affinity(dd, buf, count); -} - /* * end of per-unit (or driver, in some cases, but replicated * per unit) functions @@ -658,8 +636,6 @@ static DEVICE_ATTR(serial, S_IRUGO, show_serial, NULL); static DEVICE_ATTR(boardversion, S_IRUGO, show_boardversion, NULL); static DEVICE_ATTR(tempsense, S_IRUGO, show_tempsense, NULL); static DEVICE_ATTR(chip_reset, S_IWUSR, NULL, store_chip_reset); -static DEVICE_ATTR(sdma_affinity, S_IWUSR | S_IRUGO, show_sdma_affinity, - store_sdma_affinity); static struct device_attribute *hfi1_attributes[] = { &dev_attr_hw_rev, @@ -670,7 +646,6 @@ static struct device_attribute *hfi1_attributes[] = { &dev_attr_boardversion, &dev_attr_tempsense, &dev_attr_chip_reset, - &dev_attr_sdma_affinity, }; int hfi1_create_port_files(struct ib_device *ibdev, u8 port_num, diff --git a/drivers/infiniband/hw/hfi1/trace_rx.h b/drivers/infiniband/hw/hfi1/trace_rx.h index 11e02b228922..f77e59fb43fe 100644 --- a/drivers/infiniband/hw/hfi1/trace_rx.h +++ b/drivers/infiniband/hw/hfi1/trace_rx.h @@ -253,66 +253,6 @@ TRACE_EVENT(hfi1_mmu_invalidate, ) ); -#define SNOOP_PRN \ - "slid %.4x dlid %.4x qpn 0x%.6x opcode 0x%.2x,%s " \ - "svc lvl %d pkey 0x%.4x [header = %d bytes] [data = %d bytes]" - -TRACE_EVENT(snoop_capture, - TP_PROTO(struct hfi1_devdata *dd, - int hdr_len, - struct ib_header *hdr, - int data_len, - void *data), - TP_ARGS(dd, hdr_len, hdr, data_len, data), - TP_STRUCT__entry( - DD_DEV_ENTRY(dd) - __field(u16, slid) - __field(u16, dlid) - __field(u32, qpn) - __field(u8, opcode) - __field(u8, sl) - __field(u16, pkey) - __field(u32, hdr_len) - __field(u32, data_len) - __field(u8, lnh) - __dynamic_array(u8, raw_hdr, hdr_len) - __dynamic_array(u8, raw_pkt, data_len) - ), - TP_fast_assign( - struct ib_other_headers *ohdr; - - __entry->lnh = (u8)(be16_to_cpu(hdr->lrh[0]) & 3); - if (__entry->lnh == HFI1_LRH_BTH) - ohdr = &hdr->u.oth; - else - ohdr = &hdr->u.l.oth; - DD_DEV_ASSIGN(dd); - __entry->slid = be16_to_cpu(hdr->lrh[3]); - __entry->dlid = be16_to_cpu(hdr->lrh[1]); - __entry->qpn = be32_to_cpu(ohdr->bth[1]) & RVT_QPN_MASK; - __entry->opcode = (be32_to_cpu(ohdr->bth[0]) >> 24) & 0xff; - __entry->sl = (u8)(be16_to_cpu(hdr->lrh[0]) >> 4) & 0xf; - __entry->pkey = be32_to_cpu(ohdr->bth[0]) & 0xffff; - __entry->hdr_len = hdr_len; - __entry->data_len = data_len; - memcpy(__get_dynamic_array(raw_hdr), hdr, hdr_len); - memcpy(__get_dynamic_array(raw_pkt), data, data_len); - ), - TP_printk( - "[%s] " SNOOP_PRN, - __get_str(dev), - __entry->slid, - __entry->dlid, - __entry->qpn, - __entry->opcode, - show_ib_opcode(__entry->opcode), - __entry->sl, - __entry->pkey, - __entry->hdr_len, - __entry->data_len - ) -); - #endif /* __HFI1_TRACE_RX_H */ #undef TRACE_INCLUDE_PATH diff --git a/drivers/infiniband/hw/hfi1/user_sdma.c b/drivers/infiniband/hw/hfi1/user_sdma.c index a761f804111e..77697d690f3e 100644 --- a/drivers/infiniband/hw/hfi1/user_sdma.c +++ b/drivers/infiniband/hw/hfi1/user_sdma.c @@ -1144,7 +1144,7 @@ static int pin_vector_pages(struct user_sdma_request *req, rb_node = hfi1_mmu_rb_extract(pq->handler, (unsigned long)iovec->iov.iov_base, iovec->iov.iov_len); - if (rb_node && !IS_ERR(rb_node)) + if (rb_node) node = container_of(rb_node, struct sdma_mmu_node, rb); else rb_node = NULL; diff --git a/drivers/infiniband/hw/mlx4/ah.c b/drivers/infiniband/hw/mlx4/ah.c index 5fc623362731..b9bf0759f10a 100644 --- a/drivers/infiniband/hw/mlx4/ah.c +++ b/drivers/infiniband/hw/mlx4/ah.c @@ -102,7 +102,10 @@ static struct ib_ah *create_iboe_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr if (vlan_tag < 0x1000) vlan_tag |= (ah_attr->sl & 7) << 13; ah->av.eth.port_pd = cpu_to_be32(to_mpd(pd)->pdn | (ah_attr->port_num << 24)); - ah->av.eth.gid_index = mlx4_ib_gid_index_to_real_index(ibdev, ah_attr->port_num, ah_attr->grh.sgid_index); + ret = mlx4_ib_gid_index_to_real_index(ibdev, ah_attr->port_num, ah_attr->grh.sgid_index); + if (ret < 0) + return ERR_PTR(ret); + ah->av.eth.gid_index = ret; ah->av.eth.vlan = cpu_to_be16(vlan_tag); ah->av.eth.hop_limit = ah_attr->grh.hop_limit; if (ah_attr->static_rate) { diff --git a/drivers/infiniband/hw/mlx4/cq.c b/drivers/infiniband/hw/mlx4/cq.c index 1ea686b9e0f9..6a0fec357dae 100644 --- a/drivers/infiniband/hw/mlx4/cq.c +++ b/drivers/infiniband/hw/mlx4/cq.c @@ -253,11 +253,14 @@ struct ib_cq *mlx4_ib_create_cq(struct ib_device *ibdev, if (context) if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof (__u32))) { err = -EFAULT; - goto err_dbmap; + goto err_cq_free; } return &cq->ibcq; +err_cq_free: + mlx4_cq_free(dev->dev, &cq->mcq); + err_dbmap: if (context) mlx4_ib_db_unmap_user(to_mucontext(context), &cq->db); diff --git a/drivers/infiniband/hw/mlx5/cq.c b/drivers/infiniband/hw/mlx5/cq.c index 79d017baf6f4..fcd04b881ec1 100644 --- a/drivers/infiniband/hw/mlx5/cq.c +++ b/drivers/infiniband/hw/mlx5/cq.c @@ -932,8 +932,7 @@ struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev, if (err) goto err_create; } else { - /* for now choose 64 bytes till we have a proper interface */ - cqe_size = 64; + cqe_size = cache_line_size() == 128 ? 128 : 64; err = create_cq_kernel(dev, cq, entries, cqe_size, &cqb, &index, &inlen); if (err) diff --git a/drivers/infiniband/hw/mlx5/main.c b/drivers/infiniband/hw/mlx5/main.c index 63036c731626..32b09f059c84 100644 --- a/drivers/infiniband/hw/mlx5/main.c +++ b/drivers/infiniband/hw/mlx5/main.c @@ -2311,14 +2311,14 @@ static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context, { struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context; struct ib_event ibev; - + bool fatal = false; u8 port = 0; switch (event) { case MLX5_DEV_EVENT_SYS_ERROR: - ibdev->ib_active = false; ibev.event = IB_EVENT_DEVICE_FATAL; mlx5_ib_handle_internal_error(ibdev); + fatal = true; break; case MLX5_DEV_EVENT_PORT_UP: @@ -2370,6 +2370,9 @@ static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context, if (ibdev->ib_active) ib_dispatch_event(&ibev); + + if (fatal) + ibdev->ib_active = false; } static void get_ext_port_caps(struct mlx5_ib_dev *dev) @@ -3115,7 +3118,7 @@ static void *mlx5_ib_add(struct mlx5_core_dev *mdev) } err = init_node_data(dev); if (err) - goto err_dealloc; + goto err_free_port; mutex_init(&dev->flow_db.lock); mutex_init(&dev->cap_mask_mutex); @@ -3125,7 +3128,7 @@ static void *mlx5_ib_add(struct mlx5_core_dev *mdev) if (ll == IB_LINK_LAYER_ETHERNET) { err = mlx5_enable_roce(dev); if (err) - goto err_dealloc; + goto err_free_port; } err = create_dev_resources(&dev->devr); diff --git a/drivers/infiniband/hw/mlx5/mlx5_ib.h b/drivers/infiniband/hw/mlx5/mlx5_ib.h index dcdcd195fe53..7d689903c87c 100644 --- a/drivers/infiniband/hw/mlx5/mlx5_ib.h +++ b/drivers/infiniband/hw/mlx5/mlx5_ib.h @@ -626,6 +626,8 @@ struct mlx5_ib_dev { struct mlx5_ib_resources devr; struct mlx5_mr_cache cache; struct timer_list delay_timer; + /* Prevents soft lock on massive reg MRs */ + struct mutex slow_path_mutex; int fill_delay; #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING struct ib_odp_caps odp_caps; diff --git a/drivers/infiniband/hw/mlx5/mr.c b/drivers/infiniband/hw/mlx5/mr.c index d4ad672b905b..4e9012463c37 100644 --- a/drivers/infiniband/hw/mlx5/mr.c +++ b/drivers/infiniband/hw/mlx5/mr.c @@ -610,6 +610,7 @@ int mlx5_mr_cache_init(struct mlx5_ib_dev *dev) int err; int i; + mutex_init(&dev->slow_path_mutex); cache->wq = alloc_ordered_workqueue("mkey_cache", WQ_MEM_RECLAIM); if (!cache->wq) { mlx5_ib_warn(dev, "failed to create work queue\n"); @@ -1182,9 +1183,12 @@ struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, goto error; } - if (!mr) + if (!mr) { + mutex_lock(&dev->slow_path_mutex); mr = reg_create(NULL, pd, virt_addr, length, umem, ncont, page_shift, access_flags); + mutex_unlock(&dev->slow_path_mutex); + } if (IS_ERR(mr)) { err = PTR_ERR(mr); diff --git a/drivers/infiniband/hw/mlx5/qp.c b/drivers/infiniband/hw/mlx5/qp.c index 7ce97daf26c6..d1e921816bfe 100644 --- a/drivers/infiniband/hw/mlx5/qp.c +++ b/drivers/infiniband/hw/mlx5/qp.c @@ -2051,8 +2051,8 @@ struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n", qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn, - to_mcq(init_attr->recv_cq)->mcq.cqn, - to_mcq(init_attr->send_cq)->mcq.cqn); + init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1, + init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1); qp->trans_qp.xrcdn = xrcdn; @@ -4814,6 +4814,14 @@ struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, udata->inlen)) return ERR_PTR(-EOPNOTSUPP); + if (init_attr->log_ind_tbl_size > + MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) { + mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n", + init_attr->log_ind_tbl_size, + MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)); + return ERR_PTR(-EINVAL); + } + min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); if (udata->outlen && udata->outlen < min_resp_len) return ERR_PTR(-EINVAL); diff --git a/drivers/infiniband/sw/rdmavt/dma.c b/drivers/infiniband/sw/rdmavt/dma.c index 01f71caa3ac4..f2cefb0d9180 100644 --- a/drivers/infiniband/sw/rdmavt/dma.c +++ b/drivers/infiniband/sw/rdmavt/dma.c @@ -90,9 +90,6 @@ static u64 rvt_dma_map_page(struct ib_device *dev, struct page *page, if (WARN_ON(!valid_dma_direction(direction))) return BAD_DMA_ADDRESS; - if (offset + size > PAGE_SIZE) - return BAD_DMA_ADDRESS; - addr = (u64)page_address(page); if (addr) addr += offset; diff --git a/drivers/infiniband/sw/rxe/rxe_net.c b/drivers/infiniband/sw/rxe/rxe_net.c index b8258e4f0aea..ffff5a54cb34 100644 --- a/drivers/infiniband/sw/rxe/rxe_net.c +++ b/drivers/infiniband/sw/rxe/rxe_net.c @@ -243,10 +243,8 @@ static struct socket *rxe_setup_udp_tunnel(struct net *net, __be16 port, { int err; struct socket *sock; - struct udp_port_cfg udp_cfg; - struct udp_tunnel_sock_cfg tnl_cfg; - - memset(&udp_cfg, 0, sizeof(udp_cfg)); + struct udp_port_cfg udp_cfg = {0}; + struct udp_tunnel_sock_cfg tnl_cfg = {0}; if (ipv6) { udp_cfg.family = AF_INET6; @@ -264,10 +262,8 @@ static struct socket *rxe_setup_udp_tunnel(struct net *net, __be16 port, return ERR_PTR(err); } - tnl_cfg.sk_user_data = NULL; tnl_cfg.encap_type = 1; tnl_cfg.encap_rcv = rxe_udp_encap_recv; - tnl_cfg.encap_destroy = NULL; /* Setup UDP tunnel */ setup_udp_tunnel_sock(net, sock, &tnl_cfg); diff --git a/drivers/infiniband/sw/rxe/rxe_qp.c b/drivers/infiniband/sw/rxe/rxe_qp.c index b8036cfbce04..c3e60e4bde6e 100644 --- a/drivers/infiniband/sw/rxe/rxe_qp.c +++ b/drivers/infiniband/sw/rxe/rxe_qp.c @@ -522,6 +522,7 @@ static void rxe_qp_reset(struct rxe_qp *qp) if (qp->sq.queue) { __rxe_do_task(&qp->comp.task); __rxe_do_task(&qp->req.task); + rxe_queue_reset(qp->sq.queue); } /* cleanup attributes */ @@ -573,6 +574,7 @@ void rxe_qp_error(struct rxe_qp *qp) { qp->req.state = QP_STATE_ERROR; qp->resp.state = QP_STATE_ERROR; + qp->attr.qp_state = IB_QPS_ERR; /* drain work and packet queues */ rxe_run_task(&qp->resp.task, 1); diff --git a/drivers/infiniband/sw/rxe/rxe_queue.c b/drivers/infiniband/sw/rxe/rxe_queue.c index 08274254eb88..d14bf496d62d 100644 --- a/drivers/infiniband/sw/rxe/rxe_queue.c +++ b/drivers/infiniband/sw/rxe/rxe_queue.c @@ -84,6 +84,15 @@ err1: return -EINVAL; } +inline void rxe_queue_reset(struct rxe_queue *q) +{ + /* queue is comprised from header and the memory + * of the actual queue. See "struct rxe_queue_buf" in rxe_queue.h + * reset only the queue itself and not the management header + */ + memset(q->buf->data, 0, q->buf_size - sizeof(struct rxe_queue_buf)); +} + struct rxe_queue *rxe_queue_init(struct rxe_dev *rxe, int *num_elem, unsigned int elem_size) diff --git a/drivers/infiniband/sw/rxe/rxe_queue.h b/drivers/infiniband/sw/rxe/rxe_queue.h index 239fd609c31e..8c8641c87817 100644 --- a/drivers/infiniband/sw/rxe/rxe_queue.h +++ b/drivers/infiniband/sw/rxe/rxe_queue.h @@ -84,6 +84,8 @@ int do_mmap_info(struct rxe_dev *rxe, size_t buf_size, struct rxe_mmap_info **ip_p); +void rxe_queue_reset(struct rxe_queue *q); + struct rxe_queue *rxe_queue_init(struct rxe_dev *rxe, int *num_elem, unsigned int elem_size); diff --git a/drivers/infiniband/sw/rxe/rxe_req.c b/drivers/infiniband/sw/rxe/rxe_req.c index 832846b73ea0..22bd9630dcd9 100644 --- a/drivers/infiniband/sw/rxe/rxe_req.c +++ b/drivers/infiniband/sw/rxe/rxe_req.c @@ -696,7 +696,8 @@ next_wqe: qp->req.wqe_index); wqe->state = wqe_state_done; wqe->status = IB_WC_SUCCESS; - goto complete; + __rxe_do_task(&qp->comp.task); + return 0; } payload = mtu; } @@ -745,13 +746,17 @@ err: wqe->status = IB_WC_LOC_PROT_ERR; wqe->state = wqe_state_error; -complete: - if (qp_type(qp) != IB_QPT_RC) { - while (rxe_completer(qp) == 0) - ; - } - - return 0; + /* + * IBA Spec. Section 10.7.3.1 SIGNALED COMPLETIONS + * ---------8<---------8<------------- + * ...Note that if a completion error occurs, a Work Completion + * will always be generated, even if the signaling + * indicator requests an Unsignaled Completion. + * ---------8<---------8<------------- + */ + wqe->wr.send_flags |= IB_SEND_SIGNALED; + __rxe_do_task(&qp->comp.task); + return -EAGAIN; exit: return -EAGAIN; diff --git a/drivers/input/mouse/psmouse-base.c b/drivers/input/mouse/psmouse-base.c index fb4b185dea96..bee267424972 100644 --- a/drivers/input/mouse/psmouse-base.c +++ b/drivers/input/mouse/psmouse-base.c @@ -1115,10 +1115,6 @@ static int psmouse_extensions(struct psmouse *psmouse, if (psmouse_try_protocol(psmouse, PSMOUSE_TOUCHKIT_PS2, &max_proto, set_properties, true)) return PSMOUSE_TOUCHKIT_PS2; - - if (psmouse_try_protocol(psmouse, PSMOUSE_BYD, - &max_proto, set_properties, true)) - return PSMOUSE_BYD; } /* diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index 15c01c3cd540..e6f9b2d745ca 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -2636,17 +2636,26 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev) /* And we're up. Go go go! */ of_iommu_set_ops(dev->of_node, &arm_smmu_ops); #ifdef CONFIG_PCI - pci_request_acs(); - ret = bus_set_iommu(&pci_bus_type, &arm_smmu_ops); - if (ret) - return ret; + if (pci_bus_type.iommu_ops != &arm_smmu_ops) { + pci_request_acs(); + ret = bus_set_iommu(&pci_bus_type, &arm_smmu_ops); + if (ret) + return ret; + } #endif #ifdef CONFIG_ARM_AMBA - ret = bus_set_iommu(&amba_bustype, &arm_smmu_ops); - if (ret) - return ret; + if (amba_bustype.iommu_ops != &arm_smmu_ops) { + ret = bus_set_iommu(&amba_bustype, &arm_smmu_ops); + if (ret) + return ret; + } #endif - return bus_set_iommu(&platform_bus_type, &arm_smmu_ops); + if (platform_bus_type.iommu_ops != &arm_smmu_ops) { + ret = bus_set_iommu(&platform_bus_type, &arm_smmu_ops); + if (ret) + return ret; + } + return 0; } static int arm_smmu_device_remove(struct platform_device *pdev) diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index c841eb7a1a74..8f7281444551 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -324,8 +324,10 @@ struct arm_smmu_master_cfg { #define INVALID_SMENDX -1 #define __fwspec_cfg(fw) ((struct arm_smmu_master_cfg *)fw->iommu_priv) #define fwspec_smmu(fw) (__fwspec_cfg(fw)->smmu) +#define fwspec_smendx(fw, i) \ + (i >= fw->num_ids ? INVALID_SMENDX : __fwspec_cfg(fw)->smendx[i]) #define for_each_cfg_sme(fw, i, idx) \ - for (i = 0; idx = __fwspec_cfg(fw)->smendx[i], i < fw->num_ids; ++i) + for (i = 0; idx = fwspec_smendx(fw, i), i < fw->num_ids; ++i) struct arm_smmu_device { struct device *dev; @@ -1228,6 +1230,16 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) return -ENXIO; } + /* + * FIXME: The arch/arm DMA API code tries to attach devices to its own + * domains between of_xlate() and add_device() - we have no way to cope + * with that, so until ARM gets converted to rely on groups and default + * domains, just say no (but more politely than by dereferencing NULL). + * This should be at least a WARN_ON once that's sorted. + */ + if (!fwspec->iommu_priv) + return -ENODEV; + smmu = fwspec_smmu(fwspec); /* Ensure that the domain is finalised */ ret = arm_smmu_init_domain_context(domain, smmu); @@ -1390,7 +1402,7 @@ static int arm_smmu_add_device(struct device *dev) fwspec = dev->iommu_fwspec; if (ret) goto out_free; - } else if (fwspec) { + } else if (fwspec && fwspec->ops == &arm_smmu_ops) { smmu = arm_smmu_get_by_node(to_of_node(fwspec->iommu_fwnode)); } else { return -ENODEV; diff --git a/drivers/iommu/dmar.c b/drivers/iommu/dmar.c index 58470f5ced04..8c53748a769d 100644 --- a/drivers/iommu/dmar.c +++ b/drivers/iommu/dmar.c @@ -338,7 +338,9 @@ static int dmar_pci_bus_notifier(struct notifier_block *nb, struct pci_dev *pdev = to_pci_dev(data); struct dmar_pci_notify_info *info; - /* Only care about add/remove events for physical functions */ + /* Only care about add/remove events for physical functions. + * For VFs we actually do the lookup based on the corresponding + * PF in device_to_iommu() anyway. */ if (pdev->is_virtfn) return NOTIFY_DONE; if (action != BUS_NOTIFY_ADD_DEVICE && diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c index a4407eabf0e6..d8376c2d18b3 100644 --- a/drivers/iommu/intel-iommu.c +++ b/drivers/iommu/intel-iommu.c @@ -892,7 +892,13 @@ static struct intel_iommu *device_to_iommu(struct device *dev, u8 *bus, u8 *devf return NULL; if (dev_is_pci(dev)) { + struct pci_dev *pf_pdev; + pdev = to_pci_dev(dev); + /* VFs aren't listed in scope tables; we need to look up + * the PF instead to find the IOMMU. */ + pf_pdev = pci_physfn(pdev); + dev = &pf_pdev->dev; segment = pci_domain_nr(pdev->bus); } else if (has_acpi_companion(dev)) dev = &ACPI_COMPANION(dev)->dev; @@ -905,6 +911,13 @@ static struct intel_iommu *device_to_iommu(struct device *dev, u8 *bus, u8 *devf for_each_active_dev_scope(drhd->devices, drhd->devices_cnt, i, tmp) { if (tmp == dev) { + /* For a VF use its original BDF# not that of the PF + * which we used for the IOMMU lookup. Strictly speaking + * we could do this for all PCI devices; we only need to + * get the BDF# from the scope table for ACPI matches. */ + if (pdev->is_virtfn) + goto got_pdev; + *bus = drhd->devices[i].bus; *devfn = drhd->devices[i].devfn; goto out; @@ -1711,6 +1724,7 @@ static void disable_dmar_iommu(struct intel_iommu *iommu) if (!iommu->domains || !iommu->domain_ids) return; +again: spin_lock_irqsave(&device_domain_lock, flags); list_for_each_entry_safe(info, tmp, &device_domain_list, global) { struct dmar_domain *domain; @@ -1723,10 +1737,19 @@ static void disable_dmar_iommu(struct intel_iommu *iommu) domain = info->domain; - dmar_remove_one_dev_info(domain, info->dev); + __dmar_remove_one_dev_info(info); - if (!domain_type_is_vm_or_si(domain)) + if (!domain_type_is_vm_or_si(domain)) { + /* + * The domain_exit() function can't be called under + * device_domain_lock, as it takes this lock itself. + * So release the lock here and re-run the loop + * afterwards. + */ + spin_unlock_irqrestore(&device_domain_lock, flags); domain_exit(domain); + goto again; + } } spin_unlock_irqrestore(&device_domain_lock, flags); diff --git a/drivers/iommu/intel-svm.c b/drivers/iommu/intel-svm.c index 8ebb3530afa7..cb72e0011310 100644 --- a/drivers/iommu/intel-svm.c +++ b/drivers/iommu/intel-svm.c @@ -39,10 +39,18 @@ int intel_svm_alloc_pasid_tables(struct intel_iommu *iommu) struct page *pages; int order; - order = ecap_pss(iommu->ecap) + 7 - PAGE_SHIFT; - if (order < 0) - order = 0; - + /* Start at 2 because it's defined as 2^(1+PSS) */ + iommu->pasid_max = 2 << ecap_pss(iommu->ecap); + + /* Eventually I'm promised we will get a multi-level PASID table + * and it won't have to be physically contiguous. Until then, + * limit the size because 8MiB contiguous allocations can be hard + * to come by. The limit of 0x20000, which is 1MiB for each of + * the PASID and PASID-state tables, is somewhat arbitrary. */ + if (iommu->pasid_max > 0x20000) + iommu->pasid_max = 0x20000; + + order = get_order(sizeof(struct pasid_entry) * iommu->pasid_max); pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, order); if (!pages) { pr_warn("IOMMU: %s: Failed to allocate PASID table\n", @@ -53,6 +61,8 @@ int intel_svm_alloc_pasid_tables(struct intel_iommu *iommu) pr_info("%s: Allocated order %d PASID table.\n", iommu->name, order); if (ecap_dis(iommu->ecap)) { + /* Just making it explicit... */ + BUILD_BUG_ON(sizeof(struct pasid_entry) != sizeof(struct pasid_state_entry)); pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, order); if (pages) iommu->pasid_state_table = page_address(pages); @@ -68,11 +78,7 @@ int intel_svm_alloc_pasid_tables(struct intel_iommu *iommu) int intel_svm_free_pasid_tables(struct intel_iommu *iommu) { - int order; - - order = ecap_pss(iommu->ecap) + 7 - PAGE_SHIFT; - if (order < 0) - order = 0; + int order = get_order(sizeof(struct pasid_entry) * iommu->pasid_max); if (iommu->pasid_table) { free_pages((unsigned long)iommu->pasid_table, order); @@ -371,8 +377,8 @@ int intel_svm_bind_mm(struct device *dev, int *pasid, int flags, struct svm_dev_ } svm->iommu = iommu; - if (pasid_max > 2 << ecap_pss(iommu->ecap)) - pasid_max = 2 << ecap_pss(iommu->ecap); + if (pasid_max > iommu->pasid_max) + pasid_max = iommu->pasid_max; /* Do not use PASID 0 in caching mode (virtualised IOMMU) */ ret = idr_alloc(&iommu->pasid_idr, svm, diff --git a/drivers/mailbox/pcc.c b/drivers/mailbox/pcc.c index 08c87fadca8c..1f32688c312d 100644 --- a/drivers/mailbox/pcc.c +++ b/drivers/mailbox/pcc.c @@ -65,6 +65,7 @@ #include <linux/mailbox_controller.h> #include <linux/mailbox_client.h> #include <linux/io-64-nonatomic-lo-hi.h> +#include <acpi/pcc.h> #include "mailbox.h" @@ -267,6 +268,8 @@ struct mbox_chan *pcc_mbox_request_channel(struct mbox_client *cl, if (chan->txdone_method == TXDONE_BY_POLL && cl->knows_txdone) chan->txdone_method |= TXDONE_BY_ACK; + spin_unlock_irqrestore(&chan->lock, flags); + if (pcc_doorbell_irq[subspace_id] > 0) { int rc; @@ -275,12 +278,11 @@ struct mbox_chan *pcc_mbox_request_channel(struct mbox_client *cl, if (unlikely(rc)) { dev_err(dev, "failed to register PCC interrupt %d\n", pcc_doorbell_irq[subspace_id]); + pcc_mbox_free_channel(chan); chan = ERR_PTR(rc); } } - spin_unlock_irqrestore(&chan->lock, flags); - return chan; } EXPORT_SYMBOL_GPL(pcc_mbox_request_channel); @@ -304,20 +306,19 @@ void pcc_mbox_free_channel(struct mbox_chan *chan) return; } + if (pcc_doorbell_irq[id] > 0) + devm_free_irq(chan->mbox->dev, pcc_doorbell_irq[id], chan); + spin_lock_irqsave(&chan->lock, flags); chan->cl = NULL; chan->active_req = NULL; if (chan->txdone_method == (TXDONE_BY_POLL | TXDONE_BY_ACK)) chan->txdone_method = TXDONE_BY_POLL; - if (pcc_doorbell_irq[id] > 0) - devm_free_irq(chan->mbox->dev, pcc_doorbell_irq[id], chan); - spin_unlock_irqrestore(&chan->lock, flags); } EXPORT_SYMBOL_GPL(pcc_mbox_free_channel); - /** * pcc_send_data - Called from Mailbox Controller code. Used * here only to ring the channel doorbell. The PCC client diff --git a/drivers/media/dvb-frontends/Kconfig b/drivers/media/dvb-frontends/Kconfig index 012225587c25..b71b747ee0ba 100644 --- a/drivers/media/dvb-frontends/Kconfig +++ b/drivers/media/dvb-frontends/Kconfig @@ -513,6 +513,11 @@ config DVB_AS102_FE depends on DVB_CORE default DVB_AS102 +config DVB_GP8PSK_FE + tristate + depends on DVB_CORE + default DVB_USB_GP8PSK + comment "DVB-C (cable) frontends" depends on DVB_CORE diff --git a/drivers/media/dvb-frontends/Makefile b/drivers/media/dvb-frontends/Makefile index e90165ad361b..93921a4eaa27 100644 --- a/drivers/media/dvb-frontends/Makefile +++ b/drivers/media/dvb-frontends/Makefile @@ -121,6 +121,7 @@ obj-$(CONFIG_DVB_RTL2832_SDR) += rtl2832_sdr.o obj-$(CONFIG_DVB_M88RS2000) += m88rs2000.o obj-$(CONFIG_DVB_AF9033) += af9033.o obj-$(CONFIG_DVB_AS102_FE) += as102_fe.o +obj-$(CONFIG_DVB_GP8PSK_FE) += gp8psk-fe.o obj-$(CONFIG_DVB_TC90522) += tc90522.o obj-$(CONFIG_DVB_HORUS3A) += horus3a.o obj-$(CONFIG_DVB_ASCOT2E) += ascot2e.o diff --git a/drivers/media/usb/dvb-usb/gp8psk-fe.c b/drivers/media/dvb-frontends/gp8psk-fe.c index db6eb79cde07..93f59bfea092 100644 --- a/drivers/media/usb/dvb-usb/gp8psk-fe.c +++ b/drivers/media/dvb-frontends/gp8psk-fe.c @@ -1,5 +1,5 @@ -/* DVB USB compliant Linux driver for the - * - GENPIX 8pks/qpsk/DCII USB2.0 DVB-S module +/* + * Frontend driver for the GENPIX 8pks/qpsk/DCII USB2.0 DVB-S module * * Copyright (C) 2006,2007 Alan Nisota (alannisota@gmail.com) * Copyright (C) 2006,2007 Genpix Electronics (genpix@genpix-electronics.com) @@ -8,17 +8,31 @@ * * This module is based off the vp7045 and vp702x modules * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the Free - * Software Foundation, version 2. - * - * see Documentation/dvb/README.dvb-usb for more information + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation, version 2. */ -#include "gp8psk.h" + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include "gp8psk-fe.h" +#include "dvb_frontend.h" + +static int debug; +module_param(debug, int, 0644); +MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off)."); + +#define dprintk(fmt, arg...) do { \ + if (debug) \ + printk(KERN_DEBUG pr_fmt("%s: " fmt), \ + __func__, ##arg); \ +} while (0) struct gp8psk_fe_state { struct dvb_frontend fe; - struct dvb_usb_device *d; + void *priv; + const struct gp8psk_fe_ops *ops; + bool is_rev1; u8 lock; u16 snr; unsigned long next_status_check; @@ -29,22 +43,24 @@ static int gp8psk_tuned_to_DCII(struct dvb_frontend *fe) { struct gp8psk_fe_state *st = fe->demodulator_priv; u8 status; - gp8psk_usb_in_op(st->d, GET_8PSK_CONFIG, 0, 0, &status, 1); + + st->ops->in(st->priv, GET_8PSK_CONFIG, 0, 0, &status, 1); return status & bmDCtuned; } static int gp8psk_set_tuner_mode(struct dvb_frontend *fe, int mode) { - struct gp8psk_fe_state *state = fe->demodulator_priv; - return gp8psk_usb_out_op(state->d, SET_8PSK_CONFIG, mode, 0, NULL, 0); + struct gp8psk_fe_state *st = fe->demodulator_priv; + + return st->ops->out(st->priv, SET_8PSK_CONFIG, mode, 0, NULL, 0); } static int gp8psk_fe_update_status(struct gp8psk_fe_state *st) { u8 buf[6]; if (time_after(jiffies,st->next_status_check)) { - gp8psk_usb_in_op(st->d, GET_SIGNAL_LOCK, 0,0,&st->lock,1); - gp8psk_usb_in_op(st->d, GET_SIGNAL_STRENGTH, 0,0,buf,6); + st->ops->in(st->priv, GET_SIGNAL_LOCK, 0, 0, &st->lock, 1); + st->ops->in(st->priv, GET_SIGNAL_STRENGTH, 0, 0, buf, 6); st->snr = (buf[1]) << 8 | buf[0]; st->next_status_check = jiffies + (st->status_check_interval*HZ)/1000; } @@ -116,13 +132,12 @@ static int gp8psk_fe_get_tune_settings(struct dvb_frontend* fe, struct dvb_front static int gp8psk_fe_set_frontend(struct dvb_frontend *fe) { - struct gp8psk_fe_state *state = fe->demodulator_priv; + struct gp8psk_fe_state *st = fe->demodulator_priv; struct dtv_frontend_properties *c = &fe->dtv_property_cache; u8 cmd[10]; u32 freq = c->frequency * 1000; - int gp_product_id = le16_to_cpu(state->d->udev->descriptor.idProduct); - deb_fe("%s()\n", __func__); + dprintk("%s()\n", __func__); cmd[4] = freq & 0xff; cmd[5] = (freq >> 8) & 0xff; @@ -136,21 +151,21 @@ static int gp8psk_fe_set_frontend(struct dvb_frontend *fe) switch (c->delivery_system) { case SYS_DVBS: if (c->modulation != QPSK) { - deb_fe("%s: unsupported modulation selected (%d)\n", + dprintk("%s: unsupported modulation selected (%d)\n", __func__, c->modulation); return -EOPNOTSUPP; } c->fec_inner = FEC_AUTO; break; case SYS_DVBS2: /* kept for backwards compatibility */ - deb_fe("%s: DVB-S2 delivery system selected\n", __func__); + dprintk("%s: DVB-S2 delivery system selected\n", __func__); break; case SYS_TURBO: - deb_fe("%s: Turbo-FEC delivery system selected\n", __func__); + dprintk("%s: Turbo-FEC delivery system selected\n", __func__); break; default: - deb_fe("%s: unsupported delivery system selected (%d)\n", + dprintk("%s: unsupported delivery system selected (%d)\n", __func__, c->delivery_system); return -EOPNOTSUPP; } @@ -161,9 +176,9 @@ static int gp8psk_fe_set_frontend(struct dvb_frontend *fe) cmd[3] = (c->symbol_rate >> 24) & 0xff; switch (c->modulation) { case QPSK: - if (gp_product_id == USB_PID_GENPIX_8PSK_REV_1_WARM) + if (st->is_rev1) if (gp8psk_tuned_to_DCII(fe)) - gp8psk_bcm4500_reload(state->d); + st->ops->reload(st->priv); switch (c->fec_inner) { case FEC_1_2: cmd[9] = 0; break; @@ -207,18 +222,18 @@ static int gp8psk_fe_set_frontend(struct dvb_frontend *fe) cmd[9] = 0; break; default: /* Unknown modulation */ - deb_fe("%s: unsupported modulation selected (%d)\n", + dprintk("%s: unsupported modulation selected (%d)\n", __func__, c->modulation); return -EOPNOTSUPP; } - if (gp_product_id == USB_PID_GENPIX_8PSK_REV_1_WARM) + if (st->is_rev1) gp8psk_set_tuner_mode(fe, 0); - gp8psk_usb_out_op(state->d, TUNE_8PSK, 0, 0, cmd, 10); + st->ops->out(st->priv, TUNE_8PSK, 0, 0, cmd, 10); - state->lock = 0; - state->next_status_check = jiffies; - state->status_check_interval = 200; + st->lock = 0; + st->next_status_check = jiffies; + st->status_check_interval = 200; return 0; } @@ -228,9 +243,9 @@ static int gp8psk_fe_send_diseqc_msg (struct dvb_frontend* fe, { struct gp8psk_fe_state *st = fe->demodulator_priv; - deb_fe("%s\n",__func__); + dprintk("%s\n", __func__); - if (gp8psk_usb_out_op(st->d,SEND_DISEQC_COMMAND, m->msg[0], 0, + if (st->ops->out(st->priv, SEND_DISEQC_COMMAND, m->msg[0], 0, m->msg, m->msg_len)) { return -EINVAL; } @@ -243,12 +258,12 @@ static int gp8psk_fe_send_diseqc_burst(struct dvb_frontend *fe, struct gp8psk_fe_state *st = fe->demodulator_priv; u8 cmd; - deb_fe("%s\n",__func__); + dprintk("%s\n", __func__); /* These commands are certainly wrong */ cmd = (burst == SEC_MINI_A) ? 0x00 : 0x01; - if (gp8psk_usb_out_op(st->d,SEND_DISEQC_COMMAND, cmd, 0, + if (st->ops->out(st->priv, SEND_DISEQC_COMMAND, cmd, 0, &cmd, 0)) { return -EINVAL; } @@ -258,10 +273,10 @@ static int gp8psk_fe_send_diseqc_burst(struct dvb_frontend *fe, static int gp8psk_fe_set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone) { - struct gp8psk_fe_state* state = fe->demodulator_priv; + struct gp8psk_fe_state *st = fe->demodulator_priv; - if (gp8psk_usb_out_op(state->d,SET_22KHZ_TONE, - (tone == SEC_TONE_ON), 0, NULL, 0)) { + if (st->ops->out(st->priv, SET_22KHZ_TONE, + (tone == SEC_TONE_ON), 0, NULL, 0)) { return -EINVAL; } return 0; @@ -270,9 +285,9 @@ static int gp8psk_fe_set_tone(struct dvb_frontend *fe, static int gp8psk_fe_set_voltage(struct dvb_frontend *fe, enum fe_sec_voltage voltage) { - struct gp8psk_fe_state* state = fe->demodulator_priv; + struct gp8psk_fe_state *st = fe->demodulator_priv; - if (gp8psk_usb_out_op(state->d,SET_LNB_VOLTAGE, + if (st->ops->out(st->priv, SET_LNB_VOLTAGE, voltage == SEC_VOLTAGE_18, 0, NULL, 0)) { return -EINVAL; } @@ -281,52 +296,60 @@ static int gp8psk_fe_set_voltage(struct dvb_frontend *fe, static int gp8psk_fe_enable_high_lnb_voltage(struct dvb_frontend* fe, long onoff) { - struct gp8psk_fe_state* state = fe->demodulator_priv; - return gp8psk_usb_out_op(state->d, USE_EXTRA_VOLT, onoff, 0,NULL,0); + struct gp8psk_fe_state *st = fe->demodulator_priv; + + return st->ops->out(st->priv, USE_EXTRA_VOLT, onoff, 0, NULL, 0); } static int gp8psk_fe_send_legacy_dish_cmd (struct dvb_frontend* fe, unsigned long sw_cmd) { - struct gp8psk_fe_state* state = fe->demodulator_priv; + struct gp8psk_fe_state *st = fe->demodulator_priv; u8 cmd = sw_cmd & 0x7f; - if (gp8psk_usb_out_op(state->d,SET_DN_SWITCH, cmd, 0, - NULL, 0)) { + if (st->ops->out(st->priv, SET_DN_SWITCH, cmd, 0, NULL, 0)) return -EINVAL; - } - if (gp8psk_usb_out_op(state->d,SET_LNB_VOLTAGE, !!(sw_cmd & 0x80), - 0, NULL, 0)) { + + if (st->ops->out(st->priv, SET_LNB_VOLTAGE, !!(sw_cmd & 0x80), + 0, NULL, 0)) return -EINVAL; - } return 0; } static void gp8psk_fe_release(struct dvb_frontend* fe) { - struct gp8psk_fe_state *state = fe->demodulator_priv; - kfree(state); + struct gp8psk_fe_state *st = fe->demodulator_priv; + + kfree(st); } static struct dvb_frontend_ops gp8psk_fe_ops; -struct dvb_frontend * gp8psk_fe_attach(struct dvb_usb_device *d) +struct dvb_frontend *gp8psk_fe_attach(const struct gp8psk_fe_ops *ops, + void *priv, bool is_rev1) { - struct gp8psk_fe_state *s = kzalloc(sizeof(struct gp8psk_fe_state), GFP_KERNEL); - if (s == NULL) - goto error; - - s->d = d; - memcpy(&s->fe.ops, &gp8psk_fe_ops, sizeof(struct dvb_frontend_ops)); - s->fe.demodulator_priv = s; - - goto success; -error: - return NULL; -success: - return &s->fe; -} + struct gp8psk_fe_state *st; + if (!ops || !ops->in || !ops->out || !ops->reload) { + pr_err("Error! gp8psk-fe ops not defined.\n"); + return NULL; + } + + st = kzalloc(sizeof(struct gp8psk_fe_state), GFP_KERNEL); + if (!st) + return NULL; + + memcpy(&st->fe.ops, &gp8psk_fe_ops, sizeof(struct dvb_frontend_ops)); + st->fe.demodulator_priv = st; + st->ops = ops; + st->priv = priv; + st->is_rev1 = is_rev1; + + pr_info("Frontend %sattached\n", is_rev1 ? "revision 1 " : ""); + + return &st->fe; +} +EXPORT_SYMBOL_GPL(gp8psk_fe_attach); static struct dvb_frontend_ops gp8psk_fe_ops = { .delsys = { SYS_DVBS }, @@ -370,3 +393,8 @@ static struct dvb_frontend_ops gp8psk_fe_ops = { .dishnetwork_send_legacy_command = gp8psk_fe_send_legacy_dish_cmd, .enable_high_lnb_voltage = gp8psk_fe_enable_high_lnb_voltage }; + +MODULE_AUTHOR("Alan Nisota <alannisota@gamil.com>"); +MODULE_DESCRIPTION("Frontend Driver for Genpix DVB-S"); +MODULE_VERSION("1.1"); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/dvb-frontends/gp8psk-fe.h b/drivers/media/dvb-frontends/gp8psk-fe.h new file mode 100644 index 000000000000..6c7944b1ecd6 --- /dev/null +++ b/drivers/media/dvb-frontends/gp8psk-fe.h @@ -0,0 +1,82 @@ +/* + * gp8psk_fe driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef GP8PSK_FE_H +#define GP8PSK_FE_H + +#include <linux/types.h> + +/* gp8psk commands */ + +#define GET_8PSK_CONFIG 0x80 /* in */ +#define SET_8PSK_CONFIG 0x81 +#define I2C_WRITE 0x83 +#define I2C_READ 0x84 +#define ARM_TRANSFER 0x85 +#define TUNE_8PSK 0x86 +#define GET_SIGNAL_STRENGTH 0x87 /* in */ +#define LOAD_BCM4500 0x88 +#define BOOT_8PSK 0x89 /* in */ +#define START_INTERSIL 0x8A /* in */ +#define SET_LNB_VOLTAGE 0x8B +#define SET_22KHZ_TONE 0x8C +#define SEND_DISEQC_COMMAND 0x8D +#define SET_DVB_MODE 0x8E +#define SET_DN_SWITCH 0x8F +#define GET_SIGNAL_LOCK 0x90 /* in */ +#define GET_FW_VERS 0x92 +#define GET_SERIAL_NUMBER 0x93 /* in */ +#define USE_EXTRA_VOLT 0x94 +#define GET_FPGA_VERS 0x95 +#define CW3K_INIT 0x9d + +/* PSK_configuration bits */ +#define bm8pskStarted 0x01 +#define bm8pskFW_Loaded 0x02 +#define bmIntersilOn 0x04 +#define bmDVBmode 0x08 +#define bm22kHz 0x10 +#define bmSEL18V 0x20 +#define bmDCtuned 0x40 +#define bmArmed 0x80 + +/* Satellite modulation modes */ +#define ADV_MOD_DVB_QPSK 0 /* DVB-S QPSK */ +#define ADV_MOD_TURBO_QPSK 1 /* Turbo QPSK */ +#define ADV_MOD_TURBO_8PSK 2 /* Turbo 8PSK (also used for Trellis 8PSK) */ +#define ADV_MOD_TURBO_16QAM 3 /* Turbo 16QAM (also used for Trellis 8PSK) */ + +#define ADV_MOD_DCII_C_QPSK 4 /* Digicipher II Combo */ +#define ADV_MOD_DCII_I_QPSK 5 /* Digicipher II I-stream */ +#define ADV_MOD_DCII_Q_QPSK 6 /* Digicipher II Q-stream */ +#define ADV_MOD_DCII_C_OQPSK 7 /* Digicipher II offset QPSK */ +#define ADV_MOD_DSS_QPSK 8 /* DSS (DIRECTV) QPSK */ +#define ADV_MOD_DVB_BPSK 9 /* DVB-S BPSK */ + +/* firmware revision id's */ +#define GP8PSK_FW_REV1 0x020604 +#define GP8PSK_FW_REV2 0x020704 +#define GP8PSK_FW_VERS(_fw_vers) \ + ((_fw_vers)[2]<<0x10 | (_fw_vers)[1]<<0x08 | (_fw_vers)[0]) + +struct gp8psk_fe_ops { + int (*in)(void *priv, u8 req, u16 value, u16 index, u8 *b, int blen); + int (*out)(void *priv, u8 req, u16 value, u16 index, u8 *b, int blen); + int (*reload)(void *priv); +}; + +struct dvb_frontend *gp8psk_fe_attach(const struct gp8psk_fe_ops *ops, + void *priv, bool is_rev1); + +#endif diff --git a/drivers/media/i2c/ir-kbd-i2c.c b/drivers/media/i2c/ir-kbd-i2c.c index f95a6bc839d5..cede3975d04b 100644 --- a/drivers/media/i2c/ir-kbd-i2c.c +++ b/drivers/media/i2c/ir-kbd-i2c.c @@ -118,7 +118,7 @@ static int get_key_haup_common(struct IR_i2c *ir, enum rc_type *protocol, *protocol = RC_TYPE_RC6_MCE; dev &= 0x7f; dprintk(1, "ir hauppauge (rc6-mce): t%d vendor=%d dev=%d code=%d\n", - toggle, vendor, dev, code); + *ptoggle, vendor, dev, code); } else { *ptoggle = 0; *protocol = RC_TYPE_RC6_6A_32; diff --git a/drivers/media/tuners/tuner-xc2028.c b/drivers/media/tuners/tuner-xc2028.c index 317ef63ee789..8d96a22647b3 100644 --- a/drivers/media/tuners/tuner-xc2028.c +++ b/drivers/media/tuners/tuner-xc2028.c @@ -281,6 +281,14 @@ static void free_firmware(struct xc2028_data *priv) int i; tuner_dbg("%s called\n", __func__); + /* free allocated f/w string */ + if (priv->fname != firmware_name) + kfree(priv->fname); + priv->fname = NULL; + + priv->state = XC2028_NO_FIRMWARE; + memset(&priv->cur_fw, 0, sizeof(priv->cur_fw)); + if (!priv->firm) return; @@ -291,9 +299,6 @@ static void free_firmware(struct xc2028_data *priv) priv->firm = NULL; priv->firm_size = 0; - priv->state = XC2028_NO_FIRMWARE; - - memset(&priv->cur_fw, 0, sizeof(priv->cur_fw)); } static int load_all_firmwares(struct dvb_frontend *fe, @@ -884,9 +889,8 @@ read_not_reliable: return 0; fail: - priv->state = XC2028_NO_FIRMWARE; + free_firmware(priv); - memset(&priv->cur_fw, 0, sizeof(priv->cur_fw)); if (retry_count < 8) { msleep(50); retry_count++; @@ -1332,11 +1336,8 @@ static int xc2028_dvb_release(struct dvb_frontend *fe) mutex_lock(&xc2028_list_mutex); /* only perform final cleanup if this is the last instance */ - if (hybrid_tuner_report_instance_count(priv) == 1) { + if (hybrid_tuner_report_instance_count(priv) == 1) free_firmware(priv); - kfree(priv->ctrl.fname); - priv->ctrl.fname = NULL; - } if (priv) hybrid_tuner_release_state(priv); @@ -1399,19 +1400,8 @@ static int xc2028_set_config(struct dvb_frontend *fe, void *priv_cfg) /* * Copy the config data. - * For the firmware name, keep a local copy of the string, - * in order to avoid troubles during device release. */ - kfree(priv->ctrl.fname); - priv->ctrl.fname = NULL; memcpy(&priv->ctrl, p, sizeof(priv->ctrl)); - if (p->fname) { - priv->ctrl.fname = kstrdup(p->fname, GFP_KERNEL); - if (priv->ctrl.fname == NULL) { - rc = -ENOMEM; - goto unlock; - } - } /* * If firmware name changed, frees firmware. As free_firmware will @@ -1426,10 +1416,15 @@ static int xc2028_set_config(struct dvb_frontend *fe, void *priv_cfg) if (priv->state == XC2028_NO_FIRMWARE) { if (!firmware_name[0]) - priv->fname = priv->ctrl.fname; + priv->fname = kstrdup(p->fname, GFP_KERNEL); else priv->fname = firmware_name; + if (!priv->fname) { + rc = -ENOMEM; + goto unlock; + } + rc = request_firmware_nowait(THIS_MODULE, 1, priv->fname, priv->i2c_props.adap->dev.parent, diff --git a/drivers/media/usb/dvb-usb/Makefile b/drivers/media/usb/dvb-usb/Makefile index 2a7b5a963acf..3b3f32b426d1 100644 --- a/drivers/media/usb/dvb-usb/Makefile +++ b/drivers/media/usb/dvb-usb/Makefile @@ -8,7 +8,7 @@ obj-$(CONFIG_DVB_USB_VP7045) += dvb-usb-vp7045.o dvb-usb-vp702x-objs := vp702x.o vp702x-fe.o obj-$(CONFIG_DVB_USB_VP702X) += dvb-usb-vp702x.o -dvb-usb-gp8psk-objs := gp8psk.o gp8psk-fe.o +dvb-usb-gp8psk-objs := gp8psk.o obj-$(CONFIG_DVB_USB_GP8PSK) += dvb-usb-gp8psk.o dvb-usb-dtt200u-objs := dtt200u.o dtt200u-fe.o diff --git a/drivers/media/usb/dvb-usb/af9005.c b/drivers/media/usb/dvb-usb/af9005.c index b257780fb380..7853261906b1 100644 --- a/drivers/media/usb/dvb-usb/af9005.c +++ b/drivers/media/usb/dvb-usb/af9005.c @@ -53,7 +53,6 @@ struct af9005_device_state { u8 sequence; int led_state; unsigned char data[256]; - struct mutex data_mutex; }; static int af9005_generic_read_write(struct dvb_usb_device *d, u16 reg, @@ -72,7 +71,7 @@ static int af9005_generic_read_write(struct dvb_usb_device *d, u16 reg, return -EINVAL; } - mutex_lock(&st->data_mutex); + mutex_lock(&d->data_mutex); st->data[0] = 14; /* rest of buffer length low */ st->data[1] = 0; /* rest of buffer length high */ @@ -140,7 +139,7 @@ static int af9005_generic_read_write(struct dvb_usb_device *d, u16 reg, values[i] = st->data[8 + i]; ret: - mutex_unlock(&st->data_mutex); + mutex_unlock(&d->data_mutex); return ret; } @@ -481,7 +480,7 @@ int af9005_send_command(struct dvb_usb_device *d, u8 command, u8 * wbuf, } packet_len = wlen + 5; - mutex_lock(&st->data_mutex); + mutex_lock(&d->data_mutex); st->data[0] = (u8) (packet_len & 0xff); st->data[1] = (u8) ((packet_len & 0xff00) >> 8); @@ -512,7 +511,7 @@ int af9005_send_command(struct dvb_usb_device *d, u8 command, u8 * wbuf, rbuf[i] = st->data[i + 7]; } - mutex_unlock(&st->data_mutex); + mutex_unlock(&d->data_mutex); return ret; } @@ -523,7 +522,7 @@ int af9005_read_eeprom(struct dvb_usb_device *d, u8 address, u8 * values, u8 seq; int ret, i; - mutex_lock(&st->data_mutex); + mutex_lock(&d->data_mutex); memset(st->data, 0, sizeof(st->data)); @@ -559,7 +558,7 @@ int af9005_read_eeprom(struct dvb_usb_device *d, u8 address, u8 * values, for (i = 0; i < len; i++) values[i] = st->data[6 + i]; } - mutex_unlock(&st->data_mutex); + mutex_unlock(&d->data_mutex); return ret; } @@ -847,7 +846,7 @@ static int af9005_rc_query(struct dvb_usb_device *d, u32 * event, int *state) return 0; } - mutex_lock(&st->data_mutex); + mutex_lock(&d->data_mutex); /* deb_info("rc_query\n"); */ st->data[0] = 3; /* rest of packet length low */ @@ -890,7 +889,7 @@ static int af9005_rc_query(struct dvb_usb_device *d, u32 * event, int *state) } ret: - mutex_unlock(&st->data_mutex); + mutex_unlock(&d->data_mutex); return ret; } @@ -1004,20 +1003,8 @@ static struct dvb_usb_device_properties af9005_properties; static int af9005_usb_probe(struct usb_interface *intf, const struct usb_device_id *id) { - struct dvb_usb_device *d; - struct af9005_device_state *st; - int ret; - - ret = dvb_usb_device_init(intf, &af9005_properties, - THIS_MODULE, &d, adapter_nr); - - if (ret < 0) - return ret; - - st = d->priv; - mutex_init(&st->data_mutex); - - return 0; + return dvb_usb_device_init(intf, &af9005_properties, + THIS_MODULE, NULL, adapter_nr); } enum af9005_usb_table_entry { diff --git a/drivers/media/usb/dvb-usb/cinergyT2-core.c b/drivers/media/usb/dvb-usb/cinergyT2-core.c index 8ac825413d5a..290275bc7fde 100644 --- a/drivers/media/usb/dvb-usb/cinergyT2-core.c +++ b/drivers/media/usb/dvb-usb/cinergyT2-core.c @@ -42,7 +42,6 @@ DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); struct cinergyt2_state { u8 rc_counter; unsigned char data[64]; - struct mutex data_mutex; }; /* We are missing a release hook with usb_device data */ @@ -56,12 +55,12 @@ static int cinergyt2_streaming_ctrl(struct dvb_usb_adapter *adap, int enable) struct cinergyt2_state *st = d->priv; int ret; - mutex_lock(&st->data_mutex); + mutex_lock(&d->data_mutex); st->data[0] = CINERGYT2_EP1_CONTROL_STREAM_TRANSFER; st->data[1] = enable ? 1 : 0; ret = dvb_usb_generic_rw(d, st->data, 2, st->data, 64, 0); - mutex_unlock(&st->data_mutex); + mutex_unlock(&d->data_mutex); return ret; } @@ -71,12 +70,12 @@ static int cinergyt2_power_ctrl(struct dvb_usb_device *d, int enable) struct cinergyt2_state *st = d->priv; int ret; - mutex_lock(&st->data_mutex); + mutex_lock(&d->data_mutex); st->data[0] = CINERGYT2_EP1_SLEEP_MODE; st->data[1] = enable ? 0 : 1; ret = dvb_usb_generic_rw(d, st->data, 2, st->data, 3, 0); - mutex_unlock(&st->data_mutex); + mutex_unlock(&d->data_mutex); return ret; } @@ -89,7 +88,7 @@ static int cinergyt2_frontend_attach(struct dvb_usb_adapter *adap) adap->fe_adap[0].fe = cinergyt2_fe_attach(adap->dev); - mutex_lock(&st->data_mutex); + mutex_lock(&d->data_mutex); st->data[0] = CINERGYT2_EP1_GET_FIRMWARE_VERSION; ret = dvb_usb_generic_rw(d, st->data, 1, st->data, 3, 0); @@ -97,7 +96,7 @@ static int cinergyt2_frontend_attach(struct dvb_usb_adapter *adap) deb_rc("cinergyt2_power_ctrl() Failed to retrieve sleep " "state info\n"); } - mutex_unlock(&st->data_mutex); + mutex_unlock(&d->data_mutex); /* Copy this pointer as we are gonna need it in the release phase */ cinergyt2_usb_device = adap->dev; @@ -166,7 +165,7 @@ static int cinergyt2_rc_query(struct dvb_usb_device *d, u32 *event, int *state) *state = REMOTE_NO_KEY_PRESSED; - mutex_lock(&st->data_mutex); + mutex_lock(&d->data_mutex); st->data[0] = CINERGYT2_EP1_GET_RC_EVENTS; ret = dvb_usb_generic_rw(d, st->data, 1, st->data, 5, 0); @@ -202,29 +201,17 @@ static int cinergyt2_rc_query(struct dvb_usb_device *d, u32 *event, int *state) } ret: - mutex_unlock(&st->data_mutex); + mutex_unlock(&d->data_mutex); return ret; } static int cinergyt2_usb_probe(struct usb_interface *intf, const struct usb_device_id *id) { - struct dvb_usb_device *d; - struct cinergyt2_state *st; - int ret; - - ret = dvb_usb_device_init(intf, &cinergyt2_properties, - THIS_MODULE, &d, adapter_nr); - if (ret < 0) - return ret; - - st = d->priv; - mutex_init(&st->data_mutex); - - return 0; + return dvb_usb_device_init(intf, &cinergyt2_properties, + THIS_MODULE, NULL, adapter_nr); } - static struct usb_device_id cinergyt2_usb_table[] = { { USB_DEVICE(USB_VID_TERRATEC, 0x0038) }, { 0 } diff --git a/drivers/media/usb/dvb-usb/cxusb.c b/drivers/media/usb/dvb-usb/cxusb.c index 39772812269d..243403081fa5 100644 --- a/drivers/media/usb/dvb-usb/cxusb.c +++ b/drivers/media/usb/dvb-usb/cxusb.c @@ -68,7 +68,7 @@ static int cxusb_ctrl_msg(struct dvb_usb_device *d, wo = (rbuf == NULL || rlen == 0); /* write-only */ - mutex_lock(&st->data_mutex); + mutex_lock(&d->data_mutex); st->data[0] = cmd; memcpy(&st->data[1], wbuf, wlen); if (wo) @@ -77,7 +77,7 @@ static int cxusb_ctrl_msg(struct dvb_usb_device *d, ret = dvb_usb_generic_rw(d, st->data, 1 + wlen, rbuf, rlen, 0); - mutex_unlock(&st->data_mutex); + mutex_unlock(&d->data_mutex); return ret; } @@ -1461,43 +1461,36 @@ static struct dvb_usb_device_properties cxusb_mygica_t230_properties; static int cxusb_probe(struct usb_interface *intf, const struct usb_device_id *id) { - struct dvb_usb_device *d; - struct cxusb_state *st; - if (0 == dvb_usb_device_init(intf, &cxusb_medion_properties, - THIS_MODULE, &d, adapter_nr) || + THIS_MODULE, NULL, adapter_nr) || 0 == dvb_usb_device_init(intf, &cxusb_bluebird_lgh064f_properties, - THIS_MODULE, &d, adapter_nr) || + THIS_MODULE, NULL, adapter_nr) || 0 == dvb_usb_device_init(intf, &cxusb_bluebird_dee1601_properties, - THIS_MODULE, &d, adapter_nr) || + THIS_MODULE, NULL, adapter_nr) || 0 == dvb_usb_device_init(intf, &cxusb_bluebird_lgz201_properties, - THIS_MODULE, &d, adapter_nr) || + THIS_MODULE, NULL, adapter_nr) || 0 == dvb_usb_device_init(intf, &cxusb_bluebird_dtt7579_properties, - THIS_MODULE, &d, adapter_nr) || + THIS_MODULE, NULL, adapter_nr) || 0 == dvb_usb_device_init(intf, &cxusb_bluebird_dualdig4_properties, - THIS_MODULE, &d, adapter_nr) || + THIS_MODULE, NULL, adapter_nr) || 0 == dvb_usb_device_init(intf, &cxusb_bluebird_nano2_properties, - THIS_MODULE, &d, adapter_nr) || + THIS_MODULE, NULL, adapter_nr) || 0 == dvb_usb_device_init(intf, &cxusb_bluebird_nano2_needsfirmware_properties, - THIS_MODULE, &d, adapter_nr) || + THIS_MODULE, NULL, adapter_nr) || 0 == dvb_usb_device_init(intf, &cxusb_aver_a868r_properties, - THIS_MODULE, &d, adapter_nr) || + THIS_MODULE, NULL, adapter_nr) || 0 == dvb_usb_device_init(intf, &cxusb_bluebird_dualdig4_rev2_properties, - THIS_MODULE, &d, adapter_nr) || + THIS_MODULE, NULL, adapter_nr) || 0 == dvb_usb_device_init(intf, &cxusb_d680_dmb_properties, - THIS_MODULE, &d, adapter_nr) || + THIS_MODULE, NULL, adapter_nr) || 0 == dvb_usb_device_init(intf, &cxusb_mygica_d689_properties, - THIS_MODULE, &d, adapter_nr) || + THIS_MODULE, NULL, adapter_nr) || 0 == dvb_usb_device_init(intf, &cxusb_mygica_t230_properties, - THIS_MODULE, &d, adapter_nr) || - 0) { - st = d->priv; - mutex_init(&st->data_mutex); - + THIS_MODULE, NULL, adapter_nr) || + 0) return 0; - } return -EINVAL; } diff --git a/drivers/media/usb/dvb-usb/cxusb.h b/drivers/media/usb/dvb-usb/cxusb.h index 9f3ee0e47d5c..18acda19527a 100644 --- a/drivers/media/usb/dvb-usb/cxusb.h +++ b/drivers/media/usb/dvb-usb/cxusb.h @@ -37,7 +37,6 @@ struct cxusb_state { struct i2c_client *i2c_client_tuner; unsigned char data[MAX_XFER_SIZE]; - struct mutex data_mutex; }; #endif diff --git a/drivers/media/usb/dvb-usb/dib0700_core.c b/drivers/media/usb/dvb-usb/dib0700_core.c index 92d5408684ac..47ce9d5de4c6 100644 --- a/drivers/media/usb/dvb-usb/dib0700_core.c +++ b/drivers/media/usb/dvb-usb/dib0700_core.c @@ -704,7 +704,7 @@ static void dib0700_rc_urb_completion(struct urb *purb) struct dvb_usb_device *d = purb->context; struct dib0700_rc_response *poll_reply; enum rc_type protocol; - u32 uninitialized_var(keycode); + u32 keycode; u8 toggle; deb_info("%s()\n", __func__); @@ -745,7 +745,8 @@ static void dib0700_rc_urb_completion(struct urb *purb) poll_reply->nec.data == 0x00 && poll_reply->nec.not_data == 0xff) { poll_reply->data_state = 2; - break; + rc_repeat(d->rc_dev); + goto resubmit; } if ((poll_reply->nec.data ^ poll_reply->nec.not_data) != 0xff) { diff --git a/drivers/media/usb/dvb-usb/dtt200u.c b/drivers/media/usb/dvb-usb/dtt200u.c index f88572c7ae7c..fcbff7fb0c4e 100644 --- a/drivers/media/usb/dvb-usb/dtt200u.c +++ b/drivers/media/usb/dvb-usb/dtt200u.c @@ -22,7 +22,6 @@ DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); struct dtt200u_state { unsigned char data[80]; - struct mutex data_mutex; }; static int dtt200u_power_ctrl(struct dvb_usb_device *d, int onoff) @@ -30,23 +29,24 @@ static int dtt200u_power_ctrl(struct dvb_usb_device *d, int onoff) struct dtt200u_state *st = d->priv; int ret = 0; - mutex_lock(&st->data_mutex); + mutex_lock(&d->data_mutex); st->data[0] = SET_INIT; if (onoff) ret = dvb_usb_generic_write(d, st->data, 2); - mutex_unlock(&st->data_mutex); + mutex_unlock(&d->data_mutex); return ret; } static int dtt200u_streaming_ctrl(struct dvb_usb_adapter *adap, int onoff) { - struct dtt200u_state *st = adap->dev->priv; + struct dvb_usb_device *d = adap->dev; + struct dtt200u_state *st = d->priv; int ret; - mutex_lock(&st->data_mutex); + mutex_lock(&d->data_mutex); st->data[0] = SET_STREAMING; st->data[1] = onoff; @@ -61,26 +61,27 @@ static int dtt200u_streaming_ctrl(struct dvb_usb_adapter *adap, int onoff) ret = dvb_usb_generic_write(adap->dev, st->data, 1); ret: - mutex_unlock(&st->data_mutex); + mutex_unlock(&d->data_mutex); return ret; } static int dtt200u_pid_filter(struct dvb_usb_adapter *adap, int index, u16 pid, int onoff) { - struct dtt200u_state *st = adap->dev->priv; + struct dvb_usb_device *d = adap->dev; + struct dtt200u_state *st = d->priv; int ret; pid = onoff ? pid : 0; - mutex_lock(&st->data_mutex); + mutex_lock(&d->data_mutex); st->data[0] = SET_PID_FILTER; st->data[1] = index; st->data[2] = pid & 0xff; st->data[3] = (pid >> 8) & 0x1f; ret = dvb_usb_generic_write(adap->dev, st->data, 4); - mutex_unlock(&st->data_mutex); + mutex_unlock(&d->data_mutex); return ret; } @@ -91,7 +92,7 @@ static int dtt200u_rc_query(struct dvb_usb_device *d) u32 scancode; int ret; - mutex_lock(&st->data_mutex); + mutex_lock(&d->data_mutex); st->data[0] = GET_RC_CODE; ret = dvb_usb_generic_rw(d, st->data, 1, st->data, 5, 0); @@ -126,7 +127,7 @@ static int dtt200u_rc_query(struct dvb_usb_device *d) deb_info("st->data: %*ph\n", 5, st->data); ret: - mutex_unlock(&st->data_mutex); + mutex_unlock(&d->data_mutex); return ret; } @@ -145,24 +146,17 @@ static struct dvb_usb_device_properties wt220u_miglia_properties; static int dtt200u_usb_probe(struct usb_interface *intf, const struct usb_device_id *id) { - struct dvb_usb_device *d; - struct dtt200u_state *st; - if (0 == dvb_usb_device_init(intf, &dtt200u_properties, - THIS_MODULE, &d, adapter_nr) || + THIS_MODULE, NULL, adapter_nr) || 0 == dvb_usb_device_init(intf, &wt220u_properties, - THIS_MODULE, &d, adapter_nr) || + THIS_MODULE, NULL, adapter_nr) || 0 == dvb_usb_device_init(intf, &wt220u_fc_properties, - THIS_MODULE, &d, adapter_nr) || + THIS_MODULE, NULL, adapter_nr) || 0 == dvb_usb_device_init(intf, &wt220u_zl0353_properties, - THIS_MODULE, &d, adapter_nr) || + THIS_MODULE, NULL, adapter_nr) || 0 == dvb_usb_device_init(intf, &wt220u_miglia_properties, - THIS_MODULE, &d, adapter_nr)) { - st = d->priv; - mutex_init(&st->data_mutex); - + THIS_MODULE, NULL, adapter_nr)) return 0; - } return -ENODEV; } diff --git a/drivers/media/usb/dvb-usb/dvb-usb-init.c b/drivers/media/usb/dvb-usb/dvb-usb-init.c index 3896ba9a4179..84308569e7dc 100644 --- a/drivers/media/usb/dvb-usb/dvb-usb-init.c +++ b/drivers/media/usb/dvb-usb/dvb-usb-init.c @@ -142,6 +142,7 @@ static int dvb_usb_init(struct dvb_usb_device *d, short *adapter_nums) { int ret = 0; + mutex_init(&d->data_mutex); mutex_init(&d->usb_mutex); mutex_init(&d->i2c_mutex); diff --git a/drivers/media/usb/dvb-usb/dvb-usb.h b/drivers/media/usb/dvb-usb/dvb-usb.h index 639c4678c65b..107255b08b2b 100644 --- a/drivers/media/usb/dvb-usb/dvb-usb.h +++ b/drivers/media/usb/dvb-usb/dvb-usb.h @@ -404,8 +404,12 @@ struct dvb_usb_adapter { * Powered is in/decremented for each call to modify the state. * @udev: pointer to the device's struct usb_device. * - * @usb_mutex: semaphore of USB control messages (reading needs two messages) - * @i2c_mutex: semaphore for i2c-transfers + * @data_mutex: mutex to protect the data structure used to store URB data + * @usb_mutex: mutex of USB control messages (reading needs two messages). + * Please notice that this mutex is used internally at the generic + * URB control functions. So, drivers using dvb_usb_generic_rw() and + * derivated functions should not lock it internally. + * @i2c_mutex: mutex for i2c-transfers * * @i2c_adap: device's i2c_adapter if it uses I2CoverUSB * @@ -433,6 +437,7 @@ struct dvb_usb_device { int powered; /* locking */ + struct mutex data_mutex; struct mutex usb_mutex; /* i2c */ diff --git a/drivers/media/usb/dvb-usb/gp8psk.c b/drivers/media/usb/dvb-usb/gp8psk.c index adfd76491451..993bb7a72985 100644 --- a/drivers/media/usb/dvb-usb/gp8psk.c +++ b/drivers/media/usb/dvb-usb/gp8psk.c @@ -15,6 +15,7 @@ * see Documentation/dvb/README.dvb-usb for more information */ #include "gp8psk.h" +#include "gp8psk-fe.h" /* debug */ static char bcm4500_firmware[] = "dvb-usb-gp8psk-02.fw"; @@ -28,34 +29,8 @@ struct gp8psk_state { unsigned char data[80]; }; -static int gp8psk_get_fw_version(struct dvb_usb_device *d, u8 *fw_vers) -{ - return (gp8psk_usb_in_op(d, GET_FW_VERS, 0, 0, fw_vers, 6)); -} - -static int gp8psk_get_fpga_version(struct dvb_usb_device *d, u8 *fpga_vers) -{ - return (gp8psk_usb_in_op(d, GET_FPGA_VERS, 0, 0, fpga_vers, 1)); -} - -static void gp8psk_info(struct dvb_usb_device *d) -{ - u8 fpga_vers, fw_vers[6]; - - if (!gp8psk_get_fw_version(d, fw_vers)) - info("FW Version = %i.%02i.%i (0x%x) Build %4i/%02i/%02i", - fw_vers[2], fw_vers[1], fw_vers[0], GP8PSK_FW_VERS(fw_vers), - 2000 + fw_vers[5], fw_vers[4], fw_vers[3]); - else - info("failed to get FW version"); - - if (!gp8psk_get_fpga_version(d, &fpga_vers)) - info("FPGA Version = %i", fpga_vers); - else - info("failed to get FPGA version"); -} - -int gp8psk_usb_in_op(struct dvb_usb_device *d, u8 req, u16 value, u16 index, u8 *b, int blen) +static int gp8psk_usb_in_op(struct dvb_usb_device *d, u8 req, u16 value, + u16 index, u8 *b, int blen) { struct gp8psk_state *st = d->priv; int ret = 0,try = 0; @@ -67,7 +42,6 @@ int gp8psk_usb_in_op(struct dvb_usb_device *d, u8 req, u16 value, u16 index, u8 return ret; while (ret >= 0 && ret != blen && try < 3) { - memcpy(st->data, b, blen); ret = usb_control_msg(d->udev, usb_rcvctrlpipe(d->udev,0), req, @@ -81,8 +55,10 @@ int gp8psk_usb_in_op(struct dvb_usb_device *d, u8 req, u16 value, u16 index, u8 if (ret < 0 || ret != blen) { warn("usb in %d operation failed.", req); ret = -EIO; - } else + } else { ret = 0; + memcpy(b, st->data, blen); + } deb_xfer("in: req. %x, val: %x, ind: %x, buffer: ",req,value,index); debug_dump(b,blen,deb_xfer); @@ -92,7 +68,7 @@ int gp8psk_usb_in_op(struct dvb_usb_device *d, u8 req, u16 value, u16 index, u8 return ret; } -int gp8psk_usb_out_op(struct dvb_usb_device *d, u8 req, u16 value, +static int gp8psk_usb_out_op(struct dvb_usb_device *d, u8 req, u16 value, u16 index, u8 *b, int blen) { struct gp8psk_state *st = d->priv; @@ -123,6 +99,34 @@ int gp8psk_usb_out_op(struct dvb_usb_device *d, u8 req, u16 value, return ret; } + +static int gp8psk_get_fw_version(struct dvb_usb_device *d, u8 *fw_vers) +{ + return gp8psk_usb_in_op(d, GET_FW_VERS, 0, 0, fw_vers, 6); +} + +static int gp8psk_get_fpga_version(struct dvb_usb_device *d, u8 *fpga_vers) +{ + return gp8psk_usb_in_op(d, GET_FPGA_VERS, 0, 0, fpga_vers, 1); +} + +static void gp8psk_info(struct dvb_usb_device *d) +{ + u8 fpga_vers, fw_vers[6]; + + if (!gp8psk_get_fw_version(d, fw_vers)) + info("FW Version = %i.%02i.%i (0x%x) Build %4i/%02i/%02i", + fw_vers[2], fw_vers[1], fw_vers[0], GP8PSK_FW_VERS(fw_vers), + 2000 + fw_vers[5], fw_vers[4], fw_vers[3]); + else + info("failed to get FW version"); + + if (!gp8psk_get_fpga_version(d, &fpga_vers)) + info("FPGA Version = %i", fpga_vers); + else + info("failed to get FPGA version"); +} + static int gp8psk_load_bcm4500fw(struct dvb_usb_device *d) { int ret; @@ -225,10 +229,13 @@ static int gp8psk_power_ctrl(struct dvb_usb_device *d, int onoff) return 0; } -int gp8psk_bcm4500_reload(struct dvb_usb_device *d) +static int gp8psk_bcm4500_reload(struct dvb_usb_device *d) { u8 buf; int gp_product_id = le16_to_cpu(d->udev->descriptor.idProduct); + + deb_xfer("reloading firmware\n"); + /* Turn off 8psk power */ if (gp8psk_usb_in_op(d, BOOT_8PSK, 0, 0, &buf, 1)) return -EINVAL; @@ -247,9 +254,47 @@ static int gp8psk_streaming_ctrl(struct dvb_usb_adapter *adap, int onoff) return gp8psk_usb_out_op(adap->dev, ARM_TRANSFER, onoff, 0 , NULL, 0); } +/* Callbacks for gp8psk-fe.c */ + +static int gp8psk_fe_in(void *priv, u8 req, u16 value, + u16 index, u8 *b, int blen) +{ + struct dvb_usb_device *d = priv; + + return gp8psk_usb_in_op(d, req, value, index, b, blen); +} + +static int gp8psk_fe_out(void *priv, u8 req, u16 value, + u16 index, u8 *b, int blen) +{ + struct dvb_usb_device *d = priv; + + return gp8psk_usb_out_op(d, req, value, index, b, blen); +} + +static int gp8psk_fe_reload(void *priv) +{ + struct dvb_usb_device *d = priv; + + return gp8psk_bcm4500_reload(d); +} + +const struct gp8psk_fe_ops gp8psk_fe_ops = { + .in = gp8psk_fe_in, + .out = gp8psk_fe_out, + .reload = gp8psk_fe_reload, +}; + static int gp8psk_frontend_attach(struct dvb_usb_adapter *adap) { - adap->fe_adap[0].fe = gp8psk_fe_attach(adap->dev); + struct dvb_usb_device *d = adap->dev; + int id = le16_to_cpu(d->udev->descriptor.idProduct); + int is_rev1; + + is_rev1 = (id == USB_PID_GENPIX_8PSK_REV_1_WARM) ? true : false; + + adap->fe_adap[0].fe = dvb_attach(gp8psk_fe_attach, + &gp8psk_fe_ops, d, is_rev1); return 0; } diff --git a/drivers/media/usb/dvb-usb/gp8psk.h b/drivers/media/usb/dvb-usb/gp8psk.h index ed32b9da4843..d8975b866dee 100644 --- a/drivers/media/usb/dvb-usb/gp8psk.h +++ b/drivers/media/usb/dvb-usb/gp8psk.h @@ -24,58 +24,6 @@ extern int dvb_usb_gp8psk_debug; #define deb_info(args...) dprintk(dvb_usb_gp8psk_debug,0x01,args) #define deb_xfer(args...) dprintk(dvb_usb_gp8psk_debug,0x02,args) #define deb_rc(args...) dprintk(dvb_usb_gp8psk_debug,0x04,args) -#define deb_fe(args...) dprintk(dvb_usb_gp8psk_debug,0x08,args) - -/* Twinhan Vendor requests */ -#define TH_COMMAND_IN 0xC0 -#define TH_COMMAND_OUT 0xC1 - -/* gp8psk commands */ - -#define GET_8PSK_CONFIG 0x80 /* in */ -#define SET_8PSK_CONFIG 0x81 -#define I2C_WRITE 0x83 -#define I2C_READ 0x84 -#define ARM_TRANSFER 0x85 -#define TUNE_8PSK 0x86 -#define GET_SIGNAL_STRENGTH 0x87 /* in */ -#define LOAD_BCM4500 0x88 -#define BOOT_8PSK 0x89 /* in */ -#define START_INTERSIL 0x8A /* in */ -#define SET_LNB_VOLTAGE 0x8B -#define SET_22KHZ_TONE 0x8C -#define SEND_DISEQC_COMMAND 0x8D -#define SET_DVB_MODE 0x8E -#define SET_DN_SWITCH 0x8F -#define GET_SIGNAL_LOCK 0x90 /* in */ -#define GET_FW_VERS 0x92 -#define GET_SERIAL_NUMBER 0x93 /* in */ -#define USE_EXTRA_VOLT 0x94 -#define GET_FPGA_VERS 0x95 -#define CW3K_INIT 0x9d - -/* PSK_configuration bits */ -#define bm8pskStarted 0x01 -#define bm8pskFW_Loaded 0x02 -#define bmIntersilOn 0x04 -#define bmDVBmode 0x08 -#define bm22kHz 0x10 -#define bmSEL18V 0x20 -#define bmDCtuned 0x40 -#define bmArmed 0x80 - -/* Satellite modulation modes */ -#define ADV_MOD_DVB_QPSK 0 /* DVB-S QPSK */ -#define ADV_MOD_TURBO_QPSK 1 /* Turbo QPSK */ -#define ADV_MOD_TURBO_8PSK 2 /* Turbo 8PSK (also used for Trellis 8PSK) */ -#define ADV_MOD_TURBO_16QAM 3 /* Turbo 16QAM (also used for Trellis 8PSK) */ - -#define ADV_MOD_DCII_C_QPSK 4 /* Digicipher II Combo */ -#define ADV_MOD_DCII_I_QPSK 5 /* Digicipher II I-stream */ -#define ADV_MOD_DCII_Q_QPSK 6 /* Digicipher II Q-stream */ -#define ADV_MOD_DCII_C_OQPSK 7 /* Digicipher II offset QPSK */ -#define ADV_MOD_DSS_QPSK 8 /* DSS (DIRECTV) QPSK */ -#define ADV_MOD_DVB_BPSK 9 /* DVB-S BPSK */ #define GET_USB_SPEED 0x07 @@ -86,15 +34,4 @@ extern int dvb_usb_gp8psk_debug; #define PRODUCT_STRING_READ 0x0D #define FW_BCD_VERSION_READ 0x14 -/* firmware revision id's */ -#define GP8PSK_FW_REV1 0x020604 -#define GP8PSK_FW_REV2 0x020704 -#define GP8PSK_FW_VERS(_fw_vers) ((_fw_vers)[2]<<0x10 | (_fw_vers)[1]<<0x08 | (_fw_vers)[0]) - -extern struct dvb_frontend * gp8psk_fe_attach(struct dvb_usb_device *d); -extern int gp8psk_usb_in_op(struct dvb_usb_device *d, u8 req, u16 value, u16 index, u8 *b, int blen); -extern int gp8psk_usb_out_op(struct dvb_usb_device *d, u8 req, u16 value, - u16 index, u8 *b, int blen); -extern int gp8psk_bcm4500_reload(struct dvb_usb_device *d); - #endif diff --git a/drivers/mfd/intel-lpss-pci.c b/drivers/mfd/intel-lpss-pci.c index 3228fd182a99..9ff243970e93 100644 --- a/drivers/mfd/intel-lpss-pci.c +++ b/drivers/mfd/intel-lpss-pci.c @@ -123,19 +123,6 @@ static const struct intel_lpss_platform_info apl_i2c_info = { .properties = apl_i2c_properties, }; -static const struct intel_lpss_platform_info kbl_info = { - .clk_rate = 120000000, -}; - -static const struct intel_lpss_platform_info kbl_uart_info = { - .clk_rate = 120000000, - .clk_con_id = "baudclk", -}; - -static const struct intel_lpss_platform_info kbl_i2c_info = { - .clk_rate = 133000000, -}; - static const struct pci_device_id intel_lpss_pci_ids[] = { /* BXT A-Step */ { PCI_VDEVICE(INTEL, 0x0aac), (kernel_ulong_t)&bxt_i2c_info }, @@ -207,15 +194,15 @@ static const struct pci_device_id intel_lpss_pci_ids[] = { { PCI_VDEVICE(INTEL, 0xa161), (kernel_ulong_t)&spt_i2c_info }, { PCI_VDEVICE(INTEL, 0xa166), (kernel_ulong_t)&spt_uart_info }, /* KBL-H */ - { PCI_VDEVICE(INTEL, 0xa2a7), (kernel_ulong_t)&kbl_uart_info }, - { PCI_VDEVICE(INTEL, 0xa2a8), (kernel_ulong_t)&kbl_uart_info }, - { PCI_VDEVICE(INTEL, 0xa2a9), (kernel_ulong_t)&kbl_info }, - { PCI_VDEVICE(INTEL, 0xa2aa), (kernel_ulong_t)&kbl_info }, - { PCI_VDEVICE(INTEL, 0xa2e0), (kernel_ulong_t)&kbl_i2c_info }, - { PCI_VDEVICE(INTEL, 0xa2e1), (kernel_ulong_t)&kbl_i2c_info }, - { PCI_VDEVICE(INTEL, 0xa2e2), (kernel_ulong_t)&kbl_i2c_info }, - { PCI_VDEVICE(INTEL, 0xa2e3), (kernel_ulong_t)&kbl_i2c_info }, - { PCI_VDEVICE(INTEL, 0xa2e6), (kernel_ulong_t)&kbl_uart_info }, + { PCI_VDEVICE(INTEL, 0xa2a7), (kernel_ulong_t)&spt_uart_info }, + { PCI_VDEVICE(INTEL, 0xa2a8), (kernel_ulong_t)&spt_uart_info }, + { PCI_VDEVICE(INTEL, 0xa2a9), (kernel_ulong_t)&spt_info }, + { PCI_VDEVICE(INTEL, 0xa2aa), (kernel_ulong_t)&spt_info }, + { PCI_VDEVICE(INTEL, 0xa2e0), (kernel_ulong_t)&spt_i2c_info }, + { PCI_VDEVICE(INTEL, 0xa2e1), (kernel_ulong_t)&spt_i2c_info }, + { PCI_VDEVICE(INTEL, 0xa2e2), (kernel_ulong_t)&spt_i2c_info }, + { PCI_VDEVICE(INTEL, 0xa2e3), (kernel_ulong_t)&spt_i2c_info }, + { PCI_VDEVICE(INTEL, 0xa2e6), (kernel_ulong_t)&spt_uart_info }, { } }; MODULE_DEVICE_TABLE(pci, intel_lpss_pci_ids); diff --git a/drivers/mfd/intel-lpss.c b/drivers/mfd/intel-lpss.c index 41b113875d64..70c646b0097d 100644 --- a/drivers/mfd/intel-lpss.c +++ b/drivers/mfd/intel-lpss.c @@ -502,9 +502,6 @@ int intel_lpss_suspend(struct device *dev) for (i = 0; i < LPSS_PRIV_REG_COUNT; i++) lpss->priv_ctx[i] = readl(lpss->priv + i * 4); - /* Put the device into reset state */ - writel(0, lpss->priv + LPSS_PRIV_RESETS); - return 0; } EXPORT_SYMBOL_GPL(intel_lpss_suspend); diff --git a/drivers/mfd/intel_soc_pmic_bxtwc.c b/drivers/mfd/intel_soc_pmic_bxtwc.c index 43e54b7e908f..f9a8c5203873 100644 --- a/drivers/mfd/intel_soc_pmic_bxtwc.c +++ b/drivers/mfd/intel_soc_pmic_bxtwc.c @@ -86,6 +86,7 @@ enum bxtwc_irqs_level2 { BXTWC_THRM2_IRQ, BXTWC_BCU_IRQ, BXTWC_ADC_IRQ, + BXTWC_USBC_IRQ, BXTWC_CHGR0_IRQ, BXTWC_CHGR1_IRQ, BXTWC_GPIO0_IRQ, @@ -111,7 +112,8 @@ static const struct regmap_irq bxtwc_regmap_irqs_level2[] = { REGMAP_IRQ_REG(BXTWC_THRM2_IRQ, 2, 0xff), REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 3, 0x1f), REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 4, 0xff), - REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 5, 0x3f), + REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 5, BIT(5)), + REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 5, 0x1f), REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 6, 0x1f), REGMAP_IRQ_REG(BXTWC_GPIO0_IRQ, 7, 0xff), REGMAP_IRQ_REG(BXTWC_GPIO1_IRQ, 8, 0x3f), @@ -146,7 +148,7 @@ static struct resource adc_resources[] = { }; static struct resource usbc_resources[] = { - DEFINE_RES_IRQ_NAMED(BXTWC_CHGR0_IRQ, "USBC"), + DEFINE_RES_IRQ(BXTWC_USBC_IRQ), }; static struct resource charger_resources[] = { diff --git a/drivers/mfd/mfd-core.c b/drivers/mfd/mfd-core.c index 3ac486a597f3..c57e407020f1 100644 --- a/drivers/mfd/mfd-core.c +++ b/drivers/mfd/mfd-core.c @@ -399,6 +399,8 @@ int mfd_clone_cell(const char *cell, const char **clones, size_t n_clones) clones[i]); } + put_device(dev); + return 0; } EXPORT_SYMBOL(mfd_clone_cell); diff --git a/drivers/mfd/stmpe.c b/drivers/mfd/stmpe.c index cfdae8a3d779..b0c7bcdaf5df 100644 --- a/drivers/mfd/stmpe.c +++ b/drivers/mfd/stmpe.c @@ -851,6 +851,8 @@ static int stmpe_reset(struct stmpe *stmpe) if (ret < 0) return ret; + msleep(10); + timeout = jiffies + msecs_to_jiffies(100); while (time_before(jiffies, timeout)) { ret = __stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL]); diff --git a/drivers/mfd/syscon.c b/drivers/mfd/syscon.c index 2f2225e845ef..b93fe4c4957a 100644 --- a/drivers/mfd/syscon.c +++ b/drivers/mfd/syscon.c @@ -73,8 +73,10 @@ static struct syscon *of_syscon_register(struct device_node *np) /* Parse the device's DT node for an endianness specification */ if (of_property_read_bool(np, "big-endian")) syscon_config.val_format_endian = REGMAP_ENDIAN_BIG; - else if (of_property_read_bool(np, "little-endian")) + else if (of_property_read_bool(np, "little-endian")) syscon_config.val_format_endian = REGMAP_ENDIAN_LITTLE; + else if (of_property_read_bool(np, "native-endian")) + syscon_config.val_format_endian = REGMAP_ENDIAN_NATIVE; /* * search for reg-io-width property in DT. If it is not provided, diff --git a/drivers/mfd/wm8994-core.c b/drivers/mfd/wm8994-core.c index 7eec619a6023..8588dbad3301 100644 --- a/drivers/mfd/wm8994-core.c +++ b/drivers/mfd/wm8994-core.c @@ -393,8 +393,13 @@ static int wm8994_device_init(struct wm8994 *wm8994, int irq) BUG(); goto err; } - - ret = devm_regulator_bulk_get(wm8994->dev, wm8994->num_supplies, + + /* + * Can't use devres helper here as some of the supplies are provided by + * wm8994->dev's children (regulators) and those regulators are + * unregistered by the devres core before the supplies are freed. + */ + ret = regulator_bulk_get(wm8994->dev, wm8994->num_supplies, wm8994->supplies); if (ret != 0) { dev_err(wm8994->dev, "Failed to get supplies: %d\n", ret); @@ -405,7 +410,7 @@ static int wm8994_device_init(struct wm8994 *wm8994, int irq) wm8994->supplies); if (ret != 0) { dev_err(wm8994->dev, "Failed to enable supplies: %d\n", ret); - goto err; + goto err_regulator_free; } ret = wm8994_reg_read(wm8994, WM8994_SOFTWARE_RESET); @@ -596,6 +601,8 @@ err_irq: err_enable: regulator_bulk_disable(wm8994->num_supplies, wm8994->supplies); +err_regulator_free: + regulator_bulk_free(wm8994->num_supplies, wm8994->supplies); err: mfd_remove_devices(wm8994->dev); return ret; @@ -604,10 +611,11 @@ err: static void wm8994_device_exit(struct wm8994 *wm8994) { pm_runtime_disable(wm8994->dev); - mfd_remove_devices(wm8994->dev); wm8994_irq_exit(wm8994); regulator_bulk_disable(wm8994->num_supplies, wm8994->supplies); + regulator_bulk_free(wm8994->num_supplies, wm8994->supplies); + mfd_remove_devices(wm8994->dev); } static const struct of_device_id wm8994_of_match[] = { diff --git a/drivers/misc/mei/bus-fixup.c b/drivers/misc/mei/bus-fixup.c index e9e6ea3ab73c..75b9d4ac8b1e 100644 --- a/drivers/misc/mei/bus-fixup.c +++ b/drivers/misc/mei/bus-fixup.c @@ -178,7 +178,7 @@ static int mei_nfc_if_version(struct mei_cl *cl, ret = 0; bytes_recv = __mei_cl_recv(cl, (u8 *)reply, if_version_length); - if (bytes_recv < 0 || bytes_recv < sizeof(struct mei_nfc_reply)) { + if (bytes_recv < if_version_length) { dev_err(bus->dev, "Could not read IF version\n"); ret = -EIO; goto err; diff --git a/drivers/mmc/card/mmc_test.c b/drivers/mmc/card/mmc_test.c index 5a8dc5a76e0d..3678220964fe 100644 --- a/drivers/mmc/card/mmc_test.c +++ b/drivers/mmc/card/mmc_test.c @@ -2347,7 +2347,7 @@ static int mmc_test_ongoing_transfer(struct mmc_test_card *test, struct mmc_test_req *rq = mmc_test_req_alloc(); struct mmc_host *host = test->card->host; struct mmc_test_area *t = &test->area; - struct mmc_async_req areq; + struct mmc_test_async_req test_areq = { .test = test }; struct mmc_request *mrq; unsigned long timeout; bool expired = false; @@ -2363,8 +2363,8 @@ static int mmc_test_ongoing_transfer(struct mmc_test_card *test, mrq->sbc = &rq->sbc; mrq->cap_cmd_during_tfr = true; - areq.mrq = mrq; - areq.err_check = mmc_test_check_result_async; + test_areq.areq.mrq = mrq; + test_areq.areq.err_check = mmc_test_check_result_async; mmc_test_prepare_mrq(test, mrq, t->sg, t->sg_len, dev_addr, t->blocks, 512, write); @@ -2378,7 +2378,7 @@ static int mmc_test_ongoing_transfer(struct mmc_test_card *test, /* Start ongoing data request */ if (use_areq) { - mmc_start_req(host, &areq, &ret); + mmc_start_req(host, &test_areq.areq, &ret); if (ret) goto out_free; } else { diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c index 39fc5b2b96c5..df19777068a6 100644 --- a/drivers/mmc/core/mmc.c +++ b/drivers/mmc/core/mmc.c @@ -26,6 +26,8 @@ #include "mmc_ops.h" #include "sd_ops.h" +#define DEFAULT_CMD6_TIMEOUT_MS 500 + static const unsigned int tran_exp[] = { 10000, 100000, 1000000, 10000000, 0, 0, 0, 0 @@ -571,6 +573,7 @@ static int mmc_decode_ext_csd(struct mmc_card *card, u8 *ext_csd) card->erased_byte = 0x0; /* eMMC v4.5 or later */ + card->ext_csd.generic_cmd6_time = DEFAULT_CMD6_TIMEOUT_MS; if (card->ext_csd.rev >= 6) { card->ext_csd.feature_support |= MMC_DISCARD_FEATURE; diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c index 4fcbc4012ed0..df478ae72e23 100644 --- a/drivers/mmc/host/dw_mmc.c +++ b/drivers/mmc/host/dw_mmc.c @@ -1058,6 +1058,7 @@ static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data) spin_unlock_irqrestore(&host->irq_lock, irqflags); if (host->dma_ops->start(host, sg_len)) { + host->dma_ops->stop(host); /* We can't do DMA, try PIO for this one */ dev_dbg(host->dev, "%s: fall back to PIO mode for current transfer\n", @@ -2940,7 +2941,7 @@ static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) return ERR_PTR(-ENOMEM); /* find reset controller when exist */ - pdata->rstc = devm_reset_control_get_optional(dev, NULL); + pdata->rstc = devm_reset_control_get_optional(dev, "reset"); if (IS_ERR(pdata->rstc)) { if (PTR_ERR(pdata->rstc) == -EPROBE_DEFER) return ERR_PTR(-EPROBE_DEFER); diff --git a/drivers/mmc/host/mxs-mmc.c b/drivers/mmc/host/mxs-mmc.c index d839147e591d..44ecebd1ea8c 100644 --- a/drivers/mmc/host/mxs-mmc.c +++ b/drivers/mmc/host/mxs-mmc.c @@ -661,13 +661,13 @@ static int mxs_mmc_probe(struct platform_device *pdev) platform_set_drvdata(pdev, mmc); + spin_lock_init(&host->lock); + ret = devm_request_irq(&pdev->dev, irq_err, mxs_mmc_irq_handler, 0, dev_name(&pdev->dev), host); if (ret) goto out_free_dma; - spin_lock_init(&host->lock); - ret = mmc_add_host(mmc); if (ret) goto out_free_dma; diff --git a/drivers/mmc/host/sdhci-of-esdhc.c b/drivers/mmc/host/sdhci-of-esdhc.c index fb71c866eacc..1bb11e4a9fe5 100644 --- a/drivers/mmc/host/sdhci-of-esdhc.c +++ b/drivers/mmc/host/sdhci-of-esdhc.c @@ -66,6 +66,20 @@ static u32 esdhc_readl_fixup(struct sdhci_host *host, return ret; } } + /* + * The DAT[3:0] line signal levels and the CMD line signal level are + * not compatible with standard SDHC register. The line signal levels + * DAT[7:0] are at bits 31:24 and the command line signal level is at + * bit 23. All other bits are the same as in the standard SDHC + * register. + */ + if (spec_reg == SDHCI_PRESENT_STATE) { + ret = value & 0x000fffff; + ret |= (value >> 4) & SDHCI_DATA_LVL_MASK; + ret |= (value << 1) & SDHCI_CMD_LVL; + return ret; + } + ret = value; return ret; } diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 71654b90227f..42ef3ebb1d8c 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -2086,6 +2086,10 @@ static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) if (!host->tuning_done) { pr_info(DRIVER_NAME ": Timeout waiting for Buffer Read Ready interrupt during tuning procedure, falling back to fixed sampling clock\n"); + + sdhci_do_reset(host, SDHCI_RESET_CMD); + sdhci_do_reset(host, SDHCI_RESET_DATA); + ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); ctrl &= ~SDHCI_CTRL_TUNED_CLK; ctrl &= ~SDHCI_CTRL_EXEC_TUNING; @@ -2286,10 +2290,8 @@ static bool sdhci_request_done(struct sdhci_host *host) for (i = 0; i < SDHCI_MAX_MRQS; i++) { mrq = host->mrqs_done[i]; - if (mrq) { - host->mrqs_done[i] = NULL; + if (mrq) break; - } } if (!mrq) { @@ -2320,6 +2322,17 @@ static bool sdhci_request_done(struct sdhci_host *host) * upon error conditions. */ if (sdhci_needs_reset(host, mrq)) { + /* + * Do not finish until command and data lines are available for + * reset. Note there can only be one other mrq, so it cannot + * also be in mrqs_done, otherwise host->cmd and host->data_cmd + * would both be null. + */ + if (host->cmd || host->data_cmd) { + spin_unlock_irqrestore(&host->lock, flags); + return true; + } + /* Some controllers need this kick or reset won't work here */ if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) /* This is to force an update */ @@ -2327,10 +2340,8 @@ static bool sdhci_request_done(struct sdhci_host *host) /* Spec says we should do both at the same time, but Ricoh controllers do not like that. */ - if (!host->cmd) - sdhci_do_reset(host, SDHCI_RESET_CMD); - if (!host->data_cmd) - sdhci_do_reset(host, SDHCI_RESET_DATA); + sdhci_do_reset(host, SDHCI_RESET_CMD); + sdhci_do_reset(host, SDHCI_RESET_DATA); host->pending_reset = false; } @@ -2338,6 +2349,8 @@ static bool sdhci_request_done(struct sdhci_host *host) if (!sdhci_has_requests(host)) sdhci_led_deactivate(host); + host->mrqs_done[i] = NULL; + mmiowb(); spin_unlock_irqrestore(&host->lock, flags); @@ -2512,9 +2525,6 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) if (!host->data) { struct mmc_command *data_cmd = host->data_cmd; - if (data_cmd) - host->data_cmd = NULL; - /* * The "data complete" interrupt is also used to * indicate that a busy state has ended. See comment @@ -2522,11 +2532,13 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) */ if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) { if (intmask & SDHCI_INT_DATA_TIMEOUT) { + host->data_cmd = NULL; data_cmd->error = -ETIMEDOUT; sdhci_finish_mrq(host, data_cmd->mrq); return; } if (intmask & SDHCI_INT_DATA_END) { + host->data_cmd = NULL; /* * Some cards handle busy-end interrupt * before the command completed, so make @@ -2912,6 +2924,10 @@ int sdhci_runtime_resume_host(struct sdhci_host *host) spin_unlock_irqrestore(&host->lock, flags); } + if ((mmc->caps2 & MMC_CAP2_HS400_ES) && + mmc->ops->hs400_enhanced_strobe) + mmc->ops->hs400_enhanced_strobe(mmc, &mmc->ios); + spin_lock_irqsave(&host->lock, flags); host->runtime_suspended = false; diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 766df17fb7eb..2570455b219a 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -73,6 +73,7 @@ #define SDHCI_DATA_LVL_MASK 0x00F00000 #define SDHCI_DATA_LVL_SHIFT 20 #define SDHCI_DATA_0_LVL_MASK 0x00100000 +#define SDHCI_CMD_LVL 0x01000000 #define SDHCI_HOST_CONTROL 0x28 #define SDHCI_CTRL_LED 0x01 diff --git a/drivers/net/can/sja1000/plx_pci.c b/drivers/net/can/sja1000/plx_pci.c index 3eb7430dffbf..f8ff25c8ee2e 100644 --- a/drivers/net/can/sja1000/plx_pci.c +++ b/drivers/net/can/sja1000/plx_pci.c @@ -142,6 +142,9 @@ struct plx_pci_card { #define CTI_PCI_VENDOR_ID 0x12c4 #define CTI_PCI_DEVICE_ID_CRG001 0x0900 +#define MOXA_PCI_VENDOR_ID 0x1393 +#define MOXA_PCI_DEVICE_ID 0x0100 + static void plx_pci_reset_common(struct pci_dev *pdev); static void plx9056_pci_reset_common(struct pci_dev *pdev); static void plx_pci_reset_marathon_pci(struct pci_dev *pdev); @@ -258,6 +261,14 @@ static struct plx_pci_card_info plx_pci_card_info_elcus = { /* based on PLX9030 */ }; +static struct plx_pci_card_info plx_pci_card_info_moxa = { + "MOXA", 2, + PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, + {0, 0x00, 0x00}, { {0, 0x00, 0x80}, {1, 0x00, 0x80} }, + &plx_pci_reset_common + /* based on PLX9052 */ +}; + static const struct pci_device_id plx_pci_tbl[] = { { /* Adlink PCI-7841/cPCI-7841 */ @@ -357,6 +368,13 @@ static const struct pci_device_id plx_pci_tbl[] = { 0, 0, (kernel_ulong_t)&plx_pci_card_info_elcus }, + { + /* moxa */ + MOXA_PCI_VENDOR_ID, MOXA_PCI_DEVICE_ID, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + (kernel_ulong_t)&plx_pci_card_info_moxa + }, { 0,} }; MODULE_DEVICE_TABLE(pci, plx_pci_tbl); diff --git a/drivers/net/can/usb/peak_usb/pcan_ucan.h b/drivers/net/can/usb/peak_usb/pcan_ucan.h index e8fc4952c6b0..2147678f0225 100644 --- a/drivers/net/can/usb/peak_usb/pcan_ucan.h +++ b/drivers/net/can/usb/peak_usb/pcan_ucan.h @@ -43,11 +43,22 @@ struct __packed pucan_command { u16 args[3]; }; +#define PUCAN_TSLOW_BRP_BITS 10 +#define PUCAN_TSLOW_TSGEG1_BITS 8 +#define PUCAN_TSLOW_TSGEG2_BITS 7 +#define PUCAN_TSLOW_SJW_BITS 7 + +#define PUCAN_TSLOW_BRP_MASK ((1 << PUCAN_TSLOW_BRP_BITS) - 1) +#define PUCAN_TSLOW_TSEG1_MASK ((1 << PUCAN_TSLOW_TSGEG1_BITS) - 1) +#define PUCAN_TSLOW_TSEG2_MASK ((1 << PUCAN_TSLOW_TSGEG2_BITS) - 1) +#define PUCAN_TSLOW_SJW_MASK ((1 << PUCAN_TSLOW_SJW_BITS) - 1) + /* uCAN TIMING_SLOW command fields */ -#define PUCAN_TSLOW_SJW_T(s, t) (((s) & 0xf) | ((!!(t)) << 7)) -#define PUCAN_TSLOW_TSEG2(t) ((t) & 0xf) -#define PUCAN_TSLOW_TSEG1(t) ((t) & 0x3f) -#define PUCAN_TSLOW_BRP(b) ((b) & 0x3ff) +#define PUCAN_TSLOW_SJW_T(s, t) (((s) & PUCAN_TSLOW_SJW_MASK) | \ + ((!!(t)) << 7)) +#define PUCAN_TSLOW_TSEG2(t) ((t) & PUCAN_TSLOW_TSEG2_MASK) +#define PUCAN_TSLOW_TSEG1(t) ((t) & PUCAN_TSLOW_TSEG1_MASK) +#define PUCAN_TSLOW_BRP(b) ((b) & PUCAN_TSLOW_BRP_MASK) struct __packed pucan_timing_slow { __le16 opcode_channel; @@ -60,11 +71,21 @@ struct __packed pucan_timing_slow { __le16 brp; /* BaudRate Prescaler */ }; +#define PUCAN_TFAST_BRP_BITS 10 +#define PUCAN_TFAST_TSGEG1_BITS 5 +#define PUCAN_TFAST_TSGEG2_BITS 4 +#define PUCAN_TFAST_SJW_BITS 4 + +#define PUCAN_TFAST_BRP_MASK ((1 << PUCAN_TFAST_BRP_BITS) - 1) +#define PUCAN_TFAST_TSEG1_MASK ((1 << PUCAN_TFAST_TSGEG1_BITS) - 1) +#define PUCAN_TFAST_TSEG2_MASK ((1 << PUCAN_TFAST_TSGEG2_BITS) - 1) +#define PUCAN_TFAST_SJW_MASK ((1 << PUCAN_TFAST_SJW_BITS) - 1) + /* uCAN TIMING_FAST command fields */ -#define PUCAN_TFAST_SJW(s) ((s) & 0x3) -#define PUCAN_TFAST_TSEG2(t) ((t) & 0x7) -#define PUCAN_TFAST_TSEG1(t) ((t) & 0xf) -#define PUCAN_TFAST_BRP(b) ((b) & 0x3ff) +#define PUCAN_TFAST_SJW(s) ((s) & PUCAN_TFAST_SJW_MASK) +#define PUCAN_TFAST_TSEG2(t) ((t) & PUCAN_TFAST_TSEG2_MASK) +#define PUCAN_TFAST_TSEG1(t) ((t) & PUCAN_TFAST_TSEG1_MASK) +#define PUCAN_TFAST_BRP(b) ((b) & PUCAN_TFAST_BRP_MASK) struct __packed pucan_timing_fast { __le16 opcode_channel; diff --git a/drivers/net/can/usb/peak_usb/pcan_usb_core.c b/drivers/net/can/usb/peak_usb/pcan_usb_core.c index c06382cdfdfe..f3141ca56bc3 100644 --- a/drivers/net/can/usb/peak_usb/pcan_usb_core.c +++ b/drivers/net/can/usb/peak_usb/pcan_usb_core.c @@ -39,6 +39,7 @@ static struct usb_device_id peak_usb_table[] = { {USB_DEVICE(PCAN_USB_VENDOR_ID, PCAN_USBPRO_PRODUCT_ID)}, {USB_DEVICE(PCAN_USB_VENDOR_ID, PCAN_USBFD_PRODUCT_ID)}, {USB_DEVICE(PCAN_USB_VENDOR_ID, PCAN_USBPROFD_PRODUCT_ID)}, + {USB_DEVICE(PCAN_USB_VENDOR_ID, PCAN_USBX6_PRODUCT_ID)}, {} /* Terminating entry */ }; @@ -50,6 +51,7 @@ static const struct peak_usb_adapter *const peak_usb_adapters_list[] = { &pcan_usb_pro, &pcan_usb_fd, &pcan_usb_pro_fd, + &pcan_usb_x6, }; /* diff --git a/drivers/net/can/usb/peak_usb/pcan_usb_core.h b/drivers/net/can/usb/peak_usb/pcan_usb_core.h index 506fe506c9d3..3cbfb069893d 100644 --- a/drivers/net/can/usb/peak_usb/pcan_usb_core.h +++ b/drivers/net/can/usb/peak_usb/pcan_usb_core.h @@ -27,6 +27,7 @@ #define PCAN_USBPRO_PRODUCT_ID 0x000d #define PCAN_USBPROFD_PRODUCT_ID 0x0011 #define PCAN_USBFD_PRODUCT_ID 0x0012 +#define PCAN_USBX6_PRODUCT_ID 0x0014 #define PCAN_USB_DRIVER_NAME "peak_usb" @@ -90,6 +91,7 @@ extern const struct peak_usb_adapter pcan_usb; extern const struct peak_usb_adapter pcan_usb_pro; extern const struct peak_usb_adapter pcan_usb_fd; extern const struct peak_usb_adapter pcan_usb_pro_fd; +extern const struct peak_usb_adapter pcan_usb_x6; struct peak_time_ref { struct timeval tv_host_0, tv_host; diff --git a/drivers/net/can/usb/peak_usb/pcan_usb_fd.c b/drivers/net/can/usb/peak_usb/pcan_usb_fd.c index ce44a033f63b..304732550f0a 100644 --- a/drivers/net/can/usb/peak_usb/pcan_usb_fd.c +++ b/drivers/net/can/usb/peak_usb/pcan_usb_fd.c @@ -993,24 +993,24 @@ static void pcan_usb_fd_free(struct peak_usb_device *dev) static const struct can_bittiming_const pcan_usb_fd_const = { .name = "pcan_usb_fd", .tseg1_min = 1, - .tseg1_max = 64, + .tseg1_max = (1 << PUCAN_TSLOW_TSGEG1_BITS), .tseg2_min = 1, - .tseg2_max = 16, - .sjw_max = 16, + .tseg2_max = (1 << PUCAN_TSLOW_TSGEG2_BITS), + .sjw_max = (1 << PUCAN_TSLOW_SJW_BITS), .brp_min = 1, - .brp_max = 1024, + .brp_max = (1 << PUCAN_TSLOW_BRP_BITS), .brp_inc = 1, }; static const struct can_bittiming_const pcan_usb_fd_data_const = { .name = "pcan_usb_fd", .tseg1_min = 1, - .tseg1_max = 16, + .tseg1_max = (1 << PUCAN_TFAST_TSGEG1_BITS), .tseg2_min = 1, - .tseg2_max = 8, - .sjw_max = 4, + .tseg2_max = (1 << PUCAN_TFAST_TSGEG2_BITS), + .sjw_max = (1 << PUCAN_TFAST_SJW_BITS), .brp_min = 1, - .brp_max = 1024, + .brp_max = (1 << PUCAN_TFAST_BRP_BITS), .brp_inc = 1, }; @@ -1065,24 +1065,24 @@ const struct peak_usb_adapter pcan_usb_fd = { static const struct can_bittiming_const pcan_usb_pro_fd_const = { .name = "pcan_usb_pro_fd", .tseg1_min = 1, - .tseg1_max = 64, + .tseg1_max = (1 << PUCAN_TSLOW_TSGEG1_BITS), .tseg2_min = 1, - .tseg2_max = 16, - .sjw_max = 16, + .tseg2_max = (1 << PUCAN_TSLOW_TSGEG2_BITS), + .sjw_max = (1 << PUCAN_TSLOW_SJW_BITS), .brp_min = 1, - .brp_max = 1024, + .brp_max = (1 << PUCAN_TSLOW_BRP_BITS), .brp_inc = 1, }; static const struct can_bittiming_const pcan_usb_pro_fd_data_const = { .name = "pcan_usb_pro_fd", .tseg1_min = 1, - .tseg1_max = 16, + .tseg1_max = (1 << PUCAN_TFAST_TSGEG1_BITS), .tseg2_min = 1, - .tseg2_max = 8, - .sjw_max = 4, + .tseg2_max = (1 << PUCAN_TFAST_TSGEG2_BITS), + .sjw_max = (1 << PUCAN_TFAST_SJW_BITS), .brp_min = 1, - .brp_max = 1024, + .brp_max = (1 << PUCAN_TFAST_BRP_BITS), .brp_inc = 1, }; @@ -1132,3 +1132,75 @@ const struct peak_usb_adapter pcan_usb_pro_fd = { .do_get_berr_counter = pcan_usb_fd_get_berr_counter, }; + +/* describes the PCAN-USB X6 adapter */ +static const struct can_bittiming_const pcan_usb_x6_const = { + .name = "pcan_usb_x6", + .tseg1_min = 1, + .tseg1_max = (1 << PUCAN_TSLOW_TSGEG1_BITS), + .tseg2_min = 1, + .tseg2_max = (1 << PUCAN_TSLOW_TSGEG2_BITS), + .sjw_max = (1 << PUCAN_TSLOW_SJW_BITS), + .brp_min = 1, + .brp_max = (1 << PUCAN_TSLOW_BRP_BITS), + .brp_inc = 1, +}; + +static const struct can_bittiming_const pcan_usb_x6_data_const = { + .name = "pcan_usb_x6", + .tseg1_min = 1, + .tseg1_max = (1 << PUCAN_TFAST_TSGEG1_BITS), + .tseg2_min = 1, + .tseg2_max = (1 << PUCAN_TFAST_TSGEG2_BITS), + .sjw_max = (1 << PUCAN_TFAST_SJW_BITS), + .brp_min = 1, + .brp_max = (1 << PUCAN_TFAST_BRP_BITS), + .brp_inc = 1, +}; + +const struct peak_usb_adapter pcan_usb_x6 = { + .name = "PCAN-USB X6", + .device_id = PCAN_USBX6_PRODUCT_ID, + .ctrl_count = PCAN_USBPROFD_CHANNEL_COUNT, + .ctrlmode_supported = CAN_CTRLMODE_FD | + CAN_CTRLMODE_3_SAMPLES | CAN_CTRLMODE_LISTENONLY, + .clock = { + .freq = PCAN_UFD_CRYSTAL_HZ, + }, + .bittiming_const = &pcan_usb_x6_const, + .data_bittiming_const = &pcan_usb_x6_data_const, + + /* size of device private data */ + .sizeof_dev_private = sizeof(struct pcan_usb_fd_device), + + /* timestamps usage */ + .ts_used_bits = 32, + .ts_period = 1000000, /* calibration period in ts. */ + .us_per_ts_scale = 1, /* us = (ts * scale) >> shift */ + .us_per_ts_shift = 0, + + /* give here messages in/out endpoints */ + .ep_msg_in = PCAN_USBPRO_EP_MSGIN, + .ep_msg_out = {PCAN_USBPRO_EP_MSGOUT_0, PCAN_USBPRO_EP_MSGOUT_1}, + + /* size of rx/tx usb buffers */ + .rx_buffer_size = PCAN_UFD_RX_BUFFER_SIZE, + .tx_buffer_size = PCAN_UFD_TX_BUFFER_SIZE, + + /* device callbacks */ + .intf_probe = pcan_usb_pro_probe, /* same as PCAN-USB Pro */ + .dev_init = pcan_usb_fd_init, + + .dev_exit = pcan_usb_fd_exit, + .dev_free = pcan_usb_fd_free, + .dev_set_bus = pcan_usb_fd_set_bus, + .dev_set_bittiming = pcan_usb_fd_set_bittiming_slow, + .dev_set_data_bittiming = pcan_usb_fd_set_bittiming_fast, + .dev_decode_buf = pcan_usb_fd_decode_buf, + .dev_start = pcan_usb_fd_start, + .dev_stop = pcan_usb_fd_stop, + .dev_restart_async = pcan_usb_fd_restart_async, + .dev_encode_msg = pcan_usb_fd_encode_msg, + + .do_get_berr_counter = pcan_usb_fd_get_berr_counter, +}; diff --git a/drivers/net/dsa/b53/b53_common.c b/drivers/net/dsa/b53/b53_common.c index 7717b19dc806..947adda3397d 100644 --- a/drivers/net/dsa/b53/b53_common.c +++ b/drivers/net/dsa/b53/b53_common.c @@ -962,9 +962,10 @@ static void b53_vlan_add(struct dsa_switch *ds, int port, vl->members |= BIT(port) | BIT(cpu_port); if (untagged) - vl->untag |= BIT(port) | BIT(cpu_port); + vl->untag |= BIT(port); else - vl->untag &= ~(BIT(port) | BIT(cpu_port)); + vl->untag &= ~BIT(port); + vl->untag &= ~BIT(cpu_port); b53_set_vlan_entry(dev, vid, vl); b53_fast_age_vlan(dev, vid); @@ -973,8 +974,6 @@ static void b53_vlan_add(struct dsa_switch *ds, int port, if (pvid) { b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), vlan->vid_end); - b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(cpu_port), - vlan->vid_end); b53_fast_age_vlan(dev, vid); } } @@ -984,7 +983,6 @@ static int b53_vlan_del(struct dsa_switch *ds, int port, { struct b53_device *dev = ds->priv; bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; - unsigned int cpu_port = dev->cpu_port; struct b53_vlan *vl; u16 vid; u16 pvid; @@ -997,8 +995,6 @@ static int b53_vlan_del(struct dsa_switch *ds, int port, b53_get_vlan_entry(dev, vid, vl); vl->members &= ~BIT(port); - if ((vl->members & BIT(cpu_port)) == BIT(cpu_port)) - vl->members = 0; if (pvid == vid) { if (is5325(dev) || is5365(dev)) @@ -1007,18 +1003,14 @@ static int b53_vlan_del(struct dsa_switch *ds, int port, pvid = 0; } - if (untagged) { + if (untagged) vl->untag &= ~(BIT(port)); - if ((vl->untag & BIT(cpu_port)) == BIT(cpu_port)) - vl->untag = 0; - } b53_set_vlan_entry(dev, vid, vl); b53_fast_age_vlan(dev, vid); } b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid); - b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(cpu_port), pvid); b53_fast_age_vlan(dev, pvid); return 0; diff --git a/drivers/net/dsa/bcm_sf2.c b/drivers/net/dsa/bcm_sf2.c index e3ee27ce13dd..9ec33b51a0ed 100644 --- a/drivers/net/dsa/bcm_sf2.c +++ b/drivers/net/dsa/bcm_sf2.c @@ -588,6 +588,7 @@ static void bcm_sf2_sw_adjust_link(struct dsa_switch *ds, int port, struct phy_device *phydev) { struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); + struct ethtool_eee *p = &priv->port_sts[port].eee; u32 id_mode_dis = 0, port_mode; const char *str = NULL; u32 reg; @@ -662,6 +663,9 @@ force_link: reg |= DUPLX_MODE; core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(port)); + + if (!phydev->is_pseudo_fixed_link) + p->eee_enabled = bcm_sf2_eee_init(ds, port, phydev); } static void bcm_sf2_sw_fixed_link_update(struct dsa_switch *ds, int port, diff --git a/drivers/net/ethernet/altera/altera_tse_main.c b/drivers/net/ethernet/altera/altera_tse_main.c index bda31f308cc2..a0eee7218695 100644 --- a/drivers/net/ethernet/altera/altera_tse_main.c +++ b/drivers/net/ethernet/altera/altera_tse_main.c @@ -400,12 +400,6 @@ static int tse_rx(struct altera_tse_private *priv, int limit) skb_put(skb, pktlength); - /* make cache consistent with receive packet buffer */ - dma_sync_single_for_cpu(priv->device, - priv->rx_ring[entry].dma_addr, - priv->rx_ring[entry].len, - DMA_FROM_DEVICE); - dma_unmap_single(priv->device, priv->rx_ring[entry].dma_addr, priv->rx_ring[entry].len, DMA_FROM_DEVICE); @@ -469,7 +463,6 @@ static int tse_tx_complete(struct altera_tse_private *priv) if (unlikely(netif_queue_stopped(priv->dev) && tse_tx_avail(priv) > TSE_TX_THRESH(priv))) { - netif_tx_lock(priv->dev); if (netif_queue_stopped(priv->dev) && tse_tx_avail(priv) > TSE_TX_THRESH(priv)) { if (netif_msg_tx_done(priv)) @@ -477,7 +470,6 @@ static int tse_tx_complete(struct altera_tse_private *priv) __func__); netif_wake_queue(priv->dev); } - netif_tx_unlock(priv->dev); } spin_unlock(&priv->tx_lock); @@ -592,10 +584,6 @@ static int tse_start_xmit(struct sk_buff *skb, struct net_device *dev) buffer->dma_addr = dma_addr; buffer->len = nopaged_len; - /* Push data out of the cache hierarchy into main memory */ - dma_sync_single_for_device(priv->device, buffer->dma_addr, - buffer->len, DMA_TO_DEVICE); - priv->dmaops->tx_buffer(priv, buffer); skb_tx_timestamp(skb); @@ -819,6 +807,8 @@ static int init_phy(struct net_device *dev) if (!phydev) { netdev_err(dev, "Could not find the PHY\n"); + if (fixed_link) + of_phy_deregister_fixed_link(priv->device->of_node); return -ENODEV; } @@ -1545,10 +1535,15 @@ err_free_netdev: static int altera_tse_remove(struct platform_device *pdev) { struct net_device *ndev = platform_get_drvdata(pdev); + struct altera_tse_private *priv = netdev_priv(ndev); - if (ndev->phydev) + if (ndev->phydev) { phy_disconnect(ndev->phydev); + if (of_phy_is_fixed_link(priv->device->of_node)) + of_phy_deregister_fixed_link(priv->device->of_node); + } + platform_set_drvdata(pdev, NULL); altera_tse_mdio_destroy(ndev); unregister_netdev(ndev); diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-main.c b/drivers/net/ethernet/amd/xgbe/xgbe-main.c index 9de078819aa6..4f7635178200 100644 --- a/drivers/net/ethernet/amd/xgbe/xgbe-main.c +++ b/drivers/net/ethernet/amd/xgbe/xgbe-main.c @@ -829,7 +829,7 @@ static int xgbe_remove(struct platform_device *pdev) return 0; } -#ifdef CONFIG_PM +#ifdef CONFIG_PM_SLEEP static int xgbe_suspend(struct device *dev) { struct net_device *netdev = dev_get_drvdata(dev); @@ -874,7 +874,7 @@ static int xgbe_resume(struct device *dev) return ret; } -#endif /* CONFIG_PM */ +#endif /* CONFIG_PM_SLEEP */ #ifdef CONFIG_ACPI static const struct acpi_device_id xgbe_acpi_match[] = { diff --git a/drivers/net/ethernet/apm/xgene/xgene_enet_hw.c b/drivers/net/ethernet/apm/xgene/xgene_enet_hw.c index c481f104a8fe..5390ae89136c 100644 --- a/drivers/net/ethernet/apm/xgene/xgene_enet_hw.c +++ b/drivers/net/ethernet/apm/xgene/xgene_enet_hw.c @@ -204,17 +204,6 @@ static u32 xgene_enet_ring_len(struct xgene_enet_desc_ring *ring) return num_msgs; } -static void xgene_enet_setup_coalescing(struct xgene_enet_desc_ring *ring) -{ - u32 data = 0x7777; - - xgene_enet_ring_wr32(ring, CSR_PBM_COAL, 0x8e); - xgene_enet_ring_wr32(ring, CSR_PBM_CTICK1, data); - xgene_enet_ring_wr32(ring, CSR_PBM_CTICK2, data << 16); - xgene_enet_ring_wr32(ring, CSR_THRESHOLD0_SET1, 0x40); - xgene_enet_ring_wr32(ring, CSR_THRESHOLD1_SET1, 0x80); -} - void xgene_enet_parse_error(struct xgene_enet_desc_ring *ring, struct xgene_enet_pdata *pdata, enum xgene_enet_err_code status) @@ -929,5 +918,4 @@ struct xgene_ring_ops xgene_ring1_ops = { .clear = xgene_enet_clear_ring, .wr_cmd = xgene_enet_wr_cmd, .len = xgene_enet_ring_len, - .coalesce = xgene_enet_setup_coalescing, }; diff --git a/drivers/net/ethernet/apm/xgene/xgene_enet_hw.h b/drivers/net/ethernet/apm/xgene/xgene_enet_hw.h index 8456337a237d..06e598c8bc16 100644 --- a/drivers/net/ethernet/apm/xgene/xgene_enet_hw.h +++ b/drivers/net/ethernet/apm/xgene/xgene_enet_hw.h @@ -55,8 +55,10 @@ enum xgene_enet_rm { #define PREFETCH_BUF_EN BIT(21) #define CSR_RING_ID_BUF 0x000c #define CSR_PBM_COAL 0x0014 +#define CSR_PBM_CTICK0 0x0018 #define CSR_PBM_CTICK1 0x001c #define CSR_PBM_CTICK2 0x0020 +#define CSR_PBM_CTICK3 0x0024 #define CSR_THRESHOLD0_SET1 0x0030 #define CSR_THRESHOLD1_SET1 0x0034 #define CSR_RING_NE_INT_MODE 0x017c diff --git a/drivers/net/ethernet/apm/xgene/xgene_enet_main.c b/drivers/net/ethernet/apm/xgene/xgene_enet_main.c index 429f18fc5503..8158d4698734 100644 --- a/drivers/net/ethernet/apm/xgene/xgene_enet_main.c +++ b/drivers/net/ethernet/apm/xgene/xgene_enet_main.c @@ -1188,7 +1188,8 @@ static int xgene_enet_create_desc_rings(struct net_device *ndev) tx_ring->dst_ring_num = xgene_enet_dst_ring_num(cp_ring); } - pdata->ring_ops->coalesce(pdata->tx_ring[0]); + if (pdata->ring_ops->coalesce) + pdata->ring_ops->coalesce(pdata->tx_ring[0]); pdata->tx_qcnt_hi = pdata->tx_ring[0]->slots - 128; return 0; diff --git a/drivers/net/ethernet/apm/xgene/xgene_enet_ring2.c b/drivers/net/ethernet/apm/xgene/xgene_enet_ring2.c index 2b76732add5d..af51dd5844ce 100644 --- a/drivers/net/ethernet/apm/xgene/xgene_enet_ring2.c +++ b/drivers/net/ethernet/apm/xgene/xgene_enet_ring2.c @@ -30,7 +30,7 @@ static void xgene_enet_ring_init(struct xgene_enet_desc_ring *ring) ring_cfg[0] |= SET_VAL(X2_INTLINE, ring->id & RING_BUFNUM_MASK); ring_cfg[3] |= SET_BIT(X2_DEQINTEN); } - ring_cfg[0] |= SET_VAL(X2_CFGCRID, 1); + ring_cfg[0] |= SET_VAL(X2_CFGCRID, 2); addr >>= 8; ring_cfg[2] |= QCOHERENT | SET_VAL(RINGADDRL, addr); @@ -192,13 +192,15 @@ static u32 xgene_enet_ring_len(struct xgene_enet_desc_ring *ring) static void xgene_enet_setup_coalescing(struct xgene_enet_desc_ring *ring) { - u32 data = 0x7777; + u32 data = 0x77777777; xgene_enet_ring_wr32(ring, CSR_PBM_COAL, 0x8e); + xgene_enet_ring_wr32(ring, CSR_PBM_CTICK0, data); xgene_enet_ring_wr32(ring, CSR_PBM_CTICK1, data); - xgene_enet_ring_wr32(ring, CSR_PBM_CTICK2, data << 16); - xgene_enet_ring_wr32(ring, CSR_THRESHOLD0_SET1, 0x40); - xgene_enet_ring_wr32(ring, CSR_THRESHOLD1_SET1, 0x80); + xgene_enet_ring_wr32(ring, CSR_PBM_CTICK2, data); + xgene_enet_ring_wr32(ring, CSR_PBM_CTICK3, data); + xgene_enet_ring_wr32(ring, CSR_THRESHOLD0_SET1, 0x08); + xgene_enet_ring_wr32(ring, CSR_THRESHOLD1_SET1, 0x10); } struct xgene_ring_ops xgene_ring2_ops = { diff --git a/drivers/net/ethernet/arc/emac_main.c b/drivers/net/ethernet/arc/emac_main.c index b0da9693f28a..be865b4dada2 100644 --- a/drivers/net/ethernet/arc/emac_main.c +++ b/drivers/net/ethernet/arc/emac_main.c @@ -460,7 +460,7 @@ static void arc_emac_set_rx_mode(struct net_device *ndev) if (ndev->flags & IFF_ALLMULTI) { arc_reg_set(priv, R_LAFL, ~0); arc_reg_set(priv, R_LAFH, ~0); - } else { + } else if (ndev->flags & IFF_MULTICAST) { struct netdev_hw_addr *ha; unsigned int filter[2] = { 0, 0 }; int bit; @@ -472,6 +472,9 @@ static void arc_emac_set_rx_mode(struct net_device *ndev) arc_reg_set(priv, R_LAFL, filter[0]); arc_reg_set(priv, R_LAFH, filter[1]); + } else { + arc_reg_set(priv, R_LAFL, 0); + arc_reg_set(priv, R_LAFH, 0); } } } @@ -764,8 +767,6 @@ int arc_emac_probe(struct net_device *ndev, int interface) ndev->netdev_ops = &arc_emac_netdev_ops; ndev->ethtool_ops = &arc_emac_ethtool_ops; ndev->watchdog_timeo = TX_TIMEOUT; - /* FIXME :: no multicast support yet */ - ndev->flags &= ~IFF_MULTICAST; priv = netdev_priv(ndev); priv->dev = dev; diff --git a/drivers/net/ethernet/aurora/nb8800.c b/drivers/net/ethernet/aurora/nb8800.c index 00c38bf151e6..e078d8da978c 100644 --- a/drivers/net/ethernet/aurora/nb8800.c +++ b/drivers/net/ethernet/aurora/nb8800.c @@ -1466,12 +1466,12 @@ static int nb8800_probe(struct platform_device *pdev) ret = nb8800_hw_init(dev); if (ret) - goto err_free_bus; + goto err_deregister_fixed_link; if (ops && ops->init) { ret = ops->init(dev); if (ret) - goto err_free_bus; + goto err_deregister_fixed_link; } dev->netdev_ops = &nb8800_netdev_ops; @@ -1504,6 +1504,9 @@ static int nb8800_probe(struct platform_device *pdev) err_free_dma: nb8800_dma_free(dev); +err_deregister_fixed_link: + if (of_phy_is_fixed_link(pdev->dev.of_node)) + of_phy_deregister_fixed_link(pdev->dev.of_node); err_free_bus: of_node_put(priv->phy_node); mdiobus_unregister(bus); @@ -1521,6 +1524,8 @@ static int nb8800_remove(struct platform_device *pdev) struct nb8800_priv *priv = netdev_priv(ndev); unregister_netdev(ndev); + if (of_phy_is_fixed_link(pdev->dev.of_node)) + of_phy_deregister_fixed_link(pdev->dev.of_node); of_node_put(priv->phy_node); mdiobus_unregister(priv->mii_bus); diff --git a/drivers/net/ethernet/broadcom/bcmsysport.c b/drivers/net/ethernet/broadcom/bcmsysport.c index c3354b9941d1..25d1eb4933d0 100644 --- a/drivers/net/ethernet/broadcom/bcmsysport.c +++ b/drivers/net/ethernet/broadcom/bcmsysport.c @@ -1755,13 +1755,13 @@ static int bcm_sysport_probe(struct platform_device *pdev) if (priv->irq0 <= 0 || priv->irq1 <= 0) { dev_err(&pdev->dev, "invalid interrupts\n"); ret = -EINVAL; - goto err; + goto err_free_netdev; } priv->base = devm_ioremap_resource(&pdev->dev, r); if (IS_ERR(priv->base)) { ret = PTR_ERR(priv->base); - goto err; + goto err_free_netdev; } priv->netdev = dev; @@ -1779,7 +1779,7 @@ static int bcm_sysport_probe(struct platform_device *pdev) ret = of_phy_register_fixed_link(dn); if (ret) { dev_err(&pdev->dev, "failed to register fixed PHY\n"); - goto err; + goto err_free_netdev; } priv->phy_dn = dn; @@ -1821,7 +1821,7 @@ static int bcm_sysport_probe(struct platform_device *pdev) ret = register_netdev(dev); if (ret) { dev_err(&pdev->dev, "failed to register net_device\n"); - goto err; + goto err_deregister_fixed_link; } priv->rev = topctrl_readl(priv, REV_CNTL) & REV_MASK; @@ -1832,7 +1832,11 @@ static int bcm_sysport_probe(struct platform_device *pdev) priv->base, priv->irq0, priv->irq1, txq, rxq); return 0; -err: + +err_deregister_fixed_link: + if (of_phy_is_fixed_link(dn)) + of_phy_deregister_fixed_link(dn); +err_free_netdev: free_netdev(dev); return ret; } @@ -1840,11 +1844,14 @@ err: static int bcm_sysport_remove(struct platform_device *pdev) { struct net_device *dev = dev_get_drvdata(&pdev->dev); + struct device_node *dn = pdev->dev.of_node; /* Not much to do, ndo_close has been called * and we use managed allocations */ unregister_netdev(dev); + if (of_phy_is_fixed_link(dn)) + of_phy_deregister_fixed_link(dn); free_netdev(dev); dev_set_drvdata(&pdev->dev, NULL); diff --git a/drivers/net/ethernet/broadcom/bgmac.c b/drivers/net/ethernet/broadcom/bgmac.c index 31ca204b38d2..49f4cafe5438 100644 --- a/drivers/net/ethernet/broadcom/bgmac.c +++ b/drivers/net/ethernet/broadcom/bgmac.c @@ -307,6 +307,10 @@ static void bgmac_dma_rx_enable(struct bgmac *bgmac, u32 ctl; ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL); + + /* preserve ONLY bits 16-17 from current hardware value */ + ctl &= BGMAC_DMA_RX_ADDREXT_MASK; + if (bgmac->feature_flags & BGMAC_FEAT_RX_MASK_SETUP) { ctl &= ~BGMAC_DMA_RX_BL_MASK; ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT; @@ -317,7 +321,6 @@ static void bgmac_dma_rx_enable(struct bgmac *bgmac, ctl &= ~BGMAC_DMA_RX_PT_MASK; ctl |= BGMAC_DMA_RX_PT_1 << BGMAC_DMA_RX_PT_SHIFT; } - ctl &= BGMAC_DMA_RX_ADDREXT_MASK; ctl |= BGMAC_DMA_RX_ENABLE; ctl |= BGMAC_DMA_RX_PARITY_DISABLE; ctl |= BGMAC_DMA_RX_OVERFLOW_CONT; @@ -1046,9 +1049,9 @@ static void bgmac_enable(struct bgmac *bgmac) mode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >> BGMAC_DS_MM_SHIFT; - if (!(bgmac->feature_flags & BGMAC_FEAT_CLKCTLST) || mode != 0) + if (bgmac->feature_flags & BGMAC_FEAT_CLKCTLST || mode != 0) bgmac_set(bgmac, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT); - if (bgmac->feature_flags & BGMAC_FEAT_CLKCTLST && mode == 2) + if (!(bgmac->feature_flags & BGMAC_FEAT_CLKCTLST) && mode == 2) bgmac_cco_ctl_maskset(bgmac, 1, ~0, BGMAC_CHIPCTL_1_RXC_DLL_BYPASS); diff --git a/drivers/net/ethernet/broadcom/bnx2.c b/drivers/net/ethernet/broadcom/bnx2.c index b3791b394715..1f7034d739b0 100644 --- a/drivers/net/ethernet/broadcom/bnx2.c +++ b/drivers/net/ethernet/broadcom/bnx2.c @@ -49,6 +49,7 @@ #include <linux/firmware.h> #include <linux/log2.h> #include <linux/aer.h> +#include <linux/crash_dump.h> #if IS_ENABLED(CONFIG_CNIC) #define BCM_CNIC 1 @@ -4764,15 +4765,16 @@ bnx2_setup_msix_tbl(struct bnx2 *bp) BNX2_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR); } -static int -bnx2_reset_chip(struct bnx2 *bp, u32 reset_code) +static void +bnx2_wait_dma_complete(struct bnx2 *bp) { u32 val; - int i, rc = 0; - u8 old_port; + int i; - /* Wait for the current PCI transaction to complete before - * issuing a reset. */ + /* + * Wait for the current PCI transaction to complete before + * issuing a reset. + */ if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) || (BNX2_CHIP(bp) == BNX2_CHIP_5708)) { BNX2_WR(bp, BNX2_MISC_ENABLE_CLR_BITS, @@ -4796,6 +4798,21 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code) } } + return; +} + + +static int +bnx2_reset_chip(struct bnx2 *bp, u32 reset_code) +{ + u32 val; + int i, rc = 0; + u8 old_port; + + /* Wait for the current PCI transaction to complete before + * issuing a reset. */ + bnx2_wait_dma_complete(bp); + /* Wait for the firmware to tell us it is ok to issue a reset. */ bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1); @@ -6361,6 +6378,10 @@ bnx2_open(struct net_device *dev) struct bnx2 *bp = netdev_priv(dev); int rc; + rc = bnx2_request_firmware(bp); + if (rc < 0) + goto out; + netif_carrier_off(dev); bnx2_disable_int(bp); @@ -6429,6 +6450,7 @@ open_err: bnx2_free_irq(bp); bnx2_free_mem(bp); bnx2_del_napi(bp); + bnx2_release_firmware(bp); goto out; } @@ -8575,12 +8597,15 @@ bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) pci_set_drvdata(pdev, dev); - rc = bnx2_request_firmware(bp); - if (rc < 0) - goto error; - + /* + * In-flight DMA from 1st kernel could continue going in kdump kernel. + * New io-page table has been created before bnx2 does reset at open stage. + * We have to wait for the in-flight DMA to complete to avoid it look up + * into the newly created io-page table. + */ + if (is_kdump_kernel()) + bnx2_wait_dma_complete(bp); - bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET); memcpy(dev->dev_addr, bp->mac_addr, ETH_ALEN); dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | @@ -8613,7 +8638,6 @@ bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) return 0; error: - bnx2_release_firmware(bp); pci_iounmap(pdev, bp->regview); pci_release_regions(pdev); pci_disable_device(pdev); diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.c b/drivers/net/ethernet/broadcom/bnxt/bnxt.c index a9f9f3738022..ee1a803aa11a 100644 --- a/drivers/net/ethernet/broadcom/bnxt/bnxt.c +++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.c @@ -1811,6 +1811,9 @@ static int bnxt_busy_poll(struct napi_struct *napi) if (atomic_read(&bp->intr_sem) != 0) return LL_FLUSH_FAILED; + if (!bp->link_info.link_up) + return LL_FLUSH_FAILED; + if (!bnxt_lock_poll(bnapi)) return LL_FLUSH_BUSY; @@ -3210,11 +3213,17 @@ static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port, goto err_out; } - if (tunnel_type & TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN) + switch (tunnel_type) { + case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN: bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id; - - else if (tunnel_type & TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE) + break; + case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE: bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id; + break; + default: + break; + } + err_out: mutex_unlock(&bp->hwrm_cmd_lock); return rc; @@ -4934,6 +4943,10 @@ static void bnxt_del_napi(struct bnxt *bp) napi_hash_del(&bnapi->napi); netif_napi_del(&bnapi->napi); } + /* We called napi_hash_del() before netif_napi_del(), we need + * to respect an RCU grace period before freeing napi structures. + */ + synchronize_net(); } static void bnxt_init_napi(struct bnxt *bp) @@ -6309,6 +6322,7 @@ static int bnxt_setup_tc(struct net_device *dev, u32 handle, __be16 proto, struct tc_to_netdev *ntc) { struct bnxt *bp = netdev_priv(dev); + bool sh = false; u8 tc; if (ntc->type != TC_SETUP_MQPRIO) @@ -6325,12 +6339,11 @@ static int bnxt_setup_tc(struct net_device *dev, u32 handle, __be16 proto, if (netdev_get_num_tc(dev) == tc) return 0; + if (bp->flags & BNXT_FLAG_SHARED_RINGS) + sh = true; + if (tc) { int max_rx_rings, max_tx_rings, rc; - bool sh = false; - - if (bp->flags & BNXT_FLAG_SHARED_RINGS) - sh = true; rc = bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, sh); if (rc || bp->tx_nr_rings_per_tc * tc > max_tx_rings) @@ -6348,7 +6361,8 @@ static int bnxt_setup_tc(struct net_device *dev, u32 handle, __be16 proto, bp->tx_nr_rings = bp->tx_nr_rings_per_tc; netdev_reset_tc(dev); } - bp->cp_nr_rings = max_t(int, bp->tx_nr_rings, bp->rx_nr_rings); + bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : + bp->tx_nr_rings + bp->rx_nr_rings; bp->num_stat_ctxs = bp->cp_nr_rings; if (netif_running(bp->dev)) diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt_sriov.c b/drivers/net/ethernet/broadcom/bnxt/bnxt_sriov.c index ec6cd18842c3..60e2af8678bd 100644 --- a/drivers/net/ethernet/broadcom/bnxt/bnxt_sriov.c +++ b/drivers/net/ethernet/broadcom/bnxt/bnxt_sriov.c @@ -774,8 +774,8 @@ static int bnxt_vf_set_link(struct bnxt *bp, struct bnxt_vf_info *vf) if (vf->flags & BNXT_VF_LINK_UP) { /* if physical link is down, force link up on VF */ - if (phy_qcfg_resp.link == - PORT_PHY_QCFG_RESP_LINK_NO_LINK) { + if (phy_qcfg_resp.link != + PORT_PHY_QCFG_RESP_LINK_LINK) { phy_qcfg_resp.link = PORT_PHY_QCFG_RESP_LINK_LINK; phy_qcfg_resp.link_speed = cpu_to_le16( diff --git a/drivers/net/ethernet/broadcom/genet/bcmgenet.c b/drivers/net/ethernet/broadcom/genet/bcmgenet.c index 4464bc5db934..a4e60e56c14f 100644 --- a/drivers/net/ethernet/broadcom/genet/bcmgenet.c +++ b/drivers/net/ethernet/broadcom/genet/bcmgenet.c @@ -1172,6 +1172,7 @@ static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev, struct bcmgenet_tx_ring *ring) { struct bcmgenet_priv *priv = netdev_priv(dev); + struct device *kdev = &priv->pdev->dev; struct enet_cb *tx_cb_ptr; struct netdev_queue *txq; unsigned int pkts_compl = 0; @@ -1199,13 +1200,13 @@ static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev, if (tx_cb_ptr->skb) { pkts_compl++; bytes_compl += GENET_CB(tx_cb_ptr->skb)->bytes_sent; - dma_unmap_single(&dev->dev, + dma_unmap_single(kdev, dma_unmap_addr(tx_cb_ptr, dma_addr), dma_unmap_len(tx_cb_ptr, dma_len), DMA_TO_DEVICE); bcmgenet_free_cb(tx_cb_ptr); } else if (dma_unmap_addr(tx_cb_ptr, dma_addr)) { - dma_unmap_page(&dev->dev, + dma_unmap_page(kdev, dma_unmap_addr(tx_cb_ptr, dma_addr), dma_unmap_len(tx_cb_ptr, dma_len), DMA_TO_DEVICE); @@ -1775,6 +1776,7 @@ static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv, static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv) { + struct device *kdev = &priv->pdev->dev; struct enet_cb *cb; int i; @@ -1782,7 +1784,7 @@ static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv) cb = &priv->rx_cbs[i]; if (dma_unmap_addr(cb, dma_addr)) { - dma_unmap_single(&priv->dev->dev, + dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr), priv->rx_buf_len, DMA_FROM_DEVICE); dma_unmap_addr_set(cb, dma_addr, 0); diff --git a/drivers/net/ethernet/broadcom/genet/bcmmii.c b/drivers/net/ethernet/broadcom/genet/bcmmii.c index 457c3bc8cfff..e87607621e62 100644 --- a/drivers/net/ethernet/broadcom/genet/bcmmii.c +++ b/drivers/net/ethernet/broadcom/genet/bcmmii.c @@ -542,8 +542,10 @@ static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv) /* Make sure we initialize MoCA PHYs with a link down */ if (phy_mode == PHY_INTERFACE_MODE_MOCA) { phydev = of_phy_find_device(dn); - if (phydev) + if (phydev) { phydev->link = 0; + put_device(&phydev->mdio.dev); + } } return 0; @@ -625,6 +627,7 @@ static int bcmgenet_mii_bus_init(struct bcmgenet_priv *priv) int bcmgenet_mii_init(struct net_device *dev) { struct bcmgenet_priv *priv = netdev_priv(dev); + struct device_node *dn = priv->pdev->dev.of_node; int ret; ret = bcmgenet_mii_alloc(priv); @@ -638,6 +641,8 @@ int bcmgenet_mii_init(struct net_device *dev) return 0; out: + if (of_phy_is_fixed_link(dn)) + of_phy_deregister_fixed_link(dn); of_node_put(priv->phy_dn); mdiobus_unregister(priv->mii_bus); mdiobus_free(priv->mii_bus); @@ -647,7 +652,10 @@ out: void bcmgenet_mii_exit(struct net_device *dev) { struct bcmgenet_priv *priv = netdev_priv(dev); + struct device_node *dn = priv->pdev->dev.of_node; + if (of_phy_is_fixed_link(dn)) + of_phy_deregister_fixed_link(dn); of_node_put(priv->phy_dn); mdiobus_unregister(priv->mii_bus); mdiobus_free(priv->mii_bus); diff --git a/drivers/net/ethernet/brocade/bna/bnad.c b/drivers/net/ethernet/brocade/bna/bnad.c index f9df4b5ae90e..f42f672b0e7e 100644 --- a/drivers/net/ethernet/brocade/bna/bnad.c +++ b/drivers/net/ethernet/brocade/bna/bnad.c @@ -177,6 +177,7 @@ bnad_txcmpl_process(struct bnad *bnad, struct bna_tcb *tcb) return 0; hw_cons = *(tcb->hw_consumer_index); + rmb(); cons = tcb->consumer_index; q_depth = tcb->q_depth; @@ -3094,7 +3095,7 @@ bnad_start_xmit(struct sk_buff *skb, struct net_device *netdev) BNA_QE_INDX_INC(prod, q_depth); tcb->producer_index = prod; - smp_mb(); + wmb(); if (unlikely(!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))) return NETDEV_TX_OK; @@ -3102,7 +3103,6 @@ bnad_start_xmit(struct sk_buff *skb, struct net_device *netdev) skb_tx_timestamp(skb); bna_txq_prod_indx_doorbell(tcb); - smp_mb(); return NETDEV_TX_OK; } diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c index b32444a3ed79..ec09fcece711 100644 --- a/drivers/net/ethernet/cadence/macb.c +++ b/drivers/net/ethernet/cadence/macb.c @@ -975,6 +975,7 @@ static inline void macb_init_rx_ring(struct macb *bp) addr += bp->rx_buffer_size; } bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP); + bp->rx_tail = 0; } static int macb_rx(struct macb *bp, int budget) @@ -1156,6 +1157,7 @@ static irqreturn_t macb_interrupt(int irq, void *dev_id) if (status & MACB_BIT(RXUBR)) { ctrl = macb_readl(bp, NCR); macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE)); + wmb(); macb_writel(bp, NCR, ctrl | MACB_BIT(RE)); if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) @@ -1616,8 +1618,6 @@ static void macb_init_rings(struct macb *bp) bp->queues[0].tx_head = 0; bp->queues[0].tx_tail = 0; bp->queues[0].tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP); - - bp->rx_tail = 0; } static void macb_reset_hw(struct macb *bp) @@ -2673,6 +2673,12 @@ static int at91ether_start_xmit(struct sk_buff *skb, struct net_device *dev) lp->skb_length = skb->len; lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE); + if (dma_mapping_error(NULL, lp->skb_physaddr)) { + dev_kfree_skb_any(skb); + dev->stats.tx_dropped++; + netdev_err(dev, "%s: DMA mapping error\n", __func__); + return NETDEV_TX_OK; + } /* Set address of the data in the Transmit Address register */ macb_writel(lp, TAR, lp->skb_physaddr); @@ -2764,6 +2770,7 @@ static irqreturn_t at91ether_interrupt(int irq, void *dev_id) if (intstatus & MACB_BIT(RXUBR)) { ctl = macb_readl(lp, NCR); macb_writel(lp, NCR, ctl & ~MACB_BIT(RE)); + wmb(); macb_writel(lp, NCR, ctl | MACB_BIT(RE)); } diff --git a/drivers/net/ethernet/cavium/thunder/nic.h b/drivers/net/ethernet/cavium/thunder/nic.h index 30426109711c..86bd93ce2ea3 100644 --- a/drivers/net/ethernet/cavium/thunder/nic.h +++ b/drivers/net/ethernet/cavium/thunder/nic.h @@ -47,7 +47,7 @@ /* Min/Max packet size */ #define NIC_HW_MIN_FRS 64 -#define NIC_HW_MAX_FRS 9200 /* 9216 max packet including FCS */ +#define NIC_HW_MAX_FRS 9190 /* Excluding L2 header and FCS */ /* Max pkinds */ #define NIC_MAX_PKIND 16 @@ -178,11 +178,11 @@ enum tx_stats_reg_offset { struct nicvf_hw_stats { u64 rx_bytes; + u64 rx_frames; u64 rx_ucast_frames; u64 rx_bcast_frames; u64 rx_mcast_frames; - u64 rx_fcs_errors; - u64 rx_l2_errors; + u64 rx_drops; u64 rx_drop_red; u64 rx_drop_red_bytes; u64 rx_drop_overrun; @@ -191,6 +191,19 @@ struct nicvf_hw_stats { u64 rx_drop_mcast; u64 rx_drop_l3_bcast; u64 rx_drop_l3_mcast; + u64 rx_fcs_errors; + u64 rx_l2_errors; + + u64 tx_bytes; + u64 tx_frames; + u64 tx_ucast_frames; + u64 tx_bcast_frames; + u64 tx_mcast_frames; + u64 tx_drops; +}; + +struct nicvf_drv_stats { + /* CQE Rx errs */ u64 rx_bgx_truncated_pkts; u64 rx_jabber_errs; u64 rx_fcs_errs; @@ -216,34 +229,30 @@ struct nicvf_hw_stats { u64 rx_l4_pclp; u64 rx_truncated_pkts; - u64 tx_bytes_ok; - u64 tx_ucast_frames_ok; - u64 tx_bcast_frames_ok; - u64 tx_mcast_frames_ok; - u64 tx_drops; -}; - -struct nicvf_drv_stats { - /* Rx */ - u64 rx_frames_ok; - u64 rx_frames_64; - u64 rx_frames_127; - u64 rx_frames_255; - u64 rx_frames_511; - u64 rx_frames_1023; - u64 rx_frames_1518; - u64 rx_frames_jumbo; - u64 rx_drops; - + /* CQE Tx errs */ + u64 tx_desc_fault; + u64 tx_hdr_cons_err; + u64 tx_subdesc_err; + u64 tx_max_size_exceeded; + u64 tx_imm_size_oflow; + u64 tx_data_seq_err; + u64 tx_mem_seq_err; + u64 tx_lock_viol; + u64 tx_data_fault; + u64 tx_tstmp_conflict; + u64 tx_tstmp_timeout; + u64 tx_mem_fault; + u64 tx_csum_overlap; + u64 tx_csum_overflow; + + /* driver debug stats */ u64 rcv_buffer_alloc_failures; - - /* Tx */ - u64 tx_frames_ok; - u64 tx_drops; u64 tx_tso; u64 tx_timeout; u64 txq_stop; u64 txq_wake; + + struct u64_stats_sync syncp; }; struct nicvf { @@ -282,7 +291,6 @@ struct nicvf { u8 node; u8 cpi_alg; - u16 mtu; bool link_up; u8 duplex; u32 speed; @@ -298,7 +306,7 @@ struct nicvf { /* Stats */ struct nicvf_hw_stats hw_stats; - struct nicvf_drv_stats drv_stats; + struct nicvf_drv_stats __percpu *drv_stats; struct bgx_stats bgx_stats; /* MSI-X */ diff --git a/drivers/net/ethernet/cavium/thunder/nic_main.c b/drivers/net/ethernet/cavium/thunder/nic_main.c index 2bbf4cbf08b2..6677b96e1f3f 100644 --- a/drivers/net/ethernet/cavium/thunder/nic_main.c +++ b/drivers/net/ethernet/cavium/thunder/nic_main.c @@ -11,6 +11,7 @@ #include <linux/pci.h> #include <linux/etherdevice.h> #include <linux/of.h> +#include <linux/if_vlan.h> #include "nic_reg.h" #include "nic.h" @@ -260,18 +261,31 @@ static void nic_get_bgx_stats(struct nicpf *nic, struct bgx_stats_msg *bgx) /* Update hardware min/max frame size */ static int nic_update_hw_frs(struct nicpf *nic, int new_frs, int vf) { - if ((new_frs > NIC_HW_MAX_FRS) || (new_frs < NIC_HW_MIN_FRS)) { - dev_err(&nic->pdev->dev, - "Invalid MTU setting from VF%d rejected, should be between %d and %d\n", - vf, NIC_HW_MIN_FRS, NIC_HW_MAX_FRS); + int bgx, lmac, lmac_cnt; + u64 lmac_credits; + + if ((new_frs > NIC_HW_MAX_FRS) || (new_frs < NIC_HW_MIN_FRS)) return 1; - } - new_frs += ETH_HLEN; - if (new_frs <= nic->pkind.maxlen) - return 0; - nic->pkind.maxlen = new_frs; - nic_reg_write(nic, NIC_PF_PKIND_0_15_CFG, *(u64 *)&nic->pkind); + bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); + lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); + lmac += bgx * MAX_LMAC_PER_BGX; + + new_frs += VLAN_ETH_HLEN + ETH_FCS_LEN + 4; + + /* Update corresponding LMAC credits */ + lmac_cnt = bgx_get_lmac_count(nic->node, bgx); + lmac_credits = nic_reg_read(nic, NIC_PF_LMAC_0_7_CREDIT + (lmac * 8)); + lmac_credits &= ~(0xFFFFFULL << 12); + lmac_credits |= (((((48 * 1024) / lmac_cnt) - new_frs) / 16) << 12); + nic_reg_write(nic, NIC_PF_LMAC_0_7_CREDIT + (lmac * 8), lmac_credits); + + /* Enforce MTU in HW + * This config is supported only from 88xx pass 2.0 onwards. + */ + if (!pass1_silicon(nic->pdev)) + nic_reg_write(nic, + NIC_PF_LMAC_0_7_CFG2 + (lmac * 8), new_frs); return 0; } @@ -464,7 +478,7 @@ static int nic_init_hw(struct nicpf *nic) /* PKIND configuration */ nic->pkind.minlen = 0; - nic->pkind.maxlen = NIC_HW_MAX_FRS + ETH_HLEN; + nic->pkind.maxlen = NIC_HW_MAX_FRS + VLAN_ETH_HLEN + ETH_FCS_LEN + 4; nic->pkind.lenerr_en = 1; nic->pkind.rx_hdr = 0; nic->pkind.hdr_sl = 0; @@ -837,6 +851,7 @@ static int nic_reset_stat_counters(struct nicpf *nic, nic_reg_write(nic, reg_addr, 0); } } + return 0; } diff --git a/drivers/net/ethernet/cavium/thunder/nic_reg.h b/drivers/net/ethernet/cavium/thunder/nic_reg.h index edf779f5a227..80d46337cf29 100644 --- a/drivers/net/ethernet/cavium/thunder/nic_reg.h +++ b/drivers/net/ethernet/cavium/thunder/nic_reg.h @@ -106,6 +106,7 @@ #define NIC_PF_MPI_0_2047_CFG (0x210000) #define NIC_PF_RSSI_0_4097_RQ (0x220000) #define NIC_PF_LMAC_0_7_CFG (0x240000) +#define NIC_PF_LMAC_0_7_CFG2 (0x240100) #define NIC_PF_LMAC_0_7_SW_XOFF (0x242000) #define NIC_PF_LMAC_0_7_CREDIT (0x244000) #define NIC_PF_CHAN_0_255_TX_CFG (0x400000) diff --git a/drivers/net/ethernet/cavium/thunder/nicvf_ethtool.c b/drivers/net/ethernet/cavium/thunder/nicvf_ethtool.c index ad4fddb55421..432bf6be57cb 100644 --- a/drivers/net/ethernet/cavium/thunder/nicvf_ethtool.c +++ b/drivers/net/ethernet/cavium/thunder/nicvf_ethtool.c @@ -36,11 +36,11 @@ struct nicvf_stat { static const struct nicvf_stat nicvf_hw_stats[] = { NICVF_HW_STAT(rx_bytes), + NICVF_HW_STAT(rx_frames), NICVF_HW_STAT(rx_ucast_frames), NICVF_HW_STAT(rx_bcast_frames), NICVF_HW_STAT(rx_mcast_frames), - NICVF_HW_STAT(rx_fcs_errors), - NICVF_HW_STAT(rx_l2_errors), + NICVF_HW_STAT(rx_drops), NICVF_HW_STAT(rx_drop_red), NICVF_HW_STAT(rx_drop_red_bytes), NICVF_HW_STAT(rx_drop_overrun), @@ -49,50 +49,59 @@ static const struct nicvf_stat nicvf_hw_stats[] = { NICVF_HW_STAT(rx_drop_mcast), NICVF_HW_STAT(rx_drop_l3_bcast), NICVF_HW_STAT(rx_drop_l3_mcast), - NICVF_HW_STAT(rx_bgx_truncated_pkts), - NICVF_HW_STAT(rx_jabber_errs), - NICVF_HW_STAT(rx_fcs_errs), - NICVF_HW_STAT(rx_bgx_errs), - NICVF_HW_STAT(rx_prel2_errs), - NICVF_HW_STAT(rx_l2_hdr_malformed), - NICVF_HW_STAT(rx_oversize), - NICVF_HW_STAT(rx_undersize), - NICVF_HW_STAT(rx_l2_len_mismatch), - NICVF_HW_STAT(rx_l2_pclp), - NICVF_HW_STAT(rx_ip_ver_errs), - NICVF_HW_STAT(rx_ip_csum_errs), - NICVF_HW_STAT(rx_ip_hdr_malformed), - NICVF_HW_STAT(rx_ip_payload_malformed), - NICVF_HW_STAT(rx_ip_ttl_errs), - NICVF_HW_STAT(rx_l3_pclp), - NICVF_HW_STAT(rx_l4_malformed), - NICVF_HW_STAT(rx_l4_csum_errs), - NICVF_HW_STAT(rx_udp_len_errs), - NICVF_HW_STAT(rx_l4_port_errs), - NICVF_HW_STAT(rx_tcp_flag_errs), - NICVF_HW_STAT(rx_tcp_offset_errs), - NICVF_HW_STAT(rx_l4_pclp), - NICVF_HW_STAT(rx_truncated_pkts), - NICVF_HW_STAT(tx_bytes_ok), - NICVF_HW_STAT(tx_ucast_frames_ok), - NICVF_HW_STAT(tx_bcast_frames_ok), - NICVF_HW_STAT(tx_mcast_frames_ok), + NICVF_HW_STAT(rx_fcs_errors), + NICVF_HW_STAT(rx_l2_errors), + NICVF_HW_STAT(tx_bytes), + NICVF_HW_STAT(tx_frames), + NICVF_HW_STAT(tx_ucast_frames), + NICVF_HW_STAT(tx_bcast_frames), + NICVF_HW_STAT(tx_mcast_frames), + NICVF_HW_STAT(tx_drops), }; static const struct nicvf_stat nicvf_drv_stats[] = { - NICVF_DRV_STAT(rx_frames_ok), - NICVF_DRV_STAT(rx_frames_64), - NICVF_DRV_STAT(rx_frames_127), - NICVF_DRV_STAT(rx_frames_255), - NICVF_DRV_STAT(rx_frames_511), - NICVF_DRV_STAT(rx_frames_1023), - NICVF_DRV_STAT(rx_frames_1518), - NICVF_DRV_STAT(rx_frames_jumbo), - NICVF_DRV_STAT(rx_drops), + NICVF_DRV_STAT(rx_bgx_truncated_pkts), + NICVF_DRV_STAT(rx_jabber_errs), + NICVF_DRV_STAT(rx_fcs_errs), + NICVF_DRV_STAT(rx_bgx_errs), + NICVF_DRV_STAT(rx_prel2_errs), + NICVF_DRV_STAT(rx_l2_hdr_malformed), + NICVF_DRV_STAT(rx_oversize), + NICVF_DRV_STAT(rx_undersize), + NICVF_DRV_STAT(rx_l2_len_mismatch), + NICVF_DRV_STAT(rx_l2_pclp), + NICVF_DRV_STAT(rx_ip_ver_errs), + NICVF_DRV_STAT(rx_ip_csum_errs), + NICVF_DRV_STAT(rx_ip_hdr_malformed), + NICVF_DRV_STAT(rx_ip_payload_malformed), + NICVF_DRV_STAT(rx_ip_ttl_errs), + NICVF_DRV_STAT(rx_l3_pclp), + NICVF_DRV_STAT(rx_l4_malformed), + NICVF_DRV_STAT(rx_l4_csum_errs), + NICVF_DRV_STAT(rx_udp_len_errs), + NICVF_DRV_STAT(rx_l4_port_errs), + NICVF_DRV_STAT(rx_tcp_flag_errs), + NICVF_DRV_STAT(rx_tcp_offset_errs), + NICVF_DRV_STAT(rx_l4_pclp), + NICVF_DRV_STAT(rx_truncated_pkts), + + NICVF_DRV_STAT(tx_desc_fault), + NICVF_DRV_STAT(tx_hdr_cons_err), + NICVF_DRV_STAT(tx_subdesc_err), + NICVF_DRV_STAT(tx_max_size_exceeded), + NICVF_DRV_STAT(tx_imm_size_oflow), + NICVF_DRV_STAT(tx_data_seq_err), + NICVF_DRV_STAT(tx_mem_seq_err), + NICVF_DRV_STAT(tx_lock_viol), + NICVF_DRV_STAT(tx_data_fault), + NICVF_DRV_STAT(tx_tstmp_conflict), + NICVF_DRV_STAT(tx_tstmp_timeout), + NICVF_DRV_STAT(tx_mem_fault), + NICVF_DRV_STAT(tx_csum_overlap), + NICVF_DRV_STAT(tx_csum_overflow), + NICVF_DRV_STAT(rcv_buffer_alloc_failures), - NICVF_DRV_STAT(tx_frames_ok), NICVF_DRV_STAT(tx_tso), - NICVF_DRV_STAT(tx_drops), NICVF_DRV_STAT(tx_timeout), NICVF_DRV_STAT(txq_stop), NICVF_DRV_STAT(txq_wake), @@ -278,8 +287,8 @@ static void nicvf_get_ethtool_stats(struct net_device *netdev, struct ethtool_stats *stats, u64 *data) { struct nicvf *nic = netdev_priv(netdev); - int stat; - int sqs; + int stat, tmp_stats; + int sqs, cpu; nicvf_update_stats(nic); @@ -289,9 +298,13 @@ static void nicvf_get_ethtool_stats(struct net_device *netdev, for (stat = 0; stat < nicvf_n_hw_stats; stat++) *(data++) = ((u64 *)&nic->hw_stats) [nicvf_hw_stats[stat].index]; - for (stat = 0; stat < nicvf_n_drv_stats; stat++) - *(data++) = ((u64 *)&nic->drv_stats) - [nicvf_drv_stats[stat].index]; + for (stat = 0; stat < nicvf_n_drv_stats; stat++) { + tmp_stats = 0; + for_each_possible_cpu(cpu) + tmp_stats += ((u64 *)per_cpu_ptr(nic->drv_stats, cpu)) + [nicvf_drv_stats[stat].index]; + *(data++) = tmp_stats; + } nicvf_get_qset_stats(nic, stats, &data); diff --git a/drivers/net/ethernet/cavium/thunder/nicvf_main.c b/drivers/net/ethernet/cavium/thunder/nicvf_main.c index 45a13f718863..8a37012c9c89 100644 --- a/drivers/net/ethernet/cavium/thunder/nicvf_main.c +++ b/drivers/net/ethernet/cavium/thunder/nicvf_main.c @@ -69,25 +69,6 @@ static inline u8 nicvf_netdev_qidx(struct nicvf *nic, u8 qidx) return qidx; } -static inline void nicvf_set_rx_frame_cnt(struct nicvf *nic, - struct sk_buff *skb) -{ - if (skb->len <= 64) - nic->drv_stats.rx_frames_64++; - else if (skb->len <= 127) - nic->drv_stats.rx_frames_127++; - else if (skb->len <= 255) - nic->drv_stats.rx_frames_255++; - else if (skb->len <= 511) - nic->drv_stats.rx_frames_511++; - else if (skb->len <= 1023) - nic->drv_stats.rx_frames_1023++; - else if (skb->len <= 1518) - nic->drv_stats.rx_frames_1518++; - else - nic->drv_stats.rx_frames_jumbo++; -} - /* The Cavium ThunderX network controller can *only* be found in SoCs * containing the ThunderX ARM64 CPU implementation. All accesses to the device * registers on this platform are implicitly strongly ordered with respect @@ -492,9 +473,6 @@ int nicvf_set_real_num_queues(struct net_device *netdev, static int nicvf_init_resources(struct nicvf *nic) { int err; - union nic_mbx mbx = {}; - - mbx.msg.msg = NIC_MBOX_MSG_CFG_DONE; /* Enable Qset */ nicvf_qset_config(nic, true); @@ -507,14 +485,10 @@ static int nicvf_init_resources(struct nicvf *nic) return err; } - /* Send VF config done msg to PF */ - nicvf_write_to_mbx(nic, &mbx); - return 0; } static void nicvf_snd_pkt_handler(struct net_device *netdev, - struct cmp_queue *cq, struct cqe_send_t *cqe_tx, int cqe_type, int budget, unsigned int *tx_pkts, unsigned int *tx_bytes) @@ -536,7 +510,7 @@ static void nicvf_snd_pkt_handler(struct net_device *netdev, __func__, cqe_tx->sq_qs, cqe_tx->sq_idx, cqe_tx->sqe_ptr, hdr->subdesc_cnt); - nicvf_check_cqe_tx_errs(nic, cq, cqe_tx); + nicvf_check_cqe_tx_errs(nic, cqe_tx); skb = (struct sk_buff *)sq->skbuff[cqe_tx->sqe_ptr]; if (skb) { /* Check for dummy descriptor used for HW TSO offload on 88xx */ @@ -630,8 +604,6 @@ static void nicvf_rcv_pkt_handler(struct net_device *netdev, return; } - nicvf_set_rx_frame_cnt(nic, skb); - nicvf_set_rxhash(netdev, cqe_rx, skb); skb_record_rx_queue(skb, rq_idx); @@ -703,7 +675,7 @@ loop: work_done++; break; case CQE_TYPE_SEND: - nicvf_snd_pkt_handler(netdev, cq, + nicvf_snd_pkt_handler(netdev, (void *)cq_desc, CQE_TYPE_SEND, budget, &tx_pkts, &tx_bytes); tx_done++; @@ -740,7 +712,7 @@ done: nic = nic->pnicvf; if (netif_tx_queue_stopped(txq) && netif_carrier_ok(netdev)) { netif_tx_start_queue(txq); - nic->drv_stats.txq_wake++; + this_cpu_inc(nic->drv_stats->txq_wake); if (netif_msg_tx_err(nic)) netdev_warn(netdev, "%s: Transmit queue wakeup SQ%d\n", @@ -1084,7 +1056,7 @@ static netdev_tx_t nicvf_xmit(struct sk_buff *skb, struct net_device *netdev) if (!netif_tx_queue_stopped(txq) && !nicvf_sq_append_skb(nic, skb)) { netif_tx_stop_queue(txq); - nic->drv_stats.txq_stop++; + this_cpu_inc(nic->drv_stats->txq_stop); if (netif_msg_tx_err(nic)) netdev_warn(netdev, "%s: Transmit ring full, stopping SQ%d\n", @@ -1189,14 +1161,24 @@ int nicvf_stop(struct net_device *netdev) return 0; } +static int nicvf_update_hw_max_frs(struct nicvf *nic, int mtu) +{ + union nic_mbx mbx = {}; + + mbx.frs.msg = NIC_MBOX_MSG_SET_MAX_FRS; + mbx.frs.max_frs = mtu; + mbx.frs.vf_id = nic->vf_id; + + return nicvf_send_msg_to_pf(nic, &mbx); +} + int nicvf_open(struct net_device *netdev) { - int err, qidx; + int cpu, err, qidx; struct nicvf *nic = netdev_priv(netdev); struct queue_set *qs = nic->qs; struct nicvf_cq_poll *cq_poll = NULL; - - nic->mtu = netdev->mtu; + union nic_mbx mbx = {}; netif_carrier_off(netdev); @@ -1248,9 +1230,17 @@ int nicvf_open(struct net_device *netdev) if (nic->sqs_mode) nicvf_get_primary_vf_struct(nic); - /* Configure receive side scaling */ - if (!nic->sqs_mode) + /* Configure receive side scaling and MTU */ + if (!nic->sqs_mode) { nicvf_rss_init(nic); + if (nicvf_update_hw_max_frs(nic, netdev->mtu)) + goto cleanup; + + /* Clear percpu stats */ + for_each_possible_cpu(cpu) + memset(per_cpu_ptr(nic->drv_stats, cpu), 0, + sizeof(struct nicvf_drv_stats)); + } err = nicvf_register_interrupts(nic); if (err) @@ -1276,8 +1266,9 @@ int nicvf_open(struct net_device *netdev) for (qidx = 0; qidx < qs->rbdr_cnt; qidx++) nicvf_enable_intr(nic, NICVF_INTR_RBDR, qidx); - nic->drv_stats.txq_stop = 0; - nic->drv_stats.txq_wake = 0; + /* Send VF config done msg to PF */ + mbx.msg.msg = NIC_MBOX_MSG_CFG_DONE; + nicvf_write_to_mbx(nic, &mbx); return 0; cleanup: @@ -1297,17 +1288,6 @@ napi_del: return err; } -static int nicvf_update_hw_max_frs(struct nicvf *nic, int mtu) -{ - union nic_mbx mbx = {}; - - mbx.frs.msg = NIC_MBOX_MSG_SET_MAX_FRS; - mbx.frs.max_frs = mtu; - mbx.frs.vf_id = nic->vf_id; - - return nicvf_send_msg_to_pf(nic, &mbx); -} - static int nicvf_change_mtu(struct net_device *netdev, int new_mtu) { struct nicvf *nic = netdev_priv(netdev); @@ -1318,10 +1298,13 @@ static int nicvf_change_mtu(struct net_device *netdev, int new_mtu) if (new_mtu < NIC_HW_MIN_FRS) return -EINVAL; + netdev->mtu = new_mtu; + + if (!netif_running(netdev)) + return 0; + if (nicvf_update_hw_max_frs(nic, new_mtu)) return -EINVAL; - netdev->mtu = new_mtu; - nic->mtu = new_mtu; return 0; } @@ -1379,9 +1362,10 @@ void nicvf_update_lmac_stats(struct nicvf *nic) void nicvf_update_stats(struct nicvf *nic) { - int qidx; + int qidx, cpu; + u64 tmp_stats = 0; struct nicvf_hw_stats *stats = &nic->hw_stats; - struct nicvf_drv_stats *drv_stats = &nic->drv_stats; + struct nicvf_drv_stats *drv_stats; struct queue_set *qs = nic->qs; #define GET_RX_STATS(reg) \ @@ -1404,21 +1388,33 @@ void nicvf_update_stats(struct nicvf *nic) stats->rx_drop_l3_bcast = GET_RX_STATS(RX_DRP_L3BCAST); stats->rx_drop_l3_mcast = GET_RX_STATS(RX_DRP_L3MCAST); - stats->tx_bytes_ok = GET_TX_STATS(TX_OCTS); - stats->tx_ucast_frames_ok = GET_TX_STATS(TX_UCAST); - stats->tx_bcast_frames_ok = GET_TX_STATS(TX_BCAST); - stats->tx_mcast_frames_ok = GET_TX_STATS(TX_MCAST); + stats->tx_bytes = GET_TX_STATS(TX_OCTS); + stats->tx_ucast_frames = GET_TX_STATS(TX_UCAST); + stats->tx_bcast_frames = GET_TX_STATS(TX_BCAST); + stats->tx_mcast_frames = GET_TX_STATS(TX_MCAST); stats->tx_drops = GET_TX_STATS(TX_DROP); - drv_stats->tx_frames_ok = stats->tx_ucast_frames_ok + - stats->tx_bcast_frames_ok + - stats->tx_mcast_frames_ok; - drv_stats->rx_frames_ok = stats->rx_ucast_frames + - stats->rx_bcast_frames + - stats->rx_mcast_frames; - drv_stats->rx_drops = stats->rx_drop_red + - stats->rx_drop_overrun; - drv_stats->tx_drops = stats->tx_drops; + /* On T88 pass 2.0, the dummy SQE added for TSO notification + * via CQE has 'dont_send' set. Hence HW drops the pkt pointed + * pointed by dummy SQE and results in tx_drops counter being + * incremented. Subtracting it from tx_tso counter will give + * exact tx_drops counter. + */ + if (nic->t88 && nic->hw_tso) { + for_each_possible_cpu(cpu) { + drv_stats = per_cpu_ptr(nic->drv_stats, cpu); + tmp_stats += drv_stats->tx_tso; + } + stats->tx_drops = tmp_stats - stats->tx_drops; + } + stats->tx_frames = stats->tx_ucast_frames + + stats->tx_bcast_frames + + stats->tx_mcast_frames; + stats->rx_frames = stats->rx_ucast_frames + + stats->rx_bcast_frames + + stats->rx_mcast_frames; + stats->rx_drops = stats->rx_drop_red + + stats->rx_drop_overrun; /* Update RQ and SQ stats */ for (qidx = 0; qidx < qs->rq_cnt; qidx++) @@ -1432,18 +1428,17 @@ static struct rtnl_link_stats64 *nicvf_get_stats64(struct net_device *netdev, { struct nicvf *nic = netdev_priv(netdev); struct nicvf_hw_stats *hw_stats = &nic->hw_stats; - struct nicvf_drv_stats *drv_stats = &nic->drv_stats; nicvf_update_stats(nic); stats->rx_bytes = hw_stats->rx_bytes; - stats->rx_packets = drv_stats->rx_frames_ok; - stats->rx_dropped = drv_stats->rx_drops; + stats->rx_packets = hw_stats->rx_frames; + stats->rx_dropped = hw_stats->rx_drops; stats->multicast = hw_stats->rx_mcast_frames; - stats->tx_bytes = hw_stats->tx_bytes_ok; - stats->tx_packets = drv_stats->tx_frames_ok; - stats->tx_dropped = drv_stats->tx_drops; + stats->tx_bytes = hw_stats->tx_bytes; + stats->tx_packets = hw_stats->tx_frames; + stats->tx_dropped = hw_stats->tx_drops; return stats; } @@ -1456,7 +1451,7 @@ static void nicvf_tx_timeout(struct net_device *dev) netdev_warn(dev, "%s: Transmit timed out, resetting\n", dev->name); - nic->drv_stats.tx_timeout++; + this_cpu_inc(nic->drv_stats->tx_timeout); schedule_work(&nic->reset_task); } @@ -1590,6 +1585,12 @@ static int nicvf_probe(struct pci_dev *pdev, const struct pci_device_id *ent) goto err_free_netdev; } + nic->drv_stats = netdev_alloc_pcpu_stats(struct nicvf_drv_stats); + if (!nic->drv_stats) { + err = -ENOMEM; + goto err_free_netdev; + } + err = nicvf_set_qset_resources(nic); if (err) goto err_free_netdev; @@ -1648,6 +1649,8 @@ err_unregister_interrupts: nicvf_unregister_interrupts(nic); err_free_netdev: pci_set_drvdata(pdev, NULL); + if (nic->drv_stats) + free_percpu(nic->drv_stats); free_netdev(netdev); err_release_regions: pci_release_regions(pdev); @@ -1675,6 +1678,8 @@ static void nicvf_remove(struct pci_dev *pdev) unregister_netdev(pnetdev); nicvf_unregister_interrupts(nic); pci_set_drvdata(pdev, NULL); + if (nic->drv_stats) + free_percpu(nic->drv_stats); free_netdev(netdev); pci_release_regions(pdev); pci_disable_device(pdev); diff --git a/drivers/net/ethernet/cavium/thunder/nicvf_queues.c b/drivers/net/ethernet/cavium/thunder/nicvf_queues.c index a4fc50155881..747ef0882976 100644 --- a/drivers/net/ethernet/cavium/thunder/nicvf_queues.c +++ b/drivers/net/ethernet/cavium/thunder/nicvf_queues.c @@ -104,7 +104,8 @@ static inline int nicvf_alloc_rcv_buffer(struct nicvf *nic, gfp_t gfp, nic->rb_page = alloc_pages(gfp | __GFP_COMP | __GFP_NOWARN, order); if (!nic->rb_page) { - nic->drv_stats.rcv_buffer_alloc_failures++; + this_cpu_inc(nic->pnicvf->drv_stats-> + rcv_buffer_alloc_failures); return -ENOMEM; } nic->rb_page_offset = 0; @@ -270,7 +271,8 @@ refill: rbdr_idx, new_rb); next_rbdr: /* Re-enable RBDR interrupts only if buffer allocation is success */ - if (!nic->rb_alloc_fail && rbdr->enable) + if (!nic->rb_alloc_fail && rbdr->enable && + netif_running(nic->pnicvf->netdev)) nicvf_enable_intr(nic, NICVF_INTR_RBDR, rbdr_idx); if (rbdr_idx) @@ -361,6 +363,8 @@ static int nicvf_init_snd_queue(struct nicvf *nic, static void nicvf_free_snd_queue(struct nicvf *nic, struct snd_queue *sq) { + struct sk_buff *skb; + if (!sq) return; if (!sq->dmem.base) @@ -371,6 +375,15 @@ static void nicvf_free_snd_queue(struct nicvf *nic, struct snd_queue *sq) sq->dmem.q_len * TSO_HEADER_SIZE, sq->tso_hdrs, sq->tso_hdrs_phys); + /* Free pending skbs in the queue */ + smp_rmb(); + while (sq->head != sq->tail) { + skb = (struct sk_buff *)sq->skbuff[sq->head]; + if (skb) + dev_kfree_skb_any(skb); + sq->head++; + sq->head &= (sq->dmem.q_len - 1); + } kfree(sq->skbuff); nicvf_free_q_desc_mem(nic, &sq->dmem); } @@ -483,9 +496,12 @@ static void nicvf_reset_rcv_queue_stats(struct nicvf *nic) { union nic_mbx mbx = {}; - /* Reset all RXQ's stats */ + /* Reset all RQ/SQ and VF stats */ mbx.reset_stat.msg = NIC_MBOX_MSG_RESET_STAT_COUNTER; + mbx.reset_stat.rx_stat_mask = 0x3FFF; + mbx.reset_stat.tx_stat_mask = 0x1F; mbx.reset_stat.rq_stat_mask = 0xFFFF; + mbx.reset_stat.sq_stat_mask = 0xFFFF; nicvf_send_msg_to_pf(nic, &mbx); } @@ -538,9 +554,12 @@ static void nicvf_rcv_queue_config(struct nicvf *nic, struct queue_set *qs, mbx.rq.cfg = (1ULL << 62) | (RQ_CQ_DROP << 8); nicvf_send_msg_to_pf(nic, &mbx); - nicvf_queue_reg_write(nic, NIC_QSET_RQ_GEN_CFG, 0, 0x00); - if (!nic->sqs_mode) + if (!nic->sqs_mode && (qidx == 0)) { + /* Enable checking L3/L4 length and TCP/UDP checksums */ + nicvf_queue_reg_write(nic, NIC_QSET_RQ_GEN_CFG, 0, + (BIT(24) | BIT(23) | BIT(21))); nicvf_config_vlan_stripping(nic, nic->netdev->features); + } /* Enable Receive queue */ memset(&rq_cfg, 0, sizeof(struct rq_cfg)); @@ -1029,7 +1048,7 @@ nicvf_sq_add_hdr_subdesc(struct nicvf *nic, struct snd_queue *sq, int qentry, hdr->tso_max_paysize = skb_shinfo(skb)->gso_size; /* For non-tunneled pkts, point this to L2 ethertype */ hdr->inner_l3_offset = skb_network_offset(skb) - 2; - nic->drv_stats.tx_tso++; + this_cpu_inc(nic->pnicvf->drv_stats->tx_tso); } } @@ -1161,7 +1180,7 @@ static int nicvf_sq_append_tso(struct nicvf *nic, struct snd_queue *sq, nicvf_sq_doorbell(nic, skb, sq_num, desc_cnt); - nic->drv_stats.tx_tso++; + this_cpu_inc(nic->pnicvf->drv_stats->tx_tso); return 1; } @@ -1422,8 +1441,6 @@ void nicvf_update_sq_stats(struct nicvf *nic, int sq_idx) /* Check for errors in the receive cmp.queue entry */ int nicvf_check_cqe_rx_errs(struct nicvf *nic, struct cqe_rx_t *cqe_rx) { - struct nicvf_hw_stats *stats = &nic->hw_stats; - if (!cqe_rx->err_level && !cqe_rx->err_opcode) return 0; @@ -1435,76 +1452,76 @@ int nicvf_check_cqe_rx_errs(struct nicvf *nic, struct cqe_rx_t *cqe_rx) switch (cqe_rx->err_opcode) { case CQ_RX_ERROP_RE_PARTIAL: - stats->rx_bgx_truncated_pkts++; + this_cpu_inc(nic->drv_stats->rx_bgx_truncated_pkts); break; case CQ_RX_ERROP_RE_JABBER: - stats->rx_jabber_errs++; + this_cpu_inc(nic->drv_stats->rx_jabber_errs); break; case CQ_RX_ERROP_RE_FCS: - stats->rx_fcs_errs++; + this_cpu_inc(nic->drv_stats->rx_fcs_errs); break; case CQ_RX_ERROP_RE_RX_CTL: - stats->rx_bgx_errs++; + this_cpu_inc(nic->drv_stats->rx_bgx_errs); break; case CQ_RX_ERROP_PREL2_ERR: - stats->rx_prel2_errs++; + this_cpu_inc(nic->drv_stats->rx_prel2_errs); break; case CQ_RX_ERROP_L2_MAL: - stats->rx_l2_hdr_malformed++; + this_cpu_inc(nic->drv_stats->rx_l2_hdr_malformed); break; case CQ_RX_ERROP_L2_OVERSIZE: - stats->rx_oversize++; + this_cpu_inc(nic->drv_stats->rx_oversize); break; case CQ_RX_ERROP_L2_UNDERSIZE: - stats->rx_undersize++; + this_cpu_inc(nic->drv_stats->rx_undersize); break; case CQ_RX_ERROP_L2_LENMISM: - stats->rx_l2_len_mismatch++; + this_cpu_inc(nic->drv_stats->rx_l2_len_mismatch); break; case CQ_RX_ERROP_L2_PCLP: - stats->rx_l2_pclp++; + this_cpu_inc(nic->drv_stats->rx_l2_pclp); break; case CQ_RX_ERROP_IP_NOT: - stats->rx_ip_ver_errs++; + this_cpu_inc(nic->drv_stats->rx_ip_ver_errs); break; case CQ_RX_ERROP_IP_CSUM_ERR: - stats->rx_ip_csum_errs++; + this_cpu_inc(nic->drv_stats->rx_ip_csum_errs); break; case CQ_RX_ERROP_IP_MAL: - stats->rx_ip_hdr_malformed++; + this_cpu_inc(nic->drv_stats->rx_ip_hdr_malformed); break; case CQ_RX_ERROP_IP_MALD: - stats->rx_ip_payload_malformed++; + this_cpu_inc(nic->drv_stats->rx_ip_payload_malformed); break; case CQ_RX_ERROP_IP_HOP: - stats->rx_ip_ttl_errs++; + this_cpu_inc(nic->drv_stats->rx_ip_ttl_errs); break; case CQ_RX_ERROP_L3_PCLP: - stats->rx_l3_pclp++; + this_cpu_inc(nic->drv_stats->rx_l3_pclp); break; case CQ_RX_ERROP_L4_MAL: - stats->rx_l4_malformed++; + this_cpu_inc(nic->drv_stats->rx_l4_malformed); break; case CQ_RX_ERROP_L4_CHK: - stats->rx_l4_csum_errs++; + this_cpu_inc(nic->drv_stats->rx_l4_csum_errs); break; case CQ_RX_ERROP_UDP_LEN: - stats->rx_udp_len_errs++; + this_cpu_inc(nic->drv_stats->rx_udp_len_errs); break; case CQ_RX_ERROP_L4_PORT: - stats->rx_l4_port_errs++; + this_cpu_inc(nic->drv_stats->rx_l4_port_errs); break; case CQ_RX_ERROP_TCP_FLAG: - stats->rx_tcp_flag_errs++; + this_cpu_inc(nic->drv_stats->rx_tcp_flag_errs); break; case CQ_RX_ERROP_TCP_OFFSET: - stats->rx_tcp_offset_errs++; + this_cpu_inc(nic->drv_stats->rx_tcp_offset_errs); break; case CQ_RX_ERROP_L4_PCLP: - stats->rx_l4_pclp++; + this_cpu_inc(nic->drv_stats->rx_l4_pclp); break; case CQ_RX_ERROP_RBDR_TRUNC: - stats->rx_truncated_pkts++; + this_cpu_inc(nic->drv_stats->rx_truncated_pkts); break; } @@ -1512,53 +1529,52 @@ int nicvf_check_cqe_rx_errs(struct nicvf *nic, struct cqe_rx_t *cqe_rx) } /* Check for errors in the send cmp.queue entry */ -int nicvf_check_cqe_tx_errs(struct nicvf *nic, - struct cmp_queue *cq, struct cqe_send_t *cqe_tx) +int nicvf_check_cqe_tx_errs(struct nicvf *nic, struct cqe_send_t *cqe_tx) { - struct cmp_queue_stats *stats = &cq->stats; - switch (cqe_tx->send_status) { case CQ_TX_ERROP_GOOD: - stats->tx.good++; return 0; case CQ_TX_ERROP_DESC_FAULT: - stats->tx.desc_fault++; + this_cpu_inc(nic->drv_stats->tx_desc_fault); break; case CQ_TX_ERROP_HDR_CONS_ERR: - stats->tx.hdr_cons_err++; + this_cpu_inc(nic->drv_stats->tx_hdr_cons_err); break; case CQ_TX_ERROP_SUBDC_ERR: - stats->tx.subdesc_err++; + this_cpu_inc(nic->drv_stats->tx_subdesc_err); + break; + case CQ_TX_ERROP_MAX_SIZE_VIOL: + this_cpu_inc(nic->drv_stats->tx_max_size_exceeded); break; case CQ_TX_ERROP_IMM_SIZE_OFLOW: - stats->tx.imm_size_oflow++; + this_cpu_inc(nic->drv_stats->tx_imm_size_oflow); break; case CQ_TX_ERROP_DATA_SEQUENCE_ERR: - stats->tx.data_seq_err++; + this_cpu_inc(nic->drv_stats->tx_data_seq_err); break; case CQ_TX_ERROP_MEM_SEQUENCE_ERR: - stats->tx.mem_seq_err++; + this_cpu_inc(nic->drv_stats->tx_mem_seq_err); break; case CQ_TX_ERROP_LOCK_VIOL: - stats->tx.lock_viol++; + this_cpu_inc(nic->drv_stats->tx_lock_viol); break; case CQ_TX_ERROP_DATA_FAULT: - stats->tx.data_fault++; + this_cpu_inc(nic->drv_stats->tx_data_fault); break; case CQ_TX_ERROP_TSTMP_CONFLICT: - stats->tx.tstmp_conflict++; + this_cpu_inc(nic->drv_stats->tx_tstmp_conflict); break; case CQ_TX_ERROP_TSTMP_TIMEOUT: - stats->tx.tstmp_timeout++; + this_cpu_inc(nic->drv_stats->tx_tstmp_timeout); break; case CQ_TX_ERROP_MEM_FAULT: - stats->tx.mem_fault++; + this_cpu_inc(nic->drv_stats->tx_mem_fault); break; case CQ_TX_ERROP_CK_OVERLAP: - stats->tx.csum_overlap++; + this_cpu_inc(nic->drv_stats->tx_csum_overlap); break; case CQ_TX_ERROP_CK_OFLOW: - stats->tx.csum_overflow++; + this_cpu_inc(nic->drv_stats->tx_csum_overflow); break; } diff --git a/drivers/net/ethernet/cavium/thunder/nicvf_queues.h b/drivers/net/ethernet/cavium/thunder/nicvf_queues.h index 869f3386028b..2e3c940c1093 100644 --- a/drivers/net/ethernet/cavium/thunder/nicvf_queues.h +++ b/drivers/net/ethernet/cavium/thunder/nicvf_queues.h @@ -158,6 +158,7 @@ enum CQ_TX_ERROP_E { CQ_TX_ERROP_DESC_FAULT = 0x10, CQ_TX_ERROP_HDR_CONS_ERR = 0x11, CQ_TX_ERROP_SUBDC_ERR = 0x12, + CQ_TX_ERROP_MAX_SIZE_VIOL = 0x13, CQ_TX_ERROP_IMM_SIZE_OFLOW = 0x80, CQ_TX_ERROP_DATA_SEQUENCE_ERR = 0x81, CQ_TX_ERROP_MEM_SEQUENCE_ERR = 0x82, @@ -171,25 +172,6 @@ enum CQ_TX_ERROP_E { CQ_TX_ERROP_ENUM_LAST = 0x8a, }; -struct cmp_queue_stats { - struct tx_stats { - u64 good; - u64 desc_fault; - u64 hdr_cons_err; - u64 subdesc_err; - u64 imm_size_oflow; - u64 data_seq_err; - u64 mem_seq_err; - u64 lock_viol; - u64 data_fault; - u64 tstmp_conflict; - u64 tstmp_timeout; - u64 mem_fault; - u64 csum_overlap; - u64 csum_overflow; - } tx; -} ____cacheline_aligned_in_smp; - enum RQ_SQ_STATS { RQ_SQ_STATS_OCTS, RQ_SQ_STATS_PKTS, @@ -241,7 +223,6 @@ struct cmp_queue { spinlock_t lock; /* lock to serialize processing CQEs */ void *desc; struct q_desc_mem dmem; - struct cmp_queue_stats stats; int irq; } ____cacheline_aligned_in_smp; @@ -336,6 +317,5 @@ u64 nicvf_queue_reg_read(struct nicvf *nic, void nicvf_update_rq_stats(struct nicvf *nic, int rq_idx); void nicvf_update_sq_stats(struct nicvf *nic, int sq_idx); int nicvf_check_cqe_rx_errs(struct nicvf *nic, struct cqe_rx_t *cqe_rx); -int nicvf_check_cqe_tx_errs(struct nicvf *nic, - struct cmp_queue *cq, struct cqe_send_t *cqe_tx); +int nicvf_check_cqe_tx_errs(struct nicvf *nic, struct cqe_send_t *cqe_tx); #endif /* NICVF_QUEUES_H */ diff --git a/drivers/net/ethernet/cavium/thunder/thunder_bgx.c b/drivers/net/ethernet/cavium/thunder/thunder_bgx.c index 8bbaedbb7b94..050e21fbb147 100644 --- a/drivers/net/ethernet/cavium/thunder/thunder_bgx.c +++ b/drivers/net/ethernet/cavium/thunder/thunder_bgx.c @@ -1242,8 +1242,8 @@ static int bgx_probe(struct pci_dev *pdev, const struct pci_device_id *ent) pci_read_config_word(pdev, PCI_DEVICE_ID, &sdevid); if (sdevid != PCI_DEVICE_ID_THUNDER_RGX) { - bgx->bgx_id = - (pci_resource_start(pdev, PCI_CFG_REG_BAR_NUM) >> 24) & 1; + bgx->bgx_id = (pci_resource_start(pdev, + PCI_CFG_REG_BAR_NUM) >> 24) & BGX_ID_MASK; bgx->bgx_id += nic_get_node_id(pdev) * MAX_BGX_PER_NODE; bgx->max_lmac = MAX_LMAC_PER_BGX; bgx_vnic[bgx->bgx_id] = bgx; diff --git a/drivers/net/ethernet/cavium/thunder/thunder_bgx.h b/drivers/net/ethernet/cavium/thunder/thunder_bgx.h index d59c71e4a000..01cc7c859131 100644 --- a/drivers/net/ethernet/cavium/thunder/thunder_bgx.h +++ b/drivers/net/ethernet/cavium/thunder/thunder_bgx.h @@ -28,6 +28,8 @@ #define MAX_DMAC_PER_LMAC 8 #define MAX_FRAME_SIZE 9216 +#define BGX_ID_MASK 0x3 + #define MAX_DMAC_PER_LMAC_TNS_BYPASS_MODE 2 /* Registers */ diff --git a/drivers/net/ethernet/chelsio/cxgb4/sge.c b/drivers/net/ethernet/chelsio/cxgb4/sge.c index 1e74fd6085df..e19a0ca8e5dd 100644 --- a/drivers/net/ethernet/chelsio/cxgb4/sge.c +++ b/drivers/net/ethernet/chelsio/cxgb4/sge.c @@ -2951,7 +2951,6 @@ void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, rq->cntxt_id, fl_id, 0xffff); dma_free_coherent(adap->pdev_dev, (rq->size + 1) * rq->iqe_len, rq->desc, rq->phys_addr); - napi_hash_del(&rq->napi); netif_napi_del(&rq->napi); rq->netdev = NULL; rq->cntxt_id = rq->abs_id = 0; diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_pci_id_tbl.h b/drivers/net/ethernet/chelsio/cxgb4/t4_pci_id_tbl.h index 50812a1d67bd..ecf3ccc257bc 100644 --- a/drivers/net/ethernet/chelsio/cxgb4/t4_pci_id_tbl.h +++ b/drivers/net/ethernet/chelsio/cxgb4/t4_pci_id_tbl.h @@ -168,6 +168,7 @@ CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN CH_PCI_ID_TABLE_FENTRY(0x509a), /* Custom T520-CR */ CH_PCI_ID_TABLE_FENTRY(0x509b), /* Custom T540-CR LOM */ CH_PCI_ID_TABLE_FENTRY(0x509c), /* Custom T520-CR*/ + CH_PCI_ID_TABLE_FENTRY(0x509d), /* Custom T540-CR*/ /* T6 adapters: */ @@ -178,9 +179,9 @@ CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN CH_PCI_ID_TABLE_FENTRY(0x6005), CH_PCI_ID_TABLE_FENTRY(0x6006), CH_PCI_ID_TABLE_FENTRY(0x6007), + CH_PCI_ID_TABLE_FENTRY(0x6008), CH_PCI_ID_TABLE_FENTRY(0x6009), CH_PCI_ID_TABLE_FENTRY(0x600d), - CH_PCI_ID_TABLE_FENTRY(0x6010), CH_PCI_ID_TABLE_FENTRY(0x6011), CH_PCI_ID_TABLE_FENTRY(0x6014), CH_PCI_ID_TABLE_FENTRY(0x6015), diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c index cece8a08edca..93aa2939142a 100644 --- a/drivers/net/ethernet/emulex/benet/be_main.c +++ b/drivers/net/ethernet/emulex/benet/be_main.c @@ -2813,7 +2813,6 @@ static void be_evt_queues_destroy(struct be_adapter *adapter) if (eqo->q.created) { be_eq_clean(eqo); be_cmd_q_destroy(adapter, &eqo->q, QTYPE_EQ); - napi_hash_del(&eqo->napi); netif_napi_del(&eqo->napi); free_cpumask_var(eqo->affinity_mask); } diff --git a/drivers/net/ethernet/freescale/fec.h b/drivers/net/ethernet/freescale/fec.h index c865135f3cb9..5ea740b4cf14 100644 --- a/drivers/net/ethernet/freescale/fec.h +++ b/drivers/net/ethernet/freescale/fec.h @@ -574,6 +574,8 @@ struct fec_enet_private { unsigned int reload_period; int pps_enable; unsigned int next_counter; + + u64 ethtool_stats[0]; }; void fec_ptp_init(struct platform_device *pdev); diff --git a/drivers/net/ethernet/freescale/fec_main.c b/drivers/net/ethernet/freescale/fec_main.c index 5aa9d4ded214..5f77caa59534 100644 --- a/drivers/net/ethernet/freescale/fec_main.c +++ b/drivers/net/ethernet/freescale/fec_main.c @@ -2313,14 +2313,24 @@ static const struct fec_stat { { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, }; -static void fec_enet_get_ethtool_stats(struct net_device *dev, - struct ethtool_stats *stats, u64 *data) +static void fec_enet_update_ethtool_stats(struct net_device *dev) { struct fec_enet_private *fep = netdev_priv(dev); int i; for (i = 0; i < ARRAY_SIZE(fec_stats); i++) - data[i] = readl(fep->hwp + fec_stats[i].offset); + fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset); +} + +static void fec_enet_get_ethtool_stats(struct net_device *dev, + struct ethtool_stats *stats, u64 *data) +{ + struct fec_enet_private *fep = netdev_priv(dev); + + if (netif_running(dev)) + fec_enet_update_ethtool_stats(dev); + + memcpy(data, fep->ethtool_stats, ARRAY_SIZE(fec_stats) * sizeof(u64)); } static void fec_enet_get_strings(struct net_device *netdev, @@ -2874,6 +2884,8 @@ fec_enet_close(struct net_device *ndev) if (fep->quirks & FEC_QUIRK_ERR006687) imx6q_cpuidle_fec_irqs_unused(); + fec_enet_update_ethtool_stats(ndev); + fec_enet_clk_enable(ndev, false); pinctrl_pm_select_sleep_state(&fep->pdev->dev); pm_runtime_mark_last_busy(&fep->pdev->dev); @@ -3180,6 +3192,8 @@ static int fec_enet_init(struct net_device *ndev) fec_restart(ndev); + fec_enet_update_ethtool_stats(ndev); + return 0; } @@ -3278,7 +3292,8 @@ fec_probe(struct platform_device *pdev) fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs); /* Init network device */ - ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private), + ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) + + ARRAY_SIZE(fec_stats) * sizeof(u64), num_tx_qs, num_rx_qs); if (!ndev) return -ENOMEM; @@ -3475,6 +3490,8 @@ failed_regulator: failed_clk_ipg: fec_enet_clk_enable(ndev, false); failed_clk: + if (of_phy_is_fixed_link(np)) + of_phy_deregister_fixed_link(np); failed_phy: of_node_put(phy_node); failed_ioremap: @@ -3488,6 +3505,7 @@ fec_drv_remove(struct platform_device *pdev) { struct net_device *ndev = platform_get_drvdata(pdev); struct fec_enet_private *fep = netdev_priv(ndev); + struct device_node *np = pdev->dev.of_node; cancel_work_sync(&fep->tx_timeout_work); fec_ptp_stop(pdev); @@ -3495,6 +3513,8 @@ fec_drv_remove(struct platform_device *pdev) fec_enet_mii_remove(fep); if (fep->reg_phy) regulator_disable(fep->reg_phy); + if (of_phy_is_fixed_link(np)) + of_phy_deregister_fixed_link(np); of_node_put(fep->phy_node); free_netdev(ndev); diff --git a/drivers/net/ethernet/freescale/fman/fman_memac.c b/drivers/net/ethernet/freescale/fman/fman_memac.c index 53ef51e3bd9e..71a5ded9d1de 100644 --- a/drivers/net/ethernet/freescale/fman/fman_memac.c +++ b/drivers/net/ethernet/freescale/fman/fman_memac.c @@ -1107,6 +1107,9 @@ int memac_free(struct fman_mac *memac) { free_init_resources(memac); + if (memac->pcsphy) + put_device(&memac->pcsphy->mdio.dev); + kfree(memac->memac_drv_param); kfree(memac); diff --git a/drivers/net/ethernet/freescale/fman/fman_tgec.c b/drivers/net/ethernet/freescale/fman/fman_tgec.c index efabb04a1ae8..4b0f3a50b293 100644 --- a/drivers/net/ethernet/freescale/fman/fman_tgec.c +++ b/drivers/net/ethernet/freescale/fman/fman_tgec.c @@ -722,9 +722,6 @@ int tgec_free(struct fman_mac *tgec) { free_init_resources(tgec); - if (tgec->cfg) - tgec->cfg = NULL; - kfree(tgec->cfg); kfree(tgec); diff --git a/drivers/net/ethernet/freescale/fman/mac.c b/drivers/net/ethernet/freescale/fman/mac.c index 8fe6b3e253fa..736db9d9b0ad 100644 --- a/drivers/net/ethernet/freescale/fman/mac.c +++ b/drivers/net/ethernet/freescale/fman/mac.c @@ -892,6 +892,8 @@ static int mac_probe(struct platform_device *_of_dev) priv->fixed_link->duplex = phy->duplex; priv->fixed_link->pause = phy->pause; priv->fixed_link->asym_pause = phy->asym_pause; + + put_device(&phy->mdio.dev); } err = mac_dev->init(mac_dev); diff --git a/drivers/net/ethernet/freescale/fs_enet/fs_enet-main.c b/drivers/net/ethernet/freescale/fs_enet/fs_enet-main.c index dc120c148d97..4b86260584a0 100644 --- a/drivers/net/ethernet/freescale/fs_enet/fs_enet-main.c +++ b/drivers/net/ethernet/freescale/fs_enet/fs_enet-main.c @@ -980,7 +980,7 @@ static int fs_enet_probe(struct platform_device *ofdev) err = clk_prepare_enable(clk); if (err) { ret = err; - goto out_free_fpi; + goto out_deregister_fixed_link; } fpi->clk_per = clk; } @@ -1061,6 +1061,9 @@ out_put: of_node_put(fpi->phy_node); if (fpi->clk_per) clk_disable_unprepare(fpi->clk_per); +out_deregister_fixed_link: + if (of_phy_is_fixed_link(ofdev->dev.of_node)) + of_phy_deregister_fixed_link(ofdev->dev.of_node); out_free_fpi: kfree(fpi); return ret; @@ -1079,6 +1082,8 @@ static int fs_enet_remove(struct platform_device *ofdev) of_node_put(fep->fpi->phy_node); if (fep->fpi->clk_per) clk_disable_unprepare(fep->fpi->clk_per); + if (of_phy_is_fixed_link(ofdev->dev.of_node)) + of_phy_deregister_fixed_link(ofdev->dev.of_node); free_netdev(ndev); return 0; } diff --git a/drivers/net/ethernet/freescale/gianfar.c b/drivers/net/ethernet/freescale/gianfar.c index 4b4f5bc0e279..9061c2f82b9c 100644 --- a/drivers/net/ethernet/freescale/gianfar.c +++ b/drivers/net/ethernet/freescale/gianfar.c @@ -1312,6 +1312,7 @@ static void gfar_init_addr_hash_table(struct gfar_private *priv) */ static int gfar_probe(struct platform_device *ofdev) { + struct device_node *np = ofdev->dev.of_node; struct net_device *dev = NULL; struct gfar_private *priv = NULL; int err = 0, i; @@ -1462,6 +1463,8 @@ static int gfar_probe(struct platform_device *ofdev) return 0; register_fail: + if (of_phy_is_fixed_link(np)) + of_phy_deregister_fixed_link(np); unmap_group_regs(priv); gfar_free_rx_queues(priv); gfar_free_tx_queues(priv); @@ -1474,11 +1477,16 @@ register_fail: static int gfar_remove(struct platform_device *ofdev) { struct gfar_private *priv = platform_get_drvdata(ofdev); + struct device_node *np = ofdev->dev.of_node; of_node_put(priv->phy_node); of_node_put(priv->tbi_node); unregister_netdev(priv->ndev); + + if (of_phy_is_fixed_link(np)) + of_phy_deregister_fixed_link(np); + unmap_group_regs(priv); gfar_free_rx_queues(priv); gfar_free_tx_queues(priv); diff --git a/drivers/net/ethernet/freescale/ucc_geth.c b/drivers/net/ethernet/freescale/ucc_geth.c index 186ef8f16c80..f76d33279454 100644 --- a/drivers/net/ethernet/freescale/ucc_geth.c +++ b/drivers/net/ethernet/freescale/ucc_geth.c @@ -3868,9 +3868,8 @@ static int ucc_geth_probe(struct platform_device* ofdev) dev = alloc_etherdev(sizeof(*ugeth)); if (dev == NULL) { - of_node_put(ug_info->tbi_node); - of_node_put(ug_info->phy_node); - return -ENOMEM; + err = -ENOMEM; + goto err_deregister_fixed_link; } ugeth = netdev_priv(dev); @@ -3907,10 +3906,7 @@ static int ucc_geth_probe(struct platform_device* ofdev) if (netif_msg_probe(ugeth)) pr_err("%s: Cannot register net device, aborting\n", dev->name); - free_netdev(dev); - of_node_put(ug_info->tbi_node); - of_node_put(ug_info->phy_node); - return err; + goto err_free_netdev; } mac_addr = of_get_mac_address(np); @@ -3923,16 +3919,29 @@ static int ucc_geth_probe(struct platform_device* ofdev) ugeth->node = np; return 0; + +err_free_netdev: + free_netdev(dev); +err_deregister_fixed_link: + if (of_phy_is_fixed_link(np)) + of_phy_deregister_fixed_link(np); + of_node_put(ug_info->tbi_node); + of_node_put(ug_info->phy_node); + + return err; } static int ucc_geth_remove(struct platform_device* ofdev) { struct net_device *dev = platform_get_drvdata(ofdev); struct ucc_geth_private *ugeth = netdev_priv(dev); + struct device_node *np = ofdev->dev.of_node; unregister_netdev(dev); free_netdev(dev); ucc_geth_memclean(ugeth); + if (of_phy_is_fixed_link(np)) + of_phy_deregister_fixed_link(np); of_node_put(ugeth->ug_info->tbi_node); of_node_put(ugeth->ug_info->phy_node); diff --git a/drivers/net/ethernet/hisilicon/hns/hnae.c b/drivers/net/ethernet/hisilicon/hns/hnae.c index c54c6fac0d1d..b6ed818f78ff 100644 --- a/drivers/net/ethernet/hisilicon/hns/hnae.c +++ b/drivers/net/ethernet/hisilicon/hns/hnae.c @@ -332,8 +332,10 @@ struct hnae_handle *hnae_get_handle(struct device *owner_dev, return ERR_PTR(-ENODEV); handle = dev->ops->get_handle(dev, port_id); - if (IS_ERR(handle)) + if (IS_ERR(handle)) { + put_device(&dev->cls_dev); return handle; + } handle->dev = dev; handle->owner_dev = owner_dev; @@ -356,6 +358,8 @@ out_when_init_queue: for (j = i - 1; j >= 0; j--) hnae_fini_queue(handle->qs[j]); + put_device(&dev->cls_dev); + return ERR_PTR(-ENOMEM); } EXPORT_SYMBOL(hnae_get_handle); @@ -377,6 +381,8 @@ void hnae_put_handle(struct hnae_handle *h) dev->ops->put_handle(h); module_put(dev->owner); + + put_device(&dev->cls_dev); } EXPORT_SYMBOL(hnae_put_handle); diff --git a/drivers/net/ethernet/ibm/ehea/ehea_main.c b/drivers/net/ethernet/ibm/ehea/ehea_main.c index 54efa9a5167b..bd719e25dd76 100644 --- a/drivers/net/ethernet/ibm/ehea/ehea_main.c +++ b/drivers/net/ethernet/ibm/ehea/ehea_main.c @@ -2446,6 +2446,8 @@ static int ehea_open(struct net_device *dev) netif_info(port, ifup, dev, "enabling port\n"); + netif_carrier_off(dev); + ret = ehea_up(dev); if (!ret) { port_napi_enable(port); diff --git a/drivers/net/ethernet/ibm/ibmvnic.c b/drivers/net/ethernet/ibm/ibmvnic.c index 5f44c5520fbc..0fbf686f5e7c 100644 --- a/drivers/net/ethernet/ibm/ibmvnic.c +++ b/drivers/net/ethernet/ibm/ibmvnic.c @@ -74,7 +74,6 @@ #include <asm/iommu.h> #include <linux/uaccess.h> #include <asm/firmware.h> -#include <linux/seq_file.h> #include <linux/workqueue.h> #include "ibmvnic.h" @@ -1505,9 +1504,8 @@ static void init_sub_crqs(struct ibmvnic_adapter *adapter, int retry) adapter->max_rx_add_entries_per_subcrq > entries_page ? entries_page : adapter->max_rx_add_entries_per_subcrq; - /* Choosing the maximum number of queues supported by firmware*/ - adapter->req_tx_queues = adapter->max_tx_queues; - adapter->req_rx_queues = adapter->max_rx_queues; + adapter->req_tx_queues = adapter->opt_tx_comp_sub_queues; + adapter->req_rx_queues = adapter->opt_rx_comp_queues; adapter->req_rx_add_queues = adapter->max_rx_add_queues; adapter->req_mtu = adapter->max_mtu; @@ -3706,7 +3704,7 @@ static int ibmvnic_probe(struct vio_dev *dev, const struct vio_device_id *id) struct net_device *netdev; unsigned char *mac_addr_p; struct dentry *ent; - char buf[16]; /* debugfs name buf */ + char buf[17]; /* debugfs name buf */ int rc; dev_dbg(&dev->dev, "entering ibmvnic_probe for UA 0x%x\n", @@ -3845,6 +3843,9 @@ static int ibmvnic_remove(struct vio_dev *dev) if (adapter->debugfs_dir && !IS_ERR(adapter->debugfs_dir)) debugfs_remove_recursive(adapter->debugfs_dir); + dma_unmap_single(&dev->dev, adapter->stats_token, + sizeof(struct ibmvnic_statistics), DMA_FROM_DEVICE); + if (adapter->ras_comps) dma_free_coherent(&dev->dev, adapter->ras_comp_num * diff --git a/drivers/net/ethernet/intel/igb/igb_main.c b/drivers/net/ethernet/intel/igb/igb_main.c index edc9a6ac5169..9affd7c198bd 100644 --- a/drivers/net/ethernet/intel/igb/igb_main.c +++ b/drivers/net/ethernet/intel/igb/igb_main.c @@ -4931,11 +4931,15 @@ static int igb_tso(struct igb_ring *tx_ring, /* initialize outer IP header fields */ if (ip.v4->version == 4) { + unsigned char *csum_start = skb_checksum_start(skb); + unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); + /* IP header will have to cancel out any data that * is not a part of the outer IP header */ - ip.v4->check = csum_fold(csum_add(lco_csum(skb), - csum_unfold(l4.tcp->check))); + ip.v4->check = csum_fold(csum_partial(trans_start, + csum_start - trans_start, + 0)); type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; ip.v4->tot_len = 0; diff --git a/drivers/net/ethernet/intel/igbvf/netdev.c b/drivers/net/ethernet/intel/igbvf/netdev.c index 12bb877df860..7dff7f6239cd 100644 --- a/drivers/net/ethernet/intel/igbvf/netdev.c +++ b/drivers/net/ethernet/intel/igbvf/netdev.c @@ -1965,11 +1965,15 @@ static int igbvf_tso(struct igbvf_ring *tx_ring, /* initialize outer IP header fields */ if (ip.v4->version == 4) { + unsigned char *csum_start = skb_checksum_start(skb); + unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); + /* IP header will have to cancel out any data that * is not a part of the outer IP header */ - ip.v4->check = csum_fold(csum_add(lco_csum(skb), - csum_unfold(l4.tcp->check))); + ip.v4->check = csum_fold(csum_partial(trans_start, + csum_start - trans_start, + 0)); type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; ip.v4->tot_len = 0; diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c index bd93d823cc25..fee1f2918ead 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c @@ -7277,11 +7277,15 @@ static int ixgbe_tso(struct ixgbe_ring *tx_ring, /* initialize outer IP header fields */ if (ip.v4->version == 4) { + unsigned char *csum_start = skb_checksum_start(skb); + unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); + /* IP header will have to cancel out any data that * is not a part of the outer IP header */ - ip.v4->check = csum_fold(csum_add(lco_csum(skb), - csum_unfold(l4.tcp->check))); + ip.v4->check = csum_fold(csum_partial(trans_start, + csum_start - trans_start, + 0)); type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; ip.v4->tot_len = 0; diff --git a/drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c b/drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c index 7eaac3234049..cbf70fe4028a 100644 --- a/drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c +++ b/drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c @@ -3329,11 +3329,15 @@ static int ixgbevf_tso(struct ixgbevf_ring *tx_ring, /* initialize outer IP header fields */ if (ip.v4->version == 4) { + unsigned char *csum_start = skb_checksum_start(skb); + unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); + /* IP header will have to cancel out any data that * is not a part of the outer IP header */ - ip.v4->check = csum_fold(csum_add(lco_csum(skb), - csum_unfold(l4.tcp->check))); + ip.v4->check = csum_fold(csum_partial(trans_start, + csum_start - trans_start, + 0)); type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; ip.v4->tot_len = 0; diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c index bf5cc55ba24c..5b12022adf1f 100644 --- a/drivers/net/ethernet/marvell/mv643xx_eth.c +++ b/drivers/net/ethernet/marvell/mv643xx_eth.c @@ -1381,6 +1381,7 @@ static unsigned int get_rx_coal(struct mv643xx_eth_private *mp) temp = (val & 0x003fff00) >> 8; temp *= 64000000; + temp += mp->t_clk / 2; do_div(temp, mp->t_clk); return (unsigned int)temp; @@ -1417,6 +1418,7 @@ static unsigned int get_tx_coal(struct mv643xx_eth_private *mp) temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4; temp *= 64000000; + temp += mp->t_clk / 2; do_div(temp, mp->t_clk); return (unsigned int)temp; diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c index 5cb07c2017bf..707bc4680b9b 100644 --- a/drivers/net/ethernet/marvell/mvneta.c +++ b/drivers/net/ethernet/marvell/mvneta.c @@ -4151,7 +4151,7 @@ static int mvneta_probe(struct platform_device *pdev) dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; dev->hw_features |= dev->features; dev->vlan_features |= dev->features; - dev->priv_flags |= IFF_UNICAST_FLT | IFF_LIVE_ADDR_CHANGE; + dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; dev->gso_max_segs = MVNETA_MAX_TSO_SEGS; err = register_netdev(dev); @@ -4191,6 +4191,8 @@ err_clk: clk_disable_unprepare(pp->clk); err_put_phy_node: of_node_put(phy_node); + if (of_phy_is_fixed_link(dn)) + of_phy_deregister_fixed_link(dn); err_free_irq: irq_dispose_mapping(dev->irq); err_free_netdev: @@ -4202,6 +4204,7 @@ err_free_netdev: static int mvneta_remove(struct platform_device *pdev) { struct net_device *dev = platform_get_drvdata(pdev); + struct device_node *dn = pdev->dev.of_node; struct mvneta_port *pp = netdev_priv(dev); unregister_netdev(dev); @@ -4209,6 +4212,8 @@ static int mvneta_remove(struct platform_device *pdev) clk_disable_unprepare(pp->clk); free_percpu(pp->ports); free_percpu(pp->stats); + if (of_phy_is_fixed_link(dn)) + of_phy_deregister_fixed_link(dn); irq_dispose_mapping(dev->irq); of_node_put(pp->phy_node); free_netdev(dev); diff --git a/drivers/net/ethernet/marvell/mvpp2.c b/drivers/net/ethernet/marvell/mvpp2.c index 60227a3452a4..1026c452e39d 100644 --- a/drivers/net/ethernet/marvell/mvpp2.c +++ b/drivers/net/ethernet/marvell/mvpp2.c @@ -3293,7 +3293,7 @@ static void mvpp2_cls_init(struct mvpp2 *priv) mvpp2_write(priv, MVPP2_CLS_MODE_REG, MVPP2_CLS_MODE_ACTIVE_MASK); /* Clear classifier flow table */ - memset(&fe.data, 0, MVPP2_CLS_FLOWS_TBL_DATA_WORDS); + memset(&fe.data, 0, sizeof(fe.data)); for (index = 0; index < MVPP2_CLS_FLOWS_TBL_SIZE; index++) { fe.index = index; mvpp2_cls_flow_write(priv, &fe); diff --git a/drivers/net/ethernet/marvell/sky2.c b/drivers/net/ethernet/marvell/sky2.c index f05ea56dcff2..941c8e2c944e 100644 --- a/drivers/net/ethernet/marvell/sky2.c +++ b/drivers/net/ethernet/marvell/sky2.c @@ -5220,6 +5220,19 @@ static SIMPLE_DEV_PM_OPS(sky2_pm_ops, sky2_suspend, sky2_resume); static void sky2_shutdown(struct pci_dev *pdev) { + struct sky2_hw *hw = pci_get_drvdata(pdev); + int port; + + for (port = 0; port < hw->ports; port++) { + struct net_device *ndev = hw->dev[port]; + + rtnl_lock(); + if (netif_running(ndev)) { + dev_close(ndev); + netif_device_detach(ndev); + } + rtnl_unlock(); + } sky2_suspend(&pdev->dev); pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev)); pci_set_power_state(pdev, PCI_D3hot); diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c index 4a62ffd7729d..86a89cbd3ec9 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -318,6 +318,8 @@ static int mtk_phy_connect(struct net_device *dev) return 0; err_phy: + if (of_phy_is_fixed_link(mac->of_node)) + of_phy_deregister_fixed_link(mac->of_node); of_node_put(np); dev_err(eth->dev, "%s: invalid phy\n", __func__); return -EINVAL; @@ -1923,6 +1925,8 @@ static void mtk_uninit(struct net_device *dev) struct mtk_eth *eth = mac->hw; phy_disconnect(dev->phydev); + if (of_phy_is_fixed_link(mac->of_node)) + of_phy_deregister_fixed_link(mac->of_node); mtk_irq_disable(eth, MTK_QDMA_INT_MASK, ~0); mtk_irq_disable(eth, MTK_PDMA_INT_MASK, ~0); } diff --git a/drivers/net/ethernet/mellanox/mlx4/en_netdev.c b/drivers/net/ethernet/mellanox/mlx4/en_netdev.c index 12c99a2655f2..fb8bb027b69c 100644 --- a/drivers/net/ethernet/mellanox/mlx4/en_netdev.c +++ b/drivers/net/ethernet/mellanox/mlx4/en_netdev.c @@ -129,6 +129,9 @@ static enum mlx4_net_trans_rule_id mlx4_ip_proto_to_trans_rule_id(u8 ip_proto) } }; +/* Must not acquire state_lock, as its corresponding work_sync + * is done under it. + */ static void mlx4_en_filter_work(struct work_struct *work) { struct mlx4_en_filter *filter = container_of(work, @@ -2076,13 +2079,6 @@ err: return -ENOMEM; } -static void mlx4_en_shutdown(struct net_device *dev) -{ - rtnl_lock(); - netif_device_detach(dev); - mlx4_en_close(dev); - rtnl_unlock(); -} static int mlx4_en_copy_priv(struct mlx4_en_priv *dst, struct mlx4_en_priv *src, @@ -2159,8 +2155,6 @@ void mlx4_en_destroy_netdev(struct net_device *dev) { struct mlx4_en_priv *priv = netdev_priv(dev); struct mlx4_en_dev *mdev = priv->mdev; - bool shutdown = mdev->dev->persist->interface_state & - MLX4_INTERFACE_STATE_SHUTDOWN; en_dbg(DRV, priv, "Destroying netdev on port:%d\n", priv->port); @@ -2168,10 +2162,7 @@ void mlx4_en_destroy_netdev(struct net_device *dev) if (priv->registered) { devlink_port_type_clear(mlx4_get_devlink_port(mdev->dev, priv->port)); - if (shutdown) - mlx4_en_shutdown(dev); - else - unregister_netdev(dev); + unregister_netdev(dev); } if (priv->allocated) @@ -2189,20 +2180,18 @@ void mlx4_en_destroy_netdev(struct net_device *dev) mutex_lock(&mdev->state_lock); mdev->pndev[priv->port] = NULL; mdev->upper[priv->port] = NULL; - mutex_unlock(&mdev->state_lock); #ifdef CONFIG_RFS_ACCEL mlx4_en_cleanup_filters(priv); #endif mlx4_en_free_resources(priv); + mutex_unlock(&mdev->state_lock); kfree(priv->tx_ring); kfree(priv->tx_cq); - if (!shutdown) - free_netdev(dev); - dev->ethtool_ops = NULL; + free_netdev(dev); } static int mlx4_en_change_mtu(struct net_device *dev, int new_mtu) diff --git a/drivers/net/ethernet/mellanox/mlx4/main.c b/drivers/net/ethernet/mellanox/mlx4/main.c index 6f4e67bc3538..75d07fa9d0b1 100644 --- a/drivers/net/ethernet/mellanox/mlx4/main.c +++ b/drivers/net/ethernet/mellanox/mlx4/main.c @@ -4147,11 +4147,8 @@ static void mlx4_shutdown(struct pci_dev *pdev) mlx4_info(persist->dev, "mlx4_shutdown was called\n"); mutex_lock(&persist->interface_state_mutex); - if (persist->interface_state & MLX4_INTERFACE_STATE_UP) { - /* Notify mlx4 clients that the kernel is being shut down */ - persist->interface_state |= MLX4_INTERFACE_STATE_SHUTDOWN; + if (persist->interface_state & MLX4_INTERFACE_STATE_UP) mlx4_unload_one(pdev); - } mutex_unlock(&persist->interface_state_mutex); } diff --git a/drivers/net/ethernet/mellanox/mlx4/mcg.c b/drivers/net/ethernet/mellanox/mlx4/mcg.c index 94b891c118c1..1a670b681555 100644 --- a/drivers/net/ethernet/mellanox/mlx4/mcg.c +++ b/drivers/net/ethernet/mellanox/mlx4/mcg.c @@ -1457,7 +1457,12 @@ EXPORT_SYMBOL_GPL(mlx4_multicast_detach); int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn, enum mlx4_net_trans_promisc_mode mode) { - struct mlx4_net_trans_rule rule; + struct mlx4_net_trans_rule rule = { + .queue_mode = MLX4_NET_TRANS_Q_FIFO, + .exclusive = 0, + .allow_loopback = 1, + }; + u64 *regid_p; switch (mode) { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c index f4c687ce4c59..84e8b250e2af 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -1445,6 +1445,7 @@ static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix, c->netdev = priv->netdev; c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key); c->num_tc = priv->params.num_tc; + c->xdp = !!priv->xdp_prog; if (priv->params.rx_am_enabled) rx_cq_profile = mlx5e_am_get_def_profile(priv->params.rx_cq_period_mode); @@ -1468,6 +1469,12 @@ static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix, if (err) goto err_close_tx_cqs; + /* XDP SQ CQ params are same as normal TXQ sq CQ params */ + err = c->xdp ? mlx5e_open_cq(c, &cparam->tx_cq, &c->xdp_sq.cq, + priv->params.tx_cq_moderation) : 0; + if (err) + goto err_close_rx_cq; + napi_enable(&c->napi); err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq); @@ -1488,21 +1495,10 @@ static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix, } } - if (priv->xdp_prog) { - /* XDP SQ CQ params are same as normal TXQ sq CQ params */ - err = mlx5e_open_cq(c, &cparam->tx_cq, &c->xdp_sq.cq, - priv->params.tx_cq_moderation); - if (err) - goto err_close_sqs; - - err = mlx5e_open_sq(c, 0, &cparam->xdp_sq, &c->xdp_sq); - if (err) { - mlx5e_close_cq(&c->xdp_sq.cq); - goto err_close_sqs; - } - } + err = c->xdp ? mlx5e_open_sq(c, 0, &cparam->xdp_sq, &c->xdp_sq) : 0; + if (err) + goto err_close_sqs; - c->xdp = !!priv->xdp_prog; err = mlx5e_open_rq(c, &cparam->rq, &c->rq); if (err) goto err_close_xdp_sq; @@ -1512,7 +1508,8 @@ static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix, return 0; err_close_xdp_sq: - mlx5e_close_sq(&c->xdp_sq); + if (c->xdp) + mlx5e_close_sq(&c->xdp_sq); err_close_sqs: mlx5e_close_sqs(c); @@ -1522,6 +1519,10 @@ err_close_icosq: err_disable_napi: napi_disable(&c->napi); + if (c->xdp) + mlx5e_close_cq(&c->xdp_sq.cq); + +err_close_rx_cq: mlx5e_close_cq(&c->rq.cq); err_close_tx_cqs: diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_rep.c b/drivers/net/ethernet/mellanox/mlx5/core/en_rep.c index 7fe6559e4ab3..bf1c09ca73c0 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_rep.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_rep.c @@ -308,7 +308,7 @@ static void mlx5e_build_rep_netdev(struct net_device *netdev) netdev->switchdev_ops = &mlx5e_rep_switchdev_ops; #endif - netdev->features |= NETIF_F_VLAN_CHALLENGED | NETIF_F_HW_TC; + netdev->features |= NETIF_F_VLAN_CHALLENGED | NETIF_F_HW_TC | NETIF_F_NETNS_LOCAL; netdev->hw_features |= NETIF_F_HW_TC; eth_hw_addr_random(netdev); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c index ce8c54d18906..6bb21b31cfeb 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c @@ -237,12 +237,15 @@ static int parse_cls_flower(struct mlx5e_priv *priv, struct mlx5_flow_spec *spec skb_flow_dissector_target(f->dissector, FLOW_DISSECTOR_KEY_VLAN, f->mask); - if (mask->vlan_id) { + if (mask->vlan_id || mask->vlan_priority) { MLX5_SET(fte_match_set_lyr_2_4, headers_c, vlan_tag, 1); MLX5_SET(fte_match_set_lyr_2_4, headers_v, vlan_tag, 1); MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid, mask->vlan_id); MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, key->vlan_id); + + MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio, mask->vlan_priority); + MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, key->vlan_priority); } } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index c55ad8d00c05..d239f5d0ea36 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -57,7 +57,8 @@ mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw, if (esw->mode != SRIOV_OFFLOADS) return ERR_PTR(-EOPNOTSUPP); - action = attr->action; + /* per flow vlan pop/push is emulated, don't set that into the firmware */ + action = attr->action & ~(MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH | MLX5_FLOW_CONTEXT_ACTION_VLAN_POP); if (action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) { dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c index 89696048b045..914e5466f729 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c @@ -1690,7 +1690,7 @@ static int init_root_ns(struct mlx5_flow_steering *steering) { steering->root_ns = create_root_ns(steering, FS_FT_NIC_RX); - if (IS_ERR_OR_NULL(steering->root_ns)) + if (!steering->root_ns) goto cleanup; if (init_root_tree(steering, &root_fs, &steering->root_ns->ns.node)) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/main.c b/drivers/net/ethernet/mellanox/mlx5/core/main.c index d5433c49b2b0..3b7c6a9f2b5f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/main.c @@ -46,7 +46,6 @@ #include <linux/mlx5/srq.h> #include <linux/debugfs.h> #include <linux/kmod.h> -#include <linux/delay.h> #include <linux/mlx5/mlx5_ifc.h> #ifdef CONFIG_RFS_ACCEL #include <linux/cpu_rmap.h> @@ -1226,6 +1225,9 @@ static int init_one(struct pci_dev *pdev, pci_set_drvdata(pdev, dev); + dev->pdev = pdev; + dev->event = mlx5_core_event; + if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profile)) { mlx5_core_warn(dev, "selected profile out of range, selecting default (%d)\n", @@ -1233,8 +1235,6 @@ static int init_one(struct pci_dev *pdev, prof_sel = MLX5_DEFAULT_PROF; } dev->profile = &profile[prof_sel]; - dev->pdev = pdev; - dev->event = mlx5_core_event; INIT_LIST_HEAD(&priv->ctx_list); spin_lock_init(&priv->ctx_lock); diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum.c index 1ec0a4ce3c46..dda5761e91bc 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum.c +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum.c @@ -231,7 +231,7 @@ mlxsw_sp_span_entry_create(struct mlxsw_sp_port *port) span_entry->used = true; span_entry->id = index; - span_entry->ref_count = 0; + span_entry->ref_count = 1; span_entry->local_port = local_port; return span_entry; } @@ -270,6 +270,7 @@ static struct mlxsw_sp_span_entry span_entry = mlxsw_sp_span_entry_find(port); if (span_entry) { + /* Already exists, just take a reference */ span_entry->ref_count++; return span_entry; } @@ -280,6 +281,7 @@ static struct mlxsw_sp_span_entry static int mlxsw_sp_span_entry_put(struct mlxsw_sp *mlxsw_sp, struct mlxsw_sp_span_entry *span_entry) { + WARN_ON(!span_entry->ref_count); if (--span_entry->ref_count == 0) mlxsw_sp_span_entry_destroy(mlxsw_sp, span_entry); return 0; diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum.h b/drivers/net/ethernet/mellanox/mlxsw/spectrum.h index 9b22863a924b..97bbc1d21df8 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum.h +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum.h @@ -115,7 +115,7 @@ struct mlxsw_sp_rif { struct mlxsw_sp_mid { struct list_head list; unsigned char addr[ETH_ALEN]; - u16 vid; + u16 fid; u16 mid; unsigned int ref_count; }; diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c index 4573da2c5560..e83072da6272 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c @@ -594,21 +594,22 @@ static int mlxsw_sp_vrs_init(struct mlxsw_sp *mlxsw_sp) return 0; } +static void mlxsw_sp_router_fib_flush(struct mlxsw_sp *mlxsw_sp); + static void mlxsw_sp_vrs_fini(struct mlxsw_sp *mlxsw_sp) { + mlxsw_sp_router_fib_flush(mlxsw_sp); kfree(mlxsw_sp->router.vrs); } struct mlxsw_sp_neigh_key { - unsigned char addr[sizeof(struct in6_addr)]; - struct net_device *dev; + struct neighbour *n; }; struct mlxsw_sp_neigh_entry { struct rhash_head ht_node; struct mlxsw_sp_neigh_key key; u16 rif; - struct neighbour *n; bool offloaded; struct delayed_work dw; struct mlxsw_sp_port *mlxsw_sp_port; @@ -646,19 +647,15 @@ mlxsw_sp_neigh_entry_remove(struct mlxsw_sp *mlxsw_sp, static void mlxsw_sp_router_neigh_update_hw(struct work_struct *work); static struct mlxsw_sp_neigh_entry * -mlxsw_sp_neigh_entry_create(const void *addr, size_t addr_len, - struct net_device *dev, u16 rif, - struct neighbour *n) +mlxsw_sp_neigh_entry_create(struct neighbour *n, u16 rif) { struct mlxsw_sp_neigh_entry *neigh_entry; neigh_entry = kzalloc(sizeof(*neigh_entry), GFP_ATOMIC); if (!neigh_entry) return NULL; - memcpy(neigh_entry->key.addr, addr, addr_len); - neigh_entry->key.dev = dev; + neigh_entry->key.n = n; neigh_entry->rif = rif; - neigh_entry->n = n; INIT_DELAYED_WORK(&neigh_entry->dw, mlxsw_sp_router_neigh_update_hw); INIT_LIST_HEAD(&neigh_entry->nexthop_list); return neigh_entry; @@ -671,13 +668,11 @@ mlxsw_sp_neigh_entry_destroy(struct mlxsw_sp_neigh_entry *neigh_entry) } static struct mlxsw_sp_neigh_entry * -mlxsw_sp_neigh_entry_lookup(struct mlxsw_sp *mlxsw_sp, const void *addr, - size_t addr_len, struct net_device *dev) +mlxsw_sp_neigh_entry_lookup(struct mlxsw_sp *mlxsw_sp, struct neighbour *n) { - struct mlxsw_sp_neigh_key key = {{ 0 } }; + struct mlxsw_sp_neigh_key key; - memcpy(key.addr, addr, addr_len); - key.dev = dev; + key.n = n; return rhashtable_lookup_fast(&mlxsw_sp->router.neigh_ht, &key, mlxsw_sp_neigh_ht_params); } @@ -689,26 +684,20 @@ int mlxsw_sp_router_neigh_construct(struct net_device *dev, struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; struct mlxsw_sp_neigh_entry *neigh_entry; struct mlxsw_sp_rif *r; - u32 dip; int err; if (n->tbl != &arp_tbl) return 0; - dip = ntohl(*((__be32 *) n->primary_key)); - neigh_entry = mlxsw_sp_neigh_entry_lookup(mlxsw_sp, &dip, sizeof(dip), - n->dev); - if (neigh_entry) { - WARN_ON(neigh_entry->n != n); + neigh_entry = mlxsw_sp_neigh_entry_lookup(mlxsw_sp, n); + if (neigh_entry) return 0; - } r = mlxsw_sp_rif_find_by_dev(mlxsw_sp, n->dev); if (WARN_ON(!r)) return -EINVAL; - neigh_entry = mlxsw_sp_neigh_entry_create(&dip, sizeof(dip), n->dev, - r->rif, n); + neigh_entry = mlxsw_sp_neigh_entry_create(n, r->rif); if (!neigh_entry) return -ENOMEM; err = mlxsw_sp_neigh_entry_insert(mlxsw_sp, neigh_entry); @@ -727,14 +716,11 @@ void mlxsw_sp_router_neigh_destroy(struct net_device *dev, struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; struct mlxsw_sp_neigh_entry *neigh_entry; - u32 dip; if (n->tbl != &arp_tbl) return; - dip = ntohl(*((__be32 *) n->primary_key)); - neigh_entry = mlxsw_sp_neigh_entry_lookup(mlxsw_sp, &dip, sizeof(dip), - n->dev); + neigh_entry = mlxsw_sp_neigh_entry_lookup(mlxsw_sp, n); if (!neigh_entry) return; mlxsw_sp_neigh_entry_remove(mlxsw_sp, neigh_entry); @@ -817,6 +803,26 @@ static void mlxsw_sp_router_neigh_rec_process(struct mlxsw_sp *mlxsw_sp, } } +static bool mlxsw_sp_router_rauhtd_is_full(char *rauhtd_pl) +{ + u8 num_rec, last_rec_index, num_entries; + + num_rec = mlxsw_reg_rauhtd_num_rec_get(rauhtd_pl); + last_rec_index = num_rec - 1; + + if (num_rec < MLXSW_REG_RAUHTD_REC_MAX_NUM) + return false; + if (mlxsw_reg_rauhtd_rec_type_get(rauhtd_pl, last_rec_index) == + MLXSW_REG_RAUHTD_TYPE_IPV6) + return true; + + num_entries = mlxsw_reg_rauhtd_ipv4_rec_num_entries_get(rauhtd_pl, + last_rec_index); + if (++num_entries == MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC) + return true; + return false; +} + static int mlxsw_sp_router_neighs_update_rauhtd(struct mlxsw_sp *mlxsw_sp) { char *rauhtd_pl; @@ -843,7 +849,7 @@ static int mlxsw_sp_router_neighs_update_rauhtd(struct mlxsw_sp *mlxsw_sp) for (i = 0; i < num_rec; i++) mlxsw_sp_router_neigh_rec_process(mlxsw_sp, rauhtd_pl, i); - } while (num_rec); + } while (mlxsw_sp_router_rauhtd_is_full(rauhtd_pl)); rtnl_unlock(); kfree(rauhtd_pl); @@ -862,7 +868,7 @@ static void mlxsw_sp_router_neighs_update_nh(struct mlxsw_sp *mlxsw_sp) * is active regardless of the traffic. */ if (!list_empty(&neigh_entry->nexthop_list)) - neigh_event_send(neigh_entry->n, NULL); + neigh_event_send(neigh_entry->key.n, NULL); } rtnl_unlock(); } @@ -908,9 +914,9 @@ static void mlxsw_sp_router_probe_unresolved_nexthops(struct work_struct *work) rtnl_lock(); list_for_each_entry(neigh_entry, &mlxsw_sp->router.nexthop_neighs_list, nexthop_neighs_list_node) { - if (!(neigh_entry->n->nud_state & NUD_VALID) && + if (!(neigh_entry->key.n->nud_state & NUD_VALID) && !list_empty(&neigh_entry->nexthop_list)) - neigh_event_send(neigh_entry->n, NULL); + neigh_event_send(neigh_entry->key.n, NULL); } rtnl_unlock(); @@ -927,7 +933,7 @@ static void mlxsw_sp_router_neigh_update_hw(struct work_struct *work) { struct mlxsw_sp_neigh_entry *neigh_entry = container_of(work, struct mlxsw_sp_neigh_entry, dw.work); - struct neighbour *n = neigh_entry->n; + struct neighbour *n = neigh_entry->key.n; struct mlxsw_sp_port *mlxsw_sp_port = neigh_entry->mlxsw_sp_port; struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; char rauht_pl[MLXSW_REG_RAUHT_LEN]; @@ -1030,11 +1036,8 @@ int mlxsw_sp_router_netevent_event(struct notifier_block *unused, mlxsw_sp = mlxsw_sp_port->mlxsw_sp; dip = ntohl(*((__be32 *) n->primary_key)); - neigh_entry = mlxsw_sp_neigh_entry_lookup(mlxsw_sp, - &dip, - sizeof(__be32), - dev); - if (WARN_ON(!neigh_entry) || WARN_ON(neigh_entry->n != n)) { + neigh_entry = mlxsw_sp_neigh_entry_lookup(mlxsw_sp, n); + if (WARN_ON(!neigh_entry)) { mlxsw_sp_port_dev_put(mlxsw_sp_port); return NOTIFY_DONE; } @@ -1343,33 +1346,26 @@ static int mlxsw_sp_nexthop_init(struct mlxsw_sp *mlxsw_sp, struct fib_nh *fib_nh) { struct mlxsw_sp_neigh_entry *neigh_entry; - u32 gwip = ntohl(fib_nh->nh_gw); struct net_device *dev = fib_nh->nh_dev; struct neighbour *n; u8 nud_state; - neigh_entry = mlxsw_sp_neigh_entry_lookup(mlxsw_sp, &gwip, - sizeof(gwip), dev); - if (!neigh_entry) { - __be32 gwipn = htonl(gwip); - - n = neigh_create(&arp_tbl, &gwipn, dev); + /* Take a reference of neigh here ensuring that neigh would + * not be detructed before the nexthop entry is finished. + * The reference is taken either in neigh_lookup() or + * in neith_create() in case n is not found. + */ + n = neigh_lookup(&arp_tbl, &fib_nh->nh_gw, dev); + if (!n) { + n = neigh_create(&arp_tbl, &fib_nh->nh_gw, dev); if (IS_ERR(n)) return PTR_ERR(n); neigh_event_send(n, NULL); - neigh_entry = mlxsw_sp_neigh_entry_lookup(mlxsw_sp, &gwip, - sizeof(gwip), dev); - if (!neigh_entry) { - neigh_release(n); - return -EINVAL; - } - } else { - /* Take a reference of neigh here ensuring that neigh would - * not be detructed before the nexthop entry is finished. - * The second branch takes the reference in neith_create() - */ - n = neigh_entry->n; - neigh_clone(n); + } + neigh_entry = mlxsw_sp_neigh_entry_lookup(mlxsw_sp, n); + if (!neigh_entry) { + neigh_release(n); + return -EINVAL; } /* If that is the first nexthop connected to that neigh, add to @@ -1403,7 +1399,7 @@ static void mlxsw_sp_nexthop_fini(struct mlxsw_sp *mlxsw_sp, if (list_empty(&nh->neigh_entry->nexthop_list)) list_del(&nh->neigh_entry->nexthop_neighs_list_node); - neigh_release(neigh_entry->n); + neigh_release(neigh_entry->key.n); } static struct mlxsw_sp_nexthop_group * @@ -1463,11 +1459,11 @@ static bool mlxsw_sp_nexthop_match(struct mlxsw_sp_nexthop *nh, for (i = 0; i < fi->fib_nhs; i++) { struct fib_nh *fib_nh = &fi->fib_nh[i]; - u32 gwip = ntohl(fib_nh->nh_gw); + struct neighbour *n = nh->neigh_entry->key.n; - if (memcmp(nh->neigh_entry->key.addr, - &gwip, sizeof(u32)) == 0 && - nh->neigh_entry->key.dev == fib_nh->nh_dev) + if (memcmp(n->primary_key, &fib_nh->nh_gw, + sizeof(fib_nh->nh_gw)) == 0 && + n->dev == fib_nh->nh_dev) return true; } return false; @@ -1874,18 +1870,18 @@ static int mlxsw_sp_router_set_abort_trap(struct mlxsw_sp *mlxsw_sp) return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ralue), ralue_pl); } -static void mlxsw_sp_router_fib4_abort(struct mlxsw_sp *mlxsw_sp) +static void mlxsw_sp_router_fib_flush(struct mlxsw_sp *mlxsw_sp) { struct mlxsw_resources *resources; struct mlxsw_sp_fib_entry *fib_entry; struct mlxsw_sp_fib_entry *tmp; struct mlxsw_sp_vr *vr; int i; - int err; resources = mlxsw_core_resources_get(mlxsw_sp->core); for (i = 0; i < resources->max_virtual_routers; i++) { vr = &mlxsw_sp->router.vrs[i]; + if (!vr->used) continue; @@ -1901,6 +1897,13 @@ static void mlxsw_sp_router_fib4_abort(struct mlxsw_sp *mlxsw_sp) break; } } +} + +static void mlxsw_sp_router_fib4_abort(struct mlxsw_sp *mlxsw_sp) +{ + int err; + + mlxsw_sp_router_fib_flush(mlxsw_sp); mlxsw_sp->router.aborted = true; err = mlxsw_sp_router_set_abort_trap(mlxsw_sp); if (err) @@ -1958,6 +1961,9 @@ static int mlxsw_sp_router_fib_event(struct notifier_block *nb, struct fib_entry_notifier_info *fen_info = ptr; int err; + if (!net_eq(fen_info->info.net, &init_net)) + return NOTIFY_DONE; + switch (event) { case FIB_EVENT_ENTRY_ADD: err = mlxsw_sp_router_fib4_add(mlxsw_sp, fen_info); diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_switchdev.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum_switchdev.c index 5e00c79e8133..1e2c8eca3af1 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum_switchdev.c +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum_switchdev.c @@ -929,12 +929,12 @@ static int mlxsw_sp_port_smid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mid, static struct mlxsw_sp_mid *__mlxsw_sp_mc_get(struct mlxsw_sp *mlxsw_sp, const unsigned char *addr, - u16 vid) + u16 fid) { struct mlxsw_sp_mid *mid; list_for_each_entry(mid, &mlxsw_sp->br_mids.list, list) { - if (ether_addr_equal(mid->addr, addr) && mid->vid == vid) + if (ether_addr_equal(mid->addr, addr) && mid->fid == fid) return mid; } return NULL; @@ -942,7 +942,7 @@ static struct mlxsw_sp_mid *__mlxsw_sp_mc_get(struct mlxsw_sp *mlxsw_sp, static struct mlxsw_sp_mid *__mlxsw_sp_mc_alloc(struct mlxsw_sp *mlxsw_sp, const unsigned char *addr, - u16 vid) + u16 fid) { struct mlxsw_sp_mid *mid; u16 mid_idx; @@ -958,7 +958,7 @@ static struct mlxsw_sp_mid *__mlxsw_sp_mc_alloc(struct mlxsw_sp *mlxsw_sp, set_bit(mid_idx, mlxsw_sp->br_mids.mapped); ether_addr_copy(mid->addr, addr); - mid->vid = vid; + mid->fid = fid; mid->mid = mid_idx; mid->ref_count = 0; list_add_tail(&mid->list, &mlxsw_sp->br_mids.list); @@ -991,9 +991,9 @@ static int mlxsw_sp_port_mdb_add(struct mlxsw_sp_port *mlxsw_sp_port, if (switchdev_trans_ph_prepare(trans)) return 0; - mid = __mlxsw_sp_mc_get(mlxsw_sp, mdb->addr, mdb->vid); + mid = __mlxsw_sp_mc_get(mlxsw_sp, mdb->addr, fid); if (!mid) { - mid = __mlxsw_sp_mc_alloc(mlxsw_sp, mdb->addr, mdb->vid); + mid = __mlxsw_sp_mc_alloc(mlxsw_sp, mdb->addr, fid); if (!mid) { netdev_err(dev, "Unable to allocate MC group\n"); return -ENOMEM; @@ -1137,7 +1137,7 @@ static int mlxsw_sp_port_mdb_del(struct mlxsw_sp_port *mlxsw_sp_port, u16 mid_idx; int err = 0; - mid = __mlxsw_sp_mc_get(mlxsw_sp, mdb->addr, mdb->vid); + mid = __mlxsw_sp_mc_get(mlxsw_sp, mdb->addr, fid); if (!mid) { netdev_err(dev, "Unable to remove port from MC DB\n"); return -EINVAL; diff --git a/drivers/net/ethernet/qlogic/qed/qed_hsi.h b/drivers/net/ethernet/qlogic/qed/qed_hsi.h index 72eee29c677f..2777d5bb4380 100644 --- a/drivers/net/ethernet/qlogic/qed/qed_hsi.h +++ b/drivers/net/ethernet/qlogic/qed/qed_hsi.h @@ -727,9 +727,6 @@ struct core_tx_bd_flags { #define CORE_TX_BD_FLAGS_L4_PROTOCOL_SHIFT 6 #define CORE_TX_BD_FLAGS_L4_PSEUDO_CSUM_MODE_MASK 0x1 #define CORE_TX_BD_FLAGS_L4_PSEUDO_CSUM_MODE_SHIFT 7 -#define CORE_TX_BD_FLAGS_ROCE_FLAV_MASK 0x1 -#define CORE_TX_BD_FLAGS_ROCE_FLAV_SHIFT 12 - }; struct core_tx_bd { diff --git a/drivers/net/ethernet/qlogic/qed/qed_ll2.c b/drivers/net/ethernet/qlogic/qed/qed_ll2.c index 63e1a1b0ef8e..f95385cbbd40 100644 --- a/drivers/net/ethernet/qlogic/qed/qed_ll2.c +++ b/drivers/net/ethernet/qlogic/qed/qed_ll2.c @@ -1119,6 +1119,7 @@ static void qed_ll2_prepare_tx_packet_set_bd(struct qed_hwfn *p_hwfn, start_bd->bd_flags.as_bitfield |= CORE_TX_BD_FLAGS_START_BD_MASK << CORE_TX_BD_FLAGS_START_BD_SHIFT; SET_FIELD(start_bd->bitfield0, CORE_TX_BD_NBDS, num_of_bds); + SET_FIELD(start_bd->bitfield0, CORE_TX_BD_ROCE_FLAV, type); DMA_REGPAIR_LE(start_bd->addr, first_frag); start_bd->nbytes = cpu_to_le16(first_frag_len); diff --git a/drivers/net/ethernet/qlogic/qed/qed_main.c b/drivers/net/ethernet/qlogic/qed/qed_main.c index c418360ba02a..333c7442e48a 100644 --- a/drivers/net/ethernet/qlogic/qed/qed_main.c +++ b/drivers/net/ethernet/qlogic/qed/qed_main.c @@ -839,20 +839,19 @@ static void qed_update_pf_params(struct qed_dev *cdev, { int i; + if (IS_ENABLED(CONFIG_QED_RDMA)) { + params->rdma_pf_params.num_qps = QED_ROCE_QPS; + params->rdma_pf_params.min_dpis = QED_ROCE_DPIS; + /* divide by 3 the MRs to avoid MF ILT overflow */ + params->rdma_pf_params.num_mrs = RDMA_MAX_TIDS; + params->rdma_pf_params.gl_pi = QED_ROCE_PROTOCOL_INDEX; + } + for (i = 0; i < cdev->num_hwfns; i++) { struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; p_hwfn->pf_params = *params; } - - if (!IS_ENABLED(CONFIG_QED_RDMA)) - return; - - params->rdma_pf_params.num_qps = QED_ROCE_QPS; - params->rdma_pf_params.min_dpis = QED_ROCE_DPIS; - /* divide by 3 the MRs to avoid MF ILT overflow */ - params->rdma_pf_params.num_mrs = RDMA_MAX_TIDS; - params->rdma_pf_params.gl_pi = QED_ROCE_PROTOCOL_INDEX; } static int qed_slowpath_start(struct qed_dev *cdev, diff --git a/drivers/net/ethernet/qlogic/qede/qede_ethtool.c b/drivers/net/ethernet/qlogic/qede/qede_ethtool.c index 12251a1032d1..7567cc464b88 100644 --- a/drivers/net/ethernet/qlogic/qede/qede_ethtool.c +++ b/drivers/net/ethernet/qlogic/qede/qede_ethtool.c @@ -175,16 +175,23 @@ static void qede_get_strings_stats(struct qede_dev *edev, u8 *buf) for (i = 0, k = 0; i < QEDE_QUEUE_CNT(edev); i++) { int tc; - for (j = 0; j < QEDE_NUM_RQSTATS; j++) - sprintf(buf + (k + j) * ETH_GSTRING_LEN, - "%d: %s", i, qede_rqstats_arr[j].string); - k += QEDE_NUM_RQSTATS; - for (tc = 0; tc < edev->num_tc; tc++) { - for (j = 0; j < QEDE_NUM_TQSTATS; j++) + if (edev->fp_array[i].type & QEDE_FASTPATH_RX) { + for (j = 0; j < QEDE_NUM_RQSTATS; j++) sprintf(buf + (k + j) * ETH_GSTRING_LEN, - "%d.%d: %s", i, tc, - qede_tqstats_arr[j].string); - k += QEDE_NUM_TQSTATS; + "%d: %s", i, + qede_rqstats_arr[j].string); + k += QEDE_NUM_RQSTATS; + } + + if (edev->fp_array[i].type & QEDE_FASTPATH_TX) { + for (tc = 0; tc < edev->num_tc; tc++) { + for (j = 0; j < QEDE_NUM_TQSTATS; j++) + sprintf(buf + (k + j) * + ETH_GSTRING_LEN, + "%d.%d: %s", i, tc, + qede_tqstats_arr[j].string); + k += QEDE_NUM_TQSTATS; + } } } diff --git a/drivers/net/ethernet/qlogic/qede/qede_main.c b/drivers/net/ethernet/qlogic/qede/qede_main.c index 7def29aaf65c..85f46dbecd5b 100644 --- a/drivers/net/ethernet/qlogic/qede/qede_main.c +++ b/drivers/net/ethernet/qlogic/qede/qede_main.c @@ -2839,7 +2839,7 @@ static int qede_alloc_sge_mem(struct qede_dev *edev, struct qede_rx_queue *rxq) } mapping = dma_map_page(&edev->pdev->dev, replace_buf->data, 0, - rxq->rx_buf_size, DMA_FROM_DEVICE); + PAGE_SIZE, DMA_FROM_DEVICE); if (unlikely(dma_mapping_error(&edev->pdev->dev, mapping))) { DP_NOTICE(edev, "Failed to map TPA replacement buffer\n"); diff --git a/drivers/net/ethernet/qualcomm/emac/emac-mac.c b/drivers/net/ethernet/qualcomm/emac/emac-mac.c index 6fb3bee904d3..0b4deb31e742 100644 --- a/drivers/net/ethernet/qualcomm/emac/emac-mac.c +++ b/drivers/net/ethernet/qualcomm/emac/emac-mac.c @@ -575,10 +575,11 @@ void emac_mac_start(struct emac_adapter *adpt) mac |= TXEN | RXEN; /* enable RX/TX */ - /* We don't have ethtool support yet, so force flow-control mode - * to 'full' always. - */ - mac |= TXFC | RXFC; + /* Configure MAC flow control to match the PHY's settings. */ + if (phydev->pause) + mac |= RXFC; + if (phydev->pause != phydev->asym_pause) + mac |= TXFC; /* setup link speed */ mac &= ~SPEED_MASK; @@ -1003,6 +1004,12 @@ int emac_mac_up(struct emac_adapter *adpt) writel((u32)~DIS_INT, adpt->base + EMAC_INT_STATUS); writel(adpt->irq.mask, adpt->base + EMAC_INT_MASK); + /* Enable pause frames. Without this feature, the EMAC has been shown + * to receive (and drop) frames with FCS errors at gigabit connections. + */ + adpt->phydev->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; + adpt->phydev->advertising |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; + adpt->phydev->irq = PHY_IGNORE_INTERRUPT; phy_start(adpt->phydev); diff --git a/drivers/net/ethernet/qualcomm/emac/emac-phy.c b/drivers/net/ethernet/qualcomm/emac/emac-phy.c index da4e90db4d98..99a14df28b96 100644 --- a/drivers/net/ethernet/qualcomm/emac/emac-phy.c +++ b/drivers/net/ethernet/qualcomm/emac/emac-phy.c @@ -212,6 +212,7 @@ int emac_phy_config(struct platform_device *pdev, struct emac_adapter *adpt) phy_np = of_parse_phandle(np, "phy-handle", 0); adpt->phydev = of_phy_find_device(phy_np); + of_node_put(phy_np); } if (!adpt->phydev) { diff --git a/drivers/net/ethernet/qualcomm/emac/emac-sgmii.c b/drivers/net/ethernet/qualcomm/emac/emac-sgmii.c index 75c1b530e39e..72fe343c7a36 100644 --- a/drivers/net/ethernet/qualcomm/emac/emac-sgmii.c +++ b/drivers/net/ethernet/qualcomm/emac/emac-sgmii.c @@ -421,7 +421,7 @@ static const struct emac_reg_write sgmii_v2_laned[] = { /* CDR Settings */ {EMAC_SGMII_LN_UCDR_FO_GAIN_MODE0, UCDR_STEP_BY_TWO_MODE0 | UCDR_xO_GAIN_MODE(10)}, - {EMAC_SGMII_LN_UCDR_SO_GAIN_MODE0, UCDR_xO_GAIN_MODE(6)}, + {EMAC_SGMII_LN_UCDR_SO_GAIN_MODE0, UCDR_xO_GAIN_MODE(0)}, {EMAC_SGMII_LN_UCDR_SO_CONFIG, UCDR_ENABLE | UCDR_SO_SATURATION(12)}, /* TX/RX Settings */ diff --git a/drivers/net/ethernet/qualcomm/emac/emac.c b/drivers/net/ethernet/qualcomm/emac/emac.c index 4fede4b86538..57b35aeac51a 100644 --- a/drivers/net/ethernet/qualcomm/emac/emac.c +++ b/drivers/net/ethernet/qualcomm/emac/emac.c @@ -711,6 +711,8 @@ static int emac_probe(struct platform_device *pdev) err_undo_napi: netif_napi_del(&adpt->rx_q.napi); err_undo_mdiobus: + if (!has_acpi_companion(&pdev->dev)) + put_device(&adpt->phydev->mdio.dev); mdiobus_unregister(adpt->mii_bus); err_undo_clocks: emac_clks_teardown(adpt); @@ -730,6 +732,8 @@ static int emac_remove(struct platform_device *pdev) emac_clks_teardown(adpt); + if (!has_acpi_companion(&pdev->dev)) + put_device(&adpt->phydev->mdio.dev); mdiobus_unregister(adpt->mii_bus); free_netdev(netdev); diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index 630536bc72f9..d6a217874a8b 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -1008,20 +1008,18 @@ static int ravb_phy_init(struct net_device *ndev) of_node_put(pn); if (!phydev) { netdev_err(ndev, "failed to connect PHY\n"); - return -ENOENT; + err = -ENOENT; + goto err_deregister_fixed_link; } /* This driver only support 10/100Mbit speeds on Gen3 * at this time. */ if (priv->chip_id == RCAR_GEN3) { - int err; - err = phy_set_max_speed(phydev, SPEED_100); if (err) { netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n"); - phy_disconnect(phydev); - return err; + goto err_phy_disconnect; } netdev_info(ndev, "limited PHY to 100Mbit/s\n"); @@ -1033,6 +1031,14 @@ static int ravb_phy_init(struct net_device *ndev) phy_attached_info(phydev); return 0; + +err_phy_disconnect: + phy_disconnect(phydev); +err_deregister_fixed_link: + if (of_phy_is_fixed_link(np)) + of_phy_deregister_fixed_link(np); + + return err; } /* PHY control start function */ @@ -1634,6 +1640,7 @@ static void ravb_set_rx_mode(struct net_device *ndev) /* Device close function for Ethernet AVB */ static int ravb_close(struct net_device *ndev) { + struct device_node *np = ndev->dev.parent->of_node; struct ravb_private *priv = netdev_priv(ndev); struct ravb_tstamp_skb *ts_skb, *ts_skb2; @@ -1663,6 +1670,8 @@ static int ravb_close(struct net_device *ndev) if (ndev->phydev) { phy_stop(ndev->phydev); phy_disconnect(ndev->phydev); + if (of_phy_is_fixed_link(np)) + of_phy_deregister_fixed_link(np); } if (priv->chip_id != RCAR_GEN2) { diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c index 05b0dc55de77..1a92de705199 100644 --- a/drivers/net/ethernet/renesas/sh_eth.c +++ b/drivers/net/ethernet/renesas/sh_eth.c @@ -518,7 +518,7 @@ static struct sh_eth_cpu_data r7s72100_data = { .ecsr_value = ECSR_ICD, .ecsipr_value = ECSIPR_ICDIP, - .eesipr_value = 0xff7f009f, + .eesipr_value = 0xe77f009f, .tx_check = EESR_TC1 | EESR_FTC, .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | diff --git a/drivers/net/ethernet/sfc/efx.c b/drivers/net/ethernet/sfc/efx.c index 3cf3557106c2..6b89e4a7b164 100644 --- a/drivers/net/ethernet/sfc/efx.c +++ b/drivers/net/ethernet/sfc/efx.c @@ -485,6 +485,9 @@ efx_copy_channel(const struct efx_channel *old_channel) *channel = *old_channel; channel->napi_dev = NULL; + INIT_HLIST_NODE(&channel->napi_str.napi_hash_node); + channel->napi_str.napi_id = 0; + channel->napi_str.state = 0; memset(&channel->eventq, 0, sizeof(channel->eventq)); for (j = 0; j < EFX_TXQ_TYPES; j++) { diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig index 3818c5e06eba..4b78168a5f3c 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig @@ -107,7 +107,7 @@ config DWMAC_STI config DWMAC_STM32 tristate "STM32 DWMAC support" default ARCH_STM32 - depends on OF && HAS_IOMEM + depends on OF && HAS_IOMEM && (ARCH_STM32 || COMPILE_TEST) select MFD_SYSCON ---help--- Support for ethernet controller on STM32 SOCs. diff --git a/drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c b/drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c index 2920e2ee3864..489ef146201e 100644 --- a/drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c +++ b/drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c @@ -63,8 +63,8 @@ #define TSE_PCS_SGMII_LINK_TIMER_0 0x0D40 #define TSE_PCS_SGMII_LINK_TIMER_1 0x0003 #define TSE_PCS_SW_RESET_TIMEOUT 100 -#define TSE_PCS_USE_SGMII_AN_MASK BIT(2) -#define TSE_PCS_USE_SGMII_ENA BIT(1) +#define TSE_PCS_USE_SGMII_AN_MASK BIT(1) +#define TSE_PCS_USE_SGMII_ENA BIT(0) #define SGMII_ADAPTER_CTRL_REG 0x00 #define SGMII_ADAPTER_DISABLE 0x0001 diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h index d3292c4a6eda..6d2de4e01f6d 100644 --- a/drivers/net/ethernet/stmicro/stmmac/common.h +++ b/drivers/net/ethernet/stmicro/stmmac/common.h @@ -120,14 +120,17 @@ struct stmmac_extra_stats { unsigned long ip_csum_bypassed; unsigned long ipv4_pkt_rcvd; unsigned long ipv6_pkt_rcvd; - unsigned long rx_msg_type_ext_no_ptp; - unsigned long rx_msg_type_sync; - unsigned long rx_msg_type_follow_up; - unsigned long rx_msg_type_delay_req; - unsigned long rx_msg_type_delay_resp; - unsigned long rx_msg_type_pdelay_req; - unsigned long rx_msg_type_pdelay_resp; - unsigned long rx_msg_type_pdelay_follow_up; + unsigned long no_ptp_rx_msg_type_ext; + unsigned long ptp_rx_msg_type_sync; + unsigned long ptp_rx_msg_type_follow_up; + unsigned long ptp_rx_msg_type_delay_req; + unsigned long ptp_rx_msg_type_delay_resp; + unsigned long ptp_rx_msg_type_pdelay_req; + unsigned long ptp_rx_msg_type_pdelay_resp; + unsigned long ptp_rx_msg_type_pdelay_follow_up; + unsigned long ptp_rx_msg_type_announce; + unsigned long ptp_rx_msg_type_management; + unsigned long ptp_rx_msg_pkt_reserved_type; unsigned long ptp_frame_type; unsigned long ptp_ver; unsigned long timestamp_dropped; @@ -482,11 +485,12 @@ struct stmmac_ops { /* PTP and HW Timer helpers */ struct stmmac_hwtimestamp { void (*config_hw_tstamping) (void __iomem *ioaddr, u32 data); - u32 (*config_sub_second_increment) (void __iomem *ioaddr, u32 clk_rate); + u32 (*config_sub_second_increment)(void __iomem *ioaddr, u32 ptp_clock, + int gmac4); int (*init_systime) (void __iomem *ioaddr, u32 sec, u32 nsec); int (*config_addend) (void __iomem *ioaddr, u32 addend); int (*adjust_systime) (void __iomem *ioaddr, u32 sec, u32 nsec, - int add_sub); + int add_sub, int gmac4); u64(*get_systime) (void __iomem *ioaddr); }; diff --git a/drivers/net/ethernet/stmicro/stmmac/descs.h b/drivers/net/ethernet/stmicro/stmmac/descs.h index 2e4c171a2b41..e3c86d422109 100644 --- a/drivers/net/ethernet/stmicro/stmmac/descs.h +++ b/drivers/net/ethernet/stmicro/stmmac/descs.h @@ -155,14 +155,18 @@ #define ERDES4_L3_L4_FILT_NO_MATCH_MASK GENMASK(27, 26) /* Extended RDES4 message type definitions */ -#define RDES_EXT_NO_PTP 0 -#define RDES_EXT_SYNC 1 -#define RDES_EXT_FOLLOW_UP 2 -#define RDES_EXT_DELAY_REQ 3 -#define RDES_EXT_DELAY_RESP 4 -#define RDES_EXT_PDELAY_REQ 5 -#define RDES_EXT_PDELAY_RESP 6 -#define RDES_EXT_PDELAY_FOLLOW_UP 7 +#define RDES_EXT_NO_PTP 0x0 +#define RDES_EXT_SYNC 0x1 +#define RDES_EXT_FOLLOW_UP 0x2 +#define RDES_EXT_DELAY_REQ 0x3 +#define RDES_EXT_DELAY_RESP 0x4 +#define RDES_EXT_PDELAY_REQ 0x5 +#define RDES_EXT_PDELAY_RESP 0x6 +#define RDES_EXT_PDELAY_FOLLOW_UP 0x7 +#define RDES_PTP_ANNOUNCE 0x8 +#define RDES_PTP_MANAGEMENT 0x9 +#define RDES_PTP_SIGNALING 0xa +#define RDES_PTP_PKT_RESERVED_TYPE 0xf /* Basic descriptor structure for normal and alternate descriptors */ struct dma_desc { diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c index b1e5f24708c9..e6e6c2fcc4b7 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c @@ -50,10 +50,23 @@ static int dwmac_generic_probe(struct platform_device *pdev) if (plat_dat->init) { ret = plat_dat->init(pdev, plat_dat->bsp_priv); if (ret) - return ret; + goto err_remove_config_dt; } - return stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); + ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); + if (ret) + goto err_exit; + + return 0; + +err_exit: + if (plat_dat->exit) + plat_dat->exit(pdev, plat_dat->bsp_priv); +err_remove_config_dt: + if (pdev->dev.of_node) + stmmac_remove_config_dt(pdev, plat_dat); + + return ret; } static const struct of_device_id dwmac_generic_match[] = { diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c index 36d3355f2fb0..866444b6c82f 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c @@ -271,15 +271,17 @@ static int ipq806x_gmac_probe(struct platform_device *pdev) return PTR_ERR(plat_dat); gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL); - if (!gmac) - return -ENOMEM; + if (!gmac) { + err = -ENOMEM; + goto err_remove_config_dt; + } gmac->pdev = pdev; err = ipq806x_gmac_of_parse(gmac); if (err) { dev_err(dev, "device tree parsing error\n"); - return err; + goto err_remove_config_dt; } regmap_write(gmac->qsgmii_csr, QSGMII_PCS_CAL_LCKDT_CTL, @@ -300,7 +302,8 @@ static int ipq806x_gmac_probe(struct platform_device *pdev) default: dev_err(&pdev->dev, "Unsupported PHY mode: \"%s\"\n", phy_modes(gmac->phy_mode)); - return -EINVAL; + err = -EINVAL; + goto err_remove_config_dt; } regmap_write(gmac->nss_common, NSS_COMMON_GMAC_CTL(gmac->id), val); @@ -319,7 +322,8 @@ static int ipq806x_gmac_probe(struct platform_device *pdev) default: dev_err(&pdev->dev, "Unsupported PHY mode: \"%s\"\n", phy_modes(gmac->phy_mode)); - return -EINVAL; + err = -EINVAL; + goto err_remove_config_dt; } regmap_write(gmac->nss_common, NSS_COMMON_CLK_SRC_CTRL, val); @@ -346,7 +350,16 @@ static int ipq806x_gmac_probe(struct platform_device *pdev) plat_dat->bsp_priv = gmac; plat_dat->fix_mac_speed = ipq806x_gmac_fix_mac_speed; - return stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); + err = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); + if (err) + goto err_remove_config_dt; + + return 0; + +err_remove_config_dt: + stmmac_remove_config_dt(pdev, plat_dat); + + return err; } static const struct of_device_id ipq806x_gmac_dwmac_match[] = { diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-lpc18xx.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-lpc18xx.c index 78e9d1861896..3d3f43d91b98 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-lpc18xx.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-lpc18xx.c @@ -46,7 +46,8 @@ static int lpc18xx_dwmac_probe(struct platform_device *pdev) reg = syscon_regmap_lookup_by_compatible("nxp,lpc1850-creg"); if (IS_ERR(reg)) { dev_err(&pdev->dev, "syscon lookup failed\n"); - return PTR_ERR(reg); + ret = PTR_ERR(reg); + goto err_remove_config_dt; } if (plat_dat->interface == PHY_INTERFACE_MODE_MII) { @@ -55,13 +56,23 @@ static int lpc18xx_dwmac_probe(struct platform_device *pdev) ethmode = LPC18XX_CREG_CREG6_ETHMODE_RMII; } else { dev_err(&pdev->dev, "Only MII and RMII mode supported\n"); - return -EINVAL; + ret = -EINVAL; + goto err_remove_config_dt; } regmap_update_bits(reg, LPC18XX_CREG_CREG6, LPC18XX_CREG_CREG6_ETHMODE_MASK, ethmode); - return stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); + ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); + if (ret) + goto err_remove_config_dt; + + return 0; + +err_remove_config_dt: + stmmac_remove_config_dt(pdev, plat_dat); + + return ret; } static const struct of_device_id lpc18xx_dwmac_match[] = { diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c index 309d99536a2c..7fdd1760a74c 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c @@ -64,18 +64,31 @@ static int meson6_dwmac_probe(struct platform_device *pdev) return PTR_ERR(plat_dat); dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL); - if (!dwmac) - return -ENOMEM; + if (!dwmac) { + ret = -ENOMEM; + goto err_remove_config_dt; + } res = platform_get_resource(pdev, IORESOURCE_MEM, 1); dwmac->reg = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(dwmac->reg)) - return PTR_ERR(dwmac->reg); + if (IS_ERR(dwmac->reg)) { + ret = PTR_ERR(dwmac->reg); + goto err_remove_config_dt; + } plat_dat->bsp_priv = dwmac; plat_dat->fix_mac_speed = meson6_dwmac_fix_mac_speed; - return stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); + ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); + if (ret) + goto err_remove_config_dt; + + return 0; + +err_remove_config_dt: + stmmac_remove_config_dt(pdev, plat_dat); + + return ret; } static const struct of_device_id meson6_dwmac_match[] = { diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c index 250e4ceafc8d..ffaed1f35efe 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c @@ -264,32 +264,48 @@ static int meson8b_dwmac_probe(struct platform_device *pdev) return PTR_ERR(plat_dat); dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL); - if (!dwmac) - return -ENOMEM; + if (!dwmac) { + ret = -ENOMEM; + goto err_remove_config_dt; + } res = platform_get_resource(pdev, IORESOURCE_MEM, 1); dwmac->regs = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(dwmac->regs)) - return PTR_ERR(dwmac->regs); + if (IS_ERR(dwmac->regs)) { + ret = PTR_ERR(dwmac->regs); + goto err_remove_config_dt; + } dwmac->pdev = pdev; dwmac->phy_mode = of_get_phy_mode(pdev->dev.of_node); if (dwmac->phy_mode < 0) { dev_err(&pdev->dev, "missing phy-mode property\n"); - return -EINVAL; + ret = -EINVAL; + goto err_remove_config_dt; } ret = meson8b_init_clk(dwmac); if (ret) - return ret; + goto err_remove_config_dt; ret = meson8b_init_prg_eth(dwmac); if (ret) - return ret; + goto err_remove_config_dt; plat_dat->bsp_priv = dwmac; - return stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); + ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); + if (ret) + goto err_clk_disable; + + return 0; + +err_clk_disable: + clk_disable_unprepare(dwmac->m25_div_clk); +err_remove_config_dt: + stmmac_remove_config_dt(pdev, plat_dat); + + return ret; } static int meson8b_dwmac_remove(struct platform_device *pdev) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c index 3740a4417fa0..d80c88bd2bba 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c @@ -981,14 +981,27 @@ static int rk_gmac_probe(struct platform_device *pdev) plat_dat->resume = rk_gmac_resume; plat_dat->bsp_priv = rk_gmac_setup(pdev, data); - if (IS_ERR(plat_dat->bsp_priv)) - return PTR_ERR(plat_dat->bsp_priv); + if (IS_ERR(plat_dat->bsp_priv)) { + ret = PTR_ERR(plat_dat->bsp_priv); + goto err_remove_config_dt; + } ret = rk_gmac_init(pdev, plat_dat->bsp_priv); if (ret) - return ret; + goto err_remove_config_dt; + + ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); + if (ret) + goto err_gmac_exit; + + return 0; + +err_gmac_exit: + rk_gmac_exit(pdev, plat_dat->bsp_priv); +err_remove_config_dt: + stmmac_remove_config_dt(pdev, plat_dat); - return stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); + return ret; } static const struct of_device_id rk_gmac_dwmac_match[] = { diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c index bec6963ac71e..0c420e97de1e 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c @@ -304,6 +304,8 @@ static int socfpga_dwmac_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; int ret; struct socfpga_dwmac *dwmac; + struct net_device *ndev; + struct stmmac_priv *stpriv; ret = stmmac_get_platform_resources(pdev, &stmmac_res); if (ret) @@ -314,32 +316,43 @@ static int socfpga_dwmac_probe(struct platform_device *pdev) return PTR_ERR(plat_dat); dwmac = devm_kzalloc(dev, sizeof(*dwmac), GFP_KERNEL); - if (!dwmac) - return -ENOMEM; + if (!dwmac) { + ret = -ENOMEM; + goto err_remove_config_dt; + } ret = socfpga_dwmac_parse_data(dwmac, dev); if (ret) { dev_err(dev, "Unable to parse OF data\n"); - return ret; + goto err_remove_config_dt; } plat_dat->bsp_priv = dwmac; plat_dat->fix_mac_speed = socfpga_dwmac_fix_mac_speed; ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); + if (ret) + goto err_remove_config_dt; - if (!ret) { - struct net_device *ndev = platform_get_drvdata(pdev); - struct stmmac_priv *stpriv = netdev_priv(ndev); + ndev = platform_get_drvdata(pdev); + stpriv = netdev_priv(ndev); - /* The socfpga driver needs to control the stmmac reset to - * set the phy mode. Create a copy of the core reset handel - * so it can be used by the driver later. - */ - dwmac->stmmac_rst = stpriv->stmmac_rst; + /* The socfpga driver needs to control the stmmac reset to set the phy + * mode. Create a copy of the core reset handle so it can be used by + * the driver later. + */ + dwmac->stmmac_rst = stpriv->stmmac_rst; - ret = socfpga_dwmac_set_phy_mode(dwmac); - } + ret = socfpga_dwmac_set_phy_mode(dwmac); + if (ret) + goto err_dvr_remove; + + return 0; + +err_dvr_remove: + stmmac_dvr_remove(&pdev->dev); +err_remove_config_dt: + stmmac_remove_config_dt(pdev, plat_dat); return ret; } diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c index 58c05acc2aab..060b98c37a85 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c @@ -345,13 +345,15 @@ static int sti_dwmac_probe(struct platform_device *pdev) return PTR_ERR(plat_dat); dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL); - if (!dwmac) - return -ENOMEM; + if (!dwmac) { + ret = -ENOMEM; + goto err_remove_config_dt; + } ret = sti_dwmac_parse_data(dwmac, pdev); if (ret) { dev_err(&pdev->dev, "Unable to parse OF data\n"); - return ret; + goto err_remove_config_dt; } dwmac->fix_retime_src = data->fix_retime_src; @@ -363,9 +365,20 @@ static int sti_dwmac_probe(struct platform_device *pdev) ret = sti_dwmac_init(pdev, plat_dat->bsp_priv); if (ret) - return ret; + goto err_remove_config_dt; + + ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); + if (ret) + goto err_dwmac_exit; + + return 0; + +err_dwmac_exit: + sti_dwmac_exit(pdev, plat_dat->bsp_priv); +err_remove_config_dt: + stmmac_remove_config_dt(pdev, plat_dat); - return stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); + return ret; } static const struct sti_dwmac_of_data stih4xx_dwmac_data = { diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c index e5a926b8bee7..61cb24810d10 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c @@ -107,24 +107,33 @@ static int stm32_dwmac_probe(struct platform_device *pdev) return PTR_ERR(plat_dat); dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL); - if (!dwmac) - return -ENOMEM; + if (!dwmac) { + ret = -ENOMEM; + goto err_remove_config_dt; + } ret = stm32_dwmac_parse_data(dwmac, &pdev->dev); if (ret) { dev_err(&pdev->dev, "Unable to parse OF data\n"); - return ret; + goto err_remove_config_dt; } plat_dat->bsp_priv = dwmac; ret = stm32_dwmac_init(plat_dat); if (ret) - return ret; + goto err_remove_config_dt; ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); if (ret) - stm32_dwmac_clk_disable(dwmac); + goto err_clk_disable; + + return 0; + +err_clk_disable: + stm32_dwmac_clk_disable(dwmac); +err_remove_config_dt: + stmmac_remove_config_dt(pdev, plat_dat); return ret; } diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c index adff46375a32..d07520fb969e 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c @@ -120,22 +120,27 @@ static int sun7i_gmac_probe(struct platform_device *pdev) return PTR_ERR(plat_dat); gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL); - if (!gmac) - return -ENOMEM; + if (!gmac) { + ret = -ENOMEM; + goto err_remove_config_dt; + } gmac->interface = of_get_phy_mode(dev->of_node); gmac->tx_clk = devm_clk_get(dev, "allwinner_gmac_tx"); if (IS_ERR(gmac->tx_clk)) { dev_err(dev, "could not get tx clock\n"); - return PTR_ERR(gmac->tx_clk); + ret = PTR_ERR(gmac->tx_clk); + goto err_remove_config_dt; } /* Optional regulator for PHY */ gmac->regulator = devm_regulator_get_optional(dev, "phy"); if (IS_ERR(gmac->regulator)) { - if (PTR_ERR(gmac->regulator) == -EPROBE_DEFER) - return -EPROBE_DEFER; + if (PTR_ERR(gmac->regulator) == -EPROBE_DEFER) { + ret = -EPROBE_DEFER; + goto err_remove_config_dt; + } dev_info(dev, "no regulator found\n"); gmac->regulator = NULL; } @@ -151,11 +156,18 @@ static int sun7i_gmac_probe(struct platform_device *pdev) ret = sun7i_gmac_init(pdev, plat_dat->bsp_priv); if (ret) - return ret; + goto err_remove_config_dt; ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); if (ret) - sun7i_gmac_exit(pdev, plat_dat->bsp_priv); + goto err_gmac_exit; + + return 0; + +err_gmac_exit: + sun7i_gmac_exit(pdev, plat_dat->bsp_priv); +err_remove_config_dt: + stmmac_remove_config_dt(pdev, plat_dat); return ret; } diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c index a1b17cd7886b..a601f8d43b75 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c @@ -123,22 +123,29 @@ static int dwmac4_wrback_get_rx_status(void *data, struct stmmac_extra_stats *x, x->ipv4_pkt_rcvd++; if (rdes1 & RDES1_IPV6_HEADER) x->ipv6_pkt_rcvd++; - if (message_type == RDES_EXT_SYNC) - x->rx_msg_type_sync++; + + if (message_type == RDES_EXT_NO_PTP) + x->no_ptp_rx_msg_type_ext++; + else if (message_type == RDES_EXT_SYNC) + x->ptp_rx_msg_type_sync++; else if (message_type == RDES_EXT_FOLLOW_UP) - x->rx_msg_type_follow_up++; + x->ptp_rx_msg_type_follow_up++; else if (message_type == RDES_EXT_DELAY_REQ) - x->rx_msg_type_delay_req++; + x->ptp_rx_msg_type_delay_req++; else if (message_type == RDES_EXT_DELAY_RESP) - x->rx_msg_type_delay_resp++; + x->ptp_rx_msg_type_delay_resp++; else if (message_type == RDES_EXT_PDELAY_REQ) - x->rx_msg_type_pdelay_req++; + x->ptp_rx_msg_type_pdelay_req++; else if (message_type == RDES_EXT_PDELAY_RESP) - x->rx_msg_type_pdelay_resp++; + x->ptp_rx_msg_type_pdelay_resp++; else if (message_type == RDES_EXT_PDELAY_FOLLOW_UP) - x->rx_msg_type_pdelay_follow_up++; - else - x->rx_msg_type_ext_no_ptp++; + x->ptp_rx_msg_type_pdelay_follow_up++; + else if (message_type == RDES_PTP_ANNOUNCE) + x->ptp_rx_msg_type_announce++; + else if (message_type == RDES_PTP_MANAGEMENT) + x->ptp_rx_msg_type_management++; + else if (message_type == RDES_PTP_PKT_RESERVED_TYPE) + x->ptp_rx_msg_pkt_reserved_type++; if (rdes1 & RDES1_PTP_PACKET_TYPE) x->ptp_frame_type++; @@ -204,14 +211,18 @@ static void dwmac4_rd_enable_tx_timestamp(struct dma_desc *p) static int dwmac4_wrback_get_tx_timestamp_status(struct dma_desc *p) { - return (p->des3 & TDES3_TIMESTAMP_STATUS) - >> TDES3_TIMESTAMP_STATUS_SHIFT; + /* Context type from W/B descriptor must be zero */ + if (p->des3 & TDES3_CONTEXT_TYPE) + return -EINVAL; + + /* Tx Timestamp Status is 1 so des0 and des1'll have valid values */ + if (p->des3 & TDES3_TIMESTAMP_STATUS) + return 0; + + return 1; } -/* NOTE: For RX CTX bit has to be checked before - * HAVE a specific function for TX and another one for RX - */ -static u64 dwmac4_wrback_get_timestamp(void *desc, u32 ats) +static inline u64 dwmac4_get_timestamp(void *desc, u32 ats) { struct dma_desc *p = (struct dma_desc *)desc; u64 ns; @@ -223,12 +234,54 @@ static u64 dwmac4_wrback_get_timestamp(void *desc, u32 ats) return ns; } -static int dwmac4_context_get_rx_timestamp_status(void *desc, u32 ats) +static int dwmac4_rx_check_timestamp(void *desc) +{ + struct dma_desc *p = (struct dma_desc *)desc; + u32 own, ctxt; + int ret = 1; + + own = p->des3 & RDES3_OWN; + ctxt = ((p->des3 & RDES3_CONTEXT_DESCRIPTOR) + >> RDES3_CONTEXT_DESCRIPTOR_SHIFT); + + if (likely(!own && ctxt)) { + if ((p->des0 == 0xffffffff) && (p->des1 == 0xffffffff)) + /* Corrupted value */ + ret = -EINVAL; + else + /* A valid Timestamp is ready to be read */ + ret = 0; + } + + /* Timestamp not ready */ + return ret; +} + +static int dwmac4_wrback_get_rx_timestamp_status(void *desc, u32 ats) { struct dma_desc *p = (struct dma_desc *)desc; + int ret = -EINVAL; + + /* Get the status from normal w/b descriptor */ + if (likely(p->des3 & TDES3_RS1V)) { + if (likely(p->des1 & RDES1_TIMESTAMP_AVAILABLE)) { + int i = 0; + + /* Check if timestamp is OK from context descriptor */ + do { + ret = dwmac4_rx_check_timestamp(desc); + if (ret < 0) + goto exit; + i++; - return (p->des1 & RDES1_TIMESTAMP_AVAILABLE) - >> RDES1_TIMESTAMP_AVAILABLE_SHIFT; + } while ((ret == 1) || (i < 10)); + + if (i == 10) + ret = -EBUSY; + } + } +exit: + return ret; } static void dwmac4_rd_init_rx_desc(struct dma_desc *p, int disable_rx_ic, @@ -373,8 +426,8 @@ const struct stmmac_desc_ops dwmac4_desc_ops = { .get_rx_frame_len = dwmac4_wrback_get_rx_frame_len, .enable_tx_timestamp = dwmac4_rd_enable_tx_timestamp, .get_tx_timestamp_status = dwmac4_wrback_get_tx_timestamp_status, - .get_timestamp = dwmac4_wrback_get_timestamp, - .get_rx_timestamp_status = dwmac4_context_get_rx_timestamp_status, + .get_rx_timestamp_status = dwmac4_wrback_get_rx_timestamp_status, + .get_timestamp = dwmac4_get_timestamp, .set_tx_ic = dwmac4_rd_set_tx_ic, .prepare_tx_desc = dwmac4_rd_prepare_tx_desc, .prepare_tso_tx_desc = dwmac4_rd_prepare_tso_tx_desc, diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h b/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h index 0902a2edeaa9..9736c505211a 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.h @@ -59,10 +59,13 @@ #define TDES3_CTXT_TCMSSV BIT(26) /* TDES3 Common */ +#define TDES3_RS1V BIT(26) +#define TDES3_RS1V_SHIFT 26 #define TDES3_LAST_DESCRIPTOR BIT(28) #define TDES3_LAST_DESCRIPTOR_SHIFT 28 #define TDES3_FIRST_DESCRIPTOR BIT(29) #define TDES3_CONTEXT_TYPE BIT(30) +#define TDES3_CONTEXT_TYPE_SHIFT 30 /* TDS3 use for both format (read and write back) */ #define TDES3_OWN BIT(31) @@ -117,6 +120,7 @@ #define RDES3_LAST_DESCRIPTOR BIT(28) #define RDES3_FIRST_DESCRIPTOR BIT(29) #define RDES3_CONTEXT_DESCRIPTOR BIT(30) +#define RDES3_CONTEXT_DESCRIPTOR_SHIFT 30 /* RDES3 (read format) */ #define RDES3_BUFFER1_VALID_ADDR BIT(24) diff --git a/drivers/net/ethernet/stmicro/stmmac/enh_desc.c b/drivers/net/ethernet/stmicro/stmmac/enh_desc.c index 38f19c99cf59..e75549327c34 100644 --- a/drivers/net/ethernet/stmicro/stmmac/enh_desc.c +++ b/drivers/net/ethernet/stmicro/stmmac/enh_desc.c @@ -150,22 +150,30 @@ static void enh_desc_get_ext_status(void *data, struct stmmac_extra_stats *x, x->ipv4_pkt_rcvd++; if (rdes4 & ERDES4_IPV6_PKT_RCVD) x->ipv6_pkt_rcvd++; - if (message_type == RDES_EXT_SYNC) - x->rx_msg_type_sync++; + + if (message_type == RDES_EXT_NO_PTP) + x->no_ptp_rx_msg_type_ext++; + else if (message_type == RDES_EXT_SYNC) + x->ptp_rx_msg_type_sync++; else if (message_type == RDES_EXT_FOLLOW_UP) - x->rx_msg_type_follow_up++; + x->ptp_rx_msg_type_follow_up++; else if (message_type == RDES_EXT_DELAY_REQ) - x->rx_msg_type_delay_req++; + x->ptp_rx_msg_type_delay_req++; else if (message_type == RDES_EXT_DELAY_RESP) - x->rx_msg_type_delay_resp++; + x->ptp_rx_msg_type_delay_resp++; else if (message_type == RDES_EXT_PDELAY_REQ) - x->rx_msg_type_pdelay_req++; + x->ptp_rx_msg_type_pdelay_req++; else if (message_type == RDES_EXT_PDELAY_RESP) - x->rx_msg_type_pdelay_resp++; + x->ptp_rx_msg_type_pdelay_resp++; else if (message_type == RDES_EXT_PDELAY_FOLLOW_UP) - x->rx_msg_type_pdelay_follow_up++; - else - x->rx_msg_type_ext_no_ptp++; + x->ptp_rx_msg_type_pdelay_follow_up++; + else if (message_type == RDES_PTP_ANNOUNCE) + x->ptp_rx_msg_type_announce++; + else if (message_type == RDES_PTP_MANAGEMENT) + x->ptp_rx_msg_type_management++; + else if (message_type == RDES_PTP_PKT_RESERVED_TYPE) + x->ptp_rx_msg_pkt_reserved_type++; + if (rdes4 & ERDES4_PTP_FRAME_TYPE) x->ptp_frame_type++; if (rdes4 & ERDES4_PTP_VER) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h b/drivers/net/ethernet/stmicro/stmmac/stmmac.h index b15fc55f1b96..4d2a759b8465 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h @@ -129,6 +129,7 @@ struct stmmac_priv { int irq_wake; spinlock_t ptp_lock; void __iomem *mmcaddr; + void __iomem *ptpaddr; u32 rx_tail_addr; u32 tx_tail_addr; u32 mss; diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c index 1e06173fc9d7..c5d0142adda2 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c @@ -115,14 +115,17 @@ static const struct stmmac_stats stmmac_gstrings_stats[] = { STMMAC_STAT(ip_csum_bypassed), STMMAC_STAT(ipv4_pkt_rcvd), STMMAC_STAT(ipv6_pkt_rcvd), - STMMAC_STAT(rx_msg_type_ext_no_ptp), - STMMAC_STAT(rx_msg_type_sync), - STMMAC_STAT(rx_msg_type_follow_up), - STMMAC_STAT(rx_msg_type_delay_req), - STMMAC_STAT(rx_msg_type_delay_resp), - STMMAC_STAT(rx_msg_type_pdelay_req), - STMMAC_STAT(rx_msg_type_pdelay_resp), - STMMAC_STAT(rx_msg_type_pdelay_follow_up), + STMMAC_STAT(no_ptp_rx_msg_type_ext), + STMMAC_STAT(ptp_rx_msg_type_sync), + STMMAC_STAT(ptp_rx_msg_type_follow_up), + STMMAC_STAT(ptp_rx_msg_type_delay_req), + STMMAC_STAT(ptp_rx_msg_type_delay_resp), + STMMAC_STAT(ptp_rx_msg_type_pdelay_req), + STMMAC_STAT(ptp_rx_msg_type_pdelay_resp), + STMMAC_STAT(ptp_rx_msg_type_pdelay_follow_up), + STMMAC_STAT(ptp_rx_msg_type_announce), + STMMAC_STAT(ptp_rx_msg_type_management), + STMMAC_STAT(ptp_rx_msg_pkt_reserved_type), STMMAC_STAT(ptp_frame_type), STMMAC_STAT(ptp_ver), STMMAC_STAT(timestamp_dropped), diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c index a77f68918010..10d6059b2f26 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c @@ -34,21 +34,29 @@ static void stmmac_config_hw_tstamping(void __iomem *ioaddr, u32 data) } static u32 stmmac_config_sub_second_increment(void __iomem *ioaddr, - u32 ptp_clock) + u32 ptp_clock, int gmac4) { u32 value = readl(ioaddr + PTP_TCR); unsigned long data; - /* Convert the ptp_clock to nano second - * formula = (2/ptp_clock) * 1000000000 - * where, ptp_clock = 50MHz. + /* For GMAC3.x, 4.x versions, convert the ptp_clock to nano second + * formula = (1/ptp_clock) * 1000000000 + * where ptp_clock is 50MHz if fine method is used to update system */ - data = (2000000000ULL / ptp_clock); + if (value & PTP_TCR_TSCFUPDT) + data = (1000000000ULL / 50000000); + else + data = (1000000000ULL / ptp_clock); /* 0.465ns accuracy */ if (!(value & PTP_TCR_TSCTRLSSR)) data = (data * 1000) / 465; + data &= PTP_SSIR_SSINC_MASK; + + if (gmac4) + data = data << GMAC4_PTP_SSIR_SSINC_SHIFT; + writel(data, ioaddr + PTP_SSIR); return data; @@ -104,14 +112,30 @@ static int stmmac_config_addend(void __iomem *ioaddr, u32 addend) } static int stmmac_adjust_systime(void __iomem *ioaddr, u32 sec, u32 nsec, - int add_sub) + int add_sub, int gmac4) { u32 value; int limit; + if (add_sub) { + /* If the new sec value needs to be subtracted with + * the system time, then MAC_STSUR reg should be + * programmed with (2^32 – <new_sec_value>) + */ + if (gmac4) + sec = (100000000ULL - sec); + + value = readl(ioaddr + PTP_TCR); + if (value & PTP_TCR_TSCTRLSSR) + nsec = (PTP_DIGITAL_ROLLOVER_MODE - nsec); + else + nsec = (PTP_BINARY_ROLLOVER_MODE - nsec); + } + writel(sec, ioaddr + PTP_STSUR); - writel(((add_sub << PTP_STNSUR_ADDSUB_SHIFT) | nsec), - ioaddr + PTP_STNSUR); + value = (add_sub << PTP_STNSUR_ADDSUB_SHIFT) | nsec; + writel(value, ioaddr + PTP_STNSUR); + /* issue command to initialize the system time value */ value = readl(ioaddr + PTP_TCR); value |= PTP_TCR_TSUPDT; @@ -134,8 +158,9 @@ static u64 stmmac_get_systime(void __iomem *ioaddr) { u64 ns; + /* Get the TSSS value */ ns = readl(ioaddr + PTP_STNSR); - /* convert sec time value to nanosecond */ + /* Get the TSS and convert sec time value to nanosecond */ ns += readl(ioaddr + PTP_STSR) * 1000000000ULL; return ns; diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index 48e71fad4210..caf069a465f2 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -340,18 +340,17 @@ out: /* stmmac_get_tx_hwtstamp - get HW TX timestamps * @priv: driver private structure - * @entry : descriptor index to be used. + * @p : descriptor pointer * @skb : the socket buffer * Description : * This function will read timestamp from the descriptor & pass it to stack. * and also perform some sanity checks. */ static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, - unsigned int entry, struct sk_buff *skb) + struct dma_desc *p, struct sk_buff *skb) { struct skb_shared_hwtstamps shhwtstamp; u64 ns; - void *desc = NULL; if (!priv->hwts_tx_en) return; @@ -360,58 +359,55 @@ static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) return; - if (priv->adv_ts) - desc = (priv->dma_etx + entry); - else - desc = (priv->dma_tx + entry); - /* check tx tstamp status */ - if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc)) - return; + if (!priv->hw->desc->get_tx_timestamp_status(p)) { + /* get the valid tstamp */ + ns = priv->hw->desc->get_timestamp(p, priv->adv_ts); - /* get the valid tstamp */ - ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts); + memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); + shhwtstamp.hwtstamp = ns_to_ktime(ns); - memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); - shhwtstamp.hwtstamp = ns_to_ktime(ns); - /* pass tstamp to stack */ - skb_tstamp_tx(skb, &shhwtstamp); + netdev_info(priv->dev, "get valid TX hw timestamp %llu\n", ns); + /* pass tstamp to stack */ + skb_tstamp_tx(skb, &shhwtstamp); + } return; } /* stmmac_get_rx_hwtstamp - get HW RX timestamps * @priv: driver private structure - * @entry : descriptor index to be used. + * @p : descriptor pointer + * @np : next descriptor pointer * @skb : the socket buffer * Description : * This function will read received packet's timestamp from the descriptor * and pass it to stack. It also perform some sanity checks. */ -static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, - unsigned int entry, struct sk_buff *skb) +static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p, + struct dma_desc *np, struct sk_buff *skb) { struct skb_shared_hwtstamps *shhwtstamp = NULL; u64 ns; - void *desc = NULL; if (!priv->hwts_rx_en) return; - if (priv->adv_ts) - desc = (priv->dma_erx + entry); - else - desc = (priv->dma_rx + entry); - - /* exit if rx tstamp is not valid */ - if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts)) - return; + /* Check if timestamp is available */ + if (!priv->hw->desc->get_rx_timestamp_status(p, priv->adv_ts)) { + /* For GMAC4, the valid timestamp is from CTX next desc. */ + if (priv->plat->has_gmac4) + ns = priv->hw->desc->get_timestamp(np, priv->adv_ts); + else + ns = priv->hw->desc->get_timestamp(p, priv->adv_ts); - /* get valid tstamp */ - ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts); - shhwtstamp = skb_hwtstamps(skb); - memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); - shhwtstamp->hwtstamp = ns_to_ktime(ns); + netdev_info(priv->dev, "get valid RX hw timestamp %llu\n", ns); + shhwtstamp = skb_hwtstamps(skb); + memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); + shhwtstamp->hwtstamp = ns_to_ktime(ns); + } else { + netdev_err(priv->dev, "cannot get RX hw timestamp\n"); + } } /** @@ -598,17 +594,18 @@ static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr) priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; if (!priv->hwts_tx_en && !priv->hwts_rx_en) - priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0); + priv->hw->ptp->config_hw_tstamping(priv->ptpaddr, 0); else { value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR | tstamp_all | ptp_v2 | ptp_over_ethernet | ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en | ts_master_en | snap_type_sel); - priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value); + priv->hw->ptp->config_hw_tstamping(priv->ptpaddr, value); /* program Sub Second Increment reg */ sec_inc = priv->hw->ptp->config_sub_second_increment( - priv->ioaddr, priv->clk_ptp_rate); + priv->ptpaddr, priv->clk_ptp_rate, + priv->plat->has_gmac4); temp = div_u64(1000000000ULL, sec_inc); /* calculate default added value: @@ -618,14 +615,14 @@ static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr) */ temp = (u64)(temp << 32); priv->default_addend = div_u64(temp, priv->clk_ptp_rate); - priv->hw->ptp->config_addend(priv->ioaddr, + priv->hw->ptp->config_addend(priv->ptpaddr, priv->default_addend); /* initialize system time */ ktime_get_real_ts64(&now); /* lower 32 bits of tv_sec are safe until y2106 */ - priv->hw->ptp->init_systime(priv->ioaddr, (u32)now.tv_sec, + priv->hw->ptp->init_systime(priv->ptpaddr, (u32)now.tv_sec, now.tv_nsec); } @@ -880,6 +877,13 @@ static int stmmac_init_phy(struct net_device *dev) return -ENODEV; } + /* stmmac_adjust_link will change this to PHY_IGNORE_INTERRUPT to avoid + * subsequent PHY polling, make sure we force a link transition if + * we have a UP/DOWN/UP transition + */ + if (phydev->is_pseudo_fixed_link) + phydev->irq = PHY_POLL; + pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)" " Link = %d\n", dev->name, phydev->phy_id, phydev->link); @@ -1333,7 +1337,7 @@ static void stmmac_tx_clean(struct stmmac_priv *priv) priv->dev->stats.tx_packets++; priv->xstats.tx_pkt_n++; } - stmmac_get_tx_hwtstamp(priv, entry, skb); + stmmac_get_tx_hwtstamp(priv, p, skb); } if (likely(priv->tx_skbuff_dma[entry].buf)) { @@ -1479,10 +1483,13 @@ static void stmmac_mmc_setup(struct stmmac_priv *priv) unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; - if (priv->synopsys_id >= DWMAC_CORE_4_00) + if (priv->synopsys_id >= DWMAC_CORE_4_00) { + priv->ptpaddr = priv->ioaddr + PTP_GMAC4_OFFSET; priv->mmcaddr = priv->ioaddr + MMC_GMAC4_OFFSET; - else + } else { + priv->ptpaddr = priv->ioaddr + PTP_GMAC3_X_OFFSET; priv->mmcaddr = priv->ioaddr + MMC_GMAC3_X_OFFSET; + } dwmac_mmc_intr_all_mask(priv->mmcaddr); @@ -2477,7 +2484,7 @@ static int stmmac_rx(struct stmmac_priv *priv, int limit) if (netif_msg_rx_status(priv)) { void *rx_head; - pr_debug("%s: descriptor ring:\n", __func__); + pr_info(">>>>>> %s: descriptor ring:\n", __func__); if (priv->extend_desc) rx_head = (void *)priv->dma_erx; else @@ -2488,6 +2495,7 @@ static int stmmac_rx(struct stmmac_priv *priv, int limit) while (count < limit) { int status; struct dma_desc *p; + struct dma_desc *np; if (priv->extend_desc) p = (struct dma_desc *)(priv->dma_erx + entry); @@ -2507,9 +2515,11 @@ static int stmmac_rx(struct stmmac_priv *priv, int limit) next_entry = priv->cur_rx; if (priv->extend_desc) - prefetch(priv->dma_erx + next_entry); + np = (struct dma_desc *)(priv->dma_erx + next_entry); else - prefetch(priv->dma_rx + next_entry); + np = priv->dma_rx + next_entry; + + prefetch(np); if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status)) priv->hw->desc->rx_extended_status(&priv->dev->stats, @@ -2561,7 +2571,7 @@ static int stmmac_rx(struct stmmac_priv *priv, int limit) frame_len -= ETH_FCS_LEN; if (netif_msg_rx_status(priv)) { - pr_debug("\tdesc: %p [entry %d] buff=0x%x\n", + pr_info("\tdesc: %p [entry %d] buff=0x%x\n", p, entry, des); if (frame_len > ETH_FRAME_LEN) pr_debug("\tframe size %d, COE: %d\n", @@ -2618,13 +2628,13 @@ static int stmmac_rx(struct stmmac_priv *priv, int limit) DMA_FROM_DEVICE); } - stmmac_get_rx_hwtstamp(priv, entry, skb); - if (netif_msg_pktdata(priv)) { pr_debug("frame received (%dbytes)", frame_len); print_pkt(skb->data, frame_len); } + stmmac_get_rx_hwtstamp(priv, p, np, skb); + stmmac_rx_vlan(priv->dev, skb); skb->protocol = eth_type_trans(skb, priv->dev); @@ -3406,7 +3416,6 @@ int stmmac_dvr_remove(struct device *dev) stmmac_set_mac(priv->ioaddr, false); netif_carrier_off(ndev); unregister_netdev(ndev); - of_node_put(priv->plat->phy_node); if (priv->stmmac_rst) reset_control_assert(priv->stmmac_rst); clk_disable_unprepare(priv->pclk); diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c index 0a0d6a86f397..a840818bf4df 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c @@ -200,7 +200,6 @@ static int stmmac_dt_phy(struct plat_stmmacenet_data *plat, /** * stmmac_probe_config_dt - parse device-tree driver parameters * @pdev: platform_device structure - * @plat: driver data platform structure * @mac: MAC address to use * Description: * this function is to read the driver parameters from device-tree and @@ -306,7 +305,7 @@ stmmac_probe_config_dt(struct platform_device *pdev, const char **mac) dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*dma_cfg), GFP_KERNEL); if (!dma_cfg) { - of_node_put(plat->phy_node); + stmmac_remove_config_dt(pdev, plat); return ERR_PTR(-ENOMEM); } plat->dma_cfg = dma_cfg; @@ -329,14 +328,37 @@ stmmac_probe_config_dt(struct platform_device *pdev, const char **mac) return plat; } + +/** + * stmmac_remove_config_dt - undo the effects of stmmac_probe_config_dt() + * @pdev: platform_device structure + * @plat: driver data platform structure + * + * Release resources claimed by stmmac_probe_config_dt(). + */ +void stmmac_remove_config_dt(struct platform_device *pdev, + struct plat_stmmacenet_data *plat) +{ + struct device_node *np = pdev->dev.of_node; + + if (of_phy_is_fixed_link(np)) + of_phy_deregister_fixed_link(np); + of_node_put(plat->phy_node); +} #else struct plat_stmmacenet_data * stmmac_probe_config_dt(struct platform_device *pdev, const char **mac) { return ERR_PTR(-ENOSYS); } + +void stmmac_remove_config_dt(struct platform_device *pdev, + struct plat_stmmacenet_data *plat) +{ +} #endif /* CONFIG_OF */ EXPORT_SYMBOL_GPL(stmmac_probe_config_dt); +EXPORT_SYMBOL_GPL(stmmac_remove_config_dt); int stmmac_get_platform_resources(struct platform_device *pdev, struct stmmac_resources *stmmac_res) @@ -392,10 +414,13 @@ int stmmac_pltfr_remove(struct platform_device *pdev) { struct net_device *ndev = platform_get_drvdata(pdev); struct stmmac_priv *priv = netdev_priv(ndev); + struct plat_stmmacenet_data *plat = priv->plat; int ret = stmmac_dvr_remove(&pdev->dev); - if (priv->plat->exit) - priv->plat->exit(pdev, priv->plat->bsp_priv); + if (plat->exit) + plat->exit(pdev, plat->bsp_priv); + + stmmac_remove_config_dt(pdev, plat); return ret; } diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.h b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.h index 64e147f53a9c..b72eb0de57b7 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.h +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.h @@ -23,6 +23,8 @@ struct plat_stmmacenet_data * stmmac_probe_config_dt(struct platform_device *pdev, const char **mac); +void stmmac_remove_config_dt(struct platform_device *pdev, + struct plat_stmmacenet_data *plat); int stmmac_get_platform_resources(struct platform_device *pdev, struct stmmac_resources *stmmac_res); diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c index 1477471f8d44..3eb281d1db08 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c @@ -54,7 +54,7 @@ static int stmmac_adjust_freq(struct ptp_clock_info *ptp, s32 ppb) spin_lock_irqsave(&priv->ptp_lock, flags); - priv->hw->ptp->config_addend(priv->ioaddr, addend); + priv->hw->ptp->config_addend(priv->ptpaddr, addend); spin_unlock_irqrestore(&priv->ptp_lock, flags); @@ -89,7 +89,8 @@ static int stmmac_adjust_time(struct ptp_clock_info *ptp, s64 delta) spin_lock_irqsave(&priv->ptp_lock, flags); - priv->hw->ptp->adjust_systime(priv->ioaddr, sec, nsec, neg_adj); + priv->hw->ptp->adjust_systime(priv->ptpaddr, sec, nsec, neg_adj, + priv->plat->has_gmac4); spin_unlock_irqrestore(&priv->ptp_lock, flags); @@ -114,7 +115,7 @@ static int stmmac_get_time(struct ptp_clock_info *ptp, struct timespec64 *ts) spin_lock_irqsave(&priv->ptp_lock, flags); - ns = priv->hw->ptp->get_systime(priv->ioaddr); + ns = priv->hw->ptp->get_systime(priv->ptpaddr); spin_unlock_irqrestore(&priv->ptp_lock, flags); @@ -141,7 +142,7 @@ static int stmmac_set_time(struct ptp_clock_info *ptp, spin_lock_irqsave(&priv->ptp_lock, flags); - priv->hw->ptp->init_systime(priv->ioaddr, ts->tv_sec, ts->tv_nsec); + priv->hw->ptp->init_systime(priv->ptpaddr, ts->tv_sec, ts->tv_nsec); spin_unlock_irqrestore(&priv->ptp_lock, flags); diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h b/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h index 4535df37c227..c06938c47af5 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h @@ -22,51 +22,53 @@ Author: Rayagond Kokatanur <rayagond@vayavyalabs.com> ******************************************************************************/ -#ifndef __STMMAC_PTP_H__ -#define __STMMAC_PTP_H__ +#ifndef __STMMAC_PTP_H__ +#define __STMMAC_PTP_H__ -/* IEEE 1588 PTP register offsets */ -#define PTP_TCR 0x0700 /* Timestamp Control Reg */ -#define PTP_SSIR 0x0704 /* Sub-Second Increment Reg */ -#define PTP_STSR 0x0708 /* System Time – Seconds Regr */ -#define PTP_STNSR 0x070C /* System Time – Nanoseconds Reg */ -#define PTP_STSUR 0x0710 /* System Time – Seconds Update Reg */ -#define PTP_STNSUR 0x0714 /* System Time – Nanoseconds Update Reg */ -#define PTP_TAR 0x0718 /* Timestamp Addend Reg */ -#define PTP_TTSR 0x071C /* Target Time Seconds Reg */ -#define PTP_TTNSR 0x0720 /* Target Time Nanoseconds Reg */ -#define PTP_STHWSR 0x0724 /* System Time - Higher Word Seconds Reg */ -#define PTP_TSR 0x0728 /* Timestamp Status */ +#define PTP_GMAC4_OFFSET 0xb00 +#define PTP_GMAC3_X_OFFSET 0x700 -#define PTP_STNSUR_ADDSUB_SHIFT 31 +/* IEEE 1588 PTP register offsets */ +#define PTP_TCR 0x00 /* Timestamp Control Reg */ +#define PTP_SSIR 0x04 /* Sub-Second Increment Reg */ +#define PTP_STSR 0x08 /* System Time – Seconds Regr */ +#define PTP_STNSR 0x0c /* System Time – Nanoseconds Reg */ +#define PTP_STSUR 0x10 /* System Time – Seconds Update Reg */ +#define PTP_STNSUR 0x14 /* System Time – Nanoseconds Update Reg */ +#define PTP_TAR 0x18 /* Timestamp Addend Reg */ -/* PTP TCR defines */ -#define PTP_TCR_TSENA 0x00000001 /* Timestamp Enable */ -#define PTP_TCR_TSCFUPDT 0x00000002 /* Timestamp Fine/Coarse Update */ -#define PTP_TCR_TSINIT 0x00000004 /* Timestamp Initialize */ -#define PTP_TCR_TSUPDT 0x00000008 /* Timestamp Update */ -/* Timestamp Interrupt Trigger Enable */ -#define PTP_TCR_TSTRIG 0x00000010 -#define PTP_TCR_TSADDREG 0x00000020 /* Addend Reg Update */ -#define PTP_TCR_TSENALL 0x00000100 /* Enable Timestamp for All Frames */ -/* Timestamp Digital or Binary Rollover Control */ -#define PTP_TCR_TSCTRLSSR 0x00000200 +#define PTP_STNSUR_ADDSUB_SHIFT 31 +#define PTP_DIGITAL_ROLLOVER_MODE 0x3B9ACA00 /* 10e9-1 ns */ +#define PTP_BINARY_ROLLOVER_MODE 0x80000000 /* ~0.466 ns */ +/* PTP Timestamp control register defines */ +#define PTP_TCR_TSENA BIT(0) /* Timestamp Enable */ +#define PTP_TCR_TSCFUPDT BIT(1) /* Timestamp Fine/Coarse Update */ +#define PTP_TCR_TSINIT BIT(2) /* Timestamp Initialize */ +#define PTP_TCR_TSUPDT BIT(3) /* Timestamp Update */ +#define PTP_TCR_TSTRIG BIT(4) /* Timestamp Interrupt Trigger Enable */ +#define PTP_TCR_TSADDREG BIT(5) /* Addend Reg Update */ +#define PTP_TCR_TSENALL BIT(8) /* Enable Timestamp for All Frames */ +#define PTP_TCR_TSCTRLSSR BIT(9) /* Digital or Binary Rollover Control */ /* Enable PTP packet Processing for Version 2 Format */ -#define PTP_TCR_TSVER2ENA 0x00000400 +#define PTP_TCR_TSVER2ENA BIT(10) /* Enable Processing of PTP over Ethernet Frames */ -#define PTP_TCR_TSIPENA 0x00000800 +#define PTP_TCR_TSIPENA BIT(11) /* Enable Processing of PTP Frames Sent over IPv6-UDP */ -#define PTP_TCR_TSIPV6ENA 0x00001000 +#define PTP_TCR_TSIPV6ENA BIT(12) /* Enable Processing of PTP Frames Sent over IPv4-UDP */ -#define PTP_TCR_TSIPV4ENA 0x00002000 +#define PTP_TCR_TSIPV4ENA BIT(13) /* Enable Timestamp Snapshot for Event Messages */ -#define PTP_TCR_TSEVNTENA 0x00004000 +#define PTP_TCR_TSEVNTENA BIT(14) /* Enable Snapshot for Messages Relevant to Master */ -#define PTP_TCR_TSMSTRENA 0x00008000 +#define PTP_TCR_TSMSTRENA BIT(15) /* Select PTP packets for Taking Snapshots */ -#define PTP_TCR_SNAPTYPSEL_1 0x00010000 +#define PTP_TCR_SNAPTYPSEL_1 GENMASK(17, 16) /* Enable MAC address for PTP Frame Filtering */ -#define PTP_TCR_TSENMACADDR 0x00040000 +#define PTP_TCR_TSENMACADDR BIT(18) + +/* SSIR defines */ +#define PTP_SSIR_SSINC_MASK 0xff +#define GMAC4_PTP_SSIR_SSINC_SHIFT 16 -#endif /* __STMMAC_PTP_H__ */ +#endif /* __STMMAC_PTP_H__ */ diff --git a/drivers/net/ethernet/sun/sunbmac.c b/drivers/net/ethernet/sun/sunbmac.c index aa4f9d2d8fa9..02f452730d52 100644 --- a/drivers/net/ethernet/sun/sunbmac.c +++ b/drivers/net/ethernet/sun/sunbmac.c @@ -623,6 +623,7 @@ static int bigmac_init_hw(struct bigmac *bp, int from_irq) void __iomem *gregs = bp->gregs; void __iomem *cregs = bp->creg; void __iomem *bregs = bp->bregs; + __u32 bblk_dvma = (__u32)bp->bblock_dvma; unsigned char *e = &bp->dev->dev_addr[0]; /* Latch current counters into statistics. */ @@ -671,9 +672,9 @@ static int bigmac_init_hw(struct bigmac *bp, int from_irq) bregs + BMAC_XIFCFG); /* Tell the QEC where the ring descriptors are. */ - sbus_writel(bp->bblock_dvma + bib_offset(be_rxd, 0), + sbus_writel(bblk_dvma + bib_offset(be_rxd, 0), cregs + CREG_RXDS); - sbus_writel(bp->bblock_dvma + bib_offset(be_txd, 0), + sbus_writel(bblk_dvma + bib_offset(be_txd, 0), cregs + CREG_TXDS); /* Setup the FIFO pointers into QEC local memory. */ diff --git a/drivers/net/ethernet/sun/sunbmac.h b/drivers/net/ethernet/sun/sunbmac.h index 06dd21707353..532fc56830cf 100644 --- a/drivers/net/ethernet/sun/sunbmac.h +++ b/drivers/net/ethernet/sun/sunbmac.h @@ -291,7 +291,7 @@ struct bigmac { void __iomem *bregs; /* BigMAC Registers */ void __iomem *tregs; /* BigMAC Transceiver */ struct bmac_init_block *bmac_block; /* RX and TX descriptors */ - __u32 bblock_dvma; /* RX and TX descriptors */ + dma_addr_t bblock_dvma; /* RX and TX descriptors */ spinlock_t lock; diff --git a/drivers/net/ethernet/sun/sunqe.c b/drivers/net/ethernet/sun/sunqe.c index 9b825780b3be..9582948145c1 100644 --- a/drivers/net/ethernet/sun/sunqe.c +++ b/drivers/net/ethernet/sun/sunqe.c @@ -124,7 +124,7 @@ static void qe_init_rings(struct sunqe *qep) { struct qe_init_block *qb = qep->qe_block; struct sunqe_buffers *qbufs = qep->buffers; - __u32 qbufs_dvma = qep->buffers_dvma; + __u32 qbufs_dvma = (__u32)qep->buffers_dvma; int i; qep->rx_new = qep->rx_old = qep->tx_new = qep->tx_old = 0; @@ -144,6 +144,7 @@ static int qe_init(struct sunqe *qep, int from_irq) void __iomem *mregs = qep->mregs; void __iomem *gregs = qecp->gregs; unsigned char *e = &qep->dev->dev_addr[0]; + __u32 qblk_dvma = (__u32)qep->qblock_dvma; u32 tmp; int i; @@ -152,8 +153,8 @@ static int qe_init(struct sunqe *qep, int from_irq) return -EAGAIN; /* Setup initial rx/tx init block pointers. */ - sbus_writel(qep->qblock_dvma + qib_offset(qe_rxd, 0), cregs + CREG_RXDS); - sbus_writel(qep->qblock_dvma + qib_offset(qe_txd, 0), cregs + CREG_TXDS); + sbus_writel(qblk_dvma + qib_offset(qe_rxd, 0), cregs + CREG_RXDS); + sbus_writel(qblk_dvma + qib_offset(qe_txd, 0), cregs + CREG_TXDS); /* Enable/mask the various irq's. */ sbus_writel(0, cregs + CREG_RIMASK); @@ -413,7 +414,7 @@ static void qe_rx(struct sunqe *qep) struct net_device *dev = qep->dev; struct qe_rxd *this; struct sunqe_buffers *qbufs = qep->buffers; - __u32 qbufs_dvma = qep->buffers_dvma; + __u32 qbufs_dvma = (__u32)qep->buffers_dvma; int elem = qep->rx_new; u32 flags; @@ -572,7 +573,7 @@ static int qe_start_xmit(struct sk_buff *skb, struct net_device *dev) { struct sunqe *qep = netdev_priv(dev); struct sunqe_buffers *qbufs = qep->buffers; - __u32 txbuf_dvma, qbufs_dvma = qep->buffers_dvma; + __u32 txbuf_dvma, qbufs_dvma = (__u32)qep->buffers_dvma; unsigned char *txbuf; int len, entry; diff --git a/drivers/net/ethernet/sun/sunqe.h b/drivers/net/ethernet/sun/sunqe.h index 581781b6b2fa..ae190b77431b 100644 --- a/drivers/net/ethernet/sun/sunqe.h +++ b/drivers/net/ethernet/sun/sunqe.h @@ -334,12 +334,12 @@ struct sunqe { void __iomem *qcregs; /* QEC per-channel Registers */ void __iomem *mregs; /* Per-channel MACE Registers */ struct qe_init_block *qe_block; /* RX and TX descriptors */ - __u32 qblock_dvma; /* RX and TX descriptors */ + dma_addr_t qblock_dvma; /* RX and TX descriptors */ spinlock_t lock; /* Protects txfull state */ int rx_new, rx_old; /* RX ring extents */ int tx_new, tx_old; /* TX ring extents */ struct sunqe_buffers *buffers; /* CPU visible address. */ - __u32 buffers_dvma; /* DVMA visible address. */ + dma_addr_t buffers_dvma; /* DVMA visible address. */ struct sunqec *parent; u8 mconfig; /* Base MACE mconfig value */ struct platform_device *op; /* QE's OF device struct */ diff --git a/drivers/net/ethernet/synopsys/dwc_eth_qos.c b/drivers/net/ethernet/synopsys/dwc_eth_qos.c index 5eedac495077..97d64bfed465 100644 --- a/drivers/net/ethernet/synopsys/dwc_eth_qos.c +++ b/drivers/net/ethernet/synopsys/dwc_eth_qos.c @@ -33,7 +33,6 @@ #include <linux/stat.h> #include <linux/types.h> -#include <linux/types.h> #include <linux/slab.h> #include <linux/delay.h> #include <linux/mm.h> @@ -43,7 +42,6 @@ #include <linux/phy.h> #include <linux/mii.h> -#include <linux/delay.h> #include <linux/dma-mapping.h> #include <linux/vmalloc.h> @@ -2883,7 +2881,7 @@ static int dwceqos_probe(struct platform_device *pdev) ret = of_get_phy_mode(lp->pdev->dev.of_node); if (ret < 0) { dev_err(&lp->pdev->dev, "error in getting phy i/f\n"); - goto err_out_clk_dis_phy; + goto err_out_deregister_fixed_link; } lp->phy_interface = ret; @@ -2891,14 +2889,14 @@ static int dwceqos_probe(struct platform_device *pdev) ret = dwceqos_mii_init(lp); if (ret) { dev_err(&lp->pdev->dev, "error in dwceqos_mii_init\n"); - goto err_out_clk_dis_phy; + goto err_out_deregister_fixed_link; } ret = dwceqos_mii_probe(ndev); if (ret != 0) { netdev_err(ndev, "mii_probe fail.\n"); ret = -ENXIO; - goto err_out_clk_dis_phy; + goto err_out_deregister_fixed_link; } dwceqos_set_umac_addr(lp, lp->ndev->dev_addr, 0); @@ -2916,7 +2914,7 @@ static int dwceqos_probe(struct platform_device *pdev) if (ret) { dev_err(&lp->pdev->dev, "Unable to retrieve DT, error %d\n", ret); - goto err_out_clk_dis_phy; + goto err_out_deregister_fixed_link; } dev_info(&lp->pdev->dev, "pdev->id %d, baseaddr 0x%08lx, irq %d\n", pdev->id, ndev->base_addr, ndev->irq); @@ -2926,7 +2924,7 @@ static int dwceqos_probe(struct platform_device *pdev) if (ret) { dev_err(&lp->pdev->dev, "Unable to request IRQ %d, error %d\n", ndev->irq, ret); - goto err_out_clk_dis_phy; + goto err_out_deregister_fixed_link; } if (netif_msg_probe(lp)) @@ -2937,11 +2935,14 @@ static int dwceqos_probe(struct platform_device *pdev) ret = register_netdev(ndev); if (ret) { dev_err(&pdev->dev, "Cannot register net device, aborting.\n"); - goto err_out_clk_dis_phy; + goto err_out_deregister_fixed_link; } return 0; +err_out_deregister_fixed_link: + if (of_phy_is_fixed_link(pdev->dev.of_node)) + of_phy_deregister_fixed_link(pdev->dev.of_node); err_out_clk_dis_phy: clk_disable_unprepare(lp->phy_ref_clk); err_out_clk_dis_aper: @@ -2961,8 +2962,11 @@ static int dwceqos_remove(struct platform_device *pdev) if (ndev) { lp = netdev_priv(ndev); - if (ndev->phydev) + if (ndev->phydev) { phy_disconnect(ndev->phydev); + if (of_phy_is_fixed_link(pdev->dev.of_node)) + of_phy_deregister_fixed_link(pdev->dev.of_node); + } mdiobus_unregister(lp->mii_bus); mdiobus_free(lp->mii_bus); diff --git a/drivers/net/ethernet/ti/cpsw-phy-sel.c b/drivers/net/ethernet/ti/cpsw-phy-sel.c index 054a8dd23dae..ba1e45ff6aae 100644 --- a/drivers/net/ethernet/ti/cpsw-phy-sel.c +++ b/drivers/net/ethernet/ti/cpsw-phy-sel.c @@ -176,9 +176,12 @@ void cpsw_phy_sel(struct device *dev, phy_interface_t phy_mode, int slave) } dev = bus_find_device(&platform_bus_type, NULL, node, match); + of_node_put(node); priv = dev_get_drvdata(dev); priv->cpsw_phy_sel(priv, phy_mode, slave); + + put_device(dev); } EXPORT_SYMBOL_GPL(cpsw_phy_sel); diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c index c6cff3d2ff05..b9087b828eff 100644 --- a/drivers/net/ethernet/ti/cpsw.c +++ b/drivers/net/ethernet/ti/cpsw.c @@ -2375,8 +2375,11 @@ static int cpsw_probe_dt(struct cpsw_platform_data *data, * to the PHY is the Ethernet MAC DT node. */ ret = of_phy_register_fixed_link(slave_node); - if (ret) + if (ret) { + if (ret != -EPROBE_DEFER) + dev_err(&pdev->dev, "failed to register fixed-link phy: %d\n", ret); return ret; + } slave_data->phy_node = of_node_get(slave_node); } else if (parp) { u32 phyid; @@ -2397,6 +2400,7 @@ static int cpsw_probe_dt(struct cpsw_platform_data *data, } snprintf(slave_data->phy_id, sizeof(slave_data->phy_id), PHY_ID_FMT, mdio->name, phyid); + put_device(&mdio->dev); } else { dev_err(&pdev->dev, "No slave[%d] phy_id, phy-handle, or fixed-link property\n", @@ -2440,6 +2444,34 @@ no_phy_slave: return 0; } +static void cpsw_remove_dt(struct platform_device *pdev) +{ + struct net_device *ndev = platform_get_drvdata(pdev); + struct cpsw_common *cpsw = ndev_to_cpsw(ndev); + struct cpsw_platform_data *data = &cpsw->data; + struct device_node *node = pdev->dev.of_node; + struct device_node *slave_node; + int i = 0; + + for_each_available_child_of_node(node, slave_node) { + struct cpsw_slave_data *slave_data = &data->slave_data[i]; + + if (strcmp(slave_node->name, "slave")) + continue; + + if (of_phy_is_fixed_link(slave_node)) + of_phy_deregister_fixed_link(slave_node); + + of_node_put(slave_data->phy_node); + + i++; + if (i == data->slaves) + break; + } + + of_platform_depopulate(&pdev->dev); +} + static int cpsw_probe_dual_emac(struct cpsw_priv *priv) { struct cpsw_common *cpsw = priv->cpsw; @@ -2547,6 +2579,9 @@ static int cpsw_probe(struct platform_device *pdev) int irq; cpsw = devm_kzalloc(&pdev->dev, sizeof(struct cpsw_common), GFP_KERNEL); + if (!cpsw) + return -ENOMEM; + cpsw->dev = &pdev->dev; ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES); @@ -2584,11 +2619,19 @@ static int cpsw_probe(struct platform_device *pdev) /* Select default pin state */ pinctrl_pm_select_default_state(&pdev->dev); - if (cpsw_probe_dt(&cpsw->data, pdev)) { - dev_err(&pdev->dev, "cpsw: platform data missing\n"); - ret = -ENODEV; + /* Need to enable clocks with runtime PM api to access module + * registers + */ + ret = pm_runtime_get_sync(&pdev->dev); + if (ret < 0) { + pm_runtime_put_noidle(&pdev->dev); goto clean_runtime_disable_ret; } + + ret = cpsw_probe_dt(&cpsw->data, pdev); + if (ret) + goto clean_dt_ret; + data = &cpsw->data; cpsw->rx_ch_num = 1; cpsw->tx_ch_num = 1; @@ -2608,7 +2651,7 @@ static int cpsw_probe(struct platform_device *pdev) GFP_KERNEL); if (!cpsw->slaves) { ret = -ENOMEM; - goto clean_runtime_disable_ret; + goto clean_dt_ret; } for (i = 0; i < data->slaves; i++) cpsw->slaves[i].slave_num = i; @@ -2620,7 +2663,7 @@ static int cpsw_probe(struct platform_device *pdev) if (IS_ERR(clk)) { dev_err(priv->dev, "fck is not found\n"); ret = -ENODEV; - goto clean_runtime_disable_ret; + goto clean_dt_ret; } cpsw->bus_freq_mhz = clk_get_rate(clk) / 1000000; @@ -2628,26 +2671,17 @@ static int cpsw_probe(struct platform_device *pdev) ss_regs = devm_ioremap_resource(&pdev->dev, ss_res); if (IS_ERR(ss_regs)) { ret = PTR_ERR(ss_regs); - goto clean_runtime_disable_ret; + goto clean_dt_ret; } cpsw->regs = ss_regs; - /* Need to enable clocks with runtime PM api to access module - * registers - */ - ret = pm_runtime_get_sync(&pdev->dev); - if (ret < 0) { - pm_runtime_put_noidle(&pdev->dev); - goto clean_runtime_disable_ret; - } cpsw->version = readl(&cpsw->regs->id_ver); - pm_runtime_put_sync(&pdev->dev); res = platform_get_resource(pdev, IORESOURCE_MEM, 1); cpsw->wr_regs = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(cpsw->wr_regs)) { ret = PTR_ERR(cpsw->wr_regs); - goto clean_runtime_disable_ret; + goto clean_dt_ret; } memset(&dma_params, 0, sizeof(dma_params)); @@ -2684,7 +2718,7 @@ static int cpsw_probe(struct platform_device *pdev) default: dev_err(priv->dev, "unknown version 0x%08x\n", cpsw->version); ret = -ENODEV; - goto clean_runtime_disable_ret; + goto clean_dt_ret; } for (i = 0; i < cpsw->data.slaves; i++) { struct cpsw_slave *slave = &cpsw->slaves[i]; @@ -2713,7 +2747,7 @@ static int cpsw_probe(struct platform_device *pdev) if (!cpsw->dma) { dev_err(priv->dev, "error initializing dma\n"); ret = -ENOMEM; - goto clean_runtime_disable_ret; + goto clean_dt_ret; } cpsw->txch[0] = cpdma_chan_create(cpsw->dma, 0, cpsw_tx_handler, 0); @@ -2811,16 +2845,23 @@ static int cpsw_probe(struct platform_device *pdev) ret = cpsw_probe_dual_emac(priv); if (ret) { cpsw_err(priv, probe, "error probe slave 2 emac interface\n"); - goto clean_ale_ret; + goto clean_unregister_netdev_ret; } } + pm_runtime_put(&pdev->dev); + return 0; +clean_unregister_netdev_ret: + unregister_netdev(ndev); clean_ale_ret: cpsw_ale_destroy(cpsw->ale); clean_dma_ret: cpdma_ctlr_destroy(cpsw->dma); +clean_dt_ret: + cpsw_remove_dt(pdev); + pm_runtime_put_sync(&pdev->dev); clean_runtime_disable_ret: pm_runtime_disable(&pdev->dev); clean_ndev_ret: @@ -2846,7 +2887,7 @@ static int cpsw_remove(struct platform_device *pdev) cpsw_ale_destroy(cpsw->ale); cpdma_ctlr_destroy(cpsw->dma); - of_platform_depopulate(&pdev->dev); + cpsw_remove_dt(pdev); pm_runtime_put_sync(&pdev->dev); pm_runtime_disable(&pdev->dev); if (cpsw->data.dual_emac) @@ -2889,6 +2930,8 @@ static int cpsw_resume(struct device *dev) /* Select default pin state */ pinctrl_pm_select_default_state(dev); + /* shut up ASSERT_RTNL() warning in netif_set_real_num_tx/rx_queues */ + rtnl_lock(); if (cpsw->data.dual_emac) { int i; @@ -2900,6 +2943,8 @@ static int cpsw_resume(struct device *dev) if (netif_running(ndev)) cpsw_ndo_open(ndev); } + rtnl_unlock(); + return 0; } #endif diff --git a/drivers/net/ethernet/ti/davinci_emac.c b/drivers/net/ethernet/ti/davinci_emac.c index 2fd94a5bc1f3..481c7bf0395b 100644 --- a/drivers/net/ethernet/ti/davinci_emac.c +++ b/drivers/net/ethernet/ti/davinci_emac.c @@ -1410,6 +1410,7 @@ static int emac_dev_open(struct net_device *ndev) int i = 0; struct emac_priv *priv = netdev_priv(ndev); struct phy_device *phydev = NULL; + struct device *phy = NULL; ret = pm_runtime_get_sync(&priv->pdev->dev); if (ret < 0) { @@ -1488,19 +1489,20 @@ static int emac_dev_open(struct net_device *ndev) /* use the first phy on the bus if pdata did not give us a phy id */ if (!phydev && !priv->phy_id) { - struct device *phy; - phy = bus_find_device(&mdio_bus_type, NULL, NULL, match_first_device); - if (phy) + if (phy) { priv->phy_id = dev_name(phy); + if (!priv->phy_id || !*priv->phy_id) + put_device(phy); + } } if (!phydev && priv->phy_id && *priv->phy_id) { phydev = phy_connect(ndev, priv->phy_id, &emac_adjust_link, PHY_INTERFACE_MODE_MII); - + put_device(phy); /* reference taken by bus_find_device */ if (IS_ERR(phydev)) { dev_err(emac_dev, "could not connect to phy %s\n", priv->phy_id); @@ -1765,6 +1767,7 @@ static int davinci_emac_try_get_mac(struct platform_device *pdev, */ static int davinci_emac_probe(struct platform_device *pdev) { + struct device_node *np = pdev->dev.of_node; int rc = 0; struct resource *res, *res_ctrl; struct net_device *ndev; @@ -1803,7 +1806,7 @@ static int davinci_emac_probe(struct platform_device *pdev) if (!pdata) { dev_err(&pdev->dev, "no platform data\n"); rc = -ENODEV; - goto no_pdata; + goto err_free_netdev; } /* MAC addr and PHY mask , RMII enable info from platform_data */ @@ -1939,6 +1942,10 @@ no_cpdma_chan: cpdma_chan_destroy(priv->rxchan); cpdma_ctlr_destroy(priv->dma); no_pdata: + if (of_phy_is_fixed_link(np)) + of_phy_deregister_fixed_link(np); + of_node_put(priv->phy_node); +err_free_netdev: free_netdev(ndev); return rc; } @@ -1954,6 +1961,7 @@ static int davinci_emac_remove(struct platform_device *pdev) { struct net_device *ndev = platform_get_drvdata(pdev); struct emac_priv *priv = netdev_priv(ndev); + struct device_node *np = pdev->dev.of_node; dev_notice(&ndev->dev, "DaVinci EMAC: davinci_emac_remove()\n"); @@ -1966,6 +1974,8 @@ static int davinci_emac_remove(struct platform_device *pdev) unregister_netdev(ndev); of_node_put(priv->phy_node); pm_runtime_disable(&pdev->dev); + if (of_phy_is_fixed_link(np)) + of_phy_deregister_fixed_link(np); free_netdev(ndev); return 0; diff --git a/drivers/net/ethernet/toshiba/ps3_gelic_wireless.c b/drivers/net/ethernet/toshiba/ps3_gelic_wireless.c index 446ea580ad42..928c1dca2673 100644 --- a/drivers/net/ethernet/toshiba/ps3_gelic_wireless.c +++ b/drivers/net/ethernet/toshiba/ps3_gelic_wireless.c @@ -1694,7 +1694,7 @@ struct gelic_wl_scan_info *gelic_wl_find_best_bss(struct gelic_wl_info *wl) pr_debug("%s: bssid matched\n", __func__); break; } else { - pr_debug("%s: bssid unmached\n", __func__); + pr_debug("%s: bssid unmatched\n", __func__); continue; } } diff --git a/drivers/net/ethernet/xscale/ixp4xx_eth.c b/drivers/net/ethernet/xscale/ixp4xx_eth.c index 7f127dc1b7ba..fa32391720fe 100644 --- a/drivers/net/ethernet/xscale/ixp4xx_eth.c +++ b/drivers/net/ethernet/xscale/ixp4xx_eth.c @@ -708,8 +708,7 @@ static int eth_poll(struct napi_struct *napi, int budget) if (!qmgr_stat_below_low_watermark(rxq) && napi_reschedule(napi)) { /* not empty again */ #if DEBUG_RX - printk(KERN_DEBUG "%s: eth_poll" - " napi_reschedule successed\n", + printk(KERN_DEBUG "%s: eth_poll napi_reschedule succeeded\n", dev->name); #endif qmgr_disable_irq(rxq); diff --git a/drivers/net/geneve.c b/drivers/net/geneve.c index 42edd7b7902f..8b4822ad27cb 100644 --- a/drivers/net/geneve.c +++ b/drivers/net/geneve.c @@ -859,7 +859,6 @@ static netdev_tx_t geneve_xmit_skb(struct sk_buff *skb, struct net_device *dev, struct geneve_dev *geneve = netdev_priv(dev); struct geneve_sock *gs4; struct rtable *rt = NULL; - const struct iphdr *iip; /* interior IP header */ int err = -EINVAL; struct flowi4 fl4; __u8 tos, ttl; @@ -890,8 +889,6 @@ static netdev_tx_t geneve_xmit_skb(struct sk_buff *skb, struct net_device *dev, sport = udp_flow_src_port(geneve->net, skb, 1, USHRT_MAX, true); skb_reset_mac_header(skb); - iip = ip_hdr(skb); - if (info) { const struct ip_tunnel_key *key = &info->key; u8 *opts = NULL; @@ -911,7 +908,7 @@ static netdev_tx_t geneve_xmit_skb(struct sk_buff *skb, struct net_device *dev, if (unlikely(err)) goto tx_error; - tos = ip_tunnel_ecn_encap(key->tos, iip, skb); + tos = ip_tunnel_ecn_encap(key->tos, ip_hdr(skb), skb); ttl = key->ttl; df = key->tun_flags & TUNNEL_DONT_FRAGMENT ? htons(IP_DF) : 0; } else { @@ -920,7 +917,7 @@ static netdev_tx_t geneve_xmit_skb(struct sk_buff *skb, struct net_device *dev, if (unlikely(err)) goto tx_error; - tos = ip_tunnel_ecn_encap(fl4.flowi4_tos, iip, skb); + tos = ip_tunnel_ecn_encap(fl4.flowi4_tos, ip_hdr(skb), skb); ttl = geneve->ttl; if (!ttl && IN_MULTICAST(ntohl(fl4.daddr))) ttl = 1; @@ -952,7 +949,6 @@ static netdev_tx_t geneve6_xmit_skb(struct sk_buff *skb, struct net_device *dev, { struct geneve_dev *geneve = netdev_priv(dev); struct dst_entry *dst = NULL; - const struct iphdr *iip; /* interior IP header */ struct geneve_sock *gs6; int err = -EINVAL; struct flowi6 fl6; @@ -982,8 +978,6 @@ static netdev_tx_t geneve6_xmit_skb(struct sk_buff *skb, struct net_device *dev, sport = udp_flow_src_port(geneve->net, skb, 1, USHRT_MAX, true); skb_reset_mac_header(skb); - iip = ip_hdr(skb); - if (info) { const struct ip_tunnel_key *key = &info->key; u8 *opts = NULL; @@ -1004,7 +998,7 @@ static netdev_tx_t geneve6_xmit_skb(struct sk_buff *skb, struct net_device *dev, if (unlikely(err)) goto tx_error; - prio = ip_tunnel_ecn_encap(key->tos, iip, skb); + prio = ip_tunnel_ecn_encap(key->tos, ip_hdr(skb), skb); ttl = key->ttl; label = info->key.label; } else { @@ -1014,7 +1008,7 @@ static netdev_tx_t geneve6_xmit_skb(struct sk_buff *skb, struct net_device *dev, goto tx_error; prio = ip_tunnel_ecn_encap(ip6_tclass(fl6.flowlabel), - iip, skb); + ip_hdr(skb), skb); ttl = geneve->ttl; if (!ttl && ipv6_addr_is_multicast(&fl6.daddr)) ttl = 1; diff --git a/drivers/net/ieee802154/adf7242.c b/drivers/net/ieee802154/adf7242.c index 9fa7ac9f8e68..f355df7cf84a 100644 --- a/drivers/net/ieee802154/adf7242.c +++ b/drivers/net/ieee802154/adf7242.c @@ -20,7 +20,6 @@ #include <linux/skbuff.h> #include <linux/of.h> #include <linux/irq.h> -#include <linux/delay.h> #include <linux/debugfs.h> #include <linux/bitops.h> #include <linux/ieee802154.h> diff --git a/drivers/net/ipvlan/ipvlan_main.c b/drivers/net/ipvlan/ipvlan_main.c index f442eb366863..0fef17874d50 100644 --- a/drivers/net/ipvlan/ipvlan_main.c +++ b/drivers/net/ipvlan/ipvlan_main.c @@ -497,6 +497,7 @@ static int ipvlan_link_new(struct net *src_net, struct net_device *dev, struct net_device *phy_dev; int err; u16 mode = IPVLAN_MODE_L3; + bool create = false; if (!tb[IFLA_LINK]) return -EINVAL; @@ -513,6 +514,7 @@ static int ipvlan_link_new(struct net *src_net, struct net_device *dev, err = ipvlan_port_create(phy_dev); if (err < 0) return err; + create = true; } if (data && data[IFLA_IPVLAN_MODE]) @@ -536,22 +538,27 @@ static int ipvlan_link_new(struct net *src_net, struct net_device *dev, err = register_netdevice(dev); if (err < 0) - return err; + goto destroy_ipvlan_port; err = netdev_upper_dev_link(phy_dev, dev); if (err) { - unregister_netdevice(dev); - return err; + goto unregister_netdev; } err = ipvlan_set_port_mode(port, mode); if (err) { - unregister_netdevice(dev); - return err; + goto unregister_netdev; } list_add_tail_rcu(&ipvlan->pnode, &port->ipvlans); netif_stacked_transfer_operstate(phy_dev, dev); return 0; + +unregister_netdev: + unregister_netdevice(dev); +destroy_ipvlan_port: + if (create) + ipvlan_port_destroy(phy_dev); + return err; } static void ipvlan_link_delete(struct net_device *dev, struct list_head *head) diff --git a/drivers/net/irda/w83977af_ir.c b/drivers/net/irda/w83977af_ir.c index 4e3d2e7c697c..e8c3a8c32534 100644 --- a/drivers/net/irda/w83977af_ir.c +++ b/drivers/net/irda/w83977af_ir.c @@ -518,7 +518,9 @@ static netdev_tx_t w83977af_hard_xmit(struct sk_buff *skb, mtt = irda_get_mtt(skb); pr_debug("%s(%ld), mtt=%d\n", __func__ , jiffies, mtt); - if (mtt) + if (mtt > 1000) + mdelay(mtt/1000); + else if (mtt) udelay(mtt); /* Enable DMA interrupt */ diff --git a/drivers/net/macvlan.c b/drivers/net/macvlan.c index 3234fcdea317..26d6f0bbe14b 100644 --- a/drivers/net/macvlan.c +++ b/drivers/net/macvlan.c @@ -623,7 +623,8 @@ hash_add: return 0; clear_multi: - dev_set_allmulti(lowerdev, -1); + if (dev->flags & IFF_ALLMULTI) + dev_set_allmulti(lowerdev, -1); del_unicast: dev_uc_del(lowerdev, dev->dev_addr); out: @@ -1278,6 +1279,7 @@ int macvlan_common_newlink(struct net *src_net, struct net_device *dev, struct net_device *lowerdev; int err; int macmode; + bool create = false; if (!tb[IFLA_LINK]) return -EINVAL; @@ -1304,12 +1306,18 @@ int macvlan_common_newlink(struct net *src_net, struct net_device *dev, err = macvlan_port_create(lowerdev); if (err < 0) return err; + create = true; } port = macvlan_port_get_rtnl(lowerdev); /* Only 1 macvlan device can be created in passthru mode */ - if (port->passthru) - return -EINVAL; + if (port->passthru) { + /* The macvlan port must be not created this time, + * still goto destroy_macvlan_port for readability. + */ + err = -EINVAL; + goto destroy_macvlan_port; + } vlan->lowerdev = lowerdev; vlan->dev = dev; @@ -1325,24 +1333,28 @@ int macvlan_common_newlink(struct net *src_net, struct net_device *dev, vlan->flags = nla_get_u16(data[IFLA_MACVLAN_FLAGS]); if (vlan->mode == MACVLAN_MODE_PASSTHRU) { - if (port->count) - return -EINVAL; + if (port->count) { + err = -EINVAL; + goto destroy_macvlan_port; + } port->passthru = true; eth_hw_addr_inherit(dev, lowerdev); } if (data && data[IFLA_MACVLAN_MACADDR_MODE]) { - if (vlan->mode != MACVLAN_MODE_SOURCE) - return -EINVAL; + if (vlan->mode != MACVLAN_MODE_SOURCE) { + err = -EINVAL; + goto destroy_macvlan_port; + } macmode = nla_get_u32(data[IFLA_MACVLAN_MACADDR_MODE]); err = macvlan_changelink_sources(vlan, macmode, data); if (err) - return err; + goto destroy_macvlan_port; } err = register_netdevice(dev); if (err < 0) - return err; + goto destroy_macvlan_port; dev->priv_flags |= IFF_MACVLAN; err = netdev_upper_dev_link(lowerdev, dev); @@ -1357,7 +1369,9 @@ int macvlan_common_newlink(struct net *src_net, struct net_device *dev, unregister_netdev: unregister_netdevice(dev); - +destroy_macvlan_port: + if (create) + macvlan_port_destroy(port->dev); return err; } EXPORT_SYMBOL_GPL(macvlan_common_newlink); diff --git a/drivers/net/macvtap.c b/drivers/net/macvtap.c index 070e3290aa6e..7869b0651576 100644 --- a/drivers/net/macvtap.c +++ b/drivers/net/macvtap.c @@ -491,7 +491,13 @@ static int macvtap_newlink(struct net *src_net, /* Don't put anything that may fail after macvlan_common_newlink * because we can't undo what it does. */ - return macvlan_common_newlink(src_net, dev, tb, data); + err = macvlan_common_newlink(src_net, dev, tb, data); + if (err) { + netdev_rx_handler_unregister(dev); + return err; + } + + return 0; } static void macvtap_dellink(struct net_device *dev, @@ -736,13 +742,8 @@ static ssize_t macvtap_get_user(struct macvtap_queue *q, struct msghdr *m, if (zerocopy) err = zerocopy_sg_from_iter(skb, from); - else { + else err = skb_copy_datagram_from_iter(skb, 0, from, len); - if (!err && m && m->msg_control) { - struct ubuf_info *uarg = m->msg_control; - uarg->callback(uarg, false); - } - } if (err) goto err_kfree; @@ -773,7 +774,11 @@ static ssize_t macvtap_get_user(struct macvtap_queue *q, struct msghdr *m, skb_shinfo(skb)->destructor_arg = m->msg_control; skb_shinfo(skb)->tx_flags |= SKBTX_DEV_ZEROCOPY; skb_shinfo(skb)->tx_flags |= SKBTX_SHARED_FRAG; + } else if (m && m->msg_control) { + struct ubuf_info *uarg = m->msg_control; + uarg->callback(uarg, false); } + if (vlan) { skb->dev = vlan->dev; dev_queue_xmit(skb); diff --git a/drivers/net/phy/fixed_phy.c b/drivers/net/phy/fixed_phy.c index c649c101bbab..eb5167210681 100644 --- a/drivers/net/phy/fixed_phy.c +++ b/drivers/net/phy/fixed_phy.c @@ -279,7 +279,7 @@ EXPORT_SYMBOL_GPL(fixed_phy_register); void fixed_phy_unregister(struct phy_device *phy) { phy_device_remove(phy); - + of_node_put(phy->mdio.dev.of_node); fixed_phy_del(phy->mdio.addr); } EXPORT_SYMBOL_GPL(fixed_phy_unregister); diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c index 081df68d2ce1..ea92d524d5a8 100644 --- a/drivers/net/phy/micrel.c +++ b/drivers/net/phy/micrel.c @@ -318,12 +318,12 @@ static int ksz8041_config_init(struct phy_device *phydev) /* Limit supported and advertised modes in fiber mode */ if (of_property_read_bool(of_node, "micrel,fiber-mode")) { phydev->dev_flags |= MICREL_PHY_FXEN; - phydev->supported &= SUPPORTED_FIBRE | - SUPPORTED_100baseT_Full | + phydev->supported &= SUPPORTED_100baseT_Full | SUPPORTED_100baseT_Half; - phydev->advertising &= ADVERTISED_FIBRE | - ADVERTISED_100baseT_Full | + phydev->supported |= SUPPORTED_FIBRE; + phydev->advertising &= ADVERTISED_100baseT_Full | ADVERTISED_100baseT_Half; + phydev->advertising |= ADVERTISED_FIBRE; phydev->autoneg = AUTONEG_DISABLE; } diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c index e977ba931878..1a4bf8acad78 100644 --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c @@ -723,6 +723,7 @@ struct phy_device *phy_connect(struct net_device *dev, const char *bus_id, phydev = to_phy_device(d); rc = phy_connect_direct(dev, phydev, handler, interface); + put_device(d); if (rc) return ERR_PTR(rc); @@ -953,6 +954,7 @@ struct phy_device *phy_attach(struct net_device *dev, const char *bus_id, phydev = to_phy_device(d); rc = phy_attach_direct(dev, phydev, phydev->dev_flags, interface); + put_device(d); if (rc) return ERR_PTR(rc); diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c index aadd6e9f54ad..9cbe645e3d89 100644 --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c @@ -102,15 +102,19 @@ static int rtl8211f_config_init(struct phy_device *phydev) if (ret < 0) return ret; - if (phydev->interface == PHY_INTERFACE_MODE_RGMII) { - /* enable TXDLY */ - phy_write(phydev, RTL8211F_PAGE_SELECT, 0xd08); - reg = phy_read(phydev, 0x11); + phy_write(phydev, RTL8211F_PAGE_SELECT, 0xd08); + reg = phy_read(phydev, 0x11); + + /* enable TX-delay for rgmii-id and rgmii-txid, otherwise disable it */ + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || + phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) reg |= RTL8211F_TX_DELAY; - phy_write(phydev, 0x11, reg); - /* restore to default page 0 */ - phy_write(phydev, RTL8211F_PAGE_SELECT, 0x0); - } + else + reg &= ~RTL8211F_TX_DELAY; + + phy_write(phydev, 0x11, reg); + /* restore to default page 0 */ + phy_write(phydev, RTL8211F_PAGE_SELECT, 0x0); return 0; } diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c index 2e37eb337d48..24b4a09468dd 100644 --- a/drivers/net/phy/vitesse.c +++ b/drivers/net/phy/vitesse.c @@ -62,6 +62,10 @@ /* Vitesse Extended Page Access Register */ #define MII_VSC82X4_EXT_PAGE_ACCESS 0x1f +/* Vitesse VSC8601 Extended PHY Control Register 1 */ +#define MII_VSC8601_EPHY_CTL 0x17 +#define MII_VSC8601_EPHY_CTL_RGMII_SKEW (1 << 8) + #define PHY_ID_VSC8234 0x000fc620 #define PHY_ID_VSC8244 0x000fc6c0 #define PHY_ID_VSC8514 0x00070670 @@ -111,6 +115,34 @@ static int vsc824x_config_init(struct phy_device *phydev) return err; } +/* This adds a skew for both TX and RX clocks, so the skew should only be + * applied to "rgmii-id" interfaces. It may not work as expected + * on "rgmii-txid", "rgmii-rxid" or "rgmii" interfaces. */ +static int vsc8601_add_skew(struct phy_device *phydev) +{ + int ret; + + ret = phy_read(phydev, MII_VSC8601_EPHY_CTL); + if (ret < 0) + return ret; + + ret |= MII_VSC8601_EPHY_CTL_RGMII_SKEW; + return phy_write(phydev, MII_VSC8601_EPHY_CTL, ret); +} + +static int vsc8601_config_init(struct phy_device *phydev) +{ + int ret = 0; + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) + ret = vsc8601_add_skew(phydev); + + if (ret < 0) + return ret; + + return genphy_config_init(phydev); +} + static int vsc824x_ack_interrupt(struct phy_device *phydev) { int err = 0; @@ -275,7 +307,7 @@ static struct phy_driver vsc82xx_driver[] = { .phy_id_mask = 0x000ffff0, .features = PHY_GBIT_FEATURES, .flags = PHY_HAS_INTERRUPT, - .config_init = &genphy_config_init, + .config_init = &vsc8601_config_init, .config_aneg = &genphy_config_aneg, .read_status = &genphy_read_status, .ack_interrupt = &vsc824x_ack_interrupt, diff --git a/drivers/net/tun.c b/drivers/net/tun.c index 8093e39ae263..db6acecabeaa 100644 --- a/drivers/net/tun.c +++ b/drivers/net/tun.c @@ -1246,13 +1246,8 @@ static ssize_t tun_get_user(struct tun_struct *tun, struct tun_file *tfile, if (zerocopy) err = zerocopy_sg_from_iter(skb, from); - else { + else err = skb_copy_datagram_from_iter(skb, 0, from, len); - if (!err && msg_control) { - struct ubuf_info *uarg = msg_control; - uarg->callback(uarg, false); - } - } if (err) { this_cpu_inc(tun->pcpu_stats->rx_dropped); @@ -1298,6 +1293,9 @@ static ssize_t tun_get_user(struct tun_struct *tun, struct tun_file *tfile, skb_shinfo(skb)->destructor_arg = msg_control; skb_shinfo(skb)->tx_flags |= SKBTX_DEV_ZEROCOPY; skb_shinfo(skb)->tx_flags |= SKBTX_SHARED_FRAG; + } else if (msg_control) { + struct ubuf_info *uarg = msg_control; + uarg->callback(uarg, false); } skb_reset_network_header(skb); diff --git a/drivers/net/usb/asix_devices.c b/drivers/net/usb/asix_devices.c index cce24950a0ab..dc7b6392e75a 100644 --- a/drivers/net/usb/asix_devices.c +++ b/drivers/net/usb/asix_devices.c @@ -603,12 +603,12 @@ static void ax88772_suspend(struct usbnet *dev) u16 medium; /* Stop MAC operation */ - medium = asix_read_medium_status(dev, 0); + medium = asix_read_medium_status(dev, 1); medium &= ~AX_MEDIUM_RE; - asix_write_medium_mode(dev, medium, 0); + asix_write_medium_mode(dev, medium, 1); netdev_dbg(dev->net, "ax88772_suspend: medium=0x%04x\n", - asix_read_medium_status(dev, 0)); + asix_read_medium_status(dev, 1)); /* Preserve BMCR for restoring */ priv->presvd_phy_bmcr = diff --git a/drivers/net/usb/ax88179_178a.c b/drivers/net/usb/ax88179_178a.c index e6338c16081a..8a6675d92b98 100644 --- a/drivers/net/usb/ax88179_178a.c +++ b/drivers/net/usb/ax88179_178a.c @@ -1656,6 +1656,19 @@ static const struct driver_info ax88178a_info = { .tx_fixup = ax88179_tx_fixup, }; +static const struct driver_info cypress_GX3_info = { + .description = "Cypress GX3 SuperSpeed to Gigabit Ethernet Controller", + .bind = ax88179_bind, + .unbind = ax88179_unbind, + .status = ax88179_status, + .link_reset = ax88179_link_reset, + .reset = ax88179_reset, + .stop = ax88179_stop, + .flags = FLAG_ETHER | FLAG_FRAMING_AX, + .rx_fixup = ax88179_rx_fixup, + .tx_fixup = ax88179_tx_fixup, +}; + static const struct driver_info dlink_dub1312_info = { .description = "D-Link DUB-1312 USB 3.0 to Gigabit Ethernet Adapter", .bind = ax88179_bind, @@ -1718,6 +1731,10 @@ static const struct usb_device_id products[] = { USB_DEVICE(0x0b95, 0x178a), .driver_info = (unsigned long)&ax88178a_info, }, { + /* Cypress GX3 SuperSpeed to Gigabit Ethernet Bridge Controller */ + USB_DEVICE(0x04b4, 0x3610), + .driver_info = (unsigned long)&cypress_GX3_info, +}, { /* D-Link DUB-1312 USB 3.0 to Gigabit Ethernet Adapter */ USB_DEVICE(0x2001, 0x4a00), .driver_info = (unsigned long)&dlink_dub1312_info, diff --git a/drivers/net/usb/cdc_ether.c b/drivers/net/usb/cdc_ether.c index c47ec0a04c8e..dd623f674487 100644 --- a/drivers/net/usb/cdc_ether.c +++ b/drivers/net/usb/cdc_ether.c @@ -388,12 +388,6 @@ void usbnet_cdc_status(struct usbnet *dev, struct urb *urb) case USB_CDC_NOTIFY_NETWORK_CONNECTION: netif_dbg(dev, timer, dev->net, "CDC: carrier %s\n", event->wValue ? "on" : "off"); - - /* Work-around for devices with broken off-notifications */ - if (event->wValue && - !test_bit(__LINK_STATE_NOCARRIER, &dev->net->state)) - usbnet_link_change(dev, 0, 0); - usbnet_link_change(dev, !!event->wValue, 0); break; case USB_CDC_NOTIFY_SPEED_CHANGE: /* tx/rx rates */ @@ -466,6 +460,36 @@ static int usbnet_cdc_zte_rx_fixup(struct usbnet *dev, struct sk_buff *skb) return 1; } +/* Ensure correct link state + * + * Some devices (ZTE MF823/831/910) export two carrier on notifications when + * connected. This causes the link state to be incorrect. Work around this by + * always setting the state to off, then on. + */ +void usbnet_cdc_zte_status(struct usbnet *dev, struct urb *urb) +{ + struct usb_cdc_notification *event; + + if (urb->actual_length < sizeof(*event)) + return; + + event = urb->transfer_buffer; + + if (event->bNotificationType != USB_CDC_NOTIFY_NETWORK_CONNECTION) { + usbnet_cdc_status(dev, urb); + return; + } + + netif_dbg(dev, timer, dev->net, "CDC: carrier %s\n", + event->wValue ? "on" : "off"); + + if (event->wValue && + netif_carrier_ok(dev->net)) + netif_carrier_off(dev->net); + + usbnet_link_change(dev, !!event->wValue, 0); +} + static const struct driver_info cdc_info = { .description = "CDC Ethernet Device", .flags = FLAG_ETHER | FLAG_POINTTOPOINT, @@ -481,7 +505,7 @@ static const struct driver_info zte_cdc_info = { .flags = FLAG_ETHER | FLAG_POINTTOPOINT, .bind = usbnet_cdc_zte_bind, .unbind = usbnet_cdc_unbind, - .status = usbnet_cdc_status, + .status = usbnet_cdc_zte_status, .set_rx_mode = usbnet_cdc_update_filter, .manage_power = usbnet_manage_power, .rx_fixup = usbnet_cdc_zte_rx_fixup, diff --git a/drivers/net/usb/qmi_wwan.c b/drivers/net/usb/qmi_wwan.c index 3ff76c6db4f6..6fe1cdb0174f 100644 --- a/drivers/net/usb/qmi_wwan.c +++ b/drivers/net/usb/qmi_wwan.c @@ -894,6 +894,7 @@ static const struct usb_device_id products[] = { {QMI_FIXED_INTF(0x1bbb, 0x0203, 2)}, /* Alcatel L800MA */ {QMI_FIXED_INTF(0x2357, 0x0201, 4)}, /* TP-LINK HSUPA Modem MA180 */ {QMI_FIXED_INTF(0x2357, 0x9000, 4)}, /* TP-LINK MA260 */ + {QMI_QUIRK_SET_DTR(0x1bc7, 0x1040, 2)}, /* Telit LE922A */ {QMI_FIXED_INTF(0x1bc7, 0x1200, 5)}, /* Telit LE920 */ {QMI_FIXED_INTF(0x1bc7, 0x1201, 2)}, /* Telit LE920 */ {QMI_FIXED_INTF(0x1c9e, 0x9b01, 3)}, /* XS Stick W100-2 from 4G Systems */ diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c index 44d439f50961..efb84f092492 100644 --- a/drivers/net/usb/r8152.c +++ b/drivers/net/usb/r8152.c @@ -1730,7 +1730,7 @@ static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc) u8 checksum = CHECKSUM_NONE; u32 opts2, opts3; - if (tp->version == RTL_VER_01) + if (tp->version == RTL_VER_01 || tp->version == RTL_VER_02) goto return_result; opts2 = le32_to_cpu(rx_desc->opts2); @@ -1745,7 +1745,7 @@ static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc) checksum = CHECKSUM_NONE; else checksum = CHECKSUM_UNNECESSARY; - } else if (RD_IPV6_CS) { + } else if (opts2 & RD_IPV6_CS) { if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) checksum = CHECKSUM_UNNECESSARY; else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) @@ -3266,10 +3266,8 @@ static int rtl8152_open(struct net_device *netdev) goto out; res = usb_autopm_get_interface(tp->intf); - if (res < 0) { - free_all_mem(tp); - goto out; - } + if (res < 0) + goto out_free; mutex_lock(&tp->control); @@ -3285,10 +3283,9 @@ static int rtl8152_open(struct net_device *netdev) netif_device_detach(tp->netdev); netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n", res); - free_all_mem(tp); - } else { - napi_enable(&tp->napi); + goto out_unlock; } + napi_enable(&tp->napi); mutex_unlock(&tp->control); @@ -3297,7 +3294,13 @@ static int rtl8152_open(struct net_device *netdev) tp->pm_notifier.notifier_call = rtl_notifier; register_pm_notifier(&tp->pm_notifier); #endif + return 0; +out_unlock: + mutex_unlock(&tp->control); + usb_autopm_put_interface(tp->intf); +out_free: + free_all_mem(tp); out: return res; } diff --git a/drivers/net/virtio_net.c b/drivers/net/virtio_net.c index fad84f3f4109..7276d5a95bd0 100644 --- a/drivers/net/virtio_net.c +++ b/drivers/net/virtio_net.c @@ -1497,6 +1497,11 @@ static void virtnet_free_queues(struct virtnet_info *vi) netif_napi_del(&vi->rq[i].napi); } + /* We called napi_hash_del() before netif_napi_del(), + * we need to respect an RCU grace period before freeing vi->rq + */ + synchronize_net(); + kfree(vi->rq); kfree(vi->sq); } @@ -2038,23 +2043,33 @@ static struct virtio_device_id id_table[] = { { 0 }, }; +#define VIRTNET_FEATURES \ + VIRTIO_NET_F_CSUM, VIRTIO_NET_F_GUEST_CSUM, \ + VIRTIO_NET_F_MAC, \ + VIRTIO_NET_F_HOST_TSO4, VIRTIO_NET_F_HOST_UFO, VIRTIO_NET_F_HOST_TSO6, \ + VIRTIO_NET_F_HOST_ECN, VIRTIO_NET_F_GUEST_TSO4, VIRTIO_NET_F_GUEST_TSO6, \ + VIRTIO_NET_F_GUEST_ECN, VIRTIO_NET_F_GUEST_UFO, \ + VIRTIO_NET_F_MRG_RXBUF, VIRTIO_NET_F_STATUS, VIRTIO_NET_F_CTRL_VQ, \ + VIRTIO_NET_F_CTRL_RX, VIRTIO_NET_F_CTRL_VLAN, \ + VIRTIO_NET_F_GUEST_ANNOUNCE, VIRTIO_NET_F_MQ, \ + VIRTIO_NET_F_CTRL_MAC_ADDR, \ + VIRTIO_NET_F_MTU + static unsigned int features[] = { - VIRTIO_NET_F_CSUM, VIRTIO_NET_F_GUEST_CSUM, - VIRTIO_NET_F_GSO, VIRTIO_NET_F_MAC, - VIRTIO_NET_F_HOST_TSO4, VIRTIO_NET_F_HOST_UFO, VIRTIO_NET_F_HOST_TSO6, - VIRTIO_NET_F_HOST_ECN, VIRTIO_NET_F_GUEST_TSO4, VIRTIO_NET_F_GUEST_TSO6, - VIRTIO_NET_F_GUEST_ECN, VIRTIO_NET_F_GUEST_UFO, - VIRTIO_NET_F_MRG_RXBUF, VIRTIO_NET_F_STATUS, VIRTIO_NET_F_CTRL_VQ, - VIRTIO_NET_F_CTRL_RX, VIRTIO_NET_F_CTRL_VLAN, - VIRTIO_NET_F_GUEST_ANNOUNCE, VIRTIO_NET_F_MQ, - VIRTIO_NET_F_CTRL_MAC_ADDR, + VIRTNET_FEATURES, +}; + +static unsigned int features_legacy[] = { + VIRTNET_FEATURES, + VIRTIO_NET_F_GSO, VIRTIO_F_ANY_LAYOUT, - VIRTIO_NET_F_MTU, }; static struct virtio_driver virtio_net_driver = { .feature_table = features, .feature_table_size = ARRAY_SIZE(features), + .feature_table_legacy = features_legacy, + .feature_table_size_legacy = ARRAY_SIZE(features_legacy), .driver.name = KBUILD_MODNAME, .driver.owner = THIS_MODULE, .id_table = id_table, diff --git a/drivers/net/vxlan.c b/drivers/net/vxlan.c index f3c2fa3ab0d5..2ba01ca02c9c 100644 --- a/drivers/net/vxlan.c +++ b/drivers/net/vxlan.c @@ -611,6 +611,7 @@ static int vxlan_fdb_create(struct vxlan_dev *vxlan, struct vxlan_rdst *rd = NULL; struct vxlan_fdb *f; int notify = 0; + int rc; f = __vxlan_find_mac(vxlan, mac); if (f) { @@ -641,8 +642,7 @@ static int vxlan_fdb_create(struct vxlan_dev *vxlan, if ((flags & NLM_F_APPEND) && (is_multicast_ether_addr(f->eth_addr) || is_zero_ether_addr(f->eth_addr))) { - int rc = vxlan_fdb_append(f, ip, port, vni, ifindex, - &rd); + rc = vxlan_fdb_append(f, ip, port, vni, ifindex, &rd); if (rc < 0) return rc; @@ -673,7 +673,11 @@ static int vxlan_fdb_create(struct vxlan_dev *vxlan, INIT_LIST_HEAD(&f->remotes); memcpy(f->eth_addr, mac, ETH_ALEN); - vxlan_fdb_append(f, ip, port, vni, ifindex, &rd); + rc = vxlan_fdb_append(f, ip, port, vni, ifindex, &rd); + if (rc < 0) { + kfree(f); + return rc; + } ++vxlan->addrcnt; hlist_add_head_rcu(&f->hlist, @@ -944,7 +948,9 @@ static bool vxlan_group_used(struct vxlan_net *vn, struct vxlan_dev *dev) { struct vxlan_dev *vxlan; struct vxlan_sock *sock4; - struct vxlan_sock *sock6 = NULL; +#if IS_ENABLED(CONFIG_IPV6) + struct vxlan_sock *sock6; +#endif unsigned short family = dev->default_dst.remote_ip.sa.sa_family; sock4 = rtnl_dereference(dev->vn4_sock); diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c index b777e1b2f87a..78d9966a3957 100644 --- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c +++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c @@ -4516,7 +4516,7 @@ brcmf_cfg80211_start_ap(struct wiphy *wiphy, struct net_device *ndev, /* store current 11d setting */ if (brcmf_fil_cmd_int_get(ifp, BRCMF_C_GET_REGULATORY, &ifp->vif->is_11d)) { - supports_11d = false; + is_11d = supports_11d = false; } else { country_ie = brcmf_parse_tlvs((u8 *)settings->beacon.tail, settings->beacon.tail_len, diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/d3.c b/drivers/net/wireless/intel/iwlwifi/mvm/d3.c index 4fdc3dad3e85..b88e2048ae0b 100644 --- a/drivers/net/wireless/intel/iwlwifi/mvm/d3.c +++ b/drivers/net/wireless/intel/iwlwifi/mvm/d3.c @@ -1087,6 +1087,15 @@ iwl_mvm_netdetect_config(struct iwl_mvm *mvm, ret = iwl_mvm_switch_to_d3(mvm); if (ret) return ret; + } else { + /* In theory, we wouldn't have to stop a running sched + * scan in order to start another one (for + * net-detect). But in practice this doesn't seem to + * work properly, so stop any running sched_scan now. + */ + ret = iwl_mvm_scan_stop(mvm, IWL_MVM_SCAN_SCHED, true); + if (ret) + return ret; } /* rfkill release can be either for wowlan or netdetect */ @@ -1254,7 +1263,10 @@ static int __iwl_mvm_suspend(struct ieee80211_hw *hw, out: if (ret < 0) { iwl_mvm_ref(mvm, IWL_MVM_REF_UCODE_DOWN); - ieee80211_restart_hw(mvm->hw); + if (mvm->restart_fw > 0) { + mvm->restart_fw--; + ieee80211_restart_hw(mvm->hw); + } iwl_mvm_free_nd(mvm); } out_noreset: @@ -2088,6 +2100,16 @@ static int __iwl_mvm_resume(struct iwl_mvm *mvm, bool test) iwl_mvm_update_changed_regdom(mvm); if (mvm->net_detect) { + /* If this is a non-unified image, we restart the FW, + * so no need to stop the netdetect scan. If that + * fails, continue and try to get the wake-up reasons, + * but trigger a HW restart by keeping a failure code + * in ret. + */ + if (unified_image) + ret = iwl_mvm_scan_stop(mvm, IWL_MVM_SCAN_NETDETECT, + false); + iwl_mvm_query_netdetect_reasons(mvm, vif); /* has unlocked the mutex, so skip that */ goto out; @@ -2271,7 +2293,8 @@ static void iwl_mvm_d3_test_disconn_work_iter(void *_data, u8 *mac, static int iwl_mvm_d3_test_release(struct inode *inode, struct file *file) { struct iwl_mvm *mvm = inode->i_private; - int remaining_time = 10; + bool unified_image = fw_has_capa(&mvm->fw->ucode_capa, + IWL_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG); mvm->d3_test_active = false; @@ -2282,17 +2305,21 @@ static int iwl_mvm_d3_test_release(struct inode *inode, struct file *file) mvm->trans->system_pm_mode = IWL_PLAT_PM_MODE_DISABLED; iwl_abort_notification_waits(&mvm->notif_wait); - ieee80211_restart_hw(mvm->hw); + if (!unified_image) { + int remaining_time = 10; - /* wait for restart and disconnect all interfaces */ - while (test_bit(IWL_MVM_STATUS_IN_HW_RESTART, &mvm->status) && - remaining_time > 0) { - remaining_time--; - msleep(1000); - } + ieee80211_restart_hw(mvm->hw); + + /* wait for restart and disconnect all interfaces */ + while (test_bit(IWL_MVM_STATUS_IN_HW_RESTART, &mvm->status) && + remaining_time > 0) { + remaining_time--; + msleep(1000); + } - if (remaining_time == 0) - IWL_ERR(mvm, "Timed out waiting for HW restart to finish!\n"); + if (remaining_time == 0) + IWL_ERR(mvm, "Timed out waiting for HW restart!\n"); + } ieee80211_iterate_active_interfaces_atomic( mvm->hw, IEEE80211_IFACE_ITER_NORMAL, diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c b/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c index 07da4efe8458..7b7d2a146e30 100644 --- a/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c +++ b/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c @@ -1529,8 +1529,8 @@ static ssize_t iwl_dbgfs_mem_read(struct file *file, char __user *user_buf, .data = { &cmd, }, .len = { sizeof(cmd) }, }; - size_t delta, len; - ssize_t ret; + size_t delta; + ssize_t ret, len; hcmd.id = iwl_cmd_id(*ppos >> 24 ? UMAC_RD_WR : LMAC_RD_WR, DEBUG_GROUP, 0); diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c b/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c index 318efd814037..1db1dc13e988 100644 --- a/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c +++ b/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c @@ -4121,7 +4121,6 @@ void iwl_mvm_sync_rx_queues_internal(struct iwl_mvm *mvm, struct iwl_mvm_internal_rxq_notif *notif, u32 size) { - DECLARE_WAIT_QUEUE_HEAD_ONSTACK(notif_waitq); u32 qmask = BIT(mvm->trans->num_rx_queues) - 1; int ret; @@ -4143,7 +4142,7 @@ void iwl_mvm_sync_rx_queues_internal(struct iwl_mvm *mvm, } if (notif->sync) - ret = wait_event_timeout(notif_waitq, + ret = wait_event_timeout(mvm->rx_sync_waitq, atomic_read(&mvm->queue_sync_counter) == 0, HZ); WARN_ON_ONCE(!ret); diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/mvm.h b/drivers/net/wireless/intel/iwlwifi/mvm/mvm.h index d17cbf603f7c..c60703e0c246 100644 --- a/drivers/net/wireless/intel/iwlwifi/mvm/mvm.h +++ b/drivers/net/wireless/intel/iwlwifi/mvm/mvm.h @@ -937,6 +937,7 @@ struct iwl_mvm { /* sync d0i3_tx queue and IWL_MVM_STATUS_IN_D0I3 status flag */ spinlock_t d0i3_tx_lock; wait_queue_head_t d0i3_exit_waitq; + wait_queue_head_t rx_sync_waitq; /* BT-Coex */ struct iwl_bt_coex_profile_notif last_bt_notif; diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/ops.c b/drivers/net/wireless/intel/iwlwifi/mvm/ops.c index 05fe6dd1a2c8..4d35deb628bc 100644 --- a/drivers/net/wireless/intel/iwlwifi/mvm/ops.c +++ b/drivers/net/wireless/intel/iwlwifi/mvm/ops.c @@ -619,6 +619,7 @@ iwl_op_mode_mvm_start(struct iwl_trans *trans, const struct iwl_cfg *cfg, spin_lock_init(&mvm->refs_lock); skb_queue_head_init(&mvm->d0i3_tx); init_waitqueue_head(&mvm->d0i3_exit_waitq); + init_waitqueue_head(&mvm->rx_sync_waitq); atomic_set(&mvm->queue_sync_counter, 0); diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/rxmq.c b/drivers/net/wireless/intel/iwlwifi/mvm/rxmq.c index a57c6ef5bc14..6c802cee900c 100644 --- a/drivers/net/wireless/intel/iwlwifi/mvm/rxmq.c +++ b/drivers/net/wireless/intel/iwlwifi/mvm/rxmq.c @@ -547,7 +547,8 @@ void iwl_mvm_rx_queue_notif(struct iwl_mvm *mvm, struct iwl_rx_cmd_buffer *rxb, "Received expired RX queue sync message\n"); return; } - atomic_dec(&mvm->queue_sync_counter); + if (!atomic_dec_return(&mvm->queue_sync_counter)) + wake_up(&mvm->rx_sync_waitq); } switch (internal_notif->type) { diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/scan.c b/drivers/net/wireless/intel/iwlwifi/mvm/scan.c index f279fdd6eb44..fa9743205491 100644 --- a/drivers/net/wireless/intel/iwlwifi/mvm/scan.c +++ b/drivers/net/wireless/intel/iwlwifi/mvm/scan.c @@ -1199,6 +1199,9 @@ static int iwl_mvm_num_scans(struct iwl_mvm *mvm) static int iwl_mvm_check_running_scans(struct iwl_mvm *mvm, int type) { + bool unified_image = fw_has_capa(&mvm->fw->ucode_capa, + IWL_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG); + /* This looks a bit arbitrary, but the idea is that if we run * out of possible simultaneous scans and the userspace is * trying to run a scan type that is already running, we @@ -1225,12 +1228,30 @@ static int iwl_mvm_check_running_scans(struct iwl_mvm *mvm, int type) return -EBUSY; return iwl_mvm_scan_stop(mvm, IWL_MVM_SCAN_REGULAR, true); case IWL_MVM_SCAN_NETDETECT: - /* No need to stop anything for net-detect since the - * firmware is restarted anyway. This way, any sched - * scans that were running will be restarted when we - * resume. - */ - return 0; + /* For non-unified images, there's no need to stop + * anything for net-detect since the firmware is + * restarted anyway. This way, any sched scans that + * were running will be restarted when we resume. + */ + if (!unified_image) + return 0; + + /* If this is a unified image and we ran out of scans, + * we need to stop something. Prefer stopping regular + * scans, because the results are useless at this + * point, and we should be able to keep running + * another scheduled scan while suspended. + */ + if (mvm->scan_status & IWL_MVM_SCAN_REGULAR_MASK) + return iwl_mvm_scan_stop(mvm, IWL_MVM_SCAN_REGULAR, + true); + if (mvm->scan_status & IWL_MVM_SCAN_SCHED_MASK) + return iwl_mvm_scan_stop(mvm, IWL_MVM_SCAN_SCHED, + true); + + /* fall through, something is wrong if no scan was + * running but we ran out of scans. + */ default: WARN_ON(1); break; diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/drv.c b/drivers/net/wireless/intel/iwlwifi/pcie/drv.c index 001be406a3d3..2f8134b2a504 100644 --- a/drivers/net/wireless/intel/iwlwifi/pcie/drv.c +++ b/drivers/net/wireless/intel/iwlwifi/pcie/drv.c @@ -541,48 +541,64 @@ static const struct pci_device_id iwl_hw_card_ids[] = { MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids); #ifdef CONFIG_ACPI -#define SPL_METHOD "SPLC" -#define SPL_DOMAINTYPE_MODULE BIT(0) -#define SPL_DOMAINTYPE_WIFI BIT(1) -#define SPL_DOMAINTYPE_WIGIG BIT(2) -#define SPL_DOMAINTYPE_RFEM BIT(3) +#define ACPI_SPLC_METHOD "SPLC" +#define ACPI_SPLC_DOMAIN_WIFI (0x07) -static u64 splx_get_pwr_limit(struct iwl_trans *trans, union acpi_object *splx) +static u64 splc_get_pwr_limit(struct iwl_trans *trans, union acpi_object *splc) { - union acpi_object *limits, *domain_type, *power_limit; - - if (splx->type != ACPI_TYPE_PACKAGE || - splx->package.count != 2 || - splx->package.elements[0].type != ACPI_TYPE_INTEGER || - splx->package.elements[0].integer.value != 0) { - IWL_ERR(trans, "Unsupported splx structure\n"); + union acpi_object *data_pkg, *dflt_pwr_limit; + int i; + + /* We need at least two elements, one for the revision and one + * for the data itself. Also check that the revision is + * supported (currently only revision 0). + */ + if (splc->type != ACPI_TYPE_PACKAGE || + splc->package.count < 2 || + splc->package.elements[0].type != ACPI_TYPE_INTEGER || + splc->package.elements[0].integer.value != 0) { + IWL_DEBUG_INFO(trans, + "Unsupported structure returned by the SPLC method. Ignoring.\n"); return 0; } - limits = &splx->package.elements[1]; - if (limits->type != ACPI_TYPE_PACKAGE || - limits->package.count < 2 || - limits->package.elements[0].type != ACPI_TYPE_INTEGER || - limits->package.elements[1].type != ACPI_TYPE_INTEGER) { - IWL_ERR(trans, "Invalid limits element\n"); - return 0; + /* loop through all the packages to find the one for WiFi */ + for (i = 1; i < splc->package.count; i++) { + union acpi_object *domain; + + data_pkg = &splc->package.elements[i]; + + /* Skip anything that is not a package with the right + * amount of elements (i.e. at least 2 integers). + */ + if (data_pkg->type != ACPI_TYPE_PACKAGE || + data_pkg->package.count < 2 || + data_pkg->package.elements[0].type != ACPI_TYPE_INTEGER || + data_pkg->package.elements[1].type != ACPI_TYPE_INTEGER) + continue; + + domain = &data_pkg->package.elements[0]; + if (domain->integer.value == ACPI_SPLC_DOMAIN_WIFI) + break; + + data_pkg = NULL; } - domain_type = &limits->package.elements[0]; - power_limit = &limits->package.elements[1]; - if (!(domain_type->integer.value & SPL_DOMAINTYPE_WIFI)) { - IWL_DEBUG_INFO(trans, "WiFi power is not limited\n"); + if (!data_pkg) { + IWL_DEBUG_INFO(trans, + "No element for the WiFi domain returned by the SPLC method.\n"); return 0; } - return power_limit->integer.value; + dflt_pwr_limit = &data_pkg->package.elements[1]; + return dflt_pwr_limit->integer.value; } static void set_dflt_pwr_limit(struct iwl_trans *trans, struct pci_dev *pdev) { acpi_handle pxsx_handle; acpi_handle handle; - struct acpi_buffer splx = {ACPI_ALLOCATE_BUFFER, NULL}; + struct acpi_buffer splc = {ACPI_ALLOCATE_BUFFER, NULL}; acpi_status status; pxsx_handle = ACPI_HANDLE(&pdev->dev); @@ -593,23 +609,24 @@ static void set_dflt_pwr_limit(struct iwl_trans *trans, struct pci_dev *pdev) } /* Get the method's handle */ - status = acpi_get_handle(pxsx_handle, (acpi_string)SPL_METHOD, &handle); + status = acpi_get_handle(pxsx_handle, (acpi_string)ACPI_SPLC_METHOD, + &handle); if (ACPI_FAILURE(status)) { - IWL_DEBUG_INFO(trans, "SPL method not found\n"); + IWL_DEBUG_INFO(trans, "SPLC method not found\n"); return; } /* Call SPLC with no arguments */ - status = acpi_evaluate_object(handle, NULL, NULL, &splx); + status = acpi_evaluate_object(handle, NULL, NULL, &splc); if (ACPI_FAILURE(status)) { IWL_ERR(trans, "SPLC invocation failed (0x%x)\n", status); return; } - trans->dflt_pwr_limit = splx_get_pwr_limit(trans, splx.pointer); + trans->dflt_pwr_limit = splc_get_pwr_limit(trans, splc.pointer); IWL_DEBUG_INFO(trans, "Default power limit set to %lld\n", trans->dflt_pwr_limit); - kfree(splx.pointer); + kfree(splc.pointer); } #else /* CONFIG_ACPI */ diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/tx.c b/drivers/net/wireless/intel/iwlwifi/pcie/tx.c index e9a278b60dfd..5f840f16f40b 100644 --- a/drivers/net/wireless/intel/iwlwifi/pcie/tx.c +++ b/drivers/net/wireless/intel/iwlwifi/pcie/tx.c @@ -592,6 +592,7 @@ error: static int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq, int slots_num, u32 txq_id) { + struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); int ret; txq->need_update = false; @@ -606,6 +607,13 @@ static int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq, return ret; spin_lock_init(&txq->lock); + + if (txq_id == trans_pcie->cmd_queue) { + static struct lock_class_key iwl_pcie_cmd_queue_lock_class; + + lockdep_set_class(&txq->lock, &iwl_pcie_cmd_queue_lock_class); + } + __skb_queue_head_init(&txq->overflow_q); /* diff --git a/drivers/net/wireless/mac80211_hwsim.c b/drivers/net/wireless/mac80211_hwsim.c index 431f13b4faf6..d3bad5779376 100644 --- a/drivers/net/wireless/mac80211_hwsim.c +++ b/drivers/net/wireless/mac80211_hwsim.c @@ -826,7 +826,7 @@ static void mac80211_hwsim_set_tsf(struct ieee80211_hw *hw, data->bcn_delta = do_div(delta, bcn_int); } else { data->tsf_offset -= delta; - data->bcn_delta = -do_div(delta, bcn_int); + data->bcn_delta = -(s64)do_div(delta, bcn_int); } } diff --git a/drivers/net/wireless/marvell/mwifiex/cfg80211.c b/drivers/net/wireless/marvell/mwifiex/cfg80211.c index 39ce76ad00bc..16241d21727b 100644 --- a/drivers/net/wireless/marvell/mwifiex/cfg80211.c +++ b/drivers/net/wireless/marvell/mwifiex/cfg80211.c @@ -2222,8 +2222,9 @@ done: is_scanning_required = 1; } else { mwifiex_dbg(priv->adapter, MSG, - "info: trying to associate to '%s' bssid %pM\n", - (char *)req_ssid.ssid, bss->bssid); + "info: trying to associate to '%.*s' bssid %pM\n", + req_ssid.ssid_len, (char *)req_ssid.ssid, + bss->bssid); memcpy(&priv->cfg_bssid, bss->bssid, ETH_ALEN); break; } @@ -2283,8 +2284,8 @@ mwifiex_cfg80211_connect(struct wiphy *wiphy, struct net_device *dev, } mwifiex_dbg(adapter, INFO, - "info: Trying to associate to %s and bssid %pM\n", - (char *)sme->ssid, sme->bssid); + "info: Trying to associate to %.*s and bssid %pM\n", + (int)sme->ssid_len, (char *)sme->ssid, sme->bssid); if (!mwifiex_stop_bg_scan(priv)) cfg80211_sched_scan_stopped_rtnl(priv->wdev.wiphy); @@ -2417,8 +2418,8 @@ mwifiex_cfg80211_join_ibss(struct wiphy *wiphy, struct net_device *dev, } mwifiex_dbg(priv->adapter, MSG, - "info: trying to join to %s and bssid %pM\n", - (char *)params->ssid, params->bssid); + "info: trying to join to %.*s and bssid %pM\n", + params->ssid_len, (char *)params->ssid, params->bssid); mwifiex_set_ibss_params(priv, params); diff --git a/drivers/net/xen-netfront.c b/drivers/net/xen-netfront.c index e17879dd5d5a..bf2744e1e3db 100644 --- a/drivers/net/xen-netfront.c +++ b/drivers/net/xen-netfront.c @@ -304,7 +304,7 @@ static void xennet_alloc_rx_buffers(struct netfront_queue *queue) queue->rx_skbs[id] = skb; ref = gnttab_claim_grant_reference(&queue->gref_rx_head); - BUG_ON((signed short)ref < 0); + WARN_ON_ONCE(IS_ERR_VALUE((unsigned long)(int)ref)); queue->grant_rx_ref[id] = ref; page = skb_frag_page(&skb_shinfo(skb)->frags[0]); @@ -428,7 +428,7 @@ static void xennet_tx_setup_grant(unsigned long gfn, unsigned int offset, id = get_id_from_freelist(&queue->tx_skb_freelist, queue->tx_skbs); tx = RING_GET_REQUEST(&queue->tx, queue->tx.req_prod_pvt++); ref = gnttab_claim_grant_reference(&queue->gref_tx_head); - BUG_ON((signed short)ref < 0); + WARN_ON_ONCE(IS_ERR_VALUE((unsigned long)(int)ref)); gnttab_grant_foreign_access_ref(ref, queue->info->xbdev->otherend_id, gfn, GNTMAP_readonly); diff --git a/drivers/nfc/mei_phy.c b/drivers/nfc/mei_phy.c index 83deda4bb4d6..6f9563a96488 100644 --- a/drivers/nfc/mei_phy.c +++ b/drivers/nfc/mei_phy.c @@ -133,7 +133,7 @@ static int mei_nfc_if_version(struct nfc_mei_phy *phy) return -ENOMEM; bytes_recv = mei_cldev_recv(phy->cldev, (u8 *)reply, if_version_length); - if (bytes_recv < 0 || bytes_recv < sizeof(struct mei_nfc_reply)) { + if (bytes_recv < 0 || bytes_recv < if_version_length) { pr_err("Could not read IF version\n"); r = -EIO; goto err; diff --git a/drivers/ntb/hw/intel/ntb_hw_intel.c b/drivers/ntb/hw/intel/ntb_hw_intel.c index 0d5c29ae51de..7310a261c858 100644 --- a/drivers/ntb/hw/intel/ntb_hw_intel.c +++ b/drivers/ntb/hw/intel/ntb_hw_intel.c @@ -112,17 +112,17 @@ MODULE_PARM_DESC(xeon_b2b_usd_bar2_addr64, module_param_named(xeon_b2b_usd_bar4_addr64, xeon_b2b_usd_addr.bar4_addr64, ullong, 0644); -MODULE_PARM_DESC(xeon_b2b_usd_bar2_addr64, +MODULE_PARM_DESC(xeon_b2b_usd_bar4_addr64, "XEON B2B USD BAR 4 64-bit address"); module_param_named(xeon_b2b_usd_bar4_addr32, xeon_b2b_usd_addr.bar4_addr32, ullong, 0644); -MODULE_PARM_DESC(xeon_b2b_usd_bar2_addr64, +MODULE_PARM_DESC(xeon_b2b_usd_bar4_addr32, "XEON B2B USD split-BAR 4 32-bit address"); module_param_named(xeon_b2b_usd_bar5_addr32, xeon_b2b_usd_addr.bar5_addr32, ullong, 0644); -MODULE_PARM_DESC(xeon_b2b_usd_bar2_addr64, +MODULE_PARM_DESC(xeon_b2b_usd_bar5_addr32, "XEON B2B USD split-BAR 5 32-bit address"); module_param_named(xeon_b2b_dsd_bar2_addr64, @@ -132,17 +132,17 @@ MODULE_PARM_DESC(xeon_b2b_dsd_bar2_addr64, module_param_named(xeon_b2b_dsd_bar4_addr64, xeon_b2b_dsd_addr.bar4_addr64, ullong, 0644); -MODULE_PARM_DESC(xeon_b2b_dsd_bar2_addr64, +MODULE_PARM_DESC(xeon_b2b_dsd_bar4_addr64, "XEON B2B DSD BAR 4 64-bit address"); module_param_named(xeon_b2b_dsd_bar4_addr32, xeon_b2b_dsd_addr.bar4_addr32, ullong, 0644); -MODULE_PARM_DESC(xeon_b2b_dsd_bar2_addr64, +MODULE_PARM_DESC(xeon_b2b_dsd_bar4_addr32, "XEON B2B DSD split-BAR 4 32-bit address"); module_param_named(xeon_b2b_dsd_bar5_addr32, xeon_b2b_dsd_addr.bar5_addr32, ullong, 0644); -MODULE_PARM_DESC(xeon_b2b_dsd_bar2_addr64, +MODULE_PARM_DESC(xeon_b2b_dsd_bar5_addr32, "XEON B2B DSD split-BAR 5 32-bit address"); #ifndef ioread64 @@ -1755,6 +1755,8 @@ static int xeon_setup_b2b_mw(struct intel_ntb_dev *ndev, XEON_B2B_MIN_SIZE); if (!ndev->peer_mmio) return -EIO; + + ndev->peer_addr = pci_resource_start(pdev, b2b_bar); } return 0; @@ -2019,6 +2021,7 @@ static int intel_ntb_init_pci(struct intel_ntb_dev *ndev, struct pci_dev *pdev) goto err_mmio; } ndev->peer_mmio = ndev->self_mmio; + ndev->peer_addr = pci_resource_start(pdev, 0); return 0; diff --git a/drivers/ntb/ntb_transport.c b/drivers/ntb/ntb_transport.c index 8601c10acf74..4eb8adb34508 100644 --- a/drivers/ntb/ntb_transport.c +++ b/drivers/ntb/ntb_transport.c @@ -257,7 +257,7 @@ enum { #define NTB_QP_DEF_NUM_ENTRIES 100 #define NTB_LINK_DOWN_TIMEOUT 10 #define DMA_RETRIES 20 -#define DMA_OUT_RESOURCE_TO 50 +#define DMA_OUT_RESOURCE_TO msecs_to_jiffies(50) static void ntb_transport_rxc_db(unsigned long data); static const struct ntb_ctx_ops ntb_transport_ops; diff --git a/drivers/ntb/test/ntb_perf.c b/drivers/ntb/test/ntb_perf.c index 6a50f20bf1cd..e75d4fdc0866 100644 --- a/drivers/ntb/test/ntb_perf.c +++ b/drivers/ntb/test/ntb_perf.c @@ -72,7 +72,7 @@ #define MAX_THREADS 32 #define MAX_TEST_SIZE SZ_1M #define MAX_SRCS 32 -#define DMA_OUT_RESOURCE_TO 50 +#define DMA_OUT_RESOURCE_TO msecs_to_jiffies(50) #define DMA_RETRIES 20 #define SZ_4G (1ULL << 32) #define MAX_SEG_ORDER 20 /* no larger than 1M for kmalloc buffer */ @@ -589,7 +589,7 @@ static ssize_t debugfs_run_read(struct file *filp, char __user *ubuf, return -ENOMEM; if (mutex_is_locked(&perf->run_mutex)) { - out_off = snprintf(buf, 64, "running\n"); + out_off = scnprintf(buf, 64, "running\n"); goto read_from_buf; } @@ -600,14 +600,14 @@ static ssize_t debugfs_run_read(struct file *filp, char __user *ubuf, break; if (pctx->status) { - out_off += snprintf(buf + out_off, 1024 - out_off, + out_off += scnprintf(buf + out_off, 1024 - out_off, "%d: error %d\n", i, pctx->status); continue; } rate = div64_u64(pctx->copied, pctx->diff_us); - out_off += snprintf(buf + out_off, 1024 - out_off, + out_off += scnprintf(buf + out_off, 1024 - out_off, "%d: copied %llu bytes in %llu usecs, %llu MBytes/s\n", i, pctx->copied, pctx->diff_us, rate); } diff --git a/drivers/ntb/test/ntb_pingpong.c b/drivers/ntb/test/ntb_pingpong.c index 7d311799fca1..435861189d97 100644 --- a/drivers/ntb/test/ntb_pingpong.c +++ b/drivers/ntb/test/ntb_pingpong.c @@ -88,7 +88,7 @@ MODULE_PARM_DESC(delay_ms, "Milliseconds to delay the response to peer"); static unsigned long db_init = 0x7; module_param(db_init, ulong, 0644); -MODULE_PARM_DESC(delay_ms, "Initial doorbell bits to ring on the peer"); +MODULE_PARM_DESC(db_init, "Initial doorbell bits to ring on the peer"); struct pp_ctx { struct ntb_dev *ntb; diff --git a/drivers/nvme/host/lightnvm.c b/drivers/nvme/host/lightnvm.c index f5e3011e31fc..5daf2f4be0cd 100644 --- a/drivers/nvme/host/lightnvm.c +++ b/drivers/nvme/host/lightnvm.c @@ -612,7 +612,7 @@ int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, int node, ret = nvm_register(dev); - ns->lba_shift = ilog2(dev->sec_size) - 9; + ns->lba_shift = ilog2(dev->sec_size); if (sysfs_create_group(&dev->dev.kobj, attrs)) pr_warn("%s: failed to create sysfs group for identification\n", diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c index 0248d0e21fee..5e52034ab010 100644 --- a/drivers/nvme/host/pci.c +++ b/drivers/nvme/host/pci.c @@ -1242,20 +1242,16 @@ static int nvme_configure_admin_queue(struct nvme_dev *dev) result = nvme_enable_ctrl(&dev->ctrl, cap); if (result) - goto free_nvmeq; + return result; nvmeq->cq_vector = 0; result = queue_request_irq(nvmeq); if (result) { nvmeq->cq_vector = -1; - goto free_nvmeq; + return result; } return result; - - free_nvmeq: - nvme_free_queues(dev, 0); - return result; } static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) @@ -1317,10 +1313,8 @@ static int nvme_create_io_queues(struct nvme_dev *dev) max = min(dev->max_qid, dev->queue_count - 1); for (i = dev->online_queues; i <= max; i++) { ret = nvme_create_queue(dev->queues[i], i); - if (ret) { - nvme_free_queues(dev, i); + if (ret) break; - } } /* @@ -1460,13 +1454,9 @@ static int nvme_setup_io_queues(struct nvme_dev *dev) result = queue_request_irq(adminq); if (result) { adminq->cq_vector = -1; - goto free_queues; + return result; } return nvme_create_io_queues(dev); - - free_queues: - nvme_free_queues(dev, 1); - return result; } static void nvme_del_queue_end(struct request *req, int error) diff --git a/drivers/nvme/host/rdma.c b/drivers/nvme/host/rdma.c index 5a8388177959..3d25add36d91 100644 --- a/drivers/nvme/host/rdma.c +++ b/drivers/nvme/host/rdma.c @@ -83,6 +83,7 @@ enum nvme_rdma_queue_flags { NVME_RDMA_Q_CONNECTED = (1 << 0), NVME_RDMA_IB_QUEUE_ALLOCATED = (1 << 1), NVME_RDMA_Q_DELETING = (1 << 2), + NVME_RDMA_Q_LIVE = (1 << 3), }; struct nvme_rdma_queue { @@ -624,10 +625,18 @@ static int nvme_rdma_connect_io_queues(struct nvme_rdma_ctrl *ctrl) for (i = 1; i < ctrl->queue_count; i++) { ret = nvmf_connect_io_queue(&ctrl->ctrl, i); - if (ret) - break; + if (ret) { + dev_info(ctrl->ctrl.device, + "failed to connect i/o queue: %d\n", ret); + goto out_free_queues; + } + set_bit(NVME_RDMA_Q_LIVE, &ctrl->queues[i].flags); } + return 0; + +out_free_queues: + nvme_rdma_free_io_queues(ctrl); return ret; } @@ -712,6 +721,8 @@ static void nvme_rdma_reconnect_ctrl_work(struct work_struct *work) if (ret) goto stop_admin_q; + set_bit(NVME_RDMA_Q_LIVE, &ctrl->queues[0].flags); + ret = nvme_enable_ctrl(&ctrl->ctrl, ctrl->cap); if (ret) goto stop_admin_q; @@ -761,8 +772,10 @@ static void nvme_rdma_error_recovery_work(struct work_struct *work) nvme_stop_keep_alive(&ctrl->ctrl); - for (i = 0; i < ctrl->queue_count; i++) + for (i = 0; i < ctrl->queue_count; i++) { clear_bit(NVME_RDMA_Q_CONNECTED, &ctrl->queues[i].flags); + clear_bit(NVME_RDMA_Q_LIVE, &ctrl->queues[i].flags); + } if (ctrl->queue_count > 1) nvme_stop_queues(&ctrl->ctrl); @@ -1378,6 +1391,24 @@ nvme_rdma_timeout(struct request *rq, bool reserved) return BLK_EH_HANDLED; } +/* + * We cannot accept any other command until the Connect command has completed. + */ +static inline bool nvme_rdma_queue_is_ready(struct nvme_rdma_queue *queue, + struct request *rq) +{ + if (unlikely(!test_bit(NVME_RDMA_Q_LIVE, &queue->flags))) { + struct nvme_command *cmd = (struct nvme_command *)rq->cmd; + + if (rq->cmd_type != REQ_TYPE_DRV_PRIV || + cmd->common.opcode != nvme_fabrics_command || + cmd->fabrics.fctype != nvme_fabrics_type_connect) + return false; + } + + return true; +} + static int nvme_rdma_queue_rq(struct blk_mq_hw_ctx *hctx, const struct blk_mq_queue_data *bd) { @@ -1394,6 +1425,9 @@ static int nvme_rdma_queue_rq(struct blk_mq_hw_ctx *hctx, WARN_ON_ONCE(rq->tag < 0); + if (!nvme_rdma_queue_is_ready(queue, rq)) + return BLK_MQ_RQ_QUEUE_BUSY; + dev = queue->device->dev; ib_dma_sync_single_for_cpu(dev, sqe->dma, sizeof(struct nvme_command), DMA_TO_DEVICE); @@ -1544,6 +1578,8 @@ static int nvme_rdma_configure_admin_queue(struct nvme_rdma_ctrl *ctrl) if (error) goto out_cleanup_queue; + set_bit(NVME_RDMA_Q_LIVE, &ctrl->queues[0].flags); + error = nvmf_reg_read64(&ctrl->ctrl, NVME_REG_CAP, &ctrl->cap); if (error) { dev_err(ctrl->ctrl.device, diff --git a/drivers/nvme/target/core.c b/drivers/nvme/target/core.c index b4cacb6f0258..a21437a33adb 100644 --- a/drivers/nvme/target/core.c +++ b/drivers/nvme/target/core.c @@ -838,9 +838,13 @@ static void nvmet_fatal_error_handler(struct work_struct *work) void nvmet_ctrl_fatal_error(struct nvmet_ctrl *ctrl) { - ctrl->csts |= NVME_CSTS_CFS; - INIT_WORK(&ctrl->fatal_err_work, nvmet_fatal_error_handler); - schedule_work(&ctrl->fatal_err_work); + mutex_lock(&ctrl->lock); + if (!(ctrl->csts & NVME_CSTS_CFS)) { + ctrl->csts |= NVME_CSTS_CFS; + INIT_WORK(&ctrl->fatal_err_work, nvmet_fatal_error_handler); + schedule_work(&ctrl->fatal_err_work); + } + mutex_unlock(&ctrl->lock); } EXPORT_SYMBOL_GPL(nvmet_ctrl_fatal_error); diff --git a/drivers/nvme/target/rdma.c b/drivers/nvme/target/rdma.c index f8d23999e0f2..005ef5d17a19 100644 --- a/drivers/nvme/target/rdma.c +++ b/drivers/nvme/target/rdma.c @@ -951,6 +951,7 @@ err_destroy_cq: static void nvmet_rdma_destroy_queue_ib(struct nvmet_rdma_queue *queue) { + ib_drain_qp(queue->cm_id->qp); rdma_destroy_qp(queue->cm_id); ib_free_cq(queue->cq); } @@ -1066,6 +1067,7 @@ nvmet_rdma_alloc_queue(struct nvmet_rdma_device *ndev, spin_lock_init(&queue->rsp_wr_wait_lock); INIT_LIST_HEAD(&queue->free_rsps); spin_lock_init(&queue->rsps_lock); + INIT_LIST_HEAD(&queue->queue_list); queue->idx = ida_simple_get(&nvmet_rdma_queue_ida, 0, 0, GFP_KERNEL); if (queue->idx < 0) { @@ -1244,7 +1246,6 @@ static void __nvmet_rdma_queue_disconnect(struct nvmet_rdma_queue *queue) if (disconnect) { rdma_disconnect(queue->cm_id); - ib_drain_qp(queue->cm_id->qp); schedule_work(&queue->release_work); } } @@ -1269,7 +1270,12 @@ static void nvmet_rdma_queue_connect_fail(struct rdma_cm_id *cm_id, { WARN_ON_ONCE(queue->state != NVMET_RDMA_Q_CONNECTING); - pr_err("failed to connect queue\n"); + mutex_lock(&nvmet_rdma_queue_mutex); + if (!list_empty(&queue->queue_list)) + list_del_init(&queue->queue_list); + mutex_unlock(&nvmet_rdma_queue_mutex); + + pr_err("failed to connect queue %d\n", queue->idx); schedule_work(&queue->release_work); } @@ -1352,7 +1358,13 @@ static int nvmet_rdma_cm_handler(struct rdma_cm_id *cm_id, case RDMA_CM_EVENT_ADDR_CHANGE: case RDMA_CM_EVENT_DISCONNECTED: case RDMA_CM_EVENT_TIMEWAIT_EXIT: - nvmet_rdma_queue_disconnect(queue); + /* + * We might end up here when we already freed the qp + * which means queue release sequence is in progress, + * so don't get in the way... + */ + if (queue) + nvmet_rdma_queue_disconnect(queue); break; case RDMA_CM_EVENT_DEVICE_REMOVAL: ret = nvmet_rdma_device_removal(cm_id, queue); diff --git a/drivers/of/base.c b/drivers/of/base.c index d687e6de24a0..a0bccb54a9bd 100644 --- a/drivers/of/base.c +++ b/drivers/of/base.c @@ -2077,8 +2077,6 @@ void of_alias_scan(void * (*dt_alloc)(u64 size, u64 align)) name = of_get_property(of_aliases, "stdout", NULL); if (name) of_stdout = of_find_node_opts_by_path(name, &of_stdout_options); - if (of_stdout) - console_set_by_of(); } if (!of_aliases) diff --git a/drivers/of/of_mdio.c b/drivers/of/of_mdio.c index b470f7e3521d..262281bd68fa 100644 --- a/drivers/of/of_mdio.c +++ b/drivers/of/of_mdio.c @@ -292,6 +292,7 @@ struct phy_device *of_phy_find_device(struct device_node *phy_np) mdiodev = to_mdio_device(d); if (mdiodev->flags & MDIO_DEVICE_FLAG_PHY) return to_phy_device(d); + put_device(d); } return NULL; @@ -456,8 +457,11 @@ int of_phy_register_fixed_link(struct device_node *np) status.link = 1; status.duplex = of_property_read_bool(fixed_link_node, "full-duplex"); - if (of_property_read_u32(fixed_link_node, "speed", &status.speed)) + if (of_property_read_u32(fixed_link_node, "speed", + &status.speed)) { + of_node_put(fixed_link_node); return -EINVAL; + } status.pause = of_property_read_bool(fixed_link_node, "pause"); status.asym_pause = of_property_read_bool(fixed_link_node, "asym-pause"); @@ -486,3 +490,18 @@ int of_phy_register_fixed_link(struct device_node *np) return -ENODEV; } EXPORT_SYMBOL(of_phy_register_fixed_link); + +void of_phy_deregister_fixed_link(struct device_node *np) +{ + struct phy_device *phydev; + + phydev = of_phy_find_device(np); + if (!phydev) + return; + + fixed_phy_unregister(phydev); + + put_device(&phydev->mdio.dev); /* of_phy_find_device() */ + phy_device_free(phydev); /* fixed_phy_register() */ +} +EXPORT_SYMBOL(of_phy_deregister_fixed_link); diff --git a/drivers/pci/host/pcie-designware-plat.c b/drivers/pci/host/pcie-designware-plat.c index 8df6312ed300..1a02038c4640 100644 --- a/drivers/pci/host/pcie-designware-plat.c +++ b/drivers/pci/host/pcie-designware-plat.c @@ -3,7 +3,7 @@ * * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com) * - * Authors: Joao Pinto <jpmpinto@gmail.com> + * Authors: Joao Pinto <Joao.Pinto@synopsys.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c index e0b22dab9b7a..e04f69beb42d 100644 --- a/drivers/pci/host/pcie-rockchip.c +++ b/drivers/pci/host/pcie-rockchip.c @@ -190,6 +190,9 @@ struct rockchip_pcie { struct reset_control *mgmt_rst; struct reset_control *mgmt_sticky_rst; struct reset_control *pipe_rst; + struct reset_control *pm_rst; + struct reset_control *aclk_rst; + struct reset_control *pclk_rst; struct clk *aclk_pcie; struct clk *aclk_perf_pcie; struct clk *hclk_pcie; @@ -408,6 +411,44 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) gpiod_set_value(rockchip->ep_gpio, 0); + err = reset_control_assert(rockchip->aclk_rst); + if (err) { + dev_err(dev, "assert aclk_rst err %d\n", err); + return err; + } + + err = reset_control_assert(rockchip->pclk_rst); + if (err) { + dev_err(dev, "assert pclk_rst err %d\n", err); + return err; + } + + err = reset_control_assert(rockchip->pm_rst); + if (err) { + dev_err(dev, "assert pm_rst err %d\n", err); + return err; + } + + udelay(10); + + err = reset_control_deassert(rockchip->pm_rst); + if (err) { + dev_err(dev, "deassert pm_rst err %d\n", err); + return err; + } + + err = reset_control_deassert(rockchip->aclk_rst); + if (err) { + dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err); + return err; + } + + err = reset_control_deassert(rockchip->pclk_rst); + if (err) { + dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err); + return err; + } + err = phy_init(rockchip->phy); if (err < 0) { dev_err(dev, "fail to init phy, err %d\n", err); @@ -781,6 +822,27 @@ static int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) return PTR_ERR(rockchip->pipe_rst); } + rockchip->pm_rst = devm_reset_control_get(dev, "pm"); + if (IS_ERR(rockchip->pm_rst)) { + if (PTR_ERR(rockchip->pm_rst) != -EPROBE_DEFER) + dev_err(dev, "missing pm reset property in node\n"); + return PTR_ERR(rockchip->pm_rst); + } + + rockchip->pclk_rst = devm_reset_control_get(dev, "pclk"); + if (IS_ERR(rockchip->pclk_rst)) { + if (PTR_ERR(rockchip->pclk_rst) != -EPROBE_DEFER) + dev_err(dev, "missing pclk reset property in node\n"); + return PTR_ERR(rockchip->pclk_rst); + } + + rockchip->aclk_rst = devm_reset_control_get(dev, "aclk"); + if (IS_ERR(rockchip->aclk_rst)) { + if (PTR_ERR(rockchip->aclk_rst) != -EPROBE_DEFER) + dev_err(dev, "missing aclk reset property in node\n"); + return PTR_ERR(rockchip->aclk_rst); + } + rockchip->ep_gpio = devm_gpiod_get(dev, "ep", GPIOD_OUT_HIGH); if (IS_ERR(rockchip->ep_gpio)) { dev_err(dev, "missing ep-gpios property in node\n"); diff --git a/drivers/pci/pci-mid.c b/drivers/pci/pci-mid.c index 55f453de562e..c7f3408e3148 100644 --- a/drivers/pci/pci-mid.c +++ b/drivers/pci/pci-mid.c @@ -29,6 +29,11 @@ static int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state) return intel_mid_pci_set_power_state(pdev, state); } +static pci_power_t mid_pci_get_power_state(struct pci_dev *pdev) +{ + return intel_mid_pci_get_power_state(pdev); +} + static pci_power_t mid_pci_choose_state(struct pci_dev *pdev) { return PCI_D3hot; @@ -52,6 +57,7 @@ static bool mid_pci_need_resume(struct pci_dev *dev) static struct pci_platform_pm_ops mid_pci_platform_pm = { .is_manageable = mid_pci_power_manageable, .set_state = mid_pci_set_power_state, + .get_state = mid_pci_get_power_state, .choose_state = mid_pci_choose_state, .sleep_wake = mid_pci_sleep_wake, .run_wake = mid_pci_run_wake, diff --git a/drivers/pci/pcie/aer/aer_inject.c b/drivers/pci/pcie/aer/aer_inject.c index db553dc22c8e..2b6a59266689 100644 --- a/drivers/pci/pcie/aer/aer_inject.c +++ b/drivers/pci/pcie/aer/aer_inject.c @@ -307,20 +307,6 @@ out: return 0; } -static struct pci_dev *pcie_find_root_port(struct pci_dev *dev) -{ - while (1) { - if (!pci_is_pcie(dev)) - break; - if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) - return dev; - if (!dev->bus->self) - break; - dev = dev->bus->self; - } - return NULL; -} - static int find_aer_device_iter(struct device *device, void *data) { struct pcie_device **result = data; diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index ab002671fa60..104c46d53121 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1439,6 +1439,21 @@ static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp) dev_warn(&dev->dev, "PCI-X settings not supported\n"); } +static bool pcie_root_rcb_set(struct pci_dev *dev) +{ + struct pci_dev *rp = pcie_find_root_port(dev); + u16 lnkctl; + + if (!rp) + return false; + + pcie_capability_read_word(rp, PCI_EXP_LNKCTL, &lnkctl); + if (lnkctl & PCI_EXP_LNKCTL_RCB) + return true; + + return false; +} + static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp) { int pos; @@ -1468,9 +1483,20 @@ static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp) ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or); /* Initialize Link Control Register */ - if (pcie_cap_has_lnkctl(dev)) + if (pcie_cap_has_lnkctl(dev)) { + + /* + * If the Root Port supports Read Completion Boundary of + * 128, set RCB to 128. Otherwise, clear it. + */ + hpp->pci_exp_lnkctl_and |= PCI_EXP_LNKCTL_RCB; + hpp->pci_exp_lnkctl_or &= ~PCI_EXP_LNKCTL_RCB; + if (pcie_root_rcb_set(dev)) + hpp->pci_exp_lnkctl_or |= PCI_EXP_LNKCTL_RCB; + pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL, ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or); + } /* Find Advanced Error Reporting Enhanced Capability */ pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c index 66c4d8f42233..9526e341988b 100644 --- a/drivers/pci/setup-res.c +++ b/drivers/pci/setup-res.c @@ -121,6 +121,14 @@ int pci_claim_resource(struct pci_dev *dev, int resource) return -EINVAL; } + /* + * If we have a shadow copy in RAM, the PCI device doesn't respond + * to the shadow range, so we don't need to claim it, and upstream + * bridges don't need to route the range to the device. + */ + if (res->flags & IORESOURCE_ROM_SHADOW) + return 0; + root = pci_find_parent_resource(dev, res); if (!root) { dev_info(&dev->dev, "can't claim BAR %d %pR: no compatible bridge window\n", diff --git a/drivers/pcmcia/soc_common.c b/drivers/pcmcia/soc_common.c index 153f3122283d..b6b316de055c 100644 --- a/drivers/pcmcia/soc_common.c +++ b/drivers/pcmcia/soc_common.c @@ -107,7 +107,7 @@ int soc_pcmcia_regulator_set(struct soc_pcmcia_socket *skt, ret = regulator_enable(r->reg); } else { - regulator_disable(r->reg); + ret = regulator_disable(r->reg); } if (ret == 0) r->on = on; diff --git a/drivers/phy/phy-da8xx-usb.c b/drivers/phy/phy-da8xx-usb.c index 32ae78c8ca17..c85fb0b59729 100644 --- a/drivers/phy/phy-da8xx-usb.c +++ b/drivers/phy/phy-da8xx-usb.c @@ -198,7 +198,8 @@ static int da8xx_usb_phy_probe(struct platform_device *pdev) } else { int ret; - ret = phy_create_lookup(d_phy->usb11_phy, "usb-phy", "ohci.0"); + ret = phy_create_lookup(d_phy->usb11_phy, "usb-phy", + "ohci-da8xx"); if (ret) dev_warn(dev, "Failed to create usb11 phy lookup\n"); ret = phy_create_lookup(d_phy->usb20_phy, "usb-phy", @@ -216,7 +217,7 @@ static int da8xx_usb_phy_remove(struct platform_device *pdev) if (!pdev->dev.of_node) { phy_remove_lookup(d_phy->usb20_phy, "usb-phy", "musb-da8xx"); - phy_remove_lookup(d_phy->usb11_phy, "usb-phy", "ohci.0"); + phy_remove_lookup(d_phy->usb11_phy, "usb-phy", "ohci-da8xx"); } return 0; diff --git a/drivers/phy/phy-rockchip-pcie.c b/drivers/phy/phy-rockchip-pcie.c index a2b4c6b58aea..6904633cad68 100644 --- a/drivers/phy/phy-rockchip-pcie.c +++ b/drivers/phy/phy-rockchip-pcie.c @@ -249,21 +249,10 @@ err_refclk: static int rockchip_pcie_phy_exit(struct phy *phy) { struct rockchip_pcie_phy *rk_phy = phy_get_drvdata(phy); - int err = 0; clk_disable_unprepare(rk_phy->clk_pciephy_ref); - err = reset_control_deassert(rk_phy->phy_rst); - if (err) { - dev_err(&phy->dev, "deassert phy_rst err %d\n", err); - goto err_reset; - } - - return err; - -err_reset: - clk_prepare_enable(rk_phy->clk_pciephy_ref); - return err; + return 0; } static const struct phy_ops ops = { diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c index b9342a2af7b3..fec34f5213c4 100644 --- a/drivers/phy/phy-sun4i-usb.c +++ b/drivers/phy/phy-sun4i-usb.c @@ -264,7 +264,7 @@ static int sun4i_usb_phy_init(struct phy *_phy) return ret; } - if (data->cfg->enable_pmu_unk1) { + if (phy->pmu && data->cfg->enable_pmu_unk1) { val = readl(phy->pmu + REG_PMU_UNK1); writel(val & ~2, phy->pmu + REG_PMU_UNK1); } diff --git a/drivers/phy/phy-twl4030-usb.c b/drivers/phy/phy-twl4030-usb.c index 87e6334eab93..547ca7b3f098 100644 --- a/drivers/phy/phy-twl4030-usb.c +++ b/drivers/phy/phy-twl4030-usb.c @@ -459,8 +459,6 @@ static int twl4030_phy_power_off(struct phy *phy) struct twl4030_usb *twl = phy_get_drvdata(phy); dev_dbg(twl->dev, "%s\n", __func__); - pm_runtime_mark_last_busy(twl->dev); - pm_runtime_put_autosuspend(twl->dev); return 0; } @@ -472,6 +470,8 @@ static int twl4030_phy_power_on(struct phy *phy) dev_dbg(twl->dev, "%s\n", __func__); pm_runtime_get_sync(twl->dev); schedule_delayed_work(&twl->id_workaround_work, HZ); + pm_runtime_mark_last_busy(twl->dev); + pm_runtime_put_autosuspend(twl->dev); return 0; } diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c index c8c72e8259d3..87b46390b695 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c @@ -26,7 +26,7 @@ #define ASPEED_G5_NR_PINS 228 -#define COND1 SIG_DESC_BIT(SCU90, 6, 0) +#define COND1 { SCU90, BIT(6), 0, 0 } #define COND2 { SCU94, GENMASK(1, 0), 0, 0 } #define B14 0 diff --git a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c index 7f7700716398..5d1e505c3c63 100644 --- a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c @@ -844,6 +844,6 @@ static struct platform_driver iproc_gpio_driver = { static int __init iproc_gpio_init(void) { - return platform_driver_probe(&iproc_gpio_driver, iproc_gpio_probe); + return platform_driver_register(&iproc_gpio_driver); } arch_initcall_sync(iproc_gpio_init); diff --git a/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c b/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c index 35783db1c10b..c8deb8be1da7 100644 --- a/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c @@ -741,6 +741,6 @@ static struct platform_driver nsp_gpio_driver = { static int __init nsp_gpio_init(void) { - return platform_driver_probe(&nsp_gpio_driver, nsp_gpio_probe); + return platform_driver_register(&nsp_gpio_driver); } arch_initcall_sync(nsp_gpio_init); diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index 47613201269a..79c4e14a5a75 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -687,6 +687,7 @@ static int imx_pinctrl_probe_dt(struct platform_device *pdev, if (!info->functions) return -ENOMEM; + info->group_index = 0; if (flat_funcs) { info->ngroups = of_get_child_count(np); } else { diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index 30389f4ccab4..c43b1e9a06af 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -1652,12 +1652,15 @@ static int chv_pinctrl_probe(struct platform_device *pdev) } #ifdef CONFIG_PM_SLEEP -static int chv_pinctrl_suspend(struct device *dev) +static int chv_pinctrl_suspend_noirq(struct device *dev) { struct platform_device *pdev = to_platform_device(dev); struct chv_pinctrl *pctrl = platform_get_drvdata(pdev); + unsigned long flags; int i; + raw_spin_lock_irqsave(&chv_lock, flags); + pctrl->saved_intmask = readl(pctrl->regs + CHV_INTMASK); for (i = 0; i < pctrl->community->npins; i++) { @@ -1678,15 +1681,20 @@ static int chv_pinctrl_suspend(struct device *dev) ctx->padctrl1 = readl(reg); } + raw_spin_unlock_irqrestore(&chv_lock, flags); + return 0; } -static int chv_pinctrl_resume(struct device *dev) +static int chv_pinctrl_resume_noirq(struct device *dev) { struct platform_device *pdev = to_platform_device(dev); struct chv_pinctrl *pctrl = platform_get_drvdata(pdev); + unsigned long flags; int i; + raw_spin_lock_irqsave(&chv_lock, flags); + /* * Mask all interrupts before restoring per-pin configuration * registers because we don't know in which state BIOS left them @@ -1731,12 +1739,15 @@ static int chv_pinctrl_resume(struct device *dev) chv_writel(0xffff, pctrl->regs + CHV_INTSTAT); chv_writel(pctrl->saved_intmask, pctrl->regs + CHV_INTMASK); + raw_spin_unlock_irqrestore(&chv_lock, flags); + return 0; } #endif static const struct dev_pm_ops chv_pinctrl_pm_ops = { - SET_LATE_SYSTEM_SLEEP_PM_OPS(chv_pinctrl_suspend, chv_pinctrl_resume) + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(chv_pinctrl_suspend_noirq, + chv_pinctrl_resume_noirq) }; static const struct acpi_device_id chv_pinctrl_acpi_match[] = { diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c index 99da4cf91031..b7bb37167969 100644 --- a/drivers/pinctrl/pinctrl-st.c +++ b/drivers/pinctrl/pinctrl-st.c @@ -1512,7 +1512,7 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info, if (info->irqmux_base || gpio_irq > 0) { err = gpiochip_irqchip_add(&bank->gpio_chip, &st_gpio_irqchip, 0, handle_simple_irq, - IRQ_TYPE_LEVEL_LOW); + IRQ_TYPE_NONE); if (err) { gpiochip_remove(&bank->gpio_chip); dev_info(dev, "could not add irqchip\n"); diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c index 200667f08c37..efc43711ff5c 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.c +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c @@ -1092,9 +1092,11 @@ int stm32_pctl_probe(struct platform_device *pdev) return -EINVAL; } - ret = stm32_pctrl_dt_setup_irq(pdev, pctl); - if (ret) - return ret; + if (of_find_property(np, "interrupt-parent", NULL)) { + ret = stm32_pctrl_dt_setup_irq(pdev, pctl); + if (ret) + return ret; + } for_each_child_of_node(np, child) if (of_property_read_bool(child, "gpio-controller")) diff --git a/drivers/platform/x86/ideapad-laptop.c b/drivers/platform/x86/ideapad-laptop.c index a2323941e677..a7614fc542b5 100644 --- a/drivers/platform/x86/ideapad-laptop.c +++ b/drivers/platform/x86/ideapad-laptop.c @@ -934,6 +934,13 @@ static const struct dmi_system_id no_hw_rfkill_list[] = { }, }, { + .ident = "Lenovo Yoga 900", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), + DMI_MATCH(DMI_BOARD_NAME, "VIUU4"), + }, + }, + { .ident = "Lenovo YOGA 910-13IKB", .matches = { DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), diff --git a/drivers/platform/x86/intel-hid.c b/drivers/platform/x86/intel-hid.c index ed5874217ee7..12dbb5063376 100644 --- a/drivers/platform/x86/intel-hid.c +++ b/drivers/platform/x86/intel-hid.c @@ -264,7 +264,7 @@ check_acpi_dev(acpi_handle handle, u32 lvl, void *context, void **rv) return AE_OK; if (acpi_match_device_ids(dev, ids) == 0) - if (acpi_create_platform_device(dev)) + if (acpi_create_platform_device(dev, NULL)) dev_info(&dev->dev, "intel-hid: created platform device\n"); diff --git a/drivers/platform/x86/intel-vbtn.c b/drivers/platform/x86/intel-vbtn.c index 146d02f8c9bc..78080763df51 100644 --- a/drivers/platform/x86/intel-vbtn.c +++ b/drivers/platform/x86/intel-vbtn.c @@ -164,7 +164,7 @@ check_acpi_dev(acpi_handle handle, u32 lvl, void *context, void **rv) return AE_OK; if (acpi_match_device_ids(dev, ids) == 0) - if (acpi_create_platform_device(dev)) + if (acpi_create_platform_device(dev, NULL)) dev_info(&dev->dev, "intel-vbtn: created platform device\n"); diff --git a/drivers/platform/x86/toshiba-wmi.c b/drivers/platform/x86/toshiba-wmi.c index feac4576b837..2df07ee8f3c3 100644 --- a/drivers/platform/x86/toshiba-wmi.c +++ b/drivers/platform/x86/toshiba-wmi.c @@ -24,14 +24,15 @@ #include <linux/acpi.h> #include <linux/input.h> #include <linux/input/sparse-keymap.h> +#include <linux/dmi.h> MODULE_AUTHOR("Azael Avalos"); MODULE_DESCRIPTION("Toshiba WMI Hotkey Driver"); MODULE_LICENSE("GPL"); -#define TOSHIBA_WMI_EVENT_GUID "59142400-C6A3-40FA-BADB-8A2652834100" +#define WMI_EVENT_GUID "59142400-C6A3-40FA-BADB-8A2652834100" -MODULE_ALIAS("wmi:"TOSHIBA_WMI_EVENT_GUID); +MODULE_ALIAS("wmi:"WMI_EVENT_GUID); static struct input_dev *toshiba_wmi_input_dev; @@ -63,6 +64,16 @@ static void toshiba_wmi_notify(u32 value, void *context) kfree(response.pointer); } +static struct dmi_system_id toshiba_wmi_dmi_table[] __initdata = { + { + .ident = "Toshiba laptop", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), + }, + }, + {} +}; + static int __init toshiba_wmi_input_setup(void) { acpi_status status; @@ -81,7 +92,7 @@ static int __init toshiba_wmi_input_setup(void) if (err) goto err_free_dev; - status = wmi_install_notify_handler(TOSHIBA_WMI_EVENT_GUID, + status = wmi_install_notify_handler(WMI_EVENT_GUID, toshiba_wmi_notify, NULL); if (ACPI_FAILURE(status)) { err = -EIO; @@ -95,7 +106,7 @@ static int __init toshiba_wmi_input_setup(void) return 0; err_remove_notifier: - wmi_remove_notify_handler(TOSHIBA_WMI_EVENT_GUID); + wmi_remove_notify_handler(WMI_EVENT_GUID); err_free_keymap: sparse_keymap_free(toshiba_wmi_input_dev); err_free_dev: @@ -105,7 +116,7 @@ static int __init toshiba_wmi_input_setup(void) static void toshiba_wmi_input_destroy(void) { - wmi_remove_notify_handler(TOSHIBA_WMI_EVENT_GUID); + wmi_remove_notify_handler(WMI_EVENT_GUID); sparse_keymap_free(toshiba_wmi_input_dev); input_unregister_device(toshiba_wmi_input_dev); } @@ -114,7 +125,8 @@ static int __init toshiba_wmi_init(void) { int ret; - if (!wmi_has_guid(TOSHIBA_WMI_EVENT_GUID)) + if (!wmi_has_guid(WMI_EVENT_GUID) || + !dmi_check_system(toshiba_wmi_dmi_table)) return -ENODEV; ret = toshiba_wmi_input_setup(); @@ -130,7 +142,7 @@ static int __init toshiba_wmi_init(void) static void __exit toshiba_wmi_exit(void) { - if (wmi_has_guid(TOSHIBA_WMI_EVENT_GUID)) + if (wmi_has_guid(WMI_EVENT_GUID)) toshiba_wmi_input_destroy(); } diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index 381871b2bb46..9d5bd7d5c610 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -474,6 +474,7 @@ static int meson_pwm_probe(struct platform_device *pdev) if (IS_ERR(meson->base)) return PTR_ERR(meson->base); + spin_lock_init(&meson->lock); meson->chip.dev = &pdev->dev; meson->chip.ops = &meson_pwm_ops; meson->chip.base = -1; diff --git a/drivers/pwm/sysfs.c b/drivers/pwm/sysfs.c index 0296d8178ae2..a813239300c3 100644 --- a/drivers/pwm/sysfs.c +++ b/drivers/pwm/sysfs.c @@ -425,6 +425,8 @@ void pwmchip_sysfs_unexport_children(struct pwm_chip *chip) if (test_bit(PWMF_EXPORTED, &pwm->flags)) pwm_unexport_child(parent, pwm); } + + put_device(parent); } static int __init pwm_sysfs_init(void) diff --git a/drivers/rtc/rtc-asm9260.c b/drivers/rtc/rtc-asm9260.c index 18a93d3e3f93..d36534965635 100644 --- a/drivers/rtc/rtc-asm9260.c +++ b/drivers/rtc/rtc-asm9260.c @@ -327,6 +327,7 @@ static const struct of_device_id asm9260_dt_ids[] = { { .compatible = "alphascale,asm9260-rtc", }, {} }; +MODULE_DEVICE_TABLE(of, asm9260_dt_ids); static struct platform_driver asm9260_rtc_driver = { .probe = asm9260_rtc_probe, diff --git a/drivers/rtc/rtc-cmos.c b/drivers/rtc/rtc-cmos.c index dd3d59806ffa..7030d7cd3861 100644 --- a/drivers/rtc/rtc-cmos.c +++ b/drivers/rtc/rtc-cmos.c @@ -776,7 +776,7 @@ static void cmos_do_shutdown(int rtc_irq) spin_unlock_irq(&rtc_lock); } -static void __exit cmos_do_remove(struct device *dev) +static void cmos_do_remove(struct device *dev) { struct cmos_rtc *cmos = dev_get_drvdata(dev); struct resource *ports; @@ -996,8 +996,9 @@ static u32 rtc_handler(void *context) struct cmos_rtc *cmos = dev_get_drvdata(dev); unsigned char rtc_control = 0; unsigned char rtc_intr; + unsigned long flags; - spin_lock_irq(&rtc_lock); + spin_lock_irqsave(&rtc_lock, flags); if (cmos_rtc.suspend_ctrl) rtc_control = CMOS_READ(RTC_CONTROL); if (rtc_control & RTC_AIE) { @@ -1006,7 +1007,7 @@ static u32 rtc_handler(void *context) rtc_intr = CMOS_READ(RTC_INTR_FLAGS); rtc_update_irq(cmos->rtc, 1, rtc_intr); } - spin_unlock_irq(&rtc_lock); + spin_unlock_irqrestore(&rtc_lock, flags); pm_wakeup_event(dev, 0); acpi_clear_event(ACPI_EVENT_RTC); @@ -1129,7 +1130,7 @@ static int cmos_pnp_probe(struct pnp_dev *pnp, const struct pnp_device_id *id) pnp_irq(pnp, 0)); } -static void __exit cmos_pnp_remove(struct pnp_dev *pnp) +static void cmos_pnp_remove(struct pnp_dev *pnp) { cmos_do_remove(&pnp->dev); } @@ -1161,7 +1162,7 @@ static struct pnp_driver cmos_pnp_driver = { .name = (char *) driver_name, .id_table = rtc_ids, .probe = cmos_pnp_probe, - .remove = __exit_p(cmos_pnp_remove), + .remove = cmos_pnp_remove, .shutdown = cmos_pnp_shutdown, /* flag ensures resume() gets called, and stops syslog spam */ @@ -1238,7 +1239,7 @@ static int __init cmos_platform_probe(struct platform_device *pdev) return cmos_do_probe(&pdev->dev, resource, irq); } -static int __exit cmos_platform_remove(struct platform_device *pdev) +static int cmos_platform_remove(struct platform_device *pdev) { cmos_do_remove(&pdev->dev); return 0; @@ -1263,7 +1264,7 @@ static void cmos_platform_shutdown(struct platform_device *pdev) MODULE_ALIAS("platform:rtc_cmos"); static struct platform_driver cmos_platform_driver = { - .remove = __exit_p(cmos_platform_remove), + .remove = cmos_platform_remove, .shutdown = cmos_platform_shutdown, .driver = { .name = driver_name, diff --git a/drivers/rtc/rtc-omap.c b/drivers/rtc/rtc-omap.c index b04ea9b5ae67..51e52446eacb 100644 --- a/drivers/rtc/rtc-omap.c +++ b/drivers/rtc/rtc-omap.c @@ -113,6 +113,7 @@ /* OMAP_RTC_OSC_REG bit fields: */ #define OMAP_RTC_OSC_32KCLK_EN BIT(6) #define OMAP_RTC_OSC_SEL_32KCLK_SRC BIT(3) +#define OMAP_RTC_OSC_OSC32K_GZ_DISABLE BIT(4) /* OMAP_RTC_IRQWAKEEN bit fields: */ #define OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN BIT(1) @@ -146,6 +147,7 @@ struct omap_rtc { u8 interrupts_reg; bool is_pmic_controller; bool has_ext_clk; + bool is_suspending; const struct omap_rtc_device_type *type; struct pinctrl_dev *pctldev; }; @@ -786,8 +788,9 @@ static int omap_rtc_probe(struct platform_device *pdev) */ if (rtc->has_ext_clk) { reg = rtc_read(rtc, OMAP_RTC_OSC_REG); - rtc_write(rtc, OMAP_RTC_OSC_REG, - reg | OMAP_RTC_OSC_SEL_32KCLK_SRC); + reg &= ~OMAP_RTC_OSC_OSC32K_GZ_DISABLE; + reg |= OMAP_RTC_OSC_32KCLK_EN | OMAP_RTC_OSC_SEL_32KCLK_SRC; + rtc_writel(rtc, OMAP_RTC_OSC_REG, reg); } rtc->type->lock(rtc); @@ -898,8 +901,7 @@ static int omap_rtc_suspend(struct device *dev) rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0); rtc->type->lock(rtc); - /* Disable the clock/module */ - pm_runtime_put_sync(dev); + rtc->is_suspending = true; return 0; } @@ -908,9 +910,6 @@ static int omap_rtc_resume(struct device *dev) { struct omap_rtc *rtc = dev_get_drvdata(dev); - /* Enable the clock/module so that we can access the registers */ - pm_runtime_get_sync(dev); - rtc->type->unlock(rtc); if (device_may_wakeup(dev)) disable_irq_wake(rtc->irq_alarm); @@ -918,11 +917,34 @@ static int omap_rtc_resume(struct device *dev) rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, rtc->interrupts_reg); rtc->type->lock(rtc); + rtc->is_suspending = false; + return 0; } #endif -static SIMPLE_DEV_PM_OPS(omap_rtc_pm_ops, omap_rtc_suspend, omap_rtc_resume); +#ifdef CONFIG_PM +static int omap_rtc_runtime_suspend(struct device *dev) +{ + struct omap_rtc *rtc = dev_get_drvdata(dev); + + if (rtc->is_suspending && !rtc->has_ext_clk) + return -EBUSY; + + return 0; +} + +static int omap_rtc_runtime_resume(struct device *dev) +{ + return 0; +} +#endif + +static const struct dev_pm_ops omap_rtc_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(omap_rtc_suspend, omap_rtc_resume) + SET_RUNTIME_PM_OPS(omap_rtc_runtime_suspend, + omap_rtc_runtime_resume, NULL) +}; static void omap_rtc_shutdown(struct platform_device *pdev) { diff --git a/drivers/scsi/be2iscsi/be_mgmt.c b/drivers/scsi/be2iscsi/be_mgmt.c index aebc4ddb3060..ac05317bba7f 100644 --- a/drivers/scsi/be2iscsi/be_mgmt.c +++ b/drivers/scsi/be2iscsi/be_mgmt.c @@ -1083,7 +1083,7 @@ unsigned int beiscsi_boot_get_sinfo(struct beiscsi_hba *phba) nonemb_cmd = &phba->boot_struct.nonemb_cmd; nonemb_cmd->size = sizeof(*resp); nonemb_cmd->va = pci_alloc_consistent(phba->ctrl.pdev, - sizeof(nonemb_cmd->size), + nonemb_cmd->size, &nonemb_cmd->dma); if (!nonemb_cmd->va) { mutex_unlock(&ctrl->mbox_lock); diff --git a/drivers/scsi/cxgbi/libcxgbi.c b/drivers/scsi/cxgbi/libcxgbi.c index d1421139e6ea..2ffe029ff2b6 100644 --- a/drivers/scsi/cxgbi/libcxgbi.c +++ b/drivers/scsi/cxgbi/libcxgbi.c @@ -2081,9 +2081,10 @@ void cxgbi_cleanup_task(struct iscsi_task *task) /* never reached the xmit task callout */ if (tdata->skb) __kfree_skb(tdata->skb); - memset(tdata, 0, sizeof(*tdata)); task_release_itt(task, task->hdr_itt); + memset(tdata, 0, sizeof(*tdata)); + iscsi_tcp_cleanup_task(task); } EXPORT_SYMBOL_GPL(cxgbi_cleanup_task); diff --git a/drivers/scsi/device_handler/scsi_dh_alua.c b/drivers/scsi/device_handler/scsi_dh_alua.c index 241829e59668..7bb20684e9fa 100644 --- a/drivers/scsi/device_handler/scsi_dh_alua.c +++ b/drivers/scsi/device_handler/scsi_dh_alua.c @@ -793,6 +793,7 @@ static void alua_rtpg_work(struct work_struct *work) WARN_ON(pg->flags & ALUA_PG_RUN_RTPG); WARN_ON(pg->flags & ALUA_PG_RUN_STPG); spin_unlock_irqrestore(&pg->lock, flags); + kref_put(&pg->kref, release_port_group); return; } if (pg->flags & ALUA_SYNC_STPG) @@ -890,6 +891,7 @@ static void alua_rtpg_queue(struct alua_port_group *pg, /* Do not queue if the worker is already running */ if (!(pg->flags & ALUA_PG_RUNNING)) { kref_get(&pg->kref); + sdev = NULL; start_queue = 1; } } @@ -901,7 +903,8 @@ static void alua_rtpg_queue(struct alua_port_group *pg, if (start_queue && !queue_delayed_work(alua_wq, &pg->rtpg_work, msecs_to_jiffies(ALUA_RTPG_DELAY_MSECS))) { - scsi_device_put(sdev); + if (sdev) + scsi_device_put(sdev); kref_put(&pg->kref, release_port_group); } } diff --git a/drivers/scsi/hpsa.c b/drivers/scsi/hpsa.c index d007ec18179a..a1d6ab76a514 100644 --- a/drivers/scsi/hpsa.c +++ b/drivers/scsi/hpsa.c @@ -2009,7 +2009,7 @@ static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h, static int hpsa_slave_alloc(struct scsi_device *sdev) { - struct hpsa_scsi_dev_t *sd; + struct hpsa_scsi_dev_t *sd = NULL; unsigned long flags; struct ctlr_info *h; @@ -2026,7 +2026,8 @@ static int hpsa_slave_alloc(struct scsi_device *sdev) sd->target = sdev_id(sdev); sd->lun = sdev->lun; } - } else + } + if (!sd) sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev), sdev_id(sdev), sdev->lun); @@ -3840,6 +3841,7 @@ static int hpsa_update_device_info(struct ctlr_info *h, sizeof(this_device->vendor)); memcpy(this_device->model, &inq_buff[16], sizeof(this_device->model)); + this_device->rev = inq_buff[2]; memset(this_device->device_id, 0, sizeof(this_device->device_id)); if (hpsa_get_device_id(h, scsi3addr, this_device->device_id, 8, @@ -3929,10 +3931,14 @@ static void figure_bus_target_lun(struct ctlr_info *h, if (!is_logical_dev_addr_mode(lunaddrbytes)) { /* physical device, target and lun filled in later */ - if (is_hba_lunid(lunaddrbytes)) + if (is_hba_lunid(lunaddrbytes)) { + int bus = HPSA_HBA_BUS; + + if (!device->rev) + bus = HPSA_LEGACY_HBA_BUS; hpsa_set_bus_target_lun(device, - HPSA_HBA_BUS, 0, lunid & 0x3fff); - else + bus, 0, lunid & 0x3fff); + } else /* defer target, lun assignment for physical devices */ hpsa_set_bus_target_lun(device, HPSA_PHYSICAL_DEVICE_BUS, -1, -1); diff --git a/drivers/scsi/hpsa.h b/drivers/scsi/hpsa.h index 82cdfad874f3..9ea162de80dc 100644 --- a/drivers/scsi/hpsa.h +++ b/drivers/scsi/hpsa.h @@ -69,6 +69,7 @@ struct hpsa_scsi_dev_t { u64 sas_address; unsigned char vendor[8]; /* bytes 8-15 of inquiry data */ unsigned char model[16]; /* bytes 16-31 of inquiry data */ + unsigned char rev; /* byte 2 of inquiry data */ unsigned char raid_level; /* from inquiry page 0xC1 */ unsigned char volume_offline; /* discovered via TUR or VPD */ u16 queue_depth; /* max queue_depth for this device */ @@ -402,6 +403,7 @@ struct offline_device_entry { #define HPSA_RAID_VOLUME_BUS 1 #define HPSA_EXTERNAL_RAID_VOLUME_BUS 2 #define HPSA_HBA_BUS 0 +#define HPSA_LEGACY_HBA_BUS 3 /* Send the command to the hardware diff --git a/drivers/scsi/libfc/fc_lport.c b/drivers/scsi/libfc/fc_lport.c index 04ce7cfb6d1b..50c71678a156 100644 --- a/drivers/scsi/libfc/fc_lport.c +++ b/drivers/scsi/libfc/fc_lport.c @@ -308,7 +308,7 @@ struct fc_host_statistics *fc_get_host_stats(struct Scsi_Host *shost) fc_stats = &lport->host_stats; memset(fc_stats, 0, sizeof(struct fc_host_statistics)); - fc_stats->seconds_since_last_reset = (lport->boot_time - jiffies) / HZ; + fc_stats->seconds_since_last_reset = (jiffies - lport->boot_time) / HZ; for_each_possible_cpu(cpu) { struct fc_stats *stats; diff --git a/drivers/scsi/megaraid/megaraid_sas.h b/drivers/scsi/megaraid/megaraid_sas.h index ca86c885dfaa..3aaea713bf37 100644 --- a/drivers/scsi/megaraid/megaraid_sas.h +++ b/drivers/scsi/megaraid/megaraid_sas.h @@ -2233,7 +2233,7 @@ struct megasas_instance_template { }; #define MEGASAS_IS_LOGICAL(scp) \ - (scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1 + ((scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1) #define MEGASAS_DEV_INDEX(scp) \ (((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \ diff --git a/drivers/scsi/mpt3sas/mpt3sas_scsih.c b/drivers/scsi/mpt3sas/mpt3sas_scsih.c index 209a969a979d..1c4744e78173 100644 --- a/drivers/scsi/mpt3sas/mpt3sas_scsih.c +++ b/drivers/scsi/mpt3sas/mpt3sas_scsih.c @@ -1273,9 +1273,9 @@ scsih_target_alloc(struct scsi_target *starget) sas_target_priv_data->handle = raid_device->handle; sas_target_priv_data->sas_address = raid_device->wwid; sas_target_priv_data->flags |= MPT_TARGET_FLAGS_VOLUME; - sas_target_priv_data->raid_device = raid_device; if (ioc->is_warpdrive) - raid_device->starget = starget; + sas_target_priv_data->raid_device = raid_device; + raid_device->starget = starget; } spin_unlock_irqrestore(&ioc->raid_device_lock, flags); return 0; @@ -3885,6 +3885,11 @@ _scsih_temp_threshold_events(struct MPT3SAS_ADAPTER *ioc, } } +static inline bool ata_12_16_cmd(struct scsi_cmnd *scmd) +{ + return (scmd->cmnd[0] == ATA_12 || scmd->cmnd[0] == ATA_16); +} + /** * _scsih_flush_running_cmds - completing outstanding commands. * @ioc: per adapter object @@ -3906,6 +3911,9 @@ _scsih_flush_running_cmds(struct MPT3SAS_ADAPTER *ioc) if (!scmd) continue; count++; + if (ata_12_16_cmd(scmd)) + scsi_internal_device_unblock(scmd->device, + SDEV_RUNNING); mpt3sas_base_free_smid(ioc, smid); scsi_dma_unmap(scmd); if (ioc->pci_error_recovery) @@ -4010,8 +4018,6 @@ _scsih_eedp_error_handling(struct scsi_cmnd *scmd, u16 ioc_status) SAM_STAT_CHECK_CONDITION; } - - /** * scsih_qcmd - main scsi request entry point * @scmd: pointer to scsi command object @@ -4038,6 +4044,13 @@ scsih_qcmd(struct Scsi_Host *shost, struct scsi_cmnd *scmd) if (ioc->logging_level & MPT_DEBUG_SCSI) scsi_print_command(scmd); + /* + * Lock the device for any subsequent command until command is + * done. + */ + if (ata_12_16_cmd(scmd)) + scsi_internal_device_block(scmd->device); + sas_device_priv_data = scmd->device->hostdata; if (!sas_device_priv_data || !sas_device_priv_data->sas_target) { scmd->result = DID_NO_CONNECT << 16; @@ -4613,6 +4626,9 @@ _scsih_io_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index, u32 reply) if (scmd == NULL) return 1; + if (ata_12_16_cmd(scmd)) + scsi_internal_device_unblock(scmd->device, SDEV_RUNNING); + mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); if (mpi_reply == NULL) { diff --git a/drivers/scsi/mvsas/mv_sas.c b/drivers/scsi/mvsas/mv_sas.c index 86eb19902bac..c7cc8035eacb 100644 --- a/drivers/scsi/mvsas/mv_sas.c +++ b/drivers/scsi/mvsas/mv_sas.c @@ -791,8 +791,10 @@ static int mvs_task_prep(struct sas_task *task, struct mvs_info *mvi, int is_tmf slot->slot_tag = tag; slot->buf = pci_pool_alloc(mvi->dma_pool, GFP_ATOMIC, &slot->buf_dma); - if (!slot->buf) + if (!slot->buf) { + rc = -ENOMEM; goto err_out_tag; + } memset(slot->buf, 0, MVS_SLOT_BUF_SZ); tei.task = task; diff --git a/drivers/scsi/qla2xxx/qla_os.c b/drivers/scsi/qla2xxx/qla_os.c index ace65db1d2a2..56d6142852a5 100644 --- a/drivers/scsi/qla2xxx/qla_os.c +++ b/drivers/scsi/qla2xxx/qla_os.c @@ -707,6 +707,11 @@ qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) srb_t *sp; int rval; + if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) { + cmd->result = DID_NO_CONNECT << 16; + goto qc24_fail_command; + } + if (ha->flags.eeh_busy) { if (ha->flags.pci_channel_io_perm_failure) { ql_dbg(ql_dbg_aer, vha, 0x9010, @@ -1451,6 +1456,20 @@ qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { sp = req->outstanding_cmds[cnt]; if (sp) { + /* Don't abort commands in adapter during EEH + * recovery as it's not accessible/responding. + */ + if (!ha->flags.eeh_busy) { + /* Get a reference to the sp and drop the lock. + * The reference ensures this sp->done() call + * - and not the call in qla2xxx_eh_abort() - + * ends the SCSI command (with result 'res'). + */ + sp_get(sp); + spin_unlock_irqrestore(&ha->hardware_lock, flags); + qla2xxx_eh_abort(GET_CMD_SP(sp)); + spin_lock_irqsave(&ha->hardware_lock, flags); + } req->outstanding_cmds[cnt] = NULL; sp->done(vha, sp, res); } @@ -2341,6 +2360,8 @@ qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) { scsi_qla_host_t *vha = shost_priv(shost); + if (test_bit(UNLOADING, &vha->dpc_flags)) + return 1; if (!vha->host) return 1; if (time > vha->hw->loop_reset_delay * HZ) diff --git a/drivers/scsi/qlogicpti.h b/drivers/scsi/qlogicpti.h index 4377e87ee79c..892a0b058b99 100644 --- a/drivers/scsi/qlogicpti.h +++ b/drivers/scsi/qlogicpti.h @@ -356,8 +356,8 @@ struct qlogicpti { /* The rest of the elements are unimportant for performance. */ struct qlogicpti *next; - __u32 res_dvma; /* Ptr to RESPONSE bufs (DVMA)*/ - __u32 req_dvma; /* Ptr to REQUEST bufs (DVMA) */ + dma_addr_t res_dvma; /* Ptr to RESPONSE bufs (DVMA)*/ + dma_addr_t req_dvma; /* Ptr to REQUEST bufs (DVMA) */ u_char fware_majrev, fware_minrev, fware_micrev; struct Scsi_Host *qhost; int qpti_id; diff --git a/drivers/scsi/vmw_pvscsi.c b/drivers/scsi/vmw_pvscsi.c index 4a0d3cdc607c..15ca09cd16f3 100644 --- a/drivers/scsi/vmw_pvscsi.c +++ b/drivers/scsi/vmw_pvscsi.c @@ -793,6 +793,7 @@ static int pvscsi_abort(struct scsi_cmnd *cmd) unsigned long flags; int result = SUCCESS; DECLARE_COMPLETION_ONSTACK(abort_cmp); + int done; scmd_printk(KERN_DEBUG, cmd, "task abort on host %u, %p\n", adapter->host->host_no, cmd); @@ -824,10 +825,10 @@ static int pvscsi_abort(struct scsi_cmnd *cmd) pvscsi_abort_cmd(adapter, ctx); spin_unlock_irqrestore(&adapter->hw_lock, flags); /* Wait for 2 secs for the completion. */ - wait_for_completion_timeout(&abort_cmp, msecs_to_jiffies(2000)); + done = wait_for_completion_timeout(&abort_cmp, msecs_to_jiffies(2000)); spin_lock_irqsave(&adapter->hw_lock, flags); - if (!completion_done(&abort_cmp)) { + if (!done) { /* * Failed to abort the command, unmark the fact that it * was requested to be aborted. diff --git a/drivers/scsi/vmw_pvscsi.h b/drivers/scsi/vmw_pvscsi.h index c097d2ccbde3..d41292ef85f2 100644 --- a/drivers/scsi/vmw_pvscsi.h +++ b/drivers/scsi/vmw_pvscsi.h @@ -26,7 +26,7 @@ #include <linux/types.h> -#define PVSCSI_DRIVER_VERSION_STRING "1.0.6.0-k" +#define PVSCSI_DRIVER_VERSION_STRING "1.0.7.0-k" #define PVSCSI_MAX_NUM_SG_ENTRIES_PER_SEGMENT 128 diff --git a/drivers/staging/comedi/drivers/ni_tio.c b/drivers/staging/comedi/drivers/ni_tio.c index 7043eb0543f6..5ab49a798164 100644 --- a/drivers/staging/comedi/drivers/ni_tio.c +++ b/drivers/staging/comedi/drivers/ni_tio.c @@ -207,7 +207,8 @@ static int ni_tio_clock_period_ps(const struct ni_gpct *counter, * clock period is specified by user with prescaling * already taken into account. */ - return counter->clock_period_ps; + *period_ps = counter->clock_period_ps; + return 0; } switch (generic_clock_source & NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK) { diff --git a/drivers/staging/greybus/arche-platform.c b/drivers/staging/greybus/arche-platform.c index 34307ac3f255..d33d6fe078ad 100644 --- a/drivers/staging/greybus/arche-platform.c +++ b/drivers/staging/greybus/arche-platform.c @@ -186,6 +186,7 @@ int arche_platform_change_state(enum arche_platform_state state, exit: spin_unlock_irqrestore(&arche_pdata->wake_lock, flags); mutex_unlock(&arche_pdata->platform_state_mutex); + put_device(&pdev->dev); of_node_put(np); return ret; } diff --git a/drivers/staging/iio/impedance-analyzer/ad5933.c b/drivers/staging/iio/impedance-analyzer/ad5933.c index 5eecf1cb1028..3892a7470410 100644 --- a/drivers/staging/iio/impedance-analyzer/ad5933.c +++ b/drivers/staging/iio/impedance-analyzer/ad5933.c @@ -655,6 +655,7 @@ static void ad5933_work(struct work_struct *work) __be16 buf[2]; int val[2]; unsigned char status; + int ret; mutex_lock(&indio_dev->mlock); if (st->state == AD5933_CTRL_INIT_START_FREQ) { @@ -662,19 +663,22 @@ static void ad5933_work(struct work_struct *work) ad5933_cmd(st, AD5933_CTRL_START_SWEEP); st->state = AD5933_CTRL_START_SWEEP; schedule_delayed_work(&st->work, st->poll_time_jiffies); - mutex_unlock(&indio_dev->mlock); - return; + goto out; } - ad5933_i2c_read(st->client, AD5933_REG_STATUS, 1, &status); + ret = ad5933_i2c_read(st->client, AD5933_REG_STATUS, 1, &status); + if (ret) + goto out; if (status & AD5933_STAT_DATA_VALID) { int scan_count = bitmap_weight(indio_dev->active_scan_mask, indio_dev->masklength); - ad5933_i2c_read(st->client, + ret = ad5933_i2c_read(st->client, test_bit(1, indio_dev->active_scan_mask) ? AD5933_REG_REAL_DATA : AD5933_REG_IMAG_DATA, scan_count * 2, (u8 *)buf); + if (ret) + goto out; if (scan_count == 2) { val[0] = be16_to_cpu(buf[0]); @@ -686,8 +690,7 @@ static void ad5933_work(struct work_struct *work) } else { /* no data available - try again later */ schedule_delayed_work(&st->work, st->poll_time_jiffies); - mutex_unlock(&indio_dev->mlock); - return; + goto out; } if (status & AD5933_STAT_SWEEP_DONE) { @@ -700,7 +703,7 @@ static void ad5933_work(struct work_struct *work) ad5933_cmd(st, AD5933_CTRL_INC_FREQ); schedule_delayed_work(&st->work, st->poll_time_jiffies); } - +out: mutex_unlock(&indio_dev->mlock); } diff --git a/drivers/staging/nvec/nvec_ps2.c b/drivers/staging/nvec/nvec_ps2.c index a324322ee0ad..499952c8ef39 100644 --- a/drivers/staging/nvec/nvec_ps2.c +++ b/drivers/staging/nvec/nvec_ps2.c @@ -106,13 +106,12 @@ static int nvec_mouse_probe(struct platform_device *pdev) { struct nvec_chip *nvec = dev_get_drvdata(pdev->dev.parent); struct serio *ser_dev; - char mouse_reset[] = { NVEC_PS2, SEND_COMMAND, PSMOUSE_RST, 3 }; - ser_dev = devm_kzalloc(&pdev->dev, sizeof(struct serio), GFP_KERNEL); + ser_dev = kzalloc(sizeof(struct serio), GFP_KERNEL); if (!ser_dev) return -ENOMEM; - ser_dev->id.type = SERIO_PS_PSTHRU; + ser_dev->id.type = SERIO_8042; ser_dev->write = ps2_sendcommand; ser_dev->start = ps2_startstreaming; ser_dev->stop = ps2_stopstreaming; @@ -127,9 +126,6 @@ static int nvec_mouse_probe(struct platform_device *pdev) serio_register_port(ser_dev); - /* mouse reset */ - nvec_write_async(nvec, mouse_reset, sizeof(mouse_reset)); - return 0; } diff --git a/drivers/staging/sm750fb/ddk750_reg.h b/drivers/staging/sm750fb/ddk750_reg.h index 955247979aaa..4ed6d8d7712a 100644 --- a/drivers/staging/sm750fb/ddk750_reg.h +++ b/drivers/staging/sm750fb/ddk750_reg.h @@ -601,13 +601,13 @@ #define PANEL_PLANE_TL 0x08001C #define PANEL_PLANE_TL_TOP_SHIFT 16 -#define PANEL_PLANE_TL_TOP_MASK (0xeff << 16) -#define PANEL_PLANE_TL_LEFT_MASK 0xeff +#define PANEL_PLANE_TL_TOP_MASK (0x7ff << 16) +#define PANEL_PLANE_TL_LEFT_MASK 0x7ff #define PANEL_PLANE_BR 0x080020 #define PANEL_PLANE_BR_BOTTOM_SHIFT 16 -#define PANEL_PLANE_BR_BOTTOM_MASK (0xeff << 16) -#define PANEL_PLANE_BR_RIGHT_MASK 0xeff +#define PANEL_PLANE_BR_BOTTOM_MASK (0x7ff << 16) +#define PANEL_PLANE_BR_RIGHT_MASK 0x7ff #define PANEL_HORIZONTAL_TOTAL 0x080024 #define PANEL_HORIZONTAL_TOTAL_TOTAL_SHIFT 16 diff --git a/drivers/thermal/intel_powerclamp.c b/drivers/thermal/intel_powerclamp.c index 7a223074df3d..afada655f861 100644 --- a/drivers/thermal/intel_powerclamp.c +++ b/drivers/thermal/intel_powerclamp.c @@ -669,9 +669,16 @@ static struct thermal_cooling_device_ops powerclamp_cooling_ops = { .set_cur_state = powerclamp_set_cur_state, }; +static const struct x86_cpu_id __initconst intel_powerclamp_ids[] = { + { X86_VENDOR_INTEL, X86_FAMILY_ANY, X86_MODEL_ANY, X86_FEATURE_MWAIT }, + {} +}; +MODULE_DEVICE_TABLE(x86cpu, intel_powerclamp_ids); + static int __init powerclamp_probe(void) { - if (!boot_cpu_has(X86_FEATURE_MWAIT)) { + + if (!x86_match_cpu(intel_powerclamp_ids)) { pr_err("CPU does not support MWAIT"); return -ENODEV; } diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c index 69426e644d17..3dbb4a21ab44 100644 --- a/drivers/usb/chipidea/core.c +++ b/drivers/usb/chipidea/core.c @@ -914,6 +914,7 @@ static int ci_hdrc_probe(struct platform_device *pdev) if (!ci) return -ENOMEM; + spin_lock_init(&ci->lock); ci->dev = dev; ci->platdata = dev_get_platdata(dev); ci->imx28_write_fix = !!(ci->platdata->flags & diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c index 661f43fe0f9e..c9e80ad48fdc 100644 --- a/drivers/usb/chipidea/udc.c +++ b/drivers/usb/chipidea/udc.c @@ -1889,8 +1889,6 @@ static int udc_start(struct ci_hdrc *ci) struct usb_otg_caps *otg_caps = &ci->platdata->ci_otg_caps; int retval = 0; - spin_lock_init(&ci->lock); - ci->gadget.ops = &usb_gadget_ops; ci->gadget.speed = USB_SPEED_UNKNOWN; ci->gadget.max_speed = USB_SPEED_HIGH; diff --git a/drivers/usb/class/cdc-acm.c b/drivers/usb/class/cdc-acm.c index 78f0f85bebdc..fada988512a1 100644 --- a/drivers/usb/class/cdc-acm.c +++ b/drivers/usb/class/cdc-acm.c @@ -932,8 +932,6 @@ static int wait_serial_change(struct acm *acm, unsigned long arg) DECLARE_WAITQUEUE(wait, current); struct async_icount old, new; - if (arg & (TIOCM_DSR | TIOCM_RI | TIOCM_CD)) - return -EINVAL; do { spin_lock_irq(&acm->read_lock); old = acm->oldcount; @@ -1161,6 +1159,8 @@ static int acm_probe(struct usb_interface *intf, if (quirks == IGNORE_DEVICE) return -ENODEV; + memset(&h, 0x00, sizeof(struct usb_cdc_parsed_header)); + num_rx_buf = (quirks == SINGLE_RX_URB) ? 1 : ACM_NR; /* handle quirks deadly to normal probing*/ diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 7287a763cd0c..fea446900cad 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -769,15 +769,14 @@ static int dwc3_core_init(struct dwc3 *dwc) return 0; err4: - phy_power_off(dwc->usb2_generic_phy); + phy_power_off(dwc->usb3_generic_phy); err3: - phy_power_off(dwc->usb3_generic_phy); + phy_power_off(dwc->usb2_generic_phy); err2: usb_phy_set_suspend(dwc->usb2_phy, 1); usb_phy_set_suspend(dwc->usb3_phy, 1); - dwc3_core_exit(dwc); err1: usb_phy_shutdown(dwc->usb2_phy); diff --git a/drivers/usb/dwc3/dwc3-st.c b/drivers/usb/dwc3/dwc3-st.c index 89a2f712fdfe..aaaf256f71dd 100644 --- a/drivers/usb/dwc3/dwc3-st.c +++ b/drivers/usb/dwc3/dwc3-st.c @@ -31,6 +31,7 @@ #include <linux/slab.h> #include <linux/regmap.h> #include <linux/reset.h> +#include <linux/pinctrl/consumer.h> #include <linux/usb/of.h> #include "core.h" diff --git a/drivers/usb/gadget/function/f_fs.c b/drivers/usb/gadget/function/f_fs.c index e40d47d47d82..17989b72cdae 100644 --- a/drivers/usb/gadget/function/f_fs.c +++ b/drivers/usb/gadget/function/f_fs.c @@ -3225,11 +3225,11 @@ static bool ffs_func_req_match(struct usb_function *f, switch (creq->bRequestType & USB_RECIP_MASK) { case USB_RECIP_INTERFACE: - return ffs_func_revmap_intf(func, - le16_to_cpu(creq->wIndex) >= 0); + return (ffs_func_revmap_intf(func, + le16_to_cpu(creq->wIndex)) >= 0); case USB_RECIP_ENDPOINT: - return ffs_func_revmap_ep(func, - le16_to_cpu(creq->wIndex) >= 0); + return (ffs_func_revmap_ep(func, + le16_to_cpu(creq->wIndex)) >= 0); default: return (bool) (func->ffs->user_flags & FUNCTIONFS_ALL_CTRL_RECIP); diff --git a/drivers/usb/gadget/function/u_ether.c b/drivers/usb/gadget/function/u_ether.c index fe1811650dbc..5d1bd13a56c1 100644 --- a/drivers/usb/gadget/function/u_ether.c +++ b/drivers/usb/gadget/function/u_ether.c @@ -588,14 +588,6 @@ static netdev_tx_t eth_start_xmit(struct sk_buff *skb, req->length = length; - /* throttle high/super speed IRQ rate back slightly */ - if (gadget_is_dualspeed(dev->gadget)) - req->no_interrupt = (((dev->gadget->speed == USB_SPEED_HIGH || - dev->gadget->speed == USB_SPEED_SUPER)) && - !list_empty(&dev->tx_reqs)) - ? ((atomic_read(&dev->tx_qlen) % dev->qmult) != 0) - : 0; - retval = usb_ep_queue(in, req, GFP_ATOMIC); switch (retval) { default: diff --git a/drivers/usb/host/pci-quirks.c b/drivers/usb/host/pci-quirks.c index d793f548dfe2..a9a1e4c40480 100644 --- a/drivers/usb/host/pci-quirks.c +++ b/drivers/usb/host/pci-quirks.c @@ -995,6 +995,14 @@ static void quirk_usb_handoff_xhci(struct pci_dev *pdev) } val = readl(base + ext_cap_offset); + /* Auto handoff never worked for these devices. Force it and continue */ + if ((pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) || + (pdev->vendor == PCI_VENDOR_ID_RENESAS + && pdev->device == 0x0014)) { + val = (val | XHCI_HC_OS_OWNED) & ~XHCI_HC_BIOS_OWNED; + writel(val, base + ext_cap_offset); + } + /* If the BIOS owns the HC, signal that the OS wants it, and wait */ if (val & XHCI_HC_BIOS_OWNED) { writel(val | XHCI_HC_OS_OWNED, base + ext_cap_offset); diff --git a/drivers/usb/musb/da8xx.c b/drivers/usb/musb/da8xx.c index 210b7e43a6fd..2440f88e07a3 100644 --- a/drivers/usb/musb/da8xx.c +++ b/drivers/usb/musb/da8xx.c @@ -479,7 +479,8 @@ static int da8xx_probe(struct platform_device *pdev) glue->phy = devm_phy_get(&pdev->dev, "usb-phy"); if (IS_ERR(glue->phy)) { - dev_err(&pdev->dev, "failed to get phy\n"); + if (PTR_ERR(glue->phy) != -EPROBE_DEFER) + dev_err(&pdev->dev, "failed to get phy\n"); return PTR_ERR(glue->phy); } diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c index 27dadc0d9114..c3e172e15ec3 100644 --- a/drivers/usb/musb/musb_core.c +++ b/drivers/usb/musb/musb_core.c @@ -986,7 +986,7 @@ b_host: } #endif - schedule_work(&musb->irq_work); + schedule_delayed_work(&musb->irq_work, 0); return handled; } @@ -1855,14 +1855,23 @@ static void musb_pm_runtime_check_session(struct musb *musb) MUSB_DEVCTL_HR; switch (devctl & ~s) { case MUSB_QUIRK_B_INVALID_VBUS_91: - if (!musb->session && !musb->quirk_invalid_vbus) { - musb->quirk_invalid_vbus = true; + if (musb->quirk_retries--) { musb_dbg(musb, - "First invalid vbus, assume no session"); + "Poll devctl on invalid vbus, assume no session"); + schedule_delayed_work(&musb->irq_work, + msecs_to_jiffies(1000)); + return; } - break; case MUSB_QUIRK_A_DISCONNECT_19: + if (musb->quirk_retries--) { + musb_dbg(musb, + "Poll devctl on possible host mode disconnect"); + schedule_delayed_work(&musb->irq_work, + msecs_to_jiffies(1000)); + + return; + } if (!musb->session) break; musb_dbg(musb, "Allow PM on possible host mode disconnect"); @@ -1886,9 +1895,9 @@ static void musb_pm_runtime_check_session(struct musb *musb) if (error < 0) dev_err(musb->controller, "Could not enable: %i\n", error); + musb->quirk_retries = 3; } else { musb_dbg(musb, "Allow PM with no session: %02x", devctl); - musb->quirk_invalid_vbus = false; pm_runtime_mark_last_busy(musb->controller); pm_runtime_put_autosuspend(musb->controller); } @@ -1899,7 +1908,7 @@ static void musb_pm_runtime_check_session(struct musb *musb) /* Only used to provide driver mode change events */ static void musb_irq_work(struct work_struct *data) { - struct musb *musb = container_of(data, struct musb, irq_work); + struct musb *musb = container_of(data, struct musb, irq_work.work); musb_pm_runtime_check_session(musb); @@ -1969,6 +1978,7 @@ static struct musb *allocate_instance(struct device *dev, INIT_LIST_HEAD(&musb->control); INIT_LIST_HEAD(&musb->in_bulk); INIT_LIST_HEAD(&musb->out_bulk); + INIT_LIST_HEAD(&musb->pending_list); musb->vbuserr_retry = VBUSERR_RETRY_COUNT; musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON; @@ -2018,6 +2028,84 @@ static void musb_free(struct musb *musb) musb_host_free(musb); } +struct musb_pending_work { + int (*callback)(struct musb *musb, void *data); + void *data; + struct list_head node; +}; + +/* + * Called from musb_runtime_resume(), musb_resume(), and + * musb_queue_resume_work(). Callers must take musb->lock. + */ +static int musb_run_resume_work(struct musb *musb) +{ + struct musb_pending_work *w, *_w; + unsigned long flags; + int error = 0; + + spin_lock_irqsave(&musb->list_lock, flags); + list_for_each_entry_safe(w, _w, &musb->pending_list, node) { + if (w->callback) { + error = w->callback(musb, w->data); + if (error < 0) { + dev_err(musb->controller, + "resume callback %p failed: %i\n", + w->callback, error); + } + } + list_del(&w->node); + devm_kfree(musb->controller, w); + } + spin_unlock_irqrestore(&musb->list_lock, flags); + + return error; +} + +/* + * Called to run work if device is active or else queue the work to happen + * on resume. Caller must take musb->lock and must hold an RPM reference. + * + * Note that we cowardly refuse queuing work after musb PM runtime + * resume is done calling musb_run_resume_work() and return -EINPROGRESS + * instead. + */ +int musb_queue_resume_work(struct musb *musb, + int (*callback)(struct musb *musb, void *data), + void *data) +{ + struct musb_pending_work *w; + unsigned long flags; + int error; + + if (WARN_ON(!callback)) + return -EINVAL; + + if (pm_runtime_active(musb->controller)) + return callback(musb, data); + + w = devm_kzalloc(musb->controller, sizeof(*w), GFP_ATOMIC); + if (!w) + return -ENOMEM; + + w->callback = callback; + w->data = data; + spin_lock_irqsave(&musb->list_lock, flags); + if (musb->is_runtime_suspended) { + list_add_tail(&w->node, &musb->pending_list); + error = 0; + } else { + dev_err(musb->controller, "could not add resume work %p\n", + callback); + devm_kfree(musb->controller, w); + error = -EINPROGRESS; + } + spin_unlock_irqrestore(&musb->list_lock, flags); + + return error; +} +EXPORT_SYMBOL_GPL(musb_queue_resume_work); + static void musb_deassert_reset(struct work_struct *work) { struct musb *musb; @@ -2065,6 +2153,7 @@ musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) } spin_lock_init(&musb->lock); + spin_lock_init(&musb->list_lock); musb->board_set_power = plat->set_power; musb->min_power = plat->min_power; musb->ops = plat->platform_ops; @@ -2114,11 +2203,6 @@ musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) musb->io.ep_offset = musb_flat_ep_offset; musb->io.ep_select = musb_flat_ep_select; } - /* And override them with platform specific ops if specified. */ - if (musb->ops->ep_offset) - musb->io.ep_offset = musb->ops->ep_offset; - if (musb->ops->ep_select) - musb->io.ep_select = musb->ops->ep_select; /* At least tusb6010 has its own offsets */ if (musb->ops->ep_offset) @@ -2213,7 +2297,7 @@ musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) musb_generic_disable(musb); /* Init IRQ workqueue before request_irq */ - INIT_WORK(&musb->irq_work, musb_irq_work); + INIT_DELAYED_WORK(&musb->irq_work, musb_irq_work); INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset); INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume); @@ -2296,6 +2380,7 @@ musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) if (status) goto fail5; + musb->is_initialized = 1; pm_runtime_mark_last_busy(musb->controller); pm_runtime_put_autosuspend(musb->controller); @@ -2309,7 +2394,7 @@ fail4: musb_host_cleanup(musb); fail3: - cancel_work_sync(&musb->irq_work); + cancel_delayed_work_sync(&musb->irq_work); cancel_delayed_work_sync(&musb->finish_resume_work); cancel_delayed_work_sync(&musb->deassert_reset_work); if (musb->dma_controller) @@ -2376,7 +2461,7 @@ static int musb_remove(struct platform_device *pdev) */ musb_exit_debugfs(musb); - cancel_work_sync(&musb->irq_work); + cancel_delayed_work_sync(&musb->irq_work); cancel_delayed_work_sync(&musb->finish_resume_work); cancel_delayed_work_sync(&musb->deassert_reset_work); pm_runtime_get_sync(musb->controller); @@ -2562,6 +2647,7 @@ static int musb_suspend(struct device *dev) musb_platform_disable(musb); musb_generic_disable(musb); + WARN_ON(!list_empty(&musb->pending_list)); spin_lock_irqsave(&musb->lock, flags); @@ -2583,9 +2669,11 @@ static int musb_suspend(struct device *dev) static int musb_resume(struct device *dev) { - struct musb *musb = dev_to_musb(dev); - u8 devctl; - u8 mask; + struct musb *musb = dev_to_musb(dev); + unsigned long flags; + int error; + u8 devctl; + u8 mask; /* * For static cmos like DaVinci, register values were preserved @@ -2619,6 +2707,13 @@ static int musb_resume(struct device *dev) musb_start(musb); + spin_lock_irqsave(&musb->lock, flags); + error = musb_run_resume_work(musb); + if (error) + dev_err(musb->controller, "resume work failed with %i\n", + error); + spin_unlock_irqrestore(&musb->lock, flags); + return 0; } @@ -2627,14 +2722,16 @@ static int musb_runtime_suspend(struct device *dev) struct musb *musb = dev_to_musb(dev); musb_save_context(musb); + musb->is_runtime_suspended = 1; return 0; } static int musb_runtime_resume(struct device *dev) { - struct musb *musb = dev_to_musb(dev); - static int first = 1; + struct musb *musb = dev_to_musb(dev); + unsigned long flags; + int error; /* * When pm_runtime_get_sync called for the first time in driver @@ -2645,9 +2742,10 @@ static int musb_runtime_resume(struct device *dev) * Also context restore without save does not make * any sense */ - if (!first) - musb_restore_context(musb); - first = 0; + if (!musb->is_initialized) + return 0; + + musb_restore_context(musb); if (musb->need_finish_resume) { musb->need_finish_resume = 0; @@ -2655,6 +2753,14 @@ static int musb_runtime_resume(struct device *dev) msecs_to_jiffies(USB_RESUME_TIMEOUT)); } + spin_lock_irqsave(&musb->lock, flags); + error = musb_run_resume_work(musb); + if (error) + dev_err(musb->controller, "resume work failed with %i\n", + error); + musb->is_runtime_suspended = 0; + spin_unlock_irqrestore(&musb->lock, flags); + return 0; } diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h index 2cb88a498f8a..91817d77d59c 100644 --- a/drivers/usb/musb/musb_core.h +++ b/drivers/usb/musb/musb_core.h @@ -303,13 +303,14 @@ struct musb_context_registers { struct musb { /* device lock */ spinlock_t lock; + spinlock_t list_lock; /* resume work list lock */ struct musb_io io; const struct musb_platform_ops *ops; struct musb_context_registers context; irqreturn_t (*isr)(int, void *); - struct work_struct irq_work; + struct delayed_work irq_work; struct delayed_work deassert_reset_work; struct delayed_work finish_resume_work; struct delayed_work gadget_work; @@ -337,6 +338,7 @@ struct musb { struct list_head control; /* of musb_qh */ struct list_head in_bulk; /* of musb_qh */ struct list_head out_bulk; /* of musb_qh */ + struct list_head pending_list; /* pending work list */ struct timer_list otg_timer; struct notifier_block nb; @@ -379,12 +381,15 @@ struct musb { int port_mode; /* MUSB_PORT_MODE_* */ bool session; - bool quirk_invalid_vbus; + unsigned long quirk_retries; bool is_host; int a_wait_bcon; /* VBUS timeout in msecs */ unsigned long idle_timeout; /* Next timeout in jiffies */ + unsigned is_initialized:1; + unsigned is_runtime_suspended:1; + /* active means connected and not suspended */ unsigned is_active:1; @@ -540,6 +545,10 @@ extern irqreturn_t musb_interrupt(struct musb *); extern void musb_hnp_stop(struct musb *musb); +int musb_queue_resume_work(struct musb *musb, + int (*callback)(struct musb *musb, void *data), + void *data); + static inline void musb_platform_set_vbus(struct musb *musb, int is_on) { if (musb->ops->set_vbus) diff --git a/drivers/usb/musb/musb_dsps.c b/drivers/usb/musb/musb_dsps.c index 0f17d2140db6..feae1561b9ab 100644 --- a/drivers/usb/musb/musb_dsps.c +++ b/drivers/usb/musb/musb_dsps.c @@ -185,24 +185,19 @@ static void dsps_musb_disable(struct musb *musb) musb_writel(reg_base, wrp->coreintr_clear, wrp->usb_bitmap); musb_writel(reg_base, wrp->epintr_clear, wrp->txep_bitmap | wrp->rxep_bitmap); + del_timer_sync(&glue->timer); musb_writeb(musb->mregs, MUSB_DEVCTL, 0); } -static void otg_timer(unsigned long _musb) +/* Caller must take musb->lock */ +static int dsps_check_status(struct musb *musb, void *unused) { - struct musb *musb = (void *)_musb; void __iomem *mregs = musb->mregs; struct device *dev = musb->controller; struct dsps_glue *glue = dev_get_drvdata(dev->parent); const struct dsps_musb_wrapper *wrp = glue->wrp; u8 devctl; - unsigned long flags; int skip_session = 0; - int err; - - err = pm_runtime_get_sync(dev); - if (err < 0) - dev_err(dev, "Poll could not pm_runtime_get: %i\n", err); /* * We poll because DSPS IP's won't expose several OTG-critical @@ -212,7 +207,6 @@ static void otg_timer(unsigned long _musb) dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl, usb_otg_state_string(musb->xceiv->otg->state)); - spin_lock_irqsave(&musb->lock, flags); switch (musb->xceiv->otg->state) { case OTG_STATE_A_WAIT_VRISE: mod_timer(&glue->timer, jiffies + @@ -245,8 +239,30 @@ static void otg_timer(unsigned long _musb) default: break; } - spin_unlock_irqrestore(&musb->lock, flags); + return 0; +} + +static void otg_timer(unsigned long _musb) +{ + struct musb *musb = (void *)_musb; + struct device *dev = musb->controller; + unsigned long flags; + int err; + + err = pm_runtime_get(dev); + if ((err != -EINPROGRESS) && err < 0) { + dev_err(dev, "Poll could not pm_runtime_get: %i\n", err); + pm_runtime_put_noidle(dev); + + return; + } + + spin_lock_irqsave(&musb->lock, flags); + err = musb_queue_resume_work(musb, dsps_check_status, NULL); + if (err < 0) + dev_err(dev, "%s resume work: %i\n", __func__, err); + spin_unlock_irqrestore(&musb->lock, flags); pm_runtime_mark_last_busy(dev); pm_runtime_put_autosuspend(dev); } @@ -767,28 +783,13 @@ static int dsps_probe(struct platform_device *pdev) platform_set_drvdata(pdev, glue); pm_runtime_enable(&pdev->dev); - pm_runtime_use_autosuspend(&pdev->dev); - pm_runtime_set_autosuspend_delay(&pdev->dev, 200); - - ret = pm_runtime_get_sync(&pdev->dev); - if (ret < 0) { - dev_err(&pdev->dev, "pm_runtime_get_sync FAILED"); - goto err2; - } - ret = dsps_create_musb_pdev(glue, pdev); if (ret) - goto err3; - - pm_runtime_mark_last_busy(&pdev->dev); - pm_runtime_put_autosuspend(&pdev->dev); + goto err; return 0; -err3: - pm_runtime_put_sync(&pdev->dev); -err2: - pm_runtime_dont_use_autosuspend(&pdev->dev); +err: pm_runtime_disable(&pdev->dev); return ret; } @@ -799,9 +800,6 @@ static int dsps_remove(struct platform_device *pdev) platform_device_unregister(glue->musb); - /* disable usbss clocks */ - pm_runtime_dont_use_autosuspend(&pdev->dev); - pm_runtime_put_sync(&pdev->dev); pm_runtime_disable(&pdev->dev); return 0; diff --git a/drivers/usb/musb/musb_gadget.c b/drivers/usb/musb/musb_gadget.c index 4042ea017985..a55173c9e564 100644 --- a/drivers/usb/musb/musb_gadget.c +++ b/drivers/usb/musb/musb_gadget.c @@ -1114,7 +1114,7 @@ static int musb_gadget_enable(struct usb_ep *ep, musb_ep->dma ? "dma, " : "", musb_ep->packet_sz); - schedule_work(&musb->irq_work); + schedule_delayed_work(&musb->irq_work, 0); fail: spin_unlock_irqrestore(&musb->lock, flags); @@ -1158,7 +1158,7 @@ static int musb_gadget_disable(struct usb_ep *ep) musb_ep->desc = NULL; musb_ep->end_point.desc = NULL; - schedule_work(&musb->irq_work); + schedule_delayed_work(&musb->irq_work, 0); spin_unlock_irqrestore(&(musb->lock), flags); @@ -1222,13 +1222,22 @@ void musb_ep_restart(struct musb *musb, struct musb_request *req) rxstate(musb, req); } +static int musb_ep_restart_resume_work(struct musb *musb, void *data) +{ + struct musb_request *req = data; + + musb_ep_restart(musb, req); + + return 0; +} + static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req, gfp_t gfp_flags) { struct musb_ep *musb_ep; struct musb_request *request; struct musb *musb; - int status = 0; + int status; unsigned long lockflags; if (!ep || !req) @@ -1245,6 +1254,17 @@ static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req, if (request->ep != musb_ep) return -EINVAL; + status = pm_runtime_get(musb->controller); + if ((status != -EINPROGRESS) && status < 0) { + dev_err(musb->controller, + "pm runtime get failed in %s\n", + __func__); + pm_runtime_put_noidle(musb->controller); + + return status; + } + status = 0; + trace_musb_req_enq(request); /* request is mine now... */ @@ -1255,7 +1275,6 @@ static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req, map_dma_buffer(request, musb, musb_ep); - pm_runtime_get_sync(musb->controller); spin_lock_irqsave(&musb->lock, lockflags); /* don't queue if the ep is down */ @@ -1271,8 +1290,14 @@ static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req, list_add_tail(&request->list, &musb_ep->req_list); /* it this is the head of the queue, start i/o ... */ - if (!musb_ep->busy && &request->list == musb_ep->req_list.next) - musb_ep_restart(musb, request); + if (!musb_ep->busy && &request->list == musb_ep->req_list.next) { + status = musb_queue_resume_work(musb, + musb_ep_restart_resume_work, + request); + if (status < 0) + dev_err(musb->controller, "%s resume work: %i\n", + __func__, status); + } unlock: spin_unlock_irqrestore(&musb->lock, lockflags); @@ -1969,7 +1994,7 @@ static int musb_gadget_stop(struct usb_gadget *g) */ /* Force check of devctl register for PM runtime */ - schedule_work(&musb->irq_work); + schedule_delayed_work(&musb->irq_work, 0); pm_runtime_mark_last_busy(musb->controller); pm_runtime_put_autosuspend(musb->controller); diff --git a/drivers/usb/musb/omap2430.c b/drivers/usb/musb/omap2430.c index cc1225485509..e8be8e39ab8f 100644 --- a/drivers/usb/musb/omap2430.c +++ b/drivers/usb/musb/omap2430.c @@ -513,17 +513,18 @@ static int omap2430_probe(struct platform_device *pdev) } pm_runtime_enable(glue->dev); - pm_runtime_use_autosuspend(glue->dev); - pm_runtime_set_autosuspend_delay(glue->dev, 100); ret = platform_device_add(musb); if (ret) { dev_err(&pdev->dev, "failed to register musb device\n"); - goto err2; + goto err3; } return 0; +err3: + pm_runtime_disable(glue->dev); + err2: platform_device_put(musb); @@ -535,10 +536,7 @@ static int omap2430_remove(struct platform_device *pdev) { struct omap2430_glue *glue = platform_get_drvdata(pdev); - pm_runtime_get_sync(glue->dev); platform_device_unregister(glue->musb); - pm_runtime_put_sync(glue->dev); - pm_runtime_dont_use_autosuspend(glue->dev); pm_runtime_disable(glue->dev); return 0; diff --git a/drivers/usb/musb/tusb6010.c b/drivers/usb/musb/tusb6010.c index df7c9f46be54..e85cc8e4e7a9 100644 --- a/drivers/usb/musb/tusb6010.c +++ b/drivers/usb/musb/tusb6010.c @@ -724,7 +724,7 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase) dev_dbg(musb->controller, "vbus change, %s, otg %03x\n", usb_otg_state_string(musb->xceiv->otg->state), otg_stat); idle_timeout = jiffies + (1 * HZ); - schedule_work(&musb->irq_work); + schedule_delayed_work(&musb->irq_work, 0); } else /* A-dev state machine */ { dev_dbg(musb->controller, "vbus change, %s, otg %03x\n", @@ -814,7 +814,7 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase) break; } } - schedule_work(&musb->irq_work); + schedule_delayed_work(&musb->irq_work, 0); return idle_timeout; } @@ -864,7 +864,7 @@ static irqreturn_t tusb_musb_interrupt(int irq, void *__hci) musb_writel(tbase, TUSB_PRCM_WAKEUP_CLEAR, reg); if (reg & ~TUSB_PRCM_WNORCS) { musb->is_active = 1; - schedule_work(&musb->irq_work); + schedule_delayed_work(&musb->irq_work, 0); } dev_dbg(musb->controller, "wake %sactive %02x\n", musb->is_active ? "" : "in", reg); diff --git a/drivers/usb/serial/cp210x.c b/drivers/usb/serial/cp210x.c index f61477bed3a8..243ac5ebe46a 100644 --- a/drivers/usb/serial/cp210x.c +++ b/drivers/usb/serial/cp210x.c @@ -131,6 +131,7 @@ static const struct usb_device_id id_table[] = { { USB_DEVICE(0x10C4, 0x88A4) }, /* MMB Networks ZigBee USB Device */ { USB_DEVICE(0x10C4, 0x88A5) }, /* Planet Innovation Ingeni ZigBee USB Device */ { USB_DEVICE(0x10C4, 0x8946) }, /* Ketra N1 Wireless Interface */ + { USB_DEVICE(0x10C4, 0x8962) }, /* Brim Brothers charging dock */ { USB_DEVICE(0x10C4, 0x8977) }, /* CEL MeshWorks DevKit Device */ { USB_DEVICE(0x10C4, 0x8998) }, /* KCF Technologies PRN */ { USB_DEVICE(0x10C4, 0x8A2A) }, /* HubZ dual ZigBee and Z-Wave dongle */ diff --git a/drivers/usb/serial/ftdi_sio.c b/drivers/usb/serial/ftdi_sio.c index 0ff7f38d7800..6e9fc8bcc285 100644 --- a/drivers/usb/serial/ftdi_sio.c +++ b/drivers/usb/serial/ftdi_sio.c @@ -1012,6 +1012,8 @@ static const struct usb_device_id id_table_combined[] = { { USB_DEVICE(ICPDAS_VID, ICPDAS_I7561U_PID) }, { USB_DEVICE(ICPDAS_VID, ICPDAS_I7563U_PID) }, { USB_DEVICE(WICED_VID, WICED_USB20706V2_PID) }, + { USB_DEVICE(TI_VID, TI_CC3200_LAUNCHPAD_PID), + .driver_info = (kernel_ulong_t)&ftdi_jtag_quirk }, { } /* Terminating entry */ }; diff --git a/drivers/usb/serial/ftdi_sio_ids.h b/drivers/usb/serial/ftdi_sio_ids.h index 21011c0a4c64..48ee04c94a75 100644 --- a/drivers/usb/serial/ftdi_sio_ids.h +++ b/drivers/usb/serial/ftdi_sio_ids.h @@ -596,6 +596,12 @@ #define STK541_PID 0x2109 /* Zigbee Controller */ /* + * Texas Instruments + */ +#define TI_VID 0x0451 +#define TI_CC3200_LAUNCHPAD_PID 0xC32A /* SimpleLink Wi-Fi CC3200 LaunchPad */ + +/* * Blackfin gnICE JTAG * http://docs.blackfin.uclinux.org/doku.php?id=hw:jtag:gnice */ diff --git a/drivers/usb/storage/transport.c b/drivers/usb/storage/transport.c index ffd086733421..1a59f335b063 100644 --- a/drivers/usb/storage/transport.c +++ b/drivers/usb/storage/transport.c @@ -954,10 +954,15 @@ int usb_stor_CB_transport(struct scsi_cmnd *srb, struct us_data *us) /* COMMAND STAGE */ /* let's send the command via the control pipe */ + /* + * Command is sometime (f.e. after scsi_eh_prep_cmnd) on the stack. + * Stack may be vmallocated. So no DMA for us. Make a copy. + */ + memcpy(us->iobuf, srb->cmnd, srb->cmd_len); result = usb_stor_ctrl_transfer(us, us->send_ctrl_pipe, US_CBI_ADSC, USB_TYPE_CLASS | USB_RECIP_INTERFACE, 0, - us->ifnum, srb->cmnd, srb->cmd_len); + us->ifnum, us->iobuf, srb->cmd_len); /* check the return code for the command */ usb_stor_dbg(us, "Call to usb_stor_ctrl_transfer() returned %d\n", diff --git a/drivers/uwb/lc-rc.c b/drivers/uwb/lc-rc.c index d059ad4d0dbd..97ee1b46db69 100644 --- a/drivers/uwb/lc-rc.c +++ b/drivers/uwb/lc-rc.c @@ -56,8 +56,11 @@ static struct uwb_rc *uwb_rc_find_by_index(int index) struct uwb_rc *rc = NULL; dev = class_find_device(&uwb_rc_class, NULL, &index, uwb_rc_index_match); - if (dev) + if (dev) { rc = dev_get_drvdata(dev); + put_device(dev); + } + return rc; } @@ -467,7 +470,9 @@ struct uwb_rc *__uwb_rc_try_get(struct uwb_rc *target_rc) if (dev) { rc = dev_get_drvdata(dev); __uwb_rc_get(rc); + put_device(dev); } + return rc; } EXPORT_SYMBOL_GPL(__uwb_rc_try_get); @@ -520,8 +525,11 @@ struct uwb_rc *uwb_rc_get_by_grandpa(const struct device *grandpa_dev) dev = class_find_device(&uwb_rc_class, NULL, grandpa_dev, find_rc_grandpa); - if (dev) + if (dev) { rc = dev_get_drvdata(dev); + put_device(dev); + } + return rc; } EXPORT_SYMBOL_GPL(uwb_rc_get_by_grandpa); @@ -553,8 +561,10 @@ struct uwb_rc *uwb_rc_get_by_dev(const struct uwb_dev_addr *addr) struct uwb_rc *rc = NULL; dev = class_find_device(&uwb_rc_class, NULL, addr, find_rc_dev); - if (dev) + if (dev) { rc = dev_get_drvdata(dev); + put_device(dev); + } return rc; } diff --git a/drivers/uwb/pal.c b/drivers/uwb/pal.c index c1304b8d4985..678e93741ae1 100644 --- a/drivers/uwb/pal.c +++ b/drivers/uwb/pal.c @@ -97,6 +97,8 @@ static bool uwb_rc_class_device_exists(struct uwb_rc *target_rc) dev = class_find_device(&uwb_rc_class, NULL, target_rc, find_rc); + put_device(dev); + return (dev != NULL); } diff --git a/drivers/video/fbdev/amba-clcd-versatile.c b/drivers/video/fbdev/amba-clcd-versatile.c index 19ad8645d93c..e5d9bfc1703a 100644 --- a/drivers/video/fbdev/amba-clcd-versatile.c +++ b/drivers/video/fbdev/amba-clcd-versatile.c @@ -526,8 +526,8 @@ int versatile_clcd_init_panel(struct clcd_fb *fb, np = of_find_matching_node_and_match(NULL, versatile_clcd_of_match, &clcd_id); if (!np) { - dev_err(dev, "no Versatile syscon node\n"); - return -ENODEV; + /* Vexpress does not have this */ + return 0; } versatile_clcd_type = (enum versatile_clcd)clcd_id->data; diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index fdd3228e0678..3eb58cb51e56 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -155,6 +155,7 @@ config TANGOX_WATCHDOG config WDAT_WDT tristate "ACPI Watchdog Action Table (WDAT)" depends on ACPI + select WATCHDOG_CORE select ACPI_WATCHDOG help This driver adds support for systems with ACPI Watchdog Action |