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| author |   Ben Skeggs <bskeggs@redhat.com> | 2012-02-06 11:42:29 +1000 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2012-05-24 16:31:32 +1000 |
| commit | a94ba1fcac417d0b72f73fb77e730279ca9203c3 (patch) | |
| tree | 0c2b1683eda459d20b5df9c661ed0a629327b878 /drivers | |
| parent | drm/nvc0/pm: enable mpll src pll, and calc mpll coefficients (diff) | |
| download | linux-dev-a94ba1fcac417d0b72f73fb77e730279ca9203c3.tar.xz linux-dev-a94ba1fcac417d0b72f73fb77e730279ca9203c3.zip | |
drm/nvd9/pm: oops, fix timing calc
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_mem.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c index bb2f0a43f590..ec4c53f41171 100644 --- a/drivers/gpu/drm/nouveau/nouveau_mem.c +++ b/drivers/gpu/drm/nouveau/nouveau_mem.c @@ -843,6 +843,7 @@ nouveau_mem_timing_calc(struct drm_device *dev, u32 freq, ret = nv50_mem_timing_calc(dev, freq, e, len, boot, t); break; case NV_C0: + case NV_D0: ret = nvc0_mem_timing_calc(dev, freq, e, len, boot, t); break; default: |