diff options
| author |   Michael Chan <mchan@broadcom.com> | 2006-11-19 14:14:35 -0800 |
|---|---|---|
| committer |   David S. Miller <davem@sunset.davemloft.net> | 2006-12-02 21:24:32 -0800 |
| commit | d43584c8bf851145ed7ec6d148916a01979040f4 (patch) | |
| tree | 1c2fc3ec23e3dd94123fcb12a34b4b2e4f8399da /drivers | |
| parent | [BNX2]: New firmware to support 5709 (part 4). (diff) | |
| download | linux-dev-d43584c8bf851145ed7ec6d148916a01979040f4.tar.xz linux-dev-d43584c8bf851145ed7ec6d148916a01979040f4.zip | |
[BNX2]: Download 5709 firmware.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/net/bnx2.c | 42 |
1 files changed, 38 insertions, 4 deletions
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c index 52fe620e1a4c..92897efbc263 100644 --- a/drivers/net/bnx2.c +++ b/drivers/net/bnx2.c @@ -53,6 +53,7 @@ #include "bnx2.h" #include "bnx2_fw.h" +#include "bnx2_fw2.h" #define DRV_MODULE_NAME "bnx2" #define PFX DRV_MODULE_NAME ": " @@ -2410,7 +2411,10 @@ bnx2_init_cpus(struct bnx2 *bp) cpu_reg.spad_base = BNX2_RXP_SCRATCH; cpu_reg.mips_view_base = 0x8000000; - fw = &bnx2_rxp_fw_06; + if (CHIP_NUM(bp) == CHIP_NUM_5709) + fw = &bnx2_rxp_fw_09; + else + fw = &bnx2_rxp_fw_06; rc = load_cpu_fw(bp, &cpu_reg, fw); if (rc) @@ -2430,7 +2434,10 @@ bnx2_init_cpus(struct bnx2 *bp) cpu_reg.spad_base = BNX2_TXP_SCRATCH; cpu_reg.mips_view_base = 0x8000000; - fw = &bnx2_txp_fw_06; + if (CHIP_NUM(bp) == CHIP_NUM_5709) + fw = &bnx2_txp_fw_09; + else + fw = &bnx2_txp_fw_06; rc = load_cpu_fw(bp, &cpu_reg, fw); if (rc) @@ -2450,7 +2457,10 @@ bnx2_init_cpus(struct bnx2 *bp) cpu_reg.spad_base = BNX2_TPAT_SCRATCH; cpu_reg.mips_view_base = 0x8000000; - fw = &bnx2_tpat_fw_06; + if (CHIP_NUM(bp) == CHIP_NUM_5709) + fw = &bnx2_tpat_fw_09; + else + fw = &bnx2_tpat_fw_06; rc = load_cpu_fw(bp, &cpu_reg, fw); if (rc) @@ -2470,12 +2480,36 @@ bnx2_init_cpus(struct bnx2 *bp) cpu_reg.spad_base = BNX2_COM_SCRATCH; cpu_reg.mips_view_base = 0x8000000; - fw = &bnx2_com_fw_06; + if (CHIP_NUM(bp) == CHIP_NUM_5709) + fw = &bnx2_com_fw_09; + else + fw = &bnx2_com_fw_06; rc = load_cpu_fw(bp, &cpu_reg, fw); if (rc) goto init_cpu_err; + /* Initialize the Command Processor. */ + cpu_reg.mode = BNX2_CP_CPU_MODE; + cpu_reg.mode_value_halt = BNX2_CP_CPU_MODE_SOFT_HALT; + cpu_reg.mode_value_sstep = BNX2_CP_CPU_MODE_STEP_ENA; + cpu_reg.state = BNX2_CP_CPU_STATE; + cpu_reg.state_value_clear = 0xffffff; + cpu_reg.gpr0 = BNX2_CP_CPU_REG_FILE; + cpu_reg.evmask = BNX2_CP_CPU_EVENT_MASK; + cpu_reg.pc = BNX2_CP_CPU_PROGRAM_COUNTER; + cpu_reg.inst = BNX2_CP_CPU_INSTRUCTION; + cpu_reg.bp = BNX2_CP_CPU_HW_BREAKPOINT; + cpu_reg.spad_base = BNX2_CP_SCRATCH; + cpu_reg.mips_view_base = 0x8000000; + + if (CHIP_NUM(bp) == CHIP_NUM_5709) { + fw = &bnx2_cp_fw_09; + + load_cpu_fw(bp, &cpu_reg, fw); + if (rc) + goto init_cpu_err; + } init_cpu_err: bnx2_gunzip_end(bp); return rc; |