diff options
| author |   Miquel Raynal <miquel.raynal@bootlin.com> | 2021-05-05 23:37:34 +0200 |
|---|---|---|
| committer | Miquel Raynal <miquel.raynal@bootlin.com> | 2021-05-26 10:43:40 +0200 |
| commit | dbb7b2e07564443c2d357398e83e27c2fa5a89ed (patch) | |
| tree | 2f4ae9994d1bdf62c86e34e2da385c682c50e866 /drivers | |
| parent | mtd: rawnand: Update dead URL (diff) | |
| download | linux-dev-dbb7b2e07564443c2d357398e83e27c2fa5a89ed.tar.xz linux-dev-dbb7b2e07564443c2d357398e83e27c2fa5a89ed.zip | |
mtd: rawnand: Use more recent ONFI specification wording
In particular, first ONFI specifications referred to SDR modes as
asynchronous modes, which is not the term we usually have in mind. The
spec has then been updated, so do the same here in the NAND subsystem to
avoid any possible confusion.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20210505213750.257417-7-miquel.raynal@bootlin.com
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/mtd/nand/raw/cadence-nand-controller.c | 6 | ||||
| -rw-r--r-- | drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.h | 2 | ||||
| -rw-r--r-- | drivers/mtd/nand/raw/nand_base.c | 2 | ||||
| -rw-r--r-- | drivers/mtd/nand/raw/nand_onfi.c | 2 |
4 files changed, 6 insertions, 6 deletions
diff --git a/drivers/mtd/nand/raw/cadence-nand-controller.c b/drivers/mtd/nand/raw/cadence-nand-controller.c index b46786cd53e0..7eec60ea9056 100644 --- a/drivers/mtd/nand/raw/cadence-nand-controller.c +++ b/drivers/mtd/nand/raw/cadence-nand-controller.c @@ -2348,9 +2348,9 @@ cadence_nand_setup_interface(struct nand_chip *chip, int chipnr, * for tRP and tRH timings. If it is NOT possible to sample data * with optimal tRP/tRH settings, the parameters will be extended. * If clk_period is 50ns (the lowest value) this condition is met - * for asynchronous timing modes 1, 2, 3, 4 and 5. - * If clk_period is 20ns the condition is met only - * for asynchronous timing mode 5. + * for SDR timing modes 1, 2, 3, 4 and 5. + * If clk_period is 20ns the condition is met only for SDR timing + * mode 5. */ if (sdr->tRC_min <= clk_period && sdr->tRP_min <= (clk_period / 2) && diff --git a/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.h b/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.h index fdc5ed7de083..5e1c3ddae5f8 100644 --- a/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.h +++ b/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.h @@ -79,7 +79,7 @@ enum gpmi_type { struct gpmi_devdata { enum gpmi_type type; int bch_max_ecc_strength; - int max_chain_delay; /* See the async EDO mode */ + int max_chain_delay; /* See the SDR EDO mode */ const char * const *clks; const int clks_count; }; diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index e29e5b3d31bf..f4b287b706f8 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -936,7 +936,7 @@ int nand_choose_best_sdr_timings(struct nand_chip *chip, /* Fallback to slower modes */ best_mode = iface->timings.mode; } else if (chip->parameters.onfi) { - best_mode = fls(chip->parameters.onfi->async_timing_mode) - 1; + best_mode = fls(chip->parameters.onfi->sdr_timing_modes) - 1; } for (mode = best_mode; mode >= 0; mode--) { diff --git a/drivers/mtd/nand/raw/nand_onfi.c b/drivers/mtd/nand/raw/nand_onfi.c index 45649e03797d..02303455c34f 100644 --- a/drivers/mtd/nand/raw/nand_onfi.c +++ b/drivers/mtd/nand/raw/nand_onfi.c @@ -315,7 +315,7 @@ int nand_onfi_detect(struct nand_chip *chip) onfi->tBERS = le16_to_cpu(p->t_bers); onfi->tR = le16_to_cpu(p->t_r); onfi->tCCS = le16_to_cpu(p->t_ccs); - onfi->async_timing_mode = le16_to_cpu(p->async_timing_mode); + onfi->sdr_timing_modes = le16_to_cpu(p->sdr_timing_modes); onfi->vendor_revision = le16_to_cpu(p->vendor_revision); memcpy(onfi->vendor, p->vendor, sizeof(p->vendor)); chip->parameters.onfi = onfi; |