diff options
| author |   Li Zhong <floridsleeves@gmail.com> | 2022-08-30 00:15:49 -0700 |
|---|---|---|
| committer |   Tony Nguyen <anthony.l.nguyen@intel.com> | 2022-09-08 08:25:48 -0700 |
| commit | fb1752c7df4d7bac05ae7b879415d0506b2067d9 (patch) | |
| tree | 2291d657155c6cdd3fb121aa67b2bc1195a975a3 /drivers | |
| parent | net: sparx5: fix function return type to match actual type (diff) | |
| download | linux-dev-fb1752c7df4d7bac05ae7b879415d0506b2067d9.tar.xz linux-dev-fb1752c7df4d7bac05ae7b879415d0506b2067d9.zip | |
drivers/net/ethernet/e1000e: check return value of e1e_rphy()
e1e_rphy() could return error value when reading PHY register, which
needs to be checked.
Signed-off-by: Li Zhong <floridsleeves@gmail.com>
Acked-by: Sasha Neftin <sasha.neftin@intel.com>
Tested-by: Naama Meir <naamax.meir@linux.intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/net/ethernet/intel/e1000e/phy.c | 20 |
1 files changed, 17 insertions, 3 deletions
diff --git a/drivers/net/ethernet/intel/e1000e/phy.c b/drivers/net/ethernet/intel/e1000e/phy.c index fd07c3679bb1..060b263348ce 100644 --- a/drivers/net/ethernet/intel/e1000e/phy.c +++ b/drivers/net/ethernet/intel/e1000e/phy.c @@ -2697,9 +2697,14 @@ static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, void e1000_power_up_phy_copper(struct e1000_hw *hw) { u16 mii_reg = 0; + int ret; /* The PHY will retain its settings across a power down/up cycle */ - e1e_rphy(hw, MII_BMCR, &mii_reg); + ret = e1e_rphy(hw, MII_BMCR, &mii_reg); + if (ret) { + e_dbg("Error reading PHY register\n"); + return; + } mii_reg &= ~BMCR_PDOWN; e1e_wphy(hw, MII_BMCR, mii_reg); } @@ -2715,9 +2720,14 @@ void e1000_power_up_phy_copper(struct e1000_hw *hw) void e1000_power_down_phy_copper(struct e1000_hw *hw) { u16 mii_reg = 0; + int ret; /* The PHY will retain its settings across a power down/up cycle */ - e1e_rphy(hw, MII_BMCR, &mii_reg); + ret = e1e_rphy(hw, MII_BMCR, &mii_reg); + if (ret) { + e_dbg("Error reading PHY register\n"); + return; + } mii_reg |= BMCR_PDOWN; e1e_wphy(hw, MII_BMCR, mii_reg); usleep_range(1000, 2000); @@ -3037,7 +3047,11 @@ s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw) return 0; /* Do not apply workaround if in PHY loopback bit 14 set */ - e1e_rphy(hw, MII_BMCR, &data); + ret_val = e1e_rphy(hw, MII_BMCR, &data); + if (ret_val) { + e_dbg("Error reading PHY register\n"); + return ret_val; + } if (data & BMCR_LOOPBACK) return 0; |