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author | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-05-12 18:11:33 -0700 |
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committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-05-12 18:11:33 -0700 |
commit | f7d02ae76ebbf5b8a9531fe150c49e126a397704 (patch) | |
tree | bcfdcab6e70658d55a3c843694e04e938bf9168f /include/asm-arm/arch-davinci/io.h | |
parent | include/linux: trivial repair whitespace damage (diff) | |
parent | Merge branch 'fixes' into devel (diff) | |
download | linux-dev-f7d02ae76ebbf5b8a9531fe150c49e126a397704.tar.xz linux-dev-f7d02ae76ebbf5b8a9531fe150c49e126a397704.zip |
Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (30 commits)
[ARM] Use new get_irqnr_preamble
[ARM] Ensure machine class menu is sorted alphabetically
[ARM] 4333/2: KS8695: Micrel Development board
[ARM] 4332/2: KS8695: Serial driver
[ARM] 4331/3: Support for Micrel/Kendin KS8695 processor
[ARM] 4371/1: AT91: Support for Atmel AT91SAM9RL-EK development board
[ARM] 4372/1: Define byte sizes in asm-arm/sizes.h
[ARM] 4370/3: AT91: Support for Atmel AT91SAM9RL processors.
[ARM] Update mach-types
[ARM] export symbol csum_partial_copy_from_user
[ARM] iop13xx: msi support
[ARM] stacktrace fix
[ARM] Spinlock initializer cleanup
[ARM] remove useless config option GENERIC_BUST_SPINLOCK
[ARM] 4303/3: base kernel support for TI DaVinci
[ARM] 4369/1: AT91: Fix circular dependency in header files
[ARM] 4368/1: S3C24xx: build fix
[ARM] 4364/1: AT91: LEDS on AT91SAM9261-EK
[ARM] Fix iop32x/iop33x build
[ARM] EBSA110: fix build errors caused by missing "const"
...
Diffstat (limited to 'include/asm-arm/arch-davinci/io.h')
-rw-r--r-- | include/asm-arm/arch-davinci/io.h | 79 |
1 files changed, 79 insertions, 0 deletions
diff --git a/include/asm-arm/arch-davinci/io.h b/include/asm-arm/arch-davinci/io.h new file mode 100644 index 000000000000..e7accb910864 --- /dev/null +++ b/include/asm-arm/arch-davinci/io.h @@ -0,0 +1,79 @@ +/* + * DaVinci IO address definitions + * + * Copied from include/asm/arm/arch-omap/io.h + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_IO_H +#define __ASM_ARCH_IO_H + +#define IO_SPACE_LIMIT 0xffffffff + +/* + * ---------------------------------------------------------------------------- + * I/O mapping + * ---------------------------------------------------------------------------- + */ +#define IO_PHYS 0x01c00000 +#define IO_OFFSET 0xfd000000 /* Virtual IO = 0xfec00000 */ +#define IO_SIZE 0x00400000 +#define IO_VIRT (IO_PHYS + IO_OFFSET) +#define io_p2v(pa) ((pa) + IO_OFFSET) +#define io_v2p(va) ((va) - IO_OFFSET) +#define IO_ADDRESS(x) io_p2v(x) + +/* + * We don't actually have real ISA nor PCI buses, but there is so many + * drivers out there that might just work if we fake them... + */ +#define PCIO_BASE 0 +#define __io(a) ((void __iomem *)(PCIO_BASE + (a))) +#define __mem_pci(a) (a) +#define __mem_isa(a) (a) + +#ifndef __ASSEMBLER__ + +/* + * Functions to access the DaVinci IO region + * + * NOTE: - Use davinci_read/write[bwl] for physical register addresses + * - Use __raw_read/write[bwl]() for virtual register addresses + * - Use IO_ADDRESS(phys_addr) to convert registers to virtual addresses + * - DO NOT use hardcoded virtual addresses to allow changing the + * IO address space again if needed + */ +#define davinci_readb(a) (*(volatile unsigned char *)IO_ADDRESS(a)) +#define davinci_readw(a) (*(volatile unsigned short *)IO_ADDRESS(a)) +#define davinci_readl(a) (*(volatile unsigned int *)IO_ADDRESS(a)) + +#define davinci_writeb(v,a) (*(volatile unsigned char *)IO_ADDRESS(a) = (v)) +#define davinci_writew(v,a) (*(volatile unsigned short *)IO_ADDRESS(a) = (v)) +#define davinci_writel(v,a) (*(volatile unsigned int *)IO_ADDRESS(a) = (v)) + +/* 16 bit uses LDRH/STRH, base +/- offset_8 */ +typedef struct { volatile u16 offset[256]; } __regbase16; +#define __REGV16(vaddr) ((__regbase16 *)((vaddr)&~0xff)) \ + ->offset[((vaddr)&0xff)>>1] +#define __REG16(paddr) __REGV16(io_p2v(paddr)) + +/* 8/32 bit uses LDR/STR, base +/- offset_12 */ +typedef struct { volatile u8 offset[4096]; } __regbase8; +#define __REGV8(vaddr) ((__regbase8 *)((vaddr)&~4095)) \ + ->offset[((vaddr)&4095)>>0] +#define __REG8(paddr) __REGV8(io_p2v(paddr)) + +typedef struct { volatile u32 offset[4096]; } __regbase32; +#define __REGV32(vaddr) ((__regbase32 *)((vaddr)&~4095)) \ + ->offset[((vaddr)&4095)>>2] + +#define __REG(paddr) __REGV32(io_p2v(paddr)) +#else + +#define __REG(x) (*((volatile unsigned long *)io_p2v(x))) + +#endif /* __ASSEMBLER__ */ +#endif /* __ASM_ARCH_IO_H */ |