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authorIngo Molnar <mingo@elte.hu>2008-07-18 19:31:12 +0200
committerIngo Molnar <mingo@elte.hu>2008-07-18 19:31:12 +0200
commit3e370b29d35fb01bfb92c2814d6f79bf6a2cb970 (patch)
tree3b8fb467d60bfe6a34686f4abdc3a60050ba40a4 /include/asm-arm/assembler.h
parentPCI quirks: call boot IRQ quirks at end of device init and during resume (diff)
parentMerge branch 'upstream-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mfasheh/ocfs2 (diff)
downloadlinux-dev-3e370b29d35fb01bfb92c2814d6f79bf6a2cb970.tar.xz
linux-dev-3e370b29d35fb01bfb92c2814d6f79bf6a2cb970.zip
Merge branch 'linus' into x86/pci-ioapic-boot-irq-quirks
Conflicts: drivers/pci/quirks.c Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'include/asm-arm/assembler.h')
-rw-r--r--include/asm-arm/assembler.h15
1 files changed, 15 insertions, 0 deletions
diff --git a/include/asm-arm/assembler.h b/include/asm-arm/assembler.h
index fce832820825..911393b2c6f0 100644
--- a/include/asm-arm/assembler.h
+++ b/include/asm-arm/assembler.h
@@ -56,6 +56,21 @@
#endif
/*
+ * This can be used to enable code to cacheline align the destination
+ * pointer when bulk writing to memory. Experiments on StrongARM and
+ * XScale didn't show this a worthwhile thing to do when the cache is not
+ * set to write-allocate (this would need further testing on XScale when WA
+ * is used).
+ *
+ * On Feroceon there is much to gain however, regardless of cache mode.
+ */
+#ifdef CONFIG_CPU_FEROCEON
+#define CALGN(code...) code
+#else
+#define CALGN(code...)
+#endif
+
+/*
* Enable and disable interrupts
*/
#if __LINUX_ARM_ARCH__ >= 6