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authorArnd Bergmann <arnd@arndb.de>2014-03-11 17:41:33 +0100
committerArnd Bergmann <arnd@arndb.de>2014-03-27 02:49:24 +0100
commit027f3f96962df3a222c11dace0d1ff266d836371 (patch)
tree07d6cde248de0ed50b468fc637b58c13079278e8 /include/asm-generic
parentMerge tag 'davinci-for-v3.15/soc-2' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/soc (diff)
downloadlinux-dev-027f3f96962df3a222c11dace0d1ff266d836371.tar.xz
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ARM: cache-tauros2: remove ARMv6 code
When building a kernel with support for both ARMv6 and ARMv7 but no MMU, the call from tauros2_internal_init to adjust_cr causes a link error. While that could probably be resolved, we don't actually support cache-tauros2 on ARMv6 any more. All PJ4 CPU implementations support both ARMv6 and ARMv7 and we already assume that we are using them only in ARMv7 mode. Removing the ARMv6 code path reduces the code size and avoids the linker error. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Diffstat (limited to 'include/asm-generic')
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