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| author |   Zachary Amsden <zach@vmware.com> | 2005-09-03 15:56:36 -0700 |
|---|---|---|
| committer |   Linus Torvalds <torvalds@evo.osdl.org> | 2005-09-05 00:06:11 -0700 |
| commit | 4bb0d3ec3e5b1e9e2399cdc641b3b6521ac9cdaa (patch) | |
| tree | 5e8d7646f5c6a2cec990b6d591f230d496b20664 /include/asm-i386/system.h | |
| parent | [PATCH] i386: clean up vDSO alignment padding (diff) | |
| download | linux-dev-4bb0d3ec3e5b1e9e2399cdc641b3b6521ac9cdaa.tar.xz linux-dev-4bb0d3ec3e5b1e9e2399cdc641b3b6521ac9cdaa.zip | |
[PATCH] i386: inline asm cleanup
i386 Inline asm cleanup. Use cr/dr accessor functions.
Also, a potential bugfix. Also, some CR accessors really should be volatile.
Reads from CR0 (numeric state may change in an exception handler), writes to
CR4 (flipping CR4.TSD) and reads from CR2 (page fault) prevent instruction
re-ordering. I did not add memory clobber to CR3 / CR4 / CR0 updates, as it
was not there to begin with, and in no case should kernel memory be clobbered,
except when doing a TLB flush, which already has memory clobber.
I noticed that page invalidation does not have a memory clobber. I can't find
a bug as a result, but there is definitely a potential for a bug here:
#define __flush_tlb_single(addr) \
__asm__ __volatile__("invlpg %0": :"m" (*(char *) addr))
Signed-off-by: Zachary Amsden <zach@vmware.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-i386/system.h')
| -rw-r--r-- | include/asm-i386/system.h | 28 |
1 files changed, 25 insertions, 3 deletions
diff --git a/include/asm-i386/system.h b/include/asm-i386/system.h index 3db717a244f0..8048a5e018cd 100644 --- a/include/asm-i386/system.h +++ b/include/asm-i386/system.h @@ -107,13 +107,33 @@ static inline unsigned long _get_base(char * addr) #define clts() __asm__ __volatile__ ("clts") #define read_cr0() ({ \ unsigned int __dummy; \ - __asm__( \ + __asm__ __volatile__( \ "movl %%cr0,%0\n\t" \ :"=r" (__dummy)); \ __dummy; \ }) #define write_cr0(x) \ - __asm__("movl %0,%%cr0": :"r" (x)); + __asm__ __volatile__("movl %0,%%cr0": :"r" (x)); + +#define read_cr2() ({ \ + unsigned int __dummy; \ + __asm__ __volatile__( \ + "movl %%cr2,%0\n\t" \ + :"=r" (__dummy)); \ + __dummy; \ +}) +#define write_cr2(x) \ + __asm__ __volatile__("movl %0,%%cr2": :"r" (x)); + +#define read_cr3() ({ \ + unsigned int __dummy; \ + __asm__ ( \ + "movl %%cr3,%0\n\t" \ + :"=r" (__dummy)); \ + __dummy; \ +}) +#define write_cr3(x) \ + __asm__ __volatile__("movl %0,%%cr3": :"r" (x)); #define read_cr4() ({ \ unsigned int __dummy; \ @@ -123,7 +143,7 @@ static inline unsigned long _get_base(char * addr) __dummy; \ }) #define write_cr4(x) \ - __asm__("movl %0,%%cr4": :"r" (x)); + __asm__ __volatile__("movl %0,%%cr4": :"r" (x)); #define stts() write_cr0(8 | read_cr0()) #endif /* __KERNEL__ */ @@ -447,6 +467,8 @@ struct alt_instr { #define local_irq_enable() __asm__ __volatile__("sti": : :"memory") /* used in the idle loop; sti takes one instruction cycle to complete */ #define safe_halt() __asm__ __volatile__("sti; hlt": : :"memory") +/* used when interrupts are already enabled or to shutdown the processor */ +#define halt() __asm__ __volatile__("hlt": : :"memory") #define irqs_disabled() \ ({ \ |