diff options
| author |   Tony Luck <tony.luck@intel.com> | 2005-10-28 11:15:08 -0700 |
|---|---|---|
| committer | Tony Luck <tony.luck@intel.com> | 2005-10-28 11:15:08 -0700 |
| commit | 0d9136fdbcdbddcd4eb5ac94c248c039193d4795 (patch) | |
| tree | 2e914c8afe019302199b5d807114e5b15835dc90 /include/asm-ia64/sn | |
| parent | Pull altix-fpga-reset into release branch (diff) | |
| parent | [IA64] Need to include <asm/sn/io.h> in a few more places. (diff) | |
| download | linux-dev-0d9136fdbcdbddcd4eb5ac94c248c039193d4795.tar.xz linux-dev-0d9136fdbcdbddcd4eb5ac94c248c039193d4795.zip | |
Pull altix-mmr into release branch
Diffstat (limited to 'include/asm-ia64/sn')
| -rw-r--r-- | include/asm-ia64/sn/io.h | 9 | ||||
| -rw-r--r-- | include/asm-ia64/sn/tioca_provider.h | 14 |
2 files changed, 16 insertions, 7 deletions
diff --git a/include/asm-ia64/sn/io.h b/include/asm-ia64/sn/io.h index 42209733f6b1..7597a52b426c 100644 --- a/include/asm-ia64/sn/io.h +++ b/include/asm-ia64/sn/io.h @@ -36,6 +36,15 @@ extern void sn_dma_flush(unsigned long); #define __sn_readq_relaxed ___sn_readq_relaxed /* + * Convenience macros for setting/clearing bits using the above accessors + */ + +#define __sn_setq_relaxed(addr, val) \ + writeq((__sn_readq_relaxed(addr) | (val)), (addr)) +#define __sn_clrq_relaxed(addr, val) \ + writeq((__sn_readq_relaxed(addr) & ~(val)), (addr)) + +/* * The following routines are SN Platform specific, called when * a reference is made to inX/outX set macros. SN Platform * inX set of macros ensures that Posted DMA writes on the diff --git a/include/asm-ia64/sn/tioca_provider.h b/include/asm-ia64/sn/tioca_provider.h index 5ccec608d325..b532ef6148ed 100644 --- a/include/asm-ia64/sn/tioca_provider.h +++ b/include/asm-ia64/sn/tioca_provider.h @@ -182,11 +182,11 @@ tioca_tlbflush(struct tioca_kernel *tioca_kernel) * touch every CL aligned GART entry. */ - ca_base->ca_control2 &= ~(CA_GART_MEM_PARAM); - ca_base->ca_control2 |= CA_GART_FLUSH_TLB; - ca_base->ca_control2 |= - (0x2ull << CA_GART_MEM_PARAM_SHFT); - tmp = ca_base->ca_control2; + __sn_clrq_relaxed(&ca_base->ca_control2, CA_GART_MEM_PARAM); + __sn_setq_relaxed(&ca_base->ca_control2, CA_GART_FLUSH_TLB); + __sn_setq_relaxed(&ca_base->ca_control2, + (0x2ull << CA_GART_MEM_PARAM_SHFT)); + tmp = __sn_readq_relaxed(&ca_base->ca_control2); } return; @@ -196,8 +196,8 @@ tioca_tlbflush(struct tioca_kernel *tioca_kernel) * Gart in uncached mode ... need an explicit flush. */ - ca_base->ca_control2 |= CA_GART_FLUSH_TLB; - tmp = ca_base->ca_control2; + __sn_setq_relaxed(&ca_base->ca_control2, CA_GART_FLUSH_TLB); + tmp = __sn_readq_relaxed(&ca_base->ca_control2); } extern uint32_t tioca_gart_found; |