diff options
| author |   Greg Ungerer <gerg@snapgear.com> | 2005-09-12 11:18:10 +1000 |
|---|---|---|
| committer |   Linus Torvalds <torvalds@g5.osdl.org> | 2005-09-11 20:43:47 -0700 |
| commit | d871629b83774fc24db6dd2775ceaf46b433b056 (patch) | |
| tree | 78bcd68ed5c497ee1f2bd5f42a936dac62c135e9 /include/asm-m68knommu/m527xsim.h | |
| parent | [PATCH] m68knommu: FEC eth definitions support for the 523x Coldfire processor family (diff) | |
| download | linux-dev-d871629b83774fc24db6dd2775ceaf46b433b056.tar.xz linux-dev-d871629b83774fc24db6dd2775ceaf46b433b056.zip | |
[PATCH] m68knommu: allow for SDRAM and GPIO differences on 5270/1 and 5274/5 processors
Allow for differences in the SDRAM controller setup and GPIO pin setup
of the 5270/1 and 5274/5 parts. With separate config options for each
now this no longer needs to be board specific.
Signed-off-by: Greg Ungerer <gerg@uclinux.com>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-m68knommu/m527xsim.h')
| -rw-r--r-- | include/asm-m68knommu/m527xsim.h | 21 |
1 files changed, 19 insertions, 2 deletions
diff --git a/include/asm-m68knommu/m527xsim.h b/include/asm-m68knommu/m527xsim.h index d280d013da03..e7878d0f7d7a 100644 --- a/include/asm-m68knommu/m527xsim.h +++ b/include/asm-m68knommu/m527xsim.h @@ -37,13 +37,14 @@ /* * SDRAM configuration registers. */ -#ifdef CONFIG_M5271EVB +#ifdef CONFIG_M5271 #define MCFSIM_DCR 0x40 /* SDRAM control */ #define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */ #define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */ #define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */ #define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */ -#else +#endif +#ifdef CONFIG_M5275 #define MCFSIM_DMR 0x40 /* SDRAM mode */ #define MCFSIM_DCR 0x44 /* SDRAM control */ #define MCFSIM_DCFG1 0x48 /* SDRAM configuration 1 */ @@ -54,5 +55,21 @@ #define MCFSIM_DMR1 0x5c /* SDRAM address mask 1 */ #endif +/* + * GPIO pins setups to enable the UARTs. + */ +#ifdef CONFIG_M5271 +#define MCF_GPIO_PAR_UART 0x100048 /* PAR UART address */ +#define UART0_ENABLE_MASK 0x000f +#define UART1_ENABLE_MASK 0x0ff0 +#define UART2_ENABLE_MASK 0x3000 +#endif +#ifdef CONFIG_M5275 +#define MCF_GPIO_PAR_UART 0x10007c /* PAR UART address */ +#define UART0_ENABLE_MASK 0x000f +#define UART1_ENABLE_MASK 0x00f0 +#define UART2_ENABLE_MASK 0x3f00 +#endif + /****************************************************************************/ #endif /* m527xsim_h */ |