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author | 2006-01-10 09:00:55 -0800 | |
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committer | 2006-01-10 09:00:55 -0800 | |
commit | d936cfc72032fb4af03d1edd99596d18ea1f081c (patch) | |
tree | 6d524c57fbff717ba82c6f4925659f6ec901d45d /include/asm-mips/cpu.h | |
parent | Fix rpc shutdown event condition bug (diff) | |
parent | MIPS: Malta: Change CPU default to R2. (diff) | |
download | linux-dev-d936cfc72032fb4af03d1edd99596d18ea1f081c.tar.xz linux-dev-d936cfc72032fb4af03d1edd99596d18ea1f081c.zip |
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
Diffstat (limited to 'include/asm-mips/cpu.h')
-rw-r--r-- | include/asm-mips/cpu.h | 20 |
1 files changed, 11 insertions, 9 deletions
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h index 48eac296060f..934e063e79f1 100644 --- a/include/asm-mips/cpu.h +++ b/include/asm-mips/cpu.h @@ -204,16 +204,18 @@ */ #define MIPS_CPU_ISA_I 0x00000001 #define MIPS_CPU_ISA_II 0x00000002 -#define MIPS_CPU_ISA_III 0x00008003 -#define MIPS_CPU_ISA_IV 0x00008004 -#define MIPS_CPU_ISA_V 0x00008005 -#define MIPS_CPU_ISA_M32 0x00000020 -#define MIPS_CPU_ISA_M64 0x00008040 +#define MIPS_CPU_ISA_III 0x00000003 +#define MIPS_CPU_ISA_IV 0x00000004 +#define MIPS_CPU_ISA_V 0x00000005 +#define MIPS_CPU_ISA_M32R1 0x00000020 +#define MIPS_CPU_ISA_M32R2 0x00000040 +#define MIPS_CPU_ISA_M64R1 0x00000080 +#define MIPS_CPU_ISA_M64R2 0x00000100 -/* - * Bit 15 encodes if an ISA level supports 64-bit operations. - */ -#define MIPS_CPU_ISA_64BIT 0x00008000 +#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | \ + MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 ) +#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \ + MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2) /* * CPU Option encodings |