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authorRalf Baechle <ralf@linux-mips.org>2005-05-31 11:49:19 +0000
committerRalf Baechle <ralf@linux-mips.org>2005-10-29 19:31:17 +0100
commite50c0a8fa60da9ac0e0a70caa8a3a803815c1f2f (patch)
tree1928e8b0a4b7fb615e5a9f65dc934ba2e74cb9cd /include/asm-mips/ptrace.h
parent64-bit fixes for Alchemy code ;) (diff)
downloadlinux-dev-e50c0a8fa60da9ac0e0a70caa8a3a803815c1f2f.tar.xz
linux-dev-e50c0a8fa60da9ac0e0a70caa8a3a803815c1f2f.zip
Support the MIPS32 / MIPS64 DSP ASE.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/ptrace.h')
-rw-r--r--include/asm-mips/ptrace.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/include/asm-mips/ptrace.h b/include/asm-mips/ptrace.h
index 2b5c624c3d4f..8441a5ae96e3 100644
--- a/include/asm-mips/ptrace.h
+++ b/include/asm-mips/ptrace.h
@@ -22,6 +22,8 @@
#define MMLO 68
#define FPC_CSR 69
#define FPC_EIR 70
+#define DSP_BASE 71 /* 3 more hi / lo register pairs */
+#define DSP_CONTROL 77
/*
* This struct defines the way the registers are stored on the stack during a
@@ -38,8 +40,8 @@ struct pt_regs {
/* Saved special registers. */
unsigned long cp0_status;
- unsigned long lo;
unsigned long hi;
+ unsigned long lo;
unsigned long cp0_badvaddr;
unsigned long cp0_cause;
unsigned long cp0_epc;