diff options
| author |   Mark Mason <mmason@upwardaccess.com> | 2007-03-28 14:40:25 -0700 |
|---|---|---|
| committer |   Ralf Baechle <ralf@linux-mips.org> | 2007-04-27 16:20:24 +0100 |
| commit | 8deab1144b553548fb2f1b51affdd36dcd652aaa (patch) | |
| tree | ca5c971933b74f73532381db5bb76dc2dbe34dec /include/asm-mips/sibyte/bcm1480_regs.h | |
| parent | [MIPS] Remove unused argument from kunmap_coherent(). (diff) | |
| download | linux-dev-8deab1144b553548fb2f1b51affdd36dcd652aaa.tar.xz linux-dev-8deab1144b553548fb2f1b51affdd36dcd652aaa.zip | |
[MIPS] Updated Sibyte headers
This is an update to the earlier patch for the sibyte headers, and superceeds
the previous patch. Changes were necessary to get the tbprof driver working
on the bcm1480.
Patch to update Sibyte header files to match master versions maintained
at Broadcom. This patch also corrects some whitespace problems, and
(hopefully) shouldn't introduce any new ones.
Signed-off-by: Mark Mason <mason@broadcom.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/sibyte/bcm1480_regs.h')
| -rw-r--r-- | include/asm-mips/sibyte/bcm1480_regs.h | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/include/asm-mips/sibyte/bcm1480_regs.h b/include/asm-mips/sibyte/bcm1480_regs.h index c2dd2fe3047c..bda391d3af85 100644 --- a/include/asm-mips/sibyte/bcm1480_regs.h +++ b/include/asm-mips/sibyte/bcm1480_regs.h @@ -230,6 +230,7 @@ #define A_BCM1480_DUART_IMRREG(chan) (A_BCM1480_DUART(chan) + R_BCM1480_DUART_IMRREG(chan)) #define A_BCM1480_DUART_ISRREG(chan) (A_BCM1480_DUART(chan) + R_BCM1480_DUART_ISRREG(chan)) +#define A_BCM1480_DUART_IN_PORT(chan) (A_BCM1480_DUART(chan) + R_DUART_INP_ORT) /* * These constants are the absolute addresses. @@ -404,6 +405,21 @@ #define R_BCM1480_IMR_ALIAS_MAILBOX_0 0x0000 /* 0x0x0 */ #define R_BCM1480_IMR_ALIAS_MAILBOX_0_SET 0x0008 /* 0x0x8 */ +/* + * these macros work together to build the address of a mailbox + * register, e.g., A_BCM1480_MAILBOX_REGISTER(0,R_BCM1480_IMR_MAILBOX_SET,2) + * for mbox_0_set_cpu2 returns 0x00100240C8 + */ +#define R_BCM1480_IMR_MAILBOX_CPU 0x00 +#define R_BCM1480_IMR_MAILBOX_SET 0x08 +#define R_BCM1480_IMR_MAILBOX_CLR 0x10 +#define R_BCM1480_IMR_MAILBOX_NUM_SPACING 0x20 +#define A_BCM1480_MAILBOX_REGISTER(num,reg,cpu) \ + (A_BCM1480_IMR_CPU0_BASE + \ + (num * R_BCM1480_IMR_MAILBOX_NUM_SPACING) + \ + (cpu * BCM1480_IMR_REGISTER_SPACING) + \ + (R_BCM1480_IMR_MAILBOX_0_CPU + reg)) + /* ********************************************************************* * System Performance Counter Registers (Section 4.7) ********************************************************************* */ @@ -428,6 +444,10 @@ #define A_BCM1480_SCD_PERF_CNT_6 0x0010020500 #define A_BCM1480_SCD_PERF_CNT_7 0x0010020508 +#define BCM1480_SCD_NUM_PERF_CNT 8 +#define BCM1480_SCD_PERF_CNT_SPACING 8 +#define A_BCM1480_SCD_PERF_CNT(n) (A_SCD_PERF_CNT_0+(n*BCM1480_SCD_PERF_CNT_SPACING)) + /* ********************************************************************* * System Bus Watcher Registers (Section 4.8) ********************************************************************* */ |