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authorKumar Gala <galak@kernel.crashing.org>2008-06-16 09:41:32 -0500
committerKumar Gala <galak@kernel.crashing.org>2008-06-18 16:17:56 -0500
commit3dfa8773674e16f95f70a0e631e80c69390d04d7 (patch)
tree95e8989bbc8373e61f69ca2ac4c98ffd3c709bd9 /include/asm-powerpc/cache.h
parentpowerpc/booke: Fix definitions for dbcr[1-2] and dbsr registers (diff)
downloadlinux-dev-3dfa8773674e16f95f70a0e631e80c69390d04d7.tar.xz
linux-dev-3dfa8773674e16f95f70a0e631e80c69390d04d7.zip
powerpc/booke: Add support for new e500mc core
The new e500mc core from Freescale is based on the e500v2 but with the following changes: * Supports only the Enhanced Debug Architecture (DSRR0/1, etc) * Floating Point * No SPE * Supports lwsync * Doorbell Exceptions * Hypervisor * Cache line size is now 64-bytes (e500v1/v2 have a 32-byte cache line) Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include/asm-powerpc/cache.h')
-rw-r--r--include/asm-powerpc/cache.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/include/asm-powerpc/cache.h b/include/asm-powerpc/cache.h
index 53507046a1b1..81de6eb3455d 100644
--- a/include/asm-powerpc/cache.h
+++ b/include/asm-powerpc/cache.h
@@ -8,6 +8,9 @@
#if defined(CONFIG_8xx) || defined(CONFIG_403GCX)
#define L1_CACHE_SHIFT 4
#define MAX_COPY_PREFETCH 1
+#elif defined(CONFIG_PPC_E500MC)
+#define L1_CACHE_SHIFT 6
+#define MAX_COPY_PREFETCH 4
#elif defined(CONFIG_PPC32)
#define L1_CACHE_SHIFT 5
#define MAX_COPY_PREFETCH 4