diff options
| author |   Jeremy Kerr <jk@ozlabs.org> | 2007-12-20 16:39:59 +0900 |
|---|---|---|
| committer |   Paul Mackerras <paulus@samba.org> | 2007-12-21 19:46:20 +1100 |
| commit | 8af30675c3e7b945bbaf6f57b724f246e56eb209 (patch) | |
| tree | a883fbefe8d2a4dc8c8ef4855e1159c94bcf7c64 /include/asm-powerpc | |
| parent | [POWERPC] spufs: fix incorrect interrupt status clearing in backing mbox stat poll (diff) | |
| download | linux-dev-8af30675c3e7b945bbaf6f57b724f246e56eb209.tar.xz linux-dev-8af30675c3e7b945bbaf6f57b724f246e56eb209.zip | |
[POWERPC] spufs: use #defines for SPU class [012] exception status
Add a few #defines for the class 0, 1 and 2 interrupt status bits, and
use them instead of magic numbers when we're setting or checking for
these interrupts.
Also, add a #define for the class 2 mailbox threshold interrupt mask.
Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'include/asm-powerpc')
| -rw-r--r-- | include/asm-powerpc/spu.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/include/asm-powerpc/spu.h b/include/asm-powerpc/spu.h index 543c83c2dc62..816e3dc1f66f 100644 --- a/include/asm-powerpc/spu.h +++ b/include/asm-powerpc/spu.h @@ -527,8 +527,22 @@ struct spu_priv1 { #define CLASS2_ENABLE_SPU_STOP_INTR 0x2L #define CLASS2_ENABLE_SPU_HALT_INTR 0x4L #define CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR 0x8L +#define CLASS2_ENABLE_MAILBOX_THRESHOLD_INTR 0x10L u8 pad_0x118_0x140[0x28]; /* 0x118 */ u64 int_stat_RW[3]; /* 0x140 */ +#define CLASS0_DMA_ALIGNMENT_INTR 0x1L +#define CLASS0_INVALID_DMA_COMMAND_INTR 0x2L +#define CLASS0_SPU_ERROR_INTR 0x4L +#define CLASS0_INTR_MASK 0x7L +#define CLASS1_SEGMENT_FAULT_INTR 0x1L +#define CLASS1_STORAGE_FAULT_INTR 0x2L +#define CLASS1_LS_COMPARE_SUSPEND_ON_GET_INTR 0x4L +#define CLASS1_LS_COMPARE_SUSPEND_ON_PUT_INTR 0x8L +#define CLASS2_MAILBOX_INTR 0x1L +#define CLASS2_SPU_STOP_INTR 0x2L +#define CLASS2_SPU_HALT_INTR 0x4L +#define CLASS2_SPU_DMA_TAG_GROUP_COMPLETE_INTR 0x8L +#define CLASS2_MAILBOX_THRESHOLD_INTR 0x10L u8 pad_0x158_0x180[0x28]; /* 0x158 */ u64 int_route_RW; /* 0x180 */ |