sh: Add SH-2A platform headers.

Mostly SH-2 wrappers..

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

10 files changed, 139 insertions, 0 deletions

diff --git a/include/asm-sh/cpu-sh2a/addrspace.h b/include/asm-sh/cpu-sh2a/addrspace.h
new file mode 100644
index 000000000000..3d2e9aa21522
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/addrspace.h
@@ -0,0 +1 @@
+#include <asm/cpu-sh2/addrspace.h>
diff --git a/include/asm-sh/cpu-sh2a/cache.h b/include/asm-sh/cpu-sh2a/cache.h
new file mode 100644
index 000000000000..3e4b9e480982
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/cache.h
@@ -0,0 +1,39 @@
+/*
+ * include/asm-sh/cpu-sh2a/cache.h
+ *
+ * Copyright (C) 2004 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH2A_CACHE_H
+#define __ASM_CPU_SH2A_CACHE_H
+
+#define L1_CACHE_SHIFT	4
+
+#define CCR1		0xfffc1000
+#define CCR2		0xfffc1004
+
+/* CCR1 behaves more like the traditional CCR */
+#define CCR		CCR1
+
+/*
+ * Most of the SH-2A CCR1 definitions resemble the SH-4 ones. All others not
+ * listed here are reserved.
+ */
+#define CCR_CACHE_CB	0x0000	/* Hack */
+#define CCR_CACHE_OCE	0x0001
+#define CCR_CACHE_WT	0x0002
+#define CCR_CACHE_OCI	0x0008	/* OCF */
+#define CCR_CACHE_ICE	0x0100
+#define CCR_CACHE_ICI	0x0800	/* ICF */
+
+#define CACHE_IC_ADDRESS_ARRAY	0xf0000000
+#define CACHE_OC_ADDRESS_ARRAY	0xf0800000
+
+#define CCR_CACHE_ENABLE	(CCR_CACHE_OCE | CCR_CACHE_ICE)
+#define CCR_CACHE_INVALIDATE	(CCR_CACHE_OCI | CCR_CACHE_ICI)
+
+#endif /* __ASM_CPU_SH2A_CACHE_H */
+
diff --git a/include/asm-sh/cpu-sh2a/cacheflush.h b/include/asm-sh/cpu-sh2a/cacheflush.h
new file mode 100644
index 000000000000..fa3186c73350
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/cacheflush.h
@@ -0,0 +1 @@
+#include <asm/cpu-sh2/cacheflush.h>
diff --git a/include/asm-sh/cpu-sh2a/dma.h b/include/asm-sh/cpu-sh2a/dma.h
new file mode 100644
index 000000000000..0d5ad85c1de8
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/dma.h
@@ -0,0 +1 @@
+#include <asm/cpu-sh2/dma.h>
diff --git a/include/asm-sh/cpu-sh2a/freq.h b/include/asm-sh/cpu-sh2a/freq.h
new file mode 100644
index 000000000000..e518fff6d10f
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/freq.h
@@ -0,0 +1,18 @@
+/*
+ * include/asm-sh/cpu-sh2a/freq.h
+ *
+ * Copyright (C) 2006  Yoshinori Sato
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_CPU_SH2A_FREQ_H
+#define __ASM_CPU_SH2A_FREQ_H
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7206)
+#define FREQCR	0xfffe0010
+#endif
+
+#endif /* __ASM_CPU_SH2A_FREQ_H */
+
diff --git a/include/asm-sh/cpu-sh2a/irq.h b/include/asm-sh/cpu-sh2a/irq.h
new file mode 100644
index 000000000000..d3d42f64148c
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/irq.h
@@ -0,0 +1,75 @@
+#ifndef __ASM_SH_CPU_SH2A_IRQ_H
+#define __ASM_SH_CPU_SH2A_IRQ_H
+
+#define INTC_IPR01	0xfffe0818UL
+#define INTC_IPR02	0xfffe081aUL
+#define INTC_IPR05	0xfffe0820UL
+#define INTC_IPR06	0xfffe0c00UL
+#define INTC_IPR07	0xfffe0c02UL
+#define INTC_IPR08	0xfffe0c04UL
+#define INTC_IPR09	0xfffe0c06UL
+#define INTC_IPR10	0xfffe0c08UL
+#define INTC_IPR11	0xfffe0c0aUL
+#define INTC_IPR12	0xfffe0c0cUL
+#define INTC_IPR13	0xfffe0c0eUL
+#define INTC_IPR14	0xfffe0c10UL
+
+#define INTC_ICR0	0xfffe0800UL
+#define INTC_ICR1	0xfffe0802UL
+#define INTC_ICR2	0xfffe0804UL
+#define INTC_ISR	0xfffe0806UL
+
+#define IRQ0_IRQ	64
+#define IRQ1_IRQ	65
+#define IRQ2_IRQ	66
+#define IRQ3_IRQ	67
+#define IRQ4_IRQ	68
+#define IRQ5_IRQ	69
+#define IRQ6_IRQ	70
+#define IRQ7_IRQ	71
+
+#define PINT0_IRQ	80
+#define PINT1_IRQ	81
+#define PINT2_IRQ	82
+#define PINT3_IRQ	83
+#define PINT4_IRQ	84
+#define PINT5_IRQ	85
+#define PINT6_IRQ	86
+#define PINT7_IRQ	87
+
+#define CMI0_IRQ	140
+#define CMI1_IRQ	141
+
+#define SCIF_BRI_IRQ	240
+#define SCIF_ERI_IRQ	241
+#define SCIF_RXI_IRQ	242
+#define SCIF_TXI_IRQ	243
+#define SCIF_IPR_ADDR	INTC_IPR14
+#define SCIF_IPR_POS	3
+#define SCIF_PRIORITY	3
+
+#define SCIF1_BRI_IRQ	244
+#define SCIF1_ERI_IRQ	245
+#define SCIF1_RXI_IRQ	246
+#define SCIF1_TXI_IRQ	247
+#define SCIF1_IPR_ADDR	INTC_IPR14
+#define SCIF1_IPR_POS	2
+#define SCIF1_PRIORITY	3
+
+#define SCIF2_BRI_IRQ	248
+#define SCIF2_ERI_IRQ	249
+#define SCIF2_RXI_IRQ	250
+#define SCIF2_TXI_IRQ	251
+#define SCIF2_IPR_ADDR	INTC_IPR14
+#define SCIF2_IPR_POS	1
+#define SCIF2_PRIORITY	3
+
+#define SCIF3_BRI_IRQ	252
+#define SCIF3_ERI_IRQ	253
+#define SCIF3_RXI_IRQ	254
+#define SCIF3_TXI_IRQ	255
+#define SCIF3_IPR_ADDR	INTC_IPR14
+#define SCIF3_IPR_POS	0
+#define SCIF3_PRIORITY	3
+
+#endif /* __ASM_SH_CPU_SH2A_IRQ_H */
diff --git a/include/asm-sh/cpu-sh2a/mmu_context.h b/include/asm-sh/cpu-sh2a/mmu_context.h
new file mode 100644
index 000000000000..cd2387f7db9e
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/mmu_context.h
@@ -0,0 +1 @@
+#include <asm/cpu-sh2/mmu_context.h>
diff --git a/include/asm-sh/cpu-sh2a/timer.h b/include/asm-sh/cpu-sh2a/timer.h
new file mode 100644
index 000000000000..fee504adf11e
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/timer.h
@@ -0,0 +1 @@
+#include <asm/cpu-sh2/timer.h>
diff --git a/include/asm-sh/cpu-sh2a/ubc.h b/include/asm-sh/cpu-sh2a/ubc.h
new file mode 100644
index 000000000000..cf28062b96a2
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/ubc.h
@@ -0,0 +1 @@
+#include <asm/cpu-sh2/ubc.h>
diff --git a/include/asm-sh/cpu-sh2a/watchdog.h b/include/asm-sh/cpu-sh2a/watchdog.h
new file mode 100644
index 000000000000..c1b3e2488478
--- /dev/null
+++ b/include/asm-sh/cpu-sh2a/watchdog.h
@@ -0,0 +1 @@
+#include <asm/cpu-sh2/watchdog.h>