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authorLinus Torvalds <torvalds@linux-foundation.org>2008-01-29 08:52:50 +1100
committerLinus Torvalds <torvalds@linux-foundation.org>2008-01-29 08:52:50 +1100
commite189f3495c4e30fc84fc9241096edf3932e23439 (patch)
tree5916c89ace81537a02ae01869386ba6caafdab9c /include/asm-sh/irqflags_32.h
parentMerge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/hid (diff)
parentsh: add spi header and r2d platform data V3 (diff)
downloadlinux-dev-e189f3495c4e30fc84fc9241096edf3932e23439.tar.xz
linux-dev-e189f3495c4e30fc84fc9241096edf3932e23439.zip
Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (197 commits) sh: add spi header and r2d platform data V3 sh: update r7780rp interrupt code sh: remove consistent alloc stuff from the machine vector sh: use declared coherent memory for dreamcast pci ethernet adapter sh: declared coherent memory support V2 sh: Add support for SDK7780 board. sh: constify function pointer tables sh: Kill off -traditional for linker script. cdrom: Add support for Sega Dreamcast GD-ROM. sh: Kill off hs7751rvoip reference from arch/sh/Kconfig. sh: Drop r7780rp_defconfig, use r7780mp_defconfig as kbuild default. sh: Kill off dead HS771RVoIP board support. sh: r7785rp: Fix up DECLARE_INTC_DESC() arg mismatch. sh: r7785rp: Hook up the rest of the HL7785 FPGA IRQ vectors. sh: r2d - enable sm501 usb host function sh: remove voyagergx sh: r2d - add lcd planel timings to sm501 platform data sh: Add OHCI and UDC platform devices for SH7720. sh: intc - remove default interrupt priority tables sh: Correct pte size mismatch for X2 TLB. ...
Diffstat (limited to 'include/asm-sh/irqflags_32.h')
-rw-r--r--include/asm-sh/irqflags_32.h99
1 files changed, 99 insertions, 0 deletions
diff --git a/include/asm-sh/irqflags_32.h b/include/asm-sh/irqflags_32.h
new file mode 100644
index 000000000000..60218f541340
--- /dev/null
+++ b/include/asm-sh/irqflags_32.h
@@ -0,0 +1,99 @@
+#ifndef __ASM_SH_IRQFLAGS_32_H
+#define __ASM_SH_IRQFLAGS_32_H
+
+static inline void raw_local_irq_enable(void)
+{
+ unsigned long __dummy0, __dummy1;
+
+ __asm__ __volatile__ (
+ "stc sr, %0\n\t"
+ "and %1, %0\n\t"
+#ifdef CONFIG_CPU_HAS_SR_RB
+ "stc r6_bank, %1\n\t"
+ "or %1, %0\n\t"
+#endif
+ "ldc %0, sr\n\t"
+ : "=&r" (__dummy0), "=r" (__dummy1)
+ : "1" (~0x000000f0)
+ : "memory"
+ );
+}
+
+static inline void raw_local_irq_disable(void)
+{
+ unsigned long flags;
+
+ __asm__ __volatile__ (
+ "stc sr, %0\n\t"
+ "or #0xf0, %0\n\t"
+ "ldc %0, sr\n\t"
+ : "=&z" (flags)
+ : /* no inputs */
+ : "memory"
+ );
+}
+
+static inline void set_bl_bit(void)
+{
+ unsigned long __dummy0, __dummy1;
+
+ __asm__ __volatile__ (
+ "stc sr, %0\n\t"
+ "or %2, %0\n\t"
+ "and %3, %0\n\t"
+ "ldc %0, sr\n\t"
+ : "=&r" (__dummy0), "=r" (__dummy1)
+ : "r" (0x10000000), "r" (0xffffff0f)
+ : "memory"
+ );
+}
+
+static inline void clear_bl_bit(void)
+{
+ unsigned long __dummy0, __dummy1;
+
+ __asm__ __volatile__ (
+ "stc sr, %0\n\t"
+ "and %2, %0\n\t"
+ "ldc %0, sr\n\t"
+ : "=&r" (__dummy0), "=r" (__dummy1)
+ : "1" (~0x10000000)
+ : "memory"
+ );
+}
+
+static inline unsigned long __raw_local_save_flags(void)
+{
+ unsigned long flags;
+
+ __asm__ __volatile__ (
+ "stc sr, %0\n\t"
+ "and #0xf0, %0\n\t"
+ : "=&z" (flags)
+ : /* no inputs */
+ : "memory"
+ );
+
+ return flags;
+}
+
+static inline unsigned long __raw_local_irq_save(void)
+{
+ unsigned long flags, __dummy;
+
+ __asm__ __volatile__ (
+ "stc sr, %1\n\t"
+ "mov %1, %0\n\t"
+ "or #0xf0, %0\n\t"
+ "ldc %0, sr\n\t"
+ "mov %1, %0\n\t"
+ "and #0xf0, %0\n\t"
+ : "=&z" (flags), "=&r" (__dummy)
+ : /* no inputs */
+ : "memory"
+ );
+
+ return flags;
+}
+
+#endif /* __ASM_SH_IRQFLAGS_32_H */