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| author |   David S. Miller <davem@sunset.davemloft.net> | 2007-08-08 17:11:39 -0700 |
|---|---|---|
| committer | David S. Miller <davem@sunset.davemloft.net> | 2007-08-08 17:33:45 -0700 |
| commit | 6c70b6fc7b6fc321636a014082d9e32333da1f80 (patch) | |
| tree | ff0e52bb7ba43b058b7cbb88b952fd268fbe3ad2 /include/asm-sparc64/spitfire.h | |
| parent | [SPARC64]: Fix hard-coding of cpu type output in /proc/cpuinfo on sun4v. (diff) | |
| download | linux-dev-6c70b6fc7b6fc321636a014082d9e32333da1f80.tar.xz linux-dev-6c70b6fc7b6fc321636a014082d9e32333da1f80.zip | |
[SPARC64]: Do not assume sun4v chips have load-twin/store-init support.
Check the cpu type in the OBP device tree before committing to
using the optimized Niagara memcpy and memset implementation.
If we don't recognize the cpu type, use a completely generic
version.
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/asm-sparc64/spitfire.h')
| -rw-r--r-- | include/asm-sparc64/spitfire.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/include/asm-sparc64/spitfire.h b/include/asm-sparc64/spitfire.h index 23ad8a7987ad..cf7807813e85 100644 --- a/include/asm-sparc64/spitfire.h +++ b/include/asm-sparc64/spitfire.h @@ -38,6 +38,11 @@ #define L1DCACHE_SIZE 0x4000 +#define SUN4V_CHIP_INVALID 0x00 +#define SUN4V_CHIP_NIAGARA1 0x01 +#define SUN4V_CHIP_NIAGARA2 0x02 +#define SUN4V_CHIP_UNKNOWN 0xff + #ifndef __ASSEMBLY__ enum ultra_tlb_layout { @@ -49,6 +54,8 @@ enum ultra_tlb_layout { extern enum ultra_tlb_layout tlb_type; +extern int sun4v_chip_type; + extern int cheetah_pcache_forced_on; extern void cheetah_enable_pcache(void); |