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author | Tony Luck <tony.luck@intel.com> | 2005-05-17 15:53:14 -0700 |
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committer | Tony Luck <tony.luck@intel.com> | 2005-05-17 15:53:14 -0700 |
commit | 325a479c4c110db278ef3361460a48c4093252cc (patch) | |
tree | bcfbf4d0647d9442045639a5c19da59d55190e81 /include/asm-x86_64/cpufeature.h | |
parent | [IA64] Merge audit fix for fsyscalls with syscall-optimizations (diff) | |
parent | [IA64] Fix convert_to_non_syscall() so gdb inferior calls work again (diff) | |
download | linux-dev-325a479c4c110db278ef3361460a48c4093252cc.tar.xz linux-dev-325a479c4c110db278ef3361460a48c4093252cc.zip |
Merge with temp tree to get David's gdb inferior calls patch
Diffstat (limited to 'include/asm-x86_64/cpufeature.h')
-rw-r--r-- | include/asm-x86_64/cpufeature.h | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/include/asm-x86_64/cpufeature.h b/include/asm-x86_64/cpufeature.h index e68ad97a6319..aea308c65709 100644 --- a/include/asm-x86_64/cpufeature.h +++ b/include/asm-x86_64/cpufeature.h @@ -7,7 +7,7 @@ #ifndef __ASM_X8664_CPUFEATURE_H #define __ASM_X8664_CPUFEATURE_H -#define NCAPINTS 6 +#define NCAPINTS 7 /* N 32-bit words worth of info */ /* Intel-defined CPU features, CPUID level 0x00000001, word 0 */ #define X86_FEATURE_FPU (0*32+ 0) /* Onboard FPU */ @@ -74,9 +74,15 @@ #define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */ #define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */ -/* More extended AMD flags: CPUID level 0x80000001, ecx, word 5 */ -#define X86_FEATURE_LAHF_LM (5*32+ 0) /* LAHF/SAHF in long mode */ -#define X86_FEATURE_CMP_LEGACY (5*32+ 1) /* If yes HyperThreading not valid */ +/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ +#define X86_FEATURE_XSTORE (5*32+ 2) /* on-CPU RNG present (xstore insn) */ +#define X86_FEATURE_XSTORE_EN (5*32+ 3) /* on-CPU RNG enabled */ +#define X86_FEATURE_XCRYPT (5*32+ 6) /* on-CPU crypto (xcrypt insn) */ +#define X86_FEATURE_XCRYPT_EN (5*32+ 7) /* on-CPU crypto enabled */ + +/* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */ +#define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */ +#define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */ #define cpu_has(c, bit) test_bit(bit, (c)->x86_capability) #define boot_cpu_has(bit) test_bit(bit, boot_cpu_data.x86_capability) |